Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 15
- Kernel Errors: 35
1 13:56:14.705292 lava-dispatcher, installed at version: 2023.10
2 13:56:14.705516 start: 0 validate
3 13:56:14.705664 Start time: 2024-02-01 13:56:14.705651+00:00 (UTC)
4 13:56:14.705822 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:56:14.705964 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:56:14.975117 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:56:14.975289 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:56:15.233560 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:56:15.233737 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:56:15.494213 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:56:15.494411 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:56:15.761185 validate duration: 1.06
14 13:56:15.761472 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:56:15.761566 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:56:15.761653 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:56:15.761778 Not decompressing ramdisk as can be used compressed.
18 13:56:15.761861 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 13:56:15.761927 saving as /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/ramdisk/rootfs.cpio.gz
20 13:56:15.761988 total size: 43284872 (41 MB)
21 13:56:15.763101 progress 0 % (0 MB)
22 13:56:15.774291 progress 5 % (2 MB)
23 13:56:15.785345 progress 10 % (4 MB)
24 13:56:15.796403 progress 15 % (6 MB)
25 13:56:15.807532 progress 20 % (8 MB)
26 13:56:15.819276 progress 25 % (10 MB)
27 13:56:15.830470 progress 30 % (12 MB)
28 13:56:15.843848 progress 35 % (14 MB)
29 13:56:15.857256 progress 40 % (16 MB)
30 13:56:15.869442 progress 45 % (18 MB)
31 13:56:15.880492 progress 50 % (20 MB)
32 13:56:15.891572 progress 55 % (22 MB)
33 13:56:15.902739 progress 60 % (24 MB)
34 13:56:15.913809 progress 65 % (26 MB)
35 13:56:15.924948 progress 70 % (28 MB)
36 13:56:15.936043 progress 75 % (30 MB)
37 13:56:15.947340 progress 80 % (33 MB)
38 13:56:15.958555 progress 85 % (35 MB)
39 13:56:15.969809 progress 90 % (37 MB)
40 13:56:15.980976 progress 95 % (39 MB)
41 13:56:15.991964 progress 100 % (41 MB)
42 13:56:15.992220 41 MB downloaded in 0.23 s (179.30 MB/s)
43 13:56:15.992379 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:56:15.992622 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:56:15.992708 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:56:15.992790 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:56:15.992926 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:56:15.993000 saving as /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/kernel/Image
50 13:56:15.993060 total size: 51532288 (49 MB)
51 13:56:15.993120 No compression specified
52 13:56:15.994222 progress 0 % (0 MB)
53 13:56:16.007390 progress 5 % (2 MB)
54 13:56:16.020691 progress 10 % (4 MB)
55 13:56:16.033819 progress 15 % (7 MB)
56 13:56:16.047139 progress 20 % (9 MB)
57 13:56:16.060425 progress 25 % (12 MB)
58 13:56:16.073510 progress 30 % (14 MB)
59 13:56:16.087051 progress 35 % (17 MB)
60 13:56:16.100592 progress 40 % (19 MB)
61 13:56:16.114046 progress 45 % (22 MB)
62 13:56:16.127458 progress 50 % (24 MB)
63 13:56:16.140642 progress 55 % (27 MB)
64 13:56:16.154010 progress 60 % (29 MB)
65 13:56:16.167313 progress 65 % (31 MB)
66 13:56:16.180446 progress 70 % (34 MB)
67 13:56:16.193722 progress 75 % (36 MB)
68 13:56:16.207050 progress 80 % (39 MB)
69 13:56:16.220276 progress 85 % (41 MB)
70 13:56:16.233650 progress 90 % (44 MB)
71 13:56:16.247108 progress 95 % (46 MB)
72 13:56:16.260013 progress 100 % (49 MB)
73 13:56:16.260223 49 MB downloaded in 0.27 s (183.96 MB/s)
74 13:56:16.260372 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:56:16.260600 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:56:16.260685 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:56:16.260773 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:56:16.260913 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:56:16.260988 saving as /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/dtb/mt8192-asurada-spherion-r0.dtb
81 13:56:16.261052 total size: 47278 (0 MB)
82 13:56:16.261114 No compression specified
83 13:56:16.262226 progress 69 % (0 MB)
84 13:56:16.262509 progress 100 % (0 MB)
85 13:56:16.262664 0 MB downloaded in 0.00 s (28.00 MB/s)
86 13:56:16.262784 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:56:16.263000 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:56:16.263086 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:56:16.263167 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:56:16.263276 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:56:16.263347 saving as /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/modules/modules.tar
93 13:56:16.263406 total size: 8623988 (8 MB)
94 13:56:16.263467 Using unxz to decompress xz
95 13:56:16.267439 progress 0 % (0 MB)
96 13:56:16.288242 progress 5 % (0 MB)
97 13:56:16.311596 progress 10 % (0 MB)
98 13:56:16.335073 progress 15 % (1 MB)
99 13:56:16.358588 progress 20 % (1 MB)
100 13:56:16.382742 progress 25 % (2 MB)
101 13:56:16.408237 progress 30 % (2 MB)
102 13:56:16.434234 progress 35 % (2 MB)
103 13:56:16.457261 progress 40 % (3 MB)
104 13:56:16.481559 progress 45 % (3 MB)
105 13:56:16.506695 progress 50 % (4 MB)
106 13:56:16.531205 progress 55 % (4 MB)
107 13:56:16.556083 progress 60 % (4 MB)
108 13:56:16.584041 progress 65 % (5 MB)
109 13:56:16.609467 progress 70 % (5 MB)
110 13:56:16.632991 progress 75 % (6 MB)
111 13:56:16.659751 progress 80 % (6 MB)
112 13:56:16.685208 progress 85 % (7 MB)
113 13:56:16.709832 progress 90 % (7 MB)
114 13:56:16.741489 progress 95 % (7 MB)
115 13:56:16.769344 progress 100 % (8 MB)
116 13:56:16.774260 8 MB downloaded in 0.51 s (16.10 MB/s)
117 13:56:16.774544 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:56:16.774807 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:56:16.774900 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:56:16.774992 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:56:16.775073 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:56:16.775160 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:56:16.775390 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4
125 13:56:16.775526 makedir: /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin
126 13:56:16.775631 makedir: /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/tests
127 13:56:16.775731 makedir: /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/results
128 13:56:16.775851 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-add-keys
129 13:56:16.776001 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-add-sources
130 13:56:16.776133 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-background-process-start
131 13:56:16.776259 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-background-process-stop
132 13:56:16.776385 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-common-functions
133 13:56:16.776510 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-echo-ipv4
134 13:56:16.776634 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-install-packages
135 13:56:16.776758 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-installed-packages
136 13:56:16.776882 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-os-build
137 13:56:16.777006 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-probe-channel
138 13:56:16.777129 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-probe-ip
139 13:56:16.777254 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-target-ip
140 13:56:16.777376 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-target-mac
141 13:56:16.777499 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-target-storage
142 13:56:16.777627 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-test-case
143 13:56:16.777753 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-test-event
144 13:56:16.777875 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-test-feedback
145 13:56:16.777998 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-test-raise
146 13:56:16.778144 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-test-reference
147 13:56:16.778271 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-test-runner
148 13:56:16.778394 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-test-set
149 13:56:16.778523 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-test-shell
150 13:56:16.778650 Updating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-install-packages (oe)
151 13:56:16.778802 Updating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/bin/lava-installed-packages (oe)
152 13:56:16.778923 Creating /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/environment
153 13:56:16.779023 LAVA metadata
154 13:56:16.779096 - LAVA_JOB_ID=12682963
155 13:56:16.779161 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:56:16.779262 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:56:16.779330 skipped lava-vland-overlay
158 13:56:16.779403 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:56:16.779482 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:56:16.779548 skipped lava-multinode-overlay
161 13:56:16.779620 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:56:16.779704 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:56:16.779778 Loading test definitions
164 13:56:16.779867 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:56:16.779939 Using /lava-12682963 at stage 0
166 13:56:16.780269 uuid=12682963_1.5.2.3.1 testdef=None
167 13:56:16.780355 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:56:16.780437 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:56:16.780963 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:56:16.781187 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:56:16.781800 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:56:16.782031 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:56:16.782712 runner path: /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/0/tests/0_igt-kms-mediatek test_uuid 12682963_1.5.2.3.1
176 13:56:16.782870 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:56:16.783075 Creating lava-test-runner.conf files
179 13:56:16.783137 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682963/lava-overlay-jgsbxwv4/lava-12682963/0 for stage 0
180 13:56:16.783225 - 0_igt-kms-mediatek
181 13:56:16.783321 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:56:16.783405 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:56:16.790109 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:56:16.790214 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:56:16.790300 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:56:16.790387 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:56:16.790518 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:56:18.191484 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:56:18.191975 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:56:18.192099 extracting modules file /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682963/extract-overlay-ramdisk-n6whuryq/ramdisk
191 13:56:18.440245 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:56:18.440402 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 13:56:18.440503 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682963/compress-overlay-dvzhrw0h/overlay-1.5.2.4.tar.gz to ramdisk
194 13:56:18.440574 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682963/compress-overlay-dvzhrw0h/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682963/extract-overlay-ramdisk-n6whuryq/ramdisk
195 13:56:18.447376 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:56:18.447487 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 13:56:18.447594 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:56:18.447689 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 13:56:18.447766 Building ramdisk /var/lib/lava/dispatcher/tmp/12682963/extract-overlay-ramdisk-n6whuryq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682963/extract-overlay-ramdisk-n6whuryq/ramdisk
200 13:56:19.471331 >> 369992 blocks
201 13:56:25.213265 rename /var/lib/lava/dispatcher/tmp/12682963/extract-overlay-ramdisk-n6whuryq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/ramdisk/ramdisk.cpio.gz
202 13:56:25.213736 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 13:56:25.213873 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 13:56:25.213987 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 13:56:25.214135 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/kernel/Image'
206 13:56:38.209224 Returned 0 in 12 seconds
207 13:56:38.309892 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/kernel/image.itb
208 13:56:39.171368 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:56:39.171737 output: Created: Thu Feb 1 13:56:39 2024
210 13:56:39.171843 output: Image 0 (kernel-1)
211 13:56:39.171932 output: Description:
212 13:56:39.172019 output: Created: Thu Feb 1 13:56:39 2024
213 13:56:39.172104 output: Type: Kernel Image
214 13:56:39.172185 output: Compression: lzma compressed
215 13:56:39.172267 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
216 13:56:39.172366 output: Architecture: AArch64
217 13:56:39.172466 output: OS: Linux
218 13:56:39.172564 output: Load Address: 0x00000000
219 13:56:39.172660 output: Entry Point: 0x00000000
220 13:56:39.172754 output: Hash algo: crc32
221 13:56:39.172851 output: Hash value: 5aa40db2
222 13:56:39.172948 output: Image 1 (fdt-1)
223 13:56:39.173040 output: Description: mt8192-asurada-spherion-r0
224 13:56:39.173133 output: Created: Thu Feb 1 13:56:39 2024
225 13:56:39.173226 output: Type: Flat Device Tree
226 13:56:39.173318 output: Compression: uncompressed
227 13:56:39.173410 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:56:39.173503 output: Architecture: AArch64
229 13:56:39.173595 output: Hash algo: crc32
230 13:56:39.173687 output: Hash value: cc4352de
231 13:56:39.173780 output: Image 2 (ramdisk-1)
232 13:56:39.173871 output: Description: unavailable
233 13:56:39.173962 output: Created: Thu Feb 1 13:56:39 2024
234 13:56:39.174054 output: Type: RAMDisk Image
235 13:56:39.174146 output: Compression: Unknown Compression
236 13:56:39.174237 output: Data Size: 56440155 Bytes = 55117.34 KiB = 53.83 MiB
237 13:56:39.174332 output: Architecture: AArch64
238 13:56:39.174434 output: OS: Linux
239 13:56:39.174529 output: Load Address: unavailable
240 13:56:39.174621 output: Entry Point: unavailable
241 13:56:39.174714 output: Hash algo: crc32
242 13:56:39.174806 output: Hash value: b691791a
243 13:56:39.174898 output: Default Configuration: 'conf-1'
244 13:56:39.174990 output: Configuration 0 (conf-1)
245 13:56:39.175082 output: Description: mt8192-asurada-spherion-r0
246 13:56:39.175174 output: Kernel: kernel-1
247 13:56:39.175278 output: Init Ramdisk: ramdisk-1
248 13:56:39.175375 output: FDT: fdt-1
249 13:56:39.175468 output: Loadables: kernel-1
250 13:56:39.175561 output:
251 13:56:39.175810 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:56:39.175958 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:56:39.176108 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 13:56:39.176245 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 13:56:39.176339 No LXC device requested
256 13:56:39.176467 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:56:39.176599 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 13:56:39.176716 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:56:39.176827 Checking files for TFTP limit of 4294967296 bytes.
260 13:56:39.177508 end: 1 tftp-deploy (duration 00:00:23) [common]
261 13:56:39.177649 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:56:39.177781 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:56:39.177964 substitutions:
264 13:56:39.178064 - {DTB}: 12682963/tftp-deploy-mx_x4u2x/dtb/mt8192-asurada-spherion-r0.dtb
265 13:56:39.178169 - {INITRD}: 12682963/tftp-deploy-mx_x4u2x/ramdisk/ramdisk.cpio.gz
266 13:56:39.178269 - {KERNEL}: 12682963/tftp-deploy-mx_x4u2x/kernel/Image
267 13:56:39.178368 - {LAVA_MAC}: None
268 13:56:39.178460 - {PRESEED_CONFIG}: None
269 13:56:39.178542 - {PRESEED_LOCAL}: None
270 13:56:39.178619 - {RAMDISK}: 12682963/tftp-deploy-mx_x4u2x/ramdisk/ramdisk.cpio.gz
271 13:56:39.178715 - {ROOT_PART}: None
272 13:56:39.178811 - {ROOT}: None
273 13:56:39.178906 - {SERVER_IP}: 192.168.201.1
274 13:56:39.179000 - {TEE}: None
275 13:56:39.179094 Parsed boot commands:
276 13:56:39.179188 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:56:39.179429 Parsed boot commands: tftpboot 192.168.201.1 12682963/tftp-deploy-mx_x4u2x/kernel/image.itb 12682963/tftp-deploy-mx_x4u2x/kernel/cmdline
278 13:56:39.179556 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:56:39.179689 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:56:39.179831 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:56:39.179960 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:56:39.180070 Not connected, no need to disconnect.
283 13:56:39.180189 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:56:39.180318 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:56:39.180420 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 13:56:39.184514 Setting prompt string to ['lava-test: # ']
287 13:56:39.184924 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:56:39.185078 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:56:39.185227 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:56:39.185364 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:56:39.185657 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 13:56:44.331118 >> Command sent successfully.
293 13:56:44.333961 Returned 0 in 5 seconds
294 13:56:44.434717 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:56:44.436230 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:56:44.436806 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:56:44.437424 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:56:44.437828 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:56:44.438288 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:56:44.439752 [Enter `^Ec?' for help]
302 13:56:44.612604
303 13:56:44.613153
304 13:56:44.613622 F0: 102B 0000
305 13:56:44.614055
306 13:56:44.616225 F3: 1001 0000 [0200]
307 13:56:44.616780
308 13:56:44.617229 F3: 1001 0000
309 13:56:44.617654
310 13:56:44.618063 F7: 102D 0000
311 13:56:44.618514
312 13:56:44.619508 F1: 0000 0000
313 13:56:44.619943
314 13:56:44.620382 V0: 0000 0000 [0001]
315 13:56:44.620814
316 13:56:44.622956 00: 0007 8000
317 13:56:44.623409
318 13:56:44.623854 01: 0000 0000
319 13:56:44.624282
320 13:56:44.626001 BP: 0C00 0209 [0000]
321 13:56:44.626452
322 13:56:44.626794 G0: 1182 0000
323 13:56:44.627104
324 13:56:44.630484 EC: 0000 0021 [4000]
325 13:56:44.631034
326 13:56:44.631369 S7: 0000 0000 [0000]
327 13:56:44.631776
328 13:56:44.633825 CC: 0000 0000 [0001]
329 13:56:44.634339
330 13:56:44.634721 T0: 0000 0040 [010F]
331 13:56:44.635222
332 13:56:44.635548 Jump to BL
333 13:56:44.635851
334 13:56:44.659693
335 13:56:44.660207
336 13:56:44.660542
337 13:56:44.666827 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:56:44.669920 ARM64: Exception handlers installed.
339 13:56:44.674663 ARM64: Testing exception
340 13:56:44.677591 ARM64: Done test exception
341 13:56:44.683867 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:56:44.694661 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:56:44.700744 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:56:44.710939 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:56:44.717559 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:56:44.727760 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:56:44.739043 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:56:44.745344 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:56:44.762526 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:56:44.766081 WDT: Last reset was cold boot
351 13:56:44.769402 SPI1(PAD0) initialized at 2873684 Hz
352 13:56:44.773081 SPI5(PAD0) initialized at 992727 Hz
353 13:56:44.776565 VBOOT: Loading verstage.
354 13:56:44.783062 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:56:44.785876 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:56:44.789741 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:56:44.793082 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:56:44.799987 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:56:44.806906 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:56:44.817489 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 13:56:44.817912
362 13:56:44.818238
363 13:56:44.828012 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:56:44.831729 ARM64: Exception handlers installed.
365 13:56:44.834808 ARM64: Testing exception
366 13:56:44.835341 ARM64: Done test exception
367 13:56:44.841094 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:56:44.844681 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:56:44.859658 Probing TPM: . done!
370 13:56:44.860228 TPM ready after 0 ms
371 13:56:44.867393 Connected to device vid:did:rid of 1ae0:0028:00
372 13:56:44.872884 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 13:56:44.929473 Initialized TPM device CR50 revision 0
374 13:56:44.941234 tlcl_send_startup: Startup return code is 0
375 13:56:44.941788 TPM: setup succeeded
376 13:56:44.952549 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:56:44.961232 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:56:44.972865 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:56:44.982265 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:56:44.985795 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:56:44.993606 in-header: 03 07 00 00 08 00 00 00
382 13:56:44.997290 in-data: aa e4 47 04 13 02 00 00
383 13:56:45.000723 Chrome EC: UHEPI supported
384 13:56:45.008437 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:56:45.011529 in-header: 03 ad 00 00 08 00 00 00
386 13:56:45.015439 in-data: 00 20 20 08 00 00 00 00
387 13:56:45.015862 Phase 1
388 13:56:45.019633 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:56:45.027311 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:56:45.030777 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:56:45.034719 Recovery requested (1009000e)
392 13:56:45.042383 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:56:45.047774 tlcl_extend: response is 0
394 13:56:45.057187 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:56:45.063259 tlcl_extend: response is 0
396 13:56:45.070203 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:56:45.089575 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 13:56:45.096025 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:56:45.096451
400 13:56:45.096784
401 13:56:45.107381 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:56:45.110999 ARM64: Exception handlers installed.
403 13:56:45.111418 ARM64: Testing exception
404 13:56:45.114092 ARM64: Done test exception
405 13:56:45.134685 pmic_efuse_setting: Set efuses in 11 msecs
406 13:56:45.138841 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:56:45.145359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:56:45.148784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:56:45.155571 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:56:45.159757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:56:45.162806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:56:45.166847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:56:45.174110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:56:45.177718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:56:45.181816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:56:45.188906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:56:45.193440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:56:45.196506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:56:45.200419 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:56:45.207975 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:56:45.211304 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:56:45.218795 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:56:45.226554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:56:45.229538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:56:45.237334 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:56:45.240664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:56:45.248223 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:56:45.252309 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:56:45.259913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:56:45.263917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:56:45.267031 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:56:45.274534 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:56:45.278281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:56:45.286144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:56:45.289809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:56:45.292825 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:56:45.300426 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:56:45.303988 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:56:45.307711 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:56:45.314797 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:56:45.319059 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:56:45.322491 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:56:45.330345 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:56:45.333986 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:56:45.337311 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:56:45.341815 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:56:45.346394 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:56:45.352590 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:56:45.356151 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:56:45.359627 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:56:45.363832 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:56:45.367439 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:56:45.374940 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:56:45.378764 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:56:45.381873 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:56:45.386102 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:56:45.389303 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:56:45.397201 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:56:45.404926 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:56:45.412290 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:56:45.419272 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:56:45.426351 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:56:45.430342 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:56:45.438009 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:56:45.441737 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:56:45.450030 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 13:56:45.452430 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:56:45.460462 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 13:56:45.463263 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:56:45.472313 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 13:56:45.481668 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 13:56:45.491532 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 13:56:45.501030 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 13:56:45.510743 [RTC]rtc_get_frequency_meter,154: input=16, output=815
475 13:56:45.519606 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 13:56:45.530187 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 13:56:45.534331 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 13:56:45.537777 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 13:56:45.541705 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:56:45.549151 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:56:45.552593 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:56:45.556139 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:56:45.560486 ADC[4]: Raw value=902066 ID=7
484 13:56:45.560913 ADC[3]: Raw value=213336 ID=1
485 13:56:45.563875 RAM Code: 0x71
486 13:56:45.568207 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:56:45.571276 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:56:45.578944 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:56:45.586379 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:56:45.590191 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:56:45.594004 in-header: 03 07 00 00 08 00 00 00
492 13:56:45.597545 in-data: aa e4 47 04 13 02 00 00
493 13:56:45.601404 Chrome EC: UHEPI supported
494 13:56:45.608563 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:56:45.612466 in-header: 03 ed 00 00 08 00 00 00
496 13:56:45.612970 in-data: 80 20 60 08 00 00 00 00
497 13:56:45.615836 MRC: failed to locate region type 0.
498 13:56:45.623277 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:56:45.626682 DRAM-K: Running full calibration
500 13:56:45.634248 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:56:45.634780 header.status = 0x0
502 13:56:45.638020 header.version = 0x6 (expected: 0x6)
503 13:56:45.641915 header.size = 0xd00 (expected: 0xd00)
504 13:56:45.642521 header.flags = 0x0
505 13:56:45.648752 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:56:45.668676 read SPI 0x72590 0x1c583: 12505 us, 9284 KB/s, 74.272 Mbps
507 13:56:45.675202 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:56:45.675651 dram_init: ddr_geometry: 2
509 13:56:45.679157 [EMI] MDL number = 2
510 13:56:45.679594 [EMI] Get MDL freq = 0
511 13:56:45.683989 dram_init: ddr_type: 0
512 13:56:45.684433 is_discrete_lpddr4: 1
513 13:56:45.687170 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:56:45.687612
515 13:56:45.688168
516 13:56:45.690048 [Bian_co] ETT version 0.0.0.1
517 13:56:45.694193 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:56:45.694733
519 13:56:45.697935 dramc_set_vcore_voltage set vcore to 650000
520 13:56:45.701298 Read voltage for 800, 4
521 13:56:45.701721 Vio18 = 0
522 13:56:45.705169 Vcore = 650000
523 13:56:45.705589 Vdram = 0
524 13:56:45.705923 Vddq = 0
525 13:56:45.706236 Vmddr = 0
526 13:56:45.709275 dram_init: config_dvfs: 1
527 13:56:45.713182 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:56:45.720288 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:56:45.724313 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 13:56:45.727165 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 13:56:45.730579 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 13:56:45.733681 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 13:56:45.737616 MEM_TYPE=3, freq_sel=18
534 13:56:45.741081 sv_algorithm_assistance_LP4_1600
535 13:56:45.744516 ============ PULL DRAM RESETB DOWN ============
536 13:56:45.747173 ========== PULL DRAM RESETB DOWN end =========
537 13:56:45.754238 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:56:45.757416 ===================================
539 13:56:45.758064 LPDDR4 DRAM CONFIGURATION
540 13:56:45.760998 ===================================
541 13:56:45.764159 EX_ROW_EN[0] = 0x0
542 13:56:45.764593 EX_ROW_EN[1] = 0x0
543 13:56:45.767670 LP4Y_EN = 0x0
544 13:56:45.768103 WORK_FSP = 0x0
545 13:56:45.770772 WL = 0x2
546 13:56:45.771204 RL = 0x2
547 13:56:45.774334 BL = 0x2
548 13:56:45.777609 RPST = 0x0
549 13:56:45.778040 RD_PRE = 0x0
550 13:56:45.780685 WR_PRE = 0x1
551 13:56:45.781115 WR_PST = 0x0
552 13:56:45.784530 DBI_WR = 0x0
553 13:56:45.784964 DBI_RD = 0x0
554 13:56:45.787539 OTF = 0x1
555 13:56:45.791244 ===================================
556 13:56:45.794392 ===================================
557 13:56:45.794911 ANA top config
558 13:56:45.797774 ===================================
559 13:56:45.801171 DLL_ASYNC_EN = 0
560 13:56:45.801596 ALL_SLAVE_EN = 1
561 13:56:45.804791 NEW_RANK_MODE = 1
562 13:56:45.807623 DLL_IDLE_MODE = 1
563 13:56:45.810781 LP45_APHY_COMB_EN = 1
564 13:56:45.814278 TX_ODT_DIS = 1
565 13:56:45.814768 NEW_8X_MODE = 1
566 13:56:45.818140 ===================================
567 13:56:45.821435 ===================================
568 13:56:45.825159 data_rate = 1600
569 13:56:45.828314 CKR = 1
570 13:56:45.831170 DQ_P2S_RATIO = 8
571 13:56:45.834855 ===================================
572 13:56:45.838014 CA_P2S_RATIO = 8
573 13:56:45.838466 DQ_CA_OPEN = 0
574 13:56:45.841540 DQ_SEMI_OPEN = 0
575 13:56:45.844765 CA_SEMI_OPEN = 0
576 13:56:45.847802 CA_FULL_RATE = 0
577 13:56:45.851310 DQ_CKDIV4_EN = 1
578 13:56:45.854810 CA_CKDIV4_EN = 1
579 13:56:45.855234 CA_PREDIV_EN = 0
580 13:56:45.858172 PH8_DLY = 0
581 13:56:45.861380 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:56:45.864997 DQ_AAMCK_DIV = 4
583 13:56:45.868661 CA_AAMCK_DIV = 4
584 13:56:45.869189 CA_ADMCK_DIV = 4
585 13:56:45.871690 DQ_TRACK_CA_EN = 0
586 13:56:45.875323 CA_PICK = 800
587 13:56:45.878385 CA_MCKIO = 800
588 13:56:45.881406 MCKIO_SEMI = 0
589 13:56:45.885393 PLL_FREQ = 3068
590 13:56:45.889257 DQ_UI_PI_RATIO = 32
591 13:56:45.889682 CA_UI_PI_RATIO = 0
592 13:56:45.892540 ===================================
593 13:56:45.896129 ===================================
594 13:56:45.900370 memory_type:LPDDR4
595 13:56:45.900892 GP_NUM : 10
596 13:56:45.903906 SRAM_EN : 1
597 13:56:45.904331 MD32_EN : 0
598 13:56:45.907334 ===================================
599 13:56:45.911191 [ANA_INIT] >>>>>>>>>>>>>>
600 13:56:45.914517 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:56:45.918480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:56:45.918907 ===================================
603 13:56:45.922143 data_rate = 1600,PCW = 0X7600
604 13:56:45.925543 ===================================
605 13:56:45.929082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:56:45.935916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:56:45.939063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:56:45.945851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:56:45.948826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:56:45.952111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:56:45.955547 [ANA_INIT] flow start
612 13:56:45.955982 [ANA_INIT] PLL >>>>>>>>
613 13:56:45.958959 [ANA_INIT] PLL <<<<<<<<
614 13:56:45.962018 [ANA_INIT] MIDPI >>>>>>>>
615 13:56:45.962497 [ANA_INIT] MIDPI <<<<<<<<
616 13:56:45.965759 [ANA_INIT] DLL >>>>>>>>
617 13:56:45.968980 [ANA_INIT] flow end
618 13:56:45.972114 ============ LP4 DIFF to SE enter ============
619 13:56:45.975334 ============ LP4 DIFF to SE exit ============
620 13:56:45.979759 [ANA_INIT] <<<<<<<<<<<<<
621 13:56:45.982603 [Flow] Enable top DCM control >>>>>
622 13:56:45.986191 [Flow] Enable top DCM control <<<<<
623 13:56:45.988972 Enable DLL master slave shuffle
624 13:56:45.992442 ==============================================================
625 13:56:45.995564 Gating Mode config
626 13:56:45.999372 ==============================================================
627 13:56:46.002776 Config description:
628 13:56:46.012598 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:56:46.019280 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:56:46.023025 SELPH_MODE 0: By rank 1: By Phase
631 13:56:46.029342 ==============================================================
632 13:56:46.032863 GAT_TRACK_EN = 1
633 13:56:46.036735 RX_GATING_MODE = 2
634 13:56:46.039597 RX_GATING_TRACK_MODE = 2
635 13:56:46.042603 SELPH_MODE = 1
636 13:56:46.043073 PICG_EARLY_EN = 1
637 13:56:46.045721 VALID_LAT_VALUE = 1
638 13:56:46.052457 ==============================================================
639 13:56:46.055927 Enter into Gating configuration >>>>
640 13:56:46.059511 Exit from Gating configuration <<<<
641 13:56:46.062732 Enter into DVFS_PRE_config >>>>>
642 13:56:46.072607 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:56:46.076526 Exit from DVFS_PRE_config <<<<<
644 13:56:46.079417 Enter into PICG configuration >>>>
645 13:56:46.082788 Exit from PICG configuration <<<<
646 13:56:46.086254 [RX_INPUT] configuration >>>>>
647 13:56:46.089341 [RX_INPUT] configuration <<<<<
648 13:56:46.092817 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:56:46.099602 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:56:46.106642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:56:46.109995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:56:46.116720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:56:46.123589 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:56:46.127295 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:56:46.130281 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:56:46.136784 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:56:46.140166 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:56:46.143793 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:56:46.147209 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:56:46.150512 ===================================
661 13:56:46.153453 LPDDR4 DRAM CONFIGURATION
662 13:56:46.157190 ===================================
663 13:56:46.160273 EX_ROW_EN[0] = 0x0
664 13:56:46.160703 EX_ROW_EN[1] = 0x0
665 13:56:46.163852 LP4Y_EN = 0x0
666 13:56:46.164385 WORK_FSP = 0x0
667 13:56:46.167002 WL = 0x2
668 13:56:46.167525 RL = 0x2
669 13:56:46.170479 BL = 0x2
670 13:56:46.171047 RPST = 0x0
671 13:56:46.174194 RD_PRE = 0x0
672 13:56:46.174803 WR_PRE = 0x1
673 13:56:46.177291 WR_PST = 0x0
674 13:56:46.177816 DBI_WR = 0x0
675 13:56:46.180542 DBI_RD = 0x0
676 13:56:46.180970 OTF = 0x1
677 13:56:46.183958 ===================================
678 13:56:46.190772 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:56:46.193757 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:56:46.197268 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:56:46.200640 ===================================
682 13:56:46.203803 LPDDR4 DRAM CONFIGURATION
683 13:56:46.207060 ===================================
684 13:56:46.210689 EX_ROW_EN[0] = 0x10
685 13:56:46.211131 EX_ROW_EN[1] = 0x0
686 13:56:46.213922 LP4Y_EN = 0x0
687 13:56:46.214364 WORK_FSP = 0x0
688 13:56:46.217463 WL = 0x2
689 13:56:46.218010 RL = 0x2
690 13:56:46.220659 BL = 0x2
691 13:56:46.221197 RPST = 0x0
692 13:56:46.224116 RD_PRE = 0x0
693 13:56:46.224542 WR_PRE = 0x1
694 13:56:46.227176 WR_PST = 0x0
695 13:56:46.227716 DBI_WR = 0x0
696 13:56:46.230241 DBI_RD = 0x0
697 13:56:46.230703 OTF = 0x1
698 13:56:46.234320 ===================================
699 13:56:46.240817 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:56:46.245137 nWR fixed to 40
701 13:56:46.247998 [ModeRegInit_LP4] CH0 RK0
702 13:56:46.248430 [ModeRegInit_LP4] CH0 RK1
703 13:56:46.251722 [ModeRegInit_LP4] CH1 RK0
704 13:56:46.255145 [ModeRegInit_LP4] CH1 RK1
705 13:56:46.255573 match AC timing 13
706 13:56:46.261809 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:56:46.265221 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:56:46.268392 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:56:46.275407 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:56:46.278327 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:56:46.278808 [EMI DOE] emi_dcm 0
712 13:56:46.284701 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:56:46.285242 ==
714 13:56:46.288647 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:56:46.291687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:56:46.292118 ==
717 13:56:46.299026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:56:46.301781 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:56:46.312623 [CA 0] Center 37 (7~68) winsize 62
720 13:56:46.315893 [CA 1] Center 37 (6~68) winsize 63
721 13:56:46.319399 [CA 2] Center 35 (5~66) winsize 62
722 13:56:46.322507 [CA 3] Center 34 (4~65) winsize 62
723 13:56:46.325714 [CA 4] Center 34 (3~65) winsize 63
724 13:56:46.329639 [CA 5] Center 34 (4~64) winsize 61
725 13:56:46.330300
726 13:56:46.332851 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 13:56:46.333284
728 13:56:46.336067 [CATrainingPosCal] consider 1 rank data
729 13:56:46.339619 u2DelayCellTimex100 = 270/100 ps
730 13:56:46.342388 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 13:56:46.345992 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
732 13:56:46.349282 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 13:56:46.356048 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
734 13:56:46.359157 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
735 13:56:46.362529 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
736 13:56:46.363005
737 13:56:46.365946 CA PerBit enable=1, Macro0, CA PI delay=34
738 13:56:46.366376
739 13:56:46.369215 [CBTSetCACLKResult] CA Dly = 34
740 13:56:46.369644 CS Dly: 5 (0~36)
741 13:56:46.369982 ==
742 13:56:46.372630 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:56:46.379655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:56:46.380082 ==
745 13:56:46.382796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:56:46.389539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:56:46.398508 [CA 0] Center 37 (6~68) winsize 63
748 13:56:46.402210 [CA 1] Center 37 (7~68) winsize 62
749 13:56:46.405264 [CA 2] Center 35 (5~66) winsize 62
750 13:56:46.408839 [CA 3] Center 35 (4~66) winsize 63
751 13:56:46.412195 [CA 4] Center 34 (3~65) winsize 63
752 13:56:46.414977 [CA 5] Center 33 (3~64) winsize 62
753 13:56:46.415408
754 13:56:46.418494 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:56:46.418924
756 13:56:46.422515 [CATrainingPosCal] consider 2 rank data
757 13:56:46.425192 u2DelayCellTimex100 = 270/100 ps
758 13:56:46.429215 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 13:56:46.431912 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 13:56:46.435862 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 13:56:46.442237 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
762 13:56:46.445561 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
763 13:56:46.448987 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 13:56:46.449505
765 13:56:46.452044 CA PerBit enable=1, Macro0, CA PI delay=34
766 13:56:46.452473
767 13:56:46.455613 [CBTSetCACLKResult] CA Dly = 34
768 13:56:46.456041 CS Dly: 6 (0~38)
769 13:56:46.456380
770 13:56:46.458898 ----->DramcWriteLeveling(PI) begin...
771 13:56:46.459347 ==
772 13:56:46.462389 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:56:46.468923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:56:46.469377 ==
775 13:56:46.473005 Write leveling (Byte 0): 29 => 29
776 13:56:46.473482 Write leveling (Byte 1): 28 => 28
777 13:56:46.476428 DramcWriteLeveling(PI) end<-----
778 13:56:46.476855
779 13:56:46.477194 ==
780 13:56:46.480368 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:56:46.483827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:56:46.484468 ==
783 13:56:46.487129 [Gating] SW mode calibration
784 13:56:46.493700 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:56:46.501694 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:56:46.504745 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:56:46.507936 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 13:56:46.515339 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 13:56:46.518781 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:56:46.521609 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:56:46.525264 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:56:46.531868 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:56:46.535074 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:56:46.538779 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:56:46.544979 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:56:46.548390 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:56:46.552028 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:56:46.558197 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:56:46.561586 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:56:46.565023 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:56:46.571820 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:56:46.574971 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:56:46.579208 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 13:56:46.581931 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 13:56:46.588511 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 13:56:46.591977 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:56:46.595646 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:56:46.602133 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:56:46.605376 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:56:46.608903 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:56:46.615309 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:56:46.618648 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
813 13:56:46.621821 0 9 12 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
814 13:56:46.629145 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:56:46.632237 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:56:46.635390 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:56:46.638788 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:56:46.645764 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:56:46.648893 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
820 13:56:46.652491 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
821 13:56:46.659156 0 10 12 | B1->B0 | 3030 2626 | 0 0 | (1 1) (0 0)
822 13:56:46.662556 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:56:46.666016 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:56:46.672430 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:56:46.676156 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:56:46.679101 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:56:46.686172 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:56:46.690338 0 11 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
829 13:56:46.692425 0 11 12 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
830 13:56:46.696289 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:56:46.702708 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:56:46.706004 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:56:46.709568 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:56:46.715844 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:56:46.719556 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:56:46.722816 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 13:56:46.729545 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 13:56:46.733460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:56:46.736825 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:56:46.743040 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:56:46.746312 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:56:46.749950 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:56:46.756576 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:56:46.759625 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:56:46.763218 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:56:46.766224 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:56:46.773702 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:56:46.776345 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:56:46.780026 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:56:46.786483 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:56:46.789817 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:56:46.793082 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 13:56:46.799712 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 13:56:46.800186 Total UI for P1: 0, mck2ui 16
855 13:56:46.806509 best dqsien dly found for B0: ( 0, 14, 8)
856 13:56:46.806941 Total UI for P1: 0, mck2ui 16
857 13:56:46.813209 best dqsien dly found for B1: ( 0, 14, 8)
858 13:56:46.816766 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 13:56:46.820208 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 13:56:46.820656
861 13:56:46.823218 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 13:56:46.826769 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 13:56:46.830092 [Gating] SW calibration Done
864 13:56:46.830613 ==
865 13:56:46.833656 Dram Type= 6, Freq= 0, CH_0, rank 0
866 13:56:46.836743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 13:56:46.837172 ==
868 13:56:46.837511 RX Vref Scan: 0
869 13:56:46.839895
870 13:56:46.840317 RX Vref 0 -> 0, step: 1
871 13:56:46.840654
872 13:56:46.843419 RX Delay -130 -> 252, step: 16
873 13:56:46.846913 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 13:56:46.849998 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 13:56:46.856926 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 13:56:46.859927 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 13:56:46.863598 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 13:56:46.866855 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 13:56:46.870110 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 13:56:46.877029 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 13:56:46.880082 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
882 13:56:46.883550 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 13:56:46.887185 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 13:56:46.890193 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 13:56:46.897214 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 13:56:46.900176 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 13:56:46.903962 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 13:56:46.906944 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 13:56:46.907458 ==
890 13:56:46.910338 Dram Type= 6, Freq= 0, CH_0, rank 0
891 13:56:46.913753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 13:56:46.917199 ==
893 13:56:46.917769 DQS Delay:
894 13:56:46.918289 DQS0 = 0, DQS1 = 0
895 13:56:46.920366 DQM Delay:
896 13:56:46.920940 DQM0 = 86, DQM1 = 77
897 13:56:46.924247 DQ Delay:
898 13:56:46.924927 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 13:56:46.927426 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =85
900 13:56:46.930842 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
901 13:56:46.933578 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 13:56:46.934182
903 13:56:46.937155
904 13:56:46.937769 ==
905 13:56:46.940914 Dram Type= 6, Freq= 0, CH_0, rank 0
906 13:56:46.943878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 13:56:46.944328 ==
908 13:56:46.944656
909 13:56:46.945103
910 13:56:46.947473 TX Vref Scan disable
911 13:56:46.948041 == TX Byte 0 ==
912 13:56:46.950421 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 13:56:46.957648 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 13:56:46.958258 == TX Byte 1 ==
915 13:56:46.960804 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 13:56:46.967646 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 13:56:46.968114 ==
918 13:56:46.971133 Dram Type= 6, Freq= 0, CH_0, rank 0
919 13:56:46.974385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 13:56:46.974954 ==
921 13:56:46.987649 TX Vref=22, minBit 2, minWin=27, winSum=439
922 13:56:46.990779 TX Vref=24, minBit 3, minWin=27, winSum=443
923 13:56:46.994490 TX Vref=26, minBit 3, minWin=27, winSum=446
924 13:56:46.997971 TX Vref=28, minBit 3, minWin=27, winSum=450
925 13:56:47.001176 TX Vref=30, minBit 3, minWin=27, winSum=451
926 13:56:47.004802 TX Vref=32, minBit 3, minWin=27, winSum=451
927 13:56:47.010814 [TxChooseVref] Worse bit 3, Min win 27, Win sum 451, Final Vref 30
928 13:56:47.011240
929 13:56:47.014388 Final TX Range 1 Vref 30
930 13:56:47.014857
931 13:56:47.015191 ==
932 13:56:47.017787 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:56:47.021444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:56:47.022003 ==
935 13:56:47.022532
936 13:56:47.022960
937 13:56:47.024242 TX Vref Scan disable
938 13:56:47.027984 == TX Byte 0 ==
939 13:56:47.031341 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 13:56:47.034272 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 13:56:47.038187 == TX Byte 1 ==
942 13:56:47.041767 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 13:56:47.044691 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 13:56:47.045267
945 13:56:47.048086 [DATLAT]
946 13:56:47.048509 Freq=800, CH0 RK0
947 13:56:47.048846
948 13:56:47.051298 DATLAT Default: 0xa
949 13:56:47.051718 0, 0xFFFF, sum = 0
950 13:56:47.054880 1, 0xFFFF, sum = 0
951 13:56:47.055325 2, 0xFFFF, sum = 0
952 13:56:47.058310 3, 0xFFFF, sum = 0
953 13:56:47.058778 4, 0xFFFF, sum = 0
954 13:56:47.061749 5, 0xFFFF, sum = 0
955 13:56:47.062249 6, 0xFFFF, sum = 0
956 13:56:47.065009 7, 0xFFFF, sum = 0
957 13:56:47.065441 8, 0xFFFF, sum = 0
958 13:56:47.067801 9, 0x0, sum = 1
959 13:56:47.068395 10, 0x0, sum = 2
960 13:56:47.071015 11, 0x0, sum = 3
961 13:56:47.071448 12, 0x0, sum = 4
962 13:56:47.074565 best_step = 10
963 13:56:47.074990
964 13:56:47.075328 ==
965 13:56:47.078491 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:56:47.081614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:56:47.082042 ==
968 13:56:47.082378 RX Vref Scan: 1
969 13:56:47.084643
970 13:56:47.085062 Set Vref Range= 32 -> 127
971 13:56:47.085398
972 13:56:47.088309 RX Vref 32 -> 127, step: 1
973 13:56:47.088737
974 13:56:47.091209 RX Delay -95 -> 252, step: 8
975 13:56:47.091635
976 13:56:47.095304 Set Vref, RX VrefLevel [Byte0]: 32
977 13:56:47.098315 [Byte1]: 32
978 13:56:47.098841
979 13:56:47.101744 Set Vref, RX VrefLevel [Byte0]: 33
980 13:56:47.104985 [Byte1]: 33
981 13:56:47.105413
982 13:56:47.108460 Set Vref, RX VrefLevel [Byte0]: 34
983 13:56:47.111858 [Byte1]: 34
984 13:56:47.115305
985 13:56:47.115732 Set Vref, RX VrefLevel [Byte0]: 35
986 13:56:47.118536 [Byte1]: 35
987 13:56:47.122773
988 13:56:47.123195 Set Vref, RX VrefLevel [Byte0]: 36
989 13:56:47.126628 [Byte1]: 36
990 13:56:47.131129
991 13:56:47.131650 Set Vref, RX VrefLevel [Byte0]: 37
992 13:56:47.134038 [Byte1]: 37
993 13:56:47.138612
994 13:56:47.139117 Set Vref, RX VrefLevel [Byte0]: 38
995 13:56:47.141789 [Byte1]: 38
996 13:56:47.146150
997 13:56:47.146619 Set Vref, RX VrefLevel [Byte0]: 39
998 13:56:47.149680 [Byte1]: 39
999 13:56:47.154172
1000 13:56:47.154768 Set Vref, RX VrefLevel [Byte0]: 40
1001 13:56:47.157200 [Byte1]: 40
1002 13:56:47.161455
1003 13:56:47.161879 Set Vref, RX VrefLevel [Byte0]: 41
1004 13:56:47.164691 [Byte1]: 41
1005 13:56:47.168851
1006 13:56:47.169272 Set Vref, RX VrefLevel [Byte0]: 42
1007 13:56:47.172939 [Byte1]: 42
1008 13:56:47.175946
1009 13:56:47.176369 Set Vref, RX VrefLevel [Byte0]: 43
1010 13:56:47.179202 [Byte1]: 43
1011 13:56:47.183386
1012 13:56:47.183807 Set Vref, RX VrefLevel [Byte0]: 44
1013 13:56:47.186758 [Byte1]: 44
1014 13:56:47.190835
1015 13:56:47.191260 Set Vref, RX VrefLevel [Byte0]: 45
1016 13:56:47.194585 [Byte1]: 45
1017 13:56:47.199384
1018 13:56:47.199812 Set Vref, RX VrefLevel [Byte0]: 46
1019 13:56:47.202106 [Byte1]: 46
1020 13:56:47.207008
1021 13:56:47.207528 Set Vref, RX VrefLevel [Byte0]: 47
1022 13:56:47.209638 [Byte1]: 47
1023 13:56:47.213908
1024 13:56:47.214446 Set Vref, RX VrefLevel [Byte0]: 48
1025 13:56:47.217430 [Byte1]: 48
1026 13:56:47.221887
1027 13:56:47.222437 Set Vref, RX VrefLevel [Byte0]: 49
1028 13:56:47.225231 [Byte1]: 49
1029 13:56:47.229651
1030 13:56:47.230201 Set Vref, RX VrefLevel [Byte0]: 50
1031 13:56:47.232914 [Byte1]: 50
1032 13:56:47.236769
1033 13:56:47.237176 Set Vref, RX VrefLevel [Byte0]: 51
1034 13:56:47.239913 [Byte1]: 51
1035 13:56:47.245141
1036 13:56:47.245733 Set Vref, RX VrefLevel [Byte0]: 52
1037 13:56:47.247564 [Byte1]: 52
1038 13:56:47.251812
1039 13:56:47.252258 Set Vref, RX VrefLevel [Byte0]: 53
1040 13:56:47.255474 [Byte1]: 53
1041 13:56:47.259539
1042 13:56:47.259968 Set Vref, RX VrefLevel [Byte0]: 54
1043 13:56:47.262596 [Byte1]: 54
1044 13:56:47.267501
1045 13:56:47.267929 Set Vref, RX VrefLevel [Byte0]: 55
1046 13:56:47.270870 [Byte1]: 55
1047 13:56:47.274951
1048 13:56:47.275379 Set Vref, RX VrefLevel [Byte0]: 56
1049 13:56:47.278193 [Byte1]: 56
1050 13:56:47.282773
1051 13:56:47.283430 Set Vref, RX VrefLevel [Byte0]: 57
1052 13:56:47.285808 [Byte1]: 57
1053 13:56:47.289952
1054 13:56:47.290386 Set Vref, RX VrefLevel [Byte0]: 58
1055 13:56:47.293121 [Byte1]: 58
1056 13:56:47.297793
1057 13:56:47.298207 Set Vref, RX VrefLevel [Byte0]: 59
1058 13:56:47.301222 [Byte1]: 59
1059 13:56:47.305565
1060 13:56:47.305979 Set Vref, RX VrefLevel [Byte0]: 60
1061 13:56:47.308746 [Byte1]: 60
1062 13:56:47.312851
1063 13:56:47.313265 Set Vref, RX VrefLevel [Byte0]: 61
1064 13:56:47.315831 [Byte1]: 61
1065 13:56:47.320581
1066 13:56:47.321008 Set Vref, RX VrefLevel [Byte0]: 62
1067 13:56:47.323494 [Byte1]: 62
1068 13:56:47.328296
1069 13:56:47.328713 Set Vref, RX VrefLevel [Byte0]: 63
1070 13:56:47.331387 [Byte1]: 63
1071 13:56:47.335623
1072 13:56:47.336038 Set Vref, RX VrefLevel [Byte0]: 64
1073 13:56:47.338943 [Byte1]: 64
1074 13:56:47.343630
1075 13:56:47.344137 Set Vref, RX VrefLevel [Byte0]: 65
1076 13:56:47.346735 [Byte1]: 65
1077 13:56:47.350933
1078 13:56:47.351438 Set Vref, RX VrefLevel [Byte0]: 66
1079 13:56:47.354472 [Byte1]: 66
1080 13:56:47.358352
1081 13:56:47.358959 Set Vref, RX VrefLevel [Byte0]: 67
1082 13:56:47.361839 [Byte1]: 67
1083 13:56:47.365844
1084 13:56:47.366252 Set Vref, RX VrefLevel [Byte0]: 68
1085 13:56:47.369465 [Byte1]: 68
1086 13:56:47.373714
1087 13:56:47.374231 Set Vref, RX VrefLevel [Byte0]: 69
1088 13:56:47.376829 [Byte1]: 69
1089 13:56:47.381084
1090 13:56:47.381564 Set Vref, RX VrefLevel [Byte0]: 70
1091 13:56:47.384597 [Byte1]: 70
1092 13:56:47.389406
1093 13:56:47.389888 Set Vref, RX VrefLevel [Byte0]: 71
1094 13:56:47.392309 [Byte1]: 71
1095 13:56:47.396314
1096 13:56:47.396728 Set Vref, RX VrefLevel [Byte0]: 72
1097 13:56:47.399350 [Byte1]: 72
1098 13:56:47.403850
1099 13:56:47.404261 Set Vref, RX VrefLevel [Byte0]: 73
1100 13:56:47.407120 [Byte1]: 73
1101 13:56:47.411393
1102 13:56:47.411911 Set Vref, RX VrefLevel [Byte0]: 74
1103 13:56:47.414932 [Byte1]: 74
1104 13:56:47.419164
1105 13:56:47.419677 Set Vref, RX VrefLevel [Byte0]: 75
1106 13:56:47.422186 [Byte1]: 75
1107 13:56:47.426495
1108 13:56:47.426906 Set Vref, RX VrefLevel [Byte0]: 76
1109 13:56:47.430369 [Byte1]: 76
1110 13:56:47.433970
1111 13:56:47.434381 Set Vref, RX VrefLevel [Byte0]: 77
1112 13:56:47.437470 [Byte1]: 77
1113 13:56:47.441784
1114 13:56:47.442284 Set Vref, RX VrefLevel [Byte0]: 78
1115 13:56:47.445435 [Byte1]: 78
1116 13:56:47.449622
1117 13:56:47.450130 Final RX Vref Byte 0 = 61 to rank0
1118 13:56:47.452894 Final RX Vref Byte 1 = 55 to rank0
1119 13:56:47.456564 Final RX Vref Byte 0 = 61 to rank1
1120 13:56:47.459896 Final RX Vref Byte 1 = 55 to rank1==
1121 13:56:47.463112 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 13:56:47.466389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 13:56:47.469716 ==
1124 13:56:47.470129 DQS Delay:
1125 13:56:47.470514 DQS0 = 0, DQS1 = 0
1126 13:56:47.472883 DQM Delay:
1127 13:56:47.473343 DQM0 = 88, DQM1 = 79
1128 13:56:47.476537 DQ Delay:
1129 13:56:47.477046 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1130 13:56:47.479899 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1131 13:56:47.482920 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1132 13:56:47.486613 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1133 13:56:47.487159
1134 13:56:47.489521
1135 13:56:47.496279 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1136 13:56:47.499978 CH0 RK0: MR19=606, MR18=2B11
1137 13:56:47.503240 CH0_RK0: MR19=0x606, MR18=0x2B11, DQSOSC=398, MR23=63, INC=93, DEC=62
1138 13:56:47.506627
1139 13:56:47.509999 ----->DramcWriteLeveling(PI) begin...
1140 13:56:47.510521 ==
1141 13:56:47.513658 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 13:56:47.516668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 13:56:47.517137 ==
1144 13:56:47.519985 Write leveling (Byte 0): 30 => 30
1145 13:56:47.523111 Write leveling (Byte 1): 26 => 26
1146 13:56:47.527010 DramcWriteLeveling(PI) end<-----
1147 13:56:47.527511
1148 13:56:47.527838 ==
1149 13:56:47.530358 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 13:56:47.533944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 13:56:47.534519 ==
1152 13:56:47.537141 [Gating] SW mode calibration
1153 13:56:47.543997 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 13:56:47.587880 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 13:56:47.588365 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 13:56:47.589054 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 13:56:47.589535 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 13:56:47.589863 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:56:47.590320 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:56:47.590690 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:56:47.590984 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:56:47.591269 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:56:47.591550 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:56:47.595230 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:56:47.598391 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:56:47.601646 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:56:47.605836 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:56:47.608256 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:56:47.615266 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:56:47.618780 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:56:47.621684 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:56:47.629490 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 13:56:47.632170 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1174 13:56:47.635256 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:56:47.642028 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:56:47.645623 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:56:47.649079 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:56:47.655289 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:56:47.658786 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:56:47.662383 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:56:47.665516 0 9 8 | B1->B0 | 2323 3232 | 1 1 | (0 0) (1 1)
1182 13:56:47.672472 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1183 13:56:47.675697 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 13:56:47.678967 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 13:56:47.685468 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 13:56:47.688877 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 13:56:47.692719 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 13:56:47.698904 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1189 13:56:47.703744 0 10 8 | B1->B0 | 3131 2626 | 1 0 | (1 0) (0 0)
1190 13:56:47.705606 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1191 13:56:47.712523 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:56:47.716844 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:56:47.720718 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:56:47.723507 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:56:47.727771 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:56:47.733975 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1197 13:56:47.737367 0 11 8 | B1->B0 | 2828 3d3d | 0 0 | (0 0) (1 1)
1198 13:56:47.740833 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
1199 13:56:47.744962 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 13:56:47.751742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 13:56:47.754637 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 13:56:47.758372 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 13:56:47.764878 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1204 13:56:47.768602 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 13:56:47.772129 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 13:56:47.778956 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:56:47.781906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:56:47.785547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:56:47.788536 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:56:47.795198 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:56:47.798366 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:56:47.801860 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:56:47.808830 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:56:47.811924 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:56:47.815262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:56:47.821856 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:56:47.825147 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 13:56:47.828526 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 13:56:47.835542 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 13:56:47.838983 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 13:56:47.842109 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 13:56:47.845612 Total UI for P1: 0, mck2ui 16
1223 13:56:47.848999 best dqsien dly found for B0: ( 0, 14, 4)
1224 13:56:47.852579 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 13:56:47.855343 Total UI for P1: 0, mck2ui 16
1226 13:56:47.858967 best dqsien dly found for B1: ( 0, 14, 8)
1227 13:56:47.862100 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1228 13:56:47.865471 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 13:56:47.869397
1230 13:56:47.872345 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1231 13:56:47.875873 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 13:56:47.876383 [Gating] SW calibration Done
1233 13:56:47.879126 ==
1234 13:56:47.882489 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 13:56:47.885579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 13:56:47.885997 ==
1237 13:56:47.886323 RX Vref Scan: 0
1238 13:56:47.886726
1239 13:56:47.888923 RX Vref 0 -> 0, step: 1
1240 13:56:47.889364
1241 13:56:47.892769 RX Delay -130 -> 252, step: 16
1242 13:56:47.895737 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1243 13:56:47.899400 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1244 13:56:47.902828 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 13:56:47.909874 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 13:56:47.912999 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1247 13:56:47.916121 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1248 13:56:47.919420 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1249 13:56:47.922846 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1250 13:56:47.929115 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1251 13:56:47.932742 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1252 13:56:47.935672 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 13:56:47.939425 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1254 13:56:47.942356 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1255 13:56:47.949036 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 13:56:47.952871 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1257 13:56:47.955882 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1258 13:56:47.956298 ==
1259 13:56:47.959588 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 13:56:47.962631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 13:56:47.963049 ==
1262 13:56:47.966366 DQS Delay:
1263 13:56:47.966865 DQS0 = 0, DQS1 = 0
1264 13:56:47.969641 DQM Delay:
1265 13:56:47.970055 DQM0 = 86, DQM1 = 77
1266 13:56:47.970580 DQ Delay:
1267 13:56:47.972757 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1268 13:56:47.976527 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1269 13:56:47.979457 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1270 13:56:47.982906 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1271 13:56:47.983475
1272 13:56:47.983944
1273 13:56:47.984388 ==
1274 13:56:47.986538 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 13:56:47.993285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 13:56:47.993704 ==
1277 13:56:47.994028
1278 13:56:47.994433
1279 13:56:47.994759 TX Vref Scan disable
1280 13:56:47.997075 == TX Byte 0 ==
1281 13:56:48.000051 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 13:56:48.003357 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 13:56:48.007380 == TX Byte 1 ==
1284 13:56:48.010076 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1285 13:56:48.013797 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1286 13:56:48.017223 ==
1287 13:56:48.017752 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 13:56:48.023647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 13:56:48.024166 ==
1290 13:56:48.036536 TX Vref=22, minBit 9, minWin=26, winSum=436
1291 13:56:48.040216 TX Vref=24, minBit 13, minWin=26, winSum=440
1292 13:56:48.043325 TX Vref=26, minBit 9, minWin=26, winSum=442
1293 13:56:48.046380 TX Vref=28, minBit 8, minWin=27, winSum=450
1294 13:56:48.049730 TX Vref=30, minBit 3, minWin=27, winSum=447
1295 13:56:48.053210 TX Vref=32, minBit 8, minWin=27, winSum=447
1296 13:56:48.060136 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
1297 13:56:48.060607
1298 13:56:48.063452 Final TX Range 1 Vref 28
1299 13:56:48.063861
1300 13:56:48.064182 ==
1301 13:56:48.067026 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 13:56:48.069964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 13:56:48.070276 ==
1304 13:56:48.070590
1305 13:56:48.070811
1306 13:56:48.073262 TX Vref Scan disable
1307 13:56:48.076621 == TX Byte 0 ==
1308 13:56:48.079804 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 13:56:48.083652 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 13:56:48.086748 == TX Byte 1 ==
1311 13:56:48.089709 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1312 13:56:48.093527 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1313 13:56:48.093818
1314 13:56:48.096628 [DATLAT]
1315 13:56:48.097048 Freq=800, CH0 RK1
1316 13:56:48.097291
1317 13:56:48.099767 DATLAT Default: 0xa
1318 13:56:48.100057 0, 0xFFFF, sum = 0
1319 13:56:48.103697 1, 0xFFFF, sum = 0
1320 13:56:48.104146 2, 0xFFFF, sum = 0
1321 13:56:48.106766 3, 0xFFFF, sum = 0
1322 13:56:48.107180 4, 0xFFFF, sum = 0
1323 13:56:48.110211 5, 0xFFFF, sum = 0
1324 13:56:48.110662 6, 0xFFFF, sum = 0
1325 13:56:48.113256 7, 0xFFFF, sum = 0
1326 13:56:48.113674 8, 0xFFFF, sum = 0
1327 13:56:48.117247 9, 0x0, sum = 1
1328 13:56:48.117768 10, 0x0, sum = 2
1329 13:56:48.120084 11, 0x0, sum = 3
1330 13:56:48.120497 12, 0x0, sum = 4
1331 13:56:48.123600 best_step = 10
1332 13:56:48.124006
1333 13:56:48.124327 ==
1334 13:56:48.126884 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 13:56:48.130379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 13:56:48.130827 ==
1337 13:56:48.133476 RX Vref Scan: 0
1338 13:56:48.133880
1339 13:56:48.134197 RX Vref 0 -> 0, step: 1
1340 13:56:48.134538
1341 13:56:48.136948 RX Delay -95 -> 252, step: 8
1342 13:56:48.143457 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1343 13:56:48.147048 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1344 13:56:48.150632 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1345 13:56:48.153592 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1346 13:56:48.157552 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1347 13:56:48.160497 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1348 13:56:48.167659 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1349 13:56:48.170497 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1350 13:56:48.174200 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1351 13:56:48.177654 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1352 13:56:48.181041 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1353 13:56:48.187770 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1354 13:56:48.190500 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1355 13:56:48.194153 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1356 13:56:48.197394 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 13:56:48.200505 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1358 13:56:48.200978 ==
1359 13:56:48.204385 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 13:56:48.211148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 13:56:48.211559 ==
1362 13:56:48.211881 DQS Delay:
1363 13:56:48.213994 DQS0 = 0, DQS1 = 0
1364 13:56:48.214427 DQM Delay:
1365 13:56:48.214770 DQM0 = 87, DQM1 = 78
1366 13:56:48.217699 DQ Delay:
1367 13:56:48.220600 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1368 13:56:48.224382 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1369 13:56:48.227720 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1370 13:56:48.230649 DQ12 =80, DQ13 =84, DQ14 =92, DQ15 =88
1371 13:56:48.231058
1372 13:56:48.231379
1373 13:56:48.237427 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1374 13:56:48.241743 CH0 RK1: MR19=606, MR18=2B14
1375 13:56:48.248014 CH0_RK1: MR19=0x606, MR18=0x2B14, DQSOSC=398, MR23=63, INC=93, DEC=62
1376 13:56:48.251250 [RxdqsGatingPostProcess] freq 800
1377 13:56:48.254723 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 13:56:48.257806 Pre-setting of DQS Precalculation
1379 13:56:48.264154 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 13:56:48.264787 ==
1381 13:56:48.267686 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 13:56:48.271096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 13:56:48.271512 ==
1384 13:56:48.277649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 13:56:48.281596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 13:56:48.291137 [CA 0] Center 36 (6~66) winsize 61
1387 13:56:48.294514 [CA 1] Center 36 (6~66) winsize 61
1388 13:56:48.298036 [CA 2] Center 34 (4~65) winsize 62
1389 13:56:48.301119 [CA 3] Center 33 (3~64) winsize 62
1390 13:56:48.304681 [CA 4] Center 34 (4~65) winsize 62
1391 13:56:48.308031 [CA 5] Center 33 (3~64) winsize 62
1392 13:56:48.308533
1393 13:56:48.311145 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 13:56:48.311722
1395 13:56:48.314679 [CATrainingPosCal] consider 1 rank data
1396 13:56:48.318084 u2DelayCellTimex100 = 270/100 ps
1397 13:56:48.321801 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1398 13:56:48.325156 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1399 13:56:48.327974 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1400 13:56:48.334863 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 13:56:48.338222 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 13:56:48.341774 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1403 13:56:48.342281
1404 13:56:48.345393 CA PerBit enable=1, Macro0, CA PI delay=33
1405 13:56:48.345904
1406 13:56:48.348502 [CBTSetCACLKResult] CA Dly = 33
1407 13:56:48.348914 CS Dly: 5 (0~36)
1408 13:56:48.349240 ==
1409 13:56:48.351612 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 13:56:48.358388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 13:56:48.358922 ==
1412 13:56:48.362512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 13:56:48.368198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 13:56:48.376994 [CA 0] Center 36 (6~66) winsize 61
1415 13:56:48.380647 [CA 1] Center 36 (6~66) winsize 61
1416 13:56:48.384492 [CA 2] Center 34 (4~64) winsize 61
1417 13:56:48.388232 [CA 3] Center 33 (3~64) winsize 62
1418 13:56:48.391346 [CA 4] Center 34 (3~65) winsize 63
1419 13:56:48.395096 [CA 5] Center 33 (3~64) winsize 62
1420 13:56:48.395581
1421 13:56:48.399101 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 13:56:48.399529
1423 13:56:48.402591 [CATrainingPosCal] consider 2 rank data
1424 13:56:48.406305 u2DelayCellTimex100 = 270/100 ps
1425 13:56:48.409983 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1426 13:56:48.413734 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1427 13:56:48.417560 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 13:56:48.421309 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 13:56:48.424440 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1430 13:56:48.427702 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 13:56:48.428135
1432 13:56:48.431220 CA PerBit enable=1, Macro0, CA PI delay=33
1433 13:56:48.431648
1434 13:56:48.435279 [CBTSetCACLKResult] CA Dly = 33
1435 13:56:48.435815 CS Dly: 6 (0~38)
1436 13:56:48.436261
1437 13:56:48.438165 ----->DramcWriteLeveling(PI) begin...
1438 13:56:48.438644 ==
1439 13:56:48.441758 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 13:56:48.447914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 13:56:48.448351 ==
1442 13:56:48.451724 Write leveling (Byte 0): 28 => 28
1443 13:56:48.452157 Write leveling (Byte 1): 28 => 28
1444 13:56:48.454778 DramcWriteLeveling(PI) end<-----
1445 13:56:48.455209
1446 13:56:48.455646 ==
1447 13:56:48.458015 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 13:56:48.465141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 13:56:48.465653 ==
1450 13:56:48.465987 [Gating] SW mode calibration
1451 13:56:48.475294 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 13:56:48.478514 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 13:56:48.481849 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1454 13:56:48.488326 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 13:56:48.491475 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:56:48.495429 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:56:48.501852 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:56:48.505349 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:56:48.509049 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:56:48.516324 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:56:48.518794 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:56:48.522137 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:56:48.525229 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:56:48.531976 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:56:48.535576 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:56:48.539259 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:56:48.546017 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:56:48.548939 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:56:48.552954 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:56:48.559125 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1471 13:56:48.562089 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1472 13:56:48.565484 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:56:48.572692 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:56:48.575677 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1475 13:56:48.579025 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:56:48.585921 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:56:48.589704 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:56:48.592642 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:56:48.596329 0 9 8 | B1->B0 | 2424 2525 | 0 1 | (0 0) (1 1)
1480 13:56:48.602475 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1481 13:56:48.605802 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 13:56:48.609583 0 9 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1483 13:56:48.615893 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 13:56:48.619542 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 13:56:48.622972 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 13:56:48.629650 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1487 13:56:48.632607 0 10 8 | B1->B0 | 2e2e 2d2d | 0 1 | (1 0) (1 0)
1488 13:56:48.635978 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:56:48.643246 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:56:48.646835 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:56:48.649699 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:56:48.652949 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1493 13:56:48.659597 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:56:48.663090 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1495 13:56:48.666626 0 11 8 | B1->B0 | 3131 2f2f | 1 0 | (0 0) (0 0)
1496 13:56:48.673602 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:56:48.676221 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 13:56:48.679796 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 13:56:48.686394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 13:56:48.690171 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 13:56:48.693349 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 13:56:48.699749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1503 13:56:48.703274 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1504 13:56:48.706900 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:56:48.710283 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:56:48.716926 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:56:48.720377 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:56:48.723816 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:56:48.730263 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:56:48.733815 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:56:48.736949 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:56:48.743933 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:56:48.747640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:56:48.750456 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:56:48.757263 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 13:56:48.760478 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 13:56:48.763488 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 13:56:48.770586 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 13:56:48.773778 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 13:56:48.777103 Total UI for P1: 0, mck2ui 16
1521 13:56:48.780434 best dqsien dly found for B0: ( 0, 14, 6)
1522 13:56:48.783822 Total UI for P1: 0, mck2ui 16
1523 13:56:48.787512 best dqsien dly found for B1: ( 0, 14, 6)
1524 13:56:48.790573 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1525 13:56:48.794174 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1526 13:56:48.794677
1527 13:56:48.797575 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 13:56:48.800674 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 13:56:48.803829 [Gating] SW calibration Done
1530 13:56:48.804282 ==
1531 13:56:48.806889 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 13:56:48.810535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 13:56:48.811044 ==
1534 13:56:48.813941 RX Vref Scan: 0
1535 13:56:48.814349
1536 13:56:48.814720 RX Vref 0 -> 0, step: 1
1537 13:56:48.815023
1538 13:56:48.817660 RX Delay -130 -> 252, step: 16
1539 13:56:48.820582 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1540 13:56:48.827614 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1541 13:56:48.831293 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1542 13:56:48.834801 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1543 13:56:48.838078 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1544 13:56:48.841063 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1545 13:56:48.844642 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1546 13:56:48.851173 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1547 13:56:48.854647 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1548 13:56:48.857814 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1549 13:56:48.861174 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1550 13:56:48.864000 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1551 13:56:48.871022 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1552 13:56:48.874560 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1553 13:56:48.878077 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1554 13:56:48.880952 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1555 13:56:48.881367 ==
1556 13:56:48.884777 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 13:56:48.891648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 13:56:48.892154 ==
1559 13:56:48.892482 DQS Delay:
1560 13:56:48.892784 DQS0 = 0, DQS1 = 0
1561 13:56:48.894458 DQM Delay:
1562 13:56:48.894868 DQM0 = 83, DQM1 = 76
1563 13:56:48.897902 DQ Delay:
1564 13:56:48.901655 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1565 13:56:48.902210 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =85
1566 13:56:48.904694 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1567 13:56:48.908006 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1568 13:56:48.910994
1569 13:56:48.911403
1570 13:56:48.911726 ==
1571 13:56:48.914505 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 13:56:48.918390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 13:56:48.918850 ==
1574 13:56:48.919177
1575 13:56:48.919476
1576 13:56:48.921329 TX Vref Scan disable
1577 13:56:48.921738 == TX Byte 0 ==
1578 13:56:48.928172 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1579 13:56:48.931817 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1580 13:56:48.932234 == TX Byte 1 ==
1581 13:56:48.934805 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1582 13:56:48.941918 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1583 13:56:48.942482 ==
1584 13:56:48.944783 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 13:56:48.948358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 13:56:48.948772 ==
1587 13:56:48.961623 TX Vref=22, minBit 10, minWin=26, winSum=439
1588 13:56:48.964812 TX Vref=24, minBit 3, minWin=27, winSum=444
1589 13:56:48.969323 TX Vref=26, minBit 0, minWin=27, winSum=447
1590 13:56:48.972816 TX Vref=28, minBit 4, minWin=27, winSum=447
1591 13:56:48.975753 TX Vref=30, minBit 0, minWin=28, winSum=449
1592 13:56:48.979129 TX Vref=32, minBit 0, minWin=28, winSum=452
1593 13:56:48.986068 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
1594 13:56:48.986610
1595 13:56:48.989538 Final TX Range 1 Vref 32
1596 13:56:48.990048
1597 13:56:48.990378 ==
1598 13:56:48.992412 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 13:56:48.995863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 13:56:48.996277 ==
1601 13:56:48.996657
1602 13:56:48.997004
1603 13:56:48.998909 TX Vref Scan disable
1604 13:56:49.002710 == TX Byte 0 ==
1605 13:56:49.006686 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1606 13:56:49.009283 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1607 13:56:49.012566 == TX Byte 1 ==
1608 13:56:49.016103 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1609 13:56:49.019200 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1610 13:56:49.019612
1611 13:56:49.019935 [DATLAT]
1612 13:56:49.022927 Freq=800, CH1 RK0
1613 13:56:49.023341
1614 13:56:49.026138 DATLAT Default: 0xa
1615 13:56:49.026591 0, 0xFFFF, sum = 0
1616 13:56:49.029399 1, 0xFFFF, sum = 0
1617 13:56:49.029764 2, 0xFFFF, sum = 0
1618 13:56:49.033099 3, 0xFFFF, sum = 0
1619 13:56:49.033524 4, 0xFFFF, sum = 0
1620 13:56:49.036336 5, 0xFFFF, sum = 0
1621 13:56:49.036846 6, 0xFFFF, sum = 0
1622 13:56:49.039424 7, 0xFFFF, sum = 0
1623 13:56:49.039853 8, 0xFFFF, sum = 0
1624 13:56:49.042984 9, 0x0, sum = 1
1625 13:56:49.043406 10, 0x0, sum = 2
1626 13:56:49.046229 11, 0x0, sum = 3
1627 13:56:49.046781 12, 0x0, sum = 4
1628 13:56:49.047163 best_step = 10
1629 13:56:49.047499
1630 13:56:49.049618 ==
1631 13:56:49.052935 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 13:56:49.056113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 13:56:49.056559 ==
1634 13:56:49.056888 RX Vref Scan: 1
1635 13:56:49.057238
1636 13:56:49.059831 Set Vref Range= 32 -> 127
1637 13:56:49.060240
1638 13:56:49.062935 RX Vref 32 -> 127, step: 1
1639 13:56:49.063348
1640 13:56:49.066651 RX Delay -111 -> 252, step: 8
1641 13:56:49.067070
1642 13:56:49.069747 Set Vref, RX VrefLevel [Byte0]: 32
1643 13:56:49.073049 [Byte1]: 32
1644 13:56:49.073505
1645 13:56:49.076601 Set Vref, RX VrefLevel [Byte0]: 33
1646 13:56:49.080069 [Byte1]: 33
1647 13:56:49.080491
1648 13:56:49.082833 Set Vref, RX VrefLevel [Byte0]: 34
1649 13:56:49.086316 [Byte1]: 34
1650 13:56:49.089347
1651 13:56:49.089751 Set Vref, RX VrefLevel [Byte0]: 35
1652 13:56:49.092706 [Byte1]: 35
1653 13:56:49.096907
1654 13:56:49.097315 Set Vref, RX VrefLevel [Byte0]: 36
1655 13:56:49.100608 [Byte1]: 36
1656 13:56:49.104827
1657 13:56:49.105256 Set Vref, RX VrefLevel [Byte0]: 37
1658 13:56:49.108376 [Byte1]: 37
1659 13:56:49.112245
1660 13:56:49.112652 Set Vref, RX VrefLevel [Byte0]: 38
1661 13:56:49.115543 [Byte1]: 38
1662 13:56:49.120280
1663 13:56:49.120688 Set Vref, RX VrefLevel [Byte0]: 39
1664 13:56:49.123304 [Byte1]: 39
1665 13:56:49.127911
1666 13:56:49.128368 Set Vref, RX VrefLevel [Byte0]: 40
1667 13:56:49.131250 [Byte1]: 40
1668 13:56:49.135313
1669 13:56:49.135989 Set Vref, RX VrefLevel [Byte0]: 41
1670 13:56:49.138772 [Byte1]: 41
1671 13:56:49.143091
1672 13:56:49.143697 Set Vref, RX VrefLevel [Byte0]: 42
1673 13:56:49.146579 [Byte1]: 42
1674 13:56:49.150262
1675 13:56:49.154116 Set Vref, RX VrefLevel [Byte0]: 43
1676 13:56:49.154764 [Byte1]: 43
1677 13:56:49.158223
1678 13:56:49.158878 Set Vref, RX VrefLevel [Byte0]: 44
1679 13:56:49.161306 [Byte1]: 44
1680 13:56:49.165709
1681 13:56:49.165930 Set Vref, RX VrefLevel [Byte0]: 45
1682 13:56:49.169577 [Byte1]: 45
1683 13:56:49.173582
1684 13:56:49.173826 Set Vref, RX VrefLevel [Byte0]: 46
1685 13:56:49.176503 [Byte1]: 46
1686 13:56:49.181029
1687 13:56:49.181158 Set Vref, RX VrefLevel [Byte0]: 47
1688 13:56:49.184391 [Byte1]: 47
1689 13:56:49.189174
1690 13:56:49.189276 Set Vref, RX VrefLevel [Byte0]: 48
1691 13:56:49.192476 [Byte1]: 48
1692 13:56:49.196238
1693 13:56:49.196347 Set Vref, RX VrefLevel [Byte0]: 49
1694 13:56:49.199538 [Byte1]: 49
1695 13:56:49.203820
1696 13:56:49.203932 Set Vref, RX VrefLevel [Byte0]: 50
1697 13:56:49.206831 [Byte1]: 50
1698 13:56:49.211609
1699 13:56:49.211692 Set Vref, RX VrefLevel [Byte0]: 51
1700 13:56:49.214684 [Byte1]: 51
1701 13:56:49.219408
1702 13:56:49.219495 Set Vref, RX VrefLevel [Byte0]: 52
1703 13:56:49.222359 [Byte1]: 52
1704 13:56:49.226540
1705 13:56:49.226624 Set Vref, RX VrefLevel [Byte0]: 53
1706 13:56:49.229914 [Byte1]: 53
1707 13:56:49.234580
1708 13:56:49.234680 Set Vref, RX VrefLevel [Byte0]: 54
1709 13:56:49.237881 [Byte1]: 54
1710 13:56:49.242061
1711 13:56:49.242132 Set Vref, RX VrefLevel [Byte0]: 55
1712 13:56:49.245136 [Byte1]: 55
1713 13:56:49.249372
1714 13:56:49.253221 Set Vref, RX VrefLevel [Byte0]: 56
1715 13:56:49.253304 [Byte1]: 56
1716 13:56:49.257742
1717 13:56:49.257825 Set Vref, RX VrefLevel [Byte0]: 57
1718 13:56:49.260359 [Byte1]: 57
1719 13:56:49.264728
1720 13:56:49.264816 Set Vref, RX VrefLevel [Byte0]: 58
1721 13:56:49.268206 [Byte1]: 58
1722 13:56:49.272310
1723 13:56:49.272391 Set Vref, RX VrefLevel [Byte0]: 59
1724 13:56:49.276045 [Byte1]: 59
1725 13:56:49.280659
1726 13:56:49.280742 Set Vref, RX VrefLevel [Byte0]: 60
1727 13:56:49.283466 [Byte1]: 60
1728 13:56:49.287678
1729 13:56:49.287758 Set Vref, RX VrefLevel [Byte0]: 61
1730 13:56:49.291217 [Byte1]: 61
1731 13:56:49.295931
1732 13:56:49.296020 Set Vref, RX VrefLevel [Byte0]: 62
1733 13:56:49.298704 [Byte1]: 62
1734 13:56:49.303226
1735 13:56:49.303311 Set Vref, RX VrefLevel [Byte0]: 63
1736 13:56:49.306599 [Byte1]: 63
1737 13:56:49.310751
1738 13:56:49.310836 Set Vref, RX VrefLevel [Byte0]: 64
1739 13:56:49.313890 [Byte1]: 64
1740 13:56:49.318769
1741 13:56:49.318852 Set Vref, RX VrefLevel [Byte0]: 65
1742 13:56:49.321803 [Byte1]: 65
1743 13:56:49.326006
1744 13:56:49.326089 Set Vref, RX VrefLevel [Byte0]: 66
1745 13:56:49.329676 [Byte1]: 66
1746 13:56:49.334604
1747 13:56:49.334686 Set Vref, RX VrefLevel [Byte0]: 67
1748 13:56:49.336901 [Byte1]: 67
1749 13:56:49.341114
1750 13:56:49.341196 Set Vref, RX VrefLevel [Byte0]: 68
1751 13:56:49.344695 [Byte1]: 68
1752 13:56:49.349167
1753 13:56:49.352364 Set Vref, RX VrefLevel [Byte0]: 69
1754 13:56:49.352482 [Byte1]: 69
1755 13:56:49.356882
1756 13:56:49.356999 Set Vref, RX VrefLevel [Byte0]: 70
1757 13:56:49.359831 [Byte1]: 70
1758 13:56:49.364831
1759 13:56:49.364911 Set Vref, RX VrefLevel [Byte0]: 71
1760 13:56:49.367503 [Byte1]: 71
1761 13:56:49.371833
1762 13:56:49.371953 Set Vref, RX VrefLevel [Byte0]: 72
1763 13:56:49.375402 [Byte1]: 72
1764 13:56:49.379642
1765 13:56:49.379732 Set Vref, RX VrefLevel [Byte0]: 73
1766 13:56:49.383273 [Byte1]: 73
1767 13:56:49.387517
1768 13:56:49.387598 Set Vref, RX VrefLevel [Byte0]: 74
1769 13:56:49.390336 [Byte1]: 74
1770 13:56:49.394826
1771 13:56:49.394919 Set Vref, RX VrefLevel [Byte0]: 75
1772 13:56:49.398443 [Byte1]: 75
1773 13:56:49.402910
1774 13:56:49.402990 Set Vref, RX VrefLevel [Byte0]: 76
1775 13:56:49.405921 [Byte1]: 76
1776 13:56:49.410440
1777 13:56:49.410520 Set Vref, RX VrefLevel [Byte0]: 77
1778 13:56:49.413522 [Byte1]: 77
1779 13:56:49.417784
1780 13:56:49.417864 Set Vref, RX VrefLevel [Byte0]: 78
1781 13:56:49.420972 [Byte1]: 78
1782 13:56:49.425518
1783 13:56:49.425635 Set Vref, RX VrefLevel [Byte0]: 79
1784 13:56:49.428975 [Byte1]: 79
1785 13:56:49.433477
1786 13:56:49.433557 Set Vref, RX VrefLevel [Byte0]: 80
1787 13:56:49.436607 [Byte1]: 80
1788 13:56:49.440854
1789 13:56:49.440933 Final RX Vref Byte 0 = 58 to rank0
1790 13:56:49.444396 Final RX Vref Byte 1 = 57 to rank0
1791 13:56:49.447798 Final RX Vref Byte 0 = 58 to rank1
1792 13:56:49.450972 Final RX Vref Byte 1 = 57 to rank1==
1793 13:56:49.454196 Dram Type= 6, Freq= 0, CH_1, rank 0
1794 13:56:49.457702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 13:56:49.461075 ==
1796 13:56:49.461155 DQS Delay:
1797 13:56:49.461234 DQS0 = 0, DQS1 = 0
1798 13:56:49.464329 DQM Delay:
1799 13:56:49.464470 DQM0 = 83, DQM1 = 73
1800 13:56:49.467650 DQ Delay:
1801 13:56:49.467756 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1802 13:56:49.471202 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1803 13:56:49.474788 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1804 13:56:49.477945 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1805 13:56:49.478036
1806 13:56:49.478187
1807 13:56:49.487879 [DQSOSCAuto] RK0, (LSB)MR18= 0x2aff, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1808 13:56:49.491086 CH1 RK0: MR19=605, MR18=2AFF
1809 13:56:49.495007 CH1_RK0: MR19=0x605, MR18=0x2AFF, DQSOSC=399, MR23=63, INC=92, DEC=61
1810 13:56:49.498674
1811 13:56:49.501306 ----->DramcWriteLeveling(PI) begin...
1812 13:56:49.501387 ==
1813 13:56:49.504940 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 13:56:49.508330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 13:56:49.508411 ==
1816 13:56:49.511467 Write leveling (Byte 0): 28 => 28
1817 13:56:49.514856 Write leveling (Byte 1): 32 => 32
1818 13:56:49.518302 DramcWriteLeveling(PI) end<-----
1819 13:56:49.518381
1820 13:56:49.518490 ==
1821 13:56:49.521520 Dram Type= 6, Freq= 0, CH_1, rank 1
1822 13:56:49.524799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 13:56:49.524885 ==
1824 13:56:49.528441 [Gating] SW mode calibration
1825 13:56:49.535028 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1826 13:56:49.538318 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1827 13:56:49.545190 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1828 13:56:49.548141 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
1829 13:56:49.552006 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:56:49.558597 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:56:49.561812 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:56:49.565372 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1833 13:56:49.571770 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:56:49.575078 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1835 13:56:49.578291 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:56:49.585171 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 13:56:49.588656 0 7 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1838 13:56:49.591760 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:56:49.595001 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:56:49.602193 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:56:49.605309 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:56:49.608729 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:56:49.615433 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1844 13:56:49.618764 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (1 1)
1845 13:56:49.622103 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:56:49.628962 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:56:49.631901 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:56:49.635489 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:56:49.642004 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:56:49.645358 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:56:49.648730 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:56:49.655518 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1853 13:56:49.658694 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1854 13:56:49.662348 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1855 13:56:49.665662 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 13:56:49.672759 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 13:56:49.675569 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 13:56:49.679259 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1859 13:56:49.685928 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1860 13:56:49.689188 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (0 0) (0 0)
1861 13:56:49.692824 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1862 13:56:49.699188 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:56:49.702622 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:56:49.706045 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:56:49.712356 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:56:49.716176 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:56:49.719465 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 13:56:49.722800 0 11 4 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (0 0)
1869 13:56:49.729954 0 11 8 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
1870 13:56:49.732884 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 13:56:49.735974 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 13:56:49.742953 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 13:56:49.746005 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 13:56:49.749152 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 13:56:49.755869 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 13:56:49.759644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1877 13:56:49.763362 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1878 13:56:49.769321 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:56:49.772777 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:56:49.776430 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 13:56:49.782670 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 13:56:49.785980 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 13:56:49.789871 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 13:56:49.796349 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 13:56:49.799494 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 13:56:49.802781 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 13:56:49.806266 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 13:56:49.813104 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 13:56:49.816425 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 13:56:49.819652 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 13:56:49.826787 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 13:56:49.830713 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1893 13:56:49.833671 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 13:56:49.836682 Total UI for P1: 0, mck2ui 16
1895 13:56:49.839706 best dqsien dly found for B0: ( 0, 14, 4)
1896 13:56:49.843146 Total UI for P1: 0, mck2ui 16
1897 13:56:49.847117 best dqsien dly found for B1: ( 0, 14, 4)
1898 13:56:49.849639 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1899 13:56:49.852932 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1900 13:56:49.853004
1901 13:56:49.856705 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1902 13:56:49.863075 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1903 13:56:49.863149 [Gating] SW calibration Done
1904 13:56:49.863210 ==
1905 13:56:49.867428 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 13:56:49.873083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 13:56:49.873165 ==
1908 13:56:49.873228 RX Vref Scan: 0
1909 13:56:49.873291
1910 13:56:49.876609 RX Vref 0 -> 0, step: 1
1911 13:56:49.876690
1912 13:56:49.880192 RX Delay -130 -> 252, step: 16
1913 13:56:49.883762 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1914 13:56:49.886551 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1915 13:56:49.890158 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1916 13:56:49.893251 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1917 13:56:49.900158 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1918 13:56:49.903770 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1919 13:56:49.907198 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1920 13:56:49.910092 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1921 13:56:49.913545 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1922 13:56:49.920034 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1923 13:56:49.924108 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1924 13:56:49.926962 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1925 13:56:49.930034 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1926 13:56:49.933444 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1927 13:56:49.941634 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1928 13:56:49.943858 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1929 13:56:49.943938 ==
1930 13:56:49.947307 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 13:56:49.950445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 13:56:49.950532 ==
1933 13:56:49.953753 DQS Delay:
1934 13:56:49.953832 DQS0 = 0, DQS1 = 0
1935 13:56:49.953895 DQM Delay:
1936 13:56:49.956840 DQM0 = 82, DQM1 = 79
1937 13:56:49.956922 DQ Delay:
1938 13:56:49.960480 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1939 13:56:49.963668 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1940 13:56:49.966881 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1941 13:56:49.970271 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1942 13:56:49.970351
1943 13:56:49.970463
1944 13:56:49.970523 ==
1945 13:56:49.973729 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 13:56:49.977195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 13:56:49.980536 ==
1948 13:56:49.980616
1949 13:56:49.980678
1950 13:56:49.980737 TX Vref Scan disable
1951 13:56:49.984012 == TX Byte 0 ==
1952 13:56:49.987168 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1953 13:56:49.990368 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1954 13:56:49.993620 == TX Byte 1 ==
1955 13:56:49.996930 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1956 13:56:50.000359 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1957 13:56:50.003985 ==
1958 13:56:50.004057 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 13:56:50.010773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 13:56:50.010848 ==
1961 13:56:50.023214 TX Vref=22, minBit 6, minWin=27, winSum=445
1962 13:56:50.026575 TX Vref=24, minBit 5, minWin=27, winSum=444
1963 13:56:50.029727 TX Vref=26, minBit 10, minWin=27, winSum=448
1964 13:56:50.033241 TX Vref=28, minBit 0, minWin=28, winSum=451
1965 13:56:50.036351 TX Vref=30, minBit 0, minWin=28, winSum=452
1966 13:56:50.039996 TX Vref=32, minBit 0, minWin=28, winSum=454
1967 13:56:50.046341 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1968 13:56:50.046452
1969 13:56:50.049782 Final TX Range 1 Vref 32
1970 13:56:50.049851
1971 13:56:50.049910 ==
1972 13:56:50.053430 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 13:56:50.056711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 13:56:50.056782 ==
1975 13:56:50.056841
1976 13:56:50.056896
1977 13:56:50.059662 TX Vref Scan disable
1978 13:56:50.063456 == TX Byte 0 ==
1979 13:56:50.066918 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1980 13:56:50.070256 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1981 13:56:50.073952 == TX Byte 1 ==
1982 13:56:50.077198 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1983 13:56:50.080745 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1984 13:56:50.080826
1985 13:56:50.083778 [DATLAT]
1986 13:56:50.083850 Freq=800, CH1 RK1
1987 13:56:50.083911
1988 13:56:50.087241 DATLAT Default: 0xa
1989 13:56:50.087307 0, 0xFFFF, sum = 0
1990 13:56:50.090198 1, 0xFFFF, sum = 0
1991 13:56:50.090267 2, 0xFFFF, sum = 0
1992 13:56:50.094055 3, 0xFFFF, sum = 0
1993 13:56:50.094132 4, 0xFFFF, sum = 0
1994 13:56:50.096941 5, 0xFFFF, sum = 0
1995 13:56:50.097014 6, 0xFFFF, sum = 0
1996 13:56:50.100651 7, 0xFFFF, sum = 0
1997 13:56:50.100725 8, 0xFFFF, sum = 0
1998 13:56:50.103535 9, 0x0, sum = 1
1999 13:56:50.103604 10, 0x0, sum = 2
2000 13:56:50.106700 11, 0x0, sum = 3
2001 13:56:50.106772 12, 0x0, sum = 4
2002 13:56:50.110063 best_step = 10
2003 13:56:50.110129
2004 13:56:50.110186 ==
2005 13:56:50.113557 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 13:56:50.117228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 13:56:50.117312 ==
2008 13:56:50.120257 RX Vref Scan: 0
2009 13:56:50.120334
2010 13:56:50.120422 RX Vref 0 -> 0, step: 1
2011 13:56:50.120497
2012 13:56:50.123828 RX Delay -95 -> 252, step: 8
2013 13:56:50.130062 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2014 13:56:50.133338 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2015 13:56:50.137037 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2016 13:56:50.140309 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2017 13:56:50.143414 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2018 13:56:50.146821 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2019 13:56:50.153646 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2020 13:56:50.157155 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2021 13:56:50.160207 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2022 13:56:50.163669 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2023 13:56:50.167138 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2024 13:56:50.174034 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2025 13:56:50.177511 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2026 13:56:50.181141 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2027 13:56:50.183905 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2028 13:56:50.187272 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2029 13:56:50.187351 ==
2030 13:56:50.190784 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 13:56:50.197197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 13:56:50.197279 ==
2033 13:56:50.197363 DQS Delay:
2034 13:56:50.200692 DQS0 = 0, DQS1 = 0
2035 13:56:50.200770 DQM Delay:
2036 13:56:50.200857 DQM0 = 80, DQM1 = 75
2037 13:56:50.203913 DQ Delay:
2038 13:56:50.207266 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2039 13:56:50.211016 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2040 13:56:50.214237 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2041 13:56:50.217361 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2042 13:56:50.217459
2043 13:56:50.217546
2044 13:56:50.224028 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2045 13:56:50.227662 CH1 RK1: MR19=606, MR18=1F29
2046 13:56:50.234207 CH1_RK1: MR19=0x606, MR18=0x1F29, DQSOSC=399, MR23=63, INC=92, DEC=61
2047 13:56:50.237234 [RxdqsGatingPostProcess] freq 800
2048 13:56:50.240717 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2049 13:56:50.244246 Pre-setting of DQS Precalculation
2050 13:56:50.251034 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2051 13:56:50.257652 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2052 13:56:50.264257 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2053 13:56:50.264337
2054 13:56:50.264400
2055 13:56:50.267605 [Calibration Summary] 1600 Mbps
2056 13:56:50.267685 CH 0, Rank 0
2057 13:56:50.271034 SW Impedance : PASS
2058 13:56:50.274295 DUTY Scan : NO K
2059 13:56:50.274374 ZQ Calibration : PASS
2060 13:56:50.277797 Jitter Meter : NO K
2061 13:56:50.277877 CBT Training : PASS
2062 13:56:50.280764 Write leveling : PASS
2063 13:56:50.284341 RX DQS gating : PASS
2064 13:56:50.284420 RX DQ/DQS(RDDQC) : PASS
2065 13:56:50.288067 TX DQ/DQS : PASS
2066 13:56:50.291048 RX DATLAT : PASS
2067 13:56:50.291127 RX DQ/DQS(Engine): PASS
2068 13:56:50.294584 TX OE : NO K
2069 13:56:50.294663 All Pass.
2070 13:56:50.294726
2071 13:56:50.297656 CH 0, Rank 1
2072 13:56:50.297737 SW Impedance : PASS
2073 13:56:50.301144 DUTY Scan : NO K
2074 13:56:50.304671 ZQ Calibration : PASS
2075 13:56:50.304751 Jitter Meter : NO K
2076 13:56:50.307628 CBT Training : PASS
2077 13:56:50.307708 Write leveling : PASS
2078 13:56:50.311631 RX DQS gating : PASS
2079 13:56:50.314316 RX DQ/DQS(RDDQC) : PASS
2080 13:56:50.314418 TX DQ/DQS : PASS
2081 13:56:50.317872 RX DATLAT : PASS
2082 13:56:50.321169 RX DQ/DQS(Engine): PASS
2083 13:56:50.321249 TX OE : NO K
2084 13:56:50.324904 All Pass.
2085 13:56:50.324983
2086 13:56:50.325046 CH 1, Rank 0
2087 13:56:50.327794 SW Impedance : PASS
2088 13:56:50.327899 DUTY Scan : NO K
2089 13:56:50.331787 ZQ Calibration : PASS
2090 13:56:50.334732 Jitter Meter : NO K
2091 13:56:50.334813 CBT Training : PASS
2092 13:56:50.338263 Write leveling : PASS
2093 13:56:50.341976 RX DQS gating : PASS
2094 13:56:50.342055 RX DQ/DQS(RDDQC) : PASS
2095 13:56:50.344946 TX DQ/DQS : PASS
2096 13:56:50.345026 RX DATLAT : PASS
2097 13:56:50.348713 RX DQ/DQS(Engine): PASS
2098 13:56:50.351785 TX OE : NO K
2099 13:56:50.351865 All Pass.
2100 13:56:50.351928
2101 13:56:50.351986 CH 1, Rank 1
2102 13:56:50.355001 SW Impedance : PASS
2103 13:56:50.358424 DUTY Scan : NO K
2104 13:56:50.358517 ZQ Calibration : PASS
2105 13:56:50.361625 Jitter Meter : NO K
2106 13:56:50.365033 CBT Training : PASS
2107 13:56:50.365112 Write leveling : PASS
2108 13:56:50.368400 RX DQS gating : PASS
2109 13:56:50.372259 RX DQ/DQS(RDDQC) : PASS
2110 13:56:50.372338 TX DQ/DQS : PASS
2111 13:56:50.375713 RX DATLAT : PASS
2112 13:56:50.375793 RX DQ/DQS(Engine): PASS
2113 13:56:50.378787 TX OE : NO K
2114 13:56:50.378867 All Pass.
2115 13:56:50.378929
2116 13:56:50.382530 DramC Write-DBI off
2117 13:56:50.385273 PER_BANK_REFRESH: Hybrid Mode
2118 13:56:50.385353 TX_TRACKING: ON
2119 13:56:50.388703 [GetDramInforAfterCalByMRR] Vendor 6.
2120 13:56:50.392931 [GetDramInforAfterCalByMRR] Revision 606.
2121 13:56:50.395248 [GetDramInforAfterCalByMRR] Revision 2 0.
2122 13:56:50.398973 MR0 0x3b3b
2123 13:56:50.399053 MR8 0x5151
2124 13:56:50.401809 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 13:56:50.401889
2126 13:56:50.405029 MR0 0x3b3b
2127 13:56:50.405108 MR8 0x5151
2128 13:56:50.408387 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2129 13:56:50.408467
2130 13:56:50.419052 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2131 13:56:50.421933 [FAST_K] Save calibration result to emmc
2132 13:56:50.425780 [FAST_K] Save calibration result to emmc
2133 13:56:50.425860 dram_init: config_dvfs: 1
2134 13:56:50.432155 dramc_set_vcore_voltage set vcore to 662500
2135 13:56:50.432235 Read voltage for 1200, 2
2136 13:56:50.435723 Vio18 = 0
2137 13:56:50.435802 Vcore = 662500
2138 13:56:50.435872 Vdram = 0
2139 13:56:50.438790 Vddq = 0
2140 13:56:50.438869 Vmddr = 0
2141 13:56:50.442658 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2142 13:56:50.449104 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2143 13:56:50.452170 MEM_TYPE=3, freq_sel=15
2144 13:56:50.452249 sv_algorithm_assistance_LP4_1600
2145 13:56:50.458853 ============ PULL DRAM RESETB DOWN ============
2146 13:56:50.462145 ========== PULL DRAM RESETB DOWN end =========
2147 13:56:50.465753 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2148 13:56:50.469045 ===================================
2149 13:56:50.472316 LPDDR4 DRAM CONFIGURATION
2150 13:56:50.476029 ===================================
2151 13:56:50.479416 EX_ROW_EN[0] = 0x0
2152 13:56:50.479496 EX_ROW_EN[1] = 0x0
2153 13:56:50.482269 LP4Y_EN = 0x0
2154 13:56:50.482373 WORK_FSP = 0x0
2155 13:56:50.485873 WL = 0x4
2156 13:56:50.485951 RL = 0x4
2157 13:56:50.488844 BL = 0x2
2158 13:56:50.488923 RPST = 0x0
2159 13:56:50.492424 RD_PRE = 0x0
2160 13:56:50.492511 WR_PRE = 0x1
2161 13:56:50.495984 WR_PST = 0x0
2162 13:56:50.496062 DBI_WR = 0x0
2163 13:56:50.498868 DBI_RD = 0x0
2164 13:56:50.498952 OTF = 0x1
2165 13:56:50.502675 ===================================
2166 13:56:50.505820 ===================================
2167 13:56:50.509403 ANA top config
2168 13:56:50.512829 ===================================
2169 13:56:50.512909 DLL_ASYNC_EN = 0
2170 13:56:50.516286 ALL_SLAVE_EN = 0
2171 13:56:50.519547 NEW_RANK_MODE = 1
2172 13:56:50.522887 DLL_IDLE_MODE = 1
2173 13:56:50.522967 LP45_APHY_COMB_EN = 1
2174 13:56:50.526124 TX_ODT_DIS = 1
2175 13:56:50.529671 NEW_8X_MODE = 1
2176 13:56:50.532649 ===================================
2177 13:56:50.536367 ===================================
2178 13:56:50.539335 data_rate = 2400
2179 13:56:50.542750 CKR = 1
2180 13:56:50.546056 DQ_P2S_RATIO = 8
2181 13:56:50.549752 ===================================
2182 13:56:50.549832 CA_P2S_RATIO = 8
2183 13:56:50.552620 DQ_CA_OPEN = 0
2184 13:56:50.556344 DQ_SEMI_OPEN = 0
2185 13:56:50.559562 CA_SEMI_OPEN = 0
2186 13:56:50.562805 CA_FULL_RATE = 0
2187 13:56:50.562885 DQ_CKDIV4_EN = 0
2188 13:56:50.566377 CA_CKDIV4_EN = 0
2189 13:56:50.569344 CA_PREDIV_EN = 0
2190 13:56:50.572860 PH8_DLY = 17
2191 13:56:50.576137 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2192 13:56:50.580069 DQ_AAMCK_DIV = 4
2193 13:56:50.580146 CA_AAMCK_DIV = 4
2194 13:56:50.583023 CA_ADMCK_DIV = 4
2195 13:56:50.586296 DQ_TRACK_CA_EN = 0
2196 13:56:50.589868 CA_PICK = 1200
2197 13:56:50.593038 CA_MCKIO = 1200
2198 13:56:50.596982 MCKIO_SEMI = 0
2199 13:56:50.600256 PLL_FREQ = 2366
2200 13:56:50.600335 DQ_UI_PI_RATIO = 32
2201 13:56:50.602879 CA_UI_PI_RATIO = 0
2202 13:56:50.606720 ===================================
2203 13:56:50.609630 ===================================
2204 13:56:50.613518 memory_type:LPDDR4
2205 13:56:50.616478 GP_NUM : 10
2206 13:56:50.616557 SRAM_EN : 1
2207 13:56:50.619979 MD32_EN : 0
2208 13:56:50.623027 ===================================
2209 13:56:50.623106 [ANA_INIT] >>>>>>>>>>>>>>
2210 13:56:50.626841 <<<<<< [CONFIGURE PHASE]: ANA_TX
2211 13:56:50.629776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2212 13:56:50.633270 ===================================
2213 13:56:50.636717 data_rate = 2400,PCW = 0X5b00
2214 13:56:50.639931 ===================================
2215 13:56:50.643322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2216 13:56:50.649887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2217 13:56:50.653228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2218 13:56:50.660418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2219 13:56:50.663324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2220 13:56:50.666544 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2221 13:56:50.666623 [ANA_INIT] flow start
2222 13:56:50.670636 [ANA_INIT] PLL >>>>>>>>
2223 13:56:50.673479 [ANA_INIT] PLL <<<<<<<<
2224 13:56:50.677129 [ANA_INIT] MIDPI >>>>>>>>
2225 13:56:50.677209 [ANA_INIT] MIDPI <<<<<<<<
2226 13:56:50.680111 [ANA_INIT] DLL >>>>>>>>
2227 13:56:50.683442 [ANA_INIT] DLL <<<<<<<<
2228 13:56:50.683521 [ANA_INIT] flow end
2229 13:56:50.686849 ============ LP4 DIFF to SE enter ============
2230 13:56:50.693918 ============ LP4 DIFF to SE exit ============
2231 13:56:50.693998 [ANA_INIT] <<<<<<<<<<<<<
2232 13:56:50.696858 [Flow] Enable top DCM control >>>>>
2233 13:56:50.700562 [Flow] Enable top DCM control <<<<<
2234 13:56:50.703869 Enable DLL master slave shuffle
2235 13:56:50.710579 ==============================================================
2236 13:56:50.710659 Gating Mode config
2237 13:56:50.717449 ==============================================================
2238 13:56:50.720625 Config description:
2239 13:56:50.727235 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2240 13:56:50.734256 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2241 13:56:50.740702 SELPH_MODE 0: By rank 1: By Phase
2242 13:56:50.743695 ==============================================================
2243 13:56:50.747147 GAT_TRACK_EN = 1
2244 13:56:50.750753 RX_GATING_MODE = 2
2245 13:56:50.754584 RX_GATING_TRACK_MODE = 2
2246 13:56:50.757483 SELPH_MODE = 1
2247 13:56:50.761100 PICG_EARLY_EN = 1
2248 13:56:50.764447 VALID_LAT_VALUE = 1
2249 13:56:50.770705 ==============================================================
2250 13:56:50.774006 Enter into Gating configuration >>>>
2251 13:56:50.777534 Exit from Gating configuration <<<<
2252 13:56:50.777605 Enter into DVFS_PRE_config >>>>>
2253 13:56:50.791177 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2254 13:56:50.794260 Exit from DVFS_PRE_config <<<<<
2255 13:56:50.797321 Enter into PICG configuration >>>>
2256 13:56:50.800796 Exit from PICG configuration <<<<
2257 13:56:50.800872 [RX_INPUT] configuration >>>>>
2258 13:56:50.804494 [RX_INPUT] configuration <<<<<
2259 13:56:50.811011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2260 13:56:50.814430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2261 13:56:50.821046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2262 13:56:50.827575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2263 13:56:50.834313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2264 13:56:50.841217 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2265 13:56:50.844376 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2266 13:56:50.848091 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2267 13:56:50.851252 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2268 13:56:50.857746 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2269 13:56:50.861120 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2270 13:56:50.864303 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 13:56:50.867715 ===================================
2272 13:56:50.871341 LPDDR4 DRAM CONFIGURATION
2273 13:56:50.874410 ===================================
2274 13:56:50.874480 EX_ROW_EN[0] = 0x0
2275 13:56:50.877982 EX_ROW_EN[1] = 0x0
2276 13:56:50.878052 LP4Y_EN = 0x0
2277 13:56:50.881700 WORK_FSP = 0x0
2278 13:56:50.884612 WL = 0x4
2279 13:56:50.884685 RL = 0x4
2280 13:56:50.888194 BL = 0x2
2281 13:56:50.888265 RPST = 0x0
2282 13:56:50.891688 RD_PRE = 0x0
2283 13:56:50.891757 WR_PRE = 0x1
2284 13:56:50.894616 WR_PST = 0x0
2285 13:56:50.894707 DBI_WR = 0x0
2286 13:56:50.898235 DBI_RD = 0x0
2287 13:56:50.898317 OTF = 0x1
2288 13:56:50.901392 ===================================
2289 13:56:50.904727 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2290 13:56:50.911799 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2291 13:56:50.915046 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2292 13:56:50.918884 ===================================
2293 13:56:50.921655 LPDDR4 DRAM CONFIGURATION
2294 13:56:50.925141 ===================================
2295 13:56:50.925214 EX_ROW_EN[0] = 0x10
2296 13:56:50.928114 EX_ROW_EN[1] = 0x0
2297 13:56:50.928179 LP4Y_EN = 0x0
2298 13:56:50.931738 WORK_FSP = 0x0
2299 13:56:50.931805 WL = 0x4
2300 13:56:50.934773 RL = 0x4
2301 13:56:50.934844 BL = 0x2
2302 13:56:50.938071 RPST = 0x0
2303 13:56:50.938168 RD_PRE = 0x0
2304 13:56:50.941589 WR_PRE = 0x1
2305 13:56:50.941656 WR_PST = 0x0
2306 13:56:50.944993 DBI_WR = 0x0
2307 13:56:50.945059 DBI_RD = 0x0
2308 13:56:50.948262 OTF = 0x1
2309 13:56:50.951954 ===================================
2310 13:56:50.958823 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2311 13:56:50.958897 ==
2312 13:56:50.961750 Dram Type= 6, Freq= 0, CH_0, rank 0
2313 13:56:50.965063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2314 13:56:50.965163 ==
2315 13:56:50.968506 [Duty_Offset_Calibration]
2316 13:56:50.968573 B0:2 B1:-1 CA:1
2317 13:56:50.968634
2318 13:56:50.971553 [DutyScan_Calibration_Flow] k_type=0
2319 13:56:50.981653
2320 13:56:50.981731 ==CLK 0==
2321 13:56:50.984793 Final CLK duty delay cell = -4
2322 13:56:50.987944 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2323 13:56:50.991577 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2324 13:56:50.994846 [-4] AVG Duty = 4953%(X100)
2325 13:56:50.994919
2326 13:56:50.998078 CH0 CLK Duty spec in!! Max-Min= 156%
2327 13:56:51.001991 [DutyScan_Calibration_Flow] ====Done====
2328 13:56:51.002063
2329 13:56:51.005168 [DutyScan_Calibration_Flow] k_type=1
2330 13:56:51.019698
2331 13:56:51.019774 ==DQS 0 ==
2332 13:56:51.022921 Final DQS duty delay cell = -4
2333 13:56:51.026224 [-4] MAX Duty = 5031%(X100), DQS PI = 54
2334 13:56:51.029418 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2335 13:56:51.032768 [-4] AVG Duty = 4953%(X100)
2336 13:56:51.032836
2337 13:56:51.032895 ==DQS 1 ==
2338 13:56:51.036148 Final DQS duty delay cell = -4
2339 13:56:51.039467 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2340 13:56:51.042808 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2341 13:56:51.046335 [-4] AVG Duty = 5062%(X100)
2342 13:56:51.046454
2343 13:56:51.049765 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2344 13:56:51.049833
2345 13:56:51.052684 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2346 13:56:51.056718 [DutyScan_Calibration_Flow] ====Done====
2347 13:56:51.056788
2348 13:56:51.059707 [DutyScan_Calibration_Flow] k_type=3
2349 13:56:51.076961
2350 13:56:51.077043 ==DQM 0 ==
2351 13:56:51.079972 Final DQM duty delay cell = 0
2352 13:56:51.083534 [0] MAX Duty = 5000%(X100), DQS PI = 54
2353 13:56:51.087025 [0] MIN Duty = 4907%(X100), DQS PI = 2
2354 13:56:51.087092 [0] AVG Duty = 4953%(X100)
2355 13:56:51.090009
2356 13:56:51.090074 ==DQM 1 ==
2357 13:56:51.093361 Final DQM duty delay cell = 0
2358 13:56:51.096877 [0] MAX Duty = 5156%(X100), DQS PI = 62
2359 13:56:51.100241 [0] MIN Duty = 4969%(X100), DQS PI = 10
2360 13:56:51.100316 [0] AVG Duty = 5062%(X100)
2361 13:56:51.103836
2362 13:56:51.103909 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2363 13:56:51.106796
2364 13:56:51.110267 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2365 13:56:51.113688 [DutyScan_Calibration_Flow] ====Done====
2366 13:56:51.113760
2367 13:56:51.116865 [DutyScan_Calibration_Flow] k_type=2
2368 13:56:51.132162
2369 13:56:51.132237 ==DQ 0 ==
2370 13:56:51.136020 Final DQ duty delay cell = -4
2371 13:56:51.139104 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2372 13:56:51.142916 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2373 13:56:51.145832 [-4] AVG Duty = 4969%(X100)
2374 13:56:51.145901
2375 13:56:51.145960 ==DQ 1 ==
2376 13:56:51.149050 Final DQ duty delay cell = 0
2377 13:56:51.152473 [0] MAX Duty = 5031%(X100), DQS PI = 18
2378 13:56:51.155768 [0] MIN Duty = 4907%(X100), DQS PI = 46
2379 13:56:51.155837 [0] AVG Duty = 4969%(X100)
2380 13:56:51.155895
2381 13:56:51.163004 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2382 13:56:51.163078
2383 13:56:51.165893 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2384 13:56:51.169530 [DutyScan_Calibration_Flow] ====Done====
2385 13:56:51.169600 ==
2386 13:56:51.172610 Dram Type= 6, Freq= 0, CH_1, rank 0
2387 13:56:51.175823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2388 13:56:51.175894 ==
2389 13:56:51.179183 [Duty_Offset_Calibration]
2390 13:56:51.179252 B0:1 B1:1 CA:2
2391 13:56:51.179323
2392 13:56:51.182713 [DutyScan_Calibration_Flow] k_type=0
2393 13:56:51.192615
2394 13:56:51.192691 ==CLK 0==
2395 13:56:51.195818 Final CLK duty delay cell = 0
2396 13:56:51.199788 [0] MAX Duty = 5156%(X100), DQS PI = 24
2397 13:56:51.202800 [0] MIN Duty = 4938%(X100), DQS PI = 40
2398 13:56:51.202870 [0] AVG Duty = 5047%(X100)
2399 13:56:51.206087
2400 13:56:51.209294 CH1 CLK Duty spec in!! Max-Min= 218%
2401 13:56:51.212976 [DutyScan_Calibration_Flow] ====Done====
2402 13:56:51.213054
2403 13:56:51.216035 [DutyScan_Calibration_Flow] k_type=1
2404 13:56:51.232044
2405 13:56:51.232130 ==DQS 0 ==
2406 13:56:51.235659 Final DQS duty delay cell = 0
2407 13:56:51.238893 [0] MAX Duty = 5031%(X100), DQS PI = 18
2408 13:56:51.242198 [0] MIN Duty = 4844%(X100), DQS PI = 50
2409 13:56:51.242318 [0] AVG Duty = 4937%(X100)
2410 13:56:51.245404
2411 13:56:51.245504 ==DQS 1 ==
2412 13:56:51.248815 Final DQS duty delay cell = 0
2413 13:56:51.252224 [0] MAX Duty = 5062%(X100), DQS PI = 36
2414 13:56:51.255693 [0] MIN Duty = 4907%(X100), DQS PI = 14
2415 13:56:51.255763 [0] AVG Duty = 4984%(X100)
2416 13:56:51.255822
2417 13:56:51.262032 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2418 13:56:51.262105
2419 13:56:51.265744 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2420 13:56:51.269021 [DutyScan_Calibration_Flow] ====Done====
2421 13:56:51.269099
2422 13:56:51.272396 [DutyScan_Calibration_Flow] k_type=3
2423 13:56:51.288619
2424 13:56:51.288709 ==DQM 0 ==
2425 13:56:51.292355 Final DQM duty delay cell = 0
2426 13:56:51.295220 [0] MAX Duty = 5093%(X100), DQS PI = 18
2427 13:56:51.298720 [0] MIN Duty = 4875%(X100), DQS PI = 50
2428 13:56:51.301999 [0] AVG Duty = 4984%(X100)
2429 13:56:51.302079
2430 13:56:51.302143 ==DQM 1 ==
2431 13:56:51.305350 Final DQM duty delay cell = 0
2432 13:56:51.309041 [0] MAX Duty = 5156%(X100), DQS PI = 62
2433 13:56:51.311882 [0] MIN Duty = 4938%(X100), DQS PI = 24
2434 13:56:51.315213 [0] AVG Duty = 5047%(X100)
2435 13:56:51.315293
2436 13:56:51.318588 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2437 13:56:51.318671
2438 13:56:51.321948 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2439 13:56:51.325340 [DutyScan_Calibration_Flow] ====Done====
2440 13:56:51.325420
2441 13:56:51.328826 [DutyScan_Calibration_Flow] k_type=2
2442 13:56:51.345216
2443 13:56:51.345297 ==DQ 0 ==
2444 13:56:51.348580 Final DQ duty delay cell = 0
2445 13:56:51.351825 [0] MAX Duty = 5124%(X100), DQS PI = 18
2446 13:56:51.355893 [0] MIN Duty = 4938%(X100), DQS PI = 50
2447 13:56:51.355974 [0] AVG Duty = 5031%(X100)
2448 13:56:51.356037
2449 13:56:51.358848 ==DQ 1 ==
2450 13:56:51.362713 Final DQ duty delay cell = 0
2451 13:56:51.365537 [0] MAX Duty = 5124%(X100), DQS PI = 58
2452 13:56:51.368783 [0] MIN Duty = 5000%(X100), DQS PI = 52
2453 13:56:51.368860 [0] AVG Duty = 5062%(X100)
2454 13:56:51.368926
2455 13:56:51.371903 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2456 13:56:51.371977
2457 13:56:51.375360 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2458 13:56:51.382156 [DutyScan_Calibration_Flow] ====Done====
2459 13:56:51.385519 nWR fixed to 30
2460 13:56:51.385589 [ModeRegInit_LP4] CH0 RK0
2461 13:56:51.388675 [ModeRegInit_LP4] CH0 RK1
2462 13:56:51.392046 [ModeRegInit_LP4] CH1 RK0
2463 13:56:51.392114 [ModeRegInit_LP4] CH1 RK1
2464 13:56:51.395546 match AC timing 7
2465 13:56:51.399313 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2466 13:56:51.402251 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2467 13:56:51.409306 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2468 13:56:51.412760 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2469 13:56:51.419364 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2470 13:56:51.419445 ==
2471 13:56:51.422600 Dram Type= 6, Freq= 0, CH_0, rank 0
2472 13:56:51.425920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2473 13:56:51.425993 ==
2474 13:56:51.429378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2475 13:56:51.435782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2476 13:56:51.445292 [CA 0] Center 40 (10~71) winsize 62
2477 13:56:51.448777 [CA 1] Center 39 (9~70) winsize 62
2478 13:56:51.452202 [CA 2] Center 36 (6~67) winsize 62
2479 13:56:51.455543 [CA 3] Center 36 (5~67) winsize 63
2480 13:56:51.458773 [CA 4] Center 35 (5~65) winsize 61
2481 13:56:51.461974 [CA 5] Center 34 (4~65) winsize 62
2482 13:56:51.462054
2483 13:56:51.465757 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2484 13:56:51.465837
2485 13:56:51.468895 [CATrainingPosCal] consider 1 rank data
2486 13:56:51.472274 u2DelayCellTimex100 = 270/100 ps
2487 13:56:51.475482 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2488 13:56:51.479230 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2489 13:56:51.485643 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2490 13:56:51.489058 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2491 13:56:51.492182 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2492 13:56:51.495793 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2493 13:56:51.495875
2494 13:56:51.498757 CA PerBit enable=1, Macro0, CA PI delay=34
2495 13:56:51.498838
2496 13:56:51.502039 [CBTSetCACLKResult] CA Dly = 34
2497 13:56:51.502119 CS Dly: 7 (0~38)
2498 13:56:51.502182 ==
2499 13:56:51.505619 Dram Type= 6, Freq= 0, CH_0, rank 1
2500 13:56:51.512688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 13:56:51.512770 ==
2502 13:56:51.515609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2503 13:56:51.522266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2504 13:56:51.531188 [CA 0] Center 39 (9~70) winsize 62
2505 13:56:51.534671 [CA 1] Center 40 (10~70) winsize 61
2506 13:56:51.538551 [CA 2] Center 36 (6~67) winsize 62
2507 13:56:51.541411 [CA 3] Center 36 (6~67) winsize 62
2508 13:56:51.544733 [CA 4] Center 34 (4~65) winsize 62
2509 13:56:51.548519 [CA 5] Center 34 (4~64) winsize 61
2510 13:56:51.548599
2511 13:56:51.551372 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2512 13:56:51.551453
2513 13:56:51.554713 [CATrainingPosCal] consider 2 rank data
2514 13:56:51.558634 u2DelayCellTimex100 = 270/100 ps
2515 13:56:51.561718 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2516 13:56:51.564687 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2517 13:56:51.571590 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2518 13:56:51.574826 CA3 delay=36 (6~67),Diff = 2 PI (9 cell)
2519 13:56:51.578335 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2520 13:56:51.581681 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2521 13:56:51.581787
2522 13:56:51.584791 CA PerBit enable=1, Macro0, CA PI delay=34
2523 13:56:51.584865
2524 13:56:51.588199 [CBTSetCACLKResult] CA Dly = 34
2525 13:56:51.588270 CS Dly: 8 (0~41)
2526 13:56:51.588330
2527 13:56:51.591545 ----->DramcWriteLeveling(PI) begin...
2528 13:56:51.594795 ==
2529 13:56:51.594863 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 13:56:51.601719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 13:56:51.601792 ==
2532 13:56:51.605021 Write leveling (Byte 0): 32 => 32
2533 13:56:51.608643 Write leveling (Byte 1): 29 => 29
2534 13:56:51.608716 DramcWriteLeveling(PI) end<-----
2535 13:56:51.608776
2536 13:56:51.611618 ==
2537 13:56:51.615289 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 13:56:51.618785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 13:56:51.618852 ==
2540 13:56:51.621837 [Gating] SW mode calibration
2541 13:56:51.628860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2542 13:56:51.631731 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2543 13:56:51.638662 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 13:56:51.641744 0 15 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2545 13:56:51.645264 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2546 13:56:51.652545 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 13:56:51.655550 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 13:56:51.658924 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2549 13:56:51.665561 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 13:56:51.669132 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 13:56:51.671948 1 0 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
2552 13:56:51.675213 1 0 4 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
2553 13:56:51.682583 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 13:56:51.685504 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 13:56:51.688892 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 13:56:51.696013 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 13:56:51.698815 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 13:56:51.702429 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 13:56:51.709517 1 1 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2560 13:56:51.712509 1 1 4 | B1->B0 | 3939 4444 | 1 0 | (0 0) (0 0)
2561 13:56:51.716205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 13:56:51.719006 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 13:56:51.726153 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 13:56:51.729502 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 13:56:51.732701 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 13:56:51.739208 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 13:56:51.742729 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2568 13:56:51.746275 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2569 13:56:51.752920 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:56:51.756432 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 13:56:51.759862 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 13:56:51.766569 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 13:56:51.769663 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 13:56:51.773236 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 13:56:51.776852 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 13:56:51.783170 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 13:56:51.786385 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 13:56:51.790026 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 13:56:51.796553 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 13:56:51.799749 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 13:56:51.803195 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 13:56:51.810608 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 13:56:51.813532 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2584 13:56:51.816739 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2585 13:56:51.820488 Total UI for P1: 0, mck2ui 16
2586 13:56:51.823498 best dqsien dly found for B0: ( 1, 4, 0)
2587 13:56:51.826610 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 13:56:51.829945 Total UI for P1: 0, mck2ui 16
2589 13:56:51.833496 best dqsien dly found for B1: ( 1, 4, 2)
2590 13:56:51.836590 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2591 13:56:51.839894 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2592 13:56:51.843904
2593 13:56:51.846717 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2594 13:56:51.850026 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2595 13:56:51.853447 [Gating] SW calibration Done
2596 13:56:51.853553 ==
2597 13:56:51.856847 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 13:56:51.860099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 13:56:51.860181 ==
2600 13:56:51.860244 RX Vref Scan: 0
2601 13:56:51.860304
2602 13:56:51.863562 RX Vref 0 -> 0, step: 1
2603 13:56:51.863642
2604 13:56:51.867163 RX Delay -40 -> 252, step: 8
2605 13:56:51.870700 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2606 13:56:51.873602 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2607 13:56:51.876983 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2608 13:56:51.883904 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2609 13:56:51.887136 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2610 13:56:51.890602 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2611 13:56:51.894000 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2612 13:56:51.897066 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2613 13:56:51.903687 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2614 13:56:51.907172 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2615 13:56:51.910725 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2616 13:56:51.913755 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2617 13:56:51.917220 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2618 13:56:51.920906 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2619 13:56:51.927234 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2620 13:56:51.930779 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2621 13:56:51.930864 ==
2622 13:56:51.934128 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 13:56:51.937360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 13:56:51.937440 ==
2625 13:56:51.940759 DQS Delay:
2626 13:56:51.940840 DQS0 = 0, DQS1 = 0
2627 13:56:51.940903 DQM Delay:
2628 13:56:51.944548 DQM0 = 116, DQM1 = 107
2629 13:56:51.944628 DQ Delay:
2630 13:56:51.947294 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2631 13:56:51.950857 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2632 13:56:51.954044 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2633 13:56:51.957566 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2634 13:56:51.961018
2635 13:56:51.961092
2636 13:56:51.961151 ==
2637 13:56:51.964396 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 13:56:51.967322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 13:56:51.967391 ==
2640 13:56:51.967453
2641 13:56:51.967509
2642 13:56:51.970647 TX Vref Scan disable
2643 13:56:51.970719 == TX Byte 0 ==
2644 13:56:51.977784 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2645 13:56:51.981302 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2646 13:56:51.981378 == TX Byte 1 ==
2647 13:56:51.987492 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2648 13:56:51.991057 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2649 13:56:51.991131 ==
2650 13:56:51.994503 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 13:56:51.997279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 13:56:51.997346 ==
2653 13:56:52.010055 TX Vref=22, minBit 1, minWin=24, winSum=416
2654 13:56:52.013432 TX Vref=24, minBit 0, minWin=25, winSum=421
2655 13:56:52.016639 TX Vref=26, minBit 0, minWin=26, winSum=427
2656 13:56:52.020274 TX Vref=28, minBit 0, minWin=26, winSum=426
2657 13:56:52.023289 TX Vref=30, minBit 0, minWin=26, winSum=434
2658 13:56:52.026821 TX Vref=32, minBit 0, minWin=26, winSum=432
2659 13:56:52.033216 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 30
2660 13:56:52.033318
2661 13:56:52.036552 Final TX Range 1 Vref 30
2662 13:56:52.036650
2663 13:56:52.036741 ==
2664 13:56:52.040357 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 13:56:52.043523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 13:56:52.043622 ==
2667 13:56:52.043711
2668 13:56:52.043800
2669 13:56:52.046909 TX Vref Scan disable
2670 13:56:52.050295 == TX Byte 0 ==
2671 13:56:52.053859 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2672 13:56:52.056696 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2673 13:56:52.060268 == TX Byte 1 ==
2674 13:56:52.063647 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2675 13:56:52.067061 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2676 13:56:52.067135
2677 13:56:52.070030 [DATLAT]
2678 13:56:52.070124 Freq=1200, CH0 RK0
2679 13:56:52.070211
2680 13:56:52.073593 DATLAT Default: 0xd
2681 13:56:52.073675 0, 0xFFFF, sum = 0
2682 13:56:52.077115 1, 0xFFFF, sum = 0
2683 13:56:52.077197 2, 0xFFFF, sum = 0
2684 13:56:52.080126 3, 0xFFFF, sum = 0
2685 13:56:52.080208 4, 0xFFFF, sum = 0
2686 13:56:52.083748 5, 0xFFFF, sum = 0
2687 13:56:52.083829 6, 0xFFFF, sum = 0
2688 13:56:52.086857 7, 0xFFFF, sum = 0
2689 13:56:52.086938 8, 0xFFFF, sum = 0
2690 13:56:52.090011 9, 0xFFFF, sum = 0
2691 13:56:52.090093 10, 0xFFFF, sum = 0
2692 13:56:52.093347 11, 0xFFFF, sum = 0
2693 13:56:52.096870 12, 0x0, sum = 1
2694 13:56:52.096951 13, 0x0, sum = 2
2695 13:56:52.097017 14, 0x0, sum = 3
2696 13:56:52.100161 15, 0x0, sum = 4
2697 13:56:52.100243 best_step = 13
2698 13:56:52.100307
2699 13:56:52.100365 ==
2700 13:56:52.103623 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 13:56:52.110138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 13:56:52.110219 ==
2703 13:56:52.110282 RX Vref Scan: 1
2704 13:56:52.110342
2705 13:56:52.113468 Set Vref Range= 32 -> 127
2706 13:56:52.113548
2707 13:56:52.116896 RX Vref 32 -> 127, step: 1
2708 13:56:52.117039
2709 13:56:52.120600 RX Delay -21 -> 252, step: 4
2710 13:56:52.120750
2711 13:56:52.124135 Set Vref, RX VrefLevel [Byte0]: 32
2712 13:56:52.124216 [Byte1]: 32
2713 13:56:52.128476
2714 13:56:52.128557 Set Vref, RX VrefLevel [Byte0]: 33
2715 13:56:52.131966 [Byte1]: 33
2716 13:56:52.136240
2717 13:56:52.136320 Set Vref, RX VrefLevel [Byte0]: 34
2718 13:56:52.139339 [Byte1]: 34
2719 13:56:52.144334
2720 13:56:52.144414 Set Vref, RX VrefLevel [Byte0]: 35
2721 13:56:52.147916 [Byte1]: 35
2722 13:56:52.152420
2723 13:56:52.152516 Set Vref, RX VrefLevel [Byte0]: 36
2724 13:56:52.155359 [Byte1]: 36
2725 13:56:52.160032
2726 13:56:52.160138 Set Vref, RX VrefLevel [Byte0]: 37
2727 13:56:52.163342 [Byte1]: 37
2728 13:56:52.168176
2729 13:56:52.168257 Set Vref, RX VrefLevel [Byte0]: 38
2730 13:56:52.171001 [Byte1]: 38
2731 13:56:52.175818
2732 13:56:52.175905 Set Vref, RX VrefLevel [Byte0]: 39
2733 13:56:52.179619 [Byte1]: 39
2734 13:56:52.184017
2735 13:56:52.184091 Set Vref, RX VrefLevel [Byte0]: 40
2736 13:56:52.187362 [Byte1]: 40
2737 13:56:52.191872
2738 13:56:52.191972 Set Vref, RX VrefLevel [Byte0]: 41
2739 13:56:52.195000 [Byte1]: 41
2740 13:56:52.199711
2741 13:56:52.199814 Set Vref, RX VrefLevel [Byte0]: 42
2742 13:56:52.203076 [Byte1]: 42
2743 13:56:52.207469
2744 13:56:52.207542 Set Vref, RX VrefLevel [Byte0]: 43
2745 13:56:52.210981 [Byte1]: 43
2746 13:56:52.215350
2747 13:56:52.215448 Set Vref, RX VrefLevel [Byte0]: 44
2748 13:56:52.218551 [Byte1]: 44
2749 13:56:52.223514
2750 13:56:52.223594 Set Vref, RX VrefLevel [Byte0]: 45
2751 13:56:52.226819 [Byte1]: 45
2752 13:56:52.231495
2753 13:56:52.231594 Set Vref, RX VrefLevel [Byte0]: 46
2754 13:56:52.234511 [Byte1]: 46
2755 13:56:52.239335
2756 13:56:52.239416 Set Vref, RX VrefLevel [Byte0]: 47
2757 13:56:52.242604 [Byte1]: 47
2758 13:56:52.247043
2759 13:56:52.247122 Set Vref, RX VrefLevel [Byte0]: 48
2760 13:56:52.250792 [Byte1]: 48
2761 13:56:52.255126
2762 13:56:52.255206 Set Vref, RX VrefLevel [Byte0]: 49
2763 13:56:52.258541 [Byte1]: 49
2764 13:56:52.263100
2765 13:56:52.263181 Set Vref, RX VrefLevel [Byte0]: 50
2766 13:56:52.266258 [Byte1]: 50
2767 13:56:52.271370
2768 13:56:52.271451 Set Vref, RX VrefLevel [Byte0]: 51
2769 13:56:52.274297 [Byte1]: 51
2770 13:56:52.278759
2771 13:56:52.278865 Set Vref, RX VrefLevel [Byte0]: 52
2772 13:56:52.282463 [Byte1]: 52
2773 13:56:52.286590
2774 13:56:52.286702 Set Vref, RX VrefLevel [Byte0]: 53
2775 13:56:52.290138 [Byte1]: 53
2776 13:56:52.294980
2777 13:56:52.298178 Set Vref, RX VrefLevel [Byte0]: 54
2778 13:56:52.298259 [Byte1]: 54
2779 13:56:52.302829
2780 13:56:52.302909 Set Vref, RX VrefLevel [Byte0]: 55
2781 13:56:52.306118 [Byte1]: 55
2782 13:56:52.310917
2783 13:56:52.310998 Set Vref, RX VrefLevel [Byte0]: 56
2784 13:56:52.314065 [Byte1]: 56
2785 13:56:52.318959
2786 13:56:52.319039 Set Vref, RX VrefLevel [Byte0]: 57
2787 13:56:52.321966 [Byte1]: 57
2788 13:56:52.326681
2789 13:56:52.326761 Set Vref, RX VrefLevel [Byte0]: 58
2790 13:56:52.329805 [Byte1]: 58
2791 13:56:52.334598
2792 13:56:52.334679 Set Vref, RX VrefLevel [Byte0]: 59
2793 13:56:52.337812 [Byte1]: 59
2794 13:56:52.342449
2795 13:56:52.342529 Set Vref, RX VrefLevel [Byte0]: 60
2796 13:56:52.346218 [Byte1]: 60
2797 13:56:52.350356
2798 13:56:52.350481 Set Vref, RX VrefLevel [Byte0]: 61
2799 13:56:52.353890 [Byte1]: 61
2800 13:56:52.358794
2801 13:56:52.358874 Set Vref, RX VrefLevel [Byte0]: 62
2802 13:56:52.361662 [Byte1]: 62
2803 13:56:52.365945
2804 13:56:52.366025 Set Vref, RX VrefLevel [Byte0]: 63
2805 13:56:52.369336 [Byte1]: 63
2806 13:56:52.374361
2807 13:56:52.374487 Set Vref, RX VrefLevel [Byte0]: 64
2808 13:56:52.377282 [Byte1]: 64
2809 13:56:52.382317
2810 13:56:52.382421 Set Vref, RX VrefLevel [Byte0]: 65
2811 13:56:52.385207 [Byte1]: 65
2812 13:56:52.389935
2813 13:56:52.390015 Set Vref, RX VrefLevel [Byte0]: 66
2814 13:56:52.393659 [Byte1]: 66
2815 13:56:52.397776
2816 13:56:52.397856 Set Vref, RX VrefLevel [Byte0]: 67
2817 13:56:52.400932 [Byte1]: 67
2818 13:56:52.406039
2819 13:56:52.406120 Set Vref, RX VrefLevel [Byte0]: 68
2820 13:56:52.408932 [Byte1]: 68
2821 13:56:52.413572
2822 13:56:52.413653 Set Vref, RX VrefLevel [Byte0]: 69
2823 13:56:52.416988 [Byte1]: 69
2824 13:56:52.421328
2825 13:56:52.421409 Final RX Vref Byte 0 = 56 to rank0
2826 13:56:52.425287 Final RX Vref Byte 1 = 52 to rank0
2827 13:56:52.428059 Final RX Vref Byte 0 = 56 to rank1
2828 13:56:52.431742 Final RX Vref Byte 1 = 52 to rank1==
2829 13:56:52.435289 Dram Type= 6, Freq= 0, CH_0, rank 0
2830 13:56:52.438441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 13:56:52.441824 ==
2832 13:56:52.441905 DQS Delay:
2833 13:56:52.441968 DQS0 = 0, DQS1 = 0
2834 13:56:52.444945 DQM Delay:
2835 13:56:52.445042 DQM0 = 115, DQM1 = 105
2836 13:56:52.448251 DQ Delay:
2837 13:56:52.451630 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2838 13:56:52.455115 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2839 13:56:52.458365 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2840 13:56:52.461650 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2841 13:56:52.461730
2842 13:56:52.461794
2843 13:56:52.468766 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2844 13:56:52.472146 CH0 RK0: MR19=303, MR18=FEEE
2845 13:56:52.478671 CH0_RK0: MR19=0x303, MR18=0xFEEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2846 13:56:52.478752
2847 13:56:52.482099 ----->DramcWriteLeveling(PI) begin...
2848 13:56:52.482181 ==
2849 13:56:52.485609 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 13:56:52.488744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 13:56:52.488826 ==
2852 13:56:52.491895 Write leveling (Byte 0): 32 => 32
2853 13:56:52.495489 Write leveling (Byte 1): 29 => 29
2854 13:56:52.498965 DramcWriteLeveling(PI) end<-----
2855 13:56:52.499046
2856 13:56:52.499110 ==
2857 13:56:52.502297 Dram Type= 6, Freq= 0, CH_0, rank 1
2858 13:56:52.505505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 13:56:52.505587 ==
2860 13:56:52.509269 [Gating] SW mode calibration
2861 13:56:52.515784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2862 13:56:52.522049 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2863 13:56:52.525509 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2864 13:56:52.532429 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2865 13:56:52.535708 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 13:56:52.539433 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 13:56:52.542581 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 13:56:52.549180 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 13:56:52.552373 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 13:56:52.556017 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
2871 13:56:52.562214 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2872 13:56:52.565855 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 13:56:52.569063 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 13:56:52.575743 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 13:56:52.579360 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 13:56:52.582589 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 13:56:52.589397 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2878 13:56:52.592381 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2879 13:56:52.596091 1 1 0 | B1->B0 | 3939 4343 | 0 0 | (1 1) (0 0)
2880 13:56:52.602616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 13:56:52.605756 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 13:56:52.609190 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 13:56:52.612904 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 13:56:52.619665 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 13:56:52.622883 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2886 13:56:52.626270 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2887 13:56:52.632970 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2888 13:56:52.636098 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:56:52.639566 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 13:56:52.646217 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 13:56:52.649476 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 13:56:52.653083 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 13:56:52.660385 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 13:56:52.663155 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 13:56:52.666554 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 13:56:52.669894 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 13:56:52.676546 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 13:56:52.680754 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 13:56:52.684034 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 13:56:52.689665 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 13:56:52.693771 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 13:56:52.696650 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2903 13:56:52.703211 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2904 13:56:52.703292 Total UI for P1: 0, mck2ui 16
2905 13:56:52.710720 best dqsien dly found for B0: ( 1, 3, 28)
2906 13:56:52.713537 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2907 13:56:52.717081 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 13:56:52.720097 Total UI for P1: 0, mck2ui 16
2909 13:56:52.723454 best dqsien dly found for B1: ( 1, 4, 2)
2910 13:56:52.726919 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2911 13:56:52.730266 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2912 13:56:52.730347
2913 13:56:52.733804 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2914 13:56:52.737028 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2915 13:56:52.740169 [Gating] SW calibration Done
2916 13:56:52.740250 ==
2917 13:56:52.743510 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 13:56:52.747005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 13:56:52.750514 ==
2920 13:56:52.750595 RX Vref Scan: 0
2921 13:56:52.750660
2922 13:56:52.753996 RX Vref 0 -> 0, step: 1
2923 13:56:52.754100
2924 13:56:52.757100 RX Delay -40 -> 252, step: 8
2925 13:56:52.760412 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2926 13:56:52.764093 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2927 13:56:52.766965 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2928 13:56:52.770868 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2929 13:56:52.777160 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2930 13:56:52.781011 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2931 13:56:52.783738 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2932 13:56:52.787398 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2933 13:56:52.790857 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2934 13:56:52.793751 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2935 13:56:52.800914 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2936 13:56:52.803845 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2937 13:56:52.807271 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2938 13:56:52.810498 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2939 13:56:52.813829 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2940 13:56:52.820734 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2941 13:56:52.820841 ==
2942 13:56:52.824261 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 13:56:52.827842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 13:56:52.827923 ==
2945 13:56:52.827988 DQS Delay:
2946 13:56:52.830545 DQS0 = 0, DQS1 = 0
2947 13:56:52.830626 DQM Delay:
2948 13:56:52.834251 DQM0 = 116, DQM1 = 106
2949 13:56:52.834349 DQ Delay:
2950 13:56:52.837546 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2951 13:56:52.840680 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2952 13:56:52.844344 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2953 13:56:52.847806 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2954 13:56:52.847887
2955 13:56:52.847950
2956 13:56:52.848009 ==
2957 13:56:52.851082 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 13:56:52.858350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 13:56:52.858471 ==
2960 13:56:52.858536
2961 13:56:52.858612
2962 13:56:52.858685 TX Vref Scan disable
2963 13:56:52.861042 == TX Byte 0 ==
2964 13:56:52.864706 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2965 13:56:52.867760 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2966 13:56:52.871431 == TX Byte 1 ==
2967 13:56:52.874963 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2968 13:56:52.877817 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2969 13:56:52.881373 ==
2970 13:56:52.884639 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 13:56:52.888244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 13:56:52.888326 ==
2973 13:56:52.899281 TX Vref=22, minBit 0, minWin=25, winSum=425
2974 13:56:52.902987 TX Vref=24, minBit 5, minWin=25, winSum=431
2975 13:56:52.906013 TX Vref=26, minBit 2, minWin=26, winSum=436
2976 13:56:52.909429 TX Vref=28, minBit 12, minWin=26, winSum=434
2977 13:56:52.913235 TX Vref=30, minBit 12, minWin=26, winSum=435
2978 13:56:52.915996 TX Vref=32, minBit 4, minWin=26, winSum=434
2979 13:56:52.923941 [TxChooseVref] Worse bit 2, Min win 26, Win sum 436, Final Vref 26
2980 13:56:52.924023
2981 13:56:52.926747 Final TX Range 1 Vref 26
2982 13:56:52.926828
2983 13:56:52.926892 ==
2984 13:56:52.929411 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 13:56:52.932608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 13:56:52.932689 ==
2987 13:56:52.932753
2988 13:56:52.932829
2989 13:56:52.936037 TX Vref Scan disable
2990 13:56:52.939224 == TX Byte 0 ==
2991 13:56:52.942882 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2992 13:56:52.946203 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2993 13:56:52.949721 == TX Byte 1 ==
2994 13:56:52.953189 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2995 13:56:52.956709 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2996 13:56:52.956790
2997 13:56:52.959585 [DATLAT]
2998 13:56:52.959665 Freq=1200, CH0 RK1
2999 13:56:52.959728
3000 13:56:52.963287 DATLAT Default: 0xd
3001 13:56:52.963367 0, 0xFFFF, sum = 0
3002 13:56:52.966295 1, 0xFFFF, sum = 0
3003 13:56:52.966377 2, 0xFFFF, sum = 0
3004 13:56:52.970221 3, 0xFFFF, sum = 0
3005 13:56:52.970302 4, 0xFFFF, sum = 0
3006 13:56:52.972993 5, 0xFFFF, sum = 0
3007 13:56:52.973106 6, 0xFFFF, sum = 0
3008 13:56:52.976581 7, 0xFFFF, sum = 0
3009 13:56:52.976663 8, 0xFFFF, sum = 0
3010 13:56:52.979990 9, 0xFFFF, sum = 0
3011 13:56:52.980071 10, 0xFFFF, sum = 0
3012 13:56:52.983589 11, 0xFFFF, sum = 0
3013 13:56:52.983670 12, 0x0, sum = 1
3014 13:56:52.986635 13, 0x0, sum = 2
3015 13:56:52.986717 14, 0x0, sum = 3
3016 13:56:52.989733 15, 0x0, sum = 4
3017 13:56:52.989815 best_step = 13
3018 13:56:52.989878
3019 13:56:52.989937 ==
3020 13:56:52.993388 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 13:56:53.000551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 13:56:53.000660 ==
3023 13:56:53.000756 RX Vref Scan: 0
3024 13:56:53.000825
3025 13:56:53.003467 RX Vref 0 -> 0, step: 1
3026 13:56:53.003581
3027 13:56:53.006800 RX Delay -21 -> 252, step: 4
3028 13:56:53.010113 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3029 13:56:53.013302 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3030 13:56:53.016675 iDelay=195, Bit 2, Center 112 (39 ~ 186) 148
3031 13:56:53.023351 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3032 13:56:53.026787 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3033 13:56:53.030016 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3034 13:56:53.033415 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3035 13:56:53.036903 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3036 13:56:53.043839 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3037 13:56:53.046698 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3038 13:56:53.050012 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3039 13:56:53.053400 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3040 13:56:53.057014 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3041 13:56:53.060075 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3042 13:56:53.067207 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3043 13:56:53.070321 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3044 13:56:53.070419 ==
3045 13:56:53.074036 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 13:56:53.077644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 13:56:53.077726 ==
3048 13:56:53.080405 DQS Delay:
3049 13:56:53.080485 DQS0 = 0, DQS1 = 0
3050 13:56:53.080549 DQM Delay:
3051 13:56:53.083900 DQM0 = 114, DQM1 = 104
3052 13:56:53.083981 DQ Delay:
3053 13:56:53.087110 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
3054 13:56:53.090240 DQ4 =112, DQ5 =106, DQ6 =120, DQ7 =122
3055 13:56:53.094128 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3056 13:56:53.100270 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3057 13:56:53.100365
3058 13:56:53.100429
3059 13:56:53.107184 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3060 13:56:53.110742 CH0 RK1: MR19=403, MR18=2F3
3061 13:56:53.117564 CH0_RK1: MR19=0x403, MR18=0x2F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3062 13:56:53.117695 [RxdqsGatingPostProcess] freq 1200
3063 13:56:53.124614 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3064 13:56:53.127463 best DQS0 dly(2T, 0.5T) = (0, 12)
3065 13:56:53.131097 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 13:56:53.134721 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3067 13:56:53.137889 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 13:56:53.141168 best DQS0 dly(2T, 0.5T) = (0, 11)
3069 13:56:53.144423 best DQS1 dly(2T, 0.5T) = (0, 12)
3070 13:56:53.147496 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3071 13:56:53.150964 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3072 13:56:53.151045 Pre-setting of DQS Precalculation
3073 13:56:53.158046 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3074 13:56:53.158127 ==
3075 13:56:53.161350 Dram Type= 6, Freq= 0, CH_1, rank 0
3076 13:56:53.164412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 13:56:53.164493 ==
3078 13:56:53.171575 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 13:56:53.178153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3080 13:56:53.185015 [CA 0] Center 38 (9~68) winsize 60
3081 13:56:53.188264 [CA 1] Center 38 (8~68) winsize 61
3082 13:56:53.191777 [CA 2] Center 35 (5~65) winsize 61
3083 13:56:53.194666 [CA 3] Center 34 (3~65) winsize 63
3084 13:56:53.198538 [CA 4] Center 34 (4~65) winsize 62
3085 13:56:53.201532 [CA 5] Center 34 (4~64) winsize 61
3086 13:56:53.201612
3087 13:56:53.204937 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3088 13:56:53.205018
3089 13:56:53.208720 [CATrainingPosCal] consider 1 rank data
3090 13:56:53.212195 u2DelayCellTimex100 = 270/100 ps
3091 13:56:53.215274 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3092 13:56:53.218292 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3093 13:56:53.221754 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3094 13:56:53.228259 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
3095 13:56:53.232240 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3096 13:56:53.235386 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3097 13:56:53.235466
3098 13:56:53.238710 CA PerBit enable=1, Macro0, CA PI delay=34
3099 13:56:53.238789
3100 13:56:53.241882 [CBTSetCACLKResult] CA Dly = 34
3101 13:56:53.241991 CS Dly: 6 (0~37)
3102 13:56:53.242056 ==
3103 13:56:53.245306 Dram Type= 6, Freq= 0, CH_1, rank 1
3104 13:56:53.252173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 13:56:53.252253 ==
3106 13:56:53.254986 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 13:56:53.261928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3108 13:56:53.270371 [CA 0] Center 38 (8~68) winsize 61
3109 13:56:53.273947 [CA 1] Center 38 (9~68) winsize 60
3110 13:56:53.277156 [CA 2] Center 34 (4~65) winsize 62
3111 13:56:53.280855 [CA 3] Center 34 (4~65) winsize 62
3112 13:56:53.283733 [CA 4] Center 34 (4~65) winsize 62
3113 13:56:53.287190 [CA 5] Center 33 (3~63) winsize 61
3114 13:56:53.287271
3115 13:56:53.290618 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3116 13:56:53.290699
3117 13:56:53.294017 [CATrainingPosCal] consider 2 rank data
3118 13:56:53.297701 u2DelayCellTimex100 = 270/100 ps
3119 13:56:53.300501 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3120 13:56:53.303953 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3121 13:56:53.307234 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3122 13:56:53.314544 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3123 13:56:53.317844 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3124 13:56:53.320803 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3125 13:56:53.320883
3126 13:56:53.323903 CA PerBit enable=1, Macro0, CA PI delay=33
3127 13:56:53.323983
3128 13:56:53.327382 [CBTSetCACLKResult] CA Dly = 33
3129 13:56:53.327462 CS Dly: 8 (0~41)
3130 13:56:53.327557
3131 13:56:53.331255 ----->DramcWriteLeveling(PI) begin...
3132 13:56:53.331336 ==
3133 13:56:53.334101 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 13:56:53.340851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 13:56:53.340932 ==
3136 13:56:53.344463 Write leveling (Byte 0): 27 => 27
3137 13:56:53.344547 Write leveling (Byte 1): 29 => 29
3138 13:56:53.348113 DramcWriteLeveling(PI) end<-----
3139 13:56:53.348193
3140 13:56:53.351082 ==
3141 13:56:53.351162 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 13:56:53.357399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 13:56:53.357479 ==
3144 13:56:53.361127 [Gating] SW mode calibration
3145 13:56:53.367747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3146 13:56:53.370856 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3147 13:56:53.377506 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3148 13:56:53.380833 0 15 4 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
3149 13:56:53.384503 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 13:56:53.391182 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3151 13:56:53.394987 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 13:56:53.397887 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3153 13:56:53.401707 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 13:56:53.407883 0 15 28 | B1->B0 | 3333 3333 | 1 1 | (0 0) (1 0)
3155 13:56:53.411050 1 0 0 | B1->B0 | 2525 2d2d | 0 0 | (0 1) (0 1)
3156 13:56:53.414677 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 13:56:53.421187 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3158 13:56:53.424574 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 13:56:53.428165 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 13:56:53.434418 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 13:56:53.437910 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 13:56:53.441371 1 0 28 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
3163 13:56:53.447963 1 1 0 | B1->B0 | 4545 3838 | 0 0 | (0 0) (0 0)
3164 13:56:53.451742 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 13:56:53.455217 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 13:56:53.458538 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 13:56:53.465034 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 13:56:53.468572 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 13:56:53.471912 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 13:56:53.478192 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3171 13:56:53.481756 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3172 13:56:53.484998 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 13:56:53.491795 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 13:56:53.495032 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 13:56:53.498791 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 13:56:53.504913 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 13:56:53.508286 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 13:56:53.511630 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 13:56:53.518960 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 13:56:53.522256 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 13:56:53.525239 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 13:56:53.528628 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 13:56:53.535112 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 13:56:53.538491 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 13:56:53.541629 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 13:56:53.548695 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3187 13:56:53.552366 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3188 13:56:53.555474 Total UI for P1: 0, mck2ui 16
3189 13:56:53.558915 best dqsien dly found for B1: ( 1, 3, 30)
3190 13:56:53.562060 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 13:56:53.565613 Total UI for P1: 0, mck2ui 16
3192 13:56:53.568903 best dqsien dly found for B0: ( 1, 3, 30)
3193 13:56:53.572437 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3194 13:56:53.575383 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3195 13:56:53.575463
3196 13:56:53.579025 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3197 13:56:53.585515 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3198 13:56:53.585590 [Gating] SW calibration Done
3199 13:56:53.588929 ==
3200 13:56:53.589002 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 13:56:53.595654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 13:56:53.595731 ==
3203 13:56:53.595793 RX Vref Scan: 0
3204 13:56:53.595852
3205 13:56:53.599170 RX Vref 0 -> 0, step: 1
3206 13:56:53.599241
3207 13:56:53.602732 RX Delay -40 -> 252, step: 8
3208 13:56:53.606359 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3209 13:56:53.609098 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3210 13:56:53.612358 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3211 13:56:53.618993 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3212 13:56:53.622325 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3213 13:56:53.625886 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3214 13:56:53.629337 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3215 13:56:53.632409 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3216 13:56:53.635717 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3217 13:56:53.642564 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3218 13:56:53.646074 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3219 13:56:53.649376 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3220 13:56:53.652883 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3221 13:56:53.656208 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3222 13:56:53.662851 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3223 13:56:53.666139 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3224 13:56:53.666219 ==
3225 13:56:53.669186 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 13:56:53.672993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 13:56:53.673075 ==
3228 13:56:53.673139 DQS Delay:
3229 13:56:53.676140 DQS0 = 0, DQS1 = 0
3230 13:56:53.676221 DQM Delay:
3231 13:56:53.679642 DQM0 = 116, DQM1 = 110
3232 13:56:53.679723 DQ Delay:
3233 13:56:53.682881 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3234 13:56:53.686113 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3235 13:56:53.689651 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3236 13:56:53.692981 DQ12 =123, DQ13 =115, DQ14 =115, DQ15 =115
3237 13:56:53.693061
3238 13:56:53.696592
3239 13:56:53.696672 ==
3240 13:56:53.699639 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 13:56:53.703165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 13:56:53.703263 ==
3243 13:56:53.703327
3244 13:56:53.703385
3245 13:56:53.706326 TX Vref Scan disable
3246 13:56:53.706417 == TX Byte 0 ==
3247 13:56:53.709689 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3248 13:56:53.716627 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3249 13:56:53.716708 == TX Byte 1 ==
3250 13:56:53.720001 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3251 13:56:53.726146 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3252 13:56:53.726227 ==
3253 13:56:53.730053 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 13:56:53.733330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 13:56:53.733426 ==
3256 13:56:53.744868 TX Vref=22, minBit 0, minWin=25, winSum=411
3257 13:56:53.748311 TX Vref=24, minBit 0, minWin=25, winSum=415
3258 13:56:53.751512 TX Vref=26, minBit 1, minWin=25, winSum=424
3259 13:56:53.755064 TX Vref=28, minBit 3, minWin=26, winSum=428
3260 13:56:53.758048 TX Vref=30, minBit 3, minWin=25, winSum=428
3261 13:56:53.761712 TX Vref=32, minBit 1, minWin=26, winSum=433
3262 13:56:53.768281 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 32
3263 13:56:53.768363
3264 13:56:53.771842 Final TX Range 1 Vref 32
3265 13:56:53.771924
3266 13:56:53.771987 ==
3267 13:56:53.775300 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 13:56:53.778960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 13:56:53.779042 ==
3270 13:56:53.779107
3271 13:56:53.779166
3272 13:56:53.781692 TX Vref Scan disable
3273 13:56:53.785247 == TX Byte 0 ==
3274 13:56:53.788660 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3275 13:56:53.791776 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3276 13:56:53.795317 == TX Byte 1 ==
3277 13:56:53.798592 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3278 13:56:53.802080 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3279 13:56:53.802161
3280 13:56:53.804929 [DATLAT]
3281 13:56:53.805014 Freq=1200, CH1 RK0
3282 13:56:53.805114
3283 13:56:53.808588 DATLAT Default: 0xd
3284 13:56:53.808669 0, 0xFFFF, sum = 0
3285 13:56:53.811916 1, 0xFFFF, sum = 0
3286 13:56:53.811998 2, 0xFFFF, sum = 0
3287 13:56:53.815696 3, 0xFFFF, sum = 0
3288 13:56:53.815778 4, 0xFFFF, sum = 0
3289 13:56:53.818911 5, 0xFFFF, sum = 0
3290 13:56:53.818993 6, 0xFFFF, sum = 0
3291 13:56:53.822529 7, 0xFFFF, sum = 0
3292 13:56:53.822611 8, 0xFFFF, sum = 0
3293 13:56:53.825451 9, 0xFFFF, sum = 0
3294 13:56:53.825562 10, 0xFFFF, sum = 0
3295 13:56:53.829095 11, 0xFFFF, sum = 0
3296 13:56:53.829175 12, 0x0, sum = 1
3297 13:56:53.831855 13, 0x0, sum = 2
3298 13:56:53.831937 14, 0x0, sum = 3
3299 13:56:53.835782 15, 0x0, sum = 4
3300 13:56:53.835863 best_step = 13
3301 13:56:53.835927
3302 13:56:53.835985 ==
3303 13:56:53.838651 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 13:56:53.845590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 13:56:53.845671 ==
3306 13:56:53.845735 RX Vref Scan: 1
3307 13:56:53.845793
3308 13:56:53.848882 Set Vref Range= 32 -> 127
3309 13:56:53.848962
3310 13:56:53.852459 RX Vref 32 -> 127, step: 1
3311 13:56:53.852539
3312 13:56:53.852602 RX Delay -21 -> 252, step: 4
3313 13:56:53.852661
3314 13:56:53.855478 Set Vref, RX VrefLevel [Byte0]: 32
3315 13:56:53.858731 [Byte1]: 32
3316 13:56:53.862921
3317 13:56:53.863005 Set Vref, RX VrefLevel [Byte0]: 33
3318 13:56:53.866666 [Byte1]: 33
3319 13:56:53.871026
3320 13:56:53.871105 Set Vref, RX VrefLevel [Byte0]: 34
3321 13:56:53.874357 [Byte1]: 34
3322 13:56:53.879247
3323 13:56:53.879326 Set Vref, RX VrefLevel [Byte0]: 35
3324 13:56:53.882241 [Byte1]: 35
3325 13:56:53.887056
3326 13:56:53.887134 Set Vref, RX VrefLevel [Byte0]: 36
3327 13:56:53.890379 [Byte1]: 36
3328 13:56:53.895086
3329 13:56:53.895165 Set Vref, RX VrefLevel [Byte0]: 37
3330 13:56:53.898551 [Byte1]: 37
3331 13:56:53.903197
3332 13:56:53.903277 Set Vref, RX VrefLevel [Byte0]: 38
3333 13:56:53.906049 [Byte1]: 38
3334 13:56:53.910680
3335 13:56:53.910759 Set Vref, RX VrefLevel [Byte0]: 39
3336 13:56:53.913841 [Byte1]: 39
3337 13:56:53.918890
3338 13:56:53.918969 Set Vref, RX VrefLevel [Byte0]: 40
3339 13:56:53.922920 [Byte1]: 40
3340 13:56:53.926521
3341 13:56:53.926600 Set Vref, RX VrefLevel [Byte0]: 41
3342 13:56:53.929926 [Byte1]: 41
3343 13:56:53.934181
3344 13:56:53.934260 Set Vref, RX VrefLevel [Byte0]: 42
3345 13:56:53.937784 [Byte1]: 42
3346 13:56:53.942902
3347 13:56:53.942981 Set Vref, RX VrefLevel [Byte0]: 43
3348 13:56:53.945685 [Byte1]: 43
3349 13:56:53.950335
3350 13:56:53.950452 Set Vref, RX VrefLevel [Byte0]: 44
3351 13:56:53.953879 [Byte1]: 44
3352 13:56:53.958595
3353 13:56:53.958674 Set Vref, RX VrefLevel [Byte0]: 45
3354 13:56:53.961481 [Byte1]: 45
3355 13:56:53.966105
3356 13:56:53.966185 Set Vref, RX VrefLevel [Byte0]: 46
3357 13:56:53.969225 [Byte1]: 46
3358 13:56:53.974092
3359 13:56:53.974171 Set Vref, RX VrefLevel [Byte0]: 47
3360 13:56:53.977683 [Byte1]: 47
3361 13:56:53.982110
3362 13:56:53.982190 Set Vref, RX VrefLevel [Byte0]: 48
3363 13:56:53.985287 [Byte1]: 48
3364 13:56:53.989851
3365 13:56:53.989930 Set Vref, RX VrefLevel [Byte0]: 49
3366 13:56:53.993238 [Byte1]: 49
3367 13:56:53.997998
3368 13:56:53.998078 Set Vref, RX VrefLevel [Byte0]: 50
3369 13:56:54.001988 [Byte1]: 50
3370 13:56:54.005659
3371 13:56:54.005740 Set Vref, RX VrefLevel [Byte0]: 51
3372 13:56:54.009103 [Byte1]: 51
3373 13:56:54.014077
3374 13:56:54.014157 Set Vref, RX VrefLevel [Byte0]: 52
3375 13:56:54.017082 [Byte1]: 52
3376 13:56:54.021977
3377 13:56:54.022058 Set Vref, RX VrefLevel [Byte0]: 53
3378 13:56:54.025065 [Byte1]: 53
3379 13:56:54.029477
3380 13:56:54.029560 Set Vref, RX VrefLevel [Byte0]: 54
3381 13:56:54.032733 [Byte1]: 54
3382 13:56:54.038013
3383 13:56:54.038093 Set Vref, RX VrefLevel [Byte0]: 55
3384 13:56:54.040711 [Byte1]: 55
3385 13:56:54.045486
3386 13:56:54.045566 Set Vref, RX VrefLevel [Byte0]: 56
3387 13:56:54.048872 [Byte1]: 56
3388 13:56:54.053067
3389 13:56:54.053147 Set Vref, RX VrefLevel [Byte0]: 57
3390 13:56:54.056447 [Byte1]: 57
3391 13:56:54.061028
3392 13:56:54.061109 Set Vref, RX VrefLevel [Byte0]: 58
3393 13:56:54.064767 [Byte1]: 58
3394 13:56:54.069115
3395 13:56:54.069225 Set Vref, RX VrefLevel [Byte0]: 59
3396 13:56:54.072171 [Byte1]: 59
3397 13:56:54.077106
3398 13:56:54.077187 Set Vref, RX VrefLevel [Byte0]: 60
3399 13:56:54.080363 [Byte1]: 60
3400 13:56:54.085132
3401 13:56:54.085213 Set Vref, RX VrefLevel [Byte0]: 61
3402 13:56:54.088180 [Byte1]: 61
3403 13:56:54.092689
3404 13:56:54.092769 Set Vref, RX VrefLevel [Byte0]: 62
3405 13:56:54.096082 [Byte1]: 62
3406 13:56:54.101068
3407 13:56:54.101149 Set Vref, RX VrefLevel [Byte0]: 63
3408 13:56:54.103827 [Byte1]: 63
3409 13:56:54.109170
3410 13:56:54.109251 Set Vref, RX VrefLevel [Byte0]: 64
3411 13:56:54.112555 [Byte1]: 64
3412 13:56:54.116508
3413 13:56:54.116589 Set Vref, RX VrefLevel [Byte0]: 65
3414 13:56:54.119766 [Byte1]: 65
3415 13:56:54.124834
3416 13:56:54.124915 Set Vref, RX VrefLevel [Byte0]: 66
3417 13:56:54.127700 [Byte1]: 66
3418 13:56:54.132234
3419 13:56:54.132315 Set Vref, RX VrefLevel [Byte0]: 67
3420 13:56:54.135617 [Byte1]: 67
3421 13:56:54.140728
3422 13:56:54.140845 Set Vref, RX VrefLevel [Byte0]: 68
3423 13:56:54.144396 [Byte1]: 68
3424 13:56:54.148747
3425 13:56:54.148827 Set Vref, RX VrefLevel [Byte0]: 69
3426 13:56:54.151747 [Byte1]: 69
3427 13:56:54.156332
3428 13:56:54.156412 Set Vref, RX VrefLevel [Byte0]: 70
3429 13:56:54.159944 [Byte1]: 70
3430 13:56:54.164381
3431 13:56:54.164462 Set Vref, RX VrefLevel [Byte0]: 71
3432 13:56:54.167938 [Byte1]: 71
3433 13:56:54.172155
3434 13:56:54.172236 Final RX Vref Byte 0 = 60 to rank0
3435 13:56:54.179141 Final RX Vref Byte 1 = 51 to rank0
3436 13:56:54.179238 Final RX Vref Byte 0 = 60 to rank1
3437 13:56:54.182258 Final RX Vref Byte 1 = 51 to rank1==
3438 13:56:54.185224 Dram Type= 6, Freq= 0, CH_1, rank 0
3439 13:56:54.192387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 13:56:54.192468 ==
3441 13:56:54.192532 DQS Delay:
3442 13:56:54.192592 DQS0 = 0, DQS1 = 0
3443 13:56:54.195787 DQM Delay:
3444 13:56:54.195870 DQM0 = 116, DQM1 = 109
3445 13:56:54.198659 DQ Delay:
3446 13:56:54.202333 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =116
3447 13:56:54.205571 DQ4 =116, DQ5 =122, DQ6 =126, DQ7 =114
3448 13:56:54.209091 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3449 13:56:54.212283 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3450 13:56:54.212365
3451 13:56:54.212443
3452 13:56:54.219182 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbe0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
3453 13:56:54.222279 CH1 RK0: MR19=303, MR18=FBE0
3454 13:56:54.228948 CH1_RK0: MR19=0x303, MR18=0xFBE0, DQSOSC=412, MR23=63, INC=38, DEC=25
3455 13:56:54.229050
3456 13:56:54.232173 ----->DramcWriteLeveling(PI) begin...
3457 13:56:54.232255 ==
3458 13:56:54.235856 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 13:56:54.239300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 13:56:54.239381 ==
3461 13:56:54.242644 Write leveling (Byte 0): 26 => 26
3462 13:56:54.245744 Write leveling (Byte 1): 28 => 28
3463 13:56:54.249349 DramcWriteLeveling(PI) end<-----
3464 13:56:54.249430
3465 13:56:54.249494 ==
3466 13:56:54.252752 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 13:56:54.255979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 13:56:54.256093 ==
3469 13:56:54.259403 [Gating] SW mode calibration
3470 13:56:54.265836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3471 13:56:54.272564 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3472 13:56:54.276098 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3473 13:56:54.282542 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 13:56:54.285894 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 13:56:54.289624 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3476 13:56:54.296113 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3477 13:56:54.299632 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3478 13:56:54.302925 0 15 24 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 1)
3479 13:56:54.309194 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
3480 13:56:54.312914 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 13:56:54.315979 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 13:56:54.319137 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 13:56:54.326280 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 13:56:54.329265 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 13:56:54.332704 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 13:56:54.339404 1 0 24 | B1->B0 | 2727 4343 | 0 0 | (0 0) (0 0)
3487 13:56:54.342367 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3488 13:56:54.346107 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 13:56:54.352647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 13:56:54.355689 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 13:56:54.359717 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 13:56:54.366326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 13:56:54.369228 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3494 13:56:54.372657 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3495 13:56:54.379413 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3496 13:56:54.382745 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 13:56:54.386294 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 13:56:54.392909 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 13:56:54.395815 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 13:56:54.399248 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 13:56:54.402729 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 13:56:54.409160 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 13:56:54.412972 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 13:56:54.416122 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 13:56:54.422746 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 13:56:54.426174 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 13:56:54.429632 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 13:56:54.436392 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 13:56:54.439697 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3510 13:56:54.443084 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3511 13:56:54.449726 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3512 13:56:54.449807 Total UI for P1: 0, mck2ui 16
3513 13:56:54.456310 best dqsien dly found for B0: ( 1, 3, 22)
3514 13:56:54.459440 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 13:56:54.463183 Total UI for P1: 0, mck2ui 16
3516 13:56:54.466388 best dqsien dly found for B1: ( 1, 3, 28)
3517 13:56:54.470077 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3518 13:56:54.472898 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3519 13:56:54.472979
3520 13:56:54.476022 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3521 13:56:54.479698 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3522 13:56:54.482807 [Gating] SW calibration Done
3523 13:56:54.482899 ==
3524 13:56:54.486372 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 13:56:54.489335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 13:56:54.489423 ==
3527 13:56:54.492753 RX Vref Scan: 0
3528 13:56:54.492835
3529 13:56:54.496459 RX Vref 0 -> 0, step: 1
3530 13:56:54.496545
3531 13:56:54.496610 RX Delay -40 -> 252, step: 8
3532 13:56:54.502797 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3533 13:56:54.505879 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3534 13:56:54.509451 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3535 13:56:54.512596 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3536 13:56:54.516778 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3537 13:56:54.522733 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3538 13:56:54.525818 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3539 13:56:54.530169 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3540 13:56:54.532851 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3541 13:56:54.536496 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3542 13:56:54.542843 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3543 13:56:54.546043 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3544 13:56:54.549212 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3545 13:56:54.552950 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3546 13:56:54.556023 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3547 13:56:54.562797 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3548 13:56:54.562925 ==
3549 13:56:54.566417 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 13:56:54.569186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 13:56:54.569333 ==
3552 13:56:54.569418 DQS Delay:
3553 13:56:54.572567 DQS0 = 0, DQS1 = 0
3554 13:56:54.572656 DQM Delay:
3555 13:56:54.576012 DQM0 = 112, DQM1 = 110
3556 13:56:54.576107 DQ Delay:
3557 13:56:54.579450 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3558 13:56:54.582608 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3559 13:56:54.585897 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3560 13:56:54.589394 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3561 13:56:54.589514
3562 13:56:54.589632
3563 13:56:54.592777 ==
3564 13:56:54.592867 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 13:56:54.599134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 13:56:54.599296 ==
3567 13:56:54.599392
3568 13:56:54.599475
3569 13:56:54.599576 TX Vref Scan disable
3570 13:56:54.603138 == TX Byte 0 ==
3571 13:56:54.606541 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3572 13:56:54.610045 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3573 13:56:54.613342 == TX Byte 1 ==
3574 13:56:54.616570 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3575 13:56:54.619775 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3576 13:56:54.623272 ==
3577 13:56:54.626670 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 13:56:54.629657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 13:56:54.629736 ==
3580 13:56:54.641348 TX Vref=22, minBit 0, minWin=25, winSum=418
3581 13:56:54.644672 TX Vref=24, minBit 0, minWin=25, winSum=422
3582 13:56:54.647708 TX Vref=26, minBit 3, minWin=25, winSum=427
3583 13:56:54.651186 TX Vref=28, minBit 0, minWin=26, winSum=431
3584 13:56:54.654679 TX Vref=30, minBit 2, minWin=26, winSum=433
3585 13:56:54.657631 TX Vref=32, minBit 0, minWin=26, winSum=435
3586 13:56:54.664391 [TxChooseVref] Worse bit 0, Min win 26, Win sum 435, Final Vref 32
3587 13:56:54.664532
3588 13:56:54.667571 Final TX Range 1 Vref 32
3589 13:56:54.667658
3590 13:56:54.667723 ==
3591 13:56:54.671637 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 13:56:54.674219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 13:56:54.674308 ==
3594 13:56:54.674374
3595 13:56:54.674447
3596 13:56:54.678145 TX Vref Scan disable
3597 13:56:54.681105 == TX Byte 0 ==
3598 13:56:54.684831 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3599 13:56:54.687775 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3600 13:56:54.691202 == TX Byte 1 ==
3601 13:56:54.695047 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3602 13:56:54.697779 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3603 13:56:54.697879
3604 13:56:54.701370 [DATLAT]
3605 13:56:54.701463 Freq=1200, CH1 RK1
3606 13:56:54.701531
3607 13:56:54.704516 DATLAT Default: 0xd
3608 13:56:54.704609 0, 0xFFFF, sum = 0
3609 13:56:54.707786 1, 0xFFFF, sum = 0
3610 13:56:54.707870 2, 0xFFFF, sum = 0
3611 13:56:54.711221 3, 0xFFFF, sum = 0
3612 13:56:54.711305 4, 0xFFFF, sum = 0
3613 13:56:54.714419 5, 0xFFFF, sum = 0
3614 13:56:54.714503 6, 0xFFFF, sum = 0
3615 13:56:54.718041 7, 0xFFFF, sum = 0
3616 13:56:54.718124 8, 0xFFFF, sum = 0
3617 13:56:54.721165 9, 0xFFFF, sum = 0
3618 13:56:54.721249 10, 0xFFFF, sum = 0
3619 13:56:54.724393 11, 0xFFFF, sum = 0
3620 13:56:54.727733 12, 0x0, sum = 1
3621 13:56:54.727824 13, 0x0, sum = 2
3622 13:56:54.727891 14, 0x0, sum = 3
3623 13:56:54.731322 15, 0x0, sum = 4
3624 13:56:54.731405 best_step = 13
3625 13:56:54.731470
3626 13:56:54.731530 ==
3627 13:56:54.734855 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 13:56:54.740760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 13:56:54.740844 ==
3630 13:56:54.740909 RX Vref Scan: 0
3631 13:56:54.740969
3632 13:56:54.744121 RX Vref 0 -> 0, step: 1
3633 13:56:54.744202
3634 13:56:54.747833 RX Delay -21 -> 252, step: 4
3635 13:56:54.750773 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3636 13:56:54.754315 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3637 13:56:54.761111 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3638 13:56:54.764406 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3639 13:56:54.767754 iDelay=191, Bit 4, Center 112 (47 ~ 178) 132
3640 13:56:54.771325 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3641 13:56:54.774069 iDelay=191, Bit 6, Center 120 (55 ~ 186) 132
3642 13:56:54.780941 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3643 13:56:54.784031 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3644 13:56:54.787228 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3645 13:56:54.790987 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3646 13:56:54.793807 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3647 13:56:54.800485 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3648 13:56:54.804225 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3649 13:56:54.807069 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3650 13:56:54.810625 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3651 13:56:54.810706 ==
3652 13:56:54.814193 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 13:56:54.820843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 13:56:54.820924 ==
3655 13:56:54.820988 DQS Delay:
3656 13:56:54.823853 DQS0 = 0, DQS1 = 0
3657 13:56:54.823933 DQM Delay:
3658 13:56:54.827378 DQM0 = 113, DQM1 = 109
3659 13:56:54.827458 DQ Delay:
3660 13:56:54.830802 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3661 13:56:54.833756 DQ4 =112, DQ5 =124, DQ6 =120, DQ7 =110
3662 13:56:54.836983 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =102
3663 13:56:54.840727 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3664 13:56:54.840821
3665 13:56:54.840899
3666 13:56:54.850527 [DQSOSCAuto] RK1, (LSB)MR18= 0xf800, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3667 13:56:54.850608 CH1 RK1: MR19=304, MR18=F800
3668 13:56:54.857206 CH1_RK1: MR19=0x304, MR18=0xF800, DQSOSC=410, MR23=63, INC=39, DEC=26
3669 13:56:54.860886 [RxdqsGatingPostProcess] freq 1200
3670 13:56:54.867434 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3671 13:56:54.870470 best DQS0 dly(2T, 0.5T) = (0, 11)
3672 13:56:54.874200 best DQS1 dly(2T, 0.5T) = (0, 11)
3673 13:56:54.877079 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3674 13:56:54.880719 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3675 13:56:54.883435 best DQS0 dly(2T, 0.5T) = (0, 11)
3676 13:56:54.883515 best DQS1 dly(2T, 0.5T) = (0, 11)
3677 13:56:54.887353 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3678 13:56:54.890789 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3679 13:56:54.893630 Pre-setting of DQS Precalculation
3680 13:56:54.900207 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3681 13:56:54.907150 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3682 13:56:54.913579 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3683 13:56:54.913660
3684 13:56:54.913722
3685 13:56:54.917028 [Calibration Summary] 2400 Mbps
3686 13:56:54.917107 CH 0, Rank 0
3687 13:56:54.920530 SW Impedance : PASS
3688 13:56:54.924012 DUTY Scan : NO K
3689 13:56:54.924092 ZQ Calibration : PASS
3690 13:56:54.927376 Jitter Meter : NO K
3691 13:56:54.930514 CBT Training : PASS
3692 13:56:54.930594 Write leveling : PASS
3693 13:56:54.934023 RX DQS gating : PASS
3694 13:56:54.936970 RX DQ/DQS(RDDQC) : PASS
3695 13:56:54.937050 TX DQ/DQS : PASS
3696 13:56:54.940372 RX DATLAT : PASS
3697 13:56:54.943643 RX DQ/DQS(Engine): PASS
3698 13:56:54.943726 TX OE : NO K
3699 13:56:54.943789 All Pass.
3700 13:56:54.943848
3701 13:56:54.947190 CH 0, Rank 1
3702 13:56:54.950276 SW Impedance : PASS
3703 13:56:54.950356 DUTY Scan : NO K
3704 13:56:54.953936 ZQ Calibration : PASS
3705 13:56:54.954020 Jitter Meter : NO K
3706 13:56:54.957191 CBT Training : PASS
3707 13:56:54.960529 Write leveling : PASS
3708 13:56:54.960608 RX DQS gating : PASS
3709 13:56:54.963672 RX DQ/DQS(RDDQC) : PASS
3710 13:56:54.967172 TX DQ/DQS : PASS
3711 13:56:54.967252 RX DATLAT : PASS
3712 13:56:54.970384 RX DQ/DQS(Engine): PASS
3713 13:56:54.973847 TX OE : NO K
3714 13:56:54.973926 All Pass.
3715 13:56:54.973997
3716 13:56:54.974057 CH 1, Rank 0
3717 13:56:54.977150 SW Impedance : PASS
3718 13:56:54.980394 DUTY Scan : NO K
3719 13:56:54.980473 ZQ Calibration : PASS
3720 13:56:54.984001 Jitter Meter : NO K
3721 13:56:54.986830 CBT Training : PASS
3722 13:56:54.986911 Write leveling : PASS
3723 13:56:54.990294 RX DQS gating : PASS
3724 13:56:54.993720 RX DQ/DQS(RDDQC) : PASS
3725 13:56:54.993798 TX DQ/DQS : PASS
3726 13:56:54.997303 RX DATLAT : PASS
3727 13:56:54.997383 RX DQ/DQS(Engine): PASS
3728 13:56:55.000875 TX OE : NO K
3729 13:56:55.000954 All Pass.
3730 13:56:55.001017
3731 13:56:55.003771 CH 1, Rank 1
3732 13:56:55.003876 SW Impedance : PASS
3733 13:56:55.007077 DUTY Scan : NO K
3734 13:56:55.010812 ZQ Calibration : PASS
3735 13:56:55.010891 Jitter Meter : NO K
3736 13:56:55.013815 CBT Training : PASS
3737 13:56:55.017328 Write leveling : PASS
3738 13:56:55.017407 RX DQS gating : PASS
3739 13:56:55.020200 RX DQ/DQS(RDDQC) : PASS
3740 13:56:55.024028 TX DQ/DQS : PASS
3741 13:56:55.024122 RX DATLAT : PASS
3742 13:56:55.027244 RX DQ/DQS(Engine): PASS
3743 13:56:55.030145 TX OE : NO K
3744 13:56:55.030250 All Pass.
3745 13:56:55.030340
3746 13:56:55.030461 DramC Write-DBI off
3747 13:56:55.033767 PER_BANK_REFRESH: Hybrid Mode
3748 13:56:55.036804 TX_TRACKING: ON
3749 13:56:55.043670 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3750 13:56:55.046997 [FAST_K] Save calibration result to emmc
3751 13:56:55.053459 dramc_set_vcore_voltage set vcore to 650000
3752 13:56:55.053539 Read voltage for 600, 5
3753 13:56:55.057188 Vio18 = 0
3754 13:56:55.057268 Vcore = 650000
3755 13:56:55.057331 Vdram = 0
3756 13:56:55.057389 Vddq = 0
3757 13:56:55.060647 Vmddr = 0
3758 13:56:55.063748 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3759 13:56:55.070187 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3760 13:56:55.073591 MEM_TYPE=3, freq_sel=19
3761 13:56:55.073671 sv_algorithm_assistance_LP4_1600
3762 13:56:55.080377 ============ PULL DRAM RESETB DOWN ============
3763 13:56:55.084033 ========== PULL DRAM RESETB DOWN end =========
3764 13:56:55.087111 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3765 13:56:55.090191 ===================================
3766 13:56:55.093689 LPDDR4 DRAM CONFIGURATION
3767 13:56:55.097129 ===================================
3768 13:56:55.100420 EX_ROW_EN[0] = 0x0
3769 13:56:55.100500 EX_ROW_EN[1] = 0x0
3770 13:56:55.104088 LP4Y_EN = 0x0
3771 13:56:55.104168 WORK_FSP = 0x0
3772 13:56:55.107285 WL = 0x2
3773 13:56:55.107373 RL = 0x2
3774 13:56:55.110859 BL = 0x2
3775 13:56:55.110939 RPST = 0x0
3776 13:56:55.114027 RD_PRE = 0x0
3777 13:56:55.114132 WR_PRE = 0x1
3778 13:56:55.117391 WR_PST = 0x0
3779 13:56:55.117471 DBI_WR = 0x0
3780 13:56:55.120509 DBI_RD = 0x0
3781 13:56:55.120588 OTF = 0x1
3782 13:56:55.123660 ===================================
3783 13:56:55.127476 ===================================
3784 13:56:55.130831 ANA top config
3785 13:56:55.133844 ===================================
3786 13:56:55.133924 DLL_ASYNC_EN = 0
3787 13:56:55.137253 ALL_SLAVE_EN = 1
3788 13:56:55.140484 NEW_RANK_MODE = 1
3789 13:56:55.143883 DLL_IDLE_MODE = 1
3790 13:56:55.147121 LP45_APHY_COMB_EN = 1
3791 13:56:55.147201 TX_ODT_DIS = 1
3792 13:56:55.150735 NEW_8X_MODE = 1
3793 13:56:55.154153 ===================================
3794 13:56:55.157173 ===================================
3795 13:56:55.160933 data_rate = 1200
3796 13:56:55.163873 CKR = 1
3797 13:56:55.167468 DQ_P2S_RATIO = 8
3798 13:56:55.170787 ===================================
3799 13:56:55.170867 CA_P2S_RATIO = 8
3800 13:56:55.173879 DQ_CA_OPEN = 0
3801 13:56:55.177622 DQ_SEMI_OPEN = 0
3802 13:56:55.180880 CA_SEMI_OPEN = 0
3803 13:56:55.183906 CA_FULL_RATE = 0
3804 13:56:55.187209 DQ_CKDIV4_EN = 1
3805 13:56:55.187285 CA_CKDIV4_EN = 1
3806 13:56:55.190981 CA_PREDIV_EN = 0
3807 13:56:55.194089 PH8_DLY = 0
3808 13:56:55.197436 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3809 13:56:55.200631 DQ_AAMCK_DIV = 4
3810 13:56:55.200725 CA_AAMCK_DIV = 4
3811 13:56:55.204141 CA_ADMCK_DIV = 4
3812 13:56:55.207257 DQ_TRACK_CA_EN = 0
3813 13:56:55.210962 CA_PICK = 600
3814 13:56:55.214319 CA_MCKIO = 600
3815 13:56:55.218069 MCKIO_SEMI = 0
3816 13:56:55.221388 PLL_FREQ = 2288
3817 13:56:55.221477 DQ_UI_PI_RATIO = 32
3818 13:56:55.224163 CA_UI_PI_RATIO = 0
3819 13:56:55.227710 ===================================
3820 13:56:55.231045 ===================================
3821 13:56:55.234114 memory_type:LPDDR4
3822 13:56:55.237829 GP_NUM : 10
3823 13:56:55.237909 SRAM_EN : 1
3824 13:56:55.240676 MD32_EN : 0
3825 13:56:55.244554 ===================================
3826 13:56:55.247607 [ANA_INIT] >>>>>>>>>>>>>>
3827 13:56:55.247675 <<<<<< [CONFIGURE PHASE]: ANA_TX
3828 13:56:55.250984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3829 13:56:55.253946 ===================================
3830 13:56:55.257922 data_rate = 1200,PCW = 0X5800
3831 13:56:55.260939 ===================================
3832 13:56:55.264234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3833 13:56:55.270950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3834 13:56:55.274659 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 13:56:55.281236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3836 13:56:55.284311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3837 13:56:55.287813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3838 13:56:55.290894 [ANA_INIT] flow start
3839 13:56:55.290969 [ANA_INIT] PLL >>>>>>>>
3840 13:56:55.294214 [ANA_INIT] PLL <<<<<<<<
3841 13:56:55.297935 [ANA_INIT] MIDPI >>>>>>>>
3842 13:56:55.298016 [ANA_INIT] MIDPI <<<<<<<<
3843 13:56:55.301246 [ANA_INIT] DLL >>>>>>>>
3844 13:56:55.304460 [ANA_INIT] flow end
3845 13:56:55.307578 ============ LP4 DIFF to SE enter ============
3846 13:56:55.311193 ============ LP4 DIFF to SE exit ============
3847 13:56:55.314292 [ANA_INIT] <<<<<<<<<<<<<
3848 13:56:55.318262 [Flow] Enable top DCM control >>>>>
3849 13:56:55.321312 [Flow] Enable top DCM control <<<<<
3850 13:56:55.324450 Enable DLL master slave shuffle
3851 13:56:55.328116 ==============================================================
3852 13:56:55.331254 Gating Mode config
3853 13:56:55.335154 ==============================================================
3854 13:56:55.338019 Config description:
3855 13:56:55.348029 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3856 13:56:55.354435 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3857 13:56:55.357750 SELPH_MODE 0: By rank 1: By Phase
3858 13:56:55.364775 ==============================================================
3859 13:56:55.367583 GAT_TRACK_EN = 1
3860 13:56:55.371256 RX_GATING_MODE = 2
3861 13:56:55.374406 RX_GATING_TRACK_MODE = 2
3862 13:56:55.377574 SELPH_MODE = 1
3863 13:56:55.381079 PICG_EARLY_EN = 1
3864 13:56:55.381152 VALID_LAT_VALUE = 1
3865 13:56:55.388032 ==============================================================
3866 13:56:55.391097 Enter into Gating configuration >>>>
3867 13:56:55.394516 Exit from Gating configuration <<<<
3868 13:56:55.397761 Enter into DVFS_PRE_config >>>>>
3869 13:56:55.407827 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3870 13:56:55.411392 Exit from DVFS_PRE_config <<<<<
3871 13:56:55.414353 Enter into PICG configuration >>>>
3872 13:56:55.417865 Exit from PICG configuration <<<<
3873 13:56:55.420989 [RX_INPUT] configuration >>>>>
3874 13:56:55.424533 [RX_INPUT] configuration <<<<<
3875 13:56:55.428117 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3876 13:56:55.434263 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3877 13:56:55.441022 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3878 13:56:55.447622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3879 13:56:55.454409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 13:56:55.457937 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 13:56:55.464197 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3882 13:56:55.467836 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3883 13:56:55.471237 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3884 13:56:55.474426 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3885 13:56:55.477664 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3886 13:56:55.484812 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 13:56:55.488328 ===================================
3888 13:56:55.491509 LPDDR4 DRAM CONFIGURATION
3889 13:56:55.491579 ===================================
3890 13:56:55.494554 EX_ROW_EN[0] = 0x0
3891 13:56:55.497759 EX_ROW_EN[1] = 0x0
3892 13:56:55.497828 LP4Y_EN = 0x0
3893 13:56:55.501539 WORK_FSP = 0x0
3894 13:56:55.501629 WL = 0x2
3895 13:56:55.504389 RL = 0x2
3896 13:56:55.504483 BL = 0x2
3897 13:56:55.507781 RPST = 0x0
3898 13:56:55.507855 RD_PRE = 0x0
3899 13:56:55.511393 WR_PRE = 0x1
3900 13:56:55.511487 WR_PST = 0x0
3901 13:56:55.514435 DBI_WR = 0x0
3902 13:56:55.514519 DBI_RD = 0x0
3903 13:56:55.517766 OTF = 0x1
3904 13:56:55.521229 ===================================
3905 13:56:55.524828 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3906 13:56:55.527694 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3907 13:56:55.534353 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3908 13:56:55.537752 ===================================
3909 13:56:55.537854 LPDDR4 DRAM CONFIGURATION
3910 13:56:55.541303 ===================================
3911 13:56:55.544464 EX_ROW_EN[0] = 0x10
3912 13:56:55.548271 EX_ROW_EN[1] = 0x0
3913 13:56:55.548371 LP4Y_EN = 0x0
3914 13:56:55.551399 WORK_FSP = 0x0
3915 13:56:55.551510 WL = 0x2
3916 13:56:55.554723 RL = 0x2
3917 13:56:55.554821 BL = 0x2
3918 13:56:55.557737 RPST = 0x0
3919 13:56:55.557898 RD_PRE = 0x0
3920 13:56:55.561588 WR_PRE = 0x1
3921 13:56:55.561662 WR_PST = 0x0
3922 13:56:55.564888 DBI_WR = 0x0
3923 13:56:55.564991 DBI_RD = 0x0
3924 13:56:55.567660 OTF = 0x1
3925 13:56:55.571022 ===================================
3926 13:56:55.577806 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3927 13:56:55.581197 nWR fixed to 30
3928 13:56:55.581301 [ModeRegInit_LP4] CH0 RK0
3929 13:56:55.584318 [ModeRegInit_LP4] CH0 RK1
3930 13:56:55.587898 [ModeRegInit_LP4] CH1 RK0
3931 13:56:55.588000 [ModeRegInit_LP4] CH1 RK1
3932 13:56:55.591268 match AC timing 17
3933 13:56:55.594597 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3934 13:56:55.598104 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3935 13:56:55.604745 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3936 13:56:55.608186 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3937 13:56:55.615097 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3938 13:56:55.615203 ==
3939 13:56:55.618050 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 13:56:55.621602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 13:56:55.621699 ==
3942 13:56:55.628116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3943 13:56:55.631652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3944 13:56:55.635302 [CA 0] Center 36 (6~66) winsize 61
3945 13:56:55.639263 [CA 1] Center 36 (6~66) winsize 61
3946 13:56:55.642222 [CA 2] Center 34 (4~65) winsize 62
3947 13:56:55.645373 [CA 3] Center 34 (4~64) winsize 61
3948 13:56:55.648813 [CA 4] Center 33 (3~64) winsize 62
3949 13:56:55.652146 [CA 5] Center 33 (3~64) winsize 62
3950 13:56:55.652250
3951 13:56:55.655372 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3952 13:56:55.655472
3953 13:56:55.659057 [CATrainingPosCal] consider 1 rank data
3954 13:56:55.662239 u2DelayCellTimex100 = 270/100 ps
3955 13:56:55.665320 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3956 13:56:55.669720 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 13:56:55.675640 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 13:56:55.678642 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3959 13:56:55.682413 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3960 13:56:55.685340 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 13:56:55.685412
3962 13:56:55.688503 CA PerBit enable=1, Macro0, CA PI delay=33
3963 13:56:55.688600
3964 13:56:55.692330 [CBTSetCACLKResult] CA Dly = 33
3965 13:56:55.692424 CS Dly: 5 (0~36)
3966 13:56:55.695548 ==
3967 13:56:55.695630 Dram Type= 6, Freq= 0, CH_0, rank 1
3968 13:56:55.702125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 13:56:55.702231 ==
3970 13:56:55.705506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 13:56:55.712472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3972 13:56:55.716116 [CA 0] Center 36 (6~66) winsize 61
3973 13:56:55.718964 [CA 1] Center 36 (6~66) winsize 61
3974 13:56:55.722346 [CA 2] Center 34 (4~65) winsize 62
3975 13:56:55.725742 [CA 3] Center 34 (4~65) winsize 62
3976 13:56:55.728992 [CA 4] Center 33 (3~64) winsize 62
3977 13:56:55.732593 [CA 5] Center 33 (3~64) winsize 62
3978 13:56:55.732697
3979 13:56:55.735608 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3980 13:56:55.735689
3981 13:56:55.738906 [CATrainingPosCal] consider 2 rank data
3982 13:56:55.742257 u2DelayCellTimex100 = 270/100 ps
3983 13:56:55.745504 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3984 13:56:55.748863 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 13:56:55.755530 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3986 13:56:55.759099 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3987 13:56:55.762583 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 13:56:55.765985 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 13:56:55.766059
3990 13:56:55.769374 CA PerBit enable=1, Macro0, CA PI delay=33
3991 13:56:55.769446
3992 13:56:55.772320 [CBTSetCACLKResult] CA Dly = 33
3993 13:56:55.772389 CS Dly: 5 (0~36)
3994 13:56:55.772448
3995 13:56:55.775626 ----->DramcWriteLeveling(PI) begin...
3996 13:56:55.779237 ==
3997 13:56:55.781995 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 13:56:55.785877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 13:56:55.785986 ==
4000 13:56:55.788947 Write leveling (Byte 0): 32 => 32
4001 13:56:55.792434 Write leveling (Byte 1): 31 => 31
4002 13:56:55.795523 DramcWriteLeveling(PI) end<-----
4003 13:56:55.795628
4004 13:56:55.795717 ==
4005 13:56:55.799339 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 13:56:55.802505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 13:56:55.802593 ==
4008 13:56:55.805901 [Gating] SW mode calibration
4009 13:56:55.812279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4010 13:56:55.815574 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4011 13:56:55.822595 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4012 13:56:55.825535 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 13:56:55.829145 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 13:56:55.835711 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 13:56:55.839313 0 9 16 | B1->B0 | 3030 2929 | 1 0 | (1 0) (0 0)
4016 13:56:55.842519 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 13:56:55.849242 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 13:56:55.852438 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 13:56:55.856161 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 13:56:55.862873 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 13:56:55.866012 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 13:56:55.869311 0 10 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4023 13:56:55.872853 0 10 16 | B1->B0 | 3434 3939 | 0 0 | (0 0) (0 0)
4024 13:56:55.879271 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 13:56:55.882578 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 13:56:55.886201 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 13:56:55.893149 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 13:56:55.896109 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 13:56:55.899719 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 13:56:55.906043 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 13:56:55.909617 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4032 13:56:55.913103 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 13:56:55.919912 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 13:56:55.922644 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 13:56:55.926240 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 13:56:55.932824 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 13:56:55.936381 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 13:56:55.939438 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 13:56:55.945965 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 13:56:55.949490 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 13:56:55.952933 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 13:56:55.956361 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 13:56:55.963077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 13:56:55.966069 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 13:56:55.969647 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 13:56:55.976199 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 13:56:55.979500 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4048 13:56:55.982716 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 13:56:55.986358 Total UI for P1: 0, mck2ui 16
4050 13:56:55.989650 best dqsien dly found for B0: ( 0, 13, 16)
4051 13:56:55.992755 Total UI for P1: 0, mck2ui 16
4052 13:56:55.996047 best dqsien dly found for B1: ( 0, 13, 16)
4053 13:56:55.999315 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4054 13:56:56.002606 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4055 13:56:56.002680
4056 13:56:56.009373 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4057 13:56:56.012622 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4058 13:56:56.015984 [Gating] SW calibration Done
4059 13:56:56.016057 ==
4060 13:56:56.019638 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 13:56:56.022546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 13:56:56.022651 ==
4063 13:56:56.022742 RX Vref Scan: 0
4064 13:56:56.022828
4065 13:56:56.026010 RX Vref 0 -> 0, step: 1
4066 13:56:56.026111
4067 13:56:56.029285 RX Delay -230 -> 252, step: 16
4068 13:56:56.032830 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4069 13:56:56.035994 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4070 13:56:56.042490 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4071 13:56:56.045873 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4072 13:56:56.049401 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4073 13:56:56.052847 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4074 13:56:56.059212 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4075 13:56:56.063162 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4076 13:56:56.066123 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4077 13:56:56.069664 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4078 13:56:56.072769 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4079 13:56:56.079208 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4080 13:56:56.083112 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4081 13:56:56.085979 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4082 13:56:56.089156 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4083 13:56:56.096193 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4084 13:56:56.096290 ==
4085 13:56:56.099324 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 13:56:56.103227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 13:56:56.103297 ==
4088 13:56:56.103405 DQS Delay:
4089 13:56:56.106062 DQS0 = 0, DQS1 = 0
4090 13:56:56.106159 DQM Delay:
4091 13:56:56.109371 DQM0 = 41, DQM1 = 32
4092 13:56:56.109441 DQ Delay:
4093 13:56:56.112616 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4094 13:56:56.115923 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4095 13:56:56.119491 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4096 13:56:56.122545 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4097 13:56:56.122644
4098 13:56:56.122733
4099 13:56:56.122818 ==
4100 13:56:56.126285 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 13:56:56.129352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 13:56:56.129434 ==
4103 13:56:56.129496
4104 13:56:56.129554
4105 13:56:56.132963 TX Vref Scan disable
4106 13:56:56.136326 == TX Byte 0 ==
4107 13:56:56.139719 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4108 13:56:56.142572 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4109 13:56:56.145881 == TX Byte 1 ==
4110 13:56:56.149232 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4111 13:56:56.152951 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4112 13:56:56.153051 ==
4113 13:56:56.156457 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 13:56:56.162847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 13:56:56.162927 ==
4116 13:56:56.163003
4117 13:56:56.163065
4118 13:56:56.163122 TX Vref Scan disable
4119 13:56:56.166870 == TX Byte 0 ==
4120 13:56:56.170410 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4121 13:56:56.176952 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4122 13:56:56.177050 == TX Byte 1 ==
4123 13:56:56.180365 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4124 13:56:56.184051 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4125 13:56:56.186973
4126 13:56:56.187052 [DATLAT]
4127 13:56:56.187115 Freq=600, CH0 RK0
4128 13:56:56.187174
4129 13:56:56.190526 DATLAT Default: 0x9
4130 13:56:56.190614 0, 0xFFFF, sum = 0
4131 13:56:56.193940 1, 0xFFFF, sum = 0
4132 13:56:56.194020 2, 0xFFFF, sum = 0
4133 13:56:56.197510 3, 0xFFFF, sum = 0
4134 13:56:56.197590 4, 0xFFFF, sum = 0
4135 13:56:56.200967 5, 0xFFFF, sum = 0
4136 13:56:56.201055 6, 0xFFFF, sum = 0
4137 13:56:56.204032 7, 0xFFFF, sum = 0
4138 13:56:56.204112 8, 0x0, sum = 1
4139 13:56:56.207602 9, 0x0, sum = 2
4140 13:56:56.207682 10, 0x0, sum = 3
4141 13:56:56.210895 11, 0x0, sum = 4
4142 13:56:56.210976 best_step = 9
4143 13:56:56.211037
4144 13:56:56.211094 ==
4145 13:56:56.213730 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 13:56:56.220421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 13:56:56.220501 ==
4148 13:56:56.220582 RX Vref Scan: 1
4149 13:56:56.220667
4150 13:56:56.223784 RX Vref 0 -> 0, step: 1
4151 13:56:56.223863
4152 13:56:56.227177 RX Delay -195 -> 252, step: 8
4153 13:56:56.227291
4154 13:56:56.230663 Set Vref, RX VrefLevel [Byte0]: 56
4155 13:56:56.234002 [Byte1]: 52
4156 13:56:56.234082
4157 13:56:56.237429 Final RX Vref Byte 0 = 56 to rank0
4158 13:56:56.240483 Final RX Vref Byte 1 = 52 to rank0
4159 13:56:56.243902 Final RX Vref Byte 0 = 56 to rank1
4160 13:56:56.246976 Final RX Vref Byte 1 = 52 to rank1==
4161 13:56:56.250634 Dram Type= 6, Freq= 0, CH_0, rank 0
4162 13:56:56.253791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 13:56:56.253881 ==
4164 13:56:56.257455 DQS Delay:
4165 13:56:56.257535 DQS0 = 0, DQS1 = 0
4166 13:56:56.257597 DQM Delay:
4167 13:56:56.260466 DQM0 = 42, DQM1 = 33
4168 13:56:56.260578 DQ Delay:
4169 13:56:56.263538 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4170 13:56:56.266967 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4171 13:56:56.270240 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4172 13:56:56.273808 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4173 13:56:56.273887
4174 13:56:56.273949
4175 13:56:56.284127 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4176 13:56:56.284207 CH0 RK0: MR19=808, MR18=3E1D
4177 13:56:56.290938 CH0_RK0: MR19=0x808, MR18=0x3E1D, DQSOSC=398, MR23=63, INC=165, DEC=110
4178 13:56:56.291017
4179 13:56:56.293877 ----->DramcWriteLeveling(PI) begin...
4180 13:56:56.293957 ==
4181 13:56:56.297467 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 13:56:56.303789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 13:56:56.303880 ==
4184 13:56:56.306989 Write leveling (Byte 0): 33 => 33
4185 13:56:56.310746 Write leveling (Byte 1): 30 => 30
4186 13:56:56.313412 DramcWriteLeveling(PI) end<-----
4187 13:56:56.313491
4188 13:56:56.313554 ==
4189 13:56:56.316997 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 13:56:56.320149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 13:56:56.320228 ==
4192 13:56:56.323681 [Gating] SW mode calibration
4193 13:56:56.330580 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4194 13:56:56.333719 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4195 13:56:56.340520 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4196 13:56:56.343540 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 13:56:56.346788 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4198 13:56:56.353667 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
4199 13:56:56.356853 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
4200 13:56:56.360133 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 13:56:56.366576 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 13:56:56.370410 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 13:56:56.373617 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 13:56:56.380586 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 13:56:56.383425 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 13:56:56.387009 0 10 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
4207 13:56:56.393565 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4208 13:56:56.396749 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 13:56:56.399866 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 13:56:56.406863 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 13:56:56.410861 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 13:56:56.414047 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 13:56:56.416871 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 13:56:56.423583 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 13:56:56.427194 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4216 13:56:56.430298 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 13:56:56.436723 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 13:56:56.439990 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 13:56:56.443810 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 13:56:56.450331 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 13:56:56.453587 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 13:56:56.456922 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 13:56:56.464282 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 13:56:56.467128 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 13:56:56.470127 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 13:56:56.476946 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 13:56:56.480338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 13:56:56.483915 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 13:56:56.490609 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 13:56:56.494025 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4231 13:56:56.497151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 13:56:56.500819 Total UI for P1: 0, mck2ui 16
4233 13:56:56.503515 best dqsien dly found for B0: ( 0, 13, 12)
4234 13:56:56.507442 Total UI for P1: 0, mck2ui 16
4235 13:56:56.510325 best dqsien dly found for B1: ( 0, 13, 12)
4236 13:56:56.513985 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4237 13:56:56.517003 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4238 13:56:56.517085
4239 13:56:56.520243 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4240 13:56:56.527276 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4241 13:56:56.527350 [Gating] SW calibration Done
4242 13:56:56.527413 ==
4243 13:56:56.530283 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 13:56:56.536719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 13:56:56.536811 ==
4246 13:56:56.536902 RX Vref Scan: 0
4247 13:56:56.536990
4248 13:56:56.540229 RX Vref 0 -> 0, step: 1
4249 13:56:56.540309
4250 13:56:56.543345 RX Delay -230 -> 252, step: 16
4251 13:56:56.547048 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4252 13:56:56.550371 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4253 13:56:56.553337 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4254 13:56:56.560426 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4255 13:56:56.563821 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4256 13:56:56.567134 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4257 13:56:56.570216 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4258 13:56:56.577127 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4259 13:56:56.580184 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4260 13:56:56.583659 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4261 13:56:56.586987 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4262 13:56:56.590655 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4263 13:56:56.596678 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4264 13:56:56.600706 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4265 13:56:56.604002 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4266 13:56:56.607259 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4267 13:56:56.607333 ==
4268 13:56:56.610304 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 13:56:56.616747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 13:56:56.616852 ==
4271 13:56:56.616944 DQS Delay:
4272 13:56:56.620658 DQS0 = 0, DQS1 = 0
4273 13:56:56.620738 DQM Delay:
4274 13:56:56.624127 DQM0 = 39, DQM1 = 34
4275 13:56:56.624233 DQ Delay:
4276 13:56:56.627115 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4277 13:56:56.630420 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4278 13:56:56.633602 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4279 13:56:56.636968 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4280 13:56:56.637048
4281 13:56:56.637111
4282 13:56:56.637170 ==
4283 13:56:56.640447 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 13:56:56.644123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 13:56:56.644197 ==
4286 13:56:56.644258
4287 13:56:56.644316
4288 13:56:56.647023 TX Vref Scan disable
4289 13:56:56.650157 == TX Byte 0 ==
4290 13:56:56.653855 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4291 13:56:56.657352 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4292 13:56:56.660191 == TX Byte 1 ==
4293 13:56:56.663687 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4294 13:56:56.667133 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4295 13:56:56.667239 ==
4296 13:56:56.670285 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 13:56:56.674061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 13:56:56.674144 ==
4299 13:56:56.674207
4300 13:56:56.677466
4301 13:56:56.677573 TX Vref Scan disable
4302 13:56:56.681064 == TX Byte 0 ==
4303 13:56:56.684228 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4304 13:56:56.687072 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4305 13:56:56.691016 == TX Byte 1 ==
4306 13:56:56.694161 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4307 13:56:56.700635 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4308 13:56:56.700716
4309 13:56:56.700783 [DATLAT]
4310 13:56:56.700842 Freq=600, CH0 RK1
4311 13:56:56.700898
4312 13:56:56.703872 DATLAT Default: 0x9
4313 13:56:56.703957 0, 0xFFFF, sum = 0
4314 13:56:56.707489 1, 0xFFFF, sum = 0
4315 13:56:56.707570 2, 0xFFFF, sum = 0
4316 13:56:56.710777 3, 0xFFFF, sum = 0
4317 13:56:56.714502 4, 0xFFFF, sum = 0
4318 13:56:56.714616 5, 0xFFFF, sum = 0
4319 13:56:56.717515 6, 0xFFFF, sum = 0
4320 13:56:56.717618 7, 0xFFFF, sum = 0
4321 13:56:56.717713 8, 0x0, sum = 1
4322 13:56:56.720798 9, 0x0, sum = 2
4323 13:56:56.720879 10, 0x0, sum = 3
4324 13:56:56.724033 11, 0x0, sum = 4
4325 13:56:56.724105 best_step = 9
4326 13:56:56.724164
4327 13:56:56.724219 ==
4328 13:56:56.726986 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 13:56:56.733988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 13:56:56.734068 ==
4331 13:56:56.734131 RX Vref Scan: 0
4332 13:56:56.734190
4333 13:56:56.737144 RX Vref 0 -> 0, step: 1
4334 13:56:56.737223
4335 13:56:56.740741 RX Delay -179 -> 252, step: 8
4336 13:56:56.744168 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4337 13:56:56.750362 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4338 13:56:56.753768 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4339 13:56:56.757319 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4340 13:56:56.760303 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4341 13:56:56.763558 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4342 13:56:56.770441 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4343 13:56:56.774061 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4344 13:56:56.777324 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4345 13:56:56.780542 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4346 13:56:56.787024 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4347 13:56:56.790428 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4348 13:56:56.793468 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4349 13:56:56.796863 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4350 13:56:56.803909 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4351 13:56:56.807230 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4352 13:56:56.807314 ==
4353 13:56:56.810299 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 13:56:56.813690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 13:56:56.813770 ==
4356 13:56:56.817360 DQS Delay:
4357 13:56:56.817439 DQS0 = 0, DQS1 = 0
4358 13:56:56.817501 DQM Delay:
4359 13:56:56.820456 DQM0 = 41, DQM1 = 32
4360 13:56:56.820535 DQ Delay:
4361 13:56:56.823722 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =40
4362 13:56:56.827277 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4363 13:56:56.830377 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4364 13:56:56.833718 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4365 13:56:56.833798
4366 13:56:56.833865
4367 13:56:56.843939 [DQSOSCAuto] RK1, (LSB)MR18= 0x4729, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4368 13:56:56.844047 CH0 RK1: MR19=808, MR18=4729
4369 13:56:56.850156 CH0_RK1: MR19=0x808, MR18=0x4729, DQSOSC=396, MR23=63, INC=167, DEC=111
4370 13:56:56.853805 [RxdqsGatingPostProcess] freq 600
4371 13:56:56.860403 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4372 13:56:56.864063 Pre-setting of DQS Precalculation
4373 13:56:56.867042 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4374 13:56:56.867122 ==
4375 13:56:56.870320 Dram Type= 6, Freq= 0, CH_1, rank 0
4376 13:56:56.873640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 13:56:56.873721 ==
4378 13:56:56.880875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4379 13:56:56.887211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4380 13:56:56.890796 [CA 0] Center 35 (5~66) winsize 62
4381 13:56:56.893622 [CA 1] Center 35 (5~66) winsize 62
4382 13:56:56.897113 [CA 2] Center 34 (4~65) winsize 62
4383 13:56:56.900448 [CA 3] Center 33 (3~64) winsize 62
4384 13:56:56.903872 [CA 4] Center 34 (3~65) winsize 63
4385 13:56:56.906984 [CA 5] Center 33 (2~64) winsize 63
4386 13:56:56.907064
4387 13:56:56.910836 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4388 13:56:56.910943
4389 13:56:56.913663 [CATrainingPosCal] consider 1 rank data
4390 13:56:56.917147 u2DelayCellTimex100 = 270/100 ps
4391 13:56:56.920901 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4392 13:56:56.923814 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 13:56:56.927312 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 13:56:56.930700 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4395 13:56:56.934027 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4396 13:56:56.940648 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4397 13:56:56.940723
4398 13:56:56.944385 CA PerBit enable=1, Macro0, CA PI delay=33
4399 13:56:56.944455
4400 13:56:56.947181 [CBTSetCACLKResult] CA Dly = 33
4401 13:56:56.947262 CS Dly: 5 (0~36)
4402 13:56:56.947326 ==
4403 13:56:56.950371 Dram Type= 6, Freq= 0, CH_1, rank 1
4404 13:56:56.953864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 13:56:56.953945 ==
4406 13:56:56.960300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4407 13:56:56.967306 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4408 13:56:56.970276 [CA 0] Center 35 (5~66) winsize 62
4409 13:56:56.974081 [CA 1] Center 36 (6~66) winsize 61
4410 13:56:56.977355 [CA 2] Center 34 (3~65) winsize 63
4411 13:56:56.980945 [CA 3] Center 34 (3~65) winsize 63
4412 13:56:56.983970 [CA 4] Center 34 (4~65) winsize 62
4413 13:56:56.986904 [CA 5] Center 33 (3~64) winsize 62
4414 13:56:56.986985
4415 13:56:56.990661 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4416 13:56:56.990732
4417 13:56:56.994168 [CATrainingPosCal] consider 2 rank data
4418 13:56:56.997051 u2DelayCellTimex100 = 270/100 ps
4419 13:56:57.000604 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4420 13:56:57.003839 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4421 13:56:57.007282 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 13:56:57.010593 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4423 13:56:57.013655 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 13:56:57.020419 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 13:56:57.020521
4426 13:56:57.023727 CA PerBit enable=1, Macro0, CA PI delay=33
4427 13:56:57.023830
4428 13:56:57.027401 [CBTSetCACLKResult] CA Dly = 33
4429 13:56:57.027482 CS Dly: 5 (0~36)
4430 13:56:57.027572
4431 13:56:57.030719 ----->DramcWriteLeveling(PI) begin...
4432 13:56:57.030840 ==
4433 13:56:57.033631 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 13:56:57.036972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 13:56:57.040585 ==
4436 13:56:57.040681 Write leveling (Byte 0): 30 => 30
4437 13:56:57.043973 Write leveling (Byte 1): 30 => 30
4438 13:56:57.047373 DramcWriteLeveling(PI) end<-----
4439 13:56:57.047472
4440 13:56:57.047563 ==
4441 13:56:57.050767 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 13:56:57.057402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 13:56:57.057515 ==
4444 13:56:57.057607 [Gating] SW mode calibration
4445 13:56:57.067111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4446 13:56:57.070785 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4447 13:56:57.074118 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4448 13:56:57.080657 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 13:56:57.083773 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4450 13:56:57.087540 0 9 12 | B1->B0 | 3232 3333 | 1 1 | (1 0) (1 0)
4451 13:56:57.094767 0 9 16 | B1->B0 | 2828 2929 | 1 0 | (1 0) (1 0)
4452 13:56:57.097731 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 13:56:57.100931 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 13:56:57.107529 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 13:56:57.110858 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 13:56:57.114108 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 13:56:57.120514 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 13:56:57.123789 0 10 12 | B1->B0 | 2626 2929 | 1 1 | (0 0) (0 0)
4459 13:56:57.127438 0 10 16 | B1->B0 | 3c3c 4242 | 1 0 | (0 0) (0 0)
4460 13:56:57.133721 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 13:56:57.137104 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 13:56:57.140466 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 13:56:57.147116 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 13:56:57.150352 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 13:56:57.153822 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 13:56:57.160443 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 13:56:57.164008 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4468 13:56:57.167452 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 13:56:57.173937 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 13:56:57.176812 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 13:56:57.180644 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 13:56:57.183668 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 13:56:57.190332 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 13:56:57.194076 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 13:56:57.197308 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 13:56:57.203790 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 13:56:57.206957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 13:56:57.210467 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 13:56:57.217067 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 13:56:57.220308 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 13:56:57.224027 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:56:57.230330 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 13:56:57.234139 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 13:56:57.237111 Total UI for P1: 0, mck2ui 16
4485 13:56:57.240786 best dqsien dly found for B0: ( 0, 13, 14)
4486 13:56:57.244108 Total UI for P1: 0, mck2ui 16
4487 13:56:57.247486 best dqsien dly found for B1: ( 0, 13, 14)
4488 13:56:57.250749 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4489 13:56:57.254075 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4490 13:56:57.254176
4491 13:56:57.257378 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4492 13:56:57.260621 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4493 13:56:57.264090 [Gating] SW calibration Done
4494 13:56:57.264164 ==
4495 13:56:57.267751 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 13:56:57.271057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 13:56:57.271138 ==
4498 13:56:57.274164 RX Vref Scan: 0
4499 13:56:57.274269
4500 13:56:57.277661 RX Vref 0 -> 0, step: 1
4501 13:56:57.277746
4502 13:56:57.277820 RX Delay -230 -> 252, step: 16
4503 13:56:57.284236 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4504 13:56:57.287388 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4505 13:56:57.290341 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4506 13:56:57.293805 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4507 13:56:57.300788 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4508 13:56:57.303893 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4509 13:56:57.307653 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4510 13:56:57.310864 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4511 13:56:57.314456 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4512 13:56:57.321315 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4513 13:56:57.324474 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4514 13:56:57.327880 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4515 13:56:57.330806 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4516 13:56:57.337654 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4517 13:56:57.340859 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4518 13:56:57.344058 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4519 13:56:57.344138 ==
4520 13:56:57.347664 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 13:56:57.350726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 13:56:57.350835 ==
4523 13:56:57.354722 DQS Delay:
4524 13:56:57.354801 DQS0 = 0, DQS1 = 0
4525 13:56:57.357681 DQM Delay:
4526 13:56:57.357806 DQM0 = 44, DQM1 = 36
4527 13:56:57.357887 DQ Delay:
4528 13:56:57.360546 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4529 13:56:57.364078 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4530 13:56:57.367578 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4531 13:56:57.371030 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4532 13:56:57.371132
4533 13:56:57.371216
4534 13:56:57.373890 ==
4535 13:56:57.373970 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 13:56:57.380590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 13:56:57.380699 ==
4538 13:56:57.380797
4539 13:56:57.380892
4540 13:56:57.384117 TX Vref Scan disable
4541 13:56:57.384219 == TX Byte 0 ==
4542 13:56:57.387214 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4543 13:56:57.394129 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4544 13:56:57.394211 == TX Byte 1 ==
4545 13:56:57.397607 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 13:56:57.404417 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 13:56:57.404495 ==
4548 13:56:57.407251 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 13:56:57.410830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 13:56:57.410905 ==
4551 13:56:57.410971
4552 13:56:57.411037
4553 13:56:57.414034 TX Vref Scan disable
4554 13:56:57.417776 == TX Byte 0 ==
4555 13:56:57.420570 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4556 13:56:57.423873 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4557 13:56:57.427921 == TX Byte 1 ==
4558 13:56:57.430893 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4559 13:56:57.434815 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4560 13:56:57.434901
4561 13:56:57.437955 [DATLAT]
4562 13:56:57.438060 Freq=600, CH1 RK0
4563 13:56:57.438148
4564 13:56:57.440867 DATLAT Default: 0x9
4565 13:56:57.440940 0, 0xFFFF, sum = 0
4566 13:56:57.444347 1, 0xFFFF, sum = 0
4567 13:56:57.444419 2, 0xFFFF, sum = 0
4568 13:56:57.447399 3, 0xFFFF, sum = 0
4569 13:56:57.447475 4, 0xFFFF, sum = 0
4570 13:56:57.450850 5, 0xFFFF, sum = 0
4571 13:56:57.450919 6, 0xFFFF, sum = 0
4572 13:56:57.454374 7, 0xFFFF, sum = 0
4573 13:56:57.454534 8, 0x0, sum = 1
4574 13:56:57.457340 9, 0x0, sum = 2
4575 13:56:57.457443 10, 0x0, sum = 3
4576 13:56:57.461166 11, 0x0, sum = 4
4577 13:56:57.461266 best_step = 9
4578 13:56:57.461338
4579 13:56:57.461398 ==
4580 13:56:57.464271 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 13:56:57.467230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 13:56:57.467325 ==
4583 13:56:57.470750 RX Vref Scan: 1
4584 13:56:57.470844
4585 13:56:57.474189 RX Vref 0 -> 0, step: 1
4586 13:56:57.474286
4587 13:56:57.474375 RX Delay -179 -> 252, step: 8
4588 13:56:57.474478
4589 13:56:57.477239 Set Vref, RX VrefLevel [Byte0]: 60
4590 13:56:57.480992 [Byte1]: 51
4591 13:56:57.485075
4592 13:56:57.485181 Final RX Vref Byte 0 = 60 to rank0
4593 13:56:57.488752 Final RX Vref Byte 1 = 51 to rank0
4594 13:56:57.491799 Final RX Vref Byte 0 = 60 to rank1
4595 13:56:57.495372 Final RX Vref Byte 1 = 51 to rank1==
4596 13:56:57.498566 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 13:56:57.502161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 13:56:57.505376 ==
4599 13:56:57.505456 DQS Delay:
4600 13:56:57.505520 DQS0 = 0, DQS1 = 0
4601 13:56:57.508593 DQM Delay:
4602 13:56:57.508674 DQM0 = 40, DQM1 = 33
4603 13:56:57.512011 DQ Delay:
4604 13:56:57.515478 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4605 13:56:57.515592 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4606 13:56:57.518851 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4607 13:56:57.521998 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4608 13:56:57.525460
4609 13:56:57.525559
4610 13:56:57.531863 [DQSOSCAuto] RK0, (LSB)MR18= 0x4309, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4611 13:56:57.535978 CH1 RK0: MR19=808, MR18=4309
4612 13:56:57.542375 CH1_RK0: MR19=0x808, MR18=0x4309, DQSOSC=397, MR23=63, INC=166, DEC=110
4613 13:56:57.542495
4614 13:56:57.545146 ----->DramcWriteLeveling(PI) begin...
4615 13:56:57.545221 ==
4616 13:56:57.548944 Dram Type= 6, Freq= 0, CH_1, rank 1
4617 13:56:57.551959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 13:56:57.552040 ==
4619 13:56:57.555553 Write leveling (Byte 0): 30 => 30
4620 13:56:57.558374 Write leveling (Byte 1): 30 => 30
4621 13:56:57.562137 DramcWriteLeveling(PI) end<-----
4622 13:56:57.562215
4623 13:56:57.562277 ==
4624 13:56:57.565272 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 13:56:57.568616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 13:56:57.568689 ==
4627 13:56:57.571940 [Gating] SW mode calibration
4628 13:56:57.578821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4629 13:56:57.585417 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4630 13:56:57.588558 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4631 13:56:57.591952 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 13:56:57.598327 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4633 13:56:57.602055 0 9 12 | B1->B0 | 3232 2e2e | 0 0 | (1 1) (1 1)
4634 13:56:57.605385 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4635 13:56:57.612143 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 13:56:57.615378 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4637 13:56:57.618668 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 13:56:57.625570 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 13:56:57.628652 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 13:56:57.632111 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 13:56:57.638966 0 10 12 | B1->B0 | 2f2f 3d3d | 1 0 | (0 0) (0 0)
4642 13:56:57.642568 0 10 16 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
4643 13:56:57.645430 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 13:56:57.648719 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 13:56:57.655275 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 13:56:57.658684 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 13:56:57.662760 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 13:56:57.669058 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 13:56:57.672128 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4650 13:56:57.675424 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 13:56:57.682195 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 13:56:57.685810 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 13:56:57.688882 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 13:56:57.695443 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 13:56:57.698971 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 13:56:57.701984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 13:56:57.708982 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 13:56:57.712092 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 13:56:57.715613 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 13:56:57.721818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 13:56:57.725086 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 13:56:57.728380 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 13:56:57.734952 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 13:56:57.738348 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 13:56:57.741921 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4666 13:56:57.748696 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 13:56:57.748799 Total UI for P1: 0, mck2ui 16
4668 13:56:57.751927 best dqsien dly found for B0: ( 0, 13, 12)
4669 13:56:57.755262 Total UI for P1: 0, mck2ui 16
4670 13:56:57.758708 best dqsien dly found for B1: ( 0, 13, 14)
4671 13:56:57.761790 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4672 13:56:57.768601 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4673 13:56:57.768689
4674 13:56:57.772148 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4675 13:56:57.775340 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4676 13:56:57.779013 [Gating] SW calibration Done
4677 13:56:57.779120 ==
4678 13:56:57.782061 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 13:56:57.785738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 13:56:57.785833 ==
4681 13:56:57.785932 RX Vref Scan: 0
4682 13:56:57.789102
4683 13:56:57.789198 RX Vref 0 -> 0, step: 1
4684 13:56:57.789293
4685 13:56:57.791954 RX Delay -230 -> 252, step: 16
4686 13:56:57.795076 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4687 13:56:57.801773 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4688 13:56:57.805196 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4689 13:56:57.808762 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4690 13:56:57.812170 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4691 13:56:57.815087 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4692 13:56:57.822154 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4693 13:56:57.825240 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4694 13:56:57.828799 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4695 13:56:57.831977 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4696 13:56:57.835409 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4697 13:56:57.842097 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4698 13:56:57.845545 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4699 13:56:57.849007 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4700 13:56:57.852104 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4701 13:56:57.858524 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4702 13:56:57.858617 ==
4703 13:56:57.862275 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 13:56:57.865193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 13:56:57.865289 ==
4706 13:56:57.865380 DQS Delay:
4707 13:56:57.868688 DQS0 = 0, DQS1 = 0
4708 13:56:57.868790 DQM Delay:
4709 13:56:57.872533 DQM0 = 38, DQM1 = 36
4710 13:56:57.872632 DQ Delay:
4711 13:56:57.875443 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4712 13:56:57.879140 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4713 13:56:57.882008 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4714 13:56:57.885373 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4715 13:56:57.885477
4716 13:56:57.885572
4717 13:56:57.885656 ==
4718 13:56:57.888825 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 13:56:57.892031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 13:56:57.892128 ==
4721 13:56:57.892217
4722 13:56:57.895801
4723 13:56:57.895897 TX Vref Scan disable
4724 13:56:57.899182 == TX Byte 0 ==
4725 13:56:57.902037 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 13:56:57.906799 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 13:56:57.908646 == TX Byte 1 ==
4728 13:56:57.912239 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4729 13:56:57.915179 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4730 13:56:57.915252 ==
4731 13:56:57.918780 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 13:56:57.925576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 13:56:57.925650 ==
4734 13:56:57.925711
4735 13:56:57.925780
4736 13:56:57.925835 TX Vref Scan disable
4737 13:56:57.930065 == TX Byte 0 ==
4738 13:56:57.933071 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4739 13:56:57.936667 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4740 13:56:57.939868 == TX Byte 1 ==
4741 13:56:57.943187 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4742 13:56:57.946871 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4743 13:56:57.949935
4744 13:56:57.950030 [DATLAT]
4745 13:56:57.950117 Freq=600, CH1 RK1
4746 13:56:57.950234
4747 13:56:57.953124 DATLAT Default: 0x9
4748 13:56:57.953222 0, 0xFFFF, sum = 0
4749 13:56:57.956731 1, 0xFFFF, sum = 0
4750 13:56:57.956834 2, 0xFFFF, sum = 0
4751 13:56:57.960001 3, 0xFFFF, sum = 0
4752 13:56:57.960102 4, 0xFFFF, sum = 0
4753 13:56:57.963275 5, 0xFFFF, sum = 0
4754 13:56:57.963381 6, 0xFFFF, sum = 0
4755 13:56:57.966719 7, 0xFFFF, sum = 0
4756 13:56:57.966794 8, 0x0, sum = 1
4757 13:56:57.970201 9, 0x0, sum = 2
4758 13:56:57.970301 10, 0x0, sum = 3
4759 13:56:57.973122 11, 0x0, sum = 4
4760 13:56:57.973230 best_step = 9
4761 13:56:57.973321
4762 13:56:57.973407 ==
4763 13:56:57.976749 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 13:56:57.980373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 13:56:57.983529 ==
4766 13:56:57.983625 RX Vref Scan: 0
4767 13:56:57.983714
4768 13:56:57.986871 RX Vref 0 -> 0, step: 1
4769 13:56:57.986972
4770 13:56:57.990315 RX Delay -179 -> 252, step: 8
4771 13:56:57.993830 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4772 13:56:57.996960 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4773 13:56:58.003283 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4774 13:56:58.006791 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4775 13:56:58.010084 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4776 13:56:58.013549 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4777 13:56:58.020064 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4778 13:56:58.023691 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4779 13:56:58.026600 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4780 13:56:58.030204 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4781 13:56:58.033680 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4782 13:56:58.040074 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4783 13:56:58.043884 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4784 13:56:58.046545 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4785 13:56:58.049843 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4786 13:56:58.057019 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4787 13:56:58.057096 ==
4788 13:56:58.059818 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 13:56:58.063241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 13:56:58.063313 ==
4791 13:56:58.063374 DQS Delay:
4792 13:56:58.066619 DQS0 = 0, DQS1 = 0
4793 13:56:58.066715 DQM Delay:
4794 13:56:58.070212 DQM0 = 39, DQM1 = 33
4795 13:56:58.070320 DQ Delay:
4796 13:56:58.073591 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4797 13:56:58.076807 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4798 13:56:58.080209 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4799 13:56:58.083160 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4800 13:56:58.083265
4801 13:56:58.083355
4802 13:56:58.090306 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
4803 13:56:58.093485 CH1 RK1: MR19=808, MR18=3A49
4804 13:56:58.100812 CH1_RK1: MR19=0x808, MR18=0x3A49, DQSOSC=396, MR23=63, INC=167, DEC=111
4805 13:56:58.103605 [RxdqsGatingPostProcess] freq 600
4806 13:56:58.110422 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4807 13:56:58.110513 Pre-setting of DQS Precalculation
4808 13:56:58.117245 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4809 13:56:58.123953 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4810 13:56:58.130353 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4811 13:56:58.130469
4812 13:56:58.130533
4813 13:56:58.134219 [Calibration Summary] 1200 Mbps
4814 13:56:58.137025 CH 0, Rank 0
4815 13:56:58.137103 SW Impedance : PASS
4816 13:56:58.140595 DUTY Scan : NO K
4817 13:56:58.140674 ZQ Calibration : PASS
4818 13:56:58.143603 Jitter Meter : NO K
4819 13:56:58.147025 CBT Training : PASS
4820 13:56:58.147109 Write leveling : PASS
4821 13:56:58.150262 RX DQS gating : PASS
4822 13:56:58.153578 RX DQ/DQS(RDDQC) : PASS
4823 13:56:58.153669 TX DQ/DQS : PASS
4824 13:56:58.156934 RX DATLAT : PASS
4825 13:56:58.160023 RX DQ/DQS(Engine): PASS
4826 13:56:58.160102 TX OE : NO K
4827 13:56:58.163354 All Pass.
4828 13:56:58.163446
4829 13:56:58.163510 CH 0, Rank 1
4830 13:56:58.167097 SW Impedance : PASS
4831 13:56:58.167177 DUTY Scan : NO K
4832 13:56:58.170056 ZQ Calibration : PASS
4833 13:56:58.173416 Jitter Meter : NO K
4834 13:56:58.173495 CBT Training : PASS
4835 13:56:58.176798 Write leveling : PASS
4836 13:56:58.180076 RX DQS gating : PASS
4837 13:56:58.180156 RX DQ/DQS(RDDQC) : PASS
4838 13:56:58.183427 TX DQ/DQS : PASS
4839 13:56:58.186353 RX DATLAT : PASS
4840 13:56:58.186481 RX DQ/DQS(Engine): PASS
4841 13:56:58.190113 TX OE : NO K
4842 13:56:58.190219 All Pass.
4843 13:56:58.190310
4844 13:56:58.192877 CH 1, Rank 0
4845 13:56:58.192957 SW Impedance : PASS
4846 13:56:58.196708 DUTY Scan : NO K
4847 13:56:58.199948 ZQ Calibration : PASS
4848 13:56:58.200032 Jitter Meter : NO K
4849 13:56:58.203116 CBT Training : PASS
4850 13:56:58.203203 Write leveling : PASS
4851 13:56:58.206753 RX DQS gating : PASS
4852 13:56:58.209529 RX DQ/DQS(RDDQC) : PASS
4853 13:56:58.209626 TX DQ/DQS : PASS
4854 13:56:58.213151 RX DATLAT : PASS
4855 13:56:58.216518 RX DQ/DQS(Engine): PASS
4856 13:56:58.216587 TX OE : NO K
4857 13:56:58.219606 All Pass.
4858 13:56:58.219688
4859 13:56:58.219757 CH 1, Rank 1
4860 13:56:58.223271 SW Impedance : PASS
4861 13:56:58.223379 DUTY Scan : NO K
4862 13:56:58.226751 ZQ Calibration : PASS
4863 13:56:58.229734 Jitter Meter : NO K
4864 13:56:58.229824 CBT Training : PASS
4865 13:56:58.233025 Write leveling : PASS
4866 13:56:58.236396 RX DQS gating : PASS
4867 13:56:58.236468 RX DQ/DQS(RDDQC) : PASS
4868 13:56:58.239834 TX DQ/DQS : PASS
4869 13:56:58.242935 RX DATLAT : PASS
4870 13:56:58.243007 RX DQ/DQS(Engine): PASS
4871 13:56:58.246358 TX OE : NO K
4872 13:56:58.246476 All Pass.
4873 13:56:58.246552
4874 13:56:58.249775 DramC Write-DBI off
4875 13:56:58.252743 PER_BANK_REFRESH: Hybrid Mode
4876 13:56:58.252820 TX_TRACKING: ON
4877 13:56:58.263233 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4878 13:56:58.266269 [FAST_K] Save calibration result to emmc
4879 13:56:58.269583 dramc_set_vcore_voltage set vcore to 662500
4880 13:56:58.269679 Read voltage for 933, 3
4881 13:56:58.272902 Vio18 = 0
4882 13:56:58.272969 Vcore = 662500
4883 13:56:58.273027 Vdram = 0
4884 13:56:58.276778 Vddq = 0
4885 13:56:58.276858 Vmddr = 0
4886 13:56:58.279512 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4887 13:56:58.286687 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4888 13:56:58.289605 MEM_TYPE=3, freq_sel=17
4889 13:56:58.292933 sv_algorithm_assistance_LP4_1600
4890 13:56:58.296118 ============ PULL DRAM RESETB DOWN ============
4891 13:56:58.300066 ========== PULL DRAM RESETB DOWN end =========
4892 13:56:58.306506 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4893 13:56:58.309723 ===================================
4894 13:56:58.309827 LPDDR4 DRAM CONFIGURATION
4895 13:56:58.313036 ===================================
4896 13:56:58.316589 EX_ROW_EN[0] = 0x0
4897 13:56:58.316686 EX_ROW_EN[1] = 0x0
4898 13:56:58.319598 LP4Y_EN = 0x0
4899 13:56:58.319678 WORK_FSP = 0x0
4900 13:56:58.322919 WL = 0x3
4901 13:56:58.322991 RL = 0x3
4902 13:56:58.326339 BL = 0x2
4903 13:56:58.329920 RPST = 0x0
4904 13:56:58.330016 RD_PRE = 0x0
4905 13:56:58.333078 WR_PRE = 0x1
4906 13:56:58.333148 WR_PST = 0x0
4907 13:56:58.336822 DBI_WR = 0x0
4908 13:56:58.336925 DBI_RD = 0x0
4909 13:56:58.340136 OTF = 0x1
4910 13:56:58.343252 ===================================
4911 13:56:58.346596 ===================================
4912 13:56:58.346675 ANA top config
4913 13:56:58.349992 ===================================
4914 13:56:58.353168 DLL_ASYNC_EN = 0
4915 13:56:58.356146 ALL_SLAVE_EN = 1
4916 13:56:58.356220 NEW_RANK_MODE = 1
4917 13:56:58.360047 DLL_IDLE_MODE = 1
4918 13:56:58.362951 LP45_APHY_COMB_EN = 1
4919 13:56:58.366288 TX_ODT_DIS = 1
4920 13:56:58.366384 NEW_8X_MODE = 1
4921 13:56:58.369873 ===================================
4922 13:56:58.372915 ===================================
4923 13:56:58.376478 data_rate = 1866
4924 13:56:58.379610 CKR = 1
4925 13:56:58.382926 DQ_P2S_RATIO = 8
4926 13:56:58.386713 ===================================
4927 13:56:58.389943 CA_P2S_RATIO = 8
4928 13:56:58.393646 DQ_CA_OPEN = 0
4929 13:56:58.393727 DQ_SEMI_OPEN = 0
4930 13:56:58.396589 CA_SEMI_OPEN = 0
4931 13:56:58.399889 CA_FULL_RATE = 0
4932 13:56:58.403311 DQ_CKDIV4_EN = 1
4933 13:56:58.406639 CA_CKDIV4_EN = 1
4934 13:56:58.409694 CA_PREDIV_EN = 0
4935 13:56:58.409827 PH8_DLY = 0
4936 13:56:58.413185 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4937 13:56:58.416582 DQ_AAMCK_DIV = 4
4938 13:56:58.420326 CA_AAMCK_DIV = 4
4939 13:56:58.423553 CA_ADMCK_DIV = 4
4940 13:56:58.423626 DQ_TRACK_CA_EN = 0
4941 13:56:58.427008 CA_PICK = 933
4942 13:56:58.429983 CA_MCKIO = 933
4943 13:56:58.433256 MCKIO_SEMI = 0
4944 13:56:58.436869 PLL_FREQ = 3732
4945 13:56:58.439801 DQ_UI_PI_RATIO = 32
4946 13:56:58.443169 CA_UI_PI_RATIO = 0
4947 13:56:58.446710 ===================================
4948 13:56:58.449749 ===================================
4949 13:56:58.449819 memory_type:LPDDR4
4950 13:56:58.453825 GP_NUM : 10
4951 13:56:58.456407 SRAM_EN : 1
4952 13:56:58.456477 MD32_EN : 0
4953 13:56:58.460207 ===================================
4954 13:56:58.463755 [ANA_INIT] >>>>>>>>>>>>>>
4955 13:56:58.467095 <<<<<< [CONFIGURE PHASE]: ANA_TX
4956 13:56:58.470037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4957 13:56:58.473291 ===================================
4958 13:56:58.476672 data_rate = 1866,PCW = 0X8f00
4959 13:56:58.476769 ===================================
4960 13:56:58.483312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4961 13:56:58.487092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4962 13:56:58.493111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 13:56:58.496617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4964 13:56:58.500366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4965 13:56:58.503867 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4966 13:56:58.506728 [ANA_INIT] flow start
4967 13:56:58.510034 [ANA_INIT] PLL >>>>>>>>
4968 13:56:58.510132 [ANA_INIT] PLL <<<<<<<<
4969 13:56:58.513540 [ANA_INIT] MIDPI >>>>>>>>
4970 13:56:58.516612 [ANA_INIT] MIDPI <<<<<<<<
4971 13:56:58.516713 [ANA_INIT] DLL >>>>>>>>
4972 13:56:58.520018 [ANA_INIT] flow end
4973 13:56:58.523471 ============ LP4 DIFF to SE enter ============
4974 13:56:58.526512 ============ LP4 DIFF to SE exit ============
4975 13:56:58.530172 [ANA_INIT] <<<<<<<<<<<<<
4976 13:56:58.533277 [Flow] Enable top DCM control >>>>>
4977 13:56:58.537114 [Flow] Enable top DCM control <<<<<
4978 13:56:58.540304 Enable DLL master slave shuffle
4979 13:56:58.546889 ==============================================================
4980 13:56:58.546966 Gating Mode config
4981 13:56:58.553485 ==============================================================
4982 13:56:58.553557 Config description:
4983 13:56:58.563413 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4984 13:56:58.570743 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4985 13:56:58.576561 SELPH_MODE 0: By rank 1: By Phase
4986 13:56:58.580242 ==============================================================
4987 13:56:58.583919 GAT_TRACK_EN = 1
4988 13:56:58.586735 RX_GATING_MODE = 2
4989 13:56:58.589650 RX_GATING_TRACK_MODE = 2
4990 13:56:58.593289 SELPH_MODE = 1
4991 13:56:58.597017 PICG_EARLY_EN = 1
4992 13:56:58.599673 VALID_LAT_VALUE = 1
4993 13:56:58.603399 ==============================================================
4994 13:56:58.606548 Enter into Gating configuration >>>>
4995 13:56:58.609773 Exit from Gating configuration <<<<
4996 13:56:58.613375 Enter into DVFS_PRE_config >>>>>
4997 13:56:58.626975 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4998 13:56:58.630094 Exit from DVFS_PRE_config <<<<<
4999 13:56:58.633090 Enter into PICG configuration >>>>
5000 13:56:58.636622 Exit from PICG configuration <<<<
5001 13:56:58.636728 [RX_INPUT] configuration >>>>>
5002 13:56:58.640210 [RX_INPUT] configuration <<<<<
5003 13:56:58.647124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5004 13:56:58.649558 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5005 13:56:58.656399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5006 13:56:58.663167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5007 13:56:58.669702 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5008 13:56:58.676211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5009 13:56:58.680102 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5010 13:56:58.683427 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5011 13:56:58.686444 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5012 13:56:58.693641 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5013 13:56:58.696637 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5014 13:56:58.699997 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 13:56:58.703431 ===================================
5016 13:56:58.706554 LPDDR4 DRAM CONFIGURATION
5017 13:56:58.710256 ===================================
5018 13:56:58.713497 EX_ROW_EN[0] = 0x0
5019 13:56:58.713609 EX_ROW_EN[1] = 0x0
5020 13:56:58.716832 LP4Y_EN = 0x0
5021 13:56:58.716946 WORK_FSP = 0x0
5022 13:56:58.720045 WL = 0x3
5023 13:56:58.720154 RL = 0x3
5024 13:56:58.723218 BL = 0x2
5025 13:56:58.723335 RPST = 0x0
5026 13:56:58.727163 RD_PRE = 0x0
5027 13:56:58.727277 WR_PRE = 0x1
5028 13:56:58.730232 WR_PST = 0x0
5029 13:56:58.730343 DBI_WR = 0x0
5030 13:56:58.733481 DBI_RD = 0x0
5031 13:56:58.733585 OTF = 0x1
5032 13:56:58.736504 ===================================
5033 13:56:58.739962 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5034 13:56:58.746527 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5035 13:56:58.749924 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 13:56:58.753223 ===================================
5037 13:56:58.756823 LPDDR4 DRAM CONFIGURATION
5038 13:56:58.760371 ===================================
5039 13:56:58.760448 EX_ROW_EN[0] = 0x10
5040 13:56:58.763263 EX_ROW_EN[1] = 0x0
5041 13:56:58.766579 LP4Y_EN = 0x0
5042 13:56:58.766666 WORK_FSP = 0x0
5043 13:56:58.770234 WL = 0x3
5044 13:56:58.770329 RL = 0x3
5045 13:56:58.773338 BL = 0x2
5046 13:56:58.773423 RPST = 0x0
5047 13:56:58.776846 RD_PRE = 0x0
5048 13:56:58.776952 WR_PRE = 0x1
5049 13:56:58.779872 WR_PST = 0x0
5050 13:56:58.779980 DBI_WR = 0x0
5051 13:56:58.783485 DBI_RD = 0x0
5052 13:56:58.783565 OTF = 0x1
5053 13:56:58.787018 ===================================
5054 13:56:58.793546 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5055 13:56:58.796925 nWR fixed to 30
5056 13:56:58.800316 [ModeRegInit_LP4] CH0 RK0
5057 13:56:58.800421 [ModeRegInit_LP4] CH0 RK1
5058 13:56:58.803998 [ModeRegInit_LP4] CH1 RK0
5059 13:56:58.807218 [ModeRegInit_LP4] CH1 RK1
5060 13:56:58.807298 match AC timing 9
5061 13:56:58.813903 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5062 13:56:58.817120 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5063 13:56:58.820479 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5064 13:56:58.827399 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5065 13:56:58.830658 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5066 13:56:58.830739 ==
5067 13:56:58.833820 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 13:56:58.837162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 13:56:58.837267 ==
5070 13:56:58.843920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 13:56:58.850542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5072 13:56:58.853926 [CA 0] Center 38 (8~69) winsize 62
5073 13:56:58.857029 [CA 1] Center 38 (7~69) winsize 63
5074 13:56:58.860901 [CA 2] Center 35 (5~66) winsize 62
5075 13:56:58.863939 [CA 3] Center 35 (5~65) winsize 61
5076 13:56:58.867209 [CA 4] Center 34 (4~65) winsize 62
5077 13:56:58.870483 [CA 5] Center 34 (4~64) winsize 61
5078 13:56:58.870564
5079 13:56:58.873636 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5080 13:56:58.873717
5081 13:56:58.876987 [CATrainingPosCal] consider 1 rank data
5082 13:56:58.880979 u2DelayCellTimex100 = 270/100 ps
5083 13:56:58.883784 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 13:56:58.887392 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5085 13:56:58.891097 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5086 13:56:58.894058 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5087 13:56:58.897245 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5088 13:56:58.900895 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5089 13:56:58.900975
5090 13:56:58.907638 CA PerBit enable=1, Macro0, CA PI delay=34
5091 13:56:58.907719
5092 13:56:58.907782 [CBTSetCACLKResult] CA Dly = 34
5093 13:56:58.910638 CS Dly: 6 (0~37)
5094 13:56:58.910743 ==
5095 13:56:58.913555 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 13:56:58.917070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 13:56:58.917176 ==
5098 13:56:58.923589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 13:56:58.930436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5100 13:56:58.933838 [CA 0] Center 38 (8~69) winsize 62
5101 13:56:58.937465 [CA 1] Center 38 (7~69) winsize 63
5102 13:56:58.940377 [CA 2] Center 35 (5~66) winsize 62
5103 13:56:58.943402 [CA 3] Center 35 (4~66) winsize 63
5104 13:56:58.946951 [CA 4] Center 33 (3~64) winsize 62
5105 13:56:58.950408 [CA 5] Center 33 (3~64) winsize 62
5106 13:56:58.950514
5107 13:56:58.953836 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5108 13:56:58.953917
5109 13:56:58.956787 [CATrainingPosCal] consider 2 rank data
5110 13:56:58.959996 u2DelayCellTimex100 = 270/100 ps
5111 13:56:58.963852 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5112 13:56:58.966748 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5113 13:56:58.970568 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5114 13:56:58.973841 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5115 13:56:58.977303 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5116 13:56:58.980742 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5117 13:56:58.980815
5118 13:56:58.987181 CA PerBit enable=1, Macro0, CA PI delay=34
5119 13:56:58.987262
5120 13:56:58.987325 [CBTSetCACLKResult] CA Dly = 34
5121 13:56:58.989970 CS Dly: 7 (0~39)
5122 13:56:58.990064
5123 13:56:58.993470 ----->DramcWriteLeveling(PI) begin...
5124 13:56:58.993546 ==
5125 13:56:58.997277 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 13:56:58.999909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 13:56:58.999988 ==
5128 13:56:59.003620 Write leveling (Byte 0): 28 => 28
5129 13:56:59.007104 Write leveling (Byte 1): 27 => 27
5130 13:56:59.010170 DramcWriteLeveling(PI) end<-----
5131 13:56:59.010275
5132 13:56:59.010365 ==
5133 13:56:59.013565 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 13:56:59.016899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 13:56:59.019920 ==
5136 13:56:59.019997 [Gating] SW mode calibration
5137 13:56:59.030275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5138 13:56:59.033861 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5139 13:56:59.036924 0 14 0 | B1->B0 | 2323 2828 | 1 0 | (1 1) (0 0)
5140 13:56:59.043415 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
5141 13:56:59.047511 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 13:56:59.049964 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 13:56:59.057179 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 13:56:59.060327 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 13:56:59.063461 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 13:56:59.070317 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5147 13:56:59.073517 0 15 0 | B1->B0 | 3131 2b2b | 1 0 | (1 0) (0 0)
5148 13:56:59.077311 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5149 13:56:59.083685 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 13:56:59.087386 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 13:56:59.090238 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 13:56:59.093523 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 13:56:59.100360 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 13:56:59.103798 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 13:56:59.106882 1 0 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5156 13:56:59.113348 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 13:56:59.117084 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 13:56:59.120283 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 13:56:59.127132 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 13:56:59.130350 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 13:56:59.133813 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 13:56:59.140255 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 13:56:59.143485 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5164 13:56:59.147226 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5165 13:56:59.154225 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 13:56:59.156895 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 13:56:59.160190 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 13:56:59.166859 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 13:56:59.170285 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 13:56:59.173826 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 13:56:59.180488 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 13:56:59.183816 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 13:56:59.187232 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 13:56:59.190597 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 13:56:59.197755 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 13:56:59.200586 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 13:56:59.204440 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 13:56:59.210773 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 13:56:59.213885 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5180 13:56:59.217537 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5181 13:56:59.224084 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 13:56:59.224166 Total UI for P1: 0, mck2ui 16
5183 13:56:59.230607 best dqsien dly found for B0: ( 1, 3, 2)
5184 13:56:59.230694 Total UI for P1: 0, mck2ui 16
5185 13:56:59.234022 best dqsien dly found for B1: ( 1, 3, 4)
5186 13:56:59.240655 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5187 13:56:59.244068 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5188 13:56:59.244148
5189 13:56:59.247464 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5190 13:56:59.250423 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5191 13:56:59.253926 [Gating] SW calibration Done
5192 13:56:59.254031 ==
5193 13:56:59.257554 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 13:56:59.260400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 13:56:59.260497 ==
5196 13:56:59.260584 RX Vref Scan: 0
5197 13:56:59.263870
5198 13:56:59.263939 RX Vref 0 -> 0, step: 1
5199 13:56:59.263998
5200 13:56:59.267664 RX Delay -80 -> 252, step: 8
5201 13:56:59.270570 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5202 13:56:59.273855 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5203 13:56:59.277106 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5204 13:56:59.283751 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5205 13:56:59.287393 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5206 13:56:59.290421 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5207 13:56:59.293829 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5208 13:56:59.297612 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5209 13:56:59.300811 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5210 13:56:59.307473 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5211 13:56:59.310696 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5212 13:56:59.314150 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5213 13:56:59.317619 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5214 13:56:59.320621 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5215 13:56:59.327229 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5216 13:56:59.330934 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5217 13:56:59.331040 ==
5218 13:56:59.334389 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 13:56:59.337462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 13:56:59.337558 ==
5221 13:56:59.337673 DQS Delay:
5222 13:56:59.340677 DQS0 = 0, DQS1 = 0
5223 13:56:59.340783 DQM Delay:
5224 13:56:59.344613 DQM0 = 99, DQM1 = 87
5225 13:56:59.344693 DQ Delay:
5226 13:56:59.347061 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =91
5227 13:56:59.350607 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =103
5228 13:56:59.353626 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5229 13:56:59.357175 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5230 13:56:59.357255
5231 13:56:59.357321
5232 13:56:59.357387 ==
5233 13:56:59.360698 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 13:56:59.367227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 13:56:59.367333 ==
5236 13:56:59.367425
5237 13:56:59.367511
5238 13:56:59.367574 TX Vref Scan disable
5239 13:56:59.370736 == TX Byte 0 ==
5240 13:56:59.374058 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5241 13:56:59.380432 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5242 13:56:59.380539 == TX Byte 1 ==
5243 13:56:59.383949 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5244 13:56:59.390614 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5245 13:56:59.390695 ==
5246 13:56:59.393942 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 13:56:59.397604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 13:56:59.397685 ==
5249 13:56:59.397748
5250 13:56:59.397805
5251 13:56:59.400700 TX Vref Scan disable
5252 13:56:59.400806 == TX Byte 0 ==
5253 13:56:59.407474 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5254 13:56:59.410806 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5255 13:56:59.410887 == TX Byte 1 ==
5256 13:56:59.417414 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5257 13:56:59.420414 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5258 13:56:59.420495
5259 13:56:59.420561 [DATLAT]
5260 13:56:59.424554 Freq=933, CH0 RK0
5261 13:56:59.424634
5262 13:56:59.424696 DATLAT Default: 0xd
5263 13:56:59.427412 0, 0xFFFF, sum = 0
5264 13:56:59.427523 1, 0xFFFF, sum = 0
5265 13:56:59.430681 2, 0xFFFF, sum = 0
5266 13:56:59.430762 3, 0xFFFF, sum = 0
5267 13:56:59.434125 4, 0xFFFF, sum = 0
5268 13:56:59.434233 5, 0xFFFF, sum = 0
5269 13:56:59.437145 6, 0xFFFF, sum = 0
5270 13:56:59.437253 7, 0xFFFF, sum = 0
5271 13:56:59.440642 8, 0xFFFF, sum = 0
5272 13:56:59.444245 9, 0xFFFF, sum = 0
5273 13:56:59.444326 10, 0x0, sum = 1
5274 13:56:59.444390 11, 0x0, sum = 2
5275 13:56:59.447787 12, 0x0, sum = 3
5276 13:56:59.447868 13, 0x0, sum = 4
5277 13:56:59.451274 best_step = 11
5278 13:56:59.451354
5279 13:56:59.451417 ==
5280 13:56:59.454066 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 13:56:59.457477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 13:56:59.457583 ==
5283 13:56:59.460989 RX Vref Scan: 1
5284 13:56:59.461068
5285 13:56:59.461133 RX Vref 0 -> 0, step: 1
5286 13:56:59.461191
5287 13:56:59.463890 RX Delay -61 -> 252, step: 4
5288 13:56:59.463997
5289 13:56:59.467755 Set Vref, RX VrefLevel [Byte0]: 56
5290 13:56:59.470391 [Byte1]: 52
5291 13:56:59.474581
5292 13:56:59.474661 Final RX Vref Byte 0 = 56 to rank0
5293 13:56:59.477993 Final RX Vref Byte 1 = 52 to rank0
5294 13:56:59.484252 Final RX Vref Byte 0 = 56 to rank1
5295 13:56:59.484706 Final RX Vref Byte 1 = 52 to rank1==
5296 13:56:59.487762 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 13:56:59.491664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 13:56:59.494930 ==
5299 13:56:59.495017 DQS Delay:
5300 13:56:59.495083 DQS0 = 0, DQS1 = 0
5301 13:56:59.498300 DQM Delay:
5302 13:56:59.498379 DQM0 = 96, DQM1 = 88
5303 13:56:59.501288 DQ Delay:
5304 13:56:59.505028 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5305 13:56:59.507871 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5306 13:56:59.507970 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5307 13:56:59.514315 DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =98
5308 13:56:59.514424
5309 13:56:59.514489
5310 13:56:59.521671 [DQSOSCAuto] RK0, (LSB)MR18= 0x1803, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5311 13:56:59.524561 CH0 RK0: MR19=505, MR18=1803
5312 13:56:59.531792 CH0_RK0: MR19=0x505, MR18=0x1803, DQSOSC=414, MR23=63, INC=63, DEC=42
5313 13:56:59.531872
5314 13:56:59.534693 ----->DramcWriteLeveling(PI) begin...
5315 13:56:59.534773 ==
5316 13:56:59.538799 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 13:56:59.541354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 13:56:59.541453 ==
5319 13:56:59.544709 Write leveling (Byte 0): 31 => 31
5320 13:56:59.548094 Write leveling (Byte 1): 27 => 27
5321 13:56:59.551194 DramcWriteLeveling(PI) end<-----
5322 13:56:59.551268
5323 13:56:59.551328 ==
5324 13:56:59.554754 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 13:56:59.558322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 13:56:59.558454 ==
5327 13:56:59.561344 [Gating] SW mode calibration
5328 13:56:59.567902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5329 13:56:59.574883 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5330 13:56:59.578122 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5331 13:56:59.581679 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5332 13:56:59.588093 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 13:56:59.591675 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 13:56:59.595222 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 13:56:59.601438 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 13:56:59.604766 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5337 13:56:59.608212 0 14 28 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0)
5338 13:56:59.614958 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5339 13:56:59.618249 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 13:56:59.621372 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 13:56:59.628201 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 13:56:59.631553 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 13:56:59.635158 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 13:56:59.638287 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 13:56:59.645393 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5346 13:56:59.648751 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5347 13:56:59.651579 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 13:56:59.658874 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 13:56:59.661999 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 13:56:59.665137 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 13:56:59.672340 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 13:56:59.675227 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5353 13:56:59.678598 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5354 13:56:59.684817 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5355 13:56:59.688160 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5356 13:56:59.691835 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 13:56:59.698284 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 13:56:59.701609 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 13:56:59.705046 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 13:56:59.712052 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 13:56:59.715462 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 13:56:59.718245 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 13:56:59.722295 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 13:56:59.728451 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 13:56:59.732125 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 13:56:59.734898 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 13:56:59.742168 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 13:56:59.745235 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5369 13:56:59.748390 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5370 13:56:59.751884 Total UI for P1: 0, mck2ui 16
5371 13:56:59.755320 best dqsien dly found for B0: ( 1, 2, 24)
5372 13:56:59.761787 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5373 13:56:59.765275 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 13:56:59.768351 Total UI for P1: 0, mck2ui 16
5375 13:56:59.771640 best dqsien dly found for B1: ( 1, 2, 30)
5376 13:56:59.774836 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5377 13:56:59.778598 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5378 13:56:59.778696
5379 13:56:59.781741 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5380 13:56:59.784880 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5381 13:56:59.788271 [Gating] SW calibration Done
5382 13:56:59.788346 ==
5383 13:56:59.791968 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 13:56:59.795474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 13:56:59.795547 ==
5386 13:56:59.798322 RX Vref Scan: 0
5387 13:56:59.798439
5388 13:56:59.801496 RX Vref 0 -> 0, step: 1
5389 13:56:59.801593
5390 13:56:59.801681 RX Delay -80 -> 252, step: 8
5391 13:56:59.808489 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5392 13:56:59.811948 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5393 13:56:59.815317 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5394 13:56:59.818655 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5395 13:56:59.822381 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5396 13:56:59.825248 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5397 13:56:59.831694 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5398 13:56:59.835780 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5399 13:56:59.838640 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5400 13:56:59.841853 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5401 13:56:59.845303 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5402 13:56:59.849004 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5403 13:56:59.855195 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5404 13:56:59.858550 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5405 13:56:59.862280 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5406 13:56:59.865172 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5407 13:56:59.865278 ==
5408 13:56:59.868774 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 13:56:59.872134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 13:56:59.872230 ==
5411 13:56:59.875491 DQS Delay:
5412 13:56:59.875584 DQS0 = 0, DQS1 = 0
5413 13:56:59.878601 DQM Delay:
5414 13:56:59.878681 DQM0 = 97, DQM1 = 87
5415 13:56:59.878742 DQ Delay:
5416 13:56:59.882091 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5417 13:56:59.885566 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5418 13:56:59.888837 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =79
5419 13:56:59.891883 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5420 13:56:59.891955
5421 13:56:59.892034
5422 13:56:59.895525 ==
5423 13:56:59.898876 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 13:56:59.902058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 13:56:59.902167 ==
5426 13:56:59.902267
5427 13:56:59.902353
5428 13:56:59.905183 TX Vref Scan disable
5429 13:56:59.905278 == TX Byte 0 ==
5430 13:56:59.908892 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5431 13:56:59.915262 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5432 13:56:59.915344 == TX Byte 1 ==
5433 13:56:59.919019 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5434 13:56:59.925189 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5435 13:56:59.925292 ==
5436 13:56:59.928838 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 13:56:59.931875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 13:56:59.931951 ==
5439 13:56:59.932040
5440 13:56:59.932125
5441 13:56:59.935685 TX Vref Scan disable
5442 13:56:59.938567 == TX Byte 0 ==
5443 13:56:59.942262 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5444 13:56:59.945959 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5445 13:56:59.948832 == TX Byte 1 ==
5446 13:56:59.952239 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5447 13:56:59.956287 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5448 13:56:59.956400
5449 13:56:59.956491 [DATLAT]
5450 13:56:59.958823 Freq=933, CH0 RK1
5451 13:56:59.958897
5452 13:56:59.962320 DATLAT Default: 0xb
5453 13:56:59.962465 0, 0xFFFF, sum = 0
5454 13:56:59.965806 1, 0xFFFF, sum = 0
5455 13:56:59.965914 2, 0xFFFF, sum = 0
5456 13:56:59.968818 3, 0xFFFF, sum = 0
5457 13:56:59.968928 4, 0xFFFF, sum = 0
5458 13:56:59.972615 5, 0xFFFF, sum = 0
5459 13:56:59.972692 6, 0xFFFF, sum = 0
5460 13:56:59.975879 7, 0xFFFF, sum = 0
5461 13:56:59.975982 8, 0xFFFF, sum = 0
5462 13:56:59.979233 9, 0xFFFF, sum = 0
5463 13:56:59.979333 10, 0x0, sum = 1
5464 13:56:59.982386 11, 0x0, sum = 2
5465 13:56:59.982524 12, 0x0, sum = 3
5466 13:56:59.982617 13, 0x0, sum = 4
5467 13:56:59.985916 best_step = 11
5468 13:56:59.986018
5469 13:56:59.986115 ==
5470 13:56:59.989447 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 13:56:59.992456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 13:56:59.992537 ==
5473 13:56:59.995839 RX Vref Scan: 0
5474 13:56:59.995911
5475 13:56:59.995991 RX Vref 0 -> 0, step: 1
5476 13:56:59.998885
5477 13:56:59.998973 RX Delay -61 -> 252, step: 4
5478 13:57:00.006646 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5479 13:57:00.010261 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5480 13:57:00.013169 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5481 13:57:00.016553 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5482 13:57:00.020247 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5483 13:57:00.023367 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5484 13:57:00.030109 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5485 13:57:00.033261 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5486 13:57:00.036565 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5487 13:57:00.040534 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5488 13:57:00.043626 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5489 13:57:00.047017 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5490 13:57:00.053362 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5491 13:57:00.056746 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5492 13:57:00.060264 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5493 13:57:00.063592 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5494 13:57:00.063700 ==
5495 13:57:00.067083 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 13:57:00.070036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 13:57:00.073465 ==
5498 13:57:00.073565 DQS Delay:
5499 13:57:00.073637 DQS0 = 0, DQS1 = 0
5500 13:57:00.077061 DQM Delay:
5501 13:57:00.077156 DQM0 = 95, DQM1 = 88
5502 13:57:00.079929 DQ Delay:
5503 13:57:00.080021 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5504 13:57:00.083497 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5505 13:57:00.086746 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =80
5506 13:57:00.090274 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5507 13:57:00.093340
5508 13:57:00.093444
5509 13:57:00.100236 [DQSOSCAuto] RK1, (LSB)MR18= 0x1805, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5510 13:57:00.103112 CH0 RK1: MR19=505, MR18=1805
5511 13:57:00.110127 CH0_RK1: MR19=0x505, MR18=0x1805, DQSOSC=414, MR23=63, INC=63, DEC=42
5512 13:57:00.113381 [RxdqsGatingPostProcess] freq 933
5513 13:57:00.116560 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5514 13:57:00.120090 best DQS0 dly(2T, 0.5T) = (0, 11)
5515 13:57:00.123683 best DQS1 dly(2T, 0.5T) = (0, 11)
5516 13:57:00.126863 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5517 13:57:00.130606 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5518 13:57:00.133331 best DQS0 dly(2T, 0.5T) = (0, 10)
5519 13:57:00.136884 best DQS1 dly(2T, 0.5T) = (0, 10)
5520 13:57:00.140363 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5521 13:57:00.143587 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5522 13:57:00.147092 Pre-setting of DQS Precalculation
5523 13:57:00.150448 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5524 13:57:00.150581 ==
5525 13:57:00.153771 Dram Type= 6, Freq= 0, CH_1, rank 0
5526 13:57:00.157351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 13:57:00.157431 ==
5528 13:57:00.163688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 13:57:00.170560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5530 13:57:00.173741 [CA 0] Center 36 (6~67) winsize 62
5531 13:57:00.177093 [CA 1] Center 36 (6~67) winsize 62
5532 13:57:00.180041 [CA 2] Center 34 (4~64) winsize 61
5533 13:57:00.183522 [CA 3] Center 34 (4~64) winsize 61
5534 13:57:00.187033 [CA 4] Center 34 (4~65) winsize 62
5535 13:57:00.190650 [CA 5] Center 33 (3~64) winsize 62
5536 13:57:00.190730
5537 13:57:00.193400 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5538 13:57:00.193508
5539 13:57:00.197124 [CATrainingPosCal] consider 1 rank data
5540 13:57:00.200526 u2DelayCellTimex100 = 270/100 ps
5541 13:57:00.203339 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5542 13:57:00.206757 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 13:57:00.210679 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5544 13:57:00.213485 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5545 13:57:00.216929 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5546 13:57:00.220442 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 13:57:00.220522
5548 13:57:00.227185 CA PerBit enable=1, Macro0, CA PI delay=33
5549 13:57:00.227266
5550 13:57:00.230250 [CBTSetCACLKResult] CA Dly = 33
5551 13:57:00.230329 CS Dly: 5 (0~36)
5552 13:57:00.230392 ==
5553 13:57:00.233878 Dram Type= 6, Freq= 0, CH_1, rank 1
5554 13:57:00.237454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 13:57:00.237534 ==
5556 13:57:00.244020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 13:57:00.250778 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5558 13:57:00.253471 [CA 0] Center 36 (6~67) winsize 62
5559 13:57:00.257033 [CA 1] Center 37 (7~67) winsize 61
5560 13:57:00.260795 [CA 2] Center 33 (3~64) winsize 62
5561 13:57:00.263726 [CA 3] Center 33 (3~64) winsize 62
5562 13:57:00.267436 [CA 4] Center 34 (4~64) winsize 61
5563 13:57:00.270496 [CA 5] Center 32 (2~63) winsize 62
5564 13:57:00.270589
5565 13:57:00.274014 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5566 13:57:00.274120
5567 13:57:00.277174 [CATrainingPosCal] consider 2 rank data
5568 13:57:00.280794 u2DelayCellTimex100 = 270/100 ps
5569 13:57:00.283804 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 13:57:00.287219 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5571 13:57:00.290612 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5572 13:57:00.294324 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 13:57:00.297268 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5574 13:57:00.300309 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5575 13:57:00.300437
5576 13:57:00.307082 CA PerBit enable=1, Macro0, CA PI delay=33
5577 13:57:00.307185
5578 13:57:00.307276 [CBTSetCACLKResult] CA Dly = 33
5579 13:57:00.310865 CS Dly: 5 (0~37)
5580 13:57:00.310937
5581 13:57:00.313528 ----->DramcWriteLeveling(PI) begin...
5582 13:57:00.313630 ==
5583 13:57:00.317282 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 13:57:00.320323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 13:57:00.320423 ==
5586 13:57:00.324080 Write leveling (Byte 0): 27 => 27
5587 13:57:00.327284 Write leveling (Byte 1): 28 => 28
5588 13:57:00.330666 DramcWriteLeveling(PI) end<-----
5589 13:57:00.330742
5590 13:57:00.330803 ==
5591 13:57:00.333669 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 13:57:00.337272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 13:57:00.340608 ==
5594 13:57:00.340709 [Gating] SW mode calibration
5595 13:57:00.350559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5596 13:57:00.353674 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5597 13:57:00.357064 0 14 0 | B1->B0 | 2e2e 3333 | 1 1 | (1 1) (1 1)
5598 13:57:00.363987 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 13:57:00.366916 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 13:57:00.370692 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 13:57:00.377325 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 13:57:00.380358 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 13:57:00.383443 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 13:57:00.390186 0 14 28 | B1->B0 | 3131 3030 | 1 1 | (1 0) (1 0)
5605 13:57:00.393612 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5606 13:57:00.396992 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 13:57:00.403576 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 13:57:00.406909 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 13:57:00.410453 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 13:57:00.417299 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 13:57:00.420119 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 13:57:00.423761 0 15 28 | B1->B0 | 2c2c 302f | 0 1 | (0 0) (1 1)
5613 13:57:00.429937 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5614 13:57:00.433446 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 13:57:00.436642 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 13:57:00.440040 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 13:57:00.447180 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 13:57:00.450023 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 13:57:00.453925 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 13:57:00.460101 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5621 13:57:00.463636 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5622 13:57:00.467051 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 13:57:00.473598 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 13:57:00.477001 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 13:57:00.480381 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 13:57:00.486918 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 13:57:00.490585 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 13:57:00.493845 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 13:57:00.500343 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:57:00.503535 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:57:00.506809 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:57:00.513559 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:57:00.517311 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:57:00.520325 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:57:00.524072 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5636 13:57:00.530322 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5637 13:57:00.534244 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 13:57:00.537574 Total UI for P1: 0, mck2ui 16
5639 13:57:00.540486 best dqsien dly found for B0: ( 1, 2, 26)
5640 13:57:00.543744 Total UI for P1: 0, mck2ui 16
5641 13:57:00.546968 best dqsien dly found for B1: ( 1, 2, 30)
5642 13:57:00.550290 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5643 13:57:00.553921 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5644 13:57:00.554001
5645 13:57:00.557670 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5646 13:57:00.560416 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5647 13:57:00.563683 [Gating] SW calibration Done
5648 13:57:00.563764 ==
5649 13:57:00.567080 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 13:57:00.570729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 13:57:00.573921 ==
5652 13:57:00.574001 RX Vref Scan: 0
5653 13:57:00.574063
5654 13:57:00.577301 RX Vref 0 -> 0, step: 1
5655 13:57:00.577407
5656 13:57:00.580854 RX Delay -80 -> 252, step: 8
5657 13:57:00.583660 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5658 13:57:00.587240 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5659 13:57:00.590830 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5660 13:57:00.593761 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5661 13:57:00.596885 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5662 13:57:00.603911 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5663 13:57:00.606981 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5664 13:57:00.611016 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5665 13:57:00.613894 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5666 13:57:00.616926 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5667 13:57:00.620628 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5668 13:57:00.627045 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5669 13:57:00.630476 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5670 13:57:00.633427 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5671 13:57:00.637049 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5672 13:57:00.640803 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5673 13:57:00.640881 ==
5674 13:57:00.644197 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 13:57:00.650957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 13:57:00.651122 ==
5677 13:57:00.651229 DQS Delay:
5678 13:57:00.653554 DQS0 = 0, DQS1 = 0
5679 13:57:00.653649 DQM Delay:
5680 13:57:00.653711 DQM0 = 95, DQM1 = 88
5681 13:57:00.657146 DQ Delay:
5682 13:57:00.660215 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5683 13:57:00.663947 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5684 13:57:00.667551 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5685 13:57:00.670308 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5686 13:57:00.670449
5687 13:57:00.670516
5688 13:57:00.670576 ==
5689 13:57:00.673916 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 13:57:00.677245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 13:57:00.677342 ==
5692 13:57:00.677429
5693 13:57:00.677517
5694 13:57:00.680556 TX Vref Scan disable
5695 13:57:00.680649 == TX Byte 0 ==
5696 13:57:00.687157 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5697 13:57:00.690697 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5698 13:57:00.690772 == TX Byte 1 ==
5699 13:57:00.697243 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5700 13:57:00.700712 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5701 13:57:00.700787 ==
5702 13:57:00.703851 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 13:57:00.707371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 13:57:00.707449 ==
5705 13:57:00.707511
5706 13:57:00.707570
5707 13:57:00.710700 TX Vref Scan disable
5708 13:57:00.713634 == TX Byte 0 ==
5709 13:57:00.717431 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5710 13:57:00.720663 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5711 13:57:00.723847 == TX Byte 1 ==
5712 13:57:00.727423 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5713 13:57:00.730530 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5714 13:57:00.730601
5715 13:57:00.734280 [DATLAT]
5716 13:57:00.734347 Freq=933, CH1 RK0
5717 13:57:00.734426
5718 13:57:00.737378 DATLAT Default: 0xd
5719 13:57:00.737514 0, 0xFFFF, sum = 0
5720 13:57:00.740329 1, 0xFFFF, sum = 0
5721 13:57:00.740415 2, 0xFFFF, sum = 0
5722 13:57:00.743814 3, 0xFFFF, sum = 0
5723 13:57:00.743887 4, 0xFFFF, sum = 0
5724 13:57:00.747390 5, 0xFFFF, sum = 0
5725 13:57:00.747478 6, 0xFFFF, sum = 0
5726 13:57:00.750106 7, 0xFFFF, sum = 0
5727 13:57:00.750204 8, 0xFFFF, sum = 0
5728 13:57:00.753841 9, 0xFFFF, sum = 0
5729 13:57:00.753915 10, 0x0, sum = 1
5730 13:57:00.757404 11, 0x0, sum = 2
5731 13:57:00.757510 12, 0x0, sum = 3
5732 13:57:00.760384 13, 0x0, sum = 4
5733 13:57:00.760491 best_step = 11
5734 13:57:00.760583
5735 13:57:00.760677 ==
5736 13:57:00.764365 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 13:57:00.770223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 13:57:00.770323 ==
5739 13:57:00.770460 RX Vref Scan: 1
5740 13:57:00.770551
5741 13:57:00.773796 RX Vref 0 -> 0, step: 1
5742 13:57:00.773867
5743 13:57:00.777054 RX Delay -69 -> 252, step: 4
5744 13:57:00.777127
5745 13:57:00.780453 Set Vref, RX VrefLevel [Byte0]: 60
5746 13:57:00.783572 [Byte1]: 51
5747 13:57:00.783673
5748 13:57:00.787051 Final RX Vref Byte 0 = 60 to rank0
5749 13:57:00.790306 Final RX Vref Byte 1 = 51 to rank0
5750 13:57:00.793521 Final RX Vref Byte 0 = 60 to rank1
5751 13:57:00.797128 Final RX Vref Byte 1 = 51 to rank1==
5752 13:57:00.800240 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 13:57:00.804500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 13:57:00.804615 ==
5755 13:57:00.807810 DQS Delay:
5756 13:57:00.807884 DQS0 = 0, DQS1 = 0
5757 13:57:00.807946 DQM Delay:
5758 13:57:00.810366 DQM0 = 97, DQM1 = 90
5759 13:57:00.810502 DQ Delay:
5760 13:57:00.813975 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5761 13:57:00.817435 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =96
5762 13:57:00.820628 DQ8 =78, DQ9 =76, DQ10 =92, DQ11 =86
5763 13:57:00.823565 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5764 13:57:00.823641
5765 13:57:00.823704
5766 13:57:00.833711 [DQSOSCAuto] RK0, (LSB)MR18= 0x12ef, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 416 ps
5767 13:57:00.837431 CH1 RK0: MR19=504, MR18=12EF
5768 13:57:00.840311 CH1_RK0: MR19=0x504, MR18=0x12EF, DQSOSC=416, MR23=63, INC=62, DEC=41
5769 13:57:00.840386
5770 13:57:00.843783 ----->DramcWriteLeveling(PI) begin...
5771 13:57:00.847477 ==
5772 13:57:00.847577 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 13:57:00.853994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 13:57:00.854105 ==
5775 13:57:00.857006 Write leveling (Byte 0): 26 => 26
5776 13:57:00.860578 Write leveling (Byte 1): 26 => 26
5777 13:57:00.864464 DramcWriteLeveling(PI) end<-----
5778 13:57:00.864574
5779 13:57:00.864666 ==
5780 13:57:00.867215 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 13:57:00.870335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 13:57:00.870468 ==
5783 13:57:00.873534 [Gating] SW mode calibration
5784 13:57:00.881054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5785 13:57:00.883887 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5786 13:57:00.890528 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5787 13:57:00.893868 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 13:57:00.897335 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5789 13:57:00.904216 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 13:57:00.907481 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 13:57:00.910622 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 13:57:00.917465 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
5793 13:57:00.920890 0 14 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
5794 13:57:00.923960 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5795 13:57:00.931121 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 13:57:00.934153 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 13:57:00.937661 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 13:57:00.944116 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 13:57:00.947529 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5800 13:57:00.950682 0 15 24 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
5801 13:57:00.954107 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5802 13:57:00.961000 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 13:57:00.963943 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 13:57:00.967795 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 13:57:00.974022 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 13:57:00.977685 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 13:57:00.981060 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 13:57:00.987579 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5809 13:57:00.990767 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5810 13:57:00.994341 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 13:57:01.001171 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 13:57:01.004670 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 13:57:01.008115 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 13:57:01.011070 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 13:57:01.017752 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 13:57:01.021417 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 13:57:01.024618 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 13:57:01.031078 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 13:57:01.034475 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 13:57:01.038055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 13:57:01.044772 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 13:57:01.047813 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 13:57:01.050967 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 13:57:01.057944 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5825 13:57:01.061304 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 13:57:01.064151 Total UI for P1: 0, mck2ui 16
5827 13:57:01.067848 best dqsien dly found for B0: ( 1, 2, 24)
5828 13:57:01.071518 Total UI for P1: 0, mck2ui 16
5829 13:57:01.075177 best dqsien dly found for B1: ( 1, 2, 26)
5830 13:57:01.077900 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5831 13:57:01.081335 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5832 13:57:01.081411
5833 13:57:01.084243 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5834 13:57:01.087913 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5835 13:57:01.091100 [Gating] SW calibration Done
5836 13:57:01.091208 ==
5837 13:57:01.094272 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 13:57:01.097913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 13:57:01.098003 ==
5840 13:57:01.101350 RX Vref Scan: 0
5841 13:57:01.101427
5842 13:57:01.104593 RX Vref 0 -> 0, step: 1
5843 13:57:01.104692
5844 13:57:01.104782 RX Delay -80 -> 252, step: 8
5845 13:57:01.111098 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5846 13:57:01.114269 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5847 13:57:01.117631 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5848 13:57:01.121358 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5849 13:57:01.124990 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5850 13:57:01.127989 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5851 13:57:01.134466 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5852 13:57:01.138193 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5853 13:57:01.141299 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5854 13:57:01.144605 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5855 13:57:01.148151 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5856 13:57:01.151095 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5857 13:57:01.158315 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5858 13:57:01.161389 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5859 13:57:01.164873 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5860 13:57:01.168198 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5861 13:57:01.168297 ==
5862 13:57:01.171530 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 13:57:01.175069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 13:57:01.175171 ==
5865 13:57:01.178028 DQS Delay:
5866 13:57:01.178129 DQS0 = 0, DQS1 = 0
5867 13:57:01.181610 DQM Delay:
5868 13:57:01.181697 DQM0 = 95, DQM1 = 88
5869 13:57:01.181784 DQ Delay:
5870 13:57:01.185013 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5871 13:57:01.188093 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5872 13:57:01.191483 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5873 13:57:01.194857 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5874 13:57:01.194954
5875 13:57:01.195017
5876 13:57:01.198361 ==
5877 13:57:01.201744 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 13:57:01.204502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 13:57:01.204583 ==
5880 13:57:01.204672
5881 13:57:01.204766
5882 13:57:01.207961 TX Vref Scan disable
5883 13:57:01.208033 == TX Byte 0 ==
5884 13:57:01.211384 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5885 13:57:01.218098 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5886 13:57:01.218217 == TX Byte 1 ==
5887 13:57:01.221822 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5888 13:57:01.228274 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5889 13:57:01.228377 ==
5890 13:57:01.231696 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 13:57:01.234678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 13:57:01.234752 ==
5893 13:57:01.234816
5894 13:57:01.234876
5895 13:57:01.238711 TX Vref Scan disable
5896 13:57:01.241736 == TX Byte 0 ==
5897 13:57:01.244937 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5898 13:57:01.248603 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5899 13:57:01.251644 == TX Byte 1 ==
5900 13:57:01.255096 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5901 13:57:01.258390 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5902 13:57:01.258491
5903 13:57:01.258553 [DATLAT]
5904 13:57:01.261707 Freq=933, CH1 RK1
5905 13:57:01.261787
5906 13:57:01.261850 DATLAT Default: 0xb
5907 13:57:01.265015 0, 0xFFFF, sum = 0
5908 13:57:01.268484 1, 0xFFFF, sum = 0
5909 13:57:01.268560 2, 0xFFFF, sum = 0
5910 13:57:01.271417 3, 0xFFFF, sum = 0
5911 13:57:01.271489 4, 0xFFFF, sum = 0
5912 13:57:01.275102 5, 0xFFFF, sum = 0
5913 13:57:01.275175 6, 0xFFFF, sum = 0
5914 13:57:01.278340 7, 0xFFFF, sum = 0
5915 13:57:01.278463 8, 0xFFFF, sum = 0
5916 13:57:01.282083 9, 0xFFFF, sum = 0
5917 13:57:01.282197 10, 0x0, sum = 1
5918 13:57:01.284682 11, 0x0, sum = 2
5919 13:57:01.284781 12, 0x0, sum = 3
5920 13:57:01.288384 13, 0x0, sum = 4
5921 13:57:01.288481 best_step = 11
5922 13:57:01.288568
5923 13:57:01.288652 ==
5924 13:57:01.292271 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 13:57:01.295281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 13:57:01.295367 ==
5927 13:57:01.298124 RX Vref Scan: 0
5928 13:57:01.298252
5929 13:57:01.301751 RX Vref 0 -> 0, step: 1
5930 13:57:01.301855
5931 13:57:01.301947 RX Delay -61 -> 252, step: 4
5932 13:57:01.309128 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5933 13:57:01.312869 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5934 13:57:01.315643 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5935 13:57:01.319300 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5936 13:57:01.322373 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5937 13:57:01.326228 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5938 13:57:01.332388 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5939 13:57:01.336093 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5940 13:57:01.339390 iDelay=195, Bit 8, Center 82 (-9 ~ 174) 184
5941 13:57:01.342694 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5942 13:57:01.346012 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5943 13:57:01.349334 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5944 13:57:01.355708 iDelay=195, Bit 12, Center 98 (11 ~ 186) 176
5945 13:57:01.359573 iDelay=195, Bit 13, Center 100 (11 ~ 190) 180
5946 13:57:01.362902 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5947 13:57:01.366170 iDelay=195, Bit 15, Center 100 (11 ~ 190) 180
5948 13:57:01.366301 ==
5949 13:57:01.368946 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 13:57:01.375836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 13:57:01.375921 ==
5952 13:57:01.375987 DQS Delay:
5953 13:57:01.379057 DQS0 = 0, DQS1 = 0
5954 13:57:01.379135 DQM Delay:
5955 13:57:01.379195 DQM0 = 95, DQM1 = 91
5956 13:57:01.382295 DQ Delay:
5957 13:57:01.385963 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5958 13:57:01.388886 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5959 13:57:01.392095 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =84
5960 13:57:01.395470 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5961 13:57:01.395596
5962 13:57:01.395695
5963 13:57:01.402103 [DQSOSCAuto] RK1, (LSB)MR18= 0xd16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5964 13:57:01.406035 CH1 RK1: MR19=505, MR18=D16
5965 13:57:01.412442 CH1_RK1: MR19=0x505, MR18=0xD16, DQSOSC=414, MR23=63, INC=63, DEC=42
5966 13:57:01.416066 [RxdqsGatingPostProcess] freq 933
5967 13:57:01.419230 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5968 13:57:01.422574 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 13:57:01.425707 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 13:57:01.428977 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 13:57:01.432833 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 13:57:01.435666 best DQS0 dly(2T, 0.5T) = (0, 10)
5973 13:57:01.439348 best DQS1 dly(2T, 0.5T) = (0, 10)
5974 13:57:01.442714 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5975 13:57:01.445888 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5976 13:57:01.449127 Pre-setting of DQS Precalculation
5977 13:57:01.452601 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5978 13:57:01.459043 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5979 13:57:01.469590 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5980 13:57:01.469671
5981 13:57:01.469735
5982 13:57:01.472738 [Calibration Summary] 1866 Mbps
5983 13:57:01.472819 CH 0, Rank 0
5984 13:57:01.475958 SW Impedance : PASS
5985 13:57:01.476043 DUTY Scan : NO K
5986 13:57:01.479204 ZQ Calibration : PASS
5987 13:57:01.482333 Jitter Meter : NO K
5988 13:57:01.482479 CBT Training : PASS
5989 13:57:01.486046 Write leveling : PASS
5990 13:57:01.486153 RX DQS gating : PASS
5991 13:57:01.489178 RX DQ/DQS(RDDQC) : PASS
5992 13:57:01.492964 TX DQ/DQS : PASS
5993 13:57:01.493045 RX DATLAT : PASS
5994 13:57:01.496281 RX DQ/DQS(Engine): PASS
5995 13:57:01.499759 TX OE : NO K
5996 13:57:01.499840 All Pass.
5997 13:57:01.499903
5998 13:57:01.499962 CH 0, Rank 1
5999 13:57:01.502611 SW Impedance : PASS
6000 13:57:01.506615 DUTY Scan : NO K
6001 13:57:01.506695 ZQ Calibration : PASS
6002 13:57:01.509239 Jitter Meter : NO K
6003 13:57:01.512876 CBT Training : PASS
6004 13:57:01.512983 Write leveling : PASS
6005 13:57:01.515976 RX DQS gating : PASS
6006 13:57:01.519819 RX DQ/DQS(RDDQC) : PASS
6007 13:57:01.519926 TX DQ/DQS : PASS
6008 13:57:01.523228 RX DATLAT : PASS
6009 13:57:01.523313 RX DQ/DQS(Engine): PASS
6010 13:57:01.525808 TX OE : NO K
6011 13:57:01.525897 All Pass.
6012 13:57:01.525959
6013 13:57:01.529500 CH 1, Rank 0
6014 13:57:01.529582 SW Impedance : PASS
6015 13:57:01.532676 DUTY Scan : NO K
6016 13:57:01.536121 ZQ Calibration : PASS
6017 13:57:01.536196 Jitter Meter : NO K
6018 13:57:01.539658 CBT Training : PASS
6019 13:57:01.542741 Write leveling : PASS
6020 13:57:01.542856 RX DQS gating : PASS
6021 13:57:01.545755 RX DQ/DQS(RDDQC) : PASS
6022 13:57:01.549481 TX DQ/DQS : PASS
6023 13:57:01.549582 RX DATLAT : PASS
6024 13:57:01.552789 RX DQ/DQS(Engine): PASS
6025 13:57:01.556276 TX OE : NO K
6026 13:57:01.556351 All Pass.
6027 13:57:01.556412
6028 13:57:01.556469 CH 1, Rank 1
6029 13:57:01.559190 SW Impedance : PASS
6030 13:57:01.562672 DUTY Scan : NO K
6031 13:57:01.562741 ZQ Calibration : PASS
6032 13:57:01.565867 Jitter Meter : NO K
6033 13:57:01.565948 CBT Training : PASS
6034 13:57:01.569783 Write leveling : PASS
6035 13:57:01.573034 RX DQS gating : PASS
6036 13:57:01.573129 RX DQ/DQS(RDDQC) : PASS
6037 13:57:01.575972 TX DQ/DQS : PASS
6038 13:57:01.579452 RX DATLAT : PASS
6039 13:57:01.579520 RX DQ/DQS(Engine): PASS
6040 13:57:01.582486 TX OE : NO K
6041 13:57:01.582555 All Pass.
6042 13:57:01.582614
6043 13:57:01.586726 DramC Write-DBI off
6044 13:57:01.589580 PER_BANK_REFRESH: Hybrid Mode
6045 13:57:01.589655 TX_TRACKING: ON
6046 13:57:01.599297 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6047 13:57:01.602809 [FAST_K] Save calibration result to emmc
6048 13:57:01.606162 dramc_set_vcore_voltage set vcore to 650000
6049 13:57:01.609270 Read voltage for 400, 6
6050 13:57:01.609367 Vio18 = 0
6051 13:57:01.609456 Vcore = 650000
6052 13:57:01.612968 Vdram = 0
6053 13:57:01.613062 Vddq = 0
6054 13:57:01.613150 Vmddr = 0
6055 13:57:01.619346 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6056 13:57:01.622791 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6057 13:57:01.626208 MEM_TYPE=3, freq_sel=20
6058 13:57:01.629378 sv_algorithm_assistance_LP4_800
6059 13:57:01.632561 ============ PULL DRAM RESETB DOWN ============
6060 13:57:01.635792 ========== PULL DRAM RESETB DOWN end =========
6061 13:57:01.643065 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6062 13:57:01.645862 ===================================
6063 13:57:01.645964 LPDDR4 DRAM CONFIGURATION
6064 13:57:01.649227 ===================================
6065 13:57:01.652944 EX_ROW_EN[0] = 0x0
6066 13:57:01.656278 EX_ROW_EN[1] = 0x0
6067 13:57:01.656358 LP4Y_EN = 0x0
6068 13:57:01.659266 WORK_FSP = 0x0
6069 13:57:01.659346 WL = 0x2
6070 13:57:01.663047 RL = 0x2
6071 13:57:01.663127 BL = 0x2
6072 13:57:01.666683 RPST = 0x0
6073 13:57:01.666763 RD_PRE = 0x0
6074 13:57:01.669609 WR_PRE = 0x1
6075 13:57:01.669689 WR_PST = 0x0
6076 13:57:01.673160 DBI_WR = 0x0
6077 13:57:01.673240 DBI_RD = 0x0
6078 13:57:01.676146 OTF = 0x1
6079 13:57:01.679973 ===================================
6080 13:57:01.683321 ===================================
6081 13:57:01.683404 ANA top config
6082 13:57:01.686878 ===================================
6083 13:57:01.689814 DLL_ASYNC_EN = 0
6084 13:57:01.692879 ALL_SLAVE_EN = 1
6085 13:57:01.692959 NEW_RANK_MODE = 1
6086 13:57:01.696279 DLL_IDLE_MODE = 1
6087 13:57:01.699872 LP45_APHY_COMB_EN = 1
6088 13:57:01.703132 TX_ODT_DIS = 1
6089 13:57:01.703213 NEW_8X_MODE = 1
6090 13:57:01.706217 ===================================
6091 13:57:01.709881 ===================================
6092 13:57:01.713273 data_rate = 800
6093 13:57:01.716603 CKR = 1
6094 13:57:01.719955 DQ_P2S_RATIO = 4
6095 13:57:01.723303 ===================================
6096 13:57:01.726570 CA_P2S_RATIO = 4
6097 13:57:01.729795 DQ_CA_OPEN = 0
6098 13:57:01.729902 DQ_SEMI_OPEN = 1
6099 13:57:01.733178 CA_SEMI_OPEN = 1
6100 13:57:01.736462 CA_FULL_RATE = 0
6101 13:57:01.740079 DQ_CKDIV4_EN = 0
6102 13:57:01.743625 CA_CKDIV4_EN = 1
6103 13:57:01.746359 CA_PREDIV_EN = 0
6104 13:57:01.746468 PH8_DLY = 0
6105 13:57:01.749952 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6106 13:57:01.753482 DQ_AAMCK_DIV = 0
6107 13:57:01.756454 CA_AAMCK_DIV = 0
6108 13:57:01.759842 CA_ADMCK_DIV = 4
6109 13:57:01.763042 DQ_TRACK_CA_EN = 0
6110 13:57:01.763114 CA_PICK = 800
6111 13:57:01.766365 CA_MCKIO = 400
6112 13:57:01.769559 MCKIO_SEMI = 400
6113 13:57:01.773356 PLL_FREQ = 3016
6114 13:57:01.776949 DQ_UI_PI_RATIO = 32
6115 13:57:01.780072 CA_UI_PI_RATIO = 32
6116 13:57:01.783102 ===================================
6117 13:57:01.786747 ===================================
6118 13:57:01.786855 memory_type:LPDDR4
6119 13:57:01.790088 GP_NUM : 10
6120 13:57:01.793055 SRAM_EN : 1
6121 13:57:01.793157 MD32_EN : 0
6122 13:57:01.796738 ===================================
6123 13:57:01.799616 [ANA_INIT] >>>>>>>>>>>>>>
6124 13:57:01.803482 <<<<<< [CONFIGURE PHASE]: ANA_TX
6125 13:57:01.806383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6126 13:57:01.809827 ===================================
6127 13:57:01.813221 data_rate = 800,PCW = 0X7400
6128 13:57:01.816313 ===================================
6129 13:57:01.819961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6130 13:57:01.822984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 13:57:01.836967 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 13:57:01.839810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6133 13:57:01.843135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6134 13:57:01.846220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6135 13:57:01.849825 [ANA_INIT] flow start
6136 13:57:01.849922 [ANA_INIT] PLL >>>>>>>>
6137 13:57:01.853008 [ANA_INIT] PLL <<<<<<<<
6138 13:57:01.856726 [ANA_INIT] MIDPI >>>>>>>>
6139 13:57:01.859665 [ANA_INIT] MIDPI <<<<<<<<
6140 13:57:01.859764 [ANA_INIT] DLL >>>>>>>>
6141 13:57:01.863084 [ANA_INIT] flow end
6142 13:57:01.866330 ============ LP4 DIFF to SE enter ============
6143 13:57:01.869517 ============ LP4 DIFF to SE exit ============
6144 13:57:01.872944 [ANA_INIT] <<<<<<<<<<<<<
6145 13:57:01.876442 [Flow] Enable top DCM control >>>>>
6146 13:57:01.880036 [Flow] Enable top DCM control <<<<<
6147 13:57:01.883018 Enable DLL master slave shuffle
6148 13:57:01.889821 ==============================================================
6149 13:57:01.889902 Gating Mode config
6150 13:57:01.896814 ==============================================================
6151 13:57:01.896895 Config description:
6152 13:57:01.906342 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6153 13:57:01.913150 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6154 13:57:01.920250 SELPH_MODE 0: By rank 1: By Phase
6155 13:57:01.923546 ==============================================================
6156 13:57:01.926358 GAT_TRACK_EN = 0
6157 13:57:01.930059 RX_GATING_MODE = 2
6158 13:57:01.933032 RX_GATING_TRACK_MODE = 2
6159 13:57:01.936566 SELPH_MODE = 1
6160 13:57:01.940244 PICG_EARLY_EN = 1
6161 13:57:01.943819 VALID_LAT_VALUE = 1
6162 13:57:01.946698 ==============================================================
6163 13:57:01.949956 Enter into Gating configuration >>>>
6164 13:57:01.953469 Exit from Gating configuration <<<<
6165 13:57:01.956429 Enter into DVFS_PRE_config >>>>>
6166 13:57:01.969868 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6167 13:57:01.973816 Exit from DVFS_PRE_config <<<<<
6168 13:57:01.973897 Enter into PICG configuration >>>>
6169 13:57:01.977426 Exit from PICG configuration <<<<
6170 13:57:01.979853 [RX_INPUT] configuration >>>>>
6171 13:57:01.983685 [RX_INPUT] configuration <<<<<
6172 13:57:01.989762 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6173 13:57:01.993450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6174 13:57:02.000027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6175 13:57:02.006620 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6176 13:57:02.013571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6177 13:57:02.020116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6178 13:57:02.023212 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6179 13:57:02.026767 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6180 13:57:02.029953 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6181 13:57:02.036492 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6182 13:57:02.039952 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6183 13:57:02.043616 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 13:57:02.047133 ===================================
6185 13:57:02.049992 LPDDR4 DRAM CONFIGURATION
6186 13:57:02.053454 ===================================
6187 13:57:02.053534 EX_ROW_EN[0] = 0x0
6188 13:57:02.056289 EX_ROW_EN[1] = 0x0
6189 13:57:02.060162 LP4Y_EN = 0x0
6190 13:57:02.060241 WORK_FSP = 0x0
6191 13:57:02.063768 WL = 0x2
6192 13:57:02.063847 RL = 0x2
6193 13:57:02.067097 BL = 0x2
6194 13:57:02.067176 RPST = 0x0
6195 13:57:02.069817 RD_PRE = 0x0
6196 13:57:02.069895 WR_PRE = 0x1
6197 13:57:02.073175 WR_PST = 0x0
6198 13:57:02.073253 DBI_WR = 0x0
6199 13:57:02.076948 DBI_RD = 0x0
6200 13:57:02.077028 OTF = 0x1
6201 13:57:02.079974 ===================================
6202 13:57:02.083227 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6203 13:57:02.089794 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6204 13:57:02.093580 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 13:57:02.096495 ===================================
6206 13:57:02.100491 LPDDR4 DRAM CONFIGURATION
6207 13:57:02.103097 ===================================
6208 13:57:02.103177 EX_ROW_EN[0] = 0x10
6209 13:57:02.107037 EX_ROW_EN[1] = 0x0
6210 13:57:02.107116 LP4Y_EN = 0x0
6211 13:57:02.110138 WORK_FSP = 0x0
6212 13:57:02.110217 WL = 0x2
6213 13:57:02.113059 RL = 0x2
6214 13:57:02.113157 BL = 0x2
6215 13:57:02.116424 RPST = 0x0
6216 13:57:02.119882 RD_PRE = 0x0
6217 13:57:02.119963 WR_PRE = 0x1
6218 13:57:02.123026 WR_PST = 0x0
6219 13:57:02.123106 DBI_WR = 0x0
6220 13:57:02.126743 DBI_RD = 0x0
6221 13:57:02.126824 OTF = 0x1
6222 13:57:02.129771 ===================================
6223 13:57:02.136582 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6224 13:57:02.140079 nWR fixed to 30
6225 13:57:02.143355 [ModeRegInit_LP4] CH0 RK0
6226 13:57:02.143437 [ModeRegInit_LP4] CH0 RK1
6227 13:57:02.146949 [ModeRegInit_LP4] CH1 RK0
6228 13:57:02.150326 [ModeRegInit_LP4] CH1 RK1
6229 13:57:02.150412 match AC timing 19
6230 13:57:02.157074 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6231 13:57:02.159915 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6232 13:57:02.163294 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6233 13:57:02.170051 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6234 13:57:02.173615 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6235 13:57:02.173696 ==
6236 13:57:02.176600 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 13:57:02.180247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 13:57:02.180329 ==
6239 13:57:02.186783 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 13:57:02.193366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6241 13:57:02.196786 [CA 0] Center 36 (8~64) winsize 57
6242 13:57:02.199827 [CA 1] Center 36 (8~64) winsize 57
6243 13:57:02.203274 [CA 2] Center 36 (8~64) winsize 57
6244 13:57:02.203369 [CA 3] Center 36 (8~64) winsize 57
6245 13:57:02.206514 [CA 4] Center 36 (8~64) winsize 57
6246 13:57:02.210147 [CA 5] Center 36 (8~64) winsize 57
6247 13:57:02.210265
6248 13:57:02.217044 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6249 13:57:02.217177
6250 13:57:02.220014 [CATrainingPosCal] consider 1 rank data
6251 13:57:02.220140 u2DelayCellTimex100 = 270/100 ps
6252 13:57:02.226517 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 13:57:02.230320 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 13:57:02.233173 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 13:57:02.236707 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 13:57:02.240014 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 13:57:02.243155 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 13:57:02.243279
6259 13:57:02.246868 CA PerBit enable=1, Macro0, CA PI delay=36
6260 13:57:02.246979
6261 13:57:02.250316 [CBTSetCACLKResult] CA Dly = 36
6262 13:57:02.253339 CS Dly: 1 (0~32)
6263 13:57:02.253463 ==
6264 13:57:02.256493 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 13:57:02.260306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 13:57:02.260417 ==
6267 13:57:02.266531 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 13:57:02.269813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6269 13:57:02.273329 [CA 0] Center 36 (8~64) winsize 57
6270 13:57:02.276637 [CA 1] Center 36 (8~64) winsize 57
6271 13:57:02.279991 [CA 2] Center 36 (8~64) winsize 57
6272 13:57:02.283678 [CA 3] Center 36 (8~64) winsize 57
6273 13:57:02.287129 [CA 4] Center 36 (8~64) winsize 57
6274 13:57:02.290372 [CA 5] Center 36 (8~64) winsize 57
6275 13:57:02.290555
6276 13:57:02.293379 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6277 13:57:02.293494
6278 13:57:02.296783 [CATrainingPosCal] consider 2 rank data
6279 13:57:02.300147 u2DelayCellTimex100 = 270/100 ps
6280 13:57:02.303681 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 13:57:02.306657 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 13:57:02.309729 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 13:57:02.313807 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 13:57:02.319940 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 13:57:02.323665 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 13:57:02.323790
6287 13:57:02.326879 CA PerBit enable=1, Macro0, CA PI delay=36
6288 13:57:02.327004
6289 13:57:02.329995 [CBTSetCACLKResult] CA Dly = 36
6290 13:57:02.330079 CS Dly: 1 (0~32)
6291 13:57:02.330144
6292 13:57:02.333331 ----->DramcWriteLeveling(PI) begin...
6293 13:57:02.333413 ==
6294 13:57:02.336699 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 13:57:02.343376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 13:57:02.343526 ==
6297 13:57:02.346912 Write leveling (Byte 0): 40 => 8
6298 13:57:02.346993 Write leveling (Byte 1): 32 => 0
6299 13:57:02.349971 DramcWriteLeveling(PI) end<-----
6300 13:57:02.350052
6301 13:57:02.350115 ==
6302 13:57:02.353555 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 13:57:02.360056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 13:57:02.360182 ==
6305 13:57:02.363786 [Gating] SW mode calibration
6306 13:57:02.369847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6307 13:57:02.373415 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6308 13:57:02.380423 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 13:57:02.383684 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 13:57:02.387007 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 13:57:02.389931 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 13:57:02.396537 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 13:57:02.400065 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 13:57:02.403422 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 13:57:02.410331 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 13:57:02.413613 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 13:57:02.416812 Total UI for P1: 0, mck2ui 16
6318 13:57:02.420077 best dqsien dly found for B0: ( 0, 14, 24)
6319 13:57:02.423475 Total UI for P1: 0, mck2ui 16
6320 13:57:02.426949 best dqsien dly found for B1: ( 0, 14, 24)
6321 13:57:02.430335 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6322 13:57:02.433569 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6323 13:57:02.433642
6324 13:57:02.436949 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 13:57:02.440527 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 13:57:02.443279 [Gating] SW calibration Done
6327 13:57:02.443358 ==
6328 13:57:02.446911 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 13:57:02.450137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 13:57:02.453837 ==
6331 13:57:02.453910 RX Vref Scan: 0
6332 13:57:02.453971
6333 13:57:02.457219 RX Vref 0 -> 0, step: 1
6334 13:57:02.457300
6335 13:57:02.460401 RX Delay -410 -> 252, step: 16
6336 13:57:02.463732 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6337 13:57:02.467334 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6338 13:57:02.470243 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6339 13:57:02.476845 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6340 13:57:02.480510 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6341 13:57:02.483985 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6342 13:57:02.487102 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6343 13:57:02.493636 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6344 13:57:02.497106 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6345 13:57:02.500414 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6346 13:57:02.503696 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6347 13:57:02.510605 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6348 13:57:02.513625 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6349 13:57:02.517008 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6350 13:57:02.519858 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6351 13:57:02.526634 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6352 13:57:02.526715 ==
6353 13:57:02.530424 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 13:57:02.533365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 13:57:02.533446 ==
6356 13:57:02.533509 DQS Delay:
6357 13:57:02.536881 DQS0 = 35, DQS1 = 51
6358 13:57:02.536961 DQM Delay:
6359 13:57:02.540372 DQM0 = 8, DQM1 = 10
6360 13:57:02.540451 DQ Delay:
6361 13:57:02.543813 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6362 13:57:02.546771 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6363 13:57:02.550594 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6364 13:57:02.553452 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6365 13:57:02.553555
6366 13:57:02.553643
6367 13:57:02.553746 ==
6368 13:57:02.556992 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 13:57:02.559908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 13:57:02.559983 ==
6371 13:57:02.560047
6372 13:57:02.560106
6373 13:57:02.563437 TX Vref Scan disable
6374 13:57:02.566770 == TX Byte 0 ==
6375 13:57:02.570073 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 13:57:02.573132 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 13:57:02.576623 == TX Byte 1 ==
6378 13:57:02.579628 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6379 13:57:02.583265 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6380 13:57:02.583338 ==
6381 13:57:02.586353 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 13:57:02.589995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 13:57:02.590068 ==
6384 13:57:02.593578
6385 13:57:02.593648
6386 13:57:02.593707 TX Vref Scan disable
6387 13:57:02.596796 == TX Byte 0 ==
6388 13:57:02.600024 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 13:57:02.603007 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 13:57:02.607161 == TX Byte 1 ==
6391 13:57:02.609480 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6392 13:57:02.612772 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6393 13:57:02.612843
6394 13:57:02.612925 [DATLAT]
6395 13:57:02.616393 Freq=400, CH0 RK0
6396 13:57:02.616466
6397 13:57:02.619565 DATLAT Default: 0xf
6398 13:57:02.619635 0, 0xFFFF, sum = 0
6399 13:57:02.622778 1, 0xFFFF, sum = 0
6400 13:57:02.622849 2, 0xFFFF, sum = 0
6401 13:57:02.625988 3, 0xFFFF, sum = 0
6402 13:57:02.626057 4, 0xFFFF, sum = 0
6403 13:57:02.629259 5, 0xFFFF, sum = 0
6404 13:57:02.629334 6, 0xFFFF, sum = 0
6405 13:57:02.633149 7, 0xFFFF, sum = 0
6406 13:57:02.633217 8, 0xFFFF, sum = 0
6407 13:57:02.636294 9, 0xFFFF, sum = 0
6408 13:57:02.636364 10, 0xFFFF, sum = 0
6409 13:57:02.639970 11, 0xFFFF, sum = 0
6410 13:57:02.640044 12, 0xFFFF, sum = 0
6411 13:57:02.643223 13, 0x0, sum = 1
6412 13:57:02.643300 14, 0x0, sum = 2
6413 13:57:02.645951 15, 0x0, sum = 3
6414 13:57:02.646025 16, 0x0, sum = 4
6415 13:57:02.649241 best_step = 14
6416 13:57:02.649309
6417 13:57:02.649367 ==
6418 13:57:02.652802 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 13:57:02.656252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 13:57:02.656334 ==
6421 13:57:02.659936 RX Vref Scan: 1
6422 13:57:02.660005
6423 13:57:02.660064 RX Vref 0 -> 0, step: 1
6424 13:57:02.660127
6425 13:57:02.663019 RX Delay -343 -> 252, step: 8
6426 13:57:02.663093
6427 13:57:02.666948 Set Vref, RX VrefLevel [Byte0]: 56
6428 13:57:02.669824 [Byte1]: 52
6429 13:57:02.674278
6430 13:57:02.674349 Final RX Vref Byte 0 = 56 to rank0
6431 13:57:02.677089 Final RX Vref Byte 1 = 52 to rank0
6432 13:57:02.680509 Final RX Vref Byte 0 = 56 to rank1
6433 13:57:02.684250 Final RX Vref Byte 1 = 52 to rank1==
6434 13:57:02.687572 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 13:57:02.694184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 13:57:02.694260 ==
6437 13:57:02.694321 DQS Delay:
6438 13:57:02.694378 DQS0 = 44, DQS1 = 60
6439 13:57:02.697418 DQM Delay:
6440 13:57:02.697486 DQM0 = 11, DQM1 = 14
6441 13:57:02.700548 DQ Delay:
6442 13:57:02.703854 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6443 13:57:02.703956 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6444 13:57:02.707550 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6445 13:57:02.710835 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6446 13:57:02.710916
6447 13:57:02.714136
6448 13:57:02.720530 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6449 13:57:02.723782 CH0 RK0: MR19=C0C, MR18=8B59
6450 13:57:02.731106 CH0_RK0: MR19=0xC0C, MR18=0x8B59, DQSOSC=392, MR23=63, INC=384, DEC=256
6451 13:57:02.731185 ==
6452 13:57:02.734056 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 13:57:02.737868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 13:57:02.737942 ==
6455 13:57:02.741013 [Gating] SW mode calibration
6456 13:57:02.747251 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6457 13:57:02.750799 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6458 13:57:02.757375 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 13:57:02.760744 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 13:57:02.764038 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 13:57:02.770845 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 13:57:02.773923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 13:57:02.777116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 13:57:02.784007 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 13:57:02.787674 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 13:57:02.791390 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 13:57:02.794517 Total UI for P1: 0, mck2ui 16
6468 13:57:02.797448 best dqsien dly found for B0: ( 0, 14, 24)
6469 13:57:02.800714 Total UI for P1: 0, mck2ui 16
6470 13:57:02.804118 best dqsien dly found for B1: ( 0, 14, 24)
6471 13:57:02.807385 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6472 13:57:02.810562 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6473 13:57:02.810637
6474 13:57:02.817120 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 13:57:02.820865 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 13:57:02.820944 [Gating] SW calibration Done
6477 13:57:02.823966 ==
6478 13:57:02.827421 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 13:57:02.831017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 13:57:02.831100 ==
6481 13:57:02.831163 RX Vref Scan: 0
6482 13:57:02.831223
6483 13:57:02.834128 RX Vref 0 -> 0, step: 1
6484 13:57:02.834200
6485 13:57:02.837447 RX Delay -410 -> 252, step: 16
6486 13:57:02.840993 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6487 13:57:02.843916 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6488 13:57:02.850314 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6489 13:57:02.854138 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6490 13:57:02.856756 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6491 13:57:02.864103 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6492 13:57:02.867515 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6493 13:57:02.870409 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6494 13:57:02.873826 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6495 13:57:02.876899 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6496 13:57:02.884200 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6497 13:57:02.887189 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6498 13:57:02.891232 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6499 13:57:02.896885 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6500 13:57:02.900328 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6501 13:57:02.903453 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6502 13:57:02.903530 ==
6503 13:57:02.907135 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 13:57:02.910644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 13:57:02.913809 ==
6506 13:57:02.913879 DQS Delay:
6507 13:57:02.913940 DQS0 = 35, DQS1 = 51
6508 13:57:02.916715 DQM Delay:
6509 13:57:02.916794 DQM0 = 4, DQM1 = 10
6510 13:57:02.920318 DQ Delay:
6511 13:57:02.920393 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6512 13:57:02.923357 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6513 13:57:02.927174 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6514 13:57:02.930149 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6515 13:57:02.930227
6516 13:57:02.930289
6517 13:57:02.930356 ==
6518 13:57:02.933342 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 13:57:02.940832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 13:57:02.940946 ==
6521 13:57:02.941027
6522 13:57:02.941107
6523 13:57:02.941166 TX Vref Scan disable
6524 13:57:02.943703 == TX Byte 0 ==
6525 13:57:02.947164 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6526 13:57:02.950607 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6527 13:57:02.953781 == TX Byte 1 ==
6528 13:57:02.956874 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6529 13:57:02.960226 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6530 13:57:02.960301 ==
6531 13:57:02.963923 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 13:57:02.970610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 13:57:02.970730 ==
6534 13:57:02.970859
6535 13:57:02.970972
6536 13:57:02.971073 TX Vref Scan disable
6537 13:57:02.973650 == TX Byte 0 ==
6538 13:57:02.977591 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6539 13:57:02.980421 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6540 13:57:02.983877 == TX Byte 1 ==
6541 13:57:02.987305 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6542 13:57:02.990686 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6543 13:57:02.990761
6544 13:57:02.993857 [DATLAT]
6545 13:57:02.993930 Freq=400, CH0 RK1
6546 13:57:02.993991
6547 13:57:02.997284 DATLAT Default: 0xe
6548 13:57:02.997358 0, 0xFFFF, sum = 0
6549 13:57:03.000286 1, 0xFFFF, sum = 0
6550 13:57:03.000420 2, 0xFFFF, sum = 0
6551 13:57:03.003484 3, 0xFFFF, sum = 0
6552 13:57:03.003580 4, 0xFFFF, sum = 0
6553 13:57:03.007330 5, 0xFFFF, sum = 0
6554 13:57:03.007406 6, 0xFFFF, sum = 0
6555 13:57:03.010311 7, 0xFFFF, sum = 0
6556 13:57:03.010384 8, 0xFFFF, sum = 0
6557 13:57:03.014301 9, 0xFFFF, sum = 0
6558 13:57:03.014418 10, 0xFFFF, sum = 0
6559 13:57:03.017033 11, 0xFFFF, sum = 0
6560 13:57:03.017122 12, 0xFFFF, sum = 0
6561 13:57:03.020363 13, 0x0, sum = 1
6562 13:57:03.020465 14, 0x0, sum = 2
6563 13:57:03.023661 15, 0x0, sum = 3
6564 13:57:03.023762 16, 0x0, sum = 4
6565 13:57:03.026823 best_step = 14
6566 13:57:03.026898
6567 13:57:03.026959 ==
6568 13:57:03.030212 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 13:57:03.034386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 13:57:03.034490 ==
6571 13:57:03.037205 RX Vref Scan: 0
6572 13:57:03.037274
6573 13:57:03.037333 RX Vref 0 -> 0, step: 1
6574 13:57:03.037398
6575 13:57:03.040081 RX Delay -343 -> 252, step: 8
6576 13:57:03.048921 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6577 13:57:03.051672 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6578 13:57:03.055264 iDelay=217, Bit 2, Center -36 (-279 ~ 208) 488
6579 13:57:03.058594 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6580 13:57:03.065458 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6581 13:57:03.068304 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6582 13:57:03.071583 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6583 13:57:03.074836 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6584 13:57:03.081681 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6585 13:57:03.084784 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6586 13:57:03.088022 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6587 13:57:03.091971 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6588 13:57:03.098577 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6589 13:57:03.101663 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6590 13:57:03.104880 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6591 13:57:03.108874 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6592 13:57:03.111571 ==
6593 13:57:03.115358 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 13:57:03.118264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 13:57:03.118393 ==
6596 13:57:03.118534 DQS Delay:
6597 13:57:03.122186 DQS0 = 48, DQS1 = 60
6598 13:57:03.122269 DQM Delay:
6599 13:57:03.124908 DQM0 = 13, DQM1 = 13
6600 13:57:03.124996 DQ Delay:
6601 13:57:03.128590 DQ0 =16, DQ1 =12, DQ2 =12, DQ3 =12
6602 13:57:03.131920 DQ4 =16, DQ5 =0, DQ6 =20, DQ7 =20
6603 13:57:03.135168 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6604 13:57:03.138463 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6605 13:57:03.138576
6606 13:57:03.138668
6607 13:57:03.144999 [DQSOSCAuto] RK1, (LSB)MR18= 0x9a6b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6608 13:57:03.149190 CH0 RK1: MR19=C0C, MR18=9A6B
6609 13:57:03.155315 CH0_RK1: MR19=0xC0C, MR18=0x9A6B, DQSOSC=390, MR23=63, INC=388, DEC=258
6610 13:57:03.158260 [RxdqsGatingPostProcess] freq 400
6611 13:57:03.162122 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6612 13:57:03.165131 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 13:57:03.168312 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 13:57:03.171763 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 13:57:03.175067 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 13:57:03.178703 best DQS0 dly(2T, 0.5T) = (0, 10)
6617 13:57:03.182043 best DQS1 dly(2T, 0.5T) = (0, 10)
6618 13:57:03.185121 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6619 13:57:03.188281 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6620 13:57:03.191738 Pre-setting of DQS Precalculation
6621 13:57:03.194825 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6622 13:57:03.194905 ==
6623 13:57:03.198326 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 13:57:03.205424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 13:57:03.205534 ==
6626 13:57:03.208704 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 13:57:03.214891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6628 13:57:03.218275 [CA 0] Center 36 (8~64) winsize 57
6629 13:57:03.221986 [CA 1] Center 36 (8~64) winsize 57
6630 13:57:03.225711 [CA 2] Center 36 (8~64) winsize 57
6631 13:57:03.228240 [CA 3] Center 36 (8~64) winsize 57
6632 13:57:03.231602 [CA 4] Center 36 (8~64) winsize 57
6633 13:57:03.235002 [CA 5] Center 36 (8~64) winsize 57
6634 13:57:03.235075
6635 13:57:03.238148 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6636 13:57:03.238238
6637 13:57:03.241939 [CATrainingPosCal] consider 1 rank data
6638 13:57:03.245140 u2DelayCellTimex100 = 270/100 ps
6639 13:57:03.249021 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 13:57:03.251604 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 13:57:03.255522 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 13:57:03.258032 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 13:57:03.261854 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 13:57:03.266360 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 13:57:03.268731
6646 13:57:03.271741 CA PerBit enable=1, Macro0, CA PI delay=36
6647 13:57:03.271812
6648 13:57:03.275070 [CBTSetCACLKResult] CA Dly = 36
6649 13:57:03.275142 CS Dly: 1 (0~32)
6650 13:57:03.275201 ==
6651 13:57:03.278203 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 13:57:03.281503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 13:57:03.281579 ==
6654 13:57:03.288653 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 13:57:03.294985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6656 13:57:03.298168 [CA 0] Center 36 (8~64) winsize 57
6657 13:57:03.301728 [CA 1] Center 36 (8~64) winsize 57
6658 13:57:03.304953 [CA 2] Center 36 (8~64) winsize 57
6659 13:57:03.308689 [CA 3] Center 36 (8~64) winsize 57
6660 13:57:03.308769 [CA 4] Center 36 (8~64) winsize 57
6661 13:57:03.311961 [CA 5] Center 36 (8~64) winsize 57
6662 13:57:03.312036
6663 13:57:03.318875 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6664 13:57:03.318954
6665 13:57:03.321822 [CATrainingPosCal] consider 2 rank data
6666 13:57:03.325052 u2DelayCellTimex100 = 270/100 ps
6667 13:57:03.328533 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 13:57:03.332251 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 13:57:03.335108 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 13:57:03.338989 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 13:57:03.341819 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 13:57:03.345310 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 13:57:03.345387
6674 13:57:03.348692 CA PerBit enable=1, Macro0, CA PI delay=36
6675 13:57:03.348790
6676 13:57:03.352145 [CBTSetCACLKResult] CA Dly = 36
6677 13:57:03.355560 CS Dly: 1 (0~32)
6678 13:57:03.355640
6679 13:57:03.358299 ----->DramcWriteLeveling(PI) begin...
6680 13:57:03.358436 ==
6681 13:57:03.362200 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 13:57:03.365341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 13:57:03.365422 ==
6684 13:57:03.368887 Write leveling (Byte 0): 40 => 8
6685 13:57:03.372163 Write leveling (Byte 1): 40 => 8
6686 13:57:03.376022 DramcWriteLeveling(PI) end<-----
6687 13:57:03.376103
6688 13:57:03.376166 ==
6689 13:57:03.378687 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 13:57:03.381818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 13:57:03.381894 ==
6692 13:57:03.385022 [Gating] SW mode calibration
6693 13:57:03.391800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6694 13:57:03.398388 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6695 13:57:03.402436 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 13:57:03.405236 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 13:57:03.412322 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 13:57:03.415364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 13:57:03.418321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 13:57:03.425215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 13:57:03.428557 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 13:57:03.431795 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 13:57:03.436218 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 13:57:03.439002 Total UI for P1: 0, mck2ui 16
6705 13:57:03.442296 best dqsien dly found for B0: ( 0, 14, 24)
6706 13:57:03.445028 Total UI for P1: 0, mck2ui 16
6707 13:57:03.448755 best dqsien dly found for B1: ( 0, 14, 24)
6708 13:57:03.451870 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6709 13:57:03.458655 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6710 13:57:03.458736
6711 13:57:03.461520 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 13:57:03.465116 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 13:57:03.468334 [Gating] SW calibration Done
6714 13:57:03.468414 ==
6715 13:57:03.471918 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 13:57:03.475416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 13:57:03.475496 ==
6718 13:57:03.475559 RX Vref Scan: 0
6719 13:57:03.478208
6720 13:57:03.478286 RX Vref 0 -> 0, step: 1
6721 13:57:03.478349
6722 13:57:03.481699 RX Delay -410 -> 252, step: 16
6723 13:57:03.485091 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6724 13:57:03.491759 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6725 13:57:03.495093 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6726 13:57:03.498181 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6727 13:57:03.501931 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6728 13:57:03.509088 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6729 13:57:03.511590 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6730 13:57:03.514863 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6731 13:57:03.518209 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6732 13:57:03.524777 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6733 13:57:03.528317 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6734 13:57:03.531670 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6735 13:57:03.535124 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6736 13:57:03.541655 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6737 13:57:03.545200 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6738 13:57:03.548400 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6739 13:57:03.548469 ==
6740 13:57:03.552255 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 13:57:03.555143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 13:57:03.558765 ==
6743 13:57:03.558873 DQS Delay:
6744 13:57:03.558977 DQS0 = 51, DQS1 = 59
6745 13:57:03.561647 DQM Delay:
6746 13:57:03.561717 DQM0 = 18, DQM1 = 16
6747 13:57:03.565072 DQ Delay:
6748 13:57:03.565161 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6749 13:57:03.568677 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6750 13:57:03.571776 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6751 13:57:03.575319 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6752 13:57:03.575475
6753 13:57:03.575558
6754 13:57:03.578296 ==
6755 13:57:03.581520 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 13:57:03.585092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 13:57:03.585213 ==
6758 13:57:03.585282
6759 13:57:03.585342
6760 13:57:03.588649 TX Vref Scan disable
6761 13:57:03.588733 == TX Byte 0 ==
6762 13:57:03.591751 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 13:57:03.598568 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 13:57:03.598649 == TX Byte 1 ==
6765 13:57:03.602297 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 13:57:03.605664 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 13:57:03.608417 ==
6768 13:57:03.611854 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 13:57:03.615258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 13:57:03.615339 ==
6771 13:57:03.615404
6772 13:57:03.615463
6773 13:57:03.618636 TX Vref Scan disable
6774 13:57:03.618716 == TX Byte 0 ==
6775 13:57:03.622294 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 13:57:03.628605 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 13:57:03.628687 == TX Byte 1 ==
6778 13:57:03.631822 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 13:57:03.638977 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 13:57:03.639056
6781 13:57:03.639143 [DATLAT]
6782 13:57:03.639221 Freq=400, CH1 RK0
6783 13:57:03.639297
6784 13:57:03.642043 DATLAT Default: 0xf
6785 13:57:03.642114 0, 0xFFFF, sum = 0
6786 13:57:03.645039 1, 0xFFFF, sum = 0
6787 13:57:03.645115 2, 0xFFFF, sum = 0
6788 13:57:03.648447 3, 0xFFFF, sum = 0
6789 13:57:03.648554 4, 0xFFFF, sum = 0
6790 13:57:03.651544 5, 0xFFFF, sum = 0
6791 13:57:03.655284 6, 0xFFFF, sum = 0
6792 13:57:03.655363 7, 0xFFFF, sum = 0
6793 13:57:03.658532 8, 0xFFFF, sum = 0
6794 13:57:03.658616 9, 0xFFFF, sum = 0
6795 13:57:03.661612 10, 0xFFFF, sum = 0
6796 13:57:03.661685 11, 0xFFFF, sum = 0
6797 13:57:03.664808 12, 0xFFFF, sum = 0
6798 13:57:03.664888 13, 0x0, sum = 1
6799 13:57:03.668680 14, 0x0, sum = 2
6800 13:57:03.668755 15, 0x0, sum = 3
6801 13:57:03.671692 16, 0x0, sum = 4
6802 13:57:03.671769 best_step = 14
6803 13:57:03.671848
6804 13:57:03.671923 ==
6805 13:57:03.675331 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 13:57:03.678311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 13:57:03.678455 ==
6808 13:57:03.681935 RX Vref Scan: 1
6809 13:57:03.682008
6810 13:57:03.685233 RX Vref 0 -> 0, step: 1
6811 13:57:03.685347
6812 13:57:03.685426 RX Delay -359 -> 252, step: 8
6813 13:57:03.688348
6814 13:57:03.688420 Set Vref, RX VrefLevel [Byte0]: 60
6815 13:57:03.691729 [Byte1]: 51
6816 13:57:03.697234
6817 13:57:03.697367 Final RX Vref Byte 0 = 60 to rank0
6818 13:57:03.700760 Final RX Vref Byte 1 = 51 to rank0
6819 13:57:03.703774 Final RX Vref Byte 0 = 60 to rank1
6820 13:57:03.707229 Final RX Vref Byte 1 = 51 to rank1==
6821 13:57:03.710848 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 13:57:03.714573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 13:57:03.717456 ==
6824 13:57:03.717538 DQS Delay:
6825 13:57:03.717619 DQS0 = 52, DQS1 = 60
6826 13:57:03.720889 DQM Delay:
6827 13:57:03.720968 DQM0 = 16, DQM1 = 13
6828 13:57:03.724264 DQ Delay:
6829 13:57:03.727479 DQ0 =20, DQ1 =12, DQ2 =0, DQ3 =16
6830 13:57:03.727553 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =16
6831 13:57:03.730945 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6832 13:57:03.734431 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6833 13:57:03.734505
6834 13:57:03.734591
6835 13:57:03.744171 [DQSOSCAuto] RK0, (LSB)MR18= 0x872e, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
6836 13:57:03.747300 CH1 RK0: MR19=C0C, MR18=872E
6837 13:57:03.754275 CH1_RK0: MR19=0xC0C, MR18=0x872E, DQSOSC=392, MR23=63, INC=384, DEC=256
6838 13:57:03.754352 ==
6839 13:57:03.757947 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 13:57:03.761211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 13:57:03.761292 ==
6842 13:57:03.764065 [Gating] SW mode calibration
6843 13:57:03.770317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6844 13:57:03.773976 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6845 13:57:03.780383 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 13:57:03.783699 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6847 13:57:03.787452 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 13:57:03.793856 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 13:57:03.797302 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 13:57:03.800435 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 13:57:03.807309 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 13:57:03.810608 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 13:57:03.814104 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 13:57:03.817403 Total UI for P1: 0, mck2ui 16
6855 13:57:03.820983 best dqsien dly found for B0: ( 0, 14, 24)
6856 13:57:03.824521 Total UI for P1: 0, mck2ui 16
6857 13:57:03.827073 best dqsien dly found for B1: ( 0, 14, 24)
6858 13:57:03.830257 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6859 13:57:03.834198 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6860 13:57:03.836924
6861 13:57:03.840638 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 13:57:03.843766 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 13:57:03.847212 [Gating] SW calibration Done
6864 13:57:03.847289 ==
6865 13:57:03.850334 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 13:57:03.853583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 13:57:03.853688 ==
6868 13:57:03.853790 RX Vref Scan: 0
6869 13:57:03.857069
6870 13:57:03.857144 RX Vref 0 -> 0, step: 1
6871 13:57:03.857206
6872 13:57:03.860330 RX Delay -410 -> 252, step: 16
6873 13:57:03.864035 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6874 13:57:03.870842 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6875 13:57:03.873584 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6876 13:57:03.877094 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6877 13:57:03.880533 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6878 13:57:03.887643 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6879 13:57:03.890461 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6880 13:57:03.893915 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6881 13:57:03.897249 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6882 13:57:03.903757 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6883 13:57:03.907053 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6884 13:57:03.910496 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6885 13:57:03.913723 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6886 13:57:03.920572 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6887 13:57:03.923802 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6888 13:57:03.927099 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6889 13:57:03.927172 ==
6890 13:57:03.930504 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 13:57:03.933510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 13:57:03.936797 ==
6893 13:57:03.936869 DQS Delay:
6894 13:57:03.936930 DQS0 = 51, DQS1 = 59
6895 13:57:03.940354 DQM Delay:
6896 13:57:03.940431 DQM0 = 17, DQM1 = 19
6897 13:57:03.944027 DQ Delay:
6898 13:57:03.944101 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6899 13:57:03.947155 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6900 13:57:03.950249 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6901 13:57:03.953790 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6902 13:57:03.953886
6903 13:57:03.953958
6904 13:57:03.957478 ==
6905 13:57:03.957595 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 13:57:03.963708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 13:57:03.963790 ==
6908 13:57:03.963853
6909 13:57:03.963920
6910 13:57:03.967591 TX Vref Scan disable
6911 13:57:03.967667 == TX Byte 0 ==
6912 13:57:03.970407 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6913 13:57:03.973477 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6914 13:57:03.977178 == TX Byte 1 ==
6915 13:57:03.980476 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6916 13:57:03.983805 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6917 13:57:03.987119 ==
6918 13:57:03.987193 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 13:57:03.993811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 13:57:03.993895 ==
6921 13:57:03.993959
6922 13:57:03.994018
6923 13:57:03.997047 TX Vref Scan disable
6924 13:57:03.997125 == TX Byte 0 ==
6925 13:57:04.000842 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6926 13:57:04.003842 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6927 13:57:04.007250 == TX Byte 1 ==
6928 13:57:04.010407 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6929 13:57:04.013766 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6930 13:57:04.013838
6931 13:57:04.017212 [DATLAT]
6932 13:57:04.017283 Freq=400, CH1 RK1
6933 13:57:04.017344
6934 13:57:04.020488 DATLAT Default: 0xe
6935 13:57:04.020592 0, 0xFFFF, sum = 0
6936 13:57:04.023860 1, 0xFFFF, sum = 0
6937 13:57:04.023947 2, 0xFFFF, sum = 0
6938 13:57:04.027453 3, 0xFFFF, sum = 0
6939 13:57:04.027525 4, 0xFFFF, sum = 0
6940 13:57:04.030550 5, 0xFFFF, sum = 0
6941 13:57:04.030623 6, 0xFFFF, sum = 0
6942 13:57:04.033755 7, 0xFFFF, sum = 0
6943 13:57:04.033826 8, 0xFFFF, sum = 0
6944 13:57:04.037201 9, 0xFFFF, sum = 0
6945 13:57:04.040868 10, 0xFFFF, sum = 0
6946 13:57:04.040939 11, 0xFFFF, sum = 0
6947 13:57:04.043699 12, 0xFFFF, sum = 0
6948 13:57:04.043772 13, 0x0, sum = 1
6949 13:57:04.047050 14, 0x0, sum = 2
6950 13:57:04.047124 15, 0x0, sum = 3
6951 13:57:04.047185 16, 0x0, sum = 4
6952 13:57:04.050516 best_step = 14
6953 13:57:04.050586
6954 13:57:04.050645 ==
6955 13:57:04.053936 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 13:57:04.057769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 13:57:04.057852 ==
6958 13:57:04.060989 RX Vref Scan: 0
6959 13:57:04.061061
6960 13:57:04.061128 RX Vref 0 -> 0, step: 1
6961 13:57:04.063768
6962 13:57:04.063840 RX Delay -359 -> 252, step: 8
6963 13:57:04.072464 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6964 13:57:04.076364 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6965 13:57:04.079026 iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480
6966 13:57:04.082222 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6967 13:57:04.088929 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6968 13:57:04.092026 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6969 13:57:04.095488 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6970 13:57:04.098767 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6971 13:57:04.105582 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6972 13:57:04.108616 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6973 13:57:04.112224 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6974 13:57:04.115736 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6975 13:57:04.122250 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6976 13:57:04.125532 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6977 13:57:04.128790 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6978 13:57:04.135391 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6979 13:57:04.135471 ==
6980 13:57:04.138924 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 13:57:04.142015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 13:57:04.142096 ==
6983 13:57:04.142160 DQS Delay:
6984 13:57:04.145385 DQS0 = 48, DQS1 = 56
6985 13:57:04.145466 DQM Delay:
6986 13:57:04.149235 DQM0 = 9, DQM1 = 9
6987 13:57:04.149315 DQ Delay:
6988 13:57:04.152004 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6989 13:57:04.155612 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6990 13:57:04.159322 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6991 13:57:04.162039 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6992 13:57:04.162119
6993 13:57:04.162181
6994 13:57:04.169107 [DQSOSCAuto] RK1, (LSB)MR18= 0x748a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6995 13:57:04.172255 CH1 RK1: MR19=C0C, MR18=748A
6996 13:57:04.179118 CH1_RK1: MR19=0xC0C, MR18=0x748A, DQSOSC=392, MR23=63, INC=384, DEC=256
6997 13:57:04.182474 [RxdqsGatingPostProcess] freq 400
6998 13:57:04.185729 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6999 13:57:04.189331 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 13:57:04.192217 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 13:57:04.195318 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 13:57:04.199171 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 13:57:04.202487 best DQS0 dly(2T, 0.5T) = (0, 10)
7004 13:57:04.205417 best DQS1 dly(2T, 0.5T) = (0, 10)
7005 13:57:04.208904 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7006 13:57:04.212615 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7007 13:57:04.215748 Pre-setting of DQS Precalculation
7008 13:57:04.218882 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7009 13:57:04.226060 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7010 13:57:04.236024 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7011 13:57:04.236124
7012 13:57:04.236202
7013 13:57:04.238849 [Calibration Summary] 800 Mbps
7014 13:57:04.238929 CH 0, Rank 0
7015 13:57:04.238993 SW Impedance : PASS
7016 13:57:04.242614 DUTY Scan : NO K
7017 13:57:04.245954 ZQ Calibration : PASS
7018 13:57:04.246033 Jitter Meter : NO K
7019 13:57:04.249036 CBT Training : PASS
7020 13:57:04.252567 Write leveling : PASS
7021 13:57:04.252648 RX DQS gating : PASS
7022 13:57:04.255655 RX DQ/DQS(RDDQC) : PASS
7023 13:57:04.259179 TX DQ/DQS : PASS
7024 13:57:04.259259 RX DATLAT : PASS
7025 13:57:04.262344 RX DQ/DQS(Engine): PASS
7026 13:57:04.265831 TX OE : NO K
7027 13:57:04.265911 All Pass.
7028 13:57:04.265974
7029 13:57:04.266032 CH 0, Rank 1
7030 13:57:04.269012 SW Impedance : PASS
7031 13:57:04.272412 DUTY Scan : NO K
7032 13:57:04.272492 ZQ Calibration : PASS
7033 13:57:04.275914 Jitter Meter : NO K
7034 13:57:04.279556 CBT Training : PASS
7035 13:57:04.279639 Write leveling : NO K
7036 13:57:04.282340 RX DQS gating : PASS
7037 13:57:04.282488 RX DQ/DQS(RDDQC) : PASS
7038 13:57:04.285706 TX DQ/DQS : PASS
7039 13:57:04.288959 RX DATLAT : PASS
7040 13:57:04.289038 RX DQ/DQS(Engine): PASS
7041 13:57:04.292731 TX OE : NO K
7042 13:57:04.292829 All Pass.
7043 13:57:04.292906
7044 13:57:04.295940 CH 1, Rank 0
7045 13:57:04.296020 SW Impedance : PASS
7046 13:57:04.298963 DUTY Scan : NO K
7047 13:57:04.302844 ZQ Calibration : PASS
7048 13:57:04.302922 Jitter Meter : NO K
7049 13:57:04.305768 CBT Training : PASS
7050 13:57:04.308899 Write leveling : PASS
7051 13:57:04.308973 RX DQS gating : PASS
7052 13:57:04.312635 RX DQ/DQS(RDDQC) : PASS
7053 13:57:04.315543 TX DQ/DQS : PASS
7054 13:57:04.315622 RX DATLAT : PASS
7055 13:57:04.319183 RX DQ/DQS(Engine): PASS
7056 13:57:04.319286 TX OE : NO K
7057 13:57:04.323186 All Pass.
7058 13:57:04.323268
7059 13:57:04.323330 CH 1, Rank 1
7060 13:57:04.325664 SW Impedance : PASS
7061 13:57:04.325733 DUTY Scan : NO K
7062 13:57:04.329506 ZQ Calibration : PASS
7063 13:57:04.332234 Jitter Meter : NO K
7064 13:57:04.332312 CBT Training : PASS
7065 13:57:04.336212 Write leveling : NO K
7066 13:57:04.339178 RX DQS gating : PASS
7067 13:57:04.339284 RX DQ/DQS(RDDQC) : PASS
7068 13:57:04.342380 TX DQ/DQS : PASS
7069 13:57:04.345956 RX DATLAT : PASS
7070 13:57:04.346066 RX DQ/DQS(Engine): PASS
7071 13:57:04.349015 TX OE : NO K
7072 13:57:04.349104 All Pass.
7073 13:57:04.349173
7074 13:57:04.352818 DramC Write-DBI off
7075 13:57:04.355980 PER_BANK_REFRESH: Hybrid Mode
7076 13:57:04.356101 TX_TRACKING: ON
7077 13:57:04.365847 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7078 13:57:04.369236 [FAST_K] Save calibration result to emmc
7079 13:57:04.372823 dramc_set_vcore_voltage set vcore to 725000
7080 13:57:04.375805 Read voltage for 1600, 0
7081 13:57:04.375963 Vio18 = 0
7082 13:57:04.376084 Vcore = 725000
7083 13:57:04.379261 Vdram = 0
7084 13:57:04.379415 Vddq = 0
7085 13:57:04.379565 Vmddr = 0
7086 13:57:04.386238 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7087 13:57:04.389834 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7088 13:57:04.392896 MEM_TYPE=3, freq_sel=13
7089 13:57:04.396078 sv_algorithm_assistance_LP4_3733
7090 13:57:04.399322 ============ PULL DRAM RESETB DOWN ============
7091 13:57:04.403254 ========== PULL DRAM RESETB DOWN end =========
7092 13:57:04.409842 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7093 13:57:04.412844 ===================================
7094 13:57:04.413476 LPDDR4 DRAM CONFIGURATION
7095 13:57:04.416040 ===================================
7096 13:57:04.420229 EX_ROW_EN[0] = 0x0
7097 13:57:04.423196 EX_ROW_EN[1] = 0x0
7098 13:57:04.423607 LP4Y_EN = 0x0
7099 13:57:04.426539 WORK_FSP = 0x1
7100 13:57:04.426951 WL = 0x5
7101 13:57:04.429474 RL = 0x5
7102 13:57:04.429983 BL = 0x2
7103 13:57:04.433263 RPST = 0x0
7104 13:57:04.433672 RD_PRE = 0x0
7105 13:57:04.436611 WR_PRE = 0x1
7106 13:57:04.437025 WR_PST = 0x1
7107 13:57:04.439710 DBI_WR = 0x0
7108 13:57:04.440122 DBI_RD = 0x0
7109 13:57:04.442819 OTF = 0x1
7110 13:57:04.446857 ===================================
7111 13:57:04.449352 ===================================
7112 13:57:04.449705 ANA top config
7113 13:57:04.452637 ===================================
7114 13:57:04.456322 DLL_ASYNC_EN = 0
7115 13:57:04.459251 ALL_SLAVE_EN = 0
7116 13:57:04.459539 NEW_RANK_MODE = 1
7117 13:57:04.462741 DLL_IDLE_MODE = 1
7118 13:57:04.466349 LP45_APHY_COMB_EN = 1
7119 13:57:04.469197 TX_ODT_DIS = 0
7120 13:57:04.472861 NEW_8X_MODE = 1
7121 13:57:04.475970 ===================================
7122 13:57:04.476191 ===================================
7123 13:57:04.481525 data_rate = 3200
7124 13:57:04.482728 CKR = 1
7125 13:57:04.486059 DQ_P2S_RATIO = 8
7126 13:57:04.489789 ===================================
7127 13:57:04.492798 CA_P2S_RATIO = 8
7128 13:57:04.496921 DQ_CA_OPEN = 0
7129 13:57:04.499463 DQ_SEMI_OPEN = 0
7130 13:57:04.499683 CA_SEMI_OPEN = 0
7131 13:57:04.502786 CA_FULL_RATE = 0
7132 13:57:04.506636 DQ_CKDIV4_EN = 0
7133 13:57:04.509558 CA_CKDIV4_EN = 0
7134 13:57:04.513003 CA_PREDIV_EN = 0
7135 13:57:04.515908 PH8_DLY = 12
7136 13:57:04.516085 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7137 13:57:04.519158 DQ_AAMCK_DIV = 4
7138 13:57:04.523115 CA_AAMCK_DIV = 4
7139 13:57:04.526077 CA_ADMCK_DIV = 4
7140 13:57:04.529593 DQ_TRACK_CA_EN = 0
7141 13:57:04.532564 CA_PICK = 1600
7142 13:57:04.536122 CA_MCKIO = 1600
7143 13:57:04.536306 MCKIO_SEMI = 0
7144 13:57:04.539170 PLL_FREQ = 3068
7145 13:57:04.543230 DQ_UI_PI_RATIO = 32
7146 13:57:04.546440 CA_UI_PI_RATIO = 0
7147 13:57:04.549249 ===================================
7148 13:57:04.552812 ===================================
7149 13:57:04.556027 memory_type:LPDDR4
7150 13:57:04.556205 GP_NUM : 10
7151 13:57:04.559978 SRAM_EN : 1
7152 13:57:04.560162 MD32_EN : 0
7153 13:57:04.562467 ===================================
7154 13:57:04.565796 [ANA_INIT] >>>>>>>>>>>>>>
7155 13:57:04.569224 <<<<<< [CONFIGURE PHASE]: ANA_TX
7156 13:57:04.572855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7157 13:57:04.575955 ===================================
7158 13:57:04.579293 data_rate = 3200,PCW = 0X7600
7159 13:57:04.582428 ===================================
7160 13:57:04.585946 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7161 13:57:04.589273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 13:57:04.595874 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 13:57:04.603192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7164 13:57:04.606095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7165 13:57:04.609355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7166 13:57:04.609533 [ANA_INIT] flow start
7167 13:57:04.612910 [ANA_INIT] PLL >>>>>>>>
7168 13:57:04.615885 [ANA_INIT] PLL <<<<<<<<
7169 13:57:04.616063 [ANA_INIT] MIDPI >>>>>>>>
7170 13:57:04.619255 [ANA_INIT] MIDPI <<<<<<<<
7171 13:57:04.622895 [ANA_INIT] DLL >>>>>>>>
7172 13:57:04.623073 [ANA_INIT] DLL <<<<<<<<
7173 13:57:04.626057 [ANA_INIT] flow end
7174 13:57:04.629259 ============ LP4 DIFF to SE enter ============
7175 13:57:04.632553 ============ LP4 DIFF to SE exit ============
7176 13:57:04.635921 [ANA_INIT] <<<<<<<<<<<<<
7177 13:57:04.639232 [Flow] Enable top DCM control >>>>>
7178 13:57:04.642652 [Flow] Enable top DCM control <<<<<
7179 13:57:04.645983 Enable DLL master slave shuffle
7180 13:57:04.652771 ==============================================================
7181 13:57:04.653015 Gating Mode config
7182 13:57:04.659506 ==============================================================
7183 13:57:04.659762 Config description:
7184 13:57:04.669615 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7185 13:57:04.676164 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7186 13:57:04.682732 SELPH_MODE 0: By rank 1: By Phase
7187 13:57:04.686130 ==============================================================
7188 13:57:04.690083 GAT_TRACK_EN = 1
7189 13:57:04.692866 RX_GATING_MODE = 2
7190 13:57:04.696411 RX_GATING_TRACK_MODE = 2
7191 13:57:04.700235 SELPH_MODE = 1
7192 13:57:04.702796 PICG_EARLY_EN = 1
7193 13:57:04.706364 VALID_LAT_VALUE = 1
7194 13:57:04.709861 ==============================================================
7195 13:57:04.713064 Enter into Gating configuration >>>>
7196 13:57:04.716297 Exit from Gating configuration <<<<
7197 13:57:04.720050 Enter into DVFS_PRE_config >>>>>
7198 13:57:04.732722 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7199 13:57:04.736224 Exit from DVFS_PRE_config <<<<<
7200 13:57:04.736304 Enter into PICG configuration >>>>
7201 13:57:04.739882 Exit from PICG configuration <<<<
7202 13:57:04.743340 [RX_INPUT] configuration >>>>>
7203 13:57:04.746236 [RX_INPUT] configuration <<<<<
7204 13:57:04.752960 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7205 13:57:04.756091 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7206 13:57:04.762945 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7207 13:57:04.769188 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7208 13:57:04.776901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7209 13:57:04.783059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7210 13:57:04.786611 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7211 13:57:04.789771 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7212 13:57:04.793280 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7213 13:57:04.799796 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7214 13:57:04.803374 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7215 13:57:04.806442 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 13:57:04.809836 ===================================
7217 13:57:04.812886 LPDDR4 DRAM CONFIGURATION
7218 13:57:04.816848 ===================================
7219 13:57:04.817314 EX_ROW_EN[0] = 0x0
7220 13:57:04.819839 EX_ROW_EN[1] = 0x0
7221 13:57:04.823236 LP4Y_EN = 0x0
7222 13:57:04.823643 WORK_FSP = 0x1
7223 13:57:04.826633 WL = 0x5
7224 13:57:04.827040 RL = 0x5
7225 13:57:04.829748 BL = 0x2
7226 13:57:04.830174 RPST = 0x0
7227 13:57:04.833114 RD_PRE = 0x0
7228 13:57:04.833525 WR_PRE = 0x1
7229 13:57:04.836445 WR_PST = 0x1
7230 13:57:04.836854 DBI_WR = 0x0
7231 13:57:04.839916 DBI_RD = 0x0
7232 13:57:04.840325 OTF = 0x1
7233 13:57:04.843774 ===================================
7234 13:57:04.846762 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7235 13:57:04.853266 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7236 13:57:04.856216 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 13:57:04.859560 ===================================
7238 13:57:04.862911 LPDDR4 DRAM CONFIGURATION
7239 13:57:04.866427 ===================================
7240 13:57:04.866843 EX_ROW_EN[0] = 0x10
7241 13:57:04.870119 EX_ROW_EN[1] = 0x0
7242 13:57:04.870472 LP4Y_EN = 0x0
7243 13:57:04.872871 WORK_FSP = 0x1
7244 13:57:04.873360 WL = 0x5
7245 13:57:04.876251 RL = 0x5
7246 13:57:04.879850 BL = 0x2
7247 13:57:04.880291 RPST = 0x0
7248 13:57:04.883445 RD_PRE = 0x0
7249 13:57:04.883832 WR_PRE = 0x1
7250 13:57:04.886023 WR_PST = 0x1
7251 13:57:04.886519 DBI_WR = 0x0
7252 13:57:04.889304 DBI_RD = 0x0
7253 13:57:04.889662 OTF = 0x1
7254 13:57:04.892551 ===================================
7255 13:57:04.899649 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7256 13:57:04.900039 ==
7257 13:57:04.902847 Dram Type= 6, Freq= 0, CH_0, rank 0
7258 13:57:04.906362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7259 13:57:04.906758 ==
7260 13:57:04.909960 [Duty_Offset_Calibration]
7261 13:57:04.913093 B0:2 B1:-1 CA:1
7262 13:57:04.913382
7263 13:57:04.916001 [DutyScan_Calibration_Flow] k_type=0
7264 13:57:04.923705
7265 13:57:04.923994 ==CLK 0==
7266 13:57:04.927428 Final CLK duty delay cell = -4
7267 13:57:04.930562 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7268 13:57:04.933219 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7269 13:57:04.937040 [-4] AVG Duty = 4937%(X100)
7270 13:57:04.937331
7271 13:57:04.940625 CH0 CLK Duty spec in!! Max-Min= 187%
7272 13:57:04.943697 [DutyScan_Calibration_Flow] ====Done====
7273 13:57:04.943999
7274 13:57:04.946948 [DutyScan_Calibration_Flow] k_type=1
7275 13:57:04.963234
7276 13:57:04.963757 ==DQS 0 ==
7277 13:57:04.966341 Final DQS duty delay cell = 0
7278 13:57:04.969949 [0] MAX Duty = 5125%(X100), DQS PI = 56
7279 13:57:04.973522 [0] MIN Duty = 5000%(X100), DQS PI = 16
7280 13:57:04.976661 [0] AVG Duty = 5062%(X100)
7281 13:57:04.977069
7282 13:57:04.977390 ==DQS 1 ==
7283 13:57:04.980167 Final DQS duty delay cell = -4
7284 13:57:04.983133 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7285 13:57:04.986308 [-4] MIN Duty = 5031%(X100), DQS PI = 8
7286 13:57:04.989446 [-4] AVG Duty = 5062%(X100)
7287 13:57:04.989855
7288 13:57:04.993001 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7289 13:57:04.993435
7290 13:57:04.996301 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7291 13:57:04.999750 [DutyScan_Calibration_Flow] ====Done====
7292 13:57:05.000160
7293 13:57:05.003020 [DutyScan_Calibration_Flow] k_type=3
7294 13:57:05.020338
7295 13:57:05.020634 ==DQM 0 ==
7296 13:57:05.023615 Final DQM duty delay cell = 0
7297 13:57:05.026736 [0] MAX Duty = 5000%(X100), DQS PI = 20
7298 13:57:05.029798 [0] MIN Duty = 4875%(X100), DQS PI = 4
7299 13:57:05.029973 [0] AVG Duty = 4937%(X100)
7300 13:57:05.033612
7301 13:57:05.033787 ==DQM 1 ==
7302 13:57:05.037248 Final DQM duty delay cell = 0
7303 13:57:05.040680 [0] MAX Duty = 5187%(X100), DQS PI = 58
7304 13:57:05.043399 [0] MIN Duty = 4969%(X100), DQS PI = 18
7305 13:57:05.043575 [0] AVG Duty = 5078%(X100)
7306 13:57:05.047038
7307 13:57:05.050524 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7308 13:57:05.050710
7309 13:57:05.053595 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7310 13:57:05.057238 [DutyScan_Calibration_Flow] ====Done====
7311 13:57:05.057451
7312 13:57:05.059873 [DutyScan_Calibration_Flow] k_type=2
7313 13:57:05.076591
7314 13:57:05.076767 ==DQ 0 ==
7315 13:57:05.080180 Final DQ duty delay cell = -4
7316 13:57:05.083047 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7317 13:57:05.086302 [-4] MIN Duty = 4844%(X100), DQS PI = 28
7318 13:57:05.089977 [-4] AVG Duty = 4922%(X100)
7319 13:57:05.090136
7320 13:57:05.090267 ==DQ 1 ==
7321 13:57:05.093047 Final DQ duty delay cell = 0
7322 13:57:05.096359 [0] MAX Duty = 5031%(X100), DQS PI = 30
7323 13:57:05.099645 [0] MIN Duty = 4907%(X100), DQS PI = 18
7324 13:57:05.102994 [0] AVG Duty = 4969%(X100)
7325 13:57:05.103171
7326 13:57:05.106303 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7327 13:57:05.106479
7328 13:57:05.109279 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7329 13:57:05.112701 [DutyScan_Calibration_Flow] ====Done====
7330 13:57:05.112895 ==
7331 13:57:05.116853 Dram Type= 6, Freq= 0, CH_1, rank 0
7332 13:57:05.119333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7333 13:57:05.119493 ==
7334 13:57:05.122964 [Duty_Offset_Calibration]
7335 13:57:05.123125 B0:1 B1:1 CA:2
7336 13:57:05.123285
7337 13:57:05.126024 [DutyScan_Calibration_Flow] k_type=0
7338 13:57:05.136600
7339 13:57:05.136767 ==CLK 0==
7340 13:57:05.140689 Final CLK duty delay cell = 0
7341 13:57:05.143543 [0] MAX Duty = 5187%(X100), DQS PI = 24
7342 13:57:05.146658 [0] MIN Duty = 4938%(X100), DQS PI = 58
7343 13:57:05.146821 [0] AVG Duty = 5062%(X100)
7344 13:57:05.150154
7345 13:57:05.153481 CH1 CLK Duty spec in!! Max-Min= 249%
7346 13:57:05.157051 [DutyScan_Calibration_Flow] ====Done====
7347 13:57:05.157205
7348 13:57:05.159904 [DutyScan_Calibration_Flow] k_type=1
7349 13:57:05.177087
7350 13:57:05.177289 ==DQS 0 ==
7351 13:57:05.180119 Final DQS duty delay cell = 0
7352 13:57:05.183454 [0] MAX Duty = 5062%(X100), DQS PI = 22
7353 13:57:05.186985 [0] MIN Duty = 4813%(X100), DQS PI = 50
7354 13:57:05.189850 [0] AVG Duty = 4937%(X100)
7355 13:57:05.190102
7356 13:57:05.190297 ==DQS 1 ==
7357 13:57:05.193644 Final DQS duty delay cell = 0
7358 13:57:05.197362 [0] MAX Duty = 5062%(X100), DQS PI = 58
7359 13:57:05.200115 [0] MIN Duty = 4938%(X100), DQS PI = 12
7360 13:57:05.200302 [0] AVG Duty = 5000%(X100)
7361 13:57:05.203345
7362 13:57:05.206525 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7363 13:57:05.206755
7364 13:57:05.209969 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7365 13:57:05.213570 [DutyScan_Calibration_Flow] ====Done====
7366 13:57:05.213785
7367 13:57:05.216768 [DutyScan_Calibration_Flow] k_type=3
7368 13:57:05.233914
7369 13:57:05.234322 ==DQM 0 ==
7370 13:57:05.236790 Final DQM duty delay cell = 0
7371 13:57:05.240264 [0] MAX Duty = 5124%(X100), DQS PI = 18
7372 13:57:05.243565 [0] MIN Duty = 4876%(X100), DQS PI = 46
7373 13:57:05.243976 [0] AVG Duty = 5000%(X100)
7374 13:57:05.246784
7375 13:57:05.247305 ==DQM 1 ==
7376 13:57:05.250886 Final DQM duty delay cell = 0
7377 13:57:05.253860 [0] MAX Duty = 5125%(X100), DQS PI = 10
7378 13:57:05.256665 [0] MIN Duty = 4875%(X100), DQS PI = 20
7379 13:57:05.259985 [0] AVG Duty = 5000%(X100)
7380 13:57:05.260297
7381 13:57:05.263534 CH1 DQM 0 Duty spec in!! Max-Min= 248%
7382 13:57:05.263855
7383 13:57:05.266625 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7384 13:57:05.270013 [DutyScan_Calibration_Flow] ====Done====
7385 13:57:05.270231
7386 13:57:05.273321 [DutyScan_Calibration_Flow] k_type=2
7387 13:57:05.290202
7388 13:57:05.290303 ==DQ 0 ==
7389 13:57:05.294078 Final DQ duty delay cell = 0
7390 13:57:05.297416 [0] MAX Duty = 5125%(X100), DQS PI = 22
7391 13:57:05.300259 [0] MIN Duty = 4907%(X100), DQS PI = 52
7392 13:57:05.300809 [0] AVG Duty = 5016%(X100)
7393 13:57:05.303950
7394 13:57:05.304322 ==DQ 1 ==
7395 13:57:05.307718 Final DQ duty delay cell = 0
7396 13:57:05.310592 [0] MAX Duty = 5093%(X100), DQS PI = 6
7397 13:57:05.314055 [0] MIN Duty = 5031%(X100), DQS PI = 0
7398 13:57:05.314662 [0] AVG Duty = 5062%(X100)
7399 13:57:05.315021
7400 13:57:05.317247 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7401 13:57:05.317797
7402 13:57:05.320691 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7403 13:57:05.324319 [DutyScan_Calibration_Flow] ====Done====
7404 13:57:05.329768 nWR fixed to 30
7405 13:57:05.332620 [ModeRegInit_LP4] CH0 RK0
7406 13:57:05.333141 [ModeRegInit_LP4] CH0 RK1
7407 13:57:05.335953 [ModeRegInit_LP4] CH1 RK0
7408 13:57:05.339280 [ModeRegInit_LP4] CH1 RK1
7409 13:57:05.339641 match AC timing 5
7410 13:57:05.346020 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7411 13:57:05.349241 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7412 13:57:05.352849 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7413 13:57:05.359056 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7414 13:57:05.362687 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7415 13:57:05.363115 [MiockJmeterHQA]
7416 13:57:05.363424
7417 13:57:05.365782 [DramcMiockJmeter] u1RxGatingPI = 0
7418 13:57:05.369102 0 : 4252, 4027
7419 13:57:05.369379 4 : 4257, 4029
7420 13:57:05.372230 8 : 4365, 4140
7421 13:57:05.372643 12 : 4252, 4027
7422 13:57:05.375737 16 : 4258, 4029
7423 13:57:05.376083 20 : 4363, 4137
7424 13:57:05.376377 24 : 4258, 4029
7425 13:57:05.379744 28 : 4252, 4026
7426 13:57:05.380069 32 : 4252, 4027
7427 13:57:05.382933 36 : 4255, 4029
7428 13:57:05.383271 40 : 4250, 4027
7429 13:57:05.385844 44 : 4253, 4027
7430 13:57:05.386248 48 : 4368, 4140
7431 13:57:05.389624 52 : 4250, 4026
7432 13:57:05.389985 56 : 4257, 4034
7433 13:57:05.390223 60 : 4250, 4027
7434 13:57:05.392802 64 : 4255, 4030
7435 13:57:05.393161 68 : 4250, 4027
7436 13:57:05.395901 72 : 4250, 4026
7437 13:57:05.396233 76 : 4252, 4029
7438 13:57:05.398722 80 : 4360, 4138
7439 13:57:05.399085 84 : 4361, 4138
7440 13:57:05.402155 88 : 4368, 4143
7441 13:57:05.402491 92 : 4252, 4030
7442 13:57:05.402734 96 : 4252, 3153
7443 13:57:05.406436 100 : 4361, 0
7444 13:57:05.406748 104 : 4249, 0
7445 13:57:05.409334 108 : 4249, 0
7446 13:57:05.409651 112 : 4360, 0
7447 13:57:05.409925 116 : 4250, 0
7448 13:57:05.412273 120 : 4366, 0
7449 13:57:05.412563 124 : 4363, 0
7450 13:57:05.415430 128 : 4253, 0
7451 13:57:05.415652 132 : 4252, 0
7452 13:57:05.415828 136 : 4361, 0
7453 13:57:05.418983 140 : 4363, 0
7454 13:57:05.419225 144 : 4249, 0
7455 13:57:05.419413 148 : 4252, 0
7456 13:57:05.422458 152 : 4367, 0
7457 13:57:05.422716 156 : 4250, 0
7458 13:57:05.425606 160 : 4250, 0
7459 13:57:05.425844 164 : 4252, 0
7460 13:57:05.426027 168 : 4366, 0
7461 13:57:05.428898 172 : 4250, 0
7462 13:57:05.429169 176 : 4365, 0
7463 13:57:05.432229 180 : 4253, 0
7464 13:57:05.432449 184 : 4252, 0
7465 13:57:05.432625 188 : 4250, 0
7466 13:57:05.435665 192 : 4249, 0
7467 13:57:05.435918 196 : 4250, 0
7468 13:57:05.436122 200 : 4253, 0
7469 13:57:05.438962 204 : 4250, 0
7470 13:57:05.439233 208 : 4253, 0
7471 13:57:05.442369 212 : 4250, 104
7472 13:57:05.442612 216 : 4368, 3907
7473 13:57:05.445790 220 : 4250, 4027
7474 13:57:05.446019 224 : 4252, 4029
7475 13:57:05.448847 228 : 4361, 4137
7476 13:57:05.449089 232 : 4250, 4027
7477 13:57:05.452037 236 : 4365, 4140
7478 13:57:05.452291 240 : 4249, 4027
7479 13:57:05.452502 244 : 4360, 4138
7480 13:57:05.455591 248 : 4253, 4029
7481 13:57:05.455876 252 : 4360, 4138
7482 13:57:05.459628 256 : 4254, 4030
7483 13:57:05.459885 260 : 4250, 4027
7484 13:57:05.461957 264 : 4255, 4029
7485 13:57:05.462156 268 : 4255, 4032
7486 13:57:05.465294 272 : 4253, 4029
7487 13:57:05.465514 276 : 4250, 4027
7488 13:57:05.468952 280 : 4252, 4029
7489 13:57:05.469202 284 : 4257, 4034
7490 13:57:05.472175 288 : 4252, 4030
7491 13:57:05.472403 292 : 4250, 4027
7492 13:57:05.472588 296 : 4250, 4026
7493 13:57:05.475659 300 : 4255, 4029
7494 13:57:05.476051 304 : 4365, 4140
7495 13:57:05.479432 308 : 4363, 4140
7496 13:57:05.479965 312 : 4252, 4029
7497 13:57:05.482193 316 : 4363, 4139
7498 13:57:05.482717 320 : 4254, 4030
7499 13:57:05.485537 324 : 4361, 4137
7500 13:57:05.486011 328 : 4250, 4027
7501 13:57:05.488893 332 : 4250, 3007
7502 13:57:05.489307 336 : 4257, 63
7503 13:57:05.489720
7504 13:57:05.493059 MIOCK jitter meter ch=0
7505 13:57:05.493467
7506 13:57:05.495591 1T = (336-100) = 236 dly cells
7507 13:57:05.498993 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7508 13:57:05.499403 ==
7509 13:57:05.502004 Dram Type= 6, Freq= 0, CH_0, rank 0
7510 13:57:05.509202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7511 13:57:05.509611 ==
7512 13:57:05.512340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7513 13:57:05.518745 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7514 13:57:05.521954 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7515 13:57:05.529179 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7516 13:57:05.537145 [CA 0] Center 44 (14~75) winsize 62
7517 13:57:05.540376 [CA 1] Center 44 (14~74) winsize 61
7518 13:57:05.543706 [CA 2] Center 39 (10~68) winsize 59
7519 13:57:05.547270 [CA 3] Center 39 (10~68) winsize 59
7520 13:57:05.550023 [CA 4] Center 37 (7~67) winsize 61
7521 13:57:05.553603 [CA 5] Center 37 (7~67) winsize 61
7522 13:57:05.553955
7523 13:57:05.556854 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7524 13:57:05.557143
7525 13:57:05.560317 [CATrainingPosCal] consider 1 rank data
7526 13:57:05.563439 u2DelayCellTimex100 = 275/100 ps
7527 13:57:05.566712 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7528 13:57:05.573659 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7529 13:57:05.576556 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7530 13:57:05.580186 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7531 13:57:05.583580 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7532 13:57:05.587247 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7533 13:57:05.587475
7534 13:57:05.590143 CA PerBit enable=1, Macro0, CA PI delay=37
7535 13:57:05.590364
7536 13:57:05.593497 [CBTSetCACLKResult] CA Dly = 37
7537 13:57:05.596731 CS Dly: 11 (0~42)
7538 13:57:05.600730 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7539 13:57:05.604119 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7540 13:57:05.604566 ==
7541 13:57:05.607041 Dram Type= 6, Freq= 0, CH_0, rank 1
7542 13:57:05.610355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 13:57:05.610899 ==
7544 13:57:05.617062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7545 13:57:05.620626 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7546 13:57:05.627263 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7547 13:57:05.630389 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7548 13:57:05.640681 [CA 0] Center 44 (14~74) winsize 61
7549 13:57:05.644364 [CA 1] Center 44 (14~74) winsize 61
7550 13:57:05.647582 [CA 2] Center 39 (10~69) winsize 60
7551 13:57:05.650312 [CA 3] Center 39 (10~68) winsize 59
7552 13:57:05.654076 [CA 4] Center 37 (8~67) winsize 60
7553 13:57:05.657469 [CA 5] Center 37 (7~67) winsize 61
7554 13:57:05.657603
7555 13:57:05.660454 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7556 13:57:05.660611
7557 13:57:05.663914 [CATrainingPosCal] consider 2 rank data
7558 13:57:05.666927 u2DelayCellTimex100 = 275/100 ps
7559 13:57:05.670351 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7560 13:57:05.676966 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7561 13:57:05.680504 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7562 13:57:05.683593 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7563 13:57:05.687120 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7564 13:57:05.690595 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7565 13:57:05.690729
7566 13:57:05.693705 CA PerBit enable=1, Macro0, CA PI delay=37
7567 13:57:05.693835
7568 13:57:05.696932 [CBTSetCACLKResult] CA Dly = 37
7569 13:57:05.700420 CS Dly: 12 (0~44)
7570 13:57:05.704032 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7571 13:57:05.707192 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7572 13:57:05.707345
7573 13:57:05.710621 ----->DramcWriteLeveling(PI) begin...
7574 13:57:05.710776 ==
7575 13:57:05.714285 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 13:57:05.717261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 13:57:05.720506 ==
7578 13:57:05.720672 Write leveling (Byte 0): 32 => 32
7579 13:57:05.723655 Write leveling (Byte 1): 28 => 28
7580 13:57:05.726874 DramcWriteLeveling(PI) end<-----
7581 13:57:05.727034
7582 13:57:05.727162 ==
7583 13:57:05.730283 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 13:57:05.737192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 13:57:05.737428 ==
7586 13:57:05.737593 [Gating] SW mode calibration
7587 13:57:05.747357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7588 13:57:05.750461 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7589 13:57:05.757429 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 13:57:05.760498 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 13:57:05.764122 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 13:57:05.767196 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 13:57:05.773595 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7594 13:57:05.777134 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7595 13:57:05.780952 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7596 13:57:05.787411 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 13:57:05.791247 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 13:57:05.794220 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 13:57:05.800863 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 13:57:05.804176 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 13:57:05.807658 1 5 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7602 13:57:05.814658 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7603 13:57:05.817290 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7604 13:57:05.821115 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 13:57:05.827667 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 13:57:05.830750 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 13:57:05.834231 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 13:57:05.840924 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 13:57:05.844066 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7610 13:57:05.847682 1 6 20 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
7611 13:57:05.850982 1 6 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7612 13:57:05.857996 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 13:57:05.860740 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 13:57:05.863810 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 13:57:05.870635 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 13:57:05.874512 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 13:57:05.877402 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 13:57:05.883754 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7619 13:57:05.887337 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7620 13:57:05.890662 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 13:57:05.897457 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 13:57:05.900646 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 13:57:05.904157 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 13:57:05.910425 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 13:57:05.913811 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 13:57:05.917280 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 13:57:05.923832 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 13:57:05.927561 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 13:57:05.930527 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 13:57:05.937503 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 13:57:05.940682 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 13:57:05.944152 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 13:57:05.951009 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7634 13:57:05.954135 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7635 13:57:05.957485 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 13:57:05.961786 Total UI for P1: 0, mck2ui 16
7637 13:57:05.964583 best dqsien dly found for B0: ( 1, 9, 18)
7638 13:57:05.967797 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 13:57:05.970517 Total UI for P1: 0, mck2ui 16
7640 13:57:05.974044 best dqsien dly found for B1: ( 1, 9, 22)
7641 13:57:05.977465 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7642 13:57:05.980911 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7643 13:57:05.983800
7644 13:57:05.987088 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7645 13:57:05.990750 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7646 13:57:05.993979 [Gating] SW calibration Done
7647 13:57:05.994548 ==
7648 13:57:05.997362 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 13:57:06.000870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 13:57:06.001317 ==
7651 13:57:06.001781 RX Vref Scan: 0
7652 13:57:06.004106
7653 13:57:06.004639 RX Vref 0 -> 0, step: 1
7654 13:57:06.005102
7655 13:57:06.007657 RX Delay 0 -> 252, step: 8
7656 13:57:06.011026 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7657 13:57:06.014152 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7658 13:57:06.020577 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7659 13:57:06.023946 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7660 13:57:06.027288 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7661 13:57:06.030810 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7662 13:57:06.034807 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7663 13:57:06.037986 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7664 13:57:06.044319 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7665 13:57:06.047387 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7666 13:57:06.050599 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7667 13:57:06.053944 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7668 13:57:06.057312 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7669 13:57:06.063869 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7670 13:57:06.067109 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7671 13:57:06.070471 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7672 13:57:06.070901 ==
7673 13:57:06.074376 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 13:57:06.077393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 13:57:06.080727 ==
7676 13:57:06.081077 DQS Delay:
7677 13:57:06.081458 DQS0 = 0, DQS1 = 0
7678 13:57:06.084139 DQM Delay:
7679 13:57:06.084405 DQM0 = 132, DQM1 = 125
7680 13:57:06.087089 DQ Delay:
7681 13:57:06.090454 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7682 13:57:06.094066 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7683 13:57:06.097029 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7684 13:57:06.100816 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7685 13:57:06.101086
7686 13:57:06.101297
7687 13:57:06.101489 ==
7688 13:57:06.103658 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 13:57:06.106775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 13:57:06.107137 ==
7691 13:57:06.107419
7692 13:57:06.110253
7693 13:57:06.110517 TX Vref Scan disable
7694 13:57:06.113678 == TX Byte 0 ==
7695 13:57:06.117392 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7696 13:57:06.120414 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7697 13:57:06.123631 == TX Byte 1 ==
7698 13:57:06.126707 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7699 13:57:06.130079 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7700 13:57:06.130487 ==
7701 13:57:06.133599 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 13:57:06.140661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 13:57:06.140911 ==
7704 13:57:06.153304
7705 13:57:06.156607 TX Vref early break, caculate TX vref
7706 13:57:06.159908 TX Vref=16, minBit 1, minWin=21, winSum=360
7707 13:57:06.163464 TX Vref=18, minBit 7, minWin=21, winSum=371
7708 13:57:06.166749 TX Vref=20, minBit 0, minWin=22, winSum=376
7709 13:57:06.170114 TX Vref=22, minBit 0, minWin=23, winSum=384
7710 13:57:06.173057 TX Vref=24, minBit 4, minWin=23, winSum=399
7711 13:57:06.180521 TX Vref=26, minBit 1, minWin=24, winSum=408
7712 13:57:06.183614 TX Vref=28, minBit 1, minWin=24, winSum=414
7713 13:57:06.186717 TX Vref=30, minBit 1, minWin=25, winSum=419
7714 13:57:06.190272 TX Vref=32, minBit 4, minWin=24, winSum=410
7715 13:57:06.193353 TX Vref=34, minBit 4, minWin=23, winSum=401
7716 13:57:06.196493 TX Vref=36, minBit 0, minWin=23, winSum=389
7717 13:57:06.203259 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 30
7718 13:57:06.203629
7719 13:57:06.206493 Final TX Range 0 Vref 30
7720 13:57:06.206807
7721 13:57:06.207087 ==
7722 13:57:06.209546 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 13:57:06.213601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 13:57:06.213870 ==
7725 13:57:06.214082
7726 13:57:06.214275
7727 13:57:06.216268 TX Vref Scan disable
7728 13:57:06.223823 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7729 13:57:06.224132 == TX Byte 0 ==
7730 13:57:06.226270 u2DelayCellOfst[0]=14 cells (4 PI)
7731 13:57:06.229835 u2DelayCellOfst[1]=17 cells (5 PI)
7732 13:57:06.233214 u2DelayCellOfst[2]=10 cells (3 PI)
7733 13:57:06.236331 u2DelayCellOfst[3]=14 cells (4 PI)
7734 13:57:06.239740 u2DelayCellOfst[4]=10 cells (3 PI)
7735 13:57:06.243273 u2DelayCellOfst[5]=0 cells (0 PI)
7736 13:57:06.247464 u2DelayCellOfst[6]=17 cells (5 PI)
7737 13:57:06.249380 u2DelayCellOfst[7]=17 cells (5 PI)
7738 13:57:06.252811 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7739 13:57:06.256174 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7740 13:57:06.259584 == TX Byte 1 ==
7741 13:57:06.262951 u2DelayCellOfst[8]=0 cells (0 PI)
7742 13:57:06.266183 u2DelayCellOfst[9]=0 cells (0 PI)
7743 13:57:06.269874 u2DelayCellOfst[10]=10 cells (3 PI)
7744 13:57:06.270372 u2DelayCellOfst[11]=3 cells (1 PI)
7745 13:57:06.273544 u2DelayCellOfst[12]=14 cells (4 PI)
7746 13:57:06.276482 u2DelayCellOfst[13]=14 cells (4 PI)
7747 13:57:06.279998 u2DelayCellOfst[14]=17 cells (5 PI)
7748 13:57:06.282763 u2DelayCellOfst[15]=10 cells (3 PI)
7749 13:57:06.289505 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7750 13:57:06.292690 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7751 13:57:06.292934 DramC Write-DBI on
7752 13:57:06.293119 ==
7753 13:57:06.296369 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 13:57:06.303171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 13:57:06.303423 ==
7756 13:57:06.303626
7757 13:57:06.303799
7758 13:57:06.303961 TX Vref Scan disable
7759 13:57:06.306753 == TX Byte 0 ==
7760 13:57:06.310438 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7761 13:57:06.313345 == TX Byte 1 ==
7762 13:57:06.316869 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7763 13:57:06.317183 DramC Write-DBI off
7764 13:57:06.320216
7765 13:57:06.320435 [DATLAT]
7766 13:57:06.320616 Freq=1600, CH0 RK0
7767 13:57:06.320778
7768 13:57:06.324162 DATLAT Default: 0xf
7769 13:57:06.324468 0, 0xFFFF, sum = 0
7770 13:57:06.327347 1, 0xFFFF, sum = 0
7771 13:57:06.327658 2, 0xFFFF, sum = 0
7772 13:57:06.330564 3, 0xFFFF, sum = 0
7773 13:57:06.331150 4, 0xFFFF, sum = 0
7774 13:57:06.333725 5, 0xFFFF, sum = 0
7775 13:57:06.337222 6, 0xFFFF, sum = 0
7776 13:57:06.337807 7, 0xFFFF, sum = 0
7777 13:57:06.340286 8, 0xFFFF, sum = 0
7778 13:57:06.340864 9, 0xFFFF, sum = 0
7779 13:57:06.344032 10, 0xFFFF, sum = 0
7780 13:57:06.344476 11, 0xFFFF, sum = 0
7781 13:57:06.347086 12, 0xFFFF, sum = 0
7782 13:57:06.347646 13, 0xFFFF, sum = 0
7783 13:57:06.350364 14, 0x0, sum = 1
7784 13:57:06.350799 15, 0x0, sum = 2
7785 13:57:06.353920 16, 0x0, sum = 3
7786 13:57:06.354205 17, 0x0, sum = 4
7787 13:57:06.357107 best_step = 15
7788 13:57:06.357326
7789 13:57:06.357498 ==
7790 13:57:06.360379 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 13:57:06.363246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 13:57:06.363470 ==
7793 13:57:06.363614 RX Vref Scan: 1
7794 13:57:06.363784
7795 13:57:06.366782 Set Vref Range= 24 -> 127
7796 13:57:06.366929
7797 13:57:06.370254 RX Vref 24 -> 127, step: 1
7798 13:57:06.370418
7799 13:57:06.373690 RX Delay 11 -> 252, step: 4
7800 13:57:06.373838
7801 13:57:06.376969 Set Vref, RX VrefLevel [Byte0]: 24
7802 13:57:06.380102 [Byte1]: 24
7803 13:57:06.380266
7804 13:57:06.383575 Set Vref, RX VrefLevel [Byte0]: 25
7805 13:57:06.387485 [Byte1]: 25
7806 13:57:06.387634
7807 13:57:06.389943 Set Vref, RX VrefLevel [Byte0]: 26
7808 13:57:06.393179 [Byte1]: 26
7809 13:57:06.396926
7810 13:57:06.397123 Set Vref, RX VrefLevel [Byte0]: 27
7811 13:57:06.400573 [Byte1]: 27
7812 13:57:06.404873
7813 13:57:06.405075 Set Vref, RX VrefLevel [Byte0]: 28
7814 13:57:06.408258 [Byte1]: 28
7815 13:57:06.412478
7816 13:57:06.412633 Set Vref, RX VrefLevel [Byte0]: 29
7817 13:57:06.416052 [Byte1]: 29
7818 13:57:06.419865
7819 13:57:06.420020 Set Vref, RX VrefLevel [Byte0]: 30
7820 13:57:06.423771 [Byte1]: 30
7821 13:57:06.427509
7822 13:57:06.427715 Set Vref, RX VrefLevel [Byte0]: 31
7823 13:57:06.431389 [Byte1]: 31
7824 13:57:06.435514
7825 13:57:06.436076 Set Vref, RX VrefLevel [Byte0]: 32
7826 13:57:06.438944 [Byte1]: 32
7827 13:57:06.442887
7828 13:57:06.443455 Set Vref, RX VrefLevel [Byte0]: 33
7829 13:57:06.446665 [Byte1]: 33
7830 13:57:06.450352
7831 13:57:06.450834 Set Vref, RX VrefLevel [Byte0]: 34
7832 13:57:06.454279 [Byte1]: 34
7833 13:57:06.458580
7834 13:57:06.461642 Set Vref, RX VrefLevel [Byte0]: 35
7835 13:57:06.462181 [Byte1]: 35
7836 13:57:06.465977
7837 13:57:06.466266 Set Vref, RX VrefLevel [Byte0]: 36
7838 13:57:06.469155 [Byte1]: 36
7839 13:57:06.473149
7840 13:57:06.473367 Set Vref, RX VrefLevel [Byte0]: 37
7841 13:57:06.476530 [Byte1]: 37
7842 13:57:06.481389
7843 13:57:06.481840 Set Vref, RX VrefLevel [Byte0]: 38
7844 13:57:06.484395 [Byte1]: 38
7845 13:57:06.488572
7846 13:57:06.488992 Set Vref, RX VrefLevel [Byte0]: 39
7847 13:57:06.492042 [Byte1]: 39
7848 13:57:06.496200
7849 13:57:06.496607 Set Vref, RX VrefLevel [Byte0]: 40
7850 13:57:06.499675 [Byte1]: 40
7851 13:57:06.503873
7852 13:57:06.504283 Set Vref, RX VrefLevel [Byte0]: 41
7853 13:57:06.507426 [Byte1]: 41
7854 13:57:06.511548
7855 13:57:06.511768 Set Vref, RX VrefLevel [Byte0]: 42
7856 13:57:06.514837 [Byte1]: 42
7857 13:57:06.519134
7858 13:57:06.519354 Set Vref, RX VrefLevel [Byte0]: 43
7859 13:57:06.522218 [Byte1]: 43
7860 13:57:06.526567
7861 13:57:06.526787 Set Vref, RX VrefLevel [Byte0]: 44
7862 13:57:06.529922 [Byte1]: 44
7863 13:57:06.534287
7864 13:57:06.534592 Set Vref, RX VrefLevel [Byte0]: 45
7865 13:57:06.537340 [Byte1]: 45
7866 13:57:06.541668
7867 13:57:06.541954 Set Vref, RX VrefLevel [Byte0]: 46
7868 13:57:06.544866 [Byte1]: 46
7869 13:57:06.549652
7870 13:57:06.550012 Set Vref, RX VrefLevel [Byte0]: 47
7871 13:57:06.552720 [Byte1]: 47
7872 13:57:06.557478
7873 13:57:06.557744 Set Vref, RX VrefLevel [Byte0]: 48
7874 13:57:06.560623 [Byte1]: 48
7875 13:57:06.564828
7876 13:57:06.565047 Set Vref, RX VrefLevel [Byte0]: 49
7877 13:57:06.568010 [Byte1]: 49
7878 13:57:06.572239
7879 13:57:06.572478 Set Vref, RX VrefLevel [Byte0]: 50
7880 13:57:06.575791 [Byte1]: 50
7881 13:57:06.579862
7882 13:57:06.580091 Set Vref, RX VrefLevel [Byte0]: 51
7883 13:57:06.583324 [Byte1]: 51
7884 13:57:06.587702
7885 13:57:06.587924 Set Vref, RX VrefLevel [Byte0]: 52
7886 13:57:06.590790 [Byte1]: 52
7887 13:57:06.595227
7888 13:57:06.595423 Set Vref, RX VrefLevel [Byte0]: 53
7889 13:57:06.598503 [Byte1]: 53
7890 13:57:06.602684
7891 13:57:06.602906 Set Vref, RX VrefLevel [Byte0]: 54
7892 13:57:06.605985 [Byte1]: 54
7893 13:57:06.610095
7894 13:57:06.610318 Set Vref, RX VrefLevel [Byte0]: 55
7895 13:57:06.613676 [Byte1]: 55
7896 13:57:06.617855
7897 13:57:06.618143 Set Vref, RX VrefLevel [Byte0]: 56
7898 13:57:06.621562 [Byte1]: 56
7899 13:57:06.626085
7900 13:57:06.626309 Set Vref, RX VrefLevel [Byte0]: 57
7901 13:57:06.628701 [Byte1]: 57
7902 13:57:06.633371
7903 13:57:06.633593 Set Vref, RX VrefLevel [Byte0]: 58
7904 13:57:06.636713 [Byte1]: 58
7905 13:57:06.640831
7906 13:57:06.641053 Set Vref, RX VrefLevel [Byte0]: 59
7907 13:57:06.644628 [Byte1]: 59
7908 13:57:06.648888
7909 13:57:06.649141 Set Vref, RX VrefLevel [Byte0]: 60
7910 13:57:06.651879 [Byte1]: 60
7911 13:57:06.656023
7912 13:57:06.656284 Set Vref, RX VrefLevel [Byte0]: 61
7913 13:57:06.659544 [Byte1]: 61
7914 13:57:06.664082
7915 13:57:06.664313 Set Vref, RX VrefLevel [Byte0]: 62
7916 13:57:06.666948 [Byte1]: 62
7917 13:57:06.671298
7918 13:57:06.671504 Set Vref, RX VrefLevel [Byte0]: 63
7919 13:57:06.674792 [Byte1]: 63
7920 13:57:06.679217
7921 13:57:06.679474 Set Vref, RX VrefLevel [Byte0]: 64
7922 13:57:06.682325 [Byte1]: 64
7923 13:57:06.686466
7924 13:57:06.686665 Set Vref, RX VrefLevel [Byte0]: 65
7925 13:57:06.693220 [Byte1]: 65
7926 13:57:06.693440
7927 13:57:06.696439 Set Vref, RX VrefLevel [Byte0]: 66
7928 13:57:06.699304 [Byte1]: 66
7929 13:57:06.699516
7930 13:57:06.702649 Set Vref, RX VrefLevel [Byte0]: 67
7931 13:57:06.706321 [Byte1]: 67
7932 13:57:06.706570
7933 13:57:06.709535 Set Vref, RX VrefLevel [Byte0]: 68
7934 13:57:06.713129 [Byte1]: 68
7935 13:57:06.716945
7936 13:57:06.717139 Set Vref, RX VrefLevel [Byte0]: 69
7937 13:57:06.720300 [Byte1]: 69
7938 13:57:06.724747
7939 13:57:06.724968 Set Vref, RX VrefLevel [Byte0]: 70
7940 13:57:06.728471 [Byte1]: 70
7941 13:57:06.732699
7942 13:57:06.732949 Set Vref, RX VrefLevel [Byte0]: 71
7943 13:57:06.735701 [Byte1]: 71
7944 13:57:06.740090
7945 13:57:06.740443 Set Vref, RX VrefLevel [Byte0]: 72
7946 13:57:06.743185 [Byte1]: 72
7947 13:57:06.747398
7948 13:57:06.747860 Set Vref, RX VrefLevel [Byte0]: 73
7949 13:57:06.750852 [Byte1]: 73
7950 13:57:06.755280
7951 13:57:06.755696 Set Vref, RX VrefLevel [Byte0]: 74
7952 13:57:06.758570 [Byte1]: 74
7953 13:57:06.763175
7954 13:57:06.763590 Set Vref, RX VrefLevel [Byte0]: 75
7955 13:57:06.766343 [Byte1]: 75
7956 13:57:06.770226
7957 13:57:06.770703 Set Vref, RX VrefLevel [Byte0]: 76
7958 13:57:06.773515 [Byte1]: 76
7959 13:57:06.778355
7960 13:57:06.778820 Set Vref, RX VrefLevel [Byte0]: 77
7961 13:57:06.780945 [Byte1]: 77
7962 13:57:06.785668
7963 13:57:06.785899 Final RX Vref Byte 0 = 57 to rank0
7964 13:57:06.789228 Final RX Vref Byte 1 = 63 to rank0
7965 13:57:06.792367 Final RX Vref Byte 0 = 57 to rank1
7966 13:57:06.795735 Final RX Vref Byte 1 = 63 to rank1==
7967 13:57:06.798565 Dram Type= 6, Freq= 0, CH_0, rank 0
7968 13:57:06.802544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 13:57:06.805856 ==
7970 13:57:06.806085 DQS Delay:
7971 13:57:06.806322 DQS0 = 0, DQS1 = 0
7972 13:57:06.808772 DQM Delay:
7973 13:57:06.809002 DQM0 = 128, DQM1 = 122
7974 13:57:06.812001 DQ Delay:
7975 13:57:06.815501 DQ0 =128, DQ1 =132, DQ2 =122, DQ3 =124
7976 13:57:06.818525 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =136
7977 13:57:06.822021 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7978 13:57:06.825114 DQ12 =128, DQ13 =128, DQ14 =130, DQ15 =134
7979 13:57:06.825186
7980 13:57:06.825247
7981 13:57:06.825304
7982 13:57:06.828580 [DramC_TX_OE_Calibration] TA2
7983 13:57:06.831911 Original DQ_B0 (3 6) =30, OEN = 27
7984 13:57:06.835196 Original DQ_B1 (3 6) =30, OEN = 27
7985 13:57:06.838608 24, 0x0, End_B0=24 End_B1=24
7986 13:57:06.838690 25, 0x0, End_B0=25 End_B1=25
7987 13:57:06.841711 26, 0x0, End_B0=26 End_B1=26
7988 13:57:06.845251 27, 0x0, End_B0=27 End_B1=27
7989 13:57:06.849137 28, 0x0, End_B0=28 End_B1=28
7990 13:57:06.849214 29, 0x0, End_B0=29 End_B1=29
7991 13:57:06.852219 30, 0x0, End_B0=30 End_B1=30
7992 13:57:06.855132 31, 0x4141, End_B0=30 End_B1=30
7993 13:57:06.858535 Byte0 end_step=30 best_step=27
7994 13:57:06.861864 Byte1 end_step=30 best_step=27
7995 13:57:06.865285 Byte0 TX OE(2T, 0.5T) = (3, 3)
7996 13:57:06.865362 Byte1 TX OE(2T, 0.5T) = (3, 3)
7997 13:57:06.865424
7998 13:57:06.868308
7999 13:57:06.876375 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8000 13:57:06.878754 CH0 RK0: MR19=303, MR18=1206
8001 13:57:06.885127 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
8002 13:57:06.885690
8003 13:57:06.888433 ----->DramcWriteLeveling(PI) begin...
8004 13:57:06.888874 ==
8005 13:57:06.891812 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 13:57:06.895158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 13:57:06.895569 ==
8008 13:57:06.898758 Write leveling (Byte 0): 34 => 34
8009 13:57:06.902143 Write leveling (Byte 1): 26 => 26
8010 13:57:06.905840 DramcWriteLeveling(PI) end<-----
8011 13:57:06.906368
8012 13:57:06.906870 ==
8013 13:57:06.908491 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 13:57:06.912264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 13:57:06.912703 ==
8016 13:57:06.915219 [Gating] SW mode calibration
8017 13:57:06.922310 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8018 13:57:06.928998 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8019 13:57:06.932268 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 13:57:06.935256 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 13:57:06.941713 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 13:57:06.945425 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8023 13:57:06.948635 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8024 13:57:06.955195 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8025 13:57:06.958344 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 13:57:06.962474 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 13:57:06.968647 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 13:57:06.971970 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8029 13:57:06.974662 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8030 13:57:06.981759 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8031 13:57:06.985137 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8032 13:57:06.988289 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8033 13:57:06.994876 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8034 13:57:06.997927 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 13:57:07.001344 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 13:57:07.004609 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 13:57:07.011565 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8038 13:57:07.014749 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8039 13:57:07.018369 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8040 13:57:07.025020 1 6 20 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8041 13:57:07.028382 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 13:57:07.031770 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 13:57:07.038478 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 13:57:07.041810 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 13:57:07.045484 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 13:57:07.051913 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 13:57:07.055207 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8048 13:57:07.058952 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 13:57:07.065908 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8050 13:57:07.069518 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 13:57:07.072286 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 13:57:07.078605 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 13:57:07.081629 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 13:57:07.085382 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 13:57:07.088767 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 13:57:07.094975 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 13:57:07.098422 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 13:57:07.102077 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 13:57:07.108577 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 13:57:07.111753 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 13:57:07.115173 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 13:57:07.122100 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8063 13:57:07.125288 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8064 13:57:07.128509 Total UI for P1: 0, mck2ui 16
8065 13:57:07.132285 best dqsien dly found for B0: ( 1, 9, 8)
8066 13:57:07.135444 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 13:57:07.142541 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 13:57:07.142993 Total UI for P1: 0, mck2ui 16
8069 13:57:07.145458 best dqsien dly found for B1: ( 1, 9, 18)
8070 13:57:07.152053 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8071 13:57:07.155806 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8072 13:57:07.156340
8073 13:57:07.158922 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8074 13:57:07.162384 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8075 13:57:07.165554 [Gating] SW calibration Done
8076 13:57:07.165983 ==
8077 13:57:07.168697 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 13:57:07.172034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 13:57:07.172531 ==
8080 13:57:07.175509 RX Vref Scan: 0
8081 13:57:07.175947
8082 13:57:07.176339 RX Vref 0 -> 0, step: 1
8083 13:57:07.176883
8084 13:57:07.178699 RX Delay 0 -> 252, step: 8
8085 13:57:07.183381 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8086 13:57:07.185706 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8087 13:57:07.192272 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8088 13:57:07.195396 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8089 13:57:07.198743 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8090 13:57:07.202095 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8091 13:57:07.205594 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8092 13:57:07.212244 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8093 13:57:07.215570 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8094 13:57:07.218931 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8095 13:57:07.222335 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8096 13:57:07.225730 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8097 13:57:07.232628 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8098 13:57:07.235647 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8099 13:57:07.238820 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8100 13:57:07.242662 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8101 13:57:07.243073 ==
8102 13:57:07.246444 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 13:57:07.249341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 13:57:07.252267 ==
8105 13:57:07.252680 DQS Delay:
8106 13:57:07.253006 DQS0 = 0, DQS1 = 0
8107 13:57:07.255680 DQM Delay:
8108 13:57:07.256093 DQM0 = 130, DQM1 = 124
8109 13:57:07.258816 DQ Delay:
8110 13:57:07.262979 DQ0 =131, DQ1 =131, DQ2 =123, DQ3 =131
8111 13:57:07.265693 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8112 13:57:07.269222 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8113 13:57:07.272654 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8114 13:57:07.273213
8115 13:57:07.273680
8116 13:57:07.274122 ==
8117 13:57:07.275488 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 13:57:07.278923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 13:57:07.279349 ==
8120 13:57:07.279673
8121 13:57:07.282427
8122 13:57:07.282842 TX Vref Scan disable
8123 13:57:07.285816 == TX Byte 0 ==
8124 13:57:07.289634 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8125 13:57:07.292626 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8126 13:57:07.295651 == TX Byte 1 ==
8127 13:57:07.299288 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8128 13:57:07.302542 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8129 13:57:07.302959 ==
8130 13:57:07.305676 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 13:57:07.312382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 13:57:07.312795 ==
8133 13:57:07.326205
8134 13:57:07.329237 TX Vref early break, caculate TX vref
8135 13:57:07.333134 TX Vref=16, minBit 9, minWin=21, winSum=369
8136 13:57:07.335913 TX Vref=18, minBit 9, minWin=22, winSum=378
8137 13:57:07.339152 TX Vref=20, minBit 5, minWin=23, winSum=387
8138 13:57:07.342503 TX Vref=22, minBit 9, minWin=23, winSum=396
8139 13:57:07.346061 TX Vref=24, minBit 4, minWin=24, winSum=400
8140 13:57:07.353283 TX Vref=26, minBit 4, minWin=24, winSum=411
8141 13:57:07.356525 TX Vref=28, minBit 0, minWin=25, winSum=417
8142 13:57:07.359764 TX Vref=30, minBit 0, minWin=25, winSum=416
8143 13:57:07.362754 TX Vref=32, minBit 8, minWin=24, winSum=409
8144 13:57:07.366354 TX Vref=34, minBit 4, minWin=24, winSum=402
8145 13:57:07.369426 TX Vref=36, minBit 0, minWin=24, winSum=394
8146 13:57:07.376074 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8147 13:57:07.376367
8148 13:57:07.379204 Final TX Range 0 Vref 28
8149 13:57:07.379496
8150 13:57:07.379725 ==
8151 13:57:07.382717 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 13:57:07.386016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 13:57:07.386333 ==
8154 13:57:07.386623
8155 13:57:07.386842
8156 13:57:07.389345 TX Vref Scan disable
8157 13:57:07.396034 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8158 13:57:07.396116 == TX Byte 0 ==
8159 13:57:07.398937 u2DelayCellOfst[0]=14 cells (4 PI)
8160 13:57:07.402325 u2DelayCellOfst[1]=17 cells (5 PI)
8161 13:57:07.405667 u2DelayCellOfst[2]=10 cells (3 PI)
8162 13:57:07.409162 u2DelayCellOfst[3]=10 cells (3 PI)
8163 13:57:07.412480 u2DelayCellOfst[4]=10 cells (3 PI)
8164 13:57:07.416268 u2DelayCellOfst[5]=0 cells (0 PI)
8165 13:57:07.419023 u2DelayCellOfst[6]=17 cells (5 PI)
8166 13:57:07.422771 u2DelayCellOfst[7]=17 cells (5 PI)
8167 13:57:07.425867 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8168 13:57:07.429340 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8169 13:57:07.432339 == TX Byte 1 ==
8170 13:57:07.432474 u2DelayCellOfst[8]=0 cells (0 PI)
8171 13:57:07.436167 u2DelayCellOfst[9]=0 cells (0 PI)
8172 13:57:07.439415 u2DelayCellOfst[10]=3 cells (1 PI)
8173 13:57:07.442530 u2DelayCellOfst[11]=0 cells (0 PI)
8174 13:57:07.445677 u2DelayCellOfst[12]=10 cells (3 PI)
8175 13:57:07.449366 u2DelayCellOfst[13]=10 cells (3 PI)
8176 13:57:07.452898 u2DelayCellOfst[14]=14 cells (4 PI)
8177 13:57:07.456226 u2DelayCellOfst[15]=10 cells (3 PI)
8178 13:57:07.459887 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8179 13:57:07.465817 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8180 13:57:07.466055 DramC Write-DBI on
8181 13:57:07.466339 ==
8182 13:57:07.470183 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 13:57:07.473283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 13:57:07.473611 ==
8185 13:57:07.476342
8186 13:57:07.476867
8187 13:57:07.477310 TX Vref Scan disable
8188 13:57:07.479445 == TX Byte 0 ==
8189 13:57:07.482820 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8190 13:57:07.486469 == TX Byte 1 ==
8191 13:57:07.489543 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8192 13:57:07.489916 DramC Write-DBI off
8193 13:57:07.492931
8194 13:57:07.493441 [DATLAT]
8195 13:57:07.493789 Freq=1600, CH0 RK1
8196 13:57:07.494254
8197 13:57:07.496218 DATLAT Default: 0xf
8198 13:57:07.496887 0, 0xFFFF, sum = 0
8199 13:57:07.499583 1, 0xFFFF, sum = 0
8200 13:57:07.500125 2, 0xFFFF, sum = 0
8201 13:57:07.503564 3, 0xFFFF, sum = 0
8202 13:57:07.503948 4, 0xFFFF, sum = 0
8203 13:57:07.506110 5, 0xFFFF, sum = 0
8204 13:57:07.509773 6, 0xFFFF, sum = 0
8205 13:57:07.510154 7, 0xFFFF, sum = 0
8206 13:57:07.512873 8, 0xFFFF, sum = 0
8207 13:57:07.513419 9, 0xFFFF, sum = 0
8208 13:57:07.516292 10, 0xFFFF, sum = 0
8209 13:57:07.516833 11, 0xFFFF, sum = 0
8210 13:57:07.519486 12, 0xFFFF, sum = 0
8211 13:57:07.519873 13, 0xFFFF, sum = 0
8212 13:57:07.523249 14, 0x0, sum = 1
8213 13:57:07.523660 15, 0x0, sum = 2
8214 13:57:07.526057 16, 0x0, sum = 3
8215 13:57:07.526480 17, 0x0, sum = 4
8216 13:57:07.529539 best_step = 15
8217 13:57:07.529921
8218 13:57:07.530214 ==
8219 13:57:07.532836 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 13:57:07.536217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 13:57:07.536716 ==
8222 13:57:07.537021 RX Vref Scan: 0
8223 13:57:07.537298
8224 13:57:07.539582 RX Vref 0 -> 0, step: 1
8225 13:57:07.540110
8226 13:57:07.543045 RX Delay 11 -> 252, step: 4
8227 13:57:07.546310 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8228 13:57:07.553316 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8229 13:57:07.556512 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8230 13:57:07.559666 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8231 13:57:07.563213 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8232 13:57:07.566273 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8233 13:57:07.569773 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8234 13:57:07.576367 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8235 13:57:07.579912 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8236 13:57:07.582995 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8237 13:57:07.587084 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8238 13:57:07.589969 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8239 13:57:07.596511 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8240 13:57:07.600375 iDelay=191, Bit 13, Center 128 (71 ~ 186) 116
8241 13:57:07.602679 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8242 13:57:07.606248 iDelay=191, Bit 15, Center 132 (75 ~ 190) 116
8243 13:57:07.606477 ==
8244 13:57:07.609622 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 13:57:07.616246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 13:57:07.616422 ==
8247 13:57:07.616553 DQS Delay:
8248 13:57:07.616676 DQS0 = 0, DQS1 = 0
8249 13:57:07.619317 DQM Delay:
8250 13:57:07.619500 DQM0 = 126, DQM1 = 122
8251 13:57:07.622815 DQ Delay:
8252 13:57:07.626114 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8253 13:57:07.629482 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8254 13:57:07.632632 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8255 13:57:07.636940 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8256 13:57:07.637108
8257 13:57:07.637238
8258 13:57:07.637358
8259 13:57:07.639913 [DramC_TX_OE_Calibration] TA2
8260 13:57:07.643135 Original DQ_B0 (3 6) =30, OEN = 27
8261 13:57:07.646144 Original DQ_B1 (3 6) =30, OEN = 27
8262 13:57:07.649391 24, 0x0, End_B0=24 End_B1=24
8263 13:57:07.649599 25, 0x0, End_B0=25 End_B1=25
8264 13:57:07.652487 26, 0x0, End_B0=26 End_B1=26
8265 13:57:07.655940 27, 0x0, End_B0=27 End_B1=27
8266 13:57:07.659753 28, 0x0, End_B0=28 End_B1=28
8267 13:57:07.663209 29, 0x0, End_B0=29 End_B1=29
8268 13:57:07.663512 30, 0x0, End_B0=30 End_B1=30
8269 13:57:07.666329 31, 0x4141, End_B0=30 End_B1=30
8270 13:57:07.669569 Byte0 end_step=30 best_step=27
8271 13:57:07.672627 Byte1 end_step=30 best_step=27
8272 13:57:07.676620 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 13:57:07.679352 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 13:57:07.680006
8275 13:57:07.680400
8276 13:57:07.686062 [DQSOSCAuto] RK1, (LSB)MR18= 0x170b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8277 13:57:07.689758 CH0 RK1: MR19=303, MR18=170B
8278 13:57:07.695879 CH0_RK1: MR19=0x303, MR18=0x170B, DQSOSC=398, MR23=63, INC=23, DEC=15
8279 13:57:07.700374 [RxdqsGatingPostProcess] freq 1600
8280 13:57:07.703111 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 13:57:07.706179 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 13:57:07.709740 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 13:57:07.712690 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 13:57:07.716567 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 13:57:07.719937 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 13:57:07.723188 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 13:57:07.726251 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 13:57:07.730004 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 13:57:07.730573 Pre-setting of DQS Precalculation
8290 13:57:07.736434 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 13:57:07.736994 ==
8292 13:57:07.739843 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 13:57:07.742994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 13:57:07.743491 ==
8295 13:57:07.749683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 13:57:07.753170 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 13:57:07.756606 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 13:57:07.763306 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 13:57:07.772693 [CA 0] Center 43 (15~71) winsize 57
8300 13:57:07.775854 [CA 1] Center 42 (14~71) winsize 58
8301 13:57:07.779576 [CA 2] Center 37 (9~66) winsize 58
8302 13:57:07.782261 [CA 3] Center 36 (7~66) winsize 60
8303 13:57:07.785938 [CA 4] Center 37 (8~67) winsize 60
8304 13:57:07.789028 [CA 5] Center 36 (7~66) winsize 60
8305 13:57:07.789385
8306 13:57:07.792336 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8307 13:57:07.792659
8308 13:57:07.795503 [CATrainingPosCal] consider 1 rank data
8309 13:57:07.799217 u2DelayCellTimex100 = 275/100 ps
8310 13:57:07.802859 CA0 delay=43 (15~71),Diff = 7 PI (24 cell)
8311 13:57:07.809116 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8312 13:57:07.813115 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8313 13:57:07.816405 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 13:57:07.819279 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8315 13:57:07.822924 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8316 13:57:07.823333
8317 13:57:07.825870 CA PerBit enable=1, Macro0, CA PI delay=36
8318 13:57:07.826161
8319 13:57:07.829962 [CBTSetCACLKResult] CA Dly = 36
8320 13:57:07.830267 CS Dly: 8 (0~39)
8321 13:57:07.836540 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 13:57:07.839201 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 13:57:07.839494 ==
8324 13:57:07.842681 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 13:57:07.845980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 13:57:07.846205 ==
8327 13:57:07.852804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 13:57:07.856068 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 13:57:07.859689 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 13:57:07.866121 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 13:57:07.875320 [CA 0] Center 43 (14~72) winsize 59
8332 13:57:07.879241 [CA 1] Center 43 (14~72) winsize 59
8333 13:57:07.882105 [CA 2] Center 38 (9~67) winsize 59
8334 13:57:07.885777 [CA 3] Center 37 (8~66) winsize 59
8335 13:57:07.888704 [CA 4] Center 38 (8~68) winsize 61
8336 13:57:07.892087 [CA 5] Center 36 (7~66) winsize 60
8337 13:57:07.892274
8338 13:57:07.895481 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8339 13:57:07.895658
8340 13:57:07.899111 [CATrainingPosCal] consider 2 rank data
8341 13:57:07.902441 u2DelayCellTimex100 = 275/100 ps
8342 13:57:07.905455 CA0 delay=43 (15~71),Diff = 7 PI (24 cell)
8343 13:57:07.912642 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8344 13:57:07.915507 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8345 13:57:07.919506 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8346 13:57:07.921908 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8347 13:57:07.925774 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8348 13:57:07.925978
8349 13:57:07.928901 CA PerBit enable=1, Macro0, CA PI delay=36
8350 13:57:07.929079
8351 13:57:07.932119 [CBTSetCACLKResult] CA Dly = 36
8352 13:57:07.932277 CS Dly: 11 (0~45)
8353 13:57:07.938332 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 13:57:07.942169 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 13:57:07.942313
8356 13:57:07.945198 ----->DramcWriteLeveling(PI) begin...
8357 13:57:07.945314 ==
8358 13:57:07.948652 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 13:57:07.952439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 13:57:07.952564 ==
8361 13:57:07.955504 Write leveling (Byte 0): 26 => 26
8362 13:57:07.959058 Write leveling (Byte 1): 29 => 29
8363 13:57:07.961998 DramcWriteLeveling(PI) end<-----
8364 13:57:07.962135
8365 13:57:07.962240 ==
8366 13:57:07.965093 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 13:57:07.972282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 13:57:07.972444 ==
8369 13:57:07.972539 [Gating] SW mode calibration
8370 13:57:07.982452 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 13:57:07.985599 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 13:57:07.988455 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 13:57:07.995220 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 13:57:07.998713 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 13:57:08.002184 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 13:57:08.008758 1 4 16 | B1->B0 | 2b2b 2525 | 1 1 | (0 0) (0 0)
8377 13:57:08.012100 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 13:57:08.015003 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 13:57:08.021851 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 13:57:08.025302 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 13:57:08.028672 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 13:57:08.035436 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 13:57:08.038608 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8384 13:57:08.042578 1 5 16 | B1->B0 | 2424 3131 | 1 1 | (1 0) (1 0)
8385 13:57:08.048579 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 13:57:08.051944 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 13:57:08.055131 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 13:57:08.062064 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 13:57:08.065417 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 13:57:08.068862 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 13:57:08.071863 1 6 12 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
8392 13:57:08.078836 1 6 16 | B1->B0 | 3939 2c2c | 0 0 | (0 0) (0 0)
8393 13:57:08.082008 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 13:57:08.085434 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 13:57:08.092125 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 13:57:08.095796 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 13:57:08.098478 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 13:57:08.105862 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 13:57:08.108907 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 13:57:08.111945 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8401 13:57:08.118959 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 13:57:08.121996 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 13:57:08.125198 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 13:57:08.132360 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 13:57:08.135436 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 13:57:08.139024 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 13:57:08.142319 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 13:57:08.149240 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 13:57:08.152985 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 13:57:08.155661 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 13:57:08.162498 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 13:57:08.165879 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 13:57:08.168902 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 13:57:08.175905 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 13:57:08.179052 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 13:57:08.182275 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 13:57:08.188993 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 13:57:08.189112 Total UI for P1: 0, mck2ui 16
8419 13:57:08.195737 best dqsien dly found for B0: ( 1, 9, 14)
8420 13:57:08.195856 Total UI for P1: 0, mck2ui 16
8421 13:57:08.202352 best dqsien dly found for B1: ( 1, 9, 14)
8422 13:57:08.205579 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8423 13:57:08.209008 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8424 13:57:08.209114
8425 13:57:08.211771 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8426 13:57:08.215254 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8427 13:57:08.219916 [Gating] SW calibration Done
8428 13:57:08.220023 ==
8429 13:57:08.222614 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 13:57:08.225350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 13:57:08.225460 ==
8432 13:57:08.228336 RX Vref Scan: 0
8433 13:57:08.228443
8434 13:57:08.228534 RX Vref 0 -> 0, step: 1
8435 13:57:08.228622
8436 13:57:08.232073 RX Delay 0 -> 252, step: 8
8437 13:57:08.235188 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8438 13:57:08.242135 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8439 13:57:08.245091 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8440 13:57:08.248726 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8441 13:57:08.251940 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8442 13:57:08.255283 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8443 13:57:08.261771 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8444 13:57:08.265332 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8445 13:57:08.268789 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8446 13:57:08.271884 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8447 13:57:08.275171 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8448 13:57:08.282155 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8449 13:57:08.285459 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8450 13:57:08.288784 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8451 13:57:08.292013 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8452 13:57:08.295085 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8453 13:57:08.295166 ==
8454 13:57:08.298972 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 13:57:08.305128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 13:57:08.305210 ==
8457 13:57:08.305273 DQS Delay:
8458 13:57:08.309052 DQS0 = 0, DQS1 = 0
8459 13:57:08.309132 DQM Delay:
8460 13:57:08.311942 DQM0 = 134, DQM1 = 127
8461 13:57:08.312048 DQ Delay:
8462 13:57:08.315452 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8463 13:57:08.319002 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8464 13:57:08.322310 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8465 13:57:08.325356 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =131
8466 13:57:08.325435
8467 13:57:08.325498
8468 13:57:08.325555 ==
8469 13:57:08.328770 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 13:57:08.332157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 13:57:08.335778 ==
8472 13:57:08.335858
8473 13:57:08.335921
8474 13:57:08.335979 TX Vref Scan disable
8475 13:57:08.339109 == TX Byte 0 ==
8476 13:57:08.341881 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8477 13:57:08.345436 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8478 13:57:08.348884 == TX Byte 1 ==
8479 13:57:08.352102 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8480 13:57:08.355640 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8481 13:57:08.358875 ==
8482 13:57:08.358955 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 13:57:08.365538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 13:57:08.365620 ==
8485 13:57:08.378316
8486 13:57:08.381795 TX Vref early break, caculate TX vref
8487 13:57:08.385674 TX Vref=16, minBit 8, minWin=21, winSum=363
8488 13:57:08.389093 TX Vref=18, minBit 8, minWin=21, winSum=366
8489 13:57:08.391806 TX Vref=20, minBit 8, minWin=21, winSum=382
8490 13:57:08.395264 TX Vref=22, minBit 8, minWin=23, winSum=390
8491 13:57:08.398839 TX Vref=24, minBit 5, minWin=23, winSum=401
8492 13:57:08.405388 TX Vref=26, minBit 8, minWin=24, winSum=411
8493 13:57:08.408437 TX Vref=28, minBit 9, minWin=25, winSum=417
8494 13:57:08.412379 TX Vref=30, minBit 0, minWin=25, winSum=414
8495 13:57:08.415419 TX Vref=32, minBit 8, minWin=24, winSum=405
8496 13:57:08.418805 TX Vref=34, minBit 8, minWin=23, winSum=396
8497 13:57:08.421810 TX Vref=36, minBit 6, minWin=23, winSum=383
8498 13:57:08.428926 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 28
8499 13:57:08.429020
8500 13:57:08.432262 Final TX Range 0 Vref 28
8501 13:57:08.432350
8502 13:57:08.432414 ==
8503 13:57:08.435183 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 13:57:08.438800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 13:57:08.438883 ==
8506 13:57:08.438946
8507 13:57:08.439005
8508 13:57:08.441754 TX Vref Scan disable
8509 13:57:08.448657 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8510 13:57:08.448739 == TX Byte 0 ==
8511 13:57:08.452657 u2DelayCellOfst[0]=17 cells (5 PI)
8512 13:57:08.455329 u2DelayCellOfst[1]=10 cells (3 PI)
8513 13:57:08.458931 u2DelayCellOfst[2]=0 cells (0 PI)
8514 13:57:08.462228 u2DelayCellOfst[3]=7 cells (2 PI)
8515 13:57:08.465365 u2DelayCellOfst[4]=7 cells (2 PI)
8516 13:57:08.468633 u2DelayCellOfst[5]=21 cells (6 PI)
8517 13:57:08.471788 u2DelayCellOfst[6]=17 cells (5 PI)
8518 13:57:08.471869 u2DelayCellOfst[7]=7 cells (2 PI)
8519 13:57:08.478642 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8520 13:57:08.482296 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8521 13:57:08.482379 == TX Byte 1 ==
8522 13:57:08.484986 u2DelayCellOfst[8]=0 cells (0 PI)
8523 13:57:08.488288 u2DelayCellOfst[9]=0 cells (0 PI)
8524 13:57:08.491897 u2DelayCellOfst[10]=7 cells (2 PI)
8525 13:57:08.495747 u2DelayCellOfst[11]=3 cells (1 PI)
8526 13:57:08.498654 u2DelayCellOfst[12]=10 cells (3 PI)
8527 13:57:08.501974 u2DelayCellOfst[13]=14 cells (4 PI)
8528 13:57:08.505153 u2DelayCellOfst[14]=14 cells (4 PI)
8529 13:57:08.508541 u2DelayCellOfst[15]=14 cells (4 PI)
8530 13:57:08.512511 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8531 13:57:08.518583 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8532 13:57:08.518666 DramC Write-DBI on
8533 13:57:08.518730 ==
8534 13:57:08.521887 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 13:57:08.525218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 13:57:08.525301 ==
8537 13:57:08.525379
8538 13:57:08.528556
8539 13:57:08.528637 TX Vref Scan disable
8540 13:57:08.531932 == TX Byte 0 ==
8541 13:57:08.535444 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8542 13:57:08.538996 == TX Byte 1 ==
8543 13:57:08.542703 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8544 13:57:08.542785 DramC Write-DBI off
8545 13:57:08.542849
8546 13:57:08.545178 [DATLAT]
8547 13:57:08.545257 Freq=1600, CH1 RK0
8548 13:57:08.545322
8549 13:57:08.548522 DATLAT Default: 0xf
8550 13:57:08.548602 0, 0xFFFF, sum = 0
8551 13:57:08.551884 1, 0xFFFF, sum = 0
8552 13:57:08.551966 2, 0xFFFF, sum = 0
8553 13:57:08.555176 3, 0xFFFF, sum = 0
8554 13:57:08.555258 4, 0xFFFF, sum = 0
8555 13:57:08.558341 5, 0xFFFF, sum = 0
8556 13:57:08.558447 6, 0xFFFF, sum = 0
8557 13:57:08.562288 7, 0xFFFF, sum = 0
8558 13:57:08.562371 8, 0xFFFF, sum = 0
8559 13:57:08.565179 9, 0xFFFF, sum = 0
8560 13:57:08.568926 10, 0xFFFF, sum = 0
8561 13:57:08.569008 11, 0xFFFF, sum = 0
8562 13:57:08.572289 12, 0xFFFF, sum = 0
8563 13:57:08.572371 13, 0xFFFF, sum = 0
8564 13:57:08.575411 14, 0x0, sum = 1
8565 13:57:08.575494 15, 0x0, sum = 2
8566 13:57:08.578668 16, 0x0, sum = 3
8567 13:57:08.578749 17, 0x0, sum = 4
8568 13:57:08.578813 best_step = 15
8569 13:57:08.578872
8570 13:57:08.582318 ==
8571 13:57:08.585283 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 13:57:08.588392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 13:57:08.588473 ==
8574 13:57:08.588537 RX Vref Scan: 1
8575 13:57:08.588596
8576 13:57:08.592101 Set Vref Range= 24 -> 127
8577 13:57:08.592212
8578 13:57:08.595555 RX Vref 24 -> 127, step: 1
8579 13:57:08.595636
8580 13:57:08.598548 RX Delay 11 -> 252, step: 4
8581 13:57:08.598628
8582 13:57:08.601831 Set Vref, RX VrefLevel [Byte0]: 24
8583 13:57:08.605479 [Byte1]: 24
8584 13:57:08.605560
8585 13:57:08.608540 Set Vref, RX VrefLevel [Byte0]: 25
8586 13:57:08.612231 [Byte1]: 25
8587 13:57:08.612312
8588 13:57:08.615459 Set Vref, RX VrefLevel [Byte0]: 26
8589 13:57:08.618779 [Byte1]: 26
8590 13:57:08.622225
8591 13:57:08.622305 Set Vref, RX VrefLevel [Byte0]: 27
8592 13:57:08.625923 [Byte1]: 27
8593 13:57:08.629760
8594 13:57:08.629841 Set Vref, RX VrefLevel [Byte0]: 28
8595 13:57:08.633021 [Byte1]: 28
8596 13:57:08.637511
8597 13:57:08.637592 Set Vref, RX VrefLevel [Byte0]: 29
8598 13:57:08.641021 [Byte1]: 29
8599 13:57:08.644758
8600 13:57:08.644839 Set Vref, RX VrefLevel [Byte0]: 30
8601 13:57:08.648127 [Byte1]: 30
8602 13:57:08.652376
8603 13:57:08.652456 Set Vref, RX VrefLevel [Byte0]: 31
8604 13:57:08.656277 [Byte1]: 31
8605 13:57:08.660041
8606 13:57:08.660121 Set Vref, RX VrefLevel [Byte0]: 32
8607 13:57:08.663866 [Byte1]: 32
8608 13:57:08.667567
8609 13:57:08.667647 Set Vref, RX VrefLevel [Byte0]: 33
8610 13:57:08.671176 [Byte1]: 33
8611 13:57:08.675668
8612 13:57:08.675748 Set Vref, RX VrefLevel [Byte0]: 34
8613 13:57:08.679277 [Byte1]: 34
8614 13:57:08.682673
8615 13:57:08.682754 Set Vref, RX VrefLevel [Byte0]: 35
8616 13:57:08.685915 [Byte1]: 35
8617 13:57:08.690752
8618 13:57:08.690832 Set Vref, RX VrefLevel [Byte0]: 36
8619 13:57:08.693627 [Byte1]: 36
8620 13:57:08.698370
8621 13:57:08.698496 Set Vref, RX VrefLevel [Byte0]: 37
8622 13:57:08.701242 [Byte1]: 37
8623 13:57:08.705733
8624 13:57:08.705812 Set Vref, RX VrefLevel [Byte0]: 38
8625 13:57:08.709229 [Byte1]: 38
8626 13:57:08.713825
8627 13:57:08.713905 Set Vref, RX VrefLevel [Byte0]: 39
8628 13:57:08.717181 [Byte1]: 39
8629 13:57:08.721070
8630 13:57:08.721148 Set Vref, RX VrefLevel [Byte0]: 40
8631 13:57:08.724556 [Byte1]: 40
8632 13:57:08.728297
8633 13:57:08.728375 Set Vref, RX VrefLevel [Byte0]: 41
8634 13:57:08.731663 [Byte1]: 41
8635 13:57:08.736190
8636 13:57:08.736269 Set Vref, RX VrefLevel [Byte0]: 42
8637 13:57:08.739708 [Byte1]: 42
8638 13:57:08.744119
8639 13:57:08.744197 Set Vref, RX VrefLevel [Byte0]: 43
8640 13:57:08.746959 [Byte1]: 43
8641 13:57:08.751388
8642 13:57:08.751467 Set Vref, RX VrefLevel [Byte0]: 44
8643 13:57:08.754608 [Byte1]: 44
8644 13:57:08.759017
8645 13:57:08.759096 Set Vref, RX VrefLevel [Byte0]: 45
8646 13:57:08.762547 [Byte1]: 45
8647 13:57:08.766498
8648 13:57:08.766582 Set Vref, RX VrefLevel [Byte0]: 46
8649 13:57:08.770170 [Byte1]: 46
8650 13:57:08.774221
8651 13:57:08.774300 Set Vref, RX VrefLevel [Byte0]: 47
8652 13:57:08.777783 [Byte1]: 47
8653 13:57:08.781695
8654 13:57:08.781774 Set Vref, RX VrefLevel [Byte0]: 48
8655 13:57:08.785003 [Byte1]: 48
8656 13:57:08.789595
8657 13:57:08.789673 Set Vref, RX VrefLevel [Byte0]: 49
8658 13:57:08.792568 [Byte1]: 49
8659 13:57:08.797084
8660 13:57:08.797163 Set Vref, RX VrefLevel [Byte0]: 50
8661 13:57:08.800531 [Byte1]: 50
8662 13:57:08.804735
8663 13:57:08.804814 Set Vref, RX VrefLevel [Byte0]: 51
8664 13:57:08.808035 [Byte1]: 51
8665 13:57:08.812480
8666 13:57:08.812559 Set Vref, RX VrefLevel [Byte0]: 52
8667 13:57:08.815343 [Byte1]: 52
8668 13:57:08.819845
8669 13:57:08.819951 Set Vref, RX VrefLevel [Byte0]: 53
8670 13:57:08.823348 [Byte1]: 53
8671 13:57:08.827611
8672 13:57:08.827690 Set Vref, RX VrefLevel [Byte0]: 54
8673 13:57:08.831120 [Byte1]: 54
8674 13:57:08.835201
8675 13:57:08.835281 Set Vref, RX VrefLevel [Byte0]: 55
8676 13:57:08.838579 [Byte1]: 55
8677 13:57:08.842652
8678 13:57:08.842731 Set Vref, RX VrefLevel [Byte0]: 56
8679 13:57:08.846169 [Byte1]: 56
8680 13:57:08.850328
8681 13:57:08.850468 Set Vref, RX VrefLevel [Byte0]: 57
8682 13:57:08.853735 [Byte1]: 57
8683 13:57:08.857875
8684 13:57:08.857954 Set Vref, RX VrefLevel [Byte0]: 58
8685 13:57:08.861680 [Byte1]: 58
8686 13:57:08.865509
8687 13:57:08.865587 Set Vref, RX VrefLevel [Byte0]: 59
8688 13:57:08.869037 [Byte1]: 59
8689 13:57:08.873457
8690 13:57:08.873535 Set Vref, RX VrefLevel [Byte0]: 60
8691 13:57:08.876248 [Byte1]: 60
8692 13:57:08.880651
8693 13:57:08.880756 Set Vref, RX VrefLevel [Byte0]: 61
8694 13:57:08.884548 [Byte1]: 61
8695 13:57:08.888168
8696 13:57:08.888247 Set Vref, RX VrefLevel [Byte0]: 62
8697 13:57:08.891825 [Byte1]: 62
8698 13:57:08.895772
8699 13:57:08.895850 Set Vref, RX VrefLevel [Byte0]: 63
8700 13:57:08.899057 [Byte1]: 63
8701 13:57:08.903459
8702 13:57:08.903538 Set Vref, RX VrefLevel [Byte0]: 64
8703 13:57:08.906761 [Byte1]: 64
8704 13:57:08.911098
8705 13:57:08.911177 Set Vref, RX VrefLevel [Byte0]: 65
8706 13:57:08.914427 [Byte1]: 65
8707 13:57:08.918800
8708 13:57:08.918878 Set Vref, RX VrefLevel [Byte0]: 66
8709 13:57:08.922016 [Byte1]: 66
8710 13:57:08.926697
8711 13:57:08.926775 Set Vref, RX VrefLevel [Byte0]: 67
8712 13:57:08.929509 [Byte1]: 67
8713 13:57:08.934176
8714 13:57:08.934281 Set Vref, RX VrefLevel [Byte0]: 68
8715 13:57:08.937449 [Byte1]: 68
8716 13:57:08.941807
8717 13:57:08.941886 Set Vref, RX VrefLevel [Byte0]: 69
8718 13:57:08.945011 [Byte1]: 69
8719 13:57:08.949686
8720 13:57:08.949764 Set Vref, RX VrefLevel [Byte0]: 70
8721 13:57:08.952378 [Byte1]: 70
8722 13:57:08.956933
8723 13:57:08.957013 Set Vref, RX VrefLevel [Byte0]: 71
8724 13:57:08.960287 [Byte1]: 71
8725 13:57:08.964203
8726 13:57:08.964282 Set Vref, RX VrefLevel [Byte0]: 72
8727 13:57:08.967884 [Byte1]: 72
8728 13:57:08.971990
8729 13:57:08.972095 Set Vref, RX VrefLevel [Byte0]: 73
8730 13:57:08.975500 [Byte1]: 73
8731 13:57:08.979841
8732 13:57:08.979919 Final RX Vref Byte 0 = 58 to rank0
8733 13:57:08.983179 Final RX Vref Byte 1 = 54 to rank0
8734 13:57:08.987017 Final RX Vref Byte 0 = 58 to rank1
8735 13:57:08.989655 Final RX Vref Byte 1 = 54 to rank1==
8736 13:57:08.992659 Dram Type= 6, Freq= 0, CH_1, rank 0
8737 13:57:08.999593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 13:57:08.999673 ==
8739 13:57:08.999735 DQS Delay:
8740 13:57:08.999792 DQS0 = 0, DQS1 = 0
8741 13:57:09.002779 DQM Delay:
8742 13:57:09.002858 DQM0 = 131, DQM1 = 124
8743 13:57:09.006550 DQ Delay:
8744 13:57:09.010716 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8745 13:57:09.013182 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8746 13:57:09.016760 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
8747 13:57:09.019590 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8748 13:57:09.019670
8749 13:57:09.019733
8750 13:57:09.019790
8751 13:57:09.022789 [DramC_TX_OE_Calibration] TA2
8752 13:57:09.026433 Original DQ_B0 (3 6) =30, OEN = 27
8753 13:57:09.029207 Original DQ_B1 (3 6) =30, OEN = 27
8754 13:57:09.032878 24, 0x0, End_B0=24 End_B1=24
8755 13:57:09.032959 25, 0x0, End_B0=25 End_B1=25
8756 13:57:09.036854 26, 0x0, End_B0=26 End_B1=26
8757 13:57:09.039999 27, 0x0, End_B0=27 End_B1=27
8758 13:57:09.043142 28, 0x0, End_B0=28 End_B1=28
8759 13:57:09.043222 29, 0x0, End_B0=29 End_B1=29
8760 13:57:09.046677 30, 0x0, End_B0=30 End_B1=30
8761 13:57:09.049677 31, 0x4141, End_B0=30 End_B1=30
8762 13:57:09.052811 Byte0 end_step=30 best_step=27
8763 13:57:09.056491 Byte1 end_step=30 best_step=27
8764 13:57:09.059826 Byte0 TX OE(2T, 0.5T) = (3, 3)
8765 13:57:09.059906 Byte1 TX OE(2T, 0.5T) = (3, 3)
8766 13:57:09.059969
8767 13:57:09.063692
8768 13:57:09.069767 [DQSOSCAuto] RK0, (LSB)MR18= 0x15ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8769 13:57:09.073117 CH1 RK0: MR19=302, MR18=15FF
8770 13:57:09.079672 CH1_RK0: MR19=0x302, MR18=0x15FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8771 13:57:09.079752
8772 13:57:09.083577 ----->DramcWriteLeveling(PI) begin...
8773 13:57:09.083657 ==
8774 13:57:09.086285 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 13:57:09.089852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 13:57:09.089932 ==
8777 13:57:09.093005 Write leveling (Byte 0): 25 => 25
8778 13:57:09.096726 Write leveling (Byte 1): 27 => 27
8779 13:57:09.099653 DramcWriteLeveling(PI) end<-----
8780 13:57:09.099733
8781 13:57:09.099797 ==
8782 13:57:09.103117 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 13:57:09.106738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 13:57:09.106819 ==
8785 13:57:09.109742 [Gating] SW mode calibration
8786 13:57:09.116663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8787 13:57:09.123193 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8788 13:57:09.126979 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 13:57:09.129843 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 13:57:09.136724 1 4 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8791 13:57:09.139741 1 4 12 | B1->B0 | 2525 3434 | 1 0 | (0 0) (1 1)
8792 13:57:09.143184 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 13:57:09.146569 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 13:57:09.153192 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 13:57:09.156577 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 13:57:09.159903 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 13:57:09.166497 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8798 13:57:09.170285 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
8799 13:57:09.174160 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8800 13:57:09.179595 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8801 13:57:09.183392 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 13:57:09.186653 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 13:57:09.193566 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 13:57:09.196568 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 13:57:09.200021 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8806 13:57:09.207417 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8807 13:57:09.209835 1 6 12 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
8808 13:57:09.213153 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 13:57:09.220227 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 13:57:09.223482 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 13:57:09.226716 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 13:57:09.231071 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 13:57:09.236785 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8814 13:57:09.239991 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8815 13:57:09.243592 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8816 13:57:09.250176 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8817 13:57:09.253412 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 13:57:09.256874 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 13:57:09.263607 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 13:57:09.266790 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 13:57:09.269857 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 13:57:09.277366 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 13:57:09.280688 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 13:57:09.283714 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 13:57:09.289844 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 13:57:09.293420 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 13:57:09.297121 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 13:57:09.302962 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 13:57:09.306465 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8830 13:57:09.309940 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8831 13:57:09.313002 Total UI for P1: 0, mck2ui 16
8832 13:57:09.316629 best dqsien dly found for B0: ( 1, 9, 4)
8833 13:57:09.323425 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8834 13:57:09.326326 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8835 13:57:09.329937 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 13:57:09.333448 Total UI for P1: 0, mck2ui 16
8837 13:57:09.336410 best dqsien dly found for B1: ( 1, 9, 14)
8838 13:57:09.339467 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8839 13:57:09.342850 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8840 13:57:09.342931
8841 13:57:09.346900 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8842 13:57:09.353281 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8843 13:57:09.353362 [Gating] SW calibration Done
8844 13:57:09.353426 ==
8845 13:57:09.356840 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 13:57:09.363653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 13:57:09.363750 ==
8848 13:57:09.363816 RX Vref Scan: 0
8849 13:57:09.363876
8850 13:57:09.366168 RX Vref 0 -> 0, step: 1
8851 13:57:09.366249
8852 13:57:09.369575 RX Delay 0 -> 252, step: 8
8853 13:57:09.373159 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8854 13:57:09.376465 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8855 13:57:09.379858 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8856 13:57:09.386249 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8857 13:57:09.389399 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8858 13:57:09.392744 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8859 13:57:09.396548 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8860 13:57:09.399690 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8861 13:57:09.402729 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8862 13:57:09.409697 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8863 13:57:09.413085 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8864 13:57:09.416301 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8865 13:57:09.419403 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8866 13:57:09.426145 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8867 13:57:09.429523 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8868 13:57:09.433029 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8869 13:57:09.433109 ==
8870 13:57:09.436132 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 13:57:09.439819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 13:57:09.439899 ==
8873 13:57:09.442936 DQS Delay:
8874 13:57:09.443016 DQS0 = 0, DQS1 = 0
8875 13:57:09.446097 DQM Delay:
8876 13:57:09.446176 DQM0 = 132, DQM1 = 127
8877 13:57:09.446239 DQ Delay:
8878 13:57:09.452694 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8879 13:57:09.455720 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8880 13:57:09.459626 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8881 13:57:09.462357 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8882 13:57:09.462464
8883 13:57:09.462530
8884 13:57:09.462590 ==
8885 13:57:09.466199 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 13:57:09.469705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 13:57:09.469787 ==
8888 13:57:09.469851
8889 13:57:09.469910
8890 13:57:09.472836 TX Vref Scan disable
8891 13:57:09.475841 == TX Byte 0 ==
8892 13:57:09.479650 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8893 13:57:09.482572 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8894 13:57:09.485802 == TX Byte 1 ==
8895 13:57:09.489103 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8896 13:57:09.492678 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8897 13:57:09.492758 ==
8898 13:57:09.495812 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 13:57:09.499185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 13:57:09.499266 ==
8901 13:57:09.514614
8902 13:57:09.517963 TX Vref early break, caculate TX vref
8903 13:57:09.520982 TX Vref=16, minBit 8, minWin=22, winSum=378
8904 13:57:09.524810 TX Vref=18, minBit 5, minWin=23, winSum=387
8905 13:57:09.527875 TX Vref=20, minBit 8, minWin=24, winSum=398
8906 13:57:09.531124 TX Vref=22, minBit 8, minWin=24, winSum=407
8907 13:57:09.534573 TX Vref=24, minBit 9, minWin=24, winSum=411
8908 13:57:09.541283 TX Vref=26, minBit 0, minWin=25, winSum=419
8909 13:57:09.544771 TX Vref=28, minBit 13, minWin=25, winSum=424
8910 13:57:09.547614 TX Vref=30, minBit 0, minWin=25, winSum=418
8911 13:57:09.551476 TX Vref=32, minBit 0, minWin=24, winSum=413
8912 13:57:09.554247 TX Vref=34, minBit 9, minWin=24, winSum=404
8913 13:57:09.557805 TX Vref=36, minBit 9, minWin=23, winSum=395
8914 13:57:09.564965 [TxChooseVref] Worse bit 13, Min win 25, Win sum 424, Final Vref 28
8915 13:57:09.565047
8916 13:57:09.567355 Final TX Range 0 Vref 28
8917 13:57:09.567436
8918 13:57:09.567499 ==
8919 13:57:09.571019 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 13:57:09.574632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 13:57:09.574713 ==
8922 13:57:09.574776
8923 13:57:09.578108
8924 13:57:09.578188 TX Vref Scan disable
8925 13:57:09.584055 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8926 13:57:09.584136 == TX Byte 0 ==
8927 13:57:09.588689 u2DelayCellOfst[0]=17 cells (5 PI)
8928 13:57:09.590799 u2DelayCellOfst[1]=10 cells (3 PI)
8929 13:57:09.594457 u2DelayCellOfst[2]=0 cells (0 PI)
8930 13:57:09.597453 u2DelayCellOfst[3]=7 cells (2 PI)
8931 13:57:09.600715 u2DelayCellOfst[4]=7 cells (2 PI)
8932 13:57:09.604705 u2DelayCellOfst[5]=17 cells (5 PI)
8933 13:57:09.607538 u2DelayCellOfst[6]=17 cells (5 PI)
8934 13:57:09.610522 u2DelayCellOfst[7]=3 cells (1 PI)
8935 13:57:09.614521 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8936 13:57:09.617400 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8937 13:57:09.620891 == TX Byte 1 ==
8938 13:57:09.623917 u2DelayCellOfst[8]=0 cells (0 PI)
8939 13:57:09.627583 u2DelayCellOfst[9]=7 cells (2 PI)
8940 13:57:09.627662 u2DelayCellOfst[10]=14 cells (4 PI)
8941 13:57:09.630916 u2DelayCellOfst[11]=10 cells (3 PI)
8942 13:57:09.633798 u2DelayCellOfst[12]=17 cells (5 PI)
8943 13:57:09.637047 u2DelayCellOfst[13]=17 cells (5 PI)
8944 13:57:09.640568 u2DelayCellOfst[14]=21 cells (6 PI)
8945 13:57:09.643669 u2DelayCellOfst[15]=17 cells (5 PI)
8946 13:57:09.650846 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8947 13:57:09.654124 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8948 13:57:09.654205 DramC Write-DBI on
8949 13:57:09.654268 ==
8950 13:57:09.657445 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 13:57:09.663676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 13:57:09.663758 ==
8953 13:57:09.663822
8954 13:57:09.663880
8955 13:57:09.663936 TX Vref Scan disable
8956 13:57:09.667752 == TX Byte 0 ==
8957 13:57:09.671582 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8958 13:57:09.674514 == TX Byte 1 ==
8959 13:57:09.678166 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8960 13:57:09.681036 DramC Write-DBI off
8961 13:57:09.681116
8962 13:57:09.681180 [DATLAT]
8963 13:57:09.681239 Freq=1600, CH1 RK1
8964 13:57:09.681296
8965 13:57:09.685178 DATLAT Default: 0xf
8966 13:57:09.685258 0, 0xFFFF, sum = 0
8967 13:57:09.687848 1, 0xFFFF, sum = 0
8968 13:57:09.687930 2, 0xFFFF, sum = 0
8969 13:57:09.691429 3, 0xFFFF, sum = 0
8970 13:57:09.695030 4, 0xFFFF, sum = 0
8971 13:57:09.695112 5, 0xFFFF, sum = 0
8972 13:57:09.698574 6, 0xFFFF, sum = 0
8973 13:57:09.698655 7, 0xFFFF, sum = 0
8974 13:57:09.701028 8, 0xFFFF, sum = 0
8975 13:57:09.701110 9, 0xFFFF, sum = 0
8976 13:57:09.704331 10, 0xFFFF, sum = 0
8977 13:57:09.704412 11, 0xFFFF, sum = 0
8978 13:57:09.707770 12, 0xFFFF, sum = 0
8979 13:57:09.707851 13, 0xFFFF, sum = 0
8980 13:57:09.711238 14, 0x0, sum = 1
8981 13:57:09.711319 15, 0x0, sum = 2
8982 13:57:09.714600 16, 0x0, sum = 3
8983 13:57:09.714680 17, 0x0, sum = 4
8984 13:57:09.718375 best_step = 15
8985 13:57:09.718491
8986 13:57:09.718554 ==
8987 13:57:09.721524 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 13:57:09.724943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 13:57:09.725023 ==
8990 13:57:09.725085 RX Vref Scan: 0
8991 13:57:09.725143
8992 13:57:09.727836 RX Vref 0 -> 0, step: 1
8993 13:57:09.727915
8994 13:57:09.731563 RX Delay 11 -> 252, step: 4
8995 13:57:09.735049 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8996 13:57:09.741084 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8997 13:57:09.744921 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8998 13:57:09.748561 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8999 13:57:09.751238 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9000 13:57:09.754556 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9001 13:57:09.758029 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9002 13:57:09.764890 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9003 13:57:09.767748 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9004 13:57:09.771291 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9005 13:57:09.774728 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9006 13:57:09.778079 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
9007 13:57:09.784595 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9008 13:57:09.787922 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9009 13:57:09.791302 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9010 13:57:09.794855 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9011 13:57:09.794935 ==
9012 13:57:09.798243 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 13:57:09.804819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 13:57:09.804918 ==
9015 13:57:09.805017 DQS Delay:
9016 13:57:09.808179 DQS0 = 0, DQS1 = 0
9017 13:57:09.808258 DQM Delay:
9018 13:57:09.808320 DQM0 = 129, DQM1 = 125
9019 13:57:09.811149 DQ Delay:
9020 13:57:09.814653 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9021 13:57:09.818097 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9022 13:57:09.821880 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =116
9023 13:57:09.825276 DQ12 =134, DQ13 =136, DQ14 =132, DQ15 =134
9024 13:57:09.825355
9025 13:57:09.825417
9026 13:57:09.825474
9027 13:57:09.827963 [DramC_TX_OE_Calibration] TA2
9028 13:57:09.831254 Original DQ_B0 (3 6) =30, OEN = 27
9029 13:57:09.835159 Original DQ_B1 (3 6) =30, OEN = 27
9030 13:57:09.838316 24, 0x0, End_B0=24 End_B1=24
9031 13:57:09.838461 25, 0x0, End_B0=25 End_B1=25
9032 13:57:09.841196 26, 0x0, End_B0=26 End_B1=26
9033 13:57:09.844725 27, 0x0, End_B0=27 End_B1=27
9034 13:57:09.848144 28, 0x0, End_B0=28 End_B1=28
9035 13:57:09.851747 29, 0x0, End_B0=29 End_B1=29
9036 13:57:09.851827 30, 0x0, End_B0=30 End_B1=30
9037 13:57:09.855024 31, 0x4141, End_B0=30 End_B1=30
9038 13:57:09.858092 Byte0 end_step=30 best_step=27
9039 13:57:09.861337 Byte1 end_step=30 best_step=27
9040 13:57:09.865135 Byte0 TX OE(2T, 0.5T) = (3, 3)
9041 13:57:09.865215 Byte1 TX OE(2T, 0.5T) = (3, 3)
9042 13:57:09.868010
9043 13:57:09.868089
9044 13:57:09.874548 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9045 13:57:09.878522 CH1 RK1: MR19=303, MR18=1016
9046 13:57:09.884560 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9047 13:57:09.888033 [RxdqsGatingPostProcess] freq 1600
9048 13:57:09.891563 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9049 13:57:09.894866 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 13:57:09.897977 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 13:57:09.901511 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 13:57:09.905060 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 13:57:09.910172 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 13:57:09.911640 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 13:57:09.914823 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 13:57:09.918845 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 13:57:09.918925 Pre-setting of DQS Precalculation
9058 13:57:09.925244 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9059 13:57:09.931771 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9060 13:57:09.938061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 13:57:09.938141
9062 13:57:09.938202
9063 13:57:09.941203 [Calibration Summary] 3200 Mbps
9064 13:57:09.944798 CH 0, Rank 0
9065 13:57:09.944876 SW Impedance : PASS
9066 13:57:09.948194 DUTY Scan : NO K
9067 13:57:09.951258 ZQ Calibration : PASS
9068 13:57:09.951337 Jitter Meter : NO K
9069 13:57:09.954694 CBT Training : PASS
9070 13:57:09.958010 Write leveling : PASS
9071 13:57:09.958090 RX DQS gating : PASS
9072 13:57:09.961671 RX DQ/DQS(RDDQC) : PASS
9073 13:57:09.961750 TX DQ/DQS : PASS
9074 13:57:09.964834 RX DATLAT : PASS
9075 13:57:09.967834 RX DQ/DQS(Engine): PASS
9076 13:57:09.967913 TX OE : PASS
9077 13:57:09.971217 All Pass.
9078 13:57:09.971296
9079 13:57:09.971358 CH 0, Rank 1
9080 13:57:09.974881 SW Impedance : PASS
9081 13:57:09.974959 DUTY Scan : NO K
9082 13:57:09.978598 ZQ Calibration : PASS
9083 13:57:09.981612 Jitter Meter : NO K
9084 13:57:09.981691 CBT Training : PASS
9085 13:57:09.984669 Write leveling : PASS
9086 13:57:09.987899 RX DQS gating : PASS
9087 13:57:09.987978 RX DQ/DQS(RDDQC) : PASS
9088 13:57:09.991433 TX DQ/DQS : PASS
9089 13:57:09.994842 RX DATLAT : PASS
9090 13:57:09.994920 RX DQ/DQS(Engine): PASS
9091 13:57:09.998288 TX OE : PASS
9092 13:57:09.998393 All Pass.
9093 13:57:09.998467
9094 13:57:10.001324 CH 1, Rank 0
9095 13:57:10.001403 SW Impedance : PASS
9096 13:57:10.004706 DUTY Scan : NO K
9097 13:57:10.004785 ZQ Calibration : PASS
9098 13:57:10.007858 Jitter Meter : NO K
9099 13:57:10.011748 CBT Training : PASS
9100 13:57:10.011827 Write leveling : PASS
9101 13:57:10.015132 RX DQS gating : PASS
9102 13:57:10.018344 RX DQ/DQS(RDDQC) : PASS
9103 13:57:10.018474 TX DQ/DQS : PASS
9104 13:57:10.021945 RX DATLAT : PASS
9105 13:57:10.025291 RX DQ/DQS(Engine): PASS
9106 13:57:10.025369 TX OE : PASS
9107 13:57:10.028199 All Pass.
9108 13:57:10.028278
9109 13:57:10.028340 CH 1, Rank 1
9110 13:57:10.032488 SW Impedance : PASS
9111 13:57:10.032567 DUTY Scan : NO K
9112 13:57:10.035140 ZQ Calibration : PASS
9113 13:57:10.038300 Jitter Meter : NO K
9114 13:57:10.038410 CBT Training : PASS
9115 13:57:10.041661 Write leveling : PASS
9116 13:57:10.045404 RX DQS gating : PASS
9117 13:57:10.045483 RX DQ/DQS(RDDQC) : PASS
9118 13:57:10.048373 TX DQ/DQS : PASS
9119 13:57:10.048452 RX DATLAT : PASS
9120 13:57:10.051557 RX DQ/DQS(Engine): PASS
9121 13:57:10.054728 TX OE : PASS
9122 13:57:10.054807 All Pass.
9123 13:57:10.054870
9124 13:57:10.058061 DramC Write-DBI on
9125 13:57:10.058140 PER_BANK_REFRESH: Hybrid Mode
9126 13:57:10.061566 TX_TRACKING: ON
9127 13:57:10.071366 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9128 13:57:10.077802 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9129 13:57:10.084809 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9130 13:57:10.088006 [FAST_K] Save calibration result to emmc
9131 13:57:10.091413 sync common calibartion params.
9132 13:57:10.095031 sync cbt_mode0:1, 1:1
9133 13:57:10.095110 dram_init: ddr_geometry: 2
9134 13:57:10.098202 dram_init: ddr_geometry: 2
9135 13:57:10.101604 dram_init: ddr_geometry: 2
9136 13:57:10.104572 0:dram_rank_size:100000000
9137 13:57:10.104651 1:dram_rank_size:100000000
9138 13:57:10.111267 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9139 13:57:10.115326 DFS_SHUFFLE_HW_MODE: ON
9140 13:57:10.118084 dramc_set_vcore_voltage set vcore to 725000
9141 13:57:10.118162 Read voltage for 1600, 0
9142 13:57:10.121357 Vio18 = 0
9143 13:57:10.121434 Vcore = 725000
9144 13:57:10.121495 Vdram = 0
9145 13:57:10.125105 Vddq = 0
9146 13:57:10.125196 Vmddr = 0
9147 13:57:10.128272 switch to 3200 Mbps bootup
9148 13:57:10.128394 [DramcRunTimeConfig]
9149 13:57:10.128507 PHYPLL
9150 13:57:10.131903 DPM_CONTROL_AFTERK: ON
9151 13:57:10.135360 PER_BANK_REFRESH: ON
9152 13:57:10.135439 REFRESH_OVERHEAD_REDUCTION: ON
9153 13:57:10.138724 CMD_PICG_NEW_MODE: OFF
9154 13:57:10.141630 XRTWTW_NEW_MODE: ON
9155 13:57:10.141741 XRTRTR_NEW_MODE: ON
9156 13:57:10.144701 TX_TRACKING: ON
9157 13:57:10.144778 RDSEL_TRACKING: OFF
9158 13:57:10.148075 DQS Precalculation for DVFS: ON
9159 13:57:10.148153 RX_TRACKING: OFF
9160 13:57:10.151693 HW_GATING DBG: ON
9161 13:57:10.151771 ZQCS_ENABLE_LP4: ON
9162 13:57:10.155018 RX_PICG_NEW_MODE: ON
9163 13:57:10.157996 TX_PICG_NEW_MODE: ON
9164 13:57:10.158074 ENABLE_RX_DCM_DPHY: ON
9165 13:57:10.161688 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9166 13:57:10.165080 DUMMY_READ_FOR_TRACKING: OFF
9167 13:57:10.168490 !!! SPM_CONTROL_AFTERK: OFF
9168 13:57:10.171684 !!! SPM could not control APHY
9169 13:57:10.171816 IMPEDANCE_TRACKING: ON
9170 13:57:10.174923 TEMP_SENSOR: ON
9171 13:57:10.175037 HW_SAVE_FOR_SR: OFF
9172 13:57:10.178145 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9173 13:57:10.181876 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9174 13:57:10.184665 Read ODT Tracking: ON
9175 13:57:10.184743 Refresh Rate DeBounce: ON
9176 13:57:10.188184 DFS_NO_QUEUE_FLUSH: ON
9177 13:57:10.192329 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9178 13:57:10.195089 ENABLE_DFS_RUNTIME_MRW: OFF
9179 13:57:10.195167 DDR_RESERVE_NEW_MODE: ON
9180 13:57:10.198455 MR_CBT_SWITCH_FREQ: ON
9181 13:57:10.201856 =========================
9182 13:57:10.219746 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9183 13:57:10.222928 dram_init: ddr_geometry: 2
9184 13:57:10.241103 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9185 13:57:10.244186 dram_init: dram init end (result: 0)
9186 13:57:10.251123 DRAM-K: Full calibration passed in 24613 msecs
9187 13:57:10.254167 MRC: failed to locate region type 0.
9188 13:57:10.254246 DRAM rank0 size:0x100000000,
9189 13:57:10.257537 DRAM rank1 size=0x100000000
9190 13:57:10.267897 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9191 13:57:10.274336 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9192 13:57:10.280936 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9193 13:57:10.287457 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9194 13:57:10.291212 DRAM rank0 size:0x100000000,
9195 13:57:10.294542 DRAM rank1 size=0x100000000
9196 13:57:10.294621 CBMEM:
9197 13:57:10.297627 IMD: root @ 0xfffff000 254 entries.
9198 13:57:10.301406 IMD: root @ 0xffffec00 62 entries.
9199 13:57:10.304350 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9200 13:57:10.307794 WARNING: RO_VPD is uninitialized or empty.
9201 13:57:10.314352 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9202 13:57:10.320845 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9203 13:57:10.333984 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9204 13:57:10.345753 BS: romstage times (exec / console): total (unknown) / 24110 ms
9205 13:57:10.345835
9206 13:57:10.345898
9207 13:57:10.355227 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9208 13:57:10.358807 ARM64: Exception handlers installed.
9209 13:57:10.361753 ARM64: Testing exception
9210 13:57:10.365102 ARM64: Done test exception
9211 13:57:10.365182 Enumerating buses...
9212 13:57:10.368816 Show all devs... Before device enumeration.
9213 13:57:10.371901 Root Device: enabled 1
9214 13:57:10.375262 CPU_CLUSTER: 0: enabled 1
9215 13:57:10.375342 CPU: 00: enabled 1
9216 13:57:10.378684 Compare with tree...
9217 13:57:10.378764 Root Device: enabled 1
9218 13:57:10.382319 CPU_CLUSTER: 0: enabled 1
9219 13:57:10.385473 CPU: 00: enabled 1
9220 13:57:10.385553 Root Device scanning...
9221 13:57:10.388537 scan_static_bus for Root Device
9222 13:57:10.392252 CPU_CLUSTER: 0 enabled
9223 13:57:10.395464 scan_static_bus for Root Device done
9224 13:57:10.398998 scan_bus: bus Root Device finished in 8 msecs
9225 13:57:10.399079 done
9226 13:57:10.405741 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9227 13:57:10.409028 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9228 13:57:10.415292 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9229 13:57:10.418996 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9230 13:57:10.422554 Allocating resources...
9231 13:57:10.422635 Reading resources...
9232 13:57:10.425870 Root Device read_resources bus 0 link: 0
9233 13:57:10.429008 DRAM rank0 size:0x100000000,
9234 13:57:10.431954 DRAM rank1 size=0x100000000
9235 13:57:10.435534 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9236 13:57:10.438793 CPU: 00 missing read_resources
9237 13:57:10.441766 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9238 13:57:10.448682 Root Device read_resources bus 0 link: 0 done
9239 13:57:10.448763 Done reading resources.
9240 13:57:10.455905 Show resources in subtree (Root Device)...After reading.
9241 13:57:10.458620 Root Device child on link 0 CPU_CLUSTER: 0
9242 13:57:10.462425 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 13:57:10.471792 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 13:57:10.471874 CPU: 00
9245 13:57:10.474978 Root Device assign_resources, bus 0 link: 0
9246 13:57:10.478867 CPU_CLUSTER: 0 missing set_resources
9247 13:57:10.481869 Root Device assign_resources, bus 0 link: 0 done
9248 13:57:10.485542 Done setting resources.
9249 13:57:10.492493 Show resources in subtree (Root Device)...After assigning values.
9250 13:57:10.495559 Root Device child on link 0 CPU_CLUSTER: 0
9251 13:57:10.498782 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 13:57:10.508548 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 13:57:10.508630 CPU: 00
9254 13:57:10.512323 Done allocating resources.
9255 13:57:10.515254 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9256 13:57:10.518607 Enabling resources...
9257 13:57:10.518686 done.
9258 13:57:10.522027 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9259 13:57:10.525409 Initializing devices...
9260 13:57:10.528428 Root Device init
9261 13:57:10.528508 init hardware done!
9262 13:57:10.532000 0x00000018: ctrlr->caps
9263 13:57:10.532082 52.000 MHz: ctrlr->f_max
9264 13:57:10.535631 0.400 MHz: ctrlr->f_min
9265 13:57:10.538871 0x40ff8080: ctrlr->voltages
9266 13:57:10.538954 sclk: 390625
9267 13:57:10.542253 Bus Width = 1
9268 13:57:10.542333 sclk: 390625
9269 13:57:10.542404 Bus Width = 1
9270 13:57:10.545124 Early init status = 3
9271 13:57:10.548383 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9272 13:57:10.552997 in-header: 03 fc 00 00 01 00 00 00
9273 13:57:10.556561 in-data: 00
9274 13:57:10.560326 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9275 13:57:10.565468 in-header: 03 fd 00 00 00 00 00 00
9276 13:57:10.568874 in-data:
9277 13:57:10.571739 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 13:57:10.576196 in-header: 03 fc 00 00 01 00 00 00
9279 13:57:10.579406 in-data: 00
9280 13:57:10.582742 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9281 13:57:10.588408 in-header: 03 fd 00 00 00 00 00 00
9282 13:57:10.592270 in-data:
9283 13:57:10.595106 [SSUSB] Setting up USB HOST controller...
9284 13:57:10.598787 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9285 13:57:10.602001 [SSUSB] phy power-on done.
9286 13:57:10.605296 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9287 13:57:10.611798 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9288 13:57:10.615920 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9289 13:57:10.621761 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9290 13:57:10.628353 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9291 13:57:10.635220 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9292 13:57:10.641780 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9293 13:57:10.648425 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9294 13:57:10.648508 SPM: binary array size = 0x9dc
9295 13:57:10.654999 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9296 13:57:10.662363 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9297 13:57:10.668982 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9298 13:57:10.671881 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9299 13:57:10.675064 configure_display: Starting display init
9300 13:57:10.712238 anx7625_power_on_init: Init interface.
9301 13:57:10.715116 anx7625_disable_pd_protocol: Disabled PD feature.
9302 13:57:10.718553 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9303 13:57:10.746308 anx7625_start_dp_work: Secure OCM version=00
9304 13:57:10.750108 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9305 13:57:10.764212 sp_tx_get_edid_block: EDID Block = 1
9306 13:57:10.866664 Extracted contents:
9307 13:57:10.870540 header: 00 ff ff ff ff ff ff 00
9308 13:57:10.874246 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9309 13:57:10.876798 version: 01 04
9310 13:57:10.880437 basic params: 95 1f 11 78 0a
9311 13:57:10.884089 chroma info: 76 90 94 55 54 90 27 21 50 54
9312 13:57:10.887096 established: 00 00 00
9313 13:57:10.893624 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9314 13:57:10.896803 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9315 13:57:10.903743 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9316 13:57:10.910003 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9317 13:57:10.916592 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9318 13:57:10.920295 extensions: 00
9319 13:57:10.920375 checksum: fb
9320 13:57:10.920439
9321 13:57:10.923585 Manufacturer: IVO Model 57d Serial Number 0
9322 13:57:10.926948 Made week 0 of 2020
9323 13:57:10.927028 EDID version: 1.4
9324 13:57:10.930299 Digital display
9325 13:57:10.933146 6 bits per primary color channel
9326 13:57:10.933228 DisplayPort interface
9327 13:57:10.936580 Maximum image size: 31 cm x 17 cm
9328 13:57:10.940282 Gamma: 220%
9329 13:57:10.940363 Check DPMS levels
9330 13:57:10.943289 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9331 13:57:10.946791 First detailed timing is preferred timing
9332 13:57:10.950015 Established timings supported:
9333 13:57:10.953608 Standard timings supported:
9334 13:57:10.953688 Detailed timings
9335 13:57:10.960327 Hex of detail: 383680a07038204018303c0035ae10000019
9336 13:57:10.963069 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9337 13:57:10.969757 0780 0798 07c8 0820 hborder 0
9338 13:57:10.973267 0438 043b 0447 0458 vborder 0
9339 13:57:10.973347 -hsync -vsync
9340 13:57:10.977057 Did detailed timing
9341 13:57:10.980008 Hex of detail: 000000000000000000000000000000000000
9342 13:57:10.983502 Manufacturer-specified data, tag 0
9343 13:57:10.989874 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9344 13:57:10.989955 ASCII string: InfoVision
9345 13:57:10.996785 Hex of detail: 000000fe00523134304e574635205248200a
9346 13:57:10.999772 ASCII string: R140NWF5 RH
9347 13:57:10.999852 Checksum
9348 13:57:10.999915 Checksum: 0xfb (valid)
9349 13:57:11.006889 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9350 13:57:11.009840 DSI data_rate: 832800000 bps
9351 13:57:11.013109 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9352 13:57:11.016538 anx7625_parse_edid: pixelclock(138800).
9353 13:57:11.023629 hactive(1920), hsync(48), hfp(24), hbp(88)
9354 13:57:11.026578 vactive(1080), vsync(12), vfp(3), vbp(17)
9355 13:57:11.030490 anx7625_dsi_config: config dsi.
9356 13:57:11.036328 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9357 13:57:11.049090 anx7625_dsi_config: success to config DSI
9358 13:57:11.052141 anx7625_dp_start: MIPI phy setup OK.
9359 13:57:11.056435 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9360 13:57:11.059481 mtk_ddp_mode_set invalid vrefresh 60
9361 13:57:11.063084 main_disp_path_setup
9362 13:57:11.063164 ovl_layer_smi_id_en
9363 13:57:11.065717 ovl_layer_smi_id_en
9364 13:57:11.065797 ccorr_config
9365 13:57:11.065861 aal_config
9366 13:57:11.069233 gamma_config
9367 13:57:11.069313 postmask_config
9368 13:57:11.069378 dither_config
9369 13:57:11.076343 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9370 13:57:11.082555 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9371 13:57:11.085536 Root Device init finished in 554 msecs
9372 13:57:11.085616 CPU_CLUSTER: 0 init
9373 13:57:11.095590 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9374 13:57:11.099216 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9375 13:57:11.102558 APU_MBOX 0x190000b0 = 0x10001
9376 13:57:11.105897 APU_MBOX 0x190001b0 = 0x10001
9377 13:57:11.109221 APU_MBOX 0x190005b0 = 0x10001
9378 13:57:11.112368 APU_MBOX 0x190006b0 = 0x10001
9379 13:57:11.115707 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9380 13:57:11.127815 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9381 13:57:11.140487 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9382 13:57:11.147234 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9383 13:57:11.158384 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9384 13:57:11.167596 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9385 13:57:11.170931 CPU_CLUSTER: 0 init finished in 81 msecs
9386 13:57:11.175331 Devices initialized
9387 13:57:11.177639 Show all devs... After init.
9388 13:57:11.177719 Root Device: enabled 1
9389 13:57:11.181305 CPU_CLUSTER: 0: enabled 1
9390 13:57:11.184533 CPU: 00: enabled 1
9391 13:57:11.187816 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9392 13:57:11.191111 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9393 13:57:11.194181 ELOG: NV offset 0x57f000 size 0x1000
9394 13:57:11.200992 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9395 13:57:11.207657 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9396 13:57:11.211195 ELOG: Event(17) added with size 13 at 2024-02-01 13:57:12 UTC
9397 13:57:11.214141 out: cmd=0x121: 03 db 21 01 00 00 00 00
9398 13:57:11.218584 in-header: 03 b2 00 00 2c 00 00 00
9399 13:57:11.231430 in-data: ad 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9400 13:57:11.237765 ELOG: Event(A1) added with size 10 at 2024-02-01 13:57:12 UTC
9401 13:57:11.244827 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9402 13:57:11.251242 ELOG: Event(A0) added with size 9 at 2024-02-01 13:57:12 UTC
9403 13:57:11.254617 elog_add_boot_reason: Logged dev mode boot
9404 13:57:11.257969 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9405 13:57:11.261916 Finalize devices...
9406 13:57:11.261995 Devices finalized
9407 13:57:11.268113 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9408 13:57:11.271074 Writing coreboot table at 0xffe64000
9409 13:57:11.274316 0. 000000000010a000-0000000000113fff: RAMSTAGE
9410 13:57:11.278242 1. 0000000040000000-00000000400fffff: RAM
9411 13:57:11.285421 2. 0000000040100000-000000004032afff: RAMSTAGE
9412 13:57:11.287956 3. 000000004032b000-00000000545fffff: RAM
9413 13:57:11.290982 4. 0000000054600000-000000005465ffff: BL31
9414 13:57:11.294595 5. 0000000054660000-00000000ffe63fff: RAM
9415 13:57:11.301256 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9416 13:57:11.304602 7. 0000000100000000-000000023fffffff: RAM
9417 13:57:11.304683 Passing 5 GPIOs to payload:
9418 13:57:11.311265 NAME | PORT | POLARITY | VALUE
9419 13:57:11.314192 EC in RW | 0x000000aa | low | undefined
9420 13:57:11.320892 EC interrupt | 0x00000005 | low | undefined
9421 13:57:11.324517 TPM interrupt | 0x000000ab | high | undefined
9422 13:57:11.330987 SD card detect | 0x00000011 | high | undefined
9423 13:57:11.333976 speaker enable | 0x00000093 | high | undefined
9424 13:57:11.337434 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9425 13:57:11.340924 in-header: 03 f9 00 00 02 00 00 00
9426 13:57:11.341006 in-data: 02 00
9427 13:57:11.344476 ADC[4]: Raw value=900221 ID=7
9428 13:57:11.347220 ADC[3]: Raw value=213336 ID=1
9429 13:57:11.347301 RAM Code: 0x71
9430 13:57:11.351168 ADC[6]: Raw value=74926 ID=0
9431 13:57:11.354074 ADC[5]: Raw value=211860 ID=1
9432 13:57:11.357094 SKU Code: 0x1
9433 13:57:11.360947 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum af6e
9434 13:57:11.364195 coreboot table: 964 bytes.
9435 13:57:11.367330 IMD ROOT 0. 0xfffff000 0x00001000
9436 13:57:11.370682 IMD SMALL 1. 0xffffe000 0x00001000
9437 13:57:11.373964 RO MCACHE 2. 0xffffc000 0x00001104
9438 13:57:11.377510 CONSOLE 3. 0xfff7c000 0x00080000
9439 13:57:11.380471 FMAP 4. 0xfff7b000 0x00000452
9440 13:57:11.384104 TIME STAMP 5. 0xfff7a000 0x00000910
9441 13:57:11.388036 VBOOT WORK 6. 0xfff66000 0x00014000
9442 13:57:11.391433 RAMOOPS 7. 0xffe66000 0x00100000
9443 13:57:11.393954 COREBOOT 8. 0xffe64000 0x00002000
9444 13:57:11.394035 IMD small region:
9445 13:57:11.397277 IMD ROOT 0. 0xffffec00 0x00000400
9446 13:57:11.400592 VPD 1. 0xffffeb80 0x0000006c
9447 13:57:11.404102 MMC STATUS 2. 0xffffeb60 0x00000004
9448 13:57:11.410668 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9449 13:57:11.414075 Probing TPM: done!
9450 13:57:11.417523 Connected to device vid:did:rid of 1ae0:0028:00
9451 13:57:11.427541 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9452 13:57:11.431221 Initialized TPM device CR50 revision 0
9453 13:57:11.434509 Checking cr50 for pending updates
9454 13:57:11.437634 Reading cr50 TPM mode
9455 13:57:11.446474 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9456 13:57:11.453557 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9457 13:57:11.492979 read SPI 0x3990ec 0x4f1b0: 34857 us, 9295 KB/s, 74.360 Mbps
9458 13:57:11.496764 Checking segment from ROM address 0x40100000
9459 13:57:11.499765 Checking segment from ROM address 0x4010001c
9460 13:57:11.506704 Loading segment from ROM address 0x40100000
9461 13:57:11.506786 code (compression=0)
9462 13:57:11.512949 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9463 13:57:11.523405 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9464 13:57:11.523485 it's not compressed!
9465 13:57:11.530164 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9466 13:57:11.533776 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9467 13:57:11.553910 Loading segment from ROM address 0x4010001c
9468 13:57:11.553991 Entry Point 0x80000000
9469 13:57:11.557111 Loaded segments
9470 13:57:11.560517 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9471 13:57:11.567227 Jumping to boot code at 0x80000000(0xffe64000)
9472 13:57:11.574130 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9473 13:57:11.580333 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9474 13:57:11.587739 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9475 13:57:11.591541 Checking segment from ROM address 0x40100000
9476 13:57:11.595229 Checking segment from ROM address 0x4010001c
9477 13:57:11.601276 Loading segment from ROM address 0x40100000
9478 13:57:11.601356 code (compression=1)
9479 13:57:11.607832 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9480 13:57:11.618455 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9481 13:57:11.618538 using LZMA
9482 13:57:11.626129 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9483 13:57:11.633071 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9484 13:57:11.636539 Loading segment from ROM address 0x4010001c
9485 13:57:11.636621 Entry Point 0x54601000
9486 13:57:11.639825 Loaded segments
9487 13:57:11.643175 NOTICE: MT8192 bl31_setup
9488 13:57:11.650140 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9489 13:57:11.653334 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9490 13:57:11.656744 WARNING: region 0:
9491 13:57:11.659709 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 13:57:11.659790 WARNING: region 1:
9493 13:57:11.666598 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9494 13:57:11.670494 WARNING: region 2:
9495 13:57:11.673108 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9496 13:57:11.676640 WARNING: region 3:
9497 13:57:11.680003 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9498 13:57:11.684038 WARNING: region 4:
9499 13:57:11.686866 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 13:57:11.689990 WARNING: region 5:
9501 13:57:11.693265 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 13:57:11.697121 WARNING: region 6:
9503 13:57:11.700118 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 13:57:11.700200 WARNING: region 7:
9505 13:57:11.706694 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 13:57:11.713762 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9507 13:57:11.717243 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9508 13:57:11.720270 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9509 13:57:11.726523 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9510 13:57:11.730100 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9511 13:57:11.733469 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9512 13:57:11.739874 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9513 13:57:11.743373 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9514 13:57:11.746798 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9515 13:57:11.753665 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9516 13:57:11.756833 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9517 13:57:11.760178 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9518 13:57:11.766701 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9519 13:57:11.770268 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9520 13:57:11.776800 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9521 13:57:11.780473 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9522 13:57:11.783885 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9523 13:57:11.791102 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9524 13:57:11.793914 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9525 13:57:11.797795 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9526 13:57:11.803753 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9527 13:57:11.807106 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9528 13:57:11.813690 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9529 13:57:11.817322 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9530 13:57:11.820680 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9531 13:57:11.827206 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9532 13:57:11.830774 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9533 13:57:11.834035 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9534 13:57:11.841149 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9535 13:57:11.844654 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9536 13:57:11.850819 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9537 13:57:11.854143 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9538 13:57:11.857081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9539 13:57:11.864541 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9540 13:57:11.867830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9541 13:57:11.870727 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9542 13:57:11.873802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9543 13:57:11.877356 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9544 13:57:11.884014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9545 13:57:11.887095 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9546 13:57:11.890703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9547 13:57:11.893919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9548 13:57:11.901131 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9549 13:57:11.904599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9550 13:57:11.907765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9551 13:57:11.911007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9552 13:57:11.917775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9553 13:57:11.920900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9554 13:57:11.924211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9555 13:57:11.931241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9556 13:57:11.934102 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9557 13:57:11.940895 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9558 13:57:11.944426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9559 13:57:11.947516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9560 13:57:11.954787 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9561 13:57:11.958155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9562 13:57:11.965152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9563 13:57:11.968010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9564 13:57:11.974752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9565 13:57:11.977977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9566 13:57:11.981645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9567 13:57:11.987949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9568 13:57:11.991531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9569 13:57:11.998288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9570 13:57:12.001519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9571 13:57:12.008791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9572 13:57:12.011448 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9573 13:57:12.014736 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9574 13:57:12.022138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9575 13:57:12.024952 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9576 13:57:12.031408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9577 13:57:12.034950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9578 13:57:12.038827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9579 13:57:12.045012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9580 13:57:12.048142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9581 13:57:12.054930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9582 13:57:12.058065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9583 13:57:12.065328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9584 13:57:12.068357 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9585 13:57:12.074979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9586 13:57:12.078205 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9587 13:57:12.081780 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9588 13:57:12.089147 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9589 13:57:12.092764 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9590 13:57:12.099025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9591 13:57:12.101967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9592 13:57:12.105110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9593 13:57:12.112330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9594 13:57:12.115552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9595 13:57:12.122211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9596 13:57:12.126086 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9597 13:57:12.132290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9598 13:57:12.135850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9599 13:57:12.139447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9600 13:57:12.145692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9601 13:57:12.149040 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9602 13:57:12.152666 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9603 13:57:12.159270 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9604 13:57:12.162275 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9605 13:57:12.165907 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9606 13:57:12.169384 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9607 13:57:12.175524 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9608 13:57:12.179004 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9609 13:57:12.186300 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9610 13:57:12.189474 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9611 13:57:12.192836 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9612 13:57:12.199621 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9613 13:57:12.202879 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9614 13:57:12.209114 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9615 13:57:12.212806 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9616 13:57:12.215781 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9617 13:57:12.222979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9618 13:57:12.226703 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9619 13:57:12.233724 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9620 13:57:12.236372 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9621 13:57:12.239613 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9622 13:57:12.243549 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9623 13:57:12.249647 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9624 13:57:12.253353 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9625 13:57:12.256549 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9626 13:57:12.263141 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9627 13:57:12.266519 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9628 13:57:12.269923 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9629 13:57:12.273411 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9630 13:57:12.279827 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9631 13:57:12.283182 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9632 13:57:12.286740 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9633 13:57:12.293437 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9634 13:57:12.297888 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9635 13:57:12.303337 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9636 13:57:12.306698 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9637 13:57:12.310138 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9638 13:57:12.317081 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9639 13:57:12.320507 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9640 13:57:12.323890 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9641 13:57:12.330683 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9642 13:57:12.333885 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9643 13:57:12.337011 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9644 13:57:12.343672 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9645 13:57:12.347716 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9646 13:57:12.354212 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9647 13:57:12.357543 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9648 13:57:12.360505 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9649 13:57:12.367438 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9650 13:57:12.370705 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9651 13:57:12.374295 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9652 13:57:12.380841 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9653 13:57:12.384535 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9654 13:57:12.390920 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9655 13:57:12.394689 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9656 13:57:12.397918 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9657 13:57:12.404049 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9658 13:57:12.408242 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9659 13:57:12.411304 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9660 13:57:12.417682 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9661 13:57:12.421229 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9662 13:57:12.427731 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9663 13:57:12.431366 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9664 13:57:12.434647 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9665 13:57:12.441859 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9666 13:57:12.444886 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9667 13:57:12.448075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9668 13:57:12.454658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9669 13:57:12.458343 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9670 13:57:12.464794 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9671 13:57:12.467692 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9672 13:57:12.471678 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9673 13:57:12.478190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9674 13:57:12.481806 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9675 13:57:12.488230 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9676 13:57:12.491599 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9677 13:57:12.494718 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9678 13:57:12.501283 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9679 13:57:12.504648 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9680 13:57:12.508015 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9681 13:57:12.514800 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9682 13:57:12.517884 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9683 13:57:12.524594 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9684 13:57:12.527878 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9685 13:57:12.531736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9686 13:57:12.537996 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9687 13:57:12.541345 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9688 13:57:12.548068 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9689 13:57:12.551666 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9690 13:57:12.554394 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9691 13:57:12.561671 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9692 13:57:12.565313 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9693 13:57:12.568315 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9694 13:57:12.574696 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9695 13:57:12.577896 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9696 13:57:12.585094 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9697 13:57:12.587995 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9698 13:57:12.595189 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9699 13:57:12.597946 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9700 13:57:12.601723 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9701 13:57:12.608849 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9702 13:57:12.611209 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9703 13:57:12.618321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9704 13:57:12.621683 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9705 13:57:12.625069 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9706 13:57:12.631902 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9707 13:57:12.635266 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9708 13:57:12.641403 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9709 13:57:12.644774 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9710 13:57:12.648342 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9711 13:57:12.654930 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9712 13:57:12.657954 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9713 13:57:12.665089 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9714 13:57:12.668577 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9715 13:57:12.671823 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9716 13:57:12.678424 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9717 13:57:12.682169 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9718 13:57:12.688943 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9719 13:57:12.691671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9720 13:57:12.694977 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9721 13:57:12.702359 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9722 13:57:12.705582 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9723 13:57:12.711749 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9724 13:57:12.714878 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9725 13:57:12.721575 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9726 13:57:12.724976 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9727 13:57:12.728292 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9728 13:57:12.735469 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9729 13:57:12.739290 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9730 13:57:12.744855 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9731 13:57:12.748233 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9732 13:57:12.754748 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9733 13:57:12.757870 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9734 13:57:12.761412 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9735 13:57:12.768167 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9736 13:57:12.771572 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9737 13:57:12.774722 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9738 13:57:12.778091 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9739 13:57:12.781640 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9740 13:57:12.788015 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9741 13:57:12.791722 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9742 13:57:12.798200 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9743 13:57:12.801669 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9744 13:57:12.804688 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9745 13:57:12.811606 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9746 13:57:12.814804 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9747 13:57:12.817935 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9748 13:57:12.824636 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9749 13:57:12.828704 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9750 13:57:12.831287 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9751 13:57:12.838291 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9752 13:57:12.841987 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9753 13:57:12.848370 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9754 13:57:12.851566 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9755 13:57:12.854762 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9756 13:57:12.861691 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9757 13:57:12.865110 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9758 13:57:12.868439 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9759 13:57:12.874840 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9760 13:57:12.878306 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9761 13:57:12.881336 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9762 13:57:12.888264 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9763 13:57:12.891628 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9764 13:57:12.894764 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9765 13:57:12.901927 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9766 13:57:12.904720 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9767 13:57:12.911386 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9768 13:57:12.914855 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9769 13:57:12.918240 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9770 13:57:12.924951 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9771 13:57:12.928118 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9772 13:57:12.931445 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9773 13:57:12.938110 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9774 13:57:12.941935 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9775 13:57:12.944894 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9776 13:57:12.948412 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9777 13:57:12.954891 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9778 13:57:12.958244 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9779 13:57:12.961450 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9780 13:57:12.965108 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9781 13:57:12.968737 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9782 13:57:12.975063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9783 13:57:12.978537 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9784 13:57:12.981912 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9785 13:57:12.984951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9786 13:57:12.991871 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9787 13:57:12.995551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9788 13:57:12.998675 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9789 13:57:13.005219 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9790 13:57:13.008202 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9791 13:57:13.015361 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9792 13:57:13.018138 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9793 13:57:13.025284 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9794 13:57:13.029168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9795 13:57:13.031373 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9796 13:57:13.038117 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9797 13:57:13.041400 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9798 13:57:13.048268 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9799 13:57:13.051644 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9800 13:57:13.054719 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9801 13:57:13.061576 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9802 13:57:13.064561 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9803 13:57:13.071420 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9804 13:57:13.074891 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9805 13:57:13.078345 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9806 13:57:13.084649 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9807 13:57:13.088545 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9808 13:57:13.094534 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9809 13:57:13.098373 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9810 13:57:13.102070 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9811 13:57:13.108351 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9812 13:57:13.111627 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9813 13:57:13.118370 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9814 13:57:13.121732 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9815 13:57:13.125045 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9816 13:57:13.131329 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9817 13:57:13.134616 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9818 13:57:13.141374 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9819 13:57:13.145103 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9820 13:57:13.148195 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9821 13:57:13.155001 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9822 13:57:13.158097 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9823 13:57:13.164787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9824 13:57:13.168103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9825 13:57:13.172192 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9826 13:57:13.178236 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9827 13:57:13.181727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9828 13:57:13.188125 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9829 13:57:13.191666 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9830 13:57:13.194690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9831 13:57:13.201730 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9832 13:57:13.204693 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9833 13:57:13.211510 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9834 13:57:13.214967 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9835 13:57:13.218921 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9836 13:57:13.225020 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9837 13:57:13.228607 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9838 13:57:13.235223 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9839 13:57:13.238964 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9840 13:57:13.245440 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9841 13:57:13.248627 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9842 13:57:13.251763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9843 13:57:13.258341 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9844 13:57:13.261599 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9845 13:57:13.264756 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9846 13:57:13.271544 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9847 13:57:13.275030 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9848 13:57:13.282095 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9849 13:57:13.285096 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9850 13:57:13.291659 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9851 13:57:13.294904 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9852 13:57:13.298636 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9853 13:57:13.305218 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9854 13:57:13.308446 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9855 13:57:13.311634 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9856 13:57:13.318222 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9857 13:57:13.321581 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9858 13:57:13.327997 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9859 13:57:13.331892 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9860 13:57:13.335081 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9861 13:57:13.341761 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9862 13:57:13.345135 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9863 13:57:13.352036 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9864 13:57:13.355032 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9865 13:57:13.361572 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9866 13:57:13.365141 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9867 13:57:13.368648 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9868 13:57:13.375041 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9869 13:57:13.378593 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9870 13:57:13.385143 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9871 13:57:13.388380 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9872 13:57:13.395261 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9873 13:57:13.398491 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9874 13:57:13.401778 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9875 13:57:13.408746 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9876 13:57:13.412346 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9877 13:57:13.418618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9878 13:57:13.422034 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9879 13:57:13.428894 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9880 13:57:13.431899 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9881 13:57:13.435282 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9882 13:57:13.441784 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9883 13:57:13.445287 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9884 13:57:13.451710 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9885 13:57:13.455597 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9886 13:57:13.459209 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9887 13:57:13.465626 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9888 13:57:13.468825 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9889 13:57:13.476061 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9890 13:57:13.479328 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9891 13:57:13.485294 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9892 13:57:13.488873 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9893 13:57:13.491976 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9894 13:57:13.498726 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9895 13:57:13.502286 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9896 13:57:13.509004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9897 13:57:13.512787 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9898 13:57:13.518747 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9899 13:57:13.522160 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9900 13:57:13.525582 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9901 13:57:13.532095 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9902 13:57:13.535611 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9903 13:57:13.542533 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9904 13:57:13.545847 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9905 13:57:13.552256 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9906 13:57:13.555432 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9907 13:57:13.558668 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9908 13:57:13.565579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9909 13:57:13.568844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9910 13:57:13.575385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9911 13:57:13.579081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9912 13:57:13.585430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9913 13:57:13.588884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9914 13:57:13.595463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9915 13:57:13.599255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9916 13:57:13.602195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9917 13:57:13.609117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9918 13:57:13.612072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9919 13:57:13.618716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9920 13:57:13.621960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9921 13:57:13.628809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9922 13:57:13.631928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9923 13:57:13.638745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9924 13:57:13.642079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9925 13:57:13.649222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9926 13:57:13.652316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9927 13:57:13.658892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9928 13:57:13.662240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9929 13:57:13.669108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9930 13:57:13.672300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9931 13:57:13.678941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9932 13:57:13.682350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9933 13:57:13.689207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9934 13:57:13.692830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9935 13:57:13.699133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9936 13:57:13.702698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9937 13:57:13.709600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9938 13:57:13.712653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9939 13:57:13.719015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9940 13:57:13.722387 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9941 13:57:13.722505 INFO: [APUAPC] vio 0
9942 13:57:13.729912 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9943 13:57:13.733470 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9944 13:57:13.736567 INFO: [APUAPC] D0_APC_0: 0x400510
9945 13:57:13.740064 INFO: [APUAPC] D0_APC_1: 0x0
9946 13:57:13.743130 INFO: [APUAPC] D0_APC_2: 0x1540
9947 13:57:13.746602 INFO: [APUAPC] D0_APC_3: 0x0
9948 13:57:13.749590 INFO: [APUAPC] D1_APC_0: 0xffffffff
9949 13:57:13.753849 INFO: [APUAPC] D1_APC_1: 0xffffffff
9950 13:57:13.756601 INFO: [APUAPC] D1_APC_2: 0x3fffff
9951 13:57:13.759620 INFO: [APUAPC] D1_APC_3: 0x0
9952 13:57:13.763211 INFO: [APUAPC] D2_APC_0: 0xffffffff
9953 13:57:13.766393 INFO: [APUAPC] D2_APC_1: 0xffffffff
9954 13:57:13.769801 INFO: [APUAPC] D2_APC_2: 0x3fffff
9955 13:57:13.773291 INFO: [APUAPC] D2_APC_3: 0x0
9956 13:57:13.776558 INFO: [APUAPC] D3_APC_0: 0xffffffff
9957 13:57:13.780159 INFO: [APUAPC] D3_APC_1: 0xffffffff
9958 13:57:13.783443 INFO: [APUAPC] D3_APC_2: 0x3fffff
9959 13:57:13.783523 INFO: [APUAPC] D3_APC_3: 0x0
9960 13:57:13.786985 INFO: [APUAPC] D4_APC_0: 0xffffffff
9961 13:57:13.789694 INFO: [APUAPC] D4_APC_1: 0xffffffff
9962 13:57:13.793470 INFO: [APUAPC] D4_APC_2: 0x3fffff
9963 13:57:13.796870 INFO: [APUAPC] D4_APC_3: 0x0
9964 13:57:13.799830 INFO: [APUAPC] D5_APC_0: 0xffffffff
9965 13:57:13.803006 INFO: [APUAPC] D5_APC_1: 0xffffffff
9966 13:57:13.806566 INFO: [APUAPC] D5_APC_2: 0x3fffff
9967 13:57:13.810073 INFO: [APUAPC] D5_APC_3: 0x0
9968 13:57:13.813731 INFO: [APUAPC] D6_APC_0: 0xffffffff
9969 13:57:13.816910 INFO: [APUAPC] D6_APC_1: 0xffffffff
9970 13:57:13.820039 INFO: [APUAPC] D6_APC_2: 0x3fffff
9971 13:57:13.823507 INFO: [APUAPC] D6_APC_3: 0x0
9972 13:57:13.826642 INFO: [APUAPC] D7_APC_0: 0xffffffff
9973 13:57:13.829915 INFO: [APUAPC] D7_APC_1: 0xffffffff
9974 13:57:13.833455 INFO: [APUAPC] D7_APC_2: 0x3fffff
9975 13:57:13.836708 INFO: [APUAPC] D7_APC_3: 0x0
9976 13:57:13.839940 INFO: [APUAPC] D8_APC_0: 0xffffffff
9977 13:57:13.843711 INFO: [APUAPC] D8_APC_1: 0xffffffff
9978 13:57:13.847816 INFO: [APUAPC] D8_APC_2: 0x3fffff
9979 13:57:13.850107 INFO: [APUAPC] D8_APC_3: 0x0
9980 13:57:13.853289 INFO: [APUAPC] D9_APC_0: 0xffffffff
9981 13:57:13.857336 INFO: [APUAPC] D9_APC_1: 0xffffffff
9982 13:57:13.860009 INFO: [APUAPC] D9_APC_2: 0x3fffff
9983 13:57:13.863945 INFO: [APUAPC] D9_APC_3: 0x0
9984 13:57:13.866883 INFO: [APUAPC] D10_APC_0: 0xffffffff
9985 13:57:13.870197 INFO: [APUAPC] D10_APC_1: 0xffffffff
9986 13:57:13.873465 INFO: [APUAPC] D10_APC_2: 0x3fffff
9987 13:57:13.876496 INFO: [APUAPC] D10_APC_3: 0x0
9988 13:57:13.880538 INFO: [APUAPC] D11_APC_0: 0xffffffff
9989 13:57:13.883187 INFO: [APUAPC] D11_APC_1: 0xffffffff
9990 13:57:13.886895 INFO: [APUAPC] D11_APC_2: 0x3fffff
9991 13:57:13.889932 INFO: [APUAPC] D11_APC_3: 0x0
9992 13:57:13.893582 INFO: [APUAPC] D12_APC_0: 0xffffffff
9993 13:57:13.896855 INFO: [APUAPC] D12_APC_1: 0xffffffff
9994 13:57:13.900531 INFO: [APUAPC] D12_APC_2: 0x3fffff
9995 13:57:13.903348 INFO: [APUAPC] D12_APC_3: 0x0
9996 13:57:13.906813 INFO: [APUAPC] D13_APC_0: 0xffffffff
9997 13:57:13.910263 INFO: [APUAPC] D13_APC_1: 0xffffffff
9998 13:57:13.913550 INFO: [APUAPC] D13_APC_2: 0x3fffff
9999 13:57:13.916737 INFO: [APUAPC] D13_APC_3: 0x0
10000 13:57:13.920369 INFO: [APUAPC] D14_APC_0: 0xffffffff
10001 13:57:13.923639 INFO: [APUAPC] D14_APC_1: 0xffffffff
10002 13:57:13.927259 INFO: [APUAPC] D14_APC_2: 0x3fffff
10003 13:57:13.929871 INFO: [APUAPC] D14_APC_3: 0x0
10004 13:57:13.933670 INFO: [APUAPC] D15_APC_0: 0xffffffff
10005 13:57:13.936987 INFO: [APUAPC] D15_APC_1: 0xffffffff
10006 13:57:13.940179 INFO: [APUAPC] D15_APC_2: 0x3fffff
10007 13:57:13.943370 INFO: [APUAPC] D15_APC_3: 0x0
10008 13:57:13.946881 INFO: [APUAPC] APC_CON: 0x4
10009 13:57:13.950655 INFO: [NOCDAPC] D0_APC_0: 0x0
10010 13:57:13.950737 INFO: [NOCDAPC] D0_APC_1: 0x0
10011 13:57:13.953653 INFO: [NOCDAPC] D1_APC_0: 0x0
10012 13:57:13.956874 INFO: [NOCDAPC] D1_APC_1: 0xfff
10013 13:57:13.960166 INFO: [NOCDAPC] D2_APC_0: 0x0
10014 13:57:13.963937 INFO: [NOCDAPC] D2_APC_1: 0xfff
10015 13:57:13.966833 INFO: [NOCDAPC] D3_APC_0: 0x0
10016 13:57:13.969943 INFO: [NOCDAPC] D3_APC_1: 0xfff
10017 13:57:13.973661 INFO: [NOCDAPC] D4_APC_0: 0x0
10018 13:57:13.976826 INFO: [NOCDAPC] D4_APC_1: 0xfff
10019 13:57:13.980369 INFO: [NOCDAPC] D5_APC_0: 0x0
10020 13:57:13.980450 INFO: [NOCDAPC] D5_APC_1: 0xfff
10021 13:57:13.983574 INFO: [NOCDAPC] D6_APC_0: 0x0
10022 13:57:13.986897 INFO: [NOCDAPC] D6_APC_1: 0xfff
10023 13:57:13.990799 INFO: [NOCDAPC] D7_APC_0: 0x0
10024 13:57:13.993710 INFO: [NOCDAPC] D7_APC_1: 0xfff
10025 13:57:13.997324 INFO: [NOCDAPC] D8_APC_0: 0x0
10026 13:57:13.999953 INFO: [NOCDAPC] D8_APC_1: 0xfff
10027 13:57:14.003595 INFO: [NOCDAPC] D9_APC_0: 0x0
10028 13:57:14.006800 INFO: [NOCDAPC] D9_APC_1: 0xfff
10029 13:57:14.010208 INFO: [NOCDAPC] D10_APC_0: 0x0
10030 13:57:14.013522 INFO: [NOCDAPC] D10_APC_1: 0xfff
10031 13:57:14.013603 INFO: [NOCDAPC] D11_APC_0: 0x0
10032 13:57:14.016861 INFO: [NOCDAPC] D11_APC_1: 0xfff
10033 13:57:14.020391 INFO: [NOCDAPC] D12_APC_0: 0x0
10034 13:57:14.023732 INFO: [NOCDAPC] D12_APC_1: 0xfff
10035 13:57:14.027064 INFO: [NOCDAPC] D13_APC_0: 0x0
10036 13:57:14.030222 INFO: [NOCDAPC] D13_APC_1: 0xfff
10037 13:57:14.033531 INFO: [NOCDAPC] D14_APC_0: 0x0
10038 13:57:14.037071 INFO: [NOCDAPC] D14_APC_1: 0xfff
10039 13:57:14.040462 INFO: [NOCDAPC] D15_APC_0: 0x0
10040 13:57:14.043940 INFO: [NOCDAPC] D15_APC_1: 0xfff
10041 13:57:14.047593 INFO: [NOCDAPC] APC_CON: 0x4
10042 13:57:14.050388 INFO: [APUAPC] set_apusys_apc done
10043 13:57:14.053600 INFO: [DEVAPC] devapc_init done
10044 13:57:14.057226 INFO: GICv3 without legacy support detected.
10045 13:57:14.060149 INFO: ARM GICv3 driver initialized in EL3
10046 13:57:14.063195 INFO: Maximum SPI INTID supported: 639
10047 13:57:14.066756 INFO: BL31: Initializing runtime services
10048 13:57:14.073726 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10049 13:57:14.076881 INFO: SPM: enable CPC mode
10050 13:57:14.083713 INFO: mcdi ready for mcusys-off-idle and system suspend
10051 13:57:14.087000 INFO: BL31: Preparing for EL3 exit to normal world
10052 13:57:14.090605 INFO: Entry point address = 0x80000000
10053 13:57:14.093518 INFO: SPSR = 0x8
10054 13:57:14.097894
10055 13:57:14.097975
10056 13:57:14.098041
10057 13:57:14.101085 Starting depthcharge on Spherion...
10058 13:57:14.101166
10059 13:57:14.101230 Wipe memory regions:
10060 13:57:14.101289
10061 13:57:14.101927 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10062 13:57:14.102026 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10063 13:57:14.102103 Setting prompt string to ['asurada:']
10064 13:57:14.102209 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10065 13:57:14.104856 [0x00000040000000, 0x00000054600000)
10066 13:57:14.226631
10067 13:57:14.226747 [0x00000054660000, 0x00000080000000)
10068 13:57:14.487616
10069 13:57:14.487772 [0x000000821a7280, 0x000000ffe64000)
10070 13:57:15.232540
10071 13:57:15.232678 [0x00000100000000, 0x00000240000000)
10072 13:57:17.122555
10073 13:57:17.125732 Initializing XHCI USB controller at 0x11200000.
10074 13:57:18.165028
10075 13:57:18.168098 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10076 13:57:18.168188
10077 13:57:18.168251
10078 13:57:18.168310
10079 13:57:18.168588 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 13:57:18.268946 asurada: tftpboot 192.168.201.1 12682963/tftp-deploy-mx_x4u2x/kernel/image.itb 12682963/tftp-deploy-mx_x4u2x/kernel/cmdline
10082 13:57:18.269092 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 13:57:18.269201 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10084 13:57:18.273618 tftpboot 192.168.201.1 12682963/tftp-deploy-mx_x4u2x/kernel/image.ittp-deploy-mx_x4u2x/kernel/cmdline
10085 13:57:18.273733
10086 13:57:18.273826 Waiting for link
10087 13:57:18.434159
10088 13:57:18.434309 R8152: Initializing
10089 13:57:18.434413
10090 13:57:18.437570 Version 6 (ocp_data = 5c30)
10091 13:57:18.437653
10092 13:57:18.440904 R8152: Done initializing
10093 13:57:18.440986
10094 13:57:18.441069 Adding net device
10095 13:57:20.468878
10096 13:57:20.469029 done.
10097 13:57:20.469123
10098 13:57:20.469204 MAC: 00:24:32:30:78:52
10099 13:57:20.469282
10100 13:57:20.472796 Sending DHCP discover... done.
10101 13:57:20.472879
10102 13:57:20.475666 Waiting for reply... done.
10103 13:57:20.475748
10104 13:57:20.481680 Sending DHCP request... done.
10105 13:57:20.481773
10106 13:57:20.487389 Waiting for reply... done.
10107 13:57:20.487470
10108 13:57:20.487535 My ip is 192.168.201.14
10109 13:57:20.487595
10110 13:57:20.491177 The DHCP server ip is 192.168.201.1
10111 13:57:20.491259
10112 13:57:20.497678 TFTP server IP predefined by user: 192.168.201.1
10113 13:57:20.497760
10114 13:57:20.504160 Bootfile predefined by user: 12682963/tftp-deploy-mx_x4u2x/kernel/image.itb
10115 13:57:20.504241
10116 13:57:20.507991 Sending tftp read request... done.
10117 13:57:20.508072
10118 13:57:20.511448 Waiting for the transfer...
10119 13:57:20.511529
10120 13:57:21.041421 00000000 ################################################################
10121 13:57:21.041570
10122 13:57:21.583448 00080000 ################################################################
10123 13:57:21.583611
10124 13:57:22.188094 00100000 ################################################################
10125 13:57:22.188669
10126 13:57:22.884175 00180000 ################################################################
10127 13:57:22.884604
10128 13:57:23.583752 00200000 ################################################################
10129 13:57:23.584209
10130 13:57:24.288310 00280000 ################################################################
10131 13:57:24.288915
10132 13:57:24.984022 00300000 ################################################################
10133 13:57:24.984540
10134 13:57:25.658292 00380000 ################################################################
10135 13:57:25.658859
10136 13:57:26.320560 00400000 ################################################################
10137 13:57:26.321266
10138 13:57:26.999920 00480000 ################################################################
10139 13:57:27.000417
10140 13:57:27.611009 00500000 ################################################################
10141 13:57:27.611514
10142 13:57:28.303575 00580000 ################################################################
10143 13:57:28.304099
10144 13:57:28.995324 00600000 ################################################################
10145 13:57:28.995841
10146 13:57:29.603010 00680000 ################################################################
10147 13:57:29.603143
10148 13:57:30.151291 00700000 ################################################################
10149 13:57:30.151439
10150 13:57:30.673980 00780000 ################################################################
10151 13:57:30.674119
10152 13:57:31.226509 00800000 ################################################################
10153 13:57:31.226667
10154 13:57:31.806971 00880000 ################################################################
10155 13:57:31.807110
10156 13:57:32.450489 00900000 ################################################################
10157 13:57:32.451034
10158 13:57:33.092250 00980000 ################################################################
10159 13:57:33.092385
10160 13:57:33.652465 00a00000 ################################################################
10161 13:57:33.652603
10162 13:57:34.215247 00a80000 ################################################################
10163 13:57:34.215405
10164 13:57:34.757286 00b00000 ################################################################
10165 13:57:34.757445
10166 13:57:35.296601 00b80000 ################################################################
10167 13:57:35.296735
10168 13:57:35.823956 00c00000 ################################################################
10169 13:57:35.824087
10170 13:57:36.354806 00c80000 ################################################################
10171 13:57:36.354953
10172 13:57:36.900695 00d00000 ################################################################
10173 13:57:36.900831
10174 13:57:37.423071 00d80000 ################################################################
10175 13:57:37.423206
10176 13:57:37.949712 00e00000 ################################################################
10177 13:57:37.949847
10178 13:57:38.486657 00e80000 ################################################################
10179 13:57:38.486789
10180 13:57:39.021194 00f00000 ################################################################
10181 13:57:39.021331
10182 13:57:39.548957 00f80000 ################################################################
10183 13:57:39.549122
10184 13:57:40.069605 01000000 ################################################################
10185 13:57:40.069739
10186 13:57:40.590548 01080000 ################################################################
10187 13:57:40.590704
10188 13:57:41.107891 01100000 ################################################################
10189 13:57:41.108070
10190 13:57:41.627636 01180000 ################################################################
10191 13:57:41.627798
10192 13:57:42.152903 01200000 ################################################################
10193 13:57:42.153072
10194 13:57:42.673890 01280000 ################################################################
10195 13:57:42.674050
10196 13:57:43.197238 01300000 ################################################################
10197 13:57:43.197387
10198 13:57:43.714725 01380000 ################################################################
10199 13:57:43.714909
10200 13:57:44.241893 01400000 ################################################################
10201 13:57:44.242037
10202 13:57:44.775914 01480000 ################################################################
10203 13:57:44.776061
10204 13:57:45.301453 01500000 ################################################################
10205 13:57:45.301596
10206 13:57:45.824292 01580000 ################################################################
10207 13:57:45.824470
10208 13:57:46.358078 01600000 ################################################################
10209 13:57:46.358241
10210 13:57:46.881537 01680000 ################################################################
10211 13:57:46.881702
10212 13:57:47.409871 01700000 ################################################################
10213 13:57:47.410031
10214 13:57:47.931639 01780000 ################################################################
10215 13:57:47.931771
10216 13:57:48.452280 01800000 ################################################################
10217 13:57:48.452427
10218 13:57:48.994697 01880000 ################################################################
10219 13:57:48.994832
10220 13:57:49.522282 01900000 ################################################################
10221 13:57:49.522454
10222 13:57:50.050279 01980000 ################################################################
10223 13:57:50.050493
10224 13:57:50.585022 01a00000 ################################################################
10225 13:57:50.585168
10226 13:57:51.115510 01a80000 ################################################################
10227 13:57:51.115650
10228 13:57:51.646448 01b00000 ################################################################
10229 13:57:51.646593
10230 13:57:52.171040 01b80000 ################################################################
10231 13:57:52.171180
10232 13:57:52.689497 01c00000 ################################################################
10233 13:57:52.689651
10234 13:57:53.209240 01c80000 ################################################################
10235 13:57:53.209451
10236 13:57:53.737265 01d00000 ################################################################
10237 13:57:53.737434
10238 13:57:54.263756 01d80000 ################################################################
10239 13:57:54.263898
10240 13:57:54.802780 01e00000 ################################################################
10241 13:57:54.802944
10242 13:57:55.331529 01e80000 ################################################################
10243 13:57:55.331663
10244 13:57:55.852037 01f00000 ################################################################
10245 13:57:55.852179
10246 13:57:56.371475 01f80000 ################################################################
10247 13:57:56.371647
10248 13:57:56.894607 02000000 ################################################################
10249 13:57:56.894765
10250 13:57:57.428859 02080000 ################################################################
10251 13:57:57.429022
10252 13:57:57.962075 02100000 ################################################################
10253 13:57:57.962212
10254 13:57:58.488856 02180000 ################################################################
10255 13:57:58.489009
10256 13:57:59.008822 02200000 ################################################################
10257 13:57:59.008983
10258 13:57:59.530167 02280000 ################################################################
10259 13:57:59.530345
10260 13:58:00.064565 02300000 ################################################################
10261 13:58:00.064715
10262 13:58:00.594850 02380000 ################################################################
10263 13:58:00.594998
10264 13:58:01.122268 02400000 ################################################################
10265 13:58:01.122407
10266 13:58:01.677522 02480000 ################################################################
10267 13:58:01.677655
10268 13:58:02.246154 02500000 ################################################################
10269 13:58:02.246287
10270 13:58:02.801853 02580000 ################################################################
10271 13:58:02.801989
10272 13:58:03.362251 02600000 ################################################################
10273 13:58:03.362435
10274 13:58:03.924147 02680000 ################################################################
10275 13:58:03.924277
10276 13:58:04.483543 02700000 ################################################################
10277 13:58:04.483700
10278 13:58:05.031219 02780000 ################################################################
10279 13:58:05.031351
10280 13:58:05.592945 02800000 ################################################################
10281 13:58:05.593085
10282 13:58:06.140728 02880000 ################################################################
10283 13:58:06.140898
10284 13:58:06.686878 02900000 ################################################################
10285 13:58:06.687012
10286 13:58:07.228260 02980000 ################################################################
10287 13:58:07.228466
10288 13:58:07.763196 02a00000 ################################################################
10289 13:58:07.763330
10290 13:58:08.298793 02a80000 ################################################################
10291 13:58:08.298928
10292 13:58:08.827618 02b00000 ################################################################
10293 13:58:08.827783
10294 13:58:09.350980 02b80000 ################################################################
10295 13:58:09.351143
10296 13:58:09.871339 02c00000 ################################################################
10297 13:58:09.871506
10298 13:58:10.397793 02c80000 ################################################################
10299 13:58:10.397953
10300 13:58:10.914813 02d00000 ################################################################
10301 13:58:10.914957
10302 13:58:11.453497 02d80000 ################################################################
10303 13:58:11.453629
10304 13:58:11.974875 02e00000 ################################################################
10305 13:58:11.975011
10306 13:58:12.509756 02e80000 ################################################################
10307 13:58:12.509896
10308 13:58:13.052202 02f00000 ################################################################
10309 13:58:13.052340
10310 13:58:13.591503 02f80000 ################################################################
10311 13:58:13.591643
10312 13:58:14.121694 03000000 ################################################################
10313 13:58:14.121830
10314 13:58:14.653210 03080000 ################################################################
10315 13:58:14.653393
10316 13:58:15.171413 03100000 ################################################################
10317 13:58:15.171557
10318 13:58:15.694925 03180000 ################################################################
10319 13:58:15.695064
10320 13:58:16.225367 03200000 ################################################################
10321 13:58:16.225537
10322 13:58:16.771355 03280000 ################################################################
10323 13:58:16.771495
10324 13:58:17.303126 03300000 ################################################################
10325 13:58:17.303263
10326 13:58:17.833252 03380000 ################################################################
10327 13:58:17.833419
10328 13:58:18.363547 03400000 ################################################################
10329 13:58:18.363684
10330 13:58:18.898999 03480000 ################################################################
10331 13:58:18.899166
10332 13:58:19.438649 03500000 ################################################################
10333 13:58:19.438804
10334 13:58:19.996611 03580000 ################################################################
10335 13:58:19.996748
10336 13:58:20.552432 03600000 ################################################################
10337 13:58:20.552574
10338 13:58:21.104933 03680000 ################################################################
10339 13:58:21.105079
10340 13:58:21.655933 03700000 ################################################################
10341 13:58:21.656146
10342 13:58:22.212929 03780000 ################################################################
10343 13:58:22.213091
10344 13:58:22.763214 03800000 ################################################################
10345 13:58:22.763359
10346 13:58:23.322101 03880000 ################################################################
10347 13:58:23.322249
10348 13:58:23.889224 03900000 ################################################################
10349 13:58:23.889399
10350 13:58:24.454107 03980000 ################################################################
10351 13:58:24.454292
10352 13:58:25.032751 03a00000 ################################################################
10353 13:58:25.032907
10354 13:58:25.606964 03a80000 ################################################################
10355 13:58:25.607110
10356 13:58:26.166421 03b00000 ################################################################
10357 13:58:26.166572
10358 13:58:26.724334 03b80000 ################################################################
10359 13:58:26.724471
10360 13:58:27.291551 03c00000 ################################################################
10361 13:58:27.291708
10362 13:58:27.843918 03c80000 ################################################################
10363 13:58:27.844054
10364 13:58:28.404077 03d00000 ################################################################
10365 13:58:28.404216
10366 13:58:28.975210 03d80000 ################################################################
10367 13:58:28.975367
10368 13:58:29.552025 03e00000 ################################################################
10369 13:58:29.552181
10370 13:58:30.147046 03e80000 ################################################################
10371 13:58:30.147201
10372 13:58:30.740797 03f00000 ################################################################
10373 13:58:30.740946
10374 13:58:31.330770 03f80000 ################################################################
10375 13:58:31.330922
10376 13:58:31.937301 04000000 ################################################################
10377 13:58:31.937453
10378 13:58:32.505231 04080000 ################################################################
10379 13:58:32.505384
10380 13:58:32.927610 04100000 ############################################### done.
10381 13:58:32.927761
10382 13:58:32.930287 The bootfile was 68536326 bytes long.
10383 13:58:32.930402
10384 13:58:32.933669 Sending tftp read request... done.
10385 13:58:32.933754
10386 13:58:32.937173 Waiting for the transfer...
10387 13:58:32.937257
10388 13:58:32.940403 00000000 # done.
10389 13:58:32.940486
10390 13:58:32.947097 Command line loaded dynamically from TFTP file: 12682963/tftp-deploy-mx_x4u2x/kernel/cmdline
10391 13:58:32.947186
10392 13:58:32.960294 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10393 13:58:32.960400
10394 13:58:32.960464 Loading FIT.
10395 13:58:32.960524
10396 13:58:32.963645 Image ramdisk-1 has 56440155 bytes.
10397 13:58:32.963754
10398 13:58:32.967077 Image fdt-1 has 47278 bytes.
10399 13:58:32.967161
10400 13:58:32.970258 Image kernel-1 has 12046857 bytes.
10401 13:58:32.970339
10402 13:58:32.980351 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10403 13:58:32.980444
10404 13:58:32.997141 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10405 13:58:32.997271
10406 13:58:33.003488 Choosing best match conf-1 for compat google,spherion-rev2.
10407 13:58:33.003576
10408 13:58:33.011080 Connected to device vid:did:rid of 1ae0:0028:00
10409 13:58:33.019213
10410 13:58:33.022561 tpm_get_response: command 0x17b, return code 0x0
10411 13:58:33.022645
10412 13:58:33.029563 ec_init: CrosEC protocol v3 supported (256, 248)
10413 13:58:33.029651
10414 13:58:33.032972 tpm_cleanup: add release locality here.
10415 13:58:33.033053
10416 13:58:33.036492 Shutting down all USB controllers.
10417 13:58:33.036572
10418 13:58:33.039899 Removing current net device
10419 13:58:33.039979
10420 13:58:33.043012 Exiting depthcharge with code 4 at timestamp: 108382567
10421 13:58:33.043093
10422 13:58:33.049617 LZMA decompressing kernel-1 to 0x821a6718
10423 13:58:33.049699
10424 13:58:33.052885 LZMA decompressing kernel-1 to 0x40000000
10425 13:58:34.552594
10426 13:58:34.552725 jumping to kernel
10427 13:58:34.553244 end: 2.2.4 bootloader-commands (duration 00:01:20) [common]
10428 13:58:34.553338 start: 2.2.5 auto-login-action (timeout 00:03:05) [common]
10429 13:58:34.553410 Setting prompt string to ['Linux version [0-9]']
10430 13:58:34.553478 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10431 13:58:34.553544 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10432 13:58:34.634768
10433 13:58:34.637771 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10434 13:58:34.641513 start: 2.2.5.1 login-action (timeout 00:03:05) [common]
10435 13:58:34.641602 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10436 13:58:34.641672 Setting prompt string to []
10437 13:58:34.641753 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10438 13:58:34.641827 Using line separator: #'\n'#
10439 13:58:34.641885 No login prompt set.
10440 13:58:34.641946 Parsing kernel messages
10441 13:58:34.642000 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10442 13:58:34.642101 [login-action] Waiting for messages, (timeout 00:03:05)
10443 13:58:34.661039 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10444 13:58:34.664546 [ 0.000000] random: crng init done
10445 13:58:34.671144 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10446 13:58:34.673989 [ 0.000000] efi: UEFI not found.
10447 13:58:34.681075 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10448 13:58:34.691330 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10449 13:58:34.697316 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10450 13:58:34.707424 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10451 13:58:34.714141 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10452 13:58:34.720601 [ 0.000000] printk: bootconsole [mtk8250] enabled
10453 13:58:34.727476 [ 0.000000] NUMA: No NUMA configuration found
10454 13:58:34.733793 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10455 13:58:34.737311 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10456 13:58:34.740764 [ 0.000000] Zone ranges:
10457 13:58:34.747331 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10458 13:58:34.750875 [ 0.000000] DMA32 empty
10459 13:58:34.757162 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10460 13:58:34.760828 [ 0.000000] Movable zone start for each node
10461 13:58:34.763980 [ 0.000000] Early memory node ranges
10462 13:58:34.770807 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10463 13:58:34.777322 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10464 13:58:34.784403 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10465 13:58:34.787458 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10466 13:58:34.794300 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10467 13:58:34.800689 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10468 13:58:34.859496 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10469 13:58:34.865506 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10470 13:58:34.872573 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10471 13:58:34.875737 [ 0.000000] psci: probing for conduit method from DT.
10472 13:58:34.882548 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10473 13:58:34.885437 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10474 13:58:34.892551 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10475 13:58:34.895582 [ 0.000000] psci: SMC Calling Convention v1.2
10476 13:58:34.902382 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10477 13:58:34.905442 [ 0.000000] Detected VIPT I-cache on CPU0
10478 13:58:34.912171 [ 0.000000] CPU features: detected: GIC system register CPU interface
10479 13:58:34.919121 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10480 13:58:34.925291 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10481 13:58:34.932179 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10482 13:58:34.939035 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10483 13:58:34.945726 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10484 13:58:34.952485 [ 0.000000] alternatives: applying boot alternatives
10485 13:58:34.955253 [ 0.000000] Fallback order for Node 0: 0
10486 13:58:34.962217 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10487 13:58:34.965863 [ 0.000000] Policy zone: Normal
10488 13:58:34.982387 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10489 13:58:34.992155 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10490 13:58:35.002848 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10491 13:58:35.012538 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10492 13:58:35.019060 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10493 13:58:35.022324 <6>[ 0.000000] software IO TLB: area num 8.
10494 13:58:35.079463 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10495 13:58:35.228353 <6>[ 0.000000] Memory: 7912136K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 440632K reserved, 32768K cma-reserved)
10496 13:58:35.234831 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10497 13:58:35.242049 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10498 13:58:35.245091 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10499 13:58:35.251628 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10500 13:58:35.258580 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10501 13:58:35.262394 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10502 13:58:35.272119 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10503 13:58:35.279004 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10504 13:58:35.282049 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10505 13:58:35.289184 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10506 13:58:35.293321 <6>[ 0.000000] GICv3: 608 SPIs implemented
10507 13:58:35.299496 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10508 13:58:35.302527 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10509 13:58:35.306263 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10510 13:58:35.315983 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10511 13:58:35.326040 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10512 13:58:35.339373 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10513 13:58:35.346267 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10514 13:58:35.354974 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10515 13:58:35.368131 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10516 13:58:35.374761 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10517 13:58:35.381443 <6>[ 0.009234] Console: colour dummy device 80x25
10518 13:58:35.391714 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10519 13:58:35.394833 <6>[ 0.024405] pid_max: default: 32768 minimum: 301
10520 13:58:35.401264 <6>[ 0.029276] LSM: Security Framework initializing
10521 13:58:35.408088 <6>[ 0.034217] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10522 13:58:35.417782 <6>[ 0.042031] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10523 13:58:35.424704 <6>[ 0.051443] cblist_init_generic: Setting adjustable number of callback queues.
10524 13:58:35.431000 <6>[ 0.058933] cblist_init_generic: Setting shift to 3 and lim to 1.
10525 13:58:35.440971 <6>[ 0.065310] cblist_init_generic: Setting adjustable number of callback queues.
10526 13:58:35.447974 <6>[ 0.072737] cblist_init_generic: Setting shift to 3 and lim to 1.
10527 13:58:35.450795 <6>[ 0.079180] rcu: Hierarchical SRCU implementation.
10528 13:58:35.457613 <6>[ 0.084195] rcu: Max phase no-delay instances is 1000.
10529 13:58:35.464605 <6>[ 0.091220] EFI services will not be available.
10530 13:58:35.467831 <6>[ 0.096204] smp: Bringing up secondary CPUs ...
10531 13:58:35.476058 <6>[ 0.101252] Detected VIPT I-cache on CPU1
10532 13:58:35.482876 <6>[ 0.101320] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10533 13:58:35.488995 <6>[ 0.101352] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10534 13:58:35.492116 <6>[ 0.101690] Detected VIPT I-cache on CPU2
10535 13:58:35.498508 <6>[ 0.101741] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10536 13:58:35.505552 <6>[ 0.101758] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10537 13:58:35.512359 <6>[ 0.102018] Detected VIPT I-cache on CPU3
10538 13:58:35.519130 <6>[ 0.102064] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10539 13:58:35.525741 <6>[ 0.102078] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10540 13:58:35.528773 <6>[ 0.102385] CPU features: detected: Spectre-v4
10541 13:58:35.535489 <6>[ 0.102392] CPU features: detected: Spectre-BHB
10542 13:58:35.538691 <6>[ 0.102397] Detected PIPT I-cache on CPU4
10543 13:58:35.545729 <6>[ 0.102457] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10544 13:58:35.552368 <6>[ 0.102476] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10545 13:58:35.555285 <6>[ 0.102771] Detected PIPT I-cache on CPU5
10546 13:58:35.565306 <6>[ 0.102835] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10547 13:58:35.572107 <6>[ 0.102852] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10548 13:58:35.575536 <6>[ 0.103135] Detected PIPT I-cache on CPU6
10549 13:58:35.581918 <6>[ 0.103202] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10550 13:58:35.588608 <6>[ 0.103219] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10551 13:58:35.592240 <6>[ 0.103518] Detected PIPT I-cache on CPU7
10552 13:58:35.601794 <6>[ 0.103583] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10553 13:58:35.608778 <6>[ 0.103600] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10554 13:58:35.612261 <6>[ 0.103648] smp: Brought up 1 node, 8 CPUs
10555 13:58:35.615676 <6>[ 0.244987] SMP: Total of 8 processors activated.
10556 13:58:35.622377 <6>[ 0.249908] CPU features: detected: 32-bit EL0 Support
10557 13:58:35.632110 <6>[ 0.255304] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10558 13:58:35.638898 <6>[ 0.264104] CPU features: detected: Common not Private translations
10559 13:58:35.642356 <6>[ 0.270580] CPU features: detected: CRC32 instructions
10560 13:58:35.649051 <6>[ 0.275931] CPU features: detected: RCpc load-acquire (LDAPR)
10561 13:58:35.655683 <6>[ 0.281891] CPU features: detected: LSE atomic instructions
10562 13:58:35.658645 <6>[ 0.287672] CPU features: detected: Privileged Access Never
10563 13:58:35.665992 <6>[ 0.293452] CPU features: detected: RAS Extension Support
10564 13:58:35.672058 <6>[ 0.299060] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10565 13:58:35.678854 <6>[ 0.306325] CPU: All CPU(s) started at EL2
10566 13:58:35.682301 <6>[ 0.310642] alternatives: applying system-wide alternatives
10567 13:58:35.693368 <6>[ 0.321354] devtmpfs: initialized
10568 13:58:35.705705 <6>[ 0.330326] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10569 13:58:35.715383 <6>[ 0.340288] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10570 13:58:35.718770 <6>[ 0.348029] pinctrl core: initialized pinctrl subsystem
10571 13:58:35.726964 <6>[ 0.354819] DMI not present or invalid.
10572 13:58:35.733239 <6>[ 0.359234] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10573 13:58:35.740636 <6>[ 0.366105] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10574 13:58:35.749924 <6>[ 0.373689] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10575 13:58:35.756570 <6>[ 0.381919] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10576 13:58:35.763282 <6>[ 0.390162] audit: initializing netlink subsys (disabled)
10577 13:58:35.769695 <5>[ 0.395855] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10578 13:58:35.776350 <6>[ 0.396621] thermal_sys: Registered thermal governor 'step_wise'
10579 13:58:35.783318 <6>[ 0.403824] thermal_sys: Registered thermal governor 'power_allocator'
10580 13:58:35.786273 <6>[ 0.410078] cpuidle: using governor menu
10581 13:58:35.792791 <6>[ 0.421036] NET: Registered PF_QIPCRTR protocol family
10582 13:58:35.800065 <6>[ 0.426511] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10583 13:58:35.806668 <6>[ 0.433614] ASID allocator initialised with 32768 entries
10584 13:58:35.812995 <6>[ 0.440255] Serial: AMBA PL011 UART driver
10585 13:58:35.821231 <4>[ 0.449401] Trying to register duplicate clock ID: 134
10586 13:58:35.877788 <6>[ 0.509052] KASLR enabled
10587 13:58:35.891847 <6>[ 0.516747] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10588 13:58:35.898480 <6>[ 0.523762] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10589 13:58:35.905214 <6>[ 0.530252] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10590 13:58:35.912045 <6>[ 0.537257] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10591 13:58:35.918969 <6>[ 0.543743] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10592 13:58:35.925027 <6>[ 0.550746] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10593 13:58:35.931869 <6>[ 0.557233] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10594 13:58:35.939072 <6>[ 0.564236] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10595 13:58:35.941834 <6>[ 0.571705] ACPI: Interpreter disabled.
10596 13:58:35.950160 <6>[ 0.578183] iommu: Default domain type: Translated
10597 13:58:35.957118 <6>[ 0.583330] iommu: DMA domain TLB invalidation policy: strict mode
10598 13:58:35.960172 <5>[ 0.589992] SCSI subsystem initialized
10599 13:58:35.967105 <6>[ 0.594240] usbcore: registered new interface driver usbfs
10600 13:58:35.973632 <6>[ 0.599971] usbcore: registered new interface driver hub
10601 13:58:35.976990 <6>[ 0.605525] usbcore: registered new device driver usb
10602 13:58:35.983544 <6>[ 0.611684] pps_core: LinuxPPS API ver. 1 registered
10603 13:58:35.993355 <6>[ 0.616879] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10604 13:58:35.996989 <6>[ 0.626222] PTP clock support registered
10605 13:58:35.999951 <6>[ 0.630463] EDAC MC: Ver: 3.0.0
10606 13:58:36.007635 <6>[ 0.635694] FPGA manager framework
10607 13:58:36.011127 <6>[ 0.639369] Advanced Linux Sound Architecture Driver Initialized.
10608 13:58:36.014629 <6>[ 0.646133] vgaarb: loaded
10609 13:58:36.021335 <6>[ 0.649288] clocksource: Switched to clocksource arch_sys_counter
10610 13:58:36.028572 <5>[ 0.655734] VFS: Disk quotas dquot_6.6.0
10611 13:58:36.035073 <6>[ 0.659922] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10612 13:58:36.037863 <6>[ 0.667111] pnp: PnP ACPI: disabled
10613 13:58:36.046184 <6>[ 0.673856] NET: Registered PF_INET protocol family
10614 13:58:36.052516 <6>[ 0.679449] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10615 13:58:36.067065 <6>[ 0.691789] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10616 13:58:36.077711 <6>[ 0.700602] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10617 13:58:36.083555 <6>[ 0.708576] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10618 13:58:36.090232 <6>[ 0.717281] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10619 13:58:36.102231 <6>[ 0.727030] TCP: Hash tables configured (established 65536 bind 65536)
10620 13:58:36.109129 <6>[ 0.733896] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10621 13:58:36.115710 <6>[ 0.741097] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10622 13:58:36.122687 <6>[ 0.748806] NET: Registered PF_UNIX/PF_LOCAL protocol family
10623 13:58:36.129063 <6>[ 0.754946] RPC: Registered named UNIX socket transport module.
10624 13:58:36.132581 <6>[ 0.761099] RPC: Registered udp transport module.
10625 13:58:36.138836 <6>[ 0.766031] RPC: Registered tcp transport module.
10626 13:58:36.145697 <6>[ 0.770962] RPC: Registered tcp NFSv4.1 backchannel transport module.
10627 13:58:36.148683 <6>[ 0.777624] PCI: CLS 0 bytes, default 64
10628 13:58:36.152113 <6>[ 0.781961] Unpacking initramfs...
10629 13:58:36.176516 <6>[ 0.801409] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10630 13:58:36.186717 <6>[ 0.810078] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10631 13:58:36.190290 <6>[ 0.818962] kvm [1]: IPA Size Limit: 40 bits
10632 13:58:36.196503 <6>[ 0.823492] kvm [1]: GICv3: no GICV resource entry
10633 13:58:36.200100 <6>[ 0.828514] kvm [1]: disabling GICv2 emulation
10634 13:58:36.206376 <6>[ 0.833197] kvm [1]: GIC system register CPU interface enabled
10635 13:58:36.210075 <6>[ 0.839375] kvm [1]: vgic interrupt IRQ18
10636 13:58:36.216502 <6>[ 0.843729] kvm [1]: VHE mode initialized successfully
10637 13:58:36.223176 <5>[ 0.850276] Initialise system trusted keyrings
10638 13:58:36.230488 <6>[ 0.855081] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10639 13:58:36.236794 <6>[ 0.865101] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10640 13:58:36.243629 <5>[ 0.871495] NFS: Registering the id_resolver key type
10641 13:58:36.247311 <5>[ 0.876794] Key type id_resolver registered
10642 13:58:36.253608 <5>[ 0.881211] Key type id_legacy registered
10643 13:58:36.260559 <6>[ 0.885490] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10644 13:58:36.266640 <6>[ 0.892410] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10645 13:58:36.273302 <6>[ 0.900122] 9p: Installing v9fs 9p2000 file system support
10646 13:58:36.308674 <5>[ 0.936703] Key type asymmetric registered
10647 13:58:36.312001 <5>[ 0.941041] Asymmetric key parser 'x509' registered
10648 13:58:36.322050 <6>[ 0.946188] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10649 13:58:36.325369 <6>[ 0.953802] io scheduler mq-deadline registered
10650 13:58:36.328336 <6>[ 0.958581] io scheduler kyber registered
10651 13:58:36.348037 <6>[ 0.976068] EINJ: ACPI disabled.
10652 13:58:36.380226 <4>[ 1.001762] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 13:58:36.390050 <4>[ 1.012420] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10654 13:58:36.405331 <6>[ 1.033538] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10655 13:58:36.413795 <6>[ 1.041540] printk: console [ttyS0] disabled
10656 13:58:36.441445 <6>[ 1.066197] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10657 13:58:36.448054 <6>[ 1.075673] printk: console [ttyS0] enabled
10658 13:58:36.451242 <6>[ 1.075673] printk: console [ttyS0] enabled
10659 13:58:36.458121 <6>[ 1.084575] printk: bootconsole [mtk8250] disabled
10660 13:58:36.461646 <6>[ 1.084575] printk: bootconsole [mtk8250] disabled
10661 13:58:36.467828 <6>[ 1.095857] SuperH (H)SCI(F) driver initialized
10662 13:58:36.471650 <6>[ 1.101161] msm_serial: driver initialized
10663 13:58:36.485311 <6>[ 1.110278] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10664 13:58:36.495664 <6>[ 1.118824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10665 13:58:36.502083 <6>[ 1.127367] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10666 13:58:36.511830 <6>[ 1.135996] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10667 13:58:36.522284 <6>[ 1.144711] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10668 13:58:36.529214 <6>[ 1.153425] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10669 13:58:36.538775 <6>[ 1.161966] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10670 13:58:36.545823 <6>[ 1.170784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10671 13:58:36.555372 <6>[ 1.179329] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10672 13:58:36.567329 <6>[ 1.195250] loop: module loaded
10673 13:58:36.574382 <6>[ 1.201331] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10674 13:58:36.596969 <4>[ 1.224688] mtk-pmic-keys: Failed to locate of_node [id: -1]
10675 13:58:36.603530 <6>[ 1.231565] megasas: 07.719.03.00-rc1
10676 13:58:36.613292 <6>[ 1.241157] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10677 13:58:36.621115 <6>[ 1.248676] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10678 13:58:36.637443 <6>[ 1.265414] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10679 13:58:36.694077 <6>[ 1.315480] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10680 13:58:38.553041 <6>[ 3.180969] Freeing initrd memory: 55116K
10681 13:58:38.563128 <6>[ 3.191202] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10682 13:58:38.573913 <6>[ 3.202436] tun: Universal TUN/TAP device driver, 1.6
10683 13:58:38.577679 <6>[ 3.208529] thunder_xcv, ver 1.0
10684 13:58:38.580674 <6>[ 3.212038] thunder_bgx, ver 1.0
10685 13:58:38.583904 <6>[ 3.215534] nicpf, ver 1.0
10686 13:58:38.594901 <6>[ 3.219594] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10687 13:58:38.597899 <6>[ 3.227069] hns3: Copyright (c) 2017 Huawei Corporation.
10688 13:58:38.601630 <6>[ 3.232658] hclge is initializing
10689 13:58:38.608485 <6>[ 3.236239] e1000: Intel(R) PRO/1000 Network Driver
10690 13:58:38.614645 <6>[ 3.241368] e1000: Copyright (c) 1999-2006 Intel Corporation.
10691 13:58:38.618060 <6>[ 3.247382] e1000e: Intel(R) PRO/1000 Network Driver
10692 13:58:38.624452 <6>[ 3.252597] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10693 13:58:38.631397 <6>[ 3.258784] igb: Intel(R) Gigabit Ethernet Network Driver
10694 13:58:38.638100 <6>[ 3.264434] igb: Copyright (c) 2007-2014 Intel Corporation.
10695 13:58:38.644335 <6>[ 3.270273] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10696 13:58:38.650807 <6>[ 3.276791] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10697 13:58:38.654263 <6>[ 3.283258] sky2: driver version 1.30
10698 13:58:38.661265 <6>[ 3.288290] VFIO - User Level meta-driver version: 0.3
10699 13:58:38.668545 <6>[ 3.296598] usbcore: registered new interface driver usb-storage
10700 13:58:38.675013 <6>[ 3.303053] usbcore: registered new device driver onboard-usb-hub
10701 13:58:38.683942 <6>[ 3.312293] mt6397-rtc mt6359-rtc: registered as rtc0
10702 13:58:38.693773 <6>[ 3.317761] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:58:39 UTC (1706795919)
10703 13:58:38.697018 <6>[ 3.327339] i2c_dev: i2c /dev entries driver
10704 13:58:38.714206 <6>[ 3.339261] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10705 13:58:38.733770 <6>[ 3.362253] cpu cpu0: EM: created perf domain
10706 13:58:38.737018 <6>[ 3.367182] cpu cpu4: EM: created perf domain
10707 13:58:38.744918 <6>[ 3.372824] sdhci: Secure Digital Host Controller Interface driver
10708 13:58:38.751581 <6>[ 3.379257] sdhci: Copyright(c) Pierre Ossman
10709 13:58:38.758004 <6>[ 3.384218] Synopsys Designware Multimedia Card Interface Driver
10710 13:58:38.764277 <6>[ 3.390857] sdhci-pltfm: SDHCI platform and OF driver helper
10711 13:58:38.767675 <6>[ 3.390889] mmc0: CQHCI version 5.10
10712 13:58:38.774567 <6>[ 3.400785] ledtrig-cpu: registered to indicate activity on CPUs
10713 13:58:38.781217 <6>[ 3.407878] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10714 13:58:38.787559 <6>[ 3.414909] usbcore: registered new interface driver usbhid
10715 13:58:38.791295 <6>[ 3.420731] usbhid: USB HID core driver
10716 13:58:38.797844 <6>[ 3.424934] spi_master spi0: will run message pump with realtime priority
10717 13:58:38.840035 <6>[ 3.461982] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10718 13:58:38.858809 <6>[ 3.477044] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10719 13:58:38.865902 <6>[ 3.491958] cros-ec-spi spi0.0: Chrome EC device registered
10720 13:58:38.869252 <6>[ 3.498066] mmc0: Command Queue Engine enabled
10721 13:58:38.875853 <6>[ 3.502847] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10722 13:58:38.882299 <6>[ 3.510463] mmcblk0: mmc0:0001 DA4128 116 GiB
10723 13:58:38.894668 <6>[ 3.522672] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10724 13:58:38.904172 <6>[ 3.526957] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10725 13:58:38.911071 <6>[ 3.529672] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10726 13:58:38.914296 <6>[ 3.539224] NET: Registered PF_PACKET protocol family
10727 13:58:38.921069 <6>[ 3.543898] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10728 13:58:38.924444 <6>[ 3.548506] 9pnet: Installing 9P2000 support
10729 13:58:38.930567 <6>[ 3.554313] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10730 13:58:38.937607 <5>[ 3.558203] Key type dns_resolver registered
10731 13:58:38.941177 <6>[ 3.569648] registered taskstats version 1
10732 13:58:38.947526 <5>[ 3.574029] Loading compiled-in X.509 certificates
10733 13:58:38.975893 <4>[ 3.596919] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10734 13:58:38.985784 <4>[ 3.607798] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10735 13:58:38.992372 <3>[ 3.618345] debugfs: File 'uA_load' in directory '/' already present!
10736 13:58:38.998470 <3>[ 3.625063] debugfs: File 'min_uV' in directory '/' already present!
10737 13:58:39.005491 <3>[ 3.631737] debugfs: File 'max_uV' in directory '/' already present!
10738 13:58:39.012286 <3>[ 3.638364] debugfs: File 'constraint_flags' in directory '/' already present!
10739 13:58:39.023071 <3>[ 3.648016] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10740 13:58:39.031753 <6>[ 3.660250] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10741 13:58:39.038956 <6>[ 3.666953] xhci-mtk 11200000.usb: xHCI Host Controller
10742 13:58:39.045224 <6>[ 3.672442] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10743 13:58:39.055225 <6>[ 3.680269] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10744 13:58:39.061892 <6>[ 3.689691] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10745 13:58:39.068513 <6>[ 3.695749] xhci-mtk 11200000.usb: xHCI Host Controller
10746 13:58:39.075478 <6>[ 3.701222] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10747 13:58:39.081924 <6>[ 3.708866] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10748 13:58:39.088502 <6>[ 3.716463] hub 1-0:1.0: USB hub found
10749 13:58:39.092697 <6>[ 3.720474] hub 1-0:1.0: 1 port detected
10750 13:58:39.098517 <6>[ 3.724733] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10751 13:58:39.105353 <6>[ 3.733274] hub 2-0:1.0: USB hub found
10752 13:58:39.108387 <6>[ 3.737281] hub 2-0:1.0: 1 port detected
10753 13:58:39.116465 <6>[ 3.744904] mtk-msdc 11f70000.mmc: Got CD GPIO
10754 13:58:39.126649 <6>[ 3.751760] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10755 13:58:39.133627 <6>[ 3.759789] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10756 13:58:39.143812 <4>[ 3.767684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10757 13:58:39.153324 <6>[ 3.777206] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10758 13:58:39.160111 <6>[ 3.785289] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10759 13:58:39.166775 <6>[ 3.793413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10760 13:58:39.176770 <6>[ 3.801355] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10761 13:58:39.183746 <6>[ 3.809172] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10762 13:58:39.193347 <6>[ 3.816988] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10763 13:58:39.203197 <6>[ 3.827419] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10764 13:58:39.210292 <6>[ 3.835792] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10765 13:58:39.219702 <6>[ 3.844133] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10766 13:58:39.226226 <6>[ 3.852476] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10767 13:58:39.236041 <6>[ 3.860818] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10768 13:58:39.242831 <6>[ 3.869158] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10769 13:58:39.252435 <6>[ 3.877497] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10770 13:58:39.262271 <6>[ 3.885838] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10771 13:58:39.269705 <6>[ 3.894177] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10772 13:58:39.279838 <6>[ 3.902516] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10773 13:58:39.286339 <6>[ 3.910854] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10774 13:58:39.296291 <6>[ 3.919192] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10775 13:58:39.302575 <6>[ 3.927531] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10776 13:58:39.312644 <6>[ 3.935870] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10777 13:58:39.319313 <6>[ 3.944208] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10778 13:58:39.325989 <6>[ 3.953024] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10779 13:58:39.332521 <6>[ 3.960330] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10780 13:58:39.339608 <6>[ 3.967275] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10781 13:58:39.348967 <6>[ 3.974180] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10782 13:58:39.355915 <6>[ 3.981237] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10783 13:58:39.362523 <6>[ 3.988112] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10784 13:58:39.372370 <6>[ 3.997245] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10785 13:58:39.391922 <6>[ 4.006364] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10786 13:58:39.392496 <6>[ 4.015657] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10787 13:58:39.401870 <6>[ 4.025124] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10788 13:58:39.408770 <6>[ 4.034590] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10789 13:58:39.418652 <6>[ 4.043709] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10790 13:58:39.428511 <6>[ 4.053174] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10791 13:58:39.438281 <6>[ 4.062293] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10792 13:58:39.448765 <6>[ 4.071587] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10793 13:58:39.458540 <6>[ 4.081747] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10794 13:58:39.468623 <6>[ 4.093797] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10795 13:58:39.520786 <6>[ 4.145569] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10796 13:58:39.675240 <6>[ 4.303317] hub 1-1:1.0: USB hub found
10797 13:58:39.678976 <6>[ 4.307828] hub 1-1:1.0: 4 ports detected
10798 13:58:39.688873 <6>[ 4.316671] hub 1-1:1.0: USB hub found
10799 13:58:39.691955 <6>[ 4.321023] hub 1-1:1.0: 4 ports detected
10800 13:58:39.801191 <6>[ 4.425941] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10801 13:58:39.827610 <6>[ 4.455407] hub 2-1:1.0: USB hub found
10802 13:58:39.831227 <6>[ 4.459907] hub 2-1:1.0: 3 ports detected
10803 13:58:39.840364 <6>[ 4.468308] hub 2-1:1.0: USB hub found
10804 13:58:39.843698 <6>[ 4.472786] hub 2-1:1.0: 3 ports detected
10805 13:58:40.017016 <6>[ 4.641448] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10806 13:58:40.149952 <6>[ 4.777499] hub 1-1.4:1.0: USB hub found
10807 13:58:40.152520 <6>[ 4.782163] hub 1-1.4:1.0: 2 ports detected
10808 13:58:40.162516 <6>[ 4.790221] hub 1-1.4:1.0: USB hub found
10809 13:58:40.165361 <6>[ 4.794811] hub 1-1.4:1.0: 2 ports detected
10810 13:58:40.229051 <6>[ 4.853732] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10811 13:58:40.460833 <6>[ 5.085601] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10812 13:58:40.653427 <6>[ 5.277578] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10813 13:58:51.765313 <6>[ 16.398597] ALSA device list:
10814 13:58:51.772170 <6>[ 16.401880] No soundcards found.
10815 13:58:51.779901 <6>[ 16.409833] Freeing unused kernel memory: 8448K
10816 13:58:51.783044 <6>[ 16.414856] Run /init as init process
10817 13:58:51.832743 <6>[ 16.462822] NET: Registered PF_INET6 protocol family
10818 13:58:51.839609 <6>[ 16.469157] Segment Routing with IPv6
10819 13:58:51.842919 <6>[ 16.473109] In-situ OAM (IOAM) with IPv6
10820 13:58:51.877655 <30>[ 16.488122] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10821 13:58:51.881346 <30>[ 16.512089] systemd[1]: Detected architecture arm64.
10822 13:58:51.884479
10823 13:58:51.887852 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10824 13:58:51.887927
10825 13:58:51.903711 <30>[ 16.533721] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10826 13:58:52.088341 <30>[ 16.714490] systemd[1]: Queued start job for default target Graphical Interface.
10827 13:58:52.124148 <30>[ 16.754402] systemd[1]: Created slice system-getty.slice.
10828 13:58:52.131698 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10829 13:58:52.148677 <30>[ 16.778551] systemd[1]: Created slice system-modprobe.slice.
10830 13:58:52.155293 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10831 13:58:52.171964 <30>[ 16.802028] systemd[1]: Created slice system-serial\x2dgetty.slice.
10832 13:58:52.181797 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10833 13:58:52.196825 <30>[ 16.826661] systemd[1]: Created slice User and Session Slice.
10834 13:58:52.203051 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10835 13:58:52.223640 <30>[ 16.850295] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10836 13:58:52.233733 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10837 13:58:52.251547 <30>[ 16.878334] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10838 13:58:52.258006 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10839 13:58:52.282121 <30>[ 16.905654] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10840 13:58:52.288749 <30>[ 16.917787] systemd[1]: Reached target Local Encrypted Volumes.
10841 13:58:52.295532 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10842 13:58:52.311369 <30>[ 16.941675] systemd[1]: Reached target Paths.
10843 13:58:52.315020 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10844 13:58:52.331593 <30>[ 16.961565] systemd[1]: Reached target Remote File Systems.
10845 13:58:52.338305 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10846 13:58:52.351591 <30>[ 16.981555] systemd[1]: Reached target Slices.
10847 13:58:52.354735 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10848 13:58:52.371698 <30>[ 17.001586] systemd[1]: Reached target Swap.
10849 13:58:52.374962 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10850 13:58:52.395747 <30>[ 17.022471] systemd[1]: Listening on initctl Compatibility Named Pipe.
10851 13:58:52.402042 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10852 13:58:52.409100 <30>[ 17.037799] systemd[1]: Listening on Journal Audit Socket.
10853 13:58:52.415613 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10854 13:58:52.431862 <30>[ 17.062055] systemd[1]: Listening on Journal Socket (/dev/log).
10855 13:58:52.438349 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10856 13:58:52.456863 <30>[ 17.086844] systemd[1]: Listening on Journal Socket.
10857 13:58:52.463676 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10858 13:58:52.476017 <30>[ 17.106135] systemd[1]: Listening on udev Control Socket.
10859 13:58:52.482808 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10860 13:58:52.500784 <30>[ 17.130580] systemd[1]: Listening on udev Kernel Socket.
10861 13:58:52.506815 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10862 13:58:52.559672 <30>[ 17.189802] systemd[1]: Mounting Huge Pages File System...
10863 13:58:52.566024 Mounting [0;1;39mHuge Pages File System[0m...
10864 13:58:52.583496 <30>[ 17.213637] systemd[1]: Mounting POSIX Message Queue File System...
10865 13:58:52.590701 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10866 13:58:52.627401 <30>[ 17.257676] systemd[1]: Mounting Kernel Debug File System...
10867 13:58:52.634264 Mounting [0;1;39mKernel Debug File System[0m...
10868 13:58:52.654753 <30>[ 17.282057] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10869 13:58:52.668206 <30>[ 17.295054] systemd[1]: Starting Create list of static device nodes for the current kernel...
10870 13:58:52.674821 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10871 13:58:52.695558 <30>[ 17.325759] systemd[1]: Starting Load Kernel Module configfs...
10872 13:58:52.702590 Starting [0;1;39mLoad Kernel Module configfs[0m...
10873 13:58:52.736191 <30>[ 17.365905] systemd[1]: Starting Load Kernel Module drm...
10874 13:58:52.742219 Starting [0;1;39mLoad Kernel Module drm[0m...
10875 13:58:52.762808 <30>[ 17.389701] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10876 13:58:52.777051 <30>[ 17.407099] systemd[1]: Starting Journal Service...
10877 13:58:52.780762 Starting [0;1;39mJournal Service[0m...
10878 13:58:52.798526 <30>[ 17.428432] systemd[1]: Starting Load Kernel Modules...
10879 13:58:52.805289 Starting [0;1;39mLoad Kernel Modules[0m...
10880 13:58:52.830059 <30>[ 17.456722] systemd[1]: Starting Remount Root and Kernel File Systems...
10881 13:58:52.836649 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10882 13:58:52.880443 <30>[ 17.510515] systemd[1]: Starting Coldplug All udev Devices...
10883 13:58:52.887154 Starting [0;1;39mColdplug All udev Devices[0m...
10884 13:58:52.905029 <30>[ 17.534936] systemd[1]: Started Journal Service.
10885 13:58:52.911317 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10886 13:58:52.925831 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10887 13:58:52.944052 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10888 13:58:52.960306 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10889 13:58:52.980009 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10890 13:58:52.996852 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10891 13:58:53.016938 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10892 13:58:53.032778 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10893 13:58:53.054018 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10894 13:58:53.068138 See 'systemctl status systemd-remount-fs.service' for details.
10895 13:58:53.112542 Mounting [0;1;39mKernel Configuration File System[0m...
10896 13:58:53.136368 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10897 13:58:53.148822 <46>[ 17.775792] systemd-journald[174]: Received client request to flush runtime journal.
10898 13:58:53.161647 Starting [0;1;39mLoad/Save Random Seed[0m...
10899 13:58:53.181145 Starting [0;1;39mApply Kernel Variables[0m...
10900 13:58:53.205288 Starting [0;1;39mCreate System Users[0m...
10901 13:58:53.228795 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10902 13:58:53.248337 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10903 13:58:53.268404 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10904 13:58:53.285408 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10905 13:58:53.305302 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10906 13:58:53.324259 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10907 13:58:53.367828 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10908 13:58:53.390031 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10909 13:58:53.403806 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10910 13:58:53.420012 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10911 13:58:53.468204 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10912 13:58:53.495769 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10913 13:58:53.522382 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10914 13:58:53.532167 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10915 13:58:53.594354 Starting [0;1;39mNetwork Time Synchronization[0m...
10916 13:58:53.611934 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10917 13:58:53.661164 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10918 13:58:53.677120 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10919 13:58:53.715468 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10920 13:58:53.727674 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10921 13:58:53.737476 <6>[ 18.363401] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10922 13:58:53.744099 <6>[ 18.371307] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10923 13:58:53.753881 <6>[ 18.380355] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10924 13:58:53.760684 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10925 13:58:53.775190 <3>[ 18.401640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10926 13:58:53.781640 <6>[ 18.402601] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10927 13:58:53.791528 <3>[ 18.409897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 13:58:53.798147 <3>[ 18.425225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10929 13:58:53.804684 <4>[ 18.430016] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10930 13:58:53.812123 <6>[ 18.442520] remoteproc remoteproc0: scp is available
10931 13:58:53.818988 <6>[ 18.448168] remoteproc remoteproc0: powering up scp
10932 13:58:53.825857 <3>[ 18.451864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 13:58:53.832346 <4>[ 18.451909] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10934 13:58:53.842094 <6>[ 18.453323] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10935 13:58:53.849011 <3>[ 18.461414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 13:58:53.859023 <3>[ 18.461424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10937 13:58:53.865502 <6>[ 18.469929] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10938 13:58:53.868592 <6>[ 18.470419] mc: Linux media interface: v0.10
10939 13:58:53.875270 <6>[ 18.473389] usbcore: registered new device driver r8152-cfgselector
10940 13:58:53.882451 <3>[ 18.477449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10941 13:58:53.889244 <6>[ 18.514153] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10942 13:58:53.898805 <3>[ 18.518275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10943 13:58:53.905353 <6>[ 18.525157] pci_bus 0000:00: root bus resource [bus 00-ff]
10944 13:58:53.911607 <3>[ 18.534476] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10945 13:58:53.918554 <6>[ 18.539396] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10946 13:58:53.928653 <3>[ 18.548381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10947 13:58:53.935498 <6>[ 18.549333] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10948 13:58:53.945303 <6>[ 18.554745] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10949 13:58:53.956078 <6>[ 18.560409] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10950 13:58:53.963035 <3>[ 18.562680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10951 13:58:53.969257 <6>[ 18.563861] videodev: Linux video capture interface: v2.00
10952 13:58:53.976712 <6>[ 18.570251] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10953 13:58:53.982556 <6>[ 18.570295] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10954 13:58:53.986700 <6>[ 18.570400] pci 0000:00:00.0: supports D1 D2
10955 13:58:53.993196 <6>[ 18.570404] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10956 13:58:54.004012 <6>[ 18.572139] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10957 13:58:54.009776 <4>[ 18.575664] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10958 13:58:54.016831 <4>[ 18.575664] Fallback method does not support PEC.
10959 13:58:54.022988 <3>[ 18.580534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10960 13:58:54.030015 <6>[ 18.589908] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10961 13:58:54.039673 <6>[ 18.592263] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10962 13:58:54.046497 <6>[ 18.592276] remoteproc remoteproc0: remote processor scp is now up
10963 13:58:54.049828 <6>[ 18.592275] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10964 13:58:54.060432 <3>[ 18.592666] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 13:58:54.067422 <3>[ 18.598052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10966 13:58:54.074605 <6>[ 18.603559] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10967 13:58:54.087483 <6>[ 18.605877] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10968 13:58:54.094219 <6>[ 18.607371] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10969 13:58:54.104236 <3>[ 18.609836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10970 13:58:54.110580 <6>[ 18.617293] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10971 13:58:54.117283 <3>[ 18.621802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10972 13:58:54.127903 <6>[ 18.628687] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10973 13:58:54.134631 <6>[ 18.636767] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10974 13:58:54.141079 <3>[ 18.636938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10975 13:58:54.151281 <3>[ 18.639757] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 13:58:54.157713 <3>[ 18.640671] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10977 13:58:54.165037 <6>[ 18.650679] pci 0000:01:00.0: supports D1 D2
10978 13:58:54.171833 <3>[ 18.658643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 13:58:54.175183 <6>[ 18.660110] Bluetooth: Core ver 2.22
10980 13:58:54.181961 <6>[ 18.660194] NET: Registered PF_BLUETOOTH protocol family
10981 13:58:54.189240 <6>[ 18.660198] Bluetooth: HCI device and connection manager initialized
10982 13:58:54.192424 <6>[ 18.660225] Bluetooth: HCI socket layer initialized
10983 13:58:54.199588 <6>[ 18.660234] Bluetooth: L2CAP socket layer initialized
10984 13:58:54.203369 <6>[ 18.660251] Bluetooth: SCO socket layer initialized
10985 13:58:54.213957 <4>[ 18.660911] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10986 13:58:54.220759 <4>[ 18.660923] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10987 13:58:54.227035 <6>[ 18.661425] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10988 13:58:54.237384 <6>[ 18.663588] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10989 13:58:54.243879 <6>[ 18.664899] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10990 13:58:54.250389 <3>[ 18.673470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10991 13:58:54.260836 <6>[ 18.681514] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10992 13:58:54.264312 <6>[ 18.689392] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10993 13:58:54.277889 <6>[ 18.697879] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10994 13:58:54.287314 <6>[ 18.703929] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10995 13:58:54.290832 <6>[ 18.705377] r8152 2-1.3:1.0 eth0: v1.12.13
10996 13:58:54.298111 <6>[ 18.705451] usbcore: registered new interface driver r8152
10997 13:58:54.304903 <3>[ 18.705790] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10998 13:58:54.311350 <6>[ 18.712182] usbcore: registered new interface driver uvcvideo
10999 13:58:54.315231 <6>[ 18.712352] usbcore: registered new interface driver btusb
11000 13:58:54.325545 <4>[ 18.713113] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11001 13:58:54.332571 <3>[ 18.713123] Bluetooth: hci0: Failed to load firmware file (-2)
11002 13:58:54.339197 <3>[ 18.713126] Bluetooth: hci0: Failed to set up firmware (-2)
11003 13:58:54.349351 <4>[ 18.713130] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11004 13:58:54.356358 <6>[ 18.721409] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11005 13:58:54.363373 <6>[ 18.721423] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11006 13:58:54.370600 <6>[ 18.722679] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11007 13:58:54.377385 <6>[ 18.738982] usbcore: registered new interface driver cdc_ether
11008 13:58:54.384429 <6>[ 18.746004] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11009 13:58:54.391381 <6>[ 18.761835] usbcore: registered new interface driver r8153_ecm
11010 13:58:54.401571 <3>[ 18.767124] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 13:58:54.408979 <6>[ 18.769895] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11012 13:58:54.412579 <6>[ 18.769908] pci 0000:00:00.0: PCI bridge to [bus 01]
11013 13:58:54.418716 <6>[ 18.796076] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11014 13:58:54.428586 <6>[ 18.798914] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11015 13:58:54.435536 <6>[ 18.799073] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11016 13:58:54.442240 <3>[ 18.806208] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 13:58:54.451894 <3>[ 18.807059] power_supply sbs-5-000b: driver failed to report `energy_full' property: -6
11018 13:58:54.458404 <6>[ 18.811417] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11019 13:58:54.465132 <3>[ 18.836347] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 13:58:54.471483 <6>[ 18.839020] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11021 13:58:54.481781 <3>[ 18.851272] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 13:58:54.488434 <5>[ 18.874528] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11023 13:58:54.498519 <3>[ 18.900941] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 13:58:54.505342 <5>[ 18.913392] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11025 13:58:54.514846 Startin<5>[ 19.139953] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11026 13:58:54.525180 g [0;1;39mLoad/<4>[ 19.149736] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11027 13:58:54.528098 <6>[ 19.159619] cfg80211: failed to load regulatory.db
11028 13:58:54.534852 Save Screen …of leds:white:kbd_backlight[0m...
11029 13:58:54.558429 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11030 13:58:54.569911 <6>[ 19.196703] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11031 13:58:54.576424 <6>[ 19.204218] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11032 13:58:54.579333 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11033 13:58:54.600600 <6>[ 19.230910] mt7921e 0000:01:00.0: ASIC revision: 79610010
11034 13:58:54.701629 <6>[ 19.328856] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11035 13:58:54.704674 <6>[ 19.328856]
11036 13:58:54.735989 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11037 13:58:54.751462 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11038 13:58:54.774741 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11039 13:58:54.790735 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11040 13:58:54.803649 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11041 13:58:54.827678 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11042 13:58:54.839282 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11043 13:58:54.855333 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11044 13:58:54.879096 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11045 13:58:54.920215 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11046 13:58:54.957740 Starting [0;1;39mUser Login Management[0m...
11047 13:58:54.971459 <6>[ 19.598124] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11048 13:58:54.980312 Starting [0;1;39mPermit User Sessions[0m...
11049 13:58:55.001224 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11050 13:58:55.022978 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11051 13:58:55.043632 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11052 13:58:55.059708 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11053 13:58:55.083424 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11054 13:58:55.100771 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11055 13:58:55.121304 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11056 13:58:55.128956 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11057 13:58:55.147910 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11058 13:58:55.192513 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11059 13:58:55.222982 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11060 13:58:55.259229
11061 13:58:55.259314
11062 13:58:55.263093 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11063 13:58:55.263175
11064 13:58:55.266256 debian-bullseye-arm64 login: root (automatic login)
11065 13:58:55.266337
11066 13:58:55.266409
11067 13:58:55.283762 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
11068 13:58:55.283845
11069 13:58:55.290510 The programs included with the Debian GNU/Linux system are free software;
11070 13:58:55.297555 the exact distribution terms for each program are described in the
11071 13:58:55.300490 individual files in /usr/share/doc/*/copyright.
11072 13:58:55.300571
11073 13:58:55.307025 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11074 13:58:55.310162 permitted by applicable law.
11075 13:58:55.310685 Matched prompt #10: / #
11077 13:58:55.310893 Setting prompt string to ['/ #']
11078 13:58:55.310983 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11080 13:58:55.311170 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11081 13:58:55.311255 start: 2.2.6 expect-shell-connection (timeout 00:02:44) [common]
11082 13:58:55.311323 Setting prompt string to ['/ #']
11083 13:58:55.311382 Forcing a shell prompt, looking for ['/ #']
11085 13:58:55.361590 / #
11086 13:58:55.361688 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11087 13:58:55.361762 Waiting using forced prompt support (timeout 00:02:30)
11088 13:58:55.366986
11089 13:58:55.367254 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11090 13:58:55.367347 start: 2.2.7 export-device-env (timeout 00:02:44) [common]
11091 13:58:55.367439 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11092 13:58:55.367523 end: 2.2 depthcharge-retry (duration 00:02:16) [common]
11093 13:58:55.367605 end: 2 depthcharge-action (duration 00:02:16) [common]
11094 13:58:55.367689 start: 3 lava-test-retry (timeout 00:07:20) [common]
11095 13:58:55.367771 start: 3.1 lava-test-shell (timeout 00:07:20) [common]
11096 13:58:55.367842 Using namespace: common
11098 13:58:55.468187 / # #
11099 13:58:55.468307 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11100 13:58:55.473760 #
11101 13:58:55.474024 Using /lava-12682963
11103 13:58:55.574355 / # export SHELL=/bin/sh
11104 13:58:55.580290 export SHELL=/bin/sh
11106 13:58:55.680855 / # . /lava-12682963/environment
11107 13:58:55.686675 . /lava-12682963/environment
11109 13:58:55.787430 / # /lava-12682963/bin/lava-test-runner /lava-12682963/0
11110 13:58:55.787920 Test shell timeout: 10s (minimum of the action and connection timeout)
11111 13:58:55.793504 /lava-12682963/bin/lava-test-runner /lava-12682963/0
11112 13:58:55.820109 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.449228] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12682963_1.5.2.3.1>
11113 13:58:55.820804 Received signal: <STARTRUN> 0_igt-kms-mediatek 12682963_1.5.2.3.1
11114 13:58:55.821189 Starting test lava.0_igt-kms-mediatek (12682963_1.5.2.3.1)
11115 13:58:55.821596 Skipping test definition patterns.
11116 13:58:55.824082 diatek
11117 13:58:55.826933 + cd /lava-12682963/0/tests/0_igt-kms-mediatek
11118 13:58:55.827351 + cat uuid
11119 13:58:55.830069 + UUID=12682963_1.5.2.3.1
11120 13:58:55.830524 + set +x
11121 13:58:55.846437 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversi<6>[ 20.474168] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11122 13:58:55.850274 <8>[ 20.475429] <LAVA_SIGNAL_TESTSET START core_auth>
11123 13:58:55.850991 Received signal: <TESTSET> START core_auth
11124 13:58:55.851352 Starting test_set core_auth
11125 13:58:55.859679 on core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11126 13:58:55.878238 <14>[ 20.508390] [IGT] core_auth: executing
11127 13:58:55.885225 IGT-Version: 1.2<14>[ 20.513146] [IGT] core_auth: starting subtest getclient-simple
11128 13:58:55.894835 7.1-g621c2d3 (aa<14>[ 20.520809] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11129 13:58:55.898049 rch64) (Linux: 6<14>[ 20.529074] [IGT] core_auth: exiting, ret=0
11130 13:58:55.901561 .1.72-cip13 aarch64)
11131 13:58:55.905023 Starting subtest: getclient-simple
11132 13:58:55.911421 Opened<8>[ 20.540335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11133 13:58:55.912176 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11135 13:58:55.914642 device: /dev/dri/card0
11136 13:58:55.918077 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11137 13:58:55.944917 <14>[ 20.574965] [IGT] core_auth: executing
11138 13:58:55.951727 IGT-Version: 1.2<14>[ 20.579339] [IGT] core_auth: starting subtest getclient-master-drop
11139 13:58:55.961280 7.1-g621c2d3 (aa<14>[ 20.587595] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11140 13:58:55.967964 rch64) (Linux: 6<14>[ 20.596253] [IGT] core_auth: exiting, ret=0
11141 13:58:55.968376 .1.72-cip13 aarch64)
11142 13:58:55.971239 Starting subtest: getclient-master-drop
11143 13:58:55.981261 O<8>[ 20.607332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11144 13:58:55.981676 pened device: /dev/dri/card0
11145 13:58:55.982254 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11147 13:58:55.987862 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11148 13:58:56.007802 <14>[ 20.638145] [IGT] core_auth: executing
11149 13:58:56.014607 IGT-Version: 1.2<14>[ 20.642802] [IGT] core_auth: starting subtest basic-auth
11150 13:58:56.021389 7.1-g621c2d3 (aa<14>[ 20.649732] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11151 13:58:56.027972 rch64) (Linux: 6<14>[ 20.657506] [IGT] core_auth: exiting, ret=0
11152 13:58:56.031259 .1.72-cip13 aarch64)
11153 13:58:56.031668 Opened device: /dev/dri/card0
11154 13:58:56.041370 Starting su<8>[ 20.668538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11155 13:58:56.041784 btest: basic-auth
11156 13:58:56.042367 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11158 13:58:56.044836 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11159 13:58:56.069159 <14>[ 20.699167] [IGT] core_auth: executing
11160 13:58:56.075925 IGT-Version: 1.2<14>[ 20.703777] [IGT] core_auth: starting subtest many-magics
11161 13:58:56.079456 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11162 13:58:56.082738 Opened device: /dev/dri/card0
11163 13:58:56.086042 Starting subtest: many-magics
11164 13:58:56.092716 Reopening de<14>[ 20.721571] [IGT] core_auth: finished subtest many-magics, SUCCESS
11165 13:58:56.099122 vice failed afte<14>[ 20.728339] [IGT] core_auth: exiting, ret=0
11166 13:58:56.099701 r 1020 opens
11167 13:58:56.105835 [1mSubtest many-magics: SUCCESS (0.011s)[0m
11168 13:58:56.112321 <8>[ 20.741899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11169 13:58:56.113000 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11171 13:58:56.119796 <8>[ 20.750076] <LAVA_SIGNAL_TESTSET STOP>
11172 13:58:56.120460 Received signal: <TESTSET> STOP
11173 13:58:56.120829 Closing test_set core_auth
11174 13:58:56.165348 <14>[ 20.795745] [IGT] core_getclient: executing
11175 13:58:56.172168 IGT-Version: 1.2<14>[ 20.800612] [IGT] core_getclient: exiting, ret=0
11176 13:58:56.175478 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11177 13:58:56.185420 Opened dev<8>[ 20.811324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11178 13:58:56.185502 ice: /dev/dri/card0
11179 13:58:56.185737 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11181 13:58:56.188479 SUCCESS (0.006s)
11182 13:58:56.217839 <14>[ 20.848206] [IGT] core_getstats: executing
11183 13:58:56.224047 IGT-Version: 1.2<14>[ 20.852921] [IGT] core_getstats: exiting, ret=0
11184 13:58:56.228517 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11185 13:58:56.234825 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11187 13:58:56.237873 Opened dev<8>[ 20.863483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11188 13:58:56.237954 ice: /dev/dri/card0
11189 13:58:56.240677 SUCCESS (0.006s)
11190 13:58:56.270161 <14>[ 20.900390] [IGT] core_getversion: executing
11191 13:58:56.276845 IGT-Version: 1.2<14>[ 20.905331] [IGT] core_getversion: exiting, ret=0
11192 13:58:56.280038 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11193 13:58:56.289730 Opened dev<8>[ 20.916129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11194 13:58:56.289811 ice: /dev/dri/card0
11195 13:58:56.290048 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11197 13:58:56.293602 SUCCESS (0.006s)
11198 13:58:56.322443 <14>[ 20.953024] [IGT] core_setmaster_vs_auth: executing
11199 13:58:56.329445 IGT-Version: 1.2<14>[ 20.958713] [IGT] core_setmaster_vs_auth: exiting, ret=0
11200 13:58:56.335660 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11201 13:58:56.342193 Opened dev<8>[ 20.970035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11202 13:58:56.342435 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11204 13:58:56.346093 ice: /dev/dri/card0
11205 13:58:56.346173 SUCCESS (0.007s)
11206 13:58:56.364141 <8>[ 20.994529] <LAVA_SIGNAL_TESTSET START drm_read>
11207 13:58:56.364393 Received signal: <TESTSET> START drm_read
11208 13:58:56.364513 Starting test_set drm_read
11209 13:58:56.382407 <14>[ 21.012971] [IGT] drm_read: executing
11210 13:58:56.388833 IGT-Version: 1.2<14>[ 21.017511] [IGT] drm_read: exiting, ret=77
11211 13:58:56.392409 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11212 13:58:56.399206 Opened dev<8>[ 21.027526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11213 13:58:56.399456 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11215 13:58:56.402675 ice: /dev/dri/card0
11216 13:58:56.405632 No KMS driver or no outputs, pipes: 8, outputs: 0
11217 13:58:56.409147 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11218 13:58:56.417325 <14>[ 21.047826] [IGT] drm_read: executing
11219 13:58:56.424342 IGT-Version: 1.2<14>[ 21.052228] [IGT] drm_read: exiting, ret=77
11220 13:58:56.427167 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11221 13:58:56.434180 Opened dev<8>[ 21.062271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11222 13:58:56.434451 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11224 13:58:56.437182 ice: /dev/dri/card0
11225 13:58:56.440930 No KMS driver or no outputs, pipes: 8, outputs: 0
11226 13:58:56.444677 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11227 13:58:56.452463 <14>[ 21.082541] [IGT] drm_read: executing
11228 13:58:56.458642 IGT-Version: 1.2<14>[ 21.087002] [IGT] drm_read: exiting, ret=77
11229 13:58:56.462063 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11230 13:58:56.468493 Opened dev<8>[ 21.097225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11231 13:58:56.468743 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11233 13:58:56.471872 ice: /dev/dri/card0
11234 13:58:56.475085 No KMS driver or no outputs, pipes: 8, outputs: 0
11235 13:58:56.478418 [1mSubtest empty-block: SKIP (0.000s)[0m
11236 13:58:56.487235 <14>[ 21.118078] [IGT] drm_read: executing
11237 13:58:56.493934 IGT-Version: 1.2<14>[ 21.122568] [IGT] drm_read: exiting, ret=77
11238 13:58:56.497450 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11239 13:58:56.504196 Opened dev<8>[ 21.132663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11240 13:58:56.504448 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11242 13:58:56.507244 ice: /dev/dri/card0
11243 13:58:56.510915 No KMS driver or no outputs, pipes: 8, outputs: 0
11244 13:58:56.517282 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11245 13:58:56.520422 <14>[ 21.152976] [IGT] drm_read: executing
11246 13:58:56.527108 IGT-Version: 1.2<14>[ 21.157628] [IGT] drm_read: exiting, ret=77
11247 13:58:56.531032 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11248 13:58:56.540398 Opened dev<8>[ 21.167636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11249 13:58:56.540651 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11251 13:58:56.543980 ice: /dev/dri/card0
11252 13:58:56.547165 No KMS driver or no outputs, pipes: 8, outputs: 0
11253 13:58:56.550278 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11254 13:58:56.558546 <14>[ 21.188441] [IGT] drm_read: executing
11255 13:58:56.564616 IGT-Version: 1.2<14>[ 21.192898] [IGT] drm_read: exiting, ret=77
11256 13:58:56.567908 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11257 13:58:56.574563 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11259 13:58:56.577860 Opened dev<8>[ 21.202933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11260 13:58:56.577941 ice: /dev/dri/card0
11261 13:58:56.581039 No KMS driver or no outputs, pipes: 8, outputs: 0
11262 13:58:56.587549 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11263 13:58:56.590970 <14>[ 21.223863] [IGT] drm_read: executing
11264 13:58:56.598018 IGT-Version: 1.2<14>[ 21.228316] [IGT] drm_read: exiting, ret=77
11265 13:58:56.605151 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11266 13:58:56.611488 Opened dev<8>[ 21.238467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11267 13:58:56.611741 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11269 13:58:56.614658 ice: /dev/dri/card0
11270 13:58:56.617695 No KMS driv<8>[ 21.248519] <LAVA_SIGNAL_TESTSET STOP>
11271 13:58:56.617945 Received signal: <TESTSET> STOP
11272 13:58:56.618012 Closing test_set drm_read
11273 13:58:56.620921 er or no outputs, pipes: 8, outputs: 0
11274 13:58:56.627808 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11275 13:58:56.638114 <8>[ 21.268657] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11276 13:58:56.638392 Received signal: <TESTSET> START kms_addfb_basic
11277 13:58:56.638503 Starting test_set kms_addfb_basic
11278 13:58:56.657332 <14>[ 21.287413] [IGT] kms_addfb_basic: executing
11279 13:58:56.670491 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarc<14>[ 21.296443] [IGT] kms_addfb_basic: starting subtest unused-handle
11280 13:58:56.670592 h64)
11281 13:58:56.676805 Opened dev<14>[ 21.304361] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11282 13:58:56.680057 ice: /dev/dri/card0
11283 13:58:56.683234 Starting subtest: unused-handle
11284 13:58:56.690214 [1mSubtest unused-handle: SUCCESS (0.000s<14>[ 21.320919] [IGT] kms_addfb_basic: exiting, ret=0
11285 13:58:56.690296 )[0m
11286 13:58:56.703447 Test requirement not met in function igt_require_i915, file ../lib/drmtes<8>[ 21.332200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11287 13:58:56.703701 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11289 13:58:56.706536 t.c:720:
11290 13:58:56.709848 Test requirement: is_i915_device(fd)
11291 13:58:56.716717 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11292 13:58:56.723626 Test requirement: is_i915_dev<14>[ 21.353310] [IGT] kms_addfb_basic: executing
11293 13:58:56.723708 ice(fd)
11294 13:58:56.730260 No KMS driver or no outputs, pipes: 8, outputs: 0
11295 13:58:56.736559 IGT-<14>[ 21.363320] [IGT] kms_addfb_basic: starting subtest unused-pitches
11296 13:58:56.743517 Version: 1.27.1-<14>[ 21.371246] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11297 13:58:56.749799 g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11298 13:58:56.749879 Opened device: /dev/dri/card0
11299 13:58:56.757216 Starting subtes<14>[ 21.387965] [IGT] kms_addfb_basic: exiting, ret=0
11300 13:58:56.760002 t: unused-pitches
11301 13:58:56.763340 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11302 13:58:56.773302 Test requir<8>[ 21.399008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11303 13:58:56.773556 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11305 13:58:56.777373 ement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11306 13:58:56.779664 Test requirement: is_i915_device(fd)
11307 13:58:56.789831 Test requirement not met in function igt_require_i<14>[ 21.420058] [IGT] kms_addfb_basic: executing
11308 13:58:56.793116 915, file ../lib/drmtest.c:720:
11309 13:58:56.802980 Test requirement: is_i915_devic<14>[ 21.430446] [IGT] kms_addfb_basic: starting subtest unused-offsets
11310 13:58:56.803061 e(fd)
11311 13:58:56.810021 No KMS dr<14>[ 21.438267] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11312 13:58:56.816220 iver or no outputs, pipes: 8, outputs: 0
11313 13:58:56.826443 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-<14>[ 21.454996] [IGT] kms_addfb_basic: exiting, ret=0
11314 13:58:56.826525 cip13 aarch64)
11315 13:58:56.829787 Opened device: /dev/dri/card0
11316 13:58:56.832996 Starting subtest: unused-offsets
11317 13:58:56.839455 <8>[ 21.466162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11318 13:58:56.839534
11319 13:58:56.839770 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11321 13:58:56.843153 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11322 13:58:56.849215 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11323 13:58:56.856933 Test requirement: is_i915_<14>[ 21.487091] [IGT] kms_addfb_basic: executing
11324 13:58:56.859613 device(fd)
11325 13:58:56.869318 Test requirement not met in function igt_require_i91<14>[ 21.497639] [IGT] kms_addfb_basic: starting subtest unused-modifier
11326 13:58:56.879166 5, file ../lib/d<14>[ 21.505517] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11327 13:58:56.879248 rmtest.c:720:
11328 13:58:56.882508 Test requirement: is_i915_device(fd)
11329 13:58:56.892476 No KMS driver or no outputs, pipes: 8, outp<14>[ 21.522133] [IGT] kms_addfb_basic: exiting, ret=0
11330 13:58:56.892557 uts: 0
11331 13:58:56.905608 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-ci<8>[ 21.533102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11332 13:58:56.905689 p13 aarch64)
11333 13:58:56.905939 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11335 13:58:56.908825 Opened device: /dev/dri/card0
11336 13:58:56.912558 Starting subtest: unused-modifier
11337 13:58:56.915783 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11338 13:58:56.922915 Test requirem<14>[ 21.552934] [IGT] kms_addfb_basic: executing
11339 13:58:56.935813 ent not met in function igt_require_i915, file ../lib/drmtest.c:<14>[ 21.562064] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11340 13:58:56.935894 720:
11341 13:58:56.943002 Test requi<14>[ 21.570320] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11342 13:58:56.945995 rement: is_i915_device(fd)
11343 13:58:56.955728 Test requirement not met in function igt_require_i915, file ../lib/d<14>[ 21.587075] [IGT] kms_addfb_basic: exiting, ret=77
11344 13:58:56.959271 rmtest.c:720:
11345 13:58:56.962523 Test requirement: is_i915_device(fd)
11346 13:58:56.972548 No KMS driver or no outputs<8>[ 21.598395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11347 13:58:56.972630 , pipes: 8, outputs: 0
11348 13:58:56.972865 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11350 13:58:56.979050 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11351 13:58:56.982250 Opened device: /dev/dri/card0
11352 13:58:56.988746 Starting subtest: clobberred-modifi<14>[ 21.619772] [IGT] kms_addfb_basic: executing
11353 13:58:56.988828 er
11354 13:58:57.002095 Test requirement not met in function igt_require_i915, file <14>[ 21.630158] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11355 13:58:57.012273 ../lib/drmtest.c<14>[ 21.639107] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11356 13:58:57.012356 :720:
11357 13:58:57.015407 Test requirement: is_i915_device(fd)
11358 13:58:57.022287 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11359 13:58:57.026010 <14>[ 21.656537] [IGT] kms_addfb_basic: exiting, ret=77
11360 13:58:57.026091
11361 13:58:57.042243 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<8>[ 21.667789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11362 13:58:57.042327 0:
11363 13:58:57.042566 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11365 13:58:57.045541 Test requirement: is_i915_device(fd)
11366 13:58:57.052508 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11367 13:58:57.058687 Test requirement: is_i915_device(fd<14>[ 21.690128] [IGT] kms_addfb_basic: executing
11368 13:58:57.062614 )
11369 13:58:57.065224 No KMS driver or no outputs, pipes: 8, outputs: 0
11370 13:58:57.072327 IGT-Versio<14>[ 21.700378] [IGT] kms_addfb_basic: starting subtest legacy-format
11371 13:58:57.078518 n: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11372 13:58:57.085276 Opened device: /dev/<14>[ 21.714615] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11373 13:58:57.088747 dri/card0
11374 13:58:57.092038 Starting subtest: invalid-smem-bo-on-discrete
11375 13:58:57.099242 Test requirement not met in function i<14>[ 21.730166] [IGT] kms_addfb_basic: exiting, ret=0
11376 13:58:57.105513 gt_require_intel, file ../lib/drmtest.c:715:
11377 13:58:57.115272 Test requirement: is_intel_device(<8>[ 21.741314] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11378 13:58:57.115354 fd)
11379 13:58:57.115591 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11381 13:58:57.118608 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11382 13:58:57.129025 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11383 13:58:57.131821 Test require<14>[ 21.762602] [IGT] kms_addfb_basic: executing
11384 13:58:57.135004 ment: is_i915_device(fd)
11385 13:58:57.145260 Test requirement not met in function igt_require_i915,<14>[ 21.774947] [IGT] kms_addfb_basic: starting subtest no-handle
11386 13:58:57.155010 file ../lib/drm<14>[ 21.781588] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11387 13:58:57.155091 test.c:720:
11388 13:58:57.158431 Test requirement: is_i915_device(fd)
11389 13:58:57.165232 No KMS driver or no outputs, <14>[ 21.795686] [IGT] kms_addfb_basic: exiting, ret=0
11390 13:58:57.168377 pipes: 8, outputs: 0
11391 13:58:57.178316 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip1<8>[ 21.807491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11392 13:58:57.178576 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11394 13:58:57.182618 3 aarch64)
11395 13:58:57.185219 Opened device: /dev/dri/card0
11396 13:58:57.185300 Starting subtest: legacy-format
11397 13:58:57.191814 Successfully fuzzed 10000 {bpp, depth} variations
11398 13:58:57.198617 [1mSubtest legacy-format: SUCCES<14>[ 21.828021] [IGT] kms_addfb_basic: executing
11399 13:58:57.198698 S (0.006s)[0m
11400 13:58:57.212069 Test requirement not met in function igt_require_i915, file ../l<14>[ 21.840639] [IGT] kms_addfb_basic: starting subtest basic
11401 13:58:57.218129 ib/drmtest.c:720<14>[ 21.847054] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11402 13:58:57.218210 :
11403 13:58:57.221819 Test requirement: is_i915_device(fd)
11404 13:58:57.232038 Test requirement not met in function ig<14>[ 21.860623] [IGT] kms_addfb_basic: exiting, ret=0
11405 13:58:57.235191 t_require_i915, file ../lib/drmtest.c:720:
11406 13:58:57.245096 Test requirement: is_i915_device(fd)<8>[ 21.872717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11407 13:58:57.245177
11408 13:58:57.245412 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11410 13:58:57.248266 No KMS driver or no outputs, pipes: 8, outputs: 0
11411 13:58:57.254703 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11412 13:58:57.261251 Opened device: /dev/d<14>[ 21.892513] [IGT] kms_addfb_basic: executing
11413 13:58:57.261332 ri/card0
11414 13:58:57.264578 Starting subtest: no-handle
11415 13:58:57.274703 [1mSubtest no-handle: SUCCESS (0.000s)[<14>[ 21.903930] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11416 13:58:57.274784 0m
11417 13:58:57.284501 Test require<14>[ 21.910878] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11418 13:58:57.291120 ment not met in function igt_require_i915, file ../lib/drmtest.c:720:
11419 13:58:57.294548 Test requ<14>[ 21.925135] [IGT] kms_addfb_basic: exiting, ret=0
11420 13:58:57.298068 irement: is_i915_device(fd)
11421 13:58:57.308207 Test requirement not met in function igt_require_i9<8>[ 21.937092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11422 13:58:57.308465 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11424 13:58:57.311525 15, file ../lib/drmtest.c:720:
11425 13:58:57.314817 Test requirement: is_i915_device(fd)
11426 13:58:57.321140 No KMS driver or no outputs, pipes: 8, outputs: 0
11427 13:58:57.328063 IGT-Version: 1.27.1-g621c2d3 (aarch64) <14>[ 21.957779] [IGT] kms_addfb_basic: executing
11428 13:58:57.330796 (Linux: 6.1.72-cip13 aarch64)
11429 13:58:57.334121 Opened device: /dev/dri/card0
11430 13:58:57.341267 Starting subtest: <14>[ 21.970402] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11431 13:58:57.341348 basic
11432 13:58:57.351196 [1mSubte<14>[ 21.977297] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11433 13:58:57.354223 st basic: SUCCESS (0.000s)[0m
11434 13:58:57.361159 Test requirement not met in function igt_require<14>[ 21.991417] [IGT] kms_addfb_basic: exiting, ret=0
11435 13:58:57.364243 _i915, file ../lib/drmtest.c:720:
11436 13:58:57.368029 Test requirement: is_i915_device(fd)
11437 13:58:57.374379 Test re<8>[ 22.003295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11438 13:58:57.374643 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11440 13:58:57.380798 quirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11441 13:58:57.384256 Test requirement: is_i915_device(fd)
11442 13:58:57.394224 No KMS driver or no outputs, pipes: 8, outputs<14>[ 22.024613] [IGT] kms_addfb_basic: executing
11443 13:58:57.394306 : 0
11444 13:58:57.401467 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11445 13:58:57.407419 Opene<14>[ 22.036867] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11446 13:58:57.417425 d device: /dev/d<14>[ 22.043759] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11447 13:58:57.417507 ri/card0
11448 13:58:57.420950 Starting subtest: bad-pitch-0
11449 13:58:57.427454 [1mSubtest bad-pitch-0: SUCCESS (0.000<14>[ 22.058243] [IGT] kms_addfb_basic: exiting, ret=0
11450 13:58:57.431278 s)[0m
11451 13:58:57.440960 Test requirement not met in function igt_require_i915, file ../lib/drmte<8>[ 22.069894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11452 13:58:57.441215 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11454 13:58:57.444936 st.c:720:
11455 13:58:57.447428 Test requirement: is_i915_device(fd)
11456 13:58:57.454096 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11457 13:58:57.461032 Test requirement: is_i915_de<14>[ 22.090831] [IGT] kms_addfb_basic: executing
11458 13:58:57.461113 vice(fd)
11459 13:58:57.467972 No KMS driver or no outputs, pipes: 8, outputs: 0
11460 13:58:57.474152 IGT-Version: 1.27.1<14>[ 22.103352] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11461 13:58:57.484228 -g621c2d3 (aarch<14>[ 22.110408] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11462 13:58:57.487647 64) (Linux: 6.1.72-cip13 aarch64)
11463 13:58:57.487728 Opened device: /dev/dri/card0
11464 13:58:57.493961 Starting subte<14>[ 22.124762] [IGT] kms_addfb_basic: exiting, ret=0
11465 13:58:57.497255 st: bad-pitch-32
11466 13:58:57.500692 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11467 13:58:57.510843 Test requireme<8>[ 22.136673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11468 13:58:57.511097 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11470 13:58:57.514454 nt not met in function igt_require_i915, file ../lib/drmtest.c:720:
11471 13:58:57.517549 Test requirement: is_i915_device(fd)
11472 13:58:57.527497 Test requirement not met in function <14>[ 22.157220] [IGT] kms_addfb_basic: executing
11473 13:58:57.530725 igt_require_i915, file ../lib/drmtest.c:720:
11474 13:58:57.540602 Test requirement: is_i915_device(f<14>[ 22.168656] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11475 13:58:57.540685 d)
11476 13:58:57.547033 No KMS drive<14>[ 22.175712] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11477 13:58:57.550883 r or no outputs, pipes: 8, outputs: 0
11478 13:58:57.560575 IGT-Version: 1.27.1-g621c2d3 (aarch64) (L<14>[ 22.190231] [IGT] kms_addfb_basic: exiting, ret=0
11479 13:58:57.563754 inux: 6.1.72-cip13 aarch64)
11480 13:58:57.567208 Opened device: /dev/dri/card0
11481 13:58:57.574329 Starting subtest: ba<8>[ 22.202287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11482 13:58:57.574592 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11484 13:58:57.577161 d-pitch-63
11485 13:58:57.580416 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11486 13:58:57.587129 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11487 13:58:57.590705 Test requirement: is_i915_device(fd)
11488 13:58:57.596775 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11489 13:58:57.603863 Test req<14>[ 22.233830] [IGT] kms_addfb_basic: executing
11490 13:58:57.607034 uirement: is_i915_device(fd)
11491 13:58:57.610287 No KMS driver or no outputs, pipes: 8, outputs: 0
11492 13:58:57.616722 IGT-Version: 1.<14>[ 22.246056] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11493 13:58:57.627455 27.1-g621c2d3 (a<14>[ 22.253767] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11494 13:58:57.630351 arch64) (Linux: 6.1.72-cip13 aarch64)
11495 13:58:57.633491 Opened device: /dev/dri/card0
11496 13:58:57.640084 Starting s<14>[ 22.268895] [IGT] kms_addfb_basic: exiting, ret=0
11497 13:58:57.640165 ubtest: bad-pitch-128
11498 13:58:57.650125 [1mSubtest bad-pitch-128: SUCCESS (0.000<8>[ 22.279652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11499 13:58:57.650379 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11501 13:58:57.653457 s)[0m
11502 13:58:57.659892 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11503 13:58:57.663561 Test requirement: is_i915_device(fd)
11504 13:58:57.669811 Test requiremen<14>[ 22.299309] [IGT] kms_addfb_basic: executing
11505 13:58:57.673290 t not met in function igt_require_i915, file ../lib/drmtest.c:720:
11506 13:58:57.683355 Test require<14>[ 22.310953] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11507 13:58:57.689977 ment: is_i915_de<14>[ 22.317917] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11508 13:58:57.690058 vice(fd)
11509 13:58:57.696811 No KMS driver or no outputs, pipes: 8, outputs: 0
11510 13:58:57.703092 IGT-Version: 1.27.1<14>[ 22.332331] [IGT] kms_addfb_basic: exiting, ret=0
11511 13:58:57.706864 -g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11512 13:58:57.716462 Opened device: /dev/dri/card0<8>[ 22.344167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11513 13:58:57.716543
11514 13:58:57.716779 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11516 13:58:57.720095 Starting subtest: bad-pitch-256
11517 13:58:57.723223 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11518 13:58:57.736518 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<14>[ 22.365413] [IGT] kms_addfb_basic: executing
11519 13:58:57.736600 :720:
11520 13:58:57.739658 Test requirement: is_i915_device(fd)
11521 13:58:57.750090 Test requirement not met in functio<14>[ 22.377738] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11522 13:58:57.756352 n igt_require_i9<14>[ 22.384894] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11523 13:58:57.759976 15, file ../lib/drmtest.c:720:
11524 13:58:57.763245 Test requirement: is_i915_device(fd)
11525 13:58:57.769652 No KMS dri<14>[ 22.399322] [IGT] kms_addfb_basic: exiting, ret=0
11526 13:58:57.772875 ver or no outputs, pipes: 8, outputs: 0
11527 13:58:57.783089 IGT-Version: 1.27.1-g621c2d3 (aarch64) <8>[ 22.411302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11528 13:58:57.783343 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11530 13:58:57.786386 (Linux: 6.1.72-cip13 aarch64)
11531 13:58:57.790003 Opened device: /dev/dri/card0
11532 13:58:57.793093 Starting subtest: bad-pitch-1024
11533 13:58:57.802862 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m<14>[ 22.432165] [IGT] kms_addfb_basic: executing
11534 13:58:57.802943
11535 13:58:57.809947 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11536 13:58:57.819619 Test requirement: is_i915_d<14>[ 22.445692] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11537 13:58:57.819701 evice(fd)
11538 13:58:57.826302 Test <14>[ 22.454150] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11539 13:58:57.835811 requirement not met in function igt_require_i915<14>[ 22.467160] [IGT] kms_addfb_basic: exiting, ret=0
11540 13:58:57.839157 , file ../lib/drmtest.c:720:
11541 13:58:57.849058 Test requirement: is_i915_device(f<8>[ 22.478016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11542 13:58:57.849140 d)
11543 13:58:57.849377 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11545 13:58:57.855797 No KMS driver or no outputs, pipes: 8, outputs: 0
11546 13:58:57.859450 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11547 13:58:57.862610 Opened device: /dev/dri/card0
11548 13:58:57.869354 Star<14>[ 22.498576] [IGT] kms_addfb_basic: executing
11549 13:58:57.872372 ting subtest: bad-pitch-999
11550 13:58:57.875858 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11551 13:58:57.886036 Test requirement not met in functi<14>[ 22.512702] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11552 13:58:57.892601 on igt_require_i<14>[ 22.520906] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11553 13:58:57.895903 915, file ../lib/drmtest.c:720:
11554 13:58:57.902681 Test requiremen<14>[ 22.533770] [IGT] kms_addfb_basic: exiting, ret=0
11555 13:58:57.905977 t: is_i915_device(fd)
11556 13:58:57.915809 Test requirement not met in function igt_require_i915, fi<8>[ 22.544648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11557 13:58:57.916063 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11559 13:58:57.919300 le ../lib/drmtest.c:720:
11560 13:58:57.922662 Test requirement: is_i915_device(fd)
11561 13:58:57.929340 No KMS driver or no outputs, pipes: 8, outputs: 0
11562 13:58:57.935991 IGT-Version: 1.27.1-g621c2d3 <14>[ 22.565463] [IGT] kms_addfb_basic: executing
11563 13:58:57.939141 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11564 13:58:57.942431 Opened device: /dev/dri/card0
11565 13:58:57.945627 Starting subtest: bad-pitch-65536
11566 13:58:57.952317 [1mS<14>[ 22.578965] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11567 13:58:57.962208 ubtest bad-pitch<14>[ 22.587499] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11568 13:58:57.962289 -65536: SUCCESS (0.000s)[0m
11569 13:58:57.969107 Test requirement n<14>[ 22.600653] [IGT] kms_addfb_basic: exiting, ret=0
11570 13:58:57.975808 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11571 13:58:57.985358 Test requiremen<8>[ 22.611595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11572 13:58:57.985438 t: is_i915_device(fd)
11573 13:58:57.985673 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11575 13:58:57.995864 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11576 13:58:57.998914 Test requirement: is_i915_device(fd)
11577 13:58:58.002282 No KMS driver or<14>[ 22.632971] [IGT] kms_addfb_basic: executing
11578 13:58:58.005620 no outputs, pipes: 8, outputs: 0
11579 13:58:58.012161 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11580 13:58:58.019144 Opened <14>[ 22.647661] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11581 13:58:58.029345 device: /dev/dri<14>[ 22.655648] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11582 13:58:58.029428 /card0
11583 13:58:58.032309 Starting subtest: invalid-get-prop-any
11584 13:58:58.038739 <14>[ 22.668419] [IGT] kms_addfb_basic: exiting, ret=0
11585 13:58:58.042056 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11586 13:58:58.051839 Test requirement not met<8>[ 22.679502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11587 13:58:58.052093 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11589 13:58:58.058900 in function igt_require_i915, file ../lib/drmtest.c:720:
11590 13:58:58.061823 Test requirement: is_i915_device(fd)
11591 13:58:58.071802 Test requirement not met in function igt_require_i915, file ../<14>[ 22.700675] [IGT] kms_addfb_basic: executing
11592 13:58:58.071882 lib/drmtest.c:720:
11593 13:58:58.075018 Test requirement: is_i915_device(fd)
11594 13:58:58.081640 No KMS driver or no outputs, pipes: 8, outputs: 0
11595 13:58:58.088364 IGT-Version: 1.27.1<14>[ 22.717157] [IGT] kms_addfb_basic: starting subtest master-rmfb
11596 13:58:58.095232 -g621c2d3 (aarch<14>[ 22.724251] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11597 13:58:58.105137 64) (Linux: 6.1.72-cip13 aarch64<14>[ 22.734775] [IGT] kms_addfb_basic: exiting, ret=0
11598 13:58:58.105219 )
11599 13:58:58.108240 Opened device: /dev/dri/card0
11600 13:58:58.118921 Starting subtest: invalid-get-<8>[ 22.744829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11601 13:58:58.119001 prop
11602 13:58:58.119256 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11604 13:58:58.122344 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11605 13:58:58.128781 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11606 13:58:58.135102 Tes<14>[ 22.765071] [IGT] kms_addfb_basic: executing
11607 13:58:58.138281 t requirement: is_i915_device(fd)
11608 13:58:58.145198 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11609 13:58:58.154977 Test requirement: is_i915_<14>[ 22.782442] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11610 13:58:58.155058 device(fd)
11611 13:58:58.164812 No K<14>[ 22.790137] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11612 13:58:58.171722 MS driver or no <14>[ 22.799944] [IGT] kms_addfb_basic: exiting, ret=0
11613 13:58:58.171803 outputs, pipes: 8, outputs: 0
11614 13:58:58.185230 IGT-Version: 1.27.1-g621c2d3 (aar<8>[ 22.810606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11615 13:58:58.185484 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11617 13:58:58.188158 ch64) (Linux: 6.1.72-cip13 aarch64)
11618 13:58:58.188238 Opened device: /dev/dri/card0
11619 13:58:58.195175 Starting subtest: invalid-set-prop-any
11620 13:58:58.201757 [1mSubtest invalid-set-prop-any: SU<14>[ 22.831561] [IGT] kms_addfb_basic: executing
11621 13:58:58.201836 CCESS (0.000s)[0m
11622 13:58:58.211403 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11623 13:58:58.215481 Test requirement: is_i915_device(fd)
11624 13:58:58.221644 Tes<14>[ 22.849240] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11625 13:58:58.234628 t requirement not met in function igt_require_i915, file ../lib/<14>[ 22.861948] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11626 13:58:58.234710 drmtest.c:720:
11627 13:58:58.241296 <14>[ 22.870004] [IGT] kms_addfb_basic: exiting, ret=98
11628 13:58:58.245587 Test requirement: is_i915_device(fd)
11629 13:58:58.254561 No KMS driver or no outputs, pipes: 8, out<8>[ 22.882109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11630 13:58:58.254643 puts: 0
11631 13:58:58.254879 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11633 13:58:58.261349 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11634 13:58:58.264360 Opened device: /dev/dri/card0
11635 13:58:58.268039 Starting subtest: invalid-set-prop
11636 13:58:58.274598 [1mSubtest in<14>[ 22.903542] [IGT] kms_addfb_basic: executing
11637 13:58:58.277645 valid-set-prop: SUCCESS (0.000s)[0m
11638 13:58:58.284461 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11639 13:58:58.287810 Test requirement: is_i915_device(fd)
11640 13:58:58.294235 T<14>[ 22.922214] [IGT] kms_addfb_basic: exiting, ret=77
11641 13:58:58.307373 est requirement not met in function igt_require_i915, file ../li<8>[ 22.933036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11642 13:58:58.307454 b/drmtest.c:720:
11643 13:58:58.307691 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11645 13:58:58.310810 Test requirement: is_i915_device(fd)
11646 13:58:58.318055 No KMS driver or no outputs, pipes: 8, outputs: 0
11647 13:58:58.323949 IGT-Version: 1.27.1-g621c2d3 (aarch64<14>[ 22.954653] [IGT] kms_addfb_basic: executing
11648 13:58:58.327317 ) (Linux: 6.1.72-cip13 aarch64)
11649 13:58:58.330590 Opened device: /dev/dri/card0
11650 13:58:58.334557 Starting subtest: master-rmfb
11651 13:58:58.337631 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11652 13:58:58.344384 Test requirement n<14>[ 22.972780] [IGT] kms_addfb_basic: exiting, ret=77
11653 13:58:58.351159 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11654 13:58:58.357308 <8>[ 22.983765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11655 13:58:58.357393
11656 13:58:58.357629 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11658 13:58:58.360913 Test requirement: is_i915_device(fd)
11659 13:58:58.367317 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11660 13:58:58.374150 Test requirement: is_i<14>[ 23.004302] [IGT] kms_addfb_basic: executing
11661 13:58:58.374231 915_device(fd)
11662 13:58:58.380692 No KMS driver or no outputs, pipes: 8, outputs: 0
11663 13:58:58.387702 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11664 13:58:58.390650 Opened <14>[ 23.022319] [IGT] kms_addfb_basic: exiting, ret=77
11665 13:58:58.394371 device: /dev/dri/card0
11666 13:58:58.407384 Starting subtest: addfb25-modifier-no-fl<8>[ 23.032149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11667 13:58:58.407466 ag
11668 13:58:58.407699 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11670 13:58:58.410592 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11671 13:58:58.424205 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<14>[ 23.053750] [IGT] kms_addfb_basic: executing
11672 13:58:58.424286 :
11673 13:58:58.427541 Test requirement: is_i915_device(fd)
11674 13:58:58.433738 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11675 13:58:58.443894 Test requirement: is_i915_device(fd)<14>[ 23.071704] [IGT] kms_addfb_basic: exiting, ret=77
11676 13:58:58.443975
11677 13:58:58.447325 No KMS driver or no outputs, pipes: 8, outputs: 0
11678 13:58:58.454341 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11680 13:58:58.457270 IGT-Version<8>[ 23.082703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11681 13:58:58.460685 : 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11682 13:58:58.464517 Opened device: /dev/dri/card0
11683 13:58:58.467467 Starting subtest: addfb25-bad-modifier
11684 13:58:58.474044 (kms_addfb_bas<14>[ 23.103121] [IGT] kms_addfb_basic: executing
11685 13:58:58.480240 ic:433) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11686 13:58:58.500277 (kms_addfb_basic:433) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11687 13:58:58.504192 (kms_addfb_basic:433) CRITICAL: error: 0 != -1
11688 13:58:58.504271 Stack trace:
11689 13:58:58.510305 #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11690 13:58:58.510386 #1 [<unknown>+0xcdca47e0]
11691 13:58:58.513948 #2 [<unknown>+0xcdca6278]
11692 13:58:58.516687 #3 [<unknown>+0xcdca167c]
11693 13:58:58.520019 #4 [__libc_start_main+0xe8]
11694 13:58:58.524085 #5 [<unknown>+0xcdca16b4]
11695 13:58:58.524164 #6 [<unknown>+0xcdca16b4]
11696 13:58:58.526942 Subtest addfb25-bad-modifier failed.
11697 13:58:58.530674 **** DEBUG ****
11698 13:58:58.536642 (kms_addfb_basic:433) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11699 13:58:58.546763 (kms_addfb_basic:433) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11700 13:58:58.567121 (kms_addfb_basic:433) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11701 13:58:58.569982 (kms_addfb_basic:433) CRITICAL: error: 0 != -1
11702 13:58:58.573637 (kms_addfb_basic:433) igt_core-INFO: Stack trace:
11703 13:58:58.583429 (kms_addfb_basic:433) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11704 13:58:58.586684 (kms_addfb_basic:433) igt_core-INFO: #1 [<unknown>+0xcdca47e0]
11705 13:58:58.593206 (kms_addfb_basic:433) igt_core-INFO: #2 [<unknown>+0xcdca6278]
11706 13:58:58.599708 (kms_addfb_basic:433) igt_core-INFO: #3 [<unknown>+0xcdca167c]
11707 13:58:58.606404 (kms_addfb_basic:433) igt_core-INFO: #4 [__libc_start_main+0xe8]
11708 13:58:58.609985 (kms_addfb_basic:433) igt_core-INFO: #5 [<unknown>+0xcdca16b4]
11709 13:58:58.617233 (kms_addfb_basic:433) igt_core-INFO: #6 [<unknown>+0xcdca16b4]
11710 13:58:58.617314 **** END ****
11711 13:58:58.623240 [1mSubtest addfb25-bad-modifier: FAIL (0.005s)[0m
11712 13:58:58.629795 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11713 13:58:58.632786 Test requirement: is_i915_device(fd)
11714 13:58:58.639593 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11715 13:58:58.643068 Test requirement: is_i915_device(fd)
11716 13:58:58.649636 No KMS driver or no outputs, pipes: 8, outputs: 0
11717 13:58:58.652483 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11718 13:58:58.655860 Opened device: /dev/dri/card0
11719 13:58:58.663053 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11720 13:58:58.666207 Test requirement: is_i915_device(fd)
11721 13:58:58.672321 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11722 13:58:58.679004 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11723 13:58:58.682917 Test requirement: is_i915_device(fd)
11724 13:58:58.689421 No KMS driver or no outputs, pipes: 8, outputs: 0
11725 13:58:58.692992 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11726 13:58:58.695641 Opened device: /dev/dri/card0
11727 13:58:58.702830 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11728 13:58:58.705939 Test requirement: is_i915_device(fd)
11729 13:58:58.713035 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11730 13:58:58.719369 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11731 13:58:58.722929 Test requirement: is_i915_device(fd)
11732 13:58:58.725659 No KMS driver or no outputs, pipes: 8, outputs: 0
11733 13:58:58.732459 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11734 13:58:58.735690 Opened device: /dev/dri/card0
11735 13:58:58.742306 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11736 13:58:58.745414 Test requirement: is_i915_device(fd)
11737 13:58:58.752133 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11738 13:58:58.758752 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11739 13:58:58.762148 Test requirement: is_i915_device(fd)
11740 13:58:58.765387 No KMS driver or no outputs, pipes: 8, outputs: 0
11741 13:58:58.772753 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11742 13:58:58.775343 Opened device: /dev/dri/card0
11743 13:58:58.782424 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11744 13:58:58.785751 Test requirement: is_i915_device(fd)
11745 13:58:58.792348 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11746 13:58:58.795217 Test requirement: is_i915_device(fd)
11747 13:58:58.802075 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11748 13:58:58.805513 No KMS driver or no outputs, pipes: 8, outputs: 0
11749 13:58:58.812042 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11750 13:58:58.815071 Opened device: /dev/dri/card0
11751 13:58:58.825074 Test requirement not met in function igt_require_i915, file ../lib/drm<14>[ 23.455098] [IGT] kms_addfb_basic: exiting, ret=77
11752 13:58:58.825155 test.c:720:
11753 13:58:58.828438 Test requirement: is_i915_device(fd)
11754 13:58:58.838660 Test requirem<8>[ 23.466066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11755 13:58:58.838922 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11757 13:58:58.845010 ent not met in function igt_require_i915, file ../lib/drmtest.c:720:
11758 13:58:58.849008 Test requirement: is_i915_device(fd)
11759 13:58:58.855352 [1mSubtest framebuffer-vs-set-tilin<14>[ 23.487053] [IGT] kms_addfb_basic: executing
11760 13:58:58.858379 g: SKIP (0.000s)[0m
11761 13:58:58.861608 No KMS driver or no outputs, pipes: 8, outputs: 0
11762 13:58:58.868643 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11763 13:58:58.874824 Opened device: /d<14>[ 23.505053] [IGT] kms_addfb_basic: exiting, ret=77
11764 13:58:58.874904 ev/dri/card0
11765 13:58:58.889028 Test requirement not met in function igt_require_i<8>[ 23.515974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11766 13:58:58.889282 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11768 13:58:58.892258 915, file ../lib/drmtest.c:720:
11769 13:58:58.895189 Test requirement: is_i915_device(fd)
11770 13:58:58.904957 Test requirement not met in function igt_require_i915, file ../lib/drmtes<14>[ 23.536174] [IGT] kms_addfb_basic: executing
11771 13:58:58.908611 t.c:720:
11772 13:58:58.911909 Test requirement: is_i915_device(fd)
11773 13:58:58.914974 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11774 13:58:58.918186 No KMS driver or no outputs, pipes: 8, outputs: 0
11775 13:58:58.924937 IGT-Versi<14>[ 23.554310] [IGT] kms_addfb_basic: exiting, ret=77
11776 13:58:58.932015 on: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11777 13:58:58.938972 Ope<8>[ 23.565700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11778 13:58:58.939229 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11780 13:58:58.941552 ned device: /dev/dri/card0
11781 13:58:58.948270 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11782 13:58:58.955053 Test requirement: is_i915_device(<14>[ 23.586143] [IGT] kms_addfb_basic: executing
11783 13:58:58.955134 fd)
11784 13:58:58.961832 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11785 13:58:58.964559 Test requirement: is_i915_device(fd)
11786 13:58:58.974440 [1mSubtest basic-y-tiled-legacy: <14>[ 23.603923] [IGT] kms_addfb_basic: exiting, ret=77
11787 13:58:58.974521 SKIP (0.000s)[0m
11788 13:58:58.988001 No KMS driver or no outputs, pipes: 8, output<8>[ 23.615196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11789 13:58:58.988082 s: 0
11790 13:58:58.988318 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11792 13:58:58.994573 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11793 13:58:58.994656 Opened device: /dev/dri/card0
11794 13:58:59.004501 Test requirement not met in function <14>[ 23.634528] [IGT] kms_addfb_basic: executing
11795 13:58:59.007927 igt_require_i915, file ../lib/drmtest.c:720:
11796 13:58:59.011348 Test requirement: is_i915_device(fd)
11797 13:58:59.020953 Test requirement not met in function igt_require_i915, file <14>[ 23.652241] [IGT] kms_addfb_basic: exiting, ret=77
11798 13:58:59.024330 ../lib/drmtest.c:720:
11799 13:58:59.028017 Test requirement: is_i915_device(fd)
11800 13:58:59.034628 No <8>[ 23.662301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11801 13:58:59.034881 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11803 13:58:59.038286 KMS driver or no outputs, pipes: 8, outputs: 0
11804 13:58:59.040896 [1mSubtest size-max: SKIP (0.000s)[0m
11805 13:58:59.050674 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-c<14>[ 23.681653] [IGT] kms_addfb_basic: executing
11806 13:58:59.050756 ip13 aarch64)
11807 13:58:59.054043 Opened device: /dev/dri/card0
11808 13:58:59.061499 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11809 13:58:59.067671 Test requiremen<14>[ 23.699496] [IGT] kms_addfb_basic: exiting, ret=77
11810 13:58:59.070889 t: is_i915_device(fd)
11811 13:58:59.081099 Test requirement not met in function igt_<8>[ 23.709606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11812 13:58:59.081352 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11814 13:58:59.084853 require_i915, file ../lib/drmtest.c:720:
11815 13:58:59.087463 Test requirement: is_i915_device(fd)
11816 13:58:59.090785 No KMS driver or no outputs, pipes: 8, outputs: 0
11817 13:58:59.097485 [1mSubtest t<14>[ 23.728211] [IGT] kms_addfb_basic: executing
11818 13:58:59.100813 oo-wide: SKIP (0.000s)[0m
11819 13:58:59.107447 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11820 13:58:59.110899 Opened device: /dev/dri/card0
11821 13:58:59.114298 Test requiremen<14>[ 23.746630] [IGT] kms_addfb_basic: exiting, ret=77
11822 13:58:59.127405 t not met in function igt_require_i915, file ../lib/drmtest.c:72<8>[ 23.756724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11823 13:58:59.127487 0:
11824 13:58:59.127721 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11826 13:58:59.130696 Test requirement: is_i915_device(fd)
11827 13:58:59.140792 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11828 13:58:59.144240 Test requirement: i<14>[ 23.776489] [IGT] kms_addfb_basic: executing
11829 13:58:59.147393 s_i915_device(fd)
11830 13:58:59.150875 No KMS driver or no outputs, pipes: 8, outputs: 0
11831 13:58:59.154148 [1mSubtest too-high: SKIP (0.000s)[0m
11832 13:58:59.163749 IGT-Version: 1.27.1-g621c2d3 (aar<14>[ 23.794058] [IGT] kms_addfb_basic: exiting, ret=77
11833 13:58:59.167532 ch64) (Linux: 6.1.72-cip13 aarch64)
11834 13:58:59.173822 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11836 13:58:59.177141 Opened device: /dev/dri/car<8>[ 23.803909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11837 13:58:59.177222 d0
11838 13:58:59.183958 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11839 13:58:59.187337 Test requirement: is_i915_device(fd)
11840 13:58:59.193513 Test requirement no<14>[ 23.823923] [IGT] kms_addfb_basic: executing
11841 13:58:59.197010 t met in function igt_require_i915, file ../lib/drmtest.c:720:
11842 13:58:59.200330 Test requirement: is_i915_device(fd)
11843 13:58:59.210191 No KMS driver or no outputs, pipes: 8, out<14>[ 23.841132] [IGT] kms_addfb_basic: exiting, ret=77
11844 13:58:59.210273 puts: 0
11845 13:58:59.214040 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11846 13:58:59.223405 IGT-Versio<8>[ 23.851367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11847 13:58:59.223657 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11849 13:58:59.230237 n: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11850 13:58:59.233639 Opened device: /dev/dri/card0
11851 13:58:59.239719 Test requirement not met in function igt_require_i915<14>[ 23.871887] [IGT] kms_addfb_basic: executing
11852 13:58:59.243378 , file ../lib/drmtest.c:720:
11853 13:58:59.246454 Test requirement: is_i915_device(fd)
11854 13:58:59.253524 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11855 13:58:59.260366 Test requ<14>[ 23.889966] [IGT] kms_addfb_basic: exiting, ret=77
11856 13:58:59.263247 irement: is_i915_device(fd)
11857 13:58:59.272976 No KMS driver or no outputs, pipes:<8>[ 23.901446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11858 13:58:59.273229 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11860 13:58:59.276221 8, outputs: 0
11861 13:58:59.279650 [1mSubtest small-bo: SKIP (0.000s)[0m
11862 13:58:59.286331 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11863 13:58:59.289990 Opened device: /d<14>[ 23.922443] [IGT] kms_addfb_basic: executing
11864 13:58:59.293323 ev/dri/card0
11865 13:58:59.299612 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11866 13:58:59.302629 Test requirement: is_i915_device(fd)
11867 13:58:59.309534 Test requ<14>[ 23.939666] [IGT] kms_addfb_basic: exiting, ret=77
11868 13:58:59.322565 irement not met in function igt_require_i915, file ../lib/drmtes<8>[ 23.949766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11869 13:58:59.322647 t.c:720:
11870 13:58:59.322882 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11872 13:58:59.326107 Test requirement: is_i915_device(fd)
11873 13:58:59.332726 No KMS driver or no outputs, pipes: 8, outputs: 0
11874 13:58:59.339254 [1mSubtest bo-too-small-due-to-tiling: SKIP <14>[ 23.970380] [IGT] kms_addfb_basic: executing
11875 13:58:59.342486 (0.000s)[0m
11876 13:58:59.346195 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11877 13:58:59.349533 Opened device: /dev/dri/card0
11878 13:58:59.359053 Test requirement not met in function igt_requ<14>[ 23.988194] [IGT] kms_addfb_basic: exiting, ret=77
11879 13:58:59.362502 ire_i915, file ../lib/drmtest.c:720:
11880 13:58:59.372602 Test requirement: is_i915_<8>[ 23.999553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11881 13:58:59.372682 device(fd)
11882 13:58:59.372916 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11884 13:58:59.382570 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11885 13:58:59.386052 Test requirement: is_i915_device(fd)
11886 13:58:59.389226 No KMS driv<14>[ 24.020412] [IGT] kms_addfb_basic: executing
11887 13:58:59.392524 er or no outputs, pipes: 8, outputs: 0
11888 13:58:59.398792 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11889 13:58:59.408755 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch<14>[ 24.038630] [IGT] kms_addfb_basic: exiting, ret=77
11890 13:58:59.408836 64)
11891 13:58:59.412434 Opened device: /dev/dri/card0
11892 13:58:59.422129 Test requirement not met in <8>[ 24.050067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11893 13:58:59.422384 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11895 13:58:59.428212 function igt_require_i915, file <8>[ 24.059380] <LAVA_SIGNAL_TESTSET STOP>
11896 13:58:59.428463 Received signal: <TESTSET> STOP
11897 13:58:59.428534 Closing test_set kms_addfb_basic
11898 13:58:59.432371 ../lib/drmtest.c:720:
11899 13:58:59.435461 Test requirement: is_i915_device(fd)
11900 13:58:59.442136 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11901 13:58:59.448699 Test requirement: is_i915_device<8>[ 24.079690] <LAVA_SIGNAL_TESTSET START kms_atomic>
11902 13:58:59.448779 (fd)
11903 13:58:59.449014 Received signal: <TESTSET> START kms_atomic
11904 13:58:59.449082 Starting test_set kms_atomic
11905 13:58:59.454998 No KMS driver or no outputs, pipes: 8, outputs: 0
11906 13:58:59.458434 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11907 13:58:59.468322 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: <14>[ 24.098744] [IGT] kms_atomic: executing
11908 13:58:59.474744 6.1.72-cip13 aar<14>[ 24.103669] [IGT] kms_atomic: exiting, ret=77
11909 13:58:59.474827 ch64)
11910 13:58:59.478791 Opened device: /dev/dri/card0
11911 13:58:59.488405 Test requirement not met i<8>[ 24.114061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11912 13:58:59.488658 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11914 13:58:59.491383 n function igt_require_i915, file ../lib/drmtest.c:720:
11915 13:58:59.494927 Test requirement: is_i915_device(fd)
11916 13:58:59.505060 Test requirement not met in function igt_require_<14>[ 24.134700] [IGT] kms_atomic: executing
11917 13:58:59.507875 i915, file ../li<14>[ 24.139784] [IGT] kms_atomic: exiting, ret=77
11918 13:58:59.511403 b/drmtest.c:720:
11919 13:58:59.514853 Test requirement: is_i915_device(fd)
11920 13:58:59.521549 No KMS d<8>[ 24.150194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11921 13:58:59.521800 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11923 13:58:59.528568 river or no outputs, pipes: 8, outputs: 0
11924 13:58:59.531729 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11925 13:58:59.541679 IGT-Version: 1.27.1-g621c2d3 (aarch64) (<14>[ 24.170662] [IGT] kms_atomic: executing
11926 13:58:59.545074 Linux: 6.1.72-ci<14>[ 24.176036] [IGT] kms_atomic: exiting, ret=77
11927 13:58:59.547963 p13 aarch64)
11928 13:58:59.551617 Opened device: /dev/dri/card0
11929 13:58:59.561211 Test requirement not met in functio<8>[ 24.187688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11930 13:58:59.561463 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11932 13:58:59.564449 n igt_require_i915, file ../lib/drmtest.c:720:
11933 13:58:59.567860 Test requirement: is_i915_device(fd)
11934 13:58:59.577964 Test requirement not met in function igt_require_i915, fil<14>[ 24.209688] [IGT] kms_atomic: executing
11935 13:58:59.584833 e ../lib/drmtest<14>[ 24.214758] [IGT] kms_atomic: exiting, ret=77
11936 13:58:59.584914 .c:720:
11937 13:58:59.588095 Test requirement: is_i915_device(fd)
11938 13:58:59.597743 No KMS driver or <8>[ 24.225047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11939 13:58:59.598000 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11941 13:58:59.601142 no outputs, pipes: 8, outputs: 0
11942 13:58:59.604546 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11943 13:58:59.614917 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aa<14>[ 24.245849] [IGT] kms_atomic: executing
11944 13:58:59.614998 rch64)
11945 13:58:59.621272 Opened d<14>[ 24.250926] [IGT] kms_atomic: exiting, ret=77
11946 13:58:59.621353 evice: /dev/dri/card0
11947 13:58:59.631673 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11949 13:58:59.634492 No KMS driver or no outputs, pipes: 8, ou<8>[ 24.261450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11950 13:58:59.634575 tputs: 0
11951 13:58:59.638377 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11952 13:58:59.644591 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11953 13:58:59.651211 Opened devi<14>[ 24.281167] [IGT] kms_atomic: executing
11954 13:58:59.654684 ce: /dev/dri/car<14>[ 24.286132] [IGT] kms_atomic: exiting, ret=77
11955 13:58:59.657919 d0
11956 13:58:59.661399 No KMS driver or no outputs, pipes: 8, outputs: 0
11957 13:58:59.668043 [1mSubte<8>[ 24.296360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11958 13:58:59.668295 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11960 13:58:59.674305 st plane-primary-legacy: SKIP (0.000s)[0m
11961 13:58:59.678079 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11962 13:58:59.681046 Opened device: /dev/dri/card0
11963 13:58:59.684234 <14>[ 24.316721] [IGT] kms_atomic: executing
11964 13:58:59.684315
11965 13:58:59.691336 No KMS driver o<14>[ 24.322247] [IGT] kms_atomic: exiting, ret=77
11966 13:58:59.694759 r no outputs, pipes: 8, outputs: 0
11967 13:58:59.704250 [1mSubtest plane-primary-ov<8>[ 24.332670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11968 13:58:59.704502 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11970 13:58:59.707548 erlay-mutable-zpos: SKIP (0.000s)[0m
11971 13:58:59.714228 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11972 13:58:59.717886 Opened device: /dev/dri/card0
11973 13:58:59.720723 No K<14>[ 24.353215] [IGT] kms_atomic: executing
11974 13:58:59.727538 MS driver or no <14>[ 24.358427] [IGT] kms_atomic: exiting, ret=77
11975 13:58:59.730692 outputs, pipes: 8, outputs: 0
11976 13:58:59.741022 [1mSubtest plane-immutable-zpos:<8>[ 24.368764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11977 13:58:59.741274 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11979 13:58:59.744072 SKIP (0.000s)[0m
11980 13:58:59.750501 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11981 13:58:59.753817 Opened device: /dev/dri/card0
11982 13:58:59.758216 No KMS driver or no out<14>[ 24.390191] [IGT] kms_atomic: executing
11983 13:58:59.764673 puts, pipes: 8, <14>[ 24.395147] [IGT] kms_atomic: exiting, ret=77
11984 13:58:59.767145 outputs: 0
11985 13:58:59.770959 [1mSubtest test-only: SKIP (0.000s)[0m
11986 13:58:59.777285 IGT-Versio<8>[ 24.405581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11987 13:58:59.777535 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11989 13:58:59.783887 n: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11990 13:58:59.787600 Opened device: /dev/dri/card0
11991 13:58:59.790906 No KMS driver or no outputs, pipes: 8, outputs: 0
11992 13:58:59.794273 [<14>[ 24.425797] [IGT] kms_atomic: executing
11993 13:58:59.800293 1mSubtest plane-<14>[ 24.431243] [IGT] kms_atomic: exiting, ret=77
11994 13:58:59.804346 cursor-legacy: SKIP (0.000s)[0m
11995 13:58:59.814017 IGT-Version: 1.27.1-g621c2d3 (<8>[ 24.441741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11996 13:58:59.814269 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11998 13:58:59.817137 aarch64) (Linux: 6.1.72-cip13 aarch64)
11999 13:58:59.820400 Opened device: /dev/dri/card0
12000 13:58:59.823823 No KMS driver or no outputs, pipes: 8, outputs: 0
12001 13:58:59.830231 [1mSubtest plane-inva<14>[ 24.462608] [IGT] kms_atomic: executing
12002 13:58:59.837356 lid-params: SKIP<14>[ 24.467848] [IGT] kms_atomic: exiting, ret=77
12003 13:58:59.840377 (0.000s)[0m
12004 13:58:59.850519 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<8>[ 24.478197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12005 13:58:59.850772 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12007 13:58:59.853805 1.72-cip13 aarch64)
12008 13:58:59.857037 Opened device: /dev/dri/card0
12009 13:58:59.860260 No KMS driver or no outputs, pipes: 8, outputs: 0
12010 13:58:59.867260 [1mSubtest plane-invalid-params-fence: S<14>[ 24.498782] [IGT] kms_atomic: executing
12011 13:58:59.874038 KIP (0.000s)[0m<14>[ 24.504024] [IGT] kms_atomic: exiting, ret=77
12012 13:58:59.874119
12013 13:58:59.887588 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aa<8>[ 24.514383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
12014 13:58:59.887670 rch64)
12015 13:58:59.887904 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
12017 13:58:59.893632 Opened device: /dev/dri/<8>[ 24.524406] <LAVA_SIGNAL_TESTSET STOP>
12018 13:58:59.893713 card0
12019 13:58:59.893946 Received signal: <TESTSET> STOP
12020 13:58:59.894011 Closing test_set kms_atomic
12021 13:58:59.900143 No KMS driver or no outputs, pipes: 8, outputs: 0
12022 13:58:59.903609 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12023 13:58:59.910126 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12024 13:58:59.916763 Opened devic<8>[ 24.545591] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12025 13:58:59.916869 e: /dev/dri/card0
12026 13:58:59.917162 Received signal: <TESTSET> START kms_flip_event_leak
12027 13:58:59.917230 Starting test_set kms_flip_event_leak
12028 13:58:59.923653 No KMS driver or no outputs, pipes: 8, outputs: 0
12029 13:58:59.926995 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12030 13:58:59.936871 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarc<14>[ 24.568166] [IGT] kms_flip_event_leak: executing
12031 13:58:59.939920 h64)
12032 13:58:59.943346 Opened dev<14>[ 24.574555] [IGT] kms_flip_event_leak: exiting, ret=77
12033 13:58:59.946691 ice: /dev/dri/card0
12034 13:58:59.956688 No KMS driver or no outputs, pipes: 8, outp<8>[ 24.585867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12035 13:58:59.956770 uts: 0
12036 13:58:59.957004 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12038 13:58:59.963767 [1mSubtest atomic-inval<8>[ 24.594330] <LAVA_SIGNAL_TESTSET STOP>
12039 13:58:59.964018 Received signal: <TESTSET> STOP
12040 13:58:59.964087 Closing test_set kms_flip_event_leak
12041 13:58:59.966853 id-params: SKIP (0.000s)[0m
12042 13:58:59.973671 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12043 13:58:59.977054 Opened device: /dev/dri/card0
12044 13:58:59.979885 No KMS driver or no outputs, pipes: 8, outputs: 0
12045 13:58:59.983886 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
12046 13:58:59.989978 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12047 13:58:59.996693 Opened device: /<8>[ 24.626333] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12048 13:58:59.996774 dev/dri/card0
12049 13:58:59.997008 Received signal: <TESTSET> START kms_prop_blob
12050 13:58:59.997075 Starting test_set kms_prop_blob
12051 13:59:00.003938 No KMS driver or no outputs, pipes: 8, outputs: 0
12052 13:59:00.006536 [1mSubtest basic: SKIP (0.000s)[0m
12053 13:59:00.013954 <14>[ 24.644528] [IGT] kms_prop_blob: executing
12054 13:59:00.020109 IGT-Version: 1.2<14>[ 24.649262] [IGT] kms_prop_blob: starting subtest basic
12055 13:59:00.027069 7.1-g621c2d3 (aa<14>[ 24.656121] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12056 13:59:00.033731 rch64) (Linux: 6<14>[ 24.663893] [IGT] kms_prop_blob: exiting, ret=0
12057 13:59:00.036793 .1.72-cip13 aarch64)
12058 13:59:00.040133 Opened device: /dev/dri/card0
12059 13:59:00.046819 Starting su<8>[ 24.674355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12060 13:59:00.046901 btest: basic
12061 13:59:00.047135 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12063 13:59:00.050331 [1mSubtest basic: SUCCESS (0.000s)[0m
12064 13:59:00.063408 <14>[ 24.693971] [IGT] kms_prop_blob: executing
12065 13:59:00.069811 IGT-Version: 1.2<14>[ 24.698956] [IGT] kms_prop_blob: starting subtest blob-prop-core
12066 13:59:00.079466 7.1-g621c2d3 (aa<14>[ 24.706656] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12067 13:59:00.086711 rch64) (Linux: 6<14>[ 24.715152] [IGT] kms_prop_blob: exiting, ret=0
12068 13:59:00.086792 .1.72-cip13 aarch64)
12069 13:59:00.089471 Opened device: /dev/dri/card0
12070 13:59:00.099516 Starting su<8>[ 24.725807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12071 13:59:00.099597 btest: blob-prop-core
12072 13:59:00.099832 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12074 13:59:00.106722 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12075 13:59:00.115031 <14>[ 24.745796] [IGT] kms_prop_blob: executing
12076 13:59:00.121558 IGT-Version: 1.2<14>[ 24.750565] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12077 13:59:00.131264 7.1-g621c2d3 (aa<14>[ 24.758621] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12078 13:59:00.138002 rch64) (Linux: 6<14>[ 24.767463] [IGT] kms_prop_blob: exiting, ret=0
12079 13:59:00.138085 .1.72-cip13 aarch64)
12080 13:59:00.141696 Opened device: /dev/dri/card0
12081 13:59:00.151271 Starting su<8>[ 24.778098] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12082 13:59:00.151538 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12084 13:59:00.155570 btest: blob-prop-validate
12085 13:59:00.158004 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12086 13:59:00.168006 <14>[ 24.798445] [IGT] kms_prop_blob: executing
12087 13:59:00.174016 IGT-Version: 1.2<14>[ 24.803182] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12088 13:59:00.183871 7.1-g621c2d3 (aa<14>[ 24.811212] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12089 13:59:00.187348 <14>[ 24.820060] [IGT] kms_prop_blob: exiting, ret=0
12090 13:59:00.190418 rch64) (Linux: 6.1.72-cip13 aarch64)
12091 13:59:00.200708 Opened device: /dev/dri/ca<8>[ 24.829270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12092 13:59:00.200962 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12094 13:59:00.204286 rd0
12095 13:59:00.207462 Starting subtest: blob-prop-lifetime
12096 13:59:00.210673 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12097 13:59:00.220143 <14>[ 24.850765] [IGT] kms_prop_blob: executing
12098 13:59:00.226270 IGT-Version: 1.2<14>[ 24.855523] [IGT] kms_prop_blob: starting subtest blob-multiple
12099 13:59:00.236744 7.1-g621c2d3 (aa<14>[ 24.863153] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12100 13:59:00.239655 <14>[ 24.871529] [IGT] kms_prop_blob: exiting, ret=0
12101 13:59:00.242978 rch64) (Linux: 6.1.72-cip13 aarch64)
12102 13:59:00.252976 Opened device: /dev/dri/ca<8>[ 24.880716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12103 13:59:00.253057 rd0
12104 13:59:00.253292 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12106 13:59:00.256535 Starting subtest: blob-multiple
12107 13:59:00.259642 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12108 13:59:00.270586 <14>[ 24.901102] [IGT] kms_prop_blob: executing
12109 13:59:00.276947 IGT-Version: 1.2<14>[ 24.905867] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12110 13:59:00.286908 7.1-g621c2d3 (aa<14>[ 24.914032] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12111 13:59:00.293005 rch64) (Linux: 6<14>[ 24.923095] [IGT] kms_prop_blob: exiting, ret=0
12112 13:59:00.296827 .1.72-cip13 aarch64)
12113 13:59:00.296908 Opened device: /dev/dri/card0
12114 13:59:00.306762 Starting su<8>[ 24.933791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12115 13:59:00.307015 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12117 13:59:00.309606 btest: invalid-get-prop-any
12118 13:59:00.313213 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12119 13:59:00.323303 <14>[ 24.954642] [IGT] kms_prop_blob: executing
12120 13:59:00.330016 IGT-Version: 1.2<14>[ 24.959399] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12121 13:59:00.340528 7.1-g621c2d3 (aa<14>[ 24.967214] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12122 13:59:00.346722 rch64) (Linux: 6<14>[ 24.975927] [IGT] kms_prop_blob: exiting, ret=0
12123 13:59:00.346803 .1.72-cip13 aarch64)
12124 13:59:00.350650 Opened device: /dev/dri/card0
12125 13:59:00.361033 Starting su<8>[ 24.986507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12126 13:59:00.361114 btest: invalid-get-prop
12127 13:59:00.361349 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12129 13:59:00.367194 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12130 13:59:00.376259 <14>[ 25.007198] [IGT] kms_prop_blob: executing
12131 13:59:00.382687 IGT-Version: 1.2<14>[ 25.011984] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12132 13:59:00.392796 7.1-g621c2d3 (aa<14>[ 25.020135] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12133 13:59:00.399495 rch64) (Linux: 6<14>[ 25.029200] [IGT] kms_prop_blob: exiting, ret=0
12134 13:59:00.402819 .1.72-cip13 aarch64)
12135 13:59:00.402899 Opened device: /dev/dri/card0
12136 13:59:00.412563 Starting su<8>[ 25.039871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12137 13:59:00.412816 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12139 13:59:00.416310 btest: invalid-set-prop-any
12140 13:59:00.419429 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12141 13:59:00.429512 <14>[ 25.060545] [IGT] kms_prop_blob: executing
12142 13:59:00.435960 IGT-Version: 1.2<14>[ 25.065348] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12143 13:59:00.445973 7.1-g621c2d3 (aa<14>[ 25.073174] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12144 13:59:00.452709 rch64) (Linux: 6<14>[ 25.081921] [IGT] kms_prop_blob: exiting, ret=0
12145 13:59:00.452790 .1.72-cip13 aarch64)
12146 13:59:00.455954 Opened device: /dev/dri/card0
12147 13:59:00.466009 Starting su<8>[ 25.092414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12148 13:59:00.466090 btest: invalid-set-prop
12149 13:59:00.466324 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12151 13:59:00.472533 [1mSub<8>[ 25.102415] <LAVA_SIGNAL_TESTSET STOP>
12152 13:59:00.472783 Received signal: <TESTSET> STOP
12153 13:59:00.472850 Closing test_set kms_prop_blob
12154 13:59:00.475751 test invalid-set-prop: SUCCESS (0.000s)[0m
12155 13:59:00.491304 <8>[ 25.122611] <LAVA_SIGNAL_TESTSET START kms_setmode>
12156 13:59:00.491571 Received signal: <TESTSET> START kms_setmode
12157 13:59:00.491640 Starting test_set kms_setmode
12158 13:59:00.509488 <14>[ 25.140072] [IGT] kms_setmode: executing
12159 13:59:00.515599 IGT-Version: 1.2<14>[ 25.144698] [IGT] kms_setmode: starting subtest basic
12160 13:59:00.522123 7.1-g621c2d3 (aa<14>[ 25.151359] [IGT] kms_setmode: finished subtest basic, SKIP
12161 13:59:00.528795 rch64) (Linux: 6<14>[ 25.158698] [IGT] kms_setmode: exiting, ret=77
12162 13:59:00.532463 .1.72-cip13 aarch64)
12163 13:59:00.532544 Opened device: /dev/dri/card0
12164 13:59:00.542684 Starting su<8>[ 25.169238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12165 13:59:00.542766 btest: basic
12166 13:59:00.543001 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12168 13:59:00.546015 No dynamic tests executed.
12169 13:59:00.548792 [1mSubtest basic: SKIP (0.000s)[0m
12170 13:59:00.558182 <14>[ 25.189262] [IGT] kms_setmode: executing
12171 13:59:00.565439 IGT-Version: 1.2<14>[ 25.193931] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12172 13:59:00.575050 7.1-g621c2d3 (aa<14>[ 25.202097] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12173 13:59:00.581672 rch64) (Linux: 6<14>[ 25.210993] [IGT] kms_setmode: exiting, ret=77
12174 13:59:00.581753 .1.72-cip13 aarch64)
12175 13:59:00.585044 Opened device: /dev/dri/card0
12176 13:59:00.594670 Starting su<8>[ 25.221821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12177 13:59:00.594922 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12179 13:59:00.598059 btest: basic-clone-single-crtc
12180 13:59:00.601469 No dynamic tests executed.
12181 13:59:00.604742 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12182 13:59:00.611875 <14>[ 25.242967] [IGT] kms_setmode: executing
12183 13:59:00.618765 IGT-Version: 1.2<14>[ 25.247610] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12184 13:59:00.628722 7.1-g621c2d3 (aa<14>[ 25.255972] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12185 13:59:00.635436 rch64) (Linux: 6<14>[ 25.265052] [IGT] kms_setmode: exiting, ret=77
12186 13:59:00.639116 .1.72-cip13 aarch64)
12187 13:59:00.639199 Opened device: /dev/dri/card0
12188 13:59:00.648617 Starting su<8>[ 25.275466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12189 13:59:00.648870 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12191 13:59:00.652261 btest: invalid-clone-single-crtc
12192 13:59:00.655522 No dynamic tests executed.
12193 13:59:00.658521 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12194 13:59:00.665847 <14>[ 25.297012] [IGT] kms_setmode: executing
12195 13:59:00.675736 IGT-Version: 1.2<14>[ 25.301768] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12196 13:59:00.682305 7.1-g621c2d3 (aa<14>[ 25.310395] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12197 13:59:00.689279 rch64) (Linux: 6<14>[ 25.319726] [IGT] kms_setmode: exiting, ret=77
12198 13:59:00.692428 .1.72-cip13 aarch64)
12199 13:59:00.696367 Opened device: /dev/dri/card0
12200 13:59:00.702665 Starting su<8>[ 25.330187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12201 13:59:00.702917 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12203 13:59:00.705922 btest: invalid-clone-exclusive-crtc
12204 13:59:00.709436 No dynamic tests executed.
12205 13:59:00.715605 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12206 13:59:00.718863 <14>[ 25.351746] [IGT] kms_setmode: executing
12207 13:59:00.728776 IGT-Version: 1.2<14>[ 25.356391] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12208 13:59:00.735655 7.1-g621c2d3 (aa<14>[ 25.364324] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12209 13:59:00.741977 rch64) (Linux: 6<14>[ 25.372942] [IGT] kms_setmode: exiting, ret=77
12210 13:59:00.745393 .1.72-cip13 aarch64)
12211 13:59:00.749345 Opened device: /dev/dri/card0
12212 13:59:00.755955 Starting su<8>[ 25.383449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12213 13:59:00.756208 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12215 13:59:00.759407 btest: clone-exclusive-crtc
12216 13:59:00.762658 No dynamic tests executed.
12217 13:59:00.765702 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12218 13:59:00.773595 <14>[ 25.404516] [IGT] kms_setmode: executing
12219 13:59:00.783349 IGT-Version: 1.2<14>[ 25.409174] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12220 13:59:00.793466 7.1-g621c2d3 (aa<14>[ 25.418315] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12221 13:59:00.796580 rch64) (Linux: 6<14>[ 25.428158] [IGT] kms_setmode: exiting, ret=77
12222 13:59:00.800112 .1.72-cip13 aarch64)
12223 13:59:00.803253 Opened device: /dev/dri/card0
12224 13:59:00.813783 Starting su<8>[ 25.438543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12225 13:59:00.814079 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12227 13:59:00.816476 btest: invalid-c<8>[ 25.450120] <LAVA_SIGNAL_TESTSET STOP>
12228 13:59:00.816726 Received signal: <TESTSET> STOP
12229 13:59:00.816793 Closing test_set kms_setmode
12230 13:59:00.819871 lone-single-crtc-stealing
12231 13:59:00.823463 No dynamic tests executed.
12232 13:59:00.830188 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12233 13:59:00.837446 <8>[ 25.468587] <LAVA_SIGNAL_TESTSET START kms_vblank>
12234 13:59:00.837722 Received signal: <TESTSET> START kms_vblank
12235 13:59:00.837792 Starting test_set kms_vblank
12236 13:59:00.856132 <14>[ 25.487277] [IGT] kms_vblank: executing
12237 13:59:00.862931 IGT-Version: 1.2<14>[ 25.491993] [IGT] kms_vblank: exiting, ret=77
12238 13:59:00.865987 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12239 13:59:00.873078 Opened dev<8>[ 25.502636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12240 13:59:00.873330 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12242 13:59:00.876527 ice: /dev/dri/card0
12243 13:59:00.879250 No KMS driver or no outputs, pipes: 8, outputs: 0
12244 13:59:00.883219 [1mSubtest invalid: SKIP (0.000s)[0m
12245 13:59:00.891435 <14>[ 25.522328] [IGT] kms_vblank: executing
12246 13:59:00.898019 IGT-Version: 1.2<14>[ 25.527005] [IGT] kms_vblank: exiting, ret=77
12247 13:59:00.901137 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12248 13:59:00.907707 Opened dev<8>[ 25.537593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12249 13:59:00.907960 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12251 13:59:00.911067 ice: /dev/dri/card0
12252 13:59:00.914308 No KMS driver or no outputs, pipes: 8, outputs: 0
12253 13:59:00.917796 [1mSubtest crtc-id: SKIP (0.000s)[0m
12254 13:59:00.925573 <14>[ 25.556581] [IGT] kms_vblank: executing
12255 13:59:00.932357 IGT-Version: 1.2<14>[ 25.561315] [IGT] kms_vblank: exiting, ret=77
12256 13:59:00.935640 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12257 13:59:00.945455 Opened dev<8>[ 25.571424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12258 13:59:00.945538 ice: /dev/dri/card0
12259 13:59:00.945774 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12261 13:59:00.952197 No KMS driver or no outputs, pipes: 8, outputs: 0
12262 13:59:00.955454 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12263 13:59:00.961948 <14>[ 25.593016] [IGT] kms_vblank: executing
12264 13:59:00.968563 IGT-Version: 1.2<14>[ 25.597937] [IGT] kms_vblank: exiting, ret=77
12265 13:59:00.971703 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12266 13:59:00.978486 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12268 13:59:00.982025 Opened dev<8>[ 25.607956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12269 13:59:00.982107 ice: /dev/dri/card0
12270 13:59:00.985324 No KMS driver or no outputs, pipes: 8, outputs: 0
12271 13:59:00.991664 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12272 13:59:00.994993 <14>[ 25.628654] [IGT] kms_vblank: executing
12273 13:59:01.002097 IGT-Version: 1.2<14>[ 25.633692] [IGT] kms_vblank: exiting, ret=77
12274 13:59:01.008508 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12275 13:59:01.015656 Opened dev<8>[ 25.643778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12276 13:59:01.015910 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12278 13:59:01.018996 ice: /dev/dri/card0
12279 13:59:01.022576 No KMS driver or no outputs, pipes: 8, outputs: 0
12280 13:59:01.028532 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12281 13:59:01.032051 <14>[ 25.665007] [IGT] kms_vblank: executing
12282 13:59:01.038669 IGT-Version: 1.2<14>[ 25.669892] [IGT] kms_vblank: exiting, ret=77
12283 13:59:01.045041 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12284 13:59:01.052614 Opened dev<8>[ 25.679841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12285 13:59:01.052867 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12287 13:59:01.055466 ice: /dev/dri/card0
12288 13:59:01.058505 No KMS driver or no outputs, pipes: 8, outputs: 0
12289 13:59:01.062039 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12290 13:59:01.069072 <14>[ 25.700366] [IGT] kms_vblank: executing
12291 13:59:01.075970 IGT-Version: 1.2<14>[ 25.705059] [IGT] kms_vblank: exiting, ret=77
12292 13:59:01.079480 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12293 13:59:01.089455 Opened dev<8>[ 25.715241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12294 13:59:01.089535 ice: /dev/dri/card0
12295 13:59:01.089769 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12297 13:59:01.095880 No KMS driver or no outputs, pipes: 8, outputs: 0
12298 13:59:01.099000 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12299 13:59:01.105901 <14>[ 25.736652] [IGT] kms_vblank: executing
12300 13:59:01.113295 IGT-Version: 1.2<14>[ 25.741479] [IGT] kms_vblank: exiting, ret=77
12301 13:59:01.116143 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12302 13:59:01.122722 Opened dev<8>[ 25.751831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12303 13:59:01.122974 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12305 13:59:01.126000 ice: /dev/dri/card0
12306 13:59:01.128683 No KMS driver or no outputs, pipes: 8, outputs: 0
12307 13:59:01.135572 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12308 13:59:01.138708 <14>[ 25.771936] [IGT] kms_vblank: executing
12309 13:59:01.145642 IGT-Version: 1.2<14>[ 25.776644] [IGT] kms_vblank: exiting, ret=77
12310 13:59:01.152168 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12311 13:59:01.159975 Opened dev<8>[ 25.786900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12312 13:59:01.160227 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12314 13:59:01.162340 ice: /dev/dri/card0
12315 13:59:01.166110 No KMS driver or no outputs, pipes: 8, outputs: 0
12316 13:59:01.172481 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12317 13:59:01.175871 <14>[ 25.807693] [IGT] kms_vblank: executing
12318 13:59:01.182179 IGT-Version: 1.2<14>[ 25.812407] [IGT] kms_vblank: exiting, ret=77
12319 13:59:01.185430 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12320 13:59:01.195799 Opened dev<8>[ 25.822796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12321 13:59:01.196050 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12323 13:59:01.198745 ice: /dev/dri/card0
12324 13:59:01.202377 No KMS driver or no outputs, pipes: 8, outputs: 0
12325 13:59:01.205711 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12326 13:59:01.212485 <14>[ 25.843710] [IGT] kms_vblank: executing
12327 13:59:01.219129 IGT-Version: 1.2<14>[ 25.848435] [IGT] kms_vblank: exiting, ret=77
12328 13:59:01.222573 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12329 13:59:01.232226 Opened dev<8>[ 25.858687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12330 13:59:01.232306 ice: /dev/dri/card0
12331 13:59:01.232540 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12333 13:59:01.239079 No KMS driver or no outputs, pipes: 8, outputs: 0
12334 13:59:01.242524 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12335 13:59:01.248924 <14>[ 25.879922] [IGT] kms_vblank: executing
12336 13:59:01.256037 IGT-Version: 1.2<14>[ 25.884613] [IGT] kms_vblank: exiting, ret=77
12337 13:59:01.259319 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12338 13:59:01.266215 Opened dev<8>[ 25.894780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12339 13:59:01.266467 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12341 13:59:01.269097 ice: /dev/dri/card0
12342 13:59:01.272283 No KMS driver or no outputs, pipes: 8, outputs: 0
12343 13:59:01.278942 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12344 13:59:01.282637 <14>[ 25.915369] [IGT] kms_vblank: executing
12345 13:59:01.289009 IGT-Version: 1.2<14>[ 25.920115] [IGT] kms_vblank: exiting, ret=77
12346 13:59:01.295924 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12347 13:59:01.302156 Opened dev<8>[ 25.930254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12348 13:59:01.302411 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12350 13:59:01.305776 ice: /dev/dri/card0
12351 13:59:01.309286 No KMS driver or no outputs, pipes: 8, outputs: 0
12352 13:59:01.315584 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12353 13:59:01.318890 <14>[ 25.951171] [IGT] kms_vblank: executing
12354 13:59:01.325492 IGT-Version: 1.2<14>[ 25.955946] [IGT] kms_vblank: exiting, ret=77
12355 13:59:01.328772 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12356 13:59:01.338989 Opened dev<8>[ 25.966316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12357 13:59:01.339095 ice: /dev/dri/card0
12358 13:59:01.339357 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12360 13:59:01.345634 No KMS driver or no outputs, pipes: 8, outputs: 0
12361 13:59:01.348900 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12362 13:59:01.355881 <14>[ 25.987200] [IGT] kms_vblank: executing
12363 13:59:01.362977 IGT-Version: 1.2<14>[ 25.991891] [IGT] kms_vblank: exiting, ret=77
12364 13:59:01.366246 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12365 13:59:01.375728 Opened dev<8>[ 26.002258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12366 13:59:01.375808 ice: /dev/dri/card0
12367 13:59:01.376041 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12369 13:59:01.382945 No KMS driver or no outputs, pipes: 8, outputs: 0
12370 13:59:01.386200 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12371 13:59:01.389502 <14>[ 26.022918] [IGT] kms_vblank: executing
12372 13:59:01.395980 IGT-Version: 1.2<14>[ 26.027623] [IGT] kms_vblank: exiting, ret=77
12373 13:59:01.402644 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12374 13:59:01.409709 Opened dev<8>[ 26.038266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12375 13:59:01.409960 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12377 13:59:01.412514 ice: /dev/dri/card0
12378 13:59:01.416196 No KMS driver or no outputs, pipes: 8, outputs: 0
12379 13:59:01.419204 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12380 13:59:01.427400 <14>[ 26.058651] [IGT] kms_vblank: executing
12381 13:59:01.434232 IGT-Version: 1.2<14>[ 26.063512] [IGT] kms_vblank: exiting, ret=77
12382 13:59:01.438056 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12383 13:59:01.448448 Opened dev<8>[ 26.073780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12384 13:59:01.448550 ice: /dev/dri/card0
12385 13:59:01.448811 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12387 13:59:01.454630 No KMS driver or no outputs, pipes: 8, outputs: 0
12388 13:59:01.457952 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12389 13:59:01.464384 <14>[ 26.094747] [IGT] kms_vblank: executing
12390 13:59:01.468033 IGT-Version: 1.2<14>[ 26.099543] [IGT] kms_vblank: exiting, ret=77
12391 13:59:01.474207 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12392 13:59:01.481754 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12394 13:59:01.484160 Opened dev<8>[ 26.110036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12395 13:59:01.484241 ice: /dev/dri/card0
12396 13:59:01.487406 No KMS driver or no outputs, pipes: 8, outputs: 0
12397 13:59:01.493996 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12398 13:59:01.497218 <14>[ 26.130779] [IGT] kms_vblank: executing
12399 13:59:01.504183 IGT-Version: 1.2<14>[ 26.135501] [IGT] kms_vblank: exiting, ret=77
12400 13:59:01.510495 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12401 13:59:01.517365 Opened dev<8>[ 26.145998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12402 13:59:01.517642 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12404 13:59:01.520665 ice: /dev/dri/card0
12405 13:59:01.524270 No KMS driver or no outputs, pipes: 8, outputs: 0
12406 13:59:01.530889 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12407 13:59:01.534236 <14>[ 26.167184] [IGT] kms_vblank: executing
12408 13:59:01.540870 IGT-Version: 1.2<14>[ 26.171951] [IGT] kms_vblank: exiting, ret=77
12409 13:59:01.547320 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12410 13:59:01.553931 Opened dev<8>[ 26.182399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12411 13:59:01.554174 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12413 13:59:01.557398 ice: /dev/dri/card0
12414 13:59:01.560602 No KMS driver or no outputs, pipes: 8, outputs: 0
12415 13:59:01.567288 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12416 13:59:01.570381 <14>[ 26.203257] [IGT] kms_vblank: executing
12417 13:59:01.577320 IGT-Version: 1.2<14>[ 26.208032] [IGT] kms_vblank: exiting, ret=77
12418 13:59:01.580800 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12419 13:59:01.590261 Opened dev<8>[ 26.218669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12420 13:59:01.590543 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12422 13:59:01.593848 ice: /dev/dri/card0
12423 13:59:01.597118 No KMS driver or no outputs, pipes: 8, outputs: 0
12424 13:59:01.603604 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12425 13:59:01.607137 <14>[ 26.239865] [IGT] kms_vblank: executing
12426 13:59:01.613666 IGT-Version: 1.2<14>[ 26.244829] [IGT] kms_vblank: exiting, ret=77
12427 13:59:01.620518 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12428 13:59:01.626924 Opened dev<8>[ 26.255175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12429 13:59:01.627180 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12431 13:59:01.630113 ice: /dev/dri/card0
12432 13:59:01.633999 No KMS driver or no outputs, pipes: 8, outputs: 0
12433 13:59:01.640606 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12434 13:59:01.643706 <14>[ 26.276581] [IGT] kms_vblank: executing
12435 13:59:01.650019 IGT-Version: 1.2<14>[ 26.281687] [IGT] kms_vblank: exiting, ret=77
12436 13:59:01.657310 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12437 13:59:01.666708 Opened dev<8>[ 26.291803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12438 13:59:01.666819 ice: /dev/dri/card0
12439 13:59:01.667079 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12441 13:59:01.673720 No KMS driver or no outputs, pipes: 8, outputs: 0
12442 13:59:01.676789 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12443 13:59:01.683403 <14>[ 26.313795] [IGT] kms_vblank: executing
12444 13:59:01.686584 IGT-Version: 1.2<14>[ 26.318749] [IGT] kms_vblank: exiting, ret=77
12445 13:59:01.694190 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12446 13:59:01.703988 Opened dev<8>[ 26.328766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12447 13:59:01.704068 ice: /dev/dri/card0
12448 13:59:01.704325 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12450 13:59:01.709719 No KMS driver or no outputs, pipes: 8, outputs: 0
12451 13:59:01.713723 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12452 13:59:01.719872 <14>[ 26.350994] [IGT] kms_vblank: executing
12453 13:59:01.726686 IGT-Version: 1.2<14>[ 26.355740] [IGT] kms_vblank: exiting, ret=77
12454 13:59:01.730150 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12455 13:59:01.740265 Opened dev<8>[ 26.366032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12456 13:59:01.740346 ice: /dev/dri/card0
12457 13:59:01.740580 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12459 13:59:01.747058 No KMS driver or no outputs, pipes: 8, outputs: 0
12460 13:59:01.749871 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12461 13:59:01.756461 <14>[ 26.387697] [IGT] kms_vblank: executing
12462 13:59:01.762852 IGT-Version: 1.2<14>[ 26.392414] [IGT] kms_vblank: exiting, ret=77
12463 13:59:01.766708 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12464 13:59:01.776844 Opened dev<8>[ 26.402761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12465 13:59:01.777092 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12467 13:59:01.779624 ice: /dev/dri/card0
12468 13:59:01.783506 No KMS driver or no outputs, pipes: 8, outputs: 0
12469 13:59:01.789579 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12470 13:59:01.792874 <14>[ 26.424457] [IGT] kms_vblank: executing
12471 13:59:01.799930 IGT-Version: 1.2<14>[ 26.429886] [IGT] kms_vblank: exiting, ret=77
12472 13:59:01.803124 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12473 13:59:01.812931 Opened dev<8>[ 26.440028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12474 13:59:01.813209 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12476 13:59:01.816532 ice: /dev/dri/card0
12477 13:59:01.819280 No KMS driver or no outputs, pipes: 8, outputs: 0
12478 13:59:01.826201 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12479 13:59:01.829459 <14>[ 26.461654] [IGT] kms_vblank: executing
12480 13:59:01.835866 IGT-Version: 1.2<14>[ 26.466673] [IGT] kms_vblank: exiting, ret=77
12481 13:59:01.839327 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12482 13:59:01.849478 Opened dev<8>[ 26.476918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12483 13:59:01.849767 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12485 13:59:01.852624 ice: /dev/dri/card0
12486 13:59:01.856167 No KMS driver or no outputs, pipes: 8, outputs: 0
12487 13:59:01.859120 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12488 13:59:01.866534 <14>[ 26.497873] [IGT] kms_vblank: executing
12489 13:59:01.873122 IGT-Version: 1.2<14>[ 26.502582] [IGT] kms_vblank: exiting, ret=77
12490 13:59:01.876686 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12491 13:59:01.886547 Opened dev<8>[ 26.513009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12492 13:59:01.886634 ice: /dev/dri/card0
12493 13:59:01.886873 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12495 13:59:01.889895 No KMS driver or no outputs, pipes: 8, outputs: 0
12496 13:59:01.896471 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12497 13:59:01.900187 <14>[ 26.533057] [IGT] kms_vblank: executing
12498 13:59:01.907028 IGT-Version: 1.2<14>[ 26.537978] [IGT] kms_vblank: exiting, ret=77
12499 13:59:01.913554 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12500 13:59:01.916548 Opened device: /dev/dri/card0
12501 13:59:01.923814 No KMS driv<8>[ 26.550772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12502 13:59:01.924122 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12504 13:59:01.926341 er or no outputs, pipes: 8, outputs: 0
12505 13:59:01.933052 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12506 13:59:01.941274 <14>[ 26.572226] [IGT] kms_vblank: executing
12507 13:59:01.947726 IGT-Version: 1.2<14>[ 26.576952] [IGT] kms_vblank: exiting, ret=77
12508 13:59:01.951145 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12509 13:59:01.961035 Opened device: /dev/dri/ca<8>[ 26.588580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12510 13:59:01.961117 rd0
12511 13:59:01.961351 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12513 13:59:01.964600 No KMS driver or no outputs, pipes: 8, outputs: 0
12514 13:59:01.971329 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12515 13:59:01.978996 <14>[ 26.610063] [IGT] kms_vblank: executing
12516 13:59:01.985522 IGT-Version: 1.2<14>[ 26.614811] [IGT] kms_vblank: exiting, ret=77
12517 13:59:01.988683 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12518 13:59:01.999260 Opened dev<8>[ 26.624939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12519 13:59:01.999341 ice: /dev/dri/card0
12520 13:59:01.999575 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12522 13:59:02.005539 No KMS driver or no outputs, pipes: 8, outputs: 0
12523 13:59:02.009091 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12524 13:59:02.015610 <14>[ 26.646141] [IGT] kms_vblank: executing
12525 13:59:02.018908 IGT-Version: 1.2<14>[ 26.650977] [IGT] kms_vblank: exiting, ret=77
12526 13:59:02.025361 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12527 13:59:02.032149 Opened dev<8>[ 26.661106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12528 13:59:02.032400 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12530 13:59:02.035426 ice: /dev/dri/card0
12531 13:59:02.038713 No KMS driver or no outputs, pipes: 8, outputs: 0
12532 13:59:02.045356 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12533 13:59:02.049026 <14>[ 26.681162] [IGT] kms_vblank: executing
12534 13:59:02.055015 IGT-Version: 1.2<14>[ 26.686011] [IGT] kms_vblank: exiting, ret=77
12535 13:59:02.058822 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12536 13:59:02.068405 Opened dev<8>[ 26.696386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12537 13:59:02.068660 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12539 13:59:02.072170 ice: /dev/dri/card0
12540 13:59:02.075173 No KMS driver or no outputs, pipes: 8, outputs: 0
12541 13:59:02.078521 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12542 13:59:02.085779 <14>[ 26.717191] [IGT] kms_vblank: executing
12543 13:59:02.093199 IGT-Version: 1.2<14>[ 26.721969] [IGT] kms_vblank: exiting, ret=77
12544 13:59:02.095754 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12545 13:59:02.105608 Opened dev<8>[ 26.732230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12546 13:59:02.105682 ice: /dev/dri/card0
12547 13:59:02.105917 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12549 13:59:02.112707 No KMS driver or no outputs, pipes: 8, outputs: 0
12550 13:59:02.115955 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12551 13:59:02.122537 <14>[ 26.753623] [IGT] kms_vblank: executing
12552 13:59:02.129705 IGT-Version: 1.2<14>[ 26.758352] [IGT] kms_vblank: exiting, ret=77
12553 13:59:02.132266 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12554 13:59:02.142107 Opened dev<8>[ 26.768447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12555 13:59:02.142188 ice: /dev/dri/card0
12556 13:59:02.142439 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12558 13:59:02.148894 No KMS driver or no outputs, pipes: 8, outputs: 0
12559 13:59:02.152384 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12560 13:59:02.159184 <14>[ 26.789959] [IGT] kms_vblank: executing
12561 13:59:02.165799 IGT-Version: 1.2<14>[ 26.794652] [IGT] kms_vblank: exiting, ret=77
12562 13:59:02.168820 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12563 13:59:02.175577 Opened dev<8>[ 26.804787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12564 13:59:02.175826 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12566 13:59:02.179129 ice: /dev/dri/card0
12567 13:59:02.182267 No KMS driver or no outputs, pipes: 8, outputs: 0
12568 13:59:02.189258 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12569 13:59:02.192170 <14>[ 26.825040] [IGT] kms_vblank: executing
12570 13:59:02.198797 IGT-Version: 1.2<14>[ 26.829894] [IGT] kms_vblank: exiting, ret=77
12571 13:59:02.205358 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12572 13:59:02.212524 Opened dev<8>[ 26.840126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12573 13:59:02.212770 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12575 13:59:02.215375 ice: /dev/dri/card0
12576 13:59:02.218761 No KMS driver or no outputs, pipes: 8, outputs: 0
12577 13:59:02.221944 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12578 13:59:02.229792 <14>[ 26.861327] [IGT] kms_vblank: executing
12579 13:59:02.236722 IGT-Version: 1.2<14>[ 26.866048] [IGT] kms_vblank: exiting, ret=77
12580 13:59:02.240012 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12581 13:59:02.249754 Opened dev<8>[ 26.876391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12582 13:59:02.249832 ice: /dev/dri/card0
12583 13:59:02.250067 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12585 13:59:02.256590 No KMS driver or no outputs, pipes: 8, outputs: 0
12586 13:59:02.260028 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12587 13:59:02.266570 <14>[ 26.896927] [IGT] kms_vblank: executing
12588 13:59:02.270028 IGT-Version: 1.2<14>[ 26.901881] [IGT] kms_vblank: exiting, ret=77
12589 13:59:02.276883 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12590 13:59:02.283232 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12592 13:59:02.286660 Opened dev<8>[ 26.911855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12593 13:59:02.286743 ice: /dev/dri/card0
12594 13:59:02.289877 No KMS driver or no outputs, pipes: 8, outputs: 0
12595 13:59:02.296313 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12596 13:59:02.312628 <14>[ 26.944072] [IGT] kms_vblank: executing
12597 13:59:02.320271 IGT-Version: 1.2<14>[ 26.949180] [IGT] kms_vblank: exiting, ret=77
12598 13:59:02.322760 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12599 13:59:02.329588 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12601 13:59:02.332772 Opened dev<8>[ 26.960078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12602 13:59:02.332853 ice: /dev/dri/card0
12603 13:59:02.336400 No KMS driver or no outputs, pipes: 8, outputs: 0
12604 13:59:02.342571 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12605 13:59:02.362864 <14>[ 26.994022] [IGT] kms_vblank: executing
12606 13:59:02.369430 IGT-Version: 1.2<14>[ 26.999154] [IGT] kms_vblank: exiting, ret=77
12607 13:59:02.372710 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12608 13:59:02.382955 Opened device: /dev/dri/ca<8>[ 27.010438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12609 13:59:02.383035 rd0
12610 13:59:02.383277 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12612 13:59:02.389522 No KMS driver or no outputs, pipes: 8, outputs: 0
12613 13:59:02.392614 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12614 13:59:02.400603 <14>[ 27.031826] [IGT] kms_vblank: executing
12615 13:59:02.407346 IGT-Version: 1.2<14>[ 27.036614] [IGT] kms_vblank: exiting, ret=77
12616 13:59:02.411242 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12617 13:59:02.420690 Opened dev<8>[ 27.046694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12618 13:59:02.420770 ice: /dev/dri/card0
12619 13:59:02.421004 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12621 13:59:02.426781 No KMS driver or no outputs, pipes: 8, outputs: 0
12622 13:59:02.430559 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12623 13:59:02.436783 <14>[ 27.067767] [IGT] kms_vblank: executing
12624 13:59:02.440563 IGT-Version: 1.2<14>[ 27.072501] [IGT] kms_vblank: exiting, ret=77
12625 13:59:02.447402 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12626 13:59:02.456662 Opened dev<8>[ 27.082637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12627 13:59:02.456743 ice: /dev/dri/card0
12628 13:59:02.456975 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12630 13:59:02.463332 No KMS driver or no outputs, pipes: 8, outputs: 0
12631 13:59:02.466890 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12632 13:59:02.469793 <14>[ 27.103770] [IGT] kms_vblank: executing
12633 13:59:02.477239 IGT-Version: 1.2<14>[ 27.108487] [IGT] kms_vblank: exiting, ret=77
12634 13:59:02.483433 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12635 13:59:02.490013 Opened dev<8>[ 27.118648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12636 13:59:02.490264 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12638 13:59:02.493491 ice: /dev/dri/card0
12639 13:59:02.497005 No KMS driver or no outputs, pipes: 8, outputs: 0
12640 13:59:02.503566 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12641 13:59:02.513029 <14>[ 27.144049] [IGT] kms_vblank: executing
12642 13:59:02.519768 IGT-Version: 1.2<14>[ 27.148783] [IGT] kms_vblank: exiting, ret=77
12643 13:59:02.522635 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12644 13:59:02.532409 Opened dev<8>[ 27.158788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12645 13:59:02.532660 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12647 13:59:02.535918 ice: /dev/dri/card0
12648 13:59:02.539475 No KMS driver or no outputs, pipes: 8, outputs: 0
12649 13:59:02.545842 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12650 13:59:02.549345 <14>[ 27.180294] [IGT] kms_vblank: executing
12651 13:59:02.556290 IGT-Version: 1.2<14>[ 27.185433] [IGT] kms_vblank: exiting, ret=77
12652 13:59:02.559473 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12653 13:59:02.569330 Opened dev<8>[ 27.195711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12654 13:59:02.569614 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12656 13:59:02.572619 ice: /dev/dri/card0
12657 13:59:02.576012 No KMS driver or no outputs, pipes: 8, outputs: 0
12658 13:59:02.582339 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12659 13:59:02.586044 <14>[ 27.217257] [IGT] kms_vblank: executing
12660 13:59:02.592377 IGT-Version: 1.2<14>[ 27.222069] [IGT] kms_vblank: exiting, ret=77
12661 13:59:02.595635 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12662 13:59:02.605824 Opened dev<8>[ 27.232287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12663 13:59:02.606108 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12665 13:59:02.609223 ice: /dev/dri/card0
12666 13:59:02.613054 No KMS driver or no outputs, pipes: 8, outputs: 0
12667 13:59:02.618985 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12668 13:59:02.622511 <14>[ 27.254277] [IGT] kms_vblank: executing
12669 13:59:02.629002 IGT-Version: 1.2<14>[ 27.259227] [IGT] kms_vblank: exiting, ret=77
12670 13:59:02.632261 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12671 13:59:02.642218 Opened dev<8>[ 27.269568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12672 13:59:02.642502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12674 13:59:02.645536 ice: /dev/dri/card0
12675 13:59:02.649010 No KMS driver or no outputs, pipes: 8, outputs: 0
12676 13:59:02.655693 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12677 13:59:02.659039 <14>[ 27.290985] [IGT] kms_vblank: executing
12678 13:59:02.665329 IGT-Version: 1.2<14>[ 27.295700] [IGT] kms_vblank: exiting, ret=77
12679 13:59:02.669386 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12680 13:59:02.678690 Opened dev<8>[ 27.306011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12681 13:59:02.678945 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12683 13:59:02.682190 ice: /dev/dri/card0
12684 13:59:02.685328 No KMS driver or no outputs, pipes: 8, outputs: 0
12685 13:59:02.691614 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12686 13:59:02.695122 <14>[ 27.327198] [IGT] kms_vblank: executing
12687 13:59:02.702351 IGT-Version: 1.2<14>[ 27.332062] [IGT] kms_vblank: exiting, ret=77
12688 13:59:02.705542 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12689 13:59:02.715404 Opened dev<8>[ 27.342239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12690 13:59:02.715689 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12692 13:59:02.718990 ice: /dev/dri/card0
12693 13:59:02.721914 No KMS driver or no outputs, pipes: 8, outputs: 0
12694 13:59:02.728897 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12695 13:59:02.732030 <14>[ 27.364188] [IGT] kms_vblank: executing
12696 13:59:02.738476 IGT-Version: 1.2<14>[ 27.369259] [IGT] kms_vblank: exiting, ret=77
12697 13:59:02.742259 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12698 13:59:02.752064 Opened dev<8>[ 27.379554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12699 13:59:02.752341 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12701 13:59:02.754924 ice: /dev/dri/card0
12702 13:59:02.758855 No KMS driver or no outputs, pipes: 8, outputs: 0
12703 13:59:02.765082 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12704 13:59:02.768142 <14>[ 27.401466] [IGT] kms_vblank: executing
12705 13:59:02.775466 IGT-Version: 1.2<14>[ 27.406281] [IGT] kms_vblank: exiting, ret=77
12706 13:59:02.781977 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12707 13:59:02.788758 Opened dev<8>[ 27.416430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12708 13:59:02.789038 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12710 13:59:02.791730 ice: /dev/dri/card0
12711 13:59:02.794726 No KMS driver or no outputs, pipes: 8, outputs: 0
12712 13:59:02.799119 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12713 13:59:02.806232 <14>[ 27.437173] [IGT] kms_vblank: executing
12714 13:59:02.812718 IGT-Version: 1.2<14>[ 27.441969] [IGT] kms_vblank: exiting, ret=77
12715 13:59:02.815738 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12716 13:59:02.825475 Opened dev<8>[ 27.452125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12717 13:59:02.825579 ice: /dev/dri/card0
12718 13:59:02.825843 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12720 13:59:02.828939 No KMS driver or no outputs, pipes: 8, outputs: 0
12721 13:59:02.835752 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12722 13:59:02.842303 <14>[ 27.472845] [IGT] kms_vblank: executing
12723 13:59:02.845828 IGT-Version: 1.2<14>[ 27.477664] [IGT] kms_vblank: exiting, ret=77
12724 13:59:02.852237 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12725 13:59:02.859183 Opened dev<8>[ 27.487895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12726 13:59:02.859437 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12728 13:59:02.862118 ice: /dev/dri/card0
12729 13:59:02.865631 No KMS driver or no outputs, pipes: 8, outputs: 0
12730 13:59:02.872399 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12731 13:59:02.875397 <14>[ 27.508517] [IGT] kms_vblank: executing
12732 13:59:02.882292 IGT-Version: 1.2<14>[ 27.513239] [IGT] kms_vblank: exiting, ret=77
12733 13:59:02.888634 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12734 13:59:02.895085 Opened dev<8>[ 27.523484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12735 13:59:02.895379 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12737 13:59:02.898642 ice: /dev/dri/card0
12738 13:59:02.901964 No KMS driver or no outputs, pipes: 8, outputs: 0
12739 13:59:02.905359 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12740 13:59:02.912584 <14>[ 27.544031] [IGT] kms_vblank: executing
12741 13:59:02.919664 IGT-Version: 1.2<14>[ 27.548746] [IGT] kms_vblank: exiting, ret=77
12742 13:59:02.922781 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12743 13:59:02.932666 Opened dev<8>[ 27.558917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12744 13:59:02.932747 ice: /dev/dri/card0
12745 13:59:02.932983 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12747 13:59:02.939080 No KMS driver or no outputs, pipes: 8, outputs: 0
12748 13:59:02.942499 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12749 13:59:02.949360 <14>[ 27.579958] [IGT] kms_vblank: executing
12750 13:59:02.955863 IGT-Version: 1.2<14>[ 27.584708] [IGT] kms_vblank: exiting, ret=77
12751 13:59:02.958802 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12752 13:59:02.965873 Opened dev<8>[ 27.594758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12753 13:59:02.966126 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12755 13:59:02.969267 ice: /dev/dri/card0
12756 13:59:02.972434 No KMS driver or no outputs, pipes: 8, outputs: 0
12757 13:59:02.980116 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12758 13:59:02.982255 <14>[ 27.615238] [IGT] kms_vblank: executing
12759 13:59:02.989024 IGT-Version: 1.2<14>[ 27.619941] [IGT] kms_vblank: exiting, ret=77
12760 13:59:02.995281 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12761 13:59:03.002532 Opened dev<8>[ 27.630286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12762 13:59:03.002784 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12764 13:59:03.005459 ice: /dev/dri/card0
12765 13:59:03.009200 No KMS driver or no outputs, pipes: 8, outputs: 0
12766 13:59:03.015616 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12767 13:59:03.019418 <14>[ 27.651093] [IGT] kms_vblank: executing
12768 13:59:03.025064 IGT-Version: 1.2<14>[ 27.655826] [IGT] kms_vblank: exiting, ret=77
12769 13:59:03.028496 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12770 13:59:03.038359 Opened dev<8>[ 27.666127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12771 13:59:03.038661 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12773 13:59:03.042156 ice: /dev/dri/card0
12774 13:59:03.046022 No KMS driver or no outputs, pipes: 8, outputs: 0
12775 13:59:03.048610 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12776 13:59:03.055765 <14>[ 27.687147] [IGT] kms_vblank: executing
12777 13:59:03.062775 IGT-Version: 1.2<14>[ 27.691854] [IGT] kms_vblank: exiting, ret=77
12778 13:59:03.065768 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12779 13:59:03.075636 Opened dev<8>[ 27.702262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12780 13:59:03.075717 ice: /dev/dri/card0
12781 13:59:03.075951 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12783 13:59:03.082151 No KMS driver or no outputs, pipes: 8, outputs: 0
12784 13:59:03.086018 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12785 13:59:03.092214 <14>[ 27.723743] [IGT] kms_vblank: executing
12786 13:59:03.098962 IGT-Version: 1.2<14>[ 27.728451] [IGT] kms_vblank: exiting, ret=77
12787 13:59:03.102321 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12788 13:59:03.109092 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12790 13:59:03.112480 Opened dev<8>[ 27.738564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12791 13:59:03.112563 ice: /dev/dri/card0
12792 13:59:03.115343 No KMS driver or no outputs, pipes: 8, outputs: 0
12793 13:59:03.124253 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12794 13:59:03.125658 <14>[ 27.758996] [IGT] kms_vblank: executing
12795 13:59:03.131842 IGT-Version: 1.2<14>[ 27.763719] [IGT] kms_vblank: exiting, ret=77
12796 13:59:03.138576 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12797 13:59:03.145472 Opened dev<8>[ 27.774115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12798 13:59:03.145725 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12800 13:59:03.148761 ice: /dev/dri/card0
12801 13:59:03.152505 No KMS driver or no outputs, pipes: 8, outputs: 0
12802 13:59:03.158778 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12803 13:59:03.161948 <14>[ 27.794703] [IGT] kms_vblank: executing
12804 13:59:03.168914 IGT-Version: 1.2<14>[ 27.799408] [IGT] kms_vblank: exiting, ret=77
12805 13:59:03.175020 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12806 13:59:03.181655 Opened dev<8>[ 27.809873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12807 13:59:03.181906 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12809 13:59:03.185281 ice: /dev/dri/card0
12810 13:59:03.188847 No KMS driver or no outputs, pipes: 8, outputs: 0
12811 13:59:03.191745 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12812 13:59:03.199030 <14>[ 27.830120] [IGT] kms_vblank: executing
12813 13:59:03.205793 IGT-Version: 1.2<14>[ 27.834964] [IGT] kms_vblank: exiting, ret=77
12814 13:59:03.208498 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12815 13:59:03.218508 Opened dev<8>[ 27.845273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12816 13:59:03.218589 ice: /dev/dri/card0
12817 13:59:03.218825 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12819 13:59:03.225626 No KMS driver or no outputs, pipes: 8, outputs: 0
12820 13:59:03.228616 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12821 13:59:03.236050 <14>[ 27.866549] [IGT] kms_vblank: executing
12822 13:59:03.242035 IGT-Version: 1.2<14>[ 27.871275] [IGT] kms_vblank: exiting, ret=77
12823 13:59:03.245335 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12824 13:59:03.252058 Opened dev<8>[ 27.881544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12825 13:59:03.252338 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12827 13:59:03.255573 ice: /dev/dri/card0
12828 13:59:03.258591 No KMS driver or no outputs, pipes: 8, outputs: 0
12829 13:59:03.265401 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12830 13:59:03.268499 <14>[ 27.902134] [IGT] kms_vblank: executing
12831 13:59:03.275017 IGT-Version: 1.2<14>[ 27.906998] [IGT] kms_vblank: exiting, ret=77
12832 13:59:03.281875 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12833 13:59:03.288364 Opened dev<8>[ 27.917133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12834 13:59:03.288616 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12836 13:59:03.291637 ice: /dev/dri/card0
12837 13:59:03.295111 No KMS driver or no outputs, pipes: 8, outputs: 0
12838 13:59:03.301767 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12839 13:59:03.305393 <14>[ 27.938107] [IGT] kms_vblank: executing
12840 13:59:03.311899 IGT-Version: 1.2<14>[ 27.942813] [IGT] kms_vblank: exiting, ret=77
12841 13:59:03.318623 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12842 13:59:03.324930 Opened dev<8>[ 27.952995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12843 13:59:03.325181 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12845 13:59:03.328434 ice: /dev/dri/card0
12846 13:59:03.331579 No KMS driver or no outputs, pipes: 8, outputs: 0
12847 13:59:03.338818 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12848 13:59:03.342697 <14>[ 27.973992] [IGT] kms_vblank: executing
12849 13:59:03.348248 IGT-Version: 1.2<14>[ 27.978706] [IGT] kms_vblank: exiting, ret=77
12850 13:59:03.351920 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12851 13:59:03.361830 Opened dev<8>[ 27.988878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12852 13:59:03.362082 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12854 13:59:03.365116 ice: /dev/dri/card0
12855 13:59:03.368561 No KMS driver or no outputs, pipes: 8, outputs: 0
12856 13:59:03.374733 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12857 13:59:03.378617 <14>[ 28.010562] [IGT] kms_vblank: executing
12858 13:59:03.384894 IGT-Version: 1.2<14>[ 28.015304] [IGT] kms_vblank: exiting, ret=77
12859 13:59:03.388294 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12860 13:59:03.398126 Opened dev<8>[ 28.025596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12861 13:59:03.398377 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12863 13:59:03.401946 ice: /dev/dri/card0
12864 13:59:03.405098 No KMS driver or no outputs, pipes: 8, outputs: 0
12865 13:59:03.408273 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12866 13:59:03.415825 <14>[ 28.046963] [IGT] kms_vblank: executing
12867 13:59:03.422581 IGT-Version: 1.2<14>[ 28.051680] [IGT] kms_vblank: exiting, ret=77
12868 13:59:03.425586 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12869 13:59:03.435548 Opened dev<8>[ 28.062031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12870 13:59:03.435798 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12872 13:59:03.438866 ice: /dev/dri/card0
12873 13:59:03.441991 No KMS driver or no outputs, pipes: 8, outputs: 0
12874 13:59:03.448753 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12875 13:59:03.452025 <14>[ 28.083639] [IGT] kms_vblank: executing
12876 13:59:03.458648 IGT-Version: 1.2<14>[ 28.088411] [IGT] kms_vblank: exiting, ret=77
12877 13:59:03.462035 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12878 13:59:03.471891 Opened dev<8>[ 28.098548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12879 13:59:03.472144 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12881 13:59:03.475506 ice: /dev/dri/card0
12882 13:59:03.478363 No KMS driver or no outputs, pipes: 8, outputs: 0
12883 13:59:03.485519 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12884 13:59:03.488514 <14>[ 28.120030] [IGT] kms_vblank: executing
12885 13:59:03.494974 IGT-Version: 1.2<14>[ 28.124913] [IGT] kms_vblank: exiting, ret=77
12886 13:59:03.498617 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12887 13:59:03.508838 Opened dev<8>[ 28.135216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12888 13:59:03.509091 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12890 13:59:03.511886 ice: /dev/dri/card0
12891 13:59:03.515398 No KMS driver or no outputs, pipes: 8, outputs: 0
12892 13:59:03.522163 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12893 13:59:03.525116 <14>[ 28.156882] [IGT] kms_vblank: executing
12894 13:59:03.531809 IGT-Version: 1.2<14>[ 28.162135] [IGT] kms_vblank: exiting, ret=77
12895 13:59:03.535109 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12896 13:59:03.544977 Opened dev<8>[ 28.172450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12897 13:59:03.545230 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12899 13:59:03.548355 ice: /dev/dri/card0
12900 13:59:03.551442 No KMS driver or no outputs, pipes: 8, outputs: 0
12901 13:59:03.558180 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12902 13:59:03.566369 <14>[ 28.197432] [IGT] kms_vblank: executing
12903 13:59:03.572970 IGT-Version: 1.2<14>[ 28.202152] [IGT] kms_vblank: exiting, ret=77
12904 13:59:03.575844 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12905 13:59:03.586030 Opened dev<8>[ 28.212334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12906 13:59:03.586112 ice: /dev/dri/card0
12907 13:59:03.586346 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12909 13:59:03.592960 No KMS driver or no outputs, pipes: 8, outputs: 0
12910 13:59:03.596203 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12911 13:59:03.602859 <14>[ 28.234139] [IGT] kms_vblank: executing
12912 13:59:03.609080 IGT-Version: 1.2<14>[ 28.238898] [IGT] kms_vblank: exiting, ret=77
12913 13:59:03.612861 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12914 13:59:03.622715 Opened dev<8>[ 28.248953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12915 13:59:03.622966 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12917 13:59:03.626535 ice: /dev/dri/card0
12918 13:59:03.629611 No KMS driver or no outputs, pipes: 8, outputs: 0
12919 13:59:03.635796 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12920 13:59:03.638937 <14>[ 28.271311] [IGT] kms_vblank: executing
12921 13:59:03.645512 IGT-Version: 1.2<14>[ 28.276218] [IGT] kms_vblank: exiting, ret=77
12922 13:59:03.648975 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12923 13:59:03.659325 Opened dev<8>[ 28.286281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12924 13:59:03.659575 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12926 13:59:03.662155 ice: /dev/dri/card0
12927 13:59:03.665965 No KMS driver or no outputs, pipes: 8, outputs: 0
12928 13:59:03.672890 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12929 13:59:03.676183 <14>[ 28.307868] [IGT] kms_vblank: executing
12930 13:59:03.682237 IGT-Version: 1.2<14>[ 28.313218] [IGT] kms_vblank: exiting, ret=77
12931 13:59:03.685682 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12932 13:59:03.695911 Opened dev<8>[ 28.323486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12933 13:59:03.696162 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12935 13:59:03.699559 ice: /dev/dri/card0
12936 13:59:03.702356 No KMS driver or no outputs, pipes: 8, outputs: 0
12937 13:59:03.705588 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12938 13:59:03.713174 <14>[ 28.344569] [IGT] kms_vblank: executing
12939 13:59:03.719745 IGT-Version: 1.2<14>[ 28.349357] [IGT] kms_vblank: exiting, ret=77
12940 13:59:03.722870 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12941 13:59:03.730262 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12943 13:59:03.732867 Opened dev<8>[ 28.359458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12944 13:59:03.732948 ice: /dev/dri/card0
12945 13:59:03.736250 No KMS driver or no outputs, pipes: 8, outputs: 0
12946 13:59:03.742713 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12947 13:59:03.749732 <14>[ 28.380242] [IGT] kms_vblank: executing
12948 13:59:03.753369 IGT-Version: 1.2<14>[ 28.384976] [IGT] kms_vblank: exiting, ret=77
12949 13:59:03.759670 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12950 13:59:03.766221 Opened dev<8>[ 28.395352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12951 13:59:03.766522 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12953 13:59:03.770002 ice: /dev/dri/card0
12954 13:59:03.772748 No KMS driver or no outputs, pipes: 8, outputs: 0
12955 13:59:03.779783 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12956 13:59:03.782712 <14>[ 28.416534] [IGT] kms_vblank: executing
12957 13:59:03.789636 IGT-Version: 1.2<14>[ 28.421418] [IGT] kms_vblank: exiting, ret=77
12958 13:59:03.796675 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12959 13:59:03.803100 Opened dev<8>[ 28.431598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12960 13:59:03.803358 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12962 13:59:03.806096 ice: /dev/dri/card0
12963 13:59:03.809516 No KMS driver or no outputs, pipes: 8, outputs: 0
12964 13:59:03.816157 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12965 13:59:03.819498 <14>[ 28.452302] [IGT] kms_vblank: executing
12966 13:59:03.826247 IGT-Version: 1.2<14>[ 28.457062] [IGT] kms_vblank: exiting, ret=77
12967 13:59:03.833113 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12968 13:59:03.839131 Opened dev<8>[ 28.467304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12969 13:59:03.839404 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12971 13:59:03.842519 ice: /dev/dri/card0
12972 13:59:03.846306 No KMS driver or no outputs, pipes: 8, outputs: 0
12973 13:59:03.852437 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12974 13:59:03.856542 <14>[ 28.487912] [IGT] kms_vblank: executing
12975 13:59:03.862432 IGT-Version: 1.2<14>[ 28.492693] [IGT] kms_vblank: exiting, ret=77
12976 13:59:03.865699 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12977 13:59:03.875801 Opened dev<8>[ 28.503003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12978 13:59:03.875881 ice: /dev/dri/card0
12979 13:59:03.876114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12981 13:59:03.882866 No KMS driver or no outputs, pipes: 8, outputs: 0
12982 13:59:03.885774 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12983 13:59:03.892383 <14>[ 28.523254] [IGT] kms_vblank: executing
12984 13:59:03.895664 IGT-Version: 1.2<14>[ 28.528064] [IGT] kms_vblank: exiting, ret=77
12985 13:59:03.902208 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12986 13:59:03.909170 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12988 13:59:03.911942 Opened dev<8>[ 28.538446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12989 13:59:03.912023 ice: /dev/dri/card0
12990 13:59:03.915516 No KMS driver or no outputs, pipes: 8, outputs: 0
12991 13:59:03.922225 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12992 13:59:03.925403 <14>[ 28.559009] [IGT] kms_vblank: executing
12993 13:59:03.932264 IGT-Version: 1.2<14>[ 28.563821] [IGT] kms_vblank: exiting, ret=77
12994 13:59:03.938538 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12995 13:59:03.945578 Opened dev<8>[ 28.574320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12996 13:59:03.945830 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12998 13:59:03.948835 ice: /dev/dri/card0
12999 13:59:03.952271 No KMS driver or no outputs, pipes: 8, outputs: 0
13000 13:59:03.958788 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
13001 13:59:03.962048 <14>[ 28.595120] [IGT] kms_vblank: executing
13002 13:59:03.968754 IGT-Version: 1.2<14>[ 28.599854] [IGT] kms_vblank: exiting, ret=77
13003 13:59:03.975625 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13004 13:59:03.981679 Opened dev<8>[ 28.610305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
13005 13:59:03.981930 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
13007 13:59:03.985613 ice: /dev/dri/card0
13008 13:59:03.988333 No KMS driver or no outputs, pipes: 8, outputs: 0
13009 13:59:03.995681 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
13010 13:59:03.998337 <14>[ 28.631518] [IGT] kms_vblank: executing
13011 13:59:04.004921 IGT-Version: 1.2<14>[ 28.636316] [IGT] kms_vblank: exiting, ret=77
13012 13:59:04.012212 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13013 13:59:04.018436 Opened dev<8>[ 28.646776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
13014 13:59:04.018712 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
13016 13:59:04.021920 ice: /dev/dri/card0
13017 13:59:04.025255 No KMS driver or no outputs, pipes: 8, outputs: 0
13018 13:59:04.028791 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
13019 13:59:04.035906 <14>[ 28.666734] [IGT] kms_vblank: executing
13020 13:59:04.042036 IGT-Version: 1.2<14>[ 28.671488] [IGT] kms_vblank: exiting, ret=77
13021 13:59:04.045029 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13022 13:59:04.055089 Opened dev<8>[ 28.682099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
13023 13:59:04.055170 ice: /dev/dri/card0
13024 13:59:04.055403 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
13026 13:59:04.061674 No KMS driver or no outputs, pipes: 8, outputs: 0
13027 13:59:04.064974 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
13028 13:59:04.071652 <14>[ 28.702558] [IGT] kms_vblank: executing
13029 13:59:04.075251 IGT-Version: 1.2<14>[ 28.707258] [IGT] kms_vblank: exiting, ret=77
13030 13:59:04.081777 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13031 13:59:04.088314 Opened dev<8>[ 28.717855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
13032 13:59:04.088566 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
13034 13:59:04.091619 ice: /dev/dri/card0
13035 13:59:04.095144 No KMS driver or no outputs, pipes: 8, outputs: 0
13036 13:59:04.101747 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
13037 13:59:04.105119 <14>[ 28.738501] [IGT] kms_vblank: executing
13038 13:59:04.111782 IGT-Version: 1.2<14>[ 28.743285] [IGT] kms_vblank: exiting, ret=77
13039 13:59:04.118286 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13040 13:59:04.125054 Opened dev<8>[ 28.753742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
13041 13:59:04.125307 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
13043 13:59:04.128450 ice: /dev/dri/card0
13044 13:59:04.131947 No KMS driver or no outputs, pipes: 8, outputs: 0
13045 13:59:04.138246 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
13046 13:59:04.141620 <14>[ 28.774462] [IGT] kms_vblank: executing
13047 13:59:04.148241 IGT-Version: 1.2<14>[ 28.779196] [IGT] kms_vblank: exiting, ret=77
13048 13:59:04.151723 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13049 13:59:04.161319 Opened dev<8>[ 28.789741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
13050 13:59:04.161400 ice: /dev/dri/card0
13051 13:59:04.161635 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
13053 13:59:04.168031 No KMS driver or no outputs, pipes: 8, outputs: 0
13054 13:59:04.171207 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
13055 13:59:04.179082 <14>[ 28.810011] [IGT] kms_vblank: executing
13056 13:59:04.185190 IGT-Version: 1.2<14>[ 28.814737] [IGT] kms_vblank: exiting, ret=77
13057 13:59:04.188723 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13058 13:59:04.198459 Opened dev<8>[ 28.824868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
13059 13:59:04.198542 ice: /dev/dri/card0
13060 13:59:04.198777 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
13062 13:59:04.204936 No KMS driver or no outputs, pipes: 8, outputs: 0
13063 13:59:04.208450 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
13064 13:59:04.215333 <14>[ 28.846097] [IGT] kms_vblank: executing
13065 13:59:04.222318 IGT-Version: 1.2<14>[ 28.850940] [IGT] kms_vblank: exiting, ret=77
13066 13:59:04.224878 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13067 13:59:04.234687 Opened dev<8>[ 28.861160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
13068 13:59:04.234770 ice: /dev/dri/card0
13069 13:59:04.235004 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
13071 13:59:04.241618 No KMS driver or no outputs, pipes: 8, outputs: 0
13072 13:59:04.244574 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
13073 13:59:04.251318 <14>[ 28.882257] [IGT] kms_vblank: executing
13074 13:59:04.254469 IGT-Version: 1.2<14>[ 28.886969] [IGT] kms_vblank: exiting, ret=77
13075 13:59:04.261274 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13076 13:59:04.264369 Opened device: /dev/dri/card0
13077 13:59:04.267667 No KMS driver or no outputs, pipes: 8, outputs: 0
13078 13:59:04.274773 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13079 13:59:04.281336 <8>[ 28.909600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
13080 13:59:04.281589 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13082 13:59:04.312302 <14>[ 28.943863] [IGT] kms_vblank: executing
13083 13:59:04.319078 IGT-Version: 1.2<14>[ 28.949071] [IGT] kms_vblank: exiting, ret=77
13084 13:59:04.322205 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13085 13:59:04.332510 Opened device: /dev/dri/ca<8>[ 28.960321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13086 13:59:04.332592 rd0
13087 13:59:04.332828 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13089 13:59:04.338827 No KMS driver or no outputs, pipes: 8, outputs: 0
13090 13:59:04.342672 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13091 13:59:04.351514 <14>[ 28.982529] [IGT] kms_vblank: executing
13092 13:59:04.357742 IGT-Version: 1.2<14>[ 28.987250] [IGT] kms_vblank: exiting, ret=77
13093 13:59:04.361056 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13094 13:59:04.371032 Opened device: /dev/dri/ca<8>[ 28.999721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13095 13:59:04.371113 rd0
13096 13:59:04.371348 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13098 13:59:04.377974 No KMS driver or no outputs, pipes: 8, outputs: 0
13099 13:59:04.381257 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13100 13:59:04.399644 <14>[ 29.031152] [IGT] kms_vblank: executing
13101 13:59:04.406162 IGT-Version: 1.2<14>[ 29.036330] [IGT] kms_vblank: exiting, ret=77
13102 13:59:04.409623 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13103 13:59:04.420050 Opened device: /dev/dri/ca<8>[ 29.047926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13104 13:59:04.420305 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13106 13:59:04.422909 rd0
13107 13:59:04.426434 No KMS driver or no outputs, pipes: 8, outputs: 0
13108 13:59:04.433009 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13109 13:59:04.435902 <14>[ 29.069741] [IGT] kms_vblank: executing
13110 13:59:04.442865 IGT-Version: 1.2<14>[ 29.074455] [IGT] kms_vblank: exiting, ret=77
13111 13:59:04.449808 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13112 13:59:04.459294 Opened dev<8>[ 29.084925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13113 13:59:04.459377 ice: /dev/dri/card0
13114 13:59:04.459613 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13116 13:59:04.465724 No KMS driver or no outputs, pipes: 8, outputs: 0
13117 13:59:04.469109 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13118 13:59:04.475914 <14>[ 29.107281] [IGT] kms_vblank: executing
13119 13:59:04.482523 IGT-Version: 1.2<14>[ 29.112015] [IGT] kms_vblank: exiting, ret=77
13120 13:59:04.486080 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13121 13:59:04.495902 Opened dev<8>[ 29.122292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13122 13:59:04.495985 ice: /dev/dri/card0
13123 13:59:04.496221 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13125 13:59:04.502468 No KMS driver or no outputs, pipes: 8, outputs: 0
13126 13:59:04.505743 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13127 13:59:04.512125 <14>[ 29.143666] [IGT] kms_vblank: executing
13128 13:59:04.519055 IGT-Version: 1.2<14>[ 29.148587] [IGT] kms_vblank: exiting, ret=77
13129 13:59:04.522312 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13130 13:59:04.532300 Opened dev<8>[ 29.158901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13131 13:59:04.532383 ice: /dev/dri/card0
13132 13:59:04.532618 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13134 13:59:04.538826 No KMS driver or no outputs, pipes: 8, outputs: 0
13135 13:59:04.542435 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13136 13:59:04.549433 <14>[ 29.180418] [IGT] kms_vblank: executing
13137 13:59:04.555716 IGT-Version: 1.2<14>[ 29.185175] [IGT] kms_vblank: exiting, ret=77
13138 13:59:04.558642 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13139 13:59:04.569313 Opened dev<8>[ 29.195406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13140 13:59:04.569567 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13142 13:59:04.572635 ice: /dev/dri/card0
13143 13:59:04.575335 No KMS driver or no outputs, pipes: 8, outputs: 0
13144 13:59:04.581925 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13145 13:59:04.585764 <14>[ 29.217238] [IGT] kms_vblank: executing
13146 13:59:04.591765 IGT-Version: 1.2<14>[ 29.222411] [IGT] kms_vblank: exiting, ret=77
13147 13:59:04.594979 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13148 13:59:04.605642 Opened dev<8>[ 29.232742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13149 13:59:04.605896 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13151 13:59:04.609015 ice: /dev/dri/card0
13152 13:59:04.611829 No KMS driver or no outputs, pipes: 8, outputs: 0
13153 13:59:04.618679 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13154 13:59:04.621690 <14>[ 29.254441] [IGT] kms_vblank: executing
13155 13:59:04.628527 IGT-Version: 1.2<14>[ 29.259422] [IGT] kms_vblank: exiting, ret=77
13156 13:59:04.631906 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13157 13:59:04.641839 Opened dev<8>[ 29.270034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13158 13:59:04.642092 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13160 13:59:04.645334 ice: /dev/dri/card0
13161 13:59:04.648725 No KMS driver or no outputs, pipes: 8, outputs: 0
13162 13:59:04.651557 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13163 13:59:04.658846 <14>[ 29.290255] [IGT] kms_vblank: executing
13164 13:59:04.665168 IGT-Version: 1.2<14>[ 29.294997] [IGT] kms_vblank: exiting, ret=77
13165 13:59:04.668503 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13166 13:59:04.678458 Opened dev<8>[ 29.305328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13167 13:59:04.678541 ice: /dev/dri/card0
13168 13:59:04.678776 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13170 13:59:04.682400 No KMS driver or no outputs, pipes: 8, outputs: 0
13171 13:59:04.688809 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13172 13:59:04.694808 <14>[ 29.325935] [IGT] kms_vblank: executing
13173 13:59:04.698697 IGT-Version: 1.2<14>[ 29.330623] [IGT] kms_vblank: exiting, ret=77
13174 13:59:04.704893 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13175 13:59:04.711689 Opened dev<8>[ 29.340921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13176 13:59:04.711968 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13178 13:59:04.714935 ice: /dev/dri/card0
13179 13:59:04.718151 No KMS driver or no outputs, pipes: 8, outputs: 0
13180 13:59:04.724721 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13181 13:59:04.728191 <14>[ 29.362121] [IGT] kms_vblank: executing
13182 13:59:04.734813 IGT-Version: 1.2<14>[ 29.366873] [IGT] kms_vblank: exiting, ret=77
13183 13:59:04.741437 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13184 13:59:04.748199 Opened dev<8>[ 29.376923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13185 13:59:04.748452 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13187 13:59:04.751796 ice: /dev/dri/card0
13188 13:59:04.755071 No KMS driver or no outputs, pipes: 8, outputs: 0
13189 13:59:04.761470 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13190 13:59:04.765216 <14>[ 29.398181] [IGT] kms_vblank: executing
13191 13:59:04.771290 IGT-Version: 1.2<14>[ 29.403004] [IGT] kms_vblank: exiting, ret=77
13192 13:59:04.778145 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13193 13:59:04.784818 Opened dev<8>[ 29.413113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13194 13:59:04.785069 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13196 13:59:04.788002 ice: /dev/dri/card0
13197 13:59:04.791312 No KMS driver or no outputs, pipes: 8, outputs: 0
13198 13:59:04.797800 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13199 13:59:04.801502 <14>[ 29.434069] [IGT] kms_vblank: executing
13200 13:59:04.808290 IGT-Version: 1.2<14>[ 29.438768] [IGT] kms_vblank: exiting, ret=77
13201 13:59:04.811630 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13202 13:59:04.821284 Opened dev<8>[ 29.449087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13203 13:59:04.821383 ice: /dev/dri/card0
13204 13:59:04.821633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13206 13:59:04.827969 No KMS driver or no outputs, pipes: 8, outputs: 0
13207 13:59:04.831380 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13208 13:59:04.838011 <14>[ 29.469431] [IGT] kms_vblank: executing
13209 13:59:04.844896 IGT-Version: 1.2<14>[ 29.474168] [IGT] kms_vblank: exiting, ret=77
13210 13:59:04.848016 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13211 13:59:04.858228 Opened dev<8>[ 29.484551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13212 13:59:04.858311 ice: /dev/dri/card0
13213 13:59:04.858547 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13215 13:59:04.864410 No KMS driver or no outputs, pipes: 8, outputs: 0
13216 13:59:04.868497 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13217 13:59:04.874586 <14>[ 29.505655] [IGT] kms_vblank: executing
13218 13:59:04.881031 IGT-Version: 1.2<14>[ 29.510383] [IGT] kms_vblank: exiting, ret=77
13219 13:59:04.884374 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13220 13:59:04.894141 Opened dev<8>[ 29.520591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13221 13:59:04.894223 ice: /dev/dri/card0
13222 13:59:04.894437 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13224 13:59:04.901058 No KMS driver or no outputs, pipes: 8, outputs: 0
13225 13:59:04.904220 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13226 13:59:04.911010 <14>[ 29.541809] [IGT] kms_vblank: executing
13227 13:59:04.914107 IGT-Version: 1.2<14>[ 29.546565] [IGT] kms_vblank: exiting, ret=77
13228 13:59:04.920616 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13229 13:59:04.930860 Opened dev<8>[ 29.556996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13230 13:59:04.930942 ice: /dev/dri/card0
13231 13:59:04.931176 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13233 13:59:04.937396 No KMS driver or no outputs, pipes: 8, outputs: 0
13234 13:59:04.940582 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13235 13:59:04.947256 <14>[ 29.578138] [IGT] kms_vblank: executing
13236 13:59:04.951156 IGT-Version: 1.2<14>[ 29.582847] [IGT] kms_vblank: exiting, ret=77
13237 13:59:04.957322 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13238 13:59:04.963825 Opened dev<8>[ 29.593040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13239 13:59:04.964081 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13241 13:59:04.967167 ice: /dev/dri/card0
13242 13:59:04.970733 No KMS driver or no outputs, pipes: 8, outputs: 0
13243 13:59:04.973918 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13244 13:59:04.982647 <14>[ 29.613721] [IGT] kms_vblank: executing
13245 13:59:04.988978 IGT-Version: 1.2<14>[ 29.618496] [IGT] kms_vblank: exiting, ret=77
13246 13:59:04.992009 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13247 13:59:05.002221 Opened dev<8>[ 29.628754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13248 13:59:05.002304 ice: /dev/dri/card0
13249 13:59:05.002540 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13251 13:59:05.008923 No KMS driver or no outputs, pipes: 8, outputs: 0
13252 13:59:05.012218 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13253 13:59:05.018497 <14>[ 29.649771] [IGT] kms_vblank: executing
13254 13:59:05.025379 IGT-Version: 1.2<14>[ 29.654561] [IGT] kms_vblank: exiting, ret=77
13255 13:59:05.028717 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13256 13:59:05.035260 Opened dev<8>[ 29.664721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13257 13:59:05.035513 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13259 13:59:05.038682 ice: /dev/dri/card0
13260 13:59:05.041970 No KMS driver or no outputs, pipes: 8, outputs: 0
13261 13:59:05.048640 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13262 13:59:05.051456 <14>[ 29.685462] [IGT] kms_vblank: executing
13263 13:59:05.058675 IGT-Version: 1.2<14>[ 29.690248] [IGT] kms_vblank: exiting, ret=77
13264 13:59:05.065110 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13265 13:59:05.071548 Opened dev<8>[ 29.700424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13266 13:59:05.071801 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13268 13:59:05.075153 ice: /dev/dri/card0
13269 13:59:05.078349 No KMS driver or no outputs, pipes: 8, outputs: 0
13270 13:59:05.085123 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13271 13:59:05.088301 <14>[ 29.721372] [IGT] kms_vblank: executing
13272 13:59:05.095831 IGT-Version: 1.2<14>[ 29.726175] [IGT] kms_vblank: exiting, ret=77
13273 13:59:05.101426 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13274 13:59:05.108466 Opened dev<8>[ 29.736522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13275 13:59:05.108720 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13277 13:59:05.111410 ice: /dev/dri/card0
13278 13:59:05.114778 No KMS driver or no outputs, pipes: 8, outputs: 0
13279 13:59:05.118132 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13280 13:59:05.125053 <14>[ 29.756543] [IGT] kms_vblank: executing
13281 13:59:05.131641 IGT-Version: 1.2<14>[ 29.761331] [IGT] kms_vblank: exiting, ret=77
13282 13:59:05.134854 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13283 13:59:05.144555 Opened dev<8>[ 29.771667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13284 13:59:05.144638 ice: /dev/dri/card0
13285 13:59:05.144874 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13287 13:59:05.151819 No KMS driver or no outputs, pipes: 8, outputs: 0
13288 13:59:05.154921 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13289 13:59:05.161359 <14>[ 29.792394] [IGT] kms_vblank: executing
13290 13:59:05.164990 IGT-Version: 1.2<14>[ 29.797121] [IGT] kms_vblank: exiting, ret=77
13291 13:59:05.171434 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13292 13:59:05.178309 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13294 13:59:05.181294 Opened dev<8>[ 29.807503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13295 13:59:05.181376 ice: /dev/dri/card0
13296 13:59:05.185165 No KMS driver or no outputs, pipes: 8, outputs: 0
13297 13:59:05.191376 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13298 13:59:05.194739 <14>[ 29.828046] [IGT] kms_vblank: executing
13299 13:59:05.201382 IGT-Version: 1.2<14>[ 29.832756] [IGT] kms_vblank: exiting, ret=77
13300 13:59:05.208078 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13301 13:59:05.214605 Opened dev<8>[ 29.843273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13302 13:59:05.214859 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13304 13:59:05.218040 ice: /dev/dri/card0
13305 13:59:05.221516 No KMS driver or no outputs, pipes: 8, outputs: 0
13306 13:59:05.227844 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13307 13:59:05.231374 <14>[ 29.864288] [IGT] kms_vblank: executing
13308 13:59:05.238104 IGT-Version: 1.2<14>[ 29.869027] [IGT] kms_vblank: exiting, ret=77
13309 13:59:05.241849 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13310 13:59:05.251637 Opened dev<8>[ 29.879175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13311 13:59:05.251893 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13313 13:59:05.254625 ice: /dev/dri/card0
13314 13:59:05.258058 No KMS driver or no outputs, pipes: 8, outputs: 0
13315 13:59:05.264583 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13316 13:59:05.280188 <14>[ 29.911930] [IGT] kms_vblank: executing
13317 13:59:05.287010 IGT-Version: 1.2<14>[ 29.916965] [IGT] kms_vblank: exiting, ret=77
13318 13:59:05.290660 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13319 13:59:05.299933 Opened device: /dev/dri/ca<8>[ 29.928064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13320 13:59:05.300186 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13322 13:59:05.303589 rd0
13323 13:59:05.306703 No KMS driver or no outputs, pipes: 8, outputs: 0
13324 13:59:05.313317 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13325 13:59:05.316508 <14>[ 29.950456] [IGT] kms_vblank: executing
13326 13:59:05.323076 IGT-Version: 1.2<14>[ 29.955226] [IGT] kms_vblank: exiting, ret=77
13327 13:59:05.329831 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13328 13:59:05.340448 Opened dev<8>[ 29.965762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13329 13:59:05.340529 ice: /dev/dri/card0
13330 13:59:05.340763 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13332 13:59:05.343538 No KMS driver or no outputs, pipes: 8, outputs: 0
13333 13:59:05.350033 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13334 13:59:05.356548 <14>[ 29.987564] [IGT] kms_vblank: executing
13335 13:59:05.360217 IGT-Version: 1.2<14>[ 29.992362] [IGT] kms_vblank: exiting, ret=77
13336 13:59:05.366829 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13337 13:59:05.377014 Opened dev<8>[ 30.002725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13338 13:59:05.377095 ice: /dev/dri/card0
13339 13:59:05.377329 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13341 13:59:05.383185 No KMS driver or no outputs, pipes: 8, outputs: 0
13342 13:59:05.389820 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13343 13:59:05.393153 <14>[ 30.024193] [IGT] kms_vblank: executing
13344 13:59:05.400138 IGT-Version: 1.2<14>[ 30.029800] [IGT] kms_vblank: exiting, ret=77
13345 13:59:05.403276 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13346 13:59:05.413030 Opened dev<8>[ 30.039942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13347 13:59:05.413283 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13349 13:59:05.416529 ice: /dev/dri/card0
13350 13:59:05.419548 No KMS driver or no outputs, pipes: 8, outputs: 0
13351 13:59:05.426555 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13352 13:59:05.433493 <14>[ 30.064843] [IGT] kms_vblank: executing
13353 13:59:05.439546 IGT-Version: 1.2<14>[ 30.069622] [IGT] kms_vblank: exiting, ret=77
13354 13:59:05.443495 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13355 13:59:05.453110 Opened dev<8>[ 30.079844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13356 13:59:05.453191 ice: /dev/dri/card0
13357 13:59:05.453428 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13359 13:59:05.459735 No KMS driver or no outputs, pipes: 8, outputs: 0
13360 13:59:05.463230 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13361 13:59:05.470013 <14>[ 30.101556] [IGT] kms_vblank: executing
13362 13:59:05.476784 IGT-Version: 1.2<14>[ 30.106267] [IGT] kms_vblank: exiting, ret=77
13363 13:59:05.479890 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13364 13:59:05.489846 Opened dev<8>[ 30.116668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13365 13:59:05.490099 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13367 13:59:05.492838 ice: /dev/dri/card0
13368 13:59:05.496428 No KMS driver or no outputs, pipes: 8, outputs: 0
13369 13:59:05.503173 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13370 13:59:05.506239 <14>[ 30.138833] [IGT] kms_vblank: executing
13371 13:59:05.513154 IGT-Version: 1.2<14>[ 30.143574] [IGT] kms_vblank: exiting, ret=77
13372 13:59:05.516514 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13373 13:59:05.526342 Opened dev<8>[ 30.153997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13374 13:59:05.526636 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13376 13:59:05.529829 ice: /dev/dri/card0
13377 13:59:05.532788 No KMS driver or no outputs, pipes: 8, outputs: 0
13378 13:59:05.539272 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13379 13:59:05.543145 <14>[ 30.175383] [IGT] kms_vblank: executing
13380 13:59:05.549894 IGT-Version: 1.2<14>[ 30.180557] [IGT] kms_vblank: exiting, ret=77
13381 13:59:05.552973 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13382 13:59:05.562825 Opened dev<8>[ 30.190765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13383 13:59:05.563077 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13385 13:59:05.566076 ice: /dev/dri/card0
13386 13:59:05.569660 No KMS driver or no outputs, pipes: 8, outputs: 0
13387 13:59:05.572641 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13388 13:59:05.580148 <14>[ 30.211555] [IGT] kms_vblank: executing
13389 13:59:05.587175 IGT-Version: 1.2<14>[ 30.216301] [IGT] kms_vblank: exiting, ret=77
13390 13:59:05.589869 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13391 13:59:05.596450 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13393 13:59:05.599892 Opened dev<8>[ 30.226762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13394 13:59:05.599977 ice: /dev/dri/card0
13395 13:59:05.603502 No KMS driver or no outputs, pipes: 8, outputs: 0
13396 13:59:05.609795 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13397 13:59:05.613171 <14>[ 30.247026] [IGT] kms_vblank: executing
13398 13:59:05.620007 IGT-Version: 1.2<14>[ 30.251780] [IGT] kms_vblank: exiting, ret=77
13399 13:59:05.626752 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13400 13:59:05.633229 Opened dev<8>[ 30.262149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13401 13:59:05.633482 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13403 13:59:05.636440 ice: /dev/dri/card0
13404 13:59:05.640136 No KMS driver or no outputs, pipes: 8, outputs: 0
13405 13:59:05.646708 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13406 13:59:05.650119 <14>[ 30.282956] [IGT] kms_vblank: executing
13407 13:59:05.656144 IGT-Version: 1.2<14>[ 30.287634] [IGT] kms_vblank: exiting, ret=77
13408 13:59:05.663436 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13409 13:59:05.669973 Opened dev<8>[ 30.298025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13410 13:59:05.670224 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13412 13:59:05.672677 ice: /dev/dri/card0
13413 13:59:05.676615 No KMS driver or no outputs, pipes: 8, outputs: 0
13414 13:59:05.679300 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13415 13:59:05.687160 <14>[ 30.318781] [IGT] kms_vblank: executing
13416 13:59:05.693491 IGT-Version: 1.2<14>[ 30.323482] [IGT] kms_vblank: exiting, ret=77
13417 13:59:05.697173 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13418 13:59:05.707018 Opened dev<8>[ 30.333937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13419 13:59:05.707099 ice: /dev/dri/card0
13420 13:59:05.707334 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13422 13:59:05.713712 No KMS driver or no outputs, pipes: 8, outputs: 0
13423 13:59:05.716950 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13424 13:59:05.723448 <14>[ 30.354769] [IGT] kms_vblank: executing
13425 13:59:05.726715 IGT-Version: 1.2<14>[ 30.359475] [IGT] kms_vblank: exiting, ret=77
13426 13:59:05.733891 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13427 13:59:05.740659 Opened dev<8>[ 30.370088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13428 13:59:05.740911 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13430 13:59:05.743856 ice: /dev/dri/card0
13431 13:59:05.746692 No KMS driver or no outputs, pipes: 8, outputs: 0
13432 13:59:05.753302 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13433 13:59:05.756830 <14>[ 30.390476] [IGT] kms_vblank: executing
13434 13:59:05.763198 IGT-Version: 1.2<14>[ 30.395282] [IGT] kms_vblank: exiting, ret=77
13435 13:59:05.770135 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13436 13:59:05.776785 Opened dev<8>[ 30.405877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13437 13:59:05.777042 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13439 13:59:05.780165 ice: /dev/dri/card0
13440 13:59:05.783052 No KMS driver or no outputs, pipes: 8, outputs: 0
13441 13:59:05.789849 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13442 13:59:05.793260 <14>[ 30.426486] [IGT] kms_vblank: executing
13443 13:59:05.799776 IGT-Version: 1.2<14>[ 30.431222] [IGT] kms_vblank: exiting, ret=77
13444 13:59:05.806839 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13445 13:59:05.812761 Opened dev<8>[ 30.441496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13446 13:59:05.813017 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13448 13:59:05.816459 ice: /dev/dri/card0
13449 13:59:05.819532 No KMS driver or no outputs, pipes: 8, outputs: 0
13450 13:59:05.826352 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13451 13:59:05.829518 <14>[ 30.462566] [IGT] kms_vblank: executing
13452 13:59:05.836231 IGT-Version: 1.2<14>[ 30.467293] [IGT] kms_vblank: exiting, ret=77
13453 13:59:05.839489 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13454 13:59:05.849739 Opened dev<8>[ 30.477772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13455 13:59:05.849991 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13457 13:59:05.852724 ice: /dev/dri/card0
13458 13:59:05.856268 No KMS driver or no outputs, pipes: 8, outputs: 0
13459 13:59:05.863025 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13460 13:59:05.866432 <14>[ 30.498835] [IGT] kms_vblank: executing
13461 13:59:05.872801 IGT-Version: 1.2<14>[ 30.503522] [IGT] kms_vblank: exiting, ret=77
13462 13:59:05.876392 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13463 13:59:05.886158 Opened dev<8>[ 30.514074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13464 13:59:05.886257 ice: /dev/dri/card0
13465 13:59:05.886494 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13467 13:59:05.892766 No KMS driver or no outputs, pipes: 8, outputs: 0
13468 13:59:05.896347 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13469 13:59:05.902598 <14>[ 30.534341] [IGT] kms_vblank: executing
13470 13:59:05.909184 IGT-Version: 1.2<14>[ 30.539104] [IGT] kms_vblank: exiting, ret=77
13471 13:59:05.912620 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13472 13:59:05.922780 Opened dev<8>[ 30.549353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13473 13:59:05.922864 ice: /dev/dri/card0
13474 13:59:05.923099 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13476 13:59:05.929511 No KMS driver or no outputs, pipes: 8, outputs: 0
13477 13:59:05.932529 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13478 13:59:05.939622 <14>[ 30.570355] [IGT] kms_vblank: executing
13479 13:59:05.942587 IGT-Version: 1.2<14>[ 30.575058] [IGT] kms_vblank: exiting, ret=77
13480 13:59:05.949596 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13481 13:59:05.956028 Opened dev<8>[ 30.585276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13482 13:59:05.956282 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13484 13:59:05.959428 ice: /dev/dri/card0
13485 13:59:05.962606 No KMS driver or no outputs, pipes: 8, outputs: 0
13486 13:59:05.969408 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13487 13:59:05.972843 <14>[ 30.606232] [IGT] kms_vblank: executing
13488 13:59:05.978924 IGT-Version: 1.2<14>[ 30.610996] [IGT] kms_vblank: exiting, ret=77
13489 13:59:05.986094 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13490 13:59:05.992455 Opened dev<8>[ 30.621149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13491 13:59:05.992708 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13493 13:59:05.995981 ice: /dev/dri/card0
13494 13:59:05.999024 No KMS driver or no outputs, pipes: 8, outputs: 0
13495 13:59:06.006024 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13496 13:59:06.009360 <14>[ 30.642540] [IGT] kms_vblank: executing
13497 13:59:06.016197 IGT-Version: 1.2<14>[ 30.647452] [IGT] kms_vblank: exiting, ret=77
13498 13:59:06.022273 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13499 13:59:06.028974 Opened dev<8>[ 30.657744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13500 13:59:06.029226 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13502 13:59:06.032944 ice: /dev/dri/card0
13503 13:59:06.036076 No KMS driver or no outputs, pipes: 8, outputs: 0
13504 13:59:06.039130 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13505 13:59:06.046586 <14>[ 30.678115] [IGT] kms_vblank: executing
13506 13:59:06.053396 IGT-Version: 1.2<14>[ 30.682832] [IGT] kms_vblank: exiting, ret=77
13507 13:59:06.056278 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13508 13:59:06.066018 Opened dev<8>[ 30.693245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13509 13:59:06.066099 ice: /dev/dri/card0
13510 13:59:06.066333 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13512 13:59:06.072584 No KMS driver or no outputs, pipes: 8, outputs: 0
13513 13:59:06.076149 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13514 13:59:06.082761 <14>[ 30.714178] [IGT] kms_vblank: executing
13515 13:59:06.090001 IGT-Version: 1.2<14>[ 30.719097] [IGT] kms_vblank: exiting, ret=77
13516 13:59:06.093015 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13517 13:59:06.102822 Opened dev<8>[ 30.729440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13518 13:59:06.102904 ice: /dev/dri/card0
13519 13:59:06.103139 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13521 13:59:06.109250 No KMS driver or no outputs, pipes: 8, outputs: 0
13522 13:59:06.112764 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13523 13:59:06.119541 <14>[ 30.750351] [IGT] kms_vblank: executing
13524 13:59:06.122504 IGT-Version: 1.2<14>[ 30.755086] [IGT] kms_vblank: exiting, ret=77
13525 13:59:06.129615 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13526 13:59:06.139351 Opened dev<8>[ 30.765201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13527 13:59:06.139433 ice: /dev/dri/card0
13528 13:59:06.139668 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13530 13:59:06.145906 No KMS driver or no outputs, pipes: 8, outputs: 0
13531 13:59:06.149292 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13532 13:59:06.155820 <14>[ 30.786951] [IGT] kms_vblank: executing
13533 13:59:06.159694 IGT-Version: 1.2<14>[ 30.791680] [IGT] kms_vblank: exiting, ret=77
13534 13:59:06.166525 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13535 13:59:06.176077 Opened dev<8>[ 30.801987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13536 13:59:06.176159 ice: /dev/dri/card0
13537 13:59:06.176393 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13539 13:59:06.179359 No KMS driver or no outputs, pipes: 8, outputs: 0
13540 13:59:06.186344 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13541 13:59:06.189350 <14>[ 30.823533] [IGT] kms_vblank: executing
13542 13:59:06.195983 IGT-Version: 1.2<14>[ 30.828299] [IGT] kms_vblank: exiting, ret=77
13543 13:59:06.202802 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13544 13:59:06.212676 Opened dev<8>[ 30.838275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13545 13:59:06.212758 ice: /dev/dri/card0
13546 13:59:06.212993 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13548 13:59:06.219242 No KMS driver or no outputs, pipes: 8, outputs: 0
13549 13:59:06.222763 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13550 13:59:06.226466 <14>[ 30.859852] [IGT] kms_vblank: executing
13551 13:59:06.232847 IGT-Version: 1.2<14>[ 30.864952] [IGT] kms_vblank: exiting, ret=77
13552 13:59:06.239184 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13553 13:59:06.242667 Opened device: /dev/dri/card0
13554 13:59:06.249403 No KMS driv<8>[ 30.877948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13555 13:59:06.249655 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13557 13:59:06.255915 er or no outputs, pipes: 8, outputs: 0
13558 13:59:06.259383 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13559 13:59:06.268529 <14>[ 30.900172] [IGT] kms_vblank: executing
13560 13:59:06.275097 IGT-Version: 1.2<14>[ 30.904926] [IGT] kms_vblank: exiting, ret=77
13561 13:59:06.278354 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13562 13:59:06.288184 Opened dev<8>[ 30.915277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13563 13:59:06.288437 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13565 13:59:06.291787 ice: /dev/dri/card0
13566 13:59:06.295296 No KMS driver or no outputs, pipes: 8, outputs: 0
13567 13:59:06.302606 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13568 13:59:06.305461 <14>[ 30.937074] [IGT] kms_vblank: executing
13569 13:59:06.311796 IGT-Version: 1.2<14>[ 30.942129] [IGT] kms_vblank: exiting, ret=77
13570 13:59:06.315155 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13571 13:59:06.325027 Opened dev<8>[ 30.952453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13572 13:59:06.325317 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13574 13:59:06.328767 ice: /dev/dri/card0
13575 13:59:06.332013 No KMS driver or no outputs, pipes: 8, outputs: 0
13576 13:59:06.335220 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13577 13:59:06.345452 <14>[ 30.977312] [IGT] kms_vblank: executing
13578 13:59:06.351990 IGT-Version: 1.2<14>[ 30.982184] [IGT] kms_vblank: exiting, ret=77
13579 13:59:06.355530 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13580 13:59:06.365370 Opened dev<8>[ 30.992342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13581 13:59:06.365452 ice: /dev/dri/card0
13582 13:59:06.365687 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13584 13:59:06.372199 No KMS driver or no outputs, pipes: 8, outputs: 0
13585 13:59:06.378435 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13586 13:59:06.381795 <14>[ 31.014136] [IGT] kms_vblank: executing
13587 13:59:06.388467 IGT-Version: 1.2<14>[ 31.018923] [IGT] kms_vblank: exiting, ret=77
13588 13:59:06.391639 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13589 13:59:06.401612 Opened dev<8>[ 31.029330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13590 13:59:06.401864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13592 13:59:06.405216 ice: /dev/dri/card0
13593 13:59:06.408374 No KMS driver or no outputs, pipes: 8, outputs: 0
13594 13:59:06.414859 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13595 13:59:06.418262 <14>[ 31.051099] [IGT] kms_vblank: executing
13596 13:59:06.425193 IGT-Version: 1.2<14>[ 31.056227] [IGT] kms_vblank: exiting, ret=77
13597 13:59:06.428078 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13598 13:59:06.437971 Opened dev<8>[ 31.066469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13599 13:59:06.438223 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13601 13:59:06.441348 ice: /dev/dri/card0
13602 13:59:06.445065 No KMS driver or no outputs, pipes: 8, outputs: 0
13603 13:59:06.451771 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13604 13:59:06.454842 <14>[ 31.087989] [IGT] kms_vblank: executing
13605 13:59:06.461488 IGT-Version: 1.2<14>[ 31.093265] [IGT] kms_vblank: exiting, ret=77
13606 13:59:06.468467 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13607 13:59:06.475120 Opened dev<8>[ 31.103533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13608 13:59:06.475373 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13610 13:59:06.478234 ice: /dev/dri/card0
13611 13:59:06.481590 No KMS driver or no outputs, pipes: 8, outputs: 0
13612 13:59:06.484546 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13613 13:59:06.492255 <14>[ 31.124022] [IGT] kms_vblank: executing
13614 13:59:06.498933 IGT-Version: 1.2<14>[ 31.128717] [IGT] kms_vblank: exiting, ret=77
13615 13:59:06.502372 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13616 13:59:06.511905 Opened dev<8>[ 31.139091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13617 13:59:06.511988 ice: /dev/dri/card0
13618 13:59:06.512224 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13620 13:59:06.515356 No KMS driver or no outputs, pipes: 8, outputs: 0
13621 13:59:06.521971 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13622 13:59:06.528443 <14>[ 31.159636] [IGT] kms_vblank: executing
13623 13:59:06.532024 IGT-Version: 1.2<14>[ 31.164375] [IGT] kms_vblank: exiting, ret=77
13624 13:59:06.538311 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13625 13:59:06.545199 Opened dev<8>[ 31.174461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13626 13:59:06.545481 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13628 13:59:06.548343 ice: /dev/dri/card0
13629 13:59:06.552021 No KMS driver or no outputs, pipes: 8, outputs: 0
13630 13:59:06.558570 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13631 13:59:06.562070 <14>[ 31.195239] [IGT] kms_vblank: executing
13632 13:59:06.568225 IGT-Version: 1.2<14>[ 31.199941] [IGT] kms_vblank: exiting, ret=77
13633 13:59:06.575160 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13634 13:59:06.582112 Opened dev<8>[ 31.210150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13635 13:59:06.582366 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13637 13:59:06.584946 ice: /dev/dri/card0
13638 13:59:06.588612 No KMS driver or no outputs, pipes: 8, outputs: 0
13639 13:59:06.591706 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13640 13:59:06.598922 <14>[ 31.230506] [IGT] kms_vblank: executing
13641 13:59:06.605804 IGT-Version: 1.2<14>[ 31.235265] [IGT] kms_vblank: exiting, ret=77
13642 13:59:06.608814 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13643 13:59:06.618444 Opened dev<8>[ 31.245731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13644 13:59:06.618527 ice: /dev/dri/card0
13645 13:59:06.618762 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13647 13:59:06.625494 No KMS driver or no outputs, pipes: 8, outputs: 0
13648 13:59:06.628541 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13649 13:59:06.635098 <14>[ 31.266749] [IGT] kms_vblank: executing
13650 13:59:06.642548 IGT-Version: 1.2<14>[ 31.271454] [IGT] kms_vblank: exiting, ret=77
13651 13:59:06.645513 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13652 13:59:06.652009 Opened dev<8>[ 31.281919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13653 13:59:06.652261 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13655 13:59:06.655472 ice: /dev/dri/card0
13656 13:59:06.658989 No KMS driver or no outputs, pipes: 8, outputs: 0
13657 13:59:06.665099 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13658 13:59:06.668730 <14>[ 31.301933] [IGT] kms_vblank: executing
13659 13:59:06.675446 IGT-Version: 1.2<14>[ 31.306637] [IGT] kms_vblank: exiting, ret=77
13660 13:59:06.678437 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13661 13:59:06.688744 Opened dev<8>[ 31.316918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13662 13:59:06.688998 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13664 13:59:06.692400 ice: /dev/dri/card0
13665 13:59:06.695864 No KMS driver or no outputs, pipes: 8, outputs: 0
13666 13:59:06.698458 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13667 13:59:06.705696 <14>[ 31.337843] [IGT] kms_vblank: executing
13668 13:59:06.712641 IGT-Version: 1.2<14>[ 31.342549] [IGT] kms_vblank: exiting, ret=77
13669 13:59:06.716060 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13670 13:59:06.726069 Opened dev<8>[ 31.352725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13671 13:59:06.726159 ice: /dev/dri/card0
13672 13:59:06.726402 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13674 13:59:06.732390 No KMS driver or no outputs, pipes: 8, outputs: 0
13675 13:59:06.735827 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13676 13:59:06.742638 <14>[ 31.374207] [IGT] kms_vblank: executing
13677 13:59:06.749032 IGT-Version: 1.2<14>[ 31.378907] [IGT] kms_vblank: exiting, ret=77
13678 13:59:06.752201 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13679 13:59:06.762331 Opened dev<8>[ 31.389183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13680 13:59:06.762440 ice: /dev/dri/card0
13681 13:59:06.762690 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13683 13:59:06.769131 No KMS driver or no outputs, pipes: 8, outputs: 0
13684 13:59:06.772731 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13685 13:59:06.779410 <14>[ 31.411006] [IGT] kms_vblank: executing
13686 13:59:06.786675 IGT-Version: 1.2<14>[ 31.415736] [IGT] kms_vblank: exiting, ret=77
13687 13:59:06.789119 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13688 13:59:06.796099 Opened dev<8>[ 31.426002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13689 13:59:06.796353 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13691 13:59:06.799420 ice: /dev/dri/card0
13692 13:59:06.802588 No KMS driver or no outputs, pipes: 8, outputs: 0
13693 13:59:06.809343 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13694 13:59:06.812765 <14>[ 31.446682] [IGT] kms_vblank: executing
13695 13:59:06.819593 IGT-Version: 1.2<14>[ 31.451425] [IGT] kms_vblank: exiting, ret=77
13696 13:59:06.825778 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13697 13:59:06.832350 Opened dev<8>[ 31.461787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13698 13:59:06.832603 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13700 13:59:06.836135 ice: /dev/dri/card0
13701 13:59:06.839100 No KMS driver or no outputs, pipes: 8, outputs: 0
13702 13:59:06.845950 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13703 13:59:06.849141 <14>[ 31.482229] [IGT] kms_vblank: executing
13704 13:59:06.855756 IGT-Version: 1.2<14>[ 31.486919] [IGT] kms_vblank: exiting, ret=77
13705 13:59:06.859406 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13706 13:59:06.869234 Opened dev<8>[ 31.497335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13707 13:59:06.869317 ice: /dev/dri/card0
13708 13:59:06.869552 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13710 13:59:06.876199 No KMS driver or no outputs, pipes: 8, outputs: 0
13711 13:59:06.879284 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13712 13:59:06.885873 <14>[ 31.517575] [IGT] kms_vblank: executing
13713 13:59:06.892148 IGT-Version: 1.2<14>[ 31.522362] [IGT] kms_vblank: exiting, ret=77
13714 13:59:06.895884 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13715 13:59:06.905909 Opened dev<8>[ 31.532622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13716 13:59:06.905991 ice: /dev/dri/card0
13717 13:59:06.906225 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13719 13:59:06.912521 No KMS driver or no outputs, pipes: 8, outputs: 0
13720 13:59:06.916163 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13721 13:59:06.922694 <14>[ 31.553872] [IGT] kms_vblank: executing
13722 13:59:06.925708 IGT-Version: 1.2<14>[ 31.558595] [IGT] kms_vblank: exiting, ret=77
13723 13:59:06.932955 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13724 13:59:06.939105 Opened dev<8>[ 31.568784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13725 13:59:06.939357 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13727 13:59:06.942750 ice: /dev/dri/card0
13728 13:59:06.945961 No KMS driver or no outputs, pipes: 8, outputs: 0
13729 13:59:06.952323 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13730 13:59:06.955827 <14>[ 31.589056] [IGT] kms_vblank: executing
13731 13:59:06.962620 IGT-Version: 1.2<14>[ 31.593931] [IGT] kms_vblank: exiting, ret=77
13732 13:59:06.968798 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13733 13:59:06.968880 Opened device: /dev/dri/card0
13734 13:59:06.978933 No KMS driv<8>[ 31.606597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13735 13:59:06.979187 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13737 13:59:06.981821 er or no outputs, pipes: 8, outputs: 0
13738 13:59:06.985668 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13739 13:59:06.996305 <14>[ 31.628158] [IGT] kms_vblank: executing
13740 13:59:07.002850 IGT-Version: 1.2<14>[ 31.632868] [IGT] kms_vblank: exiting, ret=77
13741 13:59:07.006519 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13742 13:59:07.016241 Opened dev<8>[ 31.643159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13743 13:59:07.016329 ice: /dev/dri/card0
13744 13:59:07.016565 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13746 13:59:07.022935 No KMS driver or no outputs, pipes: 8, outputs: 0
13747 13:59:07.026366 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13748 13:59:07.033088 <14>[ 31.664596] [IGT] kms_vblank: executing
13749 13:59:07.040399 IGT-Version: 1.2<14>[ 31.669551] [IGT] kms_vblank: exiting, ret=77
13750 13:59:07.043539 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13751 13:59:07.053376 Opened device: /dev/dri/ca<8>[ 31.680989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13752 13:59:07.053455 rd0
13753 13:59:07.053689 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13755 13:59:07.059838 No KMS driver or no outputs, pipes: 8, outputs: 0
13756 13:59:07.063141 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13757 13:59:07.071438 <14>[ 31.702985] [IGT] kms_vblank: executing
13758 13:59:07.078074 IGT-Version: 1.2<14>[ 31.707777] [IGT] kms_vblank: exiting, ret=77
13759 13:59:07.081016 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13760 13:59:07.091839 Opened dev<8>[ 31.718174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13761 13:59:07.091921 ice: /dev/dri/card0
13762 13:59:07.092157 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13764 13:59:07.098175 No KMS driver or no outputs, pipes: 8, outputs: 0
13765 13:59:07.101309 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13766 13:59:07.108024 <14>[ 31.738949] [IGT] kms_vblank: executing
13767 13:59:07.111293 IGT-Version: 1.2<14>[ 31.743680] [IGT] kms_vblank: exiting, ret=77
13768 13:59:07.118351 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13769 13:59:07.127604 Opened dev<8>[ 31.753973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13770 13:59:07.127688 ice: /dev/dri/card0
13771 13:59:07.127924 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13773 13:59:07.134513 No KMS driver or no outputs, pipes: 8, outputs: 0
13774 13:59:07.137932 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13775 13:59:07.144236 <14>[ 31.775696] [IGT] kms_vblank: executing
13776 13:59:07.147941 IGT-Version: 1.2<14>[ 31.780415] [IGT] kms_vblank: exiting, ret=77
13777 13:59:07.154361 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13778 13:59:07.164659 Opened dev<8>[ 31.790698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13779 13:59:07.164742 ice: /dev/dri/card0
13780 13:59:07.164977 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13782 13:59:07.171004 No KMS driver or no outputs, pipes: 8, outputs: 0
13783 13:59:07.174274 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13784 13:59:07.180649 <14>[ 31.811825] [IGT] kms_vblank: executing
13785 13:59:07.187537 IGT-Version: 1.2<14>[ 31.817025] [IGT] kms_vblank: exiting, ret=77
13786 13:59:07.190982 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13787 13:59:07.200598 Opened dev<8>[ 31.827479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13788 13:59:07.200851 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13790 13:59:07.204050 ice: /dev/dri/card0
13791 13:59:07.207036 No KMS driver or no outputs, pipes: 8, outputs: 0
13792 13:59:07.213828 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13793 13:59:07.217342 <14>[ 31.849054] [IGT] kms_vblank: executing
13794 13:59:07.223989 IGT-Version: 1.2<14>[ 31.854322] [IGT] kms_vblank: exiting, ret=77
13795 13:59:07.226986 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13796 13:59:07.237436 Opened dev<8>[ 31.864527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13797 13:59:07.237690 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13799 13:59:07.240149 ice: /dev/dri/card0
13800 13:59:07.243650 No KMS driver or no outputs, pipes: 8, outputs: 0
13801 13:59:07.250780 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13802 13:59:07.253469 <14>[ 31.886212] [IGT] kms_vblank: executing
13803 13:59:07.260087 IGT-Version: 1.2<14>[ 31.890924] [IGT] kms_vblank: exiting, ret=77
13804 13:59:07.263462 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13805 13:59:07.273878 Opened dev<8>[ 31.901152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13806 13:59:07.274131 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13808 13:59:07.277022 ice: /dev/dri/card0
13809 13:59:07.280751 No KMS driver or no outputs, pipes: 8, outputs: 0
13810 13:59:07.287228 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13811 13:59:07.290551 <14>[ 31.922837] [IGT] kms_vblank: executing
13812 13:59:07.296766 IGT-Version: 1.2<14>[ 31.927668] [IGT] kms_vblank: exiting, ret=77
13813 13:59:07.300061 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13814 13:59:07.309950 Opened dev<8>[ 31.938280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13815 13:59:07.310204 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13817 13:59:07.313492 ice: /dev/dri/card0
13818 13:59:07.317031 No KMS driver or no outputs, pipes: 8, outputs: 0
13819 13:59:07.323478 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13820 13:59:07.326808 <14>[ 31.959713] [IGT] kms_vblank: executing
13821 13:59:07.333110 IGT-Version: 1.2<14>[ 31.964953] [IGT] kms_vblank: exiting, ret=77
13822 13:59:07.340382 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13823 13:59:07.346614 Opened dev<8>[ 31.975376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13824 13:59:07.346869 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13826 13:59:07.349794 ice: /dev/dri/card0
13827 13:59:07.353220 No KMS driver or no outputs, pipes: 8, outputs: 0
13828 13:59:07.360003 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13829 13:59:07.363445 <14>[ 31.996846] [IGT] kms_vblank: executing
13830 13:59:07.369947 IGT-Version: 1.2<14>[ 32.002060] [IGT] kms_vblank: exiting, ret=77
13831 13:59:07.376369 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13832 13:59:07.383507 Opened dev<8>[ 32.012608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13833 13:59:07.383761 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13835 13:59:07.386554 ice: /dev/dri/card0
13836 13:59:07.389851 No KMS driver or no outputs, pipes: 8, outputs: 0
13837 13:59:07.396334 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13838 13:59:07.399964 <14>[ 32.032832] [IGT] kms_vblank: executing
13839 13:59:07.406623 IGT-Version: 1.2<14>[ 32.037654] [IGT] kms_vblank: exiting, ret=77
13840 13:59:07.410093 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13841 13:59:07.419962 Opened dev<8>[ 32.047886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13842 13:59:07.420044 ice: /dev/dri/card0
13843 13:59:07.420279 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13845 13:59:07.426451 No KMS driver or no outputs, pipes: 8, outputs: 0
13846 13:59:07.430043 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13847 13:59:07.436753 <14>[ 32.068667] [IGT] kms_vblank: executing
13848 13:59:07.443561 IGT-Version: 1.2<14>[ 32.073452] [IGT] kms_vblank: exiting, ret=77
13849 13:59:07.447166 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13850 13:59:07.457077 Opened dev<8>[ 32.083583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13851 13:59:07.457159 ice: /dev/dri/card0
13852 13:59:07.457394 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13854 13:59:07.463286 No KMS driver or no outputs, pipes: 8, outputs: 0
13855 13:59:07.466931 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13856 13:59:07.470002 <14>[ 32.103892] [IGT] kms_vblank: executing
13857 13:59:07.477102 IGT-Version: 1.2<14>[ 32.108596] [IGT] kms_vblank: exiting, ret=77
13858 13:59:07.483649 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13859 13:59:07.489711 Opened dev<8>[ 32.118778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13860 13:59:07.489963 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13862 13:59:07.493381 ice: /dev/dri/card0
13863 13:59:07.496717 No KMS driver or no outputs, pipes: 8, outputs: 0
13864 13:59:07.500047 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13865 13:59:07.507901 <14>[ 32.139563] [IGT] kms_vblank: executing
13866 13:59:07.514071 IGT-Version: 1.2<14>[ 32.144277] [IGT] kms_vblank: exiting, ret=77
13867 13:59:07.517789 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13868 13:59:07.527626 Opened dev<8>[ 32.154483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13869 13:59:07.527707 ice: /dev/dri/card0
13870 13:59:07.527941 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13872 13:59:07.534165 No KMS driver or no outputs, pipes: 8, outputs: 0
13873 13:59:07.537418 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13874 13:59:07.544257 <14>[ 32.175461] [IGT] kms_vblank: executing
13875 13:59:07.547658 IGT-Version: 1.2<14>[ 32.180178] [IGT] kms_vblank: exiting, ret=77
13876 13:59:07.554293 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13877 13:59:07.560943 Opened dev<8>[ 32.190520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13878 13:59:07.561195 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13880 13:59:07.564351 ice: /dev/dri/card0
13881 13:59:07.567765 No KMS driver or no outputs, pipes: 8, outputs: 0
13882 13:59:07.573755 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13883 13:59:07.577252 <14>[ 32.211065] [IGT] kms_vblank: executing
13884 13:59:07.583732 IGT-Version: 1.2<14>[ 32.215832] [IGT] kms_vblank: exiting, ret=77
13885 13:59:07.590882 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13886 13:59:07.597077 Opened dev<8>[ 32.226116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13887 13:59:07.597330 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13889 13:59:07.600761 ice: /dev/dri/card0
13890 13:59:07.604020 No KMS driver or no outputs, pipes: 8, outputs: 0
13891 13:59:07.610455 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13892 13:59:07.614064 <14>[ 32.246874] [IGT] kms_vblank: executing
13893 13:59:07.620530 IGT-Version: 1.2<14>[ 32.251583] [IGT] kms_vblank: exiting, ret=77
13894 13:59:07.623890 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13895 13:59:07.633621 Opened dev<8>[ 32.262004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13896 13:59:07.633873 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13898 13:59:07.637069 ice: /dev/dri/card0
13899 13:59:07.640396 No KMS driver or no outputs, pipes: 8, outputs: 0
13900 13:59:07.643614 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13901 13:59:07.650692 <14>[ 32.282740] [IGT] kms_vblank: executing
13902 13:59:07.657230 IGT-Version: 1.2<14>[ 32.287678] [IGT] kms_vblank: exiting, ret=77
13903 13:59:07.660713 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13904 13:59:07.671029 Opened dev<8>[ 32.298015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13905 13:59:07.671282 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13907 13:59:07.673945 ice: /dev/dri/card0
13908 13:59:07.677169 No KMS driver or no outputs, pipes: 8, outputs: 0
13909 13:59:07.680496 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13910 13:59:07.687582 <14>[ 32.319666] [IGT] kms_vblank: executing
13911 13:59:07.694407 IGT-Version: 1.2<14>[ 32.324424] [IGT] kms_vblank: exiting, ret=77
13912 13:59:07.697762 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13913 13:59:07.704372 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13915 13:59:07.707567 Opened dev<8>[ 32.334569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13916 13:59:07.707649 ice: /dev/dri/card0
13917 13:59:07.711199 No KMS driver or no outputs, pipes: 8, outputs: 0
13918 13:59:07.718028 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13919 13:59:07.720955 <14>[ 32.355335] [IGT] kms_vblank: executing
13920 13:59:07.727471 IGT-Version: 1.2<14>[ 32.360055] [IGT] kms_vblank: exiting, ret=77
13921 13:59:07.734693 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13922 13:59:07.741137 Opened dev<8>[ 32.370244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13923 13:59:07.741388 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13925 13:59:07.744587 ice: /dev/dri/card0
13926 13:59:07.747625 No KMS driver or no outputs, pipes: 8, outputs: 0
13927 13:59:07.754702 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13928 13:59:07.757674 <14>[ 32.391114] [IGT] kms_vblank: executing
13929 13:59:07.764304 IGT-Version: 1.2<14>[ 32.395814] [IGT] kms_vblank: exiting, ret=77
13930 13:59:07.770964 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13931 13:59:07.777649 Opened dev<8>[ 32.406121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13932 13:59:07.777902 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13934 13:59:07.781130 ice: /dev/dri/card0
13935 13:59:07.784556 No KMS driver or no outputs, pipes: 8, outputs: 0
13936 13:59:07.788072 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13937 13:59:07.794692 <14>[ 32.426398] [IGT] kms_vblank: executing
13938 13:59:07.801036 IGT-Version: 1.2<14>[ 32.431139] [IGT] kms_vblank: exiting, ret=77
13939 13:59:07.804237 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13940 13:59:07.814642 Opened dev<8>[ 32.441550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13941 13:59:07.814724 ice: /dev/dri/card0
13942 13:59:07.814959 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13944 13:59:07.820927 No KMS driver or no outputs, pipes: 8, outputs: 0
13945 13:59:07.824447 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13946 13:59:07.830906 <14>[ 32.462690] [IGT] kms_vblank: executing
13947 13:59:07.837734 IGT-Version: 1.2<14>[ 32.467387] [IGT] kms_vblank: exiting, ret=77
13948 13:59:07.840846 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13949 13:59:07.847424 Opened dev<8>[ 32.477827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13950 13:59:07.847677 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13952 13:59:07.851182 ice: /dev/dri/card0
13953 13:59:07.854078 No KMS driver or no outputs, pipes: 8, outputs: 0
13954 13:59:07.861150 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13955 13:59:07.863703 <14>[ 32.497976] [IGT] kms_vblank: executing
13956 13:59:07.871140 IGT-Version: 1.2<14>[ 32.502693] [IGT] kms_vblank: exiting, ret=77
13957 13:59:07.877394 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13958 13:59:07.884017 Opened dev<8>[ 32.513007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13959 13:59:07.884269 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13961 13:59:07.887555 ice: /dev/dri/card0
13962 13:59:07.890483 No KMS driver or no outputs, pipes: 8, outputs: 0
13963 13:59:07.896964 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13964 13:59:07.900234 <14>[ 32.534063] [IGT] kms_vblank: executing
13965 13:59:07.907148 IGT-Version: 1.2<14>[ 32.538905] [IGT] kms_vblank: exiting, ret=77
13966 13:59:07.913448 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13967 13:59:07.920081 Opened dev<8>[ 32.549458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13968 13:59:07.920334 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13970 13:59:07.923730 ice: /dev/dri/card0
13971 13:59:07.926711 No KMS driver or no outputs, pipes: 8, outputs: 0
13972 13:59:07.933532 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13973 13:59:07.936755 <14>[ 32.569947] [IGT] kms_vblank: executing
13974 13:59:07.943500 IGT-Version: 1.2<14>[ 32.574687] [IGT] kms_vblank: exiting, ret=77
13975 13:59:07.946727 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13976 13:59:07.957022 Opened dev<8>[ 32.584901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13977 13:59:07.957279 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13979 13:59:07.960384 ice: /dev/dri/card0
13980 13:59:07.963275 No KMS driver or no outputs, pipes: 8, outputs: 0
13981 13:59:07.970090 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13982 13:59:07.973158 <14>[ 32.606643] [IGT] kms_vblank: executing
13983 13:59:07.980192 IGT-Version: 1.2<14>[ 32.611397] [IGT] kms_vblank: exiting, ret=77
13984 13:59:07.983710 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13985 13:59:07.993283 Opened dev<8>[ 32.621707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13986 13:59:07.993536 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13988 13:59:07.996855 ice: /dev/dri/card0
13989 13:59:08.000167 No KMS driver or no outputs, pipes: 8, outputs: 0
13990 13:59:08.007035 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13991 13:59:08.009897 <14>[ 32.643107] [IGT] kms_vblank: executing
13992 13:59:08.016545 IGT-Version: 1.2<14>[ 32.647924] [IGT] kms_vblank: exiting, ret=77
13993 13:59:08.020614 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13994 13:59:08.030172 Opened dev<8>[ 32.658282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13995 13:59:08.030437 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13997 13:59:08.033270 ice: /dev/dri/card0
13998 13:59:08.036634 No KMS driver or no outputs, pipes: 8, outputs: 0
13999 13:59:08.043367 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
14000 13:59:08.046716 <14>[ 32.679693] [IGT] kms_vblank: executing
14001 13:59:08.053529 IGT-Version: 1.2<14>[ 32.684659] [IGT] kms_vblank: exiting, ret=77
14002 13:59:08.056881 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14003 13:59:08.066808 Opened dev<8>[ 32.694842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
14004 13:59:08.067060 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
14006 13:59:08.069729 ice: /dev/dri/card0
14007 13:59:08.073284 No KMS driver or no outputs, pipes: 8, outputs: 0
14008 13:59:08.079562 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
14009 13:59:08.083239 <14>[ 32.716249] [IGT] kms_vblank: executing
14010 13:59:08.089707 IGT-Version: 1.2<14>[ 32.721354] [IGT] kms_vblank: exiting, ret=77
14011 13:59:08.096278 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14012 13:59:08.103634 Opened dev<8>[ 32.731597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
14013 13:59:08.103886 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
14015 13:59:08.106322 ice: /dev/dri/card0
14016 13:59:08.109634 No KMS driver or no outputs, pipes: 8, outputs: 0
14017 13:59:08.116286 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
14018 13:59:08.119440 <14>[ 32.753165] [IGT] kms_vblank: executing
14019 13:59:08.127169 IGT-Version: 1.2<14>[ 32.758461] [IGT] kms_vblank: exiting, ret=77
14020 13:59:08.132756 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14021 13:59:08.143150 Opened dev<8>[ 32.768772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
14022 13:59:08.143292 ice: /dev/dri/card0
14023 13:59:08.143540 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
14025 13:59:08.146565 No KMS driver or no outputs, pipes: 8, outputs: 0
14026 13:59:08.152996 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
14027 13:59:08.156389 <14>[ 32.790371] [IGT] kms_vblank: executing
14028 13:59:08.163023 IGT-Version: 1.2<14>[ 32.795105] [IGT] kms_vblank: exiting, ret=77
14029 13:59:08.169332 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14030 13:59:08.179268 Opened dev<8>[ 32.805566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
14031 13:59:08.179350 ice: /dev/dri/card0
14032 13:59:08.179587 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
14034 13:59:08.182636 No KMS driver or no outputs, pipes: 8, outputs: 0
14035 13:59:08.189524 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
14036 13:59:08.196260 <14>[ 32.827288] [IGT] kms_vblank: executing
14037 13:59:08.199307 IGT-Version: 1.2<14>[ 32.832027] [IGT] kms_vblank: exiting, ret=77
14038 13:59:08.205931 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14039 13:59:08.216445 Opened dev<8>[ 32.842151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
14040 13:59:08.216527 ice: /dev/dri/card0
14041 13:59:08.216761 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
14043 13:59:08.222845 No KMS driver or no outputs, pipes: 8, outputs: 0
14044 13:59:08.225714 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
14045 13:59:08.232874 <14>[ 32.863936] [IGT] kms_vblank: executing
14046 13:59:08.239211 IGT-Version: 1.2<14>[ 32.869442] [IGT] kms_vblank: exiting, ret=77
14047 13:59:08.242745 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14048 13:59:08.252995 Opened dev<8>[ 32.879702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
14049 13:59:08.253250 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
14051 13:59:08.259596 ice: /dev/dri/ca<8>[ 32.890914] <LAVA_SIGNAL_TESTSET STOP>
14052 13:59:08.259678 rd0
14053 13:59:08.259911 Received signal: <TESTSET> STOP
14054 13:59:08.259975 Closing test_set kms_vblank
14055 13:59:08.265861 No KMS driv<8>[ 32.895907] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12682963_1.5.2.3.1>
14056 13:59:08.266112 Received signal: <ENDRUN> 0_igt-kms-mediatek 12682963_1.5.2.3.1
14057 13:59:08.266194 Ending use of test pattern.
14058 13:59:08.266255 Ending test lava.0_igt-kms-mediatek (12682963_1.5.2.3.1), duration 12.45
14060 13:59:08.269309 er or no outputs, pipes: 8, outputs: 0
14061 13:59:08.275799 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
14062 13:59:08.275880 + set +x
14063 13:59:08.278969 <LAVA_TEST_RUNNER EXIT>
14064 13:59:08.279220 ok: lava_test_shell seems to have completed
14065 13:59:08.283027 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
14066 13:59:08.283259 end: 3.1 lava-test-shell (duration 00:00:13) [common]
14067 13:59:08.283345 end: 3 lava-test-retry (duration 00:00:13) [common]
14068 13:59:08.283430 start: 4 finalize (timeout 00:07:07) [common]
14069 13:59:08.283517 start: 4.1 power-off (timeout 00:00:30) [common]
14070 13:59:08.283661 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
14071 13:59:08.359784 >> Command sent successfully.
14072 13:59:08.362147 Returned 0 in 0 seconds
14073 13:59:08.462580 end: 4.1 power-off (duration 00:00:00) [common]
14075 13:59:08.462902 start: 4.2 read-feedback (timeout 00:07:07) [common]
14076 13:59:08.463172 Listened to connection for namespace 'common' for up to 1s
14077 13:59:09.464121 Finalising connection for namespace 'common'
14078 13:59:09.464301 Disconnecting from shell: Finalise
14079 13:59:09.464375 / #
14080 13:59:09.564692 end: 4.2 read-feedback (duration 00:00:01) [common]
14081 13:59:09.564842 end: 4 finalize (duration 00:00:01) [common]
14082 13:59:09.564957 Cleaning after the job
14083 13:59:09.565054 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/ramdisk
14084 13:59:09.572761 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/kernel
14085 13:59:09.581503 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/dtb
14086 13:59:09.581672 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682963/tftp-deploy-mx_x4u2x/modules
14087 13:59:09.588848 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682963
14088 13:59:09.706839 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682963
14089 13:59:09.707021 Job finished correctly