Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 16
- Kernel Errors: 36
1 13:56:00.054453 lava-dispatcher, installed at version: 2023.10
2 13:56:00.054665 start: 0 validate
3 13:56:00.054801 Start time: 2024-02-01 13:56:00.054794+00:00 (UTC)
4 13:56:00.054915 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:56:00.055052 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Finitrd.cpio.gz exists
6 13:56:00.322746 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:56:00.322922 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:56:00.580748 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:56:00.580923 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:56:00.848011 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:56:00.848211 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:56:01.107294 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:56:01.107474 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:56:01.367089 validate duration: 1.31
16 13:56:01.367483 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:56:01.367646 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:56:01.367748 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:56:01.367875 Not decompressing ramdisk as can be used compressed.
20 13:56:01.367989 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/initrd.cpio.gz
21 13:56:01.368128 saving as /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/ramdisk/initrd.cpio.gz
22 13:56:01.368210 total size: 5628325 (5 MB)
23 13:56:01.373096 progress 0 % (0 MB)
24 13:56:01.374745 progress 5 % (0 MB)
25 13:56:01.376489 progress 10 % (0 MB)
26 13:56:01.378035 progress 15 % (0 MB)
27 13:56:01.379647 progress 20 % (1 MB)
28 13:56:01.381081 progress 25 % (1 MB)
29 13:56:01.382710 progress 30 % (1 MB)
30 13:56:01.384364 progress 35 % (1 MB)
31 13:56:01.385856 progress 40 % (2 MB)
32 13:56:01.387451 progress 45 % (2 MB)
33 13:56:01.388946 progress 50 % (2 MB)
34 13:56:01.390638 progress 55 % (2 MB)
35 13:56:01.392224 progress 60 % (3 MB)
36 13:56:01.393713 progress 65 % (3 MB)
37 13:56:01.395311 progress 70 % (3 MB)
38 13:56:01.396755 progress 75 % (4 MB)
39 13:56:01.398360 progress 80 % (4 MB)
40 13:56:01.399714 progress 85 % (4 MB)
41 13:56:01.401427 progress 90 % (4 MB)
42 13:56:01.403011 progress 95 % (5 MB)
43 13:56:01.404401 progress 100 % (5 MB)
44 13:56:01.404634 5 MB downloaded in 0.04 s (147.37 MB/s)
45 13:56:01.404812 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:56:01.405097 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:56:01.405208 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:56:01.405292 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:56:01.405422 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:56:01.405519 saving as /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/kernel/Image
52 13:56:01.405594 total size: 51532288 (49 MB)
53 13:56:01.405654 No compression specified
54 13:56:01.406724 progress 0 % (0 MB)
55 13:56:01.420305 progress 5 % (2 MB)
56 13:56:01.433846 progress 10 % (4 MB)
57 13:56:01.447068 progress 15 % (7 MB)
58 13:56:01.460389 progress 20 % (9 MB)
59 13:56:01.473916 progress 25 % (12 MB)
60 13:56:01.487237 progress 30 % (14 MB)
61 13:56:01.500605 progress 35 % (17 MB)
62 13:56:01.514087 progress 40 % (19 MB)
63 13:56:01.527385 progress 45 % (22 MB)
64 13:56:01.540767 progress 50 % (24 MB)
65 13:56:01.554072 progress 55 % (27 MB)
66 13:56:01.567380 progress 60 % (29 MB)
67 13:56:01.580777 progress 65 % (31 MB)
68 13:56:01.593987 progress 70 % (34 MB)
69 13:56:01.607467 progress 75 % (36 MB)
70 13:56:01.620964 progress 80 % (39 MB)
71 13:56:01.634238 progress 85 % (41 MB)
72 13:56:01.647631 progress 90 % (44 MB)
73 13:56:01.660840 progress 95 % (46 MB)
74 13:56:01.673769 progress 100 % (49 MB)
75 13:56:01.673976 49 MB downloaded in 0.27 s (183.12 MB/s)
76 13:56:01.674129 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:56:01.674362 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:56:01.674452 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:56:01.674538 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:56:01.674678 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:56:01.674747 saving as /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/dtb/mt8192-asurada-spherion-r0.dtb
83 13:56:01.674808 total size: 47278 (0 MB)
84 13:56:01.674868 No compression specified
85 13:56:01.675982 progress 69 % (0 MB)
86 13:56:01.676256 progress 100 % (0 MB)
87 13:56:01.676414 0 MB downloaded in 0.00 s (28.11 MB/s)
88 13:56:01.676536 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:56:01.676762 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:56:01.676848 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:56:01.676932 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:56:01.677047 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/full.rootfs.tar.xz
94 13:56:01.677114 saving as /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/nfsrootfs/full.rootfs.tar
95 13:56:01.677174 total size: 198084472 (188 MB)
96 13:56:01.677235 Using unxz to decompress xz
97 13:56:01.685407 progress 0 % (0 MB)
98 13:56:02.245251 progress 5 % (9 MB)
99 13:56:02.740165 progress 10 % (18 MB)
100 13:56:03.320398 progress 15 % (28 MB)
101 13:56:03.608107 progress 20 % (37 MB)
102 13:56:04.070374 progress 25 % (47 MB)
103 13:56:04.640719 progress 30 % (56 MB)
104 13:56:05.194264 progress 35 % (66 MB)
105 13:56:05.754683 progress 40 % (75 MB)
106 13:56:06.335394 progress 45 % (85 MB)
107 13:56:06.941581 progress 50 % (94 MB)
108 13:56:07.546982 progress 55 % (103 MB)
109 13:56:08.199232 progress 60 % (113 MB)
110 13:56:08.571123 progress 65 % (122 MB)
111 13:56:08.662941 progress 70 % (132 MB)
112 13:56:08.804881 progress 75 % (141 MB)
113 13:56:08.882188 progress 80 % (151 MB)
114 13:56:08.933627 progress 85 % (160 MB)
115 13:56:09.028789 progress 90 % (170 MB)
116 13:56:09.393072 progress 95 % (179 MB)
117 13:56:09.979386 progress 100 % (188 MB)
118 13:56:09.984149 188 MB downloaded in 8.31 s (22.74 MB/s)
119 13:56:09.984470 end: 1.4.1 http-download (duration 00:00:08) [common]
121 13:56:09.984803 end: 1.4 download-retry (duration 00:00:08) [common]
122 13:56:09.984909 start: 1.5 download-retry (timeout 00:09:51) [common]
123 13:56:09.985016 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 13:56:09.985191 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:56:09.985269 saving as /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/modules/modules.tar
126 13:56:09.985369 total size: 8623988 (8 MB)
127 13:56:09.985479 Using unxz to decompress xz
128 13:56:09.990264 progress 0 % (0 MB)
129 13:56:10.011478 progress 5 % (0 MB)
130 13:56:10.035615 progress 10 % (0 MB)
131 13:56:10.059804 progress 15 % (1 MB)
132 13:56:10.083661 progress 20 % (1 MB)
133 13:56:10.108017 progress 25 % (2 MB)
134 13:56:10.134131 progress 30 % (2 MB)
135 13:56:10.160874 progress 35 % (2 MB)
136 13:56:10.184681 progress 40 % (3 MB)
137 13:56:10.209348 progress 45 % (3 MB)
138 13:56:10.234887 progress 50 % (4 MB)
139 13:56:10.259433 progress 55 % (4 MB)
140 13:56:10.284521 progress 60 % (4 MB)
141 13:56:10.312543 progress 65 % (5 MB)
142 13:56:10.337866 progress 70 % (5 MB)
143 13:56:10.361512 progress 75 % (6 MB)
144 13:56:10.388340 progress 80 % (6 MB)
145 13:56:10.414466 progress 85 % (7 MB)
146 13:56:10.439882 progress 90 % (7 MB)
147 13:56:10.471703 progress 95 % (7 MB)
148 13:56:10.499755 progress 100 % (8 MB)
149 13:56:10.504625 8 MB downloaded in 0.52 s (15.84 MB/s)
150 13:56:10.504899 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:56:10.505170 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:56:10.505262 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 13:56:10.505355 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 13:56:14.190480 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12682960/extract-nfsrootfs-g0w8ha3y
156 13:56:14.190706 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:56:14.190830 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 13:56:14.191034 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1
159 13:56:14.191193 makedir: /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin
160 13:56:14.191316 makedir: /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/tests
161 13:56:14.191436 makedir: /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/results
162 13:56:14.191555 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-add-keys
163 13:56:14.191751 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-add-sources
164 13:56:14.191927 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-background-process-start
165 13:56:14.192099 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-background-process-stop
166 13:56:14.192246 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-common-functions
167 13:56:14.192395 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-echo-ipv4
168 13:56:14.192565 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-install-packages
169 13:56:14.192710 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-installed-packages
170 13:56:14.192852 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-os-build
171 13:56:14.192997 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-probe-channel
172 13:56:14.193147 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-probe-ip
173 13:56:14.193319 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-target-ip
174 13:56:14.193497 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-target-mac
175 13:56:14.193645 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-target-storage
176 13:56:14.193793 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-test-case
177 13:56:14.193940 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-test-event
178 13:56:14.194084 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-test-feedback
179 13:56:14.194230 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-test-raise
180 13:56:14.194378 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-test-reference
181 13:56:14.194552 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-test-runner
182 13:56:14.194724 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-test-set
183 13:56:14.194893 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-test-shell
184 13:56:14.195041 Updating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-add-keys (debian)
185 13:56:14.195216 Updating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-add-sources (debian)
186 13:56:14.195377 Updating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-install-packages (debian)
187 13:56:14.195542 Updating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-installed-packages (debian)
188 13:56:14.195729 Updating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/bin/lava-os-build (debian)
189 13:56:14.195896 Creating /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/environment
190 13:56:14.196034 LAVA metadata
191 13:56:14.196140 - LAVA_JOB_ID=12682960
192 13:56:14.196242 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:56:14.196397 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 13:56:14.196511 skipped lava-vland-overlay
195 13:56:14.196635 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:56:14.196762 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 13:56:14.196857 skipped lava-multinode-overlay
198 13:56:14.196976 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:56:14.197100 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 13:56:14.197214 Loading test definitions
201 13:56:14.197388 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 13:56:14.197534 Using /lava-12682960 at stage 0
203 13:56:14.197939 uuid=12682960_1.6.2.3.1 testdef=None
204 13:56:14.198067 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:56:14.198195 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 13:56:14.198825 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:56:14.199101 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 13:56:14.199731 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:56:14.200020 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 13:56:14.200586 runner path: /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/0/tests/0_timesync-off test_uuid 12682960_1.6.2.3.1
213 13:56:14.200754 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:56:14.201011 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 13:56:14.201097 Using /lava-12682960 at stage 0
217 13:56:14.201226 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:56:14.201341 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/0/tests/1_kselftest-alsa'
219 13:56:18.781353 Running '/usr/bin/git checkout kernelci.org
220 13:56:18.930439 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 13:56:18.931269 uuid=12682960_1.6.2.3.5 testdef=None
222 13:56:18.931448 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 13:56:18.931735 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 13:56:18.932518 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:56:18.932781 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 13:56:18.933852 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:56:18.934118 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 13:56:18.935082 runner path: /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/0/tests/1_kselftest-alsa test_uuid 12682960_1.6.2.3.5
232 13:56:18.935183 BOARD='mt8192-asurada-spherion-r0'
233 13:56:18.935261 BRANCH='cip'
234 13:56:18.935342 SKIPFILE='/dev/null'
235 13:56:18.935422 SKIP_INSTALL='True'
236 13:56:18.935518 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 13:56:18.935616 TST_CASENAME=''
238 13:56:18.935711 TST_CMDFILES='alsa'
239 13:56:18.935915 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:56:18.936274 Creating lava-test-runner.conf files
242 13:56:18.936378 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682960/lava-overlay-1_b54ia1/lava-12682960/0 for stage 0
243 13:56:18.936520 - 0_timesync-off
244 13:56:18.936622 - 1_kselftest-alsa
245 13:56:18.936768 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 13:56:18.936902 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 13:56:26.459600 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 13:56:26.459799 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 13:56:26.459892 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:56:26.459997 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 13:56:26.460087 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 13:56:26.630325 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:56:26.630715 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 13:56:26.630835 extracting modules file /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682960/extract-nfsrootfs-g0w8ha3y
255 13:56:26.851830 extracting modules file /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682960/extract-overlay-ramdisk-4fzkiefh/ramdisk
256 13:56:27.078974 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:56:27.079143 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 13:56:27.079239 [common] Applying overlay to NFS
259 13:56:27.079312 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682960/compress-overlay-0by_xts2/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682960/extract-nfsrootfs-g0w8ha3y
260 13:56:28.010268 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:56:28.010440 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 13:56:28.010599 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:56:28.010736 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 13:56:28.010831 Building ramdisk /var/lib/lava/dispatcher/tmp/12682960/extract-overlay-ramdisk-4fzkiefh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682960/extract-overlay-ramdisk-4fzkiefh/ramdisk
265 13:56:28.344346 >> 130539 blocks
266 13:56:30.430948 rename /var/lib/lava/dispatcher/tmp/12682960/extract-overlay-ramdisk-4fzkiefh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/ramdisk/ramdisk.cpio.gz
267 13:56:30.431387 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:56:30.431512 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 13:56:30.431615 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 13:56:30.431719 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/kernel/Image'
271 13:56:43.077015 Returned 0 in 12 seconds
272 13:56:43.177949 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/kernel/image.itb
273 13:56:43.558332 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:56:43.558707 output: Created: Thu Feb 1 13:56:43 2024
275 13:56:43.558789 output: Image 0 (kernel-1)
276 13:56:43.558856 output: Description:
277 13:56:43.558918 output: Created: Thu Feb 1 13:56:43 2024
278 13:56:43.558981 output: Type: Kernel Image
279 13:56:43.559040 output: Compression: lzma compressed
280 13:56:43.559096 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
281 13:56:43.559155 output: Architecture: AArch64
282 13:56:43.559211 output: OS: Linux
283 13:56:43.559273 output: Load Address: 0x00000000
284 13:56:43.559353 output: Entry Point: 0x00000000
285 13:56:43.559445 output: Hash algo: crc32
286 13:56:43.559506 output: Hash value: 5aa40db2
287 13:56:43.559565 output: Image 1 (fdt-1)
288 13:56:43.559618 output: Description: mt8192-asurada-spherion-r0
289 13:56:43.559673 output: Created: Thu Feb 1 13:56:43 2024
290 13:56:43.559726 output: Type: Flat Device Tree
291 13:56:43.559779 output: Compression: uncompressed
292 13:56:43.559832 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 13:56:43.559885 output: Architecture: AArch64
294 13:56:43.559938 output: Hash algo: crc32
295 13:56:43.559991 output: Hash value: cc4352de
296 13:56:43.560043 output: Image 2 (ramdisk-1)
297 13:56:43.560096 output: Description: unavailable
298 13:56:43.560149 output: Created: Thu Feb 1 13:56:43 2024
299 13:56:43.560202 output: Type: RAMDisk Image
300 13:56:43.560254 output: Compression: Unknown Compression
301 13:56:43.560307 output: Data Size: 18765661 Bytes = 18325.84 KiB = 17.90 MiB
302 13:56:43.560360 output: Architecture: AArch64
303 13:56:43.560413 output: OS: Linux
304 13:56:43.560466 output: Load Address: unavailable
305 13:56:43.560518 output: Entry Point: unavailable
306 13:56:43.560570 output: Hash algo: crc32
307 13:56:43.560622 output: Hash value: a063f04d
308 13:56:43.560675 output: Default Configuration: 'conf-1'
309 13:56:43.560727 output: Configuration 0 (conf-1)
310 13:56:43.560779 output: Description: mt8192-asurada-spherion-r0
311 13:56:43.560832 output: Kernel: kernel-1
312 13:56:43.560884 output: Init Ramdisk: ramdisk-1
313 13:56:43.560937 output: FDT: fdt-1
314 13:56:43.560989 output: Loadables: kernel-1
315 13:56:43.561042 output:
316 13:56:43.561245 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 13:56:43.561373 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 13:56:43.561492 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 13:56:43.561604 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 13:56:43.561688 No LXC device requested
321 13:56:43.561767 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:56:43.561851 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 13:56:43.561929 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:56:43.562000 Checking files for TFTP limit of 4294967296 bytes.
325 13:56:43.562506 end: 1 tftp-deploy (duration 00:00:42) [common]
326 13:56:43.562613 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:56:43.562711 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:56:43.562839 substitutions:
329 13:56:43.562909 - {DTB}: 12682960/tftp-deploy-4uofzm8x/dtb/mt8192-asurada-spherion-r0.dtb
330 13:56:43.562975 - {INITRD}: 12682960/tftp-deploy-4uofzm8x/ramdisk/ramdisk.cpio.gz
331 13:56:43.563034 - {KERNEL}: 12682960/tftp-deploy-4uofzm8x/kernel/Image
332 13:56:43.563093 - {LAVA_MAC}: None
333 13:56:43.563151 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12682960/extract-nfsrootfs-g0w8ha3y
334 13:56:43.563208 - {NFS_SERVER_IP}: 192.168.201.1
335 13:56:43.563264 - {PRESEED_CONFIG}: None
336 13:56:43.563319 - {PRESEED_LOCAL}: None
337 13:56:43.563373 - {RAMDISK}: 12682960/tftp-deploy-4uofzm8x/ramdisk/ramdisk.cpio.gz
338 13:56:43.563427 - {ROOT_PART}: None
339 13:56:43.563481 - {ROOT}: None
340 13:56:43.563535 - {SERVER_IP}: 192.168.201.1
341 13:56:43.563589 - {TEE}: None
342 13:56:43.563642 Parsed boot commands:
343 13:56:43.563694 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:56:43.563878 Parsed boot commands: tftpboot 192.168.201.1 12682960/tftp-deploy-4uofzm8x/kernel/image.itb 12682960/tftp-deploy-4uofzm8x/kernel/cmdline
345 13:56:43.563967 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:56:43.564054 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:56:43.564145 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:56:43.564230 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:56:43.564304 Not connected, no need to disconnect.
350 13:56:43.564378 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:56:43.564458 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:56:43.564526 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 13:56:43.568678 Setting prompt string to ['lava-test: # ']
354 13:56:43.569060 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:56:43.569175 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:56:43.569313 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:56:43.569494 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:56:43.569742 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 13:56:48.703491 >> Command sent successfully.
360 13:56:48.705939 Returned 0 in 5 seconds
361 13:56:48.806337 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 13:56:48.806655 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 13:56:48.806764 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 13:56:48.806855 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:56:48.806923 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:56:48.806992 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:56:48.807265 [Enter `^Ec?' for help]
369 13:56:48.980105
370 13:56:48.980236
371 13:56:48.980313 F0: 102B 0000
372 13:56:48.980378
373 13:56:48.980439 F3: 1001 0000 [0200]
374 13:56:48.980498
375 13:56:48.983758 F3: 1001 0000
376 13:56:48.983842
377 13:56:48.983908 F7: 102D 0000
378 13:56:48.983971
379 13:56:48.984032 F1: 0000 0000
380 13:56:48.984091
381 13:56:48.987406 V0: 0000 0000 [0001]
382 13:56:48.987490
383 13:56:48.987557 00: 0007 8000
384 13:56:48.987625
385 13:56:48.991199 01: 0000 0000
386 13:56:48.991311
387 13:56:48.991405 BP: 0C00 0209 [0000]
388 13:56:48.991494
389 13:56:48.991557 G0: 1182 0000
390 13:56:48.995107
391 13:56:48.995190 EC: 0000 0021 [4000]
392 13:56:48.995258
393 13:56:48.998636 S7: 0000 0000 [0000]
394 13:56:48.998720
395 13:56:48.998786 CC: 0000 0000 [0001]
396 13:56:48.998848
397 13:56:49.001973 T0: 0000 0040 [010F]
398 13:56:49.002063
399 13:56:49.002130 Jump to BL
400 13:56:49.002193
401 13:56:49.026552
402 13:56:49.026642
403 13:56:49.026709
404 13:56:49.034237 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 13:56:49.037279 ARM64: Exception handlers installed.
406 13:56:49.041169 ARM64: Testing exception
407 13:56:49.044528 ARM64: Done test exception
408 13:56:49.051804 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 13:56:49.062637 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 13:56:49.069123 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 13:56:49.079432 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 13:56:49.085953 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 13:56:49.092894 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 13:56:49.103495 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 13:56:49.110645 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 13:56:49.130200 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 13:56:49.132962 WDT: Last reset was cold boot
418 13:56:49.136549 SPI1(PAD0) initialized at 2873684 Hz
419 13:56:49.140001 SPI5(PAD0) initialized at 992727 Hz
420 13:56:49.143108 VBOOT: Loading verstage.
421 13:56:49.150100 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 13:56:49.153321 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 13:56:49.156523 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 13:56:49.159883 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 13:56:49.167610 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 13:56:49.173930 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 13:56:49.185168 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 13:56:49.185649
429 13:56:49.186005
430 13:56:49.194906 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 13:56:49.198169 ARM64: Exception handlers installed.
432 13:56:49.201471 ARM64: Testing exception
433 13:56:49.201993 ARM64: Done test exception
434 13:56:49.208403 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 13:56:49.211399 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 13:56:49.225929 Probing TPM: . done!
437 13:56:49.226359 TPM ready after 0 ms
438 13:56:49.232506 Connected to device vid:did:rid of 1ae0:0028:00
439 13:56:49.239825 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 13:56:49.278379 Initialized TPM device CR50 revision 0
441 13:56:49.290223 tlcl_send_startup: Startup return code is 0
442 13:56:49.290657 TPM: setup succeeded
443 13:56:49.301642 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 13:56:49.310664 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 13:56:49.321606 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 13:56:49.331780 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 13:56:49.335229 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 13:56:49.339870 in-header: 03 07 00 00 08 00 00 00
449 13:56:49.343121 in-data: aa e4 47 04 13 02 00 00
450 13:56:49.346407 Chrome EC: UHEPI supported
451 13:56:49.353576 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 13:56:49.357372 in-header: 03 9d 00 00 08 00 00 00
453 13:56:49.361204 in-data: 10 20 20 08 00 00 00 00
454 13:56:49.361288 Phase 1
455 13:56:49.368492 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 13:56:49.372199 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 13:56:49.379270 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 13:56:49.382743 Recovery requested (1009000e)
459 13:56:49.388732 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 13:56:49.393943 tlcl_extend: response is 0
461 13:56:49.402022 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 13:56:49.407475 tlcl_extend: response is 0
463 13:56:49.414388 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 13:56:49.435136 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 13:56:49.442446 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 13:56:49.442532
467 13:56:49.442599
468 13:56:49.450133 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 13:56:49.453802 ARM64: Exception handlers installed.
470 13:56:49.457667 ARM64: Testing exception
471 13:56:49.460899 ARM64: Done test exception
472 13:56:49.477777 pmic_efuse_setting: Set efuses in 11 msecs
473 13:56:49.485590 pmwrap_interface_init: Select PMIF_VLD_RDY
474 13:56:49.489008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 13:56:49.492646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 13:56:49.500401 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 13:56:49.504213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 13:56:49.507749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 13:56:49.515325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 13:56:49.519269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 13:56:49.522986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 13:56:49.525944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 13:56:49.532660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 13:56:49.535825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 13:56:49.542526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 13:56:49.545734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 13:56:49.552519 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 13:56:49.559370 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 13:56:49.562826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 13:56:49.569299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 13:56:49.575840 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 13:56:49.579707 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 13:56:49.586780 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 13:56:49.590717 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 13:56:49.597607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 13:56:49.604347 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 13:56:49.607791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 13:56:49.614928 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 13:56:49.618197 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 13:56:49.625210 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 13:56:49.628212 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 13:56:49.635343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 13:56:49.638680 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 13:56:49.645766 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 13:56:49.649191 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 13:56:49.652951 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 13:56:49.660268 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 13:56:49.663797 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 13:56:49.667733 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 13:56:49.674590 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 13:56:49.677935 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 13:56:49.684791 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 13:56:49.687854 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 13:56:49.691153 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 13:56:49.698109 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 13:56:49.701418 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 13:56:49.704761 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 13:56:49.711525 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 13:56:49.714638 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 13:56:49.718005 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 13:56:49.721380 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 13:56:49.727953 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 13:56:49.731373 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 13:56:49.734761 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 13:56:49.741337 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 13:56:49.751272 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 13:56:49.754861 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 13:56:49.764642 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 13:56:49.771459 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 13:56:49.778105 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 13:56:49.781262 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:56:49.784870 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 13:56:49.792621 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xf
534 13:56:49.799379 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 13:56:49.802753 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 13:56:49.806182 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 13:56:49.817427 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 13:56:49.820872 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 13:56:49.827432 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 13:56:49.830760 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 13:56:49.834281 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 13:56:49.837256 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 13:56:49.840546 ADC[4]: Raw value=895191 ID=7
544 13:56:49.844016 ADC[3]: Raw value=212700 ID=1
545 13:56:49.847193 RAM Code: 0x71
546 13:56:49.850685 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 13:56:49.854178 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 13:56:49.864395 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 13:56:49.870934 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 13:56:49.874271 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 13:56:49.877449 in-header: 03 07 00 00 08 00 00 00
552 13:56:49.880891 in-data: aa e4 47 04 13 02 00 00
553 13:56:49.884391 Chrome EC: UHEPI supported
554 13:56:49.887966 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 13:56:49.892829 in-header: 03 d5 00 00 08 00 00 00
556 13:56:49.896203 in-data: 98 20 60 08 00 00 00 00
557 13:56:49.900096 MRC: failed to locate region type 0.
558 13:56:49.906619 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 13:56:49.909887 DRAM-K: Running full calibration
560 13:56:49.916721 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 13:56:49.916805 header.status = 0x0
562 13:56:49.920103 header.version = 0x6 (expected: 0x6)
563 13:56:49.923541 header.size = 0xd00 (expected: 0xd00)
564 13:56:49.927396 header.flags = 0x0
565 13:56:49.930792 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 13:56:49.949740 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
567 13:56:49.956350 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 13:56:49.959746 dram_init: ddr_geometry: 2
569 13:56:49.959829 [EMI] MDL number = 2
570 13:56:49.963227 [EMI] Get MDL freq = 0
571 13:56:49.966303 dram_init: ddr_type: 0
572 13:56:49.966386 is_discrete_lpddr4: 1
573 13:56:49.969813 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 13:56:49.969896
575 13:56:49.969962
576 13:56:49.973187 [Bian_co] ETT version 0.0.0.1
577 13:56:49.979812 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 13:56:49.979895
579 13:56:49.983045 dramc_set_vcore_voltage set vcore to 650000
580 13:56:49.983128 Read voltage for 800, 4
581 13:56:49.986234 Vio18 = 0
582 13:56:49.986316 Vcore = 650000
583 13:56:49.986382 Vdram = 0
584 13:56:49.989858 Vddq = 0
585 13:56:49.989942 Vmddr = 0
586 13:56:49.993101 dram_init: config_dvfs: 1
587 13:56:49.996215 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 13:56:50.003150 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 13:56:50.006602 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 13:56:50.009744 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 13:56:50.012983 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 13:56:50.016322 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 13:56:50.019662 MEM_TYPE=3, freq_sel=18
594 13:56:50.022839 sv_algorithm_assistance_LP4_1600
595 13:56:50.026195 ============ PULL DRAM RESETB DOWN ============
596 13:56:50.029745 ========== PULL DRAM RESETB DOWN end =========
597 13:56:50.036283 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 13:56:50.039518 ===================================
599 13:56:50.042877 LPDDR4 DRAM CONFIGURATION
600 13:56:50.046331 ===================================
601 13:56:50.046411 EX_ROW_EN[0] = 0x0
602 13:56:50.049586 EX_ROW_EN[1] = 0x0
603 13:56:50.049661 LP4Y_EN = 0x0
604 13:56:50.052964 WORK_FSP = 0x0
605 13:56:50.053055 WL = 0x2
606 13:56:50.056372 RL = 0x2
607 13:56:50.056449 BL = 0x2
608 13:56:50.059607 RPST = 0x0
609 13:56:50.059690 RD_PRE = 0x0
610 13:56:50.062829 WR_PRE = 0x1
611 13:56:50.062912 WR_PST = 0x0
612 13:56:50.066058 DBI_WR = 0x0
613 13:56:50.066141 DBI_RD = 0x0
614 13:56:50.069440 OTF = 0x1
615 13:56:50.072877 ===================================
616 13:56:50.076461 ===================================
617 13:56:50.076544 ANA top config
618 13:56:50.079748 ===================================
619 13:56:50.083012 DLL_ASYNC_EN = 0
620 13:56:50.086116 ALL_SLAVE_EN = 1
621 13:56:50.089400 NEW_RANK_MODE = 1
622 13:56:50.089515 DLL_IDLE_MODE = 1
623 13:56:50.092774 LP45_APHY_COMB_EN = 1
624 13:56:50.096649 TX_ODT_DIS = 1
625 13:56:50.100181 NEW_8X_MODE = 1
626 13:56:50.103941 ===================================
627 13:56:50.104025 ===================================
628 13:56:50.107426 data_rate = 1600
629 13:56:50.111256 CKR = 1
630 13:56:50.115688 DQ_P2S_RATIO = 8
631 13:56:50.115774 ===================================
632 13:56:50.119029 CA_P2S_RATIO = 8
633 13:56:50.122801 DQ_CA_OPEN = 0
634 13:56:50.126583 DQ_SEMI_OPEN = 0
635 13:56:50.126667 CA_SEMI_OPEN = 0
636 13:56:50.130100 CA_FULL_RATE = 0
637 13:56:50.133955 DQ_CKDIV4_EN = 1
638 13:56:50.137751 CA_CKDIV4_EN = 1
639 13:56:50.137831 CA_PREDIV_EN = 0
640 13:56:50.141558 PH8_DLY = 0
641 13:56:50.145235 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 13:56:50.148942 DQ_AAMCK_DIV = 4
643 13:56:50.149026 CA_AAMCK_DIV = 4
644 13:56:50.152793 CA_ADMCK_DIV = 4
645 13:56:50.156454 DQ_TRACK_CA_EN = 0
646 13:56:50.160006 CA_PICK = 800
647 13:56:50.160082 CA_MCKIO = 800
648 13:56:50.163606 MCKIO_SEMI = 0
649 13:56:50.167315 PLL_FREQ = 3068
650 13:56:50.171219 DQ_UI_PI_RATIO = 32
651 13:56:50.171300 CA_UI_PI_RATIO = 0
652 13:56:50.175054 ===================================
653 13:56:50.178982 ===================================
654 13:56:50.182422 memory_type:LPDDR4
655 13:56:50.182504 GP_NUM : 10
656 13:56:50.186126 SRAM_EN : 1
657 13:56:50.189182 MD32_EN : 0
658 13:56:50.192441 ===================================
659 13:56:50.192551 [ANA_INIT] >>>>>>>>>>>>>>
660 13:56:50.195798 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 13:56:50.199393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 13:56:50.202633 ===================================
663 13:56:50.205675 data_rate = 1600,PCW = 0X7600
664 13:56:50.209328 ===================================
665 13:56:50.212644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 13:56:50.218996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 13:56:50.222434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 13:56:50.229233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 13:56:50.232975 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 13:56:50.236666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 13:56:50.236746 [ANA_INIT] flow start
672 13:56:50.240360 [ANA_INIT] PLL >>>>>>>>
673 13:56:50.240438 [ANA_INIT] PLL <<<<<<<<
674 13:56:50.243948 [ANA_INIT] MIDPI >>>>>>>>
675 13:56:50.247694 [ANA_INIT] MIDPI <<<<<<<<
676 13:56:50.247800 [ANA_INIT] DLL >>>>>>>>
677 13:56:50.251056 [ANA_INIT] flow end
678 13:56:50.255125 ============ LP4 DIFF to SE enter ============
679 13:56:50.258854 ============ LP4 DIFF to SE exit ============
680 13:56:50.262421 [ANA_INIT] <<<<<<<<<<<<<
681 13:56:50.266147 [Flow] Enable top DCM control >>>>>
682 13:56:50.266231 [Flow] Enable top DCM control <<<<<
683 13:56:50.270382 Enable DLL master slave shuffle
684 13:56:50.277292 ==============================================================
685 13:56:50.277376 Gating Mode config
686 13:56:50.284388 ==============================================================
687 13:56:50.284471 Config description:
688 13:56:50.294236 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 13:56:50.300759 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 13:56:50.307636 SELPH_MODE 0: By rank 1: By Phase
691 13:56:50.310874 ==============================================================
692 13:56:50.314506 GAT_TRACK_EN = 1
693 13:56:50.317497 RX_GATING_MODE = 2
694 13:56:50.320852 RX_GATING_TRACK_MODE = 2
695 13:56:50.324309 SELPH_MODE = 1
696 13:56:50.327543 PICG_EARLY_EN = 1
697 13:56:50.330952 VALID_LAT_VALUE = 1
698 13:56:50.334342 ==============================================================
699 13:56:50.337386 Enter into Gating configuration >>>>
700 13:56:50.340644 Exit from Gating configuration <<<<
701 13:56:50.344070 Enter into DVFS_PRE_config >>>>>
702 13:56:50.357453 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 13:56:50.360664 Exit from DVFS_PRE_config <<<<<
704 13:56:50.363956 Enter into PICG configuration >>>>
705 13:56:50.367387 Exit from PICG configuration <<<<
706 13:56:50.367470 [RX_INPUT] configuration >>>>>
707 13:56:50.370897 [RX_INPUT] configuration <<<<<
708 13:56:50.377100 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 13:56:50.380523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 13:56:50.387163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 13:56:50.393775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 13:56:50.400587 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 13:56:50.407260 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 13:56:50.410508 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 13:56:50.413904 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 13:56:50.417278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 13:56:50.423963 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 13:56:50.427454 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 13:56:50.430600 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 13:56:50.433734 ===================================
721 13:56:50.436988 LPDDR4 DRAM CONFIGURATION
722 13:56:50.440359 ===================================
723 13:56:50.443851 EX_ROW_EN[0] = 0x0
724 13:56:50.443934 EX_ROW_EN[1] = 0x0
725 13:56:50.446911 LP4Y_EN = 0x0
726 13:56:50.447033 WORK_FSP = 0x0
727 13:56:50.450479 WL = 0x2
728 13:56:50.450562 RL = 0x2
729 13:56:50.453749 BL = 0x2
730 13:56:50.453833 RPST = 0x0
731 13:56:50.456998 RD_PRE = 0x0
732 13:56:50.457081 WR_PRE = 0x1
733 13:56:50.460333 WR_PST = 0x0
734 13:56:50.460416 DBI_WR = 0x0
735 13:56:50.463631 DBI_RD = 0x0
736 13:56:50.463714 OTF = 0x1
737 13:56:50.467347 ===================================
738 13:56:50.473810 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 13:56:50.477128 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 13:56:50.480495 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 13:56:50.483772 ===================================
742 13:56:50.487485 LPDDR4 DRAM CONFIGURATION
743 13:56:50.490561 ===================================
744 13:56:50.490644 EX_ROW_EN[0] = 0x10
745 13:56:50.493680 EX_ROW_EN[1] = 0x0
746 13:56:50.497072 LP4Y_EN = 0x0
747 13:56:50.497154 WORK_FSP = 0x0
748 13:56:50.500410 WL = 0x2
749 13:56:50.500493 RL = 0x2
750 13:56:50.503814 BL = 0x2
751 13:56:50.503897 RPST = 0x0
752 13:56:50.507197 RD_PRE = 0x0
753 13:56:50.507280 WR_PRE = 0x1
754 13:56:50.510639 WR_PST = 0x0
755 13:56:50.510722 DBI_WR = 0x0
756 13:56:50.513633 DBI_RD = 0x0
757 13:56:50.513716 OTF = 0x1
758 13:56:50.517055 ===================================
759 13:56:50.523473 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 13:56:50.528183 nWR fixed to 40
761 13:56:50.531546 [ModeRegInit_LP4] CH0 RK0
762 13:56:50.531629 [ModeRegInit_LP4] CH0 RK1
763 13:56:50.534712 [ModeRegInit_LP4] CH1 RK0
764 13:56:50.537941 [ModeRegInit_LP4] CH1 RK1
765 13:56:50.538025 match AC timing 13
766 13:56:50.544728 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 13:56:50.548063 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 13:56:50.551262 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 13:56:50.558238 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 13:56:50.561210 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 13:56:50.561294 [EMI DOE] emi_dcm 0
772 13:56:50.568173 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 13:56:50.568258 ==
774 13:56:50.571476 Dram Type= 6, Freq= 0, CH_0, rank 0
775 13:56:50.574680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 13:56:50.574763 ==
777 13:56:50.581377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 13:56:50.587851 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 13:56:50.595529 [CA 0] Center 38 (7~69) winsize 63
780 13:56:50.598770 [CA 1] Center 37 (7~68) winsize 62
781 13:56:50.602188 [CA 2] Center 35 (5~66) winsize 62
782 13:56:50.605640 [CA 3] Center 35 (5~66) winsize 62
783 13:56:50.608727 [CA 4] Center 34 (4~65) winsize 62
784 13:56:50.612767 [CA 5] Center 34 (4~65) winsize 62
785 13:56:50.612850
786 13:56:50.615936 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 13:56:50.616019
788 13:56:50.619465 [CATrainingPosCal] consider 1 rank data
789 13:56:50.623308 u2DelayCellTimex100 = 270/100 ps
790 13:56:50.626859 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 13:56:50.630729 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 13:56:50.634524 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 13:56:50.638235 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 13:56:50.642102 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 13:56:50.645748 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 13:56:50.645831
797 13:56:50.649155 CA PerBit enable=1, Macro0, CA PI delay=34
798 13:56:50.649247
799 13:56:50.652901 [CBTSetCACLKResult] CA Dly = 34
800 13:56:50.652985 CS Dly: 6 (0~37)
801 13:56:50.653073 ==
802 13:56:50.656293 Dram Type= 6, Freq= 0, CH_0, rank 1
803 13:56:50.659813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 13:56:50.659891 ==
805 13:56:50.667026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 13:56:50.674362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 13:56:50.682021 [CA 0] Center 38 (7~69) winsize 63
808 13:56:50.685849 [CA 1] Center 37 (7~68) winsize 62
809 13:56:50.689861 [CA 2] Center 35 (5~66) winsize 62
810 13:56:50.693228 [CA 3] Center 35 (5~66) winsize 62
811 13:56:50.696792 [CA 4] Center 34 (4~65) winsize 62
812 13:56:50.700257 [CA 5] Center 34 (4~65) winsize 62
813 13:56:50.700333
814 13:56:50.704062 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 13:56:50.704142
816 13:56:50.707793 [CATrainingPosCal] consider 2 rank data
817 13:56:50.707874 u2DelayCellTimex100 = 270/100 ps
818 13:56:50.711663 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 13:56:50.715149 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 13:56:50.718707 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 13:56:50.722445 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 13:56:50.726484 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 13:56:50.729816 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 13:56:50.729897
825 13:56:50.733636 CA PerBit enable=1, Macro0, CA PI delay=34
826 13:56:50.733714
827 13:56:50.737039 [CBTSetCACLKResult] CA Dly = 34
828 13:56:50.740821 CS Dly: 6 (0~38)
829 13:56:50.740903
830 13:56:50.744478 ----->DramcWriteLeveling(PI) begin...
831 13:56:50.744556 ==
832 13:56:50.748202 Dram Type= 6, Freq= 0, CH_0, rank 0
833 13:56:50.752042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 13:56:50.752134 ==
835 13:56:50.755475 Write leveling (Byte 0): 34 => 34
836 13:56:50.759379 Write leveling (Byte 1): 29 => 29
837 13:56:50.759463 DramcWriteLeveling(PI) end<-----
838 13:56:50.759529
839 13:56:50.759591 ==
840 13:56:50.762771 Dram Type= 6, Freq= 0, CH_0, rank 0
841 13:56:50.766464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 13:56:50.770217 ==
843 13:56:50.770300 [Gating] SW mode calibration
844 13:56:50.777857 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 13:56:50.785019 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 13:56:50.788791 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 13:56:50.792437 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 13:56:50.795993 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 13:56:50.799769 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 13:56:50.807177 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 13:56:50.810828 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 13:56:50.814594 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 13:56:50.817763 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:56:50.821665 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:56:50.828811 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:56:50.832659 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:56:50.836456 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:56:50.840025 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:56:50.843664 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:56:50.851130 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:56:50.854499 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:56:50.857798 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:56:50.861778 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:56:50.865106 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
865 13:56:50.872713 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
866 13:56:50.876299 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
867 13:56:50.879591 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 13:56:50.883421 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 13:56:50.886774 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 13:56:50.894389 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 13:56:50.898006 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 13:56:50.901765 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
873 13:56:50.906028 0 9 12 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
874 13:56:50.909472 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 13:56:50.916676 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 13:56:50.920330 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 13:56:50.924077 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 13:56:50.927648 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 13:56:50.931125 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 13:56:50.938420 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
881 13:56:50.941887 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
882 13:56:50.944883 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 13:56:50.951573 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 13:56:50.955126 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 13:56:50.958435 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 13:56:50.961769 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 13:56:50.968231 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 13:56:50.971798 0 11 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
889 13:56:50.974743 0 11 12 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
890 13:56:50.981719 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 13:56:50.984902 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 13:56:50.988406 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 13:56:50.994767 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 13:56:50.998255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 13:56:51.001811 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 13:56:51.008434 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 13:56:51.011465 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 13:56:51.014905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 13:56:51.021441 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 13:56:51.024869 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 13:56:51.028214 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 13:56:51.034681 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:56:51.038324 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:56:51.041500 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:56:51.047996 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:56:51.051509 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:56:51.054896 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:56:51.061758 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:56:51.064831 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:56:51.068134 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:56:51.071800 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:56:51.078525 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 13:56:51.081607 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
914 13:56:51.084967 Total UI for P1: 0, mck2ui 16
915 13:56:51.088626 best dqsien dly found for B0: ( 0, 14, 8)
916 13:56:51.091933 Total UI for P1: 0, mck2ui 16
917 13:56:51.095155 best dqsien dly found for B1: ( 0, 14, 10)
918 13:56:51.098240 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
919 13:56:51.101588 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
920 13:56:51.101663
921 13:56:51.105031 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
922 13:56:51.108429 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
923 13:56:51.111661 [Gating] SW calibration Done
924 13:56:51.111741 ==
925 13:56:51.115214 Dram Type= 6, Freq= 0, CH_0, rank 0
926 13:56:51.118515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 13:56:51.121464 ==
928 13:56:51.121578 RX Vref Scan: 0
929 13:56:51.121660
930 13:56:51.124960 RX Vref 0 -> 0, step: 1
931 13:56:51.125035
932 13:56:51.128235 RX Delay -130 -> 252, step: 16
933 13:56:51.131636 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
934 13:56:51.134815 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
935 13:56:51.138371 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
936 13:56:51.141788 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
937 13:56:51.148454 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
938 13:56:51.151638 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
939 13:56:51.154975 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
940 13:56:51.158623 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
941 13:56:51.161935 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
942 13:56:51.168466 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
943 13:56:51.171736 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
944 13:56:51.175354 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
945 13:56:51.178310 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
946 13:56:51.181726 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
947 13:56:51.188583 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
948 13:56:51.191606 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
949 13:56:51.191681 ==
950 13:56:51.194914 Dram Type= 6, Freq= 0, CH_0, rank 0
951 13:56:51.198324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 13:56:51.198399 ==
953 13:56:51.201766 DQS Delay:
954 13:56:51.201843 DQS0 = 0, DQS1 = 0
955 13:56:51.201926 DQM Delay:
956 13:56:51.205136 DQM0 = 81, DQM1 = 69
957 13:56:51.205251 DQ Delay:
958 13:56:51.208658 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
959 13:56:51.211670 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
960 13:56:51.215085 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
961 13:56:51.218657 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
962 13:56:51.218734
963 13:56:51.218815
964 13:56:51.218892 ==
965 13:56:51.221910 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:56:51.225486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:56:51.225561 ==
968 13:56:51.225645
969 13:56:51.229096
970 13:56:51.229168 TX Vref Scan disable
971 13:56:51.232488 == TX Byte 0 ==
972 13:56:51.235521 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
973 13:56:51.239116 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
974 13:56:51.242310 == TX Byte 1 ==
975 13:56:51.245757 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 13:56:51.249068 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 13:56:51.249152 ==
978 13:56:51.252461 Dram Type= 6, Freq= 0, CH_0, rank 0
979 13:56:51.258813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 13:56:51.258894 ==
981 13:56:51.271194 TX Vref=22, minBit 14, minWin=26, winSum=433
982 13:56:51.274722 TX Vref=24, minBit 11, minWin=26, winSum=438
983 13:56:51.278107 TX Vref=26, minBit 5, minWin=27, winSum=445
984 13:56:51.281280 TX Vref=28, minBit 5, minWin=27, winSum=444
985 13:56:51.284472 TX Vref=30, minBit 4, minWin=27, winSum=443
986 13:56:51.291204 TX Vref=32, minBit 9, minWin=26, winSum=440
987 13:56:51.294698 [TxChooseVref] Worse bit 5, Min win 27, Win sum 445, Final Vref 26
988 13:56:51.294914
989 13:56:51.297970 Final TX Range 1 Vref 26
990 13:56:51.298143
991 13:56:51.298280 ==
992 13:56:51.301687 Dram Type= 6, Freq= 0, CH_0, rank 0
993 13:56:51.305037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 13:56:51.305463 ==
995 13:56:51.306143
996 13:56:51.308072
997 13:56:51.308422 TX Vref Scan disable
998 13:56:51.311687 == TX Byte 0 ==
999 13:56:51.315032 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1000 13:56:51.318464 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1001 13:56:51.321707 == TX Byte 1 ==
1002 13:56:51.324862 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1003 13:56:51.328322 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1004 13:56:51.331727
1005 13:56:51.332146 [DATLAT]
1006 13:56:51.332478 Freq=800, CH0 RK0
1007 13:56:51.332792
1008 13:56:51.335053 DATLAT Default: 0xa
1009 13:56:51.335473 0, 0xFFFF, sum = 0
1010 13:56:51.338507 1, 0xFFFF, sum = 0
1011 13:56:51.338947 2, 0xFFFF, sum = 0
1012 13:56:51.343706 3, 0xFFFF, sum = 0
1013 13:56:51.343789 4, 0xFFFF, sum = 0
1014 13:56:51.344653 5, 0xFFFF, sum = 0
1015 13:56:51.347808 6, 0xFFFF, sum = 0
1016 13:56:51.347892 7, 0xFFFF, sum = 0
1017 13:56:51.351409 8, 0xFFFF, sum = 0
1018 13:56:51.351498 9, 0x0, sum = 1
1019 13:56:51.351569 10, 0x0, sum = 2
1020 13:56:51.354632 11, 0x0, sum = 3
1021 13:56:51.354727 12, 0x0, sum = 4
1022 13:56:51.358008 best_step = 10
1023 13:56:51.358107
1024 13:56:51.358185 ==
1025 13:56:51.361594 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 13:56:51.364815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 13:56:51.364926 ==
1028 13:56:51.368213 RX Vref Scan: 1
1029 13:56:51.368322
1030 13:56:51.368409 Set Vref Range= 32 -> 127
1031 13:56:51.368491
1032 13:56:51.371652 RX Vref 32 -> 127, step: 1
1033 13:56:51.371732
1034 13:56:51.374833 RX Delay -111 -> 252, step: 8
1035 13:56:51.374914
1036 13:56:51.378193 Set Vref, RX VrefLevel [Byte0]: 32
1037 13:56:51.381348 [Byte1]: 32
1038 13:56:51.381429
1039 13:56:51.384681 Set Vref, RX VrefLevel [Byte0]: 33
1040 13:56:51.388050 [Byte1]: 33
1041 13:56:51.391633
1042 13:56:51.391713 Set Vref, RX VrefLevel [Byte0]: 34
1043 13:56:51.395295 [Byte1]: 34
1044 13:56:51.399608
1045 13:56:51.399688 Set Vref, RX VrefLevel [Byte0]: 35
1046 13:56:51.402831 [Byte1]: 35
1047 13:56:51.406924
1048 13:56:51.407005 Set Vref, RX VrefLevel [Byte0]: 36
1049 13:56:51.410378 [Byte1]: 36
1050 13:56:51.414760
1051 13:56:51.414843 Set Vref, RX VrefLevel [Byte0]: 37
1052 13:56:51.418016 [Byte1]: 37
1053 13:56:51.422221
1054 13:56:51.422301 Set Vref, RX VrefLevel [Byte0]: 38
1055 13:56:51.425714 [Byte1]: 38
1056 13:56:51.429949
1057 13:56:51.430029 Set Vref, RX VrefLevel [Byte0]: 39
1058 13:56:51.433107 [Byte1]: 39
1059 13:56:51.437744
1060 13:56:51.437825 Set Vref, RX VrefLevel [Byte0]: 40
1061 13:56:51.440736 [Byte1]: 40
1062 13:56:51.445371
1063 13:56:51.445440 Set Vref, RX VrefLevel [Byte0]: 41
1064 13:56:51.448462 [Byte1]: 41
1065 13:56:51.452967
1066 13:56:51.453036 Set Vref, RX VrefLevel [Byte0]: 42
1067 13:56:51.456163 [Byte1]: 42
1068 13:56:51.460531
1069 13:56:51.460605 Set Vref, RX VrefLevel [Byte0]: 43
1070 13:56:51.463825 [Byte1]: 43
1071 13:56:51.468063
1072 13:56:51.468137 Set Vref, RX VrefLevel [Byte0]: 44
1073 13:56:51.471352 [Byte1]: 44
1074 13:56:51.475767
1075 13:56:51.475839 Set Vref, RX VrefLevel [Byte0]: 45
1076 13:56:51.479196 [Byte1]: 45
1077 13:56:51.483845
1078 13:56:51.483914 Set Vref, RX VrefLevel [Byte0]: 46
1079 13:56:51.486920 [Byte1]: 46
1080 13:56:51.491070
1081 13:56:51.491139 Set Vref, RX VrefLevel [Byte0]: 47
1082 13:56:51.494376 [Byte1]: 47
1083 13:56:51.499214
1084 13:56:51.499287 Set Vref, RX VrefLevel [Byte0]: 48
1085 13:56:51.502610 [Byte1]: 48
1086 13:56:51.506931
1087 13:56:51.507010 Set Vref, RX VrefLevel [Byte0]: 49
1088 13:56:51.510155 [Byte1]: 49
1089 13:56:51.514282
1090 13:56:51.514355 Set Vref, RX VrefLevel [Byte0]: 50
1091 13:56:51.517657 [Byte1]: 50
1092 13:56:51.521792
1093 13:56:51.521865 Set Vref, RX VrefLevel [Byte0]: 51
1094 13:56:51.525154 [Byte1]: 51
1095 13:56:51.529426
1096 13:56:51.529558 Set Vref, RX VrefLevel [Byte0]: 52
1097 13:56:51.532738 [Byte1]: 52
1098 13:56:51.537070
1099 13:56:51.537143 Set Vref, RX VrefLevel [Byte0]: 53
1100 13:56:51.540139 [Byte1]: 53
1101 13:56:51.544972
1102 13:56:51.545052 Set Vref, RX VrefLevel [Byte0]: 54
1103 13:56:51.547899 [Byte1]: 54
1104 13:56:51.552221
1105 13:56:51.552302 Set Vref, RX VrefLevel [Byte0]: 55
1106 13:56:51.555759 [Byte1]: 55
1107 13:56:51.559895
1108 13:56:51.559974 Set Vref, RX VrefLevel [Byte0]: 56
1109 13:56:51.563463 [Byte1]: 56
1110 13:56:51.567736
1111 13:56:51.567816 Set Vref, RX VrefLevel [Byte0]: 57
1112 13:56:51.571040 [Byte1]: 57
1113 13:56:51.575326
1114 13:56:51.575405 Set Vref, RX VrefLevel [Byte0]: 58
1115 13:56:51.578562 [Byte1]: 58
1116 13:56:51.582789
1117 13:56:51.582869 Set Vref, RX VrefLevel [Byte0]: 59
1118 13:56:51.586318 [Byte1]: 59
1119 13:56:51.590445
1120 13:56:51.590525 Set Vref, RX VrefLevel [Byte0]: 60
1121 13:56:51.593904 [Byte1]: 60
1122 13:56:51.598204
1123 13:56:51.598284 Set Vref, RX VrefLevel [Byte0]: 61
1124 13:56:51.601669 [Byte1]: 61
1125 13:56:51.605725
1126 13:56:51.605805 Set Vref, RX VrefLevel [Byte0]: 62
1127 13:56:51.609202 [Byte1]: 62
1128 13:56:51.613259
1129 13:56:51.613365 Set Vref, RX VrefLevel [Byte0]: 63
1130 13:56:51.616748 [Byte1]: 63
1131 13:56:51.621235
1132 13:56:51.621342 Set Vref, RX VrefLevel [Byte0]: 64
1133 13:56:51.624362 [Byte1]: 64
1134 13:56:51.628724
1135 13:56:51.628804 Set Vref, RX VrefLevel [Byte0]: 65
1136 13:56:51.632109 [Byte1]: 65
1137 13:56:51.636381
1138 13:56:51.636461 Set Vref, RX VrefLevel [Byte0]: 66
1139 13:56:51.639828 [Byte1]: 66
1140 13:56:51.644117
1141 13:56:51.644197 Set Vref, RX VrefLevel [Byte0]: 67
1142 13:56:51.647211 [Byte1]: 67
1143 13:56:51.651725
1144 13:56:51.651806 Set Vref, RX VrefLevel [Byte0]: 68
1145 13:56:51.654932 [Byte1]: 68
1146 13:56:51.659139
1147 13:56:51.659209 Set Vref, RX VrefLevel [Byte0]: 69
1148 13:56:51.662613 [Byte1]: 69
1149 13:56:51.666871
1150 13:56:51.666938 Set Vref, RX VrefLevel [Byte0]: 70
1151 13:56:51.670509 [Byte1]: 70
1152 13:56:51.674472
1153 13:56:51.674539 Set Vref, RX VrefLevel [Byte0]: 71
1154 13:56:51.678111 [Byte1]: 71
1155 13:56:51.682243
1156 13:56:51.682309 Set Vref, RX VrefLevel [Byte0]: 72
1157 13:56:51.685465 [Byte1]: 72
1158 13:56:51.689972
1159 13:56:51.690042 Set Vref, RX VrefLevel [Byte0]: 73
1160 13:56:51.693003 [Byte1]: 73
1161 13:56:51.697736
1162 13:56:51.697805 Set Vref, RX VrefLevel [Byte0]: 74
1163 13:56:51.700646 [Byte1]: 74
1164 13:56:51.705028
1165 13:56:51.705126 Set Vref, RX VrefLevel [Byte0]: 75
1166 13:56:51.708525 [Byte1]: 75
1167 13:56:51.712916
1168 13:56:51.712987 Set Vref, RX VrefLevel [Byte0]: 76
1169 13:56:51.716267 [Byte1]: 76
1170 13:56:51.720327
1171 13:56:51.720396 Set Vref, RX VrefLevel [Byte0]: 77
1172 13:56:51.723822 [Byte1]: 77
1173 13:56:51.727993
1174 13:56:51.728059 Set Vref, RX VrefLevel [Byte0]: 78
1175 13:56:51.731568 [Byte1]: 78
1176 13:56:51.735606
1177 13:56:51.735679 Set Vref, RX VrefLevel [Byte0]: 79
1178 13:56:51.739023 [Byte1]: 79
1179 13:56:51.743590
1180 13:56:51.743665 Final RX Vref Byte 0 = 62 to rank0
1181 13:56:51.746763 Final RX Vref Byte 1 = 58 to rank0
1182 13:56:51.750025 Final RX Vref Byte 0 = 62 to rank1
1183 13:56:51.753239 Final RX Vref Byte 1 = 58 to rank1==
1184 13:56:51.756676 Dram Type= 6, Freq= 0, CH_0, rank 0
1185 13:56:51.763144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1186 13:56:51.763218 ==
1187 13:56:51.763280 DQS Delay:
1188 13:56:51.766594 DQS0 = 0, DQS1 = 0
1189 13:56:51.766664 DQM Delay:
1190 13:56:51.766722 DQM0 = 81, DQM1 = 67
1191 13:56:51.769825 DQ Delay:
1192 13:56:51.773366 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1193 13:56:51.776572 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1194 13:56:51.779830 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1195 13:56:51.783329 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1196 13:56:51.783396
1197 13:56:51.783453
1198 13:56:51.789669 [DQSOSCAuto] RK0, (LSB)MR18= 0x2725, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1199 13:56:51.793153 CH0 RK0: MR19=606, MR18=2725
1200 13:56:51.800104 CH0_RK0: MR19=0x606, MR18=0x2725, DQSOSC=400, MR23=63, INC=92, DEC=61
1201 13:56:51.800185
1202 13:56:51.803399 ----->DramcWriteLeveling(PI) begin...
1203 13:56:51.803469 ==
1204 13:56:51.806478 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 13:56:51.809945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 13:56:51.810023 ==
1207 13:56:51.813324 Write leveling (Byte 0): 31 => 31
1208 13:56:51.816399 Write leveling (Byte 1): 28 => 28
1209 13:56:51.819917 DramcWriteLeveling(PI) end<-----
1210 13:56:51.819988
1211 13:56:51.820048 ==
1212 13:56:51.823466 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 13:56:51.826380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1214 13:56:51.826450 ==
1215 13:56:51.829806 [Gating] SW mode calibration
1216 13:56:51.836681 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1217 13:56:51.843317 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1218 13:56:51.846633 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1219 13:56:51.849727 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 13:56:51.856364 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1221 13:56:51.859636 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:56:51.863173 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 13:56:51.869930 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:56:51.873220 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:56:51.876572 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:56:51.882988 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:56:51.886392 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:56:51.889948 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:56:51.896384 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:56:51.899720 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:56:51.903000 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 13:56:51.946773 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 13:56:51.947042 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 13:56:51.947116 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 13:56:51.947196 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 13:56:51.947258 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1237 13:56:51.947327 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1238 13:56:51.947396 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 13:56:51.947466 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:56:51.947716 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:56:51.947777 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 13:56:51.957972 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 13:56:51.961012 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1244 13:56:51.964502 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1245 13:56:51.967847 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1246 13:56:51.971138 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 13:56:51.974608 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 13:56:51.977880 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 13:56:51.984508 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 13:56:51.987745 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 13:56:51.991064 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1252 13:56:51.997753 0 10 8 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (1 0)
1253 13:56:52.001216 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1254 13:56:52.004625 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 13:56:52.008080 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 13:56:52.014654 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 13:56:52.017930 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 13:56:52.021242 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 13:56:52.028073 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
1260 13:56:52.031126 0 11 8 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
1261 13:56:52.034685 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1262 13:56:52.041405 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 13:56:52.044952 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 13:56:52.047887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 13:56:52.054866 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 13:56:52.058312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 13:56:52.061735 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 13:56:52.065755 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1269 13:56:52.069027 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1270 13:56:52.076506 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 13:56:52.079516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 13:56:52.082943 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 13:56:52.089993 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 13:56:52.093076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 13:56:52.096495 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 13:56:52.103264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 13:56:52.106561 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 13:56:52.109891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 13:56:52.113206 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 13:56:52.119863 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 13:56:52.123177 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 13:56:52.126848 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 13:56:52.133323 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 13:56:52.136737 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1285 13:56:52.140192 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 13:56:52.143126 Total UI for P1: 0, mck2ui 16
1287 13:56:52.146626 best dqsien dly found for B0: ( 0, 14, 8)
1288 13:56:52.150205 Total UI for P1: 0, mck2ui 16
1289 13:56:52.153197 best dqsien dly found for B1: ( 0, 14, 8)
1290 13:56:52.156602 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1291 13:56:52.160278 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1292 13:56:52.160349
1293 13:56:52.166707 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1294 13:56:52.169923 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1295 13:56:52.169998 [Gating] SW calibration Done
1296 13:56:52.173254 ==
1297 13:56:52.173322 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 13:56:52.179870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 13:56:52.179941 ==
1300 13:56:52.180000 RX Vref Scan: 0
1301 13:56:52.180059
1302 13:56:52.183390 RX Vref 0 -> 0, step: 1
1303 13:56:52.183456
1304 13:56:52.186491 RX Delay -130 -> 252, step: 16
1305 13:56:52.189939 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1306 13:56:52.193409 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1307 13:56:52.196422 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1308 13:56:52.203327 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1309 13:56:52.206722 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1310 13:56:52.209722 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1311 13:56:52.213424 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1312 13:56:52.216432 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1313 13:56:52.223193 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1314 13:56:52.226447 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1315 13:56:52.229868 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1316 13:56:52.233331 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1317 13:56:52.236329 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1318 13:56:52.243094 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1319 13:56:52.246501 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1320 13:56:52.250080 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1321 13:56:52.250153 ==
1322 13:56:52.253242 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 13:56:52.256387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 13:56:52.256456 ==
1325 13:56:52.259881 DQS Delay:
1326 13:56:52.259950 DQS0 = 0, DQS1 = 0
1327 13:56:52.263252 DQM Delay:
1328 13:56:52.263320 DQM0 = 80, DQM1 = 69
1329 13:56:52.263379 DQ Delay:
1330 13:56:52.266460 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1331 13:56:52.269737 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1332 13:56:52.272972 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1333 13:56:52.276459 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1334 13:56:52.276528
1335 13:56:52.276587
1336 13:56:52.279763 ==
1337 13:56:52.283186 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 13:56:52.286406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 13:56:52.286481 ==
1340 13:56:52.286546
1341 13:56:52.286607
1342 13:56:52.289911 TX Vref Scan disable
1343 13:56:52.289979 == TX Byte 0 ==
1344 13:56:52.292929 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1345 13:56:52.299990 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1346 13:56:52.300072 == TX Byte 1 ==
1347 13:56:52.303014 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1348 13:56:52.309759 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1349 13:56:52.309841 ==
1350 13:56:52.313082 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 13:56:52.316488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 13:56:52.316569 ==
1353 13:56:52.329962 TX Vref=22, minBit 1, minWin=27, winSum=439
1354 13:56:52.333033 TX Vref=24, minBit 1, minWin=27, winSum=441
1355 13:56:52.336371 TX Vref=26, minBit 1, minWin=27, winSum=446
1356 13:56:52.339722 TX Vref=28, minBit 1, minWin=27, winSum=445
1357 13:56:52.343318 TX Vref=30, minBit 14, minWin=27, winSum=451
1358 13:56:52.349883 TX Vref=32, minBit 14, minWin=27, winSum=448
1359 13:56:52.352985 [TxChooseVref] Worse bit 14, Min win 27, Win sum 451, Final Vref 30
1360 13:56:52.353098
1361 13:56:52.356512 Final TX Range 1 Vref 30
1362 13:56:52.356597
1363 13:56:52.356660 ==
1364 13:56:52.359758 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 13:56:52.363201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 13:56:52.366293 ==
1367 13:56:52.366373
1368 13:56:52.366436
1369 13:56:52.366495 TX Vref Scan disable
1370 13:56:52.370158 == TX Byte 0 ==
1371 13:56:52.373532 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1372 13:56:52.379779 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1373 13:56:52.379860 == TX Byte 1 ==
1374 13:56:52.383431 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1375 13:56:52.386915 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1376 13:56:52.390158
1377 13:56:52.390237 [DATLAT]
1378 13:56:52.390301 Freq=800, CH0 RK1
1379 13:56:52.390361
1380 13:56:52.393323 DATLAT Default: 0xa
1381 13:56:52.393403 0, 0xFFFF, sum = 0
1382 13:56:52.396864 1, 0xFFFF, sum = 0
1383 13:56:52.396946 2, 0xFFFF, sum = 0
1384 13:56:52.400082 3, 0xFFFF, sum = 0
1385 13:56:52.400162 4, 0xFFFF, sum = 0
1386 13:56:52.403356 5, 0xFFFF, sum = 0
1387 13:56:52.406469 6, 0xFFFF, sum = 0
1388 13:56:52.406550 7, 0xFFFF, sum = 0
1389 13:56:52.409952 8, 0xFFFF, sum = 0
1390 13:56:52.410033 9, 0x0, sum = 1
1391 13:56:52.410099 10, 0x0, sum = 2
1392 13:56:52.413268 11, 0x0, sum = 3
1393 13:56:52.413350 12, 0x0, sum = 4
1394 13:56:52.416433 best_step = 10
1395 13:56:52.416512
1396 13:56:52.416574 ==
1397 13:56:52.419617 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 13:56:52.423135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 13:56:52.423206 ==
1400 13:56:52.426673 RX Vref Scan: 0
1401 13:56:52.426744
1402 13:56:52.426804 RX Vref 0 -> 0, step: 1
1403 13:56:52.426867
1404 13:56:52.429720 RX Delay -111 -> 252, step: 8
1405 13:56:52.436916 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1406 13:56:52.440032 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1407 13:56:52.443394 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1408 13:56:52.446752 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1409 13:56:52.450312 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1410 13:56:52.456952 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1411 13:56:52.460307 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1412 13:56:52.463497 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1413 13:56:52.466980 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1414 13:56:52.470280 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1415 13:56:52.476989 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1416 13:56:52.480208 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1417 13:56:52.483741 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1418 13:56:52.487204 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1419 13:56:52.490450 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1420 13:56:52.497160 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1421 13:56:52.497581 ==
1422 13:56:52.500193 Dram Type= 6, Freq= 0, CH_0, rank 1
1423 13:56:52.503692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 13:56:52.504075 ==
1425 13:56:52.504380 DQS Delay:
1426 13:56:52.507013 DQS0 = 0, DQS1 = 0
1427 13:56:52.507571 DQM Delay:
1428 13:56:52.510576 DQM0 = 78, DQM1 = 70
1429 13:56:52.511014 DQ Delay:
1430 13:56:52.513459 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1431 13:56:52.516773 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =88
1432 13:56:52.520141 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1433 13:56:52.523391 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1434 13:56:52.523470
1435 13:56:52.523532
1436 13:56:52.533440 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1437 13:56:52.533554 CH0 RK1: MR19=606, MR18=4A25
1438 13:56:52.539894 CH0_RK1: MR19=0x606, MR18=0x4A25, DQSOSC=391, MR23=63, INC=96, DEC=64
1439 13:56:52.543303 [RxdqsGatingPostProcess] freq 800
1440 13:56:52.550145 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1441 13:56:52.553620 Pre-setting of DQS Precalculation
1442 13:56:52.557109 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1443 13:56:52.557184 ==
1444 13:56:52.559913 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 13:56:52.563338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 13:56:52.563407 ==
1447 13:56:52.570120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 13:56:52.576730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 13:56:52.585058 [CA 0] Center 36 (6~66) winsize 61
1450 13:56:52.588313 [CA 1] Center 36 (6~67) winsize 62
1451 13:56:52.591874 [CA 2] Center 34 (4~64) winsize 61
1452 13:56:52.595149 [CA 3] Center 34 (4~64) winsize 61
1453 13:56:52.598309 [CA 4] Center 34 (4~65) winsize 62
1454 13:56:52.601529 [CA 5] Center 33 (3~64) winsize 62
1455 13:56:52.601609
1456 13:56:52.605182 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1457 13:56:52.605261
1458 13:56:52.608268 [CATrainingPosCal] consider 1 rank data
1459 13:56:52.611618 u2DelayCellTimex100 = 270/100 ps
1460 13:56:52.615074 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1461 13:56:52.621335 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1462 13:56:52.624870 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1463 13:56:52.628181 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1464 13:56:52.631538 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1465 13:56:52.634792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1466 13:56:52.634873
1467 13:56:52.638178 CA PerBit enable=1, Macro0, CA PI delay=33
1468 13:56:52.638258
1469 13:56:52.641253 [CBTSetCACLKResult] CA Dly = 33
1470 13:56:52.641334 CS Dly: 5 (0~36)
1471 13:56:52.644678 ==
1472 13:56:52.648015 Dram Type= 6, Freq= 0, CH_1, rank 1
1473 13:56:52.651525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 13:56:52.651606 ==
1475 13:56:52.655005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1476 13:56:52.661405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1477 13:56:52.671243 [CA 0] Center 36 (6~67) winsize 62
1478 13:56:52.674711 [CA 1] Center 36 (6~67) winsize 62
1479 13:56:52.677887 [CA 2] Center 34 (4~65) winsize 62
1480 13:56:52.681193 [CA 3] Center 33 (3~64) winsize 62
1481 13:56:52.684384 [CA 4] Center 34 (4~65) winsize 62
1482 13:56:52.687865 [CA 5] Center 33 (3~64) winsize 62
1483 13:56:52.687946
1484 13:56:52.691008 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1485 13:56:52.691112
1486 13:56:52.694585 [CATrainingPosCal] consider 2 rank data
1487 13:56:52.697845 u2DelayCellTimex100 = 270/100 ps
1488 13:56:52.701097 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1489 13:56:52.704306 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1490 13:56:52.711084 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1491 13:56:52.714623 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1492 13:56:52.717971 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1493 13:56:52.721538 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1494 13:56:52.721619
1495 13:56:52.724980 CA PerBit enable=1, Macro0, CA PI delay=33
1496 13:56:52.725062
1497 13:56:52.728853 [CBTSetCACLKResult] CA Dly = 33
1498 13:56:52.728933 CS Dly: 5 (0~37)
1499 13:56:52.728998
1500 13:56:52.732438 ----->DramcWriteLeveling(PI) begin...
1501 13:56:52.732519 ==
1502 13:56:52.736354 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 13:56:52.739906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 13:56:52.739987 ==
1505 13:56:52.743674 Write leveling (Byte 0): 27 => 27
1506 13:56:52.747219 Write leveling (Byte 1): 28 => 28
1507 13:56:52.750611 DramcWriteLeveling(PI) end<-----
1508 13:56:52.750686
1509 13:56:52.750747 ==
1510 13:56:52.754529 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 13:56:52.757854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 13:56:52.757934 ==
1513 13:56:52.761274 [Gating] SW mode calibration
1514 13:56:52.768025 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1515 13:56:52.771325 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1516 13:56:52.778012 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1517 13:56:52.781344 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 13:56:52.784635 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1519 13:56:52.791507 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:56:52.794765 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:56:52.798004 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:56:52.804810 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:56:52.807996 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:56:52.811459 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:56:52.817875 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:56:52.821508 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:56:52.824701 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:56:52.831392 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:56:52.834910 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:56:52.838545 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 13:56:52.841456 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 13:56:52.848317 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:56:52.851513 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1534 13:56:52.855016 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1535 13:56:52.861251 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:56:52.864628 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 13:56:52.868075 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:56:52.874637 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:56:52.878052 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 13:56:52.881196 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 13:56:52.888018 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 13:56:52.891095 0 9 8 | B1->B0 | 2c2c 2525 | 0 1 | (1 1) (0 0)
1543 13:56:52.894461 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1544 13:56:52.901168 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 13:56:52.904609 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 13:56:52.907658 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 13:56:52.914422 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 13:56:52.917768 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 13:56:52.921040 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1550 13:56:52.928017 0 10 8 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
1551 13:56:52.931143 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 13:56:52.934583 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 13:56:52.941178 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 13:56:52.944329 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 13:56:52.947839 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 13:56:52.954636 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 13:56:52.957789 0 11 4 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
1558 13:56:52.961328 0 11 8 | B1->B0 | 3c3c 3b3b | 0 1 | (0 0) (0 0)
1559 13:56:52.964320 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 13:56:52.971092 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 13:56:52.974419 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 13:56:52.977719 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 13:56:52.984388 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 13:56:52.987671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 13:56:52.990842 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 13:56:52.997444 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1567 13:56:53.001050 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 13:56:53.004293 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 13:56:53.010969 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 13:56:53.014147 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 13:56:53.017398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 13:56:53.024110 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 13:56:53.027556 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 13:56:53.030643 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 13:56:53.037405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 13:56:53.040876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 13:56:53.044295 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 13:56:53.050446 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 13:56:53.054002 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 13:56:53.057400 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 13:56:53.064079 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 13:56:53.067635 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 13:56:53.070871 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 13:56:53.073869 Total UI for P1: 0, mck2ui 16
1585 13:56:53.077388 best dqsien dly found for B0: ( 0, 14, 10)
1586 13:56:53.080638 Total UI for P1: 0, mck2ui 16
1587 13:56:53.083669 best dqsien dly found for B1: ( 0, 14, 10)
1588 13:56:53.087098 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1589 13:56:53.090637 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1590 13:56:53.090717
1591 13:56:53.097066 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1592 13:56:53.100517 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1593 13:56:53.100598 [Gating] SW calibration Done
1594 13:56:53.103999 ==
1595 13:56:53.104079 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 13:56:53.110494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 13:56:53.110576 ==
1598 13:56:53.110640 RX Vref Scan: 0
1599 13:56:53.110701
1600 13:56:53.113735 RX Vref 0 -> 0, step: 1
1601 13:56:53.113816
1602 13:56:53.117310 RX Delay -130 -> 252, step: 16
1603 13:56:53.120532 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1604 13:56:53.123813 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1605 13:56:53.126879 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1606 13:56:53.133661 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1607 13:56:53.136972 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1608 13:56:53.140202 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1609 13:56:53.143764 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1610 13:56:53.147068 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1611 13:56:53.153603 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1612 13:56:53.156940 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1613 13:56:53.160026 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1614 13:56:53.163416 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1615 13:56:53.166847 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1616 13:56:53.173378 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1617 13:56:53.176860 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1618 13:56:53.180261 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1619 13:56:53.180394 ==
1620 13:56:53.183710 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 13:56:53.187074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 13:56:53.190506 ==
1623 13:56:53.190608 DQS Delay:
1624 13:56:53.190699 DQS0 = 0, DQS1 = 0
1625 13:56:53.193459 DQM Delay:
1626 13:56:53.193620 DQM0 = 81, DQM1 = 76
1627 13:56:53.196964 DQ Delay:
1628 13:56:53.197065 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1629 13:56:53.200424 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1630 13:56:53.203506 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1631 13:56:53.207104 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1632 13:56:53.207198
1633 13:56:53.207287
1634 13:56:53.210403 ==
1635 13:56:53.213398 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 13:56:53.217002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 13:56:53.217110 ==
1638 13:56:53.217202
1639 13:56:53.217288
1640 13:56:53.220051 TX Vref Scan disable
1641 13:56:53.220148 == TX Byte 0 ==
1642 13:56:53.223596 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 13:56:53.230383 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 13:56:53.230489 == TX Byte 1 ==
1645 13:56:53.233827 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1646 13:56:53.240502 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1647 13:56:53.240584 ==
1648 13:56:53.243692 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 13:56:53.247008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 13:56:53.247089 ==
1651 13:56:53.260150 TX Vref=22, minBit 9, minWin=27, winSum=448
1652 13:56:53.263601 TX Vref=24, minBit 9, minWin=27, winSum=451
1653 13:56:53.266608 TX Vref=26, minBit 11, minWin=27, winSum=451
1654 13:56:53.270142 TX Vref=28, minBit 11, minWin=27, winSum=458
1655 13:56:53.273708 TX Vref=30, minBit 11, minWin=28, winSum=462
1656 13:56:53.280066 TX Vref=32, minBit 1, minWin=28, winSum=457
1657 13:56:53.283669 [TxChooseVref] Worse bit 11, Min win 28, Win sum 462, Final Vref 30
1658 13:56:53.283750
1659 13:56:53.286715 Final TX Range 1 Vref 30
1660 13:56:53.286797
1661 13:56:53.286863 ==
1662 13:56:53.290100 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 13:56:53.293383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 13:56:53.296794 ==
1665 13:56:53.296875
1666 13:56:53.296940
1667 13:56:53.297036 TX Vref Scan disable
1668 13:56:53.301021 == TX Byte 0 ==
1669 13:56:53.304555 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1670 13:56:53.307795 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1671 13:56:53.311349 == TX Byte 1 ==
1672 13:56:53.314703 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1673 13:56:53.317867 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1674 13:56:53.317949
1675 13:56:53.321277 [DATLAT]
1676 13:56:53.321358 Freq=800, CH1 RK0
1677 13:56:53.321423
1678 13:56:53.324739 DATLAT Default: 0xa
1679 13:56:53.324820 0, 0xFFFF, sum = 0
1680 13:56:53.327888 1, 0xFFFF, sum = 0
1681 13:56:53.327971 2, 0xFFFF, sum = 0
1682 13:56:53.331309 3, 0xFFFF, sum = 0
1683 13:56:53.331391 4, 0xFFFF, sum = 0
1684 13:56:53.334707 5, 0xFFFF, sum = 0
1685 13:56:53.334789 6, 0xFFFF, sum = 0
1686 13:56:53.337886 7, 0xFFFF, sum = 0
1687 13:56:53.337968 8, 0xFFFF, sum = 0
1688 13:56:53.341373 9, 0x0, sum = 1
1689 13:56:53.341456 10, 0x0, sum = 2
1690 13:56:53.344618 11, 0x0, sum = 3
1691 13:56:53.344701 12, 0x0, sum = 4
1692 13:56:53.347820 best_step = 10
1693 13:56:53.347901
1694 13:56:53.347965 ==
1695 13:56:53.351168 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 13:56:53.354577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 13:56:53.354659 ==
1698 13:56:53.354724 RX Vref Scan: 1
1699 13:56:53.354785
1700 13:56:53.357741 Set Vref Range= 32 -> 127
1701 13:56:53.357822
1702 13:56:53.361207 RX Vref 32 -> 127, step: 1
1703 13:56:53.361289
1704 13:56:53.364461 RX Delay -111 -> 252, step: 8
1705 13:56:53.364542
1706 13:56:53.367926 Set Vref, RX VrefLevel [Byte0]: 32
1707 13:56:53.371236 [Byte1]: 32
1708 13:56:53.371318
1709 13:56:53.374507 Set Vref, RX VrefLevel [Byte0]: 33
1710 13:56:53.377724 [Byte1]: 33
1711 13:56:53.377806
1712 13:56:53.381013 Set Vref, RX VrefLevel [Byte0]: 34
1713 13:56:53.384563 [Byte1]: 34
1714 13:56:53.388693
1715 13:56:53.388800 Set Vref, RX VrefLevel [Byte0]: 35
1716 13:56:53.392071 [Byte1]: 35
1717 13:56:53.396133
1718 13:56:53.396214 Set Vref, RX VrefLevel [Byte0]: 36
1719 13:56:53.399446 [Byte1]: 36
1720 13:56:53.403639
1721 13:56:53.403721 Set Vref, RX VrefLevel [Byte0]: 37
1722 13:56:53.406921 [Byte1]: 37
1723 13:56:53.411472
1724 13:56:53.411554 Set Vref, RX VrefLevel [Byte0]: 38
1725 13:56:53.414756 [Byte1]: 38
1726 13:56:53.419133
1727 13:56:53.419213 Set Vref, RX VrefLevel [Byte0]: 39
1728 13:56:53.422495 [Byte1]: 39
1729 13:56:53.426796
1730 13:56:53.426876 Set Vref, RX VrefLevel [Byte0]: 40
1731 13:56:53.430056 [Byte1]: 40
1732 13:56:53.434551
1733 13:56:53.434644 Set Vref, RX VrefLevel [Byte0]: 41
1734 13:56:53.437651 [Byte1]: 41
1735 13:56:53.441970
1736 13:56:53.442074 Set Vref, RX VrefLevel [Byte0]: 42
1737 13:56:53.445868 [Byte1]: 42
1738 13:56:53.450287
1739 13:56:53.450741 Set Vref, RX VrefLevel [Byte0]: 43
1740 13:56:53.453225 [Byte1]: 43
1741 13:56:53.458009
1742 13:56:53.458427 Set Vref, RX VrefLevel [Byte0]: 44
1743 13:56:53.460867 [Byte1]: 44
1744 13:56:53.465151
1745 13:56:53.465623 Set Vref, RX VrefLevel [Byte0]: 45
1746 13:56:53.468505 [Byte1]: 45
1747 13:56:53.472894
1748 13:56:53.473314 Set Vref, RX VrefLevel [Byte0]: 46
1749 13:56:53.476135 [Byte1]: 46
1750 13:56:53.480630
1751 13:56:53.481051 Set Vref, RX VrefLevel [Byte0]: 47
1752 13:56:53.483922 [Byte1]: 47
1753 13:56:53.488160
1754 13:56:53.488573 Set Vref, RX VrefLevel [Byte0]: 48
1755 13:56:53.491433 [Byte1]: 48
1756 13:56:53.496047
1757 13:56:53.496638 Set Vref, RX VrefLevel [Byte0]: 49
1758 13:56:53.499097 [Byte1]: 49
1759 13:56:53.503423
1760 13:56:53.503840 Set Vref, RX VrefLevel [Byte0]: 50
1761 13:56:53.507026 [Byte1]: 50
1762 13:56:53.511036
1763 13:56:53.511458 Set Vref, RX VrefLevel [Byte0]: 51
1764 13:56:53.514317 [Byte1]: 51
1765 13:56:53.518752
1766 13:56:53.519167 Set Vref, RX VrefLevel [Byte0]: 52
1767 13:56:53.522068 [Byte1]: 52
1768 13:56:53.526804
1769 13:56:53.527262 Set Vref, RX VrefLevel [Byte0]: 53
1770 13:56:53.529868 [Byte1]: 53
1771 13:56:53.533924
1772 13:56:53.534338 Set Vref, RX VrefLevel [Byte0]: 54
1773 13:56:53.537548 [Byte1]: 54
1774 13:56:53.541822
1775 13:56:53.542240 Set Vref, RX VrefLevel [Byte0]: 55
1776 13:56:53.545071 [Byte1]: 55
1777 13:56:53.549402
1778 13:56:53.549867 Set Vref, RX VrefLevel [Byte0]: 56
1779 13:56:53.552671 [Byte1]: 56
1780 13:56:53.557174
1781 13:56:53.557645 Set Vref, RX VrefLevel [Byte0]: 57
1782 13:56:53.560235 [Byte1]: 57
1783 13:56:53.564585
1784 13:56:53.565002 Set Vref, RX VrefLevel [Byte0]: 58
1785 13:56:53.567859 [Byte1]: 58
1786 13:56:53.572563
1787 13:56:53.572983 Set Vref, RX VrefLevel [Byte0]: 59
1788 13:56:53.575469 [Byte1]: 59
1789 13:56:53.580077
1790 13:56:53.580508 Set Vref, RX VrefLevel [Byte0]: 60
1791 13:56:53.583347 [Byte1]: 60
1792 13:56:53.587845
1793 13:56:53.588259 Set Vref, RX VrefLevel [Byte0]: 61
1794 13:56:53.591001 [Byte1]: 61
1795 13:56:53.595205
1796 13:56:53.595615 Set Vref, RX VrefLevel [Byte0]: 62
1797 13:56:53.598633 [Byte1]: 62
1798 13:56:53.602743
1799 13:56:53.603138 Set Vref, RX VrefLevel [Byte0]: 63
1800 13:56:53.605901 [Byte1]: 63
1801 13:56:53.610525
1802 13:56:53.610819 Set Vref, RX VrefLevel [Byte0]: 64
1803 13:56:53.613577 [Byte1]: 64
1804 13:56:53.618236
1805 13:56:53.618536 Set Vref, RX VrefLevel [Byte0]: 65
1806 13:56:53.621302 [Byte1]: 65
1807 13:56:53.625673
1808 13:56:53.625971 Set Vref, RX VrefLevel [Byte0]: 66
1809 13:56:53.628894 [Byte1]: 66
1810 13:56:53.633292
1811 13:56:53.633538 Set Vref, RX VrefLevel [Byte0]: 67
1812 13:56:53.636537 [Byte1]: 67
1813 13:56:53.640903
1814 13:56:53.641051 Set Vref, RX VrefLevel [Byte0]: 68
1815 13:56:53.644258 [Byte1]: 68
1816 13:56:53.648381
1817 13:56:53.648509 Set Vref, RX VrefLevel [Byte0]: 69
1818 13:56:53.651806 [Byte1]: 69
1819 13:56:53.656056
1820 13:56:53.656188 Set Vref, RX VrefLevel [Byte0]: 70
1821 13:56:53.659609 [Byte1]: 70
1822 13:56:53.663666
1823 13:56:53.663785 Set Vref, RX VrefLevel [Byte0]: 71
1824 13:56:53.667046 [Byte1]: 71
1825 13:56:53.671858
1826 13:56:53.672024 Set Vref, RX VrefLevel [Byte0]: 72
1827 13:56:53.674864 [Byte1]: 72
1828 13:56:53.679571
1829 13:56:53.679741 Set Vref, RX VrefLevel [Byte0]: 73
1830 13:56:53.682321 [Byte1]: 73
1831 13:56:53.686534
1832 13:56:53.686626 Set Vref, RX VrefLevel [Byte0]: 74
1833 13:56:53.690111 [Byte1]: 74
1834 13:56:53.694611
1835 13:56:53.694781 Set Vref, RX VrefLevel [Byte0]: 75
1836 13:56:53.697908 [Byte1]: 75
1837 13:56:53.702459
1838 13:56:53.702638 Set Vref, RX VrefLevel [Byte0]: 76
1839 13:56:53.705447 [Byte1]: 76
1840 13:56:53.710062
1841 13:56:53.710269 Set Vref, RX VrefLevel [Byte0]: 77
1842 13:56:53.713275 [Byte1]: 77
1843 13:56:53.717560
1844 13:56:53.718028 Final RX Vref Byte 0 = 57 to rank0
1845 13:56:53.721067 Final RX Vref Byte 1 = 56 to rank0
1846 13:56:53.724283 Final RX Vref Byte 0 = 57 to rank1
1847 13:56:53.728025 Final RX Vref Byte 1 = 56 to rank1==
1848 13:56:53.731477 Dram Type= 6, Freq= 0, CH_1, rank 0
1849 13:56:53.738191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 13:56:53.738755 ==
1851 13:56:53.739121 DQS Delay:
1852 13:56:53.739461 DQS0 = 0, DQS1 = 0
1853 13:56:53.741600 DQM Delay:
1854 13:56:53.742154 DQM0 = 80, DQM1 = 71
1855 13:56:53.744594 DQ Delay:
1856 13:56:53.747977 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1857 13:56:53.748541 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1858 13:56:53.751203 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1859 13:56:53.754519 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1860 13:56:53.757965
1861 13:56:53.758525
1862 13:56:53.764785 [DQSOSCAuto] RK0, (LSB)MR18= 0x151f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1863 13:56:53.768208 CH1 RK0: MR19=606, MR18=151F
1864 13:56:53.774349 CH1_RK0: MR19=0x606, MR18=0x151F, DQSOSC=402, MR23=63, INC=91, DEC=60
1865 13:56:53.774911
1866 13:56:53.778017 ----->DramcWriteLeveling(PI) begin...
1867 13:56:53.778622 ==
1868 13:56:53.781457 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 13:56:53.784705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1870 13:56:53.785270 ==
1871 13:56:53.788365 Write leveling (Byte 0): 28 => 28
1872 13:56:53.791486 Write leveling (Byte 1): 28 => 28
1873 13:56:53.794604 DramcWriteLeveling(PI) end<-----
1874 13:56:53.795067
1875 13:56:53.795431 ==
1876 13:56:53.797981 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 13:56:53.801334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 13:56:53.801933 ==
1879 13:56:53.804887 [Gating] SW mode calibration
1880 13:56:53.811088 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1881 13:56:53.818179 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1882 13:56:53.821292 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1883 13:56:53.824613 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1884 13:56:53.831422 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 13:56:53.834524 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 13:56:53.837703 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:56:53.844661 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 13:56:53.848129 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 13:56:53.851152 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 13:56:53.858097 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:56:53.860966 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 13:56:53.864627 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 13:56:53.871077 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 13:56:53.874850 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 13:56:53.877816 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 13:56:53.881666 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 13:56:53.887988 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 13:56:53.891157 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 13:56:53.894418 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1900 13:56:53.900874 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 13:56:53.904543 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 13:56:53.907668 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 13:56:53.914191 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 13:56:53.917940 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 13:56:53.921339 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 13:56:53.928211 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1907 13:56:53.931144 0 9 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1908 13:56:53.934365 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1909 13:56:53.941315 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 13:56:53.944475 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 13:56:53.947753 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 13:56:53.954230 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 13:56:53.957676 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 13:56:53.960986 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1915 13:56:53.968040 0 10 4 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (0 0)
1916 13:56:53.971159 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 13:56:53.974151 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 13:56:53.981131 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 13:56:53.984385 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 13:56:53.987704 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 13:56:53.990953 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 13:56:53.997619 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 13:56:54.000865 0 11 4 | B1->B0 | 3232 3939 | 0 0 | (0 0) (0 0)
1924 13:56:54.004357 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1925 13:56:54.011003 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 13:56:54.014173 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 13:56:54.017564 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 13:56:54.024740 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 13:56:54.027744 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 13:56:54.031078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 13:56:54.037605 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1932 13:56:54.041207 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1933 13:56:54.044382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 13:56:54.050739 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 13:56:54.054073 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 13:56:54.057766 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 13:56:54.064643 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 13:56:54.067590 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 13:56:54.070731 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 13:56:54.077693 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 13:56:54.080803 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 13:56:54.084306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 13:56:54.090835 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 13:56:54.093966 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 13:56:54.097715 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 13:56:54.103755 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 13:56:54.107119 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1948 13:56:54.110333 Total UI for P1: 0, mck2ui 16
1949 13:56:54.113684 best dqsien dly found for B0: ( 0, 14, 2)
1950 13:56:54.117308 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1951 13:56:54.120766 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1952 13:56:54.123980 Total UI for P1: 0, mck2ui 16
1953 13:56:54.127489 best dqsien dly found for B1: ( 0, 14, 6)
1954 13:56:54.130559 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1955 13:56:54.134179 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1956 13:56:54.137223
1957 13:56:54.140619 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1958 13:56:54.143857 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1959 13:56:54.147304 [Gating] SW calibration Done
1960 13:56:54.147864 ==
1961 13:56:54.150565 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 13:56:54.153810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 13:56:54.154271 ==
1964 13:56:54.154659 RX Vref Scan: 0
1965 13:56:54.155074
1966 13:56:54.157201 RX Vref 0 -> 0, step: 1
1967 13:56:54.157824
1968 13:56:54.160631 RX Delay -130 -> 252, step: 16
1969 13:56:54.163689 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1970 13:56:54.167373 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1971 13:56:54.173946 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1972 13:56:54.177280 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1973 13:56:54.180672 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1974 13:56:54.184101 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1975 13:56:54.187536 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1976 13:56:54.194157 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1977 13:56:54.197757 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1978 13:56:54.200429 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1979 13:56:54.204258 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1980 13:56:54.207230 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1981 13:56:54.213773 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1982 13:56:54.217102 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1983 13:56:54.220577 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1984 13:56:54.224045 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1985 13:56:54.224599 ==
1986 13:56:54.227275 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 13:56:54.230294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 13:56:54.233909 ==
1989 13:56:54.234627 DQS Delay:
1990 13:56:54.235020 DQS0 = 0, DQS1 = 0
1991 13:56:54.237289 DQM Delay:
1992 13:56:54.237818 DQM0 = 80, DQM1 = 72
1993 13:56:54.240362 DQ Delay:
1994 13:56:54.243652 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1995 13:56:54.244109 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1996 13:56:54.246951 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1997 13:56:54.250337 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1998 13:56:54.253718
1999 13:56:54.254174
2000 13:56:54.254532 ==
2001 13:56:54.257282 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 13:56:54.260636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 13:56:54.261208 ==
2004 13:56:54.261629
2005 13:56:54.262038
2006 13:56:54.263692 TX Vref Scan disable
2007 13:56:54.264148 == TX Byte 0 ==
2008 13:56:54.270668 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2009 13:56:54.273938 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2010 13:56:54.274497 == TX Byte 1 ==
2011 13:56:54.280628 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2012 13:56:54.283858 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2013 13:56:54.284421 ==
2014 13:56:54.287059 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 13:56:54.290831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 13:56:54.291393 ==
2017 13:56:54.304003 TX Vref=22, minBit 0, minWin=28, winSum=453
2018 13:56:54.307254 TX Vref=24, minBit 0, minWin=28, winSum=456
2019 13:56:54.310520 TX Vref=26, minBit 6, minWin=28, winSum=459
2020 13:56:54.313842 TX Vref=28, minBit 13, minWin=28, winSum=463
2021 13:56:54.317655 TX Vref=30, minBit 4, minWin=28, winSum=460
2022 13:56:54.323961 TX Vref=32, minBit 4, minWin=28, winSum=460
2023 13:56:54.327407 [TxChooseVref] Worse bit 13, Min win 28, Win sum 463, Final Vref 28
2024 13:56:54.327968
2025 13:56:54.330945 Final TX Range 1 Vref 28
2026 13:56:54.331500
2027 13:56:54.331862 ==
2028 13:56:54.333968 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 13:56:54.337508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 13:56:54.338077 ==
2031 13:56:54.340103
2032 13:56:54.340629
2033 13:56:54.340993 TX Vref Scan disable
2034 13:56:54.344008 == TX Byte 0 ==
2035 13:56:54.346998 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2036 13:56:54.350630 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2037 13:56:54.353544 == TX Byte 1 ==
2038 13:56:54.357588 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2039 13:56:54.363951 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2040 13:56:54.364541
2041 13:56:54.364916 [DATLAT]
2042 13:56:54.365251 Freq=800, CH1 RK1
2043 13:56:54.365622
2044 13:56:54.366856 DATLAT Default: 0xa
2045 13:56:54.367311 0, 0xFFFF, sum = 0
2046 13:56:54.370324 1, 0xFFFF, sum = 0
2047 13:56:54.370783 2, 0xFFFF, sum = 0
2048 13:56:54.373634 3, 0xFFFF, sum = 0
2049 13:56:54.374199 4, 0xFFFF, sum = 0
2050 13:56:54.377286 5, 0xFFFF, sum = 0
2051 13:56:54.380873 6, 0xFFFF, sum = 0
2052 13:56:54.381430 7, 0xFFFF, sum = 0
2053 13:56:54.383929 8, 0xFFFF, sum = 0
2054 13:56:54.384485 9, 0x0, sum = 1
2055 13:56:54.384857 10, 0x0, sum = 2
2056 13:56:54.387106 11, 0x0, sum = 3
2057 13:56:54.387568 12, 0x0, sum = 4
2058 13:56:54.390513 best_step = 10
2059 13:56:54.391066
2060 13:56:54.391427 ==
2061 13:56:54.393655 Dram Type= 6, Freq= 0, CH_1, rank 1
2062 13:56:54.397249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2063 13:56:54.397880 ==
2064 13:56:54.400318 RX Vref Scan: 0
2065 13:56:54.400773
2066 13:56:54.401135 RX Vref 0 -> 0, step: 1
2067 13:56:54.401508
2068 13:56:54.403687 RX Delay -111 -> 252, step: 8
2069 13:56:54.410624 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2070 13:56:54.413661 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2071 13:56:54.417222 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2072 13:56:54.420774 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2073 13:56:54.423998 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2074 13:56:54.430624 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2075 13:56:54.433952 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2076 13:56:54.437534 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2077 13:56:54.440820 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2078 13:56:54.443979 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
2079 13:56:54.450446 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2080 13:56:54.453662 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2081 13:56:54.456823 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2082 13:56:54.460101 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2083 13:56:54.466818 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2084 13:56:54.470108 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2085 13:56:54.470569 ==
2086 13:56:54.473401 Dram Type= 6, Freq= 0, CH_1, rank 1
2087 13:56:54.476827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2088 13:56:54.477301 ==
2089 13:56:54.480006 DQS Delay:
2090 13:56:54.480571 DQS0 = 0, DQS1 = 0
2091 13:56:54.480943 DQM Delay:
2092 13:56:54.483344 DQM0 = 77, DQM1 = 72
2093 13:56:54.483819 DQ Delay:
2094 13:56:54.486554 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2095 13:56:54.489979 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2096 13:56:54.493163 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
2097 13:56:54.496485 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
2098 13:56:54.497240
2099 13:56:54.497898
2100 13:56:54.506587 [DQSOSCAuto] RK1, (LSB)MR18= 0x273f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2101 13:56:54.507010 CH1 RK1: MR19=606, MR18=273F
2102 13:56:54.513188 CH1_RK1: MR19=0x606, MR18=0x273F, DQSOSC=393, MR23=63, INC=95, DEC=63
2103 13:56:54.516747 [RxdqsGatingPostProcess] freq 800
2104 13:56:54.523338 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2105 13:56:54.526457 Pre-setting of DQS Precalculation
2106 13:56:54.529805 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2107 13:56:54.536418 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2108 13:56:54.546317 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2109 13:56:54.546731
2110 13:56:54.547059
2111 13:56:54.549535 [Calibration Summary] 1600 Mbps
2112 13:56:54.549948 CH 0, Rank 0
2113 13:56:54.552981 SW Impedance : PASS
2114 13:56:54.553397 DUTY Scan : NO K
2115 13:56:54.556555 ZQ Calibration : PASS
2116 13:56:54.559758 Jitter Meter : NO K
2117 13:56:54.560171 CBT Training : PASS
2118 13:56:54.562914 Write leveling : PASS
2119 13:56:54.562993 RX DQS gating : PASS
2120 13:56:54.566003 RX DQ/DQS(RDDQC) : PASS
2121 13:56:54.569594 TX DQ/DQS : PASS
2122 13:56:54.570009 RX DATLAT : PASS
2123 13:56:54.572966 RX DQ/DQS(Engine): PASS
2124 13:56:54.576304 TX OE : NO K
2125 13:56:54.576728 All Pass.
2126 13:56:54.577060
2127 13:56:54.577367 CH 0, Rank 1
2128 13:56:54.579733 SW Impedance : PASS
2129 13:56:54.582776 DUTY Scan : NO K
2130 13:56:54.583195 ZQ Calibration : PASS
2131 13:56:54.586239 Jitter Meter : NO K
2132 13:56:54.589985 CBT Training : PASS
2133 13:56:54.590404 Write leveling : PASS
2134 13:56:54.592544 RX DQS gating : PASS
2135 13:56:54.595859 RX DQ/DQS(RDDQC) : PASS
2136 13:56:54.595941 TX DQ/DQS : PASS
2137 13:56:54.599118 RX DATLAT : PASS
2138 13:56:54.602349 RX DQ/DQS(Engine): PASS
2139 13:56:54.602429 TX OE : NO K
2140 13:56:54.602493 All Pass.
2141 13:56:54.605792
2142 13:56:54.605871 CH 1, Rank 0
2143 13:56:54.609203 SW Impedance : PASS
2144 13:56:54.609282 DUTY Scan : NO K
2145 13:56:54.612731 ZQ Calibration : PASS
2146 13:56:54.612811 Jitter Meter : NO K
2147 13:56:54.615749 CBT Training : PASS
2148 13:56:54.619233 Write leveling : PASS
2149 13:56:54.619315 RX DQS gating : PASS
2150 13:56:54.622513 RX DQ/DQS(RDDQC) : PASS
2151 13:56:54.625867 TX DQ/DQS : PASS
2152 13:56:54.625949 RX DATLAT : PASS
2153 13:56:54.629651 RX DQ/DQS(Engine): PASS
2154 13:56:54.633167 TX OE : NO K
2155 13:56:54.633626 All Pass.
2156 13:56:54.633970
2157 13:56:54.634281 CH 1, Rank 1
2158 13:56:54.635995 SW Impedance : PASS
2159 13:56:54.639370 DUTY Scan : NO K
2160 13:56:54.639789 ZQ Calibration : PASS
2161 13:56:54.642719 Jitter Meter : NO K
2162 13:56:54.645882 CBT Training : PASS
2163 13:56:54.645963 Write leveling : PASS
2164 13:56:54.649325 RX DQS gating : PASS
2165 13:56:54.649784 RX DQ/DQS(RDDQC) : PASS
2166 13:56:54.652812 TX DQ/DQS : PASS
2167 13:56:54.656376 RX DATLAT : PASS
2168 13:56:54.656793 RX DQ/DQS(Engine): PASS
2169 13:56:54.659437 TX OE : NO K
2170 13:56:54.659859 All Pass.
2171 13:56:54.660193
2172 13:56:54.662865 DramC Write-DBI off
2173 13:56:54.666172 PER_BANK_REFRESH: Hybrid Mode
2174 13:56:54.666617 TX_TRACKING: ON
2175 13:56:54.669387 [GetDramInforAfterCalByMRR] Vendor 6.
2176 13:56:54.672841 [GetDramInforAfterCalByMRR] Revision 606.
2177 13:56:54.676208 [GetDramInforAfterCalByMRR] Revision 2 0.
2178 13:56:54.679440 MR0 0x3b3b
2179 13:56:54.679858 MR8 0x5151
2180 13:56:54.683269 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2181 13:56:54.683792
2182 13:56:54.686544 MR0 0x3b3b
2183 13:56:54.687062 MR8 0x5151
2184 13:56:54.690102 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2185 13:56:54.690619
2186 13:56:54.699748 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2187 13:56:54.702771 [FAST_K] Save calibration result to emmc
2188 13:56:54.706125 [FAST_K] Save calibration result to emmc
2189 13:56:54.709730 dram_init: config_dvfs: 1
2190 13:56:54.713134 dramc_set_vcore_voltage set vcore to 662500
2191 13:56:54.713872 Read voltage for 1200, 2
2192 13:56:54.716088 Vio18 = 0
2193 13:56:54.716547 Vcore = 662500
2194 13:56:54.716915 Vdram = 0
2195 13:56:54.719642 Vddq = 0
2196 13:56:54.720198 Vmddr = 0
2197 13:56:54.722719 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2198 13:56:54.729670 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2199 13:56:54.732636 MEM_TYPE=3, freq_sel=15
2200 13:56:54.736707 sv_algorithm_assistance_LP4_1600
2201 13:56:54.739949 ============ PULL DRAM RESETB DOWN ============
2202 13:56:54.742618 ========== PULL DRAM RESETB DOWN end =========
2203 13:56:54.746204 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2204 13:56:54.749725 ===================================
2205 13:56:54.752705 LPDDR4 DRAM CONFIGURATION
2206 13:56:54.756368 ===================================
2207 13:56:54.759613 EX_ROW_EN[0] = 0x0
2208 13:56:54.760126 EX_ROW_EN[1] = 0x0
2209 13:56:54.762948 LP4Y_EN = 0x0
2210 13:56:54.763562 WORK_FSP = 0x0
2211 13:56:54.766506 WL = 0x4
2212 13:56:54.767061 RL = 0x4
2213 13:56:54.769641 BL = 0x2
2214 13:56:54.770197 RPST = 0x0
2215 13:56:54.773169 RD_PRE = 0x0
2216 13:56:54.773781 WR_PRE = 0x1
2217 13:56:54.776194 WR_PST = 0x0
2218 13:56:54.779857 DBI_WR = 0x0
2219 13:56:54.780415 DBI_RD = 0x0
2220 13:56:54.782777 OTF = 0x1
2221 13:56:54.786339 ===================================
2222 13:56:54.789888 ===================================
2223 13:56:54.790447 ANA top config
2224 13:56:54.792874 ===================================
2225 13:56:54.796382 DLL_ASYNC_EN = 0
2226 13:56:54.796939 ALL_SLAVE_EN = 0
2227 13:56:54.799508 NEW_RANK_MODE = 1
2228 13:56:54.802915 DLL_IDLE_MODE = 1
2229 13:56:54.806127 LP45_APHY_COMB_EN = 1
2230 13:56:54.809456 TX_ODT_DIS = 1
2231 13:56:54.810104 NEW_8X_MODE = 1
2232 13:56:54.813049 ===================================
2233 13:56:54.816111 ===================================
2234 13:56:54.819392 data_rate = 2400
2235 13:56:54.822575 CKR = 1
2236 13:56:54.826320 DQ_P2S_RATIO = 8
2237 13:56:54.829652 ===================================
2238 13:56:54.832729 CA_P2S_RATIO = 8
2239 13:56:54.833140 DQ_CA_OPEN = 0
2240 13:56:54.836042 DQ_SEMI_OPEN = 0
2241 13:56:54.839567 CA_SEMI_OPEN = 0
2242 13:56:54.843175 CA_FULL_RATE = 0
2243 13:56:54.846471 DQ_CKDIV4_EN = 0
2244 13:56:54.849919 CA_CKDIV4_EN = 0
2245 13:56:54.850433 CA_PREDIV_EN = 0
2246 13:56:54.853168 PH8_DLY = 17
2247 13:56:54.856417 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2248 13:56:54.859527 DQ_AAMCK_DIV = 4
2249 13:56:54.862998 CA_AAMCK_DIV = 4
2250 13:56:54.866194 CA_ADMCK_DIV = 4
2251 13:56:54.866668 DQ_TRACK_CA_EN = 0
2252 13:56:54.869841 CA_PICK = 1200
2253 13:56:54.873134 CA_MCKIO = 1200
2254 13:56:54.876559 MCKIO_SEMI = 0
2255 13:56:54.879608 PLL_FREQ = 2366
2256 13:56:54.882982 DQ_UI_PI_RATIO = 32
2257 13:56:54.886188 CA_UI_PI_RATIO = 0
2258 13:56:54.889421 ===================================
2259 13:56:54.893043 ===================================
2260 13:56:54.893655 memory_type:LPDDR4
2261 13:56:54.896580 GP_NUM : 10
2262 13:56:54.899389 SRAM_EN : 1
2263 13:56:54.899854 MD32_EN : 0
2264 13:56:54.902526 ===================================
2265 13:56:54.905932 [ANA_INIT] >>>>>>>>>>>>>>
2266 13:56:54.909446 <<<<<< [CONFIGURE PHASE]: ANA_TX
2267 13:56:54.912865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2268 13:56:54.915909 ===================================
2269 13:56:54.919392 data_rate = 2400,PCW = 0X5b00
2270 13:56:54.923003 ===================================
2271 13:56:54.926078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2272 13:56:54.929697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2273 13:56:54.936060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 13:56:54.939152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2275 13:56:54.942709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2276 13:56:54.945968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2277 13:56:54.949296 [ANA_INIT] flow start
2278 13:56:54.952421 [ANA_INIT] PLL >>>>>>>>
2279 13:56:54.952881 [ANA_INIT] PLL <<<<<<<<
2280 13:56:54.956061 [ANA_INIT] MIDPI >>>>>>>>
2281 13:56:54.959739 [ANA_INIT] MIDPI <<<<<<<<
2282 13:56:54.960295 [ANA_INIT] DLL >>>>>>>>
2283 13:56:54.962486 [ANA_INIT] DLL <<<<<<<<
2284 13:56:54.965847 [ANA_INIT] flow end
2285 13:56:54.969590 ============ LP4 DIFF to SE enter ============
2286 13:56:54.972638 ============ LP4 DIFF to SE exit ============
2287 13:56:54.976308 [ANA_INIT] <<<<<<<<<<<<<
2288 13:56:54.979433 [Flow] Enable top DCM control >>>>>
2289 13:56:54.982650 [Flow] Enable top DCM control <<<<<
2290 13:56:54.985978 Enable DLL master slave shuffle
2291 13:56:54.989533 ==============================================================
2292 13:56:54.993037 Gating Mode config
2293 13:56:54.999223 ==============================================================
2294 13:56:54.999786 Config description:
2295 13:56:55.009290 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2296 13:56:55.015911 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2297 13:56:55.022199 SELPH_MODE 0: By rank 1: By Phase
2298 13:56:55.026001 ==============================================================
2299 13:56:55.029441 GAT_TRACK_EN = 1
2300 13:56:55.032624 RX_GATING_MODE = 2
2301 13:56:55.036149 RX_GATING_TRACK_MODE = 2
2302 13:56:55.039120 SELPH_MODE = 1
2303 13:56:55.042568 PICG_EARLY_EN = 1
2304 13:56:55.046299 VALID_LAT_VALUE = 1
2305 13:56:55.049010 ==============================================================
2306 13:56:55.052315 Enter into Gating configuration >>>>
2307 13:56:55.055621 Exit from Gating configuration <<<<
2308 13:56:55.059098 Enter into DVFS_PRE_config >>>>>
2309 13:56:55.072439 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2310 13:56:55.075832 Exit from DVFS_PRE_config <<<<<
2311 13:56:55.076394 Enter into PICG configuration >>>>
2312 13:56:55.078927 Exit from PICG configuration <<<<
2313 13:56:55.082434 [RX_INPUT] configuration >>>>>
2314 13:56:55.085682 [RX_INPUT] configuration <<<<<
2315 13:56:55.092461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2316 13:56:55.095977 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2317 13:56:55.102307 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 13:56:55.109618 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 13:56:55.115800 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2320 13:56:55.122405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2321 13:56:55.125585 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2322 13:56:55.129131 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2323 13:56:55.132667 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2324 13:56:55.139231 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2325 13:56:55.142418 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2326 13:56:55.145784 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2327 13:56:55.149215 ===================================
2328 13:56:55.152552 LPDDR4 DRAM CONFIGURATION
2329 13:56:55.155859 ===================================
2330 13:56:55.156333 EX_ROW_EN[0] = 0x0
2331 13:56:55.158696 EX_ROW_EN[1] = 0x0
2332 13:56:55.162423 LP4Y_EN = 0x0
2333 13:56:55.162981 WORK_FSP = 0x0
2334 13:56:55.166328 WL = 0x4
2335 13:56:55.166882 RL = 0x4
2336 13:56:55.169207 BL = 0x2
2337 13:56:55.169810 RPST = 0x0
2338 13:56:55.172020 RD_PRE = 0x0
2339 13:56:55.172483 WR_PRE = 0x1
2340 13:56:55.175652 WR_PST = 0x0
2341 13:56:55.176209 DBI_WR = 0x0
2342 13:56:55.179039 DBI_RD = 0x0
2343 13:56:55.179586 OTF = 0x1
2344 13:56:55.182279 ===================================
2345 13:56:55.185755 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2346 13:56:55.192253 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2347 13:56:55.195639 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2348 13:56:55.199128 ===================================
2349 13:56:55.202065 LPDDR4 DRAM CONFIGURATION
2350 13:56:55.205670 ===================================
2351 13:56:55.206254 EX_ROW_EN[0] = 0x10
2352 13:56:55.209027 EX_ROW_EN[1] = 0x0
2353 13:56:55.209641 LP4Y_EN = 0x0
2354 13:56:55.212516 WORK_FSP = 0x0
2355 13:56:55.213066 WL = 0x4
2356 13:56:55.215301 RL = 0x4
2357 13:56:55.218926 BL = 0x2
2358 13:56:55.219381 RPST = 0x0
2359 13:56:55.222034 RD_PRE = 0x0
2360 13:56:55.222485 WR_PRE = 0x1
2361 13:56:55.225673 WR_PST = 0x0
2362 13:56:55.226124 DBI_WR = 0x0
2363 13:56:55.228617 DBI_RD = 0x0
2364 13:56:55.229024 OTF = 0x1
2365 13:56:55.232284 ===================================
2366 13:56:55.238600 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2367 13:56:55.239014 ==
2368 13:56:55.242051 Dram Type= 6, Freq= 0, CH_0, rank 0
2369 13:56:55.245933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 13:56:55.246448 ==
2371 13:56:55.249312 [Duty_Offset_Calibration]
2372 13:56:55.249857 B0:2 B1:0 CA:4
2373 13:56:55.252403
2374 13:56:55.255505 [DutyScan_Calibration_Flow] k_type=0
2375 13:56:55.263609
2376 13:56:55.264119 ==CLK 0==
2377 13:56:55.266488 Final CLK duty delay cell = 0
2378 13:56:55.270230 [0] MAX Duty = 5031%(X100), DQS PI = 12
2379 13:56:55.273636 [0] MIN Duty = 4907%(X100), DQS PI = 8
2380 13:56:55.274145 [0] AVG Duty = 4969%(X100)
2381 13:56:55.276573
2382 13:56:55.280156 CH0 CLK Duty spec in!! Max-Min= 124%
2383 13:56:55.283466 [DutyScan_Calibration_Flow] ====Done====
2384 13:56:55.283981
2385 13:56:55.286090 [DutyScan_Calibration_Flow] k_type=1
2386 13:56:55.301862
2387 13:56:55.302383 ==DQS 0 ==
2388 13:56:55.305150 Final DQS duty delay cell = 0
2389 13:56:55.308851 [0] MAX Duty = 5062%(X100), DQS PI = 12
2390 13:56:55.311633 [0] MIN Duty = 4907%(X100), DQS PI = 2
2391 13:56:55.312046 [0] AVG Duty = 4984%(X100)
2392 13:56:55.315137
2393 13:56:55.315648 ==DQS 1 ==
2394 13:56:55.318338 Final DQS duty delay cell = -4
2395 13:56:55.321846 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2396 13:56:55.325279 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2397 13:56:55.328504 [-4] AVG Duty = 4922%(X100)
2398 13:56:55.329009
2399 13:56:55.331970 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2400 13:56:55.332497
2401 13:56:55.335138 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2402 13:56:55.338141 [DutyScan_Calibration_Flow] ====Done====
2403 13:56:55.338556
2404 13:56:55.341965 [DutyScan_Calibration_Flow] k_type=3
2405 13:56:55.359381
2406 13:56:55.359887 ==DQM 0 ==
2407 13:56:55.362843 Final DQM duty delay cell = 0
2408 13:56:55.366125 [0] MAX Duty = 5124%(X100), DQS PI = 28
2409 13:56:55.369654 [0] MIN Duty = 4876%(X100), DQS PI = 0
2410 13:56:55.370163 [0] AVG Duty = 5000%(X100)
2411 13:56:55.372875
2412 13:56:55.373382 ==DQM 1 ==
2413 13:56:55.376258 Final DQM duty delay cell = 4
2414 13:56:55.379467 [4] MAX Duty = 5124%(X100), DQS PI = 50
2415 13:56:55.382817 [4] MIN Duty = 5000%(X100), DQS PI = 12
2416 13:56:55.383325 [4] AVG Duty = 5062%(X100)
2417 13:56:55.386374
2418 13:56:55.389427 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2419 13:56:55.389980
2420 13:56:55.392741 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2421 13:56:55.396275 [DutyScan_Calibration_Flow] ====Done====
2422 13:56:55.396785
2423 13:56:55.398964 [DutyScan_Calibration_Flow] k_type=2
2424 13:56:55.414183
2425 13:56:55.414692 ==DQ 0 ==
2426 13:56:55.417261 Final DQ duty delay cell = -4
2427 13:56:55.420587 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2428 13:56:55.424359 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2429 13:56:55.427764 [-4] AVG Duty = 4969%(X100)
2430 13:56:55.428277
2431 13:56:55.428606 ==DQ 1 ==
2432 13:56:55.430986 Final DQ duty delay cell = -4
2433 13:56:55.434076 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2434 13:56:55.437606 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2435 13:56:55.440862 [-4] AVG Duty = 4938%(X100)
2436 13:56:55.441379
2437 13:56:55.444625 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2438 13:56:55.445149
2439 13:56:55.447811 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2440 13:56:55.451258 [DutyScan_Calibration_Flow] ====Done====
2441 13:56:55.451773 ==
2442 13:56:55.454177 Dram Type= 6, Freq= 0, CH_1, rank 0
2443 13:56:55.457419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2444 13:56:55.457905 ==
2445 13:56:55.461292 [Duty_Offset_Calibration]
2446 13:56:55.461857 B0:1 B1:-3 CA:1
2447 13:56:55.462195
2448 13:56:55.464161 [DutyScan_Calibration_Flow] k_type=0
2449 13:56:55.474892
2450 13:56:55.475402 ==CLK 0==
2451 13:56:55.478460 Final CLK duty delay cell = 0
2452 13:56:55.481738 [0] MAX Duty = 5031%(X100), DQS PI = 18
2453 13:56:55.485125 [0] MIN Duty = 4844%(X100), DQS PI = 58
2454 13:56:55.485685 [0] AVG Duty = 4937%(X100)
2455 13:56:55.488160
2456 13:56:55.491622 CH1 CLK Duty spec in!! Max-Min= 187%
2457 13:56:55.495068 [DutyScan_Calibration_Flow] ====Done====
2458 13:56:55.495582
2459 13:56:55.498447 [DutyScan_Calibration_Flow] k_type=1
2460 13:56:55.513435
2461 13:56:55.514020 ==DQS 0 ==
2462 13:56:55.516794 Final DQS duty delay cell = -4
2463 13:56:55.519905 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2464 13:56:55.523503 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2465 13:56:55.526261 [-4] AVG Duty = 4969%(X100)
2466 13:56:55.526716
2467 13:56:55.527078 ==DQS 1 ==
2468 13:56:55.529740 Final DQS duty delay cell = 0
2469 13:56:55.533156 [0] MAX Duty = 5062%(X100), DQS PI = 0
2470 13:56:55.536813 [0] MIN Duty = 4844%(X100), DQS PI = 26
2471 13:56:55.539693 [0] AVG Duty = 4953%(X100)
2472 13:56:55.540153
2473 13:56:55.542987 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2474 13:56:55.543653
2475 13:56:55.546248 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2476 13:56:55.549561 [DutyScan_Calibration_Flow] ====Done====
2477 13:56:55.549975
2478 13:56:55.552728 [DutyScan_Calibration_Flow] k_type=3
2479 13:56:55.569914
2480 13:56:55.570324 ==DQM 0 ==
2481 13:56:55.573238 Final DQM duty delay cell = 0
2482 13:56:55.576665 [0] MAX Duty = 5000%(X100), DQS PI = 22
2483 13:56:55.579584 [0] MIN Duty = 4876%(X100), DQS PI = 2
2484 13:56:55.583107 [0] AVG Duty = 4938%(X100)
2485 13:56:55.583524
2486 13:56:55.583856 ==DQM 1 ==
2487 13:56:55.586585 Final DQM duty delay cell = 0
2488 13:56:55.589889 [0] MAX Duty = 5062%(X100), DQS PI = 38
2489 13:56:55.592915 [0] MIN Duty = 4875%(X100), DQS PI = 26
2490 13:56:55.596704 [0] AVG Duty = 4968%(X100)
2491 13:56:55.597224
2492 13:56:55.600273 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2493 13:56:55.600787
2494 13:56:55.602853 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2495 13:56:55.606360 [DutyScan_Calibration_Flow] ====Done====
2496 13:56:55.606882
2497 13:56:55.609719 [DutyScan_Calibration_Flow] k_type=2
2498 13:56:55.626364
2499 13:56:55.626891 ==DQ 0 ==
2500 13:56:55.629686 Final DQ duty delay cell = 0
2501 13:56:55.632918 [0] MAX Duty = 5062%(X100), DQS PI = 18
2502 13:56:55.636317 [0] MIN Duty = 4938%(X100), DQS PI = 54
2503 13:56:55.636837 [0] AVG Duty = 5000%(X100)
2504 13:56:55.639853
2505 13:56:55.640427 ==DQ 1 ==
2506 13:56:55.642690 Final DQ duty delay cell = 0
2507 13:56:55.646109 [0] MAX Duty = 5124%(X100), DQS PI = 36
2508 13:56:55.650027 [0] MIN Duty = 4969%(X100), DQS PI = 26
2509 13:56:55.650545 [0] AVG Duty = 5046%(X100)
2510 13:56:55.650883
2511 13:56:55.652955 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2512 13:56:55.656044
2513 13:56:55.659520 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2514 13:56:55.663108 [DutyScan_Calibration_Flow] ====Done====
2515 13:56:55.666049 nWR fixed to 30
2516 13:56:55.666462 [ModeRegInit_LP4] CH0 RK0
2517 13:56:55.669824 [ModeRegInit_LP4] CH0 RK1
2518 13:56:55.673059 [ModeRegInit_LP4] CH1 RK0
2519 13:56:55.676508 [ModeRegInit_LP4] CH1 RK1
2520 13:56:55.677080 match AC timing 7
2521 13:56:55.679601 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2522 13:56:55.683231 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2523 13:56:55.689676 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2524 13:56:55.693241 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2525 13:56:55.699710 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2526 13:56:55.700233 ==
2527 13:56:55.702781 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 13:56:55.706400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 13:56:55.706982 ==
2530 13:56:55.713157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2531 13:56:55.719466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2532 13:56:55.726568 [CA 0] Center 40 (10~71) winsize 62
2533 13:56:55.729757 [CA 1] Center 39 (9~70) winsize 62
2534 13:56:55.733459 [CA 2] Center 36 (6~66) winsize 61
2535 13:56:55.736428 [CA 3] Center 35 (5~66) winsize 62
2536 13:56:55.739964 [CA 4] Center 34 (4~65) winsize 62
2537 13:56:55.743118 [CA 5] Center 33 (3~63) winsize 61
2538 13:56:55.743527
2539 13:56:55.746713 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2540 13:56:55.747259
2541 13:56:55.750138 [CATrainingPosCal] consider 1 rank data
2542 13:56:55.753257 u2DelayCellTimex100 = 270/100 ps
2543 13:56:55.756301 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2544 13:56:55.759725 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2545 13:56:55.766594 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2546 13:56:55.770306 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 13:56:55.773258 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2548 13:56:55.776778 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2549 13:56:55.777287
2550 13:56:55.779911 CA PerBit enable=1, Macro0, CA PI delay=33
2551 13:56:55.780420
2552 13:56:55.783427 [CBTSetCACLKResult] CA Dly = 33
2553 13:56:55.783932 CS Dly: 7 (0~38)
2554 13:56:55.786302 ==
2555 13:56:55.789884 Dram Type= 6, Freq= 0, CH_0, rank 1
2556 13:56:55.793369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 13:56:55.793937 ==
2558 13:56:55.796283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2559 13:56:55.803215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2560 13:56:55.812526 [CA 0] Center 40 (10~70) winsize 61
2561 13:56:55.816137 [CA 1] Center 39 (9~70) winsize 62
2562 13:56:55.819177 [CA 2] Center 35 (5~66) winsize 62
2563 13:56:55.822442 [CA 3] Center 35 (5~66) winsize 62
2564 13:56:55.825796 [CA 4] Center 34 (4~65) winsize 62
2565 13:56:55.829341 [CA 5] Center 33 (3~64) winsize 62
2566 13:56:55.829900
2567 13:56:55.832680 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2568 13:56:55.833191
2569 13:56:55.835892 [CATrainingPosCal] consider 2 rank data
2570 13:56:55.839588 u2DelayCellTimex100 = 270/100 ps
2571 13:56:55.842504 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2572 13:56:55.846106 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2573 13:56:55.852449 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2574 13:56:55.855628 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2575 13:56:55.858911 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2576 13:56:55.862535 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2577 13:56:55.863058
2578 13:56:55.865776 CA PerBit enable=1, Macro0, CA PI delay=33
2579 13:56:55.866232
2580 13:56:55.869230 [CBTSetCACLKResult] CA Dly = 33
2581 13:56:55.869788 CS Dly: 8 (0~40)
2582 13:56:55.872619
2583 13:56:55.876022 ----->DramcWriteLeveling(PI) begin...
2584 13:56:55.876545 ==
2585 13:56:55.879493 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 13:56:55.882435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 13:56:55.882901 ==
2588 13:56:55.886116 Write leveling (Byte 0): 33 => 33
2589 13:56:55.889526 Write leveling (Byte 1): 29 => 29
2590 13:56:55.892591 DramcWriteLeveling(PI) end<-----
2591 13:56:55.893102
2592 13:56:55.893437 ==
2593 13:56:55.896054 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 13:56:55.899424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 13:56:55.899939 ==
2596 13:56:55.902366 [Gating] SW mode calibration
2597 13:56:55.909236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2598 13:56:55.916074 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2599 13:56:55.919166 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 13:56:55.922275 0 15 4 | B1->B0 | 2525 3333 | 0 1 | (0 0) (0 0)
2601 13:56:55.929021 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 13:56:55.932556 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 13:56:55.935836 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 13:56:55.939253 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 13:56:55.945466 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 13:56:55.948869 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2607 13:56:55.952182 1 0 0 | B1->B0 | 3333 2c2c | 1 1 | (1 0) (1 0)
2608 13:56:55.959012 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2609 13:56:55.962211 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 13:56:55.965917 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 13:56:55.972151 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 13:56:55.976000 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 13:56:55.979232 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 13:56:55.986125 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2615 13:56:55.989126 1 1 0 | B1->B0 | 2828 3131 | 0 0 | (0 0) (1 1)
2616 13:56:55.992564 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2617 13:56:55.999099 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 13:56:56.002597 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 13:56:56.005685 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 13:56:56.012697 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 13:56:56.015852 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 13:56:56.018944 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2623 13:56:56.025862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2624 13:56:56.028748 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2625 13:56:56.032063 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 13:56:56.038774 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 13:56:56.042039 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 13:56:56.045514 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 13:56:56.049040 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 13:56:56.055377 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 13:56:56.058495 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 13:56:56.062271 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 13:56:56.068668 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 13:56:56.072438 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 13:56:56.075171 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 13:56:56.082338 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 13:56:56.085472 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 13:56:56.089158 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2639 13:56:56.095782 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2640 13:56:56.096376 Total UI for P1: 0, mck2ui 16
2641 13:56:56.102084 best dqsien dly found for B0: ( 1, 3, 28)
2642 13:56:56.105461 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2643 13:56:56.109158 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2644 13:56:56.112041 Total UI for P1: 0, mck2ui 16
2645 13:56:56.115430 best dqsien dly found for B1: ( 1, 4, 2)
2646 13:56:56.118492 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2647 13:56:56.121774 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2648 13:56:56.122204
2649 13:56:56.128715 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2650 13:56:56.131724 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2651 13:56:56.132190 [Gating] SW calibration Done
2652 13:56:56.135110 ==
2653 13:56:56.135624 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 13:56:56.141624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 13:56:56.142189 ==
2656 13:56:56.142671 RX Vref Scan: 0
2657 13:56:56.143176
2658 13:56:56.145076 RX Vref 0 -> 0, step: 1
2659 13:56:56.145673
2660 13:56:56.148295 RX Delay -40 -> 252, step: 8
2661 13:56:56.151814 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2662 13:56:56.155024 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2663 13:56:56.158615 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
2664 13:56:56.164895 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2665 13:56:56.168182 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2666 13:56:56.171642 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2667 13:56:56.174897 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2668 13:56:56.178484 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2669 13:56:56.181969 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2670 13:56:56.188533 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2671 13:56:56.191566 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2672 13:56:56.195091 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2673 13:56:56.198276 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2674 13:56:56.201629 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2675 13:56:56.208532 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2676 13:56:56.211825 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2677 13:56:56.212462 ==
2678 13:56:56.215415 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 13:56:56.218701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 13:56:56.219151 ==
2681 13:56:56.221931 DQS Delay:
2682 13:56:56.222546 DQS0 = 0, DQS1 = 0
2683 13:56:56.223096 DQM Delay:
2684 13:56:56.225255 DQM0 = 111, DQM1 = 102
2685 13:56:56.225891 DQ Delay:
2686 13:56:56.228421 DQ0 =111, DQ1 =111, DQ2 =107, DQ3 =107
2687 13:56:56.231810 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2688 13:56:56.235127 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2689 13:56:56.238692 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2690 13:56:56.242100
2691 13:56:56.242593
2692 13:56:56.242931 ==
2693 13:56:56.245335 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 13:56:56.248919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 13:56:56.249338 ==
2696 13:56:56.249740
2697 13:56:56.250055
2698 13:56:56.252050 TX Vref Scan disable
2699 13:56:56.252466 == TX Byte 0 ==
2700 13:56:56.258482 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2701 13:56:56.262062 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2702 13:56:56.262482 == TX Byte 1 ==
2703 13:56:56.268575 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2704 13:56:56.271885 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2705 13:56:56.272305 ==
2706 13:56:56.275279 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 13:56:56.278364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 13:56:56.278787 ==
2709 13:56:56.291033 TX Vref=22, minBit 1, minWin=25, winSum=417
2710 13:56:56.294444 TX Vref=24, minBit 1, minWin=26, winSum=428
2711 13:56:56.297226 TX Vref=26, minBit 7, minWin=26, winSum=433
2712 13:56:56.300878 TX Vref=28, minBit 13, minWin=26, winSum=436
2713 13:56:56.304242 TX Vref=30, minBit 1, minWin=27, winSum=436
2714 13:56:56.310662 TX Vref=32, minBit 2, minWin=26, winSum=428
2715 13:56:56.313779 [TxChooseVref] Worse bit 1, Min win 27, Win sum 436, Final Vref 30
2716 13:56:56.313867
2717 13:56:56.317488 Final TX Range 1 Vref 30
2718 13:56:56.317584
2719 13:56:56.317648 ==
2720 13:56:56.320466 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 13:56:56.324153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 13:56:56.324236 ==
2723 13:56:56.327153
2724 13:56:56.327234
2725 13:56:56.327297 TX Vref Scan disable
2726 13:56:56.330499 == TX Byte 0 ==
2727 13:56:56.333836 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2728 13:56:56.340371 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2729 13:56:56.340452 == TX Byte 1 ==
2730 13:56:56.343636 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2731 13:56:56.350371 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2732 13:56:56.350452
2733 13:56:56.350516 [DATLAT]
2734 13:56:56.350576 Freq=1200, CH0 RK0
2735 13:56:56.350634
2736 13:56:56.353735 DATLAT Default: 0xd
2737 13:56:56.353816 0, 0xFFFF, sum = 0
2738 13:56:56.357075 1, 0xFFFF, sum = 0
2739 13:56:56.360744 2, 0xFFFF, sum = 0
2740 13:56:56.360826 3, 0xFFFF, sum = 0
2741 13:56:56.363612 4, 0xFFFF, sum = 0
2742 13:56:56.363696 5, 0xFFFF, sum = 0
2743 13:56:56.367279 6, 0xFFFF, sum = 0
2744 13:56:56.367362 7, 0xFFFF, sum = 0
2745 13:56:56.370445 8, 0xFFFF, sum = 0
2746 13:56:56.370528 9, 0xFFFF, sum = 0
2747 13:56:56.373765 10, 0xFFFF, sum = 0
2748 13:56:56.373847 11, 0xFFFF, sum = 0
2749 13:56:56.377016 12, 0x0, sum = 1
2750 13:56:56.377098 13, 0x0, sum = 2
2751 13:56:56.380453 14, 0x0, sum = 3
2752 13:56:56.380535 15, 0x0, sum = 4
2753 13:56:56.380600 best_step = 13
2754 13:56:56.384036
2755 13:56:56.384116 ==
2756 13:56:56.387104 Dram Type= 6, Freq= 0, CH_0, rank 0
2757 13:56:56.390683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2758 13:56:56.390771 ==
2759 13:56:56.390839 RX Vref Scan: 1
2760 13:56:56.390904
2761 13:56:56.393965 Set Vref Range= 32 -> 127
2762 13:56:56.394046
2763 13:56:56.397034 RX Vref 32 -> 127, step: 1
2764 13:56:56.397115
2765 13:56:56.400397 RX Delay -37 -> 252, step: 4
2766 13:56:56.400479
2767 13:56:56.403802 Set Vref, RX VrefLevel [Byte0]: 32
2768 13:56:56.407129 [Byte1]: 32
2769 13:56:56.407211
2770 13:56:56.410326 Set Vref, RX VrefLevel [Byte0]: 33
2771 13:56:56.413739 [Byte1]: 33
2772 13:56:56.417269
2773 13:56:56.417350 Set Vref, RX VrefLevel [Byte0]: 34
2774 13:56:56.420752 [Byte1]: 34
2775 13:56:56.425679
2776 13:56:56.426099 Set Vref, RX VrefLevel [Byte0]: 35
2777 13:56:56.428908 [Byte1]: 35
2778 13:56:56.434168
2779 13:56:56.434691 Set Vref, RX VrefLevel [Byte0]: 36
2780 13:56:56.436914 [Byte1]: 36
2781 13:56:56.441947
2782 13:56:56.442469 Set Vref, RX VrefLevel [Byte0]: 37
2783 13:56:56.445306 [Byte1]: 37
2784 13:56:56.449883
2785 13:56:56.450401 Set Vref, RX VrefLevel [Byte0]: 38
2786 13:56:56.453351 [Byte1]: 38
2787 13:56:56.457720
2788 13:56:56.458155 Set Vref, RX VrefLevel [Byte0]: 39
2789 13:56:56.461120 [Byte1]: 39
2790 13:56:56.466006
2791 13:56:56.466544 Set Vref, RX VrefLevel [Byte0]: 40
2792 13:56:56.469298 [Byte1]: 40
2793 13:56:56.473750
2794 13:56:56.474273 Set Vref, RX VrefLevel [Byte0]: 41
2795 13:56:56.476955 [Byte1]: 41
2796 13:56:56.481608
2797 13:56:56.482031 Set Vref, RX VrefLevel [Byte0]: 42
2798 13:56:56.484879 [Byte1]: 42
2799 13:56:56.489393
2800 13:56:56.489961 Set Vref, RX VrefLevel [Byte0]: 43
2801 13:56:56.493009 [Byte1]: 43
2802 13:56:56.497575
2803 13:56:56.498042 Set Vref, RX VrefLevel [Byte0]: 44
2804 13:56:56.500755 [Byte1]: 44
2805 13:56:56.505614
2806 13:56:56.506030 Set Vref, RX VrefLevel [Byte0]: 45
2807 13:56:56.508872 [Byte1]: 45
2808 13:56:56.513630
2809 13:56:56.514167 Set Vref, RX VrefLevel [Byte0]: 46
2810 13:56:56.516760 [Byte1]: 46
2811 13:56:56.521687
2812 13:56:56.521994 Set Vref, RX VrefLevel [Byte0]: 47
2813 13:56:56.524541 [Byte1]: 47
2814 13:56:56.529289
2815 13:56:56.529529 Set Vref, RX VrefLevel [Byte0]: 48
2816 13:56:56.532819 [Byte1]: 48
2817 13:56:56.537219
2818 13:56:56.537398 Set Vref, RX VrefLevel [Byte0]: 49
2819 13:56:56.540544 [Byte1]: 49
2820 13:56:56.545374
2821 13:56:56.548194 Set Vref, RX VrefLevel [Byte0]: 50
2822 13:56:56.551756 [Byte1]: 50
2823 13:56:56.551837
2824 13:56:56.555189 Set Vref, RX VrefLevel [Byte0]: 51
2825 13:56:56.558350 [Byte1]: 51
2826 13:56:56.558432
2827 13:56:56.561810 Set Vref, RX VrefLevel [Byte0]: 52
2828 13:56:56.564827 [Byte1]: 52
2829 13:56:56.569251
2830 13:56:56.569332 Set Vref, RX VrefLevel [Byte0]: 53
2831 13:56:56.572676 [Byte1]: 53
2832 13:56:56.577242
2833 13:56:56.577322 Set Vref, RX VrefLevel [Byte0]: 54
2834 13:56:56.580544 [Byte1]: 54
2835 13:56:56.585254
2836 13:56:56.585335 Set Vref, RX VrefLevel [Byte0]: 55
2837 13:56:56.588273 [Byte1]: 55
2838 13:56:56.593371
2839 13:56:56.593452 Set Vref, RX VrefLevel [Byte0]: 56
2840 13:56:56.596458 [Byte1]: 56
2841 13:56:56.601201
2842 13:56:56.601326 Set Vref, RX VrefLevel [Byte0]: 57
2843 13:56:56.604579 [Byte1]: 57
2844 13:56:56.609296
2845 13:56:56.609422 Set Vref, RX VrefLevel [Byte0]: 58
2846 13:56:56.612406 [Byte1]: 58
2847 13:56:56.617410
2848 13:56:56.617569 Set Vref, RX VrefLevel [Byte0]: 59
2849 13:56:56.620416 [Byte1]: 59
2850 13:56:56.625197
2851 13:56:56.625283 Set Vref, RX VrefLevel [Byte0]: 60
2852 13:56:56.628524 [Byte1]: 60
2853 13:56:56.633267
2854 13:56:56.633349 Set Vref, RX VrefLevel [Byte0]: 61
2855 13:56:56.636524 [Byte1]: 61
2856 13:56:56.641158
2857 13:56:56.641268 Set Vref, RX VrefLevel [Byte0]: 62
2858 13:56:56.647659 [Byte1]: 62
2859 13:56:56.647745
2860 13:56:56.651076 Set Vref, RX VrefLevel [Byte0]: 63
2861 13:56:56.654150 [Byte1]: 63
2862 13:56:56.654257
2863 13:56:56.657581 Set Vref, RX VrefLevel [Byte0]: 64
2864 13:56:56.660844 [Byte1]: 64
2865 13:56:56.665211
2866 13:56:56.665291 Set Vref, RX VrefLevel [Byte0]: 65
2867 13:56:56.668836 [Byte1]: 65
2868 13:56:56.673857
2869 13:56:56.674028 Set Vref, RX VrefLevel [Byte0]: 66
2870 13:56:56.676795 [Byte1]: 66
2871 13:56:56.681699
2872 13:56:56.681878 Set Vref, RX VrefLevel [Byte0]: 67
2873 13:56:56.684985 [Byte1]: 67
2874 13:56:56.689859
2875 13:56:56.690046 Set Vref, RX VrefLevel [Byte0]: 68
2876 13:56:56.692905 [Byte1]: 68
2877 13:56:56.697583
2878 13:56:56.697752 Set Vref, RX VrefLevel [Byte0]: 69
2879 13:56:56.700636 [Byte1]: 69
2880 13:56:56.705302
2881 13:56:56.705451 Set Vref, RX VrefLevel [Byte0]: 70
2882 13:56:56.708847 [Byte1]: 70
2883 13:56:56.713589
2884 13:56:56.713816 Set Vref, RX VrefLevel [Byte0]: 71
2885 13:56:56.717396 [Byte1]: 71
2886 13:56:56.721755
2887 13:56:56.722088 Set Vref, RX VrefLevel [Byte0]: 72
2888 13:56:56.724717 [Byte1]: 72
2889 13:56:56.729901
2890 13:56:56.730191 Set Vref, RX VrefLevel [Byte0]: 73
2891 13:56:56.733054 [Byte1]: 73
2892 13:56:56.737843
2893 13:56:56.738251 Set Vref, RX VrefLevel [Byte0]: 74
2894 13:56:56.740904 [Byte1]: 74
2895 13:56:56.745847
2896 13:56:56.746359 Final RX Vref Byte 0 = 60 to rank0
2897 13:56:56.749360 Final RX Vref Byte 1 = 47 to rank0
2898 13:56:56.752555 Final RX Vref Byte 0 = 60 to rank1
2899 13:56:56.755734 Final RX Vref Byte 1 = 47 to rank1==
2900 13:56:56.759152 Dram Type= 6, Freq= 0, CH_0, rank 0
2901 13:56:56.762825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 13:56:56.765872 ==
2903 13:56:56.766299 DQS Delay:
2904 13:56:56.766735 DQS0 = 0, DQS1 = 0
2905 13:56:56.769070 DQM Delay:
2906 13:56:56.769687 DQM0 = 112, DQM1 = 98
2907 13:56:56.772567 DQ Delay:
2908 13:56:56.775987 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2909 13:56:56.779087 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2910 13:56:56.782587 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =92
2911 13:56:56.785729 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2912 13:56:56.786155
2913 13:56:56.786661
2914 13:56:56.792701 [DQSOSCAuto] RK0, (LSB)MR18= 0xfafa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2915 13:56:56.795670 CH0 RK0: MR19=303, MR18=FAFA
2916 13:56:56.802356 CH0_RK0: MR19=0x303, MR18=0xFAFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2917 13:56:56.802784
2918 13:56:56.805921 ----->DramcWriteLeveling(PI) begin...
2919 13:56:56.806351 ==
2920 13:56:56.808860 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 13:56:56.812343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 13:56:56.812573 ==
2923 13:56:56.815260 Write leveling (Byte 0): 32 => 32
2924 13:56:56.818822 Write leveling (Byte 1): 32 => 32
2925 13:56:56.822147 DramcWriteLeveling(PI) end<-----
2926 13:56:56.822229
2927 13:56:56.822312 ==
2928 13:56:56.825256 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 13:56:56.828801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 13:56:56.831945 ==
2931 13:56:56.832045 [Gating] SW mode calibration
2932 13:56:56.841928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2933 13:56:56.845322 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2934 13:56:56.848413 0 15 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2935 13:56:56.855116 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 13:56:56.858717 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2937 13:56:56.861899 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2938 13:56:56.868606 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2939 13:56:56.872146 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2940 13:56:56.875224 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2941 13:56:56.882086 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2942 13:56:56.885084 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2943 13:56:56.888608 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 13:56:56.895321 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2945 13:56:56.898482 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2946 13:56:56.901858 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2947 13:56:56.908519 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2948 13:56:56.911787 1 0 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2949 13:56:56.915414 1 0 28 | B1->B0 | 2828 4444 | 0 0 | (1 1) (0 0)
2950 13:56:56.922013 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2951 13:56:56.925128 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 13:56:56.928804 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 13:56:56.931697 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 13:56:56.938773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 13:56:56.941870 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 13:56:56.945238 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 13:56:56.951723 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2958 13:56:56.955091 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2959 13:56:56.958722 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 13:56:56.965219 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 13:56:56.968359 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 13:56:56.971638 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 13:56:56.978358 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 13:56:56.981708 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 13:56:56.984858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 13:56:56.991615 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 13:56:56.994878 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 13:56:56.998437 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 13:56:57.005041 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 13:56:57.008404 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 13:56:57.011943 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 13:56:57.018435 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 13:56:57.021969 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2974 13:56:57.024896 Total UI for P1: 0, mck2ui 16
2975 13:56:57.028438 best dqsien dly found for B0: ( 1, 3, 26)
2976 13:56:57.031883 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2977 13:56:57.035035 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 13:56:57.038517 Total UI for P1: 0, mck2ui 16
2979 13:56:57.041483 best dqsien dly found for B1: ( 1, 4, 0)
2980 13:56:57.045001 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2981 13:56:57.048300 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2982 13:56:57.051637
2983 13:56:57.054816 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2984 13:56:57.058279 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2985 13:56:57.061613 [Gating] SW calibration Done
2986 13:56:57.061698 ==
2987 13:56:57.064804 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 13:56:57.068414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 13:56:57.068496 ==
2990 13:56:57.068559 RX Vref Scan: 0
2991 13:56:57.068619
2992 13:56:57.071568 RX Vref 0 -> 0, step: 1
2993 13:56:57.071649
2994 13:56:57.075039 RX Delay -40 -> 252, step: 8
2995 13:56:57.078535 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2996 13:56:57.081718 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2997 13:56:57.088175 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2998 13:56:57.091855 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2999 13:56:57.095106 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3000 13:56:57.098331 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
3001 13:56:57.101896 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3002 13:56:57.104985 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3003 13:56:57.111610 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3004 13:56:57.115030 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
3005 13:56:57.118251 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3006 13:56:57.121727 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3007 13:56:57.125151 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3008 13:56:57.131736 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
3009 13:56:57.135090 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3010 13:56:57.138622 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3011 13:56:57.138703 ==
3012 13:56:57.141729 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 13:56:57.145213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 13:56:57.145294 ==
3015 13:56:57.148714 DQS Delay:
3016 13:56:57.148797 DQS0 = 0, DQS1 = 0
3017 13:56:57.151974 DQM Delay:
3018 13:56:57.152080 DQM0 = 112, DQM1 = 101
3019 13:56:57.152172 DQ Delay:
3020 13:56:57.155161 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3021 13:56:57.158461 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3022 13:56:57.162183 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3023 13:56:57.168757 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
3024 13:56:57.168841
3025 13:56:57.168966
3026 13:56:57.169026 ==
3027 13:56:57.171809 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 13:56:57.175195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 13:56:57.175276 ==
3030 13:56:57.175339
3031 13:56:57.175403
3032 13:56:57.178374 TX Vref Scan disable
3033 13:56:57.178454 == TX Byte 0 ==
3034 13:56:57.185054 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3035 13:56:57.188601 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3036 13:56:57.188674 == TX Byte 1 ==
3037 13:56:57.195158 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3038 13:56:57.198504 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3039 13:56:57.198585 ==
3040 13:56:57.201769 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 13:56:57.204994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 13:56:57.205080 ==
3043 13:56:57.217950 TX Vref=22, minBit 1, minWin=26, winSum=427
3044 13:56:57.221214 TX Vref=24, minBit 12, minWin=26, winSum=434
3045 13:56:57.224660 TX Vref=26, minBit 0, minWin=26, winSum=429
3046 13:56:57.227923 TX Vref=28, minBit 1, minWin=26, winSum=438
3047 13:56:57.231172 TX Vref=30, minBit 1, minWin=27, winSum=440
3048 13:56:57.237732 TX Vref=32, minBit 13, minWin=26, winSum=441
3049 13:56:57.241073 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 30
3050 13:56:57.241217
3051 13:56:57.244625 Final TX Range 1 Vref 30
3052 13:56:57.244748
3053 13:56:57.244844 ==
3054 13:56:57.247689 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 13:56:57.251032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 13:56:57.251195 ==
3057 13:56:57.254663
3058 13:56:57.254807
3059 13:56:57.254949 TX Vref Scan disable
3060 13:56:57.257631 == TX Byte 0 ==
3061 13:56:57.261095 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3062 13:56:57.264413 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3063 13:56:57.268011 == TX Byte 1 ==
3064 13:56:57.271295 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3065 13:56:57.274541 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3066 13:56:57.274654
3067 13:56:57.277803 [DATLAT]
3068 13:56:57.277923 Freq=1200, CH0 RK1
3069 13:56:57.278020
3070 13:56:57.281088 DATLAT Default: 0xd
3071 13:56:57.281207 0, 0xFFFF, sum = 0
3072 13:56:57.284673 1, 0xFFFF, sum = 0
3073 13:56:57.284796 2, 0xFFFF, sum = 0
3074 13:56:57.287962 3, 0xFFFF, sum = 0
3075 13:56:57.288085 4, 0xFFFF, sum = 0
3076 13:56:57.291311 5, 0xFFFF, sum = 0
3077 13:56:57.291432 6, 0xFFFF, sum = 0
3078 13:56:57.294302 7, 0xFFFF, sum = 0
3079 13:56:57.297884 8, 0xFFFF, sum = 0
3080 13:56:57.298006 9, 0xFFFF, sum = 0
3081 13:56:57.301247 10, 0xFFFF, sum = 0
3082 13:56:57.301369 11, 0xFFFF, sum = 0
3083 13:56:57.304188 12, 0x0, sum = 1
3084 13:56:57.304286 13, 0x0, sum = 2
3085 13:56:57.307760 14, 0x0, sum = 3
3086 13:56:57.307842 15, 0x0, sum = 4
3087 13:56:57.307907 best_step = 13
3088 13:56:57.310799
3089 13:56:57.310878 ==
3090 13:56:57.314231 Dram Type= 6, Freq= 0, CH_0, rank 1
3091 13:56:57.317483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 13:56:57.317578 ==
3093 13:56:57.317642 RX Vref Scan: 0
3094 13:56:57.317734
3095 13:56:57.320795 RX Vref 0 -> 0, step: 1
3096 13:56:57.320907
3097 13:56:57.324292 RX Delay -37 -> 252, step: 4
3098 13:56:57.327622 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3099 13:56:57.334053 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3100 13:56:57.337549 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3101 13:56:57.341053 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3102 13:56:57.344346 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3103 13:56:57.347862 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3104 13:56:57.354724 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3105 13:56:57.357563 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3106 13:56:57.360872 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3107 13:56:57.364364 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3108 13:56:57.367426 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3109 13:56:57.370813 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3110 13:56:57.377489 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3111 13:56:57.380774 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3112 13:56:57.384366 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3113 13:56:57.387728 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3114 13:56:57.387884 ==
3115 13:56:57.391096 Dram Type= 6, Freq= 0, CH_0, rank 1
3116 13:56:57.397457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 13:56:57.397620 ==
3118 13:56:57.397741 DQS Delay:
3119 13:56:57.400961 DQS0 = 0, DQS1 = 0
3120 13:56:57.401110 DQM Delay:
3121 13:56:57.401229 DQM0 = 111, DQM1 = 99
3122 13:56:57.404321 DQ Delay:
3123 13:56:57.407681 DQ0 =108, DQ1 =110, DQ2 =110, DQ3 =108
3124 13:56:57.410872 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3125 13:56:57.414208 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
3126 13:56:57.417552 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3127 13:56:57.417703
3128 13:56:57.417821
3129 13:56:57.427308 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3130 13:56:57.427463 CH0 RK1: MR19=403, MR18=13FC
3131 13:56:57.434084 CH0_RK1: MR19=0x403, MR18=0x13FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3132 13:56:57.437489 [RxdqsGatingPostProcess] freq 1200
3133 13:56:57.443990 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3134 13:56:57.447382 best DQS0 dly(2T, 0.5T) = (0, 11)
3135 13:56:57.450928 best DQS1 dly(2T, 0.5T) = (0, 12)
3136 13:56:57.454300 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3137 13:56:57.457497 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3138 13:56:57.457649 best DQS0 dly(2T, 0.5T) = (0, 11)
3139 13:56:57.460797 best DQS1 dly(2T, 0.5T) = (0, 12)
3140 13:56:57.464100 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3141 13:56:57.467550 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3142 13:56:57.470737 Pre-setting of DQS Precalculation
3143 13:56:57.477656 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3144 13:56:57.477806 ==
3145 13:56:57.481144 Dram Type= 6, Freq= 0, CH_1, rank 0
3146 13:56:57.484203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 13:56:57.484381 ==
3148 13:56:57.490728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3149 13:56:57.493969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3150 13:56:57.504260 [CA 0] Center 37 (7~67) winsize 61
3151 13:56:57.506947 [CA 1] Center 37 (7~68) winsize 62
3152 13:56:57.510473 [CA 2] Center 34 (4~64) winsize 61
3153 13:56:57.513747 [CA 3] Center 34 (4~64) winsize 61
3154 13:56:57.517159 [CA 4] Center 34 (4~64) winsize 61
3155 13:56:57.520575 [CA 5] Center 33 (3~63) winsize 61
3156 13:56:57.520679
3157 13:56:57.523760 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3158 13:56:57.523864
3159 13:56:57.527189 [CATrainingPosCal] consider 1 rank data
3160 13:56:57.530434 u2DelayCellTimex100 = 270/100 ps
3161 13:56:57.534047 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3162 13:56:57.537005 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3163 13:56:57.543668 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3164 13:56:57.547027 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3165 13:56:57.550353 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3166 13:56:57.553915 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3167 13:56:57.554060
3168 13:56:57.557337 CA PerBit enable=1, Macro0, CA PI delay=33
3169 13:56:57.557506
3170 13:56:57.560427 [CBTSetCACLKResult] CA Dly = 33
3171 13:56:57.560592 CS Dly: 6 (0~37)
3172 13:56:57.560760 ==
3173 13:56:57.563831 Dram Type= 6, Freq= 0, CH_1, rank 1
3174 13:56:57.570395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 13:56:57.570540 ==
3176 13:56:57.573983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3177 13:56:57.580383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3178 13:56:57.589501 [CA 0] Center 37 (7~67) winsize 61
3179 13:56:57.592806 [CA 1] Center 37 (7~68) winsize 62
3180 13:56:57.596088 [CA 2] Center 34 (4~65) winsize 62
3181 13:56:57.599366 [CA 3] Center 33 (3~64) winsize 62
3182 13:56:57.602800 [CA 4] Center 34 (4~64) winsize 61
3183 13:56:57.605892 [CA 5] Center 32 (2~63) winsize 62
3184 13:56:57.605999
3185 13:56:57.609216 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3186 13:56:57.609339
3187 13:56:57.612823 [CATrainingPosCal] consider 2 rank data
3188 13:56:57.616084 u2DelayCellTimex100 = 270/100 ps
3189 13:56:57.619290 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3190 13:56:57.622813 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3191 13:56:57.629429 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3192 13:56:57.632803 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3193 13:56:57.635963 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3194 13:56:57.639553 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3195 13:56:57.639663
3196 13:56:57.642634 CA PerBit enable=1, Macro0, CA PI delay=33
3197 13:56:57.642745
3198 13:56:57.646073 [CBTSetCACLKResult] CA Dly = 33
3199 13:56:57.646184 CS Dly: 7 (0~40)
3200 13:56:57.646316
3201 13:56:57.649456 ----->DramcWriteLeveling(PI) begin...
3202 13:56:57.653174 ==
3203 13:56:57.653811 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 13:56:57.659622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 13:56:57.660122 ==
3206 13:56:57.662954 Write leveling (Byte 0): 24 => 24
3207 13:56:57.665926 Write leveling (Byte 1): 27 => 27
3208 13:56:57.666038 DramcWriteLeveling(PI) end<-----
3209 13:56:57.669257
3210 13:56:57.669338 ==
3211 13:56:57.672534 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 13:56:57.675927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 13:56:57.676003 ==
3214 13:56:57.679453 [Gating] SW mode calibration
3215 13:56:57.686046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3216 13:56:57.689154 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3217 13:56:57.696356 0 15 0 | B1->B0 | 2c2b 2525 | 1 0 | (0 0) (0 0)
3218 13:56:57.699987 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 13:56:57.703309 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3220 13:56:57.709883 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3221 13:56:57.712982 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3222 13:56:57.716467 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3223 13:56:57.723258 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3224 13:56:57.726648 0 15 28 | B1->B0 | 3030 3232 | 0 1 | (0 1) (1 0)
3225 13:56:57.729766 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 13:56:57.736255 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3227 13:56:57.739652 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3228 13:56:57.743150 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3229 13:56:57.749606 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3230 13:56:57.752938 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3231 13:56:57.756263 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3232 13:56:57.762878 1 0 28 | B1->B0 | 4141 4141 | 0 0 | (0 0) (0 0)
3233 13:56:57.766426 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3234 13:56:57.769332 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 13:56:57.772974 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 13:56:57.779638 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 13:56:57.783005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 13:56:57.786319 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 13:56:57.792800 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 13:56:57.796024 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3241 13:56:57.799171 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3242 13:56:57.805953 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 13:56:57.809192 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 13:56:57.812650 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 13:56:57.819376 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 13:56:57.822781 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 13:56:57.825873 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 13:56:57.832467 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 13:56:57.835954 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 13:56:57.839157 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 13:56:57.845743 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 13:56:57.849166 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 13:56:57.852307 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 13:56:57.858906 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 13:56:57.862294 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 13:56:57.865680 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3257 13:56:57.872334 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3258 13:56:57.872426 Total UI for P1: 0, mck2ui 16
3259 13:56:57.878902 best dqsien dly found for B0: ( 1, 3, 28)
3260 13:56:57.878978 Total UI for P1: 0, mck2ui 16
3261 13:56:57.882795 best dqsien dly found for B1: ( 1, 3, 28)
3262 13:56:57.889403 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3263 13:56:57.892723 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3264 13:56:57.893314
3265 13:56:57.895966 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3266 13:56:57.899045 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3267 13:56:57.902439 [Gating] SW calibration Done
3268 13:56:57.902977 ==
3269 13:56:57.905516 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 13:56:57.908976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 13:56:57.909551 ==
3272 13:56:57.912454 RX Vref Scan: 0
3273 13:56:57.913134
3274 13:56:57.913669 RX Vref 0 -> 0, step: 1
3275 13:56:57.914240
3276 13:56:57.915358 RX Delay -40 -> 252, step: 8
3277 13:56:57.919036 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3278 13:56:57.925561 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3279 13:56:57.928732 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3280 13:56:57.932048 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3281 13:56:57.935530 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3282 13:56:57.939191 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3283 13:56:57.945548 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3284 13:56:57.948734 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3285 13:56:57.952167 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3286 13:56:57.955696 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3287 13:56:57.958965 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3288 13:56:57.962132 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3289 13:56:57.969103 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3290 13:56:57.972085 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3291 13:56:57.975648 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3292 13:56:57.979064 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3293 13:56:57.979486 ==
3294 13:56:57.982360 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 13:56:57.988471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 13:56:57.988553 ==
3297 13:56:57.988618 DQS Delay:
3298 13:56:57.992192 DQS0 = 0, DQS1 = 0
3299 13:56:57.992274 DQM Delay:
3300 13:56:57.992339 DQM0 = 112, DQM1 = 106
3301 13:56:57.995597 DQ Delay:
3302 13:56:57.999095 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =111
3303 13:56:58.001928 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3304 13:56:58.005677 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3305 13:56:58.009209 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3306 13:56:58.009370
3307 13:56:58.009446
3308 13:56:58.009537 ==
3309 13:56:58.012259 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 13:56:58.015298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 13:56:58.015443 ==
3312 13:56:58.018679
3313 13:56:58.018824
3314 13:56:58.018907 TX Vref Scan disable
3315 13:56:58.021859 == TX Byte 0 ==
3316 13:56:58.025277 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3317 13:56:58.028804 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3318 13:56:58.032121 == TX Byte 1 ==
3319 13:56:58.035639 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3320 13:56:58.038956 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3321 13:56:58.039219 ==
3322 13:56:58.041829 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 13:56:58.048593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 13:56:58.048702 ==
3325 13:56:58.058939 TX Vref=22, minBit 9, minWin=23, winSum=402
3326 13:56:58.062359 TX Vref=24, minBit 10, minWin=24, winSum=408
3327 13:56:58.065556 TX Vref=26, minBit 8, minWin=25, winSum=417
3328 13:56:58.069044 TX Vref=28, minBit 9, minWin=25, winSum=422
3329 13:56:58.072281 TX Vref=30, minBit 9, minWin=24, winSum=417
3330 13:56:58.078952 TX Vref=32, minBit 9, minWin=25, winSum=419
3331 13:56:58.082672 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
3332 13:56:58.082754
3333 13:56:58.085615 Final TX Range 1 Vref 28
3334 13:56:58.085697
3335 13:56:58.085761 ==
3336 13:56:58.089202 Dram Type= 6, Freq= 0, CH_1, rank 0
3337 13:56:58.092592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3338 13:56:58.092779 ==
3339 13:56:58.095998
3340 13:56:58.096169
3341 13:56:58.096256 TX Vref Scan disable
3342 13:56:58.099531 == TX Byte 0 ==
3343 13:56:58.102665 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3344 13:56:58.105623 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3345 13:56:58.109247 == TX Byte 1 ==
3346 13:56:58.112567 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3347 13:56:58.115701 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3348 13:56:58.115835
3349 13:56:58.118854 [DATLAT]
3350 13:56:58.118988 Freq=1200, CH1 RK0
3351 13:56:58.119096
3352 13:56:58.122509 DATLAT Default: 0xd
3353 13:56:58.122644 0, 0xFFFF, sum = 0
3354 13:56:58.125620 1, 0xFFFF, sum = 0
3355 13:56:58.125756 2, 0xFFFF, sum = 0
3356 13:56:58.128891 3, 0xFFFF, sum = 0
3357 13:56:58.129027 4, 0xFFFF, sum = 0
3358 13:56:58.132371 5, 0xFFFF, sum = 0
3359 13:56:58.132506 6, 0xFFFF, sum = 0
3360 13:56:58.135817 7, 0xFFFF, sum = 0
3361 13:56:58.135952 8, 0xFFFF, sum = 0
3362 13:56:58.139322 9, 0xFFFF, sum = 0
3363 13:56:58.142383 10, 0xFFFF, sum = 0
3364 13:56:58.142518 11, 0xFFFF, sum = 0
3365 13:56:58.145680 12, 0x0, sum = 1
3366 13:56:58.145813 13, 0x0, sum = 2
3367 13:56:58.145920 14, 0x0, sum = 3
3368 13:56:58.149341 15, 0x0, sum = 4
3369 13:56:58.149488 best_step = 13
3370 13:56:58.149601
3371 13:56:58.152364 ==
3372 13:56:58.152495 Dram Type= 6, Freq= 0, CH_1, rank 0
3373 13:56:58.159027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3374 13:56:58.159177 ==
3375 13:56:58.159296 RX Vref Scan: 1
3376 13:56:58.159406
3377 13:56:58.162158 Set Vref Range= 32 -> 127
3378 13:56:58.162305
3379 13:56:58.165749 RX Vref 32 -> 127, step: 1
3380 13:56:58.165918
3381 13:56:58.168965 RX Delay -21 -> 252, step: 4
3382 13:56:58.169160
3383 13:56:58.172644 Set Vref, RX VrefLevel [Byte0]: 32
3384 13:56:58.176146 [Byte1]: 32
3385 13:56:58.176475
3386 13:56:58.179273 Set Vref, RX VrefLevel [Byte0]: 33
3387 13:56:58.182683 [Byte1]: 33
3388 13:56:58.183078
3389 13:56:58.186099 Set Vref, RX VrefLevel [Byte0]: 34
3390 13:56:58.189508 [Byte1]: 34
3391 13:56:58.193511
3392 13:56:58.193923 Set Vref, RX VrefLevel [Byte0]: 35
3393 13:56:58.197073 [Byte1]: 35
3394 13:56:58.201712
3395 13:56:58.202121 Set Vref, RX VrefLevel [Byte0]: 36
3396 13:56:58.204888 [Byte1]: 36
3397 13:56:58.209546
3398 13:56:58.209978 Set Vref, RX VrefLevel [Byte0]: 37
3399 13:56:58.212864 [Byte1]: 37
3400 13:56:58.217429
3401 13:56:58.218021 Set Vref, RX VrefLevel [Byte0]: 38
3402 13:56:58.221012 [Byte1]: 38
3403 13:56:58.225280
3404 13:56:58.225763 Set Vref, RX VrefLevel [Byte0]: 39
3405 13:56:58.228436 [Byte1]: 39
3406 13:56:58.233942
3407 13:56:58.234472 Set Vref, RX VrefLevel [Byte0]: 40
3408 13:56:58.236835 [Byte1]: 40
3409 13:56:58.241294
3410 13:56:58.241870 Set Vref, RX VrefLevel [Byte0]: 41
3411 13:56:58.244755 [Byte1]: 41
3412 13:56:58.249468
3413 13:56:58.250049 Set Vref, RX VrefLevel [Byte0]: 42
3414 13:56:58.252702 [Byte1]: 42
3415 13:56:58.257418
3416 13:56:58.258032 Set Vref, RX VrefLevel [Byte0]: 43
3417 13:56:58.260511 [Byte1]: 43
3418 13:56:58.265348
3419 13:56:58.265957 Set Vref, RX VrefLevel [Byte0]: 44
3420 13:56:58.268596 [Byte1]: 44
3421 13:56:58.273239
3422 13:56:58.273856 Set Vref, RX VrefLevel [Byte0]: 45
3423 13:56:58.276189 [Byte1]: 45
3424 13:56:58.280643
3425 13:56:58.281108 Set Vref, RX VrefLevel [Byte0]: 46
3426 13:56:58.284226 [Byte1]: 46
3427 13:56:58.288861
3428 13:56:58.289271 Set Vref, RX VrefLevel [Byte0]: 47
3429 13:56:58.292065 [Byte1]: 47
3430 13:56:58.296611
3431 13:56:58.297021 Set Vref, RX VrefLevel [Byte0]: 48
3432 13:56:58.299913 [Byte1]: 48
3433 13:56:58.304411
3434 13:56:58.304890 Set Vref, RX VrefLevel [Byte0]: 49
3435 13:56:58.307806 [Byte1]: 49
3436 13:56:58.312166
3437 13:56:58.312386 Set Vref, RX VrefLevel [Byte0]: 50
3438 13:56:58.315384 [Byte1]: 50
3439 13:56:58.319960
3440 13:56:58.320189 Set Vref, RX VrefLevel [Byte0]: 51
3441 13:56:58.323440 [Byte1]: 51
3442 13:56:58.327887
3443 13:56:58.328043 Set Vref, RX VrefLevel [Byte0]: 52
3444 13:56:58.331336 [Byte1]: 52
3445 13:56:58.335942
3446 13:56:58.336047 Set Vref, RX VrefLevel [Byte0]: 53
3447 13:56:58.339067 [Byte1]: 53
3448 13:56:58.343952
3449 13:56:58.344032 Set Vref, RX VrefLevel [Byte0]: 54
3450 13:56:58.347159 [Byte1]: 54
3451 13:56:58.351544
3452 13:56:58.351628 Set Vref, RX VrefLevel [Byte0]: 55
3453 13:56:58.355364 [Byte1]: 55
3454 13:56:58.359575
3455 13:56:58.359656 Set Vref, RX VrefLevel [Byte0]: 56
3456 13:56:58.363016 [Byte1]: 56
3457 13:56:58.367608
3458 13:56:58.367693 Set Vref, RX VrefLevel [Byte0]: 57
3459 13:56:58.370617 [Byte1]: 57
3460 13:56:58.375713
3461 13:56:58.375797 Set Vref, RX VrefLevel [Byte0]: 58
3462 13:56:58.378621 [Byte1]: 58
3463 13:56:58.383497
3464 13:56:58.383580 Set Vref, RX VrefLevel [Byte0]: 59
3465 13:56:58.386513 [Byte1]: 59
3466 13:56:58.391625
3467 13:56:58.391936 Set Vref, RX VrefLevel [Byte0]: 60
3468 13:56:58.395076 [Byte1]: 60
3469 13:56:58.399290
3470 13:56:58.399612 Set Vref, RX VrefLevel [Byte0]: 61
3471 13:56:58.402572 [Byte1]: 61
3472 13:56:58.407586
3473 13:56:58.408037 Set Vref, RX VrefLevel [Byte0]: 62
3474 13:56:58.410651 [Byte1]: 62
3475 13:56:58.415382
3476 13:56:58.415877 Set Vref, RX VrefLevel [Byte0]: 63
3477 13:56:58.418621 [Byte1]: 63
3478 13:56:58.423260
3479 13:56:58.423776 Set Vref, RX VrefLevel [Byte0]: 64
3480 13:56:58.429459 [Byte1]: 64
3481 13:56:58.429910
3482 13:56:58.432921 Set Vref, RX VrefLevel [Byte0]: 65
3483 13:56:58.436349 [Byte1]: 65
3484 13:56:58.436859
3485 13:56:58.439639 Set Vref, RX VrefLevel [Byte0]: 66
3486 13:56:58.443176 [Byte1]: 66
3487 13:56:58.446930
3488 13:56:58.447248 Set Vref, RX VrefLevel [Byte0]: 67
3489 13:56:58.450339 [Byte1]: 67
3490 13:56:58.454781
3491 13:56:58.455098 Set Vref, RX VrefLevel [Byte0]: 68
3492 13:56:58.458192 [Byte1]: 68
3493 13:56:58.462761
3494 13:56:58.463079 Final RX Vref Byte 0 = 56 to rank0
3495 13:56:58.466304 Final RX Vref Byte 1 = 55 to rank0
3496 13:56:58.469465 Final RX Vref Byte 0 = 56 to rank1
3497 13:56:58.472691 Final RX Vref Byte 1 = 55 to rank1==
3498 13:56:58.476239 Dram Type= 6, Freq= 0, CH_1, rank 0
3499 13:56:58.482723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 13:56:58.483047 ==
3501 13:56:58.483306 DQS Delay:
3502 13:56:58.483544 DQS0 = 0, DQS1 = 0
3503 13:56:58.486224 DQM Delay:
3504 13:56:58.486548 DQM0 = 114, DQM1 = 107
3505 13:56:58.489189 DQ Delay:
3506 13:56:58.492800 DQ0 =118, DQ1 =110, DQ2 =104, DQ3 =112
3507 13:56:58.496042 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3508 13:56:58.499323 DQ8 =94, DQ9 =98, DQ10 =108, DQ11 =100
3509 13:56:58.502724 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3510 13:56:58.503068
3511 13:56:58.503346
3512 13:56:58.509337 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 415 ps
3513 13:56:58.512480 CH1 RK0: MR19=303, MR18=F2F8
3514 13:56:58.519286 CH1_RK0: MR19=0x303, MR18=0xF2F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3515 13:56:58.519688
3516 13:56:58.522682 ----->DramcWriteLeveling(PI) begin...
3517 13:56:58.523033 ==
3518 13:56:58.525788 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 13:56:58.529037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 13:56:58.532308 ==
3521 13:56:58.532625 Write leveling (Byte 0): 24 => 24
3522 13:56:58.535692 Write leveling (Byte 1): 28 => 28
3523 13:56:58.539058 DramcWriteLeveling(PI) end<-----
3524 13:56:58.539268
3525 13:56:58.539444 ==
3526 13:56:58.542379 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 13:56:58.548770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 13:56:58.548928 ==
3529 13:56:58.552288 [Gating] SW mode calibration
3530 13:56:58.558885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3531 13:56:58.562139 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3532 13:56:58.568730 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3533 13:56:58.572229 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3534 13:56:58.575689 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3535 13:56:58.582316 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3536 13:56:58.585590 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3537 13:56:58.588992 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3538 13:56:58.592293 0 15 24 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
3539 13:56:58.598742 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3540 13:56:58.602063 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 13:56:58.605826 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3542 13:56:58.611989 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3543 13:56:58.615320 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 13:56:58.618831 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3545 13:56:58.625426 1 0 20 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
3546 13:56:58.628764 1 0 24 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
3547 13:56:58.631986 1 0 28 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
3548 13:56:58.638479 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 13:56:58.642065 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 13:56:58.645131 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 13:56:58.651903 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 13:56:58.655382 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 13:56:58.658511 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 13:56:58.665191 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3555 13:56:58.668529 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3556 13:56:58.672111 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 13:56:58.678442 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 13:56:58.681726 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 13:56:58.685090 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 13:56:58.691858 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 13:56:58.694896 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 13:56:58.698324 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 13:56:58.704925 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 13:56:58.708283 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 13:56:58.711668 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 13:56:58.718231 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 13:56:58.721543 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 13:56:58.724598 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 13:56:58.731192 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 13:56:58.734439 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3571 13:56:58.737990 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3572 13:56:58.741249 Total UI for P1: 0, mck2ui 16
3573 13:56:58.744599 best dqsien dly found for B0: ( 1, 3, 24)
3574 13:56:58.748041 Total UI for P1: 0, mck2ui 16
3575 13:56:58.751004 best dqsien dly found for B1: ( 1, 3, 24)
3576 13:56:58.754315 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3577 13:56:58.757807 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3578 13:56:58.757930
3579 13:56:58.761058 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3580 13:56:58.767911 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3581 13:56:58.767996 [Gating] SW calibration Done
3582 13:56:58.768062 ==
3583 13:56:58.771222 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 13:56:58.777973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 13:56:58.778055 ==
3586 13:56:58.778118 RX Vref Scan: 0
3587 13:56:58.778178
3588 13:56:58.781010 RX Vref 0 -> 0, step: 1
3589 13:56:58.781090
3590 13:56:58.784550 RX Delay -40 -> 252, step: 8
3591 13:56:58.787830 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3592 13:56:58.791295 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3593 13:56:58.794356 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3594 13:56:58.801319 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3595 13:56:58.804287 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3596 13:56:58.807717 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3597 13:56:58.811031 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3598 13:56:58.814168 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3599 13:56:58.817746 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3600 13:56:58.824560 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3601 13:56:58.827548 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3602 13:56:58.831008 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3603 13:56:58.834128 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3604 13:56:58.840932 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3605 13:56:58.844047 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3606 13:56:58.847634 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3607 13:56:58.847716 ==
3608 13:56:58.850817 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 13:56:58.853911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 13:56:58.854018 ==
3611 13:56:58.857370 DQS Delay:
3612 13:56:58.857468 DQS0 = 0, DQS1 = 0
3613 13:56:58.860865 DQM Delay:
3614 13:56:58.860947 DQM0 = 110, DQM1 = 109
3615 13:56:58.861013 DQ Delay:
3616 13:56:58.867403 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3617 13:56:58.870679 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3618 13:56:58.873852 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3619 13:56:58.877301 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3620 13:56:58.877383
3621 13:56:58.877448
3622 13:56:58.877550 ==
3623 13:56:58.880719 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 13:56:58.884299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 13:56:58.884457 ==
3626 13:56:58.884534
3627 13:56:58.884601
3628 13:56:58.887116 TX Vref Scan disable
3629 13:56:58.890469 == TX Byte 0 ==
3630 13:56:58.893928 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3631 13:56:58.897051 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3632 13:56:58.900530 == TX Byte 1 ==
3633 13:56:58.903654 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3634 13:56:58.907096 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3635 13:56:58.907177 ==
3636 13:56:58.910386 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 13:56:58.913808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 13:56:58.916794 ==
3639 13:56:58.927463 TX Vref=22, minBit 9, minWin=25, winSum=422
3640 13:56:58.930864 TX Vref=24, minBit 0, minWin=26, winSum=427
3641 13:56:58.934011 TX Vref=26, minBit 3, minWin=26, winSum=434
3642 13:56:58.937341 TX Vref=28, minBit 8, minWin=26, winSum=437
3643 13:56:58.940891 TX Vref=30, minBit 8, minWin=26, winSum=434
3644 13:56:58.947353 TX Vref=32, minBit 0, minWin=26, winSum=430
3645 13:56:58.950912 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 28
3646 13:56:58.951328
3647 13:56:58.953986 Final TX Range 1 Vref 28
3648 13:56:58.954402
3649 13:56:58.954729 ==
3650 13:56:58.957527 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 13:56:58.960951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 13:56:58.963937 ==
3653 13:56:58.964349
3654 13:56:58.964675
3655 13:56:58.964977 TX Vref Scan disable
3656 13:56:58.967628 == TX Byte 0 ==
3657 13:56:58.970931 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3658 13:56:58.977235 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3659 13:56:58.977958 == TX Byte 1 ==
3660 13:56:58.980695 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3661 13:56:58.987071 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3662 13:56:58.987604
3663 13:56:58.987945 [DATLAT]
3664 13:56:58.988256 Freq=1200, CH1 RK1
3665 13:56:58.988553
3666 13:56:58.990740 DATLAT Default: 0xd
3667 13:56:58.991155 0, 0xFFFF, sum = 0
3668 13:56:58.993600 1, 0xFFFF, sum = 0
3669 13:56:58.997161 2, 0xFFFF, sum = 0
3670 13:56:58.997642 3, 0xFFFF, sum = 0
3671 13:56:59.000375 4, 0xFFFF, sum = 0
3672 13:56:59.000794 5, 0xFFFF, sum = 0
3673 13:56:59.003641 6, 0xFFFF, sum = 0
3674 13:56:59.004064 7, 0xFFFF, sum = 0
3675 13:56:59.006772 8, 0xFFFF, sum = 0
3676 13:56:59.007193 9, 0xFFFF, sum = 0
3677 13:56:59.010313 10, 0xFFFF, sum = 0
3678 13:56:59.010735 11, 0xFFFF, sum = 0
3679 13:56:59.013511 12, 0x0, sum = 1
3680 13:56:59.014107 13, 0x0, sum = 2
3681 13:56:59.016828 14, 0x0, sum = 3
3682 13:56:59.017404 15, 0x0, sum = 4
3683 13:56:59.020244 best_step = 13
3684 13:56:59.020668
3685 13:56:59.020930 ==
3686 13:56:59.023578 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 13:56:59.026597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 13:56:59.026815 ==
3689 13:56:59.026997 RX Vref Scan: 0
3690 13:56:59.027157
3691 13:56:59.030041 RX Vref 0 -> 0, step: 1
3692 13:56:59.030219
3693 13:56:59.033154 RX Delay -21 -> 252, step: 4
3694 13:56:59.036659 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3695 13:56:59.043210 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3696 13:56:59.046785 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3697 13:56:59.050000 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3698 13:56:59.052937 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3699 13:56:59.059660 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3700 13:56:59.062753 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3701 13:56:59.066295 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3702 13:56:59.069632 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3703 13:56:59.072805 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3704 13:56:59.076661 iDelay=195, Bit 10, Center 114 (47 ~ 182) 136
3705 13:56:59.083265 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3706 13:56:59.086201 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3707 13:56:59.089404 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3708 13:56:59.093058 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3709 13:56:59.099513 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3710 13:56:59.099675 ==
3711 13:56:59.102878 Dram Type= 6, Freq= 0, CH_1, rank 1
3712 13:56:59.106113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3713 13:56:59.106281 ==
3714 13:56:59.106367 DQS Delay:
3715 13:56:59.109414 DQS0 = 0, DQS1 = 0
3716 13:56:59.109588 DQM Delay:
3717 13:56:59.112925 DQM0 = 111, DQM1 = 110
3718 13:56:59.113108 DQ Delay:
3719 13:56:59.116273 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3720 13:56:59.119467 DQ4 =110, DQ5 =120, DQ6 =120, DQ7 =110
3721 13:56:59.122598 DQ8 =96, DQ9 =102, DQ10 =114, DQ11 =106
3722 13:56:59.125904 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =118
3723 13:56:59.126042
3724 13:56:59.129201
3725 13:56:59.136027 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3726 13:56:59.138989 CH1 RK1: MR19=304, MR18=FA0A
3727 13:56:59.145497 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3728 13:56:59.149250 [RxdqsGatingPostProcess] freq 1200
3729 13:56:59.152120 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3730 13:56:59.155437 best DQS0 dly(2T, 0.5T) = (0, 11)
3731 13:56:59.158688 best DQS1 dly(2T, 0.5T) = (0, 11)
3732 13:56:59.162145 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3733 13:56:59.165314 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3734 13:56:59.168920 best DQS0 dly(2T, 0.5T) = (0, 11)
3735 13:56:59.171974 best DQS1 dly(2T, 0.5T) = (0, 11)
3736 13:56:59.175589 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3737 13:56:59.178534 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3738 13:56:59.181986 Pre-setting of DQS Precalculation
3739 13:56:59.185155 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3740 13:56:59.195206 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3741 13:56:59.201729 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3742 13:56:59.201901
3743 13:56:59.202038
3744 13:56:59.205211 [Calibration Summary] 2400 Mbps
3745 13:56:59.205383 CH 0, Rank 0
3746 13:56:59.208173 SW Impedance : PASS
3747 13:56:59.208345 DUTY Scan : NO K
3748 13:56:59.211667 ZQ Calibration : PASS
3749 13:56:59.215037 Jitter Meter : NO K
3750 13:56:59.215218 CBT Training : PASS
3751 13:56:59.218145 Write leveling : PASS
3752 13:56:59.221588 RX DQS gating : PASS
3753 13:56:59.221760 RX DQ/DQS(RDDQC) : PASS
3754 13:56:59.225085 TX DQ/DQS : PASS
3755 13:56:59.228281 RX DATLAT : PASS
3756 13:56:59.228454 RX DQ/DQS(Engine): PASS
3757 13:56:59.231609 TX OE : NO K
3758 13:56:59.231782 All Pass.
3759 13:56:59.231922
3760 13:56:59.235088 CH 0, Rank 1
3761 13:56:59.235261 SW Impedance : PASS
3762 13:56:59.238121 DUTY Scan : NO K
3763 13:56:59.238294 ZQ Calibration : PASS
3764 13:56:59.241522 Jitter Meter : NO K
3765 13:56:59.244818 CBT Training : PASS
3766 13:56:59.244991 Write leveling : PASS
3767 13:56:59.248208 RX DQS gating : PASS
3768 13:56:59.251085 RX DQ/DQS(RDDQC) : PASS
3769 13:56:59.251257 TX DQ/DQS : PASS
3770 13:56:59.254859 RX DATLAT : PASS
3771 13:56:59.257869 RX DQ/DQS(Engine): PASS
3772 13:56:59.258041 TX OE : NO K
3773 13:56:59.261459 All Pass.
3774 13:56:59.261647
3775 13:56:59.261787 CH 1, Rank 0
3776 13:56:59.264999 SW Impedance : PASS
3777 13:56:59.265198 DUTY Scan : NO K
3778 13:56:59.268096 ZQ Calibration : PASS
3779 13:56:59.271455 Jitter Meter : NO K
3780 13:56:59.271695 CBT Training : PASS
3781 13:56:59.275162 Write leveling : PASS
3782 13:56:59.278251 RX DQS gating : PASS
3783 13:56:59.278641 RX DQ/DQS(RDDQC) : PASS
3784 13:56:59.281553 TX DQ/DQS : PASS
3785 13:56:59.284864 RX DATLAT : PASS
3786 13:56:59.285393 RX DQ/DQS(Engine): PASS
3787 13:56:59.288423 TX OE : NO K
3788 13:56:59.288967 All Pass.
3789 13:56:59.289423
3790 13:56:59.291265 CH 1, Rank 1
3791 13:56:59.291700 SW Impedance : PASS
3792 13:56:59.294786 DUTY Scan : NO K
3793 13:56:59.298014 ZQ Calibration : PASS
3794 13:56:59.298613 Jitter Meter : NO K
3795 13:56:59.301185 CBT Training : PASS
3796 13:56:59.304883 Write leveling : PASS
3797 13:56:59.305394 RX DQS gating : PASS
3798 13:56:59.307731 RX DQ/DQS(RDDQC) : PASS
3799 13:56:59.308150 TX DQ/DQS : PASS
3800 13:56:59.311397 RX DATLAT : PASS
3801 13:56:59.314534 RX DQ/DQS(Engine): PASS
3802 13:56:59.314955 TX OE : NO K
3803 13:56:59.317623 All Pass.
3804 13:56:59.318045
3805 13:56:59.318383 DramC Write-DBI off
3806 13:56:59.321328 PER_BANK_REFRESH: Hybrid Mode
3807 13:56:59.324765 TX_TRACKING: ON
3808 13:56:59.330842 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3809 13:56:59.334266 [FAST_K] Save calibration result to emmc
3810 13:56:59.337310 dramc_set_vcore_voltage set vcore to 650000
3811 13:56:59.340777 Read voltage for 600, 5
3812 13:56:59.341196 Vio18 = 0
3813 13:56:59.343925 Vcore = 650000
3814 13:56:59.344342 Vdram = 0
3815 13:56:59.344674 Vddq = 0
3816 13:56:59.347399 Vmddr = 0
3817 13:56:59.350655 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3818 13:56:59.357103 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3819 13:56:59.360650 MEM_TYPE=3, freq_sel=19
3820 13:56:59.361086 sv_algorithm_assistance_LP4_1600
3821 13:56:59.367198 ============ PULL DRAM RESETB DOWN ============
3822 13:56:59.370375 ========== PULL DRAM RESETB DOWN end =========
3823 13:56:59.373743 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3824 13:56:59.377260 ===================================
3825 13:56:59.380316 LPDDR4 DRAM CONFIGURATION
3826 13:56:59.383722 ===================================
3827 13:56:59.387083 EX_ROW_EN[0] = 0x0
3828 13:56:59.387501 EX_ROW_EN[1] = 0x0
3829 13:56:59.390308 LP4Y_EN = 0x0
3830 13:56:59.390727 WORK_FSP = 0x0
3831 13:56:59.393923 WL = 0x2
3832 13:56:59.394342 RL = 0x2
3833 13:56:59.396551 BL = 0x2
3834 13:56:59.396633 RPST = 0x0
3835 13:56:59.399809 RD_PRE = 0x0
3836 13:56:59.399890 WR_PRE = 0x1
3837 13:56:59.403167 WR_PST = 0x0
3838 13:56:59.403248 DBI_WR = 0x0
3839 13:56:59.406457 DBI_RD = 0x0
3840 13:56:59.406537 OTF = 0x1
3841 13:56:59.409866 ===================================
3842 13:56:59.413345 ===================================
3843 13:56:59.416419 ANA top config
3844 13:56:59.419585 ===================================
3845 13:56:59.422815 DLL_ASYNC_EN = 0
3846 13:56:59.422897 ALL_SLAVE_EN = 1
3847 13:56:59.426000 NEW_RANK_MODE = 1
3848 13:56:59.429253 DLL_IDLE_MODE = 1
3849 13:56:59.432891 LP45_APHY_COMB_EN = 1
3850 13:56:59.436095 TX_ODT_DIS = 1
3851 13:56:59.436203 NEW_8X_MODE = 1
3852 13:56:59.439616 ===================================
3853 13:56:59.442979 ===================================
3854 13:56:59.446436 data_rate = 1200
3855 13:56:59.449319 CKR = 1
3856 13:56:59.452803 DQ_P2S_RATIO = 8
3857 13:56:59.456287 ===================================
3858 13:56:59.459478 CA_P2S_RATIO = 8
3859 13:56:59.462930 DQ_CA_OPEN = 0
3860 13:56:59.463038 DQ_SEMI_OPEN = 0
3861 13:56:59.466070 CA_SEMI_OPEN = 0
3862 13:56:59.469861 CA_FULL_RATE = 0
3863 13:56:59.472778 DQ_CKDIV4_EN = 1
3864 13:56:59.476365 CA_CKDIV4_EN = 1
3865 13:56:59.479540 CA_PREDIV_EN = 0
3866 13:56:59.479633 PH8_DLY = 0
3867 13:56:59.482776 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3868 13:56:59.486068 DQ_AAMCK_DIV = 4
3869 13:56:59.489381 CA_AAMCK_DIV = 4
3870 13:56:59.492940 CA_ADMCK_DIV = 4
3871 13:56:59.495880 DQ_TRACK_CA_EN = 0
3872 13:56:59.496086 CA_PICK = 600
3873 13:56:59.499604 CA_MCKIO = 600
3874 13:56:59.502790 MCKIO_SEMI = 0
3875 13:56:59.506035 PLL_FREQ = 2288
3876 13:56:59.509067 DQ_UI_PI_RATIO = 32
3877 13:56:59.512509 CA_UI_PI_RATIO = 0
3878 13:56:59.515994 ===================================
3879 13:56:59.519202 ===================================
3880 13:56:59.519290 memory_type:LPDDR4
3881 13:56:59.522592 GP_NUM : 10
3882 13:56:59.525754 SRAM_EN : 1
3883 13:56:59.525848 MD32_EN : 0
3884 13:56:59.529628 ===================================
3885 13:56:59.532554 [ANA_INIT] >>>>>>>>>>>>>>
3886 13:56:59.535773 <<<<<< [CONFIGURE PHASE]: ANA_TX
3887 13:56:59.539040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3888 13:56:59.542347 ===================================
3889 13:56:59.545502 data_rate = 1200,PCW = 0X5800
3890 13:56:59.549073 ===================================
3891 13:56:59.552425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3892 13:56:59.555719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3893 13:56:59.562297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3894 13:56:59.566004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3895 13:56:59.572720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3896 13:56:59.576051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3897 13:56:59.576542 [ANA_INIT] flow start
3898 13:56:59.579711 [ANA_INIT] PLL >>>>>>>>
3899 13:56:59.582305 [ANA_INIT] PLL <<<<<<<<
3900 13:56:59.582728 [ANA_INIT] MIDPI >>>>>>>>
3901 13:56:59.586078 [ANA_INIT] MIDPI <<<<<<<<
3902 13:56:59.589344 [ANA_INIT] DLL >>>>>>>>
3903 13:56:59.589921 [ANA_INIT] flow end
3904 13:56:59.592348 ============ LP4 DIFF to SE enter ============
3905 13:56:59.599419 ============ LP4 DIFF to SE exit ============
3906 13:56:59.600014 [ANA_INIT] <<<<<<<<<<<<<
3907 13:56:59.602337 [Flow] Enable top DCM control >>>>>
3908 13:56:59.605762 [Flow] Enable top DCM control <<<<<
3909 13:56:59.608990 Enable DLL master slave shuffle
3910 13:56:59.615824 ==============================================================
3911 13:56:59.616371 Gating Mode config
3912 13:56:59.622315 ==============================================================
3913 13:56:59.625559 Config description:
3914 13:56:59.635657 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3915 13:56:59.642305 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3916 13:56:59.645877 SELPH_MODE 0: By rank 1: By Phase
3917 13:56:59.652132 ==============================================================
3918 13:56:59.655585 GAT_TRACK_EN = 1
3919 13:56:59.658799 RX_GATING_MODE = 2
3920 13:56:59.661746 RX_GATING_TRACK_MODE = 2
3921 13:56:59.662165 SELPH_MODE = 1
3922 13:56:59.665221 PICG_EARLY_EN = 1
3923 13:56:59.669158 VALID_LAT_VALUE = 1
3924 13:56:59.675427 ==============================================================
3925 13:56:59.678971 Enter into Gating configuration >>>>
3926 13:56:59.682157 Exit from Gating configuration <<<<
3927 13:56:59.685568 Enter into DVFS_PRE_config >>>>>
3928 13:56:59.695178 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3929 13:56:59.698137 Exit from DVFS_PRE_config <<<<<
3930 13:56:59.701655 Enter into PICG configuration >>>>
3931 13:56:59.705101 Exit from PICG configuration <<<<
3932 13:56:59.708385 [RX_INPUT] configuration >>>>>
3933 13:56:59.711535 [RX_INPUT] configuration <<<<<
3934 13:56:59.714732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3935 13:56:59.721712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3936 13:56:59.728047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3937 13:56:59.735040 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3938 13:56:59.741711 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3939 13:56:59.744751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3940 13:56:59.751497 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3941 13:56:59.754802 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3942 13:56:59.757990 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3943 13:56:59.761187 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3944 13:56:59.768065 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3945 13:56:59.770855 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 13:56:59.774850 ===================================
3947 13:56:59.778025 LPDDR4 DRAM CONFIGURATION
3948 13:56:59.781189 ===================================
3949 13:56:59.781808 EX_ROW_EN[0] = 0x0
3950 13:56:59.784564 EX_ROW_EN[1] = 0x0
3951 13:56:59.785131 LP4Y_EN = 0x0
3952 13:56:59.787941 WORK_FSP = 0x0
3953 13:56:59.788504 WL = 0x2
3954 13:56:59.791093 RL = 0x2
3955 13:56:59.791659 BL = 0x2
3956 13:56:59.794302 RPST = 0x0
3957 13:56:59.794784 RD_PRE = 0x0
3958 13:56:59.798002 WR_PRE = 0x1
3959 13:56:59.800879 WR_PST = 0x0
3960 13:56:59.801431 DBI_WR = 0x0
3961 13:56:59.804343 DBI_RD = 0x0
3962 13:56:59.805189 OTF = 0x1
3963 13:56:59.807275 ===================================
3964 13:56:59.810710 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3965 13:56:59.817158 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3966 13:56:59.820756 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3967 13:56:59.823872 ===================================
3968 13:56:59.827026 LPDDR4 DRAM CONFIGURATION
3969 13:56:59.830545 ===================================
3970 13:56:59.830986 EX_ROW_EN[0] = 0x10
3971 13:56:59.834108 EX_ROW_EN[1] = 0x0
3972 13:56:59.834532 LP4Y_EN = 0x0
3973 13:56:59.837084 WORK_FSP = 0x0
3974 13:56:59.837675 WL = 0x2
3975 13:56:59.840835 RL = 0x2
3976 13:56:59.841252 BL = 0x2
3977 13:56:59.844210 RPST = 0x0
3978 13:56:59.844624 RD_PRE = 0x0
3979 13:56:59.847166 WR_PRE = 0x1
3980 13:56:59.847582 WR_PST = 0x0
3981 13:56:59.850747 DBI_WR = 0x0
3982 13:56:59.853784 DBI_RD = 0x0
3983 13:56:59.854203 OTF = 0x1
3984 13:56:59.857257 ===================================
3985 13:56:59.864055 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3986 13:56:59.867463 nWR fixed to 30
3987 13:56:59.870520 [ModeRegInit_LP4] CH0 RK0
3988 13:56:59.870938 [ModeRegInit_LP4] CH0 RK1
3989 13:56:59.874104 [ModeRegInit_LP4] CH1 RK0
3990 13:56:59.877731 [ModeRegInit_LP4] CH1 RK1
3991 13:56:59.878256 match AC timing 17
3992 13:56:59.884155 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3993 13:56:59.887430 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3994 13:56:59.890875 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3995 13:56:59.897537 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3996 13:56:59.900744 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3997 13:56:59.901264 ==
3998 13:56:59.903615 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 13:56:59.907230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 13:56:59.907757 ==
4001 13:56:59.913585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4002 13:56:59.920591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4003 13:56:59.923696 [CA 0] Center 37 (7~67) winsize 61
4004 13:56:59.927041 [CA 1] Center 37 (7~67) winsize 61
4005 13:56:59.930008 [CA 2] Center 35 (5~65) winsize 61
4006 13:56:59.933349 [CA 3] Center 35 (5~65) winsize 61
4007 13:56:59.936695 [CA 4] Center 34 (4~65) winsize 62
4008 13:56:59.940129 [CA 5] Center 34 (4~65) winsize 62
4009 13:56:59.940548
4010 13:56:59.943465 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4011 13:56:59.943887
4012 13:56:59.946530 [CATrainingPosCal] consider 1 rank data
4013 13:56:59.950095 u2DelayCellTimex100 = 270/100 ps
4014 13:56:59.953833 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4015 13:56:59.956887 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4016 13:56:59.960373 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4017 13:56:59.963151 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4018 13:56:59.970007 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4019 13:56:59.973630 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4020 13:56:59.974159
4021 13:56:59.976864 CA PerBit enable=1, Macro0, CA PI delay=34
4022 13:56:59.977388
4023 13:56:59.980044 [CBTSetCACLKResult] CA Dly = 34
4024 13:56:59.980578 CS Dly: 7 (0~38)
4025 13:56:59.980919 ==
4026 13:56:59.983123 Dram Type= 6, Freq= 0, CH_0, rank 1
4027 13:56:59.989995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 13:56:59.990511 ==
4029 13:56:59.992980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4030 13:56:59.999534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4031 13:57:00.002874 [CA 0] Center 37 (7~67) winsize 61
4032 13:57:00.006466 [CA 1] Center 37 (7~67) winsize 61
4033 13:57:00.011377 [CA 2] Center 35 (5~65) winsize 61
4034 13:57:00.012863 [CA 3] Center 34 (4~65) winsize 62
4035 13:57:00.016303 [CA 4] Center 34 (4~64) winsize 61
4036 13:57:00.019367 [CA 5] Center 33 (3~64) winsize 62
4037 13:57:00.019789
4038 13:57:00.022701 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4039 13:57:00.023122
4040 13:57:00.026275 [CATrainingPosCal] consider 2 rank data
4041 13:57:00.029245 u2DelayCellTimex100 = 270/100 ps
4042 13:57:00.032920 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4043 13:57:00.035881 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4044 13:57:00.039111 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4045 13:57:00.045888 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4046 13:57:00.048934 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4047 13:57:00.052389 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4048 13:57:00.052523
4049 13:57:00.055755 CA PerBit enable=1, Macro0, CA PI delay=34
4050 13:57:00.055869
4051 13:57:00.058948 [CBTSetCACLKResult] CA Dly = 34
4052 13:57:00.059063 CS Dly: 6 (0~37)
4053 13:57:00.059154
4054 13:57:00.062262 ----->DramcWriteLeveling(PI) begin...
4055 13:57:00.065392 ==
4056 13:57:00.068956 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 13:57:00.072362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 13:57:00.072446 ==
4059 13:57:00.075393 Write leveling (Byte 0): 34 => 34
4060 13:57:00.078865 Write leveling (Byte 1): 31 => 31
4061 13:57:00.082010 DramcWriteLeveling(PI) end<-----
4062 13:57:00.082092
4063 13:57:00.082158 ==
4064 13:57:00.085561 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 13:57:00.088675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 13:57:00.088760 ==
4067 13:57:00.092143 [Gating] SW mode calibration
4068 13:57:00.098878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4069 13:57:00.105357 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4070 13:57:00.108427 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4071 13:57:00.111996 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4072 13:57:00.118571 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4073 13:57:00.121704 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4074 13:57:00.125186 0 9 16 | B1->B0 | 3030 2b2b | 1 0 | (1 0) (0 0)
4075 13:57:00.131560 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 13:57:00.135166 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 13:57:00.138259 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 13:57:00.145028 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4079 13:57:00.147977 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 13:57:00.151393 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 13:57:00.154593 0 10 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
4082 13:57:00.161388 0 10 16 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (0 0)
4083 13:57:00.164680 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 13:57:00.167877 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 13:57:00.174933 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 13:57:00.178011 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 13:57:00.181094 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 13:57:00.187994 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 13:57:00.191058 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 13:57:00.194362 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4091 13:57:00.201039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 13:57:00.204329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 13:57:00.207913 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 13:57:00.214451 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 13:57:00.217699 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 13:57:00.221156 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 13:57:00.227805 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 13:57:00.231056 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 13:57:00.234294 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 13:57:00.240981 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 13:57:00.244647 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 13:57:00.247684 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 13:57:00.254444 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 13:57:00.257870 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 13:57:00.261068 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4106 13:57:00.268076 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4107 13:57:00.268501 Total UI for P1: 0, mck2ui 16
4108 13:57:00.274505 best dqsien dly found for B0: ( 0, 13, 12)
4109 13:57:00.278108 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4110 13:57:00.281149 Total UI for P1: 0, mck2ui 16
4111 13:57:00.284829 best dqsien dly found for B1: ( 0, 13, 16)
4112 13:57:00.287940 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4113 13:57:00.291376 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4114 13:57:00.291893
4115 13:57:00.294326 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4116 13:57:00.298002 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4117 13:57:00.301354 [Gating] SW calibration Done
4118 13:57:00.301920 ==
4119 13:57:00.304199 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 13:57:00.310574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 13:57:00.310756 ==
4122 13:57:00.310923 RX Vref Scan: 0
4123 13:57:00.311005
4124 13:57:00.313959 RX Vref 0 -> 0, step: 1
4125 13:57:00.314126
4126 13:57:00.316952 RX Delay -230 -> 252, step: 16
4127 13:57:00.320423 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4128 13:57:00.323759 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4129 13:57:00.326828 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4130 13:57:00.333530 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4131 13:57:00.337126 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4132 13:57:00.340783 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4133 13:57:00.343945 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4134 13:57:00.350480 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4135 13:57:00.353749 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4136 13:57:00.356996 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4137 13:57:00.360244 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4138 13:57:00.363384 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4139 13:57:00.370186 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4140 13:57:00.373437 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4141 13:57:00.376815 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4142 13:57:00.383546 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4143 13:57:00.384082 ==
4144 13:57:00.386766 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 13:57:00.390065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 13:57:00.390578 ==
4147 13:57:00.390913 DQS Delay:
4148 13:57:00.393649 DQS0 = 0, DQS1 = 0
4149 13:57:00.394160 DQM Delay:
4150 13:57:00.396598 DQM0 = 37, DQM1 = 28
4151 13:57:00.397111 DQ Delay:
4152 13:57:00.400282 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4153 13:57:00.403682 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4154 13:57:00.406618 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4155 13:57:00.409839 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4156 13:57:00.410354
4157 13:57:00.410685
4158 13:57:00.411020 ==
4159 13:57:00.413177 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 13:57:00.416582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 13:57:00.417098 ==
4162 13:57:00.417432
4163 13:57:00.419530
4164 13:57:00.419943 TX Vref Scan disable
4165 13:57:00.422802 == TX Byte 0 ==
4166 13:57:00.426230 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4167 13:57:00.429704 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4168 13:57:00.432908 == TX Byte 1 ==
4169 13:57:00.435990 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4170 13:57:00.439732 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4171 13:57:00.442585 ==
4172 13:57:00.443008 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 13:57:00.449530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 13:57:00.450052 ==
4175 13:57:00.450394
4176 13:57:00.450706
4177 13:57:00.452538 TX Vref Scan disable
4178 13:57:00.452956 == TX Byte 0 ==
4179 13:57:00.459147 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4180 13:57:00.462266 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4181 13:57:00.462841 == TX Byte 1 ==
4182 13:57:00.469081 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4183 13:57:00.472497 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4184 13:57:00.473052
4185 13:57:00.473396 [DATLAT]
4186 13:57:00.475524 Freq=600, CH0 RK0
4187 13:57:00.475941
4188 13:57:00.476274 DATLAT Default: 0x9
4189 13:57:00.479053 0, 0xFFFF, sum = 0
4190 13:57:00.479662 1, 0xFFFF, sum = 0
4191 13:57:00.482228 2, 0xFFFF, sum = 0
4192 13:57:00.485657 3, 0xFFFF, sum = 0
4193 13:57:00.486084 4, 0xFFFF, sum = 0
4194 13:57:00.488906 5, 0xFFFF, sum = 0
4195 13:57:00.489337 6, 0xFFFF, sum = 0
4196 13:57:00.491548 7, 0xFFFF, sum = 0
4197 13:57:00.491634 8, 0x0, sum = 1
4198 13:57:00.491701 9, 0x0, sum = 2
4199 13:57:00.494937 10, 0x0, sum = 3
4200 13:57:00.495021 11, 0x0, sum = 4
4201 13:57:00.498486 best_step = 9
4202 13:57:00.498637
4203 13:57:00.498778 ==
4204 13:57:00.501795 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 13:57:00.505092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 13:57:00.505177 ==
4207 13:57:00.508072 RX Vref Scan: 1
4208 13:57:00.508154
4209 13:57:00.508220 RX Vref 0 -> 0, step: 1
4210 13:57:00.511616
4211 13:57:00.511699 RX Delay -195 -> 252, step: 8
4212 13:57:00.511764
4213 13:57:00.515069 Set Vref, RX VrefLevel [Byte0]: 60
4214 13:57:00.518162 [Byte1]: 47
4215 13:57:00.522623
4216 13:57:00.522707 Final RX Vref Byte 0 = 60 to rank0
4217 13:57:00.525843 Final RX Vref Byte 1 = 47 to rank0
4218 13:57:00.529383 Final RX Vref Byte 0 = 60 to rank1
4219 13:57:00.532488 Final RX Vref Byte 1 = 47 to rank1==
4220 13:57:00.536040 Dram Type= 6, Freq= 0, CH_0, rank 0
4221 13:57:00.542443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 13:57:00.542535 ==
4223 13:57:00.542602 DQS Delay:
4224 13:57:00.542664 DQS0 = 0, DQS1 = 0
4225 13:57:00.545436 DQM Delay:
4226 13:57:00.545568 DQM0 = 34, DQM1 = 29
4227 13:57:00.549598 DQ Delay:
4228 13:57:00.552321 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4229 13:57:00.555474 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4230 13:57:00.558832 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4231 13:57:00.562131 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4232 13:57:00.562218
4233 13:57:00.562284
4234 13:57:00.569165 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4235 13:57:00.572290 CH0 RK0: MR19=808, MR18=3D3D
4236 13:57:00.578937 CH0_RK0: MR19=0x808, MR18=0x3D3D, DQSOSC=398, MR23=63, INC=165, DEC=110
4237 13:57:00.579044
4238 13:57:00.582165 ----->DramcWriteLeveling(PI) begin...
4239 13:57:00.582251 ==
4240 13:57:00.585436 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 13:57:00.588934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 13:57:00.589024 ==
4243 13:57:00.592326 Write leveling (Byte 0): 32 => 32
4244 13:57:00.595669 Write leveling (Byte 1): 31 => 31
4245 13:57:00.598618 DramcWriteLeveling(PI) end<-----
4246 13:57:00.598705
4247 13:57:00.598769 ==
4248 13:57:00.601999 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 13:57:00.605143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 13:57:00.605227 ==
4251 13:57:00.608542 [Gating] SW mode calibration
4252 13:57:00.615067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4253 13:57:00.621970 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4254 13:57:00.625375 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4255 13:57:00.631760 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4256 13:57:00.635121 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4257 13:57:00.638357 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
4258 13:57:00.645197 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4259 13:57:00.648658 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 13:57:00.651623 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 13:57:00.658576 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 13:57:00.661428 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 13:57:00.664973 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 13:57:00.671597 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 13:57:00.674992 0 10 12 | B1->B0 | 2828 3131 | 0 0 | (0 0) (0 0)
4266 13:57:00.678050 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4267 13:57:00.681703 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 13:57:00.688122 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 13:57:00.691748 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 13:57:00.694786 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 13:57:00.701657 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 13:57:00.704795 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 13:57:00.707758 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4274 13:57:00.714641 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 13:57:00.717856 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 13:57:00.721113 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 13:57:00.727776 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 13:57:00.730835 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 13:57:00.734364 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 13:57:00.740765 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 13:57:00.744210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 13:57:00.747624 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 13:57:00.754135 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 13:57:00.757625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 13:57:00.760867 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 13:57:00.767339 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 13:57:00.770832 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 13:57:00.773903 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 13:57:00.780492 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4290 13:57:00.783953 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 13:57:00.787184 Total UI for P1: 0, mck2ui 16
4292 13:57:00.790553 best dqsien dly found for B0: ( 0, 13, 12)
4293 13:57:00.793897 Total UI for P1: 0, mck2ui 16
4294 13:57:00.797287 best dqsien dly found for B1: ( 0, 13, 14)
4295 13:57:00.800371 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4296 13:57:00.803749 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4297 13:57:00.803840
4298 13:57:00.807013 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4299 13:57:00.813847 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4300 13:57:00.813936 [Gating] SW calibration Done
4301 13:57:00.814003 ==
4302 13:57:00.816892 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 13:57:00.823830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 13:57:00.823924 ==
4305 13:57:00.823991 RX Vref Scan: 0
4306 13:57:00.824052
4307 13:57:00.826966 RX Vref 0 -> 0, step: 1
4308 13:57:00.827049
4309 13:57:00.830291 RX Delay -230 -> 252, step: 16
4310 13:57:00.833773 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4311 13:57:00.836977 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4312 13:57:00.843558 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4313 13:57:00.846605 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4314 13:57:00.850176 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4315 13:57:00.853531 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4316 13:57:00.856732 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4317 13:57:00.863228 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4318 13:57:00.866585 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4319 13:57:00.869804 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4320 13:57:00.873273 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4321 13:57:00.879889 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4322 13:57:00.882923 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4323 13:57:00.886160 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4324 13:57:00.889677 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4325 13:57:00.896076 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4326 13:57:00.896190 ==
4327 13:57:00.899493 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 13:57:00.903006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 13:57:00.903095 ==
4330 13:57:00.903161 DQS Delay:
4331 13:57:00.906458 DQS0 = 0, DQS1 = 0
4332 13:57:00.906567 DQM Delay:
4333 13:57:00.909468 DQM0 = 36, DQM1 = 30
4334 13:57:00.909586 DQ Delay:
4335 13:57:00.912789 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4336 13:57:00.916062 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4337 13:57:00.919634 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4338 13:57:00.923033 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =33
4339 13:57:00.923118
4340 13:57:00.923184
4341 13:57:00.923244 ==
4342 13:57:00.926114 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 13:57:00.929436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 13:57:00.929562 ==
4345 13:57:00.929629
4346 13:57:00.929689
4347 13:57:00.932956 TX Vref Scan disable
4348 13:57:00.936298 == TX Byte 0 ==
4349 13:57:00.939519 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4350 13:57:00.942874 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4351 13:57:00.946273 == TX Byte 1 ==
4352 13:57:00.949458 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4353 13:57:00.953034 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4354 13:57:00.953117 ==
4355 13:57:00.956277 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 13:57:00.962692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 13:57:00.962786 ==
4358 13:57:00.962854
4359 13:57:00.962915
4360 13:57:00.962973 TX Vref Scan disable
4361 13:57:00.967059 == TX Byte 0 ==
4362 13:57:00.970501 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4363 13:57:00.976982 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4364 13:57:00.977070 == TX Byte 1 ==
4365 13:57:00.980369 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4366 13:57:00.986903 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4367 13:57:00.986999
4368 13:57:00.987064 [DATLAT]
4369 13:57:00.987124 Freq=600, CH0 RK1
4370 13:57:00.987183
4371 13:57:00.990253 DATLAT Default: 0x9
4372 13:57:00.990338 0, 0xFFFF, sum = 0
4373 13:57:00.993795 1, 0xFFFF, sum = 0
4374 13:57:00.993883 2, 0xFFFF, sum = 0
4375 13:57:00.996894 3, 0xFFFF, sum = 0
4376 13:57:00.999937 4, 0xFFFF, sum = 0
4377 13:57:01.000021 5, 0xFFFF, sum = 0
4378 13:57:01.003309 6, 0xFFFF, sum = 0
4379 13:57:01.003395 7, 0xFFFF, sum = 0
4380 13:57:01.006853 8, 0x0, sum = 1
4381 13:57:01.006936 9, 0x0, sum = 2
4382 13:57:01.007002 10, 0x0, sum = 3
4383 13:57:01.010007 11, 0x0, sum = 4
4384 13:57:01.010090 best_step = 9
4385 13:57:01.010155
4386 13:57:01.010215 ==
4387 13:57:01.013224 Dram Type= 6, Freq= 0, CH_0, rank 1
4388 13:57:01.020115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 13:57:01.020209 ==
4390 13:57:01.020276 RX Vref Scan: 0
4391 13:57:01.020337
4392 13:57:01.023566 RX Vref 0 -> 0, step: 1
4393 13:57:01.023654
4394 13:57:01.026613 RX Delay -195 -> 252, step: 8
4395 13:57:01.030155 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4396 13:57:01.036571 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4397 13:57:01.039831 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4398 13:57:01.043115 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4399 13:57:01.046531 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4400 13:57:01.053085 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4401 13:57:01.056480 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4402 13:57:01.059722 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4403 13:57:01.063278 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4404 13:57:01.066194 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4405 13:57:01.072932 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4406 13:57:01.076355 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4407 13:57:01.079810 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4408 13:57:01.082968 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4409 13:57:01.089458 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4410 13:57:01.092914 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4411 13:57:01.093002 ==
4412 13:57:01.096068 Dram Type= 6, Freq= 0, CH_0, rank 1
4413 13:57:01.099448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 13:57:01.099533 ==
4415 13:57:01.103116 DQS Delay:
4416 13:57:01.103272 DQS0 = 0, DQS1 = 0
4417 13:57:01.106478 DQM Delay:
4418 13:57:01.106636 DQM0 = 33, DQM1 = 28
4419 13:57:01.106707 DQ Delay:
4420 13:57:01.109587 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4421 13:57:01.112892 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4422 13:57:01.116287 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4423 13:57:01.119436 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4424 13:57:01.119593
4425 13:57:01.119665
4426 13:57:01.129325 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4427 13:57:01.132819 CH0 RK1: MR19=808, MR18=6C3B
4428 13:57:01.139674 CH0_RK1: MR19=0x808, MR18=0x6C3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4429 13:57:01.139851 [RxdqsGatingPostProcess] freq 600
4430 13:57:01.145883 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4431 13:57:01.149224 Pre-setting of DQS Precalculation
4432 13:57:01.152271 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4433 13:57:01.155957 ==
4434 13:57:01.159463 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 13:57:01.162484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 13:57:01.162685 ==
4437 13:57:01.165551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4438 13:57:01.172344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4439 13:57:01.176386 [CA 0] Center 35 (5~66) winsize 62
4440 13:57:01.180037 [CA 1] Center 35 (5~66) winsize 62
4441 13:57:01.182946 [CA 2] Center 34 (4~65) winsize 62
4442 13:57:01.186343 [CA 3] Center 34 (3~65) winsize 63
4443 13:57:01.189881 [CA 4] Center 34 (4~65) winsize 62
4444 13:57:01.193162 [CA 5] Center 33 (3~64) winsize 62
4445 13:57:01.193725
4446 13:57:01.196190 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4447 13:57:01.196622
4448 13:57:01.199882 [CATrainingPosCal] consider 1 rank data
4449 13:57:01.202949 u2DelayCellTimex100 = 270/100 ps
4450 13:57:01.205720 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4451 13:57:01.212230 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4452 13:57:01.215682 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4453 13:57:01.219205 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4454 13:57:01.222504 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4455 13:57:01.225751 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4456 13:57:01.225836
4457 13:57:01.229113 CA PerBit enable=1, Macro0, CA PI delay=33
4458 13:57:01.229196
4459 13:57:01.232290 [CBTSetCACLKResult] CA Dly = 33
4460 13:57:01.232373 CS Dly: 3 (0~34)
4461 13:57:01.235744 ==
4462 13:57:01.239044 Dram Type= 6, Freq= 0, CH_1, rank 1
4463 13:57:01.242259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 13:57:01.242347 ==
4465 13:57:01.245448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4466 13:57:01.252289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4467 13:57:01.256232 [CA 0] Center 36 (6~66) winsize 61
4468 13:57:01.259378 [CA 1] Center 36 (5~67) winsize 63
4469 13:57:01.262585 [CA 2] Center 34 (4~65) winsize 62
4470 13:57:01.266044 [CA 3] Center 34 (3~65) winsize 63
4471 13:57:01.269416 [CA 4] Center 34 (4~65) winsize 62
4472 13:57:01.272741 [CA 5] Center 34 (3~65) winsize 63
4473 13:57:01.272862
4474 13:57:01.276107 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4475 13:57:01.276248
4476 13:57:01.279333 [CATrainingPosCal] consider 2 rank data
4477 13:57:01.282823 u2DelayCellTimex100 = 270/100 ps
4478 13:57:01.285870 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4479 13:57:01.292390 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4480 13:57:01.295838 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4481 13:57:01.299241 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4482 13:57:01.302330 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4483 13:57:01.305634 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4484 13:57:01.305757
4485 13:57:01.309164 CA PerBit enable=1, Macro0, CA PI delay=33
4486 13:57:01.309297
4487 13:57:01.312113 [CBTSetCACLKResult] CA Dly = 33
4488 13:57:01.315800 CS Dly: 4 (0~37)
4489 13:57:01.315924
4490 13:57:01.319086 ----->DramcWriteLeveling(PI) begin...
4491 13:57:01.319228 ==
4492 13:57:01.322195 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 13:57:01.325436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 13:57:01.325610 ==
4495 13:57:01.328962 Write leveling (Byte 0): 29 => 29
4496 13:57:01.332237 Write leveling (Byte 1): 30 => 30
4497 13:57:01.335466 DramcWriteLeveling(PI) end<-----
4498 13:57:01.335585
4499 13:57:01.335689 ==
4500 13:57:01.338963 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 13:57:01.341986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 13:57:01.342117 ==
4503 13:57:01.345577 [Gating] SW mode calibration
4504 13:57:01.352216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4505 13:57:01.358818 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4506 13:57:01.362147 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4507 13:57:01.365350 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4508 13:57:01.371966 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4509 13:57:01.375430 0 9 12 | B1->B0 | 3131 3030 | 1 1 | (1 0) (1 0)
4510 13:57:01.378763 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
4511 13:57:01.385608 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 13:57:01.388753 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 13:57:01.392095 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 13:57:01.398493 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 13:57:01.401991 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4516 13:57:01.405185 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 13:57:01.411942 0 10 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
4518 13:57:01.414965 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4519 13:57:01.418417 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 13:57:01.424861 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 13:57:01.428446 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 13:57:01.431430 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 13:57:01.434835 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 13:57:01.441659 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 13:57:01.445082 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4526 13:57:01.448195 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 13:57:01.454811 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 13:57:01.458157 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 13:57:01.461412 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 13:57:01.468176 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 13:57:01.471360 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 13:57:01.474756 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 13:57:01.481371 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 13:57:01.485290 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 13:57:01.487942 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 13:57:01.494687 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 13:57:01.497696 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 13:57:01.501108 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 13:57:01.508007 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 13:57:01.511328 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 13:57:01.514511 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4542 13:57:01.520982 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4543 13:57:01.521074 Total UI for P1: 0, mck2ui 16
4544 13:57:01.527898 best dqsien dly found for B0: ( 0, 13, 12)
4545 13:57:01.527984 Total UI for P1: 0, mck2ui 16
4546 13:57:01.534623 best dqsien dly found for B1: ( 0, 13, 12)
4547 13:57:01.537639 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4548 13:57:01.541188 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4549 13:57:01.541283
4550 13:57:01.544855 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4551 13:57:01.547793 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4552 13:57:01.551111 [Gating] SW calibration Done
4553 13:57:01.551197 ==
4554 13:57:01.554285 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 13:57:01.557733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 13:57:01.557825 ==
4557 13:57:01.560928 RX Vref Scan: 0
4558 13:57:01.561019
4559 13:57:01.561085 RX Vref 0 -> 0, step: 1
4560 13:57:01.561146
4561 13:57:01.564348 RX Delay -230 -> 252, step: 16
4562 13:57:01.570781 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4563 13:57:01.574304 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4564 13:57:01.577629 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4565 13:57:01.580986 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4566 13:57:01.584326 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4567 13:57:01.591017 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4568 13:57:01.594171 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4569 13:57:01.597177 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4570 13:57:01.600696 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4571 13:57:01.607307 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4572 13:57:01.610638 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4573 13:57:01.613763 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4574 13:57:01.617232 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4575 13:57:01.623969 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4576 13:57:01.627174 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4577 13:57:01.630209 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4578 13:57:01.630293 ==
4579 13:57:01.633704 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 13:57:01.636961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 13:57:01.640280 ==
4582 13:57:01.640371 DQS Delay:
4583 13:57:01.640438 DQS0 = 0, DQS1 = 0
4584 13:57:01.643806 DQM Delay:
4585 13:57:01.643887 DQM0 = 38, DQM1 = 28
4586 13:57:01.646927 DQ Delay:
4587 13:57:01.647009 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4588 13:57:01.650323 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4589 13:57:01.653456 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4590 13:57:01.656969 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4591 13:57:01.659898
4592 13:57:01.659985
4593 13:57:01.660051 ==
4594 13:57:01.663374 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 13:57:01.666717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 13:57:01.666801 ==
4597 13:57:01.666867
4598 13:57:01.666928
4599 13:57:01.670177 TX Vref Scan disable
4600 13:57:01.670261 == TX Byte 0 ==
4601 13:57:01.676729 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4602 13:57:01.679920 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4603 13:57:01.680021 == TX Byte 1 ==
4604 13:57:01.686729 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4605 13:57:01.689807 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4606 13:57:01.689897 ==
4607 13:57:01.693020 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 13:57:01.696561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 13:57:01.696652 ==
4610 13:57:01.696718
4611 13:57:01.696779
4612 13:57:01.699608 TX Vref Scan disable
4613 13:57:01.702937 == TX Byte 0 ==
4614 13:57:01.706437 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4615 13:57:01.709637 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4616 13:57:01.713069 == TX Byte 1 ==
4617 13:57:01.716052 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4618 13:57:01.722808 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4619 13:57:01.722919
4620 13:57:01.722993 [DATLAT]
4621 13:57:01.723056 Freq=600, CH1 RK0
4622 13:57:01.723116
4623 13:57:01.725937 DATLAT Default: 0x9
4624 13:57:01.726021 0, 0xFFFF, sum = 0
4625 13:57:01.729630 1, 0xFFFF, sum = 0
4626 13:57:01.729720 2, 0xFFFF, sum = 0
4627 13:57:01.732779 3, 0xFFFF, sum = 0
4628 13:57:01.735882 4, 0xFFFF, sum = 0
4629 13:57:01.735971 5, 0xFFFF, sum = 0
4630 13:57:01.739157 6, 0xFFFF, sum = 0
4631 13:57:01.739255 7, 0xFFFF, sum = 0
4632 13:57:01.742413 8, 0x0, sum = 1
4633 13:57:01.742504 9, 0x0, sum = 2
4634 13:57:01.742572 10, 0x0, sum = 3
4635 13:57:01.745913 11, 0x0, sum = 4
4636 13:57:01.745996 best_step = 9
4637 13:57:01.746061
4638 13:57:01.746121 ==
4639 13:57:01.749449 Dram Type= 6, Freq= 0, CH_1, rank 0
4640 13:57:01.755813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 13:57:01.755896 ==
4642 13:57:01.755962 RX Vref Scan: 1
4643 13:57:01.756024
4644 13:57:01.759228 RX Vref 0 -> 0, step: 1
4645 13:57:01.759311
4646 13:57:01.762385 RX Delay -195 -> 252, step: 8
4647 13:57:01.762470
4648 13:57:01.765899 Set Vref, RX VrefLevel [Byte0]: 56
4649 13:57:01.769351 [Byte1]: 55
4650 13:57:01.769441
4651 13:57:01.772312 Final RX Vref Byte 0 = 56 to rank0
4652 13:57:01.775794 Final RX Vref Byte 1 = 55 to rank0
4653 13:57:01.778984 Final RX Vref Byte 0 = 56 to rank1
4654 13:57:01.782385 Final RX Vref Byte 1 = 55 to rank1==
4655 13:57:01.785703 Dram Type= 6, Freq= 0, CH_1, rank 0
4656 13:57:01.788833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 13:57:01.788918 ==
4658 13:57:01.792252 DQS Delay:
4659 13:57:01.792339 DQS0 = 0, DQS1 = 0
4660 13:57:01.795746 DQM Delay:
4661 13:57:01.795828 DQM0 = 38, DQM1 = 28
4662 13:57:01.795893 DQ Delay:
4663 13:57:01.799047 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4664 13:57:01.802093 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4665 13:57:01.805481 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4666 13:57:01.808909 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4667 13:57:01.808991
4668 13:57:01.812164
4669 13:57:01.818881 [DQSOSCAuto] RK0, (LSB)MR18= 0x212e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4670 13:57:01.822008 CH1 RK0: MR19=808, MR18=212E
4671 13:57:01.828874 CH1_RK0: MR19=0x808, MR18=0x212E, DQSOSC=401, MR23=63, INC=163, DEC=108
4672 13:57:01.828956
4673 13:57:01.831929 ----->DramcWriteLeveling(PI) begin...
4674 13:57:01.832017 ==
4675 13:57:01.835724 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 13:57:01.838674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 13:57:01.838839 ==
4678 13:57:01.842025 Write leveling (Byte 0): 28 => 28
4679 13:57:01.845419 Write leveling (Byte 1): 30 => 30
4680 13:57:01.848890 DramcWriteLeveling(PI) end<-----
4681 13:57:01.849084
4682 13:57:01.849185 ==
4683 13:57:01.852159 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 13:57:01.855467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 13:57:01.855665 ==
4686 13:57:01.858720 [Gating] SW mode calibration
4687 13:57:01.865136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4688 13:57:01.871941 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4689 13:57:01.875308 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4690 13:57:01.878568 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4691 13:57:01.885280 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4692 13:57:01.888587 0 9 12 | B1->B0 | 3030 2e2e | 1 1 | (1 0) (1 0)
4693 13:57:01.892041 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 13:57:01.898506 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 13:57:01.901655 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 13:57:01.905642 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4697 13:57:01.911393 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4698 13:57:01.914745 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4699 13:57:01.918208 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4700 13:57:01.924801 0 10 12 | B1->B0 | 302f 3b3b | 1 0 | (0 0) (0 0)
4701 13:57:01.928055 0 10 16 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
4702 13:57:01.931524 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 13:57:01.938134 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 13:57:01.941121 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 13:57:01.944592 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 13:57:01.951660 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 13:57:01.954598 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 13:57:01.957608 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4709 13:57:01.964699 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 13:57:01.967485 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 13:57:01.973260 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 13:57:01.977203 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 13:57:01.980631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 13:57:01.984021 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 13:57:01.990890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 13:57:01.994206 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 13:57:01.997536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 13:57:02.003860 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 13:57:02.007518 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 13:57:02.010987 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 13:57:02.017384 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 13:57:02.020655 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 13:57:02.023914 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 13:57:02.030553 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4725 13:57:02.033993 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 13:57:02.037339 Total UI for P1: 0, mck2ui 16
4727 13:57:02.040421 best dqsien dly found for B0: ( 0, 13, 12)
4728 13:57:02.043878 Total UI for P1: 0, mck2ui 16
4729 13:57:02.047130 best dqsien dly found for B1: ( 0, 13, 12)
4730 13:57:02.050402 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4731 13:57:02.053649 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4732 13:57:02.054083
4733 13:57:02.057053 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4734 13:57:02.060199 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4735 13:57:02.063520 [Gating] SW calibration Done
4736 13:57:02.063960 ==
4737 13:57:02.066922 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 13:57:02.073412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 13:57:02.073902 ==
4740 13:57:02.074241 RX Vref Scan: 0
4741 13:57:02.074561
4742 13:57:02.076808 RX Vref 0 -> 0, step: 1
4743 13:57:02.077224
4744 13:57:02.080210 RX Delay -230 -> 252, step: 16
4745 13:57:02.083267 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4746 13:57:02.086655 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4747 13:57:02.089965 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4748 13:57:02.096572 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4749 13:57:02.099696 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4750 13:57:02.103320 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4751 13:57:02.106465 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4752 13:57:02.112927 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4753 13:57:02.116359 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4754 13:57:02.119477 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4755 13:57:02.122965 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4756 13:57:02.129770 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4757 13:57:02.133172 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4758 13:57:02.136677 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4759 13:57:02.139415 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4760 13:57:02.146627 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4761 13:57:02.147017 ==
4762 13:57:02.149789 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 13:57:02.152916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 13:57:02.153304 ==
4765 13:57:02.153615 DQS Delay:
4766 13:57:02.156156 DQS0 = 0, DQS1 = 0
4767 13:57:02.156455 DQM Delay:
4768 13:57:02.159725 DQM0 = 40, DQM1 = 35
4769 13:57:02.160024 DQ Delay:
4770 13:57:02.162998 DQ0 =41, DQ1 =41, DQ2 =17, DQ3 =41
4771 13:57:02.166159 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4772 13:57:02.169360 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4773 13:57:02.172975 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4774 13:57:02.173456
4775 13:57:02.173828
4776 13:57:02.174120 ==
4777 13:57:02.175931 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 13:57:02.179266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 13:57:02.179654 ==
4780 13:57:02.179960
4781 13:57:02.180246
4782 13:57:02.182755 TX Vref Scan disable
4783 13:57:02.186095 == TX Byte 0 ==
4784 13:57:02.189416 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4785 13:57:02.192773 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4786 13:57:02.196267 == TX Byte 1 ==
4787 13:57:02.199639 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4788 13:57:02.202768 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4789 13:57:02.203251 ==
4790 13:57:02.206237 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 13:57:02.212872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 13:57:02.213359 ==
4793 13:57:02.213734
4794 13:57:02.214030
4795 13:57:02.214324 TX Vref Scan disable
4796 13:57:02.217273 == TX Byte 0 ==
4797 13:57:02.220554 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4798 13:57:02.227042 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4799 13:57:02.227533 == TX Byte 1 ==
4800 13:57:02.230164 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4801 13:57:02.236582 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4802 13:57:02.237005
4803 13:57:02.237341 [DATLAT]
4804 13:57:02.237705 Freq=600, CH1 RK1
4805 13:57:02.238020
4806 13:57:02.239699 DATLAT Default: 0x9
4807 13:57:02.243007 0, 0xFFFF, sum = 0
4808 13:57:02.243431 1, 0xFFFF, sum = 0
4809 13:57:02.246300 2, 0xFFFF, sum = 0
4810 13:57:02.246726 3, 0xFFFF, sum = 0
4811 13:57:02.249912 4, 0xFFFF, sum = 0
4812 13:57:02.250507 5, 0xFFFF, sum = 0
4813 13:57:02.253028 6, 0xFFFF, sum = 0
4814 13:57:02.253452 7, 0xFFFF, sum = 0
4815 13:57:02.256750 8, 0x0, sum = 1
4816 13:57:02.257284 9, 0x0, sum = 2
4817 13:57:02.259957 10, 0x0, sum = 3
4818 13:57:02.260499 11, 0x0, sum = 4
4819 13:57:02.260847 best_step = 9
4820 13:57:02.261162
4821 13:57:02.263134 ==
4822 13:57:02.263553 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 13:57:02.269708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 13:57:02.270134 ==
4825 13:57:02.270471 RX Vref Scan: 0
4826 13:57:02.270788
4827 13:57:02.273192 RX Vref 0 -> 0, step: 1
4828 13:57:02.273644
4829 13:57:02.276569 RX Delay -195 -> 252, step: 8
4830 13:57:02.283204 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4831 13:57:02.286776 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4832 13:57:02.289596 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4833 13:57:02.293274 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4834 13:57:02.296633 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4835 13:57:02.303163 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4836 13:57:02.306636 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4837 13:57:02.309445 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4838 13:57:02.313147 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4839 13:57:02.316619 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4840 13:57:02.322990 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4841 13:57:02.325882 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4842 13:57:02.329350 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4843 13:57:02.336158 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4844 13:57:02.339689 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4845 13:57:02.342489 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4846 13:57:02.342909 ==
4847 13:57:02.346144 Dram Type= 6, Freq= 0, CH_1, rank 1
4848 13:57:02.349149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4849 13:57:02.349609 ==
4850 13:57:02.352521 DQS Delay:
4851 13:57:02.352942 DQS0 = 0, DQS1 = 0
4852 13:57:02.355970 DQM Delay:
4853 13:57:02.356488 DQM0 = 35, DQM1 = 30
4854 13:57:02.356829 DQ Delay:
4855 13:57:02.359404 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4856 13:57:02.362756 DQ4 =32, DQ5 =44, DQ6 =44, DQ7 =32
4857 13:57:02.365524 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4858 13:57:02.369043 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4859 13:57:02.369462
4860 13:57:02.369860
4861 13:57:02.379317 [DQSOSCAuto] RK1, (LSB)MR18= 0x3757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4862 13:57:02.382691 CH1 RK1: MR19=808, MR18=3757
4863 13:57:02.389314 CH1_RK1: MR19=0x808, MR18=0x3757, DQSOSC=393, MR23=63, INC=169, DEC=113
4864 13:57:02.389855 [RxdqsGatingPostProcess] freq 600
4865 13:57:02.395804 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4866 13:57:02.399254 Pre-setting of DQS Precalculation
4867 13:57:02.402241 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4868 13:57:02.412304 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4869 13:57:02.419044 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4870 13:57:02.419465
4871 13:57:02.419800
4872 13:57:02.422037 [Calibration Summary] 1200 Mbps
4873 13:57:02.422461 CH 0, Rank 0
4874 13:57:02.425666 SW Impedance : PASS
4875 13:57:02.426202 DUTY Scan : NO K
4876 13:57:02.429013 ZQ Calibration : PASS
4877 13:57:02.432375 Jitter Meter : NO K
4878 13:57:02.432902 CBT Training : PASS
4879 13:57:02.435755 Write leveling : PASS
4880 13:57:02.438929 RX DQS gating : PASS
4881 13:57:02.439409 RX DQ/DQS(RDDQC) : PASS
4882 13:57:02.442263 TX DQ/DQS : PASS
4883 13:57:02.445553 RX DATLAT : PASS
4884 13:57:02.445974 RX DQ/DQS(Engine): PASS
4885 13:57:02.448499 TX OE : NO K
4886 13:57:02.448917 All Pass.
4887 13:57:02.449248
4888 13:57:02.452241 CH 0, Rank 1
4889 13:57:02.452764 SW Impedance : PASS
4890 13:57:02.455325 DUTY Scan : NO K
4891 13:57:02.458426 ZQ Calibration : PASS
4892 13:57:02.458846 Jitter Meter : NO K
4893 13:57:02.462032 CBT Training : PASS
4894 13:57:02.465532 Write leveling : PASS
4895 13:57:02.466046 RX DQS gating : PASS
4896 13:57:02.468997 RX DQ/DQS(RDDQC) : PASS
4897 13:57:02.471910 TX DQ/DQS : PASS
4898 13:57:02.472427 RX DATLAT : PASS
4899 13:57:02.475051 RX DQ/DQS(Engine): PASS
4900 13:57:02.475472 TX OE : NO K
4901 13:57:02.478695 All Pass.
4902 13:57:02.479112
4903 13:57:02.479449 CH 1, Rank 0
4904 13:57:02.481870 SW Impedance : PASS
4905 13:57:02.482292 DUTY Scan : NO K
4906 13:57:02.485472 ZQ Calibration : PASS
4907 13:57:02.488530 Jitter Meter : NO K
4908 13:57:02.488954 CBT Training : PASS
4909 13:57:02.491405 Write leveling : PASS
4910 13:57:02.495117 RX DQS gating : PASS
4911 13:57:02.495538 RX DQ/DQS(RDDQC) : PASS
4912 13:57:02.498178 TX DQ/DQS : PASS
4913 13:57:02.501691 RX DATLAT : PASS
4914 13:57:02.502114 RX DQ/DQS(Engine): PASS
4915 13:57:02.505421 TX OE : NO K
4916 13:57:02.505970 All Pass.
4917 13:57:02.506307
4918 13:57:02.508955 CH 1, Rank 1
4919 13:57:02.509464 SW Impedance : PASS
4920 13:57:02.512165 DUTY Scan : NO K
4921 13:57:02.515185 ZQ Calibration : PASS
4922 13:57:02.515620 Jitter Meter : NO K
4923 13:57:02.518549 CBT Training : PASS
4924 13:57:02.519058 Write leveling : PASS
4925 13:57:02.521946 RX DQS gating : PASS
4926 13:57:02.524997 RX DQ/DQS(RDDQC) : PASS
4927 13:57:02.525417 TX DQ/DQS : PASS
4928 13:57:02.528605 RX DATLAT : PASS
4929 13:57:02.531887 RX DQ/DQS(Engine): PASS
4930 13:57:02.532400 TX OE : NO K
4931 13:57:02.535519 All Pass.
4932 13:57:02.536033
4933 13:57:02.536372 DramC Write-DBI off
4934 13:57:02.538208 PER_BANK_REFRESH: Hybrid Mode
4935 13:57:02.541770 TX_TRACKING: ON
4936 13:57:02.548420 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4937 13:57:02.551498 [FAST_K] Save calibration result to emmc
4938 13:57:02.555117 dramc_set_vcore_voltage set vcore to 662500
4939 13:57:02.558230 Read voltage for 933, 3
4940 13:57:02.558646 Vio18 = 0
4941 13:57:02.561552 Vcore = 662500
4942 13:57:02.562069 Vdram = 0
4943 13:57:02.562404 Vddq = 0
4944 13:57:02.564790 Vmddr = 0
4945 13:57:02.568347 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4946 13:57:02.574749 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4947 13:57:02.575247 MEM_TYPE=3, freq_sel=17
4948 13:57:02.577926 sv_algorithm_assistance_LP4_1600
4949 13:57:02.584822 ============ PULL DRAM RESETB DOWN ============
4950 13:57:02.588114 ========== PULL DRAM RESETB DOWN end =========
4951 13:57:02.591084 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4952 13:57:02.594508 ===================================
4953 13:57:02.597772 LPDDR4 DRAM CONFIGURATION
4954 13:57:02.601243 ===================================
4955 13:57:02.604585 EX_ROW_EN[0] = 0x0
4956 13:57:02.605093 EX_ROW_EN[1] = 0x0
4957 13:57:02.607951 LP4Y_EN = 0x0
4958 13:57:02.608460 WORK_FSP = 0x0
4959 13:57:02.611421 WL = 0x3
4960 13:57:02.611932 RL = 0x3
4961 13:57:02.614579 BL = 0x2
4962 13:57:02.614993 RPST = 0x0
4963 13:57:02.617959 RD_PRE = 0x0
4964 13:57:02.618475 WR_PRE = 0x1
4965 13:57:02.621076 WR_PST = 0x0
4966 13:57:02.621537 DBI_WR = 0x0
4967 13:57:02.624108 DBI_RD = 0x0
4968 13:57:02.624528 OTF = 0x1
4969 13:57:02.627484 ===================================
4970 13:57:02.631010 ===================================
4971 13:57:02.634337 ANA top config
4972 13:57:02.637602 ===================================
4973 13:57:02.641235 DLL_ASYNC_EN = 0
4974 13:57:02.641808 ALL_SLAVE_EN = 1
4975 13:57:02.644089 NEW_RANK_MODE = 1
4976 13:57:02.647960 DLL_IDLE_MODE = 1
4977 13:57:02.650649 LP45_APHY_COMB_EN = 1
4978 13:57:02.654189 TX_ODT_DIS = 1
4979 13:57:02.654611 NEW_8X_MODE = 1
4980 13:57:02.657572 ===================================
4981 13:57:02.660992 ===================================
4982 13:57:02.664357 data_rate = 1866
4983 13:57:02.667047 CKR = 1
4984 13:57:02.670581 DQ_P2S_RATIO = 8
4985 13:57:02.673773 ===================================
4986 13:57:02.677076 CA_P2S_RATIO = 8
4987 13:57:02.677536 DQ_CA_OPEN = 0
4988 13:57:02.680674 DQ_SEMI_OPEN = 0
4989 13:57:02.683980 CA_SEMI_OPEN = 0
4990 13:57:02.687142 CA_FULL_RATE = 0
4991 13:57:02.690418 DQ_CKDIV4_EN = 1
4992 13:57:02.693533 CA_CKDIV4_EN = 1
4993 13:57:02.697218 CA_PREDIV_EN = 0
4994 13:57:02.697808 PH8_DLY = 0
4995 13:57:02.700280 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4996 13:57:02.703892 DQ_AAMCK_DIV = 4
4997 13:57:02.707443 CA_AAMCK_DIV = 4
4998 13:57:02.710120 CA_ADMCK_DIV = 4
4999 13:57:02.713371 DQ_TRACK_CA_EN = 0
5000 13:57:02.713843 CA_PICK = 933
5001 13:57:02.716819 CA_MCKIO = 933
5002 13:57:02.720192 MCKIO_SEMI = 0
5003 13:57:02.723364 PLL_FREQ = 3732
5004 13:57:02.726429 DQ_UI_PI_RATIO = 32
5005 13:57:02.729875 CA_UI_PI_RATIO = 0
5006 13:57:02.733150 ===================================
5007 13:57:02.736843 ===================================
5008 13:57:02.740285 memory_type:LPDDR4
5009 13:57:02.740799 GP_NUM : 10
5010 13:57:02.742965 SRAM_EN : 1
5011 13:57:02.743384 MD32_EN : 0
5012 13:57:02.746518 ===================================
5013 13:57:02.749574 [ANA_INIT] >>>>>>>>>>>>>>
5014 13:57:02.753076 <<<<<< [CONFIGURE PHASE]: ANA_TX
5015 13:57:02.756185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5016 13:57:02.759480 ===================================
5017 13:57:02.762970 data_rate = 1866,PCW = 0X8f00
5018 13:57:02.766103 ===================================
5019 13:57:02.769945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5020 13:57:02.773130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5021 13:57:02.779604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5022 13:57:02.785922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5023 13:57:02.789309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5024 13:57:02.792711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5025 13:57:02.793217 [ANA_INIT] flow start
5026 13:57:02.796099 [ANA_INIT] PLL >>>>>>>>
5027 13:57:02.799110 [ANA_INIT] PLL <<<<<<<<
5028 13:57:02.799512 [ANA_INIT] MIDPI >>>>>>>>
5029 13:57:02.802411 [ANA_INIT] MIDPI <<<<<<<<
5030 13:57:02.806156 [ANA_INIT] DLL >>>>>>>>
5031 13:57:02.806681 [ANA_INIT] flow end
5032 13:57:02.812957 ============ LP4 DIFF to SE enter ============
5033 13:57:02.816082 ============ LP4 DIFF to SE exit ============
5034 13:57:02.819143 [ANA_INIT] <<<<<<<<<<<<<
5035 13:57:02.822692 [Flow] Enable top DCM control >>>>>
5036 13:57:02.825613 [Flow] Enable top DCM control <<<<<
5037 13:57:02.826040 Enable DLL master slave shuffle
5038 13:57:02.832847 ==============================================================
5039 13:57:02.836219 Gating Mode config
5040 13:57:02.839219 ==============================================================
5041 13:57:02.842500 Config description:
5042 13:57:02.852013 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5043 13:57:02.859127 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5044 13:57:02.862107 SELPH_MODE 0: By rank 1: By Phase
5045 13:57:02.868898 ==============================================================
5046 13:57:02.872140 GAT_TRACK_EN = 1
5047 13:57:02.875545 RX_GATING_MODE = 2
5048 13:57:02.878629 RX_GATING_TRACK_MODE = 2
5049 13:57:02.882118 SELPH_MODE = 1
5050 13:57:02.882536 PICG_EARLY_EN = 1
5051 13:57:02.885131 VALID_LAT_VALUE = 1
5052 13:57:02.891762 ==============================================================
5053 13:57:02.895389 Enter into Gating configuration >>>>
5054 13:57:02.898482 Exit from Gating configuration <<<<
5055 13:57:02.901579 Enter into DVFS_PRE_config >>>>>
5056 13:57:02.912158 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5057 13:57:02.915147 Exit from DVFS_PRE_config <<<<<
5058 13:57:02.918226 Enter into PICG configuration >>>>
5059 13:57:02.921879 Exit from PICG configuration <<<<
5060 13:57:02.925186 [RX_INPUT] configuration >>>>>
5061 13:57:02.928137 [RX_INPUT] configuration <<<<<
5062 13:57:02.932019 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5063 13:57:02.937997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5064 13:57:02.944685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5065 13:57:02.951582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5066 13:57:02.958429 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5067 13:57:02.965039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5068 13:57:02.968229 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5069 13:57:02.971240 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5070 13:57:02.974660 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5071 13:57:02.980608 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5072 13:57:02.984215 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5073 13:57:02.987557 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5074 13:57:02.991100 ===================================
5075 13:57:02.994024 LPDDR4 DRAM CONFIGURATION
5076 13:57:02.997548 ===================================
5077 13:57:02.997722 EX_ROW_EN[0] = 0x0
5078 13:57:03.000890 EX_ROW_EN[1] = 0x0
5079 13:57:03.004154 LP4Y_EN = 0x0
5080 13:57:03.004341 WORK_FSP = 0x0
5081 13:57:03.007580 WL = 0x3
5082 13:57:03.007780 RL = 0x3
5083 13:57:03.010657 BL = 0x2
5084 13:57:03.010854 RPST = 0x0
5085 13:57:03.013823 RD_PRE = 0x0
5086 13:57:03.014003 WR_PRE = 0x1
5087 13:57:03.017228 WR_PST = 0x0
5088 13:57:03.017443 DBI_WR = 0x0
5089 13:57:03.020761 DBI_RD = 0x0
5090 13:57:03.020950 OTF = 0x1
5091 13:57:03.023738 ===================================
5092 13:57:03.027664 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5093 13:57:03.034017 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5094 13:57:03.037236 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5095 13:57:03.040795 ===================================
5096 13:57:03.043954 LPDDR4 DRAM CONFIGURATION
5097 13:57:03.047425 ===================================
5098 13:57:03.047908 EX_ROW_EN[0] = 0x10
5099 13:57:03.051152 EX_ROW_EN[1] = 0x0
5100 13:57:03.051664 LP4Y_EN = 0x0
5101 13:57:03.054178 WORK_FSP = 0x0
5102 13:57:03.054597 WL = 0x3
5103 13:57:03.057311 RL = 0x3
5104 13:57:03.060775 BL = 0x2
5105 13:57:03.061290 RPST = 0x0
5106 13:57:03.064219 RD_PRE = 0x0
5107 13:57:03.064731 WR_PRE = 0x1
5108 13:57:03.067297 WR_PST = 0x0
5109 13:57:03.067714 DBI_WR = 0x0
5110 13:57:03.070612 DBI_RD = 0x0
5111 13:57:03.071026 OTF = 0x1
5112 13:57:03.073900 ===================================
5113 13:57:03.080424 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5114 13:57:03.084624 nWR fixed to 30
5115 13:57:03.087746 [ModeRegInit_LP4] CH0 RK0
5116 13:57:03.088163 [ModeRegInit_LP4] CH0 RK1
5117 13:57:03.091390 [ModeRegInit_LP4] CH1 RK0
5118 13:57:03.094568 [ModeRegInit_LP4] CH1 RK1
5119 13:57:03.095075 match AC timing 9
5120 13:57:03.100832 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5121 13:57:03.104220 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5122 13:57:03.107426 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5123 13:57:03.114093 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5124 13:57:03.117295 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5125 13:57:03.117888 ==
5126 13:57:03.120660 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 13:57:03.124122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 13:57:03.124542 ==
5129 13:57:03.130401 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5130 13:57:03.137283 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5131 13:57:03.140436 [CA 0] Center 38 (8~69) winsize 62
5132 13:57:03.143939 [CA 1] Center 38 (7~69) winsize 63
5133 13:57:03.147293 [CA 2] Center 35 (5~65) winsize 61
5134 13:57:03.150559 [CA 3] Center 35 (5~65) winsize 61
5135 13:57:03.153570 [CA 4] Center 34 (4~64) winsize 61
5136 13:57:03.157297 [CA 5] Center 33 (3~64) winsize 62
5137 13:57:03.157801
5138 13:57:03.160561 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5139 13:57:03.160981
5140 13:57:03.163797 [CATrainingPosCal] consider 1 rank data
5141 13:57:03.167245 u2DelayCellTimex100 = 270/100 ps
5142 13:57:03.170485 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5143 13:57:03.173748 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5144 13:57:03.176738 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5145 13:57:03.180218 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5146 13:57:03.187107 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5147 13:57:03.190098 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5148 13:57:03.190517
5149 13:57:03.193872 CA PerBit enable=1, Macro0, CA PI delay=33
5150 13:57:03.194383
5151 13:57:03.196922 [CBTSetCACLKResult] CA Dly = 33
5152 13:57:03.197339 CS Dly: 6 (0~37)
5153 13:57:03.197769 ==
5154 13:57:03.200235 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 13:57:03.206787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 13:57:03.207336 ==
5157 13:57:03.210500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5158 13:57:03.216688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5159 13:57:03.219985 [CA 0] Center 38 (8~69) winsize 62
5160 13:57:03.223497 [CA 1] Center 38 (8~69) winsize 62
5161 13:57:03.226786 [CA 2] Center 35 (5~66) winsize 62
5162 13:57:03.229906 [CA 3] Center 35 (5~65) winsize 61
5163 13:57:03.233120 [CA 4] Center 34 (4~64) winsize 61
5164 13:57:03.236444 [CA 5] Center 33 (3~64) winsize 62
5165 13:57:03.236865
5166 13:57:03.239797 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5167 13:57:03.240219
5168 13:57:03.243186 [CATrainingPosCal] consider 2 rank data
5169 13:57:03.246434 u2DelayCellTimex100 = 270/100 ps
5170 13:57:03.249986 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5171 13:57:03.253016 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5172 13:57:03.260055 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5173 13:57:03.263090 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5174 13:57:03.266255 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5175 13:57:03.269617 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5176 13:57:03.270069
5177 13:57:03.273219 CA PerBit enable=1, Macro0, CA PI delay=33
5178 13:57:03.273677
5179 13:57:03.276265 [CBTSetCACLKResult] CA Dly = 33
5180 13:57:03.276677 CS Dly: 7 (0~39)
5181 13:57:03.277034
5182 13:57:03.279750 ----->DramcWriteLeveling(PI) begin...
5183 13:57:03.282934 ==
5184 13:57:03.286279 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 13:57:03.289722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 13:57:03.290145 ==
5187 13:57:03.293266 Write leveling (Byte 0): 34 => 34
5188 13:57:03.296694 Write leveling (Byte 1): 31 => 31
5189 13:57:03.299724 DramcWriteLeveling(PI) end<-----
5190 13:57:03.300235
5191 13:57:03.300576 ==
5192 13:57:03.303129 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 13:57:03.306274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 13:57:03.306697 ==
5195 13:57:03.309445 [Gating] SW mode calibration
5196 13:57:03.316235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5197 13:57:03.322987 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5198 13:57:03.326049 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5199 13:57:03.329167 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (0 0)
5200 13:57:03.336470 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 13:57:03.339664 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 13:57:03.342881 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5203 13:57:03.349368 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5204 13:57:03.352718 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5205 13:57:03.355753 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5206 13:57:03.362496 0 15 0 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5207 13:57:03.365844 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5208 13:57:03.368928 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 13:57:03.372253 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 13:57:03.379227 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 13:57:03.382362 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 13:57:03.385756 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5213 13:57:03.392471 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5214 13:57:03.395531 1 0 0 | B1->B0 | 2e2e 3e3d | 0 1 | (0 0) (0 0)
5215 13:57:03.399145 1 0 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5216 13:57:03.405556 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 13:57:03.409091 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 13:57:03.412471 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 13:57:03.418895 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 13:57:03.422207 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 13:57:03.425323 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5222 13:57:03.432149 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5223 13:57:03.435444 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5224 13:57:03.438765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 13:57:03.445206 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 13:57:03.448703 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 13:57:03.452067 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 13:57:03.458481 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 13:57:03.461631 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 13:57:03.465153 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 13:57:03.471934 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 13:57:03.475114 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 13:57:03.478220 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 13:57:03.485171 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 13:57:03.488203 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 13:57:03.491424 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 13:57:03.497565 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5238 13:57:03.500909 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5239 13:57:03.504682 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5240 13:57:03.507849 Total UI for P1: 0, mck2ui 16
5241 13:57:03.511190 best dqsien dly found for B0: ( 1, 2, 30)
5242 13:57:03.517831 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5243 13:57:03.518040 Total UI for P1: 0, mck2ui 16
5244 13:57:03.524183 best dqsien dly found for B1: ( 1, 3, 4)
5245 13:57:03.527524 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5246 13:57:03.530970 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5247 13:57:03.531123
5248 13:57:03.534325 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5249 13:57:03.537784 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5250 13:57:03.540796 [Gating] SW calibration Done
5251 13:57:03.541218 ==
5252 13:57:03.544292 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 13:57:03.547502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 13:57:03.547931 ==
5255 13:57:03.551082 RX Vref Scan: 0
5256 13:57:03.551591
5257 13:57:03.551930 RX Vref 0 -> 0, step: 1
5258 13:57:03.552248
5259 13:57:03.554169 RX Delay -80 -> 252, step: 8
5260 13:57:03.557730 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5261 13:57:03.564149 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5262 13:57:03.567525 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5263 13:57:03.570879 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5264 13:57:03.574791 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5265 13:57:03.577576 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5266 13:57:03.580810 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5267 13:57:03.587424 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5268 13:57:03.590571 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5269 13:57:03.594208 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5270 13:57:03.597243 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5271 13:57:03.600951 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5272 13:57:03.607324 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5273 13:57:03.610937 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5274 13:57:03.614210 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5275 13:57:03.617624 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5276 13:57:03.618236 ==
5277 13:57:03.620697 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 13:57:03.624231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 13:57:03.627267 ==
5280 13:57:03.627681 DQS Delay:
5281 13:57:03.628014 DQS0 = 0, DQS1 = 0
5282 13:57:03.630870 DQM Delay:
5283 13:57:03.631383 DQM0 = 94, DQM1 = 83
5284 13:57:03.634340 DQ Delay:
5285 13:57:03.637602 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5286 13:57:03.640769 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5287 13:57:03.641184 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5288 13:57:03.647596 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5289 13:57:03.648094
5290 13:57:03.648420
5291 13:57:03.648721 ==
5292 13:57:03.650462 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 13:57:03.654045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 13:57:03.654456 ==
5295 13:57:03.654788
5296 13:57:03.655090
5297 13:57:03.657114 TX Vref Scan disable
5298 13:57:03.657561 == TX Byte 0 ==
5299 13:57:03.664004 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5300 13:57:03.667083 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5301 13:57:03.667496 == TX Byte 1 ==
5302 13:57:03.673873 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5303 13:57:03.677231 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5304 13:57:03.677683 ==
5305 13:57:03.680673 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 13:57:03.683900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 13:57:03.684317 ==
5308 13:57:03.684647
5309 13:57:03.684950
5310 13:57:03.687210 TX Vref Scan disable
5311 13:57:03.690305 == TX Byte 0 ==
5312 13:57:03.693856 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5313 13:57:03.696842 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5314 13:57:03.700351 == TX Byte 1 ==
5315 13:57:03.703807 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5316 13:57:03.707062 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5317 13:57:03.707591
5318 13:57:03.710357 [DATLAT]
5319 13:57:03.710853 Freq=933, CH0 RK0
5320 13:57:03.711191
5321 13:57:03.713576 DATLAT Default: 0xd
5322 13:57:03.713988 0, 0xFFFF, sum = 0
5323 13:57:03.716887 1, 0xFFFF, sum = 0
5324 13:57:03.717305 2, 0xFFFF, sum = 0
5325 13:57:03.720452 3, 0xFFFF, sum = 0
5326 13:57:03.720995 4, 0xFFFF, sum = 0
5327 13:57:03.723589 5, 0xFFFF, sum = 0
5328 13:57:03.724008 6, 0xFFFF, sum = 0
5329 13:57:03.726853 7, 0xFFFF, sum = 0
5330 13:57:03.730027 8, 0xFFFF, sum = 0
5331 13:57:03.730445 9, 0xFFFF, sum = 0
5332 13:57:03.733632 10, 0x0, sum = 1
5333 13:57:03.734149 11, 0x0, sum = 2
5334 13:57:03.734486 12, 0x0, sum = 3
5335 13:57:03.736699 13, 0x0, sum = 4
5336 13:57:03.737116 best_step = 11
5337 13:57:03.737446
5338 13:57:03.737809 ==
5339 13:57:03.740189 Dram Type= 6, Freq= 0, CH_0, rank 0
5340 13:57:03.746818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 13:57:03.747319 ==
5342 13:57:03.747662 RX Vref Scan: 1
5343 13:57:03.747983
5344 13:57:03.749914 RX Vref 0 -> 0, step: 1
5345 13:57:03.750335
5346 13:57:03.753390 RX Delay -69 -> 252, step: 4
5347 13:57:03.753853
5348 13:57:03.756736 Set Vref, RX VrefLevel [Byte0]: 60
5349 13:57:03.760132 [Byte1]: 47
5350 13:57:03.760549
5351 13:57:03.763684 Final RX Vref Byte 0 = 60 to rank0
5352 13:57:03.766555 Final RX Vref Byte 1 = 47 to rank0
5353 13:57:03.770005 Final RX Vref Byte 0 = 60 to rank1
5354 13:57:03.773451 Final RX Vref Byte 1 = 47 to rank1==
5355 13:57:03.776943 Dram Type= 6, Freq= 0, CH_0, rank 0
5356 13:57:03.779996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 13:57:03.780534 ==
5358 13:57:03.783393 DQS Delay:
5359 13:57:03.783811 DQS0 = 0, DQS1 = 0
5360 13:57:03.786757 DQM Delay:
5361 13:57:03.787172 DQM0 = 95, DQM1 = 82
5362 13:57:03.787501 DQ Delay:
5363 13:57:03.790165 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =94
5364 13:57:03.793141 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5365 13:57:03.796569 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5366 13:57:03.799845 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5367 13:57:03.800261
5368 13:57:03.800588
5369 13:57:03.809938 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5370 13:57:03.813453 CH0 RK0: MR19=505, MR18=1615
5371 13:57:03.819853 CH0_RK0: MR19=0x505, MR18=0x1615, DQSOSC=414, MR23=63, INC=63, DEC=42
5372 13:57:03.820235
5373 13:57:03.822923 ----->DramcWriteLeveling(PI) begin...
5374 13:57:03.823223 ==
5375 13:57:03.826306 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 13:57:03.829588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 13:57:03.829887 ==
5378 13:57:03.832855 Write leveling (Byte 0): 34 => 34
5379 13:57:03.836253 Write leveling (Byte 1): 32 => 32
5380 13:57:03.839545 DramcWriteLeveling(PI) end<-----
5381 13:57:03.839841
5382 13:57:03.840075 ==
5383 13:57:03.843059 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 13:57:03.846404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 13:57:03.846852 ==
5386 13:57:03.849714 [Gating] SW mode calibration
5387 13:57:03.856756 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5388 13:57:03.863215 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5389 13:57:03.866434 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5390 13:57:03.869307 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 13:57:03.876123 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 13:57:03.879478 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 13:57:03.882825 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 13:57:03.889193 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 13:57:03.892904 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5396 13:57:03.896144 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
5397 13:57:03.902921 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5398 13:57:03.905805 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 13:57:03.909283 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 13:57:03.915689 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 13:57:03.919042 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 13:57:03.922376 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 13:57:03.928783 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 13:57:03.932215 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5405 13:57:03.935922 1 0 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5406 13:57:03.942445 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 13:57:03.945571 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 13:57:03.948788 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 13:57:03.955512 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 13:57:03.958546 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 13:57:03.961883 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 13:57:03.968598 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5413 13:57:03.972176 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5414 13:57:03.975588 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5415 13:57:03.981742 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 13:57:03.985673 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 13:57:03.988604 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 13:57:03.995253 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 13:57:03.998402 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 13:57:04.001468 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 13:57:04.007856 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 13:57:04.011181 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 13:57:04.014807 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 13:57:04.021139 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 13:57:04.024729 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 13:57:04.028026 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 13:57:04.034672 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 13:57:04.037632 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5429 13:57:04.041415 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 13:57:04.044502 Total UI for P1: 0, mck2ui 16
5431 13:57:04.048079 best dqsien dly found for B0: ( 1, 2, 28)
5432 13:57:04.051371 Total UI for P1: 0, mck2ui 16
5433 13:57:04.054456 best dqsien dly found for B1: ( 1, 2, 30)
5434 13:57:04.057632 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5435 13:57:04.061171 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5436 13:57:04.061633
5437 13:57:04.064392 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5438 13:57:04.070940 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5439 13:57:04.071360 [Gating] SW calibration Done
5440 13:57:04.074259 ==
5441 13:57:04.074680 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 13:57:04.080854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 13:57:04.081392 ==
5444 13:57:04.081803 RX Vref Scan: 0
5445 13:57:04.082129
5446 13:57:04.084236 RX Vref 0 -> 0, step: 1
5447 13:57:04.084654
5448 13:57:04.087746 RX Delay -80 -> 252, step: 8
5449 13:57:04.091155 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5450 13:57:04.093964 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5451 13:57:04.097979 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5452 13:57:04.104169 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5453 13:57:04.107617 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5454 13:57:04.111119 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5455 13:57:04.114287 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5456 13:57:04.117290 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5457 13:57:04.123845 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5458 13:57:04.127377 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5459 13:57:04.130127 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5460 13:57:04.133615 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5461 13:57:04.136840 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5462 13:57:04.143475 iDelay=208, Bit 13, Center 87 (-8 ~ 183) 192
5463 13:57:04.146776 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5464 13:57:04.150196 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5465 13:57:04.150374 ==
5466 13:57:04.153699 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 13:57:04.157142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 13:57:04.157340 ==
5469 13:57:04.160283 DQS Delay:
5470 13:57:04.160498 DQS0 = 0, DQS1 = 0
5471 13:57:04.163558 DQM Delay:
5472 13:57:04.163813 DQM0 = 92, DQM1 = 80
5473 13:57:04.163951 DQ Delay:
5474 13:57:04.166586 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5475 13:57:04.169959 DQ4 =91, DQ5 =79, DQ6 =107, DQ7 =107
5476 13:57:04.173351 DQ8 =71, DQ9 =63, DQ10 =83, DQ11 =75
5477 13:57:04.176664 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5478 13:57:04.176866
5479 13:57:04.177025
5480 13:57:04.179976 ==
5481 13:57:04.180218 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 13:57:04.186694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 13:57:04.186994 ==
5484 13:57:04.187235
5485 13:57:04.187456
5486 13:57:04.190212 TX Vref Scan disable
5487 13:57:04.190602 == TX Byte 0 ==
5488 13:57:04.193444 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5489 13:57:04.200417 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5490 13:57:04.200981 == TX Byte 1 ==
5491 13:57:04.203371 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5492 13:57:04.210186 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5493 13:57:04.210895 ==
5494 13:57:04.213333 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 13:57:04.216771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 13:57:04.217272 ==
5497 13:57:04.217771
5498 13:57:04.218095
5499 13:57:04.220154 TX Vref Scan disable
5500 13:57:04.223095 == TX Byte 0 ==
5501 13:57:04.226776 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5502 13:57:04.229925 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5503 13:57:04.233239 == TX Byte 1 ==
5504 13:57:04.236979 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5505 13:57:04.240358 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5506 13:57:04.240873
5507 13:57:04.243383 [DATLAT]
5508 13:57:04.244093 Freq=933, CH0 RK1
5509 13:57:04.244670
5510 13:57:04.246630 DATLAT Default: 0xb
5511 13:57:04.247063 0, 0xFFFF, sum = 0
5512 13:57:04.249582 1, 0xFFFF, sum = 0
5513 13:57:04.249994 2, 0xFFFF, sum = 0
5514 13:57:04.253180 3, 0xFFFF, sum = 0
5515 13:57:04.253647 4, 0xFFFF, sum = 0
5516 13:57:04.256611 5, 0xFFFF, sum = 0
5517 13:57:04.257038 6, 0xFFFF, sum = 0
5518 13:57:04.259774 7, 0xFFFF, sum = 0
5519 13:57:04.260197 8, 0xFFFF, sum = 0
5520 13:57:04.263198 9, 0xFFFF, sum = 0
5521 13:57:04.263622 10, 0x0, sum = 1
5522 13:57:04.266262 11, 0x0, sum = 2
5523 13:57:04.266690 12, 0x0, sum = 3
5524 13:57:04.270029 13, 0x0, sum = 4
5525 13:57:04.270455 best_step = 11
5526 13:57:04.270792
5527 13:57:04.271101 ==
5528 13:57:04.272863 Dram Type= 6, Freq= 0, CH_0, rank 1
5529 13:57:04.276338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 13:57:04.279758 ==
5531 13:57:04.280193 RX Vref Scan: 0
5532 13:57:04.280527
5533 13:57:04.283416 RX Vref 0 -> 0, step: 1
5534 13:57:04.283934
5535 13:57:04.286448 RX Delay -77 -> 252, step: 4
5536 13:57:04.289462 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5537 13:57:04.293074 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5538 13:57:04.299560 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5539 13:57:04.302697 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5540 13:57:04.306179 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5541 13:57:04.309195 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5542 13:57:04.312836 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5543 13:57:04.319207 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5544 13:57:04.322118 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5545 13:57:04.325927 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5546 13:57:04.329339 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5547 13:57:04.332524 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5548 13:57:04.339716 iDelay=199, Bit 12, Center 88 (-1 ~ 178) 180
5549 13:57:04.342348 iDelay=199, Bit 13, Center 88 (-1 ~ 178) 180
5550 13:57:04.345870 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5551 13:57:04.349608 iDelay=199, Bit 15, Center 88 (-1 ~ 178) 180
5552 13:57:04.350042 ==
5553 13:57:04.352085 Dram Type= 6, Freq= 0, CH_0, rank 1
5554 13:57:04.355777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 13:57:04.359149 ==
5556 13:57:04.359661 DQS Delay:
5557 13:57:04.359996 DQS0 = 0, DQS1 = 0
5558 13:57:04.362288 DQM Delay:
5559 13:57:04.362700 DQM0 = 92, DQM1 = 83
5560 13:57:04.365397 DQ Delay:
5561 13:57:04.368805 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5562 13:57:04.371894 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5563 13:57:04.372311 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5564 13:57:04.378878 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =88
5565 13:57:04.379429
5566 13:57:04.379778
5567 13:57:04.385186 [DQSOSCAuto] RK1, (LSB)MR18= 0x3314, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5568 13:57:04.388714 CH0 RK1: MR19=505, MR18=3314
5569 13:57:04.395215 CH0_RK1: MR19=0x505, MR18=0x3314, DQSOSC=405, MR23=63, INC=66, DEC=44
5570 13:57:04.398415 [RxdqsGatingPostProcess] freq 933
5571 13:57:04.401864 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5572 13:57:04.405444 best DQS0 dly(2T, 0.5T) = (0, 10)
5573 13:57:04.408883 best DQS1 dly(2T, 0.5T) = (0, 11)
5574 13:57:04.412032 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5575 13:57:04.415036 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5576 13:57:04.418321 best DQS0 dly(2T, 0.5T) = (0, 10)
5577 13:57:04.421668 best DQS1 dly(2T, 0.5T) = (0, 10)
5578 13:57:04.425040 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5579 13:57:04.428418 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5580 13:57:04.431778 Pre-setting of DQS Precalculation
5581 13:57:04.435053 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5582 13:57:04.435470 ==
5583 13:57:04.438223 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 13:57:04.444741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 13:57:04.445157 ==
5586 13:57:04.448267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5587 13:57:04.454827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5588 13:57:04.457867 [CA 0] Center 37 (7~67) winsize 61
5589 13:57:04.461128 [CA 1] Center 37 (7~68) winsize 62
5590 13:57:04.464576 [CA 2] Center 34 (5~64) winsize 60
5591 13:57:04.467773 [CA 3] Center 34 (4~64) winsize 61
5592 13:57:04.471234 [CA 4] Center 34 (5~64) winsize 60
5593 13:57:04.474277 [CA 5] Center 34 (4~64) winsize 61
5594 13:57:04.474695
5595 13:57:04.477855 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5596 13:57:04.478273
5597 13:57:04.481304 [CATrainingPosCal] consider 1 rank data
5598 13:57:04.484623 u2DelayCellTimex100 = 270/100 ps
5599 13:57:04.487873 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5600 13:57:04.494398 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5601 13:57:04.498000 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5602 13:57:04.501189 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5603 13:57:04.504523 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5604 13:57:04.507749 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5605 13:57:04.508264
5606 13:57:04.511415 CA PerBit enable=1, Macro0, CA PI delay=34
5607 13:57:04.511934
5608 13:57:04.514185 [CBTSetCACLKResult] CA Dly = 34
5609 13:57:04.514604 CS Dly: 6 (0~37)
5610 13:57:04.517567 ==
5611 13:57:04.520695 Dram Type= 6, Freq= 0, CH_1, rank 1
5612 13:57:04.523977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 13:57:04.524398 ==
5614 13:57:04.527376 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5615 13:57:04.533964 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5616 13:57:04.538112 [CA 0] Center 38 (8~68) winsize 61
5617 13:57:04.541608 [CA 1] Center 37 (7~68) winsize 62
5618 13:57:04.544526 [CA 2] Center 35 (5~65) winsize 61
5619 13:57:04.548270 [CA 3] Center 34 (4~64) winsize 61
5620 13:57:04.551146 [CA 4] Center 35 (5~65) winsize 61
5621 13:57:04.554462 [CA 5] Center 33 (3~64) winsize 62
5622 13:57:04.554969
5623 13:57:04.557849 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5624 13:57:04.558340
5625 13:57:04.561214 [CATrainingPosCal] consider 2 rank data
5626 13:57:04.564612 u2DelayCellTimex100 = 270/100 ps
5627 13:57:04.567933 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5628 13:57:04.574520 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5629 13:57:04.577800 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5630 13:57:04.581389 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5631 13:57:04.584854 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5632 13:57:04.587879 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5633 13:57:04.588386
5634 13:57:04.591389 CA PerBit enable=1, Macro0, CA PI delay=34
5635 13:57:04.591974
5636 13:57:04.594211 [CBTSetCACLKResult] CA Dly = 34
5637 13:57:04.594658 CS Dly: 7 (0~39)
5638 13:57:04.597768
5639 13:57:04.598193 ----->DramcWriteLeveling(PI) begin...
5640 13:57:04.601186 ==
5641 13:57:04.604638 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 13:57:04.607660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 13:57:04.608179 ==
5644 13:57:04.611376 Write leveling (Byte 0): 26 => 26
5645 13:57:04.614564 Write leveling (Byte 1): 28 => 28
5646 13:57:04.617881 DramcWriteLeveling(PI) end<-----
5647 13:57:04.618429
5648 13:57:04.618771 ==
5649 13:57:04.620838 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 13:57:04.624520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 13:57:04.625036 ==
5652 13:57:04.627711 [Gating] SW mode calibration
5653 13:57:04.634510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5654 13:57:04.640895 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5655 13:57:04.644371 0 14 0 | B1->B0 | 3131 3232 | 1 1 | (1 1) (1 1)
5656 13:57:04.647745 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5657 13:57:04.654325 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 13:57:04.657515 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 13:57:04.660856 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 13:57:04.667139 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 13:57:04.670457 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 13:57:04.673844 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (0 1)
5663 13:57:04.680324 0 15 0 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
5664 13:57:04.683848 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 13:57:04.687044 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 13:57:04.693526 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 13:57:04.697040 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 13:57:04.700090 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 13:57:04.707066 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 13:57:04.710331 0 15 28 | B1->B0 | 2f2f 3434 | 0 0 | (1 1) (0 0)
5671 13:57:04.713224 1 0 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
5672 13:57:04.719824 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 13:57:04.723110 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 13:57:04.726351 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 13:57:04.733212 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 13:57:04.736396 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 13:57:04.740038 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 13:57:04.746796 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5679 13:57:04.749554 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 13:57:04.752977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 13:57:04.759711 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 13:57:04.763173 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 13:57:04.766136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 13:57:04.772877 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 13:57:04.776267 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 13:57:04.779423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 13:57:04.785773 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 13:57:04.789472 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 13:57:04.792583 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 13:57:04.798973 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 13:57:04.802728 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 13:57:04.805647 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 13:57:04.812750 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5694 13:57:04.815882 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5695 13:57:04.819336 Total UI for P1: 0, mck2ui 16
5696 13:57:04.822162 best dqsien dly found for B1: ( 1, 2, 24)
5697 13:57:04.825719 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5698 13:57:04.828831 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5699 13:57:04.832452 Total UI for P1: 0, mck2ui 16
5700 13:57:04.835791 best dqsien dly found for B0: ( 1, 2, 28)
5701 13:57:04.839232 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5702 13:57:04.845800 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5703 13:57:04.846318
5704 13:57:04.849042 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5705 13:57:04.852220 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5706 13:57:04.855790 [Gating] SW calibration Done
5707 13:57:04.856314 ==
5708 13:57:04.858711 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 13:57:04.862067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 13:57:04.862490 ==
5711 13:57:04.865123 RX Vref Scan: 0
5712 13:57:04.865587
5713 13:57:04.865946 RX Vref 0 -> 0, step: 1
5714 13:57:04.866266
5715 13:57:04.868661 RX Delay -80 -> 252, step: 8
5716 13:57:04.872361 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5717 13:57:04.875125 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5718 13:57:04.881899 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5719 13:57:04.885194 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5720 13:57:04.888514 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5721 13:57:04.891871 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5722 13:57:04.895167 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5723 13:57:04.901936 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5724 13:57:04.904743 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5725 13:57:04.908471 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5726 13:57:04.912122 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5727 13:57:04.914803 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5728 13:57:04.918426 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5729 13:57:04.925038 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5730 13:57:04.928396 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5731 13:57:04.931774 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5732 13:57:04.932323 ==
5733 13:57:04.934844 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 13:57:04.938249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 13:57:04.938787 ==
5736 13:57:04.941896 DQS Delay:
5737 13:57:04.942409 DQS0 = 0, DQS1 = 0
5738 13:57:04.945131 DQM Delay:
5739 13:57:04.945685 DQM0 = 94, DQM1 = 87
5740 13:57:04.946027 DQ Delay:
5741 13:57:04.948220 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5742 13:57:04.951591 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5743 13:57:04.954766 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =87
5744 13:57:04.958310 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5745 13:57:04.958731
5746 13:57:04.961547
5747 13:57:04.962075 ==
5748 13:57:04.964938 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 13:57:04.968176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 13:57:04.968695 ==
5751 13:57:04.969039
5752 13:57:04.969350
5753 13:57:04.971416 TX Vref Scan disable
5754 13:57:04.971837 == TX Byte 0 ==
5755 13:57:04.978062 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5756 13:57:04.981032 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5757 13:57:04.981449 == TX Byte 1 ==
5758 13:57:04.988170 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5759 13:57:04.990770 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5760 13:57:04.991191 ==
5761 13:57:04.994241 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 13:57:04.997698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 13:57:04.998123 ==
5764 13:57:04.998460
5765 13:57:04.998770
5766 13:57:05.000771 TX Vref Scan disable
5767 13:57:05.004275 == TX Byte 0 ==
5768 13:57:05.008028 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5769 13:57:05.011433 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5770 13:57:05.014159 == TX Byte 1 ==
5771 13:57:05.017756 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5772 13:57:05.021241 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5773 13:57:05.021808
5774 13:57:05.024220 [DATLAT]
5775 13:57:05.024681 Freq=933, CH1 RK0
5776 13:57:05.025031
5777 13:57:05.027337 DATLAT Default: 0xd
5778 13:57:05.027754 0, 0xFFFF, sum = 0
5779 13:57:05.030671 1, 0xFFFF, sum = 0
5780 13:57:05.031229 2, 0xFFFF, sum = 0
5781 13:57:05.033998 3, 0xFFFF, sum = 0
5782 13:57:05.034426 4, 0xFFFF, sum = 0
5783 13:57:05.037441 5, 0xFFFF, sum = 0
5784 13:57:05.037909 6, 0xFFFF, sum = 0
5785 13:57:05.041082 7, 0xFFFF, sum = 0
5786 13:57:05.041654 8, 0xFFFF, sum = 0
5787 13:57:05.044093 9, 0xFFFF, sum = 0
5788 13:57:05.044516 10, 0x0, sum = 1
5789 13:57:05.047422 11, 0x0, sum = 2
5790 13:57:05.047846 12, 0x0, sum = 3
5791 13:57:05.050977 13, 0x0, sum = 4
5792 13:57:05.051497 best_step = 11
5793 13:57:05.051837
5794 13:57:05.052152 ==
5795 13:57:05.053950 Dram Type= 6, Freq= 0, CH_1, rank 0
5796 13:57:05.060970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 13:57:05.061582 ==
5798 13:57:05.061946 RX Vref Scan: 1
5799 13:57:05.062270
5800 13:57:05.064291 RX Vref 0 -> 0, step: 1
5801 13:57:05.064794
5802 13:57:05.067983 RX Delay -69 -> 252, step: 4
5803 13:57:05.068497
5804 13:57:05.070642 Set Vref, RX VrefLevel [Byte0]: 56
5805 13:57:05.073968 [Byte1]: 55
5806 13:57:05.074380
5807 13:57:05.077302 Final RX Vref Byte 0 = 56 to rank0
5808 13:57:05.080582 Final RX Vref Byte 1 = 55 to rank0
5809 13:57:05.084062 Final RX Vref Byte 0 = 56 to rank1
5810 13:57:05.087398 Final RX Vref Byte 1 = 55 to rank1==
5811 13:57:05.090587 Dram Type= 6, Freq= 0, CH_1, rank 0
5812 13:57:05.093591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 13:57:05.094013 ==
5814 13:57:05.097131 DQS Delay:
5815 13:57:05.097578 DQS0 = 0, DQS1 = 0
5816 13:57:05.100832 DQM Delay:
5817 13:57:05.101341 DQM0 = 96, DQM1 = 88
5818 13:57:05.101716 DQ Delay:
5819 13:57:05.103939 DQ0 =102, DQ1 =94, DQ2 =84, DQ3 =94
5820 13:57:05.107360 DQ4 =94, DQ5 =104, DQ6 =108, DQ7 =94
5821 13:57:05.110621 DQ8 =76, DQ9 =80, DQ10 =86, DQ11 =80
5822 13:57:05.114207 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =94
5823 13:57:05.114718
5824 13:57:05.115051
5825 13:57:05.123563 [DQSOSCAuto] RK0, (LSB)MR18= 0x50e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5826 13:57:05.126926 CH1 RK0: MR19=505, MR18=50E
5827 13:57:05.130235 CH1_RK0: MR19=0x505, MR18=0x50E, DQSOSC=417, MR23=63, INC=62, DEC=41
5828 13:57:05.133629
5829 13:57:05.136784 ----->DramcWriteLeveling(PI) begin...
5830 13:57:05.137205 ==
5831 13:57:05.140318 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 13:57:05.143819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 13:57:05.144365 ==
5834 13:57:05.146822 Write leveling (Byte 0): 28 => 28
5835 13:57:05.150450 Write leveling (Byte 1): 27 => 27
5836 13:57:05.153919 DramcWriteLeveling(PI) end<-----
5837 13:57:05.154672
5838 13:57:05.155038 ==
5839 13:57:05.156516 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 13:57:05.159965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 13:57:05.160382 ==
5842 13:57:05.163781 [Gating] SW mode calibration
5843 13:57:05.169946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5844 13:57:05.176748 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5845 13:57:05.179883 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 13:57:05.183164 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5847 13:57:05.190128 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 13:57:05.193353 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 13:57:05.196478 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5850 13:57:05.203221 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5851 13:57:05.206676 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5852 13:57:05.209996 0 14 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5853 13:57:05.216727 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 13:57:05.219910 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 13:57:05.223290 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 13:57:05.229824 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 13:57:05.233151 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5858 13:57:05.236523 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 13:57:05.239676 0 15 24 | B1->B0 | 2828 3636 | 0 0 | (0 0) (0 0)
5860 13:57:05.246449 0 15 28 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
5861 13:57:05.250032 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 13:57:05.255892 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 13:57:05.259346 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 13:57:05.262727 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 13:57:05.266214 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 13:57:05.272585 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 13:57:05.275995 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5868 13:57:05.279773 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 13:57:05.286040 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 13:57:05.289054 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 13:57:05.292535 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 13:57:05.298866 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 13:57:05.302147 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 13:57:05.305643 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 13:57:05.312036 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 13:57:05.315591 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 13:57:05.319120 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 13:57:05.325371 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 13:57:05.328703 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 13:57:05.332158 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 13:57:05.338967 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 13:57:05.342425 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5883 13:57:05.345402 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5884 13:57:05.352568 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5885 13:57:05.355260 Total UI for P1: 0, mck2ui 16
5886 13:57:05.358765 best dqsien dly found for B0: ( 1, 2, 22)
5887 13:57:05.362032 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5888 13:57:05.365663 Total UI for P1: 0, mck2ui 16
5889 13:57:05.368842 best dqsien dly found for B1: ( 1, 2, 28)
5890 13:57:05.372108 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5891 13:57:05.375173 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5892 13:57:05.375655
5893 13:57:05.378581 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5894 13:57:05.381961 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5895 13:57:05.385631 [Gating] SW calibration Done
5896 13:57:05.386142 ==
5897 13:57:05.388621 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 13:57:05.395241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 13:57:05.395659 ==
5900 13:57:05.395992 RX Vref Scan: 0
5901 13:57:05.396302
5902 13:57:05.398858 RX Vref 0 -> 0, step: 1
5903 13:57:05.399366
5904 13:57:05.402031 RX Delay -80 -> 252, step: 8
5905 13:57:05.405424 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5906 13:57:05.409071 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5907 13:57:05.412121 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5908 13:57:05.415140 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5909 13:57:05.421802 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5910 13:57:05.425181 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5911 13:57:05.428334 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5912 13:57:05.431607 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5913 13:57:05.435147 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5914 13:57:05.441839 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5915 13:57:05.444850 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5916 13:57:05.448329 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5917 13:57:05.451663 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5918 13:57:05.454871 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5919 13:57:05.461390 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5920 13:57:05.464854 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5921 13:57:05.465364 ==
5922 13:57:05.468601 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 13:57:05.471676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 13:57:05.472111 ==
5925 13:57:05.472443 DQS Delay:
5926 13:57:05.474582 DQS0 = 0, DQS1 = 0
5927 13:57:05.475000 DQM Delay:
5928 13:57:05.478017 DQM0 = 92, DQM1 = 88
5929 13:57:05.478425 DQ Delay:
5930 13:57:05.481517 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =87
5931 13:57:05.484923 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5932 13:57:05.487991 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5933 13:57:05.491605 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5934 13:57:05.492019
5935 13:57:05.492345
5936 13:57:05.492641 ==
5937 13:57:05.494967 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 13:57:05.501595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 13:57:05.502105 ==
5940 13:57:05.502439
5941 13:57:05.502748
5942 13:57:05.503038 TX Vref Scan disable
5943 13:57:05.504291 == TX Byte 0 ==
5944 13:57:05.508021 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5945 13:57:05.514440 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5946 13:57:05.514952 == TX Byte 1 ==
5947 13:57:05.517922 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5948 13:57:05.524486 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5949 13:57:05.524983 ==
5950 13:57:05.527587 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 13:57:05.531202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 13:57:05.531616 ==
5953 13:57:05.531944
5954 13:57:05.532250
5955 13:57:05.534107 TX Vref Scan disable
5956 13:57:05.534517 == TX Byte 0 ==
5957 13:57:05.541105 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5958 13:57:05.544527 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5959 13:57:05.545044 == TX Byte 1 ==
5960 13:57:05.550693 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5961 13:57:05.554184 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5962 13:57:05.554596
5963 13:57:05.554925 [DATLAT]
5964 13:57:05.557370 Freq=933, CH1 RK1
5965 13:57:05.557961
5966 13:57:05.558430 DATLAT Default: 0xb
5967 13:57:05.560691 0, 0xFFFF, sum = 0
5968 13:57:05.561192 1, 0xFFFF, sum = 0
5969 13:57:05.564105 2, 0xFFFF, sum = 0
5970 13:57:05.564520 3, 0xFFFF, sum = 0
5971 13:57:05.567308 4, 0xFFFF, sum = 0
5972 13:57:05.570745 5, 0xFFFF, sum = 0
5973 13:57:05.571165 6, 0xFFFF, sum = 0
5974 13:57:05.573906 7, 0xFFFF, sum = 0
5975 13:57:05.574326 8, 0xFFFF, sum = 0
5976 13:57:05.577283 9, 0xFFFF, sum = 0
5977 13:57:05.577765 10, 0x0, sum = 1
5978 13:57:05.580832 11, 0x0, sum = 2
5979 13:57:05.581252 12, 0x0, sum = 3
5980 13:57:05.581624 13, 0x0, sum = 4
5981 13:57:05.583985 best_step = 11
5982 13:57:05.584396
5983 13:57:05.584726 ==
5984 13:57:05.587355 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 13:57:05.590918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 13:57:05.591334 ==
5987 13:57:05.593979 RX Vref Scan: 0
5988 13:57:05.594392
5989 13:57:05.597242 RX Vref 0 -> 0, step: 1
5990 13:57:05.597700
5991 13:57:05.598035 RX Delay -69 -> 252, step: 4
5992 13:57:05.605416 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5993 13:57:05.608617 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5994 13:57:05.611698 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5995 13:57:05.615218 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5996 13:57:05.618472 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5997 13:57:05.625106 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5998 13:57:05.628708 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5999 13:57:05.631488 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
6000 13:57:05.634974 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
6001 13:57:05.638391 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
6002 13:57:05.641597 iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196
6003 13:57:05.648033 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
6004 13:57:05.651696 iDelay=203, Bit 12, Center 100 (7 ~ 194) 188
6005 13:57:05.654370 iDelay=203, Bit 13, Center 98 (3 ~ 194) 192
6006 13:57:05.657875 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
6007 13:57:05.661271 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
6008 13:57:05.661740 ==
6009 13:57:05.664338 Dram Type= 6, Freq= 0, CH_1, rank 1
6010 13:57:05.670958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6011 13:57:05.671412 ==
6012 13:57:05.671744 DQS Delay:
6013 13:57:05.674180 DQS0 = 0, DQS1 = 0
6014 13:57:05.674597 DQM Delay:
6015 13:57:05.677594 DQM0 = 91, DQM1 = 91
6016 13:57:05.678011 DQ Delay:
6017 13:57:05.680734 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6018 13:57:05.684064 DQ4 =88, DQ5 =100, DQ6 =104, DQ7 =88
6019 13:57:05.687128 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
6020 13:57:05.690493 DQ12 =100, DQ13 =98, DQ14 =98, DQ15 =94
6021 13:57:05.690717
6022 13:57:05.690862
6023 13:57:05.696855 [DQSOSCAuto] RK1, (LSB)MR18= 0xf22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
6024 13:57:05.700362 CH1 RK1: MR19=505, MR18=F22
6025 13:57:05.706539 CH1_RK1: MR19=0x505, MR18=0xF22, DQSOSC=411, MR23=63, INC=64, DEC=42
6026 13:57:05.709973 [RxdqsGatingPostProcess] freq 933
6027 13:57:05.716727 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6028 13:57:05.720018 best DQS0 dly(2T, 0.5T) = (0, 10)
6029 13:57:05.720142 best DQS1 dly(2T, 0.5T) = (0, 10)
6030 13:57:05.723050 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6031 13:57:05.726464 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6032 13:57:05.729665 best DQS0 dly(2T, 0.5T) = (0, 10)
6033 13:57:05.733180 best DQS1 dly(2T, 0.5T) = (0, 10)
6034 13:57:05.736334 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6035 13:57:05.739984 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6036 13:57:05.743300 Pre-setting of DQS Precalculation
6037 13:57:05.749715 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6038 13:57:05.756336 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6039 13:57:05.762787 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6040 13:57:05.762912
6041 13:57:05.763004
6042 13:57:05.766299 [Calibration Summary] 1866 Mbps
6043 13:57:05.766384 CH 0, Rank 0
6044 13:57:05.769605 SW Impedance : PASS
6045 13:57:05.772771 DUTY Scan : NO K
6046 13:57:05.772857 ZQ Calibration : PASS
6047 13:57:05.776104 Jitter Meter : NO K
6048 13:57:05.779475 CBT Training : PASS
6049 13:57:05.779564 Write leveling : PASS
6050 13:57:05.782627 RX DQS gating : PASS
6051 13:57:05.786198 RX DQ/DQS(RDDQC) : PASS
6052 13:57:05.786287 TX DQ/DQS : PASS
6053 13:57:05.789091 RX DATLAT : PASS
6054 13:57:05.792609 RX DQ/DQS(Engine): PASS
6055 13:57:05.792698 TX OE : NO K
6056 13:57:05.792785 All Pass.
6057 13:57:05.795976
6058 13:57:05.796061 CH 0, Rank 1
6059 13:57:05.799199 SW Impedance : PASS
6060 13:57:05.799284 DUTY Scan : NO K
6061 13:57:05.802410 ZQ Calibration : PASS
6062 13:57:05.802537 Jitter Meter : NO K
6063 13:57:05.805904 CBT Training : PASS
6064 13:57:05.809017 Write leveling : PASS
6065 13:57:05.809112 RX DQS gating : PASS
6066 13:57:05.812335 RX DQ/DQS(RDDQC) : PASS
6067 13:57:05.815863 TX DQ/DQS : PASS
6068 13:57:05.815956 RX DATLAT : PASS
6069 13:57:05.819282 RX DQ/DQS(Engine): PASS
6070 13:57:05.822263 TX OE : NO K
6071 13:57:05.822364 All Pass.
6072 13:57:05.822453
6073 13:57:05.822536 CH 1, Rank 0
6074 13:57:05.825596 SW Impedance : PASS
6075 13:57:05.829053 DUTY Scan : NO K
6076 13:57:05.829179 ZQ Calibration : PASS
6077 13:57:05.832323 Jitter Meter : NO K
6078 13:57:05.835485 CBT Training : PASS
6079 13:57:05.835575 Write leveling : PASS
6080 13:57:05.838814 RX DQS gating : PASS
6081 13:57:05.842059 RX DQ/DQS(RDDQC) : PASS
6082 13:57:05.842149 TX DQ/DQS : PASS
6083 13:57:05.845396 RX DATLAT : PASS
6084 13:57:05.848651 RX DQ/DQS(Engine): PASS
6085 13:57:05.848794 TX OE : NO K
6086 13:57:05.848887 All Pass.
6087 13:57:05.852189
6088 13:57:05.852323 CH 1, Rank 1
6089 13:57:05.855466 SW Impedance : PASS
6090 13:57:05.855555 DUTY Scan : NO K
6091 13:57:05.858581 ZQ Calibration : PASS
6092 13:57:05.858729 Jitter Meter : NO K
6093 13:57:05.862110 CBT Training : PASS
6094 13:57:05.865322 Write leveling : PASS
6095 13:57:05.865453 RX DQS gating : PASS
6096 13:57:05.868733 RX DQ/DQS(RDDQC) : PASS
6097 13:57:05.872060 TX DQ/DQS : PASS
6098 13:57:05.872222 RX DATLAT : PASS
6099 13:57:05.875380 RX DQ/DQS(Engine): PASS
6100 13:57:05.878443 TX OE : NO K
6101 13:57:05.878581 All Pass.
6102 13:57:05.878684
6103 13:57:05.882025 DramC Write-DBI off
6104 13:57:05.882145 PER_BANK_REFRESH: Hybrid Mode
6105 13:57:05.884957 TX_TRACKING: ON
6106 13:57:05.894999 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6107 13:57:05.898083 [FAST_K] Save calibration result to emmc
6108 13:57:05.901441 dramc_set_vcore_voltage set vcore to 650000
6109 13:57:05.901591 Read voltage for 400, 6
6110 13:57:05.905056 Vio18 = 0
6111 13:57:05.905211 Vcore = 650000
6112 13:57:05.905325 Vdram = 0
6113 13:57:05.908105 Vddq = 0
6114 13:57:05.908239 Vmddr = 0
6115 13:57:05.914912 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6116 13:57:05.917987 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6117 13:57:05.921164 MEM_TYPE=3, freq_sel=20
6118 13:57:05.924678 sv_algorithm_assistance_LP4_800
6119 13:57:05.928168 ============ PULL DRAM RESETB DOWN ============
6120 13:57:05.931051 ========== PULL DRAM RESETB DOWN end =========
6121 13:57:05.937779 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6122 13:57:05.940893 ===================================
6123 13:57:05.940984 LPDDR4 DRAM CONFIGURATION
6124 13:57:05.944472 ===================================
6125 13:57:05.947796 EX_ROW_EN[0] = 0x0
6126 13:57:05.950807 EX_ROW_EN[1] = 0x0
6127 13:57:05.950933 LP4Y_EN = 0x0
6128 13:57:05.954295 WORK_FSP = 0x0
6129 13:57:05.954392 WL = 0x2
6130 13:57:05.957793 RL = 0x2
6131 13:57:05.957895 BL = 0x2
6132 13:57:05.961067 RPST = 0x0
6133 13:57:05.961168 RD_PRE = 0x0
6134 13:57:05.964107 WR_PRE = 0x1
6135 13:57:05.964203 WR_PST = 0x0
6136 13:57:05.967658 DBI_WR = 0x0
6137 13:57:05.967782 DBI_RD = 0x0
6138 13:57:05.970756 OTF = 0x1
6139 13:57:05.974107 ===================================
6140 13:57:05.977243 ===================================
6141 13:57:05.977373 ANA top config
6142 13:57:05.980596 ===================================
6143 13:57:05.983857 DLL_ASYNC_EN = 0
6144 13:57:05.987364 ALL_SLAVE_EN = 1
6145 13:57:05.990863 NEW_RANK_MODE = 1
6146 13:57:05.990996 DLL_IDLE_MODE = 1
6147 13:57:05.993693 LP45_APHY_COMB_EN = 1
6148 13:57:05.997396 TX_ODT_DIS = 1
6149 13:57:06.000640 NEW_8X_MODE = 1
6150 13:57:06.004099 ===================================
6151 13:57:06.007186 ===================================
6152 13:57:06.010656 data_rate = 800
6153 13:57:06.010778 CKR = 1
6154 13:57:06.013686 DQ_P2S_RATIO = 4
6155 13:57:06.016825 ===================================
6156 13:57:06.020302 CA_P2S_RATIO = 4
6157 13:57:06.023612 DQ_CA_OPEN = 0
6158 13:57:06.027072 DQ_SEMI_OPEN = 1
6159 13:57:06.030240 CA_SEMI_OPEN = 1
6160 13:57:06.030377 CA_FULL_RATE = 0
6161 13:57:06.033422 DQ_CKDIV4_EN = 0
6162 13:57:06.036983 CA_CKDIV4_EN = 1
6163 13:57:06.040289 CA_PREDIV_EN = 0
6164 13:57:06.043721 PH8_DLY = 0
6165 13:57:06.046926 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6166 13:57:06.047055 DQ_AAMCK_DIV = 0
6167 13:57:06.049926 CA_AAMCK_DIV = 0
6168 13:57:06.053367 CA_ADMCK_DIV = 4
6169 13:57:06.056736 DQ_TRACK_CA_EN = 0
6170 13:57:06.059766 CA_PICK = 800
6171 13:57:06.063159 CA_MCKIO = 400
6172 13:57:06.066610 MCKIO_SEMI = 400
6173 13:57:06.069929 PLL_FREQ = 3016
6174 13:57:06.070106 DQ_UI_PI_RATIO = 32
6175 13:57:06.073262 CA_UI_PI_RATIO = 32
6176 13:57:06.076392 ===================================
6177 13:57:06.079937 ===================================
6178 13:57:06.082975 memory_type:LPDDR4
6179 13:57:06.086416 GP_NUM : 10
6180 13:57:06.086518 SRAM_EN : 1
6181 13:57:06.089837 MD32_EN : 0
6182 13:57:06.093106 ===================================
6183 13:57:06.096228 [ANA_INIT] >>>>>>>>>>>>>>
6184 13:57:06.096324 <<<<<< [CONFIGURE PHASE]: ANA_TX
6185 13:57:06.099524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6186 13:57:06.102744 ===================================
6187 13:57:06.106263 data_rate = 800,PCW = 0X7400
6188 13:57:06.109593 ===================================
6189 13:57:06.112829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6190 13:57:06.119332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6191 13:57:06.129419 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6192 13:57:06.135878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6193 13:57:06.139002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6194 13:57:06.142674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6195 13:57:06.145901 [ANA_INIT] flow start
6196 13:57:06.146025 [ANA_INIT] PLL >>>>>>>>
6197 13:57:06.149056 [ANA_INIT] PLL <<<<<<<<
6198 13:57:06.152348 [ANA_INIT] MIDPI >>>>>>>>
6199 13:57:06.152516 [ANA_INIT] MIDPI <<<<<<<<
6200 13:57:06.155727 [ANA_INIT] DLL >>>>>>>>
6201 13:57:06.159180 [ANA_INIT] flow end
6202 13:57:06.162503 ============ LP4 DIFF to SE enter ============
6203 13:57:06.165616 ============ LP4 DIFF to SE exit ============
6204 13:57:06.168962 [ANA_INIT] <<<<<<<<<<<<<
6205 13:57:06.172168 [Flow] Enable top DCM control >>>>>
6206 13:57:06.175701 [Flow] Enable top DCM control <<<<<
6207 13:57:06.179064 Enable DLL master slave shuffle
6208 13:57:06.182208 ==============================================================
6209 13:57:06.185242 Gating Mode config
6210 13:57:06.191854 ==============================================================
6211 13:57:06.192026 Config description:
6212 13:57:06.201974 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6213 13:57:06.208726 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6214 13:57:06.211952 SELPH_MODE 0: By rank 1: By Phase
6215 13:57:06.218504 ==============================================================
6216 13:57:06.221829 GAT_TRACK_EN = 0
6217 13:57:06.225111 RX_GATING_MODE = 2
6218 13:57:06.228524 RX_GATING_TRACK_MODE = 2
6219 13:57:06.231612 SELPH_MODE = 1
6220 13:57:06.234977 PICG_EARLY_EN = 1
6221 13:57:06.238428 VALID_LAT_VALUE = 1
6222 13:57:06.241825 ==============================================================
6223 13:57:06.244855 Enter into Gating configuration >>>>
6224 13:57:06.248243 Exit from Gating configuration <<<<
6225 13:57:06.251348 Enter into DVFS_PRE_config >>>>>
6226 13:57:06.264666 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6227 13:57:06.267860 Exit from DVFS_PRE_config <<<<<
6228 13:57:06.271142 Enter into PICG configuration >>>>
6229 13:57:06.271343 Exit from PICG configuration <<<<
6230 13:57:06.274600 [RX_INPUT] configuration >>>>>
6231 13:57:06.277705 [RX_INPUT] configuration <<<<<
6232 13:57:06.284655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6233 13:57:06.287585 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6234 13:57:06.294670 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6235 13:57:06.301212 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6236 13:57:06.307702 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6237 13:57:06.314554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6238 13:57:06.317606 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6239 13:57:06.321027 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6240 13:57:06.327565 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6241 13:57:06.330856 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6242 13:57:06.334075 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6243 13:57:06.337415 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 13:57:06.340567 ===================================
6245 13:57:06.344186 LPDDR4 DRAM CONFIGURATION
6246 13:57:06.347275 ===================================
6247 13:57:06.350673 EX_ROW_EN[0] = 0x0
6248 13:57:06.350822 EX_ROW_EN[1] = 0x0
6249 13:57:06.353845 LP4Y_EN = 0x0
6250 13:57:06.353976 WORK_FSP = 0x0
6251 13:57:06.357340 WL = 0x2
6252 13:57:06.357491 RL = 0x2
6253 13:57:06.360648 BL = 0x2
6254 13:57:06.360784 RPST = 0x0
6255 13:57:06.363749 RD_PRE = 0x0
6256 13:57:06.363871 WR_PRE = 0x1
6257 13:57:06.367245 WR_PST = 0x0
6258 13:57:06.367402 DBI_WR = 0x0
6259 13:57:06.370478 DBI_RD = 0x0
6260 13:57:06.373811 OTF = 0x1
6261 13:57:06.373979 ===================================
6262 13:57:06.380514 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6263 13:57:06.384020 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6264 13:57:06.387070 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6265 13:57:06.390492 ===================================
6266 13:57:06.394035 LPDDR4 DRAM CONFIGURATION
6267 13:57:06.397011 ===================================
6268 13:57:06.400690 EX_ROW_EN[0] = 0x10
6269 13:57:06.400822 EX_ROW_EN[1] = 0x0
6270 13:57:06.403967 LP4Y_EN = 0x0
6271 13:57:06.404088 WORK_FSP = 0x0
6272 13:57:06.407161 WL = 0x2
6273 13:57:06.407277 RL = 0x2
6274 13:57:06.410493 BL = 0x2
6275 13:57:06.410610 RPST = 0x0
6276 13:57:06.413895 RD_PRE = 0x0
6277 13:57:06.414014 WR_PRE = 0x1
6278 13:57:06.416863 WR_PST = 0x0
6279 13:57:06.416974 DBI_WR = 0x0
6280 13:57:06.420403 DBI_RD = 0x0
6281 13:57:06.420515 OTF = 0x1
6282 13:57:06.423809 ===================================
6283 13:57:06.430306 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6284 13:57:06.434922 nWR fixed to 30
6285 13:57:06.438354 [ModeRegInit_LP4] CH0 RK0
6286 13:57:06.438543 [ModeRegInit_LP4] CH0 RK1
6287 13:57:06.441792 [ModeRegInit_LP4] CH1 RK0
6288 13:57:06.444939 [ModeRegInit_LP4] CH1 RK1
6289 13:57:06.445108 match AC timing 19
6290 13:57:06.451445 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6291 13:57:06.455110 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6292 13:57:06.458389 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6293 13:57:06.464743 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6294 13:57:06.468081 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6295 13:57:06.468219 ==
6296 13:57:06.471556 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 13:57:06.474851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 13:57:06.475000 ==
6299 13:57:06.481490 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6300 13:57:06.488284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6301 13:57:06.491329 [CA 0] Center 36 (8~64) winsize 57
6302 13:57:06.494739 [CA 1] Center 36 (8~64) winsize 57
6303 13:57:06.498322 [CA 2] Center 36 (8~64) winsize 57
6304 13:57:06.498448 [CA 3] Center 36 (8~64) winsize 57
6305 13:57:06.501339 [CA 4] Center 36 (8~64) winsize 57
6306 13:57:06.504676 [CA 5] Center 36 (8~64) winsize 57
6307 13:57:06.504798
6308 13:57:06.511532 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6309 13:57:06.511677
6310 13:57:06.514936 [CATrainingPosCal] consider 1 rank data
6311 13:57:06.517864 u2DelayCellTimex100 = 270/100 ps
6312 13:57:06.521306 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 13:57:06.524778 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 13:57:06.527784 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 13:57:06.531250 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 13:57:06.534431 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 13:57:06.537792 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 13:57:06.538033
6319 13:57:06.541039 CA PerBit enable=1, Macro0, CA PI delay=36
6320 13:57:06.541202
6321 13:57:06.544598 [CBTSetCACLKResult] CA Dly = 36
6322 13:57:06.547825 CS Dly: 1 (0~32)
6323 13:57:06.547994 ==
6324 13:57:06.551055 Dram Type= 6, Freq= 0, CH_0, rank 1
6325 13:57:06.554336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 13:57:06.554508 ==
6327 13:57:06.561099 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6328 13:57:06.564619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6329 13:57:06.567963 [CA 0] Center 36 (8~64) winsize 57
6330 13:57:06.571037 [CA 1] Center 36 (8~64) winsize 57
6331 13:57:06.574786 [CA 2] Center 36 (8~64) winsize 57
6332 13:57:06.577799 [CA 3] Center 36 (8~64) winsize 57
6333 13:57:06.581330 [CA 4] Center 36 (8~64) winsize 57
6334 13:57:06.584327 [CA 5] Center 36 (8~64) winsize 57
6335 13:57:06.584499
6336 13:57:06.588076 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6337 13:57:06.588248
6338 13:57:06.591041 [CATrainingPosCal] consider 2 rank data
6339 13:57:06.594402 u2DelayCellTimex100 = 270/100 ps
6340 13:57:06.597746 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 13:57:06.601143 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 13:57:06.607558 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 13:57:06.610918 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 13:57:06.614305 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 13:57:06.617704 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 13:57:06.617825
6347 13:57:06.620903 CA PerBit enable=1, Macro0, CA PI delay=36
6348 13:57:06.621017
6349 13:57:06.624357 [CBTSetCACLKResult] CA Dly = 36
6350 13:57:06.624529 CS Dly: 1 (0~32)
6351 13:57:06.624672
6352 13:57:06.627382 ----->DramcWriteLeveling(PI) begin...
6353 13:57:06.630784 ==
6354 13:57:06.634292 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 13:57:06.637295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 13:57:06.637413 ==
6357 13:57:06.640808 Write leveling (Byte 0): 40 => 8
6358 13:57:06.643870 Write leveling (Byte 1): 40 => 8
6359 13:57:06.647502 DramcWriteLeveling(PI) end<-----
6360 13:57:06.647623
6361 13:57:06.647721 ==
6362 13:57:06.650771 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 13:57:06.653822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 13:57:06.653948 ==
6365 13:57:06.657236 [Gating] SW mode calibration
6366 13:57:06.663905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6367 13:57:06.670590 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6368 13:57:06.673802 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6369 13:57:06.677288 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6370 13:57:06.680485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6371 13:57:06.687135 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6372 13:57:06.690310 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 13:57:06.693651 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 13:57:06.700354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6375 13:57:06.703578 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6376 13:57:06.707054 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 13:57:06.709993 Total UI for P1: 0, mck2ui 16
6378 13:57:06.713596 best dqsien dly found for B0: ( 0, 14, 24)
6379 13:57:06.716719 Total UI for P1: 0, mck2ui 16
6380 13:57:06.719982 best dqsien dly found for B1: ( 0, 14, 24)
6381 13:57:06.723486 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6382 13:57:06.730055 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6383 13:57:06.730212
6384 13:57:06.733359 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6385 13:57:06.736890 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6386 13:57:06.739832 [Gating] SW calibration Done
6387 13:57:06.739946 ==
6388 13:57:06.743279 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 13:57:06.746278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 13:57:06.746387 ==
6391 13:57:06.749724 RX Vref Scan: 0
6392 13:57:06.749837
6393 13:57:06.749936 RX Vref 0 -> 0, step: 1
6394 13:57:06.750031
6395 13:57:06.753262 RX Delay -410 -> 252, step: 16
6396 13:57:06.759639 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6397 13:57:06.763070 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6398 13:57:06.766202 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6399 13:57:06.769343 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6400 13:57:06.776168 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6401 13:57:06.779573 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6402 13:57:06.782665 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6403 13:57:06.786171 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6404 13:57:06.792493 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6405 13:57:06.795959 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6406 13:57:06.799108 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6407 13:57:06.802689 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6408 13:57:06.809246 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6409 13:57:06.812549 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6410 13:57:06.815729 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6411 13:57:06.819158 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6412 13:57:06.822542 ==
6413 13:57:06.825613 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 13:57:06.829181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 13:57:06.829306 ==
6416 13:57:06.829403 DQS Delay:
6417 13:57:06.832187 DQS0 = 59, DQS1 = 59
6418 13:57:06.832302 DQM Delay:
6419 13:57:06.835674 DQM0 = 18, DQM1 = 10
6420 13:57:06.835789 DQ Delay:
6421 13:57:06.839055 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6422 13:57:06.842059 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6423 13:57:06.845662 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6424 13:57:06.848974 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6425 13:57:06.849097
6426 13:57:06.849201
6427 13:57:06.849297 ==
6428 13:57:06.852101 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 13:57:06.855578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 13:57:06.855695 ==
6431 13:57:06.855797
6432 13:57:06.855896
6433 13:57:06.859108 TX Vref Scan disable
6434 13:57:06.859225 == TX Byte 0 ==
6435 13:57:06.865350 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 13:57:06.868706 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 13:57:06.868825 == TX Byte 1 ==
6438 13:57:06.875262 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6439 13:57:06.878654 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6440 13:57:06.878775 ==
6441 13:57:06.881933 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 13:57:06.885277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 13:57:06.885387 ==
6444 13:57:06.885488
6445 13:57:06.885581
6446 13:57:06.888354 TX Vref Scan disable
6447 13:57:06.891700 == TX Byte 0 ==
6448 13:57:06.895202 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6449 13:57:06.898390 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6450 13:57:06.901557 == TX Byte 1 ==
6451 13:57:06.905109 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6452 13:57:06.908370 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6453 13:57:06.908488
6454 13:57:06.908585 [DATLAT]
6455 13:57:06.911652 Freq=400, CH0 RK0
6456 13:57:06.911764
6457 13:57:06.911857 DATLAT Default: 0xf
6458 13:57:06.914966 0, 0xFFFF, sum = 0
6459 13:57:06.915080 1, 0xFFFF, sum = 0
6460 13:57:06.918253 2, 0xFFFF, sum = 0
6461 13:57:06.921618 3, 0xFFFF, sum = 0
6462 13:57:06.921732 4, 0xFFFF, sum = 0
6463 13:57:06.924986 5, 0xFFFF, sum = 0
6464 13:57:06.925107 6, 0xFFFF, sum = 0
6465 13:57:06.928193 7, 0xFFFF, sum = 0
6466 13:57:06.928303 8, 0xFFFF, sum = 0
6467 13:57:06.931904 9, 0xFFFF, sum = 0
6468 13:57:06.932027 10, 0xFFFF, sum = 0
6469 13:57:06.934954 11, 0xFFFF, sum = 0
6470 13:57:06.935069 12, 0xFFFF, sum = 0
6471 13:57:06.938386 13, 0x0, sum = 1
6472 13:57:06.938501 14, 0x0, sum = 2
6473 13:57:06.941609 15, 0x0, sum = 3
6474 13:57:06.941720 16, 0x0, sum = 4
6475 13:57:06.944690 best_step = 14
6476 13:57:06.944801
6477 13:57:06.944897 ==
6478 13:57:06.948161 Dram Type= 6, Freq= 0, CH_0, rank 0
6479 13:57:06.951548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 13:57:06.951663 ==
6481 13:57:06.951759 RX Vref Scan: 1
6482 13:57:06.954602
6483 13:57:06.954711 RX Vref 0 -> 0, step: 1
6484 13:57:06.954808
6485 13:57:06.958033 RX Delay -359 -> 252, step: 8
6486 13:57:06.958143
6487 13:57:06.961637 Set Vref, RX VrefLevel [Byte0]: 60
6488 13:57:06.964804 [Byte1]: 47
6489 13:57:06.969114
6490 13:57:06.969231 Final RX Vref Byte 0 = 60 to rank0
6491 13:57:06.972210 Final RX Vref Byte 1 = 47 to rank0
6492 13:57:06.975461 Final RX Vref Byte 0 = 60 to rank1
6493 13:57:06.978926 Final RX Vref Byte 1 = 47 to rank1==
6494 13:57:06.981999 Dram Type= 6, Freq= 0, CH_0, rank 0
6495 13:57:06.988451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 13:57:06.988581 ==
6497 13:57:06.988680 DQS Delay:
6498 13:57:06.991916 DQS0 = 60, DQS1 = 68
6499 13:57:06.992025 DQM Delay:
6500 13:57:06.992121 DQM0 = 14, DQM1 = 13
6501 13:57:06.995225 DQ Delay:
6502 13:57:06.998447 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6503 13:57:07.001837 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6504 13:57:07.001971 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6505 13:57:07.008610 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6506 13:57:07.008735
6507 13:57:07.008832
6508 13:57:07.015282 [DQSOSCAuto] RK0, (LSB)MR18= 0x8482, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6509 13:57:07.018467 CH0 RK0: MR19=C0C, MR18=8482
6510 13:57:07.025263 CH0_RK0: MR19=0xC0C, MR18=0x8482, DQSOSC=393, MR23=63, INC=382, DEC=254
6511 13:57:07.025398 ==
6512 13:57:07.028177 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 13:57:07.031720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 13:57:07.031850 ==
6515 13:57:07.035186 [Gating] SW mode calibration
6516 13:57:07.041738 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6517 13:57:07.048099 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6518 13:57:07.051591 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6519 13:57:07.054971 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6520 13:57:07.061367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6521 13:57:07.064860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6522 13:57:07.067924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 13:57:07.074837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 13:57:07.077993 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6525 13:57:07.081261 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6526 13:57:07.087977 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 13:57:07.088115 Total UI for P1: 0, mck2ui 16
6528 13:57:07.094323 best dqsien dly found for B0: ( 0, 14, 24)
6529 13:57:07.094441 Total UI for P1: 0, mck2ui 16
6530 13:57:07.100925 best dqsien dly found for B1: ( 0, 14, 24)
6531 13:57:07.104575 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6532 13:57:07.107903 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6533 13:57:07.108020
6534 13:57:07.111299 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6535 13:57:07.114776 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6536 13:57:07.117807 [Gating] SW calibration Done
6537 13:57:07.117932 ==
6538 13:57:07.121214 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 13:57:07.124346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 13:57:07.124466 ==
6541 13:57:07.127779 RX Vref Scan: 0
6542 13:57:07.127889
6543 13:57:07.127984 RX Vref 0 -> 0, step: 1
6544 13:57:07.128080
6545 13:57:07.131220 RX Delay -410 -> 252, step: 16
6546 13:57:07.137819 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6547 13:57:07.140851 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6548 13:57:07.144271 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6549 13:57:07.147521 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6550 13:57:07.154305 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6551 13:57:07.157605 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6552 13:57:07.161027 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6553 13:57:07.164113 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6554 13:57:07.171018 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6555 13:57:07.174053 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6556 13:57:07.177524 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6557 13:57:07.180671 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6558 13:57:07.187466 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6559 13:57:07.190946 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6560 13:57:07.193955 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6561 13:57:07.197341 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6562 13:57:07.200948 ==
6563 13:57:07.201067 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 13:57:07.207466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 13:57:07.207587 ==
6566 13:57:07.207686 DQS Delay:
6567 13:57:07.210673 DQS0 = 59, DQS1 = 59
6568 13:57:07.210786 DQM Delay:
6569 13:57:07.214007 DQM0 = 16, DQM1 = 10
6570 13:57:07.214115 DQ Delay:
6571 13:57:07.217402 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6572 13:57:07.220524 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6573 13:57:07.223984 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6574 13:57:07.227310 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6575 13:57:07.227432
6576 13:57:07.227528
6577 13:57:07.227619 ==
6578 13:57:07.230528 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 13:57:07.233990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 13:57:07.234101 ==
6581 13:57:07.234197
6582 13:57:07.234310
6583 13:57:07.237366 TX Vref Scan disable
6584 13:57:07.237483 == TX Byte 0 ==
6585 13:57:07.243728 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6586 13:57:07.247145 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6587 13:57:07.247264 == TX Byte 1 ==
6588 13:57:07.253942 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6589 13:57:07.257149 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6590 13:57:07.257266 ==
6591 13:57:07.260294 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 13:57:07.263603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 13:57:07.263720 ==
6594 13:57:07.263817
6595 13:57:07.263909
6596 13:57:07.267012 TX Vref Scan disable
6597 13:57:07.267132 == TX Byte 0 ==
6598 13:57:07.273562 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6599 13:57:07.276848 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6600 13:57:07.276966 == TX Byte 1 ==
6601 13:57:07.283371 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6602 13:57:07.286711 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6603 13:57:07.286830
6604 13:57:07.286933 [DATLAT]
6605 13:57:07.290050 Freq=400, CH0 RK1
6606 13:57:07.290164
6607 13:57:07.290265 DATLAT Default: 0xe
6608 13:57:07.293379 0, 0xFFFF, sum = 0
6609 13:57:07.293502 1, 0xFFFF, sum = 0
6610 13:57:07.296483 2, 0xFFFF, sum = 0
6611 13:57:07.296599 3, 0xFFFF, sum = 0
6612 13:57:07.300021 4, 0xFFFF, sum = 0
6613 13:57:07.300137 5, 0xFFFF, sum = 0
6614 13:57:07.303473 6, 0xFFFF, sum = 0
6615 13:57:07.303586 7, 0xFFFF, sum = 0
6616 13:57:07.306567 8, 0xFFFF, sum = 0
6617 13:57:07.310065 9, 0xFFFF, sum = 0
6618 13:57:07.310179 10, 0xFFFF, sum = 0
6619 13:57:07.313160 11, 0xFFFF, sum = 0
6620 13:57:07.313269 12, 0xFFFF, sum = 0
6621 13:57:07.316643 13, 0x0, sum = 1
6622 13:57:07.316757 14, 0x0, sum = 2
6623 13:57:07.319985 15, 0x0, sum = 3
6624 13:57:07.320098 16, 0x0, sum = 4
6625 13:57:07.320196 best_step = 14
6626 13:57:07.320288
6627 13:57:07.323480 ==
6628 13:57:07.326565 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 13:57:07.329693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 13:57:07.329820 ==
6631 13:57:07.329931 RX Vref Scan: 0
6632 13:57:07.330036
6633 13:57:07.333099 RX Vref 0 -> 0, step: 1
6634 13:57:07.333217
6635 13:57:07.336333 RX Delay -359 -> 252, step: 8
6636 13:57:07.343478 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6637 13:57:07.346843 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6638 13:57:07.350357 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6639 13:57:07.356577 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6640 13:57:07.360169 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6641 13:57:07.363625 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6642 13:57:07.366545 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6643 13:57:07.373404 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6644 13:57:07.376536 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6645 13:57:07.380050 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6646 13:57:07.383277 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6647 13:57:07.389763 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6648 13:57:07.393103 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6649 13:57:07.396483 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6650 13:57:07.400023 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6651 13:57:07.406293 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6652 13:57:07.406431 ==
6653 13:57:07.409694 Dram Type= 6, Freq= 0, CH_0, rank 1
6654 13:57:07.413302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 13:57:07.413425 ==
6656 13:57:07.413540 DQS Delay:
6657 13:57:07.416367 DQS0 = 60, DQS1 = 72
6658 13:57:07.416480 DQM Delay:
6659 13:57:07.419732 DQM0 = 11, DQM1 = 16
6660 13:57:07.419847 DQ Delay:
6661 13:57:07.423025 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6662 13:57:07.426356 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6663 13:57:07.429803 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6664 13:57:07.432842 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6665 13:57:07.432964
6666 13:57:07.433068
6667 13:57:07.439580 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6668 13:57:07.442916 CH0 RK1: MR19=C0C, MR18=C87D
6669 13:57:07.449518 CH0_RK1: MR19=0xC0C, MR18=0xC87D, DQSOSC=385, MR23=63, INC=398, DEC=265
6670 13:57:07.452927 [RxdqsGatingPostProcess] freq 400
6671 13:57:07.459636 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6672 13:57:07.462658 best DQS0 dly(2T, 0.5T) = (0, 10)
6673 13:57:07.462823 best DQS1 dly(2T, 0.5T) = (0, 10)
6674 13:57:07.465946 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6675 13:57:07.469299 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6676 13:57:07.472839 best DQS0 dly(2T, 0.5T) = (0, 10)
6677 13:57:07.476218 best DQS1 dly(2T, 0.5T) = (0, 10)
6678 13:57:07.479501 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6679 13:57:07.482573 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6680 13:57:07.486111 Pre-setting of DQS Precalculation
6681 13:57:07.492788 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6682 13:57:07.493018 ==
6683 13:57:07.496142 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 13:57:07.499114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 13:57:07.499213 ==
6686 13:57:07.505534 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6687 13:57:07.509117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6688 13:57:07.512364 [CA 0] Center 36 (8~64) winsize 57
6689 13:57:07.515603 [CA 1] Center 36 (8~64) winsize 57
6690 13:57:07.518889 [CA 2] Center 36 (8~64) winsize 57
6691 13:57:07.522173 [CA 3] Center 36 (8~64) winsize 57
6692 13:57:07.525522 [CA 4] Center 36 (8~64) winsize 57
6693 13:57:07.529168 [CA 5] Center 36 (8~64) winsize 57
6694 13:57:07.529330
6695 13:57:07.532351 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6696 13:57:07.532480
6697 13:57:07.535682 [CATrainingPosCal] consider 1 rank data
6698 13:57:07.538925 u2DelayCellTimex100 = 270/100 ps
6699 13:57:07.542010 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 13:57:07.548989 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 13:57:07.551980 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 13:57:07.555357 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 13:57:07.558631 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 13:57:07.562232 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 13:57:07.562372
6706 13:57:07.565465 CA PerBit enable=1, Macro0, CA PI delay=36
6707 13:57:07.565598
6708 13:57:07.568534 [CBTSetCACLKResult] CA Dly = 36
6709 13:57:07.568651 CS Dly: 1 (0~32)
6710 13:57:07.571840 ==
6711 13:57:07.575079 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 13:57:07.578598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 13:57:07.578717 ==
6714 13:57:07.582030 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6715 13:57:07.588740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6716 13:57:07.591980 [CA 0] Center 36 (8~64) winsize 57
6717 13:57:07.595191 [CA 1] Center 36 (8~64) winsize 57
6718 13:57:07.598654 [CA 2] Center 36 (8~64) winsize 57
6719 13:57:07.601629 [CA 3] Center 36 (8~64) winsize 57
6720 13:57:07.605061 [CA 4] Center 36 (8~64) winsize 57
6721 13:57:07.608396 [CA 5] Center 36 (8~64) winsize 57
6722 13:57:07.608559
6723 13:57:07.611627 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6724 13:57:07.611757
6725 13:57:07.614974 [CATrainingPosCal] consider 2 rank data
6726 13:57:07.618189 u2DelayCellTimex100 = 270/100 ps
6727 13:57:07.621553 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 13:57:07.624834 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 13:57:07.628025 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 13:57:07.634719 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 13:57:07.638005 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 13:57:07.641250 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 13:57:07.641370
6734 13:57:07.644734 CA PerBit enable=1, Macro0, CA PI delay=36
6735 13:57:07.644857
6736 13:57:07.648018 [CBTSetCACLKResult] CA Dly = 36
6737 13:57:07.648139 CS Dly: 1 (0~32)
6738 13:57:07.648234
6739 13:57:07.651420 ----->DramcWriteLeveling(PI) begin...
6740 13:57:07.651535 ==
6741 13:57:07.654739 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 13:57:07.661214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 13:57:07.661353 ==
6744 13:57:07.664781 Write leveling (Byte 0): 40 => 8
6745 13:57:07.667791 Write leveling (Byte 1): 40 => 8
6746 13:57:07.667915 DramcWriteLeveling(PI) end<-----
6747 13:57:07.670877
6748 13:57:07.671010 ==
6749 13:57:07.674242 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 13:57:07.677369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 13:57:07.677497 ==
6752 13:57:07.681054 [Gating] SW mode calibration
6753 13:57:07.687663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6754 13:57:07.690885 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6755 13:57:07.697274 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6756 13:57:07.700629 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6757 13:57:07.703870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6758 13:57:07.710383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6759 13:57:07.713906 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 13:57:07.717173 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 13:57:07.723727 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6762 13:57:07.726979 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6763 13:57:07.730283 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 13:57:07.733583 Total UI for P1: 0, mck2ui 16
6765 13:57:07.736701 best dqsien dly found for B0: ( 0, 14, 24)
6766 13:57:07.740329 Total UI for P1: 0, mck2ui 16
6767 13:57:07.743616 best dqsien dly found for B1: ( 0, 14, 24)
6768 13:57:07.746886 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6769 13:57:07.753472 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6770 13:57:07.753586
6771 13:57:07.756736 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6772 13:57:07.760027 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6773 13:57:07.763471 [Gating] SW calibration Done
6774 13:57:07.763573 ==
6775 13:57:07.766812 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 13:57:07.770030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 13:57:07.770120 ==
6778 13:57:07.773230 RX Vref Scan: 0
6779 13:57:07.773342
6780 13:57:07.773438 RX Vref 0 -> 0, step: 1
6781 13:57:07.773529
6782 13:57:07.776682 RX Delay -410 -> 252, step: 16
6783 13:57:07.782919 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6784 13:57:07.786239 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6785 13:57:07.789782 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6786 13:57:07.793057 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6787 13:57:07.796306 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6788 13:57:07.802907 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6789 13:57:07.806091 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6790 13:57:07.809443 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6791 13:57:07.816064 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6792 13:57:07.819401 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6793 13:57:07.822669 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6794 13:57:07.826227 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6795 13:57:07.832610 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6796 13:57:07.835714 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6797 13:57:07.839368 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6798 13:57:07.842581 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6799 13:57:07.845900 ==
6800 13:57:07.849174 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 13:57:07.852547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 13:57:07.852641 ==
6803 13:57:07.852745 DQS Delay:
6804 13:57:07.855757 DQS0 = 51, DQS1 = 67
6805 13:57:07.855849 DQM Delay:
6806 13:57:07.859046 DQM0 = 13, DQM1 = 18
6807 13:57:07.859131 DQ Delay:
6808 13:57:07.862404 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6809 13:57:07.865786 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6810 13:57:07.868744 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6811 13:57:07.872064 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6812 13:57:07.872152
6813 13:57:07.872220
6814 13:57:07.872282 ==
6815 13:57:07.875499 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 13:57:07.878730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 13:57:07.878819 ==
6818 13:57:07.878886
6819 13:57:07.878947
6820 13:57:07.882078 TX Vref Scan disable
6821 13:57:07.882164 == TX Byte 0 ==
6822 13:57:07.888983 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 13:57:07.892086 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 13:57:07.892179 == TX Byte 1 ==
6825 13:57:07.898393 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 13:57:07.901806 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 13:57:07.901898 ==
6828 13:57:07.905334 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 13:57:07.908426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 13:57:07.908515 ==
6831 13:57:07.908584
6832 13:57:07.908645
6833 13:57:07.911803 TX Vref Scan disable
6834 13:57:07.915169 == TX Byte 0 ==
6835 13:57:07.918575 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 13:57:07.921919 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 13:57:07.922008 == TX Byte 1 ==
6838 13:57:07.928522 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6839 13:57:07.931808 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6840 13:57:07.931906
6841 13:57:07.931974 [DATLAT]
6842 13:57:07.935079 Freq=400, CH1 RK0
6843 13:57:07.935166
6844 13:57:07.935233 DATLAT Default: 0xf
6845 13:57:07.938203 0, 0xFFFF, sum = 0
6846 13:57:07.938291 1, 0xFFFF, sum = 0
6847 13:57:07.941462 2, 0xFFFF, sum = 0
6848 13:57:07.944902 3, 0xFFFF, sum = 0
6849 13:57:07.944993 4, 0xFFFF, sum = 0
6850 13:57:07.948190 5, 0xFFFF, sum = 0
6851 13:57:07.948280 6, 0xFFFF, sum = 0
6852 13:57:07.951450 7, 0xFFFF, sum = 0
6853 13:57:07.951538 8, 0xFFFF, sum = 0
6854 13:57:07.954774 9, 0xFFFF, sum = 0
6855 13:57:07.954862 10, 0xFFFF, sum = 0
6856 13:57:07.958052 11, 0xFFFF, sum = 0
6857 13:57:07.958139 12, 0xFFFF, sum = 0
6858 13:57:07.961339 13, 0x0, sum = 1
6859 13:57:07.961431 14, 0x0, sum = 2
6860 13:57:07.964618 15, 0x0, sum = 3
6861 13:57:07.964706 16, 0x0, sum = 4
6862 13:57:07.967971 best_step = 14
6863 13:57:07.968061
6864 13:57:07.968129 ==
6865 13:57:07.971166 Dram Type= 6, Freq= 0, CH_1, rank 0
6866 13:57:07.974640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 13:57:07.974750 ==
6868 13:57:07.977573 RX Vref Scan: 1
6869 13:57:07.977655
6870 13:57:07.977721 RX Vref 0 -> 0, step: 1
6871 13:57:07.977783
6872 13:57:07.980955 RX Delay -375 -> 252, step: 8
6873 13:57:07.981039
6874 13:57:07.984331 Set Vref, RX VrefLevel [Byte0]: 56
6875 13:57:07.987706 [Byte1]: 55
6876 13:57:07.992282
6877 13:57:07.992369 Final RX Vref Byte 0 = 56 to rank0
6878 13:57:07.995217 Final RX Vref Byte 1 = 55 to rank0
6879 13:57:07.998643 Final RX Vref Byte 0 = 56 to rank1
6880 13:57:08.002214 Final RX Vref Byte 1 = 55 to rank1==
6881 13:57:08.005243 Dram Type= 6, Freq= 0, CH_1, rank 0
6882 13:57:08.012023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 13:57:08.012121 ==
6884 13:57:08.012189 DQS Delay:
6885 13:57:08.015447 DQS0 = 52, DQS1 = 64
6886 13:57:08.015563 DQM Delay:
6887 13:57:08.015628 DQM0 = 9, DQM1 = 10
6888 13:57:08.018607 DQ Delay:
6889 13:57:08.021985 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6890 13:57:08.022072 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6891 13:57:08.025031 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6892 13:57:08.028694 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6893 13:57:08.028788
6894 13:57:08.032033
6895 13:57:08.038558 [DQSOSCAuto] RK0, (LSB)MR18= 0x5669, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6896 13:57:08.041893 CH1 RK0: MR19=C0C, MR18=5669
6897 13:57:08.048669 CH1_RK0: MR19=0xC0C, MR18=0x5669, DQSOSC=396, MR23=63, INC=376, DEC=251
6898 13:57:08.048791 ==
6899 13:57:08.051836 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 13:57:08.054995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 13:57:08.055109 ==
6902 13:57:08.058332 [Gating] SW mode calibration
6903 13:57:08.065012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6904 13:57:08.071812 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6905 13:57:08.074796 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6906 13:57:08.078173 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6907 13:57:08.084704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6908 13:57:08.088084 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6909 13:57:08.091566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 13:57:08.094924 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 13:57:08.101208 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6912 13:57:08.104575 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6913 13:57:08.108006 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 13:57:08.111246 Total UI for P1: 0, mck2ui 16
6915 13:57:08.114740 best dqsien dly found for B0: ( 0, 14, 24)
6916 13:57:08.117991 Total UI for P1: 0, mck2ui 16
6917 13:57:08.121119 best dqsien dly found for B1: ( 0, 14, 24)
6918 13:57:08.127783 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6919 13:57:08.131070 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6920 13:57:08.131186
6921 13:57:08.134334 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6922 13:57:08.137754 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6923 13:57:08.141147 [Gating] SW calibration Done
6924 13:57:08.141263 ==
6925 13:57:08.144484 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 13:57:08.147678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 13:57:08.147795 ==
6928 13:57:08.151114 RX Vref Scan: 0
6929 13:57:08.151224
6930 13:57:08.151321 RX Vref 0 -> 0, step: 1
6931 13:57:08.151419
6932 13:57:08.154188 RX Delay -410 -> 252, step: 16
6933 13:57:08.157583 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6934 13:57:08.164264 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6935 13:57:08.167598 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6936 13:57:08.171015 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6937 13:57:08.174061 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6938 13:57:08.181004 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6939 13:57:08.184290 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6940 13:57:08.187719 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6941 13:57:08.190563 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6942 13:57:08.197243 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6943 13:57:08.200598 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6944 13:57:08.203974 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6945 13:57:08.210805 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6946 13:57:08.213770 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6947 13:57:08.217029 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6948 13:57:08.220635 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6949 13:57:08.223671 ==
6950 13:57:08.223788 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 13:57:08.230221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 13:57:08.230314 ==
6953 13:57:08.230402 DQS Delay:
6954 13:57:08.233632 DQS0 = 59, DQS1 = 67
6955 13:57:08.233715 DQM Delay:
6956 13:57:08.236911 DQM0 = 19, DQM1 = 20
6957 13:57:08.236995 DQ Delay:
6958 13:57:08.240268 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6959 13:57:08.243425 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6960 13:57:08.246861 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6961 13:57:08.250133 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6962 13:57:08.250218
6963 13:57:08.250283
6964 13:57:08.250343 ==
6965 13:57:08.253433 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 13:57:08.256911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 13:57:08.256997 ==
6968 13:57:08.257063
6969 13:57:08.257123
6970 13:57:08.260252 TX Vref Scan disable
6971 13:57:08.260336 == TX Byte 0 ==
6972 13:57:08.266901 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6973 13:57:08.270317 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6974 13:57:08.270409 == TX Byte 1 ==
6975 13:57:08.276656 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6976 13:57:08.280214 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6977 13:57:08.280318 ==
6978 13:57:08.283568 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 13:57:08.286887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 13:57:08.286993 ==
6981 13:57:08.287129
6982 13:57:08.287243
6983 13:57:08.290032 TX Vref Scan disable
6984 13:57:08.290115 == TX Byte 0 ==
6985 13:57:08.296748 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6986 13:57:08.300053 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6987 13:57:08.300141 == TX Byte 1 ==
6988 13:57:08.306688 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6989 13:57:08.310058 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6990 13:57:08.310153
6991 13:57:08.310220 [DATLAT]
6992 13:57:08.313009 Freq=400, CH1 RK1
6993 13:57:08.313093
6994 13:57:08.313157 DATLAT Default: 0xe
6995 13:57:08.316395 0, 0xFFFF, sum = 0
6996 13:57:08.316478 1, 0xFFFF, sum = 0
6997 13:57:08.319834 2, 0xFFFF, sum = 0
6998 13:57:08.319919 3, 0xFFFF, sum = 0
6999 13:57:08.323184 4, 0xFFFF, sum = 0
7000 13:57:08.323268 5, 0xFFFF, sum = 0
7001 13:57:08.326284 6, 0xFFFF, sum = 0
7002 13:57:08.326371 7, 0xFFFF, sum = 0
7003 13:57:08.329923 8, 0xFFFF, sum = 0
7004 13:57:08.332982 9, 0xFFFF, sum = 0
7005 13:57:08.333067 10, 0xFFFF, sum = 0
7006 13:57:08.336274 11, 0xFFFF, sum = 0
7007 13:57:08.336361 12, 0xFFFF, sum = 0
7008 13:57:08.339775 13, 0x0, sum = 1
7009 13:57:08.339863 14, 0x0, sum = 2
7010 13:57:08.343172 15, 0x0, sum = 3
7011 13:57:08.343295 16, 0x0, sum = 4
7012 13:57:08.343394 best_step = 14
7013 13:57:08.343492
7014 13:57:08.346538 ==
7015 13:57:08.349859 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 13:57:08.353065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 13:57:08.353189 ==
7018 13:57:08.353255 RX Vref Scan: 0
7019 13:57:08.353316
7020 13:57:08.356187 RX Vref 0 -> 0, step: 1
7021 13:57:08.356270
7022 13:57:08.359543 RX Delay -375 -> 252, step: 8
7023 13:57:08.366745 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
7024 13:57:08.370161 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7025 13:57:08.373439 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7026 13:57:08.376833 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7027 13:57:08.383445 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7028 13:57:08.386693 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7029 13:57:08.389910 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7030 13:57:08.393643 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7031 13:57:08.400336 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7032 13:57:08.403611 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7033 13:57:08.407026 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7034 13:57:08.410179 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
7035 13:57:08.416709 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7036 13:57:08.420140 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7037 13:57:08.423439 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7038 13:57:08.430032 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7039 13:57:08.430123 ==
7040 13:57:08.433391 Dram Type= 6, Freq= 0, CH_1, rank 1
7041 13:57:08.436850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7042 13:57:08.436933 ==
7043 13:57:08.436999 DQS Delay:
7044 13:57:08.439978 DQS0 = 60, DQS1 = 64
7045 13:57:08.440075 DQM Delay:
7046 13:57:08.443175 DQM0 = 13, DQM1 = 10
7047 13:57:08.443259 DQ Delay:
7048 13:57:08.446481 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7049 13:57:08.449871 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7050 13:57:08.453251 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7051 13:57:08.456590 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7052 13:57:08.456672
7053 13:57:08.456738
7054 13:57:08.462896 [DQSOSCAuto] RK1, (LSB)MR18= 0x73a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7055 13:57:08.466403 CH1 RK1: MR19=C0C, MR18=73A5
7056 13:57:08.472975 CH1_RK1: MR19=0xC0C, MR18=0x73A5, DQSOSC=389, MR23=63, INC=390, DEC=260
7057 13:57:08.476068 [RxdqsGatingPostProcess] freq 400
7058 13:57:08.482704 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7059 13:57:08.485993 best DQS0 dly(2T, 0.5T) = (0, 10)
7060 13:57:08.486122 best DQS1 dly(2T, 0.5T) = (0, 10)
7061 13:57:08.489360 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7062 13:57:08.492960 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7063 13:57:08.495858 best DQS0 dly(2T, 0.5T) = (0, 10)
7064 13:57:08.499281 best DQS1 dly(2T, 0.5T) = (0, 10)
7065 13:57:08.502670 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7066 13:57:08.505860 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7067 13:57:08.509433 Pre-setting of DQS Precalculation
7068 13:57:08.515742 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7069 13:57:08.522593 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7070 13:57:08.528938 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7071 13:57:08.529079
7072 13:57:08.529175
7073 13:57:08.532205 [Calibration Summary] 800 Mbps
7074 13:57:08.532333 CH 0, Rank 0
7075 13:57:08.535660 SW Impedance : PASS
7076 13:57:08.539008 DUTY Scan : NO K
7077 13:57:08.539124 ZQ Calibration : PASS
7078 13:57:08.542382 Jitter Meter : NO K
7079 13:57:08.545636 CBT Training : PASS
7080 13:57:08.545747 Write leveling : PASS
7081 13:57:08.548860 RX DQS gating : PASS
7082 13:57:08.548969 RX DQ/DQS(RDDQC) : PASS
7083 13:57:08.552415 TX DQ/DQS : PASS
7084 13:57:08.555475 RX DATLAT : PASS
7085 13:57:08.555589 RX DQ/DQS(Engine): PASS
7086 13:57:08.558780 TX OE : NO K
7087 13:57:08.558892 All Pass.
7088 13:57:08.558988
7089 13:57:08.562066 CH 0, Rank 1
7090 13:57:08.562226 SW Impedance : PASS
7091 13:57:08.565563 DUTY Scan : NO K
7092 13:57:08.568574 ZQ Calibration : PASS
7093 13:57:08.568687 Jitter Meter : NO K
7094 13:57:08.571908 CBT Training : PASS
7095 13:57:08.575216 Write leveling : NO K
7096 13:57:08.575329 RX DQS gating : PASS
7097 13:57:08.578491 RX DQ/DQS(RDDQC) : PASS
7098 13:57:08.581857 TX DQ/DQS : PASS
7099 13:57:08.581971 RX DATLAT : PASS
7100 13:57:08.585275 RX DQ/DQS(Engine): PASS
7101 13:57:08.588684 TX OE : NO K
7102 13:57:08.588802 All Pass.
7103 13:57:08.588902
7104 13:57:08.588997 CH 1, Rank 0
7105 13:57:08.591994 SW Impedance : PASS
7106 13:57:08.595041 DUTY Scan : NO K
7107 13:57:08.595153 ZQ Calibration : PASS
7108 13:57:08.598458 Jitter Meter : NO K
7109 13:57:08.601833 CBT Training : PASS
7110 13:57:08.601949 Write leveling : PASS
7111 13:57:08.605216 RX DQS gating : PASS
7112 13:57:08.608587 RX DQ/DQS(RDDQC) : PASS
7113 13:57:08.608698 TX DQ/DQS : PASS
7114 13:57:08.611887 RX DATLAT : PASS
7115 13:57:08.615122 RX DQ/DQS(Engine): PASS
7116 13:57:08.615238 TX OE : NO K
7117 13:57:08.615339 All Pass.
7118 13:57:08.618569
7119 13:57:08.618684 CH 1, Rank 1
7120 13:57:08.621490 SW Impedance : PASS
7121 13:57:08.621617 DUTY Scan : NO K
7122 13:57:08.624837 ZQ Calibration : PASS
7123 13:57:08.628246 Jitter Meter : NO K
7124 13:57:08.628354 CBT Training : PASS
7125 13:57:08.631600 Write leveling : NO K
7126 13:57:08.631704 RX DQS gating : PASS
7127 13:57:08.634921 RX DQ/DQS(RDDQC) : PASS
7128 13:57:08.638025 TX DQ/DQS : PASS
7129 13:57:08.638140 RX DATLAT : PASS
7130 13:57:08.641255 RX DQ/DQS(Engine): PASS
7131 13:57:08.644653 TX OE : NO K
7132 13:57:08.644768 All Pass.
7133 13:57:08.644869
7134 13:57:08.647993 DramC Write-DBI off
7135 13:57:08.648103 PER_BANK_REFRESH: Hybrid Mode
7136 13:57:08.651304 TX_TRACKING: ON
7137 13:57:08.661235 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7138 13:57:08.664364 [FAST_K] Save calibration result to emmc
7139 13:57:08.667689 dramc_set_vcore_voltage set vcore to 725000
7140 13:57:08.670925 Read voltage for 1600, 0
7141 13:57:08.671042 Vio18 = 0
7142 13:57:08.671138 Vcore = 725000
7143 13:57:08.671231 Vdram = 0
7144 13:57:08.674314 Vddq = 0
7145 13:57:08.674419 Vmddr = 0
7146 13:57:08.681026 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7147 13:57:08.684367 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7148 13:57:08.687726 MEM_TYPE=3, freq_sel=13
7149 13:57:08.690921 sv_algorithm_assistance_LP4_3733
7150 13:57:08.694294 ============ PULL DRAM RESETB DOWN ============
7151 13:57:08.697724 ========== PULL DRAM RESETB DOWN end =========
7152 13:57:08.704263 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7153 13:57:08.707794 ===================================
7154 13:57:08.707904 LPDDR4 DRAM CONFIGURATION
7155 13:57:08.710897 ===================================
7156 13:57:08.714102 EX_ROW_EN[0] = 0x0
7157 13:57:08.717570 EX_ROW_EN[1] = 0x0
7158 13:57:08.717677 LP4Y_EN = 0x0
7159 13:57:08.720763 WORK_FSP = 0x1
7160 13:57:08.720867 WL = 0x5
7161 13:57:08.723987 RL = 0x5
7162 13:57:08.724093 BL = 0x2
7163 13:57:08.727362 RPST = 0x0
7164 13:57:08.727469 RD_PRE = 0x0
7165 13:57:08.730749 WR_PRE = 0x1
7166 13:57:08.730853 WR_PST = 0x1
7167 13:57:08.734152 DBI_WR = 0x0
7168 13:57:08.734254 DBI_RD = 0x0
7169 13:57:08.737575 OTF = 0x1
7170 13:57:08.740601 ===================================
7171 13:57:08.744113 ===================================
7172 13:57:08.744223 ANA top config
7173 13:57:08.747414 ===================================
7174 13:57:08.750602 DLL_ASYNC_EN = 0
7175 13:57:08.754000 ALL_SLAVE_EN = 0
7176 13:57:08.757138 NEW_RANK_MODE = 1
7177 13:57:08.757248 DLL_IDLE_MODE = 1
7178 13:57:08.760709 LP45_APHY_COMB_EN = 1
7179 13:57:08.763706 TX_ODT_DIS = 0
7180 13:57:08.766938 NEW_8X_MODE = 1
7181 13:57:08.770417 ===================================
7182 13:57:08.773556 ===================================
7183 13:57:08.777021 data_rate = 3200
7184 13:57:08.777129 CKR = 1
7185 13:57:08.780435 DQ_P2S_RATIO = 8
7186 13:57:08.783648 ===================================
7187 13:57:08.786984 CA_P2S_RATIO = 8
7188 13:57:08.790316 DQ_CA_OPEN = 0
7189 13:57:08.793571 DQ_SEMI_OPEN = 0
7190 13:57:08.796748 CA_SEMI_OPEN = 0
7191 13:57:08.796852 CA_FULL_RATE = 0
7192 13:57:08.800125 DQ_CKDIV4_EN = 0
7193 13:57:08.803408 CA_CKDIV4_EN = 0
7194 13:57:08.806845 CA_PREDIV_EN = 0
7195 13:57:08.810113 PH8_DLY = 12
7196 13:57:08.813575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7197 13:57:08.813679 DQ_AAMCK_DIV = 4
7198 13:57:08.816884 CA_AAMCK_DIV = 4
7199 13:57:08.819924 CA_ADMCK_DIV = 4
7200 13:57:08.823446 DQ_TRACK_CA_EN = 0
7201 13:57:08.826775 CA_PICK = 1600
7202 13:57:08.830106 CA_MCKIO = 1600
7203 13:57:08.833419 MCKIO_SEMI = 0
7204 13:57:08.833550 PLL_FREQ = 3068
7205 13:57:08.836520 DQ_UI_PI_RATIO = 32
7206 13:57:08.839901 CA_UI_PI_RATIO = 0
7207 13:57:08.843301 ===================================
7208 13:57:08.846704 ===================================
7209 13:57:08.849811 memory_type:LPDDR4
7210 13:57:08.849915 GP_NUM : 10
7211 13:57:08.853003 SRAM_EN : 1
7212 13:57:08.856312 MD32_EN : 0
7213 13:57:08.859642 ===================================
7214 13:57:08.859754 [ANA_INIT] >>>>>>>>>>>>>>
7215 13:57:08.863207 <<<<<< [CONFIGURE PHASE]: ANA_TX
7216 13:57:08.866444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7217 13:57:08.869637 ===================================
7218 13:57:08.872986 data_rate = 3200,PCW = 0X7600
7219 13:57:08.876263 ===================================
7220 13:57:08.879549 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7221 13:57:08.886134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7222 13:57:08.889403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7223 13:57:08.896085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7224 13:57:08.899622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7225 13:57:08.902898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7226 13:57:08.905996 [ANA_INIT] flow start
7227 13:57:08.906113 [ANA_INIT] PLL >>>>>>>>
7228 13:57:08.909335 [ANA_INIT] PLL <<<<<<<<
7229 13:57:08.913068 [ANA_INIT] MIDPI >>>>>>>>
7230 13:57:08.913179 [ANA_INIT] MIDPI <<<<<<<<
7231 13:57:08.915987 [ANA_INIT] DLL >>>>>>>>
7232 13:57:08.919332 [ANA_INIT] DLL <<<<<<<<
7233 13:57:08.919438 [ANA_INIT] flow end
7234 13:57:08.926124 ============ LP4 DIFF to SE enter ============
7235 13:57:08.929355 ============ LP4 DIFF to SE exit ============
7236 13:57:08.929469 [ANA_INIT] <<<<<<<<<<<<<
7237 13:57:08.932668 [Flow] Enable top DCM control >>>>>
7238 13:57:08.935916 [Flow] Enable top DCM control <<<<<
7239 13:57:08.939526 Enable DLL master slave shuffle
7240 13:57:08.945986 ==============================================================
7241 13:57:08.949295 Gating Mode config
7242 13:57:08.952726 ==============================================================
7243 13:57:08.955976 Config description:
7244 13:57:08.965902 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7245 13:57:08.972545 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7246 13:57:08.975670 SELPH_MODE 0: By rank 1: By Phase
7247 13:57:08.982673 ==============================================================
7248 13:57:08.985706 GAT_TRACK_EN = 1
7249 13:57:08.989132 RX_GATING_MODE = 2
7250 13:57:08.992642 RX_GATING_TRACK_MODE = 2
7251 13:57:08.992740 SELPH_MODE = 1
7252 13:57:08.995938 PICG_EARLY_EN = 1
7253 13:57:08.999056 VALID_LAT_VALUE = 1
7254 13:57:09.005517 ==============================================================
7255 13:57:09.008945 Enter into Gating configuration >>>>
7256 13:57:09.012205 Exit from Gating configuration <<<<
7257 13:57:09.015561 Enter into DVFS_PRE_config >>>>>
7258 13:57:09.025350 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7259 13:57:09.028691 Exit from DVFS_PRE_config <<<<<
7260 13:57:09.032197 Enter into PICG configuration >>>>
7261 13:57:09.035454 Exit from PICG configuration <<<<
7262 13:57:09.038962 [RX_INPUT] configuration >>>>>
7263 13:57:09.042190 [RX_INPUT] configuration <<<<<
7264 13:57:09.045435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7265 13:57:09.052279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7266 13:57:09.058708 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7267 13:57:09.065367 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7268 13:57:09.072081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7269 13:57:09.075461 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7270 13:57:09.081728 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7271 13:57:09.085212 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7272 13:57:09.088419 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7273 13:57:09.091935 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7274 13:57:09.098363 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7275 13:57:09.101653 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 13:57:09.105119 ===================================
7277 13:57:09.108359 LPDDR4 DRAM CONFIGURATION
7278 13:57:09.111453 ===================================
7279 13:57:09.111564 EX_ROW_EN[0] = 0x0
7280 13:57:09.114887 EX_ROW_EN[1] = 0x0
7281 13:57:09.114992 LP4Y_EN = 0x0
7282 13:57:09.118303 WORK_FSP = 0x1
7283 13:57:09.118390 WL = 0x5
7284 13:57:09.121748 RL = 0x5
7285 13:57:09.121835 BL = 0x2
7286 13:57:09.124971 RPST = 0x0
7287 13:57:09.125077 RD_PRE = 0x0
7288 13:57:09.128351 WR_PRE = 0x1
7289 13:57:09.128447 WR_PST = 0x1
7290 13:57:09.131698 DBI_WR = 0x0
7291 13:57:09.134995 DBI_RD = 0x0
7292 13:57:09.135101 OTF = 0x1
7293 13:57:09.138285 ===================================
7294 13:57:09.141514 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7295 13:57:09.144669 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7296 13:57:09.151669 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7297 13:57:09.154744 ===================================
7298 13:57:09.157984 LPDDR4 DRAM CONFIGURATION
7299 13:57:09.161449 ===================================
7300 13:57:09.161575 EX_ROW_EN[0] = 0x10
7301 13:57:09.164748 EX_ROW_EN[1] = 0x0
7302 13:57:09.164858 LP4Y_EN = 0x0
7303 13:57:09.168198 WORK_FSP = 0x1
7304 13:57:09.168310 WL = 0x5
7305 13:57:09.171170 RL = 0x5
7306 13:57:09.171274 BL = 0x2
7307 13:57:09.174815 RPST = 0x0
7308 13:57:09.174934 RD_PRE = 0x0
7309 13:57:09.177798 WR_PRE = 0x1
7310 13:57:09.177902 WR_PST = 0x1
7311 13:57:09.181250 DBI_WR = 0x0
7312 13:57:09.184593 DBI_RD = 0x0
7313 13:57:09.184696 OTF = 0x1
7314 13:57:09.187545 ===================================
7315 13:57:09.194195 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7316 13:57:09.194302 ==
7317 13:57:09.197565 Dram Type= 6, Freq= 0, CH_0, rank 0
7318 13:57:09.200952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 13:57:09.201057 ==
7320 13:57:09.204072 [Duty_Offset_Calibration]
7321 13:57:09.204175 B0:2 B1:0 CA:4
7322 13:57:09.207461
7323 13:57:09.207569 [DutyScan_Calibration_Flow] k_type=0
7324 13:57:09.219001
7325 13:57:09.219120 ==CLK 0==
7326 13:57:09.222125 Final CLK duty delay cell = 0
7327 13:57:09.225388 [0] MAX Duty = 5031%(X100), DQS PI = 12
7328 13:57:09.228996 [0] MIN Duty = 4876%(X100), DQS PI = 54
7329 13:57:09.232256 [0] AVG Duty = 4953%(X100)
7330 13:57:09.232342
7331 13:57:09.235386 CH0 CLK Duty spec in!! Max-Min= 155%
7332 13:57:09.238681 [DutyScan_Calibration_Flow] ====Done====
7333 13:57:09.238767
7334 13:57:09.242022 [DutyScan_Calibration_Flow] k_type=1
7335 13:57:09.259159
7336 13:57:09.259276 ==DQS 0 ==
7337 13:57:09.262385 Final DQS duty delay cell = 0
7338 13:57:09.265646 [0] MAX Duty = 5094%(X100), DQS PI = 30
7339 13:57:09.269053 [0] MIN Duty = 4875%(X100), DQS PI = 48
7340 13:57:09.272209 [0] AVG Duty = 4984%(X100)
7341 13:57:09.272297
7342 13:57:09.272382 ==DQS 1 ==
7343 13:57:09.275394 Final DQS duty delay cell = 0
7344 13:57:09.279112 [0] MAX Duty = 5156%(X100), DQS PI = 32
7345 13:57:09.282117 [0] MIN Duty = 5062%(X100), DQS PI = 0
7346 13:57:09.285518 [0] AVG Duty = 5109%(X100)
7347 13:57:09.285628
7348 13:57:09.288934 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7349 13:57:09.289062
7350 13:57:09.292162 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7351 13:57:09.295588 [DutyScan_Calibration_Flow] ====Done====
7352 13:57:09.295696
7353 13:57:09.298760 [DutyScan_Calibration_Flow] k_type=3
7354 13:57:09.317138
7355 13:57:09.317296 ==DQM 0 ==
7356 13:57:09.320061 Final DQM duty delay cell = 0
7357 13:57:09.323265 [0] MAX Duty = 5156%(X100), DQS PI = 30
7358 13:57:09.326690 [0] MIN Duty = 4875%(X100), DQS PI = 0
7359 13:57:09.326778 [0] AVG Duty = 5015%(X100)
7360 13:57:09.330364
7361 13:57:09.330535 ==DQM 1 ==
7362 13:57:09.333400 Final DQM duty delay cell = 4
7363 13:57:09.336783 [4] MAX Duty = 5187%(X100), DQS PI = 62
7364 13:57:09.340135 [4] MIN Duty = 5000%(X100), DQS PI = 38
7365 13:57:09.343607 [4] AVG Duty = 5093%(X100)
7366 13:57:09.343689
7367 13:57:09.346827 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7368 13:57:09.346925
7369 13:57:09.350087 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7370 13:57:09.353462 [DutyScan_Calibration_Flow] ====Done====
7371 13:57:09.353577
7372 13:57:09.356560 [DutyScan_Calibration_Flow] k_type=2
7373 13:57:09.373137
7374 13:57:09.373293 ==DQ 0 ==
7375 13:57:09.376561 Final DQ duty delay cell = -4
7376 13:57:09.379726 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7377 13:57:09.383054 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7378 13:57:09.386615 [-4] AVG Duty = 4938%(X100)
7379 13:57:09.386707
7380 13:57:09.386770 ==DQ 1 ==
7381 13:57:09.389903 Final DQ duty delay cell = 0
7382 13:57:09.393301 [0] MAX Duty = 5156%(X100), DQS PI = 60
7383 13:57:09.396603 [0] MIN Duty = 5000%(X100), DQS PI = 16
7384 13:57:09.399983 [0] AVG Duty = 5078%(X100)
7385 13:57:09.400063
7386 13:57:09.403316 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7387 13:57:09.403396
7388 13:57:09.406372 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7389 13:57:09.409711 [DutyScan_Calibration_Flow] ====Done====
7390 13:57:09.409793 ==
7391 13:57:09.413101 Dram Type= 6, Freq= 0, CH_1, rank 0
7392 13:57:09.416462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7393 13:57:09.416543 ==
7394 13:57:09.419610 [Duty_Offset_Calibration]
7395 13:57:09.419690 B0:1 B1:-2 CA:1
7396 13:57:09.419754
7397 13:57:09.423103 [DutyScan_Calibration_Flow] k_type=0
7398 13:57:09.433924
7399 13:57:09.434026 ==CLK 0==
7400 13:57:09.437103 Final CLK duty delay cell = 0
7401 13:57:09.440307 [0] MAX Duty = 5062%(X100), DQS PI = 20
7402 13:57:09.443721 [0] MIN Duty = 4844%(X100), DQS PI = 2
7403 13:57:09.443804 [0] AVG Duty = 4953%(X100)
7404 13:57:09.447042
7405 13:57:09.447126 CH1 CLK Duty spec in!! Max-Min= 218%
7406 13:57:09.453733 [DutyScan_Calibration_Flow] ====Done====
7407 13:57:09.453823
7408 13:57:09.457184 [DutyScan_Calibration_Flow] k_type=1
7409 13:57:09.472725
7410 13:57:09.472903 ==DQS 0 ==
7411 13:57:09.476022 Final DQS duty delay cell = -4
7412 13:57:09.479096 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7413 13:57:09.482671 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7414 13:57:09.485991 [-4] AVG Duty = 4922%(X100)
7415 13:57:09.486083
7416 13:57:09.486161 ==DQS 1 ==
7417 13:57:09.489163 Final DQS duty delay cell = 0
7418 13:57:09.492393 [0] MAX Duty = 5093%(X100), DQS PI = 62
7419 13:57:09.495711 [0] MIN Duty = 4844%(X100), DQS PI = 24
7420 13:57:09.499094 [0] AVG Duty = 4968%(X100)
7421 13:57:09.499176
7422 13:57:09.502556 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7423 13:57:09.502638
7424 13:57:09.505438 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7425 13:57:09.509187 [DutyScan_Calibration_Flow] ====Done====
7426 13:57:09.509269
7427 13:57:09.512160 [DutyScan_Calibration_Flow] k_type=3
7428 13:57:09.529997
7429 13:57:09.530137 ==DQM 0 ==
7430 13:57:09.533301 Final DQM duty delay cell = 0
7431 13:57:09.536558 [0] MAX Duty = 5031%(X100), DQS PI = 24
7432 13:57:09.539816 [0] MIN Duty = 4813%(X100), DQS PI = 56
7433 13:57:09.543321 [0] AVG Duty = 4922%(X100)
7434 13:57:09.543474
7435 13:57:09.543541 ==DQM 1 ==
7436 13:57:09.546547 Final DQM duty delay cell = 0
7437 13:57:09.549944 [0] MAX Duty = 5062%(X100), DQS PI = 34
7438 13:57:09.553287 [0] MIN Duty = 4875%(X100), DQS PI = 26
7439 13:57:09.556711 [0] AVG Duty = 4968%(X100)
7440 13:57:09.556795
7441 13:57:09.559644 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7442 13:57:09.559726
7443 13:57:09.563072 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7444 13:57:09.566316 [DutyScan_Calibration_Flow] ====Done====
7445 13:57:09.566412
7446 13:57:09.569728 [DutyScan_Calibration_Flow] k_type=2
7447 13:57:09.586970
7448 13:57:09.587108 ==DQ 0 ==
7449 13:57:09.590307 Final DQ duty delay cell = 0
7450 13:57:09.593415 [0] MAX Duty = 5093%(X100), DQS PI = 22
7451 13:57:09.596724 [0] MIN Duty = 4907%(X100), DQS PI = 58
7452 13:57:09.596815 [0] AVG Duty = 5000%(X100)
7453 13:57:09.600230
7454 13:57:09.600359 ==DQ 1 ==
7455 13:57:09.603535 Final DQ duty delay cell = 0
7456 13:57:09.606791 [0] MAX Duty = 5125%(X100), DQS PI = 34
7457 13:57:09.609948 [0] MIN Duty = 4969%(X100), DQS PI = 24
7458 13:57:09.610040 [0] AVG Duty = 5047%(X100)
7459 13:57:09.613203
7460 13:57:09.616601 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7461 13:57:09.616687
7462 13:57:09.619902 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7463 13:57:09.623297 [DutyScan_Calibration_Flow] ====Done====
7464 13:57:09.626586 nWR fixed to 30
7465 13:57:09.626702 [ModeRegInit_LP4] CH0 RK0
7466 13:57:09.629995 [ModeRegInit_LP4] CH0 RK1
7467 13:57:09.633277 [ModeRegInit_LP4] CH1 RK0
7468 13:57:09.636731 [ModeRegInit_LP4] CH1 RK1
7469 13:57:09.636844 match AC timing 5
7470 13:57:09.643207 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7471 13:57:09.646436 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7472 13:57:09.649725 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7473 13:57:09.656511 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7474 13:57:09.659494 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7475 13:57:09.659587 [MiockJmeterHQA]
7476 13:57:09.659652
7477 13:57:09.662851 [DramcMiockJmeter] u1RxGatingPI = 0
7478 13:57:09.666233 0 : 4255, 4029
7479 13:57:09.666345 4 : 4367, 4140
7480 13:57:09.669664 8 : 4253, 4026
7481 13:57:09.669754 12 : 4252, 4027
7482 13:57:09.669823 16 : 4252, 4027
7483 13:57:09.672956 20 : 4252, 4027
7484 13:57:09.673040 24 : 4252, 4027
7485 13:57:09.676068 28 : 4363, 4137
7486 13:57:09.676178 32 : 4255, 4029
7487 13:57:09.679785 36 : 4363, 4138
7488 13:57:09.679898 40 : 4252, 4026
7489 13:57:09.683033 44 : 4252, 4027
7490 13:57:09.683119 48 : 4252, 4027
7491 13:57:09.683185 52 : 4363, 4138
7492 13:57:09.685955 56 : 4252, 4027
7493 13:57:09.686038 60 : 4361, 4137
7494 13:57:09.689297 64 : 4250, 4026
7495 13:57:09.689413 68 : 4249, 4027
7496 13:57:09.693196 72 : 4250, 4027
7497 13:57:09.693279 76 : 4250, 4027
7498 13:57:09.696044 80 : 4360, 4137
7499 13:57:09.696128 84 : 4250, 4026
7500 13:57:09.696194 88 : 4360, 4138
7501 13:57:09.699356 92 : 4250, 4027
7502 13:57:09.699440 96 : 4250, 4027
7503 13:57:09.702680 100 : 4250, 4027
7504 13:57:09.702764 104 : 4250, 3518
7505 13:57:09.705917 108 : 4250, 1
7506 13:57:09.706021 112 : 4361, 0
7507 13:57:09.706089 116 : 4361, 0
7508 13:57:09.709367 120 : 4250, 0
7509 13:57:09.709488 124 : 4250, 0
7510 13:57:09.712781 128 : 4249, 0
7511 13:57:09.712869 132 : 4250, 0
7512 13:57:09.712935 136 : 4250, 0
7513 13:57:09.715896 140 : 4250, 0
7514 13:57:09.715981 144 : 4252, 0
7515 13:57:09.719128 148 : 4361, 0
7516 13:57:09.719242 152 : 4250, 0
7517 13:57:09.719313 156 : 4249, 0
7518 13:57:09.722542 160 : 4360, 0
7519 13:57:09.722625 164 : 4361, 0
7520 13:57:09.722691 168 : 4360, 0
7521 13:57:09.725949 172 : 4250, 0
7522 13:57:09.726033 176 : 4250, 0
7523 13:57:09.729267 180 : 4250, 0
7524 13:57:09.729352 184 : 4250, 0
7525 13:57:09.729419 188 : 4250, 0
7526 13:57:09.732623 192 : 4250, 0
7527 13:57:09.732706 196 : 4250, 0
7528 13:57:09.735887 200 : 4250, 0
7529 13:57:09.735971 204 : 4361, 0
7530 13:57:09.736080 208 : 4250, 0
7531 13:57:09.739191 212 : 4250, 0
7532 13:57:09.739307 216 : 4361, 0
7533 13:57:09.742455 220 : 4360, 0
7534 13:57:09.742547 224 : 4250, 0
7535 13:57:09.742615 228 : 4250, 0
7536 13:57:09.746200 232 : 4252, 2
7537 13:57:09.746284 236 : 4250, 1274
7538 13:57:09.749116 240 : 4360, 4138
7539 13:57:09.749230 244 : 4250, 4027
7540 13:57:09.752754 248 : 4250, 4027
7541 13:57:09.752838 252 : 4250, 4027
7542 13:57:09.752905 256 : 4250, 4027
7543 13:57:09.755871 260 : 4249, 4027
7544 13:57:09.755954 264 : 4250, 4027
7545 13:57:09.759303 268 : 4250, 4027
7546 13:57:09.759411 272 : 4250, 4027
7547 13:57:09.762446 276 : 4249, 4027
7548 13:57:09.762555 280 : 4360, 4137
7549 13:57:09.765882 284 : 4361, 4137
7550 13:57:09.766007 288 : 4247, 4025
7551 13:57:09.769335 292 : 4360, 4138
7552 13:57:09.769444 296 : 4361, 4137
7553 13:57:09.772698 300 : 4250, 4027
7554 13:57:09.772783 304 : 4250, 4026
7555 13:57:09.776065 308 : 4250, 4027
7556 13:57:09.776176 312 : 4249, 4027
7557 13:57:09.776280 316 : 4250, 4027
7558 13:57:09.778978 320 : 4250, 4027
7559 13:57:09.779061 324 : 4250, 4027
7560 13:57:09.782333 328 : 4250, 4027
7561 13:57:09.782419 332 : 4360, 4137
7562 13:57:09.785467 336 : 4361, 4138
7563 13:57:09.785593 340 : 4247, 4025
7564 13:57:09.789113 344 : 4360, 4138
7565 13:57:09.789204 348 : 4360, 4137
7566 13:57:09.792165 352 : 4250, 4010
7567 13:57:09.792249 356 : 4250, 2685
7568 13:57:09.795445 360 : 4250, 0
7569 13:57:09.795556
7570 13:57:09.795652 MIOCK jitter meter ch=0
7571 13:57:09.795742
7572 13:57:09.798814 1T = (360-108) = 252 dly cells
7573 13:57:09.805717 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7574 13:57:09.805845 ==
7575 13:57:09.808693 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 13:57:09.812006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 13:57:09.812084 ==
7578 13:57:09.818820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7579 13:57:09.822138 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7580 13:57:09.825409 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7581 13:57:09.831798 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7582 13:57:09.841838 [CA 0] Center 44 (14~75) winsize 62
7583 13:57:09.845036 [CA 1] Center 43 (13~74) winsize 62
7584 13:57:09.848353 [CA 2] Center 39 (10~69) winsize 60
7585 13:57:09.851755 [CA 3] Center 39 (10~69) winsize 60
7586 13:57:09.855214 [CA 4] Center 37 (8~67) winsize 60
7587 13:57:09.858550 [CA 5] Center 37 (7~67) winsize 61
7588 13:57:09.858635
7589 13:57:09.861706 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7590 13:57:09.861817
7591 13:57:09.868190 [CATrainingPosCal] consider 1 rank data
7592 13:57:09.868285 u2DelayCellTimex100 = 258/100 ps
7593 13:57:09.875137 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7594 13:57:09.878564 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7595 13:57:09.881879 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7596 13:57:09.885212 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7597 13:57:09.888433 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7598 13:57:09.891586 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7599 13:57:09.891668
7600 13:57:09.895066 CA PerBit enable=1, Macro0, CA PI delay=37
7601 13:57:09.895149
7602 13:57:09.898297 [CBTSetCACLKResult] CA Dly = 37
7603 13:57:09.901699 CS Dly: 11 (0~42)
7604 13:57:09.905061 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7605 13:57:09.908339 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7606 13:57:09.908422 ==
7607 13:57:09.911584 Dram Type= 6, Freq= 0, CH_0, rank 1
7608 13:57:09.918270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 13:57:09.918360 ==
7610 13:57:09.921374 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7611 13:57:09.924686 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7612 13:57:09.931391 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7613 13:57:09.938075 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7614 13:57:09.945597 [CA 0] Center 44 (13~75) winsize 63
7615 13:57:09.949002 [CA 1] Center 43 (13~74) winsize 62
7616 13:57:09.952427 [CA 2] Center 39 (10~69) winsize 60
7617 13:57:09.955796 [CA 3] Center 39 (10~68) winsize 59
7618 13:57:09.958950 [CA 4] Center 38 (9~67) winsize 59
7619 13:57:09.962338 [CA 5] Center 37 (8~66) winsize 59
7620 13:57:09.962422
7621 13:57:09.965421 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7622 13:57:09.965550
7623 13:57:09.972055 [CATrainingPosCal] consider 2 rank data
7624 13:57:09.972155 u2DelayCellTimex100 = 258/100 ps
7625 13:57:09.978581 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7626 13:57:09.982299 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7627 13:57:09.985215 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7628 13:57:09.988616 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7629 13:57:09.991852 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7630 13:57:09.995524 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7631 13:57:09.995605
7632 13:57:09.998624 CA PerBit enable=1, Macro0, CA PI delay=37
7633 13:57:09.998708
7634 13:57:10.002200 [CBTSetCACLKResult] CA Dly = 37
7635 13:57:10.005517 CS Dly: 11 (0~43)
7636 13:57:10.008542 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7637 13:57:10.011888 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7638 13:57:10.011970
7639 13:57:10.015104 ----->DramcWriteLeveling(PI) begin...
7640 13:57:10.015187 ==
7641 13:57:10.018541 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 13:57:10.025132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 13:57:10.025218 ==
7644 13:57:10.028443 Write leveling (Byte 0): 35 => 35
7645 13:57:10.031769 Write leveling (Byte 1): 27 => 27
7646 13:57:10.031853 DramcWriteLeveling(PI) end<-----
7647 13:57:10.031947
7648 13:57:10.035070 ==
7649 13:57:10.038434 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 13:57:10.041813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 13:57:10.041897 ==
7652 13:57:10.045174 [Gating] SW mode calibration
7653 13:57:10.051800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7654 13:57:10.055062 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7655 13:57:10.061712 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 13:57:10.064914 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 13:57:10.068258 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 13:57:10.074727 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 13:57:10.078059 1 4 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7660 13:57:10.081600 1 4 20 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7661 13:57:10.088058 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7662 13:57:10.091333 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 13:57:10.094682 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 13:57:10.101307 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 13:57:10.104784 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7666 13:57:10.107851 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7667 13:57:10.114787 1 5 16 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7668 13:57:10.118094 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7669 13:57:10.121326 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
7670 13:57:10.128058 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 13:57:10.131198 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 13:57:10.134583 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 13:57:10.141282 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 13:57:10.144597 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 13:57:10.147758 1 6 16 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
7676 13:57:10.154575 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7677 13:57:10.157838 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7678 13:57:10.161287 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 13:57:10.167948 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 13:57:10.170896 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 13:57:10.174576 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 13:57:10.181152 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 13:57:10.184335 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7684 13:57:10.187412 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7685 13:57:10.194269 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7686 13:57:10.197687 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 13:57:10.200794 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 13:57:10.204127 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 13:57:10.210888 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 13:57:10.213950 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 13:57:10.217304 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 13:57:10.223970 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 13:57:10.227410 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 13:57:10.230786 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 13:57:10.237431 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 13:57:10.240424 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 13:57:10.244137 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 13:57:10.250441 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7699 13:57:10.253782 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7700 13:57:10.257493 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7701 13:57:10.260802 Total UI for P1: 0, mck2ui 16
7702 13:57:10.264096 best dqsien dly found for B0: ( 1, 9, 14)
7703 13:57:10.270486 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7704 13:57:10.273887 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 13:57:10.277207 Total UI for P1: 0, mck2ui 16
7706 13:57:10.280448 best dqsien dly found for B1: ( 1, 9, 24)
7707 13:57:10.283750 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7708 13:57:10.287092 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7709 13:57:10.287176
7710 13:57:10.290571 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7711 13:57:10.294014 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7712 13:57:10.296943 [Gating] SW calibration Done
7713 13:57:10.297077 ==
7714 13:57:10.300231 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 13:57:10.306878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 13:57:10.306962 ==
7717 13:57:10.307027 RX Vref Scan: 0
7718 13:57:10.307087
7719 13:57:10.310060 RX Vref 0 -> 0, step: 1
7720 13:57:10.310142
7721 13:57:10.313516 RX Delay 0 -> 252, step: 8
7722 13:57:10.316897 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7723 13:57:10.320317 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7724 13:57:10.323571 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7725 13:57:10.326757 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7726 13:57:10.333355 iDelay=192, Bit 4, Center 131 (80 ~ 183) 104
7727 13:57:10.336785 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7728 13:57:10.340154 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7729 13:57:10.343368 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7730 13:57:10.346710 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7731 13:57:10.353135 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7732 13:57:10.357272 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7733 13:57:10.359820 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7734 13:57:10.363120 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7735 13:57:10.366713 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7736 13:57:10.373035 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7737 13:57:10.376270 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7738 13:57:10.376355 ==
7739 13:57:10.379544 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 13:57:10.382865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 13:57:10.382949 ==
7742 13:57:10.386562 DQS Delay:
7743 13:57:10.386645 DQS0 = 0, DQS1 = 0
7744 13:57:10.389518 DQM Delay:
7745 13:57:10.389599 DQM0 = 129, DQM1 = 124
7746 13:57:10.389663 DQ Delay:
7747 13:57:10.392821 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7748 13:57:10.396178 DQ4 =131, DQ5 =111, DQ6 =139, DQ7 =139
7749 13:57:10.403034 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7750 13:57:10.406062 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7751 13:57:10.406148
7752 13:57:10.406212
7753 13:57:10.406271 ==
7754 13:57:10.409359 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 13:57:10.412947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 13:57:10.413029 ==
7757 13:57:10.413093
7758 13:57:10.413191
7759 13:57:10.416376 TX Vref Scan disable
7760 13:57:10.419297 == TX Byte 0 ==
7761 13:57:10.422974 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7762 13:57:10.426185 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7763 13:57:10.429306 == TX Byte 1 ==
7764 13:57:10.432757 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7765 13:57:10.436037 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7766 13:57:10.436124 ==
7767 13:57:10.439345 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 13:57:10.445773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 13:57:10.445866 ==
7770 13:57:10.458141
7771 13:57:10.461179 TX Vref early break, caculate TX vref
7772 13:57:10.464573 TX Vref=16, minBit 8, minWin=21, winSum=358
7773 13:57:10.467968 TX Vref=18, minBit 8, minWin=22, winSum=369
7774 13:57:10.471086 TX Vref=20, minBit 8, minWin=22, winSum=377
7775 13:57:10.474801 TX Vref=22, minBit 0, minWin=23, winSum=385
7776 13:57:10.478201 TX Vref=24, minBit 8, minWin=23, winSum=394
7777 13:57:10.484548 TX Vref=26, minBit 2, minWin=24, winSum=404
7778 13:57:10.487809 TX Vref=28, minBit 8, minWin=24, winSum=408
7779 13:57:10.490996 TX Vref=30, minBit 8, minWin=23, winSum=400
7780 13:57:10.494302 TX Vref=32, minBit 8, minWin=23, winSum=390
7781 13:57:10.497660 TX Vref=34, minBit 8, minWin=22, winSum=382
7782 13:57:10.504549 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 28
7783 13:57:10.504640
7784 13:57:10.507467 Final TX Range 0 Vref 28
7785 13:57:10.507551
7786 13:57:10.507616 ==
7787 13:57:10.510792 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 13:57:10.514290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 13:57:10.514376 ==
7790 13:57:10.514442
7791 13:57:10.514502
7792 13:57:10.517656 TX Vref Scan disable
7793 13:57:10.524386 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7794 13:57:10.524475 == TX Byte 0 ==
7795 13:57:10.527597 u2DelayCellOfst[0]=15 cells (4 PI)
7796 13:57:10.530753 u2DelayCellOfst[1]=18 cells (5 PI)
7797 13:57:10.534086 u2DelayCellOfst[2]=11 cells (3 PI)
7798 13:57:10.537410 u2DelayCellOfst[3]=15 cells (4 PI)
7799 13:57:10.540848 u2DelayCellOfst[4]=11 cells (3 PI)
7800 13:57:10.544178 u2DelayCellOfst[5]=0 cells (0 PI)
7801 13:57:10.547582 u2DelayCellOfst[6]=22 cells (6 PI)
7802 13:57:10.550860 u2DelayCellOfst[7]=22 cells (6 PI)
7803 13:57:10.553829 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7804 13:57:10.557066 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7805 13:57:10.560386 == TX Byte 1 ==
7806 13:57:10.563698 u2DelayCellOfst[8]=0 cells (0 PI)
7807 13:57:10.563778 u2DelayCellOfst[9]=3 cells (1 PI)
7808 13:57:10.567245 u2DelayCellOfst[10]=11 cells (3 PI)
7809 13:57:10.570377 u2DelayCellOfst[11]=11 cells (3 PI)
7810 13:57:10.573801 u2DelayCellOfst[12]=18 cells (5 PI)
7811 13:57:10.577278 u2DelayCellOfst[13]=15 cells (4 PI)
7812 13:57:10.580542 u2DelayCellOfst[14]=18 cells (5 PI)
7813 13:57:10.583922 u2DelayCellOfst[15]=15 cells (4 PI)
7814 13:57:10.590538 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7815 13:57:10.593522 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7816 13:57:10.593608 DramC Write-DBI on
7817 13:57:10.593673 ==
7818 13:57:10.596917 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 13:57:10.603381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 13:57:10.603477 ==
7821 13:57:10.603546
7822 13:57:10.603606
7823 13:57:10.603663 TX Vref Scan disable
7824 13:57:10.607968 == TX Byte 0 ==
7825 13:57:10.610926 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7826 13:57:10.614601 == TX Byte 1 ==
7827 13:57:10.617882 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7828 13:57:10.621128 DramC Write-DBI off
7829 13:57:10.621202
7830 13:57:10.621262 [DATLAT]
7831 13:57:10.621320 Freq=1600, CH0 RK0
7832 13:57:10.621403
7833 13:57:10.624123 DATLAT Default: 0xf
7834 13:57:10.627456 0, 0xFFFF, sum = 0
7835 13:57:10.627560 1, 0xFFFF, sum = 0
7836 13:57:10.630790 2, 0xFFFF, sum = 0
7837 13:57:10.630876 3, 0xFFFF, sum = 0
7838 13:57:10.634355 4, 0xFFFF, sum = 0
7839 13:57:10.634435 5, 0xFFFF, sum = 0
7840 13:57:10.637517 6, 0xFFFF, sum = 0
7841 13:57:10.637607 7, 0xFFFF, sum = 0
7842 13:57:10.640894 8, 0xFFFF, sum = 0
7843 13:57:10.641008 9, 0xFFFF, sum = 0
7844 13:57:10.644145 10, 0xFFFF, sum = 0
7845 13:57:10.644236 11, 0xFFFF, sum = 0
7846 13:57:10.647594 12, 0xFFFF, sum = 0
7847 13:57:10.647672 13, 0xEFFF, sum = 0
7848 13:57:10.650955 14, 0x0, sum = 1
7849 13:57:10.651035 15, 0x0, sum = 2
7850 13:57:10.653879 16, 0x0, sum = 3
7851 13:57:10.653955 17, 0x0, sum = 4
7852 13:57:10.657663 best_step = 15
7853 13:57:10.657741
7854 13:57:10.657804 ==
7855 13:57:10.660870 Dram Type= 6, Freq= 0, CH_0, rank 0
7856 13:57:10.663965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7857 13:57:10.664057 ==
7858 13:57:10.667207 RX Vref Scan: 1
7859 13:57:10.667293
7860 13:57:10.667357 Set Vref Range= 24 -> 127
7861 13:57:10.667417
7862 13:57:10.670831 RX Vref 24 -> 127, step: 1
7863 13:57:10.670927
7864 13:57:10.674100 RX Delay 11 -> 252, step: 4
7865 13:57:10.674174
7866 13:57:10.677366 Set Vref, RX VrefLevel [Byte0]: 24
7867 13:57:10.680627 [Byte1]: 24
7868 13:57:10.680712
7869 13:57:10.684024 Set Vref, RX VrefLevel [Byte0]: 25
7870 13:57:10.687408 [Byte1]: 25
7871 13:57:10.690703
7872 13:57:10.690778 Set Vref, RX VrefLevel [Byte0]: 26
7873 13:57:10.693795 [Byte1]: 26
7874 13:57:10.698284
7875 13:57:10.698384 Set Vref, RX VrefLevel [Byte0]: 27
7876 13:57:10.701467 [Byte1]: 27
7877 13:57:10.705627
7878 13:57:10.705703 Set Vref, RX VrefLevel [Byte0]: 28
7879 13:57:10.708891 [Byte1]: 28
7880 13:57:10.713370
7881 13:57:10.713484 Set Vref, RX VrefLevel [Byte0]: 29
7882 13:57:10.716712 [Byte1]: 29
7883 13:57:10.721140
7884 13:57:10.721224 Set Vref, RX VrefLevel [Byte0]: 30
7885 13:57:10.724299 [Byte1]: 30
7886 13:57:10.728576
7887 13:57:10.728650 Set Vref, RX VrefLevel [Byte0]: 31
7888 13:57:10.731877 [Byte1]: 31
7889 13:57:10.736246
7890 13:57:10.736331 Set Vref, RX VrefLevel [Byte0]: 32
7891 13:57:10.739520 [Byte1]: 32
7892 13:57:10.743906
7893 13:57:10.743991 Set Vref, RX VrefLevel [Byte0]: 33
7894 13:57:10.747263 [Byte1]: 33
7895 13:57:10.751560
7896 13:57:10.751652 Set Vref, RX VrefLevel [Byte0]: 34
7897 13:57:10.754537 [Byte1]: 34
7898 13:57:10.759052
7899 13:57:10.759141 Set Vref, RX VrefLevel [Byte0]: 35
7900 13:57:10.762358 [Byte1]: 35
7901 13:57:10.766480
7902 13:57:10.766595 Set Vref, RX VrefLevel [Byte0]: 36
7903 13:57:10.769985 [Byte1]: 36
7904 13:57:10.774284
7905 13:57:10.774376 Set Vref, RX VrefLevel [Byte0]: 37
7906 13:57:10.777655 [Byte1]: 37
7907 13:57:10.782036
7908 13:57:10.782155 Set Vref, RX VrefLevel [Byte0]: 38
7909 13:57:10.785246 [Byte1]: 38
7910 13:57:10.789451
7911 13:57:10.789551 Set Vref, RX VrefLevel [Byte0]: 39
7912 13:57:10.792857 [Byte1]: 39
7913 13:57:10.796950
7914 13:57:10.797028 Set Vref, RX VrefLevel [Byte0]: 40
7915 13:57:10.800482 [Byte1]: 40
7916 13:57:10.804896
7917 13:57:10.804984 Set Vref, RX VrefLevel [Byte0]: 41
7918 13:57:10.807850 [Byte1]: 41
7919 13:57:10.812492
7920 13:57:10.812570 Set Vref, RX VrefLevel [Byte0]: 42
7921 13:57:10.815390 [Byte1]: 42
7922 13:57:10.820094
7923 13:57:10.820215 Set Vref, RX VrefLevel [Byte0]: 43
7924 13:57:10.823074 [Byte1]: 43
7925 13:57:10.827636
7926 13:57:10.827739 Set Vref, RX VrefLevel [Byte0]: 44
7927 13:57:10.830805 [Byte1]: 44
7928 13:57:10.834926
7929 13:57:10.838304 Set Vref, RX VrefLevel [Byte0]: 45
7930 13:57:10.841738 [Byte1]: 45
7931 13:57:10.841848
7932 13:57:10.845111 Set Vref, RX VrefLevel [Byte0]: 46
7933 13:57:10.848030 [Byte1]: 46
7934 13:57:10.848115
7935 13:57:10.851619 Set Vref, RX VrefLevel [Byte0]: 47
7936 13:57:10.854969 [Byte1]: 47
7937 13:57:10.855067
7938 13:57:10.858386 Set Vref, RX VrefLevel [Byte0]: 48
7939 13:57:10.861565 [Byte1]: 48
7940 13:57:10.865470
7941 13:57:10.865600 Set Vref, RX VrefLevel [Byte0]: 49
7942 13:57:10.868914 [Byte1]: 49
7943 13:57:10.873393
7944 13:57:10.873539 Set Vref, RX VrefLevel [Byte0]: 50
7945 13:57:10.876613 [Byte1]: 50
7946 13:57:10.880693
7947 13:57:10.880810 Set Vref, RX VrefLevel [Byte0]: 51
7948 13:57:10.883949 [Byte1]: 51
7949 13:57:10.888401
7950 13:57:10.888486 Set Vref, RX VrefLevel [Byte0]: 52
7951 13:57:10.891702 [Byte1]: 52
7952 13:57:10.895917
7953 13:57:10.895999 Set Vref, RX VrefLevel [Byte0]: 53
7954 13:57:10.899205 [Byte1]: 53
7955 13:57:10.903629
7956 13:57:10.903711 Set Vref, RX VrefLevel [Byte0]: 54
7957 13:57:10.907118 [Byte1]: 54
7958 13:57:10.911326
7959 13:57:10.911410 Set Vref, RX VrefLevel [Byte0]: 55
7960 13:57:10.914628 [Byte1]: 55
7961 13:57:10.918881
7962 13:57:10.918963 Set Vref, RX VrefLevel [Byte0]: 56
7963 13:57:10.922184 [Byte1]: 56
7964 13:57:10.926407
7965 13:57:10.926493 Set Vref, RX VrefLevel [Byte0]: 57
7966 13:57:10.929819 [Byte1]: 57
7967 13:57:10.933908
7968 13:57:10.937288 Set Vref, RX VrefLevel [Byte0]: 58
7969 13:57:10.940567 [Byte1]: 58
7970 13:57:10.940648
7971 13:57:10.943916 Set Vref, RX VrefLevel [Byte0]: 59
7972 13:57:10.947094 [Byte1]: 59
7973 13:57:10.947182
7974 13:57:10.950579 Set Vref, RX VrefLevel [Byte0]: 60
7975 13:57:10.953614 [Byte1]: 60
7976 13:57:10.957179
7977 13:57:10.957266 Set Vref, RX VrefLevel [Byte0]: 61
7978 13:57:10.960189 [Byte1]: 61
7979 13:57:10.964380
7980 13:57:10.964463 Set Vref, RX VrefLevel [Byte0]: 62
7981 13:57:10.967738 [Byte1]: 62
7982 13:57:10.972251
7983 13:57:10.972363 Set Vref, RX VrefLevel [Byte0]: 63
7984 13:57:10.975685 [Byte1]: 63
7985 13:57:10.979628
7986 13:57:10.979714 Set Vref, RX VrefLevel [Byte0]: 64
7987 13:57:10.983257 [Byte1]: 64
7988 13:57:10.987581
7989 13:57:10.987696 Set Vref, RX VrefLevel [Byte0]: 65
7990 13:57:10.990725 [Byte1]: 65
7991 13:57:10.995069
7992 13:57:10.995158 Set Vref, RX VrefLevel [Byte0]: 66
7993 13:57:10.998497 [Byte1]: 66
7994 13:57:11.002631
7995 13:57:11.002717 Set Vref, RX VrefLevel [Byte0]: 67
7996 13:57:11.005956 [Byte1]: 67
7997 13:57:11.010250
7998 13:57:11.010337 Set Vref, RX VrefLevel [Byte0]: 68
7999 13:57:11.013333 [Byte1]: 68
8000 13:57:11.017629
8001 13:57:11.017718 Set Vref, RX VrefLevel [Byte0]: 69
8002 13:57:11.021033 [Byte1]: 69
8003 13:57:11.025424
8004 13:57:11.025549 Set Vref, RX VrefLevel [Byte0]: 70
8005 13:57:11.028736 [Byte1]: 70
8006 13:57:11.032840
8007 13:57:11.032927 Set Vref, RX VrefLevel [Byte0]: 71
8008 13:57:11.036128 [Byte1]: 71
8009 13:57:11.040697
8010 13:57:11.040785 Set Vref, RX VrefLevel [Byte0]: 72
8011 13:57:11.043971 [Byte1]: 72
8012 13:57:11.048472
8013 13:57:11.048597 Set Vref, RX VrefLevel [Byte0]: 73
8014 13:57:11.051636 [Byte1]: 73
8015 13:57:11.055698
8016 13:57:11.055785 Set Vref, RX VrefLevel [Byte0]: 74
8017 13:57:11.059280 [Byte1]: 74
8018 13:57:11.063491
8019 13:57:11.063579 Set Vref, RX VrefLevel [Byte0]: 75
8020 13:57:11.066684 [Byte1]: 75
8021 13:57:11.071207
8022 13:57:11.071303 Set Vref, RX VrefLevel [Byte0]: 76
8023 13:57:11.074298 [Byte1]: 76
8024 13:57:11.078742
8025 13:57:11.078830 Set Vref, RX VrefLevel [Byte0]: 77
8026 13:57:11.082007 [Byte1]: 77
8027 13:57:11.086473
8028 13:57:11.086566 Final RX Vref Byte 0 = 64 to rank0
8029 13:57:11.089561 Final RX Vref Byte 1 = 61 to rank0
8030 13:57:11.092849 Final RX Vref Byte 0 = 64 to rank1
8031 13:57:11.096044 Final RX Vref Byte 1 = 61 to rank1==
8032 13:57:11.099363 Dram Type= 6, Freq= 0, CH_0, rank 0
8033 13:57:11.106236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 13:57:11.106334 ==
8035 13:57:11.106401 DQS Delay:
8036 13:57:11.109578 DQS0 = 0, DQS1 = 0
8037 13:57:11.109663 DQM Delay:
8038 13:57:11.109729 DQM0 = 126, DQM1 = 120
8039 13:57:11.112867 DQ Delay:
8040 13:57:11.115986 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8041 13:57:11.119503 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8042 13:57:11.122548 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =116
8043 13:57:11.125881 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8044 13:57:11.125966
8045 13:57:11.126031
8046 13:57:11.126091
8047 13:57:11.129156 [DramC_TX_OE_Calibration] TA2
8048 13:57:11.132612 Original DQ_B0 (3 6) =30, OEN = 27
8049 13:57:11.135995 Original DQ_B1 (3 6) =30, OEN = 27
8050 13:57:11.139302 24, 0x0, End_B0=24 End_B1=24
8051 13:57:11.139388 25, 0x0, End_B0=25 End_B1=25
8052 13:57:11.142622 26, 0x0, End_B0=26 End_B1=26
8053 13:57:11.146006 27, 0x0, End_B0=27 End_B1=27
8054 13:57:11.149024 28, 0x0, End_B0=28 End_B1=28
8055 13:57:11.152453 29, 0x0, End_B0=29 End_B1=29
8056 13:57:11.152541 30, 0x0, End_B0=30 End_B1=30
8057 13:57:11.155748 31, 0x4141, End_B0=30 End_B1=30
8058 13:57:11.159053 Byte0 end_step=30 best_step=27
8059 13:57:11.162317 Byte1 end_step=30 best_step=27
8060 13:57:11.165687 Byte0 TX OE(2T, 0.5T) = (3, 3)
8061 13:57:11.168985 Byte1 TX OE(2T, 0.5T) = (3, 3)
8062 13:57:11.169072
8063 13:57:11.169137
8064 13:57:11.175671 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8065 13:57:11.178693 CH0 RK0: MR19=303, MR18=1211
8066 13:57:11.185662 CH0_RK0: MR19=0x303, MR18=0x1211, DQSOSC=400, MR23=63, INC=23, DEC=15
8067 13:57:11.185755
8068 13:57:11.188980 ----->DramcWriteLeveling(PI) begin...
8069 13:57:11.189093 ==
8070 13:57:11.192130 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 13:57:11.195642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 13:57:11.195728 ==
8073 13:57:11.198707 Write leveling (Byte 0): 35 => 35
8074 13:57:11.201975 Write leveling (Byte 1): 27 => 27
8075 13:57:11.205333 DramcWriteLeveling(PI) end<-----
8076 13:57:11.205417
8077 13:57:11.205520 ==
8078 13:57:11.208534 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 13:57:11.211941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 13:57:11.212043 ==
8081 13:57:11.215485 [Gating] SW mode calibration
8082 13:57:11.221797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8083 13:57:11.228529 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8084 13:57:11.231944 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 13:57:11.238629 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 13:57:11.242001 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 13:57:11.245200 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8088 13:57:11.251923 1 4 16 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
8089 13:57:11.255306 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8090 13:57:11.258650 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8091 13:57:11.264981 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8092 13:57:11.268340 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8093 13:57:11.271702 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8094 13:57:11.278261 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8095 13:57:11.281529 1 5 12 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
8096 13:57:11.285112 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8097 13:57:11.291302 1 5 20 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
8098 13:57:11.294750 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 13:57:11.298023 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 13:57:11.304567 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 13:57:11.308305 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 13:57:11.311204 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8103 13:57:11.317966 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8104 13:57:11.321304 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8105 13:57:11.324464 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 13:57:11.327855 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 13:57:11.334709 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 13:57:11.338026 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 13:57:11.341354 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 13:57:11.347773 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 13:57:11.351339 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8112 13:57:11.354652 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8113 13:57:11.360985 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8114 13:57:11.364255 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 13:57:11.367905 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 13:57:11.374300 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 13:57:11.377575 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 13:57:11.380819 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 13:57:11.387563 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 13:57:11.390782 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 13:57:11.394132 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 13:57:11.400626 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 13:57:11.404376 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 13:57:11.407559 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 13:57:11.414241 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 13:57:11.417537 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8127 13:57:11.420590 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8128 13:57:11.427255 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8129 13:57:11.427342 Total UI for P1: 0, mck2ui 16
8130 13:57:11.434014 best dqsien dly found for B0: ( 1, 9, 10)
8131 13:57:11.437443 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 13:57:11.440487 Total UI for P1: 0, mck2ui 16
8133 13:57:11.444037 best dqsien dly found for B1: ( 1, 9, 16)
8134 13:57:11.447218 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8135 13:57:11.450731 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8136 13:57:11.450814
8137 13:57:11.453921 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8138 13:57:11.457151 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8139 13:57:11.460720 [Gating] SW calibration Done
8140 13:57:11.460803 ==
8141 13:57:11.463685 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 13:57:11.466980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 13:57:11.470601 ==
8144 13:57:11.470689 RX Vref Scan: 0
8145 13:57:11.470772
8146 13:57:11.473641 RX Vref 0 -> 0, step: 1
8147 13:57:11.473723
8148 13:57:11.477362 RX Delay 0 -> 252, step: 8
8149 13:57:11.480325 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8150 13:57:11.483655 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8151 13:57:11.487353 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8152 13:57:11.490325 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8153 13:57:11.496878 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8154 13:57:11.500236 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8155 13:57:11.503515 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8156 13:57:11.506849 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8157 13:57:11.510064 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8158 13:57:11.517005 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8159 13:57:11.519992 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8160 13:57:11.523304 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8161 13:57:11.526695 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8162 13:57:11.530060 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8163 13:57:11.536711 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8164 13:57:11.540134 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8165 13:57:11.540217 ==
8166 13:57:11.543476 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 13:57:11.546373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 13:57:11.546456 ==
8169 13:57:11.549676 DQS Delay:
8170 13:57:11.549788 DQS0 = 0, DQS1 = 0
8171 13:57:11.549856 DQM Delay:
8172 13:57:11.553065 DQM0 = 127, DQM1 = 121
8173 13:57:11.553147 DQ Delay:
8174 13:57:11.556628 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8175 13:57:11.559920 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8176 13:57:11.566423 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
8177 13:57:11.569914 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8178 13:57:11.570005
8179 13:57:11.570084
8180 13:57:11.570144 ==
8181 13:57:11.573092 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 13:57:11.576561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 13:57:11.576644 ==
8184 13:57:11.576709
8185 13:57:11.576785
8186 13:57:11.579792 TX Vref Scan disable
8187 13:57:11.579875 == TX Byte 0 ==
8188 13:57:11.586275 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8189 13:57:11.589935 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8190 13:57:11.590018 == TX Byte 1 ==
8191 13:57:11.597438 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8192 13:57:11.599845 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8193 13:57:11.599928 ==
8194 13:57:11.603004 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 13:57:11.606324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 13:57:11.606407 ==
8197 13:57:11.621293
8198 13:57:11.624455 TX Vref early break, caculate TX vref
8199 13:57:11.627750 TX Vref=16, minBit 8, minWin=21, winSum=367
8200 13:57:11.631407 TX Vref=18, minBit 8, minWin=22, winSum=375
8201 13:57:11.634674 TX Vref=20, minBit 8, minWin=22, winSum=382
8202 13:57:11.637633 TX Vref=22, minBit 8, minWin=23, winSum=390
8203 13:57:11.641341 TX Vref=24, minBit 8, minWin=24, winSum=403
8204 13:57:11.647777 TX Vref=26, minBit 8, minWin=24, winSum=406
8205 13:57:11.651182 TX Vref=28, minBit 8, minWin=24, winSum=409
8206 13:57:11.654133 TX Vref=30, minBit 11, minWin=24, winSum=409
8207 13:57:11.657790 TX Vref=32, minBit 8, minWin=22, winSum=400
8208 13:57:11.660819 TX Vref=34, minBit 8, minWin=23, winSum=387
8209 13:57:11.667652 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 28
8210 13:57:11.667742
8211 13:57:11.670825 Final TX Range 0 Vref 28
8212 13:57:11.670911
8213 13:57:11.670977 ==
8214 13:57:11.674060 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 13:57:11.677343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 13:57:11.677427 ==
8217 13:57:11.677521
8218 13:57:11.677598
8219 13:57:11.680832 TX Vref Scan disable
8220 13:57:11.687327 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8221 13:57:11.687412 == TX Byte 0 ==
8222 13:57:11.690768 u2DelayCellOfst[0]=11 cells (3 PI)
8223 13:57:11.693775 u2DelayCellOfst[1]=18 cells (5 PI)
8224 13:57:11.697207 u2DelayCellOfst[2]=11 cells (3 PI)
8225 13:57:11.701027 u2DelayCellOfst[3]=11 cells (3 PI)
8226 13:57:11.703889 u2DelayCellOfst[4]=7 cells (2 PI)
8227 13:57:11.707182 u2DelayCellOfst[5]=0 cells (0 PI)
8228 13:57:11.710658 u2DelayCellOfst[6]=18 cells (5 PI)
8229 13:57:11.713596 u2DelayCellOfst[7]=15 cells (4 PI)
8230 13:57:11.716912 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8231 13:57:11.720263 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8232 13:57:11.723653 == TX Byte 1 ==
8233 13:57:11.727101 u2DelayCellOfst[8]=0 cells (0 PI)
8234 13:57:11.730498 u2DelayCellOfst[9]=0 cells (0 PI)
8235 13:57:11.730582 u2DelayCellOfst[10]=7 cells (2 PI)
8236 13:57:11.733734 u2DelayCellOfst[11]=7 cells (2 PI)
8237 13:57:11.736922 u2DelayCellOfst[12]=15 cells (4 PI)
8238 13:57:11.740323 u2DelayCellOfst[13]=11 cells (3 PI)
8239 13:57:11.743975 u2DelayCellOfst[14]=15 cells (4 PI)
8240 13:57:11.747130 u2DelayCellOfst[15]=11 cells (3 PI)
8241 13:57:11.750551 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8242 13:57:11.756908 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8243 13:57:11.757000 DramC Write-DBI on
8244 13:57:11.757066 ==
8245 13:57:11.760171 Dram Type= 6, Freq= 0, CH_0, rank 1
8246 13:57:11.767005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 13:57:11.767090 ==
8248 13:57:11.767155
8249 13:57:11.767215
8250 13:57:11.767273 TX Vref Scan disable
8251 13:57:11.770934 == TX Byte 0 ==
8252 13:57:11.774027 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8253 13:57:11.777682 == TX Byte 1 ==
8254 13:57:11.780898 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8255 13:57:11.784220 DramC Write-DBI off
8256 13:57:11.784330
8257 13:57:11.784423 [DATLAT]
8258 13:57:11.784511 Freq=1600, CH0 RK1
8259 13:57:11.784597
8260 13:57:11.787577 DATLAT Default: 0xf
8261 13:57:11.787658 0, 0xFFFF, sum = 0
8262 13:57:11.790549 1, 0xFFFF, sum = 0
8263 13:57:11.794099 2, 0xFFFF, sum = 0
8264 13:57:11.794183 3, 0xFFFF, sum = 0
8265 13:57:11.797272 4, 0xFFFF, sum = 0
8266 13:57:11.797382 5, 0xFFFF, sum = 0
8267 13:57:11.800589 6, 0xFFFF, sum = 0
8268 13:57:11.800672 7, 0xFFFF, sum = 0
8269 13:57:11.803875 8, 0xFFFF, sum = 0
8270 13:57:11.803958 9, 0xFFFF, sum = 0
8271 13:57:11.807367 10, 0xFFFF, sum = 0
8272 13:57:11.807450 11, 0xFFFF, sum = 0
8273 13:57:11.810713 12, 0xFFFF, sum = 0
8274 13:57:11.810798 13, 0xCFFF, sum = 0
8275 13:57:11.813973 14, 0x0, sum = 1
8276 13:57:11.814134 15, 0x0, sum = 2
8277 13:57:11.817324 16, 0x0, sum = 3
8278 13:57:11.817414 17, 0x0, sum = 4
8279 13:57:11.820716 best_step = 15
8280 13:57:11.820822
8281 13:57:11.820890 ==
8282 13:57:11.823997 Dram Type= 6, Freq= 0, CH_0, rank 1
8283 13:57:11.827372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 13:57:11.827457 ==
8285 13:57:11.827528 RX Vref Scan: 0
8286 13:57:11.830728
8287 13:57:11.830837 RX Vref 0 -> 0, step: 1
8288 13:57:11.830932
8289 13:57:11.834160 RX Delay 3 -> 252, step: 4
8290 13:57:11.837495 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8291 13:57:11.843851 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8292 13:57:11.847096 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8293 13:57:11.850907 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8294 13:57:11.854031 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8295 13:57:11.857347 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8296 13:57:11.864040 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8297 13:57:11.867236 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8298 13:57:11.870597 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8299 13:57:11.873862 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8300 13:57:11.877249 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8301 13:57:11.883620 iDelay=191, Bit 11, Center 110 (55 ~ 166) 112
8302 13:57:11.887138 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8303 13:57:11.890721 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8304 13:57:11.894056 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8305 13:57:11.897172 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8306 13:57:11.900462 ==
8307 13:57:11.903914 Dram Type= 6, Freq= 0, CH_0, rank 1
8308 13:57:11.907141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 13:57:11.907230 ==
8310 13:57:11.907296 DQS Delay:
8311 13:57:11.910452 DQS0 = 0, DQS1 = 0
8312 13:57:11.910536 DQM Delay:
8313 13:57:11.913761 DQM0 = 124, DQM1 = 117
8314 13:57:11.913850 DQ Delay:
8315 13:57:11.916941 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8316 13:57:11.920365 DQ4 =126, DQ5 =112, DQ6 =134, DQ7 =134
8317 13:57:11.923567 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =110
8318 13:57:11.926942 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8319 13:57:11.927027
8320 13:57:11.927094
8321 13:57:11.927156
8322 13:57:11.930356 [DramC_TX_OE_Calibration] TA2
8323 13:57:11.933709 Original DQ_B0 (3 6) =30, OEN = 27
8324 13:57:11.937059 Original DQ_B1 (3 6) =30, OEN = 27
8325 13:57:11.940084 24, 0x0, End_B0=24 End_B1=24
8326 13:57:11.943554 25, 0x0, End_B0=25 End_B1=25
8327 13:57:11.943640 26, 0x0, End_B0=26 End_B1=26
8328 13:57:11.946787 27, 0x0, End_B0=27 End_B1=27
8329 13:57:11.950186 28, 0x0, End_B0=28 End_B1=28
8330 13:57:11.953429 29, 0x0, End_B0=29 End_B1=29
8331 13:57:11.956851 30, 0x0, End_B0=30 End_B1=30
8332 13:57:11.956968 31, 0x4141, End_B0=30 End_B1=30
8333 13:57:11.960044 Byte0 end_step=30 best_step=27
8334 13:57:11.963261 Byte1 end_step=30 best_step=27
8335 13:57:11.966609 Byte0 TX OE(2T, 0.5T) = (3, 3)
8336 13:57:11.969941 Byte1 TX OE(2T, 0.5T) = (3, 3)
8337 13:57:11.970032
8338 13:57:11.970098
8339 13:57:11.976647 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8340 13:57:11.979847 CH0 RK1: MR19=303, MR18=220F
8341 13:57:11.986457 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8342 13:57:11.989706 [RxdqsGatingPostProcess] freq 1600
8343 13:57:11.996441 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8344 13:57:11.996530 best DQS0 dly(2T, 0.5T) = (1, 1)
8345 13:57:11.999872 best DQS1 dly(2T, 0.5T) = (1, 1)
8346 13:57:12.003011 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8347 13:57:12.006292 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8348 13:57:12.009513 best DQS0 dly(2T, 0.5T) = (1, 1)
8349 13:57:12.012826 best DQS1 dly(2T, 0.5T) = (1, 1)
8350 13:57:12.016288 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8351 13:57:12.019615 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8352 13:57:12.023208 Pre-setting of DQS Precalculation
8353 13:57:12.026401 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8354 13:57:12.026504 ==
8355 13:57:12.029657 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 13:57:12.036364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 13:57:12.036482 ==
8358 13:57:12.039841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8359 13:57:12.046022 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8360 13:57:12.049417 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8361 13:57:12.056155 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8362 13:57:12.064000 [CA 0] Center 41 (12~71) winsize 60
8363 13:57:12.067275 [CA 1] Center 42 (13~72) winsize 60
8364 13:57:12.070606 [CA 2] Center 38 (9~67) winsize 59
8365 13:57:12.074056 [CA 3] Center 37 (8~67) winsize 60
8366 13:57:12.077106 [CA 4] Center 38 (9~67) winsize 59
8367 13:57:12.080712 [CA 5] Center 36 (7~66) winsize 60
8368 13:57:12.080863
8369 13:57:12.083878 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8370 13:57:12.083961
8371 13:57:12.087122 [CATrainingPosCal] consider 1 rank data
8372 13:57:12.090552 u2DelayCellTimex100 = 258/100 ps
8373 13:57:12.093907 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8374 13:57:12.100585 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8375 13:57:12.103812 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8376 13:57:12.106958 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8377 13:57:12.110306 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8378 13:57:12.113779 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8379 13:57:12.113861
8380 13:57:12.117048 CA PerBit enable=1, Macro0, CA PI delay=36
8381 13:57:12.117129
8382 13:57:12.120323 [CBTSetCACLKResult] CA Dly = 36
8383 13:57:12.123696 CS Dly: 10 (0~41)
8384 13:57:12.126951 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8385 13:57:12.130240 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8386 13:57:12.130322 ==
8387 13:57:12.133594 Dram Type= 6, Freq= 0, CH_1, rank 1
8388 13:57:12.136794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 13:57:12.140079 ==
8390 13:57:12.143573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8391 13:57:12.146768 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8392 13:57:12.153580 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8393 13:57:12.159822 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8394 13:57:12.167330 [CA 0] Center 42 (13~72) winsize 60
8395 13:57:12.170702 [CA 1] Center 42 (13~72) winsize 60
8396 13:57:12.173726 [CA 2] Center 38 (9~67) winsize 59
8397 13:57:12.177237 [CA 3] Center 36 (7~66) winsize 60
8398 13:57:12.180510 [CA 4] Center 38 (8~68) winsize 61
8399 13:57:12.183711 [CA 5] Center 36 (6~67) winsize 62
8400 13:57:12.183813
8401 13:57:12.186941 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8402 13:57:12.187071
8403 13:57:12.190284 [CATrainingPosCal] consider 2 rank data
8404 13:57:12.193399 u2DelayCellTimex100 = 258/100 ps
8405 13:57:12.196779 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8406 13:57:12.203770 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8407 13:57:12.207104 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8408 13:57:12.210407 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8409 13:57:12.213661 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8410 13:57:12.216965 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8411 13:57:12.217048
8412 13:57:12.220200 CA PerBit enable=1, Macro0, CA PI delay=36
8413 13:57:12.220284
8414 13:57:12.223563 [CBTSetCACLKResult] CA Dly = 36
8415 13:57:12.226737 CS Dly: 11 (0~43)
8416 13:57:12.230150 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8417 13:57:12.233286 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8418 13:57:12.233372
8419 13:57:12.236697 ----->DramcWriteLeveling(PI) begin...
8420 13:57:12.236805 ==
8421 13:57:12.240038 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 13:57:12.246842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 13:57:12.246930 ==
8424 13:57:12.249936 Write leveling (Byte 0): 25 => 25
8425 13:57:12.250019 Write leveling (Byte 1): 27 => 27
8426 13:57:12.253002 DramcWriteLeveling(PI) end<-----
8427 13:57:12.253084
8428 13:57:12.256521 ==
8429 13:57:12.259776 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 13:57:12.263029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 13:57:12.263112 ==
8432 13:57:12.266384 [Gating] SW mode calibration
8433 13:57:12.273052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8434 13:57:12.276343 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8435 13:57:12.283052 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 13:57:12.286015 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 13:57:12.289593 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 13:57:12.296051 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 13:57:12.299445 1 4 16 | B1->B0 | 3232 3232 | 1 1 | (1 1) (1 1)
8440 13:57:12.302560 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 13:57:12.309404 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 13:57:12.312857 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 13:57:12.315880 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 13:57:12.322414 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 13:57:12.325960 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 13:57:12.328878 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8447 13:57:12.335619 1 5 16 | B1->B0 | 2929 2525 | 0 0 | (0 1) (0 0)
8448 13:57:12.338858 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8449 13:57:12.342103 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 13:57:12.348684 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 13:57:12.352177 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 13:57:12.355159 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 13:57:12.362003 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 13:57:12.365211 1 6 12 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
8455 13:57:12.368743 1 6 16 | B1->B0 | 3f3f 4040 | 0 0 | (0 0) (0 0)
8456 13:57:12.375375 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 13:57:12.378303 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 13:57:12.381741 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 13:57:12.388547 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 13:57:12.391495 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 13:57:12.394851 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 13:57:12.401712 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8463 13:57:12.405090 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8464 13:57:12.407983 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 13:57:12.414534 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 13:57:12.418022 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 13:57:12.421433 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 13:57:12.427846 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 13:57:12.431417 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 13:57:12.434560 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 13:57:12.441216 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 13:57:12.444839 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 13:57:12.448074 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 13:57:12.454472 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 13:57:12.457839 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 13:57:12.461140 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 13:57:12.467741 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 13:57:12.471145 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 13:57:12.474335 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8480 13:57:12.480854 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8481 13:57:12.480968 Total UI for P1: 0, mck2ui 16
8482 13:57:12.487411 best dqsien dly found for B0: ( 1, 9, 16)
8483 13:57:12.490805 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 13:57:12.493854 Total UI for P1: 0, mck2ui 16
8485 13:57:12.497369 best dqsien dly found for B1: ( 1, 9, 18)
8486 13:57:12.500682 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8487 13:57:12.504156 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8488 13:57:12.504243
8489 13:57:12.507536 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8490 13:57:12.510485 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8491 13:57:12.514166 [Gating] SW calibration Done
8492 13:57:12.514252 ==
8493 13:57:12.517042 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 13:57:12.523730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 13:57:12.523815 ==
8496 13:57:12.523889 RX Vref Scan: 0
8497 13:57:12.523956
8498 13:57:12.527074 RX Vref 0 -> 0, step: 1
8499 13:57:12.527146
8500 13:57:12.530238 RX Delay 0 -> 252, step: 8
8501 13:57:12.533825 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8502 13:57:12.537194 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8503 13:57:12.540544 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8504 13:57:12.543873 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8505 13:57:12.550268 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8506 13:57:12.553528 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8507 13:57:12.556903 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8508 13:57:12.560280 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8509 13:57:12.563632 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8510 13:57:12.570308 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8511 13:57:12.573263 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8512 13:57:12.576566 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8513 13:57:12.579979 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8514 13:57:12.583342 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8515 13:57:12.589738 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8516 13:57:12.593310 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8517 13:57:12.593463 ==
8518 13:57:12.596482 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 13:57:12.599845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 13:57:12.599966 ==
8521 13:57:12.603218 DQS Delay:
8522 13:57:12.603337 DQS0 = 0, DQS1 = 0
8523 13:57:12.603440 DQM Delay:
8524 13:57:12.606637 DQM0 = 131, DQM1 = 123
8525 13:57:12.606786 DQ Delay:
8526 13:57:12.609730 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8527 13:57:12.612979 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8528 13:57:12.619595 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
8529 13:57:12.623095 DQ12 =135, DQ13 =131, DQ14 =131, DQ15 =131
8530 13:57:12.623221
8531 13:57:12.623321
8532 13:57:12.623424 ==
8533 13:57:12.626495 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 13:57:12.629721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 13:57:12.629811 ==
8536 13:57:12.629878
8537 13:57:12.629948
8538 13:57:12.633106 TX Vref Scan disable
8539 13:57:12.636452 == TX Byte 0 ==
8540 13:57:12.639350 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8541 13:57:12.642937 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8542 13:57:12.646298 == TX Byte 1 ==
8543 13:57:12.649447 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8544 13:57:12.653035 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8545 13:57:12.653157 ==
8546 13:57:12.656248 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 13:57:12.659442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 13:57:12.662600 ==
8549 13:57:12.674613
8550 13:57:12.678322 TX Vref early break, caculate TX vref
8551 13:57:12.681521 TX Vref=16, minBit 0, minWin=22, winSum=363
8552 13:57:12.684841 TX Vref=18, minBit 1, minWin=22, winSum=368
8553 13:57:12.688166 TX Vref=20, minBit 1, minWin=23, winSum=382
8554 13:57:12.691159 TX Vref=22, minBit 1, minWin=24, winSum=398
8555 13:57:12.694451 TX Vref=24, minBit 5, minWin=24, winSum=404
8556 13:57:12.701450 TX Vref=26, minBit 1, minWin=24, winSum=411
8557 13:57:12.704590 TX Vref=28, minBit 0, minWin=25, winSum=418
8558 13:57:12.707995 TX Vref=30, minBit 0, minWin=24, winSum=417
8559 13:57:12.711232 TX Vref=32, minBit 0, minWin=24, winSum=410
8560 13:57:12.714657 TX Vref=34, minBit 0, minWin=23, winSum=399
8561 13:57:12.717965 TX Vref=36, minBit 6, minWin=22, winSum=384
8562 13:57:12.724882 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8563 13:57:12.725013
8564 13:57:12.727886 Final TX Range 0 Vref 28
8565 13:57:12.727975
8566 13:57:12.728041 ==
8567 13:57:12.731435 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 13:57:12.734682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 13:57:12.734768 ==
8570 13:57:12.734835
8571 13:57:12.734896
8572 13:57:12.738131 TX Vref Scan disable
8573 13:57:12.744421 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8574 13:57:12.744522 == TX Byte 0 ==
8575 13:57:12.747623 u2DelayCellOfst[0]=22 cells (6 PI)
8576 13:57:12.751152 u2DelayCellOfst[1]=15 cells (4 PI)
8577 13:57:12.754681 u2DelayCellOfst[2]=0 cells (0 PI)
8578 13:57:12.757794 u2DelayCellOfst[3]=7 cells (2 PI)
8579 13:57:12.760927 u2DelayCellOfst[4]=11 cells (3 PI)
8580 13:57:12.764399 u2DelayCellOfst[5]=22 cells (6 PI)
8581 13:57:12.767592 u2DelayCellOfst[6]=22 cells (6 PI)
8582 13:57:12.770974 u2DelayCellOfst[7]=7 cells (2 PI)
8583 13:57:12.774216 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8584 13:57:12.777524 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8585 13:57:12.780762 == TX Byte 1 ==
8586 13:57:12.784230 u2DelayCellOfst[8]=0 cells (0 PI)
8587 13:57:12.787594 u2DelayCellOfst[9]=3 cells (1 PI)
8588 13:57:12.790765 u2DelayCellOfst[10]=11 cells (3 PI)
8589 13:57:12.790857 u2DelayCellOfst[11]=7 cells (2 PI)
8590 13:57:12.793946 u2DelayCellOfst[12]=15 cells (4 PI)
8591 13:57:12.797173 u2DelayCellOfst[13]=18 cells (5 PI)
8592 13:57:12.800794 u2DelayCellOfst[14]=18 cells (5 PI)
8593 13:57:12.804003 u2DelayCellOfst[15]=18 cells (5 PI)
8594 13:57:12.810572 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8595 13:57:12.813923 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8596 13:57:12.814042 DramC Write-DBI on
8597 13:57:12.814114 ==
8598 13:57:12.817318 Dram Type= 6, Freq= 0, CH_1, rank 0
8599 13:57:12.823699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8600 13:57:12.823807 ==
8601 13:57:12.823876
8602 13:57:12.823963
8603 13:57:12.827161 TX Vref Scan disable
8604 13:57:12.827254 == TX Byte 0 ==
8605 13:57:12.833770 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8606 13:57:12.833884 == TX Byte 1 ==
8607 13:57:12.837084 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8608 13:57:12.840518 DramC Write-DBI off
8609 13:57:12.840614
8610 13:57:12.840682 [DATLAT]
8611 13:57:12.843478 Freq=1600, CH1 RK0
8612 13:57:12.843566
8613 13:57:12.843633 DATLAT Default: 0xf
8614 13:57:12.846757 0, 0xFFFF, sum = 0
8615 13:57:12.846877 1, 0xFFFF, sum = 0
8616 13:57:12.850030 2, 0xFFFF, sum = 0
8617 13:57:12.850119 3, 0xFFFF, sum = 0
8618 13:57:12.853295 4, 0xFFFF, sum = 0
8619 13:57:12.853414 5, 0xFFFF, sum = 0
8620 13:57:12.856655 6, 0xFFFF, sum = 0
8621 13:57:12.856739 7, 0xFFFF, sum = 0
8622 13:57:12.860250 8, 0xFFFF, sum = 0
8623 13:57:12.860340 9, 0xFFFF, sum = 0
8624 13:57:12.863297 10, 0xFFFF, sum = 0
8625 13:57:12.866730 11, 0xFFFF, sum = 0
8626 13:57:12.866827 12, 0xFFFF, sum = 0
8627 13:57:12.869861 13, 0x8FFF, sum = 0
8628 13:57:12.869952 14, 0x0, sum = 1
8629 13:57:12.873343 15, 0x0, sum = 2
8630 13:57:12.873484 16, 0x0, sum = 3
8631 13:57:12.876769 17, 0x0, sum = 4
8632 13:57:12.876885 best_step = 15
8633 13:57:12.876983
8634 13:57:12.877077 ==
8635 13:57:12.879968 Dram Type= 6, Freq= 0, CH_1, rank 0
8636 13:57:12.883345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8637 13:57:12.883466 ==
8638 13:57:12.886493 RX Vref Scan: 1
8639 13:57:12.886580
8640 13:57:12.889907 Set Vref Range= 24 -> 127
8641 13:57:12.889987
8642 13:57:12.890050 RX Vref 24 -> 127, step: 1
8643 13:57:12.890111
8644 13:57:12.893233 RX Delay 3 -> 252, step: 4
8645 13:57:12.893308
8646 13:57:12.896328 Set Vref, RX VrefLevel [Byte0]: 24
8647 13:57:12.899578 [Byte1]: 24
8648 13:57:12.903184
8649 13:57:12.903273 Set Vref, RX VrefLevel [Byte0]: 25
8650 13:57:12.906380 [Byte1]: 25
8651 13:57:12.910918
8652 13:57:12.911016 Set Vref, RX VrefLevel [Byte0]: 26
8653 13:57:12.914093 [Byte1]: 26
8654 13:57:12.918568
8655 13:57:12.918662 Set Vref, RX VrefLevel [Byte0]: 27
8656 13:57:12.921496 [Byte1]: 27
8657 13:57:12.926020
8658 13:57:12.926135 Set Vref, RX VrefLevel [Byte0]: 28
8659 13:57:12.929500 [Byte1]: 28
8660 13:57:12.933648
8661 13:57:12.933739 Set Vref, RX VrefLevel [Byte0]: 29
8662 13:57:12.936995 [Byte1]: 29
8663 13:57:12.941325
8664 13:57:12.941447 Set Vref, RX VrefLevel [Byte0]: 30
8665 13:57:12.944735 [Byte1]: 30
8666 13:57:12.948878
8667 13:57:12.948970 Set Vref, RX VrefLevel [Byte0]: 31
8668 13:57:12.952178 [Byte1]: 31
8669 13:57:12.956792
8670 13:57:12.956883 Set Vref, RX VrefLevel [Byte0]: 32
8671 13:57:12.960024 [Byte1]: 32
8672 13:57:12.964449
8673 13:57:12.964560 Set Vref, RX VrefLevel [Byte0]: 33
8674 13:57:12.967537 [Byte1]: 33
8675 13:57:12.971853
8676 13:57:12.971950 Set Vref, RX VrefLevel [Byte0]: 34
8677 13:57:12.975543 [Byte1]: 34
8678 13:57:12.979448
8679 13:57:12.979560 Set Vref, RX VrefLevel [Byte0]: 35
8680 13:57:12.983015 [Byte1]: 35
8681 13:57:12.987236
8682 13:57:12.987324 Set Vref, RX VrefLevel [Byte0]: 36
8683 13:57:12.990496 [Byte1]: 36
8684 13:57:12.994769
8685 13:57:12.994882 Set Vref, RX VrefLevel [Byte0]: 37
8686 13:57:12.998124 [Byte1]: 37
8687 13:57:13.002795
8688 13:57:13.002880 Set Vref, RX VrefLevel [Byte0]: 38
8689 13:57:13.005993 [Byte1]: 38
8690 13:57:13.010355
8691 13:57:13.010480 Set Vref, RX VrefLevel [Byte0]: 39
8692 13:57:13.013603 [Byte1]: 39
8693 13:57:13.017738
8694 13:57:13.017837 Set Vref, RX VrefLevel [Byte0]: 40
8695 13:57:13.021082 [Byte1]: 40
8696 13:57:13.025509
8697 13:57:13.025615 Set Vref, RX VrefLevel [Byte0]: 41
8698 13:57:13.028912 [Byte1]: 41
8699 13:57:13.033470
8700 13:57:13.033622 Set Vref, RX VrefLevel [Byte0]: 42
8701 13:57:13.036477 [Byte1]: 42
8702 13:57:13.041062
8703 13:57:13.041159 Set Vref, RX VrefLevel [Byte0]: 43
8704 13:57:13.044212 [Byte1]: 43
8705 13:57:13.048616
8706 13:57:13.048722 Set Vref, RX VrefLevel [Byte0]: 44
8707 13:57:13.051896 [Byte1]: 44
8708 13:57:13.056149
8709 13:57:13.056252 Set Vref, RX VrefLevel [Byte0]: 45
8710 13:57:13.059591 [Byte1]: 45
8711 13:57:13.063938
8712 13:57:13.064028 Set Vref, RX VrefLevel [Byte0]: 46
8713 13:57:13.066941 [Byte1]: 46
8714 13:57:13.071444
8715 13:57:13.071573 Set Vref, RX VrefLevel [Byte0]: 47
8716 13:57:13.074604 [Byte1]: 47
8717 13:57:13.079153
8718 13:57:13.079278 Set Vref, RX VrefLevel [Byte0]: 48
8719 13:57:13.082408 [Byte1]: 48
8720 13:57:13.086895
8721 13:57:13.087028 Set Vref, RX VrefLevel [Byte0]: 49
8722 13:57:13.089917 [Byte1]: 49
8723 13:57:13.094645
8724 13:57:13.094762 Set Vref, RX VrefLevel [Byte0]: 50
8725 13:57:13.097807 [Byte1]: 50
8726 13:57:13.102267
8727 13:57:13.102369 Set Vref, RX VrefLevel [Byte0]: 51
8728 13:57:13.105182 [Byte1]: 51
8729 13:57:13.109712
8730 13:57:13.109802 Set Vref, RX VrefLevel [Byte0]: 52
8731 13:57:13.112914 [Byte1]: 52
8732 13:57:13.117444
8733 13:57:13.117566 Set Vref, RX VrefLevel [Byte0]: 53
8734 13:57:13.120568 [Byte1]: 53
8735 13:57:13.125061
8736 13:57:13.125167 Set Vref, RX VrefLevel [Byte0]: 54
8737 13:57:13.128217 [Byte1]: 54
8738 13:57:13.132679
8739 13:57:13.132782 Set Vref, RX VrefLevel [Byte0]: 55
8740 13:57:13.135845 [Byte1]: 55
8741 13:57:13.140439
8742 13:57:13.140537 Set Vref, RX VrefLevel [Byte0]: 56
8743 13:57:13.143440 [Byte1]: 56
8744 13:57:13.147834
8745 13:57:13.147924 Set Vref, RX VrefLevel [Byte0]: 57
8746 13:57:13.151299 [Byte1]: 57
8747 13:57:13.155438
8748 13:57:13.155526 Set Vref, RX VrefLevel [Byte0]: 58
8749 13:57:13.158871 [Byte1]: 58
8750 13:57:13.163178
8751 13:57:13.163269 Set Vref, RX VrefLevel [Byte0]: 59
8752 13:57:13.166570 [Byte1]: 59
8753 13:57:13.170907
8754 13:57:13.171000 Set Vref, RX VrefLevel [Byte0]: 60
8755 13:57:13.174316 [Byte1]: 60
8756 13:57:13.178552
8757 13:57:13.178680 Set Vref, RX VrefLevel [Byte0]: 61
8758 13:57:13.181741 [Byte1]: 61
8759 13:57:13.186480
8760 13:57:13.186584 Set Vref, RX VrefLevel [Byte0]: 62
8761 13:57:13.189597 [Byte1]: 62
8762 13:57:13.193925
8763 13:57:13.194022 Set Vref, RX VrefLevel [Byte0]: 63
8764 13:57:13.197358 [Byte1]: 63
8765 13:57:13.201490
8766 13:57:13.201582 Set Vref, RX VrefLevel [Byte0]: 64
8767 13:57:13.204969 [Byte1]: 64
8768 13:57:13.209321
8769 13:57:13.209441 Set Vref, RX VrefLevel [Byte0]: 65
8770 13:57:13.212296 [Byte1]: 65
8771 13:57:13.216937
8772 13:57:13.217030 Set Vref, RX VrefLevel [Byte0]: 66
8773 13:57:13.220140 [Byte1]: 66
8774 13:57:13.224333
8775 13:57:13.224450 Set Vref, RX VrefLevel [Byte0]: 67
8776 13:57:13.227655 [Byte1]: 67
8777 13:57:13.232091
8778 13:57:13.232188 Set Vref, RX VrefLevel [Byte0]: 68
8779 13:57:13.235307 [Byte1]: 68
8780 13:57:13.239853
8781 13:57:13.239949 Set Vref, RX VrefLevel [Byte0]: 69
8782 13:57:13.243139 [Byte1]: 69
8783 13:57:13.247257
8784 13:57:13.247396 Set Vref, RX VrefLevel [Byte0]: 70
8785 13:57:13.250903 [Byte1]: 70
8786 13:57:13.254997
8787 13:57:13.255092 Final RX Vref Byte 0 = 56 to rank0
8788 13:57:13.258434 Final RX Vref Byte 1 = 55 to rank0
8789 13:57:13.261731 Final RX Vref Byte 0 = 56 to rank1
8790 13:57:13.265071 Final RX Vref Byte 1 = 55 to rank1==
8791 13:57:13.268494 Dram Type= 6, Freq= 0, CH_1, rank 0
8792 13:57:13.274881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 13:57:13.275051 ==
8794 13:57:13.275164 DQS Delay:
8795 13:57:13.275275 DQS0 = 0, DQS1 = 0
8796 13:57:13.278205 DQM Delay:
8797 13:57:13.278316 DQM0 = 130, DQM1 = 122
8798 13:57:13.281519 DQ Delay:
8799 13:57:13.284824 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8800 13:57:13.288508 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =126
8801 13:57:13.291621 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =114
8802 13:57:13.294827 DQ12 =130, DQ13 =130, DQ14 =130, DQ15 =130
8803 13:57:13.294948
8804 13:57:13.295019
8805 13:57:13.295082
8806 13:57:13.298214 [DramC_TX_OE_Calibration] TA2
8807 13:57:13.301508 Original DQ_B0 (3 6) =30, OEN = 27
8808 13:57:13.304867 Original DQ_B1 (3 6) =30, OEN = 27
8809 13:57:13.308154 24, 0x0, End_B0=24 End_B1=24
8810 13:57:13.308262 25, 0x0, End_B0=25 End_B1=25
8811 13:57:13.311474 26, 0x0, End_B0=26 End_B1=26
8812 13:57:13.314744 27, 0x0, End_B0=27 End_B1=27
8813 13:57:13.318165 28, 0x0, End_B0=28 End_B1=28
8814 13:57:13.318278 29, 0x0, End_B0=29 End_B1=29
8815 13:57:13.321528 30, 0x0, End_B0=30 End_B1=30
8816 13:57:13.324867 31, 0x4141, End_B0=30 End_B1=30
8817 13:57:13.328256 Byte0 end_step=30 best_step=27
8818 13:57:13.331560 Byte1 end_step=30 best_step=27
8819 13:57:13.334754 Byte0 TX OE(2T, 0.5T) = (3, 3)
8820 13:57:13.337962 Byte1 TX OE(2T, 0.5T) = (3, 3)
8821 13:57:13.338080
8822 13:57:13.338196
8823 13:57:13.344442 [DQSOSCAuto] RK0, (LSB)MR18= 0x90d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8824 13:57:13.348075 CH1 RK0: MR19=303, MR18=90D
8825 13:57:13.354538 CH1_RK0: MR19=0x303, MR18=0x90D, DQSOSC=403, MR23=63, INC=22, DEC=15
8826 13:57:13.354639
8827 13:57:13.357689 ----->DramcWriteLeveling(PI) begin...
8828 13:57:13.357798 ==
8829 13:57:13.361108 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 13:57:13.364440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 13:57:13.364540 ==
8832 13:57:13.367961 Write leveling (Byte 0): 23 => 23
8833 13:57:13.371200 Write leveling (Byte 1): 28 => 28
8834 13:57:13.374169 DramcWriteLeveling(PI) end<-----
8835 13:57:13.374298
8836 13:57:13.374391 ==
8837 13:57:13.377596 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 13:57:13.381028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 13:57:13.381148 ==
8840 13:57:13.384211 [Gating] SW mode calibration
8841 13:57:13.390859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8842 13:57:13.397336 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8843 13:57:13.400937 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 13:57:13.404306 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 13:57:13.410588 1 4 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8846 13:57:13.413822 1 4 12 | B1->B0 | 2e2d 3434 | 1 1 | (1 1) (1 1)
8847 13:57:13.420511 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 13:57:13.423685 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 13:57:13.427038 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 13:57:13.433810 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 13:57:13.437258 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 13:57:13.440466 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 13:57:13.446962 1 5 8 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 1)
8854 13:57:13.450120 1 5 12 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
8855 13:57:13.453388 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 13:57:13.457026 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 13:57:13.463712 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 13:57:13.466720 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 13:57:13.470232 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 13:57:13.476697 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8861 13:57:13.480122 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8862 13:57:13.483514 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8863 13:57:13.490134 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 13:57:13.493499 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 13:57:13.496721 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 13:57:13.503447 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 13:57:13.506500 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 13:57:13.509913 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 13:57:13.516388 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8870 13:57:13.519770 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8871 13:57:13.522981 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 13:57:13.529849 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 13:57:13.532840 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 13:57:13.536244 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 13:57:13.542795 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 13:57:13.545962 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 13:57:13.549644 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 13:57:13.555893 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 13:57:13.559585 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 13:57:13.562837 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 13:57:13.569259 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 13:57:13.572605 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 13:57:13.575622 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 13:57:13.582615 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 13:57:13.585540 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8886 13:57:13.589063 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8887 13:57:13.595526 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 13:57:13.599030 Total UI for P1: 0, mck2ui 16
8889 13:57:13.602415 best dqsien dly found for B0: ( 1, 9, 10)
8890 13:57:13.602567 Total UI for P1: 0, mck2ui 16
8891 13:57:13.608615 best dqsien dly found for B1: ( 1, 9, 14)
8892 13:57:13.612034 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8893 13:57:13.615404 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8894 13:57:13.615502
8895 13:57:13.618708 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8896 13:57:13.621888 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8897 13:57:13.625487 [Gating] SW calibration Done
8898 13:57:13.625595 ==
8899 13:57:13.628605 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 13:57:13.631968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 13:57:13.632062 ==
8902 13:57:13.635364 RX Vref Scan: 0
8903 13:57:13.635451
8904 13:57:13.635516 RX Vref 0 -> 0, step: 1
8905 13:57:13.638892
8906 13:57:13.638988 RX Delay 0 -> 252, step: 8
8907 13:57:13.645195 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8908 13:57:13.648442 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8909 13:57:13.651939 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8910 13:57:13.655155 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8911 13:57:13.658515 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8912 13:57:13.662010 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8913 13:57:13.668685 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8914 13:57:13.671888 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8915 13:57:13.675371 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8916 13:57:13.678367 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8917 13:57:13.681943 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8918 13:57:13.688704 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8919 13:57:13.692057 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8920 13:57:13.695439 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8921 13:57:13.698748 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8922 13:57:13.705085 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8923 13:57:13.705240 ==
8924 13:57:13.708519 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 13:57:13.711721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 13:57:13.711893 ==
8927 13:57:13.711999 DQS Delay:
8928 13:57:13.715283 DQS0 = 0, DQS1 = 0
8929 13:57:13.715417 DQM Delay:
8930 13:57:13.718698 DQM0 = 131, DQM1 = 127
8931 13:57:13.718815 DQ Delay:
8932 13:57:13.721509 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8933 13:57:13.724862 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8934 13:57:13.728604 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8935 13:57:13.731726 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8936 13:57:13.731839
8937 13:57:13.731933
8938 13:57:13.734985 ==
8939 13:57:13.738321 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 13:57:13.741674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 13:57:13.741797 ==
8942 13:57:13.741910
8943 13:57:13.742010
8944 13:57:13.744825 TX Vref Scan disable
8945 13:57:13.744943 == TX Byte 0 ==
8946 13:57:13.748085 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8947 13:57:13.754786 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8948 13:57:13.754925 == TX Byte 1 ==
8949 13:57:13.757888 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8950 13:57:13.764754 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8951 13:57:13.764872 ==
8952 13:57:13.768166 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 13:57:13.771544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 13:57:13.771671 ==
8955 13:57:13.786234
8956 13:57:13.789351 TX Vref early break, caculate TX vref
8957 13:57:13.792751 TX Vref=16, minBit 0, minWin=22, winSum=377
8958 13:57:13.796055 TX Vref=18, minBit 0, minWin=22, winSum=386
8959 13:57:13.799056 TX Vref=20, minBit 0, minWin=22, winSum=392
8960 13:57:13.802437 TX Vref=22, minBit 0, minWin=23, winSum=402
8961 13:57:13.805851 TX Vref=24, minBit 0, minWin=24, winSum=409
8962 13:57:13.812595 TX Vref=26, minBit 0, minWin=23, winSum=418
8963 13:57:13.815640 TX Vref=28, minBit 5, minWin=24, winSum=419
8964 13:57:13.818828 TX Vref=30, minBit 6, minWin=24, winSum=416
8965 13:57:13.822338 TX Vref=32, minBit 1, minWin=24, winSum=411
8966 13:57:13.825720 TX Vref=34, minBit 0, minWin=23, winSum=400
8967 13:57:13.829077 TX Vref=36, minBit 0, minWin=23, winSum=391
8968 13:57:13.835721 [TxChooseVref] Worse bit 5, Min win 24, Win sum 419, Final Vref 28
8969 13:57:13.835833
8970 13:57:13.838884 Final TX Range 0 Vref 28
8971 13:57:13.838986
8972 13:57:13.839053 ==
8973 13:57:13.842148 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 13:57:13.845864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 13:57:13.846006 ==
8976 13:57:13.846076
8977 13:57:13.849143
8978 13:57:13.849227 TX Vref Scan disable
8979 13:57:13.855453 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8980 13:57:13.855543 == TX Byte 0 ==
8981 13:57:13.858840 u2DelayCellOfst[0]=15 cells (4 PI)
8982 13:57:13.862055 u2DelayCellOfst[1]=18 cells (5 PI)
8983 13:57:13.865535 u2DelayCellOfst[2]=0 cells (0 PI)
8984 13:57:13.868861 u2DelayCellOfst[3]=7 cells (2 PI)
8985 13:57:13.872258 u2DelayCellOfst[4]=7 cells (2 PI)
8986 13:57:13.875241 u2DelayCellOfst[5]=26 cells (7 PI)
8987 13:57:13.878677 u2DelayCellOfst[6]=22 cells (6 PI)
8988 13:57:13.882009 u2DelayCellOfst[7]=7 cells (2 PI)
8989 13:57:13.885224 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8990 13:57:13.888813 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8991 13:57:13.892070 == TX Byte 1 ==
8992 13:57:13.895375 u2DelayCellOfst[8]=0 cells (0 PI)
8993 13:57:13.895504 u2DelayCellOfst[9]=7 cells (2 PI)
8994 13:57:13.898767 u2DelayCellOfst[10]=15 cells (4 PI)
8995 13:57:13.902145 u2DelayCellOfst[11]=7 cells (2 PI)
8996 13:57:13.905097 u2DelayCellOfst[12]=18 cells (5 PI)
8997 13:57:13.908503 u2DelayCellOfst[13]=18 cells (5 PI)
8998 13:57:13.911768 u2DelayCellOfst[14]=18 cells (5 PI)
8999 13:57:13.915265 u2DelayCellOfst[15]=22 cells (6 PI)
9000 13:57:13.921709 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9001 13:57:13.925037 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9002 13:57:13.925158 DramC Write-DBI on
9003 13:57:13.925253 ==
9004 13:57:13.928292 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 13:57:13.935001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 13:57:13.935156 ==
9007 13:57:13.935264
9008 13:57:13.935361
9009 13:57:13.935464 TX Vref Scan disable
9010 13:57:13.938985 == TX Byte 0 ==
9011 13:57:13.942525 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9012 13:57:13.945523 == TX Byte 1 ==
9013 13:57:13.949109 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9014 13:57:13.952181 DramC Write-DBI off
9015 13:57:13.952273
9016 13:57:13.952340 [DATLAT]
9017 13:57:13.952401 Freq=1600, CH1 RK1
9018 13:57:13.952461
9019 13:57:13.955596 DATLAT Default: 0xf
9020 13:57:13.955715 0, 0xFFFF, sum = 0
9021 13:57:13.958881 1, 0xFFFF, sum = 0
9022 13:57:13.962139 2, 0xFFFF, sum = 0
9023 13:57:13.962256 3, 0xFFFF, sum = 0
9024 13:57:13.965781 4, 0xFFFF, sum = 0
9025 13:57:13.965905 5, 0xFFFF, sum = 0
9026 13:57:13.968906 6, 0xFFFF, sum = 0
9027 13:57:13.969022 7, 0xFFFF, sum = 0
9028 13:57:13.972103 8, 0xFFFF, sum = 0
9029 13:57:13.972222 9, 0xFFFF, sum = 0
9030 13:57:13.975493 10, 0xFFFF, sum = 0
9031 13:57:13.975615 11, 0xFFFF, sum = 0
9032 13:57:13.978816 12, 0xFFFF, sum = 0
9033 13:57:13.978929 13, 0x8FFF, sum = 0
9034 13:57:13.982070 14, 0x0, sum = 1
9035 13:57:13.982187 15, 0x0, sum = 2
9036 13:57:13.985489 16, 0x0, sum = 3
9037 13:57:13.985603 17, 0x0, sum = 4
9038 13:57:13.988833 best_step = 15
9039 13:57:13.988942
9040 13:57:13.989045 ==
9041 13:57:13.992173 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 13:57:13.995350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 13:57:13.995465 ==
9044 13:57:13.998536 RX Vref Scan: 0
9045 13:57:13.998649
9046 13:57:13.998753 RX Vref 0 -> 0, step: 1
9047 13:57:13.998852
9048 13:57:14.001992 RX Delay 3 -> 252, step: 4
9049 13:57:14.008380 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9050 13:57:14.011828 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9051 13:57:14.015140 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9052 13:57:14.018435 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9053 13:57:14.021754 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9054 13:57:14.028555 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9055 13:57:14.031840 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9056 13:57:14.034888 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9057 13:57:14.038385 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9058 13:57:14.041650 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9059 13:57:14.048064 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
9060 13:57:14.051465 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9061 13:57:14.054765 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
9062 13:57:14.057959 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9063 13:57:14.061389 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9064 13:57:14.067914 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9065 13:57:14.068043 ==
9066 13:57:14.071389 Dram Type= 6, Freq= 0, CH_1, rank 1
9067 13:57:14.074541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9068 13:57:14.074668 ==
9069 13:57:14.074773 DQS Delay:
9070 13:57:14.078032 DQS0 = 0, DQS1 = 0
9071 13:57:14.078151 DQM Delay:
9072 13:57:14.081227 DQM0 = 128, DQM1 = 123
9073 13:57:14.081345 DQ Delay:
9074 13:57:14.084609 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =128
9075 13:57:14.088015 DQ4 =124, DQ5 =140, DQ6 =140, DQ7 =124
9076 13:57:14.091337 DQ8 =108, DQ9 =112, DQ10 =126, DQ11 =118
9077 13:57:14.094742 DQ12 =130, DQ13 =132, DQ14 =130, DQ15 =134
9078 13:57:14.094860
9079 13:57:14.098179
9080 13:57:14.098297
9081 13:57:14.098399 [DramC_TX_OE_Calibration] TA2
9082 13:57:14.101307 Original DQ_B0 (3 6) =30, OEN = 27
9083 13:57:14.104454 Original DQ_B1 (3 6) =30, OEN = 27
9084 13:57:14.108038 24, 0x0, End_B0=24 End_B1=24
9085 13:57:14.111038 25, 0x0, End_B0=25 End_B1=25
9086 13:57:14.114303 26, 0x0, End_B0=26 End_B1=26
9087 13:57:14.114420 27, 0x0, End_B0=27 End_B1=27
9088 13:57:14.117993 28, 0x0, End_B0=28 End_B1=28
9089 13:57:14.120911 29, 0x0, End_B0=29 End_B1=29
9090 13:57:14.124264 30, 0x0, End_B0=30 End_B1=30
9091 13:57:14.127650 31, 0x5151, End_B0=30 End_B1=30
9092 13:57:14.127765 Byte0 end_step=30 best_step=27
9093 13:57:14.131075 Byte1 end_step=30 best_step=27
9094 13:57:14.134396 Byte0 TX OE(2T, 0.5T) = (3, 3)
9095 13:57:14.137576 Byte1 TX OE(2T, 0.5T) = (3, 3)
9096 13:57:14.137694
9097 13:57:14.137794
9098 13:57:14.147797 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9099 13:57:14.147932 CH1 RK1: MR19=303, MR18=121E
9100 13:57:14.154031 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9101 13:57:14.157580 [RxdqsGatingPostProcess] freq 1600
9102 13:57:14.164380 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9103 13:57:14.167672 best DQS0 dly(2T, 0.5T) = (1, 1)
9104 13:57:14.170709 best DQS1 dly(2T, 0.5T) = (1, 1)
9105 13:57:14.170795 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9106 13:57:14.173988 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9107 13:57:14.177740 best DQS0 dly(2T, 0.5T) = (1, 1)
9108 13:57:14.180912 best DQS1 dly(2T, 0.5T) = (1, 1)
9109 13:57:14.184335 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9110 13:57:14.187657 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9111 13:57:14.190953 Pre-setting of DQS Precalculation
9112 13:57:14.197240 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9113 13:57:14.204024 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9114 13:57:14.210672 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 13:57:14.210767
9116 13:57:14.210833
9117 13:57:14.214066 [Calibration Summary] 3200 Mbps
9118 13:57:14.214150 CH 0, Rank 0
9119 13:57:14.217446 SW Impedance : PASS
9120 13:57:14.220484 DUTY Scan : NO K
9121 13:57:14.220566 ZQ Calibration : PASS
9122 13:57:14.223785 Jitter Meter : NO K
9123 13:57:14.223868 CBT Training : PASS
9124 13:57:14.227177 Write leveling : PASS
9125 13:57:14.230592 RX DQS gating : PASS
9126 13:57:14.230676 RX DQ/DQS(RDDQC) : PASS
9127 13:57:14.233963 TX DQ/DQS : PASS
9128 13:57:14.237235 RX DATLAT : PASS
9129 13:57:14.237342 RX DQ/DQS(Engine): PASS
9130 13:57:14.240509 TX OE : PASS
9131 13:57:14.240606 All Pass.
9132 13:57:14.240670
9133 13:57:14.243732 CH 0, Rank 1
9134 13:57:14.243861 SW Impedance : PASS
9135 13:57:14.246958 DUTY Scan : NO K
9136 13:57:14.250575 ZQ Calibration : PASS
9137 13:57:14.250658 Jitter Meter : NO K
9138 13:57:14.253486 CBT Training : PASS
9139 13:57:14.256843 Write leveling : PASS
9140 13:57:14.256925 RX DQS gating : PASS
9141 13:57:14.260231 RX DQ/DQS(RDDQC) : PASS
9142 13:57:14.263746 TX DQ/DQS : PASS
9143 13:57:14.263847 RX DATLAT : PASS
9144 13:57:14.267013 RX DQ/DQS(Engine): PASS
9145 13:57:14.270327 TX OE : PASS
9146 13:57:14.270412 All Pass.
9147 13:57:14.270476
9148 13:57:14.270535 CH 1, Rank 0
9149 13:57:14.273645 SW Impedance : PASS
9150 13:57:14.277018 DUTY Scan : NO K
9151 13:57:14.277106 ZQ Calibration : PASS
9152 13:57:14.280162 Jitter Meter : NO K
9153 13:57:14.280246 CBT Training : PASS
9154 13:57:14.283601 Write leveling : PASS
9155 13:57:14.286849 RX DQS gating : PASS
9156 13:57:14.286932 RX DQ/DQS(RDDQC) : PASS
9157 13:57:14.290483 TX DQ/DQS : PASS
9158 13:57:14.293703 RX DATLAT : PASS
9159 13:57:14.293785 RX DQ/DQS(Engine): PASS
9160 13:57:14.296789 TX OE : PASS
9161 13:57:14.296871 All Pass.
9162 13:57:14.296935
9163 13:57:14.300163 CH 1, Rank 1
9164 13:57:14.300245 SW Impedance : PASS
9165 13:57:14.303526 DUTY Scan : NO K
9166 13:57:14.306611 ZQ Calibration : PASS
9167 13:57:14.306695 Jitter Meter : NO K
9168 13:57:14.310205 CBT Training : PASS
9169 13:57:14.313306 Write leveling : PASS
9170 13:57:14.313387 RX DQS gating : PASS
9171 13:57:14.317004 RX DQ/DQS(RDDQC) : PASS
9172 13:57:14.320286 TX DQ/DQS : PASS
9173 13:57:14.320368 RX DATLAT : PASS
9174 13:57:14.323213 RX DQ/DQS(Engine): PASS
9175 13:57:14.326871 TX OE : PASS
9176 13:57:14.326954 All Pass.
9177 13:57:14.327018
9178 13:57:14.327077 DramC Write-DBI on
9179 13:57:14.329783 PER_BANK_REFRESH: Hybrid Mode
9180 13:57:14.333169 TX_TRACKING: ON
9181 13:57:14.339745 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9182 13:57:14.349779 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9183 13:57:14.356333 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9184 13:57:14.359695 [FAST_K] Save calibration result to emmc
9185 13:57:14.362902 sync common calibartion params.
9186 13:57:14.362985 sync cbt_mode0:1, 1:1
9187 13:57:14.366270 dram_init: ddr_geometry: 2
9188 13:57:14.369775 dram_init: ddr_geometry: 2
9189 13:57:14.373097 dram_init: ddr_geometry: 2
9190 13:57:14.373178 0:dram_rank_size:100000000
9191 13:57:14.376283 1:dram_rank_size:100000000
9192 13:57:14.382808 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9193 13:57:14.382896 DFS_SHUFFLE_HW_MODE: ON
9194 13:57:14.389729 dramc_set_vcore_voltage set vcore to 725000
9195 13:57:14.389817 Read voltage for 1600, 0
9196 13:57:14.393069 Vio18 = 0
9197 13:57:14.393151 Vcore = 725000
9198 13:57:14.393215 Vdram = 0
9199 13:57:14.396329 Vddq = 0
9200 13:57:14.396411 Vmddr = 0
9201 13:57:14.399310 switch to 3200 Mbps bootup
9202 13:57:14.399393 [DramcRunTimeConfig]
9203 13:57:14.399457 PHYPLL
9204 13:57:14.402577 DPM_CONTROL_AFTERK: ON
9205 13:57:14.406309 PER_BANK_REFRESH: ON
9206 13:57:14.406390 REFRESH_OVERHEAD_REDUCTION: ON
9207 13:57:14.409269 CMD_PICG_NEW_MODE: OFF
9208 13:57:14.412665 XRTWTW_NEW_MODE: ON
9209 13:57:14.412747 XRTRTR_NEW_MODE: ON
9210 13:57:14.415763 TX_TRACKING: ON
9211 13:57:14.415890 RDSEL_TRACKING: OFF
9212 13:57:14.419338 DQS Precalculation for DVFS: ON
9213 13:57:14.419459 RX_TRACKING: OFF
9214 13:57:14.422612 HW_GATING DBG: ON
9215 13:57:14.425719 ZQCS_ENABLE_LP4: ON
9216 13:57:14.425841 RX_PICG_NEW_MODE: ON
9217 13:57:14.428999 TX_PICG_NEW_MODE: ON
9218 13:57:14.429122 ENABLE_RX_DCM_DPHY: ON
9219 13:57:14.432264 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9220 13:57:14.435742 DUMMY_READ_FOR_TRACKING: OFF
9221 13:57:14.439168 !!! SPM_CONTROL_AFTERK: OFF
9222 13:57:14.442503 !!! SPM could not control APHY
9223 13:57:14.442626 IMPEDANCE_TRACKING: ON
9224 13:57:14.445817 TEMP_SENSOR: ON
9225 13:57:14.445939 HW_SAVE_FOR_SR: OFF
9226 13:57:14.448742 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9227 13:57:14.452513 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9228 13:57:14.455445 Read ODT Tracking: ON
9229 13:57:14.458955 Refresh Rate DeBounce: ON
9230 13:57:14.459079 DFS_NO_QUEUE_FLUSH: ON
9231 13:57:14.462022 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9232 13:57:14.465481 ENABLE_DFS_RUNTIME_MRW: OFF
9233 13:57:14.468900 DDR_RESERVE_NEW_MODE: ON
9234 13:57:14.469024 MR_CBT_SWITCH_FREQ: ON
9235 13:57:14.472245 =========================
9236 13:57:14.490609 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9237 13:57:14.494049 dram_init: ddr_geometry: 2
9238 13:57:14.512243 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9239 13:57:14.515507 dram_init: dram init end (result: 0)
9240 13:57:14.522027 DRAM-K: Full calibration passed in 24600 msecs
9241 13:57:14.525230 MRC: failed to locate region type 0.
9242 13:57:14.525370 DRAM rank0 size:0x100000000,
9243 13:57:14.528609 DRAM rank1 size=0x100000000
9244 13:57:14.538347 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9245 13:57:14.545279 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9246 13:57:14.551746 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9247 13:57:14.558439 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9248 13:57:14.561659 DRAM rank0 size:0x100000000,
9249 13:57:14.564893 DRAM rank1 size=0x100000000
9250 13:57:14.565030 CBMEM:
9251 13:57:14.568466 IMD: root @ 0xfffff000 254 entries.
9252 13:57:14.571643 IMD: root @ 0xffffec00 62 entries.
9253 13:57:14.574998 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9254 13:57:14.581670 WARNING: RO_VPD is uninitialized or empty.
9255 13:57:14.584863 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9256 13:57:14.592312 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9257 13:57:14.604810 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9258 13:57:14.616573 BS: romstage times (exec / console): total (unknown) / 24056 ms
9259 13:57:14.616694
9260 13:57:14.616797
9261 13:57:14.626505 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9262 13:57:14.629817 ARM64: Exception handlers installed.
9263 13:57:14.633000 ARM64: Testing exception
9264 13:57:14.636593 ARM64: Done test exception
9265 13:57:14.636683 Enumerating buses...
9266 13:57:14.639826 Show all devs... Before device enumeration.
9267 13:57:14.642851 Root Device: enabled 1
9268 13:57:14.646024 CPU_CLUSTER: 0: enabled 1
9269 13:57:14.646143 CPU: 00: enabled 1
9270 13:57:14.649617 Compare with tree...
9271 13:57:14.649744 Root Device: enabled 1
9272 13:57:14.652838 CPU_CLUSTER: 0: enabled 1
9273 13:57:14.655929 CPU: 00: enabled 1
9274 13:57:14.656015 Root Device scanning...
9275 13:57:14.659579 scan_static_bus for Root Device
9276 13:57:14.662711 CPU_CLUSTER: 0 enabled
9277 13:57:14.666436 scan_static_bus for Root Device done
9278 13:57:14.669695 scan_bus: bus Root Device finished in 8 msecs
9279 13:57:14.669782 done
9280 13:57:14.676095 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9281 13:57:14.679424 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9282 13:57:14.686237 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9283 13:57:14.689656 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9284 13:57:14.692615 Allocating resources...
9285 13:57:14.696001 Reading resources...
9286 13:57:14.699289 Root Device read_resources bus 0 link: 0
9287 13:57:14.699408 DRAM rank0 size:0x100000000,
9288 13:57:14.702694 DRAM rank1 size=0x100000000
9289 13:57:14.705789 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9290 13:57:14.708995 CPU: 00 missing read_resources
9291 13:57:14.712387 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9292 13:57:14.719288 Root Device read_resources bus 0 link: 0 done
9293 13:57:14.719411 Done reading resources.
9294 13:57:14.726030 Show resources in subtree (Root Device)...After reading.
9295 13:57:14.729275 Root Device child on link 0 CPU_CLUSTER: 0
9296 13:57:14.732468 CPU_CLUSTER: 0 child on link 0 CPU: 00
9297 13:57:14.742631 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9298 13:57:14.742747 CPU: 00
9299 13:57:14.745555 Root Device assign_resources, bus 0 link: 0
9300 13:57:14.748819 CPU_CLUSTER: 0 missing set_resources
9301 13:57:14.755720 Root Device assign_resources, bus 0 link: 0 done
9302 13:57:14.755818 Done setting resources.
9303 13:57:14.761944 Show resources in subtree (Root Device)...After assigning values.
9304 13:57:14.765512 Root Device child on link 0 CPU_CLUSTER: 0
9305 13:57:14.768910 CPU_CLUSTER: 0 child on link 0 CPU: 00
9306 13:57:14.778699 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9307 13:57:14.778803 CPU: 00
9308 13:57:14.781820 Done allocating resources.
9309 13:57:14.785208 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9310 13:57:14.788560 Enabling resources...
9311 13:57:14.788662 done.
9312 13:57:14.795288 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9313 13:57:14.795373 Initializing devices...
9314 13:57:14.798625 Root Device init
9315 13:57:14.798707 init hardware done!
9316 13:57:14.802017 0x00000018: ctrlr->caps
9317 13:57:14.805346 52.000 MHz: ctrlr->f_max
9318 13:57:14.805432 0.400 MHz: ctrlr->f_min
9319 13:57:14.808389 0x40ff8080: ctrlr->voltages
9320 13:57:14.811850 sclk: 390625
9321 13:57:14.811932 Bus Width = 1
9322 13:57:14.811997 sclk: 390625
9323 13:57:14.815036 Bus Width = 1
9324 13:57:14.815118 Early init status = 3
9325 13:57:14.821943 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9326 13:57:14.825320 in-header: 03 fc 00 00 01 00 00 00
9327 13:57:14.828303 in-data: 00
9328 13:57:14.831749 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9329 13:57:14.836642 in-header: 03 fd 00 00 00 00 00 00
9330 13:57:14.839933 in-data:
9331 13:57:14.843396 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9332 13:57:14.847681 in-header: 03 fc 00 00 01 00 00 00
9333 13:57:14.850749 in-data: 00
9334 13:57:14.854250 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9335 13:57:14.859797 in-header: 03 fd 00 00 00 00 00 00
9336 13:57:14.863096 in-data:
9337 13:57:14.866362 [SSUSB] Setting up USB HOST controller...
9338 13:57:14.869803 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9339 13:57:14.873187 [SSUSB] phy power-on done.
9340 13:57:14.876397 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9341 13:57:14.882730 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9342 13:57:14.886144 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9343 13:57:14.892761 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9344 13:57:14.899342 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9345 13:57:14.905915 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9346 13:57:14.912624 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9347 13:57:14.919208 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9348 13:57:14.922814 SPM: binary array size = 0x9dc
9349 13:57:14.925945 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9350 13:57:14.932647 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9351 13:57:14.939318 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9352 13:57:14.945862 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9353 13:57:14.949258 configure_display: Starting display init
9354 13:57:14.982965 anx7625_power_on_init: Init interface.
9355 13:57:14.986664 anx7625_disable_pd_protocol: Disabled PD feature.
9356 13:57:14.989874 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9357 13:57:15.017462 anx7625_start_dp_work: Secure OCM version=00
9358 13:57:15.020798 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9359 13:57:15.035492 sp_tx_get_edid_block: EDID Block = 1
9360 13:57:15.138180 Extracted contents:
9361 13:57:15.141540 header: 00 ff ff ff ff ff ff 00
9362 13:57:15.144551 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9363 13:57:15.147988 version: 01 04
9364 13:57:15.151217 basic params: 95 1f 11 78 0a
9365 13:57:15.154524 chroma info: 76 90 94 55 54 90 27 21 50 54
9366 13:57:15.158069 established: 00 00 00
9367 13:57:15.164497 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9368 13:57:15.168066 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9369 13:57:15.174551 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 13:57:15.181210 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9371 13:57:15.187777 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9372 13:57:15.190880 extensions: 00
9373 13:57:15.190999 checksum: fb
9374 13:57:15.191066
9375 13:57:15.194607 Manufacturer: IVO Model 57d Serial Number 0
9376 13:57:15.197536 Made week 0 of 2020
9377 13:57:15.197626 EDID version: 1.4
9378 13:57:15.200980 Digital display
9379 13:57:15.204225 6 bits per primary color channel
9380 13:57:15.204341 DisplayPort interface
9381 13:57:15.207559 Maximum image size: 31 cm x 17 cm
9382 13:57:15.211148 Gamma: 220%
9383 13:57:15.211265 Check DPMS levels
9384 13:57:15.214025 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9385 13:57:15.220643 First detailed timing is preferred timing
9386 13:57:15.220775 Established timings supported:
9387 13:57:15.224046 Standard timings supported:
9388 13:57:15.227402 Detailed timings
9389 13:57:15.230650 Hex of detail: 383680a07038204018303c0035ae10000019
9390 13:57:15.237203 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9391 13:57:15.240785 0780 0798 07c8 0820 hborder 0
9392 13:57:15.244070 0438 043b 0447 0458 vborder 0
9393 13:57:15.247207 -hsync -vsync
9394 13:57:15.247324 Did detailed timing
9395 13:57:15.253867 Hex of detail: 000000000000000000000000000000000000
9396 13:57:15.257103 Manufacturer-specified data, tag 0
9397 13:57:15.260387 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9398 13:57:15.263996 ASCII string: InfoVision
9399 13:57:15.267098 Hex of detail: 000000fe00523134304e574635205248200a
9400 13:57:15.270268 ASCII string: R140NWF5 RH
9401 13:57:15.270421 Checksum
9402 13:57:15.273607 Checksum: 0xfb (valid)
9403 13:57:15.277185 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9404 13:57:15.280570 DSI data_rate: 832800000 bps
9405 13:57:15.286840 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9406 13:57:15.290148 anx7625_parse_edid: pixelclock(138800).
9407 13:57:15.293761 hactive(1920), hsync(48), hfp(24), hbp(88)
9408 13:57:15.296874 vactive(1080), vsync(12), vfp(3), vbp(17)
9409 13:57:15.299871 anx7625_dsi_config: config dsi.
9410 13:57:15.306392 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9411 13:57:15.320375 anx7625_dsi_config: success to config DSI
9412 13:57:15.323298 anx7625_dp_start: MIPI phy setup OK.
9413 13:57:15.326707 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9414 13:57:15.329955 mtk_ddp_mode_set invalid vrefresh 60
9415 13:57:15.333233 main_disp_path_setup
9416 13:57:15.333343 ovl_layer_smi_id_en
9417 13:57:15.336561 ovl_layer_smi_id_en
9418 13:57:15.336655 ccorr_config
9419 13:57:15.336723 aal_config
9420 13:57:15.339766 gamma_config
9421 13:57:15.339853 postmask_config
9422 13:57:15.342965 dither_config
9423 13:57:15.346580 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9424 13:57:15.352937 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9425 13:57:15.356493 Root Device init finished in 555 msecs
9426 13:57:15.359543 CPU_CLUSTER: 0 init
9427 13:57:15.366158 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9428 13:57:15.372844 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9429 13:57:15.372981 APU_MBOX 0x190000b0 = 0x10001
9430 13:57:15.376271 APU_MBOX 0x190001b0 = 0x10001
9431 13:57:15.379669 APU_MBOX 0x190005b0 = 0x10001
9432 13:57:15.383021 APU_MBOX 0x190006b0 = 0x10001
9433 13:57:15.386358 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9434 13:57:15.399237 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9435 13:57:15.411634 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9436 13:57:15.418244 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9437 13:57:15.429896 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9438 13:57:15.439164 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9439 13:57:15.442187 CPU_CLUSTER: 0 init finished in 81 msecs
9440 13:57:15.445539 Devices initialized
9441 13:57:15.448911 Show all devs... After init.
9442 13:57:15.449016 Root Device: enabled 1
9443 13:57:15.452406 CPU_CLUSTER: 0: enabled 1
9444 13:57:15.455600 CPU: 00: enabled 1
9445 13:57:15.459086 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9446 13:57:15.462346 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9447 13:57:15.465627 ELOG: NV offset 0x57f000 size 0x1000
9448 13:57:15.472273 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9449 13:57:15.478967 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9450 13:57:15.482089 ELOG: Event(17) added with size 13 at 2024-02-01 13:57:16 UTC
9451 13:57:15.485233 out: cmd=0x121: 03 db 21 01 00 00 00 00
9452 13:57:15.489244 in-header: 03 3e 00 00 2c 00 00 00
9453 13:57:15.502814 in-data: 20 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9454 13:57:15.509566 ELOG: Event(A1) added with size 10 at 2024-02-01 13:57:16 UTC
9455 13:57:15.515870 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9456 13:57:15.522731 ELOG: Event(A0) added with size 9 at 2024-02-01 13:57:16 UTC
9457 13:57:15.526035 elog_add_boot_reason: Logged dev mode boot
9458 13:57:15.529239 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9459 13:57:15.532729 Finalize devices...
9460 13:57:15.532852 Devices finalized
9461 13:57:15.539447 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9462 13:57:15.542371 Writing coreboot table at 0xffe64000
9463 13:57:15.545748 0. 000000000010a000-0000000000113fff: RAMSTAGE
9464 13:57:15.549206 1. 0000000040000000-00000000400fffff: RAM
9465 13:57:15.552547 2. 0000000040100000-000000004032afff: RAMSTAGE
9466 13:57:15.559105 3. 000000004032b000-00000000545fffff: RAM
9467 13:57:15.562276 4. 0000000054600000-000000005465ffff: BL31
9468 13:57:15.565574 5. 0000000054660000-00000000ffe63fff: RAM
9469 13:57:15.572185 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9470 13:57:15.575344 7. 0000000100000000-000000023fffffff: RAM
9471 13:57:15.575486 Passing 5 GPIOs to payload:
9472 13:57:15.582324 NAME | PORT | POLARITY | VALUE
9473 13:57:15.585591 EC in RW | 0x000000aa | low | undefined
9474 13:57:15.592333 EC interrupt | 0x00000005 | low | undefined
9475 13:57:15.595582 TPM interrupt | 0x000000ab | high | undefined
9476 13:57:15.598889 SD card detect | 0x00000011 | high | undefined
9477 13:57:15.605442 speaker enable | 0x00000093 | high | undefined
9478 13:57:15.608915 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9479 13:57:15.611998 in-header: 03 f9 00 00 02 00 00 00
9480 13:57:15.615361 in-data: 02 00
9481 13:57:15.615472 ADC[4]: Raw value=894821 ID=7
9482 13:57:15.618644 ADC[3]: Raw value=213440 ID=1
9483 13:57:15.621969 RAM Code: 0x71
9484 13:57:15.622077 ADC[6]: Raw value=74722 ID=0
9485 13:57:15.625368 ADC[5]: Raw value=211590 ID=1
9486 13:57:15.628743 SKU Code: 0x1
9487 13:57:15.632044 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d551
9488 13:57:15.635359 coreboot table: 964 bytes.
9489 13:57:15.638581 IMD ROOT 0. 0xfffff000 0x00001000
9490 13:57:15.642043 IMD SMALL 1. 0xffffe000 0x00001000
9491 13:57:15.645016 RO MCACHE 2. 0xffffc000 0x00001104
9492 13:57:15.648723 CONSOLE 3. 0xfff7c000 0x00080000
9493 13:57:15.651728 FMAP 4. 0xfff7b000 0x00000452
9494 13:57:15.655075 TIME STAMP 5. 0xfff7a000 0x00000910
9495 13:57:15.658619 VBOOT WORK 6. 0xfff66000 0x00014000
9496 13:57:15.661947 RAMOOPS 7. 0xffe66000 0x00100000
9497 13:57:15.665167 COREBOOT 8. 0xffe64000 0x00002000
9498 13:57:15.668354 IMD small region:
9499 13:57:15.671873 IMD ROOT 0. 0xffffec00 0x00000400
9500 13:57:15.675107 VPD 1. 0xffffeb80 0x0000006c
9501 13:57:15.678550 MMC STATUS 2. 0xffffeb60 0x00000004
9502 13:57:15.681903 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9503 13:57:15.684966 Probing TPM: done!
9504 13:57:15.688533 Connected to device vid:did:rid of 1ae0:0028:00
9505 13:57:15.698778 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9506 13:57:15.702064 Initialized TPM device CR50 revision 0
9507 13:57:15.705807 Checking cr50 for pending updates
9508 13:57:15.709351 Reading cr50 TPM mode
9509 13:57:15.718230 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9510 13:57:15.724729 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9511 13:57:15.764678 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9512 13:57:15.768026 Checking segment from ROM address 0x40100000
9513 13:57:15.771455 Checking segment from ROM address 0x4010001c
9514 13:57:15.777957 Loading segment from ROM address 0x40100000
9515 13:57:15.778068 code (compression=0)
9516 13:57:15.788215 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9517 13:57:15.794652 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9518 13:57:15.794765 it's not compressed!
9519 13:57:15.801381 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9520 13:57:15.804887 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9521 13:57:15.825319 Loading segment from ROM address 0x4010001c
9522 13:57:15.825538 Entry Point 0x80000000
9523 13:57:15.828685 Loaded segments
9524 13:57:15.832024 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9525 13:57:15.838445 Jumping to boot code at 0x80000000(0xffe64000)
9526 13:57:15.845299 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9527 13:57:15.851471 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9528 13:57:15.859807 read SPI 0x8eb68 0x74a8: 3225 us, 9260 KB/s, 74.080 Mbps
9529 13:57:15.863104 Checking segment from ROM address 0x40100000
9530 13:57:15.866478 Checking segment from ROM address 0x4010001c
9531 13:57:15.873123 Loading segment from ROM address 0x40100000
9532 13:57:15.873270 code (compression=1)
9533 13:57:15.879765 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9534 13:57:15.889292 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9535 13:57:15.889467 using LZMA
9536 13:57:15.897974 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9537 13:57:15.904960 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9538 13:57:15.908200 Loading segment from ROM address 0x4010001c
9539 13:57:15.908346 Entry Point 0x54601000
9540 13:57:15.911559 Loaded segments
9541 13:57:15.914563 NOTICE: MT8192 bl31_setup
9542 13:57:15.921702 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9543 13:57:15.924915 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9544 13:57:15.928383 WARNING: region 0:
9545 13:57:15.931769 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 13:57:15.931908 WARNING: region 1:
9547 13:57:15.938178 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9548 13:57:15.941461 WARNING: region 2:
9549 13:57:15.944860 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9550 13:57:15.948238 WARNING: region 3:
9551 13:57:15.951501 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9552 13:57:15.954795 WARNING: region 4:
9553 13:57:15.961495 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9554 13:57:15.961667 WARNING: region 5:
9555 13:57:15.965003 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9556 13:57:15.968363 WARNING: region 6:
9557 13:57:15.971734 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9558 13:57:15.975077 WARNING: region 7:
9559 13:57:15.978516 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9560 13:57:15.985169 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9561 13:57:15.988098 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9562 13:57:15.991581 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9563 13:57:15.998433 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9564 13:57:16.001739 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9565 13:57:16.004905 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9566 13:57:16.011534 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9567 13:57:16.015008 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9568 13:57:16.021563 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9569 13:57:16.024947 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9570 13:57:16.028247 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9571 13:57:16.035059 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9572 13:57:16.038436 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9573 13:57:16.041742 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9574 13:57:16.048522 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9575 13:57:16.051417 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9576 13:57:16.058379 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9577 13:57:16.061471 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9578 13:57:16.064738 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9579 13:57:16.071391 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9580 13:57:16.074962 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9581 13:57:16.078316 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9582 13:57:16.085078 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9583 13:57:16.087997 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9584 13:57:16.094981 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9585 13:57:16.098141 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9586 13:57:16.101307 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9587 13:57:16.108240 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9588 13:57:16.111643 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9589 13:57:16.118250 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9590 13:57:16.121368 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9591 13:57:16.124769 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9592 13:57:16.131666 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9593 13:57:16.134958 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9594 13:57:16.137980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9595 13:57:16.141585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9596 13:57:16.148089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9597 13:57:16.151394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9598 13:57:16.154695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9599 13:57:16.158066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9600 13:57:16.164665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9601 13:57:16.168215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9602 13:57:16.171655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9603 13:57:16.175049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9604 13:57:16.181428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9605 13:57:16.184981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9606 13:57:16.188206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9607 13:57:16.191748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9608 13:57:16.198501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9609 13:57:16.201723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9610 13:57:16.208283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9611 13:57:16.211510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9612 13:57:16.214658 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9613 13:57:16.221381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9614 13:57:16.224822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9615 13:57:16.231496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9616 13:57:16.234717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9617 13:57:16.241359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9618 13:57:16.244528 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9619 13:57:16.251437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9620 13:57:16.254465 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9621 13:57:16.257826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9622 13:57:16.264598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9623 13:57:16.267890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9624 13:57:16.274725 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9625 13:57:16.277990 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9626 13:57:16.284390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9627 13:57:16.287781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9628 13:57:16.291340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9629 13:57:16.297932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9630 13:57:16.301149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9631 13:57:16.307904 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9632 13:57:16.311059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9633 13:57:16.317922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9634 13:57:16.321317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9635 13:57:16.324513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9636 13:57:16.331392 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9637 13:57:16.334763 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9638 13:57:16.341236 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9639 13:57:16.344639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9640 13:57:16.351081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9641 13:57:16.354692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9642 13:57:16.358098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9643 13:57:16.364709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9644 13:57:16.368174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9645 13:57:16.374512 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9646 13:57:16.378053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9647 13:57:16.384747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9648 13:57:16.388081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9649 13:57:16.391398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9650 13:57:16.398105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9651 13:57:16.401339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9652 13:57:16.408316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9653 13:57:16.411311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9654 13:57:16.417967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9655 13:57:16.421701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9656 13:57:16.424708 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9657 13:57:16.431319 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9658 13:57:16.434684 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9659 13:57:16.438114 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9660 13:57:16.441510 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9661 13:57:16.448005 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9662 13:57:16.451508 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9663 13:57:16.457892 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9664 13:57:16.461316 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9665 13:57:16.464552 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9666 13:57:16.471228 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9667 13:57:16.474646 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9668 13:57:16.481211 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9669 13:57:16.484853 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9670 13:57:16.488074 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9671 13:57:16.494673 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9672 13:57:16.497788 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9673 13:57:16.504839 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9674 13:57:16.507939 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9675 13:57:16.511214 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9676 13:57:16.514930 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9677 13:57:16.521189 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9678 13:57:16.524720 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9679 13:57:16.527851 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9680 13:57:16.534507 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9681 13:57:16.538170 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9682 13:57:16.541076 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9683 13:57:16.544580 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9684 13:57:16.551189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9685 13:57:16.554904 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9686 13:57:16.561207 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9687 13:57:16.564772 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9688 13:57:16.567783 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9689 13:57:16.574512 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9690 13:57:16.577962 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9691 13:57:16.581312 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9692 13:57:16.587784 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9693 13:57:16.591314 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9694 13:57:16.598026 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9695 13:57:16.601422 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9696 13:57:16.604622 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9697 13:57:16.611207 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9698 13:57:16.614536 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9699 13:57:16.621175 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9700 13:57:16.624615 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9701 13:57:16.627631 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9702 13:57:16.634271 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9703 13:57:16.637726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9704 13:57:16.641148 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9705 13:57:16.647725 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9706 13:57:16.650983 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9707 13:57:16.657714 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9708 13:57:16.661126 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9709 13:57:16.664593 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9710 13:57:16.670950 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9711 13:57:16.674464 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9712 13:57:16.680930 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9713 13:57:16.684640 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9714 13:57:16.687653 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9715 13:57:16.694284 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9716 13:57:16.697726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9717 13:57:16.704348 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9718 13:57:16.707713 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9719 13:57:16.711093 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9720 13:57:16.717775 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9721 13:57:16.721132 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9722 13:57:16.724529 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9723 13:57:16.730865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9724 13:57:16.734280 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9725 13:57:16.740819 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9726 13:57:16.744099 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9727 13:57:16.747475 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9728 13:57:16.754226 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9729 13:57:16.757719 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9730 13:57:16.764268 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9731 13:57:16.767620 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9732 13:57:16.770921 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9733 13:57:16.777713 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9734 13:57:16.780831 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9735 13:57:16.787417 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9736 13:57:16.791024 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9737 13:57:16.794194 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9738 13:57:16.800666 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9739 13:57:16.804135 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9740 13:57:16.807647 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9741 13:57:16.814056 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9742 13:57:16.817513 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9743 13:57:16.823917 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9744 13:57:16.827294 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9745 13:57:16.830709 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9746 13:57:16.837132 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9747 13:57:16.840586 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9748 13:57:16.847144 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9749 13:57:16.850691 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9750 13:57:16.853990 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9751 13:57:16.860862 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9752 13:57:16.863804 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9753 13:57:16.870171 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9754 13:57:16.873702 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9755 13:57:16.880219 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9756 13:57:16.883635 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9757 13:57:16.887143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9758 13:57:16.893716 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9759 13:57:16.897099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9760 13:57:16.903557 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9761 13:57:16.907089 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9762 13:57:16.913431 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9763 13:57:16.916871 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9764 13:57:16.920043 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9765 13:57:16.926620 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9766 13:57:16.929969 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9767 13:57:16.936578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9768 13:57:16.939908 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9769 13:57:16.943138 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9770 13:57:16.950011 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9771 13:57:16.953414 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9772 13:57:16.960111 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9773 13:57:16.963035 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9774 13:57:16.969914 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9775 13:57:16.973314 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9776 13:57:16.976502 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9777 13:57:16.983227 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9778 13:57:16.986632 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9779 13:57:16.993189 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9780 13:57:16.996348 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9781 13:57:16.999653 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9782 13:57:17.006164 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9783 13:57:17.009547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9784 13:57:17.016074 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9785 13:57:17.019513 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9786 13:57:17.026187 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9787 13:57:17.029343 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9788 13:57:17.032779 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9789 13:57:17.039375 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9790 13:57:17.042380 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9791 13:57:17.045805 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9792 13:57:17.049288 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9793 13:57:17.055740 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9794 13:57:17.059073 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9795 13:57:17.062470 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9796 13:57:17.069286 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9797 13:57:17.072728 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9798 13:57:17.075762 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9799 13:57:17.082401 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9800 13:57:17.085682 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9801 13:57:17.092338 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9802 13:57:17.095644 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9803 13:57:17.098977 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9804 13:57:17.105746 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9805 13:57:17.109012 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9806 13:57:17.112333 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9807 13:57:17.119021 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9808 13:57:17.122412 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9809 13:57:17.125531 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9810 13:57:17.132161 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9811 13:57:17.135734 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9812 13:57:17.142078 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9813 13:57:17.145242 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9814 13:57:17.148756 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9815 13:57:17.155441 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9816 13:57:17.158887 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9817 13:57:17.162127 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9818 13:57:17.168937 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9819 13:57:17.172410 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9820 13:57:17.175872 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9821 13:57:17.182333 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9822 13:57:17.185716 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9823 13:57:17.188932 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9824 13:57:17.195777 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9825 13:57:17.198971 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9826 13:57:17.205601 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9827 13:57:17.208874 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9828 13:57:17.212092 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9829 13:57:17.218836 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9830 13:57:17.222015 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9831 13:57:17.225006 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9832 13:57:17.228353 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9833 13:57:17.231925 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9834 13:57:17.238625 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9835 13:57:17.241543 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9836 13:57:17.244988 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9837 13:57:17.248346 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9838 13:57:17.255109 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9839 13:57:17.258163 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9840 13:57:17.261676 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9841 13:57:17.268073 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9842 13:57:17.271248 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9843 13:57:17.274593 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9844 13:57:17.281314 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9845 13:57:17.284714 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9846 13:57:17.291161 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9847 13:57:17.294466 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9848 13:57:17.301103 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9849 13:57:17.304354 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9850 13:57:17.307766 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9851 13:57:17.314260 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9852 13:57:17.317592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9853 13:57:17.324517 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9854 13:57:17.327498 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9855 13:57:17.334235 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9856 13:57:17.337564 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9857 13:57:17.340716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9858 13:57:17.347295 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9859 13:57:17.350825 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9860 13:57:17.357173 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9861 13:57:17.360536 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9862 13:57:17.363899 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9863 13:57:17.370638 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9864 13:57:17.373882 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9865 13:57:17.380482 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9866 13:57:17.383845 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9867 13:57:17.386867 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9868 13:57:17.393706 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9869 13:57:17.397173 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9870 13:57:17.403696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9871 13:57:17.406775 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9872 13:57:17.413659 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9873 13:57:17.416932 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9874 13:57:17.419978 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9875 13:57:17.426852 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9876 13:57:17.430191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9877 13:57:17.436917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9878 13:57:17.440247 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9879 13:57:17.443483 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9880 13:57:17.450054 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9881 13:57:17.453258 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9882 13:57:17.460001 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9883 13:57:17.463496 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9884 13:57:17.466780 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9885 13:57:17.473169 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9886 13:57:17.476468 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9887 13:57:17.483420 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9888 13:57:17.486499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9889 13:57:17.489916 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9890 13:57:17.496330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9891 13:57:17.499652 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9892 13:57:17.506379 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9893 13:57:17.509473 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9894 13:57:17.516055 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9895 13:57:17.519444 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9896 13:57:17.522731 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9897 13:57:17.529451 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9898 13:57:17.532817 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9899 13:57:17.539257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9900 13:57:17.542644 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9901 13:57:17.545941 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9902 13:57:17.552655 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9903 13:57:17.555937 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9904 13:57:17.562618 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9905 13:57:17.565893 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9906 13:57:17.569391 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9907 13:57:17.575645 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9908 13:57:17.579062 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9909 13:57:17.585454 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9910 13:57:17.588822 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9911 13:57:17.595551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9912 13:57:17.598997 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9913 13:57:17.602251 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9914 13:57:17.608653 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9915 13:57:17.612266 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9916 13:57:17.618585 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9917 13:57:17.622062 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9918 13:57:17.628590 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9919 13:57:17.631985 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9920 13:57:17.638739 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9921 13:57:17.641786 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9922 13:57:17.645251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9923 13:57:17.651874 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9924 13:57:17.655165 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9925 13:57:17.662079 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9926 13:57:17.664768 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9927 13:57:17.671812 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9928 13:57:17.675081 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9929 13:57:17.678649 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9930 13:57:17.685162 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9931 13:57:17.688183 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9932 13:57:17.694912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9933 13:57:17.698329 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9934 13:57:17.704612 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9935 13:57:17.708057 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9936 13:57:17.714759 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9937 13:57:17.718001 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9938 13:57:17.721375 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9939 13:57:17.727946 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9940 13:57:17.731476 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9941 13:57:17.737880 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9942 13:57:17.741159 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9943 13:57:17.747888 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9944 13:57:17.751354 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9945 13:57:17.754594 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9946 13:57:17.761309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9947 13:57:17.764622 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9948 13:57:17.771015 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9949 13:57:17.774284 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9950 13:57:17.781188 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9951 13:57:17.784301 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9952 13:57:17.791181 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9953 13:57:17.794626 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9954 13:57:17.797822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9955 13:57:17.804356 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9956 13:57:17.807768 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9957 13:57:17.814474 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9958 13:57:17.817852 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9959 13:57:17.824477 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9960 13:57:17.827460 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9961 13:57:17.830802 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9962 13:57:17.837325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9963 13:57:17.840836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9964 13:57:17.847552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9965 13:57:17.850842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9966 13:57:17.854225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9967 13:57:17.861064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9968 13:57:17.864354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9969 13:57:17.870851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9970 13:57:17.874189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9971 13:57:17.880873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9972 13:57:17.883982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9973 13:57:17.890688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9974 13:57:17.894059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9975 13:57:17.900642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9976 13:57:17.903888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9977 13:57:17.910788 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9978 13:57:17.914114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9979 13:57:17.920555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9980 13:57:17.923790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9981 13:57:17.930675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9982 13:57:17.933628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9983 13:57:17.940295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9984 13:57:17.943646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9985 13:57:17.950314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9986 13:57:17.953720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9987 13:57:17.960164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9988 13:57:17.963758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9989 13:57:17.970358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9990 13:57:17.973714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9991 13:57:17.980232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9992 13:57:17.983345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9993 13:57:17.990023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9994 13:57:17.993453 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9995 13:57:17.996594 INFO: [APUAPC] vio 0
9996 13:57:17.999911 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9997 13:57:18.006501 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9998 13:57:18.009689 INFO: [APUAPC] D0_APC_0: 0x400510
9999 13:57:18.009830 INFO: [APUAPC] D0_APC_1: 0x0
10000 13:57:18.013129 INFO: [APUAPC] D0_APC_2: 0x1540
10001 13:57:18.016546 INFO: [APUAPC] D0_APC_3: 0x0
10002 13:57:18.019772 INFO: [APUAPC] D1_APC_0: 0xffffffff
10003 13:57:18.023054 INFO: [APUAPC] D1_APC_1: 0xffffffff
10004 13:57:18.026321 INFO: [APUAPC] D1_APC_2: 0x3fffff
10005 13:57:18.029643 INFO: [APUAPC] D1_APC_3: 0x0
10006 13:57:18.032990 INFO: [APUAPC] D2_APC_0: 0xffffffff
10007 13:57:18.036401 INFO: [APUAPC] D2_APC_1: 0xffffffff
10008 13:57:18.039822 INFO: [APUAPC] D2_APC_2: 0x3fffff
10009 13:57:18.043154 INFO: [APUAPC] D2_APC_3: 0x0
10010 13:57:18.046192 INFO: [APUAPC] D3_APC_0: 0xffffffff
10011 13:57:18.049499 INFO: [APUAPC] D3_APC_1: 0xffffffff
10012 13:57:18.052666 INFO: [APUAPC] D3_APC_2: 0x3fffff
10013 13:57:18.056170 INFO: [APUAPC] D3_APC_3: 0x0
10014 13:57:18.059583 INFO: [APUAPC] D4_APC_0: 0xffffffff
10015 13:57:18.062958 INFO: [APUAPC] D4_APC_1: 0xffffffff
10016 13:57:18.066183 INFO: [APUAPC] D4_APC_2: 0x3fffff
10017 13:57:18.069647 INFO: [APUAPC] D4_APC_3: 0x0
10018 13:57:18.072906 INFO: [APUAPC] D5_APC_0: 0xffffffff
10019 13:57:18.075770 INFO: [APUAPC] D5_APC_1: 0xffffffff
10020 13:57:18.079198 INFO: [APUAPC] D5_APC_2: 0x3fffff
10021 13:57:18.082610 INFO: [APUAPC] D5_APC_3: 0x0
10022 13:57:18.085919 INFO: [APUAPC] D6_APC_0: 0xffffffff
10023 13:57:18.089134 INFO: [APUAPC] D6_APC_1: 0xffffffff
10024 13:57:18.092921 INFO: [APUAPC] D6_APC_2: 0x3fffff
10025 13:57:18.095797 INFO: [APUAPC] D6_APC_3: 0x0
10026 13:57:18.099570 INFO: [APUAPC] D7_APC_0: 0xffffffff
10027 13:57:18.102546 INFO: [APUAPC] D7_APC_1: 0xffffffff
10028 13:57:18.105803 INFO: [APUAPC] D7_APC_2: 0x3fffff
10029 13:57:18.109188 INFO: [APUAPC] D7_APC_3: 0x0
10030 13:57:18.112713 INFO: [APUAPC] D8_APC_0: 0xffffffff
10031 13:57:18.116076 INFO: [APUAPC] D8_APC_1: 0xffffffff
10032 13:57:18.118923 INFO: [APUAPC] D8_APC_2: 0x3fffff
10033 13:57:18.122659 INFO: [APUAPC] D8_APC_3: 0x0
10034 13:57:18.125965 INFO: [APUAPC] D9_APC_0: 0xffffffff
10035 13:57:18.129068 INFO: [APUAPC] D9_APC_1: 0xffffffff
10036 13:57:18.132383 INFO: [APUAPC] D9_APC_2: 0x3fffff
10037 13:57:18.135631 INFO: [APUAPC] D9_APC_3: 0x0
10038 13:57:18.138989 INFO: [APUAPC] D10_APC_0: 0xffffffff
10039 13:57:18.142554 INFO: [APUAPC] D10_APC_1: 0xffffffff
10040 13:57:18.145892 INFO: [APUAPC] D10_APC_2: 0x3fffff
10041 13:57:18.148926 INFO: [APUAPC] D10_APC_3: 0x0
10042 13:57:18.152366 INFO: [APUAPC] D11_APC_0: 0xffffffff
10043 13:57:18.155626 INFO: [APUAPC] D11_APC_1: 0xffffffff
10044 13:57:18.158578 INFO: [APUAPC] D11_APC_2: 0x3fffff
10045 13:57:18.161987 INFO: [APUAPC] D11_APC_3: 0x0
10046 13:57:18.165335 INFO: [APUAPC] D12_APC_0: 0xffffffff
10047 13:57:18.168808 INFO: [APUAPC] D12_APC_1: 0xffffffff
10048 13:57:18.171844 INFO: [APUAPC] D12_APC_2: 0x3fffff
10049 13:57:18.175051 INFO: [APUAPC] D12_APC_3: 0x0
10050 13:57:18.178486 INFO: [APUAPC] D13_APC_0: 0xffffffff
10051 13:57:18.182060 INFO: [APUAPC] D13_APC_1: 0xffffffff
10052 13:57:18.185389 INFO: [APUAPC] D13_APC_2: 0x3fffff
10053 13:57:18.188511 INFO: [APUAPC] D13_APC_3: 0x0
10054 13:57:18.191596 INFO: [APUAPC] D14_APC_0: 0xffffffff
10055 13:57:18.194861 INFO: [APUAPC] D14_APC_1: 0xffffffff
10056 13:57:18.198062 INFO: [APUAPC] D14_APC_2: 0x3fffff
10057 13:57:18.201498 INFO: [APUAPC] D14_APC_3: 0x0
10058 13:57:18.205070 INFO: [APUAPC] D15_APC_0: 0xffffffff
10059 13:57:18.208444 INFO: [APUAPC] D15_APC_1: 0xffffffff
10060 13:57:18.211480 INFO: [APUAPC] D15_APC_2: 0x3fffff
10061 13:57:18.214825 INFO: [APUAPC] D15_APC_3: 0x0
10062 13:57:18.218352 INFO: [APUAPC] APC_CON: 0x4
10063 13:57:18.221621 INFO: [NOCDAPC] D0_APC_0: 0x0
10064 13:57:18.224903 INFO: [NOCDAPC] D0_APC_1: 0x0
10065 13:57:18.225004 INFO: [NOCDAPC] D1_APC_0: 0x0
10066 13:57:18.228106 INFO: [NOCDAPC] D1_APC_1: 0xfff
10067 13:57:18.231401 INFO: [NOCDAPC] D2_APC_0: 0x0
10068 13:57:18.234656 INFO: [NOCDAPC] D2_APC_1: 0xfff
10069 13:57:18.238146 INFO: [NOCDAPC] D3_APC_0: 0x0
10070 13:57:18.241345 INFO: [NOCDAPC] D3_APC_1: 0xfff
10071 13:57:18.244777 INFO: [NOCDAPC] D4_APC_0: 0x0
10072 13:57:18.247766 INFO: [NOCDAPC] D4_APC_1: 0xfff
10073 13:57:18.251205 INFO: [NOCDAPC] D5_APC_0: 0x0
10074 13:57:18.254733 INFO: [NOCDAPC] D5_APC_1: 0xfff
10075 13:57:18.257673 INFO: [NOCDAPC] D6_APC_0: 0x0
10076 13:57:18.257759 INFO: [NOCDAPC] D6_APC_1: 0xfff
10077 13:57:18.260999 INFO: [NOCDAPC] D7_APC_0: 0x0
10078 13:57:18.264577 INFO: [NOCDAPC] D7_APC_1: 0xfff
10079 13:57:18.267570 INFO: [NOCDAPC] D8_APC_0: 0x0
10080 13:57:18.271125 INFO: [NOCDAPC] D8_APC_1: 0xfff
10081 13:57:18.274542 INFO: [NOCDAPC] D9_APC_0: 0x0
10082 13:57:18.277618 INFO: [NOCDAPC] D9_APC_1: 0xfff
10083 13:57:18.280905 INFO: [NOCDAPC] D10_APC_0: 0x0
10084 13:57:18.284335 INFO: [NOCDAPC] D10_APC_1: 0xfff
10085 13:57:18.287841 INFO: [NOCDAPC] D11_APC_0: 0x0
10086 13:57:18.291027 INFO: [NOCDAPC] D11_APC_1: 0xfff
10087 13:57:18.294390 INFO: [NOCDAPC] D12_APC_0: 0x0
10088 13:57:18.297571 INFO: [NOCDAPC] D12_APC_1: 0xfff
10089 13:57:18.297690 INFO: [NOCDAPC] D13_APC_0: 0x0
10090 13:57:18.301094 INFO: [NOCDAPC] D13_APC_1: 0xfff
10091 13:57:18.304683 INFO: [NOCDAPC] D14_APC_0: 0x0
10092 13:57:18.307595 INFO: [NOCDAPC] D14_APC_1: 0xfff
10093 13:57:18.310981 INFO: [NOCDAPC] D15_APC_0: 0x0
10094 13:57:18.313992 INFO: [NOCDAPC] D15_APC_1: 0xfff
10095 13:57:18.317500 INFO: [NOCDAPC] APC_CON: 0x4
10096 13:57:18.321023 INFO: [APUAPC] set_apusys_apc done
10097 13:57:18.323957 INFO: [DEVAPC] devapc_init done
10098 13:57:18.327316 INFO: GICv3 without legacy support detected.
10099 13:57:18.330661 INFO: ARM GICv3 driver initialized in EL3
10100 13:57:18.337268 INFO: Maximum SPI INTID supported: 639
10101 13:57:18.340729 INFO: BL31: Initializing runtime services
10102 13:57:18.347023 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10103 13:57:18.347243 INFO: SPM: enable CPC mode
10104 13:57:18.353816 INFO: mcdi ready for mcusys-off-idle and system suspend
10105 13:57:18.357107 INFO: BL31: Preparing for EL3 exit to normal world
10106 13:57:18.363488 INFO: Entry point address = 0x80000000
10107 13:57:18.363614 INFO: SPSR = 0x8
10108 13:57:18.369496
10109 13:57:18.369625
10110 13:57:18.369695
10111 13:57:18.372877 Starting depthcharge on Spherion...
10112 13:57:18.372974
10113 13:57:18.373042 Wipe memory regions:
10114 13:57:18.373104
10115 13:57:18.373865 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10116 13:57:18.373975 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10117 13:57:18.374060 Setting prompt string to ['asurada:']
10118 13:57:18.374142 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10119 13:57:18.376263 [0x00000040000000, 0x00000054600000)
10120 13:57:18.498690
10121 13:57:18.498827 [0x00000054660000, 0x00000080000000)
10122 13:57:18.759268
10123 13:57:18.759471 [0x000000821a7280, 0x000000ffe64000)
10124 13:57:19.504038
10125 13:57:19.504322 [0x00000100000000, 0x00000240000000)
10126 13:57:21.394227
10127 13:57:21.397500 Initializing XHCI USB controller at 0x11200000.
10128 13:57:22.435302
10129 13:57:22.438600 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10130 13:57:22.438703
10131 13:57:22.438815
10132 13:57:22.438898
10133 13:57:22.439220 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10135 13:57:22.539625 asurada: tftpboot 192.168.201.1 12682960/tftp-deploy-4uofzm8x/kernel/image.itb 12682960/tftp-deploy-4uofzm8x/kernel/cmdline
10136 13:57:22.539798 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10137 13:57:22.539925 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10138 13:57:22.544360 tftpboot 192.168.201.1 12682960/tftp-deploy-4uofzm8x/kernel/image.itp-deploy-4uofzm8x/kernel/cmdline
10139 13:57:22.544472
10140 13:57:22.544560 Waiting for link
10141 13:57:22.704677
10142 13:57:22.704823 R8152: Initializing
10143 13:57:22.704923
10144 13:57:22.708054 Version 6 (ocp_data = 5c30)
10145 13:57:22.708142
10146 13:57:22.711435 R8152: Done initializing
10147 13:57:22.711523
10148 13:57:22.711612 Adding net device
10149 13:57:24.614603
10150 13:57:24.614738 done.
10151 13:57:24.614848
10152 13:57:24.614991 MAC: 00:24:32:30:78:ff
10153 13:57:24.615086
10154 13:57:24.618083 Sending DHCP discover... done.
10155 13:57:24.618167
10156 13:57:24.621266 Waiting for reply... done.
10157 13:57:24.621347
10158 13:57:24.624531 Sending DHCP request... done.
10159 13:57:24.624613
10160 13:57:24.627796 Waiting for reply... done.
10161 13:57:24.627870
10162 13:57:24.627932 My ip is 192.168.201.21
10163 13:57:24.627991
10164 13:57:24.631283 The DHCP server ip is 192.168.201.1
10165 13:57:24.631369
10166 13:57:24.634635 TFTP server IP predefined by user: 192.168.201.1
10167 13:57:24.637654
10168 13:57:24.641240 Bootfile predefined by user: 12682960/tftp-deploy-4uofzm8x/kernel/image.itb
10169 13:57:24.644292
10170 13:57:24.644401 Sending tftp read request... done.
10171 13:57:24.644504
10172 13:57:24.651196 Waiting for the transfer...
10173 13:57:24.651295
10174 13:57:25.174289 00000000 ################################################################
10175 13:57:25.174472
10176 13:57:25.693823 00080000 ################################################################
10177 13:57:25.693961
10178 13:57:26.217028 00100000 ################################################################
10179 13:57:26.217195
10180 13:57:26.735545 00180000 ################################################################
10181 13:57:26.735724
10182 13:57:27.258612 00200000 ################################################################
10183 13:57:27.258757
10184 13:57:27.777606 00280000 ################################################################
10185 13:57:27.777787
10186 13:57:28.297388 00300000 ################################################################
10187 13:57:28.297586
10188 13:57:28.821615 00380000 ################################################################
10189 13:57:28.821764
10190 13:57:29.351091 00400000 ################################################################
10191 13:57:29.351238
10192 13:57:29.876579 00480000 ################################################################
10193 13:57:29.876748
10194 13:57:30.399555 00500000 ################################################################
10195 13:57:30.399726
10196 13:57:30.920029 00580000 ################################################################
10197 13:57:30.920189
10198 13:57:31.442308 00600000 ################################################################
10199 13:57:31.442449
10200 13:57:31.966549 00680000 ################################################################
10201 13:57:31.966682
10202 13:57:32.491607 00700000 ################################################################
10203 13:57:32.491741
10204 13:57:33.020205 00780000 ################################################################
10205 13:57:33.020347
10206 13:57:33.550793 00800000 ################################################################
10207 13:57:33.550959
10208 13:57:34.076158 00880000 ################################################################
10209 13:57:34.076298
10210 13:57:34.602112 00900000 ################################################################
10211 13:57:34.602274
10212 13:57:35.129986 00980000 ################################################################
10213 13:57:35.130127
10214 13:57:35.656921 00a00000 ################################################################
10215 13:57:35.657100
10216 13:57:36.184883 00a80000 ################################################################
10217 13:57:36.185059
10218 13:57:36.709443 00b00000 ################################################################
10219 13:57:36.709609
10220 13:57:37.245906 00b80000 ################################################################
10221 13:57:37.246066
10222 13:57:37.781739 00c00000 ################################################################
10223 13:57:37.781907
10224 13:57:38.303457 00c80000 ################################################################
10225 13:57:38.303606
10226 13:57:38.825197 00d00000 ################################################################
10227 13:57:38.825371
10228 13:57:39.352772 00d80000 ################################################################
10229 13:57:39.352929
10230 13:57:39.868148 00e00000 ################################################################
10231 13:57:39.868318
10232 13:57:40.376143 00e80000 ################################################################
10233 13:57:40.376295
10234 13:57:40.883558 00f00000 ################################################################
10235 13:57:40.883709
10236 13:57:41.405324 00f80000 ################################################################
10237 13:57:41.405497
10238 13:57:41.925397 01000000 ################################################################
10239 13:57:41.925570
10240 13:57:42.444201 01080000 ################################################################
10241 13:57:42.444362
10242 13:57:42.963175 01100000 ################################################################
10243 13:57:42.963344
10244 13:57:43.484726 01180000 ################################################################
10245 13:57:43.484864
10246 13:57:44.004533 01200000 ################################################################
10247 13:57:44.004682
10248 13:57:44.526072 01280000 ################################################################
10249 13:57:44.526210
10250 13:57:45.051717 01300000 ################################################################
10251 13:57:45.051880
10252 13:57:45.569187 01380000 ################################################################
10253 13:57:45.569339
10254 13:57:46.085990 01400000 ################################################################
10255 13:57:46.086150
10256 13:57:46.605541 01480000 ################################################################
10257 13:57:46.605692
10258 13:57:47.124729 01500000 ################################################################
10259 13:57:47.124914
10260 13:57:47.648405 01580000 ################################################################
10261 13:57:47.648588
10262 13:57:48.169848 01600000 ################################################################
10263 13:57:48.169996
10264 13:57:48.684025 01680000 ################################################################
10265 13:57:48.684202
10266 13:57:49.208692 01700000 ################################################################
10267 13:57:49.208849
10268 13:57:49.719649 01780000 ################################################################
10269 13:57:49.719787
10270 13:57:50.245842 01800000 ################################################################
10271 13:57:50.246009
10272 13:57:50.768865 01880000 ################################################################
10273 13:57:50.769004
10274 13:57:51.285411 01900000 ################################################################
10275 13:57:51.285583
10276 13:57:51.823262 01980000 ################################################################
10277 13:57:51.823401
10278 13:57:52.347015 01a00000 ################################################################
10279 13:57:52.347152
10280 13:57:52.873858 01a80000 ################################################################
10281 13:57:52.873996
10282 13:57:53.390473 01b00000 ################################################################
10283 13:57:53.390613
10284 13:57:53.925464 01b80000 ################################################################
10285 13:57:53.925607
10286 13:57:54.454295 01c00000 ################################################################
10287 13:57:54.454444
10288 13:57:54.975669 01c80000 ################################################################
10289 13:57:54.975844
10290 13:57:55.422350 01d00000 ######################################################## done.
10291 13:57:55.422492
10292 13:57:55.425929 The bootfile was 30861834 bytes long.
10293 13:57:55.426033
10294 13:57:55.429093 Sending tftp read request... done.
10295 13:57:55.429177
10296 13:57:55.432351 Waiting for the transfer...
10297 13:57:55.432441
10298 13:57:55.435420 00000000 # done.
10299 13:57:55.435505
10300 13:57:55.442121 Command line loaded dynamically from TFTP file: 12682960/tftp-deploy-4uofzm8x/kernel/cmdline
10301 13:57:55.442208
10302 13:57:55.465402 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682960/extract-nfsrootfs-g0w8ha3y,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10303 13:57:55.465550
10304 13:57:55.465661 Loading FIT.
10305 13:57:55.465754
10306 13:57:55.468541 Image ramdisk-1 has 18765661 bytes.
10307 13:57:55.468641
10308 13:57:55.471775 Image fdt-1 has 47278 bytes.
10309 13:57:55.471876
10310 13:57:55.475404 Image kernel-1 has 12046857 bytes.
10311 13:57:55.475488
10312 13:57:55.482048 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10313 13:57:55.485426
10314 13:57:55.501709 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10315 13:57:55.501808
10316 13:57:55.505245 Choosing best match conf-1 for compat google,spherion-rev2.
10317 13:57:55.510440
10318 13:57:55.515152 Connected to device vid:did:rid of 1ae0:0028:00
10319 13:57:55.522095
10320 13:57:55.525415 tpm_get_response: command 0x17b, return code 0x0
10321 13:57:55.525529
10322 13:57:55.532034 ec_init: CrosEC protocol v3 supported (256, 248)
10323 13:57:55.532121
10324 13:57:55.535307 tpm_cleanup: add release locality here.
10325 13:57:55.535392
10326 13:57:55.538481 Shutting down all USB controllers.
10327 13:57:55.538565
10328 13:57:55.542154 Removing current net device
10329 13:57:55.542239
10330 13:57:55.545394 Exiting depthcharge with code 4 at timestamp: 66517558
10331 13:57:55.545487
10332 13:57:55.552082 LZMA decompressing kernel-1 to 0x821a6718
10333 13:57:55.552181
10334 13:57:55.555561 LZMA decompressing kernel-1 to 0x40000000
10335 13:57:57.055314
10336 13:57:57.055472 jumping to kernel
10337 13:57:57.055934 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10338 13:57:57.056038 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10339 13:57:57.056117 Setting prompt string to ['Linux version [0-9]']
10340 13:57:57.056187 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10341 13:57:57.056257 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10342 13:57:57.138354
10343 13:57:57.141397 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10344 13:57:57.145091 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10345 13:57:57.145188 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10346 13:57:57.145262 Setting prompt string to []
10347 13:57:57.145360 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10348 13:57:57.145467 Using line separator: #'\n'#
10349 13:57:57.145547 No login prompt set.
10350 13:57:57.145619 Parsing kernel messages
10351 13:57:57.145678 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10352 13:57:57.145788 [login-action] Waiting for messages, (timeout 00:03:46)
10353 13:57:57.164850 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10354 13:57:57.167843 [ 0.000000] random: crng init done
10355 13:57:57.174542 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10356 13:57:57.178027 [ 0.000000] efi: UEFI not found.
10357 13:57:57.184302 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10358 13:57:57.191320 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10359 13:57:57.201228 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10360 13:57:57.211124 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10361 13:57:57.217527 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10362 13:57:57.224342 [ 0.000000] printk: bootconsole [mtk8250] enabled
10363 13:57:57.230983 [ 0.000000] NUMA: No NUMA configuration found
10364 13:57:57.237525 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10365 13:57:57.240870 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10366 13:57:57.244446 [ 0.000000] Zone ranges:
10367 13:57:57.250908 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10368 13:57:57.254174 [ 0.000000] DMA32 empty
10369 13:57:57.260878 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10370 13:57:57.264375 [ 0.000000] Movable zone start for each node
10371 13:57:57.267721 [ 0.000000] Early memory node ranges
10372 13:57:57.274375 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10373 13:57:57.280747 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10374 13:57:57.287363 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10375 13:57:57.290564 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10376 13:57:57.297435 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10377 13:57:57.304149 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10378 13:57:57.362128 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10379 13:57:57.368830 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10380 13:57:57.375361 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10381 13:57:57.378788 [ 0.000000] psci: probing for conduit method from DT.
10382 13:57:57.385298 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10383 13:57:57.388832 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10384 13:57:57.395509 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10385 13:57:57.398660 [ 0.000000] psci: SMC Calling Convention v1.2
10386 13:57:57.405089 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10387 13:57:57.408461 [ 0.000000] Detected VIPT I-cache on CPU0
10388 13:57:57.415135 [ 0.000000] CPU features: detected: GIC system register CPU interface
10389 13:57:57.421702 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10390 13:57:57.428317 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10391 13:57:57.435055 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10392 13:57:57.444706 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10393 13:57:57.451313 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10394 13:57:57.454575 [ 0.000000] alternatives: applying boot alternatives
10395 13:57:57.461256 [ 0.000000] Fallback order for Node 0: 0
10396 13:57:57.467856 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10397 13:57:57.470942 [ 0.000000] Policy zone: Normal
10398 13:57:57.494462 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682960/extract-nfsrootfs-g0w8ha3y,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10399 13:57:57.504017 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10400 13:57:57.515122 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10401 13:57:57.525316 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10402 13:57:57.531581 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10403 13:57:57.534704 <6>[ 0.000000] software IO TLB: area num 8.
10404 13:57:57.591571 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10405 13:57:57.740542 <6>[ 0.000000] Memory: 7948928K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 403840K reserved, 32768K cma-reserved)
10406 13:57:57.747294 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10407 13:57:57.753776 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10408 13:57:57.757166 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10409 13:57:57.763690 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10410 13:57:57.770519 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10411 13:57:57.773777 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10412 13:57:57.783619 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10413 13:57:57.790084 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10414 13:57:57.796760 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10415 13:57:57.803369 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10416 13:57:57.806563 <6>[ 0.000000] GICv3: 608 SPIs implemented
10417 13:57:57.809701 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10418 13:57:57.816648 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10419 13:57:57.820041 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10420 13:57:57.826177 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10421 13:57:57.839528 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10422 13:57:57.852830 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10423 13:57:57.859365 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10424 13:57:57.867283 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10425 13:57:57.880196 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10426 13:57:57.886877 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10427 13:57:57.893744 <6>[ 0.009232] Console: colour dummy device 80x25
10428 13:57:57.903648 <6>[ 0.013948] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10429 13:57:57.910273 <6>[ 0.024389] pid_max: default: 32768 minimum: 301
10430 13:57:57.913500 <6>[ 0.029261] LSM: Security Framework initializing
10431 13:57:57.920132 <6>[ 0.034198] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10432 13:57:57.929770 <6>[ 0.042062] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 13:57:57.940088 <6>[ 0.051523] cblist_init_generic: Setting adjustable number of callback queues.
10434 13:57:57.943270 <6>[ 0.059012] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 13:57:57.953144 <6>[ 0.065352] cblist_init_generic: Setting adjustable number of callback queues.
10436 13:57:57.959643 <6>[ 0.072779] cblist_init_generic: Setting shift to 3 and lim to 1.
10437 13:57:57.963232 <6>[ 0.079180] rcu: Hierarchical SRCU implementation.
10438 13:57:57.969458 <6>[ 0.084220] rcu: Max phase no-delay instances is 1000.
10439 13:57:57.976095 <6>[ 0.091278] EFI services will not be available.
10440 13:57:57.979554 <6>[ 0.096261] smp: Bringing up secondary CPUs ...
10441 13:57:57.987886 <6>[ 0.101309] Detected VIPT I-cache on CPU1
10442 13:57:57.994580 <6>[ 0.101377] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10443 13:57:58.001209 <6>[ 0.101407] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10444 13:57:58.004273 <6>[ 0.101746] Detected VIPT I-cache on CPU2
10445 13:57:58.014501 <6>[ 0.101798] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10446 13:57:58.021146 <6>[ 0.101815] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10447 13:57:58.024084 <6>[ 0.102075] Detected VIPT I-cache on CPU3
10448 13:57:58.030857 <6>[ 0.102120] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10449 13:57:58.037511 <6>[ 0.102135] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10450 13:57:58.040843 <6>[ 0.102439] CPU features: detected: Spectre-v4
10451 13:57:58.047409 <6>[ 0.102445] CPU features: detected: Spectre-BHB
10452 13:57:58.050695 <6>[ 0.102450] Detected PIPT I-cache on CPU4
10453 13:57:58.057118 <6>[ 0.102510] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10454 13:57:58.063809 <6>[ 0.102527] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10455 13:57:58.070431 <6>[ 0.102819] Detected PIPT I-cache on CPU5
10456 13:57:58.077197 <6>[ 0.102883] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10457 13:57:58.083716 <6>[ 0.102900] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10458 13:57:58.086863 <6>[ 0.103180] Detected PIPT I-cache on CPU6
10459 13:57:58.093449 <6>[ 0.103246] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10460 13:57:58.100144 <6>[ 0.103262] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10461 13:57:58.106831 <6>[ 0.103558] Detected PIPT I-cache on CPU7
10462 13:57:58.113496 <6>[ 0.103623] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10463 13:57:58.119915 <6>[ 0.103639] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10464 13:57:58.123474 <6>[ 0.103687] smp: Brought up 1 node, 8 CPUs
10465 13:57:58.129831 <6>[ 0.244997] SMP: Total of 8 processors activated.
10466 13:57:58.133356 <6>[ 0.249949] CPU features: detected: 32-bit EL0 Support
10467 13:57:58.143001 <6>[ 0.255344] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10468 13:57:58.149930 <6>[ 0.264144] CPU features: detected: Common not Private translations
10469 13:57:58.156391 <6>[ 0.270620] CPU features: detected: CRC32 instructions
10470 13:57:58.162831 <6>[ 0.275971] CPU features: detected: RCpc load-acquire (LDAPR)
10471 13:57:58.165934 <6>[ 0.281931] CPU features: detected: LSE atomic instructions
10472 13:57:58.172672 <6>[ 0.287748] CPU features: detected: Privileged Access Never
10473 13:57:58.179178 <6>[ 0.293564] CPU features: detected: RAS Extension Support
10474 13:57:58.186034 <6>[ 0.299207] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10475 13:57:58.189036 <6>[ 0.306426] CPU: All CPU(s) started at EL2
10476 13:57:58.195610 <6>[ 0.310743] alternatives: applying system-wide alternatives
10477 13:57:58.205723 <6>[ 0.321464] devtmpfs: initialized
10478 13:57:58.218060 <6>[ 0.330415] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10479 13:57:58.227940 <6>[ 0.340378] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10480 13:57:58.234819 <6>[ 0.348588] pinctrl core: initialized pinctrl subsystem
10481 13:57:58.237857 <6>[ 0.355381] DMI not present or invalid.
10482 13:57:58.244834 <6>[ 0.359794] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10483 13:57:58.254418 <6>[ 0.366595] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10484 13:57:58.260978 <6>[ 0.374182] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10485 13:57:58.271085 <6>[ 0.382413] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10486 13:57:58.274679 <6>[ 0.390654] audit: initializing netlink subsys (disabled)
10487 13:57:58.284419 <5>[ 0.396347] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10488 13:57:58.290754 <6>[ 0.397108] thermal_sys: Registered thermal governor 'step_wise'
10489 13:57:58.297367 <6>[ 0.404314] thermal_sys: Registered thermal governor 'power_allocator'
10490 13:57:58.300792 <6>[ 0.410570] cpuidle: using governor menu
10491 13:57:58.307492 <6>[ 0.421528] NET: Registered PF_QIPCRTR protocol family
10492 13:57:58.313797 <6>[ 0.427013] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10493 13:57:58.317381 <6>[ 0.434116] ASID allocator initialised with 32768 entries
10494 13:57:58.325127 <6>[ 0.440749] Serial: AMBA PL011 UART driver
10495 13:57:58.333892 <4>[ 0.449875] Trying to register duplicate clock ID: 134
10496 13:57:58.390605 <6>[ 0.509663] KASLR enabled
10497 13:57:58.404999 <6>[ 0.517441] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10498 13:57:58.411482 <6>[ 0.524452] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10499 13:57:58.418401 <6>[ 0.530940] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10500 13:57:58.424714 <6>[ 0.537946] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10501 13:57:58.431379 <6>[ 0.544434] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10502 13:57:58.438104 <6>[ 0.551439] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10503 13:57:58.444445 <6>[ 0.557927] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10504 13:57:58.451110 <6>[ 0.564932] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10505 13:57:58.454548 <6>[ 0.572470] ACPI: Interpreter disabled.
10506 13:57:58.463215 <6>[ 0.578968] iommu: Default domain type: Translated
10507 13:57:58.469942 <6>[ 0.584079] iommu: DMA domain TLB invalidation policy: strict mode
10508 13:57:58.473082 <5>[ 0.590738] SCSI subsystem initialized
10509 13:57:58.479868 <6>[ 0.594906] usbcore: registered new interface driver usbfs
10510 13:57:58.486354 <6>[ 0.600638] usbcore: registered new interface driver hub
10511 13:57:58.489844 <6>[ 0.606189] usbcore: registered new device driver usb
10512 13:57:58.496455 <6>[ 0.612332] pps_core: LinuxPPS API ver. 1 registered
10513 13:57:58.506674 <6>[ 0.617526] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10514 13:57:58.509768 <6>[ 0.626873] PTP clock support registered
10515 13:57:58.513178 <6>[ 0.631117] EDAC MC: Ver: 3.0.0
10516 13:57:58.520667 <6>[ 0.636312] FPGA manager framework
10517 13:57:58.527558 <6>[ 0.639993] Advanced Linux Sound Architecture Driver Initialized.
10518 13:57:58.530362 <6>[ 0.646779] vgaarb: loaded
10519 13:57:58.536864 <6>[ 0.649937] clocksource: Switched to clocksource arch_sys_counter
10520 13:57:58.540496 <5>[ 0.656378] VFS: Disk quotas dquot_6.6.0
10521 13:57:58.547047 <6>[ 0.660563] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10522 13:57:58.550394 <6>[ 0.667737] pnp: PnP ACPI: disabled
10523 13:57:58.558830 <6>[ 0.674484] NET: Registered PF_INET protocol family
10524 13:57:58.568570 <6>[ 0.680076] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10525 13:57:58.580105 <6>[ 0.692386] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10526 13:57:58.589850 <6>[ 0.701199] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10527 13:57:58.596596 <6>[ 0.709172] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10528 13:57:58.606132 <6>[ 0.717827] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10529 13:57:58.612866 <6>[ 0.727584] TCP: Hash tables configured (established 65536 bind 65536)
10530 13:57:58.619481 <6>[ 0.734447] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10531 13:57:58.629562 <6>[ 0.741646] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10532 13:57:58.636118 <6>[ 0.749345] NET: Registered PF_UNIX/PF_LOCAL protocol family
10533 13:57:58.639470 <6>[ 0.755495] RPC: Registered named UNIX socket transport module.
10534 13:57:58.645946 <6>[ 0.761646] RPC: Registered udp transport module.
10535 13:57:58.649161 <6>[ 0.766579] RPC: Registered tcp transport module.
10536 13:57:58.655913 <6>[ 0.771511] RPC: Registered tcp NFSv4.1 backchannel transport module.
10537 13:57:58.662441 <6>[ 0.778175] PCI: CLS 0 bytes, default 64
10538 13:57:58.665760 <6>[ 0.782488] Unpacking initramfs...
10539 13:57:58.681878 <6>[ 0.794504] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10540 13:57:58.691948 <6>[ 0.803160] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10541 13:57:58.695173 <6>[ 0.812027] kvm [1]: IPA Size Limit: 40 bits
10542 13:57:58.701843 <6>[ 0.816556] kvm [1]: GICv3: no GICV resource entry
10543 13:57:58.704943 <6>[ 0.821577] kvm [1]: disabling GICv2 emulation
10544 13:57:58.711610 <6>[ 0.826264] kvm [1]: GIC system register CPU interface enabled
10545 13:57:58.715185 <6>[ 0.832450] kvm [1]: vgic interrupt IRQ18
10546 13:57:58.721943 <6>[ 0.836807] kvm [1]: VHE mode initialized successfully
10547 13:57:58.728343 <5>[ 0.843334] Initialise system trusted keyrings
10548 13:57:58.734827 <6>[ 0.848131] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10549 13:57:58.742603 <6>[ 0.858151] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10550 13:57:58.748871 <5>[ 0.864528] NFS: Registering the id_resolver key type
10551 13:57:58.752429 <5>[ 0.869831] Key type id_resolver registered
10552 13:57:58.759124 <5>[ 0.874244] Key type id_legacy registered
10553 13:57:58.765550 <6>[ 0.878522] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10554 13:57:58.772320 <6>[ 0.885441] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10555 13:57:58.778550 <6>[ 0.893174] 9p: Installing v9fs 9p2000 file system support
10556 13:57:58.815190 <5>[ 0.930745] Key type asymmetric registered
10557 13:57:58.818331 <5>[ 0.935079] Asymmetric key parser 'x509' registered
10558 13:57:58.828417 <6>[ 0.940223] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10559 13:57:58.831489 <6>[ 0.947835] io scheduler mq-deadline registered
10560 13:57:58.834644 <6>[ 0.952608] io scheduler kyber registered
10561 13:57:58.853984 <6>[ 0.970096] EINJ: ACPI disabled.
10562 13:57:58.886990 <4>[ 0.996190] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 13:57:58.896755 <4>[ 1.006846] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 13:57:58.911825 <6>[ 1.027880] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10565 13:57:58.920079 <6>[ 1.036002] printk: console [ttyS0] disabled
10566 13:57:58.948231 <6>[ 1.060674] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10567 13:57:58.954837 <6>[ 1.070138] printk: console [ttyS0] enabled
10568 13:57:58.958320 <6>[ 1.070138] printk: console [ttyS0] enabled
10569 13:57:58.964731 <6>[ 1.079031] printk: bootconsole [mtk8250] disabled
10570 13:57:58.967997 <6>[ 1.079031] printk: bootconsole [mtk8250] disabled
10571 13:57:58.974825 <6>[ 1.090337] SuperH (H)SCI(F) driver initialized
10572 13:57:58.977886 <6>[ 1.095650] msm_serial: driver initialized
10573 13:57:58.992282 <6>[ 1.104765] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10574 13:57:59.002343 <6>[ 1.113325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10575 13:57:59.008782 <6>[ 1.121867] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10576 13:57:59.018819 <6>[ 1.130500] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10577 13:57:59.028813 <6>[ 1.139209] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10578 13:57:59.035407 <6>[ 1.147923] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10579 13:57:59.045255 <6>[ 1.156464] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10580 13:57:59.051749 <6>[ 1.165275] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10581 13:57:59.061565 <6>[ 1.173822] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10582 13:57:59.073783 <6>[ 1.189637] loop: module loaded
10583 13:57:59.080253 <6>[ 1.195664] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10584 13:57:59.103083 <4>[ 1.219155] mtk-pmic-keys: Failed to locate of_node [id: -1]
10585 13:57:59.110556 <6>[ 1.226288] megasas: 07.719.03.00-rc1
10586 13:57:59.120336 <6>[ 1.236258] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10587 13:57:59.133537 <6>[ 1.249322] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10588 13:57:59.150037 <6>[ 1.265804] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10589 13:57:59.206777 <6>[ 1.315885] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10590 13:57:59.456942 <6>[ 1.572708] Freeing initrd memory: 18324K
10591 13:57:59.468514 <6>[ 1.584279] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10592 13:57:59.479582 <6>[ 1.595357] tun: Universal TUN/TAP device driver, 1.6
10593 13:57:59.482665 <6>[ 1.601441] thunder_xcv, ver 1.0
10594 13:57:59.486301 <6>[ 1.604945] thunder_bgx, ver 1.0
10595 13:57:59.489219 <6>[ 1.608441] nicpf, ver 1.0
10596 13:57:59.499784 <6>[ 1.612482] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10597 13:57:59.503317 <6>[ 1.619958] hns3: Copyright (c) 2017 Huawei Corporation.
10598 13:57:59.506590 <6>[ 1.625545] hclge is initializing
10599 13:57:59.513367 <6>[ 1.629122] e1000: Intel(R) PRO/1000 Network Driver
10600 13:57:59.520033 <6>[ 1.634251] e1000: Copyright (c) 1999-2006 Intel Corporation.
10601 13:57:59.523101 <6>[ 1.640264] e1000e: Intel(R) PRO/1000 Network Driver
10602 13:57:59.529674 <6>[ 1.645479] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10603 13:57:59.536342 <6>[ 1.651666] igb: Intel(R) Gigabit Ethernet Network Driver
10604 13:57:59.543144 <6>[ 1.657316] igb: Copyright (c) 2007-2014 Intel Corporation.
10605 13:57:59.549883 <6>[ 1.663153] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10606 13:57:59.556439 <6>[ 1.669671] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10607 13:57:59.559726 <6>[ 1.676134] sky2: driver version 1.30
10608 13:57:59.566271 <6>[ 1.681165] VFIO - User Level meta-driver version: 0.3
10609 13:57:59.573690 <6>[ 1.689451] usbcore: registered new interface driver usb-storage
10610 13:57:59.580254 <6>[ 1.695903] usbcore: registered new device driver onboard-usb-hub
10611 13:57:59.589516 <6>[ 1.705151] mt6397-rtc mt6359-rtc: registered as rtc0
10612 13:57:59.599469 <6>[ 1.710617] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:58:00 UTC (1706795880)
10613 13:57:59.602861 <6>[ 1.720200] i2c_dev: i2c /dev entries driver
10614 13:57:59.619387 <6>[ 1.732175] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10615 13:57:59.639290 <6>[ 1.755163] cpu cpu0: EM: created perf domain
10616 13:57:59.642467 <6>[ 1.760095] cpu cpu4: EM: created perf domain
10617 13:57:59.650087 <6>[ 1.765721] sdhci: Secure Digital Host Controller Interface driver
10618 13:57:59.656555 <6>[ 1.772153] sdhci: Copyright(c) Pierre Ossman
10619 13:57:59.663325 <6>[ 1.777118] Synopsys Designware Multimedia Card Interface Driver
10620 13:57:59.669797 <6>[ 1.783767] sdhci-pltfm: SDHCI platform and OF driver helper
10621 13:57:59.673157 <6>[ 1.783814] mmc0: CQHCI version 5.10
10622 13:57:59.679856 <6>[ 1.793885] ledtrig-cpu: registered to indicate activity on CPUs
10623 13:57:59.686449 <6>[ 1.800889] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10624 13:57:59.693130 <6>[ 1.807967] usbcore: registered new interface driver usbhid
10625 13:57:59.696487 <6>[ 1.813789] usbhid: USB HID core driver
10626 13:57:59.702915 <6>[ 1.817988] spi_master spi0: will run message pump with realtime priority
10627 13:57:59.746726 <6>[ 1.855825] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10628 13:57:59.765887 <6>[ 1.871744] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10629 13:57:59.769369 <6>[ 1.885410] mmc0: Command Queue Engine enabled
10630 13:57:59.776158 <6>[ 1.890189] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10631 13:57:59.782777 <6>[ 1.897130] cros-ec-spi spi0.0: Chrome EC device registered
10632 13:57:59.785902 <6>[ 1.897409] mmcblk0: mmc0:0001 DA4128 116 GiB
10633 13:57:59.797264 <6>[ 1.912995] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10634 13:57:59.804299 <6>[ 1.920284] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10635 13:57:59.810774 <6>[ 1.926366] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10636 13:57:59.821098 <6>[ 1.932160] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10637 13:57:59.827597 <6>[ 1.932351] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10638 13:57:59.830623 <6>[ 1.942650] NET: Registered PF_PACKET protocol family
10639 13:57:59.837425 <6>[ 1.953386] 9pnet: Installing 9P2000 support
10640 13:57:59.840759 <5>[ 1.957935] Key type dns_resolver registered
10641 13:57:59.847628 <6>[ 1.962892] registered taskstats version 1
10642 13:57:59.850628 <5>[ 1.967282] Loading compiled-in X.509 certificates
10643 13:57:59.879305 <4>[ 1.988393] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 13:57:59.889380 <4>[ 1.999167] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 13:57:59.895960 <3>[ 2.009704] debugfs: File 'uA_load' in directory '/' already present!
10646 13:57:59.902503 <3>[ 2.016471] debugfs: File 'min_uV' in directory '/' already present!
10647 13:57:59.909464 <3>[ 2.023094] debugfs: File 'max_uV' in directory '/' already present!
10648 13:57:59.915959 <3>[ 2.029707] debugfs: File 'constraint_flags' in directory '/' already present!
10649 13:57:59.926313 <3>[ 2.039132] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10650 13:57:59.935597 <6>[ 2.051536] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10651 13:57:59.942571 <6>[ 2.058387] xhci-mtk 11200000.usb: xHCI Host Controller
10652 13:57:59.949269 <6>[ 2.063890] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10653 13:57:59.959175 <6>[ 2.071737] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10654 13:57:59.965769 <6>[ 2.081151] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10655 13:57:59.972310 <6>[ 2.087237] xhci-mtk 11200000.usb: xHCI Host Controller
10656 13:57:59.984216 <6>[ 2.092719] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10657 13:57:59.985780 <6>[ 2.100366] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10658 13:57:59.992372 <6>[ 2.108236] hub 1-0:1.0: USB hub found
10659 13:58:00.028915 <6>[ 2.112264] hub 1-0:1.0: 1 port detected
10660 13:58:00.029471 <6>[ 2.116547] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10661 13:58:00.029618 <6>[ 2.125306] hub 2-0:1.0: USB hub found
10662 13:58:00.029721 <6>[ 2.129335] hub 2-0:1.0: 1 port detected
10663 13:58:00.029821 <6>[ 2.135870] mtk-msdc 11f70000.mmc: Got CD GPIO
10664 13:58:00.032774 <6>[ 2.145324] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10665 13:58:00.039317 <6>[ 2.153352] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10666 13:58:00.049274 <4>[ 2.161248] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10667 13:58:00.059480 <6>[ 2.170772] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10668 13:58:00.065987 <6>[ 2.178849] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10669 13:58:00.072910 <6>[ 2.186880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10670 13:58:00.082749 <6>[ 2.194794] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10671 13:58:00.089307 <6>[ 2.202614] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10672 13:58:00.099134 <6>[ 2.210431] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10673 13:58:00.109084 <6>[ 2.220869] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10674 13:58:00.115737 <6>[ 2.229229] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10675 13:58:00.125667 <6>[ 2.237582] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10676 13:58:00.132302 <6>[ 2.245921] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10677 13:58:00.142027 <6>[ 2.254262] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10678 13:58:00.148760 <6>[ 2.262601] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10679 13:58:00.158847 <6>[ 2.270939] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10680 13:58:00.165437 <6>[ 2.279278] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10681 13:58:00.175495 <6>[ 2.287618] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10682 13:58:00.182373 <6>[ 2.295956] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10683 13:58:00.192413 <6>[ 2.304295] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10684 13:58:00.198625 <6>[ 2.312634] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10685 13:58:00.208880 <6>[ 2.320973] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10686 13:58:00.215578 <6>[ 2.329311] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10687 13:58:00.225255 <6>[ 2.337650] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10688 13:58:00.231946 <6>[ 2.346439] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10689 13:58:00.238782 <6>[ 2.353584] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10690 13:58:00.245180 <6>[ 2.360318] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10691 13:58:00.251771 <6>[ 2.367123] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10692 13:58:00.258533 <6>[ 2.374083] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10693 13:58:00.268445 <6>[ 2.380926] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10694 13:58:00.278459 <6>[ 2.390055] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10695 13:58:00.288301 <6>[ 2.399173] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10696 13:58:00.298151 <6>[ 2.408466] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10697 13:58:00.308284 <6>[ 2.417932] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10698 13:58:00.314697 <6>[ 2.427398] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10699 13:58:00.324823 <6>[ 2.436517] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10700 13:58:00.334526 <6>[ 2.445982] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10701 13:58:00.344486 <6>[ 2.455100] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10702 13:58:00.354346 <6>[ 2.464394] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10703 13:58:00.364378 <6>[ 2.474553] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10704 13:58:00.373867 <6>[ 2.486147] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10705 13:58:00.380607 <6>[ 2.495681] Trying to probe devices needed for running init ...
10706 13:58:00.425712 <6>[ 2.538233] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10707 13:58:00.579273 <6>[ 2.695334] hub 1-1:1.0: USB hub found
10708 13:58:00.582522 <6>[ 2.699788] hub 1-1:1.0: 4 ports detected
10709 13:58:00.591492 <6>[ 2.707640] hub 1-1:1.0: USB hub found
10710 13:58:00.594899 <6>[ 2.711940] hub 1-1:1.0: 4 ports detected
10711 13:58:00.705804 <6>[ 2.818597] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10712 13:58:00.733567 <6>[ 2.849623] hub 2-1:1.0: USB hub found
10713 13:58:00.736882 <6>[ 2.854201] hub 2-1:1.0: 3 ports detected
10714 13:58:00.746702 <6>[ 2.862781] hub 2-1:1.0: USB hub found
10715 13:58:00.750143 <6>[ 2.867240] hub 2-1:1.0: 3 ports detected
10716 13:58:00.917317 <6>[ 3.030252] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10717 13:58:01.049322 <6>[ 3.165163] hub 1-1.4:1.0: USB hub found
10718 13:58:01.052342 <6>[ 3.169663] hub 1-1.4:1.0: 2 ports detected
10719 13:58:01.060521 <6>[ 3.176528] hub 1-1.4:1.0: USB hub found
10720 13:58:01.063696 <6>[ 3.181066] hub 1-1.4:1.0: 2 ports detected
10721 13:58:01.129289 <6>[ 3.242285] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10722 13:58:01.361516 <6>[ 3.474254] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10723 13:58:01.553534 <6>[ 3.666224] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10724 13:58:12.678609 <6>[ 14.799224] ALSA device list:
10725 13:58:12.685193 <6>[ 14.802517] No soundcards found.
10726 13:58:12.693143 <6>[ 14.810490] Freeing unused kernel memory: 8448K
10727 13:58:12.696379 <6>[ 14.815551] Run /init as init process
10728 13:58:12.707886 Loading, please wait...
10729 13:58:12.738242 Starting systemd-udevd version 252.19-1~deb12u1
10730 13:58:12.975372 <6>[ 15.089296] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10731 13:58:12.990906 <6>[ 15.105093] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10732 13:58:12.994217 <6>[ 15.110846] remoteproc remoteproc0: scp is available
10733 13:58:13.004392 <6>[ 15.113235] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10734 13:58:13.011004 <6>[ 15.118566] remoteproc remoteproc0: powering up scp
10735 13:58:13.017541 <6>[ 15.129480] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10736 13:58:13.027428 <6>[ 15.133619] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10737 13:58:13.034147 <6>[ 15.149351] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10738 13:58:13.037409 <6>[ 15.149875] mc: Linux media interface: v0.10
10739 13:58:13.044318 <3>[ 15.158851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 13:58:13.053920 <3>[ 15.167921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 13:58:13.060377 <3>[ 15.176038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 13:58:13.067582 <6>[ 15.184673] usbcore: registered new device driver r8152-cfgselector
10743 13:58:13.077375 <3>[ 15.186399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 13:58:13.083848 <6>[ 15.188791] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10745 13:58:13.090197 <6>[ 15.189185] videodev: Linux video capture interface: v2.00
10746 13:58:13.097028 <4>[ 15.194971] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10747 13:58:13.107348 <3>[ 15.199568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 13:58:13.114011 <4>[ 15.209161] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10749 13:58:13.120791 <3>[ 15.212959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 13:58:13.130606 <3>[ 15.212969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 13:58:13.137400 <3>[ 15.212974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 13:58:13.147754 <4>[ 15.215521] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10753 13:58:13.150930 <4>[ 15.215521] Fallback method does not support PEC.
10754 13:58:13.160915 <3>[ 15.232638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10755 13:58:13.167680 <3>[ 15.236563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 13:58:13.174422 <6>[ 15.259548] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10757 13:58:13.184793 <3>[ 15.260453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 13:58:13.190923 <3>[ 15.266534] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10759 13:58:13.197386 <6>[ 15.274116] pci_bus 0000:00: root bus resource [bus 00-ff]
10760 13:58:13.203969 <6>[ 15.281317] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10761 13:58:13.213735 <6>[ 15.281445] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10762 13:58:13.220363 <6>[ 15.281451] remoteproc remoteproc0: remote processor scp is now up
10763 13:58:13.226938 <3>[ 15.282554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 13:58:13.233613 <6>[ 15.290617] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10765 13:58:13.243484 <6>[ 15.292219] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10766 13:58:13.250288 <6>[ 15.293402] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10767 13:58:13.260346 <3>[ 15.297473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 13:58:13.266879 <3>[ 15.297512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 13:58:13.276696 <6>[ 15.305663] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10770 13:58:13.286573 <6>[ 15.314179] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10771 13:58:13.296357 <3>[ 15.314331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 13:58:13.303349 <3>[ 15.314337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 13:58:13.313073 <3>[ 15.314345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 13:58:13.319856 <6>[ 15.314602] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10775 13:58:13.326487 <6>[ 15.320113] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10776 13:58:13.336359 <6>[ 15.326515] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10777 13:58:13.342693 <3>[ 15.327111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 13:58:13.352998 <3>[ 15.327131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 13:58:13.362659 <6>[ 15.330670] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10780 13:58:13.369280 <6>[ 15.335637] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10781 13:58:13.379155 <4>[ 15.353888] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10782 13:58:13.382310 <6>[ 15.357750] pci 0000:00:00.0: supports D1 D2
10783 13:58:13.385810 <6>[ 15.358110] Bluetooth: Core ver 2.22
10784 13:58:13.392305 <6>[ 15.358250] NET: Registered PF_BLUETOOTH protocol family
10785 13:58:13.399117 <6>[ 15.358253] Bluetooth: HCI device and connection manager initialized
10786 13:58:13.402464 <6>[ 15.358286] Bluetooth: HCI socket layer initialized
10787 13:58:13.409012 <6>[ 15.358292] Bluetooth: L2CAP socket layer initialized
10788 13:58:13.412310 <6>[ 15.358302] Bluetooth: SCO socket layer initialized
10789 13:58:13.422321 <4>[ 15.365886] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10790 13:58:13.428771 <6>[ 15.374113] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10791 13:58:13.435265 <6>[ 15.376059] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10792 13:58:13.445132 <6>[ 15.391536] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10793 13:58:13.451899 <6>[ 15.400381] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10794 13:58:13.462014 <6>[ 15.411781] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10795 13:58:13.472028 <6>[ 15.418414] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10796 13:58:13.475148 <6>[ 15.419397] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10797 13:58:13.481638 <6>[ 15.426840] usbcore: registered new interface driver uvcvideo
10798 13:58:13.488113 <6>[ 15.427097] usbcore: registered new interface driver btusb
10799 13:58:13.498063 <4>[ 15.428030] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10800 13:58:13.504584 <3>[ 15.428040] Bluetooth: hci0: Failed to load firmware file (-2)
10801 13:58:13.511322 <3>[ 15.428042] Bluetooth: hci0: Failed to set up firmware (-2)
10802 13:58:13.521154 <4>[ 15.428046] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10803 13:58:13.528060 <6>[ 15.434574] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10804 13:58:13.534561 <6>[ 15.438268] r8152 2-1.3:1.0 eth0: v1.12.13
10805 13:58:13.537842 <6>[ 15.438301] usbcore: registered new interface driver r8152
10806 13:58:13.544532 <6>[ 15.466388] usbcore: registered new interface driver cdc_ether
10807 13:58:13.551043 <6>[ 15.474353] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10808 13:58:13.557639 <6>[ 15.491274] usbcore: registered new interface driver r8153_ecm
10809 13:58:13.564209 <6>[ 15.500243] pci 0000:01:00.0: supports D1 D2
10810 13:58:13.567446 <6>[ 15.520596] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10811 13:58:13.577400 <6>[ 15.520640] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10812 13:58:13.583938 <6>[ 15.530096] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10813 13:58:13.590522 <6>[ 15.705137] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10814 13:58:13.597203 <6>[ 15.713219] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10815 13:58:13.607139 <6>[ 15.721219] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10816 13:58:13.613586 <6>[ 15.729221] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10817 13:58:13.623703 <6>[ 15.737221] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10818 13:58:13.626823 <6>[ 15.745222] pci 0000:00:00.0: PCI bridge to [bus 01]
10819 13:58:13.637015 <6>[ 15.750440] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10820 13:58:13.643341 <6>[ 15.758582] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10821 13:58:13.650311 <6>[ 15.765434] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10822 13:58:13.656754 <6>[ 15.772233] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10823 13:58:13.672804 <5>[ 15.786921] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10824 13:58:13.695900 <5>[ 15.810244] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10825 13:58:13.702850 <5>[ 15.817595] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10826 13:58:13.712784 <4>[ 15.826062] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10827 13:58:13.715906 <6>[ 15.834956] cfg80211: failed to load regulatory.db
10828 13:58:13.760006 <6>[ 15.874080] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10829 13:58:13.766289 <6>[ 15.881589] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10830 13:58:13.790782 <6>[ 15.908249] mt7921e 0000:01:00.0: ASIC revision: 79610010
10831 13:58:13.895938 <6>[ 16.010030] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10832 13:58:13.899266 <6>[ 16.010030]
10833 13:58:13.921460 Begin: Loading essential drivers ... done.
10834 13:58:13.924765 Begin: Running /scripts/init-premount ... done.
10835 13:58:13.931382 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10836 13:58:13.941426 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10837 13:58:13.944798 Device /sys/class/net/enx0024323078ff found
10838 13:58:13.944925 done.
10839 13:58:13.951186 Begin: Waiting up to 180 secs for any network device to become available ... done.
10840 13:58:13.992300 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10841 13:58:14.163434 <6>[ 16.277741] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10842 13:58:14.889359 <6>[ 17.007218] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10843 13:58:15.032771 <6>[ 17.150201] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10844 13:58:15.092918 IP-Config: no response after 2 secs - giving up
10845 13:58:15.135939 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10846 13:58:15.168461 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10847 13:58:15.872719 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10848 13:58:15.879409 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10849 13:58:15.886258 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10850 13:58:15.892689 host : mt8192-asurada-spherion-r0-cbg-8
10851 13:58:15.899084 domain : lava-rack
10852 13:58:15.905942 rootserver: 192.168.201.1 rootpath:
10853 13:58:15.906065 filename :
10854 13:58:16.031979 done.
10855 13:58:16.040122 Begin: Running /scripts/nfs-bottom ... done.
10856 13:58:16.059051 Begin: Running /scripts/init-bottom ... done.
10857 13:58:17.428828 <6>[ 19.546668] NET: Registered PF_INET6 protocol family
10858 13:58:17.436384 <6>[ 19.554391] Segment Routing with IPv6
10859 13:58:17.439791 <6>[ 19.558378] In-situ OAM (IOAM) with IPv6
10860 13:58:17.626292 <30>[ 19.717774] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10861 13:58:17.632920 <30>[ 19.750911] systemd[1]: Detected architecture arm64.
10862 13:58:17.649027
10863 13:58:17.652081 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10864 13:58:17.652179
10865 13:58:17.677695 <30>[ 19.795622] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10866 13:58:18.751589 <30>[ 20.866430] systemd[1]: Queued start job for default target graphical.target.
10867 13:58:18.780436 <30>[ 20.895222] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10868 13:58:18.787312 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10869 13:58:18.809329 <30>[ 20.924138] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10870 13:58:18.819115 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10871 13:58:18.837256 <30>[ 20.952048] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10872 13:58:18.847204 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10873 13:58:18.865000 <30>[ 20.979654] systemd[1]: Created slice user.slice - User and Session Slice.
10874 13:58:18.871666 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10875 13:58:18.895426 <30>[ 21.006623] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10876 13:58:18.901864 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10877 13:58:18.922894 <30>[ 21.034487] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10878 13:58:18.929540 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10879 13:58:18.957792 <30>[ 21.062868] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10880 13:58:18.968015 <30>[ 21.082919] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10881 13:58:18.974827 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10882 13:58:18.996121 <30>[ 21.110733] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10883 13:58:19.006064 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10884 13:58:19.020545 <30>[ 21.138411] systemd[1]: Reached target paths.target - Path Units.
10885 13:58:19.027265 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10886 13:58:19.047921 <30>[ 21.162695] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10887 13:58:19.054683 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10888 13:58:19.068355 <30>[ 21.186222] systemd[1]: Reached target slices.target - Slice Units.
10889 13:58:19.078316 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10890 13:58:19.092188 <30>[ 21.210305] systemd[1]: Reached target swap.target - Swaps.
10891 13:58:19.099059 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10892 13:58:19.119698 <30>[ 21.234314] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10893 13:58:19.129282 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10894 13:58:19.147969 <30>[ 21.262681] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10895 13:58:19.157838 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10896 13:58:19.178940 <30>[ 21.293546] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10897 13:58:19.188743 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10898 13:58:19.204925 <30>[ 21.319754] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10899 13:58:19.214785 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10900 13:58:19.232408 <30>[ 21.346949] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10901 13:58:19.238764 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10902 13:58:19.257351 <30>[ 21.371796] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10903 13:58:19.266650 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10904 13:58:19.286464 <30>[ 21.401229] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10905 13:58:19.296090 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10906 13:58:19.312066 <30>[ 21.426703] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10907 13:58:19.318583 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10908 13:58:19.372022 <30>[ 21.486752] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10909 13:58:19.378398 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10910 13:58:19.398180 <30>[ 21.513003] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10911 13:58:19.404883 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10912 13:58:19.425920 <30>[ 21.540798] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10913 13:58:19.432500 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10914 13:58:19.458612 <30>[ 21.566876] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10915 13:58:19.504597 <30>[ 21.619102] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10916 13:58:19.514239 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10917 13:58:19.537277 <30>[ 21.652180] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10918 13:58:19.547121 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10919 13:58:19.569729 <30>[ 21.684316] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10920 13:58:19.576030 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10921 13:58:19.601051 <30>[ 21.715959] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10922 13:58:19.610951 Starting [0;1;39mmodpr<6>[ 21.726923] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10923 13:58:19.617516 obe@drm.service[0m - Load Kernel Module drm...
10924 13:58:19.672231 <30>[ 21.786969] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10925 13:58:19.682016 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10926 13:58:19.702596 <30>[ 21.817524] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10927 13:58:19.709240 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10928 13:58:19.737553 <30>[ 21.852238] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10929 13:58:19.743959 Startin<6>[ 21.861057] fuse: init (API version 7.37)
10930 13:58:19.750535 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10931 13:58:19.800150 <30>[ 21.914970] systemd[1]: Starting systemd-journald.service - Journal Service...
10932 13:58:19.806485 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10933 13:58:19.841246 <30>[ 21.955980] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10934 13:58:19.847782 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10935 13:58:19.878761 <30>[ 21.990250] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10936 13:58:19.885141 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10937 13:58:19.944974 <30>[ 22.059117] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10938 13:58:19.955036 <3>[ 22.067664] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 13:58:19.961726 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10940 13:58:19.982969 <3>[ 22.097832] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 13:58:19.992912 <30>[ 22.097985] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10942 13:58:19.999329 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10943 13:58:20.032218 <30>[ 22.146921] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10944 13:58:20.038975 <3>[ 22.151037] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 13:58:20.048671 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10946 13:58:20.067993 <30>[ 22.182626] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10947 13:58:20.074645 <3>[ 22.184427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 13:58:20.084846 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10949 13:58:20.104406 <3>[ 22.219393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 13:58:20.114461 <30>[ 22.228856] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10951 13:58:20.121224 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10952 13:58:20.135308 <3>[ 22.250063] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 13:58:20.145293 <30>[ 22.259870] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10954 13:58:20.156242 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10955 13:58:20.165799 <3>[ 22.278972] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 13:58:20.172465 <30>[ 22.289917] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10957 13:58:20.183361 <30>[ 22.297808] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10958 13:58:20.196832 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 22.309518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 13:58:20.200096 onfigfs…[0m - Load Kernel Module configfs.
10960 13:58:20.218356 <30>[ 22.336019] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10961 13:58:20.229473 <30>[ 22.343806] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10962 13:58:20.239203 <3>[ 22.344218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 13:58:20.245711 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10964 13:58:20.262794 <30>[ 22.380357] systemd[1]: modprobe@drm.service: Deactivated successfully.
10965 13:58:20.273445 <30>[ 22.388376] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10966 13:58:20.283430 [[0;32m OK [<3>[ 22.396650] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 13:58:20.290217 0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10968 13:58:20.313906 <30>[ 22.428349] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10969 13:58:20.323593 <30>[ 22.437036] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10970 13:58:20.330464 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10971 13:58:20.349434 <30>[ 22.467385] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10972 13:58:20.360814 <30>[ 22.475428] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10973 13:58:20.384206 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Mo<4>[ 22.489730] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10974 13:58:20.384339 dule fuse.
10975 13:58:20.390732 <3>[ 22.506207] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10976 13:58:20.408273 <30>[ 22.523077] systemd[1]: Started systemd-journald.service - Journal Service.
10977 13:58:20.415116 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10978 13:58:20.441237 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10979 13:58:20.460783 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10980 13:58:20.480547 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10981 13:58:20.501006 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10982 13:58:20.520838 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10983 13:58:20.542168 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10984 13:58:20.580209 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10985 13:58:20.603359 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10986 13:58:20.628999 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10987 13:58:20.654338 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10988 13:58:20.683165 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10989 13:58:20.692985 <46>[ 22.807277] systemd-journald[310]: Received client request to flush runtime journal.
10990 13:58:20.709855 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10991 13:58:21.007764 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10992 13:58:21.024152 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10993 13:58:21.044667 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10994 13:58:21.469080 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10995 13:58:22.079788 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10996 13:58:22.116415 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10997 13:58:22.140412 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10998 13:58:22.221305 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10999 13:58:22.240284 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11000 13:58:22.259636 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11001 13:58:22.307766 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11002 13:58:22.328639 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11003 13:58:22.356937 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11004 13:58:22.391724 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11005 13:58:22.403910 See 'systemctl status systemd-binfmt.service' for details.
11006 13:58:22.645032 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11007 13:58:22.712753 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11008 13:58:22.794353 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11009 13:58:23.030529 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11010 13:58:23.089976 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11011 13:58:23.122647 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11012 13:58:23.165358 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11013 13:58:23.186030 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11014 13:58:23.292000 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11015 13:58:23.313552 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11016 13:58:23.339387 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11017 13:58:23.400313 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11018 13:58:23.420132 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11019 13:58:23.447080 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11020 13:58:23.480288 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11021 13:58:23.516782 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11022 13:58:23.572895 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11023 13:58:23.591558 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11024 13:58:23.615326 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11025 13:58:23.627222 <46>[ 25.745743] systemd-journald[310]: Time jumped backwards, rotating.
11026 13:58:23.637242 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11027 13:58:23.662960 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11028 13:58:23.948784 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11029 13:58:23.967527 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11030 13:58:24.394504 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11031 13:58:24.726733 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11032 13:58:24.742829 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11033 13:58:24.923121 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11034 13:58:24.942861 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11035 13:58:24.959392 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11036 13:58:25.116790 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11037 13:58:25.151180 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11038 13:58:25.207926 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11039 13:58:25.232005 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11040 13:58:25.414046 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11041 13:58:25.473484 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11042 13:58:25.516155 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11043 13:58:25.536104 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11044 13:58:25.565043 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11045 13:58:25.599448 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11046 13:58:25.623050 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11047 13:58:25.665381 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11048 13:58:25.689027 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11049 13:58:25.741646 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11050 13:58:25.765756 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11051 13:58:25.811769 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11052 13:58:25.898380 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11053 13:58:25.975664
11054 13:58:25.975808
11055 13:58:25.978954 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11056 13:58:25.979060
11057 13:58:25.981971 debian-bookworm-arm64 login: root (automatic login)
11058 13:58:25.982045
11059 13:58:25.982105
11060 13:58:26.307580 Linux debian-bookworm-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
11061 13:58:26.307760
11062 13:58:26.313849 The programs included with the Debian GNU/Linux system are free software;
11063 13:58:26.320713 the exact distribution terms for each program are described in the
11064 13:58:26.323960 individual files in /usr/share/doc/*/copyright.
11065 13:58:26.324050
11066 13:58:26.330573 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11067 13:58:26.333809 permitted by applicable law.
11068 13:58:27.379748 Matched prompt #10: / #
11070 13:58:27.380058 Setting prompt string to ['/ #']
11071 13:58:27.380172 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11073 13:58:27.380403 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11074 13:58:27.380506 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
11075 13:58:27.380584 Setting prompt string to ['/ #']
11076 13:58:27.380681 Forcing a shell prompt, looking for ['/ #']
11078 13:58:27.430976 / #
11079 13:58:27.431129 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11080 13:58:27.431230 Waiting using forced prompt support (timeout 00:02:30)
11081 13:58:27.435985
11082 13:58:27.436271 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11083 13:58:27.436401 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
11085 13:58:27.536834 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682960/extract-nfsrootfs-g0w8ha3y'
11086 13:58:27.541694 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682960/extract-nfsrootfs-g0w8ha3y'
11088 13:58:27.642282 / # export NFS_SERVER_IP='192.168.201.1'
11089 13:58:27.647139 export NFS_SERVER_IP='192.168.201.1'
11090 13:58:27.647431 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11091 13:58:27.647535 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11092 13:58:27.647625 end: 2 depthcharge-action (duration 00:01:44) [common]
11093 13:58:27.647717 start: 3 lava-test-retry (timeout 00:07:34) [common]
11094 13:58:27.647805 start: 3.1 lava-test-shell (timeout 00:07:34) [common]
11095 13:58:27.647881 Using namespace: common
11097 13:58:27.748240 / # #
11098 13:58:27.748408 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11099 13:58:27.753372 #
11100 13:58:27.753639 Using /lava-12682960
11102 13:58:27.853981 / # export SHELL=/bin/bash
11103 13:58:27.859023 export SHELL=/bin/bash
11105 13:58:27.959571 / # . /lava-12682960/environment
11106 13:58:27.964933 . /lava-12682960/environment
11108 13:58:28.071692 / # /lava-12682960/bin/lava-test-runner /lava-12682960/0
11109 13:58:28.071864 Test shell timeout: 10s (minimum of the action and connection timeout)
11110 13:58:28.076968 /lava-12682960/bin/lava-test-runner /lava-12682960/0
11111 13:58:28.359848 + export TESTRUN_ID=0_timesync-off
11112 13:58:28.363252 + TESTRUN_ID=0_timesync-off
11113 13:58:28.366421 + cd /lava-12682960/0/tests/0_timesync-off
11114 13:58:28.369527 ++ cat uuid
11115 13:58:28.374927 + UUID=12682960_1.6.2.3.1
11116 13:58:28.375011 + set +x
11117 13:58:28.381400 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12682960_1.6.2.3.1>
11118 13:58:28.381670 Received signal: <STARTRUN> 0_timesync-off 12682960_1.6.2.3.1
11119 13:58:28.381748 Starting test lava.0_timesync-off (12682960_1.6.2.3.1)
11120 13:58:28.381838 Skipping test definition patterns.
11121 13:58:28.384899 + systemctl stop systemd-timesyncd
11122 13:58:28.451301 + set +x
11123 13:58:28.454383 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12682960_1.6.2.3.1>
11124 13:58:28.454652 Received signal: <ENDRUN> 0_timesync-off 12682960_1.6.2.3.1
11125 13:58:28.454742 Ending use of test pattern.
11126 13:58:28.454807 Ending test lava.0_timesync-off (12682960_1.6.2.3.1), duration 0.07
11128 13:58:28.530179 + export TESTRUN_ID=1_kselftest-alsa
11129 13:58:28.533194 + TESTRUN_ID=1_kselftest-alsa
11130 13:58:28.539765 + cd /lava-12682960/0/tests/1_kselftest-alsa
11131 13:58:28.539853 ++ cat uuid
11132 13:58:28.544646 + UUID=12682960_1.6.2.3.5
11133 13:58:28.544729 + set +x
11134 13:58:28.551253 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12682960_1.6.2.3.5>
11135 13:58:28.551591 Received signal: <STARTRUN> 1_kselftest-alsa 12682960_1.6.2.3.5
11136 13:58:28.551696 Starting test lava.1_kselftest-alsa (12682960_1.6.2.3.5)
11137 13:58:28.551838 Skipping test definition patterns.
11138 13:58:28.554499 + cd ./automated/linux/kselftest/
11139 13:58:28.580919 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11140 13:58:28.625073 INFO: install_deps skipped
11141 13:58:29.134295 --2024-02-01 13:58:29-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11142 13:58:29.147469 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11143 13:58:29.281214 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11144 13:58:29.414519 HTTP request sent, awaiting response... 200 OK
11145 13:58:29.417514 Length: 2966796 (2.8M) [application/octet-stream]
11146 13:58:29.420929 Saving to: 'kselftest.tar.xz'
11147 13:58:29.421004
11148 13:58:29.421103
11149 13:58:29.681224 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11150 13:58:29.954337 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11151 13:58:30.406782 kselftest.tar.xz 7%[> ] 219.84K 409KB/s
11152 13:58:30.679352 kselftest.tar.xz 28%[====> ] 812.82K 820KB/s
11153 13:58:30.763617 kselftest.tar.xz 81%[===============> ] 2.32M 1.83MB/s
11154 13:58:30.769941 kselftest.tar.xz 100%[===================>] 2.83M 2.10MB/s in 1.3s
11155 13:58:30.770025
11156 13:58:31.028541 2024-02-01 13:58:31 (2.10 MB/s) - 'kselftest.tar.xz' saved [2966796/2966796]
11157 13:58:31.028714
11158 13:58:37.852827 skiplist:
11159 13:58:37.856422 ========================================
11160 13:58:37.859479 ========================================
11161 13:58:37.910377 alsa:mixer-test
11162 13:58:37.932112 ============== Tests to run ===============
11163 13:58:37.932243 alsa:mixer-test
11164 13:58:37.938820 ===========End Tests to run ===============
11165 13:58:37.941897 shardfile-alsa pass
11166 13:58:38.054657 <12>[ 40.175179] kselftest: Running tests in alsa
11167 13:58:38.065075 TAP version 13
11168 13:58:38.081168 1..1
11169 13:58:38.097413 # selftests: alsa: mixer-test
11170 13:58:38.602095 # TAP version 13
11171 13:58:38.602244 # 1..0
11172 13:58:38.608434 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11173 13:58:38.611604 ok 1 selftests: alsa: mixer-test
11174 13:58:39.335276 alsa_mixer-test pass
11175 13:58:39.381359 + ../../utils/send-to-lava.sh ./output/result.txt
11176 13:58:39.456877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11177 13:58:39.457214 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11179 13:58:39.511065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11180 13:58:39.511224 + set +x
11181 13:58:39.511505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11183 13:58:39.517687 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12682960_1.6.2.3.5>
11184 13:58:39.517943 Received signal: <ENDRUN> 1_kselftest-alsa 12682960_1.6.2.3.5
11185 13:58:39.518020 Ending use of test pattern.
11186 13:58:39.518083 Ending test lava.1_kselftest-alsa (12682960_1.6.2.3.5), duration 10.97
11188 13:58:39.520715 <LAVA_TEST_RUNNER EXIT>
11189 13:58:39.520967 ok: lava_test_shell seems to have completed
11190 13:58:39.521067 alsa_mixer-test: pass
shardfile-alsa: pass
11191 13:58:39.521156 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11192 13:58:39.521243 end: 3 lava-test-retry (duration 00:00:12) [common]
11193 13:58:39.521330 start: 4 finalize (timeout 00:07:22) [common]
11194 13:58:39.521419 start: 4.1 power-off (timeout 00:00:30) [common]
11195 13:58:39.521657 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11196 13:58:39.598237 >> Command sent successfully.
11197 13:58:39.601114 Returned 0 in 0 seconds
11198 13:58:39.701583 end: 4.1 power-off (duration 00:00:00) [common]
11200 13:58:39.701963 start: 4.2 read-feedback (timeout 00:07:22) [common]
11201 13:58:39.702239 Listened to connection for namespace 'common' for up to 1s
11202 13:58:40.703163 Finalising connection for namespace 'common'
11203 13:58:40.703335 Disconnecting from shell: Finalise
11204 13:58:40.703418 / #
11205 13:58:40.803783 end: 4.2 read-feedback (duration 00:00:01) [common]
11206 13:58:40.803968 end: 4 finalize (duration 00:00:01) [common]
11207 13:58:40.804087 Cleaning after the job
11208 13:58:40.804194 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/ramdisk
11209 13:58:40.807189 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/kernel
11210 13:58:40.820396 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/dtb
11211 13:58:40.820600 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/nfsrootfs
11212 13:58:40.925708 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682960/tftp-deploy-4uofzm8x/modules
11213 13:58:40.933614 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682960
11214 13:58:41.698202 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682960
11215 13:58:41.698390 Job finished correctly