Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 38
1 13:52:28.431294 lava-dispatcher, installed at version: 2023.10
2 13:52:28.431496 start: 0 validate
3 13:52:28.431627 Start time: 2024-02-01 13:52:28.431619+00:00 (UTC)
4 13:52:28.431738 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:52:28.431871 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 13:52:28.699462 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:52:28.699636 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:52:53.712441 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:52:53.713163 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:52:53.982933 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:52:53.983686 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:52:54.514665 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:52:54.515433 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:53:03.528072 validate duration: 35.10
16 13:53:03.528585 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:53:03.528800 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:53:03.528986 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:53:03.529242 Not decompressing ramdisk as can be used compressed.
20 13:53:03.529434 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 13:53:03.529580 saving as /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/ramdisk/initrd.cpio.gz
22 13:53:03.529718 total size: 4665398 (4 MB)
23 13:53:03.796875 progress 0 % (0 MB)
24 13:53:03.798449 progress 5 % (0 MB)
25 13:53:03.799766 progress 10 % (0 MB)
26 13:53:03.801034 progress 15 % (0 MB)
27 13:53:03.802540 progress 20 % (0 MB)
28 13:53:03.803907 progress 25 % (1 MB)
29 13:53:03.805183 progress 30 % (1 MB)
30 13:53:03.806417 progress 35 % (1 MB)
31 13:53:03.807711 progress 40 % (1 MB)
32 13:53:03.809212 progress 45 % (2 MB)
33 13:53:03.810507 progress 50 % (2 MB)
34 13:53:03.811868 progress 55 % (2 MB)
35 13:53:03.813102 progress 60 % (2 MB)
36 13:53:03.814509 progress 65 % (2 MB)
37 13:53:03.815785 progress 70 % (3 MB)
38 13:53:03.817199 progress 75 % (3 MB)
39 13:53:03.818434 progress 80 % (3 MB)
40 13:53:03.820027 progress 85 % (3 MB)
41 13:53:03.821328 progress 90 % (4 MB)
42 13:53:03.822691 progress 95 % (4 MB)
43 13:53:03.824609 progress 100 % (4 MB)
44 13:53:03.824830 4 MB downloaded in 0.30 s (15.08 MB/s)
45 13:53:03.824990 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:53:03.825255 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:53:03.825415 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:53:03.825519 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:53:03.825653 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:53:03.825723 saving as /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/kernel/Image
52 13:53:03.825813 total size: 51532288 (49 MB)
53 13:53:03.825889 No compression specified
54 13:53:03.827340 progress 0 % (0 MB)
55 13:53:03.841483 progress 5 % (2 MB)
56 13:53:03.855847 progress 10 % (4 MB)
57 13:53:03.870040 progress 15 % (7 MB)
58 13:53:03.883919 progress 20 % (9 MB)
59 13:53:03.897737 progress 25 % (12 MB)
60 13:53:03.911881 progress 30 % (14 MB)
61 13:53:03.926996 progress 35 % (17 MB)
62 13:53:03.941388 progress 40 % (19 MB)
63 13:53:03.955004 progress 45 % (22 MB)
64 13:53:03.968884 progress 50 % (24 MB)
65 13:53:03.983786 progress 55 % (27 MB)
66 13:53:03.998573 progress 60 % (29 MB)
67 13:53:04.014033 progress 65 % (31 MB)
68 13:53:04.028759 progress 70 % (34 MB)
69 13:53:04.043523 progress 75 % (36 MB)
70 13:53:04.059063 progress 80 % (39 MB)
71 13:53:04.073406 progress 85 % (41 MB)
72 13:53:04.088137 progress 90 % (44 MB)
73 13:53:04.102855 progress 95 % (46 MB)
74 13:53:04.116958 progress 100 % (49 MB)
75 13:53:04.117227 49 MB downloaded in 0.29 s (168.65 MB/s)
76 13:53:04.117447 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:53:04.117693 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:53:04.117784 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:53:04.117871 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:53:04.118012 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:53:04.118085 saving as /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/dtb/mt8192-asurada-spherion-r0.dtb
83 13:53:04.118155 total size: 47278 (0 MB)
84 13:53:04.118218 No compression specified
85 13:53:04.384265 progress 69 % (0 MB)
86 13:53:04.384633 progress 100 % (0 MB)
87 13:53:04.384805 0 MB downloaded in 0.27 s (0.17 MB/s)
88 13:53:04.384995 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:53:04.385318 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:53:04.385409 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:53:04.385493 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:53:04.385637 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 13:53:04.385736 saving as /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/nfsrootfs/full.rootfs.tar
95 13:53:04.385822 total size: 89451516 (85 MB)
96 13:53:04.385916 Using unxz to decompress xz
97 13:53:04.390782 progress 0 % (0 MB)
98 13:53:04.609618 progress 5 % (4 MB)
99 13:53:04.830116 progress 10 % (8 MB)
100 13:53:05.090047 progress 15 % (12 MB)
101 13:53:05.286806 progress 20 % (17 MB)
102 13:53:05.383140 progress 25 % (21 MB)
103 13:53:05.632570 progress 30 % (25 MB)
104 13:53:05.922982 progress 35 % (29 MB)
105 13:53:06.202950 progress 40 % (34 MB)
106 13:53:06.484100 progress 45 % (38 MB)
107 13:53:06.744932 progress 50 % (42 MB)
108 13:53:07.024271 progress 55 % (46 MB)
109 13:53:07.290352 progress 60 % (51 MB)
110 13:53:07.575714 progress 65 % (55 MB)
111 13:53:07.881671 progress 70 % (59 MB)
112 13:53:08.189539 progress 75 % (64 MB)
113 13:53:08.498353 progress 80 % (68 MB)
114 13:53:08.772952 progress 85 % (72 MB)
115 13:53:09.017911 progress 90 % (76 MB)
116 13:53:09.289782 progress 95 % (81 MB)
117 13:53:09.566022 progress 100 % (85 MB)
118 13:53:09.572515 85 MB downloaded in 5.19 s (16.45 MB/s)
119 13:53:09.572855 end: 1.4.1 http-download (duration 00:00:05) [common]
121 13:53:09.573265 end: 1.4 download-retry (duration 00:00:05) [common]
122 13:53:09.573387 start: 1.5 download-retry (timeout 00:09:54) [common]
123 13:53:09.573507 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 13:53:09.573705 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:53:09.573804 saving as /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/modules/modules.tar
126 13:53:09.573895 total size: 8623988 (8 MB)
127 13:53:09.573989 Using unxz to decompress xz
128 13:53:09.844328 progress 0 % (0 MB)
129 13:53:09.867041 progress 5 % (0 MB)
130 13:53:09.890862 progress 10 % (0 MB)
131 13:53:09.915316 progress 15 % (1 MB)
132 13:53:09.939672 progress 20 % (1 MB)
133 13:53:09.964577 progress 25 % (2 MB)
134 13:53:09.991538 progress 30 % (2 MB)
135 13:53:10.019113 progress 35 % (2 MB)
136 13:53:10.043879 progress 40 % (3 MB)
137 13:53:10.069171 progress 45 % (3 MB)
138 13:53:10.095258 progress 50 % (4 MB)
139 13:53:10.120314 progress 55 % (4 MB)
140 13:53:10.145866 progress 60 % (4 MB)
141 13:53:10.174709 progress 65 % (5 MB)
142 13:53:10.201210 progress 70 % (5 MB)
143 13:53:10.226127 progress 75 % (6 MB)
144 13:53:10.254089 progress 80 % (6 MB)
145 13:53:10.280661 progress 85 % (7 MB)
146 13:53:10.306540 progress 90 % (7 MB)
147 13:53:10.338987 progress 95 % (7 MB)
148 13:53:10.368877 progress 100 % (8 MB)
149 13:53:10.374160 8 MB downloaded in 0.80 s (10.28 MB/s)
150 13:53:10.374530 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:53:10.374926 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:53:10.375059 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 13:53:10.375193 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 13:53:12.260069 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12682921/extract-nfsrootfs-9lggu5gw
156 13:53:12.260266 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:53:12.260372 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 13:53:12.260687 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf
159 13:53:12.260826 makedir: /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin
160 13:53:12.260931 makedir: /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/tests
161 13:53:12.261031 makedir: /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/results
162 13:53:12.261136 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-add-keys
163 13:53:12.261281 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-add-sources
164 13:53:12.261414 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-background-process-start
165 13:53:12.261542 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-background-process-stop
166 13:53:12.261669 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-common-functions
167 13:53:12.261798 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-echo-ipv4
168 13:53:12.261926 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-install-packages
169 13:53:12.262052 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-installed-packages
170 13:53:12.262177 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-os-build
171 13:53:12.262301 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-probe-channel
172 13:53:12.262426 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-probe-ip
173 13:53:12.262552 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-target-ip
174 13:53:12.262676 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-target-mac
175 13:53:12.262802 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-target-storage
176 13:53:12.262928 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-test-case
177 13:53:12.263056 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-test-event
178 13:53:12.263182 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-test-feedback
179 13:53:12.263307 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-test-raise
180 13:53:12.263472 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-test-reference
181 13:53:12.263597 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-test-runner
182 13:53:12.263723 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-test-set
183 13:53:12.263848 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-test-shell
184 13:53:12.263975 Updating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-install-packages (oe)
185 13:53:12.264139 Updating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/bin/lava-installed-packages (oe)
186 13:53:12.264264 Creating /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/environment
187 13:53:12.264361 LAVA metadata
188 13:53:12.264434 - LAVA_JOB_ID=12682921
189 13:53:12.264497 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:53:12.264603 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 13:53:12.264669 skipped lava-vland-overlay
192 13:53:12.264744 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:53:12.264822 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 13:53:12.264882 skipped lava-multinode-overlay
195 13:53:12.264953 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:53:12.265029 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 13:53:12.265103 Loading test definitions
198 13:53:12.265193 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 13:53:12.265262 Using /lava-12682921 at stage 0
200 13:53:12.265571 uuid=12682921_1.6.2.3.1 testdef=None
201 13:53:12.265661 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:53:12.265745 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 13:53:12.266239 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:53:12.266460 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 13:53:12.267162 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:53:12.267438 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 13:53:12.268171 runner path: /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/0/tests/0_lc-compliance test_uuid 12682921_1.6.2.3.1
210 13:53:12.268328 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:53:12.268533 Creating lava-test-runner.conf files
213 13:53:12.268596 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682921/lava-overlay-zlwmqbqf/lava-12682921/0 for stage 0
214 13:53:12.268685 - 0_lc-compliance
215 13:53:12.268783 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 13:53:12.268868 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 13:53:12.275000 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 13:53:12.275127 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 13:53:12.275216 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 13:53:12.275303 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 13:53:12.275428 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 13:53:12.398447 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 13:53:12.398821 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 13:53:12.398945 extracting modules file /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682921/extract-nfsrootfs-9lggu5gw
225 13:53:12.623713 extracting modules file /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682921/extract-overlay-ramdisk-knv35_9d/ramdisk
226 13:53:12.869172 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 13:53:12.869362 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 13:53:12.869483 [common] Applying overlay to NFS
229 13:53:12.869568 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682921/compress-overlay-ayl6rc77/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682921/extract-nfsrootfs-9lggu5gw
230 13:53:12.876475 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 13:53:12.876638 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 13:53:12.876751 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 13:53:12.876860 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 13:53:12.876953 Building ramdisk /var/lib/lava/dispatcher/tmp/12682921/extract-overlay-ramdisk-knv35_9d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682921/extract-overlay-ramdisk-knv35_9d/ramdisk
235 13:53:13.213947 >> 119414 blocks
236 13:53:15.172042 rename /var/lib/lava/dispatcher/tmp/12682921/extract-overlay-ramdisk-knv35_9d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/ramdisk/ramdisk.cpio.gz
237 13:53:15.172533 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 13:53:15.172704 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 13:53:15.172858 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 13:53:15.173017 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/kernel/Image'
241 13:53:28.550987 Returned 0 in 13 seconds
242 13:53:28.651544 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/kernel/image.itb
243 13:53:29.029024 output: FIT description: Kernel Image image with one or more FDT blobs
244 13:53:29.029568 output: Created: Thu Feb 1 13:53:28 2024
245 13:53:29.029716 output: Image 0 (kernel-1)
246 13:53:29.029784 output: Description:
247 13:53:29.029849 output: Created: Thu Feb 1 13:53:28 2024
248 13:53:29.029911 output: Type: Kernel Image
249 13:53:29.029970 output: Compression: lzma compressed
250 13:53:29.030026 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
251 13:53:29.030087 output: Architecture: AArch64
252 13:53:29.030146 output: OS: Linux
253 13:53:29.030206 output: Load Address: 0x00000000
254 13:53:29.030266 output: Entry Point: 0x00000000
255 13:53:29.030322 output: Hash algo: crc32
256 13:53:29.030379 output: Hash value: 5aa40db2
257 13:53:29.030439 output: Image 1 (fdt-1)
258 13:53:29.030492 output: Description: mt8192-asurada-spherion-r0
259 13:53:29.030546 output: Created: Thu Feb 1 13:53:28 2024
260 13:53:29.030600 output: Type: Flat Device Tree
261 13:53:29.030654 output: Compression: uncompressed
262 13:53:29.030708 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 13:53:29.030763 output: Architecture: AArch64
264 13:53:29.030817 output: Hash algo: crc32
265 13:53:29.030870 output: Hash value: cc4352de
266 13:53:29.030924 output: Image 2 (ramdisk-1)
267 13:53:29.030978 output: Description: unavailable
268 13:53:29.031031 output: Created: Thu Feb 1 13:53:28 2024
269 13:53:29.031085 output: Type: RAMDisk Image
270 13:53:29.031138 output: Compression: Unknown Compression
271 13:53:29.031192 output: Data Size: 17793086 Bytes = 17376.06 KiB = 16.97 MiB
272 13:53:29.031271 output: Architecture: AArch64
273 13:53:29.031329 output: OS: Linux
274 13:53:29.031410 output: Load Address: unavailable
275 13:53:29.031465 output: Entry Point: unavailable
276 13:53:29.031519 output: Hash algo: crc32
277 13:53:29.031573 output: Hash value: ab4c3bb3
278 13:53:29.031626 output: Default Configuration: 'conf-1'
279 13:53:29.031680 output: Configuration 0 (conf-1)
280 13:53:29.031733 output: Description: mt8192-asurada-spherion-r0
281 13:53:29.031786 output: Kernel: kernel-1
282 13:53:29.031839 output: Init Ramdisk: ramdisk-1
283 13:53:29.031892 output: FDT: fdt-1
284 13:53:29.031944 output: Loadables: kernel-1
285 13:53:29.031997 output:
286 13:53:29.032204 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 13:53:29.032308 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 13:53:29.032463 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 13:53:29.032576 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
290 13:53:29.032669 No LXC device requested
291 13:53:29.032783 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 13:53:29.032881 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
293 13:53:29.032965 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 13:53:29.033035 Checking files for TFTP limit of 4294967296 bytes.
295 13:53:29.033538 end: 1 tftp-deploy (duration 00:00:26) [common]
296 13:53:29.033640 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 13:53:29.033738 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 13:53:29.033871 substitutions:
299 13:53:29.033938 - {DTB}: 12682921/tftp-deploy-7hfvud89/dtb/mt8192-asurada-spherion-r0.dtb
300 13:53:29.034003 - {INITRD}: 12682921/tftp-deploy-7hfvud89/ramdisk/ramdisk.cpio.gz
301 13:53:29.034062 - {KERNEL}: 12682921/tftp-deploy-7hfvud89/kernel/Image
302 13:53:29.034120 - {LAVA_MAC}: None
303 13:53:29.034177 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12682921/extract-nfsrootfs-9lggu5gw
304 13:53:29.034233 - {NFS_SERVER_IP}: 192.168.201.1
305 13:53:29.034288 - {PRESEED_CONFIG}: None
306 13:53:29.034343 - {PRESEED_LOCAL}: None
307 13:53:29.034398 - {RAMDISK}: 12682921/tftp-deploy-7hfvud89/ramdisk/ramdisk.cpio.gz
308 13:53:29.034452 - {ROOT_PART}: None
309 13:53:29.034505 - {ROOT}: None
310 13:53:29.034559 - {SERVER_IP}: 192.168.201.1
311 13:53:29.034612 - {TEE}: None
312 13:53:29.034665 Parsed boot commands:
313 13:53:29.034719 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 13:53:29.034908 Parsed boot commands: tftpboot 192.168.201.1 12682921/tftp-deploy-7hfvud89/kernel/image.itb 12682921/tftp-deploy-7hfvud89/kernel/cmdline
315 13:53:29.034995 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 13:53:29.035079 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 13:53:29.035172 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 13:53:29.035289 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 13:53:29.035428 Not connected, no need to disconnect.
320 13:53:29.035586 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 13:53:29.035704 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 13:53:29.035803 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
323 13:53:29.040125 Setting prompt string to ['lava-test: # ']
324 13:53:29.040528 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 13:53:29.040654 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 13:53:29.040772 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 13:53:29.040938 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 13:53:29.041162 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
329 13:53:34.174127 >> Command sent successfully.
330 13:53:34.176523 Returned 0 in 5 seconds
331 13:53:34.276893 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 13:53:34.277339 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 13:53:34.277475 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 13:53:34.277593 Setting prompt string to 'Starting depthcharge on Spherion...'
336 13:53:34.277693 Changing prompt to 'Starting depthcharge on Spherion...'
337 13:53:34.277794 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 13:53:34.278165 [Enter `^Ec?' for help]
339 13:53:34.452443
340 13:53:34.452606
341 13:53:34.452678 F0: 102B 0000
342 13:53:34.452748
343 13:53:34.452807 F3: 1001 0000 [0200]
344 13:53:34.452867
345 13:53:34.456057 F3: 1001 0000
346 13:53:34.456147
347 13:53:34.456213 F7: 102D 0000
348 13:53:34.456275
349 13:53:34.459354 F1: 0000 0000
350 13:53:34.459476
351 13:53:34.459545 V0: 0000 0000 [0001]
352 13:53:34.459609
353 13:53:34.462076 00: 0007 8000
354 13:53:34.462168
355 13:53:34.462234 01: 0000 0000
356 13:53:34.462299
357 13:53:34.466109 BP: 0C00 0209 [0000]
358 13:53:34.466193
359 13:53:34.466259 G0: 1182 0000
360 13:53:34.466321
361 13:53:34.466381 EC: 0000 0021 [4000]
362 13:53:34.469343
363 13:53:34.469425 S7: 0000 0000 [0000]
364 13:53:34.469492
365 13:53:34.469585 CC: 0000 0000 [0001]
366 13:53:34.472820
367 13:53:34.472904 T0: 0000 0040 [010F]
368 13:53:34.472971
369 13:53:34.473032 Jump to BL
370 13:53:34.473090
371 13:53:34.499117
372 13:53:34.499274
373 13:53:34.499344
374 13:53:34.506313 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 13:53:34.510237 ARM64: Exception handlers installed.
376 13:53:34.513524 ARM64: Testing exception
377 13:53:34.516866 ARM64: Done test exception
378 13:53:34.523524 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 13:53:34.533943 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 13:53:34.540164 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 13:53:34.551069 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 13:53:34.556984 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 13:53:34.563835 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 13:53:34.577192 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 13:53:34.582441 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 13:53:34.601752 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 13:53:34.604875 WDT: Last reset was cold boot
388 13:53:34.608400 SPI1(PAD0) initialized at 2873684 Hz
389 13:53:34.611761 SPI5(PAD0) initialized at 992727 Hz
390 13:53:34.614646 VBOOT: Loading verstage.
391 13:53:34.621654 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 13:53:34.625045 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 13:53:34.628401 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 13:53:34.631541 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 13:53:34.639562 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 13:53:34.646569 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 13:53:34.656747 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 13:53:34.656896
399 13:53:34.656965
400 13:53:34.666484 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 13:53:34.670305 ARM64: Exception handlers installed.
402 13:53:34.673169 ARM64: Testing exception
403 13:53:34.676944 ARM64: Done test exception
404 13:53:34.681281 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 13:53:34.684862 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 13:53:34.697754 Probing TPM: . done!
407 13:53:34.697891 TPM ready after 0 ms
408 13:53:34.705504 Connected to device vid:did:rid of 1ae0:0028:00
409 13:53:34.712185 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
410 13:53:34.769290 Initialized TPM device CR50 revision 0
411 13:53:34.780632 tlcl_send_startup: Startup return code is 0
412 13:53:34.780779 TPM: setup succeeded
413 13:53:34.792894 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 13:53:34.801607 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 13:53:34.813062 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 13:53:34.822835 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 13:53:34.826719 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 13:53:34.831813 in-header: 03 07 00 00 08 00 00 00
419 13:53:34.835405 in-data: aa e4 47 04 13 02 00 00
420 13:53:34.839304 Chrome EC: UHEPI supported
421 13:53:34.846194 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 13:53:34.849936 in-header: 03 95 00 00 08 00 00 00
423 13:53:34.850039 in-data: 18 20 20 08 00 00 00 00
424 13:53:34.853570 Phase 1
425 13:53:34.857438 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 13:53:34.860998 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 13:53:34.868607 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 13:53:34.872341 Recovery requested (1009000e)
429 13:53:34.879933 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 13:53:34.885618 tlcl_extend: response is 0
431 13:53:34.894599 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 13:53:34.900583 tlcl_extend: response is 0
433 13:53:34.907034 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 13:53:34.927284 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 13:53:34.933959 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 13:53:34.934106
437 13:53:34.934192
438 13:53:34.943946 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 13:53:34.947261 ARM64: Exception handlers installed.
440 13:53:34.950406 ARM64: Testing exception
441 13:53:34.950498 ARM64: Done test exception
442 13:53:34.972706 pmic_efuse_setting: Set efuses in 11 msecs
443 13:53:34.976666 pmwrap_interface_init: Select PMIF_VLD_RDY
444 13:53:34.982706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 13:53:34.985678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 13:53:34.992937 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 13:53:34.996408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 13:53:35.000331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 13:53:35.007224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 13:53:35.011108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 13:53:35.014944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 13:53:35.021636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 13:53:35.025180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 13:53:35.029127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 13:53:35.032814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 13:53:35.040184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 13:53:35.043793 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 13:53:35.050843 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 13:53:35.054632 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 13:53:35.062416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 13:53:35.069551 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 13:53:35.073371 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 13:53:35.080437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 13:53:35.083989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 13:53:35.091114 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 13:53:35.095042 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 13:53:35.102023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 13:53:35.105970 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 13:53:35.113352 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 13:53:35.116186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 13:53:35.123789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 13:53:35.127227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 13:53:35.130827 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 13:53:35.138280 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 13:53:35.141451 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 13:53:35.145559 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 13:53:35.152519 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 13:53:35.155611 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 13:53:35.163273 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 13:53:35.166983 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 13:53:35.171497 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 13:53:35.174943 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 13:53:35.181831 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 13:53:35.185993 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 13:53:35.188993 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 13:53:35.192499 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 13:53:35.200530 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 13:53:35.203321 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 13:53:35.207166 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 13:53:35.210987 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 13:53:35.214447 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 13:53:35.218621 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 13:53:35.222119 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 13:53:35.229142 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 13:53:35.236730 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 13:53:35.243663 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 13:53:35.247220 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 13:53:35.258030 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 13:53:35.265313 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 13:53:35.268999 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 13:53:35.272543 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 13:53:35.280422 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 13:53:35.287545 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0xc
504 13:53:35.290570 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 13:53:35.297746 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
506 13:53:35.301317 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 13:53:35.310516 [RTC]rtc_get_frequency_meter,154: input=15, output=853
508 13:53:35.320022 [RTC]rtc_get_frequency_meter,154: input=7, output=725
509 13:53:35.329220 [RTC]rtc_get_frequency_meter,154: input=11, output=789
510 13:53:35.338250 [RTC]rtc_get_frequency_meter,154: input=13, output=822
511 13:53:35.348417 [RTC]rtc_get_frequency_meter,154: input=12, output=805
512 13:53:35.357210 [RTC]rtc_get_frequency_meter,154: input=11, output=789
513 13:53:35.367610 [RTC]rtc_get_frequency_meter,154: input=12, output=804
514 13:53:35.371498 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
515 13:53:35.375240 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
516 13:53:35.378695 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 13:53:35.385715 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 13:53:35.389779 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 13:53:35.393213 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 13:53:35.396914 ADC[4]: Raw value=904433 ID=7
521 13:53:35.400657 ADC[3]: Raw value=213546 ID=1
522 13:53:35.400771 RAM Code: 0x71
523 13:53:35.404302 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 13:53:35.411607 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 13:53:35.419023 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 13:53:35.426281 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 13:53:35.430131 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 13:53:35.434227 in-header: 03 07 00 00 08 00 00 00
529 13:53:35.434334 in-data: aa e4 47 04 13 02 00 00
530 13:53:35.437859 Chrome EC: UHEPI supported
531 13:53:35.444716 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 13:53:35.448319 in-header: 03 95 00 00 08 00 00 00
533 13:53:35.452143 in-data: 18 20 20 08 00 00 00 00
534 13:53:35.455333 MRC: failed to locate region type 0.
535 13:53:35.458804 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 13:53:35.462646 DRAM-K: Running full calibration
537 13:53:35.470440 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 13:53:35.470567 header.status = 0x0
539 13:53:35.473649 header.version = 0x6 (expected: 0x6)
540 13:53:35.477661 header.size = 0xd00 (expected: 0xd00)
541 13:53:35.481432 header.flags = 0x0
542 13:53:35.484653 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 13:53:35.504351 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 13:53:35.511630 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 13:53:35.515796 dram_init: ddr_geometry: 2
546 13:53:35.515915 [EMI] MDL number = 2
547 13:53:35.519771 [EMI] Get MDL freq = 0
548 13:53:35.519873 dram_init: ddr_type: 0
549 13:53:35.523576 is_discrete_lpddr4: 1
550 13:53:35.523673 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 13:53:35.527002
552 13:53:35.527093
553 13:53:35.527161 [Bian_co] ETT version 0.0.0.1
554 13:53:35.531206 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 13:53:35.531306
556 13:53:35.538795 dramc_set_vcore_voltage set vcore to 650000
557 13:53:35.538913 Read voltage for 800, 4
558 13:53:35.538984 Vio18 = 0
559 13:53:35.542100 Vcore = 650000
560 13:53:35.542192 Vdram = 0
561 13:53:35.542282 Vddq = 0
562 13:53:35.545907 Vmddr = 0
563 13:53:35.546004 dram_init: config_dvfs: 1
564 13:53:35.551872 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 13:53:35.555195 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 13:53:35.559451 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
567 13:53:35.566434 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
568 13:53:35.569112 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
569 13:53:35.572653 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
570 13:53:35.572767 MEM_TYPE=3, freq_sel=18
571 13:53:35.576191 sv_algorithm_assistance_LP4_1600
572 13:53:35.579763 ============ PULL DRAM RESETB DOWN ============
573 13:53:35.586642 ========== PULL DRAM RESETB DOWN end =========
574 13:53:35.589905 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 13:53:35.592950 ===================================
576 13:53:35.596338 LPDDR4 DRAM CONFIGURATION
577 13:53:35.600107 ===================================
578 13:53:35.600211 EX_ROW_EN[0] = 0x0
579 13:53:35.603111 EX_ROW_EN[1] = 0x0
580 13:53:35.603204 LP4Y_EN = 0x0
581 13:53:35.606356 WORK_FSP = 0x0
582 13:53:35.606448 WL = 0x2
583 13:53:35.609789 RL = 0x2
584 13:53:35.609884 BL = 0x2
585 13:53:35.613157 RPST = 0x0
586 13:53:35.613249 RD_PRE = 0x0
587 13:53:35.616347 WR_PRE = 0x1
588 13:53:35.620098 WR_PST = 0x0
589 13:53:35.620197 DBI_WR = 0x0
590 13:53:35.623955 DBI_RD = 0x0
591 13:53:35.624046 OTF = 0x1
592 13:53:35.626843 ===================================
593 13:53:35.629917 ===================================
594 13:53:35.630013 ANA top config
595 13:53:35.633267 ===================================
596 13:53:35.636587 DLL_ASYNC_EN = 0
597 13:53:35.639751 ALL_SLAVE_EN = 1
598 13:53:35.643250 NEW_RANK_MODE = 1
599 13:53:35.646614 DLL_IDLE_MODE = 1
600 13:53:35.646705 LP45_APHY_COMB_EN = 1
601 13:53:35.649539 TX_ODT_DIS = 1
602 13:53:35.653366 NEW_8X_MODE = 1
603 13:53:35.656234 ===================================
604 13:53:35.659649 ===================================
605 13:53:35.662779 data_rate = 1600
606 13:53:35.666190 CKR = 1
607 13:53:35.666281 DQ_P2S_RATIO = 8
608 13:53:35.669847 ===================================
609 13:53:35.673328 CA_P2S_RATIO = 8
610 13:53:35.676400 DQ_CA_OPEN = 0
611 13:53:35.680526 DQ_SEMI_OPEN = 0
612 13:53:35.683342 CA_SEMI_OPEN = 0
613 13:53:35.683458 CA_FULL_RATE = 0
614 13:53:35.687034 DQ_CKDIV4_EN = 1
615 13:53:35.690212 CA_CKDIV4_EN = 1
616 13:53:35.693649 CA_PREDIV_EN = 0
617 13:53:35.696980 PH8_DLY = 0
618 13:53:35.700470 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 13:53:35.700567 DQ_AAMCK_DIV = 4
620 13:53:35.703306 CA_AAMCK_DIV = 4
621 13:53:35.706746 CA_ADMCK_DIV = 4
622 13:53:35.709962 DQ_TRACK_CA_EN = 0
623 13:53:35.713777 CA_PICK = 800
624 13:53:35.717186 CA_MCKIO = 800
625 13:53:35.717285 MCKIO_SEMI = 0
626 13:53:35.720637 PLL_FREQ = 3068
627 13:53:35.724490 DQ_UI_PI_RATIO = 32
628 13:53:35.727732 CA_UI_PI_RATIO = 0
629 13:53:35.731657 ===================================
630 13:53:35.735630 ===================================
631 13:53:35.735737 memory_type:LPDDR4
632 13:53:35.739001 GP_NUM : 10
633 13:53:35.739093 SRAM_EN : 1
634 13:53:35.742237 MD32_EN : 0
635 13:53:35.746332 ===================================
636 13:53:35.746432 [ANA_INIT] >>>>>>>>>>>>>>
637 13:53:35.749662 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 13:53:35.753569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 13:53:35.756886 ===================================
640 13:53:35.760166 data_rate = 1600,PCW = 0X7600
641 13:53:35.764202 ===================================
642 13:53:35.766940 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 13:53:35.773576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 13:53:35.776909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 13:53:35.784021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 13:53:35.786952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 13:53:35.790810 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 13:53:35.790911 [ANA_INIT] flow start
649 13:53:35.793599 [ANA_INIT] PLL >>>>>>>>
650 13:53:35.797423 [ANA_INIT] PLL <<<<<<<<
651 13:53:35.797512 [ANA_INIT] MIDPI >>>>>>>>
652 13:53:35.800371 [ANA_INIT] MIDPI <<<<<<<<
653 13:53:35.803843 [ANA_INIT] DLL >>>>>>>>
654 13:53:35.803931 [ANA_INIT] flow end
655 13:53:35.811179 ============ LP4 DIFF to SE enter ============
656 13:53:35.814158 ============ LP4 DIFF to SE exit ============
657 13:53:35.814258 [ANA_INIT] <<<<<<<<<<<<<
658 13:53:35.816910 [Flow] Enable top DCM control >>>>>
659 13:53:35.820114 [Flow] Enable top DCM control <<<<<
660 13:53:35.823641 Enable DLL master slave shuffle
661 13:53:35.830281 ==============================================================
662 13:53:35.833786 Gating Mode config
663 13:53:35.836887 ==============================================================
664 13:53:35.839933 Config description:
665 13:53:35.850340 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 13:53:35.856624 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 13:53:35.860411 SELPH_MODE 0: By rank 1: By Phase
668 13:53:35.866987 ==============================================================
669 13:53:35.870180 GAT_TRACK_EN = 1
670 13:53:35.873187 RX_GATING_MODE = 2
671 13:53:35.876591 RX_GATING_TRACK_MODE = 2
672 13:53:35.876687 SELPH_MODE = 1
673 13:53:35.879853 PICG_EARLY_EN = 1
674 13:53:35.883349 VALID_LAT_VALUE = 1
675 13:53:35.889904 ==============================================================
676 13:53:35.892999 Enter into Gating configuration >>>>
677 13:53:35.896465 Exit from Gating configuration <<<<
678 13:53:35.900300 Enter into DVFS_PRE_config >>>>>
679 13:53:35.909527 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 13:53:35.913466 Exit from DVFS_PRE_config <<<<<
681 13:53:35.916801 Enter into PICG configuration >>>>
682 13:53:35.919597 Exit from PICG configuration <<<<
683 13:53:35.923341 [RX_INPUT] configuration >>>>>
684 13:53:35.926564 [RX_INPUT] configuration <<<<<
685 13:53:35.929542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 13:53:35.936620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 13:53:35.943410 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 13:53:35.949833 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 13:53:35.956346 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 13:53:35.959751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 13:53:35.966073 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 13:53:35.969523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 13:53:35.973251 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 13:53:35.976167 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 13:53:35.979948 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 13:53:35.986041 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 13:53:35.989978 ===================================
698 13:53:35.993132 LPDDR4 DRAM CONFIGURATION
699 13:53:35.995880 ===================================
700 13:53:35.995968 EX_ROW_EN[0] = 0x0
701 13:53:35.999312 EX_ROW_EN[1] = 0x0
702 13:53:35.999436 LP4Y_EN = 0x0
703 13:53:36.002625 WORK_FSP = 0x0
704 13:53:36.002711 WL = 0x2
705 13:53:36.006094 RL = 0x2
706 13:53:36.006180 BL = 0x2
707 13:53:36.009410 RPST = 0x0
708 13:53:36.009524 RD_PRE = 0x0
709 13:53:36.012846 WR_PRE = 0x1
710 13:53:36.012932 WR_PST = 0x0
711 13:53:36.016071 DBI_WR = 0x0
712 13:53:36.016162 DBI_RD = 0x0
713 13:53:36.019157 OTF = 0x1
714 13:53:36.023077 ===================================
715 13:53:36.026316 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 13:53:36.029656 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 13:53:36.035975 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 13:53:36.039296 ===================================
719 13:53:36.039406 LPDDR4 DRAM CONFIGURATION
720 13:53:36.042649 ===================================
721 13:53:36.045997 EX_ROW_EN[0] = 0x10
722 13:53:36.049463 EX_ROW_EN[1] = 0x0
723 13:53:36.049561 LP4Y_EN = 0x0
724 13:53:36.052880 WORK_FSP = 0x0
725 13:53:36.052966 WL = 0x2
726 13:53:36.055888 RL = 0x2
727 13:53:36.055974 BL = 0x2
728 13:53:36.059339 RPST = 0x0
729 13:53:36.059448 RD_PRE = 0x0
730 13:53:36.062724 WR_PRE = 0x1
731 13:53:36.062811 WR_PST = 0x0
732 13:53:36.066029 DBI_WR = 0x0
733 13:53:36.066115 DBI_RD = 0x0
734 13:53:36.069133 OTF = 0x1
735 13:53:36.072554 ===================================
736 13:53:36.079709 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 13:53:36.083240 nWR fixed to 40
738 13:53:36.083339 [ModeRegInit_LP4] CH0 RK0
739 13:53:36.086039 [ModeRegInit_LP4] CH0 RK1
740 13:53:36.089188 [ModeRegInit_LP4] CH1 RK0
741 13:53:36.092761 [ModeRegInit_LP4] CH1 RK1
742 13:53:36.092854 match AC timing 13
743 13:53:36.099566 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 13:53:36.102893 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 13:53:36.105913 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 13:53:36.112420 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 13:53:36.116251 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 13:53:36.116361 [EMI DOE] emi_dcm 0
749 13:53:36.122661 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 13:53:36.122771 ==
751 13:53:36.125753 Dram Type= 6, Freq= 0, CH_0, rank 0
752 13:53:36.129431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 13:53:36.129529 ==
754 13:53:36.135696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 13:53:36.139160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 13:53:36.149751 [CA 0] Center 37 (7~68) winsize 62
757 13:53:36.152896 [CA 1] Center 37 (6~68) winsize 63
758 13:53:36.156340 [CA 2] Center 34 (4~65) winsize 62
759 13:53:36.159578 [CA 3] Center 35 (4~66) winsize 63
760 13:53:36.163022 [CA 4] Center 33 (3~64) winsize 62
761 13:53:36.165945 [CA 5] Center 33 (3~64) winsize 62
762 13:53:36.166037
763 13:53:36.169248 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 13:53:36.169338
765 13:53:36.172517 [CATrainingPosCal] consider 1 rank data
766 13:53:36.176190 u2DelayCellTimex100 = 270/100 ps
767 13:53:36.179501 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
768 13:53:36.185599 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
769 13:53:36.189344 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 13:53:36.192651 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
771 13:53:36.196121 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 13:53:36.198978 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 13:53:36.199069
774 13:53:36.202412 CA PerBit enable=1, Macro0, CA PI delay=33
775 13:53:36.202503
776 13:53:36.206161 [CBTSetCACLKResult] CA Dly = 33
777 13:53:36.208963 CS Dly: 5 (0~36)
778 13:53:36.209053 ==
779 13:53:36.212354 Dram Type= 6, Freq= 0, CH_0, rank 1
780 13:53:36.215746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 13:53:36.215855 ==
782 13:53:36.222320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 13:53:36.225999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 13:53:36.235993 [CA 0] Center 38 (7~69) winsize 63
785 13:53:36.239213 [CA 1] Center 37 (7~68) winsize 62
786 13:53:36.242261 [CA 2] Center 35 (4~66) winsize 63
787 13:53:36.245673 [CA 3] Center 35 (4~66) winsize 63
788 13:53:36.249484 [CA 4] Center 34 (3~65) winsize 63
789 13:53:36.252171 [CA 5] Center 33 (3~64) winsize 62
790 13:53:36.252284
791 13:53:36.255815 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 13:53:36.255908
793 13:53:36.258959 [CATrainingPosCal] consider 2 rank data
794 13:53:36.262471 u2DelayCellTimex100 = 270/100 ps
795 13:53:36.266177 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 13:53:36.272454 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 13:53:36.275615 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 13:53:36.279240 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
799 13:53:36.282106 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 13:53:36.285706 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 13:53:36.285804
802 13:53:36.289308 CA PerBit enable=1, Macro0, CA PI delay=33
803 13:53:36.289402
804 13:53:36.292165 [CBTSetCACLKResult] CA Dly = 33
805 13:53:36.292255 CS Dly: 6 (0~38)
806 13:53:36.295564
807 13:53:36.298888 ----->DramcWriteLeveling(PI) begin...
808 13:53:36.298981 ==
809 13:53:36.302490 Dram Type= 6, Freq= 0, CH_0, rank 0
810 13:53:36.305933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 13:53:36.306029 ==
812 13:53:36.309950 Write leveling (Byte 0): 29 => 29
813 13:53:36.310044 Write leveling (Byte 1): 27 => 27
814 13:53:36.314045 DramcWriteLeveling(PI) end<-----
815 13:53:36.314140
816 13:53:36.314208 ==
817 13:53:36.317794 Dram Type= 6, Freq= 0, CH_0, rank 0
818 13:53:36.320716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 13:53:36.324104 ==
820 13:53:36.324197 [Gating] SW mode calibration
821 13:53:36.330915 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 13:53:36.338186 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 13:53:36.341101 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 13:53:36.344353 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 13:53:36.351054 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 13:53:36.354493 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
827 13:53:36.358201 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:53:36.365119 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 13:53:36.367701 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 13:53:36.371131 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 13:53:36.377792 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 13:53:36.381027 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 13:53:36.384355 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 13:53:36.390950 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 13:53:36.394815 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 13:53:36.397917 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 13:53:36.405036 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 13:53:36.407441 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 13:53:36.411110 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 13:53:36.418165 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 13:53:36.420684 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
842 13:53:36.424302 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 13:53:36.430695 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 13:53:36.434612 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 13:53:36.437399 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 13:53:36.444022 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 13:53:36.447593 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 13:53:36.450849 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
849 13:53:36.457723 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
850 13:53:36.460603 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
851 13:53:36.464450 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 13:53:36.470489 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 13:53:36.473602 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 13:53:36.477445 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 13:53:36.484105 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 13:53:36.486943 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
857 13:53:36.490844 0 10 8 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
858 13:53:36.497255 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
859 13:53:36.500338 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:53:36.503528 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:53:36.510280 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:53:36.513659 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:53:36.516737 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:53:36.520468 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
865 13:53:36.527094 0 11 8 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
866 13:53:36.530475 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
867 13:53:36.534291 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 13:53:36.539878 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 13:53:36.543753 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 13:53:36.546953 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 13:53:36.553656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 13:53:36.557212 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 13:53:36.560173 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 13:53:36.567059 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 13:53:36.570298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 13:53:36.573789 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 13:53:36.580181 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 13:53:36.583417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 13:53:36.586445 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 13:53:36.593223 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 13:53:36.596458 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 13:53:36.599679 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 13:53:36.606976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 13:53:36.609923 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 13:53:36.613065 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 13:53:36.619920 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 13:53:36.623125 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 13:53:36.626488 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 13:53:36.632850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
890 13:53:36.636222 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 13:53:36.639528 Total UI for P1: 0, mck2ui 16
892 13:53:36.642927 best dqsien dly found for B0: ( 0, 14, 8)
893 13:53:36.646761 Total UI for P1: 0, mck2ui 16
894 13:53:36.649669 best dqsien dly found for B1: ( 0, 14, 10)
895 13:53:36.653036 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
896 13:53:36.656117 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 13:53:36.656210
898 13:53:36.659440 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 13:53:36.662771 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 13:53:36.665867 [Gating] SW calibration Done
901 13:53:36.665959 ==
902 13:53:36.669400 Dram Type= 6, Freq= 0, CH_0, rank 0
903 13:53:36.672907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 13:53:36.676666 ==
905 13:53:36.676762 RX Vref Scan: 0
906 13:53:36.676830
907 13:53:36.679906 RX Vref 0 -> 0, step: 1
908 13:53:36.679994
909 13:53:36.680062 RX Delay -130 -> 252, step: 16
910 13:53:36.686972 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 13:53:36.690311 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 13:53:36.693957 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 13:53:36.696811 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 13:53:36.700457 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
915 13:53:36.706503 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
916 13:53:36.710093 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 13:53:36.713252 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
918 13:53:36.716566 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
919 13:53:36.720262 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
920 13:53:36.726496 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 13:53:36.729626 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 13:53:36.732998 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
923 13:53:36.736385 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
924 13:53:36.739582 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 13:53:36.746332 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
926 13:53:36.746442 ==
927 13:53:36.749737 Dram Type= 6, Freq= 0, CH_0, rank 0
928 13:53:36.752898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 13:53:36.752992 ==
930 13:53:36.753061 DQS Delay:
931 13:53:36.756258 DQS0 = 0, DQS1 = 0
932 13:53:36.756345 DQM Delay:
933 13:53:36.759602 DQM0 = 88, DQM1 = 76
934 13:53:36.759689 DQ Delay:
935 13:53:36.763533 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 13:53:36.766338 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
937 13:53:36.769543 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
938 13:53:36.773381 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
939 13:53:36.773478
940 13:53:36.773546
941 13:53:36.773608 ==
942 13:53:36.776233 Dram Type= 6, Freq= 0, CH_0, rank 0
943 13:53:36.779568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 13:53:36.782553 ==
945 13:53:36.782642
946 13:53:36.782709
947 13:53:36.782770 TX Vref Scan disable
948 13:53:36.786047 == TX Byte 0 ==
949 13:53:36.790173 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
950 13:53:36.792735 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
951 13:53:36.796107 == TX Byte 1 ==
952 13:53:36.799577 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
953 13:53:36.802631 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
954 13:53:36.806605 ==
955 13:53:36.806702 Dram Type= 6, Freq= 0, CH_0, rank 0
956 13:53:36.813000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 13:53:36.813101 ==
958 13:53:36.824719 TX Vref=22, minBit 1, minWin=26, winSum=435
959 13:53:36.828225 TX Vref=24, minBit 5, minWin=26, winSum=439
960 13:53:36.831658 TX Vref=26, minBit 3, minWin=27, winSum=446
961 13:53:36.834899 TX Vref=28, minBit 3, minWin=27, winSum=448
962 13:53:36.838073 TX Vref=30, minBit 1, minWin=28, winSum=453
963 13:53:36.844540 TX Vref=32, minBit 8, minWin=27, winSum=450
964 13:53:36.848652 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 30
965 13:53:36.848756
966 13:53:36.851680 Final TX Range 1 Vref 30
967 13:53:36.851804
968 13:53:36.851871 ==
969 13:53:36.854635 Dram Type= 6, Freq= 0, CH_0, rank 0
970 13:53:36.857932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 13:53:36.858034 ==
972 13:53:36.861161
973 13:53:36.861248
974 13:53:36.861323 TX Vref Scan disable
975 13:53:36.864758 == TX Byte 0 ==
976 13:53:36.868295 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 13:53:36.874811 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 13:53:36.874926 == TX Byte 1 ==
979 13:53:36.877905 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
980 13:53:36.884551 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
981 13:53:36.884659
982 13:53:36.884728 [DATLAT]
983 13:53:36.884790 Freq=800, CH0 RK0
984 13:53:36.884850
985 13:53:36.888173 DATLAT Default: 0xa
986 13:53:36.888261 0, 0xFFFF, sum = 0
987 13:53:36.891136 1, 0xFFFF, sum = 0
988 13:53:36.891228 2, 0xFFFF, sum = 0
989 13:53:36.894801 3, 0xFFFF, sum = 0
990 13:53:36.897999 4, 0xFFFF, sum = 0
991 13:53:36.898091 5, 0xFFFF, sum = 0
992 13:53:36.901246 6, 0xFFFF, sum = 0
993 13:53:36.901335 7, 0xFFFF, sum = 0
994 13:53:36.905251 8, 0xFFFF, sum = 0
995 13:53:36.905341 9, 0x0, sum = 1
996 13:53:36.905409 10, 0x0, sum = 2
997 13:53:36.908019 11, 0x0, sum = 3
998 13:53:36.908108 12, 0x0, sum = 4
999 13:53:36.911301 best_step = 10
1000 13:53:36.911425
1001 13:53:36.911495 ==
1002 13:53:36.914501 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 13:53:36.917771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 13:53:36.917865 ==
1005 13:53:36.921716 RX Vref Scan: 1
1006 13:53:36.921806
1007 13:53:36.924450 Set Vref Range= 32 -> 127
1008 13:53:36.924537
1009 13:53:36.924605 RX Vref 32 -> 127, step: 1
1010 13:53:36.924667
1011 13:53:36.928127 RX Delay -95 -> 252, step: 8
1012 13:53:36.928217
1013 13:53:36.931241 Set Vref, RX VrefLevel [Byte0]: 32
1014 13:53:36.934698 [Byte1]: 32
1015 13:53:36.934790
1016 13:53:36.937791 Set Vref, RX VrefLevel [Byte0]: 33
1017 13:53:36.941222 [Byte1]: 33
1018 13:53:36.945715
1019 13:53:36.945807 Set Vref, RX VrefLevel [Byte0]: 34
1020 13:53:36.948865 [Byte1]: 34
1021 13:53:36.952735
1022 13:53:36.952825 Set Vref, RX VrefLevel [Byte0]: 35
1023 13:53:36.956484 [Byte1]: 35
1024 13:53:36.960496
1025 13:53:36.960594 Set Vref, RX VrefLevel [Byte0]: 36
1026 13:53:36.963695 [Byte1]: 36
1027 13:53:36.968116
1028 13:53:36.968208 Set Vref, RX VrefLevel [Byte0]: 37
1029 13:53:36.971281 [Byte1]: 37
1030 13:53:36.975759
1031 13:53:36.975863 Set Vref, RX VrefLevel [Byte0]: 38
1032 13:53:36.979265 [Byte1]: 38
1033 13:53:36.983221
1034 13:53:36.983321 Set Vref, RX VrefLevel [Byte0]: 39
1035 13:53:36.986701 [Byte1]: 39
1036 13:53:36.990539
1037 13:53:36.990631 Set Vref, RX VrefLevel [Byte0]: 40
1038 13:53:36.994199 [Byte1]: 40
1039 13:53:36.998663
1040 13:53:37.001348 Set Vref, RX VrefLevel [Byte0]: 41
1041 13:53:37.001439 [Byte1]: 41
1042 13:53:37.005579
1043 13:53:37.005670 Set Vref, RX VrefLevel [Byte0]: 42
1044 13:53:37.008965 [Byte1]: 42
1045 13:53:37.013535
1046 13:53:37.013633 Set Vref, RX VrefLevel [Byte0]: 43
1047 13:53:37.016764 [Byte1]: 43
1048 13:53:37.021302
1049 13:53:37.021400 Set Vref, RX VrefLevel [Byte0]: 44
1050 13:53:37.024207 [Byte1]: 44
1051 13:53:37.028461
1052 13:53:37.028554 Set Vref, RX VrefLevel [Byte0]: 45
1053 13:53:37.032348 [Byte1]: 45
1054 13:53:37.036091
1055 13:53:37.036185 Set Vref, RX VrefLevel [Byte0]: 46
1056 13:53:37.039772 [Byte1]: 46
1057 13:53:37.043702
1058 13:53:37.043790 Set Vref, RX VrefLevel [Byte0]: 47
1059 13:53:37.047528 [Byte1]: 47
1060 13:53:37.051572
1061 13:53:37.051661 Set Vref, RX VrefLevel [Byte0]: 48
1062 13:53:37.054796 [Byte1]: 48
1063 13:53:37.058930
1064 13:53:37.059019 Set Vref, RX VrefLevel [Byte0]: 49
1065 13:53:37.062096 [Byte1]: 49
1066 13:53:37.066518
1067 13:53:37.066609 Set Vref, RX VrefLevel [Byte0]: 50
1068 13:53:37.069790 [Byte1]: 50
1069 13:53:37.074338
1070 13:53:37.074428 Set Vref, RX VrefLevel [Byte0]: 51
1071 13:53:37.077232 [Byte1]: 51
1072 13:53:37.081996
1073 13:53:37.082089 Set Vref, RX VrefLevel [Byte0]: 52
1074 13:53:37.085152 [Byte1]: 52
1075 13:53:37.089447
1076 13:53:37.089541 Set Vref, RX VrefLevel [Byte0]: 53
1077 13:53:37.092906 [Byte1]: 53
1078 13:53:37.096958
1079 13:53:37.097052 Set Vref, RX VrefLevel [Byte0]: 54
1080 13:53:37.100272 [Byte1]: 54
1081 13:53:37.105050
1082 13:53:37.105147 Set Vref, RX VrefLevel [Byte0]: 55
1083 13:53:37.107958 [Byte1]: 55
1084 13:53:37.112082
1085 13:53:37.112172 Set Vref, RX VrefLevel [Byte0]: 56
1086 13:53:37.115460 [Byte1]: 56
1087 13:53:37.119818
1088 13:53:37.119915 Set Vref, RX VrefLevel [Byte0]: 57
1089 13:53:37.122812 [Byte1]: 57
1090 13:53:37.127069
1091 13:53:37.127159 Set Vref, RX VrefLevel [Byte0]: 58
1092 13:53:37.130629 [Byte1]: 58
1093 13:53:37.134816
1094 13:53:37.134913 Set Vref, RX VrefLevel [Byte0]: 59
1095 13:53:37.138037 [Byte1]: 59
1096 13:53:37.142760
1097 13:53:37.142855 Set Vref, RX VrefLevel [Byte0]: 60
1098 13:53:37.146032 [Byte1]: 60
1099 13:53:37.150155
1100 13:53:37.150244 Set Vref, RX VrefLevel [Byte0]: 61
1101 13:53:37.153482 [Byte1]: 61
1102 13:53:37.158328
1103 13:53:37.158421 Set Vref, RX VrefLevel [Byte0]: 62
1104 13:53:37.161177 [Byte1]: 62
1105 13:53:37.165078
1106 13:53:37.165167 Set Vref, RX VrefLevel [Byte0]: 63
1107 13:53:37.168553 [Byte1]: 63
1108 13:53:37.172662
1109 13:53:37.172754 Set Vref, RX VrefLevel [Byte0]: 64
1110 13:53:37.176488 [Byte1]: 64
1111 13:53:37.180251
1112 13:53:37.180341 Set Vref, RX VrefLevel [Byte0]: 65
1113 13:53:37.183478 [Byte1]: 65
1114 13:53:37.188279
1115 13:53:37.188376 Set Vref, RX VrefLevel [Byte0]: 66
1116 13:53:37.191220 [Byte1]: 66
1117 13:53:37.195948
1118 13:53:37.196041 Set Vref, RX VrefLevel [Byte0]: 67
1119 13:53:37.198931 [Byte1]: 67
1120 13:53:37.204273
1121 13:53:37.204369 Set Vref, RX VrefLevel [Byte0]: 68
1122 13:53:37.207270 [Byte1]: 68
1123 13:53:37.211044
1124 13:53:37.211135 Set Vref, RX VrefLevel [Byte0]: 69
1125 13:53:37.213975 [Byte1]: 69
1126 13:53:37.218271
1127 13:53:37.218367 Set Vref, RX VrefLevel [Byte0]: 70
1128 13:53:37.221668 [Byte1]: 70
1129 13:53:37.226147
1130 13:53:37.226241 Set Vref, RX VrefLevel [Byte0]: 71
1131 13:53:37.229298 [Byte1]: 71
1132 13:53:37.233570
1133 13:53:37.233666 Set Vref, RX VrefLevel [Byte0]: 72
1134 13:53:37.236731 [Byte1]: 72
1135 13:53:37.241271
1136 13:53:37.241372 Set Vref, RX VrefLevel [Byte0]: 73
1137 13:53:37.244606 [Byte1]: 73
1138 13:53:37.248889
1139 13:53:37.248983 Set Vref, RX VrefLevel [Byte0]: 74
1140 13:53:37.252339 [Byte1]: 74
1141 13:53:37.256553
1142 13:53:37.256652 Set Vref, RX VrefLevel [Byte0]: 75
1143 13:53:37.259862 [Byte1]: 75
1144 13:53:37.263773
1145 13:53:37.263860 Set Vref, RX VrefLevel [Byte0]: 76
1146 13:53:37.267263 [Byte1]: 76
1147 13:53:37.272119
1148 13:53:37.272211 Set Vref, RX VrefLevel [Byte0]: 77
1149 13:53:37.274856 [Byte1]: 77
1150 13:53:37.279575
1151 13:53:37.279670 Final RX Vref Byte 0 = 55 to rank0
1152 13:53:37.282754 Final RX Vref Byte 1 = 60 to rank0
1153 13:53:37.285667 Final RX Vref Byte 0 = 55 to rank1
1154 13:53:37.289379 Final RX Vref Byte 1 = 60 to rank1==
1155 13:53:37.292400 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 13:53:37.299231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 13:53:37.299337 ==
1158 13:53:37.299440 DQS Delay:
1159 13:53:37.299503 DQS0 = 0, DQS1 = 0
1160 13:53:37.302290 DQM Delay:
1161 13:53:37.302374 DQM0 = 88, DQM1 = 77
1162 13:53:37.305490 DQ Delay:
1163 13:53:37.309040 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1164 13:53:37.312305 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1165 13:53:37.315560 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =76
1166 13:53:37.318640 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1167 13:53:37.318736
1168 13:53:37.318840
1169 13:53:37.325495 [DQSOSCAuto] RK0, (LSB)MR18= 0x342e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1170 13:53:37.328744 CH0 RK0: MR19=606, MR18=342E
1171 13:53:37.335411 CH0_RK0: MR19=0x606, MR18=0x342E, DQSOSC=396, MR23=63, INC=94, DEC=62
1172 13:53:37.335530
1173 13:53:37.338660 ----->DramcWriteLeveling(PI) begin...
1174 13:53:37.338747 ==
1175 13:53:37.342168 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 13:53:37.345593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 13:53:37.345683 ==
1178 13:53:37.349011 Write leveling (Byte 0): 30 => 30
1179 13:53:37.352230 Write leveling (Byte 1): 26 => 26
1180 13:53:37.355492 DramcWriteLeveling(PI) end<-----
1181 13:53:37.355582
1182 13:53:37.355664 ==
1183 13:53:37.358566 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 13:53:37.362112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 13:53:37.362215 ==
1186 13:53:37.364984 [Gating] SW mode calibration
1187 13:53:37.409643 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 13:53:37.410271 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 13:53:37.410361 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 13:53:37.410613 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1191 13:53:37.410866 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1192 13:53:37.411349 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1193 13:53:37.411935 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:53:37.412017 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:53:37.412459 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:53:37.453804 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 13:53:37.454142 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 13:53:37.454239 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 13:53:37.454305 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 13:53:37.454768 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 13:53:37.455228 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 13:53:37.455892 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 13:53:37.456002 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:53:37.456282 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:53:37.457004 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:53:37.494473 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 13:53:37.494829 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1208 13:53:37.494909 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:53:37.494973 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:53:37.495045 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 13:53:37.495908 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 13:53:37.496540 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:53:37.496624 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:53:37.496884 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1215 13:53:37.499317 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1216 13:53:37.502894 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1217 13:53:37.506333 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 13:53:37.509400 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 13:53:37.516079 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 13:53:37.519340 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 13:53:37.522955 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 13:53:37.526158 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
1223 13:53:37.532781 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
1224 13:53:37.536022 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:53:37.539799 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:53:37.545861 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:53:37.549824 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:53:37.554294 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:53:37.557536 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:53:37.561499 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1231 13:53:37.568656 0 11 8 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
1232 13:53:37.572135 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 13:53:37.575662 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 13:53:37.579014 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 13:53:37.585736 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 13:53:37.588906 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 13:53:37.592151 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 13:53:37.598943 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1239 13:53:37.602703 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1240 13:53:37.605548 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 13:53:37.612565 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 13:53:37.615611 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 13:53:37.618923 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 13:53:37.625511 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 13:53:37.628765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 13:53:37.632152 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 13:53:37.638539 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 13:53:37.642312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 13:53:37.645007 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 13:53:37.651444 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 13:53:37.654989 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 13:53:37.658793 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 13:53:37.664709 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1254 13:53:37.668055 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1255 13:53:37.671543 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1256 13:53:37.674652 Total UI for P1: 0, mck2ui 16
1257 13:53:37.677865 best dqsien dly found for B0: ( 0, 14, 2)
1258 13:53:37.684687 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 13:53:37.684796 Total UI for P1: 0, mck2ui 16
1260 13:53:37.691133 best dqsien dly found for B1: ( 0, 14, 8)
1261 13:53:37.694515 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1262 13:53:37.698203 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1263 13:53:37.698316
1264 13:53:37.701542 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1265 13:53:37.704604 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1266 13:53:37.707931 [Gating] SW calibration Done
1267 13:53:37.708010 ==
1268 13:53:37.711216 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 13:53:37.714539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 13:53:37.714616 ==
1271 13:53:37.717646 RX Vref Scan: 0
1272 13:53:37.717723
1273 13:53:37.717786 RX Vref 0 -> 0, step: 1
1274 13:53:37.717849
1275 13:53:37.721174 RX Delay -130 -> 252, step: 16
1276 13:53:37.724448 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1277 13:53:37.731244 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1278 13:53:37.734249 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1279 13:53:37.737938 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1280 13:53:37.741575 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1281 13:53:37.744349 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1282 13:53:37.751613 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1283 13:53:37.754633 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1284 13:53:37.757946 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1285 13:53:37.760840 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1286 13:53:37.764173 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1287 13:53:37.770831 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1288 13:53:37.774688 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1289 13:53:37.777829 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1290 13:53:37.781097 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1291 13:53:37.784230 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1292 13:53:37.787875 ==
1293 13:53:37.790754 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 13:53:37.794256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 13:53:37.794354 ==
1296 13:53:37.794444 DQS Delay:
1297 13:53:37.797591 DQS0 = 0, DQS1 = 0
1298 13:53:37.797679 DQM Delay:
1299 13:53:37.800693 DQM0 = 86, DQM1 = 77
1300 13:53:37.800780 DQ Delay:
1301 13:53:37.804131 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1302 13:53:37.807550 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1303 13:53:37.810750 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1304 13:53:37.814313 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1305 13:53:37.814395
1306 13:53:37.814460
1307 13:53:37.814519 ==
1308 13:53:37.818167 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 13:53:37.821146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 13:53:37.821236 ==
1311 13:53:37.821301
1312 13:53:37.821361
1313 13:53:37.824317 TX Vref Scan disable
1314 13:53:37.827510 == TX Byte 0 ==
1315 13:53:37.830484 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1316 13:53:37.833777 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1317 13:53:37.837298 == TX Byte 1 ==
1318 13:53:37.840476 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1319 13:53:37.843729 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1320 13:53:37.843810 ==
1321 13:53:37.847023 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 13:53:37.853536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 13:53:37.853637 ==
1324 13:53:37.865674 TX Vref=22, minBit 0, minWin=27, winSum=441
1325 13:53:37.869062 TX Vref=24, minBit 0, minWin=27, winSum=446
1326 13:53:37.872145 TX Vref=26, minBit 1, minWin=27, winSum=445
1327 13:53:37.875535 TX Vref=28, minBit 2, minWin=27, winSum=449
1328 13:53:37.879030 TX Vref=30, minBit 2, minWin=27, winSum=453
1329 13:53:37.885956 TX Vref=32, minBit 6, minWin=27, winSum=452
1330 13:53:37.889028 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 30
1331 13:53:37.889118
1332 13:53:37.892486 Final TX Range 1 Vref 30
1333 13:53:37.892562
1334 13:53:37.892622 ==
1335 13:53:37.895604 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 13:53:37.898785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 13:53:37.898863 ==
1338 13:53:37.902106
1339 13:53:37.902186
1340 13:53:37.902248 TX Vref Scan disable
1341 13:53:37.905824 == TX Byte 0 ==
1342 13:53:37.908995 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1343 13:53:37.915569 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1344 13:53:37.915669 == TX Byte 1 ==
1345 13:53:37.918911 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1346 13:53:37.925726 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1347 13:53:37.925831
1348 13:53:37.925896 [DATLAT]
1349 13:53:37.925955 Freq=800, CH0 RK1
1350 13:53:37.926014
1351 13:53:37.929019 DATLAT Default: 0xa
1352 13:53:37.929095 0, 0xFFFF, sum = 0
1353 13:53:37.932311 1, 0xFFFF, sum = 0
1354 13:53:37.935612 2, 0xFFFF, sum = 0
1355 13:53:37.935695 3, 0xFFFF, sum = 0
1356 13:53:37.939256 4, 0xFFFF, sum = 0
1357 13:53:37.939337 5, 0xFFFF, sum = 0
1358 13:53:37.942089 6, 0xFFFF, sum = 0
1359 13:53:37.942177 7, 0xFFFF, sum = 0
1360 13:53:37.945379 8, 0xFFFF, sum = 0
1361 13:53:37.945458 9, 0x0, sum = 1
1362 13:53:37.948439 10, 0x0, sum = 2
1363 13:53:37.948513 11, 0x0, sum = 3
1364 13:53:37.948577 12, 0x0, sum = 4
1365 13:53:37.951898 best_step = 10
1366 13:53:37.952000
1367 13:53:37.952092 ==
1368 13:53:37.955480 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 13:53:37.958609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 13:53:37.958687 ==
1371 13:53:37.961887 RX Vref Scan: 0
1372 13:53:37.961969
1373 13:53:37.962032 RX Vref 0 -> 0, step: 1
1374 13:53:37.965289
1375 13:53:37.965396 RX Delay -95 -> 252, step: 8
1376 13:53:37.972442 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1377 13:53:37.975286 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1378 13:53:37.979290 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1379 13:53:37.982278 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1380 13:53:37.985319 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1381 13:53:37.991975 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1382 13:53:37.996400 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1383 13:53:37.998466 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1384 13:53:38.001971 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1385 13:53:38.005323 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1386 13:53:38.011966 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1387 13:53:38.016041 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1388 13:53:38.018664 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1389 13:53:38.022042 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1390 13:53:38.029177 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1391 13:53:38.031668 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1392 13:53:38.031756 ==
1393 13:53:38.035209 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 13:53:38.038932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 13:53:38.039015 ==
1396 13:53:38.041716 DQS Delay:
1397 13:53:38.041788 DQS0 = 0, DQS1 = 0
1398 13:53:38.041865 DQM Delay:
1399 13:53:38.045322 DQM0 = 86, DQM1 = 76
1400 13:53:38.045399 DQ Delay:
1401 13:53:38.048778 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1402 13:53:38.051779 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1403 13:53:38.055485 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1404 13:53:38.058436 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1405 13:53:38.058512
1406 13:53:38.058574
1407 13:53:38.068416 [DQSOSCAuto] RK1, (LSB)MR18= 0x2824, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1408 13:53:38.068536 CH0 RK1: MR19=606, MR18=2824
1409 13:53:38.075145 CH0_RK1: MR19=0x606, MR18=0x2824, DQSOSC=399, MR23=63, INC=92, DEC=61
1410 13:53:38.078639 [RxdqsGatingPostProcess] freq 800
1411 13:53:38.085640 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1412 13:53:38.088342 Pre-setting of DQS Precalculation
1413 13:53:38.091610 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1414 13:53:38.091690 ==
1415 13:53:38.094852 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 13:53:38.101601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 13:53:38.101701 ==
1418 13:53:38.104912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 13:53:38.111326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 13:53:38.120684 [CA 0] Center 37 (6~68) winsize 63
1421 13:53:38.123829 [CA 1] Center 37 (6~68) winsize 63
1422 13:53:38.127321 [CA 2] Center 35 (5~66) winsize 62
1423 13:53:38.131001 [CA 3] Center 34 (4~65) winsize 62
1424 13:53:38.133615 [CA 4] Center 35 (4~66) winsize 63
1425 13:53:38.137117 [CA 5] Center 34 (4~65) winsize 62
1426 13:53:38.137215
1427 13:53:38.140666 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1428 13:53:38.140750
1429 13:53:38.143691 [CATrainingPosCal] consider 1 rank data
1430 13:53:38.147077 u2DelayCellTimex100 = 270/100 ps
1431 13:53:38.150534 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1432 13:53:38.156867 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1433 13:53:38.160917 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1434 13:53:38.163621 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 13:53:38.167706 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1436 13:53:38.170125 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 13:53:38.170207
1438 13:53:38.174098 CA PerBit enable=1, Macro0, CA PI delay=34
1439 13:53:38.174177
1440 13:53:38.177201 [CBTSetCACLKResult] CA Dly = 34
1441 13:53:38.180155 CS Dly: 4 (0~35)
1442 13:53:38.180232 ==
1443 13:53:38.183280 Dram Type= 6, Freq= 0, CH_1, rank 1
1444 13:53:38.186798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 13:53:38.186886 ==
1446 13:53:38.193521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 13:53:38.197152 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 13:53:38.206888 [CA 0] Center 36 (6~67) winsize 62
1449 13:53:38.209992 [CA 1] Center 36 (6~67) winsize 62
1450 13:53:38.213855 [CA 2] Center 35 (4~66) winsize 63
1451 13:53:38.218338 [CA 3] Center 34 (4~65) winsize 62
1452 13:53:38.220955 [CA 4] Center 34 (4~65) winsize 62
1453 13:53:38.224827 [CA 5] Center 34 (4~65) winsize 62
1454 13:53:38.224915
1455 13:53:38.227994 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1456 13:53:38.228067
1457 13:53:38.231519 [CATrainingPosCal] consider 2 rank data
1458 13:53:38.235234 u2DelayCellTimex100 = 270/100 ps
1459 13:53:38.239196 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 13:53:38.242724 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 13:53:38.246110 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1462 13:53:38.250343 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 13:53:38.253381 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 13:53:38.256338 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 13:53:38.256422
1466 13:53:38.259961 CA PerBit enable=1, Macro0, CA PI delay=34
1467 13:53:38.260041
1468 13:53:38.263275 [CBTSetCACLKResult] CA Dly = 34
1469 13:53:38.263403 CS Dly: 5 (0~37)
1470 13:53:38.263512
1471 13:53:38.266875 ----->DramcWriteLeveling(PI) begin...
1472 13:53:38.269649 ==
1473 13:53:38.273091 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 13:53:38.276480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 13:53:38.276562 ==
1476 13:53:38.280154 Write leveling (Byte 0): 26 => 26
1477 13:53:38.282958 Write leveling (Byte 1): 25 => 25
1478 13:53:38.286757 DramcWriteLeveling(PI) end<-----
1479 13:53:38.286838
1480 13:53:38.286899 ==
1481 13:53:38.289992 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 13:53:38.293295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 13:53:38.293376 ==
1484 13:53:38.296500 [Gating] SW mode calibration
1485 13:53:38.303295 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1486 13:53:38.309840 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1487 13:53:38.312980 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1488 13:53:38.316218 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1489 13:53:38.320021 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:53:38.326568 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:53:38.329576 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:53:38.333103 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:53:38.339333 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:53:38.342924 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 13:53:38.345997 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 13:53:38.352916 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 13:53:38.355876 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 13:53:38.359275 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 13:53:38.365948 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 13:53:38.369229 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 13:53:38.373023 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 13:53:38.379513 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:53:38.382963 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1504 13:53:38.386067 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1505 13:53:38.392540 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:53:38.396011 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 13:53:38.399128 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:53:38.405951 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 13:53:38.409283 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 13:53:38.413038 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 13:53:38.419726 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 13:53:38.422567 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 13:53:38.426243 0 9 8 | B1->B0 | 2d2d 3232 | 0 1 | (0 0) (1 1)
1514 13:53:38.432509 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 13:53:38.436207 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 13:53:38.439188 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 13:53:38.445834 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 13:53:38.449052 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 13:53:38.452631 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1520 13:53:38.456746 0 10 4 | B1->B0 | 3333 3030 | 1 1 | (0 0) (1 1)
1521 13:53:38.462964 0 10 8 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1522 13:53:38.466068 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:53:38.469028 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:53:38.475755 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:53:38.478951 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:53:38.482659 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:53:38.489384 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:53:38.492708 0 11 4 | B1->B0 | 2626 2e2e | 0 1 | (0 0) (0 0)
1529 13:53:38.496230 0 11 8 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
1530 13:53:38.502956 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 13:53:38.505716 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 13:53:38.509525 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 13:53:38.515594 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 13:53:38.518924 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 13:53:38.522667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 13:53:38.529045 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1537 13:53:38.532022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 13:53:38.536291 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 13:53:38.542345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 13:53:38.545507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 13:53:38.548901 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 13:53:38.555166 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 13:53:38.559706 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 13:53:38.562343 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 13:53:38.568815 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 13:53:38.572004 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 13:53:38.575192 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 13:53:38.582067 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 13:53:38.585565 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 13:53:38.588651 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 13:53:38.595154 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 13:53:38.599128 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1553 13:53:38.601762 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 13:53:38.605415 Total UI for P1: 0, mck2ui 16
1555 13:53:38.608611 best dqsien dly found for B0: ( 0, 14, 4)
1556 13:53:38.611989 Total UI for P1: 0, mck2ui 16
1557 13:53:38.615787 best dqsien dly found for B1: ( 0, 14, 4)
1558 13:53:38.618833 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1559 13:53:38.622035 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1560 13:53:38.622136
1561 13:53:38.625188 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1562 13:53:38.628341 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1563 13:53:38.632283 [Gating] SW calibration Done
1564 13:53:38.632378 ==
1565 13:53:38.635219 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 13:53:38.639018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 13:53:38.642332 ==
1568 13:53:38.642425 RX Vref Scan: 0
1569 13:53:38.642509
1570 13:53:38.645170 RX Vref 0 -> 0, step: 1
1571 13:53:38.645263
1572 13:53:38.648783 RX Delay -130 -> 252, step: 16
1573 13:53:38.652088 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1574 13:53:38.656122 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1575 13:53:38.658814 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1576 13:53:38.662371 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1577 13:53:38.668517 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1578 13:53:38.671839 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1579 13:53:38.675544 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1580 13:53:38.678683 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1581 13:53:38.682031 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1582 13:53:38.688751 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1583 13:53:38.691794 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1584 13:53:38.695068 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1585 13:53:38.698985 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1586 13:53:38.701716 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1587 13:53:38.708622 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1588 13:53:38.711963 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1589 13:53:38.712056 ==
1590 13:53:38.715126 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 13:53:38.718481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 13:53:38.718568 ==
1593 13:53:38.721857 DQS Delay:
1594 13:53:38.721946 DQS0 = 0, DQS1 = 0
1595 13:53:38.722010 DQM Delay:
1596 13:53:38.725494 DQM0 = 87, DQM1 = 81
1597 13:53:38.725580 DQ Delay:
1598 13:53:38.728802 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1599 13:53:38.731658 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1600 13:53:38.735279 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1601 13:53:38.738270 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1602 13:53:38.738360
1603 13:53:38.738424
1604 13:53:38.738484 ==
1605 13:53:38.741432 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 13:53:38.747968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 13:53:38.748069 ==
1608 13:53:38.748136
1609 13:53:38.748196
1610 13:53:38.748253 TX Vref Scan disable
1611 13:53:38.752186 == TX Byte 0 ==
1612 13:53:38.755290 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1613 13:53:38.761737 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1614 13:53:38.761847 == TX Byte 1 ==
1615 13:53:38.765144 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1616 13:53:38.772230 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1617 13:53:38.772342 ==
1618 13:53:38.775275 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 13:53:38.778161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 13:53:38.778247 ==
1621 13:53:38.790908 TX Vref=22, minBit 6, minWin=26, winSum=440
1622 13:53:38.794640 TX Vref=24, minBit 0, minWin=27, winSum=442
1623 13:53:38.797856 TX Vref=26, minBit 1, minWin=27, winSum=450
1624 13:53:38.801596 TX Vref=28, minBit 1, minWin=27, winSum=454
1625 13:53:38.804813 TX Vref=30, minBit 0, minWin=27, winSum=452
1626 13:53:38.808005 TX Vref=32, minBit 1, minWin=27, winSum=449
1627 13:53:38.814516 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 28
1628 13:53:38.814623
1629 13:53:38.818805 Final TX Range 1 Vref 28
1630 13:53:38.818901
1631 13:53:38.818967 ==
1632 13:53:38.821209 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 13:53:38.824672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 13:53:38.824760 ==
1635 13:53:38.824831
1636 13:53:38.824890
1637 13:53:38.828136 TX Vref Scan disable
1638 13:53:38.831807 == TX Byte 0 ==
1639 13:53:38.834955 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1640 13:53:38.838054 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1641 13:53:38.841838 == TX Byte 1 ==
1642 13:53:38.844504 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1643 13:53:38.847793 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1644 13:53:38.847880
1645 13:53:38.851343 [DATLAT]
1646 13:53:38.851436 Freq=800, CH1 RK0
1647 13:53:38.851507
1648 13:53:38.855117 DATLAT Default: 0xa
1649 13:53:38.855229 0, 0xFFFF, sum = 0
1650 13:53:38.858077 1, 0xFFFF, sum = 0
1651 13:53:38.858164 2, 0xFFFF, sum = 0
1652 13:53:38.861156 3, 0xFFFF, sum = 0
1653 13:53:38.861247 4, 0xFFFF, sum = 0
1654 13:53:38.864829 5, 0xFFFF, sum = 0
1655 13:53:38.864916 6, 0xFFFF, sum = 0
1656 13:53:38.867921 7, 0xFFFF, sum = 0
1657 13:53:38.868007 8, 0xFFFF, sum = 0
1658 13:53:38.871293 9, 0x0, sum = 1
1659 13:53:38.871386 10, 0x0, sum = 2
1660 13:53:38.874433 11, 0x0, sum = 3
1661 13:53:38.874550 12, 0x0, sum = 4
1662 13:53:38.878440 best_step = 10
1663 13:53:38.878525
1664 13:53:38.878590 ==
1665 13:53:38.881133 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 13:53:38.885195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 13:53:38.885285 ==
1668 13:53:38.887908 RX Vref Scan: 1
1669 13:53:38.887993
1670 13:53:38.888059 Set Vref Range= 32 -> 127
1671 13:53:38.888120
1672 13:53:38.891000 RX Vref 32 -> 127, step: 1
1673 13:53:38.891083
1674 13:53:38.895033 RX Delay -95 -> 252, step: 8
1675 13:53:38.895122
1676 13:53:38.898058 Set Vref, RX VrefLevel [Byte0]: 32
1677 13:53:38.901134 [Byte1]: 32
1678 13:53:38.901218
1679 13:53:38.904921 Set Vref, RX VrefLevel [Byte0]: 33
1680 13:53:38.907762 [Byte1]: 33
1681 13:53:38.911208
1682 13:53:38.911295 Set Vref, RX VrefLevel [Byte0]: 34
1683 13:53:38.914303 [Byte1]: 34
1684 13:53:38.918983
1685 13:53:38.919075 Set Vref, RX VrefLevel [Byte0]: 35
1686 13:53:38.922002 [Byte1]: 35
1687 13:53:38.926319
1688 13:53:38.926413 Set Vref, RX VrefLevel [Byte0]: 36
1689 13:53:38.929576 [Byte1]: 36
1690 13:53:38.934060
1691 13:53:38.934158 Set Vref, RX VrefLevel [Byte0]: 37
1692 13:53:38.936938 [Byte1]: 37
1693 13:53:38.941431
1694 13:53:38.944929 Set Vref, RX VrefLevel [Byte0]: 38
1695 13:53:38.948508 [Byte1]: 38
1696 13:53:38.948606
1697 13:53:38.951160 Set Vref, RX VrefLevel [Byte0]: 39
1698 13:53:38.954738 [Byte1]: 39
1699 13:53:38.954827
1700 13:53:38.957774 Set Vref, RX VrefLevel [Byte0]: 40
1701 13:53:38.960873 [Byte1]: 40
1702 13:53:38.960960
1703 13:53:38.964332 Set Vref, RX VrefLevel [Byte0]: 41
1704 13:53:38.967906 [Byte1]: 41
1705 13:53:38.972085
1706 13:53:38.972177 Set Vref, RX VrefLevel [Byte0]: 42
1707 13:53:38.975144 [Byte1]: 42
1708 13:53:38.979443
1709 13:53:38.979531 Set Vref, RX VrefLevel [Byte0]: 43
1710 13:53:38.982647 [Byte1]: 43
1711 13:53:38.987266
1712 13:53:38.987357 Set Vref, RX VrefLevel [Byte0]: 44
1713 13:53:38.990763 [Byte1]: 44
1714 13:53:38.995098
1715 13:53:38.995188 Set Vref, RX VrefLevel [Byte0]: 45
1716 13:53:38.997945 [Byte1]: 45
1717 13:53:39.002342
1718 13:53:39.002430 Set Vref, RX VrefLevel [Byte0]: 46
1719 13:53:39.005829 [Byte1]: 46
1720 13:53:39.009820
1721 13:53:39.009908 Set Vref, RX VrefLevel [Byte0]: 47
1722 13:53:39.013049 [Byte1]: 47
1723 13:53:39.017818
1724 13:53:39.017906 Set Vref, RX VrefLevel [Byte0]: 48
1725 13:53:39.020426 [Byte1]: 48
1726 13:53:39.025130
1727 13:53:39.025226 Set Vref, RX VrefLevel [Byte0]: 49
1728 13:53:39.028553 [Byte1]: 49
1729 13:53:39.032980
1730 13:53:39.033069 Set Vref, RX VrefLevel [Byte0]: 50
1731 13:53:39.035681 [Byte1]: 50
1732 13:53:39.039920
1733 13:53:39.043407 Set Vref, RX VrefLevel [Byte0]: 51
1734 13:53:39.047218 [Byte1]: 51
1735 13:53:39.047308
1736 13:53:39.049825 Set Vref, RX VrefLevel [Byte0]: 52
1737 13:53:39.053272 [Byte1]: 52
1738 13:53:39.053358
1739 13:53:39.056608 Set Vref, RX VrefLevel [Byte0]: 53
1740 13:53:39.059899 [Byte1]: 53
1741 13:53:39.059985
1742 13:53:39.063213 Set Vref, RX VrefLevel [Byte0]: 54
1743 13:53:39.066472 [Byte1]: 54
1744 13:53:39.070788
1745 13:53:39.070906 Set Vref, RX VrefLevel [Byte0]: 55
1746 13:53:39.073907 [Byte1]: 55
1747 13:53:39.078425
1748 13:53:39.078511 Set Vref, RX VrefLevel [Byte0]: 56
1749 13:53:39.081627 [Byte1]: 56
1750 13:53:39.085553
1751 13:53:39.085643 Set Vref, RX VrefLevel [Byte0]: 57
1752 13:53:39.089825 [Byte1]: 57
1753 13:53:39.093369
1754 13:53:39.093456 Set Vref, RX VrefLevel [Byte0]: 58
1755 13:53:39.097079 [Byte1]: 58
1756 13:53:39.101110
1757 13:53:39.101201 Set Vref, RX VrefLevel [Byte0]: 59
1758 13:53:39.104180 [Byte1]: 59
1759 13:53:39.109039
1760 13:53:39.109131 Set Vref, RX VrefLevel [Byte0]: 60
1761 13:53:39.112027 [Byte1]: 60
1762 13:53:39.116283
1763 13:53:39.116371 Set Vref, RX VrefLevel [Byte0]: 61
1764 13:53:39.120511 [Byte1]: 61
1765 13:53:39.123855
1766 13:53:39.123970 Set Vref, RX VrefLevel [Byte0]: 62
1767 13:53:39.127275 [Byte1]: 62
1768 13:53:39.131728
1769 13:53:39.131830 Set Vref, RX VrefLevel [Byte0]: 63
1770 13:53:39.135012 [Byte1]: 63
1771 13:53:39.138851
1772 13:53:39.138946 Set Vref, RX VrefLevel [Byte0]: 64
1773 13:53:39.142566 [Byte1]: 64
1774 13:53:39.146572
1775 13:53:39.146665 Set Vref, RX VrefLevel [Byte0]: 65
1776 13:53:39.150070 [Byte1]: 65
1777 13:53:39.154283
1778 13:53:39.154373 Set Vref, RX VrefLevel [Byte0]: 66
1779 13:53:39.157943 [Byte1]: 66
1780 13:53:39.162067
1781 13:53:39.162155 Set Vref, RX VrefLevel [Byte0]: 67
1782 13:53:39.165411 [Byte1]: 67
1783 13:53:39.169186
1784 13:53:39.169273 Set Vref, RX VrefLevel [Byte0]: 68
1785 13:53:39.172657 [Byte1]: 68
1786 13:53:39.176942
1787 13:53:39.177032 Set Vref, RX VrefLevel [Byte0]: 69
1788 13:53:39.180136 [Byte1]: 69
1789 13:53:39.184992
1790 13:53:39.185084 Set Vref, RX VrefLevel [Byte0]: 70
1791 13:53:39.187801 [Byte1]: 70
1792 13:53:39.192381
1793 13:53:39.192475 Set Vref, RX VrefLevel [Byte0]: 71
1794 13:53:39.196003 [Byte1]: 71
1795 13:53:39.199782
1796 13:53:39.199871 Set Vref, RX VrefLevel [Byte0]: 72
1797 13:53:39.203309 [Byte1]: 72
1798 13:53:39.207634
1799 13:53:39.207728 Set Vref, RX VrefLevel [Byte0]: 73
1800 13:53:39.210873 [Byte1]: 73
1801 13:53:39.215150
1802 13:53:39.215239 Set Vref, RX VrefLevel [Byte0]: 74
1803 13:53:39.218701 [Byte1]: 74
1804 13:53:39.222637
1805 13:53:39.222731 Set Vref, RX VrefLevel [Byte0]: 75
1806 13:53:39.226389 [Byte1]: 75
1807 13:53:39.230081
1808 13:53:39.230176 Final RX Vref Byte 0 = 60 to rank0
1809 13:53:39.233608 Final RX Vref Byte 1 = 57 to rank0
1810 13:53:39.236704 Final RX Vref Byte 0 = 60 to rank1
1811 13:53:39.239975 Final RX Vref Byte 1 = 57 to rank1==
1812 13:53:39.243390 Dram Type= 6, Freq= 0, CH_1, rank 0
1813 13:53:39.250022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 13:53:39.250131 ==
1815 13:53:39.250199 DQS Delay:
1816 13:53:39.253133 DQS0 = 0, DQS1 = 0
1817 13:53:39.253245 DQM Delay:
1818 13:53:39.253311 DQM0 = 87, DQM1 = 81
1819 13:53:39.256763 DQ Delay:
1820 13:53:39.259979 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1821 13:53:39.263757 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1822 13:53:39.266649 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1823 13:53:39.269837 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1824 13:53:39.269926
1825 13:53:39.269995
1826 13:53:39.276245 [DQSOSCAuto] RK0, (LSB)MR18= 0x182c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1827 13:53:39.279680 CH1 RK0: MR19=606, MR18=182C
1828 13:53:39.286135 CH1_RK0: MR19=0x606, MR18=0x182C, DQSOSC=398, MR23=63, INC=93, DEC=62
1829 13:53:39.286244
1830 13:53:39.289852 ----->DramcWriteLeveling(PI) begin...
1831 13:53:39.289946 ==
1832 13:53:39.292825 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 13:53:39.296858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 13:53:39.296953 ==
1835 13:53:39.299883 Write leveling (Byte 0): 28 => 28
1836 13:53:39.303092 Write leveling (Byte 1): 28 => 28
1837 13:53:39.307521 DramcWriteLeveling(PI) end<-----
1838 13:53:39.307614
1839 13:53:39.307680 ==
1840 13:53:39.309554 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 13:53:39.313044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 13:53:39.313132 ==
1843 13:53:39.316862 [Gating] SW mode calibration
1844 13:53:39.323082 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1845 13:53:39.330182 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1846 13:53:39.332732 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1847 13:53:39.339459 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1848 13:53:39.343310 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1849 13:53:39.346102 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:53:39.353222 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:53:39.355968 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:53:39.359297 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:53:39.365692 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:53:39.369030 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:53:39.372959 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:53:39.379005 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:53:39.382220 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:53:39.385588 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:53:39.392717 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 13:53:39.395759 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 13:53:39.398872 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:53:39.405415 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1863 13:53:39.408932 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1864 13:53:39.411836 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:53:39.418567 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:53:39.421868 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:53:39.425554 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 13:53:39.428630 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 13:53:39.435005 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 13:53:39.438875 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 13:53:39.442130 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1872 13:53:39.448889 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1873 13:53:39.451845 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 13:53:39.455277 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 13:53:39.461907 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 13:53:39.465264 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 13:53:39.468712 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 13:53:39.475100 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1879 13:53:39.478709 0 10 4 | B1->B0 | 3131 2a2a | 1 1 | (1 1) (1 1)
1880 13:53:39.481455 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1881 13:53:39.488437 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:53:39.491593 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:53:39.495312 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 13:53:39.501713 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 13:53:39.505310 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 13:53:39.508288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:53:39.514831 0 11 4 | B1->B0 | 2b2b 3c3c | 0 0 | (0 0) (0 0)
1888 13:53:39.518178 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1889 13:53:39.521603 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 13:53:39.528755 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 13:53:39.531370 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 13:53:39.534790 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 13:53:39.541027 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 13:53:39.545299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1895 13:53:39.548063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1896 13:53:39.554475 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 13:53:39.557716 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 13:53:39.561294 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 13:53:39.568056 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 13:53:39.571810 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 13:53:39.574310 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 13:53:39.581083 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 13:53:39.584444 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 13:53:39.587999 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 13:53:39.594439 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 13:53:39.597417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 13:53:39.601187 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 13:53:39.607909 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 13:53:39.611114 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 13:53:39.614007 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 13:53:39.620608 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 13:53:39.620743 Total UI for P1: 0, mck2ui 16
1913 13:53:39.624278 best dqsien dly found for B0: ( 0, 14, 2)
1914 13:53:39.627218 Total UI for P1: 0, mck2ui 16
1915 13:53:39.630689 best dqsien dly found for B1: ( 0, 14, 2)
1916 13:53:39.634142 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1917 13:53:39.640788 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1918 13:53:39.640905
1919 13:53:39.644008 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1920 13:53:39.647474 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1921 13:53:39.650539 [Gating] SW calibration Done
1922 13:53:39.650660 ==
1923 13:53:39.654084 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 13:53:39.657050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 13:53:39.657134 ==
1926 13:53:39.660482 RX Vref Scan: 0
1927 13:53:39.660607
1928 13:53:39.660704 RX Vref 0 -> 0, step: 1
1929 13:53:39.660796
1930 13:53:39.664368 RX Delay -130 -> 252, step: 16
1931 13:53:39.667081 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1932 13:53:39.673732 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1933 13:53:39.677362 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1934 13:53:39.680616 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1935 13:53:39.684052 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1936 13:53:39.686969 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1937 13:53:39.690448 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1938 13:53:39.696984 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1939 13:53:39.700014 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1940 13:53:39.703326 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1941 13:53:39.707419 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1942 13:53:39.713749 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1943 13:53:39.716841 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1944 13:53:39.720528 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1945 13:53:39.723448 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1946 13:53:39.726835 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1947 13:53:39.726923 ==
1948 13:53:39.730102 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 13:53:39.736578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 13:53:39.736689 ==
1951 13:53:39.736758 DQS Delay:
1952 13:53:39.740093 DQS0 = 0, DQS1 = 0
1953 13:53:39.740177 DQM Delay:
1954 13:53:39.740243 DQM0 = 84, DQM1 = 84
1955 13:53:39.743564 DQ Delay:
1956 13:53:39.746939 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1957 13:53:39.750247 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1958 13:53:39.753571 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1959 13:53:39.757397 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1960 13:53:39.757485
1961 13:53:39.757556
1962 13:53:39.757617 ==
1963 13:53:39.760182 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 13:53:39.763290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 13:53:39.763386 ==
1966 13:53:39.763454
1967 13:53:39.763514
1968 13:53:39.767089 TX Vref Scan disable
1969 13:53:39.770373 == TX Byte 0 ==
1970 13:53:39.773873 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1971 13:53:39.777204 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1972 13:53:39.780116 == TX Byte 1 ==
1973 13:53:39.783623 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 13:53:39.786536 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 13:53:39.786624 ==
1976 13:53:39.789837 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 13:53:39.793420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 13:53:39.793514 ==
1979 13:53:39.807826 TX Vref=22, minBit 0, minWin=27, winSum=444
1980 13:53:39.810901 TX Vref=24, minBit 1, minWin=27, winSum=449
1981 13:53:39.814289 TX Vref=26, minBit 1, minWin=27, winSum=449
1982 13:53:39.817537 TX Vref=28, minBit 4, minWin=27, winSum=454
1983 13:53:39.820602 TX Vref=30, minBit 0, minWin=27, winSum=453
1984 13:53:39.827093 TX Vref=32, minBit 0, minWin=27, winSum=451
1985 13:53:39.830977 [TxChooseVref] Worse bit 4, Min win 27, Win sum 454, Final Vref 28
1986 13:53:39.831098
1987 13:53:39.834084 Final TX Range 1 Vref 28
1988 13:53:39.834171
1989 13:53:39.834236 ==
1990 13:53:39.837647 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 13:53:39.840438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 13:53:39.840523 ==
1993 13:53:39.843937
1994 13:53:39.844021
1995 13:53:39.844085 TX Vref Scan disable
1996 13:53:39.847285 == TX Byte 0 ==
1997 13:53:39.850533 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1998 13:53:39.857325 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1999 13:53:39.857433 == TX Byte 1 ==
2000 13:53:39.861122 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2001 13:53:39.866945 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2002 13:53:39.867046
2003 13:53:39.867112 [DATLAT]
2004 13:53:39.867172 Freq=800, CH1 RK1
2005 13:53:39.867231
2006 13:53:39.870700 DATLAT Default: 0xa
2007 13:53:39.870790 0, 0xFFFF, sum = 0
2008 13:53:39.874004 1, 0xFFFF, sum = 0
2009 13:53:39.877111 2, 0xFFFF, sum = 0
2010 13:53:39.877199 3, 0xFFFF, sum = 0
2011 13:53:39.880107 4, 0xFFFF, sum = 0
2012 13:53:39.880193 5, 0xFFFF, sum = 0
2013 13:53:39.884184 6, 0xFFFF, sum = 0
2014 13:53:39.884279 7, 0xFFFF, sum = 0
2015 13:53:39.886819 8, 0xFFFF, sum = 0
2016 13:53:39.886906 9, 0x0, sum = 1
2017 13:53:39.890667 10, 0x0, sum = 2
2018 13:53:39.890761 11, 0x0, sum = 3
2019 13:53:39.893718 12, 0x0, sum = 4
2020 13:53:39.893804 best_step = 10
2021 13:53:39.893870
2022 13:53:39.893931 ==
2023 13:53:39.897208 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 13:53:39.900505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 13:53:39.900593 ==
2026 13:53:39.903779 RX Vref Scan: 0
2027 13:53:39.903867
2028 13:53:39.907148 RX Vref 0 -> 0, step: 1
2029 13:53:39.907234
2030 13:53:39.907300 RX Delay -95 -> 252, step: 8
2031 13:53:39.914065 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2032 13:53:39.917407 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2033 13:53:39.920692 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2034 13:53:39.923766 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
2035 13:53:39.927144 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2036 13:53:39.933762 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2037 13:53:39.937043 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2038 13:53:39.940488 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2039 13:53:39.943564 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2040 13:53:39.947954 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2041 13:53:39.953665 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2042 13:53:39.956793 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2043 13:53:39.960201 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2044 13:53:39.963587 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2045 13:53:39.970692 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2046 13:53:39.974135 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2047 13:53:39.974237 ==
2048 13:53:39.976850 Dram Type= 6, Freq= 0, CH_1, rank 1
2049 13:53:39.980156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2050 13:53:39.980244 ==
2051 13:53:39.980334 DQS Delay:
2052 13:53:39.983905 DQS0 = 0, DQS1 = 0
2053 13:53:39.983990 DQM Delay:
2054 13:53:39.986804 DQM0 = 87, DQM1 = 83
2055 13:53:39.986889 DQ Delay:
2056 13:53:39.990747 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2057 13:53:39.993579 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2058 13:53:39.997228 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
2059 13:53:40.000044 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2060 13:53:40.000135
2061 13:53:40.000202
2062 13:53:40.010805 [DQSOSCAuto] RK1, (LSB)MR18= 0x233e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2063 13:53:40.010929 CH1 RK1: MR19=606, MR18=233E
2064 13:53:40.016807 CH1_RK1: MR19=0x606, MR18=0x233E, DQSOSC=394, MR23=63, INC=95, DEC=63
2065 13:53:40.020154 [RxdqsGatingPostProcess] freq 800
2066 13:53:40.026346 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2067 13:53:40.029978 Pre-setting of DQS Precalculation
2068 13:53:40.033190 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2069 13:53:40.039741 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2070 13:53:40.050044 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2071 13:53:40.050174
2072 13:53:40.050243
2073 13:53:40.053462 [Calibration Summary] 1600 Mbps
2074 13:53:40.053567 CH 0, Rank 0
2075 13:53:40.056791 SW Impedance : PASS
2076 13:53:40.056877 DUTY Scan : NO K
2077 13:53:40.059681 ZQ Calibration : PASS
2078 13:53:40.063385 Jitter Meter : NO K
2079 13:53:40.063493 CBT Training : PASS
2080 13:53:40.066296 Write leveling : PASS
2081 13:53:40.066381 RX DQS gating : PASS
2082 13:53:40.069896 RX DQ/DQS(RDDQC) : PASS
2083 13:53:40.072940 TX DQ/DQS : PASS
2084 13:53:40.073033 RX DATLAT : PASS
2085 13:53:40.076627 RX DQ/DQS(Engine): PASS
2086 13:53:40.079944 TX OE : NO K
2087 13:53:40.080041 All Pass.
2088 13:53:40.080107
2089 13:53:40.080168 CH 0, Rank 1
2090 13:53:40.082958 SW Impedance : PASS
2091 13:53:40.086145 DUTY Scan : NO K
2092 13:53:40.086231 ZQ Calibration : PASS
2093 13:53:40.089625 Jitter Meter : NO K
2094 13:53:40.092621 CBT Training : PASS
2095 13:53:40.092710 Write leveling : PASS
2096 13:53:40.096566 RX DQS gating : PASS
2097 13:53:40.099109 RX DQ/DQS(RDDQC) : PASS
2098 13:53:40.099196 TX DQ/DQS : PASS
2099 13:53:40.102579 RX DATLAT : PASS
2100 13:53:40.105935 RX DQ/DQS(Engine): PASS
2101 13:53:40.106024 TX OE : NO K
2102 13:53:40.109422 All Pass.
2103 13:53:40.109511
2104 13:53:40.109577 CH 1, Rank 0
2105 13:53:40.112408 SW Impedance : PASS
2106 13:53:40.112511 DUTY Scan : NO K
2107 13:53:40.115976 ZQ Calibration : PASS
2108 13:53:40.119279 Jitter Meter : NO K
2109 13:53:40.119394 CBT Training : PASS
2110 13:53:40.122458 Write leveling : PASS
2111 13:53:40.125829 RX DQS gating : PASS
2112 13:53:40.125923 RX DQ/DQS(RDDQC) : PASS
2113 13:53:40.129127 TX DQ/DQS : PASS
2114 13:53:40.129213 RX DATLAT : PASS
2115 13:53:40.132523 RX DQ/DQS(Engine): PASS
2116 13:53:40.136184 TX OE : NO K
2117 13:53:40.136280 All Pass.
2118 13:53:40.136347
2119 13:53:40.136409 CH 1, Rank 1
2120 13:53:40.139337 SW Impedance : PASS
2121 13:53:40.142352 DUTY Scan : NO K
2122 13:53:40.142467 ZQ Calibration : PASS
2123 13:53:40.145902 Jitter Meter : NO K
2124 13:53:40.149342 CBT Training : PASS
2125 13:53:40.149430 Write leveling : PASS
2126 13:53:40.152368 RX DQS gating : PASS
2127 13:53:40.155872 RX DQ/DQS(RDDQC) : PASS
2128 13:53:40.155959 TX DQ/DQS : PASS
2129 13:53:40.159535 RX DATLAT : PASS
2130 13:53:40.162518 RX DQ/DQS(Engine): PASS
2131 13:53:40.162605 TX OE : NO K
2132 13:53:40.165851 All Pass.
2133 13:53:40.165942
2134 13:53:40.166009 DramC Write-DBI off
2135 13:53:40.168989 PER_BANK_REFRESH: Hybrid Mode
2136 13:53:40.169074 TX_TRACKING: ON
2137 13:53:40.172733 [GetDramInforAfterCalByMRR] Vendor 6.
2138 13:53:40.178885 [GetDramInforAfterCalByMRR] Revision 606.
2139 13:53:40.182473 [GetDramInforAfterCalByMRR] Revision 2 0.
2140 13:53:40.182571 MR0 0x3b3b
2141 13:53:40.182639 MR8 0x5151
2142 13:53:40.185677 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2143 13:53:40.185764
2144 13:53:40.188809 MR0 0x3b3b
2145 13:53:40.188895 MR8 0x5151
2146 13:53:40.192235 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2147 13:53:40.192321
2148 13:53:40.202325 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2149 13:53:40.205358 [FAST_K] Save calibration result to emmc
2150 13:53:40.208823 [FAST_K] Save calibration result to emmc
2151 13:53:40.212002 dram_init: config_dvfs: 1
2152 13:53:40.215543 dramc_set_vcore_voltage set vcore to 662500
2153 13:53:40.219087 Read voltage for 1200, 2
2154 13:53:40.219185 Vio18 = 0
2155 13:53:40.219250 Vcore = 662500
2156 13:53:40.222448 Vdram = 0
2157 13:53:40.222532 Vddq = 0
2158 13:53:40.222598 Vmddr = 0
2159 13:53:40.228541 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2160 13:53:40.231938 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2161 13:53:40.235119 MEM_TYPE=3, freq_sel=15
2162 13:53:40.238464 sv_algorithm_assistance_LP4_1600
2163 13:53:40.241814 ============ PULL DRAM RESETB DOWN ============
2164 13:53:40.245230 ========== PULL DRAM RESETB DOWN end =========
2165 13:53:40.251841 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2166 13:53:40.255469 ===================================
2167 13:53:40.258260 LPDDR4 DRAM CONFIGURATION
2168 13:53:40.261623 ===================================
2169 13:53:40.261717 EX_ROW_EN[0] = 0x0
2170 13:53:40.265336 EX_ROW_EN[1] = 0x0
2171 13:53:40.265426 LP4Y_EN = 0x0
2172 13:53:40.268255 WORK_FSP = 0x0
2173 13:53:40.268339 WL = 0x4
2174 13:53:40.271743 RL = 0x4
2175 13:53:40.271830 BL = 0x2
2176 13:53:40.274585 RPST = 0x0
2177 13:53:40.274695 RD_PRE = 0x0
2178 13:53:40.278458 WR_PRE = 0x1
2179 13:53:40.278547 WR_PST = 0x0
2180 13:53:40.281745 DBI_WR = 0x0
2181 13:53:40.281830 DBI_RD = 0x0
2182 13:53:40.285223 OTF = 0x1
2183 13:53:40.288395 ===================================
2184 13:53:40.291582 ===================================
2185 13:53:40.291678 ANA top config
2186 13:53:40.294542 ===================================
2187 13:53:40.298126 DLL_ASYNC_EN = 0
2188 13:53:40.301233 ALL_SLAVE_EN = 0
2189 13:53:40.304681 NEW_RANK_MODE = 1
2190 13:53:40.304773 DLL_IDLE_MODE = 1
2191 13:53:40.307942 LP45_APHY_COMB_EN = 1
2192 13:53:40.311207 TX_ODT_DIS = 1
2193 13:53:40.315212 NEW_8X_MODE = 1
2194 13:53:40.318338 ===================================
2195 13:53:40.321659 ===================================
2196 13:53:40.324575 data_rate = 2400
2197 13:53:40.328465 CKR = 1
2198 13:53:40.328561 DQ_P2S_RATIO = 8
2199 13:53:40.331492 ===================================
2200 13:53:40.334575 CA_P2S_RATIO = 8
2201 13:53:40.338169 DQ_CA_OPEN = 0
2202 13:53:40.341966 DQ_SEMI_OPEN = 0
2203 13:53:40.344903 CA_SEMI_OPEN = 0
2204 13:53:40.344981 CA_FULL_RATE = 0
2205 13:53:40.347850 DQ_CKDIV4_EN = 0
2206 13:53:40.351272 CA_CKDIV4_EN = 0
2207 13:53:40.354450 CA_PREDIV_EN = 0
2208 13:53:40.357915 PH8_DLY = 17
2209 13:53:40.361592 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2210 13:53:40.361672 DQ_AAMCK_DIV = 4
2211 13:53:40.365164 CA_AAMCK_DIV = 4
2212 13:53:40.367630 CA_ADMCK_DIV = 4
2213 13:53:40.371002 DQ_TRACK_CA_EN = 0
2214 13:53:40.374571 CA_PICK = 1200
2215 13:53:40.378213 CA_MCKIO = 1200
2216 13:53:40.380986 MCKIO_SEMI = 0
2217 13:53:40.381101 PLL_FREQ = 2366
2218 13:53:40.384757 DQ_UI_PI_RATIO = 32
2219 13:53:40.387794 CA_UI_PI_RATIO = 0
2220 13:53:40.391058 ===================================
2221 13:53:40.394466 ===================================
2222 13:53:40.397570 memory_type:LPDDR4
2223 13:53:40.401635 GP_NUM : 10
2224 13:53:40.401755 SRAM_EN : 1
2225 13:53:40.404274 MD32_EN : 0
2226 13:53:40.407844 ===================================
2227 13:53:40.407951 [ANA_INIT] >>>>>>>>>>>>>>
2228 13:53:40.410949 <<<<<< [CONFIGURE PHASE]: ANA_TX
2229 13:53:40.414238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2230 13:53:40.417682 ===================================
2231 13:53:40.420915 data_rate = 2400,PCW = 0X5b00
2232 13:53:40.424867 ===================================
2233 13:53:40.427600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2234 13:53:40.434574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2235 13:53:40.437458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2236 13:53:40.444187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2237 13:53:40.447788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2238 13:53:40.451345 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2239 13:53:40.454286 [ANA_INIT] flow start
2240 13:53:40.454390 [ANA_INIT] PLL >>>>>>>>
2241 13:53:40.457522 [ANA_INIT] PLL <<<<<<<<
2242 13:53:40.460879 [ANA_INIT] MIDPI >>>>>>>>
2243 13:53:40.460980 [ANA_INIT] MIDPI <<<<<<<<
2244 13:53:40.463906 [ANA_INIT] DLL >>>>>>>>
2245 13:53:40.467559 [ANA_INIT] DLL <<<<<<<<
2246 13:53:40.467672 [ANA_INIT] flow end
2247 13:53:40.473919 ============ LP4 DIFF to SE enter ============
2248 13:53:40.477231 ============ LP4 DIFF to SE exit ============
2249 13:53:40.480588 [ANA_INIT] <<<<<<<<<<<<<
2250 13:53:40.483696 [Flow] Enable top DCM control >>>>>
2251 13:53:40.487305 [Flow] Enable top DCM control <<<<<
2252 13:53:40.487468 Enable DLL master slave shuffle
2253 13:53:40.493888 ==============================================================
2254 13:53:40.497201 Gating Mode config
2255 13:53:40.500643 ==============================================================
2256 13:53:40.503546 Config description:
2257 13:53:40.513482 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2258 13:53:40.519961 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2259 13:53:40.523874 SELPH_MODE 0: By rank 1: By Phase
2260 13:53:40.529736 ==============================================================
2261 13:53:40.533542 GAT_TRACK_EN = 1
2262 13:53:40.536625 RX_GATING_MODE = 2
2263 13:53:40.539606 RX_GATING_TRACK_MODE = 2
2264 13:53:40.543622 SELPH_MODE = 1
2265 13:53:40.546595 PICG_EARLY_EN = 1
2266 13:53:40.546680 VALID_LAT_VALUE = 1
2267 13:53:40.553357 ==============================================================
2268 13:53:40.556664 Enter into Gating configuration >>>>
2269 13:53:40.560003 Exit from Gating configuration <<<<
2270 13:53:40.562959 Enter into DVFS_PRE_config >>>>>
2271 13:53:40.573132 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2272 13:53:40.576607 Exit from DVFS_PRE_config <<<<<
2273 13:53:40.579813 Enter into PICG configuration >>>>
2274 13:53:40.582934 Exit from PICG configuration <<<<
2275 13:53:40.586152 [RX_INPUT] configuration >>>>>
2276 13:53:40.589493 [RX_INPUT] configuration <<<<<
2277 13:53:40.592993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2278 13:53:40.600034 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2279 13:53:40.606217 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 13:53:40.612853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 13:53:40.619892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2282 13:53:40.626095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2283 13:53:40.629277 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2284 13:53:40.632636 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2285 13:53:40.635858 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2286 13:53:40.642472 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2287 13:53:40.646075 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2288 13:53:40.649242 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 13:53:40.652957 ===================================
2290 13:53:40.655933 LPDDR4 DRAM CONFIGURATION
2291 13:53:40.659163 ===================================
2292 13:53:40.659274 EX_ROW_EN[0] = 0x0
2293 13:53:40.662370 EX_ROW_EN[1] = 0x0
2294 13:53:40.662474 LP4Y_EN = 0x0
2295 13:53:40.665666 WORK_FSP = 0x0
2296 13:53:40.668935 WL = 0x4
2297 13:53:40.669045 RL = 0x4
2298 13:53:40.672414 BL = 0x2
2299 13:53:40.672553 RPST = 0x0
2300 13:53:40.676042 RD_PRE = 0x0
2301 13:53:40.676165 WR_PRE = 0x1
2302 13:53:40.679553 WR_PST = 0x0
2303 13:53:40.679666 DBI_WR = 0x0
2304 13:53:40.682264 DBI_RD = 0x0
2305 13:53:40.682371 OTF = 0x1
2306 13:53:40.685897 ===================================
2307 13:53:40.689240 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2308 13:53:40.695792 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2309 13:53:40.698861 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 13:53:40.702170 ===================================
2311 13:53:40.705377 LPDDR4 DRAM CONFIGURATION
2312 13:53:40.708990 ===================================
2313 13:53:40.709112 EX_ROW_EN[0] = 0x10
2314 13:53:40.712087 EX_ROW_EN[1] = 0x0
2315 13:53:40.712181 LP4Y_EN = 0x0
2316 13:53:40.715460 WORK_FSP = 0x0
2317 13:53:40.718630 WL = 0x4
2318 13:53:40.718709 RL = 0x4
2319 13:53:40.721782 BL = 0x2
2320 13:53:40.721881 RPST = 0x0
2321 13:53:40.725655 RD_PRE = 0x0
2322 13:53:40.725743 WR_PRE = 0x1
2323 13:53:40.728706 WR_PST = 0x0
2324 13:53:40.728778 DBI_WR = 0x0
2325 13:53:40.731973 DBI_RD = 0x0
2326 13:53:40.732059 OTF = 0x1
2327 13:53:40.735324 ===================================
2328 13:53:40.741925 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2329 13:53:40.742067 ==
2330 13:53:40.744948 Dram Type= 6, Freq= 0, CH_0, rank 0
2331 13:53:40.748302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2332 13:53:40.751501 ==
2333 13:53:40.751582 [Duty_Offset_Calibration]
2334 13:53:40.754906 B0:2 B1:0 CA:4
2335 13:53:40.755004
2336 13:53:40.758372 [DutyScan_Calibration_Flow] k_type=0
2337 13:53:40.767049
2338 13:53:40.767191 ==CLK 0==
2339 13:53:40.770065 Final CLK duty delay cell = 0
2340 13:53:40.773195 [0] MAX Duty = 5156%(X100), DQS PI = 14
2341 13:53:40.776444 [0] MIN Duty = 5000%(X100), DQS PI = 8
2342 13:53:40.776526 [0] AVG Duty = 5078%(X100)
2343 13:53:40.779783
2344 13:53:40.783528 CH0 CLK Duty spec in!! Max-Min= 156%
2345 13:53:40.786685 [DutyScan_Calibration_Flow] ====Done====
2346 13:53:40.786767
2347 13:53:40.789574 [DutyScan_Calibration_Flow] k_type=1
2348 13:53:40.805928
2349 13:53:40.806060 ==DQS 0 ==
2350 13:53:40.809048 Final DQS duty delay cell = 0
2351 13:53:40.812756 [0] MAX Duty = 5156%(X100), DQS PI = 16
2352 13:53:40.816571 [0] MIN Duty = 5093%(X100), DQS PI = 2
2353 13:53:40.816653 [0] AVG Duty = 5124%(X100)
2354 13:53:40.819243
2355 13:53:40.819342 ==DQS 1 ==
2356 13:53:40.822770 Final DQS duty delay cell = 0
2357 13:53:40.826145 [0] MAX Duty = 5125%(X100), DQS PI = 48
2358 13:53:40.829024 [0] MIN Duty = 5000%(X100), DQS PI = 0
2359 13:53:40.829114 [0] AVG Duty = 5062%(X100)
2360 13:53:40.832591
2361 13:53:40.835930 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2362 13:53:40.836012
2363 13:53:40.839382 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2364 13:53:40.842284 [DutyScan_Calibration_Flow] ====Done====
2365 13:53:40.842389
2366 13:53:40.845820 [DutyScan_Calibration_Flow] k_type=3
2367 13:53:40.862677
2368 13:53:40.862815 ==DQM 0 ==
2369 13:53:40.865537 Final DQM duty delay cell = 0
2370 13:53:40.868679 [0] MAX Duty = 5094%(X100), DQS PI = 20
2371 13:53:40.872371 [0] MIN Duty = 4844%(X100), DQS PI = 54
2372 13:53:40.875330 [0] AVG Duty = 4969%(X100)
2373 13:53:40.875463
2374 13:53:40.875527 ==DQM 1 ==
2375 13:53:40.878794 Final DQM duty delay cell = 0
2376 13:53:40.881983 [0] MAX Duty = 5000%(X100), DQS PI = 6
2377 13:53:40.885379 [0] MIN Duty = 4875%(X100), DQS PI = 20
2378 13:53:40.888511 [0] AVG Duty = 4937%(X100)
2379 13:53:40.888593
2380 13:53:40.892187 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2381 13:53:40.892266
2382 13:53:40.895280 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2383 13:53:40.898874 [DutyScan_Calibration_Flow] ====Done====
2384 13:53:40.898951
2385 13:53:40.902609 [DutyScan_Calibration_Flow] k_type=2
2386 13:53:40.918537
2387 13:53:40.918666 ==DQ 0 ==
2388 13:53:40.922054 Final DQ duty delay cell = 0
2389 13:53:40.925250 [0] MAX Duty = 5156%(X100), DQS PI = 20
2390 13:53:40.928772 [0] MIN Duty = 5000%(X100), DQS PI = 8
2391 13:53:40.928857 [0] AVG Duty = 5078%(X100)
2392 13:53:40.931783
2393 13:53:40.931858 ==DQ 1 ==
2394 13:53:40.935184 Final DQ duty delay cell = 0
2395 13:53:40.938549 [0] MAX Duty = 5125%(X100), DQS PI = 6
2396 13:53:40.941538 [0] MIN Duty = 4938%(X100), DQS PI = 16
2397 13:53:40.941644 [0] AVG Duty = 5031%(X100)
2398 13:53:40.941732
2399 13:53:40.944927 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2400 13:53:40.948365
2401 13:53:40.951781 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2402 13:53:40.955171 [DutyScan_Calibration_Flow] ====Done====
2403 13:53:40.955276 ==
2404 13:53:40.958683 Dram Type= 6, Freq= 0, CH_1, rank 0
2405 13:53:40.961474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2406 13:53:40.961553 ==
2407 13:53:40.965304 [Duty_Offset_Calibration]
2408 13:53:40.965382 B0:0 B1:-1 CA:3
2409 13:53:40.965446
2410 13:53:40.968298 [DutyScan_Calibration_Flow] k_type=0
2411 13:53:40.977960
2412 13:53:40.978086 ==CLK 0==
2413 13:53:40.981147 Final CLK duty delay cell = -4
2414 13:53:40.984455 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2415 13:53:40.987634 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2416 13:53:40.991020 [-4] AVG Duty = 4938%(X100)
2417 13:53:40.991104
2418 13:53:40.994670 CH1 CLK Duty spec in!! Max-Min= 124%
2419 13:53:40.997651 [DutyScan_Calibration_Flow] ====Done====
2420 13:53:40.997729
2421 13:53:41.001816 [DutyScan_Calibration_Flow] k_type=1
2422 13:53:41.017554
2423 13:53:41.017687 ==DQS 0 ==
2424 13:53:41.021039 Final DQS duty delay cell = 0
2425 13:53:41.024047 [0] MAX Duty = 5187%(X100), DQS PI = 30
2426 13:53:41.027577 [0] MIN Duty = 4907%(X100), DQS PI = 38
2427 13:53:41.031091 [0] AVG Duty = 5047%(X100)
2428 13:53:41.031201
2429 13:53:41.031291 ==DQS 1 ==
2430 13:53:41.034576 Final DQS duty delay cell = 0
2431 13:53:41.037423 [0] MAX Duty = 5156%(X100), DQS PI = 8
2432 13:53:41.040982 [0] MIN Duty = 5031%(X100), DQS PI = 18
2433 13:53:41.044300 [0] AVG Duty = 5093%(X100)
2434 13:53:41.044382
2435 13:53:41.047610 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2436 13:53:41.047683
2437 13:53:41.050800 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2438 13:53:41.053867 [DutyScan_Calibration_Flow] ====Done====
2439 13:53:41.053943
2440 13:53:41.057269 [DutyScan_Calibration_Flow] k_type=3
2441 13:53:41.074152
2442 13:53:41.074285 ==DQM 0 ==
2443 13:53:41.077594 Final DQM duty delay cell = 0
2444 13:53:41.080638 [0] MAX Duty = 5031%(X100), DQS PI = 28
2445 13:53:41.083999 [0] MIN Duty = 4813%(X100), DQS PI = 38
2446 13:53:41.087634 [0] AVG Duty = 4922%(X100)
2447 13:53:41.087719
2448 13:53:41.087782 ==DQM 1 ==
2449 13:53:41.090514 Final DQM duty delay cell = 0
2450 13:53:41.093656 [0] MAX Duty = 4969%(X100), DQS PI = 32
2451 13:53:41.096952 [0] MIN Duty = 4813%(X100), DQS PI = 0
2452 13:53:41.100264 [0] AVG Duty = 4891%(X100)
2453 13:53:41.100346
2454 13:53:41.104009 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2455 13:53:41.104083
2456 13:53:41.106920 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2457 13:53:41.110113 [DutyScan_Calibration_Flow] ====Done====
2458 13:53:41.110185
2459 13:53:41.113691 [DutyScan_Calibration_Flow] k_type=2
2460 13:53:41.129627
2461 13:53:41.129711 ==DQ 0 ==
2462 13:53:41.133011 Final DQ duty delay cell = -4
2463 13:53:41.136125 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2464 13:53:41.139846 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2465 13:53:41.143210 [-4] AVG Duty = 4937%(X100)
2466 13:53:41.143323
2467 13:53:41.143424 ==DQ 1 ==
2468 13:53:41.146209 Final DQ duty delay cell = 0
2469 13:53:41.149547 [0] MAX Duty = 5031%(X100), DQS PI = 32
2470 13:53:41.153332 [0] MIN Duty = 4844%(X100), DQS PI = 62
2471 13:53:41.155985 [0] AVG Duty = 4937%(X100)
2472 13:53:41.156054
2473 13:53:41.159905 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2474 13:53:41.159975
2475 13:53:41.162656 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2476 13:53:41.166176 [DutyScan_Calibration_Flow] ====Done====
2477 13:53:41.169508 nWR fixed to 30
2478 13:53:41.172851 [ModeRegInit_LP4] CH0 RK0
2479 13:53:41.172931 [ModeRegInit_LP4] CH0 RK1
2480 13:53:41.175935 [ModeRegInit_LP4] CH1 RK0
2481 13:53:41.179864 [ModeRegInit_LP4] CH1 RK1
2482 13:53:41.179962 match AC timing 7
2483 13:53:41.186224 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2484 13:53:41.189601 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2485 13:53:41.192896 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2486 13:53:41.199614 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2487 13:53:41.202791 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2488 13:53:41.202893 ==
2489 13:53:41.205790 Dram Type= 6, Freq= 0, CH_0, rank 0
2490 13:53:41.209502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 13:53:41.209606 ==
2492 13:53:41.216107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 13:53:41.222608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2494 13:53:41.230010 [CA 0] Center 39 (9~70) winsize 62
2495 13:53:41.233517 [CA 1] Center 39 (9~70) winsize 62
2496 13:53:41.236455 [CA 2] Center 35 (5~66) winsize 62
2497 13:53:41.239544 [CA 3] Center 35 (5~66) winsize 62
2498 13:53:41.243177 [CA 4] Center 33 (3~64) winsize 62
2499 13:53:41.247003 [CA 5] Center 33 (3~63) winsize 61
2500 13:53:41.247101
2501 13:53:41.249831 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2502 13:53:41.249929
2503 13:53:41.253015 [CATrainingPosCal] consider 1 rank data
2504 13:53:41.256508 u2DelayCellTimex100 = 270/100 ps
2505 13:53:41.259857 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2506 13:53:41.263454 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2507 13:53:41.270282 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2508 13:53:41.273212 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2509 13:53:41.276480 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2510 13:53:41.279872 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2511 13:53:41.279973
2512 13:53:41.283041 CA PerBit enable=1, Macro0, CA PI delay=33
2513 13:53:41.283144
2514 13:53:41.286906 [CBTSetCACLKResult] CA Dly = 33
2515 13:53:41.287010 CS Dly: 7 (0~38)
2516 13:53:41.287105 ==
2517 13:53:41.290446 Dram Type= 6, Freq= 0, CH_0, rank 1
2518 13:53:41.296392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 13:53:41.296494 ==
2520 13:53:41.299890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2521 13:53:41.306700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2522 13:53:41.315634 [CA 0] Center 39 (9~70) winsize 62
2523 13:53:41.319358 [CA 1] Center 39 (9~70) winsize 62
2524 13:53:41.322296 [CA 2] Center 35 (5~66) winsize 62
2525 13:53:41.325577 [CA 3] Center 35 (4~66) winsize 63
2526 13:53:41.329127 [CA 4] Center 34 (4~65) winsize 62
2527 13:53:41.332284 [CA 5] Center 33 (3~64) winsize 62
2528 13:53:41.332385
2529 13:53:41.335394 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2530 13:53:41.335507
2531 13:53:41.338952 [CATrainingPosCal] consider 2 rank data
2532 13:53:41.342349 u2DelayCellTimex100 = 270/100 ps
2533 13:53:41.345567 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2534 13:53:41.352641 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2535 13:53:41.355234 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 13:53:41.358775 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2537 13:53:41.361922 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2538 13:53:41.365471 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2539 13:53:41.365573
2540 13:53:41.368963 CA PerBit enable=1, Macro0, CA PI delay=33
2541 13:53:41.369062
2542 13:53:41.371820 [CBTSetCACLKResult] CA Dly = 33
2543 13:53:41.371900 CS Dly: 8 (0~41)
2544 13:53:41.375224
2545 13:53:41.378938 ----->DramcWriteLeveling(PI) begin...
2546 13:53:41.379040 ==
2547 13:53:41.381752 Dram Type= 6, Freq= 0, CH_0, rank 0
2548 13:53:41.385131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2549 13:53:41.385242 ==
2550 13:53:41.388401 Write leveling (Byte 0): 30 => 30
2551 13:53:41.392062 Write leveling (Byte 1): 27 => 27
2552 13:53:41.395004 DramcWriteLeveling(PI) end<-----
2553 13:53:41.395089
2554 13:53:41.395154 ==
2555 13:53:41.398683 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 13:53:41.402000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 13:53:41.402101 ==
2558 13:53:41.405003 [Gating] SW mode calibration
2559 13:53:41.411704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2560 13:53:41.418514 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2561 13:53:41.421406 0 15 0 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
2562 13:53:41.425264 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2563 13:53:41.431156 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 13:53:41.434511 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 13:53:41.437669 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 13:53:41.444598 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 13:53:41.448185 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2568 13:53:41.451027 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2569 13:53:41.458094 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
2570 13:53:41.461641 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 13:53:41.464791 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 13:53:41.471583 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 13:53:41.474517 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 13:53:41.477913 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 13:53:41.484781 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2576 13:53:41.487825 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2577 13:53:41.491204 1 1 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2578 13:53:41.497555 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 13:53:41.500753 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 13:53:41.504979 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 13:53:41.510608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 13:53:41.514128 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 13:53:41.517533 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 13:53:41.523939 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2585 13:53:41.527581 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2586 13:53:41.530521 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2587 13:53:41.537045 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 13:53:41.540934 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 13:53:41.543865 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 13:53:41.550597 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 13:53:41.554128 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 13:53:41.557269 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 13:53:41.560444 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 13:53:41.567293 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 13:53:41.570636 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 13:53:41.573677 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 13:53:41.580302 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 13:53:41.583848 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 13:53:41.586950 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2600 13:53:41.593663 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2601 13:53:41.596953 Total UI for P1: 0, mck2ui 16
2602 13:53:41.600553 best dqsien dly found for B0: ( 1, 3, 24)
2603 13:53:41.603693 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2604 13:53:41.607139 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2605 13:53:41.613547 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 13:53:41.613620 Total UI for P1: 0, mck2ui 16
2607 13:53:41.620180 best dqsien dly found for B1: ( 1, 4, 2)
2608 13:53:41.623588 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2609 13:53:41.626824 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2610 13:53:41.626931
2611 13:53:41.630555 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2612 13:53:41.633688 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2613 13:53:41.636836 [Gating] SW calibration Done
2614 13:53:41.636912 ==
2615 13:53:41.640588 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 13:53:41.644067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 13:53:41.644140 ==
2618 13:53:41.646537 RX Vref Scan: 0
2619 13:53:41.646606
2620 13:53:41.646666 RX Vref 0 -> 0, step: 1
2621 13:53:41.646769
2622 13:53:41.650211 RX Delay -40 -> 252, step: 8
2623 13:53:41.653429 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2624 13:53:41.660266 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2625 13:53:41.663490 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2626 13:53:41.666826 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2627 13:53:41.670163 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2628 13:53:41.673635 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2629 13:53:41.680449 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2630 13:53:41.683283 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2631 13:53:41.687165 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2632 13:53:41.690530 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2633 13:53:41.693161 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2634 13:53:41.699830 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2635 13:53:41.703586 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
2636 13:53:41.706577 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2637 13:53:41.709863 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2638 13:53:41.713255 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2639 13:53:41.716831 ==
2640 13:53:41.716929 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 13:53:41.723481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 13:53:41.723585 ==
2643 13:53:41.723684 DQS Delay:
2644 13:53:41.726482 DQS0 = 0, DQS1 = 0
2645 13:53:41.726562 DQM Delay:
2646 13:53:41.729700 DQM0 = 120, DQM1 = 107
2647 13:53:41.729786 DQ Delay:
2648 13:53:41.733232 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2649 13:53:41.736210 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2650 13:53:41.740139 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2651 13:53:41.743524 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111
2652 13:53:41.743612
2653 13:53:41.743677
2654 13:53:41.743735 ==
2655 13:53:41.746288 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 13:53:41.752914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 13:53:41.753019 ==
2658 13:53:41.753109
2659 13:53:41.753203
2660 13:53:41.753289 TX Vref Scan disable
2661 13:53:41.756264 == TX Byte 0 ==
2662 13:53:41.760053 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2663 13:53:41.766213 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2664 13:53:41.766294 == TX Byte 1 ==
2665 13:53:41.769900 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2666 13:53:41.773251 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2667 13:53:41.776313 ==
2668 13:53:41.779852 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 13:53:41.783168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 13:53:41.783279 ==
2671 13:53:41.794530 TX Vref=22, minBit 0, minWin=25, winSum=408
2672 13:53:41.797789 TX Vref=24, minBit 1, minWin=25, winSum=415
2673 13:53:41.801305 TX Vref=26, minBit 5, minWin=25, winSum=417
2674 13:53:41.804308 TX Vref=28, minBit 1, minWin=25, winSum=424
2675 13:53:41.807828 TX Vref=30, minBit 0, minWin=26, winSum=429
2676 13:53:41.811090 TX Vref=32, minBit 0, minWin=26, winSum=427
2677 13:53:41.817463 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
2678 13:53:41.817573
2679 13:53:41.821057 Final TX Range 1 Vref 30
2680 13:53:41.821161
2681 13:53:41.821261 ==
2682 13:53:41.824471 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 13:53:41.828039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 13:53:41.828146 ==
2685 13:53:41.830985
2686 13:53:41.831084
2687 13:53:41.831182 TX Vref Scan disable
2688 13:53:41.834086 == TX Byte 0 ==
2689 13:53:41.837513 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2690 13:53:41.840781 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2691 13:53:41.844725 == TX Byte 1 ==
2692 13:53:41.847330 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2693 13:53:41.850675 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2694 13:53:41.854299
2695 13:53:41.854409 [DATLAT]
2696 13:53:41.854509 Freq=1200, CH0 RK0
2697 13:53:41.854608
2698 13:53:41.857975 DATLAT Default: 0xd
2699 13:53:41.858083 0, 0xFFFF, sum = 0
2700 13:53:41.861107 1, 0xFFFF, sum = 0
2701 13:53:41.861209 2, 0xFFFF, sum = 0
2702 13:53:41.863811 3, 0xFFFF, sum = 0
2703 13:53:41.867649 4, 0xFFFF, sum = 0
2704 13:53:41.867734 5, 0xFFFF, sum = 0
2705 13:53:41.870447 6, 0xFFFF, sum = 0
2706 13:53:41.870530 7, 0xFFFF, sum = 0
2707 13:53:41.873873 8, 0xFFFF, sum = 0
2708 13:53:41.873959 9, 0xFFFF, sum = 0
2709 13:53:41.877345 10, 0xFFFF, sum = 0
2710 13:53:41.877429 11, 0xFFFF, sum = 0
2711 13:53:41.880945 12, 0x0, sum = 1
2712 13:53:41.881024 13, 0x0, sum = 2
2713 13:53:41.883813 14, 0x0, sum = 3
2714 13:53:41.883923 15, 0x0, sum = 4
2715 13:53:41.887150 best_step = 13
2716 13:53:41.887222
2717 13:53:41.887282 ==
2718 13:53:41.890372 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 13:53:41.893841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 13:53:41.893922 ==
2721 13:53:41.893986 RX Vref Scan: 1
2722 13:53:41.896859
2723 13:53:41.896977 Set Vref Range= 32 -> 127
2724 13:53:41.897078
2725 13:53:41.901364 RX Vref 32 -> 127, step: 1
2726 13:53:41.901469
2727 13:53:41.903712 RX Delay -21 -> 252, step: 4
2728 13:53:41.903802
2729 13:53:41.906770 Set Vref, RX VrefLevel [Byte0]: 32
2730 13:53:41.910595 [Byte1]: 32
2731 13:53:41.910701
2732 13:53:41.913590 Set Vref, RX VrefLevel [Byte0]: 33
2733 13:53:41.916726 [Byte1]: 33
2734 13:53:41.920651
2735 13:53:41.920753 Set Vref, RX VrefLevel [Byte0]: 34
2736 13:53:41.923956 [Byte1]: 34
2737 13:53:41.928851
2738 13:53:41.928965 Set Vref, RX VrefLevel [Byte0]: 35
2739 13:53:41.932002 [Byte1]: 35
2740 13:53:41.936345
2741 13:53:41.936457 Set Vref, RX VrefLevel [Byte0]: 36
2742 13:53:41.939762 [Byte1]: 36
2743 13:53:41.944294
2744 13:53:41.944403 Set Vref, RX VrefLevel [Byte0]: 37
2745 13:53:41.947852 [Byte1]: 37
2746 13:53:41.952415
2747 13:53:41.952532 Set Vref, RX VrefLevel [Byte0]: 38
2748 13:53:41.955517 [Byte1]: 38
2749 13:53:41.960500
2750 13:53:41.960604 Set Vref, RX VrefLevel [Byte0]: 39
2751 13:53:41.963565 [Byte1]: 39
2752 13:53:41.967981
2753 13:53:41.968070 Set Vref, RX VrefLevel [Byte0]: 40
2754 13:53:41.971418 [Byte1]: 40
2755 13:53:41.975894
2756 13:53:41.975979 Set Vref, RX VrefLevel [Byte0]: 41
2757 13:53:41.979321 [Byte1]: 41
2758 13:53:41.983902
2759 13:53:41.984015 Set Vref, RX VrefLevel [Byte0]: 42
2760 13:53:41.987595 [Byte1]: 42
2761 13:53:41.992397
2762 13:53:41.992498 Set Vref, RX VrefLevel [Byte0]: 43
2763 13:53:41.995439 [Byte1]: 43
2764 13:53:41.999793
2765 13:53:41.999917 Set Vref, RX VrefLevel [Byte0]: 44
2766 13:53:42.003136 [Byte1]: 44
2767 13:53:42.007544
2768 13:53:42.007667 Set Vref, RX VrefLevel [Byte0]: 45
2769 13:53:42.011105 [Byte1]: 45
2770 13:53:42.015776
2771 13:53:42.015881 Set Vref, RX VrefLevel [Byte0]: 46
2772 13:53:42.018818 [Byte1]: 46
2773 13:53:42.024605
2774 13:53:42.024711 Set Vref, RX VrefLevel [Byte0]: 47
2775 13:53:42.026808 [Byte1]: 47
2776 13:53:42.031560
2777 13:53:42.031675 Set Vref, RX VrefLevel [Byte0]: 48
2778 13:53:42.034742 [Byte1]: 48
2779 13:53:42.039250
2780 13:53:42.039422 Set Vref, RX VrefLevel [Byte0]: 49
2781 13:53:42.042650 [Byte1]: 49
2782 13:53:42.047388
2783 13:53:42.047517 Set Vref, RX VrefLevel [Byte0]: 50
2784 13:53:42.050677 [Byte1]: 50
2785 13:53:42.055510
2786 13:53:42.055618 Set Vref, RX VrefLevel [Byte0]: 51
2787 13:53:42.058712 [Byte1]: 51
2788 13:53:42.063317
2789 13:53:42.063470 Set Vref, RX VrefLevel [Byte0]: 52
2790 13:53:42.066692 [Byte1]: 52
2791 13:53:42.071188
2792 13:53:42.071312 Set Vref, RX VrefLevel [Byte0]: 53
2793 13:53:42.074506 [Byte1]: 53
2794 13:53:42.079834
2795 13:53:42.079939 Set Vref, RX VrefLevel [Byte0]: 54
2796 13:53:42.082513 [Byte1]: 54
2797 13:53:42.087487
2798 13:53:42.087571 Set Vref, RX VrefLevel [Byte0]: 55
2799 13:53:42.090261 [Byte1]: 55
2800 13:53:42.095303
2801 13:53:42.095424 Set Vref, RX VrefLevel [Byte0]: 56
2802 13:53:42.098398 [Byte1]: 56
2803 13:53:42.103687
2804 13:53:42.103796 Set Vref, RX VrefLevel [Byte0]: 57
2805 13:53:42.106300 [Byte1]: 57
2806 13:53:42.110765
2807 13:53:42.110866 Set Vref, RX VrefLevel [Byte0]: 58
2808 13:53:42.114178 [Byte1]: 58
2809 13:53:42.118526
2810 13:53:42.118608 Set Vref, RX VrefLevel [Byte0]: 59
2811 13:53:42.122125 [Byte1]: 59
2812 13:53:42.126706
2813 13:53:42.126790 Set Vref, RX VrefLevel [Byte0]: 60
2814 13:53:42.130074 [Byte1]: 60
2815 13:53:42.134927
2816 13:53:42.135014 Set Vref, RX VrefLevel [Byte0]: 61
2817 13:53:42.137744 [Byte1]: 61
2818 13:53:42.142894
2819 13:53:42.142976 Set Vref, RX VrefLevel [Byte0]: 62
2820 13:53:42.145534 [Byte1]: 62
2821 13:53:42.150611
2822 13:53:42.150713 Set Vref, RX VrefLevel [Byte0]: 63
2823 13:53:42.153625 [Byte1]: 63
2824 13:53:42.158717
2825 13:53:42.158817 Set Vref, RX VrefLevel [Byte0]: 64
2826 13:53:42.161788 [Byte1]: 64
2827 13:53:42.166476
2828 13:53:42.166568 Set Vref, RX VrefLevel [Byte0]: 65
2829 13:53:42.169486 [Byte1]: 65
2830 13:53:42.174262
2831 13:53:42.174346 Set Vref, RX VrefLevel [Byte0]: 66
2832 13:53:42.177508 [Byte1]: 66
2833 13:53:42.182453
2834 13:53:42.182570 Set Vref, RX VrefLevel [Byte0]: 67
2835 13:53:42.185792 [Byte1]: 67
2836 13:53:42.190036
2837 13:53:42.190142 Set Vref, RX VrefLevel [Byte0]: 68
2838 13:53:42.193457 [Byte1]: 68
2839 13:53:42.198486
2840 13:53:42.198578 Set Vref, RX VrefLevel [Byte0]: 69
2841 13:53:42.201152 [Byte1]: 69
2842 13:53:42.206025
2843 13:53:42.206108 Final RX Vref Byte 0 = 57 to rank0
2844 13:53:42.209109 Final RX Vref Byte 1 = 50 to rank0
2845 13:53:42.212669 Final RX Vref Byte 0 = 57 to rank1
2846 13:53:42.215720 Final RX Vref Byte 1 = 50 to rank1==
2847 13:53:42.219340 Dram Type= 6, Freq= 0, CH_0, rank 0
2848 13:53:42.225667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 13:53:42.225771 ==
2850 13:53:42.225855 DQS Delay:
2851 13:53:42.229199 DQS0 = 0, DQS1 = 0
2852 13:53:42.229301 DQM Delay:
2853 13:53:42.229394 DQM0 = 119, DQM1 = 106
2854 13:53:42.232086 DQ Delay:
2855 13:53:42.235592 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2856 13:53:42.239205 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2857 13:53:42.242471 DQ8 =96, DQ9 =90, DQ10 =106, DQ11 =100
2858 13:53:42.245599 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =114
2859 13:53:42.245687
2860 13:53:42.245751
2861 13:53:42.256266 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2862 13:53:42.256362 CH0 RK0: MR19=403, MR18=4FF
2863 13:53:42.262439 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2864 13:53:42.262554
2865 13:53:42.265475 ----->DramcWriteLeveling(PI) begin...
2866 13:53:42.265572 ==
2867 13:53:42.269152 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 13:53:42.272277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 13:53:42.275764 ==
2870 13:53:42.275848 Write leveling (Byte 0): 31 => 31
2871 13:53:42.278608 Write leveling (Byte 1): 26 => 26
2872 13:53:42.282301 DramcWriteLeveling(PI) end<-----
2873 13:53:42.282383
2874 13:53:42.282460 ==
2875 13:53:42.285680 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 13:53:42.292245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 13:53:42.292338 ==
2878 13:53:42.292402 [Gating] SW mode calibration
2879 13:53:42.302114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2880 13:53:42.305423 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2881 13:53:42.312004 0 15 0 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
2882 13:53:42.315467 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2883 13:53:42.319177 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 13:53:42.322081 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 13:53:42.328917 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 13:53:42.331975 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 13:53:42.335717 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2888 13:53:42.341994 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
2889 13:53:42.345645 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2890 13:53:42.349075 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 13:53:42.355329 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 13:53:42.359292 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 13:53:42.362524 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 13:53:42.369050 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 13:53:42.371896 1 0 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2896 13:53:42.375467 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2897 13:53:42.381961 1 1 0 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
2898 13:53:42.385830 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 13:53:42.388871 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 13:53:42.395253 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 13:53:42.398494 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 13:53:42.401827 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 13:53:42.408770 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2904 13:53:42.412488 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2905 13:53:42.415483 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 13:53:42.421689 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 13:53:42.425375 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 13:53:42.428564 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 13:53:42.435248 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 13:53:42.438462 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 13:53:42.442039 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 13:53:42.445267 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 13:53:42.452141 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 13:53:42.455207 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 13:53:42.458178 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 13:53:42.465212 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 13:53:42.468232 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 13:53:42.471536 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2919 13:53:42.478888 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2920 13:53:42.481591 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2921 13:53:42.484832 Total UI for P1: 0, mck2ui 16
2922 13:53:42.488241 best dqsien dly found for B0: ( 1, 3, 22)
2923 13:53:42.492367 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 13:53:42.494802 Total UI for P1: 0, mck2ui 16
2925 13:53:42.498409 best dqsien dly found for B1: ( 1, 3, 28)
2926 13:53:42.501358 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2927 13:53:42.504784 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2928 13:53:42.504886
2929 13:53:42.511865 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2930 13:53:42.514691 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2931 13:53:42.518650 [Gating] SW calibration Done
2932 13:53:42.518754 ==
2933 13:53:42.521190 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 13:53:42.524443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 13:53:42.524548 ==
2936 13:53:42.524651 RX Vref Scan: 0
2937 13:53:42.524739
2938 13:53:42.527884 RX Vref 0 -> 0, step: 1
2939 13:53:42.527984
2940 13:53:42.531527 RX Delay -40 -> 252, step: 8
2941 13:53:42.534726 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2942 13:53:42.537977 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2943 13:53:42.544580 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2944 13:53:42.547722 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2945 13:53:42.550787 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2946 13:53:42.554478 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2947 13:53:42.557711 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2948 13:53:42.563952 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2949 13:53:42.567335 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2950 13:53:42.570987 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2951 13:53:42.574377 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2952 13:53:42.577298 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2953 13:53:42.584162 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2954 13:53:42.587790 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2955 13:53:42.591089 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2956 13:53:42.594214 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2957 13:53:42.594311 ==
2958 13:53:42.597870 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 13:53:42.604403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 13:53:42.604478 ==
2961 13:53:42.604545 DQS Delay:
2962 13:53:42.607250 DQS0 = 0, DQS1 = 0
2963 13:53:42.607340 DQM Delay:
2964 13:53:42.610308 DQM0 = 119, DQM1 = 106
2965 13:53:42.610412 DQ Delay:
2966 13:53:42.614204 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2967 13:53:42.617064 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2968 13:53:42.620232 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2969 13:53:42.623766 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2970 13:53:42.623850
2971 13:53:42.623943
2972 13:53:42.624030 ==
2973 13:53:42.626808 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 13:53:42.633860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 13:53:42.634047 ==
2976 13:53:42.634235
2977 13:53:42.634338
2978 13:53:42.634424 TX Vref Scan disable
2979 13:53:42.636783 == TX Byte 0 ==
2980 13:53:42.640793 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2981 13:53:42.646945 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2982 13:53:42.647021 == TX Byte 1 ==
2983 13:53:42.650383 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2984 13:53:42.653343 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2985 13:53:42.656986 ==
2986 13:53:42.660108 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 13:53:42.663508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 13:53:42.663607 ==
2989 13:53:42.675096 TX Vref=22, minBit 4, minWin=24, winSum=411
2990 13:53:42.678525 TX Vref=24, minBit 8, minWin=25, winSum=414
2991 13:53:42.682121 TX Vref=26, minBit 5, minWin=25, winSum=420
2992 13:53:42.684786 TX Vref=28, minBit 2, minWin=26, winSum=427
2993 13:53:42.688032 TX Vref=30, minBit 0, minWin=26, winSum=424
2994 13:53:42.694706 TX Vref=32, minBit 14, minWin=25, winSum=423
2995 13:53:42.698417 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 28
2996 13:53:42.698520
2997 13:53:42.701690 Final TX Range 1 Vref 28
2998 13:53:42.701773
2999 13:53:42.701843 ==
3000 13:53:42.704864 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 13:53:42.708335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 13:53:42.711270 ==
3003 13:53:42.711352
3004 13:53:42.711453
3005 13:53:42.711513 TX Vref Scan disable
3006 13:53:42.714635 == TX Byte 0 ==
3007 13:53:42.718161 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3008 13:53:42.721914 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3009 13:53:42.724920 == TX Byte 1 ==
3010 13:53:42.728280 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3011 13:53:42.734610 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3012 13:53:42.734716
3013 13:53:42.734784 [DATLAT]
3014 13:53:42.734845 Freq=1200, CH0 RK1
3015 13:53:42.734905
3016 13:53:42.738151 DATLAT Default: 0xd
3017 13:53:42.738224 0, 0xFFFF, sum = 0
3018 13:53:42.741704 1, 0xFFFF, sum = 0
3019 13:53:42.741783 2, 0xFFFF, sum = 0
3020 13:53:42.744831 3, 0xFFFF, sum = 0
3021 13:53:42.747881 4, 0xFFFF, sum = 0
3022 13:53:42.747957 5, 0xFFFF, sum = 0
3023 13:53:42.751989 6, 0xFFFF, sum = 0
3024 13:53:42.752073 7, 0xFFFF, sum = 0
3025 13:53:42.754496 8, 0xFFFF, sum = 0
3026 13:53:42.754571 9, 0xFFFF, sum = 0
3027 13:53:42.758632 10, 0xFFFF, sum = 0
3028 13:53:42.758712 11, 0xFFFF, sum = 0
3029 13:53:42.761403 12, 0x0, sum = 1
3030 13:53:42.761480 13, 0x0, sum = 2
3031 13:53:42.764645 14, 0x0, sum = 3
3032 13:53:42.764722 15, 0x0, sum = 4
3033 13:53:42.767843 best_step = 13
3034 13:53:42.767935
3035 13:53:42.767997 ==
3036 13:53:42.771076 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 13:53:42.774460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 13:53:42.774546 ==
3039 13:53:42.774627 RX Vref Scan: 0
3040 13:53:42.774724
3041 13:53:42.777936 RX Vref 0 -> 0, step: 1
3042 13:53:42.778018
3043 13:53:42.781237 RX Delay -21 -> 252, step: 4
3044 13:53:42.784762 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3045 13:53:42.791227 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3046 13:53:42.794997 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3047 13:53:42.797868 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3048 13:53:42.801447 iDelay=195, Bit 4, Center 118 (55 ~ 182) 128
3049 13:53:42.804814 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3050 13:53:42.811097 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3051 13:53:42.814955 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3052 13:53:42.817780 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3053 13:53:42.821316 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3054 13:53:42.824894 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3055 13:53:42.830819 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3056 13:53:42.834304 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3057 13:53:42.837445 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3058 13:53:42.840718 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3059 13:53:42.847255 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3060 13:53:42.847351 ==
3061 13:53:42.851916 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 13:53:42.854045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 13:53:42.854162 ==
3064 13:53:42.854291 DQS Delay:
3065 13:53:42.857231 DQS0 = 0, DQS1 = 0
3066 13:53:42.857330 DQM Delay:
3067 13:53:42.860503 DQM0 = 117, DQM1 = 106
3068 13:53:42.860582 DQ Delay:
3069 13:53:42.863725 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3070 13:53:42.867350 DQ4 =118, DQ5 =112, DQ6 =128, DQ7 =122
3071 13:53:42.870285 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3072 13:53:42.874988 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
3073 13:53:42.875068
3074 13:53:42.875132
3075 13:53:42.883923 [DQSOSCAuto] RK1, (LSB)MR18= 0xfcfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3076 13:53:42.887158 CH0 RK1: MR19=303, MR18=FCFA
3077 13:53:42.890269 CH0_RK1: MR19=0x303, MR18=0xFCFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3078 13:53:42.893622 [RxdqsGatingPostProcess] freq 1200
3079 13:53:42.900659 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3080 13:53:42.903747 best DQS0 dly(2T, 0.5T) = (0, 11)
3081 13:53:42.906895 best DQS1 dly(2T, 0.5T) = (0, 12)
3082 13:53:42.910597 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3083 13:53:42.913587 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3084 13:53:42.916741 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 13:53:42.920407 best DQS1 dly(2T, 0.5T) = (0, 11)
3086 13:53:42.923494 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 13:53:42.926781 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3088 13:53:42.930542 Pre-setting of DQS Precalculation
3089 13:53:42.933605 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3090 13:53:42.933689 ==
3091 13:53:42.937407 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 13:53:42.940352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 13:53:42.940429 ==
3094 13:53:42.947342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 13:53:42.953842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3096 13:53:42.961243 [CA 0] Center 38 (8~68) winsize 61
3097 13:53:42.965127 [CA 1] Center 37 (7~68) winsize 62
3098 13:53:42.967576 [CA 2] Center 35 (6~65) winsize 60
3099 13:53:42.971223 [CA 3] Center 34 (4~64) winsize 61
3100 13:53:42.974590 [CA 4] Center 34 (4~65) winsize 62
3101 13:53:42.977757 [CA 5] Center 34 (4~64) winsize 61
3102 13:53:42.977844
3103 13:53:42.981064 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 13:53:42.981141
3105 13:53:42.984193 [CATrainingPosCal] consider 1 rank data
3106 13:53:42.987540 u2DelayCellTimex100 = 270/100 ps
3107 13:53:42.990925 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3108 13:53:42.997708 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3109 13:53:43.001028 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3110 13:53:43.004152 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3111 13:53:43.007429 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3112 13:53:43.010895 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3113 13:53:43.010971
3114 13:53:43.013978 CA PerBit enable=1, Macro0, CA PI delay=34
3115 13:53:43.014057
3116 13:53:43.017977 [CBTSetCACLKResult] CA Dly = 34
3117 13:53:43.018056 CS Dly: 5 (0~36)
3118 13:53:43.020774 ==
3119 13:53:43.024508 Dram Type= 6, Freq= 0, CH_1, rank 1
3120 13:53:43.027955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 13:53:43.028031 ==
3122 13:53:43.031004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 13:53:43.037587 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3124 13:53:43.046606 [CA 0] Center 37 (7~68) winsize 62
3125 13:53:43.049965 [CA 1] Center 38 (8~69) winsize 62
3126 13:53:43.053212 [CA 2] Center 35 (5~65) winsize 61
3127 13:53:43.057107 [CA 3] Center 33 (3~64) winsize 62
3128 13:53:43.059938 [CA 4] Center 34 (4~64) winsize 61
3129 13:53:43.063191 [CA 5] Center 33 (3~64) winsize 62
3130 13:53:43.063264
3131 13:53:43.066720 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3132 13:53:43.066795
3133 13:53:43.069889 [CATrainingPosCal] consider 2 rank data
3134 13:53:43.073023 u2DelayCellTimex100 = 270/100 ps
3135 13:53:43.076292 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3136 13:53:43.083008 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3137 13:53:43.086267 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3138 13:53:43.090424 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3139 13:53:43.093237 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3140 13:53:43.096431 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3141 13:53:43.096523
3142 13:53:43.099537 CA PerBit enable=1, Macro0, CA PI delay=34
3143 13:53:43.099610
3144 13:53:43.103087 [CBTSetCACLKResult] CA Dly = 34
3145 13:53:43.106319 CS Dly: 6 (0~39)
3146 13:53:43.106408
3147 13:53:43.109861 ----->DramcWriteLeveling(PI) begin...
3148 13:53:43.109944 ==
3149 13:53:43.112907 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 13:53:43.116346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 13:53:43.116468 ==
3152 13:53:43.119550 Write leveling (Byte 0): 26 => 26
3153 13:53:43.123034 Write leveling (Byte 1): 27 => 27
3154 13:53:43.126182 DramcWriteLeveling(PI) end<-----
3155 13:53:43.126260
3156 13:53:43.126325 ==
3157 13:53:43.129701 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 13:53:43.132681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 13:53:43.132759 ==
3160 13:53:43.136043 [Gating] SW mode calibration
3161 13:53:43.142779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3162 13:53:43.149560 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3163 13:53:43.152635 0 15 0 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
3164 13:53:43.156238 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 13:53:43.162733 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 13:53:43.166029 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 13:53:43.169432 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 13:53:43.176160 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 13:53:43.179510 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3170 13:53:43.182946 0 15 28 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (0 0)
3171 13:53:43.189317 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 13:53:43.192547 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 13:53:43.196107 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 13:53:43.202680 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 13:53:43.205963 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 13:53:43.209438 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 13:53:43.215734 1 0 24 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
3178 13:53:43.219037 1 0 28 | B1->B0 | 3d3d 4545 | 0 0 | (1 1) (0 0)
3179 13:53:43.222523 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 13:53:43.229234 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 13:53:43.232755 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 13:53:43.235273 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 13:53:43.239040 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 13:53:43.245780 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 13:53:43.249046 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 13:53:43.252068 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 13:53:43.258813 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 13:53:43.262202 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 13:53:43.265476 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 13:53:43.272356 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 13:53:43.275757 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 13:53:43.278795 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 13:53:43.285050 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 13:53:43.288572 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 13:53:43.292080 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 13:53:43.298436 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 13:53:43.302209 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 13:53:43.305105 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 13:53:43.312065 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 13:53:43.315405 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 13:53:43.318400 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3202 13:53:43.325010 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3203 13:53:43.325090 Total UI for P1: 0, mck2ui 16
3204 13:53:43.331789 best dqsien dly found for B0: ( 1, 3, 24)
3205 13:53:43.335265 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 13:53:43.338315 Total UI for P1: 0, mck2ui 16
3207 13:53:43.341619 best dqsien dly found for B1: ( 1, 3, 28)
3208 13:53:43.345241 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3209 13:53:43.348333 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3210 13:53:43.348408
3211 13:53:43.351559 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3212 13:53:43.354829 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3213 13:53:43.358246 [Gating] SW calibration Done
3214 13:53:43.358321 ==
3215 13:53:43.361703 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 13:53:43.364879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 13:53:43.368373 ==
3218 13:53:43.368447 RX Vref Scan: 0
3219 13:53:43.368510
3220 13:53:43.371572 RX Vref 0 -> 0, step: 1
3221 13:53:43.371673
3222 13:53:43.374788 RX Delay -40 -> 252, step: 8
3223 13:53:43.378237 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3224 13:53:43.381673 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3225 13:53:43.384689 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3226 13:53:43.387984 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3227 13:53:43.394759 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3228 13:53:43.397917 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3229 13:53:43.401388 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3230 13:53:43.404476 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3231 13:53:43.407843 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3232 13:53:43.414607 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3233 13:53:43.417748 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3234 13:53:43.421395 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3235 13:53:43.424626 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3236 13:53:43.427463 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3237 13:53:43.434264 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3238 13:53:43.438215 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3239 13:53:43.438295 ==
3240 13:53:43.441039 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 13:53:43.444399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 13:53:43.444476 ==
3243 13:53:43.447705 DQS Delay:
3244 13:53:43.447780 DQS0 = 0, DQS1 = 0
3245 13:53:43.447840 DQM Delay:
3246 13:53:43.450827 DQM0 = 115, DQM1 = 112
3247 13:53:43.450896 DQ Delay:
3248 13:53:43.454398 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3249 13:53:43.457424 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3250 13:53:43.464458 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3251 13:53:43.467741 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3252 13:53:43.467823
3253 13:53:43.467886
3254 13:53:43.467945 ==
3255 13:53:43.470494 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 13:53:43.474099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 13:53:43.474175 ==
3258 13:53:43.474235
3259 13:53:43.474291
3260 13:53:43.477456 TX Vref Scan disable
3261 13:53:43.477528 == TX Byte 0 ==
3262 13:53:43.483979 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3263 13:53:43.487610 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3264 13:53:43.490894 == TX Byte 1 ==
3265 13:53:43.494204 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3266 13:53:43.498250 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3267 13:53:43.498326 ==
3268 13:53:43.500506 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 13:53:43.504158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 13:53:43.504233 ==
3271 13:53:43.516675 TX Vref=22, minBit 9, minWin=24, winSum=406
3272 13:53:43.520132 TX Vref=24, minBit 9, minWin=24, winSum=413
3273 13:53:43.523426 TX Vref=26, minBit 9, minWin=25, winSum=419
3274 13:53:43.526791 TX Vref=28, minBit 9, minWin=25, winSum=426
3275 13:53:43.530102 TX Vref=30, minBit 3, minWin=26, winSum=427
3276 13:53:43.536579 TX Vref=32, minBit 9, minWin=25, winSum=424
3277 13:53:43.540053 [TxChooseVref] Worse bit 3, Min win 26, Win sum 427, Final Vref 30
3278 13:53:43.540138
3279 13:53:43.543090 Final TX Range 1 Vref 30
3280 13:53:43.543206
3281 13:53:43.543300 ==
3282 13:53:43.546925 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 13:53:43.549835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 13:53:43.552891 ==
3285 13:53:43.552978
3286 13:53:43.553070
3287 13:53:43.553158 TX Vref Scan disable
3288 13:53:43.556467 == TX Byte 0 ==
3289 13:53:43.560223 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3290 13:53:43.563136 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3291 13:53:43.566543 == TX Byte 1 ==
3292 13:53:43.570111 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3293 13:53:43.573446 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3294 13:53:43.576520
3295 13:53:43.576594 [DATLAT]
3296 13:53:43.576655 Freq=1200, CH1 RK0
3297 13:53:43.576714
3298 13:53:43.579585 DATLAT Default: 0xd
3299 13:53:43.579686 0, 0xFFFF, sum = 0
3300 13:53:43.583510 1, 0xFFFF, sum = 0
3301 13:53:43.583616 2, 0xFFFF, sum = 0
3302 13:53:43.586181 3, 0xFFFF, sum = 0
3303 13:53:43.589472 4, 0xFFFF, sum = 0
3304 13:53:43.589544 5, 0xFFFF, sum = 0
3305 13:53:43.593464 6, 0xFFFF, sum = 0
3306 13:53:43.593563 7, 0xFFFF, sum = 0
3307 13:53:43.596299 8, 0xFFFF, sum = 0
3308 13:53:43.596393 9, 0xFFFF, sum = 0
3309 13:53:43.599427 10, 0xFFFF, sum = 0
3310 13:53:43.599498 11, 0xFFFF, sum = 0
3311 13:53:43.602611 12, 0x0, sum = 1
3312 13:53:43.602707 13, 0x0, sum = 2
3313 13:53:43.606002 14, 0x0, sum = 3
3314 13:53:43.606100 15, 0x0, sum = 4
3315 13:53:43.609303 best_step = 13
3316 13:53:43.609374
3317 13:53:43.609433 ==
3318 13:53:43.612772 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 13:53:43.616401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 13:53:43.616475 ==
3321 13:53:43.616536 RX Vref Scan: 1
3322 13:53:43.616594
3323 13:53:43.619914 Set Vref Range= 32 -> 127
3324 13:53:43.620009
3325 13:53:43.622845 RX Vref 32 -> 127, step: 1
3326 13:53:43.622945
3327 13:53:43.626373 RX Delay -13 -> 252, step: 4
3328 13:53:43.626468
3329 13:53:43.629523 Set Vref, RX VrefLevel [Byte0]: 32
3330 13:53:43.633062 [Byte1]: 32
3331 13:53:43.633206
3332 13:53:43.636596 Set Vref, RX VrefLevel [Byte0]: 33
3333 13:53:43.639617 [Byte1]: 33
3334 13:53:43.642922
3335 13:53:43.643026 Set Vref, RX VrefLevel [Byte0]: 34
3336 13:53:43.646665 [Byte1]: 34
3337 13:53:43.650515
3338 13:53:43.650622 Set Vref, RX VrefLevel [Byte0]: 35
3339 13:53:43.654719 [Byte1]: 35
3340 13:53:43.658909
3341 13:53:43.658978 Set Vref, RX VrefLevel [Byte0]: 36
3342 13:53:43.662173 [Byte1]: 36
3343 13:53:43.666782
3344 13:53:43.666865 Set Vref, RX VrefLevel [Byte0]: 37
3345 13:53:43.669852 [Byte1]: 37
3346 13:53:43.674355
3347 13:53:43.674436 Set Vref, RX VrefLevel [Byte0]: 38
3348 13:53:43.678358 [Byte1]: 38
3349 13:53:43.682240
3350 13:53:43.682321 Set Vref, RX VrefLevel [Byte0]: 39
3351 13:53:43.685735 [Byte1]: 39
3352 13:53:43.690140
3353 13:53:43.690220 Set Vref, RX VrefLevel [Byte0]: 40
3354 13:53:43.693665 [Byte1]: 40
3355 13:53:43.698195
3356 13:53:43.698276 Set Vref, RX VrefLevel [Byte0]: 41
3357 13:53:43.701233 [Byte1]: 41
3358 13:53:43.705858
3359 13:53:43.705938 Set Vref, RX VrefLevel [Byte0]: 42
3360 13:53:43.709406 [Byte1]: 42
3361 13:53:43.713661
3362 13:53:43.713755 Set Vref, RX VrefLevel [Byte0]: 43
3363 13:53:43.717113 [Byte1]: 43
3364 13:53:43.721953
3365 13:53:43.722036 Set Vref, RX VrefLevel [Byte0]: 44
3366 13:53:43.724791 [Byte1]: 44
3367 13:53:43.729746
3368 13:53:43.729828 Set Vref, RX VrefLevel [Byte0]: 45
3369 13:53:43.732983 [Byte1]: 45
3370 13:53:43.737613
3371 13:53:43.737699 Set Vref, RX VrefLevel [Byte0]: 46
3372 13:53:43.740716 [Byte1]: 46
3373 13:53:43.745159
3374 13:53:43.745245 Set Vref, RX VrefLevel [Byte0]: 47
3375 13:53:43.749076 [Byte1]: 47
3376 13:53:43.753724
3377 13:53:43.753809 Set Vref, RX VrefLevel [Byte0]: 48
3378 13:53:43.756951 [Byte1]: 48
3379 13:53:43.761628
3380 13:53:43.761714 Set Vref, RX VrefLevel [Byte0]: 49
3381 13:53:43.764413 [Byte1]: 49
3382 13:53:43.769402
3383 13:53:43.769488 Set Vref, RX VrefLevel [Byte0]: 50
3384 13:53:43.772638 [Byte1]: 50
3385 13:53:43.776640
3386 13:53:43.776724 Set Vref, RX VrefLevel [Byte0]: 51
3387 13:53:43.780056 [Byte1]: 51
3388 13:53:43.784869
3389 13:53:43.784957 Set Vref, RX VrefLevel [Byte0]: 52
3390 13:53:43.788028 [Byte1]: 52
3391 13:53:43.792586
3392 13:53:43.792681 Set Vref, RX VrefLevel [Byte0]: 53
3393 13:53:43.795744 [Byte1]: 53
3394 13:53:43.800603
3395 13:53:43.800693 Set Vref, RX VrefLevel [Byte0]: 54
3396 13:53:43.803604 [Byte1]: 54
3397 13:53:43.808483
3398 13:53:43.808573 Set Vref, RX VrefLevel [Byte0]: 55
3399 13:53:43.811687 [Byte1]: 55
3400 13:53:43.816272
3401 13:53:43.816360 Set Vref, RX VrefLevel [Byte0]: 56
3402 13:53:43.819629 [Byte1]: 56
3403 13:53:43.824875
3404 13:53:43.824968 Set Vref, RX VrefLevel [Byte0]: 57
3405 13:53:43.827249 [Byte1]: 57
3406 13:53:43.832079
3407 13:53:43.832171 Set Vref, RX VrefLevel [Byte0]: 58
3408 13:53:43.835232 [Byte1]: 58
3409 13:53:43.840146
3410 13:53:43.840263 Set Vref, RX VrefLevel [Byte0]: 59
3411 13:53:43.846334 [Byte1]: 59
3412 13:53:43.846430
3413 13:53:43.849988 Set Vref, RX VrefLevel [Byte0]: 60
3414 13:53:43.853043 [Byte1]: 60
3415 13:53:43.853129
3416 13:53:43.856420 Set Vref, RX VrefLevel [Byte0]: 61
3417 13:53:43.859698 [Byte1]: 61
3418 13:53:43.863792
3419 13:53:43.863881 Set Vref, RX VrefLevel [Byte0]: 62
3420 13:53:43.867041 [Byte1]: 62
3421 13:53:43.871597
3422 13:53:43.871718 Set Vref, RX VrefLevel [Byte0]: 63
3423 13:53:43.874388 [Byte1]: 63
3424 13:53:43.879406
3425 13:53:43.879611 Set Vref, RX VrefLevel [Byte0]: 64
3426 13:53:43.882616 [Byte1]: 64
3427 13:53:43.887270
3428 13:53:43.887400 Set Vref, RX VrefLevel [Byte0]: 65
3429 13:53:43.890641 [Byte1]: 65
3430 13:53:43.895619
3431 13:53:43.895720 Final RX Vref Byte 0 = 52 to rank0
3432 13:53:43.898651 Final RX Vref Byte 1 = 52 to rank0
3433 13:53:43.901576 Final RX Vref Byte 0 = 52 to rank1
3434 13:53:43.904932 Final RX Vref Byte 1 = 52 to rank1==
3435 13:53:43.908376 Dram Type= 6, Freq= 0, CH_1, rank 0
3436 13:53:43.915005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 13:53:43.915111 ==
3438 13:53:43.915179 DQS Delay:
3439 13:53:43.915240 DQS0 = 0, DQS1 = 0
3440 13:53:43.918422 DQM Delay:
3441 13:53:43.918508 DQM0 = 114, DQM1 = 113
3442 13:53:43.921718 DQ Delay:
3443 13:53:43.924837 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3444 13:53:43.929174 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3445 13:53:43.931720 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3446 13:53:43.934981 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =122
3447 13:53:43.935073
3448 13:53:43.935140
3449 13:53:43.944572 [DQSOSCAuto] RK0, (LSB)MR18= 0xf805, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3450 13:53:43.944689 CH1 RK0: MR19=304, MR18=F805
3451 13:53:43.951174 CH1_RK0: MR19=0x304, MR18=0xF805, DQSOSC=408, MR23=63, INC=39, DEC=26
3452 13:53:43.951302
3453 13:53:43.955183 ----->DramcWriteLeveling(PI) begin...
3454 13:53:43.955312 ==
3455 13:53:43.958398 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 13:53:43.964670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 13:53:43.964817 ==
3458 13:53:43.968056 Write leveling (Byte 0): 26 => 26
3459 13:53:43.968166 Write leveling (Byte 1): 30 => 30
3460 13:53:43.971252 DramcWriteLeveling(PI) end<-----
3461 13:53:43.971368
3462 13:53:43.971439 ==
3463 13:53:43.974663 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 13:53:43.981355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 13:53:43.981457 ==
3466 13:53:43.984746 [Gating] SW mode calibration
3467 13:53:43.991632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3468 13:53:43.994430 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3469 13:53:44.001530 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 13:53:44.004394 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 13:53:44.007926 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 13:53:44.015292 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 13:53:44.018618 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 13:53:44.021350 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3475 13:53:44.028001 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
3476 13:53:44.031102 0 15 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3477 13:53:44.034472 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 13:53:44.040866 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 13:53:44.044255 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 13:53:44.047803 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 13:53:44.054029 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 13:53:44.057367 1 0 20 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
3483 13:53:44.061034 1 0 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
3484 13:53:44.067704 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3485 13:53:44.070428 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 13:53:44.073977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 13:53:44.080900 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 13:53:44.083861 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 13:53:44.087335 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 13:53:44.093494 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 13:53:44.096964 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3492 13:53:44.100655 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3493 13:53:44.106977 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 13:53:44.110109 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 13:53:44.113705 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 13:53:44.119890 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 13:53:44.123053 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 13:53:44.126418 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 13:53:44.133058 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 13:53:44.136243 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 13:53:44.139759 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 13:53:44.146190 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 13:53:44.149793 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 13:53:44.152682 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 13:53:44.159464 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 13:53:44.163091 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 13:53:44.165845 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3508 13:53:44.172637 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3509 13:53:44.172725 Total UI for P1: 0, mck2ui 16
3510 13:53:44.179122 best dqsien dly found for B0: ( 1, 3, 24)
3511 13:53:44.182621 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 13:53:44.185659 Total UI for P1: 0, mck2ui 16
3513 13:53:44.189270 best dqsien dly found for B1: ( 1, 3, 28)
3514 13:53:44.192261 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3515 13:53:44.195623 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3516 13:53:44.195717
3517 13:53:44.199085 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3518 13:53:44.202255 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3519 13:53:44.205771 [Gating] SW calibration Done
3520 13:53:44.205854 ==
3521 13:53:44.208602 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 13:53:44.216316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 13:53:44.216406 ==
3524 13:53:44.216511 RX Vref Scan: 0
3525 13:53:44.216574
3526 13:53:44.218553 RX Vref 0 -> 0, step: 1
3527 13:53:44.218635
3528 13:53:44.222193 RX Delay -40 -> 252, step: 8
3529 13:53:44.225139 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3530 13:53:44.228427 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3531 13:53:44.231861 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3532 13:53:44.235132 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3533 13:53:44.241986 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3534 13:53:44.244888 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3535 13:53:44.248163 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3536 13:53:44.251514 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3537 13:53:44.254832 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3538 13:53:44.261574 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3539 13:53:44.264653 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3540 13:53:44.268025 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3541 13:53:44.271594 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3542 13:53:44.278655 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3543 13:53:44.281111 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3544 13:53:44.284503 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3545 13:53:44.284589 ==
3546 13:53:44.288129 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 13:53:44.291229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 13:53:44.291316 ==
3549 13:53:44.294455 DQS Delay:
3550 13:53:44.294540 DQS0 = 0, DQS1 = 0
3551 13:53:44.297936 DQM Delay:
3552 13:53:44.298025 DQM0 = 115, DQM1 = 112
3553 13:53:44.300881 DQ Delay:
3554 13:53:44.304347 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3555 13:53:44.307749 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3556 13:53:44.311224 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3557 13:53:44.314365 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3558 13:53:44.314448
3559 13:53:44.314513
3560 13:53:44.314573 ==
3561 13:53:44.317883 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 13:53:44.320970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 13:53:44.321054 ==
3564 13:53:44.321119
3565 13:53:44.321180
3566 13:53:44.324151 TX Vref Scan disable
3567 13:53:44.327500 == TX Byte 0 ==
3568 13:53:44.330993 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 13:53:44.334069 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 13:53:44.337242 == TX Byte 1 ==
3571 13:53:44.341207 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3572 13:53:44.343793 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3573 13:53:44.343880 ==
3574 13:53:44.347009 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 13:53:44.353851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 13:53:44.353940 ==
3577 13:53:44.364511 TX Vref=22, minBit 9, minWin=25, winSum=424
3578 13:53:44.367715 TX Vref=24, minBit 1, minWin=26, winSum=429
3579 13:53:44.371107 TX Vref=26, minBit 1, minWin=26, winSum=429
3580 13:53:44.374423 TX Vref=28, minBit 1, minWin=26, winSum=430
3581 13:53:44.377725 TX Vref=30, minBit 1, minWin=26, winSum=432
3582 13:53:44.384231 TX Vref=32, minBit 9, minWin=26, winSum=430
3583 13:53:44.387871 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3584 13:53:44.387956
3585 13:53:44.391181 Final TX Range 1 Vref 30
3586 13:53:44.391291
3587 13:53:44.391427 ==
3588 13:53:44.394075 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 13:53:44.397191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 13:53:44.400356 ==
3591 13:53:44.400479
3592 13:53:44.400544
3593 13:53:44.400604 TX Vref Scan disable
3594 13:53:44.404294 == TX Byte 0 ==
3595 13:53:44.407872 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3596 13:53:44.414086 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3597 13:53:44.414176 == TX Byte 1 ==
3598 13:53:44.417561 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3599 13:53:44.425388 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3600 13:53:44.425473
3601 13:53:44.425560 [DATLAT]
3602 13:53:44.425641 Freq=1200, CH1 RK1
3603 13:53:44.425722
3604 13:53:44.427433 DATLAT Default: 0xd
3605 13:53:44.430220 0, 0xFFFF, sum = 0
3606 13:53:44.430326 1, 0xFFFF, sum = 0
3607 13:53:44.433767 2, 0xFFFF, sum = 0
3608 13:53:44.433856 3, 0xFFFF, sum = 0
3609 13:53:44.437005 4, 0xFFFF, sum = 0
3610 13:53:44.437091 5, 0xFFFF, sum = 0
3611 13:53:44.440183 6, 0xFFFF, sum = 0
3612 13:53:44.440269 7, 0xFFFF, sum = 0
3613 13:53:44.443338 8, 0xFFFF, sum = 0
3614 13:53:44.443483 9, 0xFFFF, sum = 0
3615 13:53:44.446658 10, 0xFFFF, sum = 0
3616 13:53:44.446745 11, 0xFFFF, sum = 0
3617 13:53:44.450020 12, 0x0, sum = 1
3618 13:53:44.450107 13, 0x0, sum = 2
3619 13:53:44.453659 14, 0x0, sum = 3
3620 13:53:44.453745 15, 0x0, sum = 4
3621 13:53:44.456742 best_step = 13
3622 13:53:44.456826
3623 13:53:44.456913 ==
3624 13:53:44.459875 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 13:53:44.463557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 13:53:44.463642 ==
3627 13:53:44.466721 RX Vref Scan: 0
3628 13:53:44.466805
3629 13:53:44.466892 RX Vref 0 -> 0, step: 1
3630 13:53:44.467011
3631 13:53:44.470258 RX Delay -13 -> 252, step: 4
3632 13:53:44.476627 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3633 13:53:44.479642 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3634 13:53:44.483287 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3635 13:53:44.486761 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3636 13:53:44.489914 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3637 13:53:44.496335 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3638 13:53:44.499885 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3639 13:53:44.503145 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3640 13:53:44.506215 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3641 13:53:44.512857 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3642 13:53:44.515714 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3643 13:53:44.519188 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3644 13:53:44.522697 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3645 13:53:44.525743 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3646 13:53:44.532201 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3647 13:53:44.535685 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3648 13:53:44.535771 ==
3649 13:53:44.539132 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 13:53:44.542087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 13:53:44.542173 ==
3652 13:53:44.545356 DQS Delay:
3653 13:53:44.545441 DQS0 = 0, DQS1 = 0
3654 13:53:44.548806 DQM Delay:
3655 13:53:44.548891 DQM0 = 115, DQM1 = 112
3656 13:53:44.548978 DQ Delay:
3657 13:53:44.555172 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3658 13:53:44.558616 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3659 13:53:44.562184 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3660 13:53:44.565235 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3661 13:53:44.565320
3662 13:53:44.565406
3663 13:53:44.571579 [DQSOSCAuto] RK1, (LSB)MR18= 0xf70a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3664 13:53:44.575039 CH1 RK1: MR19=304, MR18=F70A
3665 13:53:44.581744 CH1_RK1: MR19=0x304, MR18=0xF70A, DQSOSC=406, MR23=63, INC=39, DEC=26
3666 13:53:44.585371 [RxdqsGatingPostProcess] freq 1200
3667 13:53:44.591717 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3668 13:53:44.594796 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 13:53:44.594881 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 13:53:44.597947 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 13:53:44.601153 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 13:53:44.604521 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 13:53:44.608088 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 13:53:44.611463 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 13:53:44.614739 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 13:53:44.618334 Pre-setting of DQS Precalculation
3677 13:53:44.624855 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3678 13:53:44.630852 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3679 13:53:44.637350 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3680 13:53:44.637440
3681 13:53:44.637530
3682 13:53:44.640826 [Calibration Summary] 2400 Mbps
3683 13:53:44.640911 CH 0, Rank 0
3684 13:53:44.644418 SW Impedance : PASS
3685 13:53:44.647993 DUTY Scan : NO K
3686 13:53:44.648079 ZQ Calibration : PASS
3687 13:53:44.650791 Jitter Meter : NO K
3688 13:53:44.654128 CBT Training : PASS
3689 13:53:44.654214 Write leveling : PASS
3690 13:53:44.657633 RX DQS gating : PASS
3691 13:53:44.661052 RX DQ/DQS(RDDQC) : PASS
3692 13:53:44.661137 TX DQ/DQS : PASS
3693 13:53:44.664555 RX DATLAT : PASS
3694 13:53:44.667519 RX DQ/DQS(Engine): PASS
3695 13:53:44.667604 TX OE : NO K
3696 13:53:44.670623 All Pass.
3697 13:53:44.670707
3698 13:53:44.670793 CH 0, Rank 1
3699 13:53:44.673822 SW Impedance : PASS
3700 13:53:44.673909 DUTY Scan : NO K
3701 13:53:44.677317 ZQ Calibration : PASS
3702 13:53:44.680584 Jitter Meter : NO K
3703 13:53:44.680670 CBT Training : PASS
3704 13:53:44.684258 Write leveling : PASS
3705 13:53:44.687204 RX DQS gating : PASS
3706 13:53:44.687289 RX DQ/DQS(RDDQC) : PASS
3707 13:53:44.690573 TX DQ/DQS : PASS
3708 13:53:44.690659 RX DATLAT : PASS
3709 13:53:44.693820 RX DQ/DQS(Engine): PASS
3710 13:53:44.697241 TX OE : NO K
3711 13:53:44.697327 All Pass.
3712 13:53:44.697414
3713 13:53:44.700126 CH 1, Rank 0
3714 13:53:44.700211 SW Impedance : PASS
3715 13:53:44.703489 DUTY Scan : NO K
3716 13:53:44.703574 ZQ Calibration : PASS
3717 13:53:44.707235 Jitter Meter : NO K
3718 13:53:44.710978 CBT Training : PASS
3719 13:53:44.711063 Write leveling : PASS
3720 13:53:44.713272 RX DQS gating : PASS
3721 13:53:44.717102 RX DQ/DQS(RDDQC) : PASS
3722 13:53:44.717190 TX DQ/DQS : PASS
3723 13:53:44.720273 RX DATLAT : PASS
3724 13:53:44.723208 RX DQ/DQS(Engine): PASS
3725 13:53:44.723293 TX OE : NO K
3726 13:53:44.726908 All Pass.
3727 13:53:44.726992
3728 13:53:44.727079 CH 1, Rank 1
3729 13:53:44.730098 SW Impedance : PASS
3730 13:53:44.730182 DUTY Scan : NO K
3731 13:53:44.733336 ZQ Calibration : PASS
3732 13:53:44.736359 Jitter Meter : NO K
3733 13:53:44.736444 CBT Training : PASS
3734 13:53:44.739819 Write leveling : PASS
3735 13:53:44.743324 RX DQS gating : PASS
3736 13:53:44.743448 RX DQ/DQS(RDDQC) : PASS
3737 13:53:44.746552 TX DQ/DQS : PASS
3738 13:53:44.749475 RX DATLAT : PASS
3739 13:53:44.749561 RX DQ/DQS(Engine): PASS
3740 13:53:44.753462 TX OE : NO K
3741 13:53:44.753548 All Pass.
3742 13:53:44.753635
3743 13:53:44.756322 DramC Write-DBI off
3744 13:53:44.759604 PER_BANK_REFRESH: Hybrid Mode
3745 13:53:44.759688 TX_TRACKING: ON
3746 13:53:44.769176 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3747 13:53:44.772916 [FAST_K] Save calibration result to emmc
3748 13:53:44.775848 dramc_set_vcore_voltage set vcore to 650000
3749 13:53:44.779252 Read voltage for 600, 5
3750 13:53:44.779335 Vio18 = 0
3751 13:53:44.779460 Vcore = 650000
3752 13:53:44.782421 Vdram = 0
3753 13:53:44.782505 Vddq = 0
3754 13:53:44.782592 Vmddr = 0
3755 13:53:44.789434 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3756 13:53:44.792377 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3757 13:53:44.795859 MEM_TYPE=3, freq_sel=19
3758 13:53:44.799099 sv_algorithm_assistance_LP4_1600
3759 13:53:44.801932 ============ PULL DRAM RESETB DOWN ============
3760 13:53:44.808825 ========== PULL DRAM RESETB DOWN end =========
3761 13:53:44.811937 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3762 13:53:44.815144 ===================================
3763 13:53:44.818608 LPDDR4 DRAM CONFIGURATION
3764 13:53:44.821851 ===================================
3765 13:53:44.821937 EX_ROW_EN[0] = 0x0
3766 13:53:44.825209 EX_ROW_EN[1] = 0x0
3767 13:53:44.825294 LP4Y_EN = 0x0
3768 13:53:44.828479 WORK_FSP = 0x0
3769 13:53:44.828564 WL = 0x2
3770 13:53:44.831863 RL = 0x2
3771 13:53:44.835206 BL = 0x2
3772 13:53:44.835307 RPST = 0x0
3773 13:53:44.838899 RD_PRE = 0x0
3774 13:53:44.838984 WR_PRE = 0x1
3775 13:53:44.841685 WR_PST = 0x0
3776 13:53:44.841770 DBI_WR = 0x0
3777 13:53:44.845374 DBI_RD = 0x0
3778 13:53:44.845460 OTF = 0x1
3779 13:53:44.848380 ===================================
3780 13:53:44.851664 ===================================
3781 13:53:44.854998 ANA top config
3782 13:53:44.858916 ===================================
3783 13:53:44.859001 DLL_ASYNC_EN = 0
3784 13:53:44.861724 ALL_SLAVE_EN = 1
3785 13:53:44.864666 NEW_RANK_MODE = 1
3786 13:53:44.868121 DLL_IDLE_MODE = 1
3787 13:53:44.871166 LP45_APHY_COMB_EN = 1
3788 13:53:44.871251 TX_ODT_DIS = 1
3789 13:53:44.874827 NEW_8X_MODE = 1
3790 13:53:44.877698 ===================================
3791 13:53:44.881142 ===================================
3792 13:53:44.884422 data_rate = 1200
3793 13:53:44.888017 CKR = 1
3794 13:53:44.891245 DQ_P2S_RATIO = 8
3795 13:53:44.894266 ===================================
3796 13:53:44.897391 CA_P2S_RATIO = 8
3797 13:53:44.897476 DQ_CA_OPEN = 0
3798 13:53:44.901183 DQ_SEMI_OPEN = 0
3799 13:53:44.904056 CA_SEMI_OPEN = 0
3800 13:53:44.907161 CA_FULL_RATE = 0
3801 13:53:44.910389 DQ_CKDIV4_EN = 1
3802 13:53:44.914497 CA_CKDIV4_EN = 1
3803 13:53:44.914582 CA_PREDIV_EN = 0
3804 13:53:44.916997 PH8_DLY = 0
3805 13:53:44.920422 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3806 13:53:44.923972 DQ_AAMCK_DIV = 4
3807 13:53:44.926933 CA_AAMCK_DIV = 4
3808 13:53:44.930688 CA_ADMCK_DIV = 4
3809 13:53:44.930785 DQ_TRACK_CA_EN = 0
3810 13:53:44.933922 CA_PICK = 600
3811 13:53:44.936978 CA_MCKIO = 600
3812 13:53:44.940322 MCKIO_SEMI = 0
3813 13:53:44.944103 PLL_FREQ = 2288
3814 13:53:44.946786 DQ_UI_PI_RATIO = 32
3815 13:53:44.950347 CA_UI_PI_RATIO = 0
3816 13:53:44.953700 ===================================
3817 13:53:44.956910 ===================================
3818 13:53:44.956996 memory_type:LPDDR4
3819 13:53:44.959920 GP_NUM : 10
3820 13:53:44.963114 SRAM_EN : 1
3821 13:53:44.963224 MD32_EN : 0
3822 13:53:44.966818 ===================================
3823 13:53:44.969712 [ANA_INIT] >>>>>>>>>>>>>>
3824 13:53:44.973329 <<<<<< [CONFIGURE PHASE]: ANA_TX
3825 13:53:44.976553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3826 13:53:44.979797 ===================================
3827 13:53:44.983796 data_rate = 1200,PCW = 0X5800
3828 13:53:44.986654 ===================================
3829 13:53:44.989586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3830 13:53:44.992724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3831 13:53:44.999285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3832 13:53:45.002842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3833 13:53:45.009596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3834 13:53:45.012504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3835 13:53:45.012590 [ANA_INIT] flow start
3836 13:53:45.016502 [ANA_INIT] PLL >>>>>>>>
3837 13:53:45.019313 [ANA_INIT] PLL <<<<<<<<
3838 13:53:45.019437 [ANA_INIT] MIDPI >>>>>>>>
3839 13:53:45.022473 [ANA_INIT] MIDPI <<<<<<<<
3840 13:53:45.026059 [ANA_INIT] DLL >>>>>>>>
3841 13:53:45.026145 [ANA_INIT] flow end
3842 13:53:45.032468 ============ LP4 DIFF to SE enter ============
3843 13:53:45.035562 ============ LP4 DIFF to SE exit ============
3844 13:53:45.039960 [ANA_INIT] <<<<<<<<<<<<<
3845 13:53:45.040047 [Flow] Enable top DCM control >>>>>
3846 13:53:45.042236 [Flow] Enable top DCM control <<<<<
3847 13:53:45.045470 Enable DLL master slave shuffle
3848 13:53:45.052226 ==============================================================
3849 13:53:45.055893 Gating Mode config
3850 13:53:45.058587 ==============================================================
3851 13:53:45.062238 Config description:
3852 13:53:45.072350 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3853 13:53:45.078713 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3854 13:53:45.081800 SELPH_MODE 0: By rank 1: By Phase
3855 13:53:45.088539 ==============================================================
3856 13:53:45.091751 GAT_TRACK_EN = 1
3857 13:53:45.094962 RX_GATING_MODE = 2
3858 13:53:45.098587 RX_GATING_TRACK_MODE = 2
3859 13:53:45.101838 SELPH_MODE = 1
3860 13:53:45.101924 PICG_EARLY_EN = 1
3861 13:53:45.105176 VALID_LAT_VALUE = 1
3862 13:53:45.111981 ==============================================================
3863 13:53:45.115209 Enter into Gating configuration >>>>
3864 13:53:45.118067 Exit from Gating configuration <<<<
3865 13:53:45.121991 Enter into DVFS_PRE_config >>>>>
3866 13:53:45.131531 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3867 13:53:45.135053 Exit from DVFS_PRE_config <<<<<
3868 13:53:45.137704 Enter into PICG configuration >>>>
3869 13:53:45.140988 Exit from PICG configuration <<<<
3870 13:53:45.145096 [RX_INPUT] configuration >>>>>
3871 13:53:45.148051 [RX_INPUT] configuration <<<<<
3872 13:53:45.154308 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3873 13:53:45.157678 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3874 13:53:45.163891 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 13:53:45.170949 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 13:53:45.177678 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3877 13:53:45.183608 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3878 13:53:45.187048 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3879 13:53:45.190296 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3880 13:53:45.194021 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3881 13:53:45.199997 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3882 13:53:45.203996 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3883 13:53:45.207234 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3884 13:53:45.210177 ===================================
3885 13:53:45.213809 LPDDR4 DRAM CONFIGURATION
3886 13:53:45.216745 ===================================
3887 13:53:45.220597 EX_ROW_EN[0] = 0x0
3888 13:53:45.220683 EX_ROW_EN[1] = 0x0
3889 13:53:45.223387 LP4Y_EN = 0x0
3890 13:53:45.223487 WORK_FSP = 0x0
3891 13:53:45.226973 WL = 0x2
3892 13:53:45.227082 RL = 0x2
3893 13:53:45.229835 BL = 0x2
3894 13:53:45.229920 RPST = 0x0
3895 13:53:45.233138 RD_PRE = 0x0
3896 13:53:45.233250 WR_PRE = 0x1
3897 13:53:45.236465 WR_PST = 0x0
3898 13:53:45.236551 DBI_WR = 0x0
3899 13:53:45.239825 DBI_RD = 0x0
3900 13:53:45.243709 OTF = 0x1
3901 13:53:45.243796 ===================================
3902 13:53:45.250150 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3903 13:53:45.253230 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3904 13:53:45.256320 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 13:53:45.259512 ===================================
3906 13:53:45.262809 LPDDR4 DRAM CONFIGURATION
3907 13:53:45.266367 ===================================
3908 13:53:45.270012 EX_ROW_EN[0] = 0x10
3909 13:53:45.270099 EX_ROW_EN[1] = 0x0
3910 13:53:45.273131 LP4Y_EN = 0x0
3911 13:53:45.273252 WORK_FSP = 0x0
3912 13:53:45.276168 WL = 0x2
3913 13:53:45.276254 RL = 0x2
3914 13:53:45.279240 BL = 0x2
3915 13:53:45.279322 RPST = 0x0
3916 13:53:45.282703 RD_PRE = 0x0
3917 13:53:45.282785 WR_PRE = 0x1
3918 13:53:45.285908 WR_PST = 0x0
3919 13:53:45.289011 DBI_WR = 0x0
3920 13:53:45.289094 DBI_RD = 0x0
3921 13:53:45.292666 OTF = 0x1
3922 13:53:45.295644 ===================================
3923 13:53:45.299273 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3924 13:53:45.304403 nWR fixed to 30
3925 13:53:45.307913 [ModeRegInit_LP4] CH0 RK0
3926 13:53:45.308019 [ModeRegInit_LP4] CH0 RK1
3927 13:53:45.310890 [ModeRegInit_LP4] CH1 RK0
3928 13:53:45.314022 [ModeRegInit_LP4] CH1 RK1
3929 13:53:45.314104 match AC timing 17
3930 13:53:45.320793 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3931 13:53:45.324027 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3932 13:53:45.327543 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3933 13:53:45.334092 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3934 13:53:45.337330 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3935 13:53:45.337415 ==
3936 13:53:45.340636 Dram Type= 6, Freq= 0, CH_0, rank 0
3937 13:53:45.343579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 13:53:45.343665 ==
3939 13:53:45.350537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 13:53:45.356882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3941 13:53:45.360700 [CA 0] Center 36 (6~67) winsize 62
3942 13:53:45.363474 [CA 1] Center 36 (6~66) winsize 61
3943 13:53:45.366985 [CA 2] Center 34 (4~65) winsize 62
3944 13:53:45.370272 [CA 3] Center 34 (4~65) winsize 62
3945 13:53:45.373279 [CA 4] Center 34 (3~65) winsize 63
3946 13:53:45.377223 [CA 5] Center 33 (3~64) winsize 62
3947 13:53:45.377306
3948 13:53:45.380055 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3949 13:53:45.380137
3950 13:53:45.383213 [CATrainingPosCal] consider 1 rank data
3951 13:53:45.387001 u2DelayCellTimex100 = 270/100 ps
3952 13:53:45.389874 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3953 13:53:45.393204 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3954 13:53:45.396923 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3955 13:53:45.403076 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3956 13:53:45.406236 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3957 13:53:45.409899 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 13:53:45.409984
3959 13:53:45.413196 CA PerBit enable=1, Macro0, CA PI delay=33
3960 13:53:45.413288
3961 13:53:45.416614 [CBTSetCACLKResult] CA Dly = 33
3962 13:53:45.416697 CS Dly: 5 (0~36)
3963 13:53:45.416762 ==
3964 13:53:45.419868 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 13:53:45.426009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 13:53:45.426093 ==
3967 13:53:45.429445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 13:53:45.436328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3969 13:53:45.439801 [CA 0] Center 36 (6~67) winsize 62
3970 13:53:45.443037 [CA 1] Center 36 (6~67) winsize 62
3971 13:53:45.446184 [CA 2] Center 34 (4~65) winsize 62
3972 13:53:45.449384 [CA 3] Center 34 (4~65) winsize 62
3973 13:53:45.452810 [CA 4] Center 34 (3~65) winsize 63
3974 13:53:45.456096 [CA 5] Center 33 (3~64) winsize 62
3975 13:53:45.456179
3976 13:53:45.459260 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3977 13:53:45.459404
3978 13:53:45.462712 [CATrainingPosCal] consider 2 rank data
3979 13:53:45.466003 u2DelayCellTimex100 = 270/100 ps
3980 13:53:45.469692 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3981 13:53:45.475881 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3982 13:53:45.479201 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3983 13:53:45.483025 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3984 13:53:45.486472 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3985 13:53:45.488887 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 13:53:45.488970
3987 13:53:45.492255 CA PerBit enable=1, Macro0, CA PI delay=33
3988 13:53:45.492338
3989 13:53:45.496127 [CBTSetCACLKResult] CA Dly = 33
3990 13:53:45.498741 CS Dly: 6 (0~38)
3991 13:53:45.498823
3992 13:53:45.502069 ----->DramcWriteLeveling(PI) begin...
3993 13:53:45.502152 ==
3994 13:53:45.505543 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 13:53:45.509251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 13:53:45.509334 ==
3997 13:53:45.512165 Write leveling (Byte 0): 32 => 32
3998 13:53:45.515550 Write leveling (Byte 1): 31 => 31
3999 13:53:45.518454 DramcWriteLeveling(PI) end<-----
4000 13:53:45.518536
4001 13:53:45.518599 ==
4002 13:53:45.521745 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 13:53:45.525196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 13:53:45.525279 ==
4005 13:53:45.528619 [Gating] SW mode calibration
4006 13:53:45.534919 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4007 13:53:45.541674 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4008 13:53:45.545229 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 13:53:45.551346 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 13:53:45.554701 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 13:53:45.557755 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
4012 13:53:45.564248 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (1 1)
4013 13:53:45.567570 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 13:53:45.570850 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 13:53:45.577690 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 13:53:45.581382 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 13:53:45.584324 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 13:53:45.590832 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 13:53:45.594172 0 10 12 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (0 0)
4020 13:53:45.597626 0 10 16 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
4021 13:53:45.604100 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 13:53:45.607136 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 13:53:45.610446 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 13:53:45.617248 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 13:53:45.620669 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 13:53:45.623740 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 13:53:45.630195 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4028 13:53:45.633580 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4029 13:53:45.637299 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 13:53:45.643252 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 13:53:45.646821 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 13:53:45.650001 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 13:53:45.656637 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 13:53:45.660160 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 13:53:45.663165 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 13:53:45.669711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 13:53:45.673169 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 13:53:45.676278 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 13:53:45.682868 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 13:53:45.686543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 13:53:45.689897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 13:53:45.696618 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 13:53:45.700272 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 13:53:45.702688 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 13:53:45.706122 Total UI for P1: 0, mck2ui 16
4046 13:53:45.709588 best dqsien dly found for B0: ( 0, 13, 14)
4047 13:53:45.712532 Total UI for P1: 0, mck2ui 16
4048 13:53:45.716325 best dqsien dly found for B1: ( 0, 13, 14)
4049 13:53:45.719009 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4050 13:53:45.722923 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4051 13:53:45.723008
4052 13:53:45.728940 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4053 13:53:45.732770 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4054 13:53:45.735710 [Gating] SW calibration Done
4055 13:53:45.735799 ==
4056 13:53:45.738912 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 13:53:45.742332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 13:53:45.742419 ==
4059 13:53:45.742506 RX Vref Scan: 0
4060 13:53:45.742589
4061 13:53:45.745436 RX Vref 0 -> 0, step: 1
4062 13:53:45.745522
4063 13:53:45.748968 RX Delay -230 -> 252, step: 16
4064 13:53:45.752247 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4065 13:53:45.758753 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4066 13:53:45.762256 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4067 13:53:45.765311 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4068 13:53:45.768333 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4069 13:53:45.771923 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4070 13:53:45.778189 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4071 13:53:45.782199 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4072 13:53:45.785024 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4073 13:53:45.788490 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4074 13:53:45.795616 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4075 13:53:45.798534 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4076 13:53:45.801558 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4077 13:53:45.804915 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4078 13:53:45.811849 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4079 13:53:45.815101 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4080 13:53:45.815212 ==
4081 13:53:45.817934 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 13:53:45.821526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 13:53:45.821619 ==
4084 13:53:45.824630 DQS Delay:
4085 13:53:45.824716 DQS0 = 0, DQS1 = 0
4086 13:53:45.824803 DQM Delay:
4087 13:53:45.828137 DQM0 = 45, DQM1 = 36
4088 13:53:45.828223 DQ Delay:
4089 13:53:45.831508 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4090 13:53:45.834416 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4091 13:53:45.837594 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4092 13:53:45.841309 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4093 13:53:45.841397
4094 13:53:45.841483
4095 13:53:45.841565 ==
4096 13:53:45.844380 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 13:53:45.850947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 13:53:45.851039 ==
4099 13:53:45.851126
4100 13:53:45.851208
4101 13:53:45.851306 TX Vref Scan disable
4102 13:53:45.855182 == TX Byte 0 ==
4103 13:53:45.858151 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4104 13:53:45.864651 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4105 13:53:45.864791 == TX Byte 1 ==
4106 13:53:45.868247 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4107 13:53:45.874676 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4108 13:53:45.874789 ==
4109 13:53:45.878113 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 13:53:45.881443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 13:53:45.881537 ==
4112 13:53:45.881604
4113 13:53:45.881665
4114 13:53:45.884433 TX Vref Scan disable
4115 13:53:45.887578 == TX Byte 0 ==
4116 13:53:45.891050 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4117 13:53:45.894065 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4118 13:53:45.897540 == TX Byte 1 ==
4119 13:53:45.900873 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4120 13:53:45.904023 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4121 13:53:45.904108
4122 13:53:45.907265 [DATLAT]
4123 13:53:45.907379 Freq=600, CH0 RK0
4124 13:53:45.907448
4125 13:53:45.910680 DATLAT Default: 0x9
4126 13:53:45.910788 0, 0xFFFF, sum = 0
4127 13:53:45.913860 1, 0xFFFF, sum = 0
4128 13:53:45.913944 2, 0xFFFF, sum = 0
4129 13:53:45.917272 3, 0xFFFF, sum = 0
4130 13:53:45.917374 4, 0xFFFF, sum = 0
4131 13:53:45.920640 5, 0xFFFF, sum = 0
4132 13:53:45.920735 6, 0xFFFF, sum = 0
4133 13:53:45.923764 7, 0xFFFF, sum = 0
4134 13:53:45.923858 8, 0x0, sum = 1
4135 13:53:45.927171 9, 0x0, sum = 2
4136 13:53:45.927270 10, 0x0, sum = 3
4137 13:53:45.930240 11, 0x0, sum = 4
4138 13:53:45.930332 best_step = 9
4139 13:53:45.930413
4140 13:53:45.930489 ==
4141 13:53:45.933647 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 13:53:45.937263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 13:53:45.940043 ==
4144 13:53:45.940154 RX Vref Scan: 1
4145 13:53:45.940256
4146 13:53:45.943648 RX Vref 0 -> 0, step: 1
4147 13:53:45.943752
4148 13:53:45.946647 RX Delay -179 -> 252, step: 8
4149 13:53:45.946759
4150 13:53:45.950182 Set Vref, RX VrefLevel [Byte0]: 57
4151 13:53:45.953296 [Byte1]: 50
4152 13:53:45.953396
4153 13:53:45.956806 Final RX Vref Byte 0 = 57 to rank0
4154 13:53:45.961278 Final RX Vref Byte 1 = 50 to rank0
4155 13:53:45.963050 Final RX Vref Byte 0 = 57 to rank1
4156 13:53:45.966914 Final RX Vref Byte 1 = 50 to rank1==
4157 13:53:45.969834 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 13:53:45.973178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 13:53:45.973303 ==
4160 13:53:45.976382 DQS Delay:
4161 13:53:45.976484 DQS0 = 0, DQS1 = 0
4162 13:53:45.976576 DQM Delay:
4163 13:53:45.979561 DQM0 = 44, DQM1 = 36
4164 13:53:45.979633 DQ Delay:
4165 13:53:45.983028 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4166 13:53:45.986169 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4167 13:53:45.989644 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =28
4168 13:53:45.993646 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4169 13:53:45.993751
4170 13:53:45.993876
4171 13:53:46.003286 [DQSOSCAuto] RK0, (LSB)MR18= 0x453c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4172 13:53:46.005984 CH0 RK0: MR19=808, MR18=453C
4173 13:53:46.012524 CH0_RK0: MR19=0x808, MR18=0x453C, DQSOSC=396, MR23=63, INC=167, DEC=111
4174 13:53:46.012632
4175 13:53:46.015735 ----->DramcWriteLeveling(PI) begin...
4176 13:53:46.015809 ==
4177 13:53:46.019607 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 13:53:46.022211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 13:53:46.022311 ==
4180 13:53:46.026503 Write leveling (Byte 0): 32 => 32
4181 13:53:46.028878 Write leveling (Byte 1): 28 => 28
4182 13:53:46.032435 DramcWriteLeveling(PI) end<-----
4183 13:53:46.032533
4184 13:53:46.032624 ==
4185 13:53:46.035951 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 13:53:46.038940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 13:53:46.039048 ==
4188 13:53:46.042105 [Gating] SW mode calibration
4189 13:53:46.048774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4190 13:53:46.055490 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4191 13:53:46.059181 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 13:53:46.062191 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 13:53:46.068401 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 13:53:46.071995 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
4195 13:53:46.074903 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4196 13:53:46.081603 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 13:53:46.084822 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 13:53:46.087871 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 13:53:46.094632 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 13:53:46.097986 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 13:53:46.101300 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 13:53:46.108325 0 10 12 | B1->B0 | 2828 3939 | 0 0 | (0 0) (1 1)
4203 13:53:46.111350 0 10 16 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
4204 13:53:46.114139 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 13:53:46.121037 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 13:53:46.124126 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 13:53:46.130866 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 13:53:46.133925 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 13:53:46.137195 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 13:53:46.143668 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4211 13:53:46.147220 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 13:53:46.150320 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 13:53:46.156990 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 13:53:46.160697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 13:53:46.163425 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 13:53:46.170471 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 13:53:46.173430 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 13:53:46.176610 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 13:53:46.183884 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 13:53:46.186979 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 13:53:46.189722 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 13:53:46.196769 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 13:53:46.199806 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 13:53:46.203173 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 13:53:46.209554 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 13:53:46.213010 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 13:53:46.216106 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 13:53:46.219224 Total UI for P1: 0, mck2ui 16
4229 13:53:46.222565 best dqsien dly found for B0: ( 0, 13, 14)
4230 13:53:46.225894 Total UI for P1: 0, mck2ui 16
4231 13:53:46.229248 best dqsien dly found for B1: ( 0, 13, 14)
4232 13:53:46.232989 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4233 13:53:46.235994 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4234 13:53:46.236110
4235 13:53:46.242389 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4236 13:53:46.245972 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 13:53:46.249439 [Gating] SW calibration Done
4238 13:53:46.249525 ==
4239 13:53:46.252311 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 13:53:46.255784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 13:53:46.255870 ==
4242 13:53:46.255937 RX Vref Scan: 0
4243 13:53:46.256000
4244 13:53:46.259354 RX Vref 0 -> 0, step: 1
4245 13:53:46.259449
4246 13:53:46.262515 RX Delay -230 -> 252, step: 16
4247 13:53:46.265401 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4248 13:53:46.269078 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4249 13:53:46.275260 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4250 13:53:46.278981 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4251 13:53:46.282227 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4252 13:53:46.285336 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4253 13:53:46.292145 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4254 13:53:46.295848 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4255 13:53:46.298576 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4256 13:53:46.301747 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4257 13:53:46.308690 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4258 13:53:46.312130 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4259 13:53:46.315368 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4260 13:53:46.318155 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4261 13:53:46.324674 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4262 13:53:46.328030 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4263 13:53:46.328111 ==
4264 13:53:46.331229 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 13:53:46.334639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 13:53:46.334743 ==
4267 13:53:46.338670 DQS Delay:
4268 13:53:46.338753 DQS0 = 0, DQS1 = 0
4269 13:53:46.338852 DQM Delay:
4270 13:53:46.341652 DQM0 = 45, DQM1 = 36
4271 13:53:46.341762 DQ Delay:
4272 13:53:46.344394 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4273 13:53:46.348124 DQ4 =41, DQ5 =41, DQ6 =65, DQ7 =49
4274 13:53:46.351011 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4275 13:53:46.354652 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4276 13:53:46.354730
4277 13:53:46.354813
4278 13:53:46.354893 ==
4279 13:53:46.358342 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 13:53:46.364385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 13:53:46.364474 ==
4282 13:53:46.364557
4283 13:53:46.364636
4284 13:53:46.364712 TX Vref Scan disable
4285 13:53:46.368179 == TX Byte 0 ==
4286 13:53:46.372048 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4287 13:53:46.378171 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4288 13:53:46.378270 == TX Byte 1 ==
4289 13:53:46.381594 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4290 13:53:46.388471 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4291 13:53:46.388556 ==
4292 13:53:46.391262 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 13:53:46.394579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 13:53:46.394656 ==
4295 13:53:46.394739
4296 13:53:46.394817
4297 13:53:46.398194 TX Vref Scan disable
4298 13:53:46.401076 == TX Byte 0 ==
4299 13:53:46.405132 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4300 13:53:46.407590 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4301 13:53:46.411289 == TX Byte 1 ==
4302 13:53:46.414220 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4303 13:53:46.417743 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4304 13:53:46.417819
4305 13:53:46.420943 [DATLAT]
4306 13:53:46.421018 Freq=600, CH0 RK1
4307 13:53:46.421098
4308 13:53:46.424597 DATLAT Default: 0x9
4309 13:53:46.424674 0, 0xFFFF, sum = 0
4310 13:53:46.427774 1, 0xFFFF, sum = 0
4311 13:53:46.427850 2, 0xFFFF, sum = 0
4312 13:53:46.431219 3, 0xFFFF, sum = 0
4313 13:53:46.431294 4, 0xFFFF, sum = 0
4314 13:53:46.434173 5, 0xFFFF, sum = 0
4315 13:53:46.434248 6, 0xFFFF, sum = 0
4316 13:53:46.437033 7, 0xFFFF, sum = 0
4317 13:53:46.437111 8, 0x0, sum = 1
4318 13:53:46.440618 9, 0x0, sum = 2
4319 13:53:46.440695 10, 0x0, sum = 3
4320 13:53:46.443588 11, 0x0, sum = 4
4321 13:53:46.443664 best_step = 9
4322 13:53:46.443744
4323 13:53:46.443822 ==
4324 13:53:46.447065 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 13:53:46.450412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 13:53:46.454077 ==
4327 13:53:46.454152 RX Vref Scan: 0
4328 13:53:46.454233
4329 13:53:46.457309 RX Vref 0 -> 0, step: 1
4330 13:53:46.457416
4331 13:53:46.460376 RX Delay -179 -> 252, step: 8
4332 13:53:46.463856 iDelay=205, Bit 0, Center 44 (-99 ~ 188) 288
4333 13:53:46.466866 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4334 13:53:46.473624 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4335 13:53:46.476731 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4336 13:53:46.480116 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4337 13:53:46.483258 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4338 13:53:46.490021 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4339 13:53:46.493083 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4340 13:53:46.496506 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4341 13:53:46.499656 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4342 13:53:46.502962 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4343 13:53:46.510216 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4344 13:53:46.513973 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4345 13:53:46.516477 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4346 13:53:46.519925 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4347 13:53:46.526598 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4348 13:53:46.526718 ==
4349 13:53:46.530027 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 13:53:46.533051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 13:53:46.533127 ==
4352 13:53:46.533192 DQS Delay:
4353 13:53:46.536084 DQS0 = 0, DQS1 = 0
4354 13:53:46.536155 DQM Delay:
4355 13:53:46.539714 DQM0 = 43, DQM1 = 37
4356 13:53:46.539783 DQ Delay:
4357 13:53:46.542717 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4358 13:53:46.545908 DQ4 =48, DQ5 =32, DQ6 =52, DQ7 =48
4359 13:53:46.549250 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4360 13:53:46.552481 DQ12 =40, DQ13 =44, DQ14 =48, DQ15 =44
4361 13:53:46.552565
4362 13:53:46.552630
4363 13:53:46.562458 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4364 13:53:46.562549 CH0 RK1: MR19=808, MR18=3C38
4365 13:53:46.569077 CH0_RK1: MR19=0x808, MR18=0x3C38, DQSOSC=398, MR23=63, INC=165, DEC=110
4366 13:53:46.572121 [RxdqsGatingPostProcess] freq 600
4367 13:53:46.578908 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4368 13:53:46.582335 Pre-setting of DQS Precalculation
4369 13:53:46.585454 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4370 13:53:46.585556 ==
4371 13:53:46.589256 Dram Type= 6, Freq= 0, CH_1, rank 0
4372 13:53:46.595373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 13:53:46.595482 ==
4374 13:53:46.598411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 13:53:46.605318 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4376 13:53:46.608579 [CA 0] Center 35 (5~66) winsize 62
4377 13:53:46.611883 [CA 1] Center 35 (5~66) winsize 62
4378 13:53:46.615388 [CA 2] Center 34 (4~65) winsize 62
4379 13:53:46.619011 [CA 3] Center 34 (4~65) winsize 62
4380 13:53:46.622399 [CA 4] Center 34 (4~65) winsize 62
4381 13:53:46.625399 [CA 5] Center 34 (3~65) winsize 63
4382 13:53:46.625500
4383 13:53:46.628356 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4384 13:53:46.628447
4385 13:53:46.631745 [CATrainingPosCal] consider 1 rank data
4386 13:53:46.634757 u2DelayCellTimex100 = 270/100 ps
4387 13:53:46.638000 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4388 13:53:46.644819 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4389 13:53:46.647912 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 13:53:46.651131 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 13:53:46.654710 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 13:53:46.657692 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4393 13:53:46.657777
4394 13:53:46.661062 CA PerBit enable=1, Macro0, CA PI delay=34
4395 13:53:46.661145
4396 13:53:46.664770 [CBTSetCACLKResult] CA Dly = 34
4397 13:53:46.667878 CS Dly: 5 (0~36)
4398 13:53:46.667968 ==
4399 13:53:46.670910 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 13:53:46.674740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 13:53:46.674825 ==
4402 13:53:46.681122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 13:53:46.684204 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4404 13:53:46.688688 [CA 0] Center 35 (5~66) winsize 62
4405 13:53:46.691917 [CA 1] Center 35 (5~66) winsize 62
4406 13:53:46.695168 [CA 2] Center 34 (4~65) winsize 62
4407 13:53:46.698432 [CA 3] Center 34 (3~65) winsize 63
4408 13:53:46.701784 [CA 4] Center 34 (4~65) winsize 62
4409 13:53:46.705088 [CA 5] Center 34 (3~65) winsize 63
4410 13:53:46.705197
4411 13:53:46.708229 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4412 13:53:46.708332
4413 13:53:46.711584 [CATrainingPosCal] consider 2 rank data
4414 13:53:46.714732 u2DelayCellTimex100 = 270/100 ps
4415 13:53:46.718197 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4416 13:53:46.724551 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4417 13:53:46.728074 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 13:53:46.731242 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 13:53:46.734541 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 13:53:46.737734 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4421 13:53:46.737845
4422 13:53:46.741267 CA PerBit enable=1, Macro0, CA PI delay=34
4423 13:53:46.741407
4424 13:53:46.744297 [CBTSetCACLKResult] CA Dly = 34
4425 13:53:46.747846 CS Dly: 5 (0~37)
4426 13:53:46.747953
4427 13:53:46.751574 ----->DramcWriteLeveling(PI) begin...
4428 13:53:46.751665 ==
4429 13:53:46.754325 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 13:53:46.757676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 13:53:46.757842 ==
4432 13:53:46.760965 Write leveling (Byte 0): 29 => 29
4433 13:53:46.764109 Write leveling (Byte 1): 30 => 30
4434 13:53:46.768159 DramcWriteLeveling(PI) end<-----
4435 13:53:46.768269
4436 13:53:46.768367 ==
4437 13:53:46.771010 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 13:53:46.774848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 13:53:46.774937 ==
4440 13:53:46.778235 [Gating] SW mode calibration
4441 13:53:46.784370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4442 13:53:46.790466 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4443 13:53:46.794359 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 13:53:46.797109 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 13:53:46.804606 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 13:53:46.807133 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 1)
4447 13:53:46.810596 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 13:53:46.817035 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 13:53:46.820396 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 13:53:46.823588 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 13:53:46.830046 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 13:53:46.833521 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 13:53:46.836604 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4454 13:53:46.843184 0 10 12 | B1->B0 | 3030 3535 | 0 0 | (0 0) (0 0)
4455 13:53:46.846433 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 13:53:46.849467 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 13:53:46.856172 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 13:53:46.859687 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 13:53:46.865829 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 13:53:46.869032 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 13:53:46.872679 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 13:53:46.878917 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4463 13:53:46.882187 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 13:53:46.886346 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 13:53:46.892151 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 13:53:46.895563 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 13:53:46.899165 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 13:53:46.905661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 13:53:46.908677 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 13:53:46.912243 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 13:53:46.918811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 13:53:46.921708 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 13:53:46.925167 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 13:53:46.931398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 13:53:46.934933 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 13:53:46.938881 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 13:53:46.944763 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 13:53:46.948721 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4479 13:53:46.951657 Total UI for P1: 0, mck2ui 16
4480 13:53:46.954609 best dqsien dly found for B0: ( 0, 13, 10)
4481 13:53:46.958111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 13:53:46.961262 Total UI for P1: 0, mck2ui 16
4483 13:53:46.964317 best dqsien dly found for B1: ( 0, 13, 12)
4484 13:53:46.967587 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4485 13:53:46.971430 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4486 13:53:46.971551
4487 13:53:46.978028 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4488 13:53:46.981611 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4489 13:53:46.984693 [Gating] SW calibration Done
4490 13:53:46.984766 ==
4491 13:53:46.987585 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 13:53:46.990908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 13:53:46.991006 ==
4494 13:53:46.991095 RX Vref Scan: 0
4495 13:53:46.991187
4496 13:53:46.994486 RX Vref 0 -> 0, step: 1
4497 13:53:46.994561
4498 13:53:46.997296 RX Delay -230 -> 252, step: 16
4499 13:53:47.000925 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4500 13:53:47.007766 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4501 13:53:47.010531 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4502 13:53:47.014516 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4503 13:53:47.017495 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4504 13:53:47.020596 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4505 13:53:47.027272 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4506 13:53:47.030539 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4507 13:53:47.033940 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4508 13:53:47.037184 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4509 13:53:47.043920 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4510 13:53:47.047080 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4511 13:53:47.049995 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4512 13:53:47.053514 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4513 13:53:47.060519 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4514 13:53:47.063563 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4515 13:53:47.063661 ==
4516 13:53:47.066910 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 13:53:47.069808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 13:53:47.069891 ==
4519 13:53:47.073282 DQS Delay:
4520 13:53:47.073364 DQS0 = 0, DQS1 = 0
4521 13:53:47.073430 DQM Delay:
4522 13:53:47.076568 DQM0 = 40, DQM1 = 36
4523 13:53:47.076705 DQ Delay:
4524 13:53:47.079568 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4525 13:53:47.082876 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4526 13:53:47.086142 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4527 13:53:47.089960 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4528 13:53:47.090043
4529 13:53:47.090109
4530 13:53:47.090172 ==
4531 13:53:47.093153 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 13:53:47.099842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 13:53:47.099924 ==
4534 13:53:47.099990
4535 13:53:47.100050
4536 13:53:47.102693 TX Vref Scan disable
4537 13:53:47.102775 == TX Byte 0 ==
4538 13:53:47.105832 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4539 13:53:47.112717 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4540 13:53:47.112801 == TX Byte 1 ==
4541 13:53:47.116179 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 13:53:47.122483 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 13:53:47.122603 ==
4544 13:53:47.126415 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 13:53:47.129083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 13:53:47.129206 ==
4547 13:53:47.129308
4548 13:53:47.129410
4549 13:53:47.132342 TX Vref Scan disable
4550 13:53:47.135622 == TX Byte 0 ==
4551 13:53:47.138968 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4552 13:53:47.142184 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4553 13:53:47.145441 == TX Byte 1 ==
4554 13:53:47.149013 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4555 13:53:47.151993 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4556 13:53:47.152130
4557 13:53:47.155285 [DATLAT]
4558 13:53:47.155435 Freq=600, CH1 RK0
4559 13:53:47.155506
4560 13:53:47.158668 DATLAT Default: 0x9
4561 13:53:47.158777 0, 0xFFFF, sum = 0
4562 13:53:47.162625 1, 0xFFFF, sum = 0
4563 13:53:47.162712 2, 0xFFFF, sum = 0
4564 13:53:47.165973 3, 0xFFFF, sum = 0
4565 13:53:47.166062 4, 0xFFFF, sum = 0
4566 13:53:47.168877 5, 0xFFFF, sum = 0
4567 13:53:47.168964 6, 0xFFFF, sum = 0
4568 13:53:47.171923 7, 0xFFFF, sum = 0
4569 13:53:47.172059 8, 0x0, sum = 1
4570 13:53:47.175343 9, 0x0, sum = 2
4571 13:53:47.175468 10, 0x0, sum = 3
4572 13:53:47.178456 11, 0x0, sum = 4
4573 13:53:47.178566 best_step = 9
4574 13:53:47.178667
4575 13:53:47.178733 ==
4576 13:53:47.181755 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 13:53:47.188596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 13:53:47.188680 ==
4579 13:53:47.188745 RX Vref Scan: 1
4580 13:53:47.188805
4581 13:53:47.191595 RX Vref 0 -> 0, step: 1
4582 13:53:47.191707
4583 13:53:47.194670 RX Delay -195 -> 252, step: 8
4584 13:53:47.194775
4585 13:53:47.198112 Set Vref, RX VrefLevel [Byte0]: 52
4586 13:53:47.201303 [Byte1]: 52
4587 13:53:47.201386
4588 13:53:47.205307 Final RX Vref Byte 0 = 52 to rank0
4589 13:53:47.208684 Final RX Vref Byte 1 = 52 to rank0
4590 13:53:47.211466 Final RX Vref Byte 0 = 52 to rank1
4591 13:53:47.214621 Final RX Vref Byte 1 = 52 to rank1==
4592 13:53:47.218087 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 13:53:47.221906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 13:53:47.221993 ==
4595 13:53:47.224353 DQS Delay:
4596 13:53:47.224460 DQS0 = 0, DQS1 = 0
4597 13:53:47.227589 DQM Delay:
4598 13:53:47.227699 DQM0 = 43, DQM1 = 35
4599 13:53:47.231294 DQ Delay:
4600 13:53:47.231427 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4601 13:53:47.235068 DQ4 =40, DQ5 =48, DQ6 =56, DQ7 =36
4602 13:53:47.237731 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4603 13:53:47.241030 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4604 13:53:47.241112
4605 13:53:47.244431
4606 13:53:47.250918 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4607 13:53:47.254484 CH1 RK0: MR19=808, MR18=2E48
4608 13:53:47.260656 CH1_RK0: MR19=0x808, MR18=0x2E48, DQSOSC=396, MR23=63, INC=167, DEC=111
4609 13:53:47.260836
4610 13:53:47.264217 ----->DramcWriteLeveling(PI) begin...
4611 13:53:47.264468 ==
4612 13:53:47.267443 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 13:53:47.270287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 13:53:47.270447 ==
4615 13:53:47.273949 Write leveling (Byte 0): 30 => 30
4616 13:53:47.277211 Write leveling (Byte 1): 30 => 30
4617 13:53:47.280243 DramcWriteLeveling(PI) end<-----
4618 13:53:47.280402
4619 13:53:47.280504 ==
4620 13:53:47.284027 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 13:53:47.287477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 13:53:47.287668 ==
4623 13:53:47.290215 [Gating] SW mode calibration
4624 13:53:47.296610 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4625 13:53:47.303233 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4626 13:53:47.307151 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 13:53:47.313369 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 13:53:47.316512 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 13:53:47.320075 0 9 12 | B1->B0 | 3333 3030 | 1 0 | (1 0) (1 1)
4630 13:53:47.326796 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4631 13:53:47.329910 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 13:53:47.333037 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 13:53:47.339841 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 13:53:47.343476 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 13:53:47.346201 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 13:53:47.352662 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4637 13:53:47.355929 0 10 12 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
4638 13:53:47.359494 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4639 13:53:47.366332 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 13:53:47.369255 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 13:53:47.372458 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 13:53:47.379075 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 13:53:47.382400 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 13:53:47.385739 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4645 13:53:47.392246 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4646 13:53:47.395776 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 13:53:47.398666 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 13:53:47.405447 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 13:53:47.408918 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 13:53:47.411974 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 13:53:47.419297 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 13:53:47.422156 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 13:53:47.425392 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 13:53:47.431895 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 13:53:47.435309 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 13:53:47.438174 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 13:53:47.445013 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 13:53:47.448255 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 13:53:47.451420 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 13:53:47.458536 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 13:53:47.461735 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 13:53:47.464702 Total UI for P1: 0, mck2ui 16
4663 13:53:47.467973 best dqsien dly found for B0: ( 0, 13, 10)
4664 13:53:47.471282 Total UI for P1: 0, mck2ui 16
4665 13:53:47.474731 best dqsien dly found for B1: ( 0, 13, 10)
4666 13:53:47.477718 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4667 13:53:47.481108 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4668 13:53:47.481206
4669 13:53:47.484737 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4670 13:53:47.487856 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4671 13:53:47.490900 [Gating] SW calibration Done
4672 13:53:47.490998 ==
4673 13:53:47.494205 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 13:53:47.500613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 13:53:47.500724 ==
4676 13:53:47.500815 RX Vref Scan: 0
4677 13:53:47.500912
4678 13:53:47.504170 RX Vref 0 -> 0, step: 1
4679 13:53:47.504282
4680 13:53:47.507470 RX Delay -230 -> 252, step: 16
4681 13:53:47.510381 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4682 13:53:47.514064 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4683 13:53:47.520349 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4684 13:53:47.523815 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4685 13:53:47.527558 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4686 13:53:47.530144 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4687 13:53:47.534024 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4688 13:53:47.540271 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4689 13:53:47.543518 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4690 13:53:47.546788 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4691 13:53:47.550500 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4692 13:53:47.557080 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4693 13:53:47.560141 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4694 13:53:47.563297 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4695 13:53:47.566270 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4696 13:53:47.572985 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4697 13:53:47.573130 ==
4698 13:53:47.576390 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 13:53:47.579282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 13:53:47.579420 ==
4701 13:53:47.579509 DQS Delay:
4702 13:53:47.582546 DQS0 = 0, DQS1 = 0
4703 13:53:47.582644 DQM Delay:
4704 13:53:47.585957 DQM0 = 43, DQM1 = 40
4705 13:53:47.586101 DQ Delay:
4706 13:53:47.589928 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4707 13:53:47.593348 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4708 13:53:47.596168 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4709 13:53:47.599480 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4710 13:53:47.599562
4711 13:53:47.599626
4712 13:53:47.599685 ==
4713 13:53:47.602557 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 13:53:47.609068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 13:53:47.609231 ==
4716 13:53:47.609332
4717 13:53:47.609408
4718 13:53:47.609466 TX Vref Scan disable
4719 13:53:47.612727 == TX Byte 0 ==
4720 13:53:47.616101 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 13:53:47.622762 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 13:53:47.622882 == TX Byte 1 ==
4723 13:53:47.626171 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4724 13:53:47.632175 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4725 13:53:47.632286 ==
4726 13:53:47.635818 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 13:53:47.638685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 13:53:47.638791 ==
4729 13:53:47.638915
4730 13:53:47.639015
4731 13:53:47.642867 TX Vref Scan disable
4732 13:53:47.645673 == TX Byte 0 ==
4733 13:53:47.649114 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4734 13:53:47.652731 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4735 13:53:47.655799 == TX Byte 1 ==
4736 13:53:47.658617 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4737 13:53:47.661930 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4738 13:53:47.662018
4739 13:53:47.662085 [DATLAT]
4740 13:53:47.665928 Freq=600, CH1 RK1
4741 13:53:47.666013
4742 13:53:47.668725 DATLAT Default: 0x9
4743 13:53:47.668842 0, 0xFFFF, sum = 0
4744 13:53:47.672036 1, 0xFFFF, sum = 0
4745 13:53:47.672149 2, 0xFFFF, sum = 0
4746 13:53:47.675267 3, 0xFFFF, sum = 0
4747 13:53:47.675387 4, 0xFFFF, sum = 0
4748 13:53:47.678473 5, 0xFFFF, sum = 0
4749 13:53:47.678579 6, 0xFFFF, sum = 0
4750 13:53:47.681677 7, 0xFFFF, sum = 0
4751 13:53:47.681781 8, 0x0, sum = 1
4752 13:53:47.684915 9, 0x0, sum = 2
4753 13:53:47.685021 10, 0x0, sum = 3
4754 13:53:47.688820 11, 0x0, sum = 4
4755 13:53:47.688926 best_step = 9
4756 13:53:47.689018
4757 13:53:47.689108 ==
4758 13:53:47.691629 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 13:53:47.694833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 13:53:47.694933 ==
4761 13:53:47.698138 RX Vref Scan: 0
4762 13:53:47.698270
4763 13:53:47.701292 RX Vref 0 -> 0, step: 1
4764 13:53:47.701394
4765 13:53:47.701490 RX Delay -179 -> 252, step: 8
4766 13:53:47.709518 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4767 13:53:47.712845 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4768 13:53:47.716212 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4769 13:53:47.719346 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4770 13:53:47.726767 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4771 13:53:47.729227 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4772 13:53:47.732441 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4773 13:53:47.735924 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4774 13:53:47.742640 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4775 13:53:47.745548 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4776 13:53:47.748870 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4777 13:53:47.752003 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4778 13:53:47.759073 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4779 13:53:47.762095 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4780 13:53:47.765503 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4781 13:53:47.768973 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4782 13:53:47.769046 ==
4783 13:53:47.772407 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 13:53:47.778423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 13:53:47.778534 ==
4786 13:53:47.778631 DQS Delay:
4787 13:53:47.782161 DQS0 = 0, DQS1 = 0
4788 13:53:47.782275 DQM Delay:
4789 13:53:47.785531 DQM0 = 37, DQM1 = 36
4790 13:53:47.785630 DQ Delay:
4791 13:53:47.788650 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4792 13:53:47.792334 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4793 13:53:47.795271 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4794 13:53:47.798680 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4795 13:53:47.798783
4796 13:53:47.798872
4797 13:53:47.804936 [DQSOSCAuto] RK1, (LSB)MR18= 0x3055, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4798 13:53:47.808276 CH1 RK1: MR19=808, MR18=3055
4799 13:53:47.814686 CH1_RK1: MR19=0x808, MR18=0x3055, DQSOSC=393, MR23=63, INC=169, DEC=113
4800 13:53:47.818396 [RxdqsGatingPostProcess] freq 600
4801 13:53:47.824656 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4802 13:53:47.824759 Pre-setting of DQS Precalculation
4803 13:53:47.831544 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4804 13:53:47.837764 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4805 13:53:47.844431 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4806 13:53:47.844534
4807 13:53:47.844628
4808 13:53:47.847836 [Calibration Summary] 1200 Mbps
4809 13:53:47.851356 CH 0, Rank 0
4810 13:53:47.851462 SW Impedance : PASS
4811 13:53:47.854116 DUTY Scan : NO K
4812 13:53:47.857791 ZQ Calibration : PASS
4813 13:53:47.857874 Jitter Meter : NO K
4814 13:53:47.861097 CBT Training : PASS
4815 13:53:47.864205 Write leveling : PASS
4816 13:53:47.864287 RX DQS gating : PASS
4817 13:53:47.867709 RX DQ/DQS(RDDQC) : PASS
4818 13:53:47.871224 TX DQ/DQS : PASS
4819 13:53:47.871332 RX DATLAT : PASS
4820 13:53:47.874175 RX DQ/DQS(Engine): PASS
4821 13:53:47.877550 TX OE : NO K
4822 13:53:47.877634 All Pass.
4823 13:53:47.877699
4824 13:53:47.877758 CH 0, Rank 1
4825 13:53:47.880664 SW Impedance : PASS
4826 13:53:47.883768 DUTY Scan : NO K
4827 13:53:47.883849 ZQ Calibration : PASS
4828 13:53:47.887233 Jitter Meter : NO K
4829 13:53:47.887314 CBT Training : PASS
4830 13:53:47.890378 Write leveling : PASS
4831 13:53:47.894001 RX DQS gating : PASS
4832 13:53:47.894107 RX DQ/DQS(RDDQC) : PASS
4833 13:53:47.897392 TX DQ/DQS : PASS
4834 13:53:47.900568 RX DATLAT : PASS
4835 13:53:47.900675 RX DQ/DQS(Engine): PASS
4836 13:53:47.903896 TX OE : NO K
4837 13:53:47.903976 All Pass.
4838 13:53:47.904041
4839 13:53:47.907166 CH 1, Rank 0
4840 13:53:47.907247 SW Impedance : PASS
4841 13:53:47.910821 DUTY Scan : NO K
4842 13:53:47.914193 ZQ Calibration : PASS
4843 13:53:47.914275 Jitter Meter : NO K
4844 13:53:47.917271 CBT Training : PASS
4845 13:53:47.920109 Write leveling : PASS
4846 13:53:47.920194 RX DQS gating : PASS
4847 13:53:47.923521 RX DQ/DQS(RDDQC) : PASS
4848 13:53:47.927370 TX DQ/DQS : PASS
4849 13:53:47.927467 RX DATLAT : PASS
4850 13:53:47.929928 RX DQ/DQS(Engine): PASS
4851 13:53:47.933261 TX OE : NO K
4852 13:53:47.933346 All Pass.
4853 13:53:47.933412
4854 13:53:47.933471 CH 1, Rank 1
4855 13:53:47.936888 SW Impedance : PASS
4856 13:53:47.939910 DUTY Scan : NO K
4857 13:53:47.939990 ZQ Calibration : PASS
4858 13:53:47.943641 Jitter Meter : NO K
4859 13:53:47.946754 CBT Training : PASS
4860 13:53:47.946834 Write leveling : PASS
4861 13:53:47.950156 RX DQS gating : PASS
4862 13:53:47.953016 RX DQ/DQS(RDDQC) : PASS
4863 13:53:47.953100 TX DQ/DQS : PASS
4864 13:53:47.956247 RX DATLAT : PASS
4865 13:53:47.959650 RX DQ/DQS(Engine): PASS
4866 13:53:47.959731 TX OE : NO K
4867 13:53:47.959796 All Pass.
4868 13:53:47.963090
4869 13:53:47.963196 DramC Write-DBI off
4870 13:53:47.966309 PER_BANK_REFRESH: Hybrid Mode
4871 13:53:47.966391 TX_TRACKING: ON
4872 13:53:47.976588 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4873 13:53:47.979200 [FAST_K] Save calibration result to emmc
4874 13:53:47.982943 dramc_set_vcore_voltage set vcore to 662500
4875 13:53:47.985924 Read voltage for 933, 3
4876 13:53:47.986004 Vio18 = 0
4877 13:53:47.989329 Vcore = 662500
4878 13:53:47.989420 Vdram = 0
4879 13:53:47.989485 Vddq = 0
4880 13:53:47.989545 Vmddr = 0
4881 13:53:47.995736 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4882 13:53:48.002763 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4883 13:53:48.002845 MEM_TYPE=3, freq_sel=17
4884 13:53:48.006204 sv_algorithm_assistance_LP4_1600
4885 13:53:48.009403 ============ PULL DRAM RESETB DOWN ============
4886 13:53:48.015754 ========== PULL DRAM RESETB DOWN end =========
4887 13:53:48.018776 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4888 13:53:48.022284 ===================================
4889 13:53:48.025765 LPDDR4 DRAM CONFIGURATION
4890 13:53:48.028567 ===================================
4891 13:53:48.028649 EX_ROW_EN[0] = 0x0
4892 13:53:48.032303 EX_ROW_EN[1] = 0x0
4893 13:53:48.035542 LP4Y_EN = 0x0
4894 13:53:48.035623 WORK_FSP = 0x0
4895 13:53:48.038941 WL = 0x3
4896 13:53:48.039021 RL = 0x3
4897 13:53:48.041843 BL = 0x2
4898 13:53:48.041924 RPST = 0x0
4899 13:53:48.045558 RD_PRE = 0x0
4900 13:53:48.045639 WR_PRE = 0x1
4901 13:53:48.048515 WR_PST = 0x0
4902 13:53:48.048599 DBI_WR = 0x0
4903 13:53:48.052489 DBI_RD = 0x0
4904 13:53:48.052610 OTF = 0x1
4905 13:53:48.055090 ===================================
4906 13:53:48.058752 ===================================
4907 13:53:48.061839 ANA top config
4908 13:53:48.065058 ===================================
4909 13:53:48.068428 DLL_ASYNC_EN = 0
4910 13:53:48.068509 ALL_SLAVE_EN = 1
4911 13:53:48.071551 NEW_RANK_MODE = 1
4912 13:53:48.075107 DLL_IDLE_MODE = 1
4913 13:53:48.078168 LP45_APHY_COMB_EN = 1
4914 13:53:48.078270 TX_ODT_DIS = 1
4915 13:53:48.081614 NEW_8X_MODE = 1
4916 13:53:48.085061 ===================================
4917 13:53:48.087970 ===================================
4918 13:53:48.091145 data_rate = 1866
4919 13:53:48.094784 CKR = 1
4920 13:53:48.097999 DQ_P2S_RATIO = 8
4921 13:53:48.101729 ===================================
4922 13:53:48.104366 CA_P2S_RATIO = 8
4923 13:53:48.104439 DQ_CA_OPEN = 0
4924 13:53:48.107865 DQ_SEMI_OPEN = 0
4925 13:53:48.111411 CA_SEMI_OPEN = 0
4926 13:53:48.114619 CA_FULL_RATE = 0
4927 13:53:48.118117 DQ_CKDIV4_EN = 1
4928 13:53:48.120983 CA_CKDIV4_EN = 1
4929 13:53:48.121083 CA_PREDIV_EN = 0
4930 13:53:48.124510 PH8_DLY = 0
4931 13:53:48.127605 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4932 13:53:48.131297 DQ_AAMCK_DIV = 4
4933 13:53:48.134225 CA_AAMCK_DIV = 4
4934 13:53:48.137551 CA_ADMCK_DIV = 4
4935 13:53:48.137650 DQ_TRACK_CA_EN = 0
4936 13:53:48.140821 CA_PICK = 933
4937 13:53:48.144064 CA_MCKIO = 933
4938 13:53:48.147994 MCKIO_SEMI = 0
4939 13:53:48.150698 PLL_FREQ = 3732
4940 13:53:48.154272 DQ_UI_PI_RATIO = 32
4941 13:53:48.157696 CA_UI_PI_RATIO = 0
4942 13:53:48.160491 ===================================
4943 13:53:48.164077 ===================================
4944 13:53:48.164180 memory_type:LPDDR4
4945 13:53:48.167069 GP_NUM : 10
4946 13:53:48.170727 SRAM_EN : 1
4947 13:53:48.170823 MD32_EN : 0
4948 13:53:48.173711 ===================================
4949 13:53:48.177081 [ANA_INIT] >>>>>>>>>>>>>>
4950 13:53:48.180147 <<<<<< [CONFIGURE PHASE]: ANA_TX
4951 13:53:48.183889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4952 13:53:48.186853 ===================================
4953 13:53:48.190322 data_rate = 1866,PCW = 0X8f00
4954 13:53:48.193681 ===================================
4955 13:53:48.197099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4956 13:53:48.203308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 13:53:48.206910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 13:53:48.213253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4959 13:53:48.216226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4960 13:53:48.219620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4961 13:53:48.219701 [ANA_INIT] flow start
4962 13:53:48.222829 [ANA_INIT] PLL >>>>>>>>
4963 13:53:48.226058 [ANA_INIT] PLL <<<<<<<<
4964 13:53:48.226132 [ANA_INIT] MIDPI >>>>>>>>
4965 13:53:48.230180 [ANA_INIT] MIDPI <<<<<<<<
4966 13:53:48.232538 [ANA_INIT] DLL >>>>>>>>
4967 13:53:48.232616 [ANA_INIT] flow end
4968 13:53:48.239331 ============ LP4 DIFF to SE enter ============
4969 13:53:48.242653 ============ LP4 DIFF to SE exit ============
4970 13:53:48.245968 [ANA_INIT] <<<<<<<<<<<<<
4971 13:53:48.249432 [Flow] Enable top DCM control >>>>>
4972 13:53:48.253130 [Flow] Enable top DCM control <<<<<
4973 13:53:48.255855 Enable DLL master slave shuffle
4974 13:53:48.259015 ==============================================================
4975 13:53:48.262643 Gating Mode config
4976 13:53:48.265605 ==============================================================
4977 13:53:48.269113 Config description:
4978 13:53:48.278654 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4979 13:53:48.285880 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4980 13:53:48.288969 SELPH_MODE 0: By rank 1: By Phase
4981 13:53:48.295440 ==============================================================
4982 13:53:48.298983 GAT_TRACK_EN = 1
4983 13:53:48.302103 RX_GATING_MODE = 2
4984 13:53:48.305159 RX_GATING_TRACK_MODE = 2
4985 13:53:48.308710 SELPH_MODE = 1
4986 13:53:48.311505 PICG_EARLY_EN = 1
4987 13:53:48.315192 VALID_LAT_VALUE = 1
4988 13:53:48.318180 ==============================================================
4989 13:53:48.321514 Enter into Gating configuration >>>>
4990 13:53:48.324874 Exit from Gating configuration <<<<
4991 13:53:48.328463 Enter into DVFS_PRE_config >>>>>
4992 13:53:48.341110 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4993 13:53:48.344564 Exit from DVFS_PRE_config <<<<<
4994 13:53:48.348145 Enter into PICG configuration >>>>
4995 13:53:48.348223 Exit from PICG configuration <<<<
4996 13:53:48.351896 [RX_INPUT] configuration >>>>>
4997 13:53:48.354392 [RX_INPUT] configuration <<<<<
4998 13:53:48.360907 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4999 13:53:48.364346 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5000 13:53:48.371227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 13:53:48.377550 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 13:53:48.383932 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 13:53:48.390905 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 13:53:48.393855 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5005 13:53:48.397548 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5006 13:53:48.404108 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5007 13:53:48.407544 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5008 13:53:48.410312 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5009 13:53:48.413836 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 13:53:48.417322 ===================================
5011 13:53:48.420906 LPDDR4 DRAM CONFIGURATION
5012 13:53:48.423694 ===================================
5013 13:53:48.427355 EX_ROW_EN[0] = 0x0
5014 13:53:48.427461 EX_ROW_EN[1] = 0x0
5015 13:53:48.430559 LP4Y_EN = 0x0
5016 13:53:48.430626 WORK_FSP = 0x0
5017 13:53:48.433707 WL = 0x3
5018 13:53:48.433775 RL = 0x3
5019 13:53:48.437339 BL = 0x2
5020 13:53:48.437435 RPST = 0x0
5021 13:53:48.440372 RD_PRE = 0x0
5022 13:53:48.443548 WR_PRE = 0x1
5023 13:53:48.443619 WR_PST = 0x0
5024 13:53:48.446779 DBI_WR = 0x0
5025 13:53:48.446848 DBI_RD = 0x0
5026 13:53:48.449968 OTF = 0x1
5027 13:53:48.453641 ===================================
5028 13:53:48.456857 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5029 13:53:48.460223 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5030 13:53:48.463480 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 13:53:48.466650 ===================================
5032 13:53:48.470133 LPDDR4 DRAM CONFIGURATION
5033 13:53:48.473388 ===================================
5034 13:53:48.476820 EX_ROW_EN[0] = 0x10
5035 13:53:48.476894 EX_ROW_EN[1] = 0x0
5036 13:53:48.479615 LP4Y_EN = 0x0
5037 13:53:48.479685 WORK_FSP = 0x0
5038 13:53:48.483246 WL = 0x3
5039 13:53:48.483329 RL = 0x3
5040 13:53:48.486436 BL = 0x2
5041 13:53:48.489781 RPST = 0x0
5042 13:53:48.489852 RD_PRE = 0x0
5043 13:53:48.493150 WR_PRE = 0x1
5044 13:53:48.493246 WR_PST = 0x0
5045 13:53:48.496390 DBI_WR = 0x0
5046 13:53:48.496462 DBI_RD = 0x0
5047 13:53:48.499683 OTF = 0x1
5048 13:53:48.502680 ===================================
5049 13:53:48.509298 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5050 13:53:48.512737 nWR fixed to 30
5051 13:53:48.512809 [ModeRegInit_LP4] CH0 RK0
5052 13:53:48.515686 [ModeRegInit_LP4] CH0 RK1
5053 13:53:48.519311 [ModeRegInit_LP4] CH1 RK0
5054 13:53:48.519435 [ModeRegInit_LP4] CH1 RK1
5055 13:53:48.522809 match AC timing 9
5056 13:53:48.525662 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5057 13:53:48.529438 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5058 13:53:48.536149 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5059 13:53:48.538783 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5060 13:53:48.546560 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5061 13:53:48.546634 ==
5062 13:53:48.548959 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 13:53:48.552659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 13:53:48.552733 ==
5065 13:53:48.558970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 13:53:48.564956 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5067 13:53:48.568431 [CA 0] Center 38 (7~69) winsize 63
5068 13:53:48.572182 [CA 1] Center 37 (7~68) winsize 62
5069 13:53:48.575101 [CA 2] Center 35 (5~65) winsize 61
5070 13:53:48.578502 [CA 3] Center 34 (4~65) winsize 62
5071 13:53:48.581525 [CA 4] Center 33 (3~64) winsize 62
5072 13:53:48.584953 [CA 5] Center 33 (3~63) winsize 61
5073 13:53:48.585025
5074 13:53:48.588146 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5075 13:53:48.588215
5076 13:53:48.591605 [CATrainingPosCal] consider 1 rank data
5077 13:53:48.594675 u2DelayCellTimex100 = 270/100 ps
5078 13:53:48.597766 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5079 13:53:48.602064 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5080 13:53:48.605130 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5081 13:53:48.607913 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5082 13:53:48.611189 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5083 13:53:48.614503 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5084 13:53:48.617848
5085 13:53:48.621471 CA PerBit enable=1, Macro0, CA PI delay=33
5086 13:53:48.621541
5087 13:53:48.624445 [CBTSetCACLKResult] CA Dly = 33
5088 13:53:48.624518 CS Dly: 5 (0~36)
5089 13:53:48.624581 ==
5090 13:53:48.627853 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 13:53:48.631440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 13:53:48.634918 ==
5093 13:53:48.637982 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 13:53:48.643961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5095 13:53:48.647275 [CA 0] Center 38 (8~69) winsize 62
5096 13:53:48.650935 [CA 1] Center 37 (7~68) winsize 62
5097 13:53:48.653928 [CA 2] Center 35 (5~65) winsize 61
5098 13:53:48.657588 [CA 3] Center 34 (4~65) winsize 62
5099 13:53:48.660514 [CA 4] Center 33 (3~64) winsize 62
5100 13:53:48.663779 [CA 5] Center 33 (3~63) winsize 61
5101 13:53:48.663862
5102 13:53:48.667172 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5103 13:53:48.667279
5104 13:53:48.670281 [CATrainingPosCal] consider 2 rank data
5105 13:53:48.674391 u2DelayCellTimex100 = 270/100 ps
5106 13:53:48.677357 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5107 13:53:48.680283 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5108 13:53:48.683707 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5109 13:53:48.690600 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5110 13:53:48.694147 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5111 13:53:48.696813 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5112 13:53:48.696885
5113 13:53:48.700405 CA PerBit enable=1, Macro0, CA PI delay=33
5114 13:53:48.700502
5115 13:53:48.703314 [CBTSetCACLKResult] CA Dly = 33
5116 13:53:48.703429 CS Dly: 6 (0~39)
5117 13:53:48.703518
5118 13:53:48.706577 ----->DramcWriteLeveling(PI) begin...
5119 13:53:48.709930 ==
5120 13:53:48.713763 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 13:53:48.716554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 13:53:48.716626 ==
5123 13:53:48.719790 Write leveling (Byte 0): 31 => 31
5124 13:53:48.723225 Write leveling (Byte 1): 25 => 25
5125 13:53:48.726701 DramcWriteLeveling(PI) end<-----
5126 13:53:48.726769
5127 13:53:48.726829 ==
5128 13:53:48.729672 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 13:53:48.733353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 13:53:48.733447 ==
5131 13:53:48.736874 [Gating] SW mode calibration
5132 13:53:48.742921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5133 13:53:48.749540 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5134 13:53:48.753256 0 14 0 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 1)
5135 13:53:48.756536 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 13:53:48.762821 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 13:53:48.766236 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 13:53:48.768966 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 13:53:48.775573 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 13:53:48.779125 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5141 13:53:48.783084 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5142 13:53:48.788721 0 15 0 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
5143 13:53:48.792233 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5144 13:53:48.796171 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 13:53:48.802367 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 13:53:48.805348 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 13:53:48.808586 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 13:53:48.815401 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 13:53:48.818340 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
5150 13:53:48.821806 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5151 13:53:48.828300 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 13:53:48.831637 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 13:53:48.835014 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 13:53:48.841451 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 13:53:48.844870 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 13:53:48.848508 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5157 13:53:48.854880 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5158 13:53:48.858329 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5159 13:53:48.861841 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:53:48.868668 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 13:53:48.871604 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 13:53:48.874701 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 13:53:48.881188 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 13:53:48.884734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 13:53:48.887750 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 13:53:48.894307 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 13:53:48.897238 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 13:53:48.900767 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 13:53:48.907184 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 13:53:48.910712 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 13:53:48.913939 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 13:53:48.920767 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5173 13:53:48.923740 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5174 13:53:48.926963 Total UI for P1: 0, mck2ui 16
5175 13:53:48.930638 best dqsien dly found for B0: ( 1, 2, 24)
5176 13:53:48.934018 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5177 13:53:48.940157 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 13:53:48.944263 Total UI for P1: 0, mck2ui 16
5179 13:53:48.946872 best dqsien dly found for B1: ( 1, 2, 30)
5180 13:53:48.950207 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5181 13:53:48.953310 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5182 13:53:48.953381
5183 13:53:48.956555 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5184 13:53:48.960312 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5185 13:53:48.963145 [Gating] SW calibration Done
5186 13:53:48.963213 ==
5187 13:53:48.966645 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 13:53:48.969905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 13:53:48.970001 ==
5190 13:53:48.973627 RX Vref Scan: 0
5191 13:53:48.973699
5192 13:53:48.976397 RX Vref 0 -> 0, step: 1
5193 13:53:48.976498
5194 13:53:48.976590 RX Delay -80 -> 252, step: 8
5195 13:53:48.983636 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5196 13:53:48.986666 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5197 13:53:48.989892 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5198 13:53:48.993478 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5199 13:53:48.996414 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5200 13:53:48.999797 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5201 13:53:49.006369 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5202 13:53:49.009662 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5203 13:53:49.012715 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5204 13:53:49.015914 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5205 13:53:49.022777 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5206 13:53:49.026143 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5207 13:53:49.029098 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5208 13:53:49.032536 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5209 13:53:49.035981 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5210 13:53:49.039074 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5211 13:53:49.042986 ==
5212 13:53:49.045586 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 13:53:49.048956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 13:53:49.049030 ==
5215 13:53:49.049092 DQS Delay:
5216 13:53:49.052402 DQS0 = 0, DQS1 = 0
5217 13:53:49.052472 DQM Delay:
5218 13:53:49.055545 DQM0 = 103, DQM1 = 87
5219 13:53:49.055613 DQ Delay:
5220 13:53:49.058821 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5221 13:53:49.062182 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =107
5222 13:53:49.065501 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5223 13:53:49.068697 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5224 13:53:49.068766
5225 13:53:49.068844
5226 13:53:49.068904 ==
5227 13:53:49.072085 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 13:53:49.075541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 13:53:49.078557 ==
5230 13:53:49.078651
5231 13:53:49.078715
5232 13:53:49.078774 TX Vref Scan disable
5233 13:53:49.081707 == TX Byte 0 ==
5234 13:53:49.085286 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5235 13:53:49.088416 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5236 13:53:49.091966 == TX Byte 1 ==
5237 13:53:49.095017 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5238 13:53:49.101375 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5239 13:53:49.101453 ==
5240 13:53:49.105218 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 13:53:49.107952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 13:53:49.108022 ==
5243 13:53:49.108083
5244 13:53:49.108140
5245 13:53:49.111506 TX Vref Scan disable
5246 13:53:49.111574 == TX Byte 0 ==
5247 13:53:49.117903 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5248 13:53:49.121179 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5249 13:53:49.124471 == TX Byte 1 ==
5250 13:53:49.127848 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5251 13:53:49.131344 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5252 13:53:49.131462
5253 13:53:49.131525 [DATLAT]
5254 13:53:49.134483 Freq=933, CH0 RK0
5255 13:53:49.134550
5256 13:53:49.137780 DATLAT Default: 0xd
5257 13:53:49.137850 0, 0xFFFF, sum = 0
5258 13:53:49.140935 1, 0xFFFF, sum = 0
5259 13:53:49.141014 2, 0xFFFF, sum = 0
5260 13:53:49.144526 3, 0xFFFF, sum = 0
5261 13:53:49.144626 4, 0xFFFF, sum = 0
5262 13:53:49.147601 5, 0xFFFF, sum = 0
5263 13:53:49.147675 6, 0xFFFF, sum = 0
5264 13:53:49.150980 7, 0xFFFF, sum = 0
5265 13:53:49.151079 8, 0xFFFF, sum = 0
5266 13:53:49.154296 9, 0xFFFF, sum = 0
5267 13:53:49.154395 10, 0x0, sum = 1
5268 13:53:49.157472 11, 0x0, sum = 2
5269 13:53:49.157569 12, 0x0, sum = 3
5270 13:53:49.160707 13, 0x0, sum = 4
5271 13:53:49.160780 best_step = 11
5272 13:53:49.160841
5273 13:53:49.160903 ==
5274 13:53:49.164220 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 13:53:49.167784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 13:53:49.170859 ==
5277 13:53:49.170932 RX Vref Scan: 1
5278 13:53:49.170994
5279 13:53:49.174202 RX Vref 0 -> 0, step: 1
5280 13:53:49.174297
5281 13:53:49.177412 RX Delay -61 -> 252, step: 4
5282 13:53:49.177485
5283 13:53:49.180888 Set Vref, RX VrefLevel [Byte0]: 57
5284 13:53:49.183754 [Byte1]: 50
5285 13:53:49.183823
5286 13:53:49.186943 Final RX Vref Byte 0 = 57 to rank0
5287 13:53:49.190718 Final RX Vref Byte 1 = 50 to rank0
5288 13:53:49.193915 Final RX Vref Byte 0 = 57 to rank1
5289 13:53:49.197230 Final RX Vref Byte 1 = 50 to rank1==
5290 13:53:49.200909 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 13:53:49.203870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 13:53:49.203941 ==
5293 13:53:49.206952 DQS Delay:
5294 13:53:49.207021 DQS0 = 0, DQS1 = 0
5295 13:53:49.207081 DQM Delay:
5296 13:53:49.210330 DQM0 = 102, DQM1 = 90
5297 13:53:49.210399 DQ Delay:
5298 13:53:49.213569 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5299 13:53:49.216953 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =108
5300 13:53:49.220587 DQ8 =82, DQ9 =76, DQ10 =92, DQ11 =86
5301 13:53:49.223346 DQ12 =98, DQ13 =92, DQ14 =98, DQ15 =98
5302 13:53:49.223455
5303 13:53:49.223519
5304 13:53:49.233242 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5305 13:53:49.236354 CH0 RK0: MR19=505, MR18=1E18
5306 13:53:49.242932 CH0_RK0: MR19=0x505, MR18=0x1E18, DQSOSC=412, MR23=63, INC=63, DEC=42
5307 13:53:49.243029
5308 13:53:49.246181 ----->DramcWriteLeveling(PI) begin...
5309 13:53:49.246258 ==
5310 13:53:49.249918 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 13:53:49.253000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 13:53:49.253078 ==
5313 13:53:49.256647 Write leveling (Byte 0): 30 => 30
5314 13:53:49.259653 Write leveling (Byte 1): 28 => 28
5315 13:53:49.262745 DramcWriteLeveling(PI) end<-----
5316 13:53:49.262814
5317 13:53:49.262873 ==
5318 13:53:49.266195 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 13:53:49.269192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 13:53:49.269262 ==
5321 13:53:49.272718 [Gating] SW mode calibration
5322 13:53:49.279214 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5323 13:53:49.285729 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5324 13:53:49.289287 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5325 13:53:49.295753 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 13:53:49.298801 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 13:53:49.302174 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 13:53:49.308812 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 13:53:49.312662 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 13:53:49.315256 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 13:53:49.322220 0 14 28 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (1 0)
5332 13:53:49.325327 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5333 13:53:49.328327 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 13:53:49.335205 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 13:53:49.338556 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 13:53:49.342386 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 13:53:49.348473 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 13:53:49.351217 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5339 13:53:49.354737 0 15 28 | B1->B0 | 2c2c 3a3a | 0 0 | (0 0) (1 1)
5340 13:53:49.361596 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5341 13:53:49.364748 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 13:53:49.368277 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 13:53:49.374505 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 13:53:49.377888 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 13:53:49.381455 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 13:53:49.387501 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5347 13:53:49.390909 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5348 13:53:49.394409 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5349 13:53:49.401149 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 13:53:49.404043 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 13:53:49.407662 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 13:53:49.414081 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 13:53:49.417376 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 13:53:49.420887 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 13:53:49.426864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 13:53:49.430533 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 13:53:49.433839 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 13:53:49.440106 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 13:53:49.443306 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 13:53:49.447105 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 13:53:49.453433 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 13:53:49.456796 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5363 13:53:49.459955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5364 13:53:49.466557 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 13:53:49.466657 Total UI for P1: 0, mck2ui 16
5366 13:53:49.473252 best dqsien dly found for B0: ( 1, 2, 26)
5367 13:53:49.473324 Total UI for P1: 0, mck2ui 16
5368 13:53:49.479992 best dqsien dly found for B1: ( 1, 2, 30)
5369 13:53:49.483076 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5370 13:53:49.486923 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5371 13:53:49.486994
5372 13:53:49.489821 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5373 13:53:49.493287 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5374 13:53:49.496705 [Gating] SW calibration Done
5375 13:53:49.496779 ==
5376 13:53:49.499577 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 13:53:49.502892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 13:53:49.502991 ==
5379 13:53:49.506605 RX Vref Scan: 0
5380 13:53:49.506677
5381 13:53:49.506738 RX Vref 0 -> 0, step: 1
5382 13:53:49.506800
5383 13:53:49.509599 RX Delay -80 -> 252, step: 8
5384 13:53:49.516501 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5385 13:53:49.519637 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5386 13:53:49.522706 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5387 13:53:49.526267 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5388 13:53:49.529551 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5389 13:53:49.532687 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5390 13:53:49.540006 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5391 13:53:49.542610 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5392 13:53:49.545835 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5393 13:53:49.549517 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5394 13:53:49.552190 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5395 13:53:49.558879 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5396 13:53:49.562109 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5397 13:53:49.565331 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5398 13:53:49.568895 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5399 13:53:49.572402 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5400 13:53:49.572474 ==
5401 13:53:49.575319 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 13:53:49.582088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 13:53:49.582161 ==
5404 13:53:49.582223 DQS Delay:
5405 13:53:49.585216 DQS0 = 0, DQS1 = 0
5406 13:53:49.585284 DQM Delay:
5407 13:53:49.585355 DQM0 = 101, DQM1 = 89
5408 13:53:49.588862 DQ Delay:
5409 13:53:49.591863 DQ0 =103, DQ1 =107, DQ2 =95, DQ3 =99
5410 13:53:49.594960 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5411 13:53:49.598177 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5412 13:53:49.601990 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5413 13:53:49.602071
5414 13:53:49.602205
5415 13:53:49.602266 ==
5416 13:53:49.605091 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 13:53:49.608247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 13:53:49.608343 ==
5419 13:53:49.608408
5420 13:53:49.608468
5421 13:53:49.611446 TX Vref Scan disable
5422 13:53:49.614850 == TX Byte 0 ==
5423 13:53:49.618470 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5424 13:53:49.621487 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5425 13:53:49.625069 == TX Byte 1 ==
5426 13:53:49.628181 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5427 13:53:49.631237 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5428 13:53:49.631343 ==
5429 13:53:49.634624 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 13:53:49.641725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 13:53:49.641807 ==
5432 13:53:49.641872
5433 13:53:49.641931
5434 13:53:49.641989 TX Vref Scan disable
5435 13:53:49.645756 == TX Byte 0 ==
5436 13:53:49.651542 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5437 13:53:49.655491 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5438 13:53:49.655575 == TX Byte 1 ==
5439 13:53:49.658665 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5440 13:53:49.665766 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5441 13:53:49.665847
5442 13:53:49.665912 [DATLAT]
5443 13:53:49.665972 Freq=933, CH0 RK1
5444 13:53:49.666030
5445 13:53:49.668641 DATLAT Default: 0xb
5446 13:53:49.668728 0, 0xFFFF, sum = 0
5447 13:53:49.672120 1, 0xFFFF, sum = 0
5448 13:53:49.675288 2, 0xFFFF, sum = 0
5449 13:53:49.675394 3, 0xFFFF, sum = 0
5450 13:53:49.678457 4, 0xFFFF, sum = 0
5451 13:53:49.678547 5, 0xFFFF, sum = 0
5452 13:53:49.682021 6, 0xFFFF, sum = 0
5453 13:53:49.682103 7, 0xFFFF, sum = 0
5454 13:53:49.684823 8, 0xFFFF, sum = 0
5455 13:53:49.684908 9, 0xFFFF, sum = 0
5456 13:53:49.688416 10, 0x0, sum = 1
5457 13:53:49.688502 11, 0x0, sum = 2
5458 13:53:49.691563 12, 0x0, sum = 3
5459 13:53:49.691651 13, 0x0, sum = 4
5460 13:53:49.691717 best_step = 11
5461 13:53:49.695019
5462 13:53:49.695100 ==
5463 13:53:49.698497 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 13:53:49.701583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 13:53:49.701665 ==
5466 13:53:49.701730 RX Vref Scan: 0
5467 13:53:49.701790
5468 13:53:49.704680 RX Vref 0 -> 0, step: 1
5469 13:53:49.704761
5470 13:53:49.708389 RX Delay -61 -> 252, step: 4
5471 13:53:49.714862 iDelay=199, Bit 0, Center 102 (19 ~ 186) 168
5472 13:53:49.718144 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5473 13:53:49.721580 iDelay=199, Bit 2, Center 96 (11 ~ 182) 172
5474 13:53:49.724311 iDelay=199, Bit 3, Center 98 (11 ~ 186) 176
5475 13:53:49.727628 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5476 13:53:49.734574 iDelay=199, Bit 5, Center 92 (7 ~ 178) 172
5477 13:53:49.737949 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5478 13:53:49.741261 iDelay=199, Bit 7, Center 108 (23 ~ 194) 172
5479 13:53:49.744512 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5480 13:53:49.747454 iDelay=199, Bit 9, Center 80 (-5 ~ 166) 172
5481 13:53:49.751292 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5482 13:53:49.757921 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5483 13:53:49.760946 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5484 13:53:49.764222 iDelay=199, Bit 13, Center 96 (11 ~ 182) 172
5485 13:53:49.767613 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5486 13:53:49.773755 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5487 13:53:49.773861 ==
5488 13:53:49.777014 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 13:53:49.780676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 13:53:49.780758 ==
5491 13:53:49.780823 DQS Delay:
5492 13:53:49.783936 DQS0 = 0, DQS1 = 0
5493 13:53:49.784017 DQM Delay:
5494 13:53:49.787138 DQM0 = 101, DQM1 = 91
5495 13:53:49.787209 DQ Delay:
5496 13:53:49.790233 DQ0 =102, DQ1 =104, DQ2 =96, DQ3 =98
5497 13:53:49.794082 DQ4 =104, DQ5 =92, DQ6 =110, DQ7 =108
5498 13:53:49.797269 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =82
5499 13:53:49.800142 DQ12 =96, DQ13 =96, DQ14 =102, DQ15 =96
5500 13:53:49.800223
5501 13:53:49.800286
5502 13:53:49.810036 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5503 13:53:49.810118 CH0 RK1: MR19=505, MR18=1512
5504 13:53:49.816458 CH0_RK1: MR19=0x505, MR18=0x1512, DQSOSC=415, MR23=63, INC=62, DEC=41
5505 13:53:49.819690 [RxdqsGatingPostProcess] freq 933
5506 13:53:49.826660 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5507 13:53:49.829673 best DQS0 dly(2T, 0.5T) = (0, 10)
5508 13:53:49.832923 best DQS1 dly(2T, 0.5T) = (0, 10)
5509 13:53:49.836208 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5510 13:53:49.839694 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5511 13:53:49.843084 best DQS0 dly(2T, 0.5T) = (0, 10)
5512 13:53:49.846094 best DQS1 dly(2T, 0.5T) = (0, 10)
5513 13:53:49.849768 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5514 13:53:49.853566 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5515 13:53:49.853647 Pre-setting of DQS Precalculation
5516 13:53:49.859530 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5517 13:53:49.859611 ==
5518 13:53:49.862887 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 13:53:49.866638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 13:53:49.866725 ==
5521 13:53:49.872916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 13:53:49.879539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 13:53:49.882428 [CA 0] Center 36 (6~67) winsize 62
5524 13:53:49.886321 [CA 1] Center 36 (6~67) winsize 62
5525 13:53:49.889314 [CA 2] Center 34 (4~65) winsize 62
5526 13:53:49.892245 [CA 3] Center 33 (3~64) winsize 62
5527 13:53:49.895505 [CA 4] Center 34 (3~65) winsize 63
5528 13:53:49.899075 [CA 5] Center 33 (3~64) winsize 62
5529 13:53:49.899156
5530 13:53:49.902342 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 13:53:49.902423
5532 13:53:49.905453 [CATrainingPosCal] consider 1 rank data
5533 13:53:49.908888 u2DelayCellTimex100 = 270/100 ps
5534 13:53:49.912591 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 13:53:49.915706 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 13:53:49.919201 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5537 13:53:49.922177 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 13:53:49.928897 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5539 13:53:49.932064 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5540 13:53:49.932145
5541 13:53:49.935269 CA PerBit enable=1, Macro0, CA PI delay=33
5542 13:53:49.935354
5543 13:53:49.938705 [CBTSetCACLKResult] CA Dly = 33
5544 13:53:49.938787 CS Dly: 5 (0~36)
5545 13:53:49.938851 ==
5546 13:53:49.941913 Dram Type= 6, Freq= 0, CH_1, rank 1
5547 13:53:49.948748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 13:53:49.948830 ==
5549 13:53:49.951711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5550 13:53:49.958706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5551 13:53:49.961834 [CA 0] Center 36 (6~66) winsize 61
5552 13:53:49.965042 [CA 1] Center 36 (6~67) winsize 62
5553 13:53:49.968235 [CA 2] Center 34 (4~65) winsize 62
5554 13:53:49.971560 [CA 3] Center 33 (3~64) winsize 62
5555 13:53:49.974982 [CA 4] Center 34 (4~64) winsize 61
5556 13:53:49.978351 [CA 5] Center 33 (3~64) winsize 62
5557 13:53:49.978432
5558 13:53:49.981501 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5559 13:53:49.981582
5560 13:53:49.984515 [CATrainingPosCal] consider 2 rank data
5561 13:53:49.988473 u2DelayCellTimex100 = 270/100 ps
5562 13:53:49.991413 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5563 13:53:49.997773 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 13:53:50.001140 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 13:53:50.004839 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 13:53:50.007531 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5567 13:53:50.010803 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5568 13:53:50.010884
5569 13:53:50.014559 CA PerBit enable=1, Macro0, CA PI delay=33
5570 13:53:50.014665
5571 13:53:50.017379 [CBTSetCACLKResult] CA Dly = 33
5572 13:53:50.017464 CS Dly: 6 (0~38)
5573 13:53:50.020948
5574 13:53:50.024314 ----->DramcWriteLeveling(PI) begin...
5575 13:53:50.024399 ==
5576 13:53:50.027299 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 13:53:50.030860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 13:53:50.030941 ==
5579 13:53:50.034065 Write leveling (Byte 0): 29 => 29
5580 13:53:50.037275 Write leveling (Byte 1): 29 => 29
5581 13:53:50.040449 DramcWriteLeveling(PI) end<-----
5582 13:53:50.040529
5583 13:53:50.040597 ==
5584 13:53:50.044016 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 13:53:50.047298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 13:53:50.047410 ==
5587 13:53:50.050549 [Gating] SW mode calibration
5588 13:53:50.057261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5589 13:53:50.063907 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5590 13:53:50.066631 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 13:53:50.069825 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 13:53:50.076594 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 13:53:50.079836 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 13:53:50.083031 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 13:53:50.089785 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 13:53:50.093447 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
5597 13:53:50.096835 0 14 28 | B1->B0 | 2c2c 2828 | 0 0 | (0 1) (0 1)
5598 13:53:50.102852 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 13:53:50.106188 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 13:53:50.109491 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 13:53:50.116341 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 13:53:50.119280 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 13:53:50.122698 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 13:53:50.129373 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5605 13:53:50.132740 0 15 28 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
5606 13:53:50.135803 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 13:53:50.142485 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 13:53:50.145399 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 13:53:50.152116 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 13:53:50.156056 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 13:53:50.159517 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 13:53:50.165272 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 13:53:50.168491 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5614 13:53:50.172217 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5615 13:53:50.178667 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 13:53:50.181780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 13:53:50.185089 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 13:53:50.191508 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 13:53:50.195419 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 13:53:50.198291 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 13:53:50.204849 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 13:53:50.208109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 13:53:50.211356 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 13:53:50.218133 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 13:53:50.221252 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 13:53:50.224719 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 13:53:50.231125 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 13:53:50.235188 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5629 13:53:50.238105 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5630 13:53:50.244816 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5631 13:53:50.244923 Total UI for P1: 0, mck2ui 16
5632 13:53:50.247670 best dqsien dly found for B0: ( 1, 2, 26)
5633 13:53:50.254523 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 13:53:50.257436 Total UI for P1: 0, mck2ui 16
5635 13:53:50.260770 best dqsien dly found for B1: ( 1, 2, 30)
5636 13:53:50.264287 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5637 13:53:50.267881 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5638 13:53:50.267961
5639 13:53:50.272059 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5640 13:53:50.274321 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5641 13:53:50.277418 [Gating] SW calibration Done
5642 13:53:50.277499 ==
5643 13:53:50.280781 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 13:53:50.284473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 13:53:50.287595 ==
5646 13:53:50.287677 RX Vref Scan: 0
5647 13:53:50.287741
5648 13:53:50.290889 RX Vref 0 -> 0, step: 1
5649 13:53:50.290970
5650 13:53:50.293835 RX Delay -80 -> 252, step: 8
5651 13:53:50.297558 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5652 13:53:50.300414 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5653 13:53:50.303746 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5654 13:53:50.306793 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5655 13:53:50.310467 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5656 13:53:50.316984 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5657 13:53:50.320059 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5658 13:53:50.323551 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5659 13:53:50.326551 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5660 13:53:50.330098 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5661 13:53:50.333717 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5662 13:53:50.339610 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5663 13:53:50.343168 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5664 13:53:50.346487 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5665 13:53:50.350229 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5666 13:53:50.352976 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5667 13:53:50.356598 ==
5668 13:53:50.356679 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 13:53:50.362790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 13:53:50.362872 ==
5671 13:53:50.362936 DQS Delay:
5672 13:53:50.366151 DQS0 = 0, DQS1 = 0
5673 13:53:50.366235 DQM Delay:
5674 13:53:50.369330 DQM0 = 99, DQM1 = 96
5675 13:53:50.369411 DQ Delay:
5676 13:53:50.372879 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5677 13:53:50.376181 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5678 13:53:50.379515 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5679 13:53:50.382587 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5680 13:53:50.382693
5681 13:53:50.382785
5682 13:53:50.382847 ==
5683 13:53:50.385910 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 13:53:50.388900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 13:53:50.392634 ==
5686 13:53:50.392720
5687 13:53:50.392804
5688 13:53:50.392868 TX Vref Scan disable
5689 13:53:50.395863 == TX Byte 0 ==
5690 13:53:50.398836 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5691 13:53:50.402370 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5692 13:53:50.405738 == TX Byte 1 ==
5693 13:53:50.409169 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5694 13:53:50.415546 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5695 13:53:50.415633 ==
5696 13:53:50.418360 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 13:53:50.422013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 13:53:50.422111 ==
5699 13:53:50.422200
5700 13:53:50.422285
5701 13:53:50.425350 TX Vref Scan disable
5702 13:53:50.425451 == TX Byte 0 ==
5703 13:53:50.431729 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5704 13:53:50.435546 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5705 13:53:50.435620 == TX Byte 1 ==
5706 13:53:50.441806 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5707 13:53:50.445044 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5708 13:53:50.445242
5709 13:53:50.445310 [DATLAT]
5710 13:53:50.448328 Freq=933, CH1 RK0
5711 13:53:50.448409
5712 13:53:50.448474 DATLAT Default: 0xd
5713 13:53:50.451368 0, 0xFFFF, sum = 0
5714 13:53:50.454762 1, 0xFFFF, sum = 0
5715 13:53:50.454848 2, 0xFFFF, sum = 0
5716 13:53:50.458602 3, 0xFFFF, sum = 0
5717 13:53:50.458687 4, 0xFFFF, sum = 0
5718 13:53:50.461752 5, 0xFFFF, sum = 0
5719 13:53:50.461834 6, 0xFFFF, sum = 0
5720 13:53:50.465228 7, 0xFFFF, sum = 0
5721 13:53:50.465310 8, 0xFFFF, sum = 0
5722 13:53:50.467955 9, 0xFFFF, sum = 0
5723 13:53:50.468041 10, 0x0, sum = 1
5724 13:53:50.471601 11, 0x0, sum = 2
5725 13:53:50.471686 12, 0x0, sum = 3
5726 13:53:50.475384 13, 0x0, sum = 4
5727 13:53:50.475479 best_step = 11
5728 13:53:50.475543
5729 13:53:50.475603 ==
5730 13:53:50.478069 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 13:53:50.481494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 13:53:50.481576 ==
5733 13:53:50.484686 RX Vref Scan: 1
5734 13:53:50.484766
5735 13:53:50.487730 RX Vref 0 -> 0, step: 1
5736 13:53:50.487810
5737 13:53:50.487874 RX Delay -53 -> 252, step: 4
5738 13:53:50.487934
5739 13:53:50.491555 Set Vref, RX VrefLevel [Byte0]: 52
5740 13:53:50.494978 [Byte1]: 52
5741 13:53:50.499922
5742 13:53:50.500002 Final RX Vref Byte 0 = 52 to rank0
5743 13:53:50.503879 Final RX Vref Byte 1 = 52 to rank0
5744 13:53:50.506031 Final RX Vref Byte 0 = 52 to rank1
5745 13:53:50.509798 Final RX Vref Byte 1 = 52 to rank1==
5746 13:53:50.512910 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 13:53:50.519255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 13:53:50.519370 ==
5749 13:53:50.519467 DQS Delay:
5750 13:53:50.522249 DQS0 = 0, DQS1 = 0
5751 13:53:50.522329 DQM Delay:
5752 13:53:50.522393 DQM0 = 98, DQM1 = 95
5753 13:53:50.526192 DQ Delay:
5754 13:53:50.528845 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =98
5755 13:53:50.532664 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5756 13:53:50.535821 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =88
5757 13:53:50.539276 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5758 13:53:50.539347
5759 13:53:50.539447
5760 13:53:50.545170 [DQSOSCAuto] RK0, (LSB)MR18= 0x818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5761 13:53:50.548682 CH1 RK0: MR19=505, MR18=818
5762 13:53:50.555444 CH1_RK0: MR19=0x505, MR18=0x818, DQSOSC=414, MR23=63, INC=63, DEC=42
5763 13:53:50.555521
5764 13:53:50.558544 ----->DramcWriteLeveling(PI) begin...
5765 13:53:50.558619 ==
5766 13:53:50.561869 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 13:53:50.565170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 13:53:50.565260 ==
5769 13:53:50.568591 Write leveling (Byte 0): 29 => 29
5770 13:53:50.571395 Write leveling (Byte 1): 29 => 29
5771 13:53:50.575137 DramcWriteLeveling(PI) end<-----
5772 13:53:50.575233
5773 13:53:50.575323 ==
5774 13:53:50.578459 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 13:53:50.584981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 13:53:50.585055 ==
5777 13:53:50.585117 [Gating] SW mode calibration
5778 13:53:50.595056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5779 13:53:50.598232 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5780 13:53:50.604712 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 13:53:50.607839 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 13:53:50.611338 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 13:53:50.617824 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 13:53:50.620771 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 13:53:50.624198 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 13:53:50.630726 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
5787 13:53:50.634560 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5788 13:53:50.637500 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 13:53:50.643816 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 13:53:50.647319 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 13:53:50.650544 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 13:53:50.657005 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 13:53:50.660231 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 13:53:50.663574 0 15 24 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
5795 13:53:50.670589 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5796 13:53:50.673519 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 13:53:50.676897 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 13:53:50.683321 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 13:53:50.687129 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 13:53:50.690057 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 13:53:50.696701 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 13:53:50.700268 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 13:53:50.703145 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5804 13:53:50.710554 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5805 13:53:50.713503 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 13:53:50.716384 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 13:53:50.723316 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 13:53:50.725923 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 13:53:50.729150 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 13:53:50.735839 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 13:53:50.739922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 13:53:50.742826 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 13:53:50.748969 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 13:53:50.752420 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 13:53:50.755867 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 13:53:50.762514 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 13:53:50.765886 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 13:53:50.769029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 13:53:50.775687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5820 13:53:50.775767 Total UI for P1: 0, mck2ui 16
5821 13:53:50.782197 best dqsien dly found for B0: ( 1, 2, 26)
5822 13:53:50.785754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 13:53:50.788661 Total UI for P1: 0, mck2ui 16
5824 13:53:50.792160 best dqsien dly found for B1: ( 1, 2, 28)
5825 13:53:50.795523 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5826 13:53:50.798681 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5827 13:53:50.798763
5828 13:53:50.802072 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5829 13:53:50.805503 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5830 13:53:50.808725 [Gating] SW calibration Done
5831 13:53:50.808806 ==
5832 13:53:50.812355 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 13:53:50.815317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 13:53:50.818805 ==
5835 13:53:50.818886 RX Vref Scan: 0
5836 13:53:50.818954
5837 13:53:50.822058 RX Vref 0 -> 0, step: 1
5838 13:53:50.822144
5839 13:53:50.825019 RX Delay -80 -> 252, step: 8
5840 13:53:50.828131 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5841 13:53:50.832485 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5842 13:53:50.835262 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5843 13:53:50.838319 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5844 13:53:50.845220 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5845 13:53:50.848250 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5846 13:53:50.851516 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5847 13:53:50.854823 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5848 13:53:50.858315 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5849 13:53:50.861296 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5850 13:53:50.867789 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5851 13:53:50.870910 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5852 13:53:50.874385 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5853 13:53:50.877484 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5854 13:53:50.880965 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5855 13:53:50.887754 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5856 13:53:50.887839 ==
5857 13:53:50.891285 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 13:53:50.894329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 13:53:50.894410 ==
5860 13:53:50.894475 DQS Delay:
5861 13:53:50.897620 DQS0 = 0, DQS1 = 0
5862 13:53:50.897704 DQM Delay:
5863 13:53:50.900588 DQM0 = 97, DQM1 = 94
5864 13:53:50.900668 DQ Delay:
5865 13:53:50.904136 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5866 13:53:50.907388 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5867 13:53:50.910658 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5868 13:53:50.913966 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5869 13:53:50.914063
5870 13:53:50.914152
5871 13:53:50.914238 ==
5872 13:53:50.917291 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 13:53:50.923750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 13:53:50.923824 ==
5875 13:53:50.923889
5876 13:53:50.923946
5877 13:53:50.924002 TX Vref Scan disable
5878 13:53:50.927310 == TX Byte 0 ==
5879 13:53:50.930435 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5880 13:53:50.936876 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5881 13:53:50.936948 == TX Byte 1 ==
5882 13:53:50.940383 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5883 13:53:50.946888 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5884 13:53:50.946989 ==
5885 13:53:50.950603 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 13:53:50.953598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 13:53:50.953704 ==
5888 13:53:50.953796
5889 13:53:50.953882
5890 13:53:50.956881 TX Vref Scan disable
5891 13:53:50.956981 == TX Byte 0 ==
5892 13:53:50.963669 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5893 13:53:50.966882 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5894 13:53:50.966956 == TX Byte 1 ==
5895 13:53:50.973187 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5896 13:53:50.976528 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5897 13:53:50.976602
5898 13:53:50.976668 [DATLAT]
5899 13:53:50.979814 Freq=933, CH1 RK1
5900 13:53:50.979909
5901 13:53:50.979996 DATLAT Default: 0xb
5902 13:53:50.983081 0, 0xFFFF, sum = 0
5903 13:53:50.983153 1, 0xFFFF, sum = 0
5904 13:53:50.987243 2, 0xFFFF, sum = 0
5905 13:53:50.989775 3, 0xFFFF, sum = 0
5906 13:53:50.989846 4, 0xFFFF, sum = 0
5907 13:53:50.993247 5, 0xFFFF, sum = 0
5908 13:53:50.993316 6, 0xFFFF, sum = 0
5909 13:53:50.996828 7, 0xFFFF, sum = 0
5910 13:53:50.996924 8, 0xFFFF, sum = 0
5911 13:53:50.999938 9, 0xFFFF, sum = 0
5912 13:53:51.000011 10, 0x0, sum = 1
5913 13:53:51.003330 11, 0x0, sum = 2
5914 13:53:51.003446 12, 0x0, sum = 3
5915 13:53:51.006255 13, 0x0, sum = 4
5916 13:53:51.006325 best_step = 11
5917 13:53:51.006384
5918 13:53:51.006441 ==
5919 13:53:51.009801 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 13:53:51.012780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 13:53:51.012848 ==
5922 13:53:51.015966 RX Vref Scan: 0
5923 13:53:51.016034
5924 13:53:51.019721 RX Vref 0 -> 0, step: 1
5925 13:53:51.019788
5926 13:53:51.019852 RX Delay -53 -> 252, step: 4
5927 13:53:51.027749 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5928 13:53:51.030347 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5929 13:53:51.033914 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5930 13:53:51.037450 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5931 13:53:51.040581 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5932 13:53:51.047210 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5933 13:53:51.050922 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5934 13:53:51.053574 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5935 13:53:51.057003 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5936 13:53:51.060684 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5937 13:53:51.063781 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5938 13:53:51.070485 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5939 13:53:51.073392 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5940 13:53:51.076854 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5941 13:53:51.080436 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5942 13:53:51.086466 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5943 13:53:51.086544 ==
5944 13:53:51.090231 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 13:53:51.093365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 13:53:51.093434 ==
5947 13:53:51.093506 DQS Delay:
5948 13:53:51.096752 DQS0 = 0, DQS1 = 0
5949 13:53:51.096821 DQM Delay:
5950 13:53:51.100102 DQM0 = 97, DQM1 = 92
5951 13:53:51.100169 DQ Delay:
5952 13:53:51.103351 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =94
5953 13:53:51.106665 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5954 13:53:51.109726 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5955 13:53:51.112956 DQ12 =102, DQ13 =102, DQ14 =96, DQ15 =102
5956 13:53:51.113028
5957 13:53:51.113087
5958 13:53:51.122922 [DQSOSCAuto] RK1, (LSB)MR18= 0xa20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5959 13:53:51.122994 CH1 RK1: MR19=505, MR18=A20
5960 13:53:51.129965 CH1_RK1: MR19=0x505, MR18=0xA20, DQSOSC=411, MR23=63, INC=64, DEC=42
5961 13:53:51.132992 [RxdqsGatingPostProcess] freq 933
5962 13:53:51.139670 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5963 13:53:51.142753 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 13:53:51.146337 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 13:53:51.149031 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 13:53:51.152659 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 13:53:51.155787 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 13:53:51.155872 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 13:53:51.159570 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 13:53:51.162594 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 13:53:51.165876 Pre-setting of DQS Precalculation
5972 13:53:51.172588 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5973 13:53:51.178599 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5974 13:53:51.185424 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5975 13:53:51.185509
5976 13:53:51.185574
5977 13:53:51.189215 [Calibration Summary] 1866 Mbps
5978 13:53:51.192124 CH 0, Rank 0
5979 13:53:51.192196 SW Impedance : PASS
5980 13:53:51.195320 DUTY Scan : NO K
5981 13:53:51.198390 ZQ Calibration : PASS
5982 13:53:51.198466 Jitter Meter : NO K
5983 13:53:51.201808 CBT Training : PASS
5984 13:53:51.205218 Write leveling : PASS
5985 13:53:51.205290 RX DQS gating : PASS
5986 13:53:51.208659 RX DQ/DQS(RDDQC) : PASS
5987 13:53:51.208729 TX DQ/DQS : PASS
5988 13:53:51.211573 RX DATLAT : PASS
5989 13:53:51.215384 RX DQ/DQS(Engine): PASS
5990 13:53:51.215472 TX OE : NO K
5991 13:53:51.218114 All Pass.
5992 13:53:51.218185
5993 13:53:51.218245 CH 0, Rank 1
5994 13:53:51.221519 SW Impedance : PASS
5995 13:53:51.221589 DUTY Scan : NO K
5996 13:53:51.224643 ZQ Calibration : PASS
5997 13:53:51.228726 Jitter Meter : NO K
5998 13:53:51.228797 CBT Training : PASS
5999 13:53:51.231741 Write leveling : PASS
6000 13:53:51.234915 RX DQS gating : PASS
6001 13:53:51.234996 RX DQ/DQS(RDDQC) : PASS
6002 13:53:51.238213 TX DQ/DQS : PASS
6003 13:53:51.241967 RX DATLAT : PASS
6004 13:53:51.242075 RX DQ/DQS(Engine): PASS
6005 13:53:51.244561 TX OE : NO K
6006 13:53:51.244665 All Pass.
6007 13:53:51.244732
6008 13:53:51.248345 CH 1, Rank 0
6009 13:53:51.248426 SW Impedance : PASS
6010 13:53:51.251402 DUTY Scan : NO K
6011 13:53:51.254432 ZQ Calibration : PASS
6012 13:53:51.254512 Jitter Meter : NO K
6013 13:53:51.257458 CBT Training : PASS
6014 13:53:51.260827 Write leveling : PASS
6015 13:53:51.260934 RX DQS gating : PASS
6016 13:53:51.264169 RX DQ/DQS(RDDQC) : PASS
6017 13:53:51.267486 TX DQ/DQS : PASS
6018 13:53:51.267568 RX DATLAT : PASS
6019 13:53:51.270646 RX DQ/DQS(Engine): PASS
6020 13:53:51.274108 TX OE : NO K
6021 13:53:51.274189 All Pass.
6022 13:53:51.274253
6023 13:53:51.274312 CH 1, Rank 1
6024 13:53:51.277581 SW Impedance : PASS
6025 13:53:51.280699 DUTY Scan : NO K
6026 13:53:51.280779 ZQ Calibration : PASS
6027 13:53:51.284195 Jitter Meter : NO K
6028 13:53:51.287251 CBT Training : PASS
6029 13:53:51.287330 Write leveling : PASS
6030 13:53:51.290639 RX DQS gating : PASS
6031 13:53:51.294090 RX DQ/DQS(RDDQC) : PASS
6032 13:53:51.294174 TX DQ/DQS : PASS
6033 13:53:51.297421 RX DATLAT : PASS
6034 13:53:51.297502 RX DQ/DQS(Engine): PASS
6035 13:53:51.300510 TX OE : NO K
6036 13:53:51.300591 All Pass.
6037 13:53:51.300655
6038 13:53:51.303748 DramC Write-DBI off
6039 13:53:51.307066 PER_BANK_REFRESH: Hybrid Mode
6040 13:53:51.307172 TX_TRACKING: ON
6041 13:53:51.316705 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6042 13:53:51.319986 [FAST_K] Save calibration result to emmc
6043 13:53:51.323568 dramc_set_vcore_voltage set vcore to 650000
6044 13:53:51.326650 Read voltage for 400, 6
6045 13:53:51.326759 Vio18 = 0
6046 13:53:51.329855 Vcore = 650000
6047 13:53:51.329958 Vdram = 0
6048 13:53:51.330048 Vddq = 0
6049 13:53:51.330140 Vmddr = 0
6050 13:53:51.336671 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6051 13:53:51.343240 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6052 13:53:51.343357 MEM_TYPE=3, freq_sel=20
6053 13:53:51.346412 sv_algorithm_assistance_LP4_800
6054 13:53:51.350169 ============ PULL DRAM RESETB DOWN ============
6055 13:53:51.357031 ========== PULL DRAM RESETB DOWN end =========
6056 13:53:51.359563 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6057 13:53:51.363310 ===================================
6058 13:53:51.366202 LPDDR4 DRAM CONFIGURATION
6059 13:53:51.370104 ===================================
6060 13:53:51.370185 EX_ROW_EN[0] = 0x0
6061 13:53:51.372897 EX_ROW_EN[1] = 0x0
6062 13:53:51.376031 LP4Y_EN = 0x0
6063 13:53:51.376112 WORK_FSP = 0x0
6064 13:53:51.379472 WL = 0x2
6065 13:53:51.379559 RL = 0x2
6066 13:53:51.383223 BL = 0x2
6067 13:53:51.383329 RPST = 0x0
6068 13:53:51.386132 RD_PRE = 0x0
6069 13:53:51.386213 WR_PRE = 0x1
6070 13:53:51.389242 WR_PST = 0x0
6071 13:53:51.389322 DBI_WR = 0x0
6072 13:53:51.392882 DBI_RD = 0x0
6073 13:53:51.392963 OTF = 0x1
6074 13:53:51.395912 ===================================
6075 13:53:51.398948 ===================================
6076 13:53:51.402448 ANA top config
6077 13:53:51.405742 ===================================
6078 13:53:51.409210 DLL_ASYNC_EN = 0
6079 13:53:51.409290 ALL_SLAVE_EN = 1
6080 13:53:51.412470 NEW_RANK_MODE = 1
6081 13:53:51.415876 DLL_IDLE_MODE = 1
6082 13:53:51.419495 LP45_APHY_COMB_EN = 1
6083 13:53:51.419576 TX_ODT_DIS = 1
6084 13:53:51.422552 NEW_8X_MODE = 1
6085 13:53:51.425439 ===================================
6086 13:53:51.429283 ===================================
6087 13:53:51.432439 data_rate = 800
6088 13:53:51.435944 CKR = 1
6089 13:53:51.438625 DQ_P2S_RATIO = 4
6090 13:53:51.441905 ===================================
6091 13:53:51.445327 CA_P2S_RATIO = 4
6092 13:53:51.448756 DQ_CA_OPEN = 0
6093 13:53:51.448837 DQ_SEMI_OPEN = 1
6094 13:53:51.451993 CA_SEMI_OPEN = 1
6095 13:53:51.455001 CA_FULL_RATE = 0
6096 13:53:51.458670 DQ_CKDIV4_EN = 0
6097 13:53:51.462005 CA_CKDIV4_EN = 1
6098 13:53:51.465520 CA_PREDIV_EN = 0
6099 13:53:51.465603 PH8_DLY = 0
6100 13:53:51.468106 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6101 13:53:51.471373 DQ_AAMCK_DIV = 0
6102 13:53:51.474772 CA_AAMCK_DIV = 0
6103 13:53:51.478124 CA_ADMCK_DIV = 4
6104 13:53:51.481294 DQ_TRACK_CA_EN = 0
6105 13:53:51.481406 CA_PICK = 800
6106 13:53:51.485029 CA_MCKIO = 400
6107 13:53:51.487980 MCKIO_SEMI = 400
6108 13:53:51.491396 PLL_FREQ = 3016
6109 13:53:51.494580 DQ_UI_PI_RATIO = 32
6110 13:53:51.497986 CA_UI_PI_RATIO = 32
6111 13:53:51.501067 ===================================
6112 13:53:51.504273 ===================================
6113 13:53:51.507535 memory_type:LPDDR4
6114 13:53:51.507607 GP_NUM : 10
6115 13:53:51.511007 SRAM_EN : 1
6116 13:53:51.511077 MD32_EN : 0
6117 13:53:51.514387 ===================================
6118 13:53:51.517753 [ANA_INIT] >>>>>>>>>>>>>>
6119 13:53:51.520867 <<<<<< [CONFIGURE PHASE]: ANA_TX
6120 13:53:51.524023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6121 13:53:51.527326 ===================================
6122 13:53:51.530769 data_rate = 800,PCW = 0X7400
6123 13:53:51.533971 ===================================
6124 13:53:51.536961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6125 13:53:51.544207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 13:53:51.553664 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 13:53:51.560723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6128 13:53:51.563715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6129 13:53:51.566701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6130 13:53:51.566775 [ANA_INIT] flow start
6131 13:53:51.570140 [ANA_INIT] PLL >>>>>>>>
6132 13:53:51.573481 [ANA_INIT] PLL <<<<<<<<
6133 13:53:51.573554 [ANA_INIT] MIDPI >>>>>>>>
6134 13:53:51.577024 [ANA_INIT] MIDPI <<<<<<<<
6135 13:53:51.579800 [ANA_INIT] DLL >>>>>>>>
6136 13:53:51.579876 [ANA_INIT] flow end
6137 13:53:51.586732 ============ LP4 DIFF to SE enter ============
6138 13:53:51.589968 ============ LP4 DIFF to SE exit ============
6139 13:53:51.593604 [ANA_INIT] <<<<<<<<<<<<<
6140 13:53:51.596447 [Flow] Enable top DCM control >>>>>
6141 13:53:51.599996 [Flow] Enable top DCM control <<<<<
6142 13:53:51.600092 Enable DLL master slave shuffle
6143 13:53:51.607080 ==============================================================
6144 13:53:51.609834 Gating Mode config
6145 13:53:51.613262 ==============================================================
6146 13:53:51.616227 Config description:
6147 13:53:51.626029 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6148 13:53:51.633282 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6149 13:53:51.636560 SELPH_MODE 0: By rank 1: By Phase
6150 13:53:51.642719 ==============================================================
6151 13:53:51.646422 GAT_TRACK_EN = 0
6152 13:53:51.649327 RX_GATING_MODE = 2
6153 13:53:51.652366 RX_GATING_TRACK_MODE = 2
6154 13:53:51.656015 SELPH_MODE = 1
6155 13:53:51.659136 PICG_EARLY_EN = 1
6156 13:53:51.659217 VALID_LAT_VALUE = 1
6157 13:53:51.665661 ==============================================================
6158 13:53:51.668869 Enter into Gating configuration >>>>
6159 13:53:51.672149 Exit from Gating configuration <<<<
6160 13:53:51.675331 Enter into DVFS_PRE_config >>>>>
6161 13:53:51.685676 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6162 13:53:51.688437 Exit from DVFS_PRE_config <<<<<
6163 13:53:51.692040 Enter into PICG configuration >>>>
6164 13:53:51.695566 Exit from PICG configuration <<<<
6165 13:53:51.698912 [RX_INPUT] configuration >>>>>
6166 13:53:51.701735 [RX_INPUT] configuration <<<<<
6167 13:53:51.708469 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6168 13:53:51.711983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6169 13:53:51.718524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 13:53:51.724928 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 13:53:51.731311 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 13:53:51.738389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 13:53:51.741502 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6174 13:53:51.744922 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6175 13:53:51.748040 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6176 13:53:51.754400 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6177 13:53:51.757942 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6178 13:53:51.760867 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 13:53:51.764193 ===================================
6180 13:53:51.767632 LPDDR4 DRAM CONFIGURATION
6181 13:53:51.770754 ===================================
6182 13:53:51.774278 EX_ROW_EN[0] = 0x0
6183 13:53:51.774347 EX_ROW_EN[1] = 0x0
6184 13:53:51.777435 LP4Y_EN = 0x0
6185 13:53:51.777504 WORK_FSP = 0x0
6186 13:53:51.781023 WL = 0x2
6187 13:53:51.781118 RL = 0x2
6188 13:53:51.784070 BL = 0x2
6189 13:53:51.784166 RPST = 0x0
6190 13:53:51.787087 RD_PRE = 0x0
6191 13:53:51.787180 WR_PRE = 0x1
6192 13:53:51.790696 WR_PST = 0x0
6193 13:53:51.793997 DBI_WR = 0x0
6194 13:53:51.794064 DBI_RD = 0x0
6195 13:53:51.797237 OTF = 0x1
6196 13:53:51.800329 ===================================
6197 13:53:51.804147 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6198 13:53:51.806997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6199 13:53:51.810767 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 13:53:51.813810 ===================================
6201 13:53:51.817086 LPDDR4 DRAM CONFIGURATION
6202 13:53:51.820068 ===================================
6203 13:53:51.823537 EX_ROW_EN[0] = 0x10
6204 13:53:51.823606 EX_ROW_EN[1] = 0x0
6205 13:53:51.826658 LP4Y_EN = 0x0
6206 13:53:51.826726 WORK_FSP = 0x0
6207 13:53:51.830412 WL = 0x2
6208 13:53:51.830506 RL = 0x2
6209 13:53:51.833351 BL = 0x2
6210 13:53:51.833420 RPST = 0x0
6211 13:53:51.836811 RD_PRE = 0x0
6212 13:53:51.840004 WR_PRE = 0x1
6213 13:53:51.840102 WR_PST = 0x0
6214 13:53:51.843414 DBI_WR = 0x0
6215 13:53:51.843487 DBI_RD = 0x0
6216 13:53:51.846379 OTF = 0x1
6217 13:53:51.849801 ===================================
6218 13:53:51.852819 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6219 13:53:51.858644 nWR fixed to 30
6220 13:53:51.862433 [ModeRegInit_LP4] CH0 RK0
6221 13:53:51.862501 [ModeRegInit_LP4] CH0 RK1
6222 13:53:51.865215 [ModeRegInit_LP4] CH1 RK0
6223 13:53:51.868612 [ModeRegInit_LP4] CH1 RK1
6224 13:53:51.868681 match AC timing 19
6225 13:53:51.875127 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6226 13:53:51.878525 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6227 13:53:51.881380 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6228 13:53:51.887963 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6229 13:53:51.891959 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6230 13:53:51.892030 ==
6231 13:53:51.894502 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 13:53:51.898187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 13:53:51.898282 ==
6234 13:53:51.904770 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 13:53:51.911205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 13:53:51.914592 [CA 0] Center 36 (8~64) winsize 57
6237 13:53:51.917894 [CA 1] Center 36 (8~64) winsize 57
6238 13:53:51.921108 [CA 2] Center 36 (8~64) winsize 57
6239 13:53:51.924741 [CA 3] Center 36 (8~64) winsize 57
6240 13:53:51.927544 [CA 4] Center 36 (8~64) winsize 57
6241 13:53:51.931188 [CA 5] Center 36 (8~64) winsize 57
6242 13:53:51.931262
6243 13:53:51.934617 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 13:53:51.934756
6245 13:53:51.937830 [CATrainingPosCal] consider 1 rank data
6246 13:53:51.941001 u2DelayCellTimex100 = 270/100 ps
6247 13:53:51.944337 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 13:53:51.947582 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 13:53:51.950654 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 13:53:51.954221 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 13:53:51.957325 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 13:53:51.960935 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 13:53:51.961022
6254 13:53:51.964216 CA PerBit enable=1, Macro0, CA PI delay=36
6255 13:53:51.967727
6256 13:53:51.967797 [CBTSetCACLKResult] CA Dly = 36
6257 13:53:51.970946 CS Dly: 1 (0~32)
6258 13:53:51.971017 ==
6259 13:53:51.974180 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 13:53:51.977200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 13:53:51.977271 ==
6262 13:53:51.984026 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 13:53:51.990298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6264 13:53:51.994146 [CA 0] Center 36 (8~64) winsize 57
6265 13:53:51.997224 [CA 1] Center 36 (8~64) winsize 57
6266 13:53:52.000643 [CA 2] Center 36 (8~64) winsize 57
6267 13:53:52.003411 [CA 3] Center 36 (8~64) winsize 57
6268 13:53:52.003516 [CA 4] Center 36 (8~64) winsize 57
6269 13:53:52.006911 [CA 5] Center 36 (8~64) winsize 57
6270 13:53:52.007009
6271 13:53:52.013628 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6272 13:53:52.013704
6273 13:53:52.016885 [CATrainingPosCal] consider 2 rank data
6274 13:53:52.020440 u2DelayCellTimex100 = 270/100 ps
6275 13:53:52.023348 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 13:53:52.026594 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 13:53:52.030044 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 13:53:52.033261 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 13:53:52.037269 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 13:53:52.040127 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 13:53:52.040200
6282 13:53:52.044433 CA PerBit enable=1, Macro0, CA PI delay=36
6283 13:53:52.044546
6284 13:53:52.046468 [CBTSetCACLKResult] CA Dly = 36
6285 13:53:52.049914 CS Dly: 1 (0~32)
6286 13:53:52.049987
6287 13:53:52.053099 ----->DramcWriteLeveling(PI) begin...
6288 13:53:52.053187 ==
6289 13:53:52.056605 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 13:53:52.059770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 13:53:52.059842 ==
6292 13:53:52.062995 Write leveling (Byte 0): 40 => 8
6293 13:53:52.066530 Write leveling (Byte 1): 40 => 8
6294 13:53:52.070088 DramcWriteLeveling(PI) end<-----
6295 13:53:52.070187
6296 13:53:52.070275 ==
6297 13:53:52.073338 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 13:53:52.076914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 13:53:52.076995 ==
6300 13:53:52.079317 [Gating] SW mode calibration
6301 13:53:52.086463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6302 13:53:52.093153 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6303 13:53:52.096254 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 13:53:52.102795 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 13:53:52.106070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 13:53:52.109614 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 13:53:52.115676 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 13:53:52.119304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 13:53:52.123035 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 13:53:52.129368 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 13:53:52.132860 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 13:53:52.135580 Total UI for P1: 0, mck2ui 16
6313 13:53:52.138838 best dqsien dly found for B0: ( 0, 14, 24)
6314 13:53:52.142077 Total UI for P1: 0, mck2ui 16
6315 13:53:52.145124 best dqsien dly found for B1: ( 0, 14, 24)
6316 13:53:52.148588 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6317 13:53:52.152453 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6318 13:53:52.152528
6319 13:53:52.155509 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 13:53:52.158348 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 13:53:52.161575 [Gating] SW calibration Done
6322 13:53:52.161646 ==
6323 13:53:52.165036 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 13:53:52.171616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 13:53:52.171691 ==
6326 13:53:52.171754 RX Vref Scan: 0
6327 13:53:52.171813
6328 13:53:52.174732 RX Vref 0 -> 0, step: 1
6329 13:53:52.174802
6330 13:53:52.178124 RX Delay -410 -> 252, step: 16
6331 13:53:52.181262 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6332 13:53:52.184531 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6333 13:53:52.191153 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6334 13:53:52.194422 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6335 13:53:52.198830 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6336 13:53:52.201288 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6337 13:53:52.208030 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6338 13:53:52.211100 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6339 13:53:52.214955 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6340 13:53:52.217670 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6341 13:53:52.224726 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6342 13:53:52.227474 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6343 13:53:52.230602 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6344 13:53:52.234034 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6345 13:53:52.240742 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6346 13:53:52.243928 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6347 13:53:52.244007 ==
6348 13:53:52.247577 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 13:53:52.250858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 13:53:52.250937 ==
6351 13:53:52.253859 DQS Delay:
6352 13:53:52.253930 DQS0 = 35, DQS1 = 51
6353 13:53:52.256912 DQM Delay:
6354 13:53:52.256981 DQM0 = 7, DQM1 = 11
6355 13:53:52.260711 DQ Delay:
6356 13:53:52.260778 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6357 13:53:52.263996 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6358 13:53:52.267064 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6359 13:53:52.270255 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6360 13:53:52.270324
6361 13:53:52.270382
6362 13:53:52.270438 ==
6363 13:53:52.273692 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 13:53:52.280484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 13:53:52.280554 ==
6366 13:53:52.280632
6367 13:53:52.280696
6368 13:53:52.280752 TX Vref Scan disable
6369 13:53:52.283353 == TX Byte 0 ==
6370 13:53:52.286987 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 13:53:52.290163 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 13:53:52.293688 == TX Byte 1 ==
6373 13:53:52.297232 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 13:53:52.300255 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 13:53:52.300336 ==
6376 13:53:52.303524 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 13:53:52.310315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 13:53:52.310390 ==
6379 13:53:52.310452
6380 13:53:52.310513
6381 13:53:52.313188 TX Vref Scan disable
6382 13:53:52.313261 == TX Byte 0 ==
6383 13:53:52.316688 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 13:53:52.323164 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 13:53:52.323236 == TX Byte 1 ==
6386 13:53:52.326869 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 13:53:52.329874 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 13:53:52.333357
6389 13:53:52.333424 [DATLAT]
6390 13:53:52.333483 Freq=400, CH0 RK0
6391 13:53:52.333540
6392 13:53:52.336280 DATLAT Default: 0xf
6393 13:53:52.336345 0, 0xFFFF, sum = 0
6394 13:53:52.339714 1, 0xFFFF, sum = 0
6395 13:53:52.339781 2, 0xFFFF, sum = 0
6396 13:53:52.343277 3, 0xFFFF, sum = 0
6397 13:53:52.346559 4, 0xFFFF, sum = 0
6398 13:53:52.346632 5, 0xFFFF, sum = 0
6399 13:53:52.349591 6, 0xFFFF, sum = 0
6400 13:53:52.349661 7, 0xFFFF, sum = 0
6401 13:53:52.353266 8, 0xFFFF, sum = 0
6402 13:53:52.353338 9, 0xFFFF, sum = 0
6403 13:53:52.356361 10, 0xFFFF, sum = 0
6404 13:53:52.356429 11, 0xFFFF, sum = 0
6405 13:53:52.359301 12, 0xFFFF, sum = 0
6406 13:53:52.359423 13, 0x0, sum = 1
6407 13:53:52.362825 14, 0x0, sum = 2
6408 13:53:52.362892 15, 0x0, sum = 3
6409 13:53:52.366241 16, 0x0, sum = 4
6410 13:53:52.366335 best_step = 14
6411 13:53:52.366420
6412 13:53:52.366503 ==
6413 13:53:52.370003 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 13:53:52.372883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 13:53:52.376438 ==
6416 13:53:52.376530 RX Vref Scan: 1
6417 13:53:52.376615
6418 13:53:52.379489 RX Vref 0 -> 0, step: 1
6419 13:53:52.379581
6420 13:53:52.382527 RX Delay -343 -> 252, step: 8
6421 13:53:52.382595
6422 13:53:52.385780 Set Vref, RX VrefLevel [Byte0]: 57
6423 13:53:52.389488 [Byte1]: 50
6424 13:53:52.389555
6425 13:53:52.392407 Final RX Vref Byte 0 = 57 to rank0
6426 13:53:52.395825 Final RX Vref Byte 1 = 50 to rank0
6427 13:53:52.398788 Final RX Vref Byte 0 = 57 to rank1
6428 13:53:52.402466 Final RX Vref Byte 1 = 50 to rank1==
6429 13:53:52.405376 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 13:53:52.409046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 13:53:52.412234 ==
6432 13:53:52.412331 DQS Delay:
6433 13:53:52.412419 DQS0 = 44, DQS1 = 56
6434 13:53:52.415172 DQM Delay:
6435 13:53:52.415292 DQM0 = 11, DQM1 = 14
6436 13:53:52.418870 DQ Delay:
6437 13:53:52.422277 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6438 13:53:52.422352 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6439 13:53:52.425633 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6440 13:53:52.428540 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6441 13:53:52.428608
6442 13:53:52.428667
6443 13:53:52.438621 [DQSOSCAuto] RK0, (LSB)MR18= 0x9185, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6444 13:53:52.442065 CH0 RK0: MR19=C0C, MR18=9185
6445 13:53:52.447995 CH0_RK0: MR19=0xC0C, MR18=0x9185, DQSOSC=391, MR23=63, INC=386, DEC=257
6446 13:53:52.448097 ==
6447 13:53:52.451394 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 13:53:52.455585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 13:53:52.455657 ==
6450 13:53:52.458500 [Gating] SW mode calibration
6451 13:53:52.464679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6452 13:53:52.471284 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6453 13:53:52.474735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 13:53:52.478090 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 13:53:52.484610 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 13:53:52.487532 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 13:53:52.490769 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 13:53:52.497557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 13:53:52.500667 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 13:53:52.504088 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 13:53:52.510446 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 13:53:52.510550 Total UI for P1: 0, mck2ui 16
6463 13:53:52.517215 best dqsien dly found for B0: ( 0, 14, 24)
6464 13:53:52.517411 Total UI for P1: 0, mck2ui 16
6465 13:53:52.523907 best dqsien dly found for B1: ( 0, 14, 24)
6466 13:53:52.527130 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6467 13:53:52.530394 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6468 13:53:52.530490
6469 13:53:52.533949 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 13:53:52.537098 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 13:53:52.540119 [Gating] SW calibration Done
6472 13:53:52.540200 ==
6473 13:53:52.543554 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 13:53:52.546811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 13:53:52.546918 ==
6476 13:53:52.550239 RX Vref Scan: 0
6477 13:53:52.550345
6478 13:53:52.553607 RX Vref 0 -> 0, step: 1
6479 13:53:52.553688
6480 13:53:52.553753 RX Delay -410 -> 252, step: 16
6481 13:53:52.560213 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6482 13:53:52.563213 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6483 13:53:52.566709 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6484 13:53:52.569916 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6485 13:53:52.576971 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6486 13:53:52.580375 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6487 13:53:52.583599 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6488 13:53:52.586570 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6489 13:53:52.593048 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6490 13:53:52.596245 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6491 13:53:52.599724 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6492 13:53:52.606106 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6493 13:53:52.609330 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6494 13:53:52.612585 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6495 13:53:52.616101 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6496 13:53:52.622935 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6497 13:53:52.623007 ==
6498 13:53:52.626117 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 13:53:52.629043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 13:53:52.629113 ==
6501 13:53:52.629172 DQS Delay:
6502 13:53:52.632877 DQS0 = 35, DQS1 = 59
6503 13:53:52.632944 DQM Delay:
6504 13:53:52.635776 DQM0 = 5, DQM1 = 17
6505 13:53:52.635843 DQ Delay:
6506 13:53:52.639035 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6507 13:53:52.642626 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6508 13:53:52.646037 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6509 13:53:52.649204 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6510 13:53:52.649278
6511 13:53:52.649338
6512 13:53:52.649395 ==
6513 13:53:52.652709 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 13:53:52.655658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 13:53:52.655738 ==
6516 13:53:52.655806
6517 13:53:52.655864
6518 13:53:52.658729 TX Vref Scan disable
6519 13:53:52.662703 == TX Byte 0 ==
6520 13:53:52.665518 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6521 13:53:52.668907 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6522 13:53:52.672032 == TX Byte 1 ==
6523 13:53:52.675486 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6524 13:53:52.678844 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6525 13:53:52.678956 ==
6526 13:53:52.681859 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 13:53:52.685343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 13:53:52.688409 ==
6529 13:53:52.688518
6530 13:53:52.688613
6531 13:53:52.688701 TX Vref Scan disable
6532 13:53:52.691604 == TX Byte 0 ==
6533 13:53:52.695073 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6534 13:53:52.698771 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6535 13:53:52.701482 == TX Byte 1 ==
6536 13:53:52.705100 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6537 13:53:52.707928 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6538 13:53:52.708020
6539 13:53:52.711520 [DATLAT]
6540 13:53:52.711602 Freq=400, CH0 RK1
6541 13:53:52.711667
6542 13:53:52.714726 DATLAT Default: 0xe
6543 13:53:52.714803 0, 0xFFFF, sum = 0
6544 13:53:52.717951 1, 0xFFFF, sum = 0
6545 13:53:52.718028 2, 0xFFFF, sum = 0
6546 13:53:52.721160 3, 0xFFFF, sum = 0
6547 13:53:52.721232 4, 0xFFFF, sum = 0
6548 13:53:52.724537 5, 0xFFFF, sum = 0
6549 13:53:52.724610 6, 0xFFFF, sum = 0
6550 13:53:52.728177 7, 0xFFFF, sum = 0
6551 13:53:52.728251 8, 0xFFFF, sum = 0
6552 13:53:52.731054 9, 0xFFFF, sum = 0
6553 13:53:52.731126 10, 0xFFFF, sum = 0
6554 13:53:52.734683 11, 0xFFFF, sum = 0
6555 13:53:52.737912 12, 0xFFFF, sum = 0
6556 13:53:52.737985 13, 0x0, sum = 1
6557 13:53:52.741282 14, 0x0, sum = 2
6558 13:53:52.741388 15, 0x0, sum = 3
6559 13:53:52.741494 16, 0x0, sum = 4
6560 13:53:52.744359 best_step = 14
6561 13:53:52.744468
6562 13:53:52.744561 ==
6563 13:53:52.747801 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 13:53:52.750949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 13:53:52.751065 ==
6566 13:53:52.754220 RX Vref Scan: 0
6567 13:53:52.754350
6568 13:53:52.757103 RX Vref 0 -> 0, step: 1
6569 13:53:52.757214
6570 13:53:52.757306 RX Delay -359 -> 252, step: 8
6571 13:53:52.766076 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6572 13:53:52.769082 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6573 13:53:52.772382 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6574 13:53:52.779152 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6575 13:53:52.782328 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6576 13:53:52.785817 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6577 13:53:52.788918 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6578 13:53:52.795763 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6579 13:53:52.799105 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6580 13:53:52.802172 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6581 13:53:52.805567 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6582 13:53:52.812519 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6583 13:53:52.815649 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6584 13:53:52.818463 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6585 13:53:52.821796 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6586 13:53:52.828763 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6587 13:53:52.828845 ==
6588 13:53:52.831622 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 13:53:52.835577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 13:53:52.835652 ==
6591 13:53:52.838654 DQS Delay:
6592 13:53:52.838755 DQS0 = 40, DQS1 = 60
6593 13:53:52.838844 DQM Delay:
6594 13:53:52.841544 DQM0 = 6, DQM1 = 15
6595 13:53:52.841642 DQ Delay:
6596 13:53:52.844987 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6597 13:53:52.848338 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6598 13:53:52.851577 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6599 13:53:52.854657 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6600 13:53:52.854729
6601 13:53:52.854790
6602 13:53:52.861487 [DQSOSCAuto] RK1, (LSB)MR18= 0x847e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6603 13:53:52.864720 CH0 RK1: MR19=C0C, MR18=847E
6604 13:53:52.871299 CH0_RK1: MR19=0xC0C, MR18=0x847E, DQSOSC=393, MR23=63, INC=382, DEC=254
6605 13:53:52.874832 [RxdqsGatingPostProcess] freq 400
6606 13:53:52.881258 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6607 13:53:52.884375 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 13:53:52.887697 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 13:53:52.891610 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 13:53:52.894525 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 13:53:52.897875 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 13:53:52.897953 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 13:53:52.901098 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 13:53:52.904223 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 13:53:52.907822 Pre-setting of DQS Precalculation
6616 13:53:52.914347 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6617 13:53:52.914424 ==
6618 13:53:52.917526 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 13:53:52.921108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 13:53:52.921186 ==
6621 13:53:52.927906 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 13:53:52.933891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 13:53:52.937519 [CA 0] Center 36 (8~64) winsize 57
6624 13:53:52.940765 [CA 1] Center 36 (8~64) winsize 57
6625 13:53:52.944149 [CA 2] Center 36 (8~64) winsize 57
6626 13:53:52.944252 [CA 3] Center 36 (8~64) winsize 57
6627 13:53:52.947444 [CA 4] Center 36 (8~64) winsize 57
6628 13:53:52.950281 [CA 5] Center 36 (8~64) winsize 57
6629 13:53:52.950387
6630 13:53:52.956806 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 13:53:52.956916
6632 13:53:52.960599 [CATrainingPosCal] consider 1 rank data
6633 13:53:52.963601 u2DelayCellTimex100 = 270/100 ps
6634 13:53:52.966727 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 13:53:52.970114 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 13:53:52.973825 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 13:53:52.976908 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 13:53:52.980181 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 13:53:52.983117 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 13:53:52.983198
6641 13:53:52.986543 CA PerBit enable=1, Macro0, CA PI delay=36
6642 13:53:52.986657
6643 13:53:52.990036 [CBTSetCACLKResult] CA Dly = 36
6644 13:53:52.993371 CS Dly: 1 (0~32)
6645 13:53:52.993445 ==
6646 13:53:52.996371 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 13:53:53.000055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 13:53:53.000131 ==
6649 13:53:53.006532 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 13:53:53.013027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6651 13:53:53.016180 [CA 0] Center 36 (8~64) winsize 57
6652 13:53:53.016322 [CA 1] Center 36 (8~64) winsize 57
6653 13:53:53.019470 [CA 2] Center 36 (8~64) winsize 57
6654 13:53:53.022780 [CA 3] Center 36 (8~64) winsize 57
6655 13:53:53.026389 [CA 4] Center 36 (8~64) winsize 57
6656 13:53:53.029904 [CA 5] Center 36 (8~64) winsize 57
6657 13:53:53.029985
6658 13:53:53.033162 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6659 13:53:53.033245
6660 13:53:53.039241 [CATrainingPosCal] consider 2 rank data
6661 13:53:53.039325 u2DelayCellTimex100 = 270/100 ps
6662 13:53:53.046901 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 13:53:53.049170 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 13:53:53.052992 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 13:53:53.055921 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 13:53:53.059489 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 13:53:53.062484 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 13:53:53.062568
6669 13:53:53.065740 CA PerBit enable=1, Macro0, CA PI delay=36
6670 13:53:53.065842
6671 13:53:53.069357 [CBTSetCACLKResult] CA Dly = 36
6672 13:53:53.072475 CS Dly: 1 (0~32)
6673 13:53:53.072558
6674 13:53:53.075879 ----->DramcWriteLeveling(PI) begin...
6675 13:53:53.075984 ==
6676 13:53:53.078972 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 13:53:53.082203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 13:53:53.082287 ==
6679 13:53:53.085741 Write leveling (Byte 0): 40 => 8
6680 13:53:53.088978 Write leveling (Byte 1): 40 => 8
6681 13:53:53.091808 DramcWriteLeveling(PI) end<-----
6682 13:53:53.091924
6683 13:53:53.092019 ==
6684 13:53:53.095368 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 13:53:53.098417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 13:53:53.098523 ==
6687 13:53:53.102416 [Gating] SW mode calibration
6688 13:53:53.108640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6689 13:53:53.115011 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6690 13:53:53.118738 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 13:53:53.125274 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 13:53:53.128862 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 13:53:53.131993 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 13:53:53.138363 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 13:53:53.141294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 13:53:53.144875 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 13:53:53.148592 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 13:53:53.154685 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 13:53:53.158102 Total UI for P1: 0, mck2ui 16
6700 13:53:53.161667 best dqsien dly found for B0: ( 0, 14, 24)
6701 13:53:53.164848 Total UI for P1: 0, mck2ui 16
6702 13:53:53.167759 best dqsien dly found for B1: ( 0, 14, 24)
6703 13:53:53.171451 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6704 13:53:53.174492 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6705 13:53:53.174570
6706 13:53:53.177706 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 13:53:53.180809 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 13:53:53.184687 [Gating] SW calibration Done
6709 13:53:53.184775 ==
6710 13:53:53.188038 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 13:53:53.191003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 13:53:53.191099 ==
6713 13:53:53.194161 RX Vref Scan: 0
6714 13:53:53.194232
6715 13:53:53.197868 RX Vref 0 -> 0, step: 1
6716 13:53:53.197963
6717 13:53:53.201285 RX Delay -410 -> 252, step: 16
6718 13:53:53.204472 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6719 13:53:53.207366 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6720 13:53:53.210805 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6721 13:53:53.217168 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6722 13:53:53.220602 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6723 13:53:53.223995 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6724 13:53:53.227421 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6725 13:53:53.234040 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6726 13:53:53.237221 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6727 13:53:53.240333 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6728 13:53:53.243808 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6729 13:53:53.250325 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6730 13:53:53.253433 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6731 13:53:53.257073 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6732 13:53:53.263372 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6733 13:53:53.267067 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6734 13:53:53.267187 ==
6735 13:53:53.269849 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 13:53:53.273408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 13:53:53.273505 ==
6738 13:53:53.276490 DQS Delay:
6739 13:53:53.276596 DQS0 = 35, DQS1 = 51
6740 13:53:53.276686 DQM Delay:
6741 13:53:53.279780 DQM0 = 6, DQM1 = 13
6742 13:53:53.279857 DQ Delay:
6743 13:53:53.283215 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6744 13:53:53.286702 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6745 13:53:53.289683 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6746 13:53:53.293045 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6747 13:53:53.293149
6748 13:53:53.293283
6749 13:53:53.293382 ==
6750 13:53:53.296520 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 13:53:53.299546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 13:53:53.303174 ==
6753 13:53:53.303301
6754 13:53:53.303419
6755 13:53:53.303482 TX Vref Scan disable
6756 13:53:53.306516 == TX Byte 0 ==
6757 13:53:53.309922 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 13:53:53.313191 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 13:53:53.316110 == TX Byte 1 ==
6760 13:53:53.319639 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 13:53:53.322985 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 13:53:53.323092 ==
6763 13:53:53.326149 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 13:53:53.333025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 13:53:53.333164 ==
6766 13:53:53.333261
6767 13:53:53.333355
6768 13:53:53.333441 TX Vref Scan disable
6769 13:53:53.335889 == TX Byte 0 ==
6770 13:53:53.340392 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 13:53:53.342605 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 13:53:53.346396 == TX Byte 1 ==
6773 13:53:53.348851 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 13:53:53.352357 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 13:53:53.352443
6776 13:53:53.355706 [DATLAT]
6777 13:53:53.355788 Freq=400, CH1 RK0
6778 13:53:53.355855
6779 13:53:53.358793 DATLAT Default: 0xf
6780 13:53:53.358883 0, 0xFFFF, sum = 0
6781 13:53:53.362238 1, 0xFFFF, sum = 0
6782 13:53:53.362343 2, 0xFFFF, sum = 0
6783 13:53:53.365750 3, 0xFFFF, sum = 0
6784 13:53:53.365852 4, 0xFFFF, sum = 0
6785 13:53:53.369119 5, 0xFFFF, sum = 0
6786 13:53:53.369196 6, 0xFFFF, sum = 0
6787 13:53:53.372392 7, 0xFFFF, sum = 0
6788 13:53:53.372495 8, 0xFFFF, sum = 0
6789 13:53:53.375435 9, 0xFFFF, sum = 0
6790 13:53:53.378662 10, 0xFFFF, sum = 0
6791 13:53:53.378765 11, 0xFFFF, sum = 0
6792 13:53:53.382111 12, 0xFFFF, sum = 0
6793 13:53:53.382213 13, 0x0, sum = 1
6794 13:53:53.385311 14, 0x0, sum = 2
6795 13:53:53.385387 15, 0x0, sum = 3
6796 13:53:53.388828 16, 0x0, sum = 4
6797 13:53:53.388915 best_step = 14
6798 13:53:53.388982
6799 13:53:53.389044 ==
6800 13:53:53.392120 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 13:53:53.395354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 13:53:53.395446 ==
6803 13:53:53.398805 RX Vref Scan: 1
6804 13:53:53.398913
6805 13:53:53.402174 RX Vref 0 -> 0, step: 1
6806 13:53:53.402259
6807 13:53:53.402356 RX Delay -343 -> 252, step: 8
6808 13:53:53.404939
6809 13:53:53.405021 Set Vref, RX VrefLevel [Byte0]: 52
6810 13:53:53.408315 [Byte1]: 52
6811 13:53:53.413943
6812 13:53:53.414026 Final RX Vref Byte 0 = 52 to rank0
6813 13:53:53.417751 Final RX Vref Byte 1 = 52 to rank0
6814 13:53:53.420421 Final RX Vref Byte 0 = 52 to rank1
6815 13:53:53.423689 Final RX Vref Byte 1 = 52 to rank1==
6816 13:53:53.427343 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 13:53:53.433675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 13:53:53.433759 ==
6819 13:53:53.433828 DQS Delay:
6820 13:53:53.436859 DQS0 = 44, DQS1 = 52
6821 13:53:53.436933 DQM Delay:
6822 13:53:53.440257 DQM0 = 10, DQM1 = 10
6823 13:53:53.440341 DQ Delay:
6824 13:53:53.443381 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6825 13:53:53.446637 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6826 13:53:53.446721 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6827 13:53:53.453509 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6828 13:53:53.453593
6829 13:53:53.453660
6830 13:53:53.460665 [DQSOSCAuto] RK0, (LSB)MR18= 0x6189, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6831 13:53:53.463088 CH1 RK0: MR19=C0C, MR18=6189
6832 13:53:53.469824 CH1_RK0: MR19=0xC0C, MR18=0x6189, DQSOSC=392, MR23=63, INC=384, DEC=256
6833 13:53:53.469907 ==
6834 13:53:53.473293 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 13:53:53.476410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 13:53:53.476492 ==
6837 13:53:53.479836 [Gating] SW mode calibration
6838 13:53:53.486057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6839 13:53:53.493065 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6840 13:53:53.496027 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 13:53:53.499472 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 13:53:53.506158 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 13:53:53.509271 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 13:53:53.512549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 13:53:53.519052 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 13:53:53.522556 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 13:53:53.529002 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 13:53:53.532186 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 13:53:53.535574 Total UI for P1: 0, mck2ui 16
6850 13:53:53.539015 best dqsien dly found for B0: ( 0, 14, 24)
6851 13:53:53.541927 Total UI for P1: 0, mck2ui 16
6852 13:53:53.545275 best dqsien dly found for B1: ( 0, 14, 24)
6853 13:53:53.548632 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6854 13:53:53.551981 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6855 13:53:53.552063
6856 13:53:53.554907 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 13:53:53.558291 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 13:53:53.561522 [Gating] SW calibration Done
6859 13:53:53.561605 ==
6860 13:53:53.565045 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 13:53:53.568521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 13:53:53.571337 ==
6863 13:53:53.571460 RX Vref Scan: 0
6864 13:53:53.571527
6865 13:53:53.574926 RX Vref 0 -> 0, step: 1
6866 13:53:53.575007
6867 13:53:53.578508 RX Delay -410 -> 252, step: 16
6868 13:53:53.581179 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6869 13:53:53.584481 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6870 13:53:53.588285 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6871 13:53:53.594944 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6872 13:53:53.597925 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6873 13:53:53.601396 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6874 13:53:53.604529 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6875 13:53:53.611206 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6876 13:53:53.614711 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6877 13:53:53.617926 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6878 13:53:53.621378 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6879 13:53:53.627829 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6880 13:53:53.631230 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6881 13:53:53.634448 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6882 13:53:53.641109 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6883 13:53:53.644373 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6884 13:53:53.644480 ==
6885 13:53:53.647791 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 13:53:53.651063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 13:53:53.651167 ==
6888 13:53:53.653891 DQS Delay:
6889 13:53:53.653967 DQS0 = 43, DQS1 = 51
6890 13:53:53.654038 DQM Delay:
6891 13:53:53.657481 DQM0 = 9, DQM1 = 15
6892 13:53:53.657565 DQ Delay:
6893 13:53:53.660651 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6894 13:53:53.664005 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6895 13:53:53.667833 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6896 13:53:53.670596 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6897 13:53:53.670678
6898 13:53:53.670743
6899 13:53:53.670803 ==
6900 13:53:53.674635 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 13:53:53.677454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 13:53:53.680973 ==
6903 13:53:53.681054
6904 13:53:53.681120
6905 13:53:53.681180 TX Vref Scan disable
6906 13:53:53.683634 == TX Byte 0 ==
6907 13:53:53.687106 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6908 13:53:53.690785 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6909 13:53:53.693504 == TX Byte 1 ==
6910 13:53:53.697142 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6911 13:53:53.700153 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6912 13:53:53.700235 ==
6913 13:53:53.703628 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 13:53:53.710338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 13:53:53.710420 ==
6916 13:53:53.710485
6917 13:53:53.710545
6918 13:53:53.710604 TX Vref Scan disable
6919 13:53:53.713920 == TX Byte 0 ==
6920 13:53:53.716657 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6921 13:53:53.720212 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6922 13:53:53.723484 == TX Byte 1 ==
6923 13:53:53.726442 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6924 13:53:53.730555 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6925 13:53:53.730637
6926 13:53:53.733421 [DATLAT]
6927 13:53:53.733502 Freq=400, CH1 RK1
6928 13:53:53.733568
6929 13:53:53.736882 DATLAT Default: 0xe
6930 13:53:53.736963 0, 0xFFFF, sum = 0
6931 13:53:53.739722 1, 0xFFFF, sum = 0
6932 13:53:53.739805 2, 0xFFFF, sum = 0
6933 13:53:53.743561 3, 0xFFFF, sum = 0
6934 13:53:53.743643 4, 0xFFFF, sum = 0
6935 13:53:53.746304 5, 0xFFFF, sum = 0
6936 13:53:53.746387 6, 0xFFFF, sum = 0
6937 13:53:53.749515 7, 0xFFFF, sum = 0
6938 13:53:53.749599 8, 0xFFFF, sum = 0
6939 13:53:53.753254 9, 0xFFFF, sum = 0
6940 13:53:53.756189 10, 0xFFFF, sum = 0
6941 13:53:53.756272 11, 0xFFFF, sum = 0
6942 13:53:53.759602 12, 0xFFFF, sum = 0
6943 13:53:53.759684 13, 0x0, sum = 1
6944 13:53:53.763371 14, 0x0, sum = 2
6945 13:53:53.763483 15, 0x0, sum = 3
6946 13:53:53.766691 16, 0x0, sum = 4
6947 13:53:53.766774 best_step = 14
6948 13:53:53.766838
6949 13:53:53.766899 ==
6950 13:53:53.769609 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 13:53:53.772666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 13:53:53.772748 ==
6953 13:53:53.776129 RX Vref Scan: 0
6954 13:53:53.776211
6955 13:53:53.779958 RX Vref 0 -> 0, step: 1
6956 13:53:53.780039
6957 13:53:53.780103 RX Delay -343 -> 252, step: 8
6958 13:53:53.788372 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6959 13:53:53.791676 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6960 13:53:53.794942 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6961 13:53:53.801020 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6962 13:53:53.804810 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6963 13:53:53.808001 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6964 13:53:53.811271 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6965 13:53:53.818053 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6966 13:53:53.820763 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6967 13:53:53.824331 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6968 13:53:53.827761 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6969 13:53:53.834488 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6970 13:53:53.837262 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6971 13:53:53.841127 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6972 13:53:53.844184 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6973 13:53:53.850772 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6974 13:53:53.850852 ==
6975 13:53:53.853784 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 13:53:53.857302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 13:53:53.857384 ==
6978 13:53:53.857449 DQS Delay:
6979 13:53:53.860656 DQS0 = 48, DQS1 = 52
6980 13:53:53.860738 DQM Delay:
6981 13:53:53.864263 DQM0 = 11, DQM1 = 10
6982 13:53:53.864344 DQ Delay:
6983 13:53:53.866947 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6984 13:53:53.870528 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6985 13:53:53.874140 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6986 13:53:53.877495 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6987 13:53:53.877610
6988 13:53:53.877705
6989 13:53:53.886809 [DQSOSCAuto] RK1, (LSB)MR18= 0x6fa6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6990 13:53:53.886892 CH1 RK1: MR19=C0C, MR18=6FA6
6991 13:53:53.893676 CH1_RK1: MR19=0xC0C, MR18=0x6FA6, DQSOSC=389, MR23=63, INC=390, DEC=260
6992 13:53:53.896910 [RxdqsGatingPostProcess] freq 400
6993 13:53:53.903803 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6994 13:53:53.906893 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 13:53:53.910250 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 13:53:53.913439 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 13:53:53.916642 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 13:53:53.919700 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 13:53:53.919778 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 13:53:53.923682 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 13:53:53.926374 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 13:53:53.929555 Pre-setting of DQS Precalculation
7003 13:53:53.936122 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7004 13:53:53.942734 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7005 13:53:53.949293 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7006 13:53:53.949417
7007 13:53:53.949505
7008 13:53:53.952702 [Calibration Summary] 800 Mbps
7009 13:53:53.956320 CH 0, Rank 0
7010 13:53:53.956399 SW Impedance : PASS
7011 13:53:53.958966 DUTY Scan : NO K
7012 13:53:53.962383 ZQ Calibration : PASS
7013 13:53:53.962487 Jitter Meter : NO K
7014 13:53:53.965627 CBT Training : PASS
7015 13:53:53.969400 Write leveling : PASS
7016 13:53:53.969484 RX DQS gating : PASS
7017 13:53:53.972400 RX DQ/DQS(RDDQC) : PASS
7018 13:53:53.972484 TX DQ/DQS : PASS
7019 13:53:53.975873 RX DATLAT : PASS
7020 13:53:53.979332 RX DQ/DQS(Engine): PASS
7021 13:53:53.979431 TX OE : NO K
7022 13:53:53.982400 All Pass.
7023 13:53:53.982483
7024 13:53:53.982550 CH 0, Rank 1
7025 13:53:53.985766 SW Impedance : PASS
7026 13:53:53.985850 DUTY Scan : NO K
7027 13:53:53.989098 ZQ Calibration : PASS
7028 13:53:53.992113 Jitter Meter : NO K
7029 13:53:53.992196 CBT Training : PASS
7030 13:53:53.995635 Write leveling : NO K
7031 13:53:53.998853 RX DQS gating : PASS
7032 13:53:53.998936 RX DQ/DQS(RDDQC) : PASS
7033 13:53:54.002266 TX DQ/DQS : PASS
7034 13:53:54.005318 RX DATLAT : PASS
7035 13:53:54.005402 RX DQ/DQS(Engine): PASS
7036 13:53:54.009336 TX OE : NO K
7037 13:53:54.009420 All Pass.
7038 13:53:54.009487
7039 13:53:54.011920 CH 1, Rank 0
7040 13:53:54.012004 SW Impedance : PASS
7041 13:53:54.015340 DUTY Scan : NO K
7042 13:53:54.018653 ZQ Calibration : PASS
7043 13:53:54.018737 Jitter Meter : NO K
7044 13:53:54.022196 CBT Training : PASS
7045 13:53:54.025162 Write leveling : PASS
7046 13:53:54.025246 RX DQS gating : PASS
7047 13:53:54.028877 RX DQ/DQS(RDDQC) : PASS
7048 13:53:54.031698 TX DQ/DQS : PASS
7049 13:53:54.031782 RX DATLAT : PASS
7050 13:53:54.034894 RX DQ/DQS(Engine): PASS
7051 13:53:54.038062 TX OE : NO K
7052 13:53:54.038146 All Pass.
7053 13:53:54.038212
7054 13:53:54.038274 CH 1, Rank 1
7055 13:53:54.041433 SW Impedance : PASS
7056 13:53:54.045216 DUTY Scan : NO K
7057 13:53:54.045295 ZQ Calibration : PASS
7058 13:53:54.047838 Jitter Meter : NO K
7059 13:53:54.051667 CBT Training : PASS
7060 13:53:54.051780 Write leveling : NO K
7061 13:53:54.054791 RX DQS gating : PASS
7062 13:53:54.057983 RX DQ/DQS(RDDQC) : PASS
7063 13:53:54.058061 TX DQ/DQS : PASS
7064 13:53:54.061634 RX DATLAT : PASS
7065 13:53:54.061736 RX DQ/DQS(Engine): PASS
7066 13:53:54.064418 TX OE : NO K
7067 13:53:54.064494 All Pass.
7068 13:53:54.064581
7069 13:53:54.068292 DramC Write-DBI off
7070 13:53:54.071718 PER_BANK_REFRESH: Hybrid Mode
7071 13:53:54.071797 TX_TRACKING: ON
7072 13:53:54.081302 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7073 13:53:54.084493 [FAST_K] Save calibration result to emmc
7074 13:53:54.088058 dramc_set_vcore_voltage set vcore to 725000
7075 13:53:54.091012 Read voltage for 1600, 0
7076 13:53:54.091095 Vio18 = 0
7077 13:53:54.094423 Vcore = 725000
7078 13:53:54.094506 Vdram = 0
7079 13:53:54.094572 Vddq = 0
7080 13:53:54.094633 Vmddr = 0
7081 13:53:54.101034 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7082 13:53:54.107787 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7083 13:53:54.107871 MEM_TYPE=3, freq_sel=13
7084 13:53:54.110904 sv_algorithm_assistance_LP4_3733
7085 13:53:54.114253 ============ PULL DRAM RESETB DOWN ============
7086 13:53:54.120589 ========== PULL DRAM RESETB DOWN end =========
7087 13:53:54.124248 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7088 13:53:54.127609 ===================================
7089 13:53:54.130980 LPDDR4 DRAM CONFIGURATION
7090 13:53:54.133982 ===================================
7091 13:53:54.134067 EX_ROW_EN[0] = 0x0
7092 13:53:54.137347 EX_ROW_EN[1] = 0x0
7093 13:53:54.140516 LP4Y_EN = 0x0
7094 13:53:54.140589 WORK_FSP = 0x1
7095 13:53:54.144064 WL = 0x5
7096 13:53:54.144151 RL = 0x5
7097 13:53:54.147766 BL = 0x2
7098 13:53:54.147854 RPST = 0x0
7099 13:53:54.150433 RD_PRE = 0x0
7100 13:53:54.150537 WR_PRE = 0x1
7101 13:53:54.153490 WR_PST = 0x1
7102 13:53:54.153593 DBI_WR = 0x0
7103 13:53:54.156979 DBI_RD = 0x0
7104 13:53:54.157058 OTF = 0x1
7105 13:53:54.160854 ===================================
7106 13:53:54.163714 ===================================
7107 13:53:54.166769 ANA top config
7108 13:53:54.170663 ===================================
7109 13:53:54.170740 DLL_ASYNC_EN = 0
7110 13:53:54.173671 ALL_SLAVE_EN = 0
7111 13:53:54.176823 NEW_RANK_MODE = 1
7112 13:53:54.179994 DLL_IDLE_MODE = 1
7113 13:53:54.183410 LP45_APHY_COMB_EN = 1
7114 13:53:54.183510 TX_ODT_DIS = 0
7115 13:53:54.186683 NEW_8X_MODE = 1
7116 13:53:54.190246 ===================================
7117 13:53:54.193215 ===================================
7118 13:53:54.196293 data_rate = 3200
7119 13:53:54.199623 CKR = 1
7120 13:53:54.203170 DQ_P2S_RATIO = 8
7121 13:53:54.206518 ===================================
7122 13:53:54.210030 CA_P2S_RATIO = 8
7123 13:53:54.210132 DQ_CA_OPEN = 0
7124 13:53:54.213188 DQ_SEMI_OPEN = 0
7125 13:53:54.216822 CA_SEMI_OPEN = 0
7126 13:53:54.219537 CA_FULL_RATE = 0
7127 13:53:54.222703 DQ_CKDIV4_EN = 0
7128 13:53:54.226605 CA_CKDIV4_EN = 0
7129 13:53:54.226679 CA_PREDIV_EN = 0
7130 13:53:54.229485 PH8_DLY = 12
7131 13:53:54.233164 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7132 13:53:54.236266 DQ_AAMCK_DIV = 4
7133 13:53:54.239680 CA_AAMCK_DIV = 4
7134 13:53:54.242746 CA_ADMCK_DIV = 4
7135 13:53:54.242830 DQ_TRACK_CA_EN = 0
7136 13:53:54.246587 CA_PICK = 1600
7137 13:53:54.249436 CA_MCKIO = 1600
7138 13:53:54.252727 MCKIO_SEMI = 0
7139 13:53:54.256105 PLL_FREQ = 3068
7140 13:53:54.259539 DQ_UI_PI_RATIO = 32
7141 13:53:54.262569 CA_UI_PI_RATIO = 0
7142 13:53:54.266119 ===================================
7143 13:53:54.269246 ===================================
7144 13:53:54.269330 memory_type:LPDDR4
7145 13:53:54.272739 GP_NUM : 10
7146 13:53:54.275684 SRAM_EN : 1
7147 13:53:54.275768 MD32_EN : 0
7148 13:53:54.279508 ===================================
7149 13:53:54.282638 [ANA_INIT] >>>>>>>>>>>>>>
7150 13:53:54.285662 <<<<<< [CONFIGURE PHASE]: ANA_TX
7151 13:53:54.289051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7152 13:53:54.291996 ===================================
7153 13:53:54.295224 data_rate = 3200,PCW = 0X7600
7154 13:53:54.298544 ===================================
7155 13:53:54.302129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7156 13:53:54.308467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 13:53:54.312320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 13:53:54.318662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7159 13:53:54.321682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7160 13:53:54.325354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7161 13:53:54.325439 [ANA_INIT] flow start
7162 13:53:54.328550 [ANA_INIT] PLL >>>>>>>>
7163 13:53:54.331966 [ANA_INIT] PLL <<<<<<<<
7164 13:53:54.332050 [ANA_INIT] MIDPI >>>>>>>>
7165 13:53:54.334901 [ANA_INIT] MIDPI <<<<<<<<
7166 13:53:54.338673 [ANA_INIT] DLL >>>>>>>>
7167 13:53:54.341275 [ANA_INIT] DLL <<<<<<<<
7168 13:53:54.341382 [ANA_INIT] flow end
7169 13:53:54.345027 ============ LP4 DIFF to SE enter ============
7170 13:53:54.351189 ============ LP4 DIFF to SE exit ============
7171 13:53:54.351274 [ANA_INIT] <<<<<<<<<<<<<
7172 13:53:54.354803 [Flow] Enable top DCM control >>>>>
7173 13:53:54.357672 [Flow] Enable top DCM control <<<<<
7174 13:53:54.360976 Enable DLL master slave shuffle
7175 13:53:54.367813 ==============================================================
7176 13:53:54.367896 Gating Mode config
7177 13:53:54.374373 ==============================================================
7178 13:53:54.377454 Config description:
7179 13:53:54.387307 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7180 13:53:54.394470 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7181 13:53:54.397659 SELPH_MODE 0: By rank 1: By Phase
7182 13:53:54.403954 ==============================================================
7183 13:53:54.407546 GAT_TRACK_EN = 1
7184 13:53:54.410299 RX_GATING_MODE = 2
7185 13:53:54.413726 RX_GATING_TRACK_MODE = 2
7186 13:53:54.413807 SELPH_MODE = 1
7187 13:53:54.417086 PICG_EARLY_EN = 1
7188 13:53:54.420555 VALID_LAT_VALUE = 1
7189 13:53:54.426981 ==============================================================
7190 13:53:54.430380 Enter into Gating configuration >>>>
7191 13:53:54.433389 Exit from Gating configuration <<<<
7192 13:53:54.437365 Enter into DVFS_PRE_config >>>>>
7193 13:53:54.446775 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7194 13:53:54.450087 Exit from DVFS_PRE_config <<<<<
7195 13:53:54.453444 Enter into PICG configuration >>>>
7196 13:53:54.456783 Exit from PICG configuration <<<<
7197 13:53:54.459913 [RX_INPUT] configuration >>>>>
7198 13:53:54.463246 [RX_INPUT] configuration <<<<<
7199 13:53:54.466943 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7200 13:53:54.472850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7201 13:53:54.479567 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 13:53:54.486290 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 13:53:54.492822 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 13:53:54.499351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 13:53:54.502521 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7206 13:53:54.506080 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7207 13:53:54.509293 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7208 13:53:54.515855 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7209 13:53:54.519331 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7210 13:53:54.522756 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 13:53:54.525745 ===================================
7212 13:53:54.529309 LPDDR4 DRAM CONFIGURATION
7213 13:53:54.532428 ===================================
7214 13:53:54.532510 EX_ROW_EN[0] = 0x0
7215 13:53:54.535803 EX_ROW_EN[1] = 0x0
7216 13:53:54.538977 LP4Y_EN = 0x0
7217 13:53:54.539057 WORK_FSP = 0x1
7218 13:53:54.542251 WL = 0x5
7219 13:53:54.542333 RL = 0x5
7220 13:53:54.545449 BL = 0x2
7221 13:53:54.545531 RPST = 0x0
7222 13:53:54.549224 RD_PRE = 0x0
7223 13:53:54.549306 WR_PRE = 0x1
7224 13:53:54.551877 WR_PST = 0x1
7225 13:53:54.551958 DBI_WR = 0x0
7226 13:53:54.555268 DBI_RD = 0x0
7227 13:53:54.555425 OTF = 0x1
7228 13:53:54.558527 ===================================
7229 13:53:54.562198 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7230 13:53:54.568704 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7231 13:53:54.571790 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 13:53:54.575209 ===================================
7233 13:53:54.578630 LPDDR4 DRAM CONFIGURATION
7234 13:53:54.581500 ===================================
7235 13:53:54.581575 EX_ROW_EN[0] = 0x10
7236 13:53:54.584791 EX_ROW_EN[1] = 0x0
7237 13:53:54.588029 LP4Y_EN = 0x0
7238 13:53:54.588128 WORK_FSP = 0x1
7239 13:53:54.591343 WL = 0x5
7240 13:53:54.591454 RL = 0x5
7241 13:53:54.594689 BL = 0x2
7242 13:53:54.594761 RPST = 0x0
7243 13:53:54.598608 RD_PRE = 0x0
7244 13:53:54.598709 WR_PRE = 0x1
7245 13:53:54.601105 WR_PST = 0x1
7246 13:53:54.601177 DBI_WR = 0x0
7247 13:53:54.604718 DBI_RD = 0x0
7248 13:53:54.604816 OTF = 0x1
7249 13:53:54.607691 ===================================
7250 13:53:54.614907 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7251 13:53:54.614987 ==
7252 13:53:54.617666 Dram Type= 6, Freq= 0, CH_0, rank 0
7253 13:53:54.624386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7254 13:53:54.624475 ==
7255 13:53:54.624592 [Duty_Offset_Calibration]
7256 13:53:54.627318 B0:2 B1:0 CA:4
7257 13:53:54.627453
7258 13:53:54.630698 [DutyScan_Calibration_Flow] k_type=0
7259 13:53:54.639224
7260 13:53:54.639318 ==CLK 0==
7261 13:53:54.642531 Final CLK duty delay cell = -4
7262 13:53:54.646072 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7263 13:53:54.649032 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7264 13:53:54.652706 [-4] AVG Duty = 4937%(X100)
7265 13:53:54.652783
7266 13:53:54.655834 CH0 CLK Duty spec in!! Max-Min= 187%
7267 13:53:54.659509 [DutyScan_Calibration_Flow] ====Done====
7268 13:53:54.659584
7269 13:53:54.662611 [DutyScan_Calibration_Flow] k_type=1
7270 13:53:54.679646
7271 13:53:54.679789 ==DQS 0 ==
7272 13:53:54.683523 Final DQS duty delay cell = 0
7273 13:53:54.686349 [0] MAX Duty = 5218%(X100), DQS PI = 20
7274 13:53:54.689719 [0] MIN Duty = 5093%(X100), DQS PI = 4
7275 13:53:54.693236 [0] AVG Duty = 5155%(X100)
7276 13:53:54.693360
7277 13:53:54.693428 ==DQS 1 ==
7278 13:53:54.696246 Final DQS duty delay cell = 0
7279 13:53:54.699656 [0] MAX Duty = 5187%(X100), DQS PI = 2
7280 13:53:54.703168 [0] MIN Duty = 4969%(X100), DQS PI = 10
7281 13:53:54.706146 [0] AVG Duty = 5078%(X100)
7282 13:53:54.706225
7283 13:53:54.709342 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7284 13:53:54.709424
7285 13:53:54.712507 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7286 13:53:54.715879 [DutyScan_Calibration_Flow] ====Done====
7287 13:53:54.715962
7288 13:53:54.719588 [DutyScan_Calibration_Flow] k_type=3
7289 13:53:54.736582
7290 13:53:54.736661 ==DQM 0 ==
7291 13:53:54.739982 Final DQM duty delay cell = 0
7292 13:53:54.743469 [0] MAX Duty = 5124%(X100), DQS PI = 22
7293 13:53:54.746911 [0] MIN Duty = 4875%(X100), DQS PI = 56
7294 13:53:54.749604 [0] AVG Duty = 4999%(X100)
7295 13:53:54.749720
7296 13:53:54.749826 ==DQM 1 ==
7297 13:53:54.753154 Final DQM duty delay cell = 0
7298 13:53:54.756889 [0] MAX Duty = 5000%(X100), DQS PI = 2
7299 13:53:54.759890 [0] MIN Duty = 4813%(X100), DQS PI = 16
7300 13:53:54.763068 [0] AVG Duty = 4906%(X100)
7301 13:53:54.763142
7302 13:53:54.766388 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7303 13:53:54.766468
7304 13:53:54.769831 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7305 13:53:54.773137 [DutyScan_Calibration_Flow] ====Done====
7306 13:53:54.773213
7307 13:53:54.776497 [DutyScan_Calibration_Flow] k_type=2
7308 13:53:54.793866
7309 13:53:54.793982 ==DQ 0 ==
7310 13:53:54.797283 Final DQ duty delay cell = 0
7311 13:53:54.800663 [0] MAX Duty = 5156%(X100), DQS PI = 20
7312 13:53:54.803861 [0] MIN Duty = 4938%(X100), DQS PI = 12
7313 13:53:54.803968 [0] AVG Duty = 5047%(X100)
7314 13:53:54.806913
7315 13:53:54.806985 ==DQ 1 ==
7316 13:53:54.810325 Final DQ duty delay cell = 0
7317 13:53:54.813405 [0] MAX Duty = 5218%(X100), DQS PI = 2
7318 13:53:54.817260 [0] MIN Duty = 4907%(X100), DQS PI = 32
7319 13:53:54.817334 [0] AVG Duty = 5062%(X100)
7320 13:53:54.820353
7321 13:53:54.823302 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7322 13:53:54.823388
7323 13:53:54.827181 CH0 DQ 1 Duty spec in!! Max-Min= 311%
7324 13:53:54.830303 [DutyScan_Calibration_Flow] ====Done====
7325 13:53:54.830380 ==
7326 13:53:54.833115 Dram Type= 6, Freq= 0, CH_1, rank 0
7327 13:53:54.836622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7328 13:53:54.836697 ==
7329 13:53:54.840181 [Duty_Offset_Calibration]
7330 13:53:54.840263 B0:0 B1:-1 CA:3
7331 13:53:54.840328
7332 13:53:54.843416 [DutyScan_Calibration_Flow] k_type=0
7333 13:53:54.853589
7334 13:53:54.853679 ==CLK 0==
7335 13:53:54.856593 Final CLK duty delay cell = -4
7336 13:53:54.860405 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7337 13:53:54.863025 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7338 13:53:54.866422 [-4] AVG Duty = 4922%(X100)
7339 13:53:54.866531
7340 13:53:54.870126 CH1 CLK Duty spec in!! Max-Min= 156%
7341 13:53:54.872956 [DutyScan_Calibration_Flow] ====Done====
7342 13:53:54.873033
7343 13:53:54.876453 [DutyScan_Calibration_Flow] k_type=1
7344 13:53:54.892200
7345 13:53:54.892285 ==DQS 0 ==
7346 13:53:54.895864 Final DQS duty delay cell = 0
7347 13:53:54.899252 [0] MAX Duty = 5218%(X100), DQS PI = 28
7348 13:53:54.902286 [0] MIN Duty = 4907%(X100), DQS PI = 58
7349 13:53:54.905833 [0] AVG Duty = 5062%(X100)
7350 13:53:54.905909
7351 13:53:54.905974 ==DQS 1 ==
7352 13:53:54.909725 Final DQS duty delay cell = -4
7353 13:53:54.912819 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7354 13:53:54.915330 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7355 13:53:54.918770 [-4] AVG Duty = 4922%(X100)
7356 13:53:54.918851
7357 13:53:54.922576 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7358 13:53:54.922659
7359 13:53:54.926210 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7360 13:53:54.928932 [DutyScan_Calibration_Flow] ====Done====
7361 13:53:54.929019
7362 13:53:54.931896 [DutyScan_Calibration_Flow] k_type=3
7363 13:53:54.949969
7364 13:53:54.950079 ==DQM 0 ==
7365 13:53:54.952861 Final DQM duty delay cell = 0
7366 13:53:54.956659 [0] MAX Duty = 5062%(X100), DQS PI = 30
7367 13:53:54.959648 [0] MIN Duty = 4782%(X100), DQS PI = 40
7368 13:53:54.963181 [0] AVG Duty = 4922%(X100)
7369 13:53:54.963290
7370 13:53:54.963405 ==DQM 1 ==
7371 13:53:54.966034 Final DQM duty delay cell = 0
7372 13:53:54.969633 [0] MAX Duty = 5000%(X100), DQS PI = 30
7373 13:53:54.972615 [0] MIN Duty = 4813%(X100), DQS PI = 0
7374 13:53:54.976315 [0] AVG Duty = 4906%(X100)
7375 13:53:54.976421
7376 13:53:54.979145 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7377 13:53:54.979252
7378 13:53:54.982507 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7379 13:53:54.985993 [DutyScan_Calibration_Flow] ====Done====
7380 13:53:54.986074
7381 13:53:54.989040 [DutyScan_Calibration_Flow] k_type=2
7382 13:53:55.005886
7383 13:53:55.005969 ==DQ 0 ==
7384 13:53:55.009388 Final DQ duty delay cell = -4
7385 13:53:55.012458 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7386 13:53:55.015449 [-4] MIN Duty = 4813%(X100), DQS PI = 22
7387 13:53:55.018796 [-4] AVG Duty = 4875%(X100)
7388 13:53:55.018878
7389 13:53:55.018942 ==DQ 1 ==
7390 13:53:55.022215 Final DQ duty delay cell = 0
7391 13:53:55.025897 [0] MAX Duty = 5000%(X100), DQS PI = 26
7392 13:53:55.028970 [0] MIN Duty = 4875%(X100), DQS PI = 54
7393 13:53:55.032475 [0] AVG Duty = 4937%(X100)
7394 13:53:55.032552
7395 13:53:55.035178 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7396 13:53:55.035251
7397 13:53:55.038830 CH1 DQ 1 Duty spec in!! Max-Min= 125%
7398 13:53:55.042025 [DutyScan_Calibration_Flow] ====Done====
7399 13:53:55.045750 nWR fixed to 30
7400 13:53:55.048738 [ModeRegInit_LP4] CH0 RK0
7401 13:53:55.048890 [ModeRegInit_LP4] CH0 RK1
7402 13:53:55.052311 [ModeRegInit_LP4] CH1 RK0
7403 13:53:55.055166 [ModeRegInit_LP4] CH1 RK1
7404 13:53:55.055268 match AC timing 5
7405 13:53:55.061738 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7406 13:53:55.065171 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7407 13:53:55.068730 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7408 13:53:55.074856 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7409 13:53:55.078937 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7410 13:53:55.079013 [MiockJmeterHQA]
7411 13:53:55.079085
7412 13:53:55.081529 [DramcMiockJmeter] u1RxGatingPI = 0
7413 13:53:55.085036 0 : 4365, 4137
7414 13:53:55.085115 4 : 4254, 4029
7415 13:53:55.088173 8 : 4257, 4029
7416 13:53:55.088285 12 : 4252, 4027
7417 13:53:55.091687 16 : 4253, 4026
7418 13:53:55.091764 20 : 4363, 4138
7419 13:53:55.091829 24 : 4365, 4139
7420 13:53:55.095012 28 : 4257, 4029
7421 13:53:55.095087 32 : 4257, 4029
7422 13:53:55.098545 36 : 4258, 4029
7423 13:53:55.098650 40 : 4252, 4027
7424 13:53:55.101528 44 : 4253, 4029
7425 13:53:55.101629 48 : 4361, 4138
7426 13:53:55.104950 52 : 4257, 4030
7427 13:53:55.105028 56 : 4365, 4137
7428 13:53:55.105093 60 : 4257, 4029
7429 13:53:55.108106 64 : 4253, 4027
7430 13:53:55.108181 68 : 4252, 4027
7431 13:53:55.111566 72 : 4368, 4140
7432 13:53:55.111679 76 : 4363, 4137
7433 13:53:55.114797 80 : 4257, 4029
7434 13:53:55.114881 84 : 4257, 4029
7435 13:53:55.118331 88 : 4252, 4027
7436 13:53:55.118415 92 : 4257, 4029
7437 13:53:55.118482 96 : 4255, 2830
7438 13:53:55.121377 100 : 4363, 0
7439 13:53:55.121461 104 : 4253, 0
7440 13:53:55.124554 108 : 4366, 0
7441 13:53:55.124639 112 : 4257, 0
7442 13:53:55.124706 116 : 4363, 0
7443 13:53:55.128334 120 : 4257, 0
7444 13:53:55.128419 124 : 4257, 0
7445 13:53:55.131618 128 : 4252, 0
7446 13:53:55.131702 132 : 4255, 0
7447 13:53:55.131769 136 : 4257, 0
7448 13:53:55.134490 140 : 4252, 0
7449 13:53:55.134575 144 : 4253, 0
7450 13:53:55.137880 148 : 4368, 0
7451 13:53:55.137965 152 : 4363, 0
7452 13:53:55.138031 156 : 4249, 0
7453 13:53:55.141369 160 : 4366, 0
7454 13:53:55.141454 164 : 4363, 0
7455 13:53:55.141521 168 : 4363, 0
7456 13:53:55.144683 172 : 4257, 0
7457 13:53:55.144767 176 : 4257, 0
7458 13:53:55.147925 180 : 4257, 0
7459 13:53:55.148009 184 : 4255, 0
7460 13:53:55.148076 188 : 4255, 0
7461 13:53:55.151027 192 : 4252, 0
7462 13:53:55.151139 196 : 4255, 0
7463 13:53:55.155278 200 : 4368, 0
7464 13:53:55.155402 204 : 4252, 0
7465 13:53:55.155475 208 : 4252, 0
7466 13:53:55.158026 212 : 4257, 0
7467 13:53:55.158108 216 : 4257, 0
7468 13:53:55.161397 220 : 4363, 918
7469 13:53:55.161506 224 : 4257, 4018
7470 13:53:55.164481 228 : 4257, 4030
7471 13:53:55.164564 232 : 4255, 4029
7472 13:53:55.167492 236 : 4252, 4027
7473 13:53:55.167574 240 : 4257, 4029
7474 13:53:55.170824 244 : 4368, 4140
7475 13:53:55.170906 248 : 4253, 4027
7476 13:53:55.170972 252 : 4363, 4138
7477 13:53:55.174211 256 : 4363, 4137
7478 13:53:55.174294 260 : 4257, 4029
7479 13:53:55.177358 264 : 4257, 4029
7480 13:53:55.177441 268 : 4366, 4140
7481 13:53:55.180679 272 : 4252, 4027
7482 13:53:55.180762 276 : 4257, 4029
7483 13:53:55.184024 280 : 4257, 4029
7484 13:53:55.184107 284 : 4255, 4029
7485 13:53:55.187169 288 : 4252, 4027
7486 13:53:55.187251 292 : 4257, 4029
7487 13:53:55.190393 296 : 4368, 4140
7488 13:53:55.190477 300 : 4253, 4027
7489 13:53:55.193930 304 : 4363, 4138
7490 13:53:55.194012 308 : 4363, 4137
7491 13:53:55.196808 312 : 4257, 4029
7492 13:53:55.196891 316 : 4257, 4030
7493 13:53:55.196957 320 : 4366, 4140
7494 13:53:55.200617 324 : 4252, 4027
7495 13:53:55.200700 328 : 4257, 4029
7496 13:53:55.203486 332 : 4257, 3799
7497 13:53:55.203569 336 : 4255, 1587
7498 13:53:55.203635
7499 13:53:55.206772 MIOCK jitter meter ch=0
7500 13:53:55.206891
7501 13:53:55.210269 1T = (336-100) = 236 dly cells
7502 13:53:55.217044 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7503 13:53:55.217123 ==
7504 13:53:55.220601 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 13:53:55.223326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 13:53:55.223427 ==
7507 13:53:55.230229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 13:53:55.233545 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 13:53:55.236621 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 13:53:55.243145 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 13:53:55.252509 [CA 0] Center 43 (13~74) winsize 62
7512 13:53:55.255353 [CA 1] Center 43 (13~73) winsize 61
7513 13:53:55.259247 [CA 2] Center 39 (10~68) winsize 59
7514 13:53:55.262077 [CA 3] Center 38 (9~67) winsize 59
7515 13:53:55.265766 [CA 4] Center 36 (7~66) winsize 60
7516 13:53:55.268632 [CA 5] Center 36 (6~66) winsize 61
7517 13:53:55.268712
7518 13:53:55.271915 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 13:53:55.272000
7520 13:53:55.278823 [CATrainingPosCal] consider 1 rank data
7521 13:53:55.278907 u2DelayCellTimex100 = 275/100 ps
7522 13:53:55.285189 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7523 13:53:55.288418 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7524 13:53:55.291682 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7525 13:53:55.295397 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7526 13:53:55.298364 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7527 13:53:55.301648 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7528 13:53:55.301730
7529 13:53:55.304850 CA PerBit enable=1, Macro0, CA PI delay=36
7530 13:53:55.304932
7531 13:53:55.308339 [CBTSetCACLKResult] CA Dly = 36
7532 13:53:55.312080 CS Dly: 10 (0~41)
7533 13:53:55.315183 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 13:53:55.318054 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 13:53:55.318136 ==
7536 13:53:55.321719 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 13:53:55.328178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 13:53:55.328261 ==
7539 13:53:55.331329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 13:53:55.338239 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 13:53:55.341428 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 13:53:55.348131 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 13:53:55.355971 [CA 0] Center 44 (14~74) winsize 61
7544 13:53:55.359257 [CA 1] Center 44 (14~74) winsize 61
7545 13:53:55.362587 [CA 2] Center 39 (10~68) winsize 59
7546 13:53:55.366246 [CA 3] Center 39 (10~68) winsize 59
7547 13:53:55.369247 [CA 4] Center 37 (7~67) winsize 61
7548 13:53:55.372713 [CA 5] Center 36 (7~66) winsize 60
7549 13:53:55.372867
7550 13:53:55.376515 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 13:53:55.376682
7552 13:53:55.382830 [CATrainingPosCal] consider 2 rank data
7553 13:53:55.383024 u2DelayCellTimex100 = 275/100 ps
7554 13:53:55.389023 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7555 13:53:55.392600 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7556 13:53:55.396404 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7557 13:53:55.399437 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7558 13:53:55.402690 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7559 13:53:55.405889 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7560 13:53:55.406275
7561 13:53:55.409078 CA PerBit enable=1, Macro0, CA PI delay=36
7562 13:53:55.409491
7563 13:53:55.412429 [CBTSetCACLKResult] CA Dly = 36
7564 13:53:55.415774 CS Dly: 11 (0~43)
7565 13:53:55.419119 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 13:53:55.422065 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 13:53:55.422422
7568 13:53:55.428843 ----->DramcWriteLeveling(PI) begin...
7569 13:53:55.429247 ==
7570 13:53:55.432375 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 13:53:55.435597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 13:53:55.436104 ==
7573 13:53:55.438454 Write leveling (Byte 0): 37 => 37
7574 13:53:55.441795 Write leveling (Byte 1): 25 => 25
7575 13:53:55.445374 DramcWriteLeveling(PI) end<-----
7576 13:53:55.445850
7577 13:53:55.446280 ==
7578 13:53:55.448364 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 13:53:55.451766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 13:53:55.452301 ==
7581 13:53:55.455087 [Gating] SW mode calibration
7582 13:53:55.462327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 13:53:55.468578 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 13:53:55.471794 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 13:53:55.474840 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 13:53:55.481211 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7587 13:53:55.484961 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7588 13:53:55.487898 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7589 13:53:55.494574 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7590 13:53:55.497919 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 13:53:55.501393 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 13:53:55.507773 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 13:53:55.510915 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 13:53:55.514219 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7595 13:53:55.521130 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7596 13:53:55.524813 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7597 13:53:55.527341 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7598 13:53:55.533914 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7599 13:53:55.537367 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 13:53:55.540725 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 13:53:55.547275 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 13:53:55.550681 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7603 13:53:55.553665 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7604 13:53:55.560318 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7605 13:53:55.563682 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7606 13:53:55.566935 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 13:53:55.573359 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 13:53:55.577315 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 13:53:55.580399 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 13:53:55.586502 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 13:53:55.590499 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7612 13:53:55.593934 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7613 13:53:55.600115 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 13:53:55.603174 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 13:53:55.606649 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 13:53:55.613055 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 13:53:55.616751 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 13:53:55.619717 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 13:53:55.627179 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 13:53:55.629674 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 13:53:55.633030 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 13:53:55.639500 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 13:53:55.643211 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 13:53:55.646108 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 13:53:55.652683 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 13:53:55.656144 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 13:53:55.659359 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 13:53:55.665811 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7629 13:53:55.669036 Total UI for P1: 0, mck2ui 16
7630 13:53:55.672400 best dqsien dly found for B0: ( 1, 9, 10)
7631 13:53:55.675637 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7632 13:53:55.679403 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 13:53:55.682216 Total UI for P1: 0, mck2ui 16
7634 13:53:55.685917 best dqsien dly found for B1: ( 1, 9, 20)
7635 13:53:55.688946 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7636 13:53:55.692394 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7637 13:53:55.692840
7638 13:53:55.698726 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7639 13:53:55.702041 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7640 13:53:55.705447 [Gating] SW calibration Done
7641 13:53:55.705865 ==
7642 13:53:55.708612 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 13:53:55.712182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 13:53:55.712604 ==
7645 13:53:55.715104 RX Vref Scan: 0
7646 13:53:55.715557
7647 13:53:55.715926 RX Vref 0 -> 0, step: 1
7648 13:53:55.716418
7649 13:53:55.718706 RX Delay 0 -> 252, step: 8
7650 13:53:55.721835 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7651 13:53:55.725639 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7652 13:53:55.731658 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7653 13:53:55.735437 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7654 13:53:55.738524 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7655 13:53:55.741943 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7656 13:53:55.744867 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7657 13:53:55.751689 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7658 13:53:55.755151 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7659 13:53:55.758347 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7660 13:53:55.761510 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7661 13:53:55.768153 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7662 13:53:55.771137 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7663 13:53:55.774397 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7664 13:53:55.777849 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7665 13:53:55.780824 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7666 13:53:55.784351 ==
7667 13:53:55.784771 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 13:53:55.791418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 13:53:55.791869 ==
7670 13:53:55.792219 DQS Delay:
7671 13:53:55.794811 DQS0 = 0, DQS1 = 0
7672 13:53:55.795297 DQM Delay:
7673 13:53:55.797487 DQM0 = 130, DQM1 = 127
7674 13:53:55.797900 DQ Delay:
7675 13:53:55.801135 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7676 13:53:55.804652 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7677 13:53:55.807356 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7678 13:53:55.810630 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =131
7679 13:53:55.811068
7680 13:53:55.811428
7681 13:53:55.811764 ==
7682 13:53:55.814273 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 13:53:55.820636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 13:53:55.821139 ==
7685 13:53:55.821473
7686 13:53:55.821783
7687 13:53:55.822076 TX Vref Scan disable
7688 13:53:55.824739 == TX Byte 0 ==
7689 13:53:55.828012 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7690 13:53:55.834258 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7691 13:53:55.834676 == TX Byte 1 ==
7692 13:53:55.838184 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7693 13:53:55.844821 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7694 13:53:55.845380 ==
7695 13:53:55.847925 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 13:53:55.850888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 13:53:55.851304 ==
7698 13:53:55.864740
7699 13:53:55.868049 TX Vref early break, caculate TX vref
7700 13:53:55.871350 TX Vref=16, minBit 4, minWin=22, winSum=366
7701 13:53:55.875126 TX Vref=18, minBit 1, minWin=22, winSum=376
7702 13:53:55.877860 TX Vref=20, minBit 3, minWin=23, winSum=384
7703 13:53:55.881057 TX Vref=22, minBit 4, minWin=24, winSum=398
7704 13:53:55.884277 TX Vref=24, minBit 1, minWin=25, winSum=411
7705 13:53:55.891045 TX Vref=26, minBit 1, minWin=25, winSum=416
7706 13:53:55.894552 TX Vref=28, minBit 4, minWin=25, winSum=420
7707 13:53:55.897493 TX Vref=30, minBit 1, minWin=25, winSum=417
7708 13:53:55.900691 TX Vref=32, minBit 13, minWin=24, winSum=406
7709 13:53:55.904221 TX Vref=34, minBit 0, minWin=24, winSum=397
7710 13:53:55.911102 [TxChooseVref] Worse bit 4, Min win 25, Win sum 420, Final Vref 28
7711 13:53:55.911689
7712 13:53:55.913800 Final TX Range 0 Vref 28
7713 13:53:55.914241
7714 13:53:55.914594 ==
7715 13:53:55.917297 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 13:53:55.920630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 13:53:55.921090 ==
7718 13:53:55.921429
7719 13:53:55.923687
7720 13:53:55.924102 TX Vref Scan disable
7721 13:53:55.930728 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7722 13:53:55.931248 == TX Byte 0 ==
7723 13:53:55.933643 u2DelayCellOfst[0]=14 cells (4 PI)
7724 13:53:55.936827 u2DelayCellOfst[1]=17 cells (5 PI)
7725 13:53:55.940322 u2DelayCellOfst[2]=14 cells (4 PI)
7726 13:53:55.943638 u2DelayCellOfst[3]=14 cells (4 PI)
7727 13:53:55.947145 u2DelayCellOfst[4]=14 cells (4 PI)
7728 13:53:55.949938 u2DelayCellOfst[5]=0 cells (0 PI)
7729 13:53:55.952972 u2DelayCellOfst[6]=21 cells (6 PI)
7730 13:53:55.956428 u2DelayCellOfst[7]=17 cells (5 PI)
7731 13:53:55.959862 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7732 13:53:55.963159 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7733 13:53:55.966413 == TX Byte 1 ==
7734 13:53:55.969703 u2DelayCellOfst[8]=0 cells (0 PI)
7735 13:53:55.973085 u2DelayCellOfst[9]=0 cells (0 PI)
7736 13:53:55.976281 u2DelayCellOfst[10]=3 cells (1 PI)
7737 13:53:55.979830 u2DelayCellOfst[11]=0 cells (0 PI)
7738 13:53:55.982799 u2DelayCellOfst[12]=7 cells (2 PI)
7739 13:53:55.986146 u2DelayCellOfst[13]=7 cells (2 PI)
7740 13:53:55.989528 u2DelayCellOfst[14]=14 cells (4 PI)
7741 13:53:55.992813 u2DelayCellOfst[15]=7 cells (2 PI)
7742 13:53:55.996824 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7743 13:53:55.999101 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7744 13:53:56.002575 DramC Write-DBI on
7745 13:53:56.003002 ==
7746 13:53:56.006032 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 13:53:56.009537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 13:53:56.010070 ==
7749 13:53:56.010427
7750 13:53:56.010735
7751 13:53:56.012170 TX Vref Scan disable
7752 13:53:56.015870 == TX Byte 0 ==
7753 13:53:56.019159 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7754 13:53:56.019727 == TX Byte 1 ==
7755 13:53:56.025833 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7756 13:53:56.026379 DramC Write-DBI off
7757 13:53:56.026719
7758 13:53:56.027045 [DATLAT]
7759 13:53:56.028972 Freq=1600, CH0 RK0
7760 13:53:56.029518
7761 13:53:56.032080 DATLAT Default: 0xf
7762 13:53:56.032495 0, 0xFFFF, sum = 0
7763 13:53:56.035111 1, 0xFFFF, sum = 0
7764 13:53:56.035622 2, 0xFFFF, sum = 0
7765 13:53:56.039116 3, 0xFFFF, sum = 0
7766 13:53:56.039701 4, 0xFFFF, sum = 0
7767 13:53:56.042397 5, 0xFFFF, sum = 0
7768 13:53:56.042826 6, 0xFFFF, sum = 0
7769 13:53:56.045201 7, 0xFFFF, sum = 0
7770 13:53:56.045623 8, 0xFFFF, sum = 0
7771 13:53:56.048515 9, 0xFFFF, sum = 0
7772 13:53:56.048960 10, 0xFFFF, sum = 0
7773 13:53:56.051778 11, 0xFFFF, sum = 0
7774 13:53:56.052217 12, 0xFFFF, sum = 0
7775 13:53:56.055131 13, 0xFFFF, sum = 0
7776 13:53:56.058533 14, 0x0, sum = 1
7777 13:53:56.059033 15, 0x0, sum = 2
7778 13:53:56.059456 16, 0x0, sum = 3
7779 13:53:56.062278 17, 0x0, sum = 4
7780 13:53:56.062697 best_step = 15
7781 13:53:56.063047
7782 13:53:56.063356 ==
7783 13:53:56.065170 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 13:53:56.071397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 13:53:56.072005 ==
7786 13:53:56.072533 RX Vref Scan: 1
7787 13:53:56.073040
7788 13:53:56.074717 Set Vref Range= 24 -> 127
7789 13:53:56.075285
7790 13:53:56.077567 RX Vref 24 -> 127, step: 1
7791 13:53:56.078157
7792 13:53:56.081715 RX Delay 19 -> 252, step: 4
7793 13:53:56.082131
7794 13:53:56.084458 Set Vref, RX VrefLevel [Byte0]: 24
7795 13:53:56.087945 [Byte1]: 24
7796 13:53:56.088419
7797 13:53:56.091134 Set Vref, RX VrefLevel [Byte0]: 25
7798 13:53:56.094624 [Byte1]: 25
7799 13:53:56.095042
7800 13:53:56.097878 Set Vref, RX VrefLevel [Byte0]: 26
7801 13:53:56.100847 [Byte1]: 26
7802 13:53:56.104360
7803 13:53:56.104777 Set Vref, RX VrefLevel [Byte0]: 27
7804 13:53:56.107895 [Byte1]: 27
7805 13:53:56.112382
7806 13:53:56.112893 Set Vref, RX VrefLevel [Byte0]: 28
7807 13:53:56.115833 [Byte1]: 28
7808 13:53:56.119800
7809 13:53:56.120226 Set Vref, RX VrefLevel [Byte0]: 29
7810 13:53:56.123163 [Byte1]: 29
7811 13:53:56.127330
7812 13:53:56.127883 Set Vref, RX VrefLevel [Byte0]: 30
7813 13:53:56.130886 [Byte1]: 30
7814 13:53:56.134526
7815 13:53:56.134944 Set Vref, RX VrefLevel [Byte0]: 31
7816 13:53:56.138227 [Byte1]: 31
7817 13:53:56.142555
7818 13:53:56.142973 Set Vref, RX VrefLevel [Byte0]: 32
7819 13:53:56.145443 [Byte1]: 32
7820 13:53:56.150040
7821 13:53:56.150494 Set Vref, RX VrefLevel [Byte0]: 33
7822 13:53:56.153287 [Byte1]: 33
7823 13:53:56.157592
7824 13:53:56.158008 Set Vref, RX VrefLevel [Byte0]: 34
7825 13:53:56.160834 [Byte1]: 34
7826 13:53:56.165089
7827 13:53:56.165524 Set Vref, RX VrefLevel [Byte0]: 35
7828 13:53:56.168436 [Byte1]: 35
7829 13:53:56.172507
7830 13:53:56.172865 Set Vref, RX VrefLevel [Byte0]: 36
7831 13:53:56.176058 [Byte1]: 36
7832 13:53:56.180327
7833 13:53:56.180760 Set Vref, RX VrefLevel [Byte0]: 37
7834 13:53:56.183638 [Byte1]: 37
7835 13:53:56.188177
7836 13:53:56.188620 Set Vref, RX VrefLevel [Byte0]: 38
7837 13:53:56.191507 [Byte1]: 38
7838 13:53:56.195154
7839 13:53:56.195656 Set Vref, RX VrefLevel [Byte0]: 39
7840 13:53:56.198769 [Byte1]: 39
7841 13:53:56.203222
7842 13:53:56.203737 Set Vref, RX VrefLevel [Byte0]: 40
7843 13:53:56.206050 [Byte1]: 40
7844 13:53:56.210504
7845 13:53:56.211002 Set Vref, RX VrefLevel [Byte0]: 41
7846 13:53:56.213794 [Byte1]: 41
7847 13:53:56.218822
7848 13:53:56.219333 Set Vref, RX VrefLevel [Byte0]: 42
7849 13:53:56.221553 [Byte1]: 42
7850 13:53:56.225975
7851 13:53:56.226637 Set Vref, RX VrefLevel [Byte0]: 43
7852 13:53:56.229034 [Byte1]: 43
7853 13:53:56.233675
7854 13:53:56.234204 Set Vref, RX VrefLevel [Byte0]: 44
7855 13:53:56.236667 [Byte1]: 44
7856 13:53:56.241101
7857 13:53:56.241513 Set Vref, RX VrefLevel [Byte0]: 45
7858 13:53:56.244169 [Byte1]: 45
7859 13:53:56.248707
7860 13:53:56.249120 Set Vref, RX VrefLevel [Byte0]: 46
7861 13:53:56.251593 [Byte1]: 46
7862 13:53:56.256089
7863 13:53:56.256502 Set Vref, RX VrefLevel [Byte0]: 47
7864 13:53:56.259328 [Byte1]: 47
7865 13:53:56.263631
7866 13:53:56.264046 Set Vref, RX VrefLevel [Byte0]: 48
7867 13:53:56.266987 [Byte1]: 48
7868 13:53:56.271102
7869 13:53:56.271567 Set Vref, RX VrefLevel [Byte0]: 49
7870 13:53:56.274546 [Byte1]: 49
7871 13:53:56.278744
7872 13:53:56.279269 Set Vref, RX VrefLevel [Byte0]: 50
7873 13:53:56.281753 [Byte1]: 50
7874 13:53:56.286432
7875 13:53:56.286859 Set Vref, RX VrefLevel [Byte0]: 51
7876 13:53:56.289404 [Byte1]: 51
7877 13:53:56.294271
7878 13:53:56.294686 Set Vref, RX VrefLevel [Byte0]: 52
7879 13:53:56.297157 [Byte1]: 52
7880 13:53:56.301298
7881 13:53:56.301764 Set Vref, RX VrefLevel [Byte0]: 53
7882 13:53:56.305076 [Byte1]: 53
7883 13:53:56.309571
7884 13:53:56.310135 Set Vref, RX VrefLevel [Byte0]: 54
7885 13:53:56.312621 [Byte1]: 54
7886 13:53:56.316467
7887 13:53:56.316884 Set Vref, RX VrefLevel [Byte0]: 55
7888 13:53:56.320007 [Byte1]: 55
7889 13:53:56.324227
7890 13:53:56.324646 Set Vref, RX VrefLevel [Byte0]: 56
7891 13:53:56.327730 [Byte1]: 56
7892 13:53:56.331757
7893 13:53:56.332185 Set Vref, RX VrefLevel [Byte0]: 57
7894 13:53:56.335172 [Byte1]: 57
7895 13:53:56.339058
7896 13:53:56.339520 Set Vref, RX VrefLevel [Byte0]: 58
7897 13:53:56.342512 [Byte1]: 58
7898 13:53:56.347042
7899 13:53:56.347500 Set Vref, RX VrefLevel [Byte0]: 59
7900 13:53:56.350411 [Byte1]: 59
7901 13:53:56.354463
7902 13:53:56.354879 Set Vref, RX VrefLevel [Byte0]: 60
7903 13:53:56.357553 [Byte1]: 60
7904 13:53:56.362112
7905 13:53:56.362529 Set Vref, RX VrefLevel [Byte0]: 61
7906 13:53:56.365074 [Byte1]: 61
7907 13:53:56.369285
7908 13:53:56.369703 Set Vref, RX VrefLevel [Byte0]: 62
7909 13:53:56.372574 [Byte1]: 62
7910 13:53:56.377996
7911 13:53:56.378547 Set Vref, RX VrefLevel [Byte0]: 63
7912 13:53:56.380308 [Byte1]: 63
7913 13:53:56.384723
7914 13:53:56.385144 Set Vref, RX VrefLevel [Byte0]: 64
7915 13:53:56.388294 [Byte1]: 64
7916 13:53:56.391986
7917 13:53:56.392401 Set Vref, RX VrefLevel [Byte0]: 65
7918 13:53:56.395655 [Byte1]: 65
7919 13:53:56.399895
7920 13:53:56.400308 Set Vref, RX VrefLevel [Byte0]: 66
7921 13:53:56.403279 [Byte1]: 66
7922 13:53:56.407427
7923 13:53:56.407890 Set Vref, RX VrefLevel [Byte0]: 67
7924 13:53:56.410603 [Byte1]: 67
7925 13:53:56.414972
7926 13:53:56.415428 Set Vref, RX VrefLevel [Byte0]: 68
7927 13:53:56.417942 [Byte1]: 68
7928 13:53:56.422647
7929 13:53:56.423063 Set Vref, RX VrefLevel [Byte0]: 69
7930 13:53:56.425907 [Byte1]: 69
7931 13:53:56.430217
7932 13:53:56.430633 Set Vref, RX VrefLevel [Byte0]: 70
7933 13:53:56.433216 [Byte1]: 70
7934 13:53:56.438058
7935 13:53:56.438471 Set Vref, RX VrefLevel [Byte0]: 71
7936 13:53:56.441212 [Byte1]: 71
7937 13:53:56.445370
7938 13:53:56.445785 Set Vref, RX VrefLevel [Byte0]: 72
7939 13:53:56.448597 [Byte1]: 72
7940 13:53:56.452819
7941 13:53:56.453236 Set Vref, RX VrefLevel [Byte0]: 73
7942 13:53:56.455944 [Byte1]: 73
7943 13:53:56.460800
7944 13:53:56.461213 Final RX Vref Byte 0 = 60 to rank0
7945 13:53:56.464174 Final RX Vref Byte 1 = 60 to rank0
7946 13:53:56.466919 Final RX Vref Byte 0 = 60 to rank1
7947 13:53:56.470248 Final RX Vref Byte 1 = 60 to rank1==
7948 13:53:56.473891 Dram Type= 6, Freq= 0, CH_0, rank 0
7949 13:53:56.480096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 13:53:56.480519 ==
7951 13:53:56.480852 DQS Delay:
7952 13:53:56.483291 DQS0 = 0, DQS1 = 0
7953 13:53:56.483766 DQM Delay:
7954 13:53:56.486511 DQM0 = 128, DQM1 = 124
7955 13:53:56.486925 DQ Delay:
7956 13:53:56.489884 DQ0 =128, DQ1 =130, DQ2 =126, DQ3 =124
7957 13:53:56.493414 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7958 13:53:56.496638 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7959 13:53:56.500088 DQ12 =132, DQ13 =128, DQ14 =134, DQ15 =130
7960 13:53:56.500503
7961 13:53:56.500831
7962 13:53:56.501135
7963 13:53:56.502750 [DramC_TX_OE_Calibration] TA2
7964 13:53:56.506529 Original DQ_B0 (3 6) =30, OEN = 27
7965 13:53:56.509809 Original DQ_B1 (3 6) =30, OEN = 27
7966 13:53:56.512918 24, 0x0, End_B0=24 End_B1=24
7967 13:53:56.516599 25, 0x0, End_B0=25 End_B1=25
7968 13:53:56.517024 26, 0x0, End_B0=26 End_B1=26
7969 13:53:56.519469 27, 0x0, End_B0=27 End_B1=27
7970 13:53:56.522889 28, 0x0, End_B0=28 End_B1=28
7971 13:53:56.526298 29, 0x0, End_B0=29 End_B1=29
7972 13:53:56.529247 30, 0x0, End_B0=30 End_B1=30
7973 13:53:56.529671 31, 0x4141, End_B0=30 End_B1=30
7974 13:53:56.532326 Byte0 end_step=30 best_step=27
7975 13:53:56.535650 Byte1 end_step=30 best_step=27
7976 13:53:56.539130 Byte0 TX OE(2T, 0.5T) = (3, 3)
7977 13:53:56.542392 Byte1 TX OE(2T, 0.5T) = (3, 3)
7978 13:53:56.542805
7979 13:53:56.543128
7980 13:53:56.549332 [DQSOSCAuto] RK0, (LSB)MR18= 0x1612, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7981 13:53:56.551923 CH0 RK0: MR19=303, MR18=1612
7982 13:53:56.558601 CH0_RK0: MR19=0x303, MR18=0x1612, DQSOSC=398, MR23=63, INC=23, DEC=15
7983 13:53:56.559144
7984 13:53:56.562020 ----->DramcWriteLeveling(PI) begin...
7985 13:53:56.562438 ==
7986 13:53:56.565535 Dram Type= 6, Freq= 0, CH_0, rank 1
7987 13:53:56.568865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 13:53:56.571915 ==
7989 13:53:56.572421 Write leveling (Byte 0): 33 => 33
7990 13:53:56.575261 Write leveling (Byte 1): 28 => 28
7991 13:53:56.578522 DramcWriteLeveling(PI) end<-----
7992 13:53:56.578930
7993 13:53:56.579255 ==
7994 13:53:56.581998 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 13:53:56.587920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 13:53:56.588333 ==
7997 13:53:56.591802 [Gating] SW mode calibration
7998 13:53:56.598803 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7999 13:53:56.601394 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8000 13:53:56.608236 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 13:53:56.611313 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 13:53:56.614653 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8003 13:53:56.620984 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8004 13:53:56.624712 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8005 13:53:56.627466 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 13:53:56.634301 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 13:53:56.637692 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 13:53:56.641210 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 13:53:56.647576 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8010 13:53:56.650546 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8011 13:53:56.654206 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8012 13:53:56.660309 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8013 13:53:56.664159 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8014 13:53:56.667436 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 13:53:56.673521 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 13:53:56.677079 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 13:53:56.680483 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8018 13:53:56.686790 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8019 13:53:56.690067 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8020 13:53:56.693987 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8021 13:53:56.700588 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 13:53:56.703205 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 13:53:56.706520 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 13:53:56.713421 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 13:53:56.716450 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8026 13:53:56.719743 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 13:53:56.726281 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8028 13:53:56.729349 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8029 13:53:56.732822 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 13:53:56.739617 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 13:53:56.743108 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 13:53:56.746408 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 13:53:56.752530 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 13:53:56.756027 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 13:53:56.759424 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 13:53:56.765546 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 13:53:56.768936 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 13:53:56.772951 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 13:53:56.779018 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 13:53:56.782357 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 13:53:56.785520 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 13:53:56.792134 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 13:53:56.795465 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8044 13:53:56.799006 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8045 13:53:56.802162 Total UI for P1: 0, mck2ui 16
8046 13:53:56.805503 best dqsien dly found for B0: ( 1, 9, 10)
8047 13:53:56.811666 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8048 13:53:56.815529 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 13:53:56.818385 Total UI for P1: 0, mck2ui 16
8050 13:53:56.821591 best dqsien dly found for B1: ( 1, 9, 18)
8051 13:53:56.825012 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8052 13:53:56.828477 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8053 13:53:56.828931
8054 13:53:56.831776 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8055 13:53:56.837937 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8056 13:53:56.838682 [Gating] SW calibration Done
8057 13:53:56.841754 ==
8058 13:53:56.844477 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 13:53:56.847979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 13:53:56.848379 ==
8061 13:53:56.848719 RX Vref Scan: 0
8062 13:53:56.849041
8063 13:53:56.850996 RX Vref 0 -> 0, step: 1
8064 13:53:56.851432
8065 13:53:56.854164 RX Delay 0 -> 252, step: 8
8066 13:53:56.857394 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8067 13:53:56.860913 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8068 13:53:56.863968 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8069 13:53:56.871039 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8070 13:53:56.874143 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8071 13:53:56.877494 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8072 13:53:56.881191 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8073 13:53:56.883706 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8074 13:53:56.890928 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8075 13:53:56.894055 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8076 13:53:56.897752 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8077 13:53:56.900943 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8078 13:53:56.907581 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8079 13:53:56.910792 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8080 13:53:56.914155 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8081 13:53:56.917031 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8082 13:53:56.917441 ==
8083 13:53:56.920555 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 13:53:56.927058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 13:53:56.927501 ==
8086 13:53:56.927834 DQS Delay:
8087 13:53:56.930181 DQS0 = 0, DQS1 = 0
8088 13:53:56.930614 DQM Delay:
8089 13:53:56.933643 DQM0 = 132, DQM1 = 124
8090 13:53:56.934057 DQ Delay:
8091 13:53:56.936885 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8092 13:53:56.940409 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8093 13:53:56.943464 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8094 13:53:56.946482 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8095 13:53:56.946894
8096 13:53:56.947219
8097 13:53:56.947591 ==
8098 13:53:56.950040 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 13:53:56.956312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 13:53:56.956730 ==
8101 13:53:56.957087
8102 13:53:56.957399
8103 13:53:56.957697 TX Vref Scan disable
8104 13:53:56.960254 == TX Byte 0 ==
8105 13:53:56.963578 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8106 13:53:56.970015 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8107 13:53:56.970452 == TX Byte 1 ==
8108 13:53:56.973183 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8109 13:53:56.979479 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8110 13:53:56.979896 ==
8111 13:53:56.982754 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 13:53:56.985859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 13:53:56.986272 ==
8114 13:53:56.999215
8115 13:53:57.002934 TX Vref early break, caculate TX vref
8116 13:53:57.005918 TX Vref=16, minBit 9, minWin=23, winSum=383
8117 13:53:57.009542 TX Vref=18, minBit 0, minWin=24, winSum=390
8118 13:53:57.012192 TX Vref=20, minBit 2, minWin=24, winSum=400
8119 13:53:57.015773 TX Vref=22, minBit 0, minWin=25, winSum=406
8120 13:53:57.019278 TX Vref=24, minBit 1, minWin=25, winSum=415
8121 13:53:57.026334 TX Vref=26, minBit 1, minWin=25, winSum=421
8122 13:53:57.029275 TX Vref=28, minBit 0, minWin=26, winSum=424
8123 13:53:57.032165 TX Vref=30, minBit 2, minWin=25, winSum=419
8124 13:53:57.035406 TX Vref=32, minBit 7, minWin=24, winSum=411
8125 13:53:57.039019 TX Vref=34, minBit 1, minWin=24, winSum=399
8126 13:53:57.045254 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8127 13:53:57.045677
8128 13:53:57.048743 Final TX Range 0 Vref 28
8129 13:53:57.049164
8130 13:53:57.049495 ==
8131 13:53:57.051954 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 13:53:57.055029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 13:53:57.055478 ==
8134 13:53:57.055817
8135 13:53:57.056156
8136 13:53:57.058375 TX Vref Scan disable
8137 13:53:57.064853 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8138 13:53:57.065302 == TX Byte 0 ==
8139 13:53:57.068658 u2DelayCellOfst[0]=14 cells (4 PI)
8140 13:53:57.071928 u2DelayCellOfst[1]=17 cells (5 PI)
8141 13:53:57.074823 u2DelayCellOfst[2]=14 cells (4 PI)
8142 13:53:57.077932 u2DelayCellOfst[3]=10 cells (3 PI)
8143 13:53:57.081445 u2DelayCellOfst[4]=10 cells (3 PI)
8144 13:53:57.084957 u2DelayCellOfst[5]=0 cells (0 PI)
8145 13:53:57.087828 u2DelayCellOfst[6]=17 cells (5 PI)
8146 13:53:57.091069 u2DelayCellOfst[7]=17 cells (5 PI)
8147 13:53:57.094335 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8148 13:53:57.098112 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8149 13:53:57.101616 == TX Byte 1 ==
8150 13:53:57.104295 u2DelayCellOfst[8]=0 cells (0 PI)
8151 13:53:57.107645 u2DelayCellOfst[9]=0 cells (0 PI)
8152 13:53:57.111111 u2DelayCellOfst[10]=7 cells (2 PI)
8153 13:53:57.114072 u2DelayCellOfst[11]=3 cells (1 PI)
8154 13:53:57.114603 u2DelayCellOfst[12]=10 cells (3 PI)
8155 13:53:57.117801 u2DelayCellOfst[13]=10 cells (3 PI)
8156 13:53:57.121099 u2DelayCellOfst[14]=17 cells (5 PI)
8157 13:53:57.124480 u2DelayCellOfst[15]=10 cells (3 PI)
8158 13:53:57.131014 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8159 13:53:57.134177 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8160 13:53:57.134596 DramC Write-DBI on
8161 13:53:57.137302 ==
8162 13:53:57.141019 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 13:53:57.144158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 13:53:57.144579 ==
8165 13:53:57.144939
8166 13:53:57.145272
8167 13:53:57.147544 TX Vref Scan disable
8168 13:53:57.147967 == TX Byte 0 ==
8169 13:53:57.154211 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8170 13:53:57.154627 == TX Byte 1 ==
8171 13:53:57.157433 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8172 13:53:57.160494 DramC Write-DBI off
8173 13:53:57.160911
8174 13:53:57.161253 [DATLAT]
8175 13:53:57.163459 Freq=1600, CH0 RK1
8176 13:53:57.163877
8177 13:53:57.164207 DATLAT Default: 0xf
8178 13:53:57.167098 0, 0xFFFF, sum = 0
8179 13:53:57.167744 1, 0xFFFF, sum = 0
8180 13:53:57.170066 2, 0xFFFF, sum = 0
8181 13:53:57.173863 3, 0xFFFF, sum = 0
8182 13:53:57.174286 4, 0xFFFF, sum = 0
8183 13:53:57.176681 5, 0xFFFF, sum = 0
8184 13:53:57.177105 6, 0xFFFF, sum = 0
8185 13:53:57.180554 7, 0xFFFF, sum = 0
8186 13:53:57.180976 8, 0xFFFF, sum = 0
8187 13:53:57.183682 9, 0xFFFF, sum = 0
8188 13:53:57.184162 10, 0xFFFF, sum = 0
8189 13:53:57.186602 11, 0xFFFF, sum = 0
8190 13:53:57.187101 12, 0xFFFF, sum = 0
8191 13:53:57.189963 13, 0xFFFF, sum = 0
8192 13:53:57.190554 14, 0x0, sum = 1
8193 13:53:57.193486 15, 0x0, sum = 2
8194 13:53:57.193925 16, 0x0, sum = 3
8195 13:53:57.196761 17, 0x0, sum = 4
8196 13:53:57.197183 best_step = 15
8197 13:53:57.197606
8198 13:53:57.198149 ==
8199 13:53:57.199760 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 13:53:57.206473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 13:53:57.206966 ==
8202 13:53:57.207330 RX Vref Scan: 0
8203 13:53:57.207714
8204 13:53:57.209744 RX Vref 0 -> 0, step: 1
8205 13:53:57.210156
8206 13:53:57.212843 RX Delay 11 -> 252, step: 4
8207 13:53:57.216285 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8208 13:53:57.219349 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8209 13:53:57.223076 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8210 13:53:57.230385 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8211 13:53:57.232927 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8212 13:53:57.236489 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8213 13:53:57.239352 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8214 13:53:57.242784 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8215 13:53:57.249443 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8216 13:53:57.253304 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8217 13:53:57.255483 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8218 13:53:57.259112 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8219 13:53:57.265503 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8220 13:53:57.269586 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8221 13:53:57.271911 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8222 13:53:57.275597 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8223 13:53:57.275998 ==
8224 13:53:57.278822 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 13:53:57.285787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 13:53:57.286331 ==
8227 13:53:57.286787 DQS Delay:
8228 13:53:57.289022 DQS0 = 0, DQS1 = 0
8229 13:53:57.289405 DQM Delay:
8230 13:53:57.291895 DQM0 = 128, DQM1 = 124
8231 13:53:57.292270 DQ Delay:
8232 13:53:57.295040 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8233 13:53:57.298450 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
8234 13:53:57.302394 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8235 13:53:57.304905 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8236 13:53:57.305305
8237 13:53:57.305729
8238 13:53:57.306252
8239 13:53:57.308564 [DramC_TX_OE_Calibration] TA2
8240 13:53:57.312477 Original DQ_B0 (3 6) =30, OEN = 27
8241 13:53:57.315280 Original DQ_B1 (3 6) =30, OEN = 27
8242 13:53:57.318688 24, 0x0, End_B0=24 End_B1=24
8243 13:53:57.321242 25, 0x0, End_B0=25 End_B1=25
8244 13:53:57.321666 26, 0x0, End_B0=26 End_B1=26
8245 13:53:57.324513 27, 0x0, End_B0=27 End_B1=27
8246 13:53:57.328390 28, 0x0, End_B0=28 End_B1=28
8247 13:53:57.331258 29, 0x0, End_B0=29 End_B1=29
8248 13:53:57.334543 30, 0x0, End_B0=30 End_B1=30
8249 13:53:57.334988 31, 0x5151, End_B0=30 End_B1=30
8250 13:53:57.337983 Byte0 end_step=30 best_step=27
8251 13:53:57.341036 Byte1 end_step=30 best_step=27
8252 13:53:57.344418 Byte0 TX OE(2T, 0.5T) = (3, 3)
8253 13:53:57.347854 Byte1 TX OE(2T, 0.5T) = (3, 3)
8254 13:53:57.348268
8255 13:53:57.348597
8256 13:53:57.354059 [DQSOSCAuto] RK1, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
8257 13:53:57.358001 CH0 RK1: MR19=303, MR18=1613
8258 13:53:57.364092 CH0_RK1: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
8259 13:53:57.367463 [RxdqsGatingPostProcess] freq 1600
8260 13:53:57.374573 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8261 13:53:57.377475 best DQS0 dly(2T, 0.5T) = (1, 1)
8262 13:53:57.377889 best DQS1 dly(2T, 0.5T) = (1, 1)
8263 13:53:57.380711 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8264 13:53:57.384074 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8265 13:53:57.387068 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 13:53:57.390722 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 13:53:57.393914 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 13:53:57.397408 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 13:53:57.400210 Pre-setting of DQS Precalculation
8270 13:53:57.403464 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8271 13:53:57.406876 ==
8272 13:53:57.410226 Dram Type= 6, Freq= 0, CH_1, rank 0
8273 13:53:57.413357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 13:53:57.413818 ==
8275 13:53:57.420073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 13:53:57.423405 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 13:53:57.426996 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 13:53:57.433238 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 13:53:57.441646 [CA 0] Center 42 (12~72) winsize 61
8280 13:53:57.445053 [CA 1] Center 42 (13~72) winsize 60
8281 13:53:57.448655 [CA 2] Center 38 (9~68) winsize 60
8282 13:53:57.451773 [CA 3] Center 37 (8~67) winsize 60
8283 13:53:57.455096 [CA 4] Center 38 (8~68) winsize 61
8284 13:53:57.458120 [CA 5] Center 36 (7~66) winsize 60
8285 13:53:57.458507
8286 13:53:57.461542 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8287 13:53:57.461960
8288 13:53:57.465186 [CATrainingPosCal] consider 1 rank data
8289 13:53:57.468311 u2DelayCellTimex100 = 275/100 ps
8290 13:53:57.474792 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8291 13:53:57.477786 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8292 13:53:57.481466 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8293 13:53:57.484161 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8294 13:53:57.487834 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8295 13:53:57.491024 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8296 13:53:57.491106
8297 13:53:57.494369 CA PerBit enable=1, Macro0, CA PI delay=36
8298 13:53:57.494447
8299 13:53:57.497394 [CBTSetCACLKResult] CA Dly = 36
8300 13:53:57.500847 CS Dly: 8 (0~39)
8301 13:53:57.504136 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 13:53:57.507219 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 13:53:57.507316 ==
8304 13:53:57.510338 Dram Type= 6, Freq= 0, CH_1, rank 1
8305 13:53:57.516944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 13:53:57.517020 ==
8307 13:53:57.520132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 13:53:57.526595 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 13:53:57.530529 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 13:53:57.536478 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 13:53:57.544335 [CA 0] Center 41 (11~71) winsize 61
8312 13:53:57.547597 [CA 1] Center 42 (13~71) winsize 59
8313 13:53:57.550960 [CA 2] Center 37 (8~67) winsize 60
8314 13:53:57.554220 [CA 3] Center 36 (7~66) winsize 60
8315 13:53:57.557875 [CA 4] Center 36 (7~66) winsize 60
8316 13:53:57.560760 [CA 5] Center 36 (6~66) winsize 61
8317 13:53:57.560837
8318 13:53:57.564158 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 13:53:57.564233
8320 13:53:57.567328 [CATrainingPosCal] consider 2 rank data
8321 13:53:57.570660 u2DelayCellTimex100 = 275/100 ps
8322 13:53:57.577225 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8323 13:53:57.580641 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8324 13:53:57.583951 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8325 13:53:57.587720 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8326 13:53:57.591118 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8327 13:53:57.593911 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8328 13:53:57.594011
8329 13:53:57.597362 CA PerBit enable=1, Macro0, CA PI delay=36
8330 13:53:57.597460
8331 13:53:57.600723 [CBTSetCACLKResult] CA Dly = 36
8332 13:53:57.604465 CS Dly: 9 (0~42)
8333 13:53:57.607293 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 13:53:57.610536 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 13:53:57.610633
8336 13:53:57.614265 ----->DramcWriteLeveling(PI) begin...
8337 13:53:57.614364 ==
8338 13:53:57.616992 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 13:53:57.623800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 13:53:57.623905 ==
8341 13:53:57.627029 Write leveling (Byte 0): 26 => 26
8342 13:53:57.630016 Write leveling (Byte 1): 26 => 26
8343 13:53:57.630090 DramcWriteLeveling(PI) end<-----
8344 13:53:57.633565
8345 13:53:57.633636 ==
8346 13:53:57.636665 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 13:53:57.639989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 13:53:57.640063 ==
8349 13:53:57.643041 [Gating] SW mode calibration
8350 13:53:57.650217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8351 13:53:57.653309 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8352 13:53:57.659946 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 13:53:57.663228 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 13:53:57.666291 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8355 13:53:57.672791 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8356 13:53:57.675988 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 13:53:57.683129 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 13:53:57.686159 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 13:53:57.689545 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 13:53:57.692581 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 13:53:57.699120 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 13:53:57.702425 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 13:53:57.706006 1 5 12 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
8364 13:53:57.712560 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8365 13:53:57.715677 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 13:53:57.719385 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 13:53:57.725686 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 13:53:57.728776 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 13:53:57.732105 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 13:53:57.738749 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8371 13:53:57.742432 1 6 12 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
8372 13:53:57.745479 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 13:53:57.752156 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 13:53:57.755211 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 13:53:57.758866 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 13:53:57.765240 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 13:53:57.768228 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 13:53:57.775416 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8379 13:53:57.778976 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8380 13:53:57.781856 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8381 13:53:57.788232 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 13:53:57.791377 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 13:53:57.794788 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 13:53:57.801617 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 13:53:57.804736 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 13:53:57.808015 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 13:53:57.814520 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 13:53:57.817804 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 13:53:57.821085 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 13:53:57.827403 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 13:53:57.831001 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 13:53:57.834375 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 13:53:57.840610 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 13:53:57.844039 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8395 13:53:57.847377 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8396 13:53:57.854081 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8397 13:53:57.854162 Total UI for P1: 0, mck2ui 16
8398 13:53:57.861201 best dqsien dly found for B0: ( 1, 9, 10)
8399 13:53:57.863602 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 13:53:57.867154 Total UI for P1: 0, mck2ui 16
8401 13:53:57.870146 best dqsien dly found for B1: ( 1, 9, 14)
8402 13:53:57.873433 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8403 13:53:57.876955 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8404 13:53:57.877028
8405 13:53:57.880311 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8406 13:53:57.883303 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8407 13:53:57.886644 [Gating] SW calibration Done
8408 13:53:57.886718 ==
8409 13:53:57.890192 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 13:53:57.893586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 13:53:57.896706 ==
8412 13:53:57.896783 RX Vref Scan: 0
8413 13:53:57.896848
8414 13:53:57.899827 RX Vref 0 -> 0, step: 1
8415 13:53:57.899900
8416 13:53:57.903262 RX Delay 0 -> 252, step: 8
8417 13:53:57.906942 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8418 13:53:57.909994 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8419 13:53:57.913385 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8420 13:53:57.916568 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8421 13:53:57.923149 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8422 13:53:57.926426 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8423 13:53:57.929828 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8424 13:53:57.932733 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8425 13:53:57.936222 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8426 13:53:57.942708 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8427 13:53:57.946459 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8428 13:53:57.949928 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8429 13:53:57.952936 iDelay=200, Bit 12, Center 143 (96 ~ 191) 96
8430 13:53:57.955812 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8431 13:53:57.962608 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8432 13:53:57.965644 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8433 13:53:57.965739 ==
8434 13:53:57.969250 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 13:53:57.972387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 13:53:57.972464 ==
8437 13:53:57.975853 DQS Delay:
8438 13:53:57.975923 DQS0 = 0, DQS1 = 0
8439 13:53:57.979221 DQM Delay:
8440 13:53:57.979319 DQM0 = 135, DQM1 = 132
8441 13:53:57.979440 DQ Delay:
8442 13:53:57.982173 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8443 13:53:57.988792 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =131
8444 13:53:57.991923 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8445 13:53:57.995474 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8446 13:53:57.995549
8447 13:53:57.995612
8448 13:53:57.995671 ==
8449 13:53:57.998521 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 13:53:58.001991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 13:53:58.002071 ==
8452 13:53:58.002134
8453 13:53:58.002192
8454 13:53:58.005138 TX Vref Scan disable
8455 13:53:58.008312 == TX Byte 0 ==
8456 13:53:58.011855 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8457 13:53:58.015167 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8458 13:53:58.018680 == TX Byte 1 ==
8459 13:53:58.022060 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8460 13:53:58.024849 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8461 13:53:58.024924 ==
8462 13:53:58.028622 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 13:53:58.034543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 13:53:58.034625 ==
8465 13:53:58.046247
8466 13:53:58.049475 TX Vref early break, caculate TX vref
8467 13:53:58.052573 TX Vref=16, minBit 8, minWin=22, winSum=369
8468 13:53:58.056236 TX Vref=18, minBit 12, minWin=22, winSum=378
8469 13:53:58.059738 TX Vref=20, minBit 3, minWin=23, winSum=386
8470 13:53:58.062649 TX Vref=22, minBit 8, minWin=23, winSum=394
8471 13:53:58.065635 TX Vref=24, minBit 9, minWin=23, winSum=405
8472 13:53:58.072595 TX Vref=26, minBit 3, minWin=25, winSum=415
8473 13:53:58.075766 TX Vref=28, minBit 11, minWin=25, winSum=419
8474 13:53:58.078936 TX Vref=30, minBit 0, minWin=25, winSum=417
8475 13:53:58.082496 TX Vref=32, minBit 0, minWin=24, winSum=407
8476 13:53:58.085779 TX Vref=34, minBit 11, minWin=23, winSum=394
8477 13:53:58.092147 [TxChooseVref] Worse bit 11, Min win 25, Win sum 419, Final Vref 28
8478 13:53:58.092253
8479 13:53:58.095152 Final TX Range 0 Vref 28
8480 13:53:58.095249
8481 13:53:58.095340 ==
8482 13:53:58.098737 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 13:53:58.102504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 13:53:58.102580 ==
8485 13:53:58.105306
8486 13:53:58.105405
8487 13:53:58.105494 TX Vref Scan disable
8488 13:53:58.111837 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8489 13:53:58.111916 == TX Byte 0 ==
8490 13:53:58.115292 u2DelayCellOfst[0]=14 cells (4 PI)
8491 13:53:58.118957 u2DelayCellOfst[1]=10 cells (3 PI)
8492 13:53:58.121674 u2DelayCellOfst[2]=0 cells (0 PI)
8493 13:53:58.124991 u2DelayCellOfst[3]=7 cells (2 PI)
8494 13:53:58.128660 u2DelayCellOfst[4]=7 cells (2 PI)
8495 13:53:58.131839 u2DelayCellOfst[5]=17 cells (5 PI)
8496 13:53:58.135099 u2DelayCellOfst[6]=14 cells (4 PI)
8497 13:53:58.138048 u2DelayCellOfst[7]=7 cells (2 PI)
8498 13:53:58.141555 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8499 13:53:58.144747 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8500 13:53:58.147871 == TX Byte 1 ==
8501 13:53:58.151262 u2DelayCellOfst[8]=0 cells (0 PI)
8502 13:53:58.154310 u2DelayCellOfst[9]=3 cells (1 PI)
8503 13:53:58.158316 u2DelayCellOfst[10]=14 cells (4 PI)
8504 13:53:58.161957 u2DelayCellOfst[11]=3 cells (1 PI)
8505 13:53:58.164314 u2DelayCellOfst[12]=14 cells (4 PI)
8506 13:53:58.167559 u2DelayCellOfst[13]=17 cells (5 PI)
8507 13:53:58.171251 u2DelayCellOfst[14]=17 cells (5 PI)
8508 13:53:58.174314 u2DelayCellOfst[15]=17 cells (5 PI)
8509 13:53:58.177472 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8510 13:53:58.180872 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8511 13:53:58.184086 DramC Write-DBI on
8512 13:53:58.184158 ==
8513 13:53:58.187684 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 13:53:58.190805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 13:53:58.190880 ==
8516 13:53:58.190941
8517 13:53:58.190998
8518 13:53:58.194458 TX Vref Scan disable
8519 13:53:58.194585 == TX Byte 0 ==
8520 13:53:58.200542 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8521 13:53:58.200615 == TX Byte 1 ==
8522 13:53:58.207161 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8523 13:53:58.207260 DramC Write-DBI off
8524 13:53:58.207349
8525 13:53:58.207478 [DATLAT]
8526 13:53:58.210408 Freq=1600, CH1 RK0
8527 13:53:58.210506
8528 13:53:58.213756 DATLAT Default: 0xf
8529 13:53:58.213851 0, 0xFFFF, sum = 0
8530 13:53:58.217123 1, 0xFFFF, sum = 0
8531 13:53:58.217221 2, 0xFFFF, sum = 0
8532 13:53:58.220670 3, 0xFFFF, sum = 0
8533 13:53:58.220745 4, 0xFFFF, sum = 0
8534 13:53:58.223585 5, 0xFFFF, sum = 0
8535 13:53:58.223681 6, 0xFFFF, sum = 0
8536 13:53:58.226714 7, 0xFFFF, sum = 0
8537 13:53:58.226802 8, 0xFFFF, sum = 0
8538 13:53:58.229987 9, 0xFFFF, sum = 0
8539 13:53:58.230090 10, 0xFFFF, sum = 0
8540 13:53:58.233569 11, 0xFFFF, sum = 0
8541 13:53:58.233667 12, 0xFFFF, sum = 0
8542 13:53:58.236829 13, 0xFFFF, sum = 0
8543 13:53:58.236909 14, 0x0, sum = 1
8544 13:53:58.240039 15, 0x0, sum = 2
8545 13:53:58.240142 16, 0x0, sum = 3
8546 13:53:58.243220 17, 0x0, sum = 4
8547 13:53:58.243289 best_step = 15
8548 13:53:58.243410
8549 13:53:58.243471 ==
8550 13:53:58.246794 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 13:53:58.252851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 13:53:58.252930 ==
8553 13:53:58.252995 RX Vref Scan: 1
8554 13:53:58.253054
8555 13:53:58.256931 Set Vref Range= 24 -> 127
8556 13:53:58.257001
8557 13:53:58.259778 RX Vref 24 -> 127, step: 1
8558 13:53:58.259870
8559 13:53:58.263114 RX Delay 19 -> 252, step: 4
8560 13:53:58.263217
8561 13:53:58.266301 Set Vref, RX VrefLevel [Byte0]: 24
8562 13:53:58.269464 [Byte1]: 24
8563 13:53:58.269560
8564 13:53:58.272868 Set Vref, RX VrefLevel [Byte0]: 25
8565 13:53:58.275782 [Byte1]: 25
8566 13:53:58.275850
8567 13:53:58.279280 Set Vref, RX VrefLevel [Byte0]: 26
8568 13:53:58.282376 [Byte1]: 26
8569 13:53:58.285974
8570 13:53:58.286072 Set Vref, RX VrefLevel [Byte0]: 27
8571 13:53:58.289130 [Byte1]: 27
8572 13:53:58.293711
8573 13:53:58.293813 Set Vref, RX VrefLevel [Byte0]: 28
8574 13:53:58.296779 [Byte1]: 28
8575 13:53:58.301281
8576 13:53:58.301380 Set Vref, RX VrefLevel [Byte0]: 29
8577 13:53:58.304106 [Byte1]: 29
8578 13:53:58.308783
8579 13:53:58.308854 Set Vref, RX VrefLevel [Byte0]: 30
8580 13:53:58.312085 [Byte1]: 30
8581 13:53:58.316431
8582 13:53:58.316497 Set Vref, RX VrefLevel [Byte0]: 31
8583 13:53:58.319683 [Byte1]: 31
8584 13:53:58.324109
8585 13:53:58.324177 Set Vref, RX VrefLevel [Byte0]: 32
8586 13:53:58.327266 [Byte1]: 32
8587 13:53:58.331252
8588 13:53:58.331325 Set Vref, RX VrefLevel [Byte0]: 33
8589 13:53:58.334494 [Byte1]: 33
8590 13:53:58.338915
8591 13:53:58.338991 Set Vref, RX VrefLevel [Byte0]: 34
8592 13:53:58.343136 [Byte1]: 34
8593 13:53:58.346443
8594 13:53:58.346523 Set Vref, RX VrefLevel [Byte0]: 35
8595 13:53:58.349791 [Byte1]: 35
8596 13:53:58.353843
8597 13:53:58.353943 Set Vref, RX VrefLevel [Byte0]: 36
8598 13:53:58.357744 [Byte1]: 36
8599 13:53:58.361495
8600 13:53:58.361610 Set Vref, RX VrefLevel [Byte0]: 37
8601 13:53:58.365364 [Byte1]: 37
8602 13:53:58.369181
8603 13:53:58.369258 Set Vref, RX VrefLevel [Byte0]: 38
8604 13:53:58.372728 [Byte1]: 38
8605 13:53:58.376706
8606 13:53:58.376781 Set Vref, RX VrefLevel [Byte0]: 39
8607 13:53:58.380389 [Byte1]: 39
8608 13:53:58.384574
8609 13:53:58.384645 Set Vref, RX VrefLevel [Byte0]: 40
8610 13:53:58.387513 [Byte1]: 40
8611 13:53:58.392359
8612 13:53:58.392433 Set Vref, RX VrefLevel [Byte0]: 41
8613 13:53:58.395879 [Byte1]: 41
8614 13:53:58.399554
8615 13:53:58.399626 Set Vref, RX VrefLevel [Byte0]: 42
8616 13:53:58.402934 [Byte1]: 42
8617 13:53:58.407219
8618 13:53:58.407344 Set Vref, RX VrefLevel [Byte0]: 43
8619 13:53:58.411015 [Byte1]: 43
8620 13:53:58.415041
8621 13:53:58.415139 Set Vref, RX VrefLevel [Byte0]: 44
8622 13:53:58.417976 [Byte1]: 44
8623 13:53:58.422137
8624 13:53:58.422234 Set Vref, RX VrefLevel [Byte0]: 45
8625 13:53:58.425513 [Byte1]: 45
8626 13:53:58.429730
8627 13:53:58.429827 Set Vref, RX VrefLevel [Byte0]: 46
8628 13:53:58.432891 [Byte1]: 46
8629 13:53:58.437441
8630 13:53:58.437544 Set Vref, RX VrefLevel [Byte0]: 47
8631 13:53:58.440586 [Byte1]: 47
8632 13:53:58.444925
8633 13:53:58.445023 Set Vref, RX VrefLevel [Byte0]: 48
8634 13:53:58.448465 [Byte1]: 48
8635 13:53:58.452865
8636 13:53:58.452937 Set Vref, RX VrefLevel [Byte0]: 49
8637 13:53:58.455821 [Byte1]: 49
8638 13:53:58.459972
8639 13:53:58.460072 Set Vref, RX VrefLevel [Byte0]: 50
8640 13:53:58.463560 [Byte1]: 50
8641 13:53:58.467924
8642 13:53:58.468026 Set Vref, RX VrefLevel [Byte0]: 51
8643 13:53:58.471548 [Byte1]: 51
8644 13:53:58.475680
8645 13:53:58.475779 Set Vref, RX VrefLevel [Byte0]: 52
8646 13:53:58.478526 [Byte1]: 52
8647 13:53:58.482887
8648 13:53:58.482981 Set Vref, RX VrefLevel [Byte0]: 53
8649 13:53:58.486102 [Byte1]: 53
8650 13:53:58.490719
8651 13:53:58.490817 Set Vref, RX VrefLevel [Byte0]: 54
8652 13:53:58.493957 [Byte1]: 54
8653 13:53:58.497965
8654 13:53:58.498060 Set Vref, RX VrefLevel [Byte0]: 55
8655 13:53:58.501240 [Byte1]: 55
8656 13:53:58.505420
8657 13:53:58.505520 Set Vref, RX VrefLevel [Byte0]: 56
8658 13:53:58.508693 [Byte1]: 56
8659 13:53:58.513075
8660 13:53:58.513175 Set Vref, RX VrefLevel [Byte0]: 57
8661 13:53:58.516423 [Byte1]: 57
8662 13:53:58.520852
8663 13:53:58.520951 Set Vref, RX VrefLevel [Byte0]: 58
8664 13:53:58.524334 [Byte1]: 58
8665 13:53:58.528107
8666 13:53:58.528186 Set Vref, RX VrefLevel [Byte0]: 59
8667 13:53:58.532017 [Byte1]: 59
8668 13:53:58.535847
8669 13:53:58.535916 Set Vref, RX VrefLevel [Byte0]: 60
8670 13:53:58.539150 [Byte1]: 60
8671 13:53:58.543596
8672 13:53:58.543673 Set Vref, RX VrefLevel [Byte0]: 61
8673 13:53:58.546739 [Byte1]: 61
8674 13:53:58.550870
8675 13:53:58.550968 Set Vref, RX VrefLevel [Byte0]: 62
8676 13:53:58.554578 [Byte1]: 62
8677 13:53:58.558826
8678 13:53:58.558926 Set Vref, RX VrefLevel [Byte0]: 63
8679 13:53:58.561862 [Byte1]: 63
8680 13:53:58.565950
8681 13:53:58.566053 Set Vref, RX VrefLevel [Byte0]: 64
8682 13:53:58.569609 [Byte1]: 64
8683 13:53:58.573643
8684 13:53:58.573742 Set Vref, RX VrefLevel [Byte0]: 65
8685 13:53:58.577382 [Byte1]: 65
8686 13:53:58.581510
8687 13:53:58.581608 Set Vref, RX VrefLevel [Byte0]: 66
8688 13:53:58.584492 [Byte1]: 66
8689 13:53:58.588791
8690 13:53:58.588862 Set Vref, RX VrefLevel [Byte0]: 67
8691 13:53:58.592458 [Byte1]: 67
8692 13:53:58.596666
8693 13:53:58.596737 Set Vref, RX VrefLevel [Byte0]: 68
8694 13:53:58.599840 [Byte1]: 68
8695 13:53:58.604228
8696 13:53:58.604303 Set Vref, RX VrefLevel [Byte0]: 69
8697 13:53:58.607132 [Byte1]: 69
8698 13:53:58.611917
8699 13:53:58.612017 Set Vref, RX VrefLevel [Byte0]: 70
8700 13:53:58.615118 [Byte1]: 70
8701 13:53:58.619297
8702 13:53:58.619438 Set Vref, RX VrefLevel [Byte0]: 71
8703 13:53:58.622208 [Byte1]: 71
8704 13:53:58.626740
8705 13:53:58.626838 Final RX Vref Byte 0 = 55 to rank0
8706 13:53:58.629830 Final RX Vref Byte 1 = 55 to rank0
8707 13:53:58.633707 Final RX Vref Byte 0 = 55 to rank1
8708 13:53:58.636765 Final RX Vref Byte 1 = 55 to rank1==
8709 13:53:58.639753 Dram Type= 6, Freq= 0, CH_1, rank 0
8710 13:53:58.646232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8711 13:53:58.646340 ==
8712 13:53:58.646449 DQS Delay:
8713 13:53:58.649521 DQS0 = 0, DQS1 = 0
8714 13:53:58.649617 DQM Delay:
8715 13:53:58.649707 DQM0 = 131, DQM1 = 130
8716 13:53:58.652776 DQ Delay:
8717 13:53:58.656408 DQ0 =140, DQ1 =130, DQ2 =116, DQ3 =132
8718 13:53:58.659545 DQ4 =126, DQ5 =140, DQ6 =144, DQ7 =126
8719 13:53:58.663203 DQ8 =114, DQ9 =118, DQ10 =132, DQ11 =122
8720 13:53:58.666124 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8721 13:53:58.666221
8722 13:53:58.666310
8723 13:53:58.666399
8724 13:53:58.670150 [DramC_TX_OE_Calibration] TA2
8725 13:53:58.673187 Original DQ_B0 (3 6) =30, OEN = 27
8726 13:53:58.676572 Original DQ_B1 (3 6) =30, OEN = 27
8727 13:53:58.679583 24, 0x0, End_B0=24 End_B1=24
8728 13:53:58.682879 25, 0x0, End_B0=25 End_B1=25
8729 13:53:58.682981 26, 0x0, End_B0=26 End_B1=26
8730 13:53:58.686059 27, 0x0, End_B0=27 End_B1=27
8731 13:53:58.689532 28, 0x0, End_B0=28 End_B1=28
8732 13:53:58.692601 29, 0x0, End_B0=29 End_B1=29
8733 13:53:58.692709 30, 0x0, End_B0=30 End_B1=30
8734 13:53:58.696091 31, 0x4141, End_B0=30 End_B1=30
8735 13:53:58.698971 Byte0 end_step=30 best_step=27
8736 13:53:58.702450 Byte1 end_step=30 best_step=27
8737 13:53:58.705688 Byte0 TX OE(2T, 0.5T) = (3, 3)
8738 13:53:58.708779 Byte1 TX OE(2T, 0.5T) = (3, 3)
8739 13:53:58.708875
8740 13:53:58.708966
8741 13:53:58.715628 [DQSOSCAuto] RK0, (LSB)MR18= 0xa14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8742 13:53:58.718630 CH1 RK0: MR19=303, MR18=A14
8743 13:53:58.725411 CH1_RK0: MR19=0x303, MR18=0xA14, DQSOSC=399, MR23=63, INC=23, DEC=15
8744 13:53:58.725516
8745 13:53:58.728910 ----->DramcWriteLeveling(PI) begin...
8746 13:53:58.728986 ==
8747 13:53:58.732026 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 13:53:58.735254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 13:53:58.735380 ==
8750 13:53:58.738529 Write leveling (Byte 0): 24 => 24
8751 13:53:58.741942 Write leveling (Byte 1): 24 => 24
8752 13:53:58.745358 DramcWriteLeveling(PI) end<-----
8753 13:53:58.745463
8754 13:53:58.745555 ==
8755 13:53:58.748543 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 13:53:58.751765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 13:53:58.755032 ==
8758 13:53:58.755134 [Gating] SW mode calibration
8759 13:53:58.765106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8760 13:53:58.768247 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8761 13:53:58.771489 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 13:53:58.778416 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 13:53:58.781375 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8764 13:53:58.784922 1 4 12 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
8765 13:53:58.791683 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 13:53:58.794531 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 13:53:58.798082 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 13:53:58.804475 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 13:53:58.807902 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 13:53:58.810923 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8771 13:53:58.817703 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8772 13:53:58.820969 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8773 13:53:58.824351 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8774 13:53:58.830533 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 13:53:58.834122 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 13:53:58.840567 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 13:53:58.843857 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 13:53:58.847301 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8779 13:53:58.853642 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8780 13:53:58.857245 1 6 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8781 13:53:58.860239 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 13:53:58.866949 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 13:53:58.869995 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 13:53:58.873465 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 13:53:58.876650 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 13:53:58.883239 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8787 13:53:58.887219 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8788 13:53:58.890352 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8789 13:53:58.896409 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8790 13:53:58.900080 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 13:53:58.906190 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 13:53:58.909701 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 13:53:58.912628 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 13:53:58.919542 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 13:53:58.922522 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 13:53:58.926178 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 13:53:58.932863 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 13:53:58.935741 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 13:53:58.938784 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 13:53:58.945616 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 13:53:58.948805 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 13:53:58.952087 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8803 13:53:58.959037 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8804 13:53:58.962102 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8805 13:53:58.965123 Total UI for P1: 0, mck2ui 16
8806 13:53:58.968525 best dqsien dly found for B0: ( 1, 9, 6)
8807 13:53:58.971640 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 13:53:58.974942 Total UI for P1: 0, mck2ui 16
8809 13:53:58.978847 best dqsien dly found for B1: ( 1, 9, 12)
8810 13:53:58.981965 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8811 13:53:58.985310 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8812 13:53:58.985409
8813 13:53:58.991622 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8814 13:53:58.995486 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8815 13:53:58.998267 [Gating] SW calibration Done
8816 13:53:58.998368 ==
8817 13:53:59.001696 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 13:53:59.005158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 13:53:59.005268 ==
8820 13:53:59.005360 RX Vref Scan: 0
8821 13:53:59.005450
8822 13:53:59.008553 RX Vref 0 -> 0, step: 1
8823 13:53:59.008651
8824 13:53:59.011306 RX Delay 0 -> 252, step: 8
8825 13:53:59.014535 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8826 13:53:59.017789 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8827 13:53:59.024588 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8828 13:53:59.028095 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8829 13:53:59.030960 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8830 13:53:59.034776 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8831 13:53:59.037692 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8832 13:53:59.043981 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8833 13:53:59.047605 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8834 13:53:59.050794 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8835 13:53:59.053937 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8836 13:53:59.057160 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8837 13:53:59.063719 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8838 13:53:59.066909 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8839 13:53:59.070488 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8840 13:53:59.073902 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8841 13:53:59.074005 ==
8842 13:53:59.076901 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 13:53:59.083616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 13:53:59.083699 ==
8845 13:53:59.083766 DQS Delay:
8846 13:53:59.086668 DQS0 = 0, DQS1 = 0
8847 13:53:59.086739 DQM Delay:
8848 13:53:59.090198 DQM0 = 137, DQM1 = 130
8849 13:53:59.090299 DQ Delay:
8850 13:53:59.093571 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =135
8851 13:53:59.096695 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8852 13:53:59.100413 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8853 13:53:59.103696 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8854 13:53:59.103788
8855 13:53:59.103853
8856 13:53:59.103913 ==
8857 13:53:59.107425 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 13:53:59.113475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 13:53:59.113576 ==
8860 13:53:59.113674
8861 13:53:59.113766
8862 13:53:59.113840 TX Vref Scan disable
8863 13:53:59.116951 == TX Byte 0 ==
8864 13:53:59.120217 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8865 13:53:59.126799 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8866 13:53:59.126938 == TX Byte 1 ==
8867 13:53:59.129927 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8868 13:53:59.136601 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8869 13:53:59.136679 ==
8870 13:53:59.139743 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 13:53:59.143145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 13:53:59.143240 ==
8873 13:53:59.156318
8874 13:53:59.160021 TX Vref early break, caculate TX vref
8875 13:53:59.162951 TX Vref=16, minBit 1, minWin=23, winSum=382
8876 13:53:59.166374 TX Vref=18, minBit 5, minWin=23, winSum=386
8877 13:53:59.169738 TX Vref=20, minBit 9, minWin=22, winSum=396
8878 13:53:59.173152 TX Vref=22, minBit 8, minWin=24, winSum=403
8879 13:53:59.179303 TX Vref=24, minBit 9, minWin=24, winSum=412
8880 13:53:59.183021 TX Vref=26, minBit 1, minWin=25, winSum=415
8881 13:53:59.186110 TX Vref=28, minBit 9, minWin=24, winSum=423
8882 13:53:59.189451 TX Vref=30, minBit 9, minWin=25, winSum=423
8883 13:53:59.193041 TX Vref=32, minBit 1, minWin=25, winSum=413
8884 13:53:59.196499 TX Vref=34, minBit 0, minWin=24, winSum=403
8885 13:53:59.202482 TX Vref=36, minBit 0, minWin=24, winSum=396
8886 13:53:59.206069 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 30
8887 13:53:59.206151
8888 13:53:59.209117 Final TX Range 0 Vref 30
8889 13:53:59.209199
8890 13:53:59.209263 ==
8891 13:53:59.212467 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 13:53:59.216222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 13:53:59.219198 ==
8894 13:53:59.219279
8895 13:53:59.219347
8896 13:53:59.219417 TX Vref Scan disable
8897 13:53:59.226247 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8898 13:53:59.226329 == TX Byte 0 ==
8899 13:53:59.229288 u2DelayCellOfst[0]=14 cells (4 PI)
8900 13:53:59.232360 u2DelayCellOfst[1]=10 cells (3 PI)
8901 13:53:59.235969 u2DelayCellOfst[2]=0 cells (0 PI)
8902 13:53:59.239062 u2DelayCellOfst[3]=7 cells (2 PI)
8903 13:53:59.242458 u2DelayCellOfst[4]=7 cells (2 PI)
8904 13:53:59.245664 u2DelayCellOfst[5]=14 cells (4 PI)
8905 13:53:59.249013 u2DelayCellOfst[6]=17 cells (5 PI)
8906 13:53:59.252209 u2DelayCellOfst[7]=7 cells (2 PI)
8907 13:53:59.255866 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8908 13:53:59.258573 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8909 13:53:59.261864 == TX Byte 1 ==
8910 13:53:59.265717 u2DelayCellOfst[8]=0 cells (0 PI)
8911 13:53:59.268491 u2DelayCellOfst[9]=3 cells (1 PI)
8912 13:53:59.271837 u2DelayCellOfst[10]=14 cells (4 PI)
8913 13:53:59.275163 u2DelayCellOfst[11]=7 cells (2 PI)
8914 13:53:59.278630 u2DelayCellOfst[12]=17 cells (5 PI)
8915 13:53:59.281750 u2DelayCellOfst[13]=17 cells (5 PI)
8916 13:53:59.284914 u2DelayCellOfst[14]=21 cells (6 PI)
8917 13:53:59.285016 u2DelayCellOfst[15]=21 cells (6 PI)
8918 13:53:59.292120 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8919 13:53:59.295085 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8920 13:53:59.298132 DramC Write-DBI on
8921 13:53:59.298229 ==
8922 13:53:59.301389 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 13:53:59.304739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 13:53:59.304811 ==
8925 13:53:59.304872
8926 13:53:59.304930
8927 13:53:59.307997 TX Vref Scan disable
8928 13:53:59.308092 == TX Byte 0 ==
8929 13:53:59.315049 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8930 13:53:59.315166 == TX Byte 1 ==
8931 13:53:59.318097 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8932 13:53:59.321674 DramC Write-DBI off
8933 13:53:59.321745
8934 13:53:59.321808 [DATLAT]
8935 13:53:59.325155 Freq=1600, CH1 RK1
8936 13:53:59.325252
8937 13:53:59.325339 DATLAT Default: 0xf
8938 13:53:59.327939 0, 0xFFFF, sum = 0
8939 13:53:59.330987 1, 0xFFFF, sum = 0
8940 13:53:59.331058 2, 0xFFFF, sum = 0
8941 13:53:59.334674 3, 0xFFFF, sum = 0
8942 13:53:59.334746 4, 0xFFFF, sum = 0
8943 13:53:59.337528 5, 0xFFFF, sum = 0
8944 13:53:59.337598 6, 0xFFFF, sum = 0
8945 13:53:59.340864 7, 0xFFFF, sum = 0
8946 13:53:59.340961 8, 0xFFFF, sum = 0
8947 13:53:59.343925 9, 0xFFFF, sum = 0
8948 13:53:59.343997 10, 0xFFFF, sum = 0
8949 13:53:59.347561 11, 0xFFFF, sum = 0
8950 13:53:59.347630 12, 0xFFFF, sum = 0
8951 13:53:59.350951 13, 0xFFFF, sum = 0
8952 13:53:59.351022 14, 0x0, sum = 1
8953 13:53:59.353899 15, 0x0, sum = 2
8954 13:53:59.353971 16, 0x0, sum = 3
8955 13:53:59.357476 17, 0x0, sum = 4
8956 13:53:59.357573 best_step = 15
8957 13:53:59.357660
8958 13:53:59.357744 ==
8959 13:53:59.360789 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 13:53:59.367190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 13:53:59.367278 ==
8962 13:53:59.367394 RX Vref Scan: 0
8963 13:53:59.367497
8964 13:53:59.370464 RX Vref 0 -> 0, step: 1
8965 13:53:59.370536
8966 13:53:59.373721 RX Delay 11 -> 252, step: 4
8967 13:53:59.377227 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8968 13:53:59.380220 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8969 13:53:59.386732 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8970 13:53:59.390168 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8971 13:53:59.393458 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8972 13:53:59.396717 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8973 13:53:59.399903 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8974 13:53:59.406328 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8975 13:53:59.410402 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8976 13:53:59.413457 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8977 13:53:59.416387 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8978 13:53:59.420163 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8979 13:53:59.426332 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8980 13:53:59.429763 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8981 13:53:59.433216 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8982 13:53:59.436162 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8983 13:53:59.436262 ==
8984 13:53:59.439560 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 13:53:59.446057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 13:53:59.446130 ==
8987 13:53:59.446192 DQS Delay:
8988 13:53:59.449157 DQS0 = 0, DQS1 = 0
8989 13:53:59.449226 DQM Delay:
8990 13:53:59.452708 DQM0 = 133, DQM1 = 127
8991 13:53:59.452794 DQ Delay:
8992 13:53:59.456418 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8993 13:53:59.459421 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8994 13:53:59.463596 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8995 13:53:59.465899 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =136
8996 13:53:59.465982
8997 13:53:59.466067
8998 13:53:59.466148
8999 13:53:59.469035 [DramC_TX_OE_Calibration] TA2
9000 13:53:59.472332 Original DQ_B0 (3 6) =30, OEN = 27
9001 13:53:59.475982 Original DQ_B1 (3 6) =30, OEN = 27
9002 13:53:59.479543 24, 0x0, End_B0=24 End_B1=24
9003 13:53:59.482379 25, 0x0, End_B0=25 End_B1=25
9004 13:53:59.482463 26, 0x0, End_B0=26 End_B1=26
9005 13:53:59.485639 27, 0x0, End_B0=27 End_B1=27
9006 13:53:59.488917 28, 0x0, End_B0=28 End_B1=28
9007 13:53:59.492304 29, 0x0, End_B0=29 End_B1=29
9008 13:53:59.495588 30, 0x0, End_B0=30 End_B1=30
9009 13:53:59.495674 31, 0x5151, End_B0=30 End_B1=30
9010 13:53:59.499010 Byte0 end_step=30 best_step=27
9011 13:53:59.502173 Byte1 end_step=30 best_step=27
9012 13:53:59.505634 Byte0 TX OE(2T, 0.5T) = (3, 3)
9013 13:53:59.508658 Byte1 TX OE(2T, 0.5T) = (3, 3)
9014 13:53:59.508741
9015 13:53:59.508826
9016 13:53:59.515490 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9017 13:53:59.519131 CH1 RK1: MR19=303, MR18=101E
9018 13:53:59.525380 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
9019 13:53:59.528467 [RxdqsGatingPostProcess] freq 1600
9020 13:53:59.535162 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9021 13:53:59.538113 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 13:53:59.538185 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 13:53:59.541739 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 13:53:59.544993 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 13:53:59.548067 best DQS0 dly(2T, 0.5T) = (1, 1)
9026 13:53:59.551425 best DQS1 dly(2T, 0.5T) = (1, 1)
9027 13:53:59.555128 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9028 13:53:59.558033 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9029 13:53:59.561499 Pre-setting of DQS Precalculation
9030 13:53:59.567961 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9031 13:53:59.574692 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9032 13:53:59.580888 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9033 13:53:59.580967
9034 13:53:59.581029
9035 13:53:59.584235 [Calibration Summary] 3200 Mbps
9036 13:53:59.584312 CH 0, Rank 0
9037 13:53:59.587966 SW Impedance : PASS
9038 13:53:59.591090 DUTY Scan : NO K
9039 13:53:59.591170 ZQ Calibration : PASS
9040 13:53:59.594180 Jitter Meter : NO K
9041 13:53:59.597706 CBT Training : PASS
9042 13:53:59.597786 Write leveling : PASS
9043 13:53:59.601360 RX DQS gating : PASS
9044 13:53:59.604228 RX DQ/DQS(RDDQC) : PASS
9045 13:53:59.604309 TX DQ/DQS : PASS
9046 13:53:59.607636 RX DATLAT : PASS
9047 13:53:59.607715 RX DQ/DQS(Engine): PASS
9048 13:53:59.610971 TX OE : PASS
9049 13:53:59.611051 All Pass.
9050 13:53:59.611114
9051 13:53:59.614571 CH 0, Rank 1
9052 13:53:59.614651 SW Impedance : PASS
9053 13:53:59.617487 DUTY Scan : NO K
9054 13:53:59.621162 ZQ Calibration : PASS
9055 13:53:59.621242 Jitter Meter : NO K
9056 13:53:59.624351 CBT Training : PASS
9057 13:53:59.627530 Write leveling : PASS
9058 13:53:59.627611 RX DQS gating : PASS
9059 13:53:59.630695 RX DQ/DQS(RDDQC) : PASS
9060 13:53:59.634341 TX DQ/DQS : PASS
9061 13:53:59.634421 RX DATLAT : PASS
9062 13:53:59.637415 RX DQ/DQS(Engine): PASS
9063 13:53:59.640731 TX OE : PASS
9064 13:53:59.640811 All Pass.
9065 13:53:59.640880
9066 13:53:59.640947 CH 1, Rank 0
9067 13:53:59.644189 SW Impedance : PASS
9068 13:53:59.647159 DUTY Scan : NO K
9069 13:53:59.647272 ZQ Calibration : PASS
9070 13:53:59.650492 Jitter Meter : NO K
9071 13:53:59.653654 CBT Training : PASS
9072 13:53:59.653791 Write leveling : PASS
9073 13:53:59.657085 RX DQS gating : PASS
9074 13:53:59.660405 RX DQ/DQS(RDDQC) : PASS
9075 13:53:59.660501 TX DQ/DQS : PASS
9076 13:53:59.664056 RX DATLAT : PASS
9077 13:53:59.667102 RX DQ/DQS(Engine): PASS
9078 13:53:59.667196 TX OE : PASS
9079 13:53:59.670043 All Pass.
9080 13:53:59.670144
9081 13:53:59.670210 CH 1, Rank 1
9082 13:53:59.673745 SW Impedance : PASS
9083 13:53:59.673839 DUTY Scan : NO K
9084 13:53:59.676355 ZQ Calibration : PASS
9085 13:53:59.679653 Jitter Meter : NO K
9086 13:53:59.679733 CBT Training : PASS
9087 13:53:59.683181 Write leveling : PASS
9088 13:53:59.686485 RX DQS gating : PASS
9089 13:53:59.686571 RX DQ/DQS(RDDQC) : PASS
9090 13:53:59.689910 TX DQ/DQS : PASS
9091 13:53:59.693017 RX DATLAT : PASS
9092 13:53:59.693097 RX DQ/DQS(Engine): PASS
9093 13:53:59.696166 TX OE : PASS
9094 13:53:59.696247 All Pass.
9095 13:53:59.696310
9096 13:53:59.699790 DramC Write-DBI on
9097 13:53:59.702727 PER_BANK_REFRESH: Hybrid Mode
9098 13:53:59.702807 TX_TRACKING: ON
9099 13:53:59.713304 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9100 13:53:59.719204 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9101 13:53:59.725719 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 13:53:59.728939 [FAST_K] Save calibration result to emmc
9103 13:53:59.732344 sync common calibartion params.
9104 13:53:59.736486 sync cbt_mode0:1, 1:1
9105 13:53:59.739547 dram_init: ddr_geometry: 2
9106 13:53:59.739622 dram_init: ddr_geometry: 2
9107 13:53:59.742587 dram_init: ddr_geometry: 2
9108 13:53:59.746275 0:dram_rank_size:100000000
9109 13:53:59.748958 1:dram_rank_size:100000000
9110 13:53:59.752589 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9111 13:53:59.755604 DFS_SHUFFLE_HW_MODE: ON
9112 13:53:59.759051 dramc_set_vcore_voltage set vcore to 725000
9113 13:53:59.762141 Read voltage for 1600, 0
9114 13:53:59.762210 Vio18 = 0
9115 13:53:59.762269 Vcore = 725000
9116 13:53:59.765384 Vdram = 0
9117 13:53:59.765460 Vddq = 0
9118 13:53:59.765522 Vmddr = 0
9119 13:53:59.768749 switch to 3200 Mbps bootup
9120 13:53:59.772172 [DramcRunTimeConfig]
9121 13:53:59.772248 PHYPLL
9122 13:53:59.772310 DPM_CONTROL_AFTERK: ON
9123 13:53:59.775558 PER_BANK_REFRESH: ON
9124 13:53:59.779027 REFRESH_OVERHEAD_REDUCTION: ON
9125 13:53:59.779098 CMD_PICG_NEW_MODE: OFF
9126 13:53:59.782917 XRTWTW_NEW_MODE: ON
9127 13:53:59.785101 XRTRTR_NEW_MODE: ON
9128 13:53:59.785171 TX_TRACKING: ON
9129 13:53:59.789172 RDSEL_TRACKING: OFF
9130 13:53:59.789263 DQS Precalculation for DVFS: ON
9131 13:53:59.791814 RX_TRACKING: OFF
9132 13:53:59.791884 HW_GATING DBG: ON
9133 13:53:59.795323 ZQCS_ENABLE_LP4: ON
9134 13:53:59.798802 RX_PICG_NEW_MODE: ON
9135 13:53:59.798872 TX_PICG_NEW_MODE: ON
9136 13:53:59.802014 ENABLE_RX_DCM_DPHY: ON
9137 13:53:59.805295 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9138 13:53:59.805365 DUMMY_READ_FOR_TRACKING: OFF
9139 13:53:59.808368 !!! SPM_CONTROL_AFTERK: OFF
9140 13:53:59.811837 !!! SPM could not control APHY
9141 13:53:59.815231 IMPEDANCE_TRACKING: ON
9142 13:53:59.815341 TEMP_SENSOR: ON
9143 13:53:59.818624 HW_SAVE_FOR_SR: OFF
9144 13:53:59.821465 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9145 13:53:59.824774 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9146 13:53:59.824854 Read ODT Tracking: ON
9147 13:53:59.827888 Refresh Rate DeBounce: ON
9148 13:53:59.831239 DFS_NO_QUEUE_FLUSH: ON
9149 13:53:59.834314 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9150 13:53:59.834394 ENABLE_DFS_RUNTIME_MRW: OFF
9151 13:53:59.838176 DDR_RESERVE_NEW_MODE: ON
9152 13:53:59.841160 MR_CBT_SWITCH_FREQ: ON
9153 13:53:59.841241 =========================
9154 13:53:59.861442 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9155 13:53:59.864592 dram_init: ddr_geometry: 2
9156 13:53:59.883046 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9157 13:53:59.886196 dram_init: dram init end (result: 0)
9158 13:53:59.892420 DRAM-K: Full calibration passed in 24417 msecs
9159 13:53:59.895972 MRC: failed to locate region type 0.
9160 13:53:59.896053 DRAM rank0 size:0x100000000,
9161 13:53:59.899234 DRAM rank1 size=0x100000000
9162 13:53:59.909296 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9163 13:53:59.915775 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9164 13:53:59.922457 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9165 13:53:59.932451 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9166 13:53:59.932532 DRAM rank0 size:0x100000000,
9167 13:53:59.935352 DRAM rank1 size=0x100000000
9168 13:53:59.935463 CBMEM:
9169 13:53:59.939017 IMD: root @ 0xfffff000 254 entries.
9170 13:53:59.942609 IMD: root @ 0xffffec00 62 entries.
9171 13:53:59.945454 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9172 13:53:59.952110 WARNING: RO_VPD is uninitialized or empty.
9173 13:53:59.955242 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9174 13:53:59.962860 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9175 13:53:59.975596 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9176 13:53:59.987187 BS: romstage times (exec / console): total (unknown) / 23949 ms
9177 13:53:59.987270
9178 13:53:59.987334
9179 13:53:59.996806 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9180 13:54:00.000237 ARM64: Exception handlers installed.
9181 13:54:00.003508 ARM64: Testing exception
9182 13:54:00.006597 ARM64: Done test exception
9183 13:54:00.006677 Enumerating buses...
9184 13:54:00.010845 Show all devs... Before device enumeration.
9185 13:54:00.013125 Root Device: enabled 1
9186 13:54:00.017270 CPU_CLUSTER: 0: enabled 1
9187 13:54:00.017350 CPU: 00: enabled 1
9188 13:54:00.020113 Compare with tree...
9189 13:54:00.020193 Root Device: enabled 1
9190 13:54:00.023302 CPU_CLUSTER: 0: enabled 1
9191 13:54:00.026648 CPU: 00: enabled 1
9192 13:54:00.026727 Root Device scanning...
9193 13:54:00.029831 scan_static_bus for Root Device
9194 13:54:00.033126 CPU_CLUSTER: 0 enabled
9195 13:54:00.036370 scan_static_bus for Root Device done
9196 13:54:00.039757 scan_bus: bus Root Device finished in 8 msecs
9197 13:54:00.039837 done
9198 13:54:00.046272 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9199 13:54:00.049758 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9200 13:54:00.055912 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9201 13:54:00.062540 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9202 13:54:00.062647 Allocating resources...
9203 13:54:00.066008 Reading resources...
9204 13:54:00.069171 Root Device read_resources bus 0 link: 0
9205 13:54:00.072922 DRAM rank0 size:0x100000000,
9206 13:54:00.073003 DRAM rank1 size=0x100000000
9207 13:54:00.079453 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9208 13:54:00.079535 CPU: 00 missing read_resources
9209 13:54:00.085884 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9210 13:54:00.088709 Root Device read_resources bus 0 link: 0 done
9211 13:54:00.092063 Done reading resources.
9212 13:54:00.095614 Show resources in subtree (Root Device)...After reading.
9213 13:54:00.099179 Root Device child on link 0 CPU_CLUSTER: 0
9214 13:54:00.102056 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 13:54:00.112351 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 13:54:00.112433 CPU: 00
9217 13:54:00.118860 Root Device assign_resources, bus 0 link: 0
9218 13:54:00.122201 CPU_CLUSTER: 0 missing set_resources
9219 13:54:00.125043 Root Device assign_resources, bus 0 link: 0 done
9220 13:54:00.128625 Done setting resources.
9221 13:54:00.131599 Show resources in subtree (Root Device)...After assigning values.
9222 13:54:00.134993 Root Device child on link 0 CPU_CLUSTER: 0
9223 13:54:00.141693 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 13:54:00.148377 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 13:54:00.151876 CPU: 00
9226 13:54:00.151960 Done allocating resources.
9227 13:54:00.158049 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9228 13:54:00.158155 Enabling resources...
9229 13:54:00.161325 done.
9230 13:54:00.164528 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9231 13:54:00.167937 Initializing devices...
9232 13:54:00.168036 Root Device init
9233 13:54:00.171737 init hardware done!
9234 13:54:00.171820 0x00000018: ctrlr->caps
9235 13:54:00.174829 52.000 MHz: ctrlr->f_max
9236 13:54:00.177901 0.400 MHz: ctrlr->f_min
9237 13:54:00.181569 0x40ff8080: ctrlr->voltages
9238 13:54:00.181672 sclk: 390625
9239 13:54:00.181765 Bus Width = 1
9240 13:54:00.184413 sclk: 390625
9241 13:54:00.184496 Bus Width = 1
9242 13:54:00.187763 Early init status = 3
9243 13:54:00.191422 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9244 13:54:00.194241 in-header: 03 fc 00 00 01 00 00 00
9245 13:54:00.197599 in-data: 00
9246 13:54:00.201520 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9247 13:54:00.205666 in-header: 03 fd 00 00 00 00 00 00
9248 13:54:00.208671 in-data:
9249 13:54:00.212702 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9250 13:54:00.215837 in-header: 03 fc 00 00 01 00 00 00
9251 13:54:00.219264 in-data: 00
9252 13:54:00.222024 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9253 13:54:00.226714 in-header: 03 fd 00 00 00 00 00 00
9254 13:54:00.230374 in-data:
9255 13:54:00.233371 [SSUSB] Setting up USB HOST controller...
9256 13:54:00.237017 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9257 13:54:00.240338 [SSUSB] phy power-on done.
9258 13:54:00.243585 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9259 13:54:00.250020 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9260 13:54:00.253201 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9261 13:54:00.260156 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9262 13:54:00.266745 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9263 13:54:00.273351 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9264 13:54:00.279920 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9265 13:54:00.285927 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9266 13:54:00.289293 SPM: binary array size = 0x9dc
9267 13:54:00.293365 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9268 13:54:00.299787 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9269 13:54:00.305828 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9270 13:54:00.312690 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9271 13:54:00.316145 configure_display: Starting display init
9272 13:54:00.350335 anx7625_power_on_init: Init interface.
9273 13:54:00.353369 anx7625_disable_pd_protocol: Disabled PD feature.
9274 13:54:00.357602 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9275 13:54:00.384813 anx7625_start_dp_work: Secure OCM version=00
9276 13:54:00.387584 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9277 13:54:00.402806 sp_tx_get_edid_block: EDID Block = 1
9278 13:54:00.505335 Extracted contents:
9279 13:54:00.508772 header: 00 ff ff ff ff ff ff 00
9280 13:54:00.512330 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9281 13:54:00.515253 version: 01 04
9282 13:54:00.518224 basic params: 95 1f 11 78 0a
9283 13:54:00.521825 chroma info: 76 90 94 55 54 90 27 21 50 54
9284 13:54:00.524878 established: 00 00 00
9285 13:54:00.531662 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9286 13:54:00.535159 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9287 13:54:00.541340 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9288 13:54:00.547915 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9289 13:54:00.554756 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9290 13:54:00.558282 extensions: 00
9291 13:54:00.558360 checksum: fb
9292 13:54:00.558448
9293 13:54:00.561522 Manufacturer: IVO Model 57d Serial Number 0
9294 13:54:00.564441 Made week 0 of 2020
9295 13:54:00.568103 EDID version: 1.4
9296 13:54:00.568200 Digital display
9297 13:54:00.571122 6 bits per primary color channel
9298 13:54:00.571232 DisplayPort interface
9299 13:54:00.574596 Maximum image size: 31 cm x 17 cm
9300 13:54:00.577510 Gamma: 220%
9301 13:54:00.577586 Check DPMS levels
9302 13:54:00.584440 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9303 13:54:00.587520 First detailed timing is preferred timing
9304 13:54:00.590738 Established timings supported:
9305 13:54:00.590832 Standard timings supported:
9306 13:54:00.593712 Detailed timings
9307 13:54:00.597594 Hex of detail: 383680a07038204018303c0035ae10000019
9308 13:54:00.604340 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9309 13:54:00.607096 0780 0798 07c8 0820 hborder 0
9310 13:54:00.610771 0438 043b 0447 0458 vborder 0
9311 13:54:00.613942 -hsync -vsync
9312 13:54:00.614015 Did detailed timing
9313 13:54:00.620374 Hex of detail: 000000000000000000000000000000000000
9314 13:54:00.623936 Manufacturer-specified data, tag 0
9315 13:54:00.627192 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9316 13:54:00.630073 ASCII string: InfoVision
9317 13:54:00.633375 Hex of detail: 000000fe00523134304e574635205248200a
9318 13:54:00.637165 ASCII string: R140NWF5 RH
9319 13:54:00.637243 Checksum
9320 13:54:00.640409 Checksum: 0xfb (valid)
9321 13:54:00.643303 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9322 13:54:00.646707 DSI data_rate: 832800000 bps
9323 13:54:00.653166 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9324 13:54:00.656360 anx7625_parse_edid: pixelclock(138800).
9325 13:54:00.659830 hactive(1920), hsync(48), hfp(24), hbp(88)
9326 13:54:00.663123 vactive(1080), vsync(12), vfp(3), vbp(17)
9327 13:54:00.666058 anx7625_dsi_config: config dsi.
9328 13:54:00.673253 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9329 13:54:00.687139 anx7625_dsi_config: success to config DSI
9330 13:54:00.690812 anx7625_dp_start: MIPI phy setup OK.
9331 13:54:00.693885 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9332 13:54:00.697211 mtk_ddp_mode_set invalid vrefresh 60
9333 13:54:00.700237 main_disp_path_setup
9334 13:54:00.700320 ovl_layer_smi_id_en
9335 13:54:00.703914 ovl_layer_smi_id_en
9336 13:54:00.703994 ccorr_config
9337 13:54:00.704057 aal_config
9338 13:54:00.707314 gamma_config
9339 13:54:00.707414 postmask_config
9340 13:54:00.710397 dither_config
9341 13:54:00.713550 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9342 13:54:00.720084 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9343 13:54:00.723338 Root Device init finished in 551 msecs
9344 13:54:00.726939 CPU_CLUSTER: 0 init
9345 13:54:00.733420 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9346 13:54:00.740295 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9347 13:54:00.740374 APU_MBOX 0x190000b0 = 0x10001
9348 13:54:00.743610 APU_MBOX 0x190001b0 = 0x10001
9349 13:54:00.746444 APU_MBOX 0x190005b0 = 0x10001
9350 13:54:00.749640 APU_MBOX 0x190006b0 = 0x10001
9351 13:54:00.756144 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9352 13:54:00.766350 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9353 13:54:00.778752 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9354 13:54:00.785216 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9355 13:54:00.797133 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9356 13:54:00.805894 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9357 13:54:00.809181 CPU_CLUSTER: 0 init finished in 81 msecs
9358 13:54:00.812566 Devices initialized
9359 13:54:00.815891 Show all devs... After init.
9360 13:54:00.815973 Root Device: enabled 1
9361 13:54:00.819321 CPU_CLUSTER: 0: enabled 1
9362 13:54:00.822622 CPU: 00: enabled 1
9363 13:54:00.825515 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9364 13:54:00.829092 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9365 13:54:00.832367 ELOG: NV offset 0x57f000 size 0x1000
9366 13:54:00.839082 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9367 13:54:00.846203 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9368 13:54:00.848880 ELOG: Event(17) added with size 13 at 2024-02-01 13:54:02 UTC
9369 13:54:00.855372 out: cmd=0x121: 03 db 21 01 00 00 00 00
9370 13:54:00.859132 in-header: 03 3a 00 00 2c 00 00 00
9371 13:54:00.868648 in-data: 25 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9372 13:54:00.875448 ELOG: Event(A1) added with size 10 at 2024-02-01 13:54:02 UTC
9373 13:54:00.881875 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9374 13:54:00.888811 ELOG: Event(A0) added with size 9 at 2024-02-01 13:54:02 UTC
9375 13:54:00.891784 elog_add_boot_reason: Logged dev mode boot
9376 13:54:00.898295 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9377 13:54:00.898375 Finalize devices...
9378 13:54:00.901650 Devices finalized
9379 13:54:00.905121 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9380 13:54:00.908742 Writing coreboot table at 0xffe64000
9381 13:54:00.911336 0. 000000000010a000-0000000000113fff: RAMSTAGE
9382 13:54:00.918009 1. 0000000040000000-00000000400fffff: RAM
9383 13:54:00.921365 2. 0000000040100000-000000004032afff: RAMSTAGE
9384 13:54:00.924814 3. 000000004032b000-00000000545fffff: RAM
9385 13:54:00.928596 4. 0000000054600000-000000005465ffff: BL31
9386 13:54:00.931635 5. 0000000054660000-00000000ffe63fff: RAM
9387 13:54:00.938158 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9388 13:54:00.941286 7. 0000000100000000-000000023fffffff: RAM
9389 13:54:00.944566 Passing 5 GPIOs to payload:
9390 13:54:00.948328 NAME | PORT | POLARITY | VALUE
9391 13:54:00.954132 EC in RW | 0x000000aa | low | undefined
9392 13:54:00.958020 EC interrupt | 0x00000005 | low | undefined
9393 13:54:00.964403 TPM interrupt | 0x000000ab | high | undefined
9394 13:54:00.967579 SD card detect | 0x00000011 | high | undefined
9395 13:54:00.970700 speaker enable | 0x00000093 | high | undefined
9396 13:54:00.973780 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9397 13:54:00.978109 in-header: 03 f9 00 00 02 00 00 00
9398 13:54:00.980927 in-data: 02 00
9399 13:54:00.984419 ADC[4]: Raw value=903694 ID=7
9400 13:54:00.988037 ADC[3]: Raw value=213546 ID=1
9401 13:54:00.988117 RAM Code: 0x71
9402 13:54:00.991088 ADC[6]: Raw value=74630 ID=0
9403 13:54:00.994330 ADC[5]: Raw value=213916 ID=1
9404 13:54:00.994411 SKU Code: 0x1
9405 13:54:01.001551 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 98c0
9406 13:54:01.001631 coreboot table: 964 bytes.
9407 13:54:01.004017 IMD ROOT 0. 0xfffff000 0x00001000
9408 13:54:01.007649 IMD SMALL 1. 0xffffe000 0x00001000
9409 13:54:01.010756 RO MCACHE 2. 0xffffc000 0x00001104
9410 13:54:01.013852 CONSOLE 3. 0xfff7c000 0x00080000
9411 13:54:01.017439 FMAP 4. 0xfff7b000 0x00000452
9412 13:54:01.020580 TIME STAMP 5. 0xfff7a000 0x00000910
9413 13:54:01.024158 VBOOT WORK 6. 0xfff66000 0x00014000
9414 13:54:01.027661 RAMOOPS 7. 0xffe66000 0x00100000
9415 13:54:01.030402 COREBOOT 8. 0xffe64000 0x00002000
9416 13:54:01.033615 IMD small region:
9417 13:54:01.037146 IMD ROOT 0. 0xffffec00 0x00000400
9418 13:54:01.040470 VPD 1. 0xffffeb80 0x0000006c
9419 13:54:01.043596 MMC STATUS 2. 0xffffeb60 0x00000004
9420 13:54:01.050031 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9421 13:54:01.050112 Probing TPM: done!
9422 13:54:01.057266 Connected to device vid:did:rid of 1ae0:0028:00
9423 13:54:01.063549 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9424 13:54:01.067213 Initialized TPM device CR50 revision 0
9425 13:54:01.070779 Checking cr50 for pending updates
9426 13:54:01.075970 Reading cr50 TPM mode
9427 13:54:01.084406 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9428 13:54:01.090647 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9429 13:54:01.131583 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9430 13:54:01.134150 Checking segment from ROM address 0x40100000
9431 13:54:01.137924 Checking segment from ROM address 0x4010001c
9432 13:54:01.144255 Loading segment from ROM address 0x40100000
9433 13:54:01.144336 code (compression=0)
9434 13:54:01.154720 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9435 13:54:01.160847 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9436 13:54:01.160928 it's not compressed!
9437 13:54:01.167224 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9438 13:54:01.174016 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9439 13:54:01.191849 Loading segment from ROM address 0x4010001c
9440 13:54:01.191940 Entry Point 0x80000000
9441 13:54:01.195151 Loaded segments
9442 13:54:01.198508 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9443 13:54:01.204488 Jumping to boot code at 0x80000000(0xffe64000)
9444 13:54:01.211845 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9445 13:54:01.217821 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9446 13:54:01.225740 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9447 13:54:01.229277 Checking segment from ROM address 0x40100000
9448 13:54:01.232639 Checking segment from ROM address 0x4010001c
9449 13:54:01.239209 Loading segment from ROM address 0x40100000
9450 13:54:01.239290 code (compression=1)
9451 13:54:01.245892 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9452 13:54:01.255689 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9453 13:54:01.255771 using LZMA
9454 13:54:01.264650 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9455 13:54:01.270951 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9456 13:54:01.274190 Loading segment from ROM address 0x4010001c
9457 13:54:01.274271 Entry Point 0x54601000
9458 13:54:01.277344 Loaded segments
9459 13:54:01.280692 NOTICE: MT8192 bl31_setup
9460 13:54:01.287684 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9461 13:54:01.291223 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9462 13:54:01.294404 WARNING: region 0:
9463 13:54:01.297807 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 13:54:01.297888 WARNING: region 1:
9465 13:54:01.304522 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9466 13:54:01.308170 WARNING: region 2:
9467 13:54:01.310953 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9468 13:54:01.314411 WARNING: region 3:
9469 13:54:01.318298 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 13:54:01.321065 WARNING: region 4:
9471 13:54:01.327731 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9472 13:54:01.327812 WARNING: region 5:
9473 13:54:01.331279 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 13:54:01.335828 WARNING: region 6:
9475 13:54:01.338031 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 13:54:01.340937 WARNING: region 7:
9477 13:54:01.344947 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 13:54:01.351294 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9479 13:54:01.354575 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9480 13:54:01.358237 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9481 13:54:01.364536 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9482 13:54:01.367717 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9483 13:54:01.371311 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9484 13:54:01.377803 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9485 13:54:01.380950 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9486 13:54:01.388112 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9487 13:54:01.391349 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9488 13:54:01.394253 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9489 13:54:01.401015 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9490 13:54:01.404210 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9491 13:54:01.408130 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9492 13:54:01.414509 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9493 13:54:01.417874 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9494 13:54:01.424570 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9495 13:54:01.427621 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9496 13:54:01.430959 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9497 13:54:01.437395 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9498 13:54:01.440740 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9499 13:54:01.444540 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9500 13:54:01.450794 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9501 13:54:01.454080 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9502 13:54:01.460736 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9503 13:54:01.463948 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9504 13:54:01.470605 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9505 13:54:01.474131 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9506 13:54:01.477506 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9507 13:54:01.484155 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9508 13:54:01.487384 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9509 13:54:01.493517 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9510 13:54:01.497128 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9511 13:54:01.500334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9512 13:54:01.503674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9513 13:54:01.510399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9514 13:54:01.513506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9515 13:54:01.517428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9516 13:54:01.520299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9517 13:54:01.526869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9518 13:54:01.530058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9519 13:54:01.533607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9520 13:54:01.536758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9521 13:54:01.544192 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9522 13:54:01.546567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9523 13:54:01.550221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9524 13:54:01.553720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9525 13:54:01.560172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9526 13:54:01.563345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9527 13:54:01.566820 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9528 13:54:01.573622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9529 13:54:01.577038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9530 13:54:01.583248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9531 13:54:01.586527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9532 13:54:01.593291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9533 13:54:01.596454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9534 13:54:01.600320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9535 13:54:01.606557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9536 13:54:01.609691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9537 13:54:01.616454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9538 13:54:01.619979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9539 13:54:01.626652 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9540 13:54:01.629866 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9541 13:54:01.636832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9542 13:54:01.639702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9543 13:54:01.646905 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9544 13:54:01.650247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9545 13:54:01.652765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9546 13:54:01.659716 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9547 13:54:01.663252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9548 13:54:01.669372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9549 13:54:01.672774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9550 13:54:01.679380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9551 13:54:01.682887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9552 13:54:01.686352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9553 13:54:01.692812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9554 13:54:01.696224 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9555 13:54:01.702941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9556 13:54:01.706553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9557 13:54:01.713322 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9558 13:54:01.716818 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9559 13:54:01.719926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9560 13:54:01.726421 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9561 13:54:01.729593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9562 13:54:01.735828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9563 13:54:01.739245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9564 13:54:01.746146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9565 13:54:01.749401 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9566 13:54:01.752850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9567 13:54:01.759540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9568 13:54:01.763083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9569 13:54:01.769238 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9570 13:54:01.772760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9571 13:54:01.779379 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9572 13:54:01.782462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9573 13:54:01.789231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9574 13:54:01.792612 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9575 13:54:01.795443 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9576 13:54:01.798884 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9577 13:54:01.805650 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9578 13:54:01.808938 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9579 13:54:01.812110 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9580 13:54:01.819074 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9581 13:54:01.822224 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9582 13:54:01.829488 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9583 13:54:01.832017 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9584 13:54:01.835628 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9585 13:54:01.842644 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9586 13:54:01.845368 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9587 13:54:01.851948 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9588 13:54:01.855744 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9589 13:54:01.858849 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9590 13:54:01.865616 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9591 13:54:01.868678 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9592 13:54:01.875195 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9593 13:54:01.878849 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9594 13:54:01.882759 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9595 13:54:01.888892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9596 13:54:01.891903 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9597 13:54:01.895057 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9598 13:54:01.898977 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9599 13:54:01.905291 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9600 13:54:01.908369 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9601 13:54:01.911766 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9602 13:54:01.918206 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9603 13:54:01.921860 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9604 13:54:01.924712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9605 13:54:01.931763 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9606 13:54:01.935275 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9607 13:54:01.942000 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9608 13:54:01.944900 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9609 13:54:01.948613 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9610 13:54:01.955276 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9611 13:54:01.958256 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9612 13:54:01.961291 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9613 13:54:01.968196 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9614 13:54:01.971753 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9615 13:54:01.978223 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9616 13:54:01.981600 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9617 13:54:01.985179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9618 13:54:01.991464 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9619 13:54:01.995092 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9620 13:54:02.001913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9621 13:54:02.004599 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9622 13:54:02.008014 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9623 13:54:02.014398 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9624 13:54:02.018338 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9625 13:54:02.024727 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9626 13:54:02.027801 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9627 13:54:02.031467 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9628 13:54:02.037965 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9629 13:54:02.041565 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9630 13:54:02.044446 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9631 13:54:02.051139 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9632 13:54:02.054625 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9633 13:54:02.061156 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9634 13:54:02.064689 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9635 13:54:02.068072 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9636 13:54:02.074440 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9637 13:54:02.078221 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9638 13:54:02.084624 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9639 13:54:02.087579 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9640 13:54:02.091712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9641 13:54:02.097994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9642 13:54:02.100760 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9643 13:54:02.107353 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9644 13:54:02.110954 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9645 13:54:02.114336 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9646 13:54:02.120782 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9647 13:54:02.123812 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9648 13:54:02.130458 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9649 13:54:02.133645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9650 13:54:02.136899 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9651 13:54:02.143762 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9652 13:54:02.146726 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9653 13:54:02.154163 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9654 13:54:02.156926 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9655 13:54:02.160015 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9656 13:54:02.166853 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9657 13:54:02.170207 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9658 13:54:02.176722 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9659 13:54:02.179950 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9660 13:54:02.183208 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9661 13:54:02.189983 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9662 13:54:02.193407 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9663 13:54:02.199837 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9664 13:54:02.203155 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9665 13:54:02.206901 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9666 13:54:02.212771 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9667 13:54:02.216342 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9668 13:54:02.222881 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9669 13:54:02.226610 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9670 13:54:02.229652 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9671 13:54:02.236520 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9672 13:54:02.239575 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9673 13:54:02.246499 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9674 13:54:02.249327 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9675 13:54:02.256128 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9676 13:54:02.258966 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9677 13:54:02.262329 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9678 13:54:02.269673 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9679 13:54:02.272425 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9680 13:54:02.279054 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9681 13:54:02.282228 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9682 13:54:02.288766 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9683 13:54:02.292171 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9684 13:54:02.295616 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9685 13:54:02.301895 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9686 13:54:02.305739 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9687 13:54:02.312150 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9688 13:54:02.315495 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9689 13:54:02.321893 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9690 13:54:02.325184 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9691 13:54:02.328538 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9692 13:54:02.335188 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9693 13:54:02.338568 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9694 13:54:02.344986 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9695 13:54:02.348637 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9696 13:54:02.355586 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9697 13:54:02.358580 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9698 13:54:02.361649 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9699 13:54:02.367923 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9700 13:54:02.371356 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9701 13:54:02.377875 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9702 13:54:02.381586 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9703 13:54:02.387924 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9704 13:54:02.391612 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9705 13:54:02.394544 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9706 13:54:02.401615 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9707 13:54:02.404351 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9708 13:54:02.407498 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9709 13:54:02.410982 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9710 13:54:02.417682 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9711 13:54:02.420573 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9712 13:54:02.423935 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9713 13:54:02.430478 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9714 13:54:02.434008 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9715 13:54:02.440574 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9716 13:54:02.443937 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9717 13:54:02.447130 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9718 13:54:02.453771 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9719 13:54:02.457165 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9720 13:54:02.463295 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9721 13:54:02.466674 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9722 13:54:02.470389 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9723 13:54:02.476796 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9724 13:54:02.479998 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9725 13:54:02.483103 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9726 13:54:02.490151 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9727 13:54:02.493109 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9728 13:54:02.496275 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9729 13:54:02.502916 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9730 13:54:02.506036 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9731 13:54:02.512838 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9732 13:54:02.516344 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9733 13:54:02.519720 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9734 13:54:02.526173 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9735 13:54:02.529044 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9736 13:54:02.532806 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9737 13:54:02.539479 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9738 13:54:02.542808 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9739 13:54:02.549169 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9740 13:54:02.552802 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9741 13:54:02.555704 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9742 13:54:02.562317 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9743 13:54:02.565574 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9744 13:54:02.572007 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9745 13:54:02.575612 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9746 13:54:02.579031 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9747 13:54:02.582244 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9748 13:54:02.588481 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9749 13:54:02.591622 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9750 13:54:02.595552 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9751 13:54:02.598717 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9752 13:54:02.604957 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9753 13:54:02.608415 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9754 13:54:02.611724 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9755 13:54:02.614793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9756 13:54:02.621709 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9757 13:54:02.624639 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9758 13:54:02.628193 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9759 13:54:02.634333 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9760 13:54:02.638019 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9761 13:54:02.640955 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9762 13:54:02.648067 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9763 13:54:02.650980 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9764 13:54:02.657878 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9765 13:54:02.661167 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9766 13:54:02.667907 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9767 13:54:02.670571 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9768 13:54:02.674420 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9769 13:54:02.680953 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9770 13:54:02.684283 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9771 13:54:02.690830 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9772 13:54:02.694084 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9773 13:54:02.701462 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9774 13:54:02.703914 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9775 13:54:02.707230 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9776 13:54:02.713716 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9777 13:54:02.717255 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9778 13:54:02.723689 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9779 13:54:02.726921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9780 13:54:02.730700 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9781 13:54:02.736914 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9782 13:54:02.740408 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9783 13:54:02.746643 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9784 13:54:02.750173 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9785 13:54:02.753559 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9786 13:54:02.760633 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9787 13:54:02.763293 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9788 13:54:02.769931 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9789 13:54:02.773384 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9790 13:54:02.779751 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9791 13:54:02.783556 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9792 13:54:02.786837 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9793 13:54:02.793011 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9794 13:54:02.796232 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9795 13:54:02.803118 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9796 13:54:02.806560 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9797 13:54:02.809840 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9798 13:54:02.816605 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9799 13:54:02.819483 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9800 13:54:02.826521 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9801 13:54:02.829279 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9802 13:54:02.832946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9803 13:54:02.839664 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9804 13:54:02.843056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9805 13:54:02.849376 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9806 13:54:02.852582 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9807 13:54:02.859154 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9808 13:54:02.863011 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9809 13:54:02.865856 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9810 13:54:02.872357 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9811 13:54:02.875858 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9812 13:54:02.882183 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9813 13:54:02.885891 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9814 13:54:02.892207 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9815 13:54:02.895253 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9816 13:54:02.898678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9817 13:54:02.905182 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9818 13:54:02.908814 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9819 13:54:02.915318 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9820 13:54:02.918562 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9821 13:54:02.921789 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9822 13:54:02.928033 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9823 13:54:02.931486 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9824 13:54:02.937898 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9825 13:54:02.941212 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9826 13:54:02.947697 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9827 13:54:02.951024 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9828 13:54:02.954322 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9829 13:54:02.961018 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9830 13:54:02.964487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9831 13:54:02.971476 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9832 13:54:02.974579 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9833 13:54:02.977821 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9834 13:54:02.984150 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9835 13:54:02.987191 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9836 13:54:02.994294 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9837 13:54:02.997911 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9838 13:54:03.003832 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9839 13:54:03.007015 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9840 13:54:03.013667 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9841 13:54:03.017011 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9842 13:54:03.024320 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9843 13:54:03.026842 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9844 13:54:03.030382 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9845 13:54:03.037187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9846 13:54:03.040321 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9847 13:54:03.046967 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9848 13:54:03.049887 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9849 13:54:03.056691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9850 13:54:03.059842 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9851 13:54:03.066352 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9852 13:54:03.069824 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9853 13:54:03.073373 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9854 13:54:03.079821 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9855 13:54:03.082867 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9856 13:54:03.089259 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9857 13:54:03.092569 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9858 13:54:03.099508 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9859 13:54:03.102783 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9860 13:54:03.109476 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9861 13:54:03.112403 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9862 13:54:03.119032 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9863 13:54:03.122407 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9864 13:54:03.125537 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9865 13:54:03.132181 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9866 13:54:03.135474 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9867 13:54:03.142294 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9868 13:54:03.145582 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9869 13:54:03.151970 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9870 13:54:03.155606 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9871 13:54:03.158601 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9872 13:54:03.165289 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9873 13:54:03.168348 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9874 13:54:03.175206 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9875 13:54:03.178670 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9876 13:54:03.185405 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9877 13:54:03.188512 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9878 13:54:03.194758 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9879 13:54:03.198329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9880 13:54:03.201515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9881 13:54:03.208000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9882 13:54:03.211520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9883 13:54:03.218269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9884 13:54:03.221388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9885 13:54:03.227706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9886 13:54:03.231332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9887 13:54:03.237871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9888 13:54:03.240848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9889 13:54:03.247309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9890 13:54:03.250770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9891 13:54:03.257762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9892 13:54:03.260599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9893 13:54:03.267883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9894 13:54:03.270995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9895 13:54:03.277066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9896 13:54:03.280883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9897 13:54:03.287547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9898 13:54:03.290642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9899 13:54:03.297322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9900 13:54:03.300497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9901 13:54:03.306981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9902 13:54:03.310392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9903 13:54:03.316809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9904 13:54:03.320693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9905 13:54:03.326717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9906 13:54:03.329870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9907 13:54:03.336841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9908 13:54:03.340025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9909 13:54:03.346394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9910 13:54:03.349657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9911 13:54:03.356135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9912 13:54:03.359977 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9913 13:54:03.363125 INFO: [APUAPC] vio 0
9914 13:54:03.366513 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9915 13:54:03.372776 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9916 13:54:03.376058 INFO: [APUAPC] D0_APC_0: 0x400510
9917 13:54:03.376134 INFO: [APUAPC] D0_APC_1: 0x0
9918 13:54:03.379488 INFO: [APUAPC] D0_APC_2: 0x1540
9919 13:54:03.382587 INFO: [APUAPC] D0_APC_3: 0x0
9920 13:54:03.386210 INFO: [APUAPC] D1_APC_0: 0xffffffff
9921 13:54:03.389416 INFO: [APUAPC] D1_APC_1: 0xffffffff
9922 13:54:03.392989 INFO: [APUAPC] D1_APC_2: 0x3fffff
9923 13:54:03.396529 INFO: [APUAPC] D1_APC_3: 0x0
9924 13:54:03.399774 INFO: [APUAPC] D2_APC_0: 0xffffffff
9925 13:54:03.402990 INFO: [APUAPC] D2_APC_1: 0xffffffff
9926 13:54:03.406099 INFO: [APUAPC] D2_APC_2: 0x3fffff
9927 13:54:03.409500 INFO: [APUAPC] D2_APC_3: 0x0
9928 13:54:03.412927 INFO: [APUAPC] D3_APC_0: 0xffffffff
9929 13:54:03.415790 INFO: [APUAPC] D3_APC_1: 0xffffffff
9930 13:54:03.419413 INFO: [APUAPC] D3_APC_2: 0x3fffff
9931 13:54:03.422842 INFO: [APUAPC] D3_APC_3: 0x0
9932 13:54:03.426327 INFO: [APUAPC] D4_APC_0: 0xffffffff
9933 13:54:03.429509 INFO: [APUAPC] D4_APC_1: 0xffffffff
9934 13:54:03.432968 INFO: [APUAPC] D4_APC_2: 0x3fffff
9935 13:54:03.435817 INFO: [APUAPC] D4_APC_3: 0x0
9936 13:54:03.439516 INFO: [APUAPC] D5_APC_0: 0xffffffff
9937 13:54:03.442643 INFO: [APUAPC] D5_APC_1: 0xffffffff
9938 13:54:03.445797 INFO: [APUAPC] D5_APC_2: 0x3fffff
9939 13:54:03.449339 INFO: [APUAPC] D5_APC_3: 0x0
9940 13:54:03.452673 INFO: [APUAPC] D6_APC_0: 0xffffffff
9941 13:54:03.456018 INFO: [APUAPC] D6_APC_1: 0xffffffff
9942 13:54:03.459041 INFO: [APUAPC] D6_APC_2: 0x3fffff
9943 13:54:03.462485 INFO: [APUAPC] D6_APC_3: 0x0
9944 13:54:03.466309 INFO: [APUAPC] D7_APC_0: 0xffffffff
9945 13:54:03.469429 INFO: [APUAPC] D7_APC_1: 0xffffffff
9946 13:54:03.472073 INFO: [APUAPC] D7_APC_2: 0x3fffff
9947 13:54:03.475415 INFO: [APUAPC] D7_APC_3: 0x0
9948 13:54:03.479051 INFO: [APUAPC] D8_APC_0: 0xffffffff
9949 13:54:03.482459 INFO: [APUAPC] D8_APC_1: 0xffffffff
9950 13:54:03.485378 INFO: [APUAPC] D8_APC_2: 0x3fffff
9951 13:54:03.488620 INFO: [APUAPC] D8_APC_3: 0x0
9952 13:54:03.492046 INFO: [APUAPC] D9_APC_0: 0xffffffff
9953 13:54:03.495577 INFO: [APUAPC] D9_APC_1: 0xffffffff
9954 13:54:03.498468 INFO: [APUAPC] D9_APC_2: 0x3fffff
9955 13:54:03.501741 INFO: [APUAPC] D9_APC_3: 0x0
9956 13:54:03.505387 INFO: [APUAPC] D10_APC_0: 0xffffffff
9957 13:54:03.508738 INFO: [APUAPC] D10_APC_1: 0xffffffff
9958 13:54:03.511785 INFO: [APUAPC] D10_APC_2: 0x3fffff
9959 13:54:03.515246 INFO: [APUAPC] D10_APC_3: 0x0
9960 13:54:03.518949 INFO: [APUAPC] D11_APC_0: 0xffffffff
9961 13:54:03.521757 INFO: [APUAPC] D11_APC_1: 0xffffffff
9962 13:54:03.525129 INFO: [APUAPC] D11_APC_2: 0x3fffff
9963 13:54:03.528464 INFO: [APUAPC] D11_APC_3: 0x0
9964 13:54:03.531511 INFO: [APUAPC] D12_APC_0: 0xffffffff
9965 13:54:03.534751 INFO: [APUAPC] D12_APC_1: 0xffffffff
9966 13:54:03.538232 INFO: [APUAPC] D12_APC_2: 0x3fffff
9967 13:54:03.541536 INFO: [APUAPC] D12_APC_3: 0x0
9968 13:54:03.544877 INFO: [APUAPC] D13_APC_0: 0xffffffff
9969 13:54:03.547933 INFO: [APUAPC] D13_APC_1: 0xffffffff
9970 13:54:03.551413 INFO: [APUAPC] D13_APC_2: 0x3fffff
9971 13:54:03.554573 INFO: [APUAPC] D13_APC_3: 0x0
9972 13:54:03.558394 INFO: [APUAPC] D14_APC_0: 0xffffffff
9973 13:54:03.561208 INFO: [APUAPC] D14_APC_1: 0xffffffff
9974 13:54:03.564521 INFO: [APUAPC] D14_APC_2: 0x3fffff
9975 13:54:03.567826 INFO: [APUAPC] D14_APC_3: 0x0
9976 13:54:03.571165 INFO: [APUAPC] D15_APC_0: 0xffffffff
9977 13:54:03.574183 INFO: [APUAPC] D15_APC_1: 0xffffffff
9978 13:54:03.577849 INFO: [APUAPC] D15_APC_2: 0x3fffff
9979 13:54:03.581254 INFO: [APUAPC] D15_APC_3: 0x0
9980 13:54:03.584344 INFO: [APUAPC] APC_CON: 0x4
9981 13:54:03.587731 INFO: [NOCDAPC] D0_APC_0: 0x0
9982 13:54:03.590646 INFO: [NOCDAPC] D0_APC_1: 0x0
9983 13:54:03.590725 INFO: [NOCDAPC] D1_APC_0: 0x0
9984 13:54:03.594126 INFO: [NOCDAPC] D1_APC_1: 0xfff
9985 13:54:03.597673 INFO: [NOCDAPC] D2_APC_0: 0x0
9986 13:54:03.600925 INFO: [NOCDAPC] D2_APC_1: 0xfff
9987 13:54:03.604264 INFO: [NOCDAPC] D3_APC_0: 0x0
9988 13:54:03.607189 INFO: [NOCDAPC] D3_APC_1: 0xfff
9989 13:54:03.610816 INFO: [NOCDAPC] D4_APC_0: 0x0
9990 13:54:03.614310 INFO: [NOCDAPC] D4_APC_1: 0xfff
9991 13:54:03.617324 INFO: [NOCDAPC] D5_APC_0: 0x0
9992 13:54:03.620463 INFO: [NOCDAPC] D5_APC_1: 0xfff
9993 13:54:03.623577 INFO: [NOCDAPC] D6_APC_0: 0x0
9994 13:54:03.627064 INFO: [NOCDAPC] D6_APC_1: 0xfff
9995 13:54:03.627146 INFO: [NOCDAPC] D7_APC_0: 0x0
9996 13:54:03.630761 INFO: [NOCDAPC] D7_APC_1: 0xfff
9997 13:54:03.633398 INFO: [NOCDAPC] D8_APC_0: 0x0
9998 13:54:03.637757 INFO: [NOCDAPC] D8_APC_1: 0xfff
9999 13:54:03.640475 INFO: [NOCDAPC] D9_APC_0: 0x0
10000 13:54:03.643349 INFO: [NOCDAPC] D9_APC_1: 0xfff
10001 13:54:03.646856 INFO: [NOCDAPC] D10_APC_0: 0x0
10002 13:54:03.650359 INFO: [NOCDAPC] D10_APC_1: 0xfff
10003 13:54:03.653404 INFO: [NOCDAPC] D11_APC_0: 0x0
10004 13:54:03.656730 INFO: [NOCDAPC] D11_APC_1: 0xfff
10005 13:54:03.660012 INFO: [NOCDAPC] D12_APC_0: 0x0
10006 13:54:03.663475 INFO: [NOCDAPC] D12_APC_1: 0xfff
10007 13:54:03.666669 INFO: [NOCDAPC] D13_APC_0: 0x0
10008 13:54:03.669923 INFO: [NOCDAPC] D13_APC_1: 0xfff
10009 13:54:03.673128 INFO: [NOCDAPC] D14_APC_0: 0x0
10010 13:54:03.673210 INFO: [NOCDAPC] D14_APC_1: 0xfff
10011 13:54:03.676668 INFO: [NOCDAPC] D15_APC_0: 0x0
10012 13:54:03.679528 INFO: [NOCDAPC] D15_APC_1: 0xfff
10013 13:54:03.682962 INFO: [NOCDAPC] APC_CON: 0x4
10014 13:54:03.686277 INFO: [APUAPC] set_apusys_apc done
10015 13:54:03.689953 INFO: [DEVAPC] devapc_init done
10016 13:54:03.692802 INFO: GICv3 without legacy support detected.
10017 13:54:03.699376 INFO: ARM GICv3 driver initialized in EL3
10018 13:54:03.702692 INFO: Maximum SPI INTID supported: 639
10019 13:54:03.706100 INFO: BL31: Initializing runtime services
10020 13:54:03.712530 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10021 13:54:03.716000 INFO: SPM: enable CPC mode
10022 13:54:03.719426 INFO: mcdi ready for mcusys-off-idle and system suspend
10023 13:54:03.726031 INFO: BL31: Preparing for EL3 exit to normal world
10024 13:54:03.729252 INFO: Entry point address = 0x80000000
10025 13:54:03.729322 INFO: SPSR = 0x8
10026 13:54:03.736503
10027 13:54:03.736578
10028 13:54:03.736641
10029 13:54:03.739083 Starting depthcharge on Spherion...
10030 13:54:03.739166
10031 13:54:03.739230 Wipe memory regions:
10032 13:54:03.739291
10033 13:54:03.739959 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10034 13:54:03.740060 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10035 13:54:03.740144 Setting prompt string to ['asurada:']
10036 13:54:03.740225 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10037 13:54:03.742095 [0x00000040000000, 0x00000054600000)
10038 13:54:03.864616
10039 13:54:03.864730 [0x00000054660000, 0x00000080000000)
10040 13:54:04.125495
10041 13:54:04.125629 [0x000000821a7280, 0x000000ffe64000)
10042 13:54:04.870219
10043 13:54:04.870359 [0x00000100000000, 0x00000240000000)
10044 13:54:06.758724
10045 13:54:06.761975 Initializing XHCI USB controller at 0x11200000.
10046 13:54:07.800530
10047 13:54:07.803176 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10048 13:54:07.803268
10049 13:54:07.803333
10050 13:54:07.803436
10051 13:54:07.803716 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 13:54:07.904092 asurada: tftpboot 192.168.201.1 12682921/tftp-deploy-7hfvud89/kernel/image.itb 12682921/tftp-deploy-7hfvud89/kernel/cmdline
10054 13:54:07.904230 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10055 13:54:07.904318 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10056 13:54:07.908542 tftpboot 192.168.201.1 12682921/tftp-deploy-7hfvud89/kernel/image.ittp-deploy-7hfvud89/kernel/cmdline
10057 13:54:07.908627
10058 13:54:07.908692 Waiting for link
10059 13:54:08.069087
10060 13:54:08.069203 R8152: Initializing
10061 13:54:08.069273
10062 13:54:08.072374 Version 6 (ocp_data = 5c30)
10063 13:54:08.072444
10064 13:54:08.075349 R8152: Done initializing
10065 13:54:08.075456
10066 13:54:08.075517 Adding net device
10067 13:54:10.009802
10068 13:54:10.009936 done.
10069 13:54:10.010004
10070 13:54:10.010065 MAC: 00:24:32:30:7c:7b
10071 13:54:10.010123
10072 13:54:10.013052 Sending DHCP discover... done.
10073 13:54:10.013135
10074 13:54:10.016341 Waiting for reply... done.
10075 13:54:10.016424
10076 13:54:10.019829 Sending DHCP request... done.
10077 13:54:10.019911
10078 13:54:10.019976 Waiting for reply... done.
10079 13:54:10.020036
10080 13:54:10.022965 My ip is 192.168.201.14
10081 13:54:10.023077
10082 13:54:10.026436 The DHCP server ip is 192.168.201.1
10083 13:54:10.026518
10084 13:54:10.029362 TFTP server IP predefined by user: 192.168.201.1
10085 13:54:10.029445
10086 13:54:10.036320 Bootfile predefined by user: 12682921/tftp-deploy-7hfvud89/kernel/image.itb
10087 13:54:10.036403
10088 13:54:10.039562 Sending tftp read request... done.
10089 13:54:10.039643
10090 13:54:10.042881 Waiting for the transfer...
10091 13:54:10.046196
10092 13:54:10.593593 00000000 ################################################################
10093 13:54:10.593729
10094 13:54:11.116459 00080000 ################################################################
10095 13:54:11.116597
10096 13:54:11.651550 00100000 ################################################################
10097 13:54:11.651690
10098 13:54:12.178368 00180000 ################################################################
10099 13:54:12.178499
10100 13:54:12.706940 00200000 ################################################################
10101 13:54:12.707080
10102 13:54:13.371620 00280000 ################################################################
10103 13:54:13.372136
10104 13:54:14.080900 00300000 ################################################################
10105 13:54:14.081395
10106 13:54:14.783656 00380000 ################################################################
10107 13:54:14.784153
10108 13:54:15.464383 00400000 ################################################################
10109 13:54:15.464627
10110 13:54:16.070258 00480000 ################################################################
10111 13:54:16.070394
10112 13:54:16.678878 00500000 ################################################################
10113 13:54:16.679021
10114 13:54:17.262920 00580000 ################################################################
10115 13:54:17.263054
10116 13:54:17.838118 00600000 ################################################################
10117 13:54:17.838249
10118 13:54:18.412741 00680000 ################################################################
10119 13:54:18.412884
10120 13:54:19.116665 00700000 ################################################################
10121 13:54:19.117218
10122 13:54:19.775412 00780000 ################################################################
10123 13:54:19.776009
10124 13:54:20.424346 00800000 ################################################################
10125 13:54:20.424499
10126 13:54:20.981288 00880000 ################################################################
10127 13:54:20.981434
10128 13:54:21.541725 00900000 ################################################################
10129 13:54:21.541876
10130 13:54:22.178108 00980000 ################################################################
10131 13:54:22.178245
10132 13:54:22.777604 00a00000 ################################################################
10133 13:54:22.777780
10134 13:54:23.462708 00a80000 ################################################################
10135 13:54:23.462868
10136 13:54:24.151439 00b00000 ################################################################
10137 13:54:24.152048
10138 13:54:24.857378 00b80000 ################################################################
10139 13:54:24.858072
10140 13:54:25.552006 00c00000 ################################################################
10141 13:54:25.552504
10142 13:54:26.213004 00c80000 ################################################################
10143 13:54:26.213512
10144 13:54:26.883468 00d00000 ################################################################
10145 13:54:26.883600
10146 13:54:27.520366 00d80000 ################################################################
10147 13:54:27.520871
10148 13:54:28.173919 00e00000 ################################################################
10149 13:54:28.174088
10150 13:54:28.794910 00e80000 ################################################################
10151 13:54:28.795440
10152 13:54:29.442940 00f00000 ################################################################
10153 13:54:29.443477
10154 13:54:30.126809 00f80000 ################################################################
10155 13:54:30.127332
10156 13:54:30.819133 01000000 ################################################################
10157 13:54:30.819733
10158 13:54:31.497735 01080000 ################################################################
10159 13:54:31.498225
10160 13:54:32.106117 01100000 ################################################################
10161 13:54:32.106266
10162 13:54:32.674664 01180000 ################################################################
10163 13:54:32.674802
10164 13:54:33.318651 01200000 ################################################################
10165 13:54:33.319330
10166 13:54:33.987656 01280000 ################################################################
10167 13:54:33.987835
10168 13:54:34.667864 01300000 ################################################################
10169 13:54:34.668448
10170 13:54:35.357889 01380000 ################################################################
10171 13:54:35.358444
10172 13:54:36.029149 01400000 ################################################################
10173 13:54:36.029294
10174 13:54:36.674179 01480000 ################################################################
10175 13:54:36.674688
10176 13:54:37.360829 01500000 ################################################################
10177 13:54:37.361456
10178 13:54:38.055838 01580000 ################################################################
10179 13:54:38.056391
10180 13:54:38.746723 01600000 ################################################################
10181 13:54:38.747214
10182 13:54:39.414475 01680000 ################################################################
10183 13:54:39.415287
10184 13:54:40.015178 01700000 ################################################################
10185 13:54:40.015339
10186 13:54:40.579520 01780000 ################################################################
10187 13:54:40.579684
10188 13:54:41.223611 01800000 ################################################################
10189 13:54:41.224117
10190 13:54:41.880021 01880000 ################################################################
10191 13:54:41.880152
10192 13:54:42.463998 01900000 ################################################################
10193 13:54:42.464163
10194 13:54:43.136277 01980000 ################################################################
10195 13:54:43.136807
10196 13:54:43.841328 01a00000 ################################################################
10197 13:54:43.841979
10198 13:54:44.515566 01a80000 ################################################################
10199 13:54:44.516073
10200 13:54:45.221781 01b00000 ################################################################
10201 13:54:45.222438
10202 13:54:45.928425 01b80000 ################################################################
10203 13:54:45.928968
10204 13:54:46.668911 01c00000 ################################################################
10205 13:54:46.669433
10206 13:54:46.676497 01c80000 # done.
10207 13:54:46.676916
10208 13:54:46.679873 The bootfile was 29889258 bytes long.
10209 13:54:46.680293
10210 13:54:46.682633 Sending tftp read request... done.
10211 13:54:46.683193
10212 13:54:46.687024 Waiting for the transfer...
10213 13:54:46.687488
10214 13:54:46.687824 00000000 # done.
10215 13:54:46.688142
10216 13:54:46.693756 Command line loaded dynamically from TFTP file: 12682921/tftp-deploy-7hfvud89/kernel/cmdline
10217 13:54:46.696290
10218 13:54:46.716278 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682921/extract-nfsrootfs-9lggu5gw,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10219 13:54:46.716813
10220 13:54:46.717144 Loading FIT.
10221 13:54:46.719847
10222 13:54:46.720310 Image ramdisk-1 has 17793086 bytes.
10223 13:54:46.720643
10224 13:54:46.722679 Image fdt-1 has 47278 bytes.
10225 13:54:46.723095
10226 13:54:46.726259 Image kernel-1 has 12046857 bytes.
10227 13:54:46.726672
10228 13:54:46.737313 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10229 13:54:46.737831
10230 13:54:46.752617 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10231 13:54:46.753160
10232 13:54:46.759609 Choosing best match conf-1 for compat google,spherion-rev2.
10233 13:54:46.762694
10234 13:54:46.767162 Connected to device vid:did:rid of 1ae0:0028:00
10235 13:54:46.774720
10236 13:54:46.777894 tpm_get_response: command 0x17b, return code 0x0
10237 13:54:46.778411
10238 13:54:46.784195 ec_init: CrosEC protocol v3 supported (256, 248)
10239 13:54:46.784619
10240 13:54:46.787424 tpm_cleanup: add release locality here.
10241 13:54:46.787854
10242 13:54:46.790729 Shutting down all USB controllers.
10243 13:54:46.791154
10244 13:54:46.794340 Removing current net device
10245 13:54:46.794853
10246 13:54:46.797356 Exiting depthcharge with code 4 at timestamp: 72296769
10247 13:54:46.797839
10248 13:54:46.802288 LZMA decompressing kernel-1 to 0x821a6718
10249 13:54:46.804109
10250 13:54:46.807201 LZMA decompressing kernel-1 to 0x40000000
10251 13:54:48.307767
10252 13:54:48.308319 jumping to kernel
10253 13:54:48.310050 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10254 13:54:48.310585 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10255 13:54:48.311010 Setting prompt string to ['Linux version [0-9]']
10256 13:54:48.311436 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10257 13:54:48.311934 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10258 13:54:48.389578
10259 13:54:48.392615 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10260 13:54:48.396297 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10261 13:54:48.396880 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10262 13:54:48.397283 Setting prompt string to []
10263 13:54:48.397699 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10264 13:54:48.398096 Using line separator: #'\n'#
10265 13:54:48.398430 No login prompt set.
10266 13:54:48.398784 Parsing kernel messages
10267 13:54:48.399095 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10268 13:54:48.399723 [login-action] Waiting for messages, (timeout 00:03:41)
10269 13:54:48.416019 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10270 13:54:48.419280 [ 0.000000] random: crng init done
10271 13:54:48.425680 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10272 13:54:48.428703 [ 0.000000] efi: UEFI not found.
10273 13:54:48.436284 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10274 13:54:48.442267 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10275 13:54:48.452079 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10276 13:54:48.462521 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10277 13:54:48.468444 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10278 13:54:48.475517 [ 0.000000] printk: bootconsole [mtk8250] enabled
10279 13:54:48.481834 [ 0.000000] NUMA: No NUMA configuration found
10280 13:54:48.487955 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10281 13:54:48.492240 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10282 13:54:48.495171 [ 0.000000] Zone ranges:
10283 13:54:48.501553 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10284 13:54:48.504905 [ 0.000000] DMA32 empty
10285 13:54:48.511739 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10286 13:54:48.514671 [ 0.000000] Movable zone start for each node
10287 13:54:48.518473 [ 0.000000] Early memory node ranges
10288 13:54:48.525686 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10289 13:54:48.531754 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10290 13:54:48.538245 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10291 13:54:48.544836 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10292 13:54:48.551157 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10293 13:54:48.558583 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10294 13:54:48.613322 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10295 13:54:48.620697 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10296 13:54:48.626889 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10297 13:54:48.630307 [ 0.000000] psci: probing for conduit method from DT.
10298 13:54:48.637251 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10299 13:54:48.640079 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10300 13:54:48.646687 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10301 13:54:48.649987 [ 0.000000] psci: SMC Calling Convention v1.2
10302 13:54:48.657936 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10303 13:54:48.659824 [ 0.000000] Detected VIPT I-cache on CPU0
10304 13:54:48.667036 [ 0.000000] CPU features: detected: GIC system register CPU interface
10305 13:54:48.673102 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10306 13:54:48.680304 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10307 13:54:48.685853 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10308 13:54:48.696259 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10309 13:54:48.702503 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10310 13:54:48.706074 [ 0.000000] alternatives: applying boot alternatives
10311 13:54:48.712613 [ 0.000000] Fallback order for Node 0: 0
10312 13:54:48.718832 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10313 13:54:48.721906 [ 0.000000] Policy zone: Normal
10314 13:54:48.745512 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682921/extract-nfsrootfs-9lggu5gw,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10315 13:54:48.755422 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10316 13:54:48.765637 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10317 13:54:48.775669 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10318 13:54:48.782227 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10319 13:54:48.785409 <6>[ 0.000000] software IO TLB: area num 8.
10320 13:54:48.842197 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10321 13:54:48.991459 <6>[ 0.000000] Memory: 7949876K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402892K reserved, 32768K cma-reserved)
10322 13:54:48.997976 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10323 13:54:49.004329 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10324 13:54:49.007539 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10325 13:54:49.014485 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10326 13:54:49.020351 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10327 13:54:49.026951 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10328 13:54:49.034041 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10329 13:54:49.040379 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10330 13:54:49.047210 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10331 13:54:49.053885 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10332 13:54:49.056817 <6>[ 0.000000] GICv3: 608 SPIs implemented
10333 13:54:49.060204 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10334 13:54:49.067394 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10335 13:54:49.070161 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10336 13:54:49.076782 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10337 13:54:49.089647 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10338 13:54:49.102820 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10339 13:54:49.109820 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10340 13:54:49.117678 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10341 13:54:49.132300 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10342 13:54:49.137757 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10343 13:54:49.144882 <6>[ 0.009235] Console: colour dummy device 80x25
10344 13:54:49.154328 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10345 13:54:49.161030 <6>[ 0.024404] pid_max: default: 32768 minimum: 301
10346 13:54:49.164137 <6>[ 0.029299] LSM: Security Framework initializing
10347 13:54:49.170735 <6>[ 0.034237] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10348 13:54:49.180462 <6>[ 0.042053] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10349 13:54:49.190585 <6>[ 0.051478] cblist_init_generic: Setting adjustable number of callback queues.
10350 13:54:49.193485 <6>[ 0.058921] cblist_init_generic: Setting shift to 3 and lim to 1.
10351 13:54:49.203601 <6>[ 0.065260] cblist_init_generic: Setting adjustable number of callback queues.
10352 13:54:49.210155 <6>[ 0.072688] cblist_init_generic: Setting shift to 3 and lim to 1.
10353 13:54:49.213449 <6>[ 0.079127] rcu: Hierarchical SRCU implementation.
10354 13:54:49.219896 <6>[ 0.084142] rcu: Max phase no-delay instances is 1000.
10355 13:54:49.227196 <6>[ 0.091166] EFI services will not be available.
10356 13:54:49.229543 <6>[ 0.096117] smp: Bringing up secondary CPUs ...
10357 13:54:49.238882 <6>[ 0.101168] Detected VIPT I-cache on CPU1
10358 13:54:49.245156 <6>[ 0.101238] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10359 13:54:49.251927 <6>[ 0.101268] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10360 13:54:49.255549 <6>[ 0.101610] Detected VIPT I-cache on CPU2
10361 13:54:49.261840 <6>[ 0.101662] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10362 13:54:49.271486 <6>[ 0.101680] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10363 13:54:49.275061 <6>[ 0.101944] Detected VIPT I-cache on CPU3
10364 13:54:49.281764 <6>[ 0.101990] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10365 13:54:49.288584 <6>[ 0.102005] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10366 13:54:49.291424 <6>[ 0.102309] CPU features: detected: Spectre-v4
10367 13:54:49.298866 <6>[ 0.102315] CPU features: detected: Spectre-BHB
10368 13:54:49.301220 <6>[ 0.102320] Detected PIPT I-cache on CPU4
10369 13:54:49.307952 <6>[ 0.102377] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10370 13:54:49.314981 <6>[ 0.102393] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10371 13:54:49.320714 <6>[ 0.102683] Detected PIPT I-cache on CPU5
10372 13:54:49.327562 <6>[ 0.102744] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10373 13:54:49.334666 <6>[ 0.102761] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10374 13:54:49.337828 <6>[ 0.103042] Detected PIPT I-cache on CPU6
10375 13:54:49.345067 <6>[ 0.103106] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10376 13:54:49.354176 <6>[ 0.103123] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10377 13:54:49.357187 <6>[ 0.103420] Detected PIPT I-cache on CPU7
10378 13:54:49.363954 <6>[ 0.103486] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10379 13:54:49.370412 <6>[ 0.103502] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10380 13:54:49.373679 <6>[ 0.103549] smp: Brought up 1 node, 8 CPUs
10381 13:54:49.380684 <6>[ 0.244930] SMP: Total of 8 processors activated.
10382 13:54:49.384176 <6>[ 0.249851] CPU features: detected: 32-bit EL0 Support
10383 13:54:49.393381 <6>[ 0.255214] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10384 13:54:49.400047 <6>[ 0.264014] CPU features: detected: Common not Private translations
10385 13:54:49.406537 <6>[ 0.270490] CPU features: detected: CRC32 instructions
10386 13:54:49.413362 <6>[ 0.275841] CPU features: detected: RCpc load-acquire (LDAPR)
10387 13:54:49.416607 <6>[ 0.281802] CPU features: detected: LSE atomic instructions
10388 13:54:49.422779 <6>[ 0.287619] CPU features: detected: Privileged Access Never
10389 13:54:49.429959 <6>[ 0.293399] CPU features: detected: RAS Extension Support
10390 13:54:49.436755 <6>[ 0.299042] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10391 13:54:49.439528 <6>[ 0.306264] CPU: All CPU(s) started at EL2
10392 13:54:49.445976 <6>[ 0.310581] alternatives: applying system-wide alternatives
10393 13:54:49.456358 <6>[ 0.321297] devtmpfs: initialized
10394 13:54:49.472433 <6>[ 0.330266] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10395 13:54:49.478861 <6>[ 0.340230] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10396 13:54:49.482824 <6>[ 0.347897] pinctrl core: initialized pinctrl subsystem
10397 13:54:49.489955 <6>[ 0.354536] DMI not present or invalid.
10398 13:54:49.496224 <6>[ 0.358948] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10399 13:54:49.502994 <6>[ 0.365835] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10400 13:54:49.513085 <6>[ 0.373420] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10401 13:54:49.519533 <6>[ 0.381634] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10402 13:54:49.525857 <6>[ 0.389879] audit: initializing netlink subsys (disabled)
10403 13:54:49.532412 <5>[ 0.395574] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10404 13:54:49.538842 <6>[ 0.396269] thermal_sys: Registered thermal governor 'step_wise'
10405 13:54:49.545999 <6>[ 0.403540] thermal_sys: Registered thermal governor 'power_allocator'
10406 13:54:49.552085 <6>[ 0.409797] cpuidle: using governor menu
10407 13:54:49.555649 <6>[ 0.420757] NET: Registered PF_QIPCRTR protocol family
10408 13:54:49.562533 <6>[ 0.426242] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10409 13:54:49.569062 <6>[ 0.433345] ASID allocator initialised with 32768 entries
10410 13:54:49.575042 <6>[ 0.439900] Serial: AMBA PL011 UART driver
10411 13:54:49.583685 <4>[ 0.448631] Trying to register duplicate clock ID: 134
10412 13:54:49.637416 <6>[ 0.505852] KASLR enabled
10413 13:54:49.651520 <6>[ 0.513625] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10414 13:54:49.658451 <6>[ 0.520641] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10415 13:54:49.665396 <6>[ 0.527129] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10416 13:54:49.672087 <6>[ 0.534132] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10417 13:54:49.678314 <6>[ 0.540622] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10418 13:54:49.685205 <6>[ 0.547626] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10419 13:54:49.691983 <6>[ 0.554112] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10420 13:54:49.698859 <6>[ 0.561119] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10421 13:54:49.702007 <6>[ 0.568628] ACPI: Interpreter disabled.
10422 13:54:49.710248 <6>[ 0.575044] iommu: Default domain type: Translated
10423 13:54:49.716991 <6>[ 0.580157] iommu: DMA domain TLB invalidation policy: strict mode
10424 13:54:49.720350 <5>[ 0.586818] SCSI subsystem initialized
10425 13:54:49.726694 <6>[ 0.590986] usbcore: registered new interface driver usbfs
10426 13:54:49.733491 <6>[ 0.596719] usbcore: registered new interface driver hub
10427 13:54:49.736548 <6>[ 0.602269] usbcore: registered new device driver usb
10428 13:54:49.744178 <6>[ 0.608368] pps_core: LinuxPPS API ver. 1 registered
10429 13:54:49.753412 <6>[ 0.613563] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10430 13:54:49.757093 <6>[ 0.622911] PTP clock support registered
10431 13:54:49.759649 <6>[ 0.627155] EDAC MC: Ver: 3.0.0
10432 13:54:49.767714 <6>[ 0.632315] FPGA manager framework
10433 13:54:49.773846 <6>[ 0.635998] Advanced Linux Sound Architecture Driver Initialized.
10434 13:54:49.776870 <6>[ 0.642778] vgaarb: loaded
10435 13:54:49.783489 <6>[ 0.645929] clocksource: Switched to clocksource arch_sys_counter
10436 13:54:49.787571 <5>[ 0.652370] VFS: Disk quotas dquot_6.6.0
10437 13:54:49.793926 <6>[ 0.656557] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10438 13:54:49.797199 <6>[ 0.663748] pnp: PnP ACPI: disabled
10439 13:54:49.805103 <6>[ 0.670508] NET: Registered PF_INET protocol family
10440 13:54:49.815194 <6>[ 0.676101] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10441 13:54:49.827043 <6>[ 0.688440] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10442 13:54:49.836570 <6>[ 0.697255] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10443 13:54:49.843211 <6>[ 0.705225] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10444 13:54:49.853561 <6>[ 0.713931] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10445 13:54:49.860343 <6>[ 0.723689] TCP: Hash tables configured (established 65536 bind 65536)
10446 13:54:49.866423 <6>[ 0.730549] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10447 13:54:49.875956 <6>[ 0.737751] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10448 13:54:49.883310 <6>[ 0.745454] NET: Registered PF_UNIX/PF_LOCAL protocol family
10449 13:54:49.885998 <6>[ 0.751602] RPC: Registered named UNIX socket transport module.
10450 13:54:49.893106 <6>[ 0.757757] RPC: Registered udp transport module.
10451 13:54:49.896340 <6>[ 0.762688] RPC: Registered tcp transport module.
10452 13:54:49.906348 <6>[ 0.767620] RPC: Registered tcp NFSv4.1 backchannel transport module.
10453 13:54:49.909507 <6>[ 0.774285] PCI: CLS 0 bytes, default 64
10454 13:54:49.913229 <6>[ 0.778620] Unpacking initramfs...
10455 13:54:49.936379 <6>[ 0.798049] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10456 13:54:49.946841 <6>[ 0.806720] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10457 13:54:49.949976 <6>[ 0.815572] kvm [1]: IPA Size Limit: 40 bits
10458 13:54:49.956103 <6>[ 0.820102] kvm [1]: GICv3: no GICV resource entry
10459 13:54:49.960048 <6>[ 0.825123] kvm [1]: disabling GICv2 emulation
10460 13:54:49.966623 <6>[ 0.829809] kvm [1]: GIC system register CPU interface enabled
10461 13:54:49.969604 <6>[ 0.835987] kvm [1]: vgic interrupt IRQ18
10462 13:54:49.976859 <6>[ 0.840355] kvm [1]: VHE mode initialized successfully
10463 13:54:49.982178 <5>[ 0.846772] Initialise system trusted keyrings
10464 13:54:49.989260 <6>[ 0.851592] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10465 13:54:49.996883 <6>[ 0.861663] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10466 13:54:50.003047 <5>[ 0.868046] NFS: Registering the id_resolver key type
10467 13:54:50.006845 <5>[ 0.873344] Key type id_resolver registered
10468 13:54:50.013262 <5>[ 0.877759] Key type id_legacy registered
10469 13:54:50.019784 <6>[ 0.882044] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10470 13:54:50.026113 <6>[ 0.888963] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10471 13:54:50.032788 <6>[ 0.896726] 9p: Installing v9fs 9p2000 file system support
10472 13:54:50.070567 <5>[ 0.934704] Key type asymmetric registered
10473 13:54:50.073604 <5>[ 0.939036] Asymmetric key parser 'x509' registered
10474 13:54:50.082845 <6>[ 0.944224] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10475 13:54:50.086265 <6>[ 0.951845] io scheduler mq-deadline registered
10476 13:54:50.089757 <6>[ 0.956613] io scheduler kyber registered
10477 13:54:50.108578 <6>[ 0.973675] EINJ: ACPI disabled.
10478 13:54:50.141193 <4>[ 0.999494] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10479 13:54:50.150843 <4>[ 1.010126] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10480 13:54:50.166166 <6>[ 1.030949] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10481 13:54:50.174124 <6>[ 1.038991] printk: console [ttyS0] disabled
10482 13:54:50.202108 <6>[ 1.063663] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10483 13:54:50.208446 <6>[ 1.073140] printk: console [ttyS0] enabled
10484 13:54:50.212281 <6>[ 1.073140] printk: console [ttyS0] enabled
10485 13:54:50.219045 <6>[ 1.082039] printk: bootconsole [mtk8250] disabled
10486 13:54:50.221276 <6>[ 1.082039] printk: bootconsole [mtk8250] disabled
10487 13:54:50.228732 <6>[ 1.093372] SuperH (H)SCI(F) driver initialized
10488 13:54:50.231226 <6>[ 1.098650] msm_serial: driver initialized
10489 13:54:50.245961 <6>[ 1.107742] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10490 13:54:50.255601 <6>[ 1.116296] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10491 13:54:50.262453 <6>[ 1.124839] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10492 13:54:50.272574 <6>[ 1.133468] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10493 13:54:50.282705 <6>[ 1.142174] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10494 13:54:50.289404 <6>[ 1.150889] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10495 13:54:50.298933 <6>[ 1.159429] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10496 13:54:50.305638 <6>[ 1.168236] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10497 13:54:50.315607 <6>[ 1.176786] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10498 13:54:50.328019 <6>[ 1.192392] loop: module loaded
10499 13:54:50.334410 <6>[ 1.198396] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10500 13:54:50.357409 <4>[ 1.221715] mtk-pmic-keys: Failed to locate of_node [id: -1]
10501 13:54:50.363920 <6>[ 1.228704] megasas: 07.719.03.00-rc1
10502 13:54:50.373063 <6>[ 1.238141] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10503 13:54:50.380783 <6>[ 1.245329] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10504 13:54:50.396715 <6>[ 1.261999] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10505 13:54:50.453750 <6>[ 1.312121] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10506 13:54:50.656611 <6>[ 1.521998] Freeing initrd memory: 17372K
10507 13:54:50.667319 <6>[ 1.532297] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10508 13:54:50.678414 <6>[ 1.543153] tun: Universal TUN/TAP device driver, 1.6
10509 13:54:50.681300 <6>[ 1.549210] thunder_xcv, ver 1.0
10510 13:54:50.684852 <6>[ 1.552713] thunder_bgx, ver 1.0
10511 13:54:50.687810 <6>[ 1.556208] nicpf, ver 1.0
10512 13:54:50.698968 <6>[ 1.560237] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10513 13:54:50.701816 <6>[ 1.567713] hns3: Copyright (c) 2017 Huawei Corporation.
10514 13:54:50.708246 <6>[ 1.573298] hclge is initializing
10515 13:54:50.711574 <6>[ 1.576878] e1000: Intel(R) PRO/1000 Network Driver
10516 13:54:50.718555 <6>[ 1.582007] e1000: Copyright (c) 1999-2006 Intel Corporation.
10517 13:54:50.721564 <6>[ 1.588019] e1000e: Intel(R) PRO/1000 Network Driver
10518 13:54:50.728406 <6>[ 1.593235] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10519 13:54:50.735021 <6>[ 1.599423] igb: Intel(R) Gigabit Ethernet Network Driver
10520 13:54:50.741545 <6>[ 1.605072] igb: Copyright (c) 2007-2014 Intel Corporation.
10521 13:54:50.748027 <6>[ 1.610908] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10522 13:54:50.754831 <6>[ 1.617425] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10523 13:54:50.758494 <6>[ 1.623885] sky2: driver version 1.30
10524 13:54:50.765665 <6>[ 1.628874] VFIO - User Level meta-driver version: 0.3
10525 13:54:50.772079 <6>[ 1.637097] usbcore: registered new interface driver usb-storage
10526 13:54:50.778740 <6>[ 1.643545] usbcore: registered new device driver onboard-usb-hub
10527 13:54:50.788223 <6>[ 1.652688] mt6397-rtc mt6359-rtc: registered as rtc0
10528 13:54:50.797526 <6>[ 1.658154] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:54:52 UTC (1706795692)
10529 13:54:50.801049 <6>[ 1.667714] i2c_dev: i2c /dev entries driver
10530 13:54:50.817922 <6>[ 1.679316] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10531 13:54:50.838320 <6>[ 1.703295] cpu cpu0: EM: created perf domain
10532 13:54:50.841287 <6>[ 1.708226] cpu cpu4: EM: created perf domain
10533 13:54:50.848688 <6>[ 1.713787] sdhci: Secure Digital Host Controller Interface driver
10534 13:54:50.855255 <6>[ 1.720221] sdhci: Copyright(c) Pierre Ossman
10535 13:54:50.861978 <6>[ 1.725177] Synopsys Designware Multimedia Card Interface Driver
10536 13:54:50.868470 <6>[ 1.731810] sdhci-pltfm: SDHCI platform and OF driver helper
10537 13:54:50.872098 <6>[ 1.731849] mmc0: CQHCI version 5.10
10538 13:54:50.878484 <6>[ 1.741894] ledtrig-cpu: registered to indicate activity on CPUs
10539 13:54:50.885386 <6>[ 1.748938] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10540 13:54:50.891656 <6>[ 1.755995] usbcore: registered new interface driver usbhid
10541 13:54:50.895047 <6>[ 1.761817] usbhid: USB HID core driver
10542 13:54:50.901682 <6>[ 1.766029] spi_master spi0: will run message pump with realtime priority
10543 13:54:50.948006 <6>[ 1.806578] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10544 13:54:50.968340 <6>[ 1.822413] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10545 13:54:50.971469 <6>[ 1.835966] mmc0: Command Queue Engine enabled
10546 13:54:50.978389 <6>[ 1.838843] cros-ec-spi spi0.0: Chrome EC device registered
10547 13:54:50.981344 <6>[ 1.840704] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10548 13:54:50.988849 <6>[ 1.853839] mmcblk0: mmc0:0001 DA4128 116 GiB
10549 13:54:51.000841 <6>[ 1.861820] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10550 13:54:51.007441 <6>[ 1.866641] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10551 13:54:51.013542 <6>[ 1.872184] NET: Registered PF_PACKET protocol family
10552 13:54:51.016946 <6>[ 1.878083] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10553 13:54:51.023402 <6>[ 1.882458] 9pnet: Installing 9P2000 support
10554 13:54:51.026188 <6>[ 1.888283] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10555 13:54:51.033379 <5>[ 1.892135] Key type dns_resolver registered
10556 13:54:51.039553 <6>[ 1.898026] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10557 13:54:51.043245 <6>[ 1.902330] registered taskstats version 1
10558 13:54:51.046267 <5>[ 1.912765] Loading compiled-in X.509 certificates
10559 13:54:51.079209 <4>[ 1.937253] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10560 13:54:51.088949 <4>[ 1.947991] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10561 13:54:51.095522 <3>[ 1.958539] debugfs: File 'uA_load' in directory '/' already present!
10562 13:54:51.101898 <3>[ 1.965243] debugfs: File 'min_uV' in directory '/' already present!
10563 13:54:51.108715 <3>[ 1.971899] debugfs: File 'max_uV' in directory '/' already present!
10564 13:54:51.115122 <3>[ 1.978511] debugfs: File 'constraint_flags' in directory '/' already present!
10565 13:54:51.127246 <3>[ 1.988489] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10566 13:54:51.136295 <6>[ 2.001333] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10567 13:54:51.143052 <6>[ 2.008303] xhci-mtk 11200000.usb: xHCI Host Controller
10568 13:54:51.149821 <6>[ 2.013800] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10569 13:54:51.160108 <6>[ 2.021648] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10570 13:54:51.166912 <6>[ 2.031064] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10571 13:54:51.173037 <6>[ 2.037144] xhci-mtk 11200000.usb: xHCI Host Controller
10572 13:54:51.179962 <6>[ 2.042620] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10573 13:54:51.186484 <6>[ 2.050267] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10574 13:54:51.194146 <6>[ 2.057913] hub 1-0:1.0: USB hub found
10575 13:54:51.196148 <6>[ 2.061923] hub 1-0:1.0: 1 port detected
10576 13:54:51.203231 <6>[ 2.066185] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10577 13:54:51.209549 <6>[ 2.074720] hub 2-0:1.0: USB hub found
10578 13:54:51.212637 <6>[ 2.078723] hub 2-0:1.0: 1 port detected
10579 13:54:51.221995 <6>[ 2.086857] mtk-msdc 11f70000.mmc: Got CD GPIO
10580 13:54:51.231817 <6>[ 2.093148] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10581 13:54:51.238499 <6>[ 2.101229] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10582 13:54:51.248797 <4>[ 2.109152] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10583 13:54:51.258277 <6>[ 2.118852] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10584 13:54:51.265193 <6>[ 2.126944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10585 13:54:51.271500 <6>[ 2.135132] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10586 13:54:51.281232 <6>[ 2.143065] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10587 13:54:51.288487 <6>[ 2.150887] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10588 13:54:51.298390 <6>[ 2.158719] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10589 13:54:51.308677 <6>[ 2.169282] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10590 13:54:51.315069 <6>[ 2.177665] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10591 13:54:51.324515 <6>[ 2.186008] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10592 13:54:51.331111 <6>[ 2.194347] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10593 13:54:51.340903 <6>[ 2.202685] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10594 13:54:51.347790 <6>[ 2.211025] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10595 13:54:51.357640 <6>[ 2.219365] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10596 13:54:51.365213 <6>[ 2.227703] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10597 13:54:51.374467 <6>[ 2.236043] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10598 13:54:51.383888 <6>[ 2.244381] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10599 13:54:51.390827 <6>[ 2.252732] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10600 13:54:51.400992 <6>[ 2.261070] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10601 13:54:51.408079 <6>[ 2.269409] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10602 13:54:51.417634 <6>[ 2.277749] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10603 13:54:51.424080 <6>[ 2.286089] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10604 13:54:51.430646 <6>[ 2.294834] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10605 13:54:51.437432 <6>[ 2.302006] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10606 13:54:51.444221 <6>[ 2.308734] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10607 13:54:51.450528 <6>[ 2.315497] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10608 13:54:51.460507 <6>[ 2.322443] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10609 13:54:51.467446 <6>[ 2.329285] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10610 13:54:51.477146 <6>[ 2.338413] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10611 13:54:51.487303 <6>[ 2.347532] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10612 13:54:51.496756 <6>[ 2.356826] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10613 13:54:51.506829 <6>[ 2.366293] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10614 13:54:51.513663 <6>[ 2.375766] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10615 13:54:51.523482 <6>[ 2.384902] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10616 13:54:51.533472 <6>[ 2.394368] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10617 13:54:51.543431 <6>[ 2.403486] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10618 13:54:51.553427 <6>[ 2.412780] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10619 13:54:51.562978 <6>[ 2.422939] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10620 13:54:51.573104 <6>[ 2.434929] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10621 13:54:51.579545 <6>[ 2.444625] Trying to probe devices needed for running init ...
10622 13:54:51.624313 <6>[ 2.486200] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10623 13:54:51.779247 <6>[ 2.644036] hub 1-1:1.0: USB hub found
10624 13:54:51.781786 <6>[ 2.648559] hub 1-1:1.0: 4 ports detected
10625 13:54:51.792114 <6>[ 2.657498] hub 1-1:1.0: USB hub found
10626 13:54:51.795415 <6>[ 2.661858] hub 1-1:1.0: 4 ports detected
10627 13:54:51.904906 <6>[ 2.766538] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10628 13:54:51.930962 <6>[ 2.796229] hub 2-1:1.0: USB hub found
10629 13:54:51.934105 <6>[ 2.800756] hub 2-1:1.0: 3 ports detected
10630 13:54:51.943488 <6>[ 2.808559] hub 2-1:1.0: USB hub found
10631 13:54:51.946990 <6>[ 2.813004] hub 2-1:1.0: 3 ports detected
10632 13:54:52.120617 <6>[ 2.982297] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10633 13:54:52.252693 <6>[ 3.117885] hub 1-1.4:1.0: USB hub found
10634 13:54:52.256100 <6>[ 3.122537] hub 1-1.4:1.0: 2 ports detected
10635 13:54:52.265752 <6>[ 3.130878] hub 1-1.4:1.0: USB hub found
10636 13:54:52.269140 <6>[ 3.135499] hub 1-1.4:1.0: 2 ports detected
10637 13:54:52.336327 <6>[ 3.198360] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10638 13:54:52.565444 <6>[ 3.426219] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10639 13:54:52.756220 <6>[ 3.618215] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10640 13:55:03.865202 <6>[ 14.735199] ALSA device list:
10641 13:55:03.871846 <6>[ 14.738495] No soundcards found.
10642 13:55:03.880324 <6>[ 14.746468] Freeing unused kernel memory: 8448K
10643 13:55:03.883341 <6>[ 14.751461] Run /init as init process
10644 13:55:03.894773 Loading, please wait...
10645 13:55:03.914673 Starting version 247.3-7+deb11u2
10646 13:55:04.102210 <6>[ 14.965513] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10647 13:55:04.113523 <6>[ 14.979925] remoteproc remoteproc0: scp is available
10648 13:55:04.120024 <6>[ 14.985631] remoteproc remoteproc0: powering up scp
10649 13:55:04.126651 <6>[ 14.990808] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10650 13:55:04.136412 <6>[ 14.992369] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10651 13:55:04.143692 <6>[ 14.995098] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10652 13:55:04.149655 <3>[ 14.995869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 13:55:04.159636 <3>[ 14.995880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 13:55:04.166097 <3>[ 14.995884] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 13:55:04.176053 <3>[ 14.996594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 13:55:04.182722 <3>[ 14.996599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 13:55:04.192643 <3>[ 14.996602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 13:55:04.199770 <3>[ 14.996607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 13:55:04.209317 <3>[ 14.996610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 13:55:04.215713 <3>[ 14.996638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 13:55:04.225549 <3>[ 14.996660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10662 13:55:04.232212 <3>[ 14.996663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10663 13:55:04.238682 <3>[ 14.996665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10664 13:55:04.249684 <3>[ 14.997141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 13:55:04.255888 <3>[ 14.997146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10666 13:55:04.265878 <3>[ 14.997149] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 13:55:04.272855 <3>[ 14.997152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 13:55:04.282604 <3>[ 14.997154] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 13:55:04.289072 <3>[ 14.997170] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 13:55:04.295490 <6>[ 15.001066] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10671 13:55:04.305336 <6>[ 15.006967] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10672 13:55:04.308213 <6>[ 15.007895] mc: Linux media interface: v0.10
10673 13:55:04.315401 <6>[ 15.009066] usbcore: registered new device driver r8152-cfgselector
10674 13:55:04.324897 <4>[ 15.024525] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10675 13:55:04.328755 <4>[ 15.024525] Fallback method does not support PEC.
10676 13:55:04.338974 <6>[ 15.030984] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10677 13:55:04.341696 <6>[ 15.034384] videodev: Linux video capture interface: v2.00
10678 13:55:04.352020 <4>[ 15.039496] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10679 13:55:04.355825 <6>[ 15.175250] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10680 13:55:04.365599 <6>[ 15.175482] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10681 13:55:04.373285 <4>[ 15.175630] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10682 13:55:04.379526 <6>[ 15.179855] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10683 13:55:04.386386 <6>[ 15.179872] remoteproc remoteproc0: remote processor scp is now up
10684 13:55:04.392830 <6>[ 15.180022] pci_bus 0000:00: root bus resource [bus 00-ff]
10685 13:55:04.402782 <6>[ 15.194341] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10686 13:55:04.409515 <6>[ 15.200263] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10687 13:55:04.419109 <6>[ 15.209908] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10688 13:55:04.425705 <6>[ 15.210712] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10689 13:55:04.436004 <6>[ 15.215129] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10690 13:55:04.445900 <6>[ 15.215642] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10691 13:55:04.452503 <3>[ 15.228274] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10692 13:55:04.459289 <6>[ 15.228832] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10693 13:55:04.468404 <6>[ 15.246432] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10694 13:55:04.475495 <6>[ 15.251645] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10695 13:55:04.485116 <3>[ 15.258297] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10696 13:55:04.488555 <6>[ 15.263869] pci 0000:00:00.0: supports D1 D2
10697 13:55:04.498279 <4>[ 15.285472] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10698 13:55:04.504910 <6>[ 15.290040] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10699 13:55:04.511928 <6>[ 15.290973] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10700 13:55:04.521659 <4>[ 15.298315] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10701 13:55:04.531309 <6>[ 15.298448] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10702 13:55:04.537764 <6>[ 15.308455] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10703 13:55:04.541146 <6>[ 15.317108] Bluetooth: Core ver 2.22
10704 13:55:04.548285 <6>[ 15.325296] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10705 13:55:04.554420 <6>[ 15.331601] NET: Registered PF_BLUETOOTH protocol family
10706 13:55:04.561156 <6>[ 15.339881] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10707 13:55:04.568505 <6>[ 15.347339] Bluetooth: HCI device and connection manager initialized
10708 13:55:04.574701 <6>[ 15.348248] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10709 13:55:04.588148 <6>[ 15.349393] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10710 13:55:04.594300 <6>[ 15.349516] usbcore: registered new interface driver uvcvideo
10711 13:55:04.601497 <6>[ 15.356123] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10712 13:55:04.603996 <6>[ 15.360652] Bluetooth: HCI socket layer initialized
10713 13:55:04.610969 <6>[ 15.366065] r8152 2-1.3:1.0 eth0: v1.12.13
10714 13:55:04.618204 <6>[ 15.366110] usbcore: registered new interface driver r8152
10715 13:55:04.620542 <6>[ 15.369814] pci 0000:01:00.0: supports D1 D2
10716 13:55:04.627193 <6>[ 15.376542] Bluetooth: L2CAP socket layer initialized
10717 13:55:04.634084 <6>[ 15.384790] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10718 13:55:04.637180 <6>[ 15.384940] usbcore: registered new interface driver cdc_ether
10719 13:55:04.643792 <6>[ 15.385749] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10720 13:55:04.650618 <6>[ 15.392877] Bluetooth: SCO socket layer initialized
10721 13:55:04.657259 <6>[ 15.393040] usbcore: registered new interface driver r8153_ecm
10722 13:55:04.663968 <6>[ 15.401941] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10723 13:55:04.669949 <6>[ 15.414110] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10724 13:55:04.673543 <6>[ 15.477857] usbcore: registered new interface driver btusb
10725 13:55:04.687425 <4>[ 15.478826] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10726 13:55:04.689930 <3>[ 15.478842] Bluetooth: hci0: Failed to load firmware file (-2)
10727 13:55:04.697134 <3>[ 15.478848] Bluetooth: hci0: Failed to set up firmware (-2)
10728 13:55:04.706250 <4>[ 15.478855] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10729 13:55:04.716334 <6>[ 15.481749] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10730 13:55:04.723467 <6>[ 15.587504] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10731 13:55:04.733431 <6>[ 15.595507] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10732 13:55:04.739708 <6>[ 15.603512] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10733 13:55:04.750400 <6>[ 15.611512] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10734 13:55:04.753771 <6>[ 15.619513] pci 0000:00:00.0: PCI bridge to [bus 01]
10735 13:55:04.762503 <6>[ 15.624730] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10736 13:55:04.769264 <6>[ 15.632866] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10737 13:55:04.776010 <6>[ 15.639751] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10738 13:55:04.782353 <6>[ 15.646513] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10739 13:55:04.797248 <5>[ 15.660679] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10740 13:55:04.819026 <5>[ 15.681567] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10741 13:55:04.825481 <5>[ 15.688691] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10742 13:55:04.834733 <4>[ 15.697101] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10743 13:55:04.839099 <6>[ 15.705979] cfg80211: failed to load regulatory.db
10744 13:55:04.886908 <6>[ 15.750045] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10745 13:55:04.893450 <6>[ 15.757566] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10746 13:55:04.917988 <6>[ 15.784206] mt7921e 0000:01:00.0: ASIC revision: 79610010
10747 13:55:05.018211 <6>[ 15.881492] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10748 13:55:05.021146 <6>[ 15.881492]
10749 13:55:05.024463 Begin: Loading essential drivers ... done.
10750 13:55:05.028219 Begin: Running /scripts/init-premount ... done.
10751 13:55:05.035791 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10752 13:55:05.044225 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10753 13:55:05.048035 Device /sys/class/net/enx002432307c7b found
10754 13:55:05.048592 done.
10755 13:55:05.082866 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10756 13:55:05.292230 <6>[ 16.155957] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10757 13:55:06.106145 <6>[ 16.973074] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10758 13:55:06.136063 <6>[ 17.003105] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10759 13:55:06.291111 IP-Config: no response after 2 secs - giving up
10760 13:55:06.323295 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10761 13:55:07.042738 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10762 13:55:07.049280 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10763 13:55:07.056087 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10764 13:55:07.062764 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10765 13:55:07.068907 host : mt8192-asurada-spherion-r0-cbg-2
10766 13:55:07.075614 domain : lava-rack
10767 13:55:07.079052 rootserver: 192.168.201.1 rootpath:
10768 13:55:07.079685 filename :
10769 13:55:07.206576 done.
10770 13:55:07.215890 Begin: Running /scripts/nfs-bottom ... done.
10771 13:55:07.239155 Begin: Running /scripts/init-bottom ... done.
10772 13:55:08.495773 <6>[ 19.363169] NET: Registered PF_INET6 protocol family
10773 13:55:08.503131 <6>[ 19.370452] Segment Routing with IPv6
10774 13:55:08.506390 <6>[ 19.374395] In-situ OAM (IOAM) with IPv6
10775 13:55:08.647535 <30>[ 19.495020] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10776 13:55:08.653962 <30>[ 19.519467] systemd[1]: Detected architecture arm64.
10777 13:55:08.675171
10778 13:55:08.678490 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10779 13:55:08.678924
10780 13:55:08.694336 <30>[ 19.561441] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10781 13:55:09.642040 <30>[ 20.505787] systemd[1]: Queued start job for default target Graphical Interface.
10782 13:55:09.669408 <30>[ 20.536659] systemd[1]: Created slice system-getty.slice.
10783 13:55:09.675892 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10784 13:55:09.692534 <30>[ 20.559679] systemd[1]: Created slice system-modprobe.slice.
10785 13:55:09.699009 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10786 13:55:09.716720 <30>[ 20.584302] systemd[1]: Created slice system-serial\x2dgetty.slice.
10787 13:55:09.727451 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10788 13:55:09.740345 <30>[ 20.607280] systemd[1]: Created slice User and Session Slice.
10789 13:55:09.746827 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10790 13:55:09.767870 <30>[ 20.631056] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10791 13:55:09.777175 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10792 13:55:09.795358 <30>[ 20.658974] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10793 13:55:09.801649 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10794 13:55:09.825847 <30>[ 20.686360] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10795 13:55:09.832575 <30>[ 20.698552] systemd[1]: Reached target Local Encrypted Volumes.
10796 13:55:09.839153 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10797 13:55:09.855450 <30>[ 20.722783] systemd[1]: Reached target Paths.
10798 13:55:09.862109 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10799 13:55:09.875053 <30>[ 20.742211] systemd[1]: Reached target Remote File Systems.
10800 13:55:09.881720 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10801 13:55:09.899723 <30>[ 20.766585] systemd[1]: Reached target Slices.
10802 13:55:09.905840 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10803 13:55:09.919237 <30>[ 20.786246] systemd[1]: Reached target Swap.
10804 13:55:09.922051 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10805 13:55:09.942699 <30>[ 20.806705] systemd[1]: Listening on initctl Compatibility Named Pipe.
10806 13:55:09.949420 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10807 13:55:09.956082 <30>[ 20.823039] systemd[1]: Listening on Journal Audit Socket.
10808 13:55:09.963185 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10809 13:55:09.980945 <30>[ 20.847698] systemd[1]: Listening on Journal Socket (/dev/log).
10810 13:55:09.987041 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10811 13:55:10.003574 <30>[ 20.870796] systemd[1]: Listening on Journal Socket.
10812 13:55:10.010543 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10813 13:55:10.028096 <30>[ 20.891927] systemd[1]: Listening on Network Service Netlink Socket.
10814 13:55:10.034202 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10815 13:55:10.051192 <30>[ 20.917521] systemd[1]: Listening on udev Control Socket.
10816 13:55:10.057253 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10817 13:55:10.071592 <30>[ 20.938661] systemd[1]: Listening on udev Kernel Socket.
10818 13:55:10.078530 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10819 13:55:10.135139 <30>[ 21.002443] systemd[1]: Mounting Huge Pages File System...
10820 13:55:10.141877 Mounting [0;1;39mHuge Pages File System[0m...
10821 13:55:10.160034 <30>[ 21.026720] systemd[1]: Mounting POSIX Message Queue File System...
10822 13:55:10.166383 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10823 13:55:10.214981 <30>[ 21.082710] systemd[1]: Mounting Kernel Debug File System...
10824 13:55:10.221664 Mounting [0;1;39mKernel Debug File System[0m...
10825 13:55:10.238440 <30>[ 21.102609] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10826 13:55:10.255718 <30>[ 21.119578] systemd[1]: Starting Create list of static device nodes for the current kernel...
10827 13:55:10.265836 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10828 13:55:10.311542 <30>[ 21.179189] systemd[1]: Starting Load Kernel Module configfs...
10829 13:55:10.318075 Starting [0;1;39mLoad Kernel Module configfs[0m...
10830 13:55:10.340536 <30>[ 21.207412] systemd[1]: Starting Load Kernel Module drm...
10831 13:55:10.347182 Starting [0;1;39mLoad Kernel Module drm[0m...
10832 13:55:10.364093 <30>[ 21.231363] systemd[1]: Starting Load Kernel Module fuse...
10833 13:55:10.370650 Starting [0;1;39mLoad Kernel Module fuse[0m...
10834 13:55:10.406848 <30>[ 21.270707] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10835 13:55:10.413924 <6>[ 21.281006] fuse: init (API version 7.37)
10836 13:55:10.455978 <30>[ 21.322815] systemd[1]: Starting Journal Service...
10837 13:55:10.459222 Starting [0;1;39mJournal Service[0m...
10838 13:55:10.486187 <30>[ 21.353238] systemd[1]: Starting Load Kernel Modules...
10839 13:55:10.492459 Starting [0;1;39mLoad Kernel Modules[0m...
10840 13:55:10.513389 <30>[ 21.377318] systemd[1]: Starting Remount Root and Kernel File Systems...
10841 13:55:10.519412 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10842 13:55:10.539924 <30>[ 21.407606] systemd[1]: Starting Coldplug All udev Devices...
10843 13:55:10.547347 Starting [0;1;39mColdplug All udev Devices[0m...
10844 13:55:10.568014 <30>[ 21.434456] systemd[1]: Mounted Huge Pages File System.
10845 13:55:10.573609 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10846 13:55:10.586962 <30>[ 21.454599] systemd[1]: Mounted POSIX Message Queue File System.
10847 13:55:10.593745 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10848 13:55:10.611234 <30>[ 21.478896] systemd[1]: Mounted Kernel Debug File System.
10849 13:55:10.617956 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10850 13:55:10.639110 <30>[ 21.503505] systemd[1]: Finished Create list of static device nodes for the current kernel.
10851 13:55:10.650251 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10852 13:55:10.664614 <30>[ 21.532069] systemd[1]: modprobe@configfs.service: Succeeded.
10853 13:55:10.671837 <30>[ 21.539356] systemd[1]: Finished Load Kernel Module configfs.
10854 13:55:10.678670 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10855 13:55:10.696258 <30>[ 21.563401] systemd[1]: modprobe@drm.service: Succeeded.
10856 13:55:10.702740 <30>[ 21.569816] systemd[1]: Finished Load Kernel Module drm.
10857 13:55:10.709671 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10858 13:55:10.723758 <30>[ 21.591115] systemd[1]: modprobe@fuse.service: Succeeded.
10859 13:55:10.730272 <30>[ 21.597832] systemd[1]: Finished Load Kernel Module fuse.
10860 13:55:10.737159 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10861 13:55:10.754323 <3>[ 21.617956] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 13:55:10.761603 <30>[ 21.628516] systemd[1]: Finished Load Kernel Modules.
10863 13:55:10.767769 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10864 13:55:10.786884 <3>[ 21.650417] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 13:55:10.793190 <30>[ 21.651788] systemd[1]: Finished Remount Root and Kernel File Systems.
10866 13:55:10.799966 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10867 13:55:10.835540 <3>[ 21.699526] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 13:55:10.868092 <3>[ 21.732160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 13:55:10.874507 <30>[ 21.733257] systemd[1]: Mounting FUSE Control File System...
10870 13:55:10.881434 Mounting [0;1;39mFUSE Control File System[0m...
10871 13:55:10.900027 <3>[ 21.764294] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 13:55:10.906638 <30>[ 21.765418] systemd[1]: Mounting Kernel Configuration File System...
10873 13:55:10.913192 Mounting [0;1;39mKernel Configuration File System[0m...
10874 13:55:10.933955 <3>[ 21.797232] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 13:55:10.943470 <30>[ 21.801772] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10876 13:55:10.953503 <30>[ 21.815421] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10877 13:55:10.968388 <3>[ 21.832783] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 13:55:10.979689 <30>[ 21.846982] systemd[1]: Starting Load/Save Random Seed...
10879 13:55:10.986388 Starting [0;1;39mLoad/Save Random Seed[0m...
10880 13:55:11.001439 <3>[ 21.865721] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 13:55:11.010249 <30>[ 21.877949] systemd[1]: Starting Apply Kernel Variables...
10882 13:55:11.017090 Starting [0;1;39mApply Kernel Variables[0m...
10883 13:55:11.028462 <3>[ 21.892317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 13:55:11.055502 <3>[ 21.919104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 13:55:11.073031 <4>[ 21.927969] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10886 13:55:11.075870 <30>[ 21.934810] systemd[1]: Starting Create System Users...
10887 13:55:11.085897 <3>[ 21.943609] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10888 13:55:11.089558 Starting [0;1;39mCreate System Users[0m...
10889 13:55:11.110965 <29>[ 21.973694] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10890 13:55:11.120153 <28>[ 21.984289] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10891 13:55:11.126577 <27>[ 21.993910] systemd[1]: Failed to start Coldplug All udev Devices.
10892 13:55:11.133323 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10893 13:55:11.150772 See 'systemctl status systemd-udev-trigger.service' for details.
10894 13:55:11.167640 <30>[ 22.034740] systemd[1]: Mounted FUSE Control File System.
10895 13:55:11.174207 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10896 13:55:11.190850 <30>[ 22.058322] systemd[1]: Started Journal Service.
10897 13:55:11.197003 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10898 13:55:11.212571 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10899 13:55:11.229091 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10900 13:55:11.244773 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10901 13:55:11.252849 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10902 13:55:11.299822 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10903 13:55:11.317823 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10904 13:55:11.371450 <46>[ 22.235765] systemd-journald[296]: Received client request to flush runtime journal.
10905 13:55:11.516087 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10906 13:55:11.531848 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10907 13:55:11.547308 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10908 13:55:11.610735 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10909 13:55:12.772731 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10910 13:55:12.820572 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10911 13:55:12.895610 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10912 13:55:12.935442 Starting [0;1;39mNetwork Service[0m...
10913 13:55:13.284536 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10914 13:55:13.307891 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10915 13:55:13.366980 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10916 13:55:13.622049 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10917 13:55:13.642074 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10918 13:55:13.683243 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10919 13:55:13.704326 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10920 13:55:13.718773 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10921 13:55:13.762955 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10922 13:55:13.816130 Starting [0;1;39mNetwork Name Resolution[0m...
10923 13:55:13.844497 Starting [0;1;39mNetwork Time Synchronization[0m...
10924 13:55:13.863328 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10925 13:55:13.879702 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10926 13:55:13.945654 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10927 13:55:14.126864 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10928 13:55:14.147256 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10929 13:55:14.170078 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10930 13:55:14.186327 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10931 13:55:14.193269 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10932 13:55:14.318287 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10933 13:55:14.351302 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10934 13:55:14.389936 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10935 13:55:14.447172 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10936 13:55:14.462878 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10937 13:55:14.810311 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10938 13:55:14.822165 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10939 13:55:14.837899 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10940 13:55:14.878633 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10941 13:55:15.214607 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10942 13:55:15.570593 Starting [0;1;39mUser Login Management[0m...
10943 13:55:15.587654 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10944 13:55:15.604998 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10945 13:55:15.621140 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10946 13:55:15.666715 Starting [0;1;39mPermit User Sessions[0m...
10947 13:55:15.794382 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10948 13:55:15.842203 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10949 13:55:15.861983 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10950 13:55:15.878715 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10951 13:55:15.901908 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10952 13:55:15.943578 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10953 13:55:15.964473 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10954 13:55:15.979856 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10955 13:55:16.035832 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10956 13:55:16.087521 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10957 13:55:16.195066
10958 13:55:16.195611
10959 13:55:16.198440 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10960 13:55:16.198857
10961 13:55:16.201748 debian-bullseye-arm64 login: root (automatic login)
10962 13:55:16.202165
10963 13:55:16.202494
10964 13:55:16.550225 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
10965 13:55:16.550727
10966 13:55:16.557308 The programs included with the Debian GNU/Linux system are free software;
10967 13:55:16.563541 the exact distribution terms for each program are described in the
10968 13:55:16.566831 individual files in /usr/share/doc/*/copyright.
10969 13:55:16.567246
10970 13:55:16.573276 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10971 13:55:16.576812 permitted by applicable law.
10972 13:55:16.706124 Matched prompt #10: / #
10974 13:55:16.707214 Setting prompt string to ['/ #']
10975 13:55:16.707685 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10977 13:55:16.708655 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10978 13:55:16.709146 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
10979 13:55:16.709507 Setting prompt string to ['/ #']
10980 13:55:16.709821 Forcing a shell prompt, looking for ['/ #']
10982 13:55:16.760625 / #
10983 13:55:16.761282 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10984 13:55:16.761804 Waiting using forced prompt support (timeout 00:02:30)
10985 13:55:16.767086
10986 13:55:16.768060 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10987 13:55:16.768762 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
10989 13:55:16.870106 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682921/extract-nfsrootfs-9lggu5gw'
10990 13:55:16.876576 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682921/extract-nfsrootfs-9lggu5gw'
10992 13:55:16.978552 / # export NFS_SERVER_IP='192.168.201.1'
10993 13:55:16.984726 export NFS_SERVER_IP='192.168.201.1'
10994 13:55:16.985661 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10995 13:55:16.986218 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
10996 13:55:16.986700 end: 2 depthcharge-action (duration 00:01:48) [common]
10997 13:55:16.987199 start: 3 lava-test-retry (timeout 00:30:00) [common]
10998 13:55:16.987751 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10999 13:55:16.988222 Using namespace: common
11001 13:55:17.089598 / # #
11002 13:55:17.090247 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11003 13:55:17.096271 #
11004 13:55:17.097141 Using /lava-12682921
11006 13:55:17.198460 / # export SHELL=/bin/sh
11007 13:55:17.205169 export SHELL=/bin/sh
11009 13:55:17.306865 / # . /lava-12682921/environment
11010 13:55:17.313531 . /lava-12682921/environment
11012 13:55:17.422132 / # /lava-12682921/bin/lava-test-runner /lava-12682921/0
11013 13:55:17.422766 Test shell timeout: 10s (minimum of the action and connection timeout)
11014 13:55:17.428719 /lava-12682921/bin/lava-test-runner /lava-12682921/0
11015 13:55:17.729429 + export TESTRUN_ID=0_lc-compliance
11016 13:55:17.735587 + cd /lava-12682921/0/tests/0_lc-compliance
11017 13:55:17.736017 + cat uuid
11018 13:55:17.748846 + UUID=12682921_1.6.2.3.1
11019 13:55:17.749269 + set +x
11020 13:55:17.755264 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12682921_1.6.2.3.1>
11021 13:55:17.755980 Received signal: <STARTRUN> 0_lc-compliance 12682921_1.6.2.3.1
11022 13:55:17.756359 Starting test lava.0_lc-compliance (12682921_1.6.2.3.1)
11023 13:55:17.756773 Skipping test definition patterns.
11024 13:55:17.758476 + /usr/bin/lc-compliance-parser.sh
11025 13:55:19.026131 [0:00:29.773838309] [403] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
11026 13:55:19.029118 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11027 13:55:19.044768 [0:00:29.792672924] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11028 13:55:19.099300 [0:00:29.847210232] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11029 13:55:19.128117 [==========] Running 120 tests from 1 test suite.
11030 13:55:19.152299 [0:00:29.900268232] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11031 13:55:19.207739 [0:00:29.955606617] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11032 13:55:19.236679 [----------] Global test environment set-up.
11033 13:55:19.345121 [----------] 120 tests from CaptureTests/SingleStream
11034 13:55:19.455683 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11035 13:55:19.536547 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11036 13:55:19.536926 Received signal: <TESTSET> START CaptureTests/SingleStream
11037 13:55:19.537053 Starting test_set CaptureTests/SingleStream
11038 13:55:19.539437 Camera needs 4 requests, can't test only 1
11039 13:55:19.642477 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11040 13:55:19.739170
11041 13:55:19.846327 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (55 ms)
11042 13:55:19.902431 [0:00:30.650938463] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11043 13:55:19.977328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11044 13:55:19.978064 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11046 13:55:20.000964 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11047 13:55:20.073855 Camera needs 4 requests, can't test only 2
11048 13:55:20.178250 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11049 13:55:20.281388
11050 13:55:20.390655 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (52 ms)
11051 13:55:20.511189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11052 13:55:20.511941 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11054 13:55:20.532827 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11055 13:55:20.602876 Camera needs 4 requests, can't test only 3
11056 13:55:20.709446 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11057 13:55:20.809640 [0:00:31.558023540] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11058 13:55:20.809810
11059 13:55:20.919683 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (56 ms)
11060 13:55:21.046258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11061 13:55:21.047049 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11063 13:55:21.068445 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11064 13:55:21.139085 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (694 ms)
11065 13:55:21.261015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11066 13:55:21.261315 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11068 13:55:21.282714 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11069 13:55:21.355162 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (907 ms)
11070 13:55:21.478370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11071 13:55:21.479117 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11073 13:55:21.501496 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11074 13:55:22.056460 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1255 ms)
11075 13:55:22.066046 [0:00:32.813109309] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11076 13:55:22.183413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11077 13:55:22.184154 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11079 13:55:22.207053 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11080 13:55:23.870584 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1814 ms)
11081 13:55:23.879787 [0:00:34.627272463] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11082 13:55:23.995163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11083 13:55:23.995933 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11085 13:55:24.015132 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11086 13:55:26.596246 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2727 ms)
11087 13:55:26.606443 [0:00:37.354963232] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11088 13:55:26.726705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11089 13:55:26.727481 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11091 13:55:26.747660 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11092 13:55:30.791315 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4195 ms)
11093 13:55:30.800704 [0:00:41.550888848] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11094 13:55:30.901958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11095 13:55:30.902285 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11097 13:55:30.921296 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11098 13:55:35.284311 <6>[ 46.158179] vpu: disabling
11099 13:55:35.287172 <6>[ 46.161477] vproc2: disabling
11100 13:55:35.291150 <6>[ 46.164961] vproc1: disabling
11101 13:55:35.294627 <6>[ 46.168615] vaud18: disabling
11102 13:55:35.301497 <6>[ 46.172300] vsram_others: disabling
11103 13:55:35.304783 <6>[ 46.176449] va09: disabling
11104 13:55:35.308319 <6>[ 46.179795] vsram_md: disabling
11105 13:55:35.310988 <6>[ 46.183443] Vgpu: disabling
11106 13:55:37.367055 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6577 ms)
11107 13:55:37.376813 [0:00:48.127805925] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11108 13:55:37.430184 [0:00:48.180414618] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11109 13:55:37.486862 [0:00:48.236564618] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11110 13:55:37.489618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11111 13:55:37.489909 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11113 13:55:37.503586 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11114 13:55:37.541641 [0:00:48.292287233] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 13:55:37.564334 Camera needs 4 requests, can't test only 1
11116 13:55:37.642047 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11117 13:55:37.728095
11118 13:55:37.825172 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (54 ms)
11119 13:55:37.932962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11120 13:55:37.933268 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11122 13:55:37.951822 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11123 13:55:38.015954 Camera needs 4 requests, can't test only 2
11124 13:55:38.107412 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11125 13:55:38.202959
11126 13:55:38.236779 [0:00:48.987121156] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 13:55:38.303522 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (56 ms)
11128 13:55:38.415645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11129 13:55:38.415983 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11131 13:55:38.434815 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11132 13:55:38.495622 Camera needs 4 requests, can't test only 3
11133 13:55:38.588114 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11134 13:55:38.675850
11135 13:55:38.773698 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (57 ms)
11136 13:55:38.880401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11137 13:55:38.880727 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11139 13:55:38.901202 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11140 13:55:38.964279 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (694 ms)
11141 13:55:39.067768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11142 13:55:39.068094 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11144 13:55:39.088032 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11145 13:55:39.141878 [0:00:49.892449079] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11146 13:55:39.148765 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (905 ms)
11147 13:55:39.249172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11148 13:55:39.249500 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11150 13:55:39.265676 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11151 13:55:40.388239 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1255 ms)
11152 13:55:40.401754 [0:00:51.147493233] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11153 13:55:40.501092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11154 13:55:40.501415 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11156 13:55:40.521090 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11157 13:55:42.204812 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1816 ms)
11158 13:55:42.216860 [0:00:52.963127156] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11159 13:55:42.308215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11160 13:55:42.308543 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11162 13:55:42.327227 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11163 13:55:44.928098 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2725 ms)
11164 13:55:44.941493 [0:00:55.689580695] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11165 13:55:45.038148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11166 13:55:45.038486 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11168 13:55:45.057772 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11169 13:55:49.124174 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4196 ms)
11170 13:55:49.136700 [0:00:59.885697554] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11171 13:55:49.244609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11172 13:55:49.244935 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11174 13:55:49.265661 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11175 13:55:55.701349 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6576 ms)
11176 13:55:55.713225 [0:01:06.461588991] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11177 13:55:55.762889 [0:01:06.514048567] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 13:55:55.815338 [0:01:06.566402769] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11179 13:55:55.829876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11180 13:55:55.830564 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11182 13:55:55.850830 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11183 13:55:55.868210 [0:01:06.618920800] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11184 13:55:55.926048 Camera needs 4 requests, can't test only 1
11185 13:55:56.024158 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11186 13:55:56.128035
11187 13:55:56.234248 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (54 ms)
11188 13:55:56.353864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11189 13:55:56.354576 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11191 13:55:56.375216 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11192 13:55:56.444617 Camera needs 4 requests, can't test only 2
11193 13:55:56.545846 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11194 13:55:56.561159 [0:01:07.312086742] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11195 13:55:56.647185
11196 13:55:56.759902 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (52 ms)
11197 13:55:56.883309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11198 13:55:56.884103 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11200 13:55:56.906494 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11201 13:55:56.973013 Camera needs 4 requests, can't test only 3
11202 13:55:57.075858 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11203 13:55:57.180203
11204 13:55:57.291181 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (53 ms)
11205 13:55:57.415177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11206 13:55:57.415960 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11208 13:55:57.438163 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11209 13:55:57.464477 [0:01:08.215516979] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11210 13:55:57.516860 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (693 ms)
11211 13:55:57.646694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11212 13:55:57.647545 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11214 13:55:57.669891 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11215 13:55:57.740812 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (904 ms)
11216 13:55:57.865438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11217 13:55:57.866341 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11219 13:55:57.888533 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11220 13:55:58.710980 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1254 ms)
11221 13:55:58.723741 [0:01:09.470372463] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11222 13:55:58.836309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11223 13:55:58.837071 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11225 13:55:58.858638 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11226 13:56:00.526069 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1815 ms)
11227 13:56:00.538006 [0:01:11.285005727] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11228 13:56:00.637995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11229 13:56:00.638891 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11231 13:56:00.656792 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11232 13:56:03.249965 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2724 ms)
11233 13:56:03.262166 [0:01:14.010790534] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11234 13:56:03.345182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11235 13:56:03.345479 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11237 13:56:03.360432 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11238 13:56:07.444568 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4196 ms)
11239 13:56:07.457583 [0:01:18.206746696] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11240 13:56:07.536794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11241 13:56:07.537085 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11243 13:56:07.554529 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11244 13:56:14.020442 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6576 ms)
11245 13:56:14.033832 [0:01:24.783120965] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11246 13:56:14.081593 [0:01:24.834050442] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11247 13:56:14.127279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11248 13:56:14.127581 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11250 13:56:14.140361 [0:01:24.889265944] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11251 13:56:14.146996 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11252 13:56:14.189513 [0:01:24.942293589] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11253 13:56:14.206734 Camera needs 4 requests, can't test only 1
11254 13:56:14.292855 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11255 13:56:14.371779
11256 13:56:14.454569 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (54 ms)
11257 13:56:14.543523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11258 13:56:14.543820 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11260 13:56:14.559422 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11261 13:56:14.612006 Camera needs 4 requests, can't test only 2
11262 13:56:14.689537 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11263 13:56:14.764217
11264 13:56:14.850488 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (53 ms)
11265 13:56:14.886090 [0:01:25.637954941] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11266 13:56:14.952892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11267 13:56:14.953175 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11269 13:56:14.968862 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11270 13:56:15.021471 Camera needs 4 requests, can't test only 3
11271 13:56:15.098397 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11272 13:56:15.173403
11273 13:56:15.255414 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (55 ms)
11274 13:56:15.350166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11275 13:56:15.350464 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11277 13:56:15.367518 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11278 13:56:15.423055 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (695 ms)
11279 13:56:15.517756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11280 13:56:15.518061 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11282 13:56:15.535637 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11283 13:56:15.782870 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (905 ms)
11284 13:56:15.795583 [0:01:26.543921545] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11285 13:56:15.878351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11286 13:56:15.878642 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11288 13:56:15.894212 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11289 13:56:17.037282 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1254 ms)
11290 13:56:17.050680 [0:01:27.798714637] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11291 13:56:17.139181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11292 13:56:17.139471 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11294 13:56:17.156888 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11295 13:56:18.851915 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1815 ms)
11296 13:56:18.865489 [0:01:29.613557387] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11297 13:56:18.950318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11298 13:56:18.950611 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11300 13:56:18.966987 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11301 13:56:21.577405 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2725 ms)
11302 13:56:21.590056 [0:01:32.340307386] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11303 13:56:21.671907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11304 13:56:21.672192 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11306 13:56:21.688069 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11307 13:56:25.772797 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4197 ms)
11308 13:56:25.786071 [0:01:36.536538256] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11309 13:56:25.865740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11310 13:56:25.866028 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11312 13:56:25.882625 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11313 13:56:32.349139 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6576 ms)
11314 13:56:32.362018 [0:01:43.112799938] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11315 13:56:32.409884 [0:01:43.164236919] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11316 13:56:32.449107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11317 13:56:32.449376 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11319 13:56:32.464023 [0:01:43.218405719] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11320 13:56:32.467619 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11321 13:56:32.516871 [0:01:43.270951997] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11322 13:56:32.524642 Camera needs 4 requests, can't test only 1
11323 13:56:32.602127 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11324 13:56:32.671635
11325 13:56:32.757393 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (54 ms)
11326 13:56:32.852510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11327 13:56:32.852808 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11329 13:56:32.869751 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11330 13:56:32.926002 Camera needs 4 requests, can't test only 2
11331 13:56:33.006950 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11332 13:56:33.087312
11333 13:56:33.174607 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11334 13:56:33.271603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11335 13:56:33.271899 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11337 13:56:33.286804 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11338 13:56:33.345226 Camera needs 4 requests, can't test only 3
11339 13:56:33.427288 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11340 13:56:33.503790
11341 13:56:33.583836 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (53 ms)
11342 13:56:33.676897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11343 13:56:33.677185 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11345 13:56:33.693008 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11346 13:56:34.585285 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2076 ms)
11347 13:56:34.598014 [0:01:45.347802505] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11348 13:56:34.682910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11349 13:56:34.683196 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11351 13:56:34.698583 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11352 13:56:37.292491 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2708 ms)
11353 13:56:37.305666 [0:01:48.057434082] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11354 13:56:37.388718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11355 13:56:37.389002 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11357 13:56:37.405541 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11358 13:56:41.050754 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3758 ms)
11359 13:56:41.063948 [0:01:51.815613366] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11360 13:56:41.163551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11361 13:56:41.164250 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11363 13:56:41.184289 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11364 13:56:46.486790 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5436 ms)
11365 13:56:46.499883 [0:01:57.252557765] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11366 13:56:46.606600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11367 13:56:46.606895 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11369 13:56:46.626164 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11370 13:56:54.657035 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8170 ms)
11371 13:56:54.669819 [0:02:05.421799179] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11372 13:56:54.788280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11373 13:56:54.788985 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11375 13:56:54.808547 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11376 13:57:07.233875 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12575 ms)
11377 13:57:07.246682 [0:02:17.997921226] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11378 13:57:07.355846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11379 13:57:07.356568 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11381 13:57:07.375490 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11382 13:57:26.951954 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19718 ms)
11383 13:57:26.965601 [0:02:37.716051845] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11384 13:57:27.013413 [0:02:37.767148176] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11385 13:57:27.064037 [0:02:37.818222152] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11386 13:57:27.071441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11387 13:57:27.072141 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11389 13:57:27.091941 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11390 13:57:27.116099 [0:02:37.870010439] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11391 13:57:27.165852 Camera needs 4 requests, can't test only 1
11392 13:57:27.264594 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11393 13:57:27.356242
11394 13:57:27.460689 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (54 ms)
11395 13:57:27.568615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11396 13:57:27.569393 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11398 13:57:27.584587 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11399 13:57:27.652304 Camera needs 4 requests, can't test only 2
11400 13:57:27.751908 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11401 13:57:27.849517
11402 13:57:27.951490 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (51 ms)
11403 13:57:28.067837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11404 13:57:28.068576 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11406 13:57:28.085914 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11407 13:57:28.155297 Camera needs 4 requests, can't test only 3
11408 13:57:28.256566 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11409 13:57:28.353785
11410 13:57:28.464728 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (52 ms)
11411 13:57:28.583184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11412 13:57:28.583959 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11414 13:57:28.598834 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11415 13:57:29.185472 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2074 ms)
11416 13:57:29.195854 [0:02:39.945039960] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11417 13:57:29.304652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11418 13:57:29.305401 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11420 13:57:29.322740 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11421 13:57:31.897784 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2712 ms)
11422 13:57:31.907373 [0:02:42.659009167] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11423 13:57:31.992578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11424 13:57:31.992860 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11426 13:57:32.006516 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11427 13:57:35.655142 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3758 ms)
11428 13:57:35.664891 [0:02:46.415964278] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11429 13:57:35.745239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11430 13:57:35.745519 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11432 13:57:35.757396 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11433 13:57:41.092147 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5437 ms)
11434 13:57:41.101829 [0:02:51.853319433] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11435 13:57:41.194002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11436 13:57:41.194289 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11438 13:57:41.207983 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11439 13:57:49.263144 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8171 ms)
11440 13:57:49.272631 [0:03:00.024407147] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11441 13:57:49.387472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11442 13:57:49.388182 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11444 13:57:49.404503 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11445 13:58:01.841298 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12579 ms)
11446 13:58:01.851531 [0:03:12.603502284] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11447 13:58:01.974021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11448 13:58:01.974783 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11450 13:58:01.991183 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11451 13:58:21.560318 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19720 ms)
11452 13:58:21.569912 [0:03:32.323332552] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11453 13:58:21.617415 [0:03:32.374215785] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11454 13:58:21.668925 [0:03:32.425476772] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11455 13:58:21.680911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11456 13:58:21.681620 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11458 13:58:21.699167 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11459 13:58:21.720675 [0:03:32.477266582] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11460 13:58:21.771065 Camera needs 4 requests, can't test only 1
11461 13:58:21.871631 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11462 13:58:21.966034
11463 13:58:22.067494 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (53 ms)
11464 13:58:22.184913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11465 13:58:22.185638 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11467 13:58:22.201970 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11468 13:58:22.266030 Camera needs 4 requests, can't test only 2
11469 13:58:22.360511 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11470 13:58:22.459442
11471 13:58:22.567493 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (51 ms)
11472 13:58:22.684643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11473 13:58:22.685379 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11475 13:58:22.702640 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11476 13:58:22.767448 Camera needs 4 requests, can't test only 3
11477 13:58:22.868010 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11478 13:58:22.959528
11479 13:58:23.063472 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (52 ms)
11480 13:58:23.181639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11481 13:58:23.182490 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11483 13:58:23.199317 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11484 13:58:23.792336 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2076 ms)
11485 13:58:23.802751 [0:03:34.554661588] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11486 13:58:23.911220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11487 13:58:23.911982 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11489 13:58:23.927776 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11490 13:58:26.498794 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2707 ms)
11491 13:58:26.508796 [0:03:37.262811883] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11492 13:58:26.620275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11493 13:58:26.621039 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11495 13:58:26.637703 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11496 13:58:30.256472 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3758 ms)
11497 13:58:30.266070 [0:03:41.020050349] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11498 13:58:30.366956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11499 13:58:30.367771 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11501 13:58:30.384888 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11502 13:58:35.693509 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5437 ms)
11503 13:58:35.703205 [0:03:46.457758496] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11504 13:58:35.810418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11505 13:58:35.811146 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11507 13:58:35.829315 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11508 13:58:43.864409 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8171 ms)
11509 13:58:43.873684 [0:03:54.629152040] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11510 13:58:43.981681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11511 13:58:43.981974 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11513 13:58:43.997007 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11514 13:58:56.442517 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12579 ms)
11515 13:58:56.452377 [0:04:07.208746316] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11516 13:58:56.562835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11517 13:58:56.563682 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11519 13:58:56.581251 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11520 13:59:16.161049 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19717 ms)
11521 13:59:16.170212 [0:04:26.925761398] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11522 13:59:16.220246 [0:04:26.978954964] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11523 13:59:16.271815 [0:04:27.030089907] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11524 13:59:16.294430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11525 13:59:16.295186 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11527 13:59:16.313475 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11528 13:59:16.322853 [0:04:27.083060206] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11529 13:59:16.378687 Camera needs 4 requests, can't test only 1
11530 13:59:16.478547 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11531 13:59:16.573573
11532 13:59:16.681275 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (54 ms)
11533 13:59:16.797158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11534 13:59:16.797927 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11536 13:59:16.815636 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11537 13:59:16.876970 Camera needs 4 requests, can't test only 2
11538 13:59:16.976792 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11539 13:59:17.075648
11540 13:59:17.181757 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (53 ms)
11541 13:59:17.295030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11542 13:59:17.295826 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11544 13:59:17.311452 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11545 13:59:17.377002 Camera needs 4 requests, can't test only 3
11546 13:59:17.473887 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11547 13:59:17.563907
11548 13:59:17.666395 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (53 ms)
11549 13:59:17.787011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11550 13:59:17.787796 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11552 13:59:17.802407 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11553 13:59:18.397123 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2076 ms)
11554 13:59:18.406671 [0:04:29.160081386] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11555 13:59:18.514079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11556 13:59:18.514817 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11558 13:59:18.530422 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11559 13:59:21.107527 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2710 ms)
11560 13:59:21.117433 [0:04:31.872098271] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11561 13:59:21.225655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11562 13:59:21.226502 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11564 13:59:21.243928 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11565 13:59:24.864455 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3756 ms)
11566 13:59:24.874835 [0:04:35.629268515] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11567 13:59:24.986615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11568 13:59:24.987464 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11570 13:59:25.004765 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11571 13:59:30.302415 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5438 ms)
11572 13:59:30.312662 [0:04:41.067203202] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11573 13:59:30.403485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11574 13:59:30.403789 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11576 13:59:30.417492 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11577 13:59:38.471339 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8169 ms)
11578 13:59:38.480822 [0:04:49.235098170] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11579 13:59:38.571445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11580 13:59:38.571747 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11582 13:59:38.585267 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11583 13:59:51.049572 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12577 ms)
11584 13:59:51.058559 [0:05:01.813949443] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11585 13:59:51.150064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11586 13:59:51.150357 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11588 13:59:51.164038 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11589 14:00:10.769338 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19720 ms)
11590 14:00:10.779134 [0:05:21.533217382] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11591 14:00:10.869092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11592 14:00:10.869413 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11594 14:00:10.883826 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11595 14:00:11.181842 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (416 ms)
11596 14:00:11.194687 [0:05:21.947584423] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11597 14:00:11.275278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11598 14:00:11.275648 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11600 14:00:11.295500 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11601 14:00:11.668391 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (487 ms)
11602 14:00:11.681516 [0:05:22.434064380] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11603 14:00:11.764588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11604 14:00:11.764911 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11606 14:00:11.781531 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11607 14:00:12.223561 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (554 ms)
11608 14:00:12.236224 [0:05:22.988646679] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11609 14:00:12.344492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11610 14:00:12.345163 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11612 14:00:12.363678 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11613 14:00:12.918111 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (695 ms)
11614 14:00:12.931355 [0:05:23.683625530] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11615 14:00:13.039479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11616 14:00:13.040258 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11618 14:00:13.059344 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11619 14:00:13.823547 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (905 ms)
11620 14:00:13.835878 [0:05:24.588766924] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11621 14:00:13.921925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11622 14:00:13.922354 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11624 14:00:13.940232 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11625 14:00:15.078161 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1254 ms)
11626 14:00:15.091029 [0:05:25.843454643] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11627 14:00:15.194148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11628 14:00:15.194884 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11630 14:00:15.215113 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11631 14:00:16.892946 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1815 ms)
11632 14:00:16.905823 [0:05:27.657757144] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11633 14:00:17.019354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11634 14:00:17.020140 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11636 14:00:17.038842 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11637 14:00:19.616938 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2724 ms)
11638 14:00:19.629853 [0:05:30.383542346] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11639 14:00:19.737001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11640 14:00:19.737734 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11642 14:00:19.758005 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11643 14:00:23.812366 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4196 ms)
11644 14:00:23.825025 [0:05:34.579218001] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11645 14:00:23.912499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11646 14:00:23.912793 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11648 14:00:23.929266 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11649 14:00:30.387034 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6575 ms)
11650 14:00:30.400484 [0:05:41.154999298] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11651 14:00:30.485742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11652 14:00:30.486034 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11654 14:00:30.503128 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11655 14:00:30.806184 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (416 ms)
11656 14:00:30.815793 [0:05:41.569088690] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11657 14:00:30.907485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11658 14:00:30.907774 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11660 14:00:30.919568 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11661 14:00:31.292677 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (486 ms)
11662 14:00:31.302789 [0:05:42.055801518] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11663 14:00:31.387145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11664 14:00:31.387409 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11666 14:00:31.400722 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11667 14:00:31.847107 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (555 ms)
11668 14:00:31.857078 [0:05:42.611111056] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11669 14:00:31.947510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11670 14:00:31.947794 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11672 14:00:31.961297 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11673 14:00:32.543710 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (697 ms)
11674 14:00:32.553469 [0:05:43.307744499] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11675 14:00:32.648237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11676 14:00:32.648519 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11678 14:00:32.662919 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11679 14:00:33.451114 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (907 ms)
11680 14:00:33.460675 [0:05:44.215232515] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11681 14:00:33.550446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11682 14:00:33.550732 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11684 14:00:33.562934 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11685 14:00:34.707315 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1256 ms)
11686 14:00:34.717530 [0:05:45.471852438] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11687 14:00:34.806006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11688 14:00:34.806292 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11690 14:00:34.821896 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11691 14:00:36.524447 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1816 ms)
11692 14:00:36.534103 [0:05:47.288618854] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11693 14:00:36.626991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11694 14:00:36.627284 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11696 14:00:36.640515 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11697 14:00:39.252215 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2727 ms)
11698 14:00:39.261690 [0:05:50.015256683] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11699 14:00:39.375465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11700 14:00:39.376211 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11702 14:00:39.393107 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11703 14:00:43.448226 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4196 ms)
11704 14:00:43.458544 [0:05:54.211832949] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11705 14:00:43.567043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11706 14:00:43.567837 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11708 14:00:43.583018 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11709 14:00:50.024809 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6577 ms)
11710 14:00:50.034215 [0:06:00.788408570] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11711 14:00:50.144380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11712 14:00:50.145088 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11714 14:00:50.161299 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11715 14:00:50.441089 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (416 ms)
11716 14:00:50.450426 [0:06:01.205077762] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11717 14:00:50.563865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11718 14:00:50.564570 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11720 14:00:50.581857 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11721 14:00:50.929321 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (487 ms)
11722 14:00:50.938539 [0:06:01.692555157] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11723 14:00:51.052305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11724 14:00:51.053124 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11726 14:00:51.070523 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11727 14:00:51.485354 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (557 ms)
11728 14:00:51.495474 [0:06:02.249532170] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11729 14:00:51.612412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11730 14:00:51.613150 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11732 14:00:51.629866 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11733 14:00:52.181405 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (696 ms)
11734 14:00:52.191255 [0:06:02.945415455] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11735 14:00:52.308361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11736 14:00:52.309108 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11738 14:00:52.324905 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11739 14:00:53.089651 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (908 ms)
11740 14:00:53.099507 [0:06:03.854817588] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11741 14:00:53.211921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11742 14:00:53.212699 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11744 14:00:53.231484 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11745 14:00:54.345484 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1256 ms)
11746 14:00:54.355319 [0:06:05.110601448] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11747 14:00:54.464357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11748 14:00:54.465102 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11750 14:00:54.484336 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11751 14:00:56.161379 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1815 ms)
11752 14:00:56.171049 [0:06:06.925851606] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11753 14:00:56.276704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11754 14:00:56.277441 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11756 14:00:56.294055 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11757 14:00:58.888715 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2728 ms)
11758 14:00:58.898118 [0:06:09.653259148] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11759 14:00:58.995950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11760 14:00:58.996260 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11762 14:00:59.010113 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11763 14:01:03.084157 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4195 ms)
11764 14:01:03.094384 [0:06:13.848947042] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11765 14:01:03.202857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11766 14:01:03.203614 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11768 14:01:03.220011 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11769 14:01:09.659294 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6575 ms)
11770 14:01:09.669463 [0:06:20.423967639] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11771 14:01:09.767537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11772 14:01:09.768257 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11774 14:01:09.786640 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11775 14:01:10.073858 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (414 ms)
11776 14:01:10.084087 [0:06:20.838697633] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11777 14:01:10.177579 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11779 14:01:10.181288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11780 14:01:10.196862 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11781 14:01:10.560409 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (486 ms)
11782 14:01:10.569533 [0:06:21.324298829] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11783 14:01:10.677677 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11785 14:01:10.680480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11786 14:01:10.695974 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11787 14:01:11.114431 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (554 ms)
11788 14:01:11.124422 [0:06:21.879158882] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11789 14:01:11.237583 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11791 14:01:11.240297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11792 14:01:11.257953 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11793 14:01:11.809576 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (695 ms)
11794 14:01:11.819669 [0:06:22.574385709] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11795 14:01:11.921142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11796 14:01:11.922099 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11798 14:01:11.940940 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11799 14:01:12.716372 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (907 ms)
11800 14:01:12.726039 [0:06:23.481117338] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11801 14:01:12.815392 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11803 14:01:12.818713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11804 14:01:12.833653 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11805 14:01:13.971520 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1255 ms)
11806 14:01:13.982322 [0:06:24.736516504] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11807 14:01:14.079728 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11809 14:01:14.082639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11810 14:01:14.102327 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11811 14:01:15.787589 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1815 ms)
11812 14:01:15.797277 [0:06:26.551641140] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11813 14:01:15.889324 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11815 14:01:15.891952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11816 14:01:15.909242 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11817 14:01:18.513182 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2727 ms)
11818 14:01:18.523956 [0:06:29.278894828] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11819 14:01:18.618954 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11821 14:01:18.621188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11822 14:01:18.635242 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11823 14:01:22.709357 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4196 ms)
11824 14:01:22.719229 [0:06:33.474330333] [403] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11825 14:01:22.815378 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11827 14:01:22.818928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11828 14:01:22.833690 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11829 14:01:29.285365 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6576 ms)
11830 14:01:29.400277 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11832 14:01:29.403081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11833 14:01:29.422589 [----------] 120 tests from CaptureTests/SingleStream (370257 ms total)
11834 14:01:29.516884
11835 14:01:29.616460 [----------] Global test environment tear-down
11836 14:01:29.718590 [==========] 120 tests from 1 test suite ran. (370257 ms total)
11837 14:01:29.825275 <LAVA_SIGNAL_TESTSET STOP>
11838 14:01:29.826059 Received signal: <TESTSET> STOP
11839 14:01:29.826434 Closing test_set CaptureTests/SingleStream
11840 14:01:29.837266 + set +x
11841 14:01:29.840779 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12682921_1.6.2.3.1>
11842 14:01:29.841451 Received signal: <ENDRUN> 0_lc-compliance 12682921_1.6.2.3.1
11843 14:01:29.841843 Ending use of test pattern.
11844 14:01:29.842163 Ending test lava.0_lc-compliance (12682921_1.6.2.3.1), duration 372.09
11846 14:01:29.844142 <LAVA_TEST_RUNNER EXIT>
11847 14:01:29.844812 ok: lava_test_shell seems to have completed
11848 14:01:29.854103 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11849 14:01:29.855128 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11850 14:01:29.855619 end: 3 lava-test-retry (duration 00:06:13) [common]
11851 14:01:29.856072 start: 4 finalize (timeout 00:10:00) [common]
11852 14:01:29.856526 start: 4.1 power-off (timeout 00:00:30) [common]
11853 14:01:29.857257 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11854 14:01:29.942712 >> Command sent successfully.
11855 14:01:29.947464 Returned 0 in 0 seconds
11856 14:01:30.048439 end: 4.1 power-off (duration 00:00:00) [common]
11858 14:01:30.049846 start: 4.2 read-feedback (timeout 00:10:00) [common]
11859 14:01:30.051042 Listened to connection for namespace 'common' for up to 1s
11860 14:01:31.051675 Finalising connection for namespace 'common'
11861 14:01:31.052285 Disconnecting from shell: Finalise
11862 14:01:31.052669 / #
11863 14:01:31.153637 end: 4.2 read-feedback (duration 00:00:01) [common]
11864 14:01:31.154454 end: 4 finalize (duration 00:00:01) [common]
11865 14:01:31.155028 Cleaning after the job
11866 14:01:31.155539 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/ramdisk
11867 14:01:31.166708 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/kernel
11868 14:01:31.204874 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/dtb
11869 14:01:31.205192 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/nfsrootfs
11870 14:01:31.266429 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682921/tftp-deploy-7hfvud89/modules
11871 14:01:31.273885 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682921
11872 14:01:31.592013 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682921
11873 14:01:31.592193 Job finished correctly