Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 16
- Kernel Errors: 30
1 13:56:29.274311 lava-dispatcher, installed at version: 2023.10
2 13:56:29.274508 start: 0 validate
3 13:56:29.274678 Start time: 2024-02-01 13:56:29.274670+00:00 (UTC)
4 13:56:29.274796 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:56:29.274928 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:56:29.559299 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:56:29.559474 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:56:29.817153 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:56:29.817334 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:56:30.090311 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:56:30.090470 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:56:30.357477 validate duration: 1.08
14 13:56:30.357819 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:56:30.357961 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:56:30.358067 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:56:30.358197 Not decompressing ramdisk as can be used compressed.
18 13:56:30.358282 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 13:56:30.358348 saving as /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/ramdisk/rootfs.cpio.gz
20 13:56:30.358411 total size: 26246609 (25 MB)
21 13:56:30.359427 progress 0 % (0 MB)
22 13:56:30.366291 progress 5 % (1 MB)
23 13:56:30.372887 progress 10 % (2 MB)
24 13:56:30.379624 progress 15 % (3 MB)
25 13:56:30.386335 progress 20 % (5 MB)
26 13:56:30.392983 progress 25 % (6 MB)
27 13:56:30.399590 progress 30 % (7 MB)
28 13:56:30.406248 progress 35 % (8 MB)
29 13:56:30.412864 progress 40 % (10 MB)
30 13:56:30.419495 progress 45 % (11 MB)
31 13:56:30.426123 progress 50 % (12 MB)
32 13:56:30.432789 progress 55 % (13 MB)
33 13:56:30.439434 progress 60 % (15 MB)
34 13:56:30.446082 progress 65 % (16 MB)
35 13:56:30.452631 progress 70 % (17 MB)
36 13:56:30.459199 progress 75 % (18 MB)
37 13:56:30.465849 progress 80 % (20 MB)
38 13:56:30.472525 progress 85 % (21 MB)
39 13:56:30.479110 progress 90 % (22 MB)
40 13:56:30.485634 progress 95 % (23 MB)
41 13:56:30.492201 progress 100 % (25 MB)
42 13:56:30.492567 25 MB downloaded in 0.13 s (186.58 MB/s)
43 13:56:30.492732 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:56:30.492972 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:56:30.493058 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:56:30.493143 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:56:30.493276 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:56:30.493347 saving as /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/kernel/Image
50 13:56:30.493407 total size: 51532288 (49 MB)
51 13:56:30.493467 No compression specified
52 13:56:30.494592 progress 0 % (0 MB)
53 13:56:30.507428 progress 5 % (2 MB)
54 13:56:30.520377 progress 10 % (4 MB)
55 13:56:30.533187 progress 15 % (7 MB)
56 13:56:30.546213 progress 20 % (9 MB)
57 13:56:30.559080 progress 25 % (12 MB)
58 13:56:30.571830 progress 30 % (14 MB)
59 13:56:30.584821 progress 35 % (17 MB)
60 13:56:30.597995 progress 40 % (19 MB)
61 13:56:30.610803 progress 45 % (22 MB)
62 13:56:30.623749 progress 50 % (24 MB)
63 13:56:30.636556 progress 55 % (27 MB)
64 13:56:30.649580 progress 60 % (29 MB)
65 13:56:30.662426 progress 65 % (31 MB)
66 13:56:30.675240 progress 70 % (34 MB)
67 13:56:30.688200 progress 75 % (36 MB)
68 13:56:30.701250 progress 80 % (39 MB)
69 13:56:30.714074 progress 85 % (41 MB)
70 13:56:30.727080 progress 90 % (44 MB)
71 13:56:30.740233 progress 95 % (46 MB)
72 13:56:30.753141 progress 100 % (49 MB)
73 13:56:30.753352 49 MB downloaded in 0.26 s (189.06 MB/s)
74 13:56:30.753504 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:56:30.753737 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:56:30.753827 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:56:30.753914 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:56:30.754082 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:56:30.754152 saving as /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/dtb/mt8192-asurada-spherion-r0.dtb
81 13:56:30.754214 total size: 47278 (0 MB)
82 13:56:30.754276 No compression specified
83 13:56:30.755358 progress 69 % (0 MB)
84 13:56:30.755625 progress 100 % (0 MB)
85 13:56:30.755784 0 MB downloaded in 0.00 s (28.76 MB/s)
86 13:56:30.755906 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:56:30.756126 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:56:30.756210 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:56:30.756292 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:56:30.756402 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:56:30.756469 saving as /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/modules/modules.tar
93 13:56:30.756529 total size: 8623988 (8 MB)
94 13:56:30.756614 Using unxz to decompress xz
95 13:56:30.760074 progress 0 % (0 MB)
96 13:56:30.780952 progress 5 % (0 MB)
97 13:56:30.804685 progress 10 % (0 MB)
98 13:56:30.828315 progress 15 % (1 MB)
99 13:56:30.852731 progress 20 % (1 MB)
100 13:56:30.878090 progress 25 % (2 MB)
101 13:56:30.906962 progress 30 % (2 MB)
102 13:56:30.933469 progress 35 % (2 MB)
103 13:56:30.956792 progress 40 % (3 MB)
104 13:56:30.980817 progress 45 % (3 MB)
105 13:56:31.006108 progress 50 % (4 MB)
106 13:56:31.030070 progress 55 % (4 MB)
107 13:56:31.054644 progress 60 % (4 MB)
108 13:56:31.081709 progress 65 % (5 MB)
109 13:56:31.106570 progress 70 % (5 MB)
110 13:56:31.129832 progress 75 % (6 MB)
111 13:56:31.156408 progress 80 % (6 MB)
112 13:56:31.181498 progress 85 % (7 MB)
113 13:56:31.206394 progress 90 % (7 MB)
114 13:56:31.237789 progress 95 % (7 MB)
115 13:56:31.265674 progress 100 % (8 MB)
116 13:56:31.270563 8 MB downloaded in 0.51 s (16.00 MB/s)
117 13:56:31.270808 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:56:31.271063 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:56:31.271157 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:56:31.271254 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:56:31.271334 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:56:31.271423 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:56:31.271637 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m
125 13:56:31.271765 makedir: /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin
126 13:56:31.271868 makedir: /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/tests
127 13:56:31.271963 makedir: /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/results
128 13:56:31.272078 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-add-keys
129 13:56:31.272225 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-add-sources
130 13:56:31.272356 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-background-process-start
131 13:56:31.272484 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-background-process-stop
132 13:56:31.272605 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-common-functions
133 13:56:31.272725 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-echo-ipv4
134 13:56:31.272847 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-install-packages
135 13:56:31.272966 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-installed-packages
136 13:56:31.273084 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-os-build
137 13:56:31.273203 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-probe-channel
138 13:56:31.273321 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-probe-ip
139 13:56:31.273440 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-target-ip
140 13:56:31.273558 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-target-mac
141 13:56:31.273677 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-target-storage
142 13:56:31.273800 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-test-case
143 13:56:31.273919 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-test-event
144 13:56:31.274045 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-test-feedback
145 13:56:31.274164 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-test-raise
146 13:56:31.274283 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-test-reference
147 13:56:31.274402 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-test-runner
148 13:56:31.274520 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-test-set
149 13:56:31.274641 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-test-shell
150 13:56:31.274763 Updating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-install-packages (oe)
151 13:56:31.274904 Updating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/bin/lava-installed-packages (oe)
152 13:56:31.275027 Creating /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/environment
153 13:56:31.275129 LAVA metadata
154 13:56:31.275204 - LAVA_JOB_ID=12682956
155 13:56:31.275270 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:56:31.275371 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:56:31.275438 skipped lava-vland-overlay
158 13:56:31.275513 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:56:31.275592 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:56:31.275656 skipped lava-multinode-overlay
161 13:56:31.275732 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:56:31.275815 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:56:31.275890 Loading test definitions
164 13:56:31.275979 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:56:31.276053 Using /lava-12682956 at stage 0
166 13:56:31.276334 uuid=12682956_1.5.2.3.1 testdef=None
167 13:56:31.276421 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:56:31.276509 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:56:31.277013 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:56:31.277233 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:56:31.277842 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:56:31.278111 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:56:31.278683 runner path: /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12682956_1.5.2.3.1
176 13:56:31.278833 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:56:31.279042 Creating lava-test-runner.conf files
179 13:56:31.279106 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682956/lava-overlay-892yzo6m/lava-12682956/0 for stage 0
180 13:56:31.279192 - 0_v4l2-compliance-mtk-vcodec-enc
181 13:56:31.279305 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:56:31.279438 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:56:31.285945 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:56:31.286084 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:56:31.286173 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:56:31.286263 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:56:31.286353 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:56:31.962970 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:56:31.963328 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:56:31.963446 extracting modules file /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682956/extract-overlay-ramdisk-yojli4es/ramdisk
191 13:56:32.170554 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:56:32.170725 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:56:32.170827 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682956/compress-overlay-rifkm_j8/overlay-1.5.2.4.tar.gz to ramdisk
194 13:56:32.170899 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682956/compress-overlay-rifkm_j8/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682956/extract-overlay-ramdisk-yojli4es/ramdisk
195 13:56:32.177167 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:56:32.177280 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:56:32.177374 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:56:32.177468 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:56:32.177546 Building ramdisk /var/lib/lava/dispatcher/tmp/12682956/extract-overlay-ramdisk-yojli4es/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682956/extract-overlay-ramdisk-yojli4es/ramdisk
200 13:56:32.747464 >> 228443 blocks
201 13:56:36.635302 rename /var/lib/lava/dispatcher/tmp/12682956/extract-overlay-ramdisk-yojli4es/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/ramdisk/ramdisk.cpio.gz
202 13:56:36.635793 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 13:56:36.635986 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 13:56:36.636140 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 13:56:36.636308 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/kernel/Image'
206 13:56:49.060512 Returned 0 in 12 seconds
207 13:56:49.161419 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/kernel/image.itb
208 13:56:49.751228 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:56:49.751580 output: Created: Thu Feb 1 13:56:49 2024
210 13:56:49.751684 output: Image 0 (kernel-1)
211 13:56:49.751772 output: Description:
212 13:56:49.751859 output: Created: Thu Feb 1 13:56:49 2024
213 13:56:49.751944 output: Type: Kernel Image
214 13:56:49.752027 output: Compression: lzma compressed
215 13:56:49.752107 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
216 13:56:49.752206 output: Architecture: AArch64
217 13:56:49.752305 output: OS: Linux
218 13:56:49.752404 output: Load Address: 0x00000000
219 13:56:49.752501 output: Entry Point: 0x00000000
220 13:56:49.752595 output: Hash algo: crc32
221 13:56:49.752692 output: Hash value: 5aa40db2
222 13:56:49.752788 output: Image 1 (fdt-1)
223 13:56:49.752883 output: Description: mt8192-asurada-spherion-r0
224 13:56:49.752977 output: Created: Thu Feb 1 13:56:49 2024
225 13:56:49.753071 output: Type: Flat Device Tree
226 13:56:49.753165 output: Compression: uncompressed
227 13:56:49.753258 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:56:49.753351 output: Architecture: AArch64
229 13:56:49.753444 output: Hash algo: crc32
230 13:56:49.753537 output: Hash value: cc4352de
231 13:56:49.753629 output: Image 2 (ramdisk-1)
232 13:56:49.753721 output: Description: unavailable
233 13:56:49.753814 output: Created: Thu Feb 1 13:56:49 2024
234 13:56:49.753906 output: Type: RAMDisk Image
235 13:56:49.754046 output: Compression: Unknown Compression
236 13:56:49.754141 output: Data Size: 39372104 Bytes = 38449.32 KiB = 37.55 MiB
237 13:56:49.754235 output: Architecture: AArch64
238 13:56:49.754328 output: OS: Linux
239 13:56:49.754421 output: Load Address: unavailable
240 13:56:49.754514 output: Entry Point: unavailable
241 13:56:49.754607 output: Hash algo: crc32
242 13:56:49.754699 output: Hash value: 41d91d2a
243 13:56:49.754791 output: Default Configuration: 'conf-1'
244 13:56:49.754883 output: Configuration 0 (conf-1)
245 13:56:49.754976 output: Description: mt8192-asurada-spherion-r0
246 13:56:49.755068 output: Kernel: kernel-1
247 13:56:49.755160 output: Init Ramdisk: ramdisk-1
248 13:56:49.755252 output: FDT: fdt-1
249 13:56:49.755344 output: Loadables: kernel-1
250 13:56:49.755436 output:
251 13:56:49.755670 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 13:56:49.755813 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 13:56:49.755962 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 13:56:49.756098 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 13:56:49.756215 No LXC device requested
256 13:56:49.756341 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:56:49.756470 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 13:56:49.756589 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:56:49.756697 Checking files for TFTP limit of 4294967296 bytes.
260 13:56:49.757348 end: 1 tftp-deploy (duration 00:00:19) [common]
261 13:56:49.757492 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:56:49.757626 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:56:49.757801 substitutions:
264 13:56:49.757901 - {DTB}: 12682956/tftp-deploy-melxan2z/dtb/mt8192-asurada-spherion-r0.dtb
265 13:56:49.757998 - {INITRD}: 12682956/tftp-deploy-melxan2z/ramdisk/ramdisk.cpio.gz
266 13:56:49.758079 - {KERNEL}: 12682956/tftp-deploy-melxan2z/kernel/Image
267 13:56:49.758159 - {LAVA_MAC}: None
268 13:56:49.758237 - {PRESEED_CONFIG}: None
269 13:56:49.758315 - {PRESEED_LOCAL}: None
270 13:56:49.758411 - {RAMDISK}: 12682956/tftp-deploy-melxan2z/ramdisk/ramdisk.cpio.gz
271 13:56:49.758508 - {ROOT_PART}: None
272 13:56:49.758604 - {ROOT}: None
273 13:56:49.758702 - {SERVER_IP}: 192.168.201.1
274 13:56:49.758798 - {TEE}: None
275 13:56:49.758895 Parsed boot commands:
276 13:56:49.758991 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:56:49.759224 Parsed boot commands: tftpboot 192.168.201.1 12682956/tftp-deploy-melxan2z/kernel/image.itb 12682956/tftp-deploy-melxan2z/kernel/cmdline
278 13:56:49.759353 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:56:49.759487 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:56:49.759625 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:56:49.759751 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:56:49.759861 Not connected, no need to disconnect.
283 13:56:49.759979 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:56:49.760106 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:56:49.760209 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 13:56:49.763714 Setting prompt string to ['lava-test: # ']
287 13:56:49.764078 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:56:49.764226 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:56:49.764341 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:56:49.764454 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:56:49.764764 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 13:56:54.913002 >> Command sent successfully.
293 13:56:54.923857 Returned 0 in 5 seconds
294 13:56:55.025258 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:56:55.026969 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:56:55.027619 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:56:55.028167 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:56:55.028614 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:56:55.029139 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:56:55.030623 [Enter `^Ec?' for help]
302 13:56:55.188746
303 13:56:55.189356
304 13:56:55.189864 F0: 102B 0000
305 13:56:55.190420
306 13:56:55.190872 F3: 1001 0000 [0200]
307 13:56:55.192701
308 13:56:55.193202 F3: 1001 0000
309 13:56:55.193693
310 13:56:55.194237 F7: 102D 0000
311 13:56:55.194697
312 13:56:55.195825 F1: 0000 0000
313 13:56:55.196318
314 13:56:55.196805 V0: 0000 0000 [0001]
315 13:56:55.197405
316 13:56:55.198940 00: 0007 8000
317 13:56:55.199460
318 13:56:55.199955 01: 0000 0000
319 13:56:55.200434
320 13:56:55.202255 BP: 0C00 0209 [0000]
321 13:56:55.202749
322 13:56:55.203236 G0: 1182 0000
323 13:56:55.203658
324 13:56:55.205919 EC: 0000 0021 [4000]
325 13:56:55.206425
326 13:56:55.206876 S7: 0000 0000 [0000]
327 13:56:55.207300
328 13:56:55.209469 CC: 0000 0000 [0001]
329 13:56:55.209915
330 13:56:55.210401 T0: 0000 0040 [010F]
331 13:56:55.210824
332 13:56:55.211238 Jump to BL
333 13:56:55.211739
334 13:56:55.236146
335 13:56:55.236696
336 13:56:55.237156
337 13:56:55.243205 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:56:55.247191 ARM64: Exception handlers installed.
339 13:56:55.250883 ARM64: Testing exception
340 13:56:55.254133 ARM64: Done test exception
341 13:56:55.261085 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:56:55.271348 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:56:55.278133 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:56:55.287849 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:56:55.294393 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:56:55.301516 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:56:55.312764 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:56:55.319529 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:56:55.339054 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:56:55.342323 WDT: Last reset was cold boot
351 13:56:55.345537 SPI1(PAD0) initialized at 2873684 Hz
352 13:56:55.349116 SPI5(PAD0) initialized at 992727 Hz
353 13:56:55.352575 VBOOT: Loading verstage.
354 13:56:55.359047 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:56:55.362569 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:56:55.366066 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:56:55.368736 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:56:55.376387 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:56:55.382872 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:56:55.393905 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 13:56:55.394452
362 13:56:55.394827
363 13:56:55.404197 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:56:55.407472 ARM64: Exception handlers installed.
365 13:56:55.410490 ARM64: Testing exception
366 13:56:55.410918 ARM64: Done test exception
367 13:56:55.417293 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:56:55.420915 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:56:55.434879 Probing TPM: . done!
370 13:56:55.435517 TPM ready after 0 ms
371 13:56:55.441984 Connected to device vid:did:rid of 1ae0:0028:00
372 13:56:55.448635 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 13:56:55.452348 Initialized TPM device CR50 revision 0
374 13:56:55.518237 tlcl_send_startup: Startup return code is 0
375 13:56:55.519158 TPM: setup succeeded
376 13:56:55.529021 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:56:55.538210 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:56:55.548299 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:56:55.557674 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:56:55.560566 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:56:55.569073 in-header: 03 07 00 00 08 00 00 00
382 13:56:55.572805 in-data: aa e4 47 04 13 02 00 00
383 13:56:55.575907 Chrome EC: UHEPI supported
384 13:56:55.583475 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:56:55.587075 in-header: 03 ad 00 00 08 00 00 00
386 13:56:55.590519 in-data: 00 20 20 08 00 00 00 00
387 13:56:55.591041 Phase 1
388 13:56:55.594194 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:56:55.602093 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:56:55.606289 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:56:55.610006 Recovery requested (1009000e)
392 13:56:55.618317 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:56:55.623507 tlcl_extend: response is 0
394 13:56:55.633475 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:56:55.638543 tlcl_extend: response is 0
396 13:56:55.645301 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:56:55.666426 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 13:56:55.673259 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:56:55.673742
400 13:56:55.674238
401 13:56:55.682976 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:56:55.686350 ARM64: Exception handlers installed.
403 13:56:55.686883 ARM64: Testing exception
404 13:56:55.690005 ARM64: Done test exception
405 13:56:55.711696 pmic_efuse_setting: Set efuses in 11 msecs
406 13:56:55.714905 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:56:55.722024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:56:55.725390 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:56:55.728938 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:56:55.735586 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:56:55.739209 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:56:55.743352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:56:55.750422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:56:55.753874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:56:55.757488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:56:55.764893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:56:55.768642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:56:55.772154 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:56:55.775466 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:56:55.782547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:56:55.789611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:56:55.796528 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:56:55.800170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:56:55.807357 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:56:55.810886 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:56:55.817763 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:56:55.821057 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:56:55.828469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:56:55.834953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:56:55.838159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:56:55.845197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:56:55.851597 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:56:55.855176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:56:55.861714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:56:55.864912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:56:55.868618 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:56:55.875039 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:56:55.881784 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:56:55.885311 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:56:55.891448 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:56:55.894854 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:56:55.901794 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:56:55.905184 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:56:55.911450 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:56:55.915027 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:56:55.918802 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:56:55.922463 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:56:55.929684 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:56:55.933087 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:56:55.936181 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:56:55.939662 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:56:55.946497 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:56:55.949617 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:56:55.953359 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:56:55.960102 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:56:55.963382 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:56:55.966695 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:56:55.973395 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:56:55.983289 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:56:55.986567 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:56:55.993744 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:56:56.005066 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:56:56.008924 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:56:56.012320 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:56:56.016107 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:56:56.025021 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2f
467 13:56:56.028570 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:56:56.036365 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 13:56:56.039480 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:56:56.049205 [RTC]rtc_get_frequency_meter,154: input=15, output=771
471 13:56:56.058298 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 13:56:56.067692 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 13:56:56.077274 [RTC]rtc_get_frequency_meter,154: input=17, output=819
474 13:56:56.086610 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 13:56:56.090207 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 13:56:56.096643 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 13:56:56.099857 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 13:56:56.103052 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 13:56:56.106259 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 13:56:56.110486 ADC[4]: Raw value=902876 ID=7
481 13:56:56.113841 ADC[3]: Raw value=213179 ID=1
482 13:56:56.114600 RAM Code: 0x71
483 13:56:56.118232 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 13:56:56.125153 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 13:56:56.132979 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 13:56:56.139856 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 13:56:56.142559 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 13:56:56.146147 in-header: 03 07 00 00 08 00 00 00
489 13:56:56.149706 in-data: aa e4 47 04 13 02 00 00
490 13:56:56.152812 Chrome EC: UHEPI supported
491 13:56:56.159628 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 13:56:56.163453 in-header: 03 ed 00 00 08 00 00 00
493 13:56:56.166259 in-data: 80 20 60 08 00 00 00 00
494 13:56:56.169847 MRC: failed to locate region type 0.
495 13:56:56.176319 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 13:56:56.179373 DRAM-K: Running full calibration
497 13:56:56.182821 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 13:56:56.186055 header.status = 0x0
499 13:56:56.189603 header.version = 0x6 (expected: 0x6)
500 13:56:56.192732 header.size = 0xd00 (expected: 0xd00)
501 13:56:56.196571 header.flags = 0x0
502 13:56:56.199762 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 13:56:56.218446 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
504 13:56:56.225087 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 13:56:56.228572 dram_init: ddr_geometry: 2
506 13:56:56.229152 [EMI] MDL number = 2
507 13:56:56.231556 [EMI] Get MDL freq = 0
508 13:56:56.235353 dram_init: ddr_type: 0
509 13:56:56.235832 is_discrete_lpddr4: 1
510 13:56:56.238379 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 13:56:56.238856
512 13:56:56.239233
513 13:56:56.241569 [Bian_co] ETT version 0.0.0.1
514 13:56:56.248321 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 13:56:56.249036
516 13:56:56.252012 dramc_set_vcore_voltage set vcore to 650000
517 13:56:56.252514 Read voltage for 800, 4
518 13:56:56.254939 Vio18 = 0
519 13:56:56.255604 Vcore = 650000
520 13:56:56.256028 Vdram = 0
521 13:56:56.258191 Vddq = 0
522 13:56:56.258756 Vmddr = 0
523 13:56:56.261646 dram_init: config_dvfs: 1
524 13:56:56.265603 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 13:56:56.271623 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 13:56:56.275059 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
527 13:56:56.278495 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
528 13:56:56.281585 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 13:56:56.285274 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 13:56:56.288744 MEM_TYPE=3, freq_sel=18
531 13:56:56.291578 sv_algorithm_assistance_LP4_1600
532 13:56:56.295071 ============ PULL DRAM RESETB DOWN ============
533 13:56:56.298574 ========== PULL DRAM RESETB DOWN end =========
534 13:56:56.305604 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 13:56:56.308784 ===================================
536 13:56:56.309387 LPDDR4 DRAM CONFIGURATION
537 13:56:56.311783 ===================================
538 13:56:56.315241 EX_ROW_EN[0] = 0x0
539 13:56:56.318498 EX_ROW_EN[1] = 0x0
540 13:56:56.318993 LP4Y_EN = 0x0
541 13:56:56.321453 WORK_FSP = 0x0
542 13:56:56.322005 WL = 0x2
543 13:56:56.324891 RL = 0x2
544 13:56:56.325432 BL = 0x2
545 13:56:56.328437 RPST = 0x0
546 13:56:56.328919 RD_PRE = 0x0
547 13:56:56.331772 WR_PRE = 0x1
548 13:56:56.332250 WR_PST = 0x0
549 13:56:56.334841 DBI_WR = 0x0
550 13:56:56.335279 DBI_RD = 0x0
551 13:56:56.338517 OTF = 0x1
552 13:56:56.341864 ===================================
553 13:56:56.345089 ===================================
554 13:56:56.345526 ANA top config
555 13:56:56.348437 ===================================
556 13:56:56.351879 DLL_ASYNC_EN = 0
557 13:56:56.355458 ALL_SLAVE_EN = 1
558 13:56:56.358538 NEW_RANK_MODE = 1
559 13:56:56.359022 DLL_IDLE_MODE = 1
560 13:56:56.361722 LP45_APHY_COMB_EN = 1
561 13:56:56.365047 TX_ODT_DIS = 1
562 13:56:56.368836 NEW_8X_MODE = 1
563 13:56:56.371781 ===================================
564 13:56:56.375461 ===================================
565 13:56:56.378183 data_rate = 1600
566 13:56:56.378621 CKR = 1
567 13:56:56.382222 DQ_P2S_RATIO = 8
568 13:56:56.384806 ===================================
569 13:56:56.388428 CA_P2S_RATIO = 8
570 13:56:56.391800 DQ_CA_OPEN = 0
571 13:56:56.394707 DQ_SEMI_OPEN = 0
572 13:56:56.395179 CA_SEMI_OPEN = 0
573 13:56:56.398574 CA_FULL_RATE = 0
574 13:56:56.402021 DQ_CKDIV4_EN = 1
575 13:56:56.404913 CA_CKDIV4_EN = 1
576 13:56:56.408159 CA_PREDIV_EN = 0
577 13:56:56.411655 PH8_DLY = 0
578 13:56:56.412107 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 13:56:56.414600 DQ_AAMCK_DIV = 4
580 13:56:56.418387 CA_AAMCK_DIV = 4
581 13:56:56.421456 CA_ADMCK_DIV = 4
582 13:56:56.425057 DQ_TRACK_CA_EN = 0
583 13:56:56.428193 CA_PICK = 800
584 13:56:56.431310 CA_MCKIO = 800
585 13:56:56.431740 MCKIO_SEMI = 0
586 13:56:56.434713 PLL_FREQ = 3068
587 13:56:56.438353 DQ_UI_PI_RATIO = 32
588 13:56:56.442165 CA_UI_PI_RATIO = 0
589 13:56:56.445184 ===================================
590 13:56:56.448586 ===================================
591 13:56:56.451949 memory_type:LPDDR4
592 13:56:56.452492 GP_NUM : 10
593 13:56:56.455182 SRAM_EN : 1
594 13:56:56.455728 MD32_EN : 0
595 13:56:56.458547 ===================================
596 13:56:56.462411 [ANA_INIT] >>>>>>>>>>>>>>
597 13:56:56.466006 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 13:56:56.469772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 13:56:56.473719 ===================================
600 13:56:56.474438 data_rate = 1600,PCW = 0X7600
601 13:56:56.476908 ===================================
602 13:56:56.480510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 13:56:56.487948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 13:56:56.491337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 13:56:56.495070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 13:56:56.501896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 13:56:56.505490 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 13:56:56.506077 [ANA_INIT] flow start
609 13:56:56.508698 [ANA_INIT] PLL >>>>>>>>
610 13:56:56.512040 [ANA_INIT] PLL <<<<<<<<
611 13:56:56.512618 [ANA_INIT] MIDPI >>>>>>>>
612 13:56:56.515403 [ANA_INIT] MIDPI <<<<<<<<
613 13:56:56.518610 [ANA_INIT] DLL >>>>>>>>
614 13:56:56.519094 [ANA_INIT] flow end
615 13:56:56.521794 ============ LP4 DIFF to SE enter ============
616 13:56:56.528822 ============ LP4 DIFF to SE exit ============
617 13:56:56.529354 [ANA_INIT] <<<<<<<<<<<<<
618 13:56:56.531918 [Flow] Enable top DCM control >>>>>
619 13:56:56.535219 [Flow] Enable top DCM control <<<<<
620 13:56:56.538768 Enable DLL master slave shuffle
621 13:56:56.545306 ==============================================================
622 13:56:56.545747 Gating Mode config
623 13:56:56.551896 ==============================================================
624 13:56:56.555002 Config description:
625 13:56:56.565415 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 13:56:56.569006 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 13:56:56.575284 SELPH_MODE 0: By rank 1: By Phase
628 13:56:56.582583 ==============================================================
629 13:56:56.583165 GAT_TRACK_EN = 1
630 13:56:56.585243 RX_GATING_MODE = 2
631 13:56:56.588411 RX_GATING_TRACK_MODE = 2
632 13:56:56.592067 SELPH_MODE = 1
633 13:56:56.595568 PICG_EARLY_EN = 1
634 13:56:56.598718 VALID_LAT_VALUE = 1
635 13:56:56.605065 ==============================================================
636 13:56:56.608809 Enter into Gating configuration >>>>
637 13:56:56.612887 Exit from Gating configuration <<<<
638 13:56:56.613418 Enter into DVFS_PRE_config >>>>>
639 13:56:56.623861 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 13:56:56.627200 Exit from DVFS_PRE_config <<<<<
641 13:56:56.630662 Enter into PICG configuration >>>>
642 13:56:56.634419 Exit from PICG configuration <<<<
643 13:56:56.638371 [RX_INPUT] configuration >>>>>
644 13:56:56.641822 [RX_INPUT] configuration <<<<<
645 13:56:56.645485 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 13:56:56.649405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 13:56:56.656736 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 13:56:56.663640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 13:56:56.670483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:56:56.674032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:56:56.677977 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 13:56:56.681619 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 13:56:56.689318 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 13:56:56.692753 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 13:56:56.696772 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 13:56:56.699853 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 13:56:56.703565 ===================================
658 13:56:56.707527 LPDDR4 DRAM CONFIGURATION
659 13:56:56.710853 ===================================
660 13:56:56.711287 EX_ROW_EN[0] = 0x0
661 13:56:56.714687 EX_ROW_EN[1] = 0x0
662 13:56:56.715233 LP4Y_EN = 0x0
663 13:56:56.718510 WORK_FSP = 0x0
664 13:56:56.718939 WL = 0x2
665 13:56:56.719282 RL = 0x2
666 13:56:56.722122 BL = 0x2
667 13:56:56.722652 RPST = 0x0
668 13:56:56.726351 RD_PRE = 0x0
669 13:56:56.726881 WR_PRE = 0x1
670 13:56:56.729384 WR_PST = 0x0
671 13:56:56.729913 DBI_WR = 0x0
672 13:56:56.733482 DBI_RD = 0x0
673 13:56:56.733914 OTF = 0x1
674 13:56:56.736822 ===================================
675 13:56:56.740793 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 13:56:56.744621 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 13:56:56.751955 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 13:56:56.752400 ===================================
679 13:56:56.755208 LPDDR4 DRAM CONFIGURATION
680 13:56:56.759294 ===================================
681 13:56:56.759737 EX_ROW_EN[0] = 0x10
682 13:56:56.762945 EX_ROW_EN[1] = 0x0
683 13:56:56.763383 LP4Y_EN = 0x0
684 13:56:56.766791 WORK_FSP = 0x0
685 13:56:56.767262 WL = 0x2
686 13:56:56.770262 RL = 0x2
687 13:56:56.770738 BL = 0x2
688 13:56:56.773971 RPST = 0x0
689 13:56:56.774492 RD_PRE = 0x0
690 13:56:56.777342 WR_PRE = 0x1
691 13:56:56.777785 WR_PST = 0x0
692 13:56:56.781500 DBI_WR = 0x0
693 13:56:56.781970 DBI_RD = 0x0
694 13:56:56.784809 OTF = 0x1
695 13:56:56.785249 ===================================
696 13:56:56.791641 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 13:56:56.796916 nWR fixed to 40
698 13:56:56.797400 [ModeRegInit_LP4] CH0 RK0
699 13:56:56.800795 [ModeRegInit_LP4] CH0 RK1
700 13:56:56.805014 [ModeRegInit_LP4] CH1 RK0
701 13:56:56.805483 [ModeRegInit_LP4] CH1 RK1
702 13:56:56.808575 match AC timing 13
703 13:56:56.813016 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 13:56:56.816526 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 13:56:56.819826 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 13:56:56.827263 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 13:56:56.830983 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 13:56:56.831535 [EMI DOE] emi_dcm 0
709 13:56:56.835350 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 13:56:56.836109 ==
711 13:56:56.839127 Dram Type= 6, Freq= 0, CH_0, rank 0
712 13:56:56.842508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 13:56:56.843216 ==
714 13:56:56.850003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 13:56:56.856712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 13:56:56.864124 [CA 0] Center 37 (7~68) winsize 62
717 13:56:56.867882 [CA 1] Center 38 (7~69) winsize 63
718 13:56:56.871252 [CA 2] Center 35 (5~66) winsize 62
719 13:56:56.874874 [CA 3] Center 35 (4~66) winsize 63
720 13:56:56.879024 [CA 4] Center 34 (4~65) winsize 62
721 13:56:56.882758 [CA 5] Center 33 (3~64) winsize 62
722 13:56:56.883219
723 13:56:56.886496 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 13:56:56.886928
725 13:56:56.889871 [CATrainingPosCal] consider 1 rank data
726 13:56:56.893763 u2DelayCellTimex100 = 270/100 ps
727 13:56:56.894258 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
728 13:56:56.897695 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 13:56:56.905042 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 13:56:56.908675 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
731 13:56:56.909210 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 13:56:56.915494 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 13:56:56.916028
734 13:56:56.918455 CA PerBit enable=1, Macro0, CA PI delay=33
735 13:56:56.918884
736 13:56:56.922023 [CBTSetCACLKResult] CA Dly = 33
737 13:56:56.922563 CS Dly: 5 (0~36)
738 13:56:56.922907 ==
739 13:56:56.925247 Dram Type= 6, Freq= 0, CH_0, rank 1
740 13:56:56.928340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 13:56:56.931886 ==
742 13:56:56.935473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 13:56:56.942196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 13:56:56.950882 [CA 0] Center 38 (7~69) winsize 63
745 13:56:56.954282 [CA 1] Center 38 (7~69) winsize 63
746 13:56:56.957173 [CA 2] Center 35 (5~66) winsize 62
747 13:56:56.960687 [CA 3] Center 35 (5~66) winsize 62
748 13:56:56.963946 [CA 4] Center 35 (4~66) winsize 63
749 13:56:56.967397 [CA 5] Center 34 (4~65) winsize 62
750 13:56:56.967903
751 13:56:56.971212 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 13:56:56.971804
753 13:56:56.973998 [CATrainingPosCal] consider 2 rank data
754 13:56:56.977690 u2DelayCellTimex100 = 270/100 ps
755 13:56:56.980800 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
756 13:56:56.984231 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 13:56:56.991192 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
758 13:56:56.994357 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 13:56:56.997372 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 13:56:57.000549 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 13:56:57.000975
762 13:56:57.004593 CA PerBit enable=1, Macro0, CA PI delay=34
763 13:56:57.005121
764 13:56:57.007623 [CBTSetCACLKResult] CA Dly = 34
765 13:56:57.008051 CS Dly: 6 (0~38)
766 13:56:57.008390
767 13:56:57.010629 ----->DramcWriteLeveling(PI) begin...
768 13:56:57.014114 ==
769 13:56:57.014684 Dram Type= 6, Freq= 0, CH_0, rank 0
770 13:56:57.020989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 13:56:57.021527 ==
772 13:56:57.024012 Write leveling (Byte 0): 34 => 34
773 13:56:57.027123 Write leveling (Byte 1): 31 => 31
774 13:56:57.030825 DramcWriteLeveling(PI) end<-----
775 13:56:57.031366
776 13:56:57.031709 ==
777 13:56:57.034232 Dram Type= 6, Freq= 0, CH_0, rank 0
778 13:56:57.037464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 13:56:57.038029 ==
780 13:56:57.041363 [Gating] SW mode calibration
781 13:56:57.048326 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 13:56:57.052266 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 13:56:57.056345 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 13:56:57.059627 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 13:56:57.065883 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 13:56:57.069809 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 13:56:57.073505 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 13:56:57.079900 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:56:57.083558 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:56:57.086742 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:56:57.093436 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:56:57.096494 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:56:57.099932 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:56:57.103028 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:56:57.110129 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:56:57.113038 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:56:57.116689 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:56:57.123493 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:56:57.126701 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 13:56:57.130214 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
801 13:56:57.136684 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:56:57.140081 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
803 13:56:57.143164 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:56:57.150052 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:56:57.153604 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:56:57.156937 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:56:57.163222 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:56:57.166622 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:56:57.170260 0 9 8 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
810 13:56:57.173535 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
811 13:56:57.179937 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 13:56:57.183617 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 13:56:57.186757 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 13:56:57.193335 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:56:57.196595 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:56:57.200008 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
817 13:56:57.207179 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
818 13:56:57.210184 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 13:56:57.214034 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:56:57.220529 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 13:56:57.223867 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:56:57.226942 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:56:57.233663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:56:57.236964 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
825 13:56:57.240534 0 11 8 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
826 13:56:57.244138 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
827 13:56:57.250380 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 13:56:57.253872 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 13:56:57.257426 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:56:57.264226 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:56:57.267224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:56:57.270598 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 13:56:57.277499 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 13:56:57.280399 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 13:56:57.284304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 13:56:57.290449 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:56:57.293743 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:56:57.297103 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:56:57.303805 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:56:57.307497 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:56:57.310507 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:56:57.317287 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:56:57.320801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:56:57.323957 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:56:57.327184 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:56:57.334051 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:56:57.337380 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:56:57.340645 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 13:56:57.347403 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 13:56:57.350451 Total UI for P1: 0, mck2ui 16
851 13:56:57.353872 best dqsien dly found for B0: ( 0, 14, 4)
852 13:56:57.357500 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 13:56:57.360535 Total UI for P1: 0, mck2ui 16
854 13:56:57.364186 best dqsien dly found for B1: ( 0, 14, 8)
855 13:56:57.367244 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
856 13:56:57.370574 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 13:56:57.371157
858 13:56:57.374041 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 13:56:57.377442 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 13:56:57.380438 [Gating] SW calibration Done
861 13:56:57.380915 ==
862 13:56:57.384030 Dram Type= 6, Freq= 0, CH_0, rank 0
863 13:56:57.387615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 13:56:57.390477 ==
865 13:56:57.390958 RX Vref Scan: 0
866 13:56:57.391344
867 13:56:57.394129 RX Vref 0 -> 0, step: 1
868 13:56:57.394625
869 13:56:57.397420 RX Delay -130 -> 252, step: 16
870 13:56:57.400789 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
871 13:56:57.404085 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 13:56:57.407316 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
873 13:56:57.410633 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
874 13:56:57.413813 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
875 13:56:57.420583 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 13:56:57.424185 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 13:56:57.427583 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 13:56:57.431062 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 13:56:57.434133 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
880 13:56:57.440787 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
881 13:56:57.444374 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
882 13:56:57.447251 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
883 13:56:57.450927 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 13:56:57.453986 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 13:56:57.460842 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
886 13:56:57.461274 ==
887 13:56:57.464167 Dram Type= 6, Freq= 0, CH_0, rank 0
888 13:56:57.467740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 13:56:57.468173 ==
890 13:56:57.468513 DQS Delay:
891 13:56:57.471199 DQS0 = 0, DQS1 = 0
892 13:56:57.471801 DQM Delay:
893 13:56:57.474635 DQM0 = 93, DQM1 = 84
894 13:56:57.475112 DQ Delay:
895 13:56:57.477745 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
896 13:56:57.480906 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
897 13:56:57.484978 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =85
898 13:56:57.488022 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
899 13:56:57.488680
900 13:56:57.489033
901 13:56:57.489357 ==
902 13:56:57.490961 Dram Type= 6, Freq= 0, CH_0, rank 0
903 13:56:57.494416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 13:56:57.494901 ==
905 13:56:57.497589
906 13:56:57.498060
907 13:56:57.498413 TX Vref Scan disable
908 13:56:57.500907 == TX Byte 0 ==
909 13:56:57.504598 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
910 13:56:57.507685 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
911 13:56:57.510815 == TX Byte 1 ==
912 13:56:57.514461 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 13:56:57.517496 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 13:56:57.517964 ==
915 13:56:57.521244 Dram Type= 6, Freq= 0, CH_0, rank 0
916 13:56:57.527871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 13:56:57.528432 ==
918 13:56:57.540062 TX Vref=22, minBit 6, minWin=27, winSum=438
919 13:56:57.543222 TX Vref=24, minBit 6, minWin=27, winSum=441
920 13:56:57.546760 TX Vref=26, minBit 8, minWin=27, winSum=445
921 13:56:57.550127 TX Vref=28, minBit 8, minWin=27, winSum=448
922 13:56:57.553568 TX Vref=30, minBit 0, minWin=28, winSum=454
923 13:56:57.556760 TX Vref=32, minBit 8, minWin=27, winSum=451
924 13:56:57.563171 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
925 13:56:57.563751
926 13:56:57.566476 Final TX Range 1 Vref 30
927 13:56:57.566955
928 13:56:57.567333 ==
929 13:56:57.570280 Dram Type= 6, Freq= 0, CH_0, rank 0
930 13:56:57.573211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 13:56:57.573689 ==
932 13:56:57.574096
933 13:56:57.574448
934 13:56:57.576745 TX Vref Scan disable
935 13:56:57.580185 == TX Byte 0 ==
936 13:56:57.583603 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
937 13:56:57.587070 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
938 13:56:57.590111 == TX Byte 1 ==
939 13:56:57.593550 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 13:56:57.596883 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 13:56:57.597521
942 13:56:57.599858 [DATLAT]
943 13:56:57.600355 Freq=800, CH0 RK0
944 13:56:57.600786
945 13:56:57.603225 DATLAT Default: 0xa
946 13:56:57.603757 0, 0xFFFF, sum = 0
947 13:56:57.606674 1, 0xFFFF, sum = 0
948 13:56:57.607169 2, 0xFFFF, sum = 0
949 13:56:57.610002 3, 0xFFFF, sum = 0
950 13:56:57.610519 4, 0xFFFF, sum = 0
951 13:56:57.613795 5, 0xFFFF, sum = 0
952 13:56:57.614432 6, 0xFFFF, sum = 0
953 13:56:57.616526 7, 0xFFFF, sum = 0
954 13:56:57.617031 8, 0xFFFF, sum = 0
955 13:56:57.620261 9, 0x0, sum = 1
956 13:56:57.620824 10, 0x0, sum = 2
957 13:56:57.623443 11, 0x0, sum = 3
958 13:56:57.623924 12, 0x0, sum = 4
959 13:56:57.626697 best_step = 10
960 13:56:57.627219
961 13:56:57.627753 ==
962 13:56:57.630475 Dram Type= 6, Freq= 0, CH_0, rank 0
963 13:56:57.633408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 13:56:57.633993 ==
965 13:56:57.637061 RX Vref Scan: 1
966 13:56:57.637535
967 13:56:57.637912 Set Vref Range= 32 -> 127
968 13:56:57.638309
969 13:56:57.639868 RX Vref 32 -> 127, step: 1
970 13:56:57.640302
971 13:56:57.643713 RX Delay -79 -> 252, step: 8
972 13:56:57.644149
973 13:56:57.647134 Set Vref, RX VrefLevel [Byte0]: 32
974 13:56:57.650469 [Byte1]: 32
975 13:56:57.651160
976 13:56:57.653911 Set Vref, RX VrefLevel [Byte0]: 33
977 13:56:57.657132 [Byte1]: 33
978 13:56:57.660404
979 13:56:57.660989 Set Vref, RX VrefLevel [Byte0]: 34
980 13:56:57.663346 [Byte1]: 34
981 13:56:57.667612
982 13:56:57.668201 Set Vref, RX VrefLevel [Byte0]: 35
983 13:56:57.670925 [Byte1]: 35
984 13:56:57.675084
985 13:56:57.675670 Set Vref, RX VrefLevel [Byte0]: 36
986 13:56:57.678629 [Byte1]: 36
987 13:56:57.682499
988 13:56:57.682974 Set Vref, RX VrefLevel [Byte0]: 37
989 13:56:57.686174 [Byte1]: 37
990 13:56:57.690158
991 13:56:57.693669 Set Vref, RX VrefLevel [Byte0]: 38
992 13:56:57.694181 [Byte1]: 38
993 13:56:57.698059
994 13:56:57.698693 Set Vref, RX VrefLevel [Byte0]: 39
995 13:56:57.701277 [Byte1]: 39
996 13:56:57.705616
997 13:56:57.706145 Set Vref, RX VrefLevel [Byte0]: 40
998 13:56:57.708430 [Byte1]: 40
999 13:56:57.713819
1000 13:56:57.714361 Set Vref, RX VrefLevel [Byte0]: 41
1001 13:56:57.716768 [Byte1]: 41
1002 13:56:57.720860
1003 13:56:57.721313 Set Vref, RX VrefLevel [Byte0]: 42
1004 13:56:57.724187 [Byte1]: 42
1005 13:56:57.728104
1006 13:56:57.728535 Set Vref, RX VrefLevel [Byte0]: 43
1007 13:56:57.731466 [Byte1]: 43
1008 13:56:57.735902
1009 13:56:57.736335 Set Vref, RX VrefLevel [Byte0]: 44
1010 13:56:57.738811 [Byte1]: 44
1011 13:56:57.743071
1012 13:56:57.743625 Set Vref, RX VrefLevel [Byte0]: 45
1013 13:56:57.746396 [Byte1]: 45
1014 13:56:57.750485
1015 13:56:57.750940 Set Vref, RX VrefLevel [Byte0]: 46
1016 13:56:57.753766 [Byte1]: 46
1017 13:56:57.758038
1018 13:56:57.758474 Set Vref, RX VrefLevel [Byte0]: 47
1019 13:56:57.761475 [Byte1]: 47
1020 13:56:57.765712
1021 13:56:57.766330 Set Vref, RX VrefLevel [Byte0]: 48
1022 13:56:57.769578 [Byte1]: 48
1023 13:56:57.773534
1024 13:56:57.774124 Set Vref, RX VrefLevel [Byte0]: 49
1025 13:56:57.776711 [Byte1]: 49
1026 13:56:57.781106
1027 13:56:57.781662 Set Vref, RX VrefLevel [Byte0]: 50
1028 13:56:57.784166 [Byte1]: 50
1029 13:56:57.788484
1030 13:56:57.789019 Set Vref, RX VrefLevel [Byte0]: 51
1031 13:56:57.791460 [Byte1]: 51
1032 13:56:57.795982
1033 13:56:57.796433 Set Vref, RX VrefLevel [Byte0]: 52
1034 13:56:57.799077 [Byte1]: 52
1035 13:56:57.803482
1036 13:56:57.804026 Set Vref, RX VrefLevel [Byte0]: 53
1037 13:56:57.806741 [Byte1]: 53
1038 13:56:57.810833
1039 13:56:57.811264 Set Vref, RX VrefLevel [Byte0]: 54
1040 13:56:57.814025 [Byte1]: 54
1041 13:56:57.818827
1042 13:56:57.819363 Set Vref, RX VrefLevel [Byte0]: 55
1043 13:56:57.821975 [Byte1]: 55
1044 13:56:57.826107
1045 13:56:57.826591 Set Vref, RX VrefLevel [Byte0]: 56
1046 13:56:57.829097 [Byte1]: 56
1047 13:56:57.833489
1048 13:56:57.833934 Set Vref, RX VrefLevel [Byte0]: 57
1049 13:56:57.836788 [Byte1]: 57
1050 13:56:57.840986
1051 13:56:57.841452 Set Vref, RX VrefLevel [Byte0]: 58
1052 13:56:57.844616 [Byte1]: 58
1053 13:56:57.848687
1054 13:56:57.849218 Set Vref, RX VrefLevel [Byte0]: 59
1055 13:56:57.852193 [Byte1]: 59
1056 13:56:57.856167
1057 13:56:57.856659 Set Vref, RX VrefLevel [Byte0]: 60
1058 13:56:57.859718 [Byte1]: 60
1059 13:56:57.863809
1060 13:56:57.864276 Set Vref, RX VrefLevel [Byte0]: 61
1061 13:56:57.867312 [Byte1]: 61
1062 13:56:57.871509
1063 13:56:57.872075 Set Vref, RX VrefLevel [Byte0]: 62
1064 13:56:57.874484 [Byte1]: 62
1065 13:56:57.878858
1066 13:56:57.879445 Set Vref, RX VrefLevel [Byte0]: 63
1067 13:56:57.882451 [Byte1]: 63
1068 13:56:57.886679
1069 13:56:57.887249 Set Vref, RX VrefLevel [Byte0]: 64
1070 13:56:57.889819 [Byte1]: 64
1071 13:56:57.893882
1072 13:56:57.894397 Set Vref, RX VrefLevel [Byte0]: 65
1073 13:56:57.897237 [Byte1]: 65
1074 13:56:57.901695
1075 13:56:57.902423 Set Vref, RX VrefLevel [Byte0]: 66
1076 13:56:57.904994 [Byte1]: 66
1077 13:56:57.909117
1078 13:56:57.909593 Set Vref, RX VrefLevel [Byte0]: 67
1079 13:56:57.912248 [Byte1]: 67
1080 13:56:57.916515
1081 13:56:57.917091 Set Vref, RX VrefLevel [Byte0]: 68
1082 13:56:57.920334 [Byte1]: 68
1083 13:56:57.924424
1084 13:56:57.924991 Set Vref, RX VrefLevel [Byte0]: 69
1085 13:56:57.927529 [Byte1]: 69
1086 13:56:57.931570
1087 13:56:57.932057 Set Vref, RX VrefLevel [Byte0]: 70
1088 13:56:57.935021 [Byte1]: 70
1089 13:56:57.938984
1090 13:56:57.939469 Set Vref, RX VrefLevel [Byte0]: 71
1091 13:56:57.942464 [Byte1]: 71
1092 13:56:57.946730
1093 13:56:57.947203 Set Vref, RX VrefLevel [Byte0]: 72
1094 13:56:57.950073 [Byte1]: 72
1095 13:56:57.954431
1096 13:56:57.954906 Set Vref, RX VrefLevel [Byte0]: 73
1097 13:56:57.957621 [Byte1]: 73
1098 13:56:57.961819
1099 13:56:57.962324 Set Vref, RX VrefLevel [Byte0]: 74
1100 13:56:57.965122 [Byte1]: 74
1101 13:56:57.969834
1102 13:56:57.970330 Set Vref, RX VrefLevel [Byte0]: 75
1103 13:56:57.973331 [Byte1]: 75
1104 13:56:57.977036
1105 13:56:57.977559 Set Vref, RX VrefLevel [Byte0]: 76
1106 13:56:57.980142 [Byte1]: 76
1107 13:56:57.984436
1108 13:56:57.984961 Set Vref, RX VrefLevel [Byte0]: 77
1109 13:56:57.987732 [Byte1]: 77
1110 13:56:57.991926
1111 13:56:57.992353 Final RX Vref Byte 0 = 60 to rank0
1112 13:56:57.995494 Final RX Vref Byte 1 = 63 to rank0
1113 13:56:57.998730 Final RX Vref Byte 0 = 60 to rank1
1114 13:56:58.001925 Final RX Vref Byte 1 = 63 to rank1==
1115 13:56:58.005701 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 13:56:58.011935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 13:56:58.012451 ==
1118 13:56:58.012848 DQS Delay:
1119 13:56:58.013239 DQS0 = 0, DQS1 = 0
1120 13:56:58.015495 DQM Delay:
1121 13:56:58.016108 DQM0 = 93, DQM1 = 83
1122 13:56:58.019300 DQ Delay:
1123 13:56:58.021988 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1124 13:56:58.025898 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1125 13:56:58.029184 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1126 13:56:58.032070 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1127 13:56:58.032501
1128 13:56:58.032967
1129 13:56:58.038717 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1130 13:56:58.042242 CH0 RK0: MR19=606, MR18=3D38
1131 13:56:58.049183 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1132 13:56:58.049744
1133 13:56:58.052074 ----->DramcWriteLeveling(PI) begin...
1134 13:56:58.052580 ==
1135 13:56:58.055849 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 13:56:58.058782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 13:56:58.059232 ==
1138 13:56:58.062315 Write leveling (Byte 0): 31 => 31
1139 13:56:58.065457 Write leveling (Byte 1): 26 => 26
1140 13:56:58.069316 DramcWriteLeveling(PI) end<-----
1141 13:56:58.069877
1142 13:56:58.070396 ==
1143 13:56:58.072352 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 13:56:58.075668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 13:56:58.076255 ==
1146 13:56:58.079212 [Gating] SW mode calibration
1147 13:56:58.086046 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 13:56:58.092593 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 13:56:58.095655 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 13:56:58.098876 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 13:56:58.105892 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1152 13:56:58.109150 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:56:58.112594 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:56:58.160266 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:56:58.160884 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:56:58.161282 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:56:58.162015 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:56:58.162398 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:56:58.162743 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:56:58.163072 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:56:58.163393 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:56:58.163705 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:56:58.164019 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:56:58.164330 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:56:58.204544 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:56:58.205152 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1167 13:56:58.205920 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1168 13:56:58.206338 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:56:58.206692 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:56:58.207029 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:56:58.207361 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:56:58.207748 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:56:58.208086 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:56:58.208408 0 9 4 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
1175 13:56:58.226413 0 9 8 | B1->B0 | 2e2e 3333 | 0 0 | (0 0) (0 0)
1176 13:56:58.227381 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 13:56:58.227790 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 13:56:58.228147 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:56:58.228487 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:56:58.230171 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:56:58.236910 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:56:58.240790 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1183 13:56:58.243799 0 10 8 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
1184 13:56:58.250779 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:56:58.253775 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:56:58.256965 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:56:58.263705 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:56:58.267433 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:56:58.270083 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:56:58.277081 0 11 4 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
1191 13:56:58.280177 0 11 8 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1192 13:56:58.283642 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 13:56:58.290277 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:56:58.294154 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:56:58.298017 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:56:58.301762 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:56:58.305474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:56:58.312371 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1199 13:56:58.315875 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 13:56:58.319029 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:56:58.322663 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:56:58.329574 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:56:58.332741 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:56:58.336323 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:56:58.342891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:56:58.346693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:56:58.350056 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:56:58.356214 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:56:58.359937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:56:58.362671 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:56:58.369411 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:56:58.373021 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:56:58.376311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:56:58.382768 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 13:56:58.386197 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 13:56:58.389435 Total UI for P1: 0, mck2ui 16
1217 13:56:58.392884 best dqsien dly found for B0: ( 0, 14, 4)
1218 13:56:58.396088 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 13:56:58.399371 Total UI for P1: 0, mck2ui 16
1220 13:56:58.402859 best dqsien dly found for B1: ( 0, 14, 6)
1221 13:56:58.406323 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1222 13:56:58.409551 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1223 13:56:58.410151
1224 13:56:58.413121 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 13:56:58.416100 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1226 13:56:58.419352 [Gating] SW calibration Done
1227 13:56:58.419918 ==
1228 13:56:58.422471 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 13:56:58.429633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 13:56:58.430229 ==
1231 13:56:58.430614 RX Vref Scan: 0
1232 13:56:58.430966
1233 13:56:58.432504 RX Vref 0 -> 0, step: 1
1234 13:56:58.432973
1235 13:56:58.436010 RX Delay -130 -> 252, step: 16
1236 13:56:58.439231 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 13:56:58.442770 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1238 13:56:58.446048 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1239 13:56:58.449436 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1240 13:56:58.456296 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1241 13:56:58.459312 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1242 13:56:58.462569 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 13:56:58.465936 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1244 13:56:58.469303 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1245 13:56:58.475754 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1246 13:56:58.479165 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1247 13:56:58.482946 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1248 13:56:58.486033 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1249 13:56:58.489413 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 13:56:58.496049 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1251 13:56:58.499150 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1252 13:56:58.499622 ==
1253 13:56:58.503023 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 13:56:58.506476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 13:56:58.506949 ==
1256 13:56:58.509193 DQS Delay:
1257 13:56:58.509661 DQS0 = 0, DQS1 = 0
1258 13:56:58.510082 DQM Delay:
1259 13:56:58.513132 DQM0 = 90, DQM1 = 78
1260 13:56:58.513708 DQ Delay:
1261 13:56:58.516315 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1262 13:56:58.519560 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1263 13:56:58.523138 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1264 13:56:58.526515 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
1265 13:56:58.527096
1266 13:56:58.527478
1267 13:56:58.527825 ==
1268 13:56:58.529636 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 13:56:58.536080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 13:56:58.536646 ==
1271 13:56:58.537025
1272 13:56:58.537370
1273 13:56:58.537697 TX Vref Scan disable
1274 13:56:58.540086 == TX Byte 0 ==
1275 13:56:58.543219 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 13:56:58.546509 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 13:56:58.550083 == TX Byte 1 ==
1278 13:56:58.553153 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1279 13:56:58.556726 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1280 13:56:58.559999 ==
1281 13:56:58.563084 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 13:56:58.566570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 13:56:58.567045 ==
1284 13:56:58.579461 TX Vref=22, minBit 8, minWin=26, winSum=443
1285 13:56:58.582777 TX Vref=24, minBit 8, minWin=27, winSum=449
1286 13:56:58.585877 TX Vref=26, minBit 10, minWin=27, winSum=453
1287 13:56:58.589747 TX Vref=28, minBit 4, minWin=28, winSum=457
1288 13:56:58.593002 TX Vref=30, minBit 3, minWin=28, winSum=456
1289 13:56:58.599528 TX Vref=32, minBit 6, minWin=28, winSum=460
1290 13:56:58.602654 [TxChooseVref] Worse bit 6, Min win 28, Win sum 460, Final Vref 32
1291 13:56:58.603127
1292 13:56:58.605904 Final TX Range 1 Vref 32
1293 13:56:58.606430
1294 13:56:58.606796 ==
1295 13:56:58.609284 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 13:56:58.612607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 13:56:58.613071 ==
1298 13:56:58.616051
1299 13:56:58.616463
1300 13:56:58.616791 TX Vref Scan disable
1301 13:56:58.619352 == TX Byte 0 ==
1302 13:56:58.622912 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1303 13:56:58.629098 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1304 13:56:58.629395 == TX Byte 1 ==
1305 13:56:58.632926 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1306 13:56:58.639732 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1307 13:56:58.640124
1308 13:56:58.640363 [DATLAT]
1309 13:56:58.640581 Freq=800, CH0 RK1
1310 13:56:58.640797
1311 13:56:58.642996 DATLAT Default: 0xa
1312 13:56:58.643389 0, 0xFFFF, sum = 0
1313 13:56:58.646420 1, 0xFFFF, sum = 0
1314 13:56:58.646815 2, 0xFFFF, sum = 0
1315 13:56:58.649468 3, 0xFFFF, sum = 0
1316 13:56:58.649773 4, 0xFFFF, sum = 0
1317 13:56:58.653018 5, 0xFFFF, sum = 0
1318 13:56:58.653320 6, 0xFFFF, sum = 0
1319 13:56:58.656359 7, 0xFFFF, sum = 0
1320 13:56:58.659692 8, 0xFFFF, sum = 0
1321 13:56:58.660086 9, 0x0, sum = 1
1322 13:56:58.660329 10, 0x0, sum = 2
1323 13:56:58.662748 11, 0x0, sum = 3
1324 13:56:58.663161 12, 0x0, sum = 4
1325 13:56:58.666592 best_step = 10
1326 13:56:58.667069
1327 13:56:58.667371 ==
1328 13:56:58.669747 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 13:56:58.673341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 13:56:58.673894 ==
1331 13:56:58.676491 RX Vref Scan: 0
1332 13:56:58.676944
1333 13:56:58.677304 RX Vref 0 -> 0, step: 1
1334 13:56:58.677638
1335 13:56:58.679384 RX Delay -79 -> 252, step: 8
1336 13:56:58.686507 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1337 13:56:58.689698 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1338 13:56:58.693129 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1339 13:56:58.696344 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1340 13:56:58.699434 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1341 13:56:58.706417 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1342 13:56:58.709697 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1343 13:56:58.712872 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1344 13:56:58.716460 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1345 13:56:58.719522 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1346 13:56:58.726097 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1347 13:56:58.729546 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1348 13:56:58.733119 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1349 13:56:58.736622 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 13:56:58.739687 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1351 13:56:58.746537 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1352 13:56:58.747090 ==
1353 13:56:58.750055 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 13:56:58.753037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 13:56:58.753598 ==
1356 13:56:58.754010 DQS Delay:
1357 13:56:58.756073 DQS0 = 0, DQS1 = 0
1358 13:56:58.756716 DQM Delay:
1359 13:56:58.759674 DQM0 = 91, DQM1 = 81
1360 13:56:58.760128 DQ Delay:
1361 13:56:58.763219 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =84
1362 13:56:58.766536 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1363 13:56:58.769868 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1364 13:56:58.773167 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1365 13:56:58.773722
1366 13:56:58.774141
1367 13:56:58.782871 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1368 13:56:58.783428 CH0 RK1: MR19=606, MR18=421D
1369 13:56:58.790017 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1370 13:56:58.793105 [RxdqsGatingPostProcess] freq 800
1371 13:56:58.799382 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 13:56:58.802840 Pre-setting of DQS Precalculation
1373 13:56:58.806576 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 13:56:58.807127 ==
1375 13:56:58.809908 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 13:56:58.813366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 13:56:58.813933 ==
1378 13:56:58.819736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 13:56:58.826502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 13:56:58.834676 [CA 0] Center 36 (6~67) winsize 62
1381 13:56:58.838045 [CA 1] Center 36 (6~67) winsize 62
1382 13:56:58.841623 [CA 2] Center 34 (4~65) winsize 62
1383 13:56:58.844848 [CA 3] Center 34 (4~65) winsize 62
1384 13:56:58.848099 [CA 4] Center 34 (4~65) winsize 62
1385 13:56:58.851443 [CA 5] Center 33 (3~64) winsize 62
1386 13:56:58.852005
1387 13:56:58.854684 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1388 13:56:58.855240
1389 13:56:58.857912 [CATrainingPosCal] consider 1 rank data
1390 13:56:58.861343 u2DelayCellTimex100 = 270/100 ps
1391 13:56:58.864796 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 13:56:58.868304 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 13:56:58.874817 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1394 13:56:58.878178 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 13:56:58.881700 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 13:56:58.884645 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 13:56:58.885105
1398 13:56:58.888224 CA PerBit enable=1, Macro0, CA PI delay=33
1399 13:56:58.888779
1400 13:56:58.891364 [CBTSetCACLKResult] CA Dly = 33
1401 13:56:58.891921 CS Dly: 5 (0~36)
1402 13:56:58.892288 ==
1403 13:56:58.894877 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 13:56:58.901497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 13:56:58.902132 ==
1406 13:56:58.904697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 13:56:58.911246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 13:56:58.921053 [CA 0] Center 36 (6~67) winsize 62
1409 13:56:58.924186 [CA 1] Center 37 (6~68) winsize 63
1410 13:56:58.927599 [CA 2] Center 35 (4~66) winsize 63
1411 13:56:58.931075 [CA 3] Center 34 (4~65) winsize 62
1412 13:56:58.934153 [CA 4] Center 34 (4~65) winsize 62
1413 13:56:58.937393 [CA 5] Center 34 (4~64) winsize 61
1414 13:56:58.937853
1415 13:56:58.940796 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 13:56:58.941366
1417 13:56:58.944132 [CATrainingPosCal] consider 2 rank data
1418 13:56:58.947581 u2DelayCellTimex100 = 270/100 ps
1419 13:56:58.950820 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 13:56:58.954423 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 13:56:58.961567 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 13:56:58.962206 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 13:56:58.965352 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 13:56:58.968855 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 13:56:58.969437
1426 13:56:58.972804 CA PerBit enable=1, Macro0, CA PI delay=34
1427 13:56:58.973368
1428 13:56:58.976468 [CBTSetCACLKResult] CA Dly = 34
1429 13:56:58.980412 CS Dly: 6 (0~38)
1430 13:56:58.980963
1431 13:56:58.983626 ----->DramcWriteLeveling(PI) begin...
1432 13:56:58.984087 ==
1433 13:56:58.987478 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 13:56:58.990664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 13:56:58.991230 ==
1436 13:56:58.994688 Write leveling (Byte 0): 26 => 26
1437 13:56:58.995147 Write leveling (Byte 1): 31 => 31
1438 13:56:58.998054 DramcWriteLeveling(PI) end<-----
1439 13:56:58.998565
1440 13:56:59.001283 ==
1441 13:56:59.001818 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 13:56:59.008183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 13:56:59.008757 ==
1444 13:56:59.011381 [Gating] SW mode calibration
1445 13:56:59.018407 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 13:56:59.021719 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 13:56:59.028108 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1448 13:56:59.031601 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1449 13:56:59.034834 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1450 13:56:59.038074 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:56:59.044694 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:56:59.048263 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:56:59.051778 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:56:59.058520 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:56:59.061283 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:56:59.065402 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:56:59.071663 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:56:59.075187 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:56:59.078371 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:56:59.084733 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:56:59.088250 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:56:59.091523 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:56:59.098524 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1464 13:56:59.101627 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1465 13:56:59.104716 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:56:59.111485 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:56:59.114935 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:56:59.118739 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:56:59.122074 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:56:59.128429 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:56:59.132018 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:56:59.134907 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1473 13:56:59.141741 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 13:56:59.145264 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 13:56:59.148384 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:56:59.155235 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:56:59.158168 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:56:59.161367 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 13:56:59.168609 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1480 13:56:59.171743 0 10 4 | B1->B0 | 2d2d 2b2b | 1 1 | (1 0) (1 0)
1481 13:56:59.175002 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1482 13:56:59.182006 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:56:59.184559 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:56:59.188707 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:56:59.194942 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:56:59.198367 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:56:59.201415 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1488 13:56:59.208066 0 11 4 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)
1489 13:56:59.211283 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 13:56:59.214974 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 13:56:59.221668 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:56:59.225209 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:56:59.228460 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:56:59.231419 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:56:59.238639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1496 13:56:59.241672 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1497 13:56:59.244920 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:56:59.251551 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:56:59.255030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:56:59.258240 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:56:59.265610 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:56:59.268145 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:56:59.271439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:56:59.278543 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:56:59.281540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:56:59.285272 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:56:59.291968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:56:59.294997 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:56:59.298414 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:56:59.301799 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:56:59.308344 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1512 13:56:59.312435 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1513 13:56:59.315549 Total UI for P1: 0, mck2ui 16
1514 13:56:59.318716 best dqsien dly found for B0: ( 0, 14, 0)
1515 13:56:59.322252 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1516 13:56:59.328847 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 13:56:59.329426 Total UI for P1: 0, mck2ui 16
1518 13:56:59.335380 best dqsien dly found for B1: ( 0, 14, 6)
1519 13:56:59.338512 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1520 13:56:59.342298 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 13:56:59.342880
1522 13:56:59.345261 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1523 13:56:59.348833 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 13:56:59.351998 [Gating] SW calibration Done
1525 13:56:59.352475 ==
1526 13:56:59.355593 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 13:56:59.358643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 13:56:59.359277 ==
1529 13:56:59.361862 RX Vref Scan: 0
1530 13:56:59.362367
1531 13:56:59.362741 RX Vref 0 -> 0, step: 1
1532 13:56:59.363091
1533 13:56:59.365160 RX Delay -130 -> 252, step: 16
1534 13:56:59.368853 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1535 13:56:59.375307 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1536 13:56:59.378501 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1537 13:56:59.382149 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1538 13:56:59.385144 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1539 13:56:59.388644 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1540 13:56:59.395605 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1541 13:56:59.398810 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1542 13:56:59.402141 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1543 13:56:59.405693 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1544 13:56:59.408484 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1545 13:56:59.415669 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1546 13:56:59.418835 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1547 13:56:59.422492 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1548 13:56:59.425775 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1549 13:56:59.429043 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1550 13:56:59.429609 ==
1551 13:56:59.432164 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 13:56:59.438772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 13:56:59.439344 ==
1554 13:56:59.439719 DQS Delay:
1555 13:56:59.442195 DQS0 = 0, DQS1 = 0
1556 13:56:59.442762 DQM Delay:
1557 13:56:59.443144 DQM0 = 88, DQM1 = 80
1558 13:56:59.445612 DQ Delay:
1559 13:56:59.448623 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1560 13:56:59.452427 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1561 13:56:59.455380 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1562 13:56:59.458904 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 13:56:59.459498
1564 13:56:59.459871
1565 13:56:59.460218 ==
1566 13:56:59.462125 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 13:56:59.465615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 13:56:59.466238 ==
1569 13:56:59.466626
1570 13:56:59.466969
1571 13:56:59.469050 TX Vref Scan disable
1572 13:56:59.472202 == TX Byte 0 ==
1573 13:56:59.475226 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1574 13:56:59.478597 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1575 13:56:59.481652 == TX Byte 1 ==
1576 13:56:59.484919 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1577 13:56:59.488350 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1578 13:56:59.488922 ==
1579 13:56:59.491703 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 13:56:59.495189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 13:56:59.498151 ==
1582 13:56:59.509885 TX Vref=22, minBit 15, minWin=26, winSum=443
1583 13:56:59.513222 TX Vref=24, minBit 8, minWin=27, winSum=450
1584 13:56:59.516497 TX Vref=26, minBit 8, minWin=27, winSum=453
1585 13:56:59.520071 TX Vref=28, minBit 15, minWin=27, winSum=456
1586 13:56:59.523305 TX Vref=30, minBit 15, minWin=27, winSum=459
1587 13:56:59.530135 TX Vref=32, minBit 11, minWin=27, winSum=456
1588 13:56:59.533717 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 30
1589 13:56:59.534345
1590 13:56:59.536932 Final TX Range 1 Vref 30
1591 13:56:59.537396
1592 13:56:59.537761 ==
1593 13:56:59.540086 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 13:56:59.544140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 13:56:59.544953 ==
1596 13:56:59.545368
1597 13:56:59.545716
1598 13:56:59.547570 TX Vref Scan disable
1599 13:56:59.550841 == TX Byte 0 ==
1600 13:56:59.554243 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1601 13:56:59.557579 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1602 13:56:59.561069 == TX Byte 1 ==
1603 13:56:59.564412 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1604 13:56:59.567634 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1605 13:56:59.568107
1606 13:56:59.570725 [DATLAT]
1607 13:56:59.571195 Freq=800, CH1 RK0
1608 13:56:59.571569
1609 13:56:59.574401 DATLAT Default: 0xa
1610 13:56:59.574971 0, 0xFFFF, sum = 0
1611 13:56:59.578170 1, 0xFFFF, sum = 0
1612 13:56:59.578732 2, 0xFFFF, sum = 0
1613 13:56:59.580722 3, 0xFFFF, sum = 0
1614 13:56:59.581305 4, 0xFFFF, sum = 0
1615 13:56:59.583935 5, 0xFFFF, sum = 0
1616 13:56:59.584449 6, 0xFFFF, sum = 0
1617 13:56:59.587310 7, 0xFFFF, sum = 0
1618 13:56:59.587787 8, 0xFFFF, sum = 0
1619 13:56:59.590875 9, 0x0, sum = 1
1620 13:56:59.591461 10, 0x0, sum = 2
1621 13:56:59.594172 11, 0x0, sum = 3
1622 13:56:59.594741 12, 0x0, sum = 4
1623 13:56:59.597569 best_step = 10
1624 13:56:59.598159
1625 13:56:59.598536 ==
1626 13:56:59.600718 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 13:56:59.603955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 13:56:59.604428 ==
1629 13:56:59.607395 RX Vref Scan: 1
1630 13:56:59.607957
1631 13:56:59.608333 Set Vref Range= 32 -> 127
1632 13:56:59.608772
1633 13:56:59.610613 RX Vref 32 -> 127, step: 1
1634 13:56:59.611082
1635 13:56:59.613725 RX Delay -95 -> 252, step: 8
1636 13:56:59.614224
1637 13:56:59.616997 Set Vref, RX VrefLevel [Byte0]: 32
1638 13:56:59.621033 [Byte1]: 32
1639 13:56:59.621604
1640 13:56:59.624193 Set Vref, RX VrefLevel [Byte0]: 33
1641 13:56:59.627416 [Byte1]: 33
1642 13:56:59.630579
1643 13:56:59.631046 Set Vref, RX VrefLevel [Byte0]: 34
1644 13:56:59.634120 [Byte1]: 34
1645 13:56:59.638565
1646 13:56:59.639130 Set Vref, RX VrefLevel [Byte0]: 35
1647 13:56:59.641901 [Byte1]: 35
1648 13:56:59.646055
1649 13:56:59.646612 Set Vref, RX VrefLevel [Byte0]: 36
1650 13:56:59.649044 [Byte1]: 36
1651 13:56:59.653734
1652 13:56:59.654346 Set Vref, RX VrefLevel [Byte0]: 37
1653 13:56:59.656950 [Byte1]: 37
1654 13:56:59.661265
1655 13:56:59.661923 Set Vref, RX VrefLevel [Byte0]: 38
1656 13:56:59.664497 [Byte1]: 38
1657 13:56:59.668738
1658 13:56:59.669302 Set Vref, RX VrefLevel [Byte0]: 39
1659 13:56:59.672261 [Byte1]: 39
1660 13:56:59.676565
1661 13:56:59.677034 Set Vref, RX VrefLevel [Byte0]: 40
1662 13:56:59.679578 [Byte1]: 40
1663 13:56:59.684017
1664 13:56:59.684623 Set Vref, RX VrefLevel [Byte0]: 41
1665 13:56:59.687018 [Byte1]: 41
1666 13:56:59.691519
1667 13:56:59.692098 Set Vref, RX VrefLevel [Byte0]: 42
1668 13:56:59.694971 [Byte1]: 42
1669 13:56:59.698948
1670 13:56:59.699512 Set Vref, RX VrefLevel [Byte0]: 43
1671 13:56:59.702269 [Byte1]: 43
1672 13:56:59.706513
1673 13:56:59.706972 Set Vref, RX VrefLevel [Byte0]: 44
1674 13:56:59.709906 [Byte1]: 44
1675 13:56:59.714628
1676 13:56:59.715089 Set Vref, RX VrefLevel [Byte0]: 45
1677 13:56:59.717919 [Byte1]: 45
1678 13:56:59.722260
1679 13:56:59.722820 Set Vref, RX VrefLevel [Byte0]: 46
1680 13:56:59.725359 [Byte1]: 46
1681 13:56:59.730003
1682 13:56:59.730570 Set Vref, RX VrefLevel [Byte0]: 47
1683 13:56:59.733248 [Byte1]: 47
1684 13:56:59.737389
1685 13:56:59.738005 Set Vref, RX VrefLevel [Byte0]: 48
1686 13:56:59.740813 [Byte1]: 48
1687 13:56:59.744998
1688 13:56:59.745580 Set Vref, RX VrefLevel [Byte0]: 49
1689 13:56:59.748305 [Byte1]: 49
1690 13:56:59.752409
1691 13:56:59.752972 Set Vref, RX VrefLevel [Byte0]: 50
1692 13:56:59.756056 [Byte1]: 50
1693 13:56:59.760112
1694 13:56:59.760674 Set Vref, RX VrefLevel [Byte0]: 51
1695 13:56:59.763396 [Byte1]: 51
1696 13:56:59.767995
1697 13:56:59.768843 Set Vref, RX VrefLevel [Byte0]: 52
1698 13:56:59.770815 [Byte1]: 52
1699 13:56:59.774922
1700 13:56:59.775385 Set Vref, RX VrefLevel [Byte0]: 53
1701 13:56:59.778447 [Byte1]: 53
1702 13:56:59.782893
1703 13:56:59.783357 Set Vref, RX VrefLevel [Byte0]: 54
1704 13:56:59.785981 [Byte1]: 54
1705 13:56:59.790437
1706 13:56:59.790902 Set Vref, RX VrefLevel [Byte0]: 55
1707 13:56:59.793472 [Byte1]: 55
1708 13:56:59.798302
1709 13:56:59.798763 Set Vref, RX VrefLevel [Byte0]: 56
1710 13:56:59.801645 [Byte1]: 56
1711 13:56:59.805652
1712 13:56:59.806263 Set Vref, RX VrefLevel [Byte0]: 57
1713 13:56:59.808679 [Byte1]: 57
1714 13:56:59.813354
1715 13:56:59.813816 Set Vref, RX VrefLevel [Byte0]: 58
1716 13:56:59.816355 [Byte1]: 58
1717 13:56:59.820773
1718 13:56:59.821350 Set Vref, RX VrefLevel [Byte0]: 59
1719 13:56:59.824018 [Byte1]: 59
1720 13:56:59.828353
1721 13:56:59.828908 Set Vref, RX VrefLevel [Byte0]: 60
1722 13:56:59.831954 [Byte1]: 60
1723 13:56:59.836379
1724 13:56:59.836945 Set Vref, RX VrefLevel [Byte0]: 61
1725 13:56:59.839048 [Byte1]: 61
1726 13:56:59.843821
1727 13:56:59.844385 Set Vref, RX VrefLevel [Byte0]: 62
1728 13:56:59.846848 [Byte1]: 62
1729 13:56:59.851313
1730 13:56:59.851879 Set Vref, RX VrefLevel [Byte0]: 63
1731 13:56:59.854360 [Byte1]: 63
1732 13:56:59.858783
1733 13:56:59.859245 Set Vref, RX VrefLevel [Byte0]: 64
1734 13:56:59.861917 [Byte1]: 64
1735 13:56:59.866306
1736 13:56:59.866868 Set Vref, RX VrefLevel [Byte0]: 65
1737 13:56:59.869903 [Byte1]: 65
1738 13:56:59.874150
1739 13:56:59.874710 Set Vref, RX VrefLevel [Byte0]: 66
1740 13:56:59.877369 [Byte1]: 66
1741 13:56:59.881681
1742 13:56:59.882290 Set Vref, RX VrefLevel [Byte0]: 67
1743 13:56:59.884514 [Byte1]: 67
1744 13:56:59.889646
1745 13:56:59.890288 Set Vref, RX VrefLevel [Byte0]: 68
1746 13:56:59.892350 [Byte1]: 68
1747 13:56:59.897029
1748 13:56:59.897610 Set Vref, RX VrefLevel [Byte0]: 69
1749 13:56:59.899795 [Byte1]: 69
1750 13:56:59.904334
1751 13:56:59.904799 Set Vref, RX VrefLevel [Byte0]: 70
1752 13:56:59.907466 [Byte1]: 70
1753 13:56:59.911633
1754 13:56:59.912104 Set Vref, RX VrefLevel [Byte0]: 71
1755 13:56:59.915117 [Byte1]: 71
1756 13:56:59.919452
1757 13:56:59.919935 Set Vref, RX VrefLevel [Byte0]: 72
1758 13:56:59.922751 [Byte1]: 72
1759 13:56:59.927217
1760 13:56:59.927798 Set Vref, RX VrefLevel [Byte0]: 73
1761 13:56:59.930348 [Byte1]: 73
1762 13:56:59.934823
1763 13:56:59.935384 Set Vref, RX VrefLevel [Byte0]: 74
1764 13:56:59.938058 [Byte1]: 74
1765 13:56:59.942277
1766 13:56:59.942844 Set Vref, RX VrefLevel [Byte0]: 75
1767 13:56:59.945682 [Byte1]: 75
1768 13:56:59.949662
1769 13:56:59.950171 Set Vref, RX VrefLevel [Byte0]: 76
1770 13:56:59.953198 [Byte1]: 76
1771 13:56:59.957536
1772 13:56:59.958144 Set Vref, RX VrefLevel [Byte0]: 77
1773 13:56:59.960778 [Byte1]: 77
1774 13:56:59.965083
1775 13:56:59.965651 Set Vref, RX VrefLevel [Byte0]: 78
1776 13:56:59.968540 [Byte1]: 78
1777 13:56:59.972628
1778 13:56:59.973194 Final RX Vref Byte 0 = 51 to rank0
1779 13:56:59.976145 Final RX Vref Byte 1 = 63 to rank0
1780 13:56:59.979368 Final RX Vref Byte 0 = 51 to rank1
1781 13:56:59.982852 Final RX Vref Byte 1 = 63 to rank1==
1782 13:56:59.986343 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 13:56:59.992893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 13:56:59.993464 ==
1785 13:56:59.993839 DQS Delay:
1786 13:56:59.994228 DQS0 = 0, DQS1 = 0
1787 13:56:59.995750 DQM Delay:
1788 13:56:59.996213 DQM0 = 92, DQM1 = 83
1789 13:56:59.999342 DQ Delay:
1790 13:57:00.003060 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1791 13:57:00.003547 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1792 13:57:00.006149 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1793 13:57:00.009593 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1794 13:57:00.013039
1795 13:57:00.013532
1796 13:57:00.019825 [DQSOSCAuto] RK0, (LSB)MR18= 0x3250, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
1797 13:57:00.022558 CH1 RK0: MR19=606, MR18=3250
1798 13:57:00.029870 CH1_RK0: MR19=0x606, MR18=0x3250, DQSOSC=389, MR23=63, INC=97, DEC=65
1799 13:57:00.030488
1800 13:57:00.033017 ----->DramcWriteLeveling(PI) begin...
1801 13:57:00.033492 ==
1802 13:57:00.035960 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 13:57:00.039491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 13:57:00.039962 ==
1805 13:57:00.042937 Write leveling (Byte 0): 26 => 26
1806 13:57:00.046196 Write leveling (Byte 1): 31 => 31
1807 13:57:00.049521 DramcWriteLeveling(PI) end<-----
1808 13:57:00.050107
1809 13:57:00.050482 ==
1810 13:57:00.053226 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 13:57:00.056431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 13:57:00.057001 ==
1813 13:57:00.059260 [Gating] SW mode calibration
1814 13:57:00.066730 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 13:57:00.072797 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 13:57:00.076113 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 13:57:00.079712 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1818 13:57:00.086110 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1819 13:57:00.089748 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:57:00.093031 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:57:00.099586 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:57:00.103091 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:57:00.106146 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:57:00.112602 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:57:00.115957 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:57:00.119513 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:57:00.126194 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:57:00.129670 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:57:00.132927 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:57:00.136223 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:57:00.142996 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:57:00.146313 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1833 13:57:00.149747 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1834 13:57:00.156201 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1835 13:57:00.160083 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:57:00.162797 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 13:57:00.169449 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:57:00.172934 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:57:00.176168 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:57:00.183238 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:57:00.186419 0 9 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1842 13:57:00.189685 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1843 13:57:00.196499 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 13:57:00.199603 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 13:57:00.203103 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 13:57:00.210006 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 13:57:00.213065 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 13:57:00.216386 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1849 13:57:00.219833 0 10 4 | B1->B0 | 2e2e 3131 | 0 0 | (0 1) (0 1)
1850 13:57:00.226533 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1851 13:57:00.230030 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:57:00.232989 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:57:00.239856 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:57:00.243607 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:57:00.246596 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:57:00.253152 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:57:00.256329 0 11 4 | B1->B0 | 3939 3131 | 0 0 | (1 1) (1 1)
1858 13:57:00.259363 0 11 8 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
1859 13:57:00.266270 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 13:57:00.269761 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 13:57:00.273029 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 13:57:00.279780 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 13:57:00.282872 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 13:57:00.286604 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 13:57:00.289991 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1866 13:57:00.296655 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:57:00.300475 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:57:00.303120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:57:00.309901 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:57:00.313676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:57:00.316838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:57:00.323464 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:57:00.327030 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:57:00.330254 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:57:00.336767 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 13:57:00.340064 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:57:00.343526 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:57:00.350359 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:57:00.353541 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:57:00.356707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 13:57:00.360223 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1882 13:57:00.366405 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1883 13:57:00.370131 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 13:57:00.373227 Total UI for P1: 0, mck2ui 16
1885 13:57:00.376765 best dqsien dly found for B0: ( 0, 14, 8)
1886 13:57:00.380078 Total UI for P1: 0, mck2ui 16
1887 13:57:00.383274 best dqsien dly found for B1: ( 0, 14, 6)
1888 13:57:00.386778 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1889 13:57:00.390083 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1890 13:57:00.390558
1891 13:57:00.393519 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1892 13:57:00.396775 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1893 13:57:00.400290 [Gating] SW calibration Done
1894 13:57:00.400867 ==
1895 13:57:00.403391 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 13:57:00.406631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 13:57:00.410465 ==
1898 13:57:00.411034 RX Vref Scan: 0
1899 13:57:00.411407
1900 13:57:00.413365 RX Vref 0 -> 0, step: 1
1901 13:57:00.413829
1902 13:57:00.416956 RX Delay -130 -> 252, step: 16
1903 13:57:00.420276 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1904 13:57:00.423506 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1905 13:57:00.426604 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1906 13:57:00.430055 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1907 13:57:00.436944 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1908 13:57:00.440109 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1909 13:57:00.443657 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1910 13:57:00.446944 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1911 13:57:00.450297 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1912 13:57:00.456875 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1913 13:57:00.460073 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1914 13:57:00.463487 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1915 13:57:00.466478 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1916 13:57:00.470141 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1917 13:57:00.476522 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1918 13:57:00.480212 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1919 13:57:00.480784 ==
1920 13:57:00.483840 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 13:57:00.486755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 13:57:00.487229 ==
1923 13:57:00.489843 DQS Delay:
1924 13:57:00.490341 DQS0 = 0, DQS1 = 0
1925 13:57:00.490712 DQM Delay:
1926 13:57:00.493480 DQM0 = 89, DQM1 = 82
1927 13:57:00.494100 DQ Delay:
1928 13:57:00.496554 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1929 13:57:00.500118 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1930 13:57:00.503233 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1931 13:57:00.507051 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1932 13:57:00.507619
1933 13:57:00.507997
1934 13:57:00.508342 ==
1935 13:57:00.509805 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 13:57:00.513252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 13:57:00.516713 ==
1938 13:57:00.517290
1939 13:57:00.517665
1940 13:57:00.518230 TX Vref Scan disable
1941 13:57:00.520305 == TX Byte 0 ==
1942 13:57:00.523725 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1943 13:57:00.526724 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1944 13:57:00.530339 == TX Byte 1 ==
1945 13:57:00.533285 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1946 13:57:00.536517 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1947 13:57:00.540088 ==
1948 13:57:00.543037 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 13:57:00.546296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 13:57:00.546772 ==
1951 13:57:00.559410 TX Vref=22, minBit 8, minWin=27, winSum=449
1952 13:57:00.562675 TX Vref=24, minBit 12, minWin=27, winSum=452
1953 13:57:00.565961 TX Vref=26, minBit 9, minWin=27, winSum=454
1954 13:57:00.569416 TX Vref=28, minBit 8, minWin=28, winSum=457
1955 13:57:00.572531 TX Vref=30, minBit 8, minWin=28, winSum=459
1956 13:57:00.575815 TX Vref=32, minBit 8, minWin=28, winSum=459
1957 13:57:00.582441 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1958 13:57:00.582776
1959 13:57:00.586280 Final TX Range 1 Vref 30
1960 13:57:00.586604
1961 13:57:00.586861 ==
1962 13:57:00.589128 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 13:57:00.592663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 13:57:00.592990 ==
1965 13:57:00.593247
1966 13:57:00.596064
1967 13:57:00.596492 TX Vref Scan disable
1968 13:57:00.599269 == TX Byte 0 ==
1969 13:57:00.602671 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1970 13:57:00.606096 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1971 13:57:00.609205 == TX Byte 1 ==
1972 13:57:00.612823 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1973 13:57:00.615741 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1974 13:57:00.619393
1975 13:57:00.619823 [DATLAT]
1976 13:57:00.620086 Freq=800, CH1 RK1
1977 13:57:00.620329
1978 13:57:00.622635 DATLAT Default: 0xa
1979 13:57:00.622959 0, 0xFFFF, sum = 0
1980 13:57:00.625807 1, 0xFFFF, sum = 0
1981 13:57:00.626160 2, 0xFFFF, sum = 0
1982 13:57:00.629588 3, 0xFFFF, sum = 0
1983 13:57:00.630062 4, 0xFFFF, sum = 0
1984 13:57:00.632633 5, 0xFFFF, sum = 0
1985 13:57:00.636524 6, 0xFFFF, sum = 0
1986 13:57:00.636960 7, 0xFFFF, sum = 0
1987 13:57:00.639411 8, 0xFFFF, sum = 0
1988 13:57:00.639844 9, 0x0, sum = 1
1989 13:57:00.640116 10, 0x0, sum = 2
1990 13:57:00.642787 11, 0x0, sum = 3
1991 13:57:00.643118 12, 0x0, sum = 4
1992 13:57:00.646107 best_step = 10
1993 13:57:00.646429
1994 13:57:00.646687 ==
1995 13:57:00.649592 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 13:57:00.653294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 13:57:00.653755 ==
1998 13:57:00.656421 RX Vref Scan: 0
1999 13:57:00.656747
2000 13:57:00.657003 RX Vref 0 -> 0, step: 1
2001 13:57:00.657246
2002 13:57:00.659272 RX Delay -95 -> 252, step: 8
2003 13:57:00.665860 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2004 13:57:00.669436 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2005 13:57:00.672786 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2006 13:57:00.676279 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2007 13:57:00.679220 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2008 13:57:00.685878 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2009 13:57:00.689199 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2010 13:57:00.692540 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2011 13:57:00.696211 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2012 13:57:00.699679 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2013 13:57:00.702945 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2014 13:57:00.709315 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2015 13:57:00.712874 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2016 13:57:00.715866 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2017 13:57:00.719587 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2018 13:57:00.726429 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2019 13:57:00.726892 ==
2020 13:57:00.729637 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 13:57:00.733234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 13:57:00.733813 ==
2023 13:57:00.734227 DQS Delay:
2024 13:57:00.736012 DQS0 = 0, DQS1 = 0
2025 13:57:00.736579 DQM Delay:
2026 13:57:00.739368 DQM0 = 91, DQM1 = 84
2027 13:57:00.739831 DQ Delay:
2028 13:57:00.742804 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2029 13:57:00.746391 DQ4 =96, DQ5 =104, DQ6 =96, DQ7 =88
2030 13:57:00.749703 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2031 13:57:00.752712 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2032 13:57:00.753279
2033 13:57:00.753646
2034 13:57:00.759648 [DQSOSCAuto] RK1, (LSB)MR18= 0x370c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2035 13:57:00.762597 CH1 RK1: MR19=606, MR18=370C
2036 13:57:00.769249 CH1_RK1: MR19=0x606, MR18=0x370C, DQSOSC=395, MR23=63, INC=94, DEC=63
2037 13:57:00.772872 [RxdqsGatingPostProcess] freq 800
2038 13:57:00.779385 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 13:57:00.782611 Pre-setting of DQS Precalculation
2040 13:57:00.786101 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 13:57:00.793118 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 13:57:00.799609 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 13:57:00.800173
2044 13:57:00.800539
2045 13:57:00.802296 [Calibration Summary] 1600 Mbps
2046 13:57:00.805644 CH 0, Rank 0
2047 13:57:00.806149 SW Impedance : PASS
2048 13:57:00.809088 DUTY Scan : NO K
2049 13:57:00.812661 ZQ Calibration : PASS
2050 13:57:00.813228 Jitter Meter : NO K
2051 13:57:00.815916 CBT Training : PASS
2052 13:57:00.819113 Write leveling : PASS
2053 13:57:00.819672 RX DQS gating : PASS
2054 13:57:00.822451 RX DQ/DQS(RDDQC) : PASS
2055 13:57:00.823019 TX DQ/DQS : PASS
2056 13:57:00.826055 RX DATLAT : PASS
2057 13:57:00.828976 RX DQ/DQS(Engine): PASS
2058 13:57:00.829440 TX OE : NO K
2059 13:57:00.832571 All Pass.
2060 13:57:00.833157
2061 13:57:00.833532 CH 0, Rank 1
2062 13:57:00.835942 SW Impedance : PASS
2063 13:57:00.836502 DUTY Scan : NO K
2064 13:57:00.838923 ZQ Calibration : PASS
2065 13:57:00.842372 Jitter Meter : NO K
2066 13:57:00.842931 CBT Training : PASS
2067 13:57:00.845828 Write leveling : PASS
2068 13:57:00.848956 RX DQS gating : PASS
2069 13:57:00.849425 RX DQ/DQS(RDDQC) : PASS
2070 13:57:00.852280 TX DQ/DQS : PASS
2071 13:57:00.856017 RX DATLAT : PASS
2072 13:57:00.856580 RX DQ/DQS(Engine): PASS
2073 13:57:00.859234 TX OE : NO K
2074 13:57:00.859804 All Pass.
2075 13:57:00.860179
2076 13:57:00.862234 CH 1, Rank 0
2077 13:57:00.862694 SW Impedance : PASS
2078 13:57:00.865606 DUTY Scan : NO K
2079 13:57:00.869139 ZQ Calibration : PASS
2080 13:57:00.869605 Jitter Meter : NO K
2081 13:57:00.872484 CBT Training : PASS
2082 13:57:00.873080 Write leveling : PASS
2083 13:57:00.875658 RX DQS gating : PASS
2084 13:57:00.878961 RX DQ/DQS(RDDQC) : PASS
2085 13:57:00.879537 TX DQ/DQS : PASS
2086 13:57:00.882252 RX DATLAT : PASS
2087 13:57:00.885548 RX DQ/DQS(Engine): PASS
2088 13:57:00.886062 TX OE : NO K
2089 13:57:00.888971 All Pass.
2090 13:57:00.889446
2091 13:57:00.889810 CH 1, Rank 1
2092 13:57:00.892294 SW Impedance : PASS
2093 13:57:00.892857 DUTY Scan : NO K
2094 13:57:00.895708 ZQ Calibration : PASS
2095 13:57:00.899252 Jitter Meter : NO K
2096 13:57:00.899930 CBT Training : PASS
2097 13:57:00.902611 Write leveling : PASS
2098 13:57:00.905758 RX DQS gating : PASS
2099 13:57:00.906339 RX DQ/DQS(RDDQC) : PASS
2100 13:57:00.909082 TX DQ/DQS : PASS
2101 13:57:00.912443 RX DATLAT : PASS
2102 13:57:00.913011 RX DQ/DQS(Engine): PASS
2103 13:57:00.915645 TX OE : NO K
2104 13:57:00.916218 All Pass.
2105 13:57:00.916593
2106 13:57:00.918749 DramC Write-DBI off
2107 13:57:00.922171 PER_BANK_REFRESH: Hybrid Mode
2108 13:57:00.922631 TX_TRACKING: ON
2109 13:57:00.925667 [GetDramInforAfterCalByMRR] Vendor 6.
2110 13:57:00.928970 [GetDramInforAfterCalByMRR] Revision 606.
2111 13:57:00.932361 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 13:57:00.935659 MR0 0x3b3b
2113 13:57:00.936214 MR8 0x5151
2114 13:57:00.938961 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 13:57:00.939427
2116 13:57:00.939792 MR0 0x3b3b
2117 13:57:00.941983 MR8 0x5151
2118 13:57:00.945514 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 13:57:00.946008
2120 13:57:00.952245 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 13:57:00.959017 [FAST_K] Save calibration result to emmc
2122 13:57:00.962350 [FAST_K] Save calibration result to emmc
2123 13:57:00.962915 dram_init: config_dvfs: 1
2124 13:57:00.965729 dramc_set_vcore_voltage set vcore to 662500
2125 13:57:00.969008 Read voltage for 1200, 2
2126 13:57:00.969470 Vio18 = 0
2127 13:57:00.972538 Vcore = 662500
2128 13:57:00.973109 Vdram = 0
2129 13:57:00.973481 Vddq = 0
2130 13:57:00.976014 Vmddr = 0
2131 13:57:00.979092 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 13:57:00.986006 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 13:57:00.986585 MEM_TYPE=3, freq_sel=15
2134 13:57:00.989015 sv_algorithm_assistance_LP4_1600
2135 13:57:00.996004 ============ PULL DRAM RESETB DOWN ============
2136 13:57:00.999213 ========== PULL DRAM RESETB DOWN end =========
2137 13:57:01.002623 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 13:57:01.005684 ===================================
2139 13:57:01.009383 LPDDR4 DRAM CONFIGURATION
2140 13:57:01.012448 ===================================
2141 13:57:01.013021 EX_ROW_EN[0] = 0x0
2142 13:57:01.015936 EX_ROW_EN[1] = 0x0
2143 13:57:01.019438 LP4Y_EN = 0x0
2144 13:57:01.020019 WORK_FSP = 0x0
2145 13:57:01.022578 WL = 0x4
2146 13:57:01.023040 RL = 0x4
2147 13:57:01.026173 BL = 0x2
2148 13:57:01.026739 RPST = 0x0
2149 13:57:01.029242 RD_PRE = 0x0
2150 13:57:01.029807 WR_PRE = 0x1
2151 13:57:01.032455 WR_PST = 0x0
2152 13:57:01.033021 DBI_WR = 0x0
2153 13:57:01.036173 DBI_RD = 0x0
2154 13:57:01.036736 OTF = 0x1
2155 13:57:01.039198 ===================================
2156 13:57:01.042713 ===================================
2157 13:57:01.045970 ANA top config
2158 13:57:01.049388 ===================================
2159 13:57:01.049990 DLL_ASYNC_EN = 0
2160 13:57:01.052649 ALL_SLAVE_EN = 0
2161 13:57:01.055938 NEW_RANK_MODE = 1
2162 13:57:01.059774 DLL_IDLE_MODE = 1
2163 13:57:01.060340 LP45_APHY_COMB_EN = 1
2164 13:57:01.062441 TX_ODT_DIS = 1
2165 13:57:01.065896 NEW_8X_MODE = 1
2166 13:57:01.069638 ===================================
2167 13:57:01.073082 ===================================
2168 13:57:01.075962 data_rate = 2400
2169 13:57:01.079360 CKR = 1
2170 13:57:01.079932 DQ_P2S_RATIO = 8
2171 13:57:01.082520 ===================================
2172 13:57:01.086372 CA_P2S_RATIO = 8
2173 13:57:01.089507 DQ_CA_OPEN = 0
2174 13:57:01.092946 DQ_SEMI_OPEN = 0
2175 13:57:01.096217 CA_SEMI_OPEN = 0
2176 13:57:01.099330 CA_FULL_RATE = 0
2177 13:57:01.099919 DQ_CKDIV4_EN = 0
2178 13:57:01.102679 CA_CKDIV4_EN = 0
2179 13:57:01.105903 CA_PREDIV_EN = 0
2180 13:57:01.108887 PH8_DLY = 17
2181 13:57:01.112389 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 13:57:01.116095 DQ_AAMCK_DIV = 4
2183 13:57:01.116686 CA_AAMCK_DIV = 4
2184 13:57:01.118951 CA_ADMCK_DIV = 4
2185 13:57:01.122418 DQ_TRACK_CA_EN = 0
2186 13:57:01.125636 CA_PICK = 1200
2187 13:57:01.129151 CA_MCKIO = 1200
2188 13:57:01.132242 MCKIO_SEMI = 0
2189 13:57:01.135813 PLL_FREQ = 2366
2190 13:57:01.139071 DQ_UI_PI_RATIO = 32
2191 13:57:01.139550 CA_UI_PI_RATIO = 0
2192 13:57:01.142416 ===================================
2193 13:57:01.146299 ===================================
2194 13:57:01.149296 memory_type:LPDDR4
2195 13:57:01.152892 GP_NUM : 10
2196 13:57:01.153470 SRAM_EN : 1
2197 13:57:01.155858 MD32_EN : 0
2198 13:57:01.159322 ===================================
2199 13:57:01.162632 [ANA_INIT] >>>>>>>>>>>>>>
2200 13:57:01.163210 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 13:57:01.165656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 13:57:01.169775 ===================================
2203 13:57:01.172589 data_rate = 2400,PCW = 0X5b00
2204 13:57:01.175963 ===================================
2205 13:57:01.179107 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 13:57:01.185922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 13:57:01.192683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 13:57:01.196226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 13:57:01.199182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 13:57:01.202486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 13:57:01.205779 [ANA_INIT] flow start
2212 13:57:01.206433 [ANA_INIT] PLL >>>>>>>>
2213 13:57:01.209173 [ANA_INIT] PLL <<<<<<<<
2214 13:57:01.212436 [ANA_INIT] MIDPI >>>>>>>>
2215 13:57:01.212905 [ANA_INIT] MIDPI <<<<<<<<
2216 13:57:01.215844 [ANA_INIT] DLL >>>>>>>>
2217 13:57:01.219294 [ANA_INIT] DLL <<<<<<<<
2218 13:57:01.219766 [ANA_INIT] flow end
2219 13:57:01.225800 ============ LP4 DIFF to SE enter ============
2220 13:57:01.229719 ============ LP4 DIFF to SE exit ============
2221 13:57:01.232455 [ANA_INIT] <<<<<<<<<<<<<
2222 13:57:01.235605 [Flow] Enable top DCM control >>>>>
2223 13:57:01.236094 [Flow] Enable top DCM control <<<<<
2224 13:57:01.239077 Enable DLL master slave shuffle
2225 13:57:01.246121 ==============================================================
2226 13:57:01.249198 Gating Mode config
2227 13:57:01.252757 ==============================================================
2228 13:57:01.256245 Config description:
2229 13:57:01.266084 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 13:57:01.272512 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 13:57:01.276131 SELPH_MODE 0: By rank 1: By Phase
2232 13:57:01.282444 ==============================================================
2233 13:57:01.286058 GAT_TRACK_EN = 1
2234 13:57:01.289062 RX_GATING_MODE = 2
2235 13:57:01.289562 RX_GATING_TRACK_MODE = 2
2236 13:57:01.293004 SELPH_MODE = 1
2237 13:57:01.296123 PICG_EARLY_EN = 1
2238 13:57:01.299476 VALID_LAT_VALUE = 1
2239 13:57:01.306133 ==============================================================
2240 13:57:01.309535 Enter into Gating configuration >>>>
2241 13:57:01.312854 Exit from Gating configuration <<<<
2242 13:57:01.316137 Enter into DVFS_PRE_config >>>>>
2243 13:57:01.326228 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 13:57:01.329452 Exit from DVFS_PRE_config <<<<<
2245 13:57:01.333009 Enter into PICG configuration >>>>
2246 13:57:01.336139 Exit from PICG configuration <<<<
2247 13:57:01.339414 [RX_INPUT] configuration >>>>>
2248 13:57:01.342835 [RX_INPUT] configuration <<<<<
2249 13:57:01.346181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 13:57:01.352886 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 13:57:01.359669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 13:57:01.362842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 13:57:01.369630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 13:57:01.376639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 13:57:01.379804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 13:57:01.382744 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 13:57:01.389831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 13:57:01.393016 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 13:57:01.396347 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 13:57:01.402998 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 13:57:01.406314 ===================================
2262 13:57:01.406883 LPDDR4 DRAM CONFIGURATION
2263 13:57:01.409352 ===================================
2264 13:57:01.412945 EX_ROW_EN[0] = 0x0
2265 13:57:01.413415 EX_ROW_EN[1] = 0x0
2266 13:57:01.416377 LP4Y_EN = 0x0
2267 13:57:01.416848 WORK_FSP = 0x0
2268 13:57:01.419834 WL = 0x4
2269 13:57:01.420434 RL = 0x4
2270 13:57:01.422802 BL = 0x2
2271 13:57:01.423370 RPST = 0x0
2272 13:57:01.426399 RD_PRE = 0x0
2273 13:57:01.426871 WR_PRE = 0x1
2274 13:57:01.429678 WR_PST = 0x0
2275 13:57:01.433042 DBI_WR = 0x0
2276 13:57:01.433610 DBI_RD = 0x0
2277 13:57:01.436130 OTF = 0x1
2278 13:57:01.439777 ===================================
2279 13:57:01.443212 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 13:57:01.446338 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 13:57:01.449831 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 13:57:01.453069 ===================================
2283 13:57:01.456361 LPDDR4 DRAM CONFIGURATION
2284 13:57:01.459998 ===================================
2285 13:57:01.462723 EX_ROW_EN[0] = 0x10
2286 13:57:01.463231 EX_ROW_EN[1] = 0x0
2287 13:57:01.466520 LP4Y_EN = 0x0
2288 13:57:01.467083 WORK_FSP = 0x0
2289 13:57:01.469496 WL = 0x4
2290 13:57:01.470108 RL = 0x4
2291 13:57:01.473086 BL = 0x2
2292 13:57:01.473657 RPST = 0x0
2293 13:57:01.475918 RD_PRE = 0x0
2294 13:57:01.476374 WR_PRE = 0x1
2295 13:57:01.479179 WR_PST = 0x0
2296 13:57:01.479641 DBI_WR = 0x0
2297 13:57:01.482617 DBI_RD = 0x0
2298 13:57:01.486155 OTF = 0x1
2299 13:57:01.489571 ===================================
2300 13:57:01.492665 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 13:57:01.493126 ==
2302 13:57:01.496034 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 13:57:01.502976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 13:57:01.503533 ==
2305 13:57:01.503900 [Duty_Offset_Calibration]
2306 13:57:01.506291 B0:2 B1:0 CA:1
2307 13:57:01.506838
2308 13:57:01.509549 [DutyScan_Calibration_Flow] k_type=0
2309 13:57:01.518183
2310 13:57:01.518723 ==CLK 0==
2311 13:57:01.520945 Final CLK duty delay cell = -4
2312 13:57:01.524416 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2313 13:57:01.527899 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2314 13:57:01.530908 [-4] AVG Duty = 4953%(X100)
2315 13:57:01.531406
2316 13:57:01.534195 CH0 CLK Duty spec in!! Max-Min= 156%
2317 13:57:01.537837 [DutyScan_Calibration_Flow] ====Done====
2318 13:57:01.538327
2319 13:57:01.541127 [DutyScan_Calibration_Flow] k_type=1
2320 13:57:01.556465
2321 13:57:01.556919 ==DQS 0 ==
2322 13:57:01.560003 Final DQS duty delay cell = 0
2323 13:57:01.563191 [0] MAX Duty = 5187%(X100), DQS PI = 30
2324 13:57:01.566561 [0] MIN Duty = 4938%(X100), DQS PI = 0
2325 13:57:01.567017 [0] AVG Duty = 5062%(X100)
2326 13:57:01.570187
2327 13:57:01.570729 ==DQS 1 ==
2328 13:57:01.573262 Final DQS duty delay cell = -4
2329 13:57:01.576834 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2330 13:57:01.580071 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2331 13:57:01.583125 [-4] AVG Duty = 5015%(X100)
2332 13:57:01.583588
2333 13:57:01.586610 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2334 13:57:01.587067
2335 13:57:01.589844 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2336 13:57:01.593081 [DutyScan_Calibration_Flow] ====Done====
2337 13:57:01.593535
2338 13:57:01.596324 [DutyScan_Calibration_Flow] k_type=3
2339 13:57:01.613350
2340 13:57:01.613828 ==DQM 0 ==
2341 13:57:01.616734 Final DQM duty delay cell = 0
2342 13:57:01.620025 [0] MAX Duty = 5062%(X100), DQS PI = 24
2343 13:57:01.623614 [0] MIN Duty = 4813%(X100), DQS PI = 0
2344 13:57:01.624167 [0] AVG Duty = 4937%(X100)
2345 13:57:01.624531
2346 13:57:01.626624 ==DQM 1 ==
2347 13:57:01.630499 Final DQM duty delay cell = 0
2348 13:57:01.633614 [0] MAX Duty = 5187%(X100), DQS PI = 48
2349 13:57:01.637011 [0] MIN Duty = 5000%(X100), DQS PI = 22
2350 13:57:01.637565 [0] AVG Duty = 5093%(X100)
2351 13:57:01.637927
2352 13:57:01.643831 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2353 13:57:01.644470
2354 13:57:01.646910 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2355 13:57:01.650408 [DutyScan_Calibration_Flow] ====Done====
2356 13:57:01.650865
2357 13:57:01.653550 [DutyScan_Calibration_Flow] k_type=2
2358 13:57:01.669172
2359 13:57:01.669721 ==DQ 0 ==
2360 13:57:01.672387 Final DQ duty delay cell = -4
2361 13:57:01.675722 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2362 13:57:01.679193 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2363 13:57:01.682534 [-4] AVG Duty = 4953%(X100)
2364 13:57:01.683112
2365 13:57:01.683492 ==DQ 1 ==
2366 13:57:01.686033 Final DQ duty delay cell = 0
2367 13:57:01.689043 [0] MAX Duty = 4969%(X100), DQS PI = 58
2368 13:57:01.692755 [0] MIN Duty = 4907%(X100), DQS PI = 0
2369 13:57:01.693488 [0] AVG Duty = 4938%(X100)
2370 13:57:01.695889
2371 13:57:01.699046 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2372 13:57:01.699520
2373 13:57:01.702338 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2374 13:57:01.705716 [DutyScan_Calibration_Flow] ====Done====
2375 13:57:01.706242 ==
2376 13:57:01.708878 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 13:57:01.712078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 13:57:01.712550 ==
2379 13:57:01.715694 [Duty_Offset_Calibration]
2380 13:57:01.716165 B0:0 B1:-1 CA:2
2381 13:57:01.716537
2382 13:57:01.719120 [DutyScan_Calibration_Flow] k_type=0
2383 13:57:01.729519
2384 13:57:01.730132 ==CLK 0==
2385 13:57:01.732667 Final CLK duty delay cell = 0
2386 13:57:01.736314 [0] MAX Duty = 5156%(X100), DQS PI = 16
2387 13:57:01.739167 [0] MIN Duty = 4938%(X100), DQS PI = 44
2388 13:57:01.739639 [0] AVG Duty = 5047%(X100)
2389 13:57:01.742588
2390 13:57:01.746097 CH1 CLK Duty spec in!! Max-Min= 218%
2391 13:57:01.749498 [DutyScan_Calibration_Flow] ====Done====
2392 13:57:01.750128
2393 13:57:01.752316 [DutyScan_Calibration_Flow] k_type=1
2394 13:57:01.769091
2395 13:57:01.769667 ==DQS 0 ==
2396 13:57:01.772056 Final DQS duty delay cell = 0
2397 13:57:01.775450 [0] MAX Duty = 5093%(X100), DQS PI = 26
2398 13:57:01.779005 [0] MIN Duty = 4969%(X100), DQS PI = 0
2399 13:57:01.779589 [0] AVG Duty = 5031%(X100)
2400 13:57:01.782055
2401 13:57:01.782520 ==DQS 1 ==
2402 13:57:01.785585 Final DQS duty delay cell = 0
2403 13:57:01.788601 [0] MAX Duty = 5156%(X100), DQS PI = 0
2404 13:57:01.792351 [0] MIN Duty = 4844%(X100), DQS PI = 34
2405 13:57:01.792920 [0] AVG Duty = 5000%(X100)
2406 13:57:01.793293
2407 13:57:01.795679 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2408 13:57:01.799055
2409 13:57:01.802316 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2410 13:57:01.805662 [DutyScan_Calibration_Flow] ====Done====
2411 13:57:01.806154
2412 13:57:01.809115 [DutyScan_Calibration_Flow] k_type=3
2413 13:57:01.825875
2414 13:57:01.826466 ==DQM 0 ==
2415 13:57:01.829443 Final DQM duty delay cell = 4
2416 13:57:01.832644 [4] MAX Duty = 5124%(X100), DQS PI = 22
2417 13:57:01.836086 [4] MIN Duty = 4938%(X100), DQS PI = 48
2418 13:57:01.839425 [4] AVG Duty = 5031%(X100)
2419 13:57:01.839995
2420 13:57:01.840365 ==DQM 1 ==
2421 13:57:01.842598 Final DQM duty delay cell = 0
2422 13:57:01.845996 [0] MAX Duty = 5249%(X100), DQS PI = 0
2423 13:57:01.849581 [0] MIN Duty = 4875%(X100), DQS PI = 36
2424 13:57:01.850187 [0] AVG Duty = 5062%(X100)
2425 13:57:01.852776
2426 13:57:01.855811 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2427 13:57:01.856280
2428 13:57:01.859505 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2429 13:57:01.862768 [DutyScan_Calibration_Flow] ====Done====
2430 13:57:01.863335
2431 13:57:01.866019 [DutyScan_Calibration_Flow] k_type=2
2432 13:57:01.882697
2433 13:57:01.883263 ==DQ 0 ==
2434 13:57:01.885626 Final DQ duty delay cell = 0
2435 13:57:01.889220 [0] MAX Duty = 5062%(X100), DQS PI = 22
2436 13:57:01.892624 [0] MIN Duty = 4938%(X100), DQS PI = 0
2437 13:57:01.893204 [0] AVG Duty = 5000%(X100)
2438 13:57:01.893683
2439 13:57:01.896080 ==DQ 1 ==
2440 13:57:01.899379 Final DQ duty delay cell = 0
2441 13:57:01.902680 [0] MAX Duty = 5031%(X100), DQS PI = 0
2442 13:57:01.905898 [0] MIN Duty = 4813%(X100), DQS PI = 34
2443 13:57:01.906418 [0] AVG Duty = 4922%(X100)
2444 13:57:01.906889
2445 13:57:01.908936 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2446 13:57:01.909414
2447 13:57:01.912841 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2448 13:57:01.919132 [DutyScan_Calibration_Flow] ====Done====
2449 13:57:01.922600 nWR fixed to 30
2450 13:57:01.923177 [ModeRegInit_LP4] CH0 RK0
2451 13:57:01.925828 [ModeRegInit_LP4] CH0 RK1
2452 13:57:01.929194 [ModeRegInit_LP4] CH1 RK0
2453 13:57:01.929776 [ModeRegInit_LP4] CH1 RK1
2454 13:57:01.932448 match AC timing 7
2455 13:57:01.936014 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 13:57:01.938937 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 13:57:01.945597 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 13:57:01.949229 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 13:57:01.956050 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 13:57:01.956630 ==
2461 13:57:01.959502 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 13:57:01.962527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 13:57:01.962997 ==
2464 13:57:01.968976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 13:57:01.972150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2466 13:57:01.982660 [CA 0] Center 38 (7~69) winsize 63
2467 13:57:01.985582 [CA 1] Center 38 (7~69) winsize 63
2468 13:57:01.989263 [CA 2] Center 34 (4~65) winsize 62
2469 13:57:01.992566 [CA 3] Center 34 (4~65) winsize 62
2470 13:57:01.995651 [CA 4] Center 33 (3~64) winsize 62
2471 13:57:01.998764 [CA 5] Center 33 (3~63) winsize 61
2472 13:57:01.999251
2473 13:57:02.002329 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2474 13:57:02.002903
2475 13:57:02.005357 [CATrainingPosCal] consider 1 rank data
2476 13:57:02.008741 u2DelayCellTimex100 = 270/100 ps
2477 13:57:02.012071 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2478 13:57:02.015506 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2479 13:57:02.021904 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
2480 13:57:02.025680 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2481 13:57:02.028650 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2482 13:57:02.032817 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2483 13:57:02.033392
2484 13:57:02.035653 CA PerBit enable=1, Macro0, CA PI delay=33
2485 13:57:02.036227
2486 13:57:02.038959 [CBTSetCACLKResult] CA Dly = 33
2487 13:57:02.039535 CS Dly: 6 (0~37)
2488 13:57:02.042247 ==
2489 13:57:02.042821 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 13:57:02.048977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 13:57:02.049557 ==
2492 13:57:02.051987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 13:57:02.059058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2494 13:57:02.068128 [CA 0] Center 38 (7~69) winsize 63
2495 13:57:02.071062 [CA 1] Center 38 (7~69) winsize 63
2496 13:57:02.074835 [CA 2] Center 35 (5~66) winsize 62
2497 13:57:02.077925 [CA 3] Center 35 (4~66) winsize 63
2498 13:57:02.081196 [CA 4] Center 34 (3~65) winsize 63
2499 13:57:02.084821 [CA 5] Center 33 (3~63) winsize 61
2500 13:57:02.085407
2501 13:57:02.088025 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2502 13:57:02.088602
2503 13:57:02.091644 [CATrainingPosCal] consider 2 rank data
2504 13:57:02.094883 u2DelayCellTimex100 = 270/100 ps
2505 13:57:02.098220 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2506 13:57:02.101264 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2507 13:57:02.104942 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2508 13:57:02.111633 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2509 13:57:02.114954 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2510 13:57:02.118168 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2511 13:57:02.118640
2512 13:57:02.121541 CA PerBit enable=1, Macro0, CA PI delay=33
2513 13:57:02.122141
2514 13:57:02.124935 [CBTSetCACLKResult] CA Dly = 33
2515 13:57:02.125503 CS Dly: 7 (0~39)
2516 13:57:02.125881
2517 13:57:02.127921 ----->DramcWriteLeveling(PI) begin...
2518 13:57:02.128443 ==
2519 13:57:02.131051 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 13:57:02.137777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 13:57:02.138291 ==
2522 13:57:02.141655 Write leveling (Byte 0): 33 => 33
2523 13:57:02.144943 Write leveling (Byte 1): 31 => 31
2524 13:57:02.145511 DramcWriteLeveling(PI) end<-----
2525 13:57:02.145889
2526 13:57:02.148042 ==
2527 13:57:02.151792 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 13:57:02.155228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 13:57:02.155803 ==
2530 13:57:02.157997 [Gating] SW mode calibration
2531 13:57:02.165335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 13:57:02.168011 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 13:57:02.174708 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2534 13:57:02.178325 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2535 13:57:02.182037 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 13:57:02.188379 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 13:57:02.191825 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 13:57:02.194854 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 13:57:02.202043 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2540 13:57:02.204980 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2541 13:57:02.208321 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2542 13:57:02.211620 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 13:57:02.218345 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 13:57:02.221665 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 13:57:02.225161 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 13:57:02.231791 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 13:57:02.235001 1 0 24 | B1->B0 | 2323 3736 | 0 1 | (0 0) (0 0)
2548 13:57:02.238430 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2549 13:57:02.245035 1 1 0 | B1->B0 | 3636 4646 | 1 0 | (1 1) (0 0)
2550 13:57:02.248182 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 13:57:02.251785 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 13:57:02.258398 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 13:57:02.261622 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 13:57:02.264887 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 13:57:02.271836 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 13:57:02.274821 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2557 13:57:02.278351 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2558 13:57:02.284899 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:57:02.288196 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:57:02.291315 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:57:02.294845 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:57:02.301610 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:57:02.304811 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:57:02.308458 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:57:02.314734 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:57:02.318004 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:57:02.321332 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 13:57:02.328040 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 13:57:02.331674 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:57:02.334666 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 13:57:02.341598 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2572 13:57:02.344854 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 13:57:02.348112 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 13:57:02.351636 Total UI for P1: 0, mck2ui 16
2575 13:57:02.354936 best dqsien dly found for B0: ( 1, 3, 26)
2576 13:57:02.361516 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 13:57:02.361763 Total UI for P1: 0, mck2ui 16
2578 13:57:02.368070 best dqsien dly found for B1: ( 1, 4, 0)
2579 13:57:02.371655 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2580 13:57:02.374790 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2581 13:57:02.375035
2582 13:57:02.378259 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2583 13:57:02.381847 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2584 13:57:02.384612 [Gating] SW calibration Done
2585 13:57:02.384855 ==
2586 13:57:02.388339 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 13:57:02.391654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 13:57:02.391898 ==
2589 13:57:02.392092 RX Vref Scan: 0
2590 13:57:02.394673
2591 13:57:02.394914 RX Vref 0 -> 0, step: 1
2592 13:57:02.395109
2593 13:57:02.398114 RX Delay -40 -> 252, step: 8
2594 13:57:02.401500 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2595 13:57:02.405265 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2596 13:57:02.411782 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2597 13:57:02.415143 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2598 13:57:02.418508 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2599 13:57:02.422164 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2600 13:57:02.425450 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2601 13:57:02.432467 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2602 13:57:02.435674 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2603 13:57:02.438537 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2604 13:57:02.442389 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2605 13:57:02.445864 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2606 13:57:02.449098 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2607 13:57:02.455539 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2608 13:57:02.458945 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2609 13:57:02.462433 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2610 13:57:02.463003 ==
2611 13:57:02.465660 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 13:57:02.468974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 13:57:02.472157 ==
2614 13:57:02.472722 DQS Delay:
2615 13:57:02.473097 DQS0 = 0, DQS1 = 0
2616 13:57:02.475500 DQM Delay:
2617 13:57:02.475975 DQM0 = 122, DQM1 = 110
2618 13:57:02.479386 DQ Delay:
2619 13:57:02.482585 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2620 13:57:02.485625 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2621 13:57:02.489039 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2622 13:57:02.492549 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2623 13:57:02.493124
2624 13:57:02.493501
2625 13:57:02.493850 ==
2626 13:57:02.495742 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 13:57:02.498868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 13:57:02.499434 ==
2629 13:57:02.499812
2630 13:57:02.500162
2631 13:57:02.502056 TX Vref Scan disable
2632 13:57:02.505508 == TX Byte 0 ==
2633 13:57:02.508565 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2634 13:57:02.511967 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2635 13:57:02.515356 == TX Byte 1 ==
2636 13:57:02.518763 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2637 13:57:02.522183 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2638 13:57:02.522657 ==
2639 13:57:02.525458 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 13:57:02.528444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 13:57:02.532151 ==
2642 13:57:02.542392 TX Vref=22, minBit 0, minWin=24, winSum=399
2643 13:57:02.545749 TX Vref=24, minBit 4, minWin=23, winSum=402
2644 13:57:02.548834 TX Vref=26, minBit 4, minWin=24, winSum=409
2645 13:57:02.552429 TX Vref=28, minBit 0, minWin=25, winSum=415
2646 13:57:02.555566 TX Vref=30, minBit 1, minWin=25, winSum=416
2647 13:57:02.558835 TX Vref=32, minBit 1, minWin=25, winSum=415
2648 13:57:02.565909 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 30
2649 13:57:02.566519
2650 13:57:02.569225 Final TX Range 1 Vref 30
2651 13:57:02.569795
2652 13:57:02.570229 ==
2653 13:57:02.571924 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 13:57:02.575505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 13:57:02.575980 ==
2656 13:57:02.576354
2657 13:57:02.576701
2658 13:57:02.578893 TX Vref Scan disable
2659 13:57:02.582691 == TX Byte 0 ==
2660 13:57:02.585633 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2661 13:57:02.589092 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2662 13:57:02.592056 == TX Byte 1 ==
2663 13:57:02.595844 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2664 13:57:02.598667 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2665 13:57:02.599144
2666 13:57:02.602390 [DATLAT]
2667 13:57:02.602953 Freq=1200, CH0 RK0
2668 13:57:02.603329
2669 13:57:02.605816 DATLAT Default: 0xd
2670 13:57:02.606421 0, 0xFFFF, sum = 0
2671 13:57:02.608834 1, 0xFFFF, sum = 0
2672 13:57:02.609313 2, 0xFFFF, sum = 0
2673 13:57:02.612313 3, 0xFFFF, sum = 0
2674 13:57:02.612832 4, 0xFFFF, sum = 0
2675 13:57:02.615502 5, 0xFFFF, sum = 0
2676 13:57:02.616080 6, 0xFFFF, sum = 0
2677 13:57:02.618726 7, 0xFFFF, sum = 0
2678 13:57:02.619203 8, 0xFFFF, sum = 0
2679 13:57:02.622279 9, 0xFFFF, sum = 0
2680 13:57:02.625436 10, 0xFFFF, sum = 0
2681 13:57:02.625912 11, 0xFFFF, sum = 0
2682 13:57:02.628549 12, 0x0, sum = 1
2683 13:57:02.629020 13, 0x0, sum = 2
2684 13:57:02.629396 14, 0x0, sum = 3
2685 13:57:02.631917 15, 0x0, sum = 4
2686 13:57:02.632420 best_step = 13
2687 13:57:02.632790
2688 13:57:02.633131 ==
2689 13:57:02.635541 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 13:57:02.642118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 13:57:02.642594 ==
2692 13:57:02.642988 RX Vref Scan: 1
2693 13:57:02.643329
2694 13:57:02.645576 Set Vref Range= 32 -> 127
2695 13:57:02.646071
2696 13:57:02.648883 RX Vref 32 -> 127, step: 1
2697 13:57:02.649350
2698 13:57:02.652569 RX Delay -13 -> 252, step: 4
2699 13:57:02.653143
2700 13:57:02.655626 Set Vref, RX VrefLevel [Byte0]: 32
2701 13:57:02.659116 [Byte1]: 32
2702 13:57:02.659585
2703 13:57:02.662242 Set Vref, RX VrefLevel [Byte0]: 33
2704 13:57:02.665739 [Byte1]: 33
2705 13:57:02.666366
2706 13:57:02.669008 Set Vref, RX VrefLevel [Byte0]: 34
2707 13:57:02.672168 [Byte1]: 34
2708 13:57:02.676197
2709 13:57:02.676694 Set Vref, RX VrefLevel [Byte0]: 35
2710 13:57:02.679639 [Byte1]: 35
2711 13:57:02.684062
2712 13:57:02.684632 Set Vref, RX VrefLevel [Byte0]: 36
2713 13:57:02.687557 [Byte1]: 36
2714 13:57:02.691612
2715 13:57:02.692079 Set Vref, RX VrefLevel [Byte0]: 37
2716 13:57:02.695353 [Byte1]: 37
2717 13:57:02.699664
2718 13:57:02.700232 Set Vref, RX VrefLevel [Byte0]: 38
2719 13:57:02.703218 [Byte1]: 38
2720 13:57:02.707731
2721 13:57:02.708326 Set Vref, RX VrefLevel [Byte0]: 39
2722 13:57:02.711352 [Byte1]: 39
2723 13:57:02.715581
2724 13:57:02.716152 Set Vref, RX VrefLevel [Byte0]: 40
2725 13:57:02.718786 [Byte1]: 40
2726 13:57:02.723703
2727 13:57:02.724164 Set Vref, RX VrefLevel [Byte0]: 41
2728 13:57:02.726474 [Byte1]: 41
2729 13:57:02.731586
2730 13:57:02.732157 Set Vref, RX VrefLevel [Byte0]: 42
2731 13:57:02.734450 [Byte1]: 42
2732 13:57:02.738943
2733 13:57:02.739427 Set Vref, RX VrefLevel [Byte0]: 43
2734 13:57:02.742482 [Byte1]: 43
2735 13:57:02.747100
2736 13:57:02.747719 Set Vref, RX VrefLevel [Byte0]: 44
2737 13:57:02.750063 [Byte1]: 44
2738 13:57:02.754678
2739 13:57:02.755141 Set Vref, RX VrefLevel [Byte0]: 45
2740 13:57:02.758399 [Byte1]: 45
2741 13:57:02.762913
2742 13:57:02.763484 Set Vref, RX VrefLevel [Byte0]: 46
2743 13:57:02.766144 [Byte1]: 46
2744 13:57:02.770609
2745 13:57:02.771185 Set Vref, RX VrefLevel [Byte0]: 47
2746 13:57:02.774251 [Byte1]: 47
2747 13:57:02.778548
2748 13:57:02.779117 Set Vref, RX VrefLevel [Byte0]: 48
2749 13:57:02.781893 [Byte1]: 48
2750 13:57:02.786451
2751 13:57:02.787020 Set Vref, RX VrefLevel [Byte0]: 49
2752 13:57:02.789696 [Byte1]: 49
2753 13:57:02.794562
2754 13:57:02.795139 Set Vref, RX VrefLevel [Byte0]: 50
2755 13:57:02.797904 [Byte1]: 50
2756 13:57:02.802378
2757 13:57:02.802948 Set Vref, RX VrefLevel [Byte0]: 51
2758 13:57:02.805574 [Byte1]: 51
2759 13:57:02.810318
2760 13:57:02.810888 Set Vref, RX VrefLevel [Byte0]: 52
2761 13:57:02.813473 [Byte1]: 52
2762 13:57:02.818237
2763 13:57:02.818807 Set Vref, RX VrefLevel [Byte0]: 53
2764 13:57:02.821143 [Byte1]: 53
2765 13:57:02.826292
2766 13:57:02.826876 Set Vref, RX VrefLevel [Byte0]: 54
2767 13:57:02.829128 [Byte1]: 54
2768 13:57:02.834004
2769 13:57:02.834492 Set Vref, RX VrefLevel [Byte0]: 55
2770 13:57:02.837669 [Byte1]: 55
2771 13:57:02.841768
2772 13:57:02.842387 Set Vref, RX VrefLevel [Byte0]: 56
2773 13:57:02.844936 [Byte1]: 56
2774 13:57:02.849610
2775 13:57:02.850206 Set Vref, RX VrefLevel [Byte0]: 57
2776 13:57:02.853154 [Byte1]: 57
2777 13:57:02.857764
2778 13:57:02.858364 Set Vref, RX VrefLevel [Byte0]: 58
2779 13:57:02.861055 [Byte1]: 58
2780 13:57:02.865615
2781 13:57:02.866222 Set Vref, RX VrefLevel [Byte0]: 59
2782 13:57:02.869189 [Byte1]: 59
2783 13:57:02.873793
2784 13:57:02.874404 Set Vref, RX VrefLevel [Byte0]: 60
2785 13:57:02.877286 [Byte1]: 60
2786 13:57:02.881588
2787 13:57:02.882192 Set Vref, RX VrefLevel [Byte0]: 61
2788 13:57:02.885120 [Byte1]: 61
2789 13:57:02.889153
2790 13:57:02.889716 Set Vref, RX VrefLevel [Byte0]: 62
2791 13:57:02.892507 [Byte1]: 62
2792 13:57:02.897224
2793 13:57:02.897798 Set Vref, RX VrefLevel [Byte0]: 63
2794 13:57:02.900617 [Byte1]: 63
2795 13:57:02.905424
2796 13:57:02.906021 Set Vref, RX VrefLevel [Byte0]: 64
2797 13:57:02.908281 [Byte1]: 64
2798 13:57:02.912868
2799 13:57:02.913440 Set Vref, RX VrefLevel [Byte0]: 65
2800 13:57:02.916164 [Byte1]: 65
2801 13:57:02.920545
2802 13:57:02.921072 Set Vref, RX VrefLevel [Byte0]: 66
2803 13:57:02.924426 [Byte1]: 66
2804 13:57:02.928529
2805 13:57:02.929107 Set Vref, RX VrefLevel [Byte0]: 67
2806 13:57:02.931821 [Byte1]: 67
2807 13:57:02.936387
2808 13:57:02.936954 Set Vref, RX VrefLevel [Byte0]: 68
2809 13:57:02.939865 [Byte1]: 68
2810 13:57:02.944464
2811 13:57:02.944991 Set Vref, RX VrefLevel [Byte0]: 69
2812 13:57:02.950561 [Byte1]: 69
2813 13:57:02.951032
2814 13:57:02.954288 Set Vref, RX VrefLevel [Byte0]: 70
2815 13:57:02.957417 [Byte1]: 70
2816 13:57:02.957890
2817 13:57:02.961433 Set Vref, RX VrefLevel [Byte0]: 71
2818 13:57:02.964131 [Byte1]: 71
2819 13:57:02.967948
2820 13:57:02.968528 Final RX Vref Byte 0 = 60 to rank0
2821 13:57:02.971711 Final RX Vref Byte 1 = 50 to rank0
2822 13:57:02.974985 Final RX Vref Byte 0 = 60 to rank1
2823 13:57:02.978265 Final RX Vref Byte 1 = 50 to rank1==
2824 13:57:02.981435 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 13:57:02.988273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 13:57:02.988860 ==
2827 13:57:02.989237 DQS Delay:
2828 13:57:02.989582 DQS0 = 0, DQS1 = 0
2829 13:57:02.991278 DQM Delay:
2830 13:57:02.991745 DQM0 = 123, DQM1 = 109
2831 13:57:02.994322 DQ Delay:
2832 13:57:02.998103 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2833 13:57:03.001587 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2834 13:57:03.004779 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2835 13:57:03.008006 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2836 13:57:03.008596
2837 13:57:03.008974
2838 13:57:03.014568 [DQSOSCAuto] RK0, (LSB)MR18= 0x805, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2839 13:57:03.018191 CH0 RK0: MR19=404, MR18=805
2840 13:57:03.024696 CH0_RK0: MR19=0x404, MR18=0x805, DQSOSC=406, MR23=63, INC=39, DEC=26
2841 13:57:03.025283
2842 13:57:03.028533 ----->DramcWriteLeveling(PI) begin...
2843 13:57:03.029117 ==
2844 13:57:03.031784 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 13:57:03.034767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 13:57:03.035241 ==
2847 13:57:03.038084 Write leveling (Byte 0): 35 => 35
2848 13:57:03.041354 Write leveling (Byte 1): 30 => 30
2849 13:57:03.044471 DramcWriteLeveling(PI) end<-----
2850 13:57:03.044938
2851 13:57:03.045306 ==
2852 13:57:03.048107 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 13:57:03.051748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 13:57:03.054716 ==
2855 13:57:03.055284 [Gating] SW mode calibration
2856 13:57:03.064707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 13:57:03.068166 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 13:57:03.071893 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2859 13:57:03.078079 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 13:57:03.081646 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 13:57:03.084721 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 13:57:03.091230 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 13:57:03.094866 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 13:57:03.098487 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2865 13:57:03.105020 0 15 28 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 0)
2866 13:57:03.108057 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 13:57:03.111272 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 13:57:03.117985 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 13:57:03.121531 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 13:57:03.124483 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 13:57:03.131269 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 13:57:03.134822 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2873 13:57:03.138380 1 0 28 | B1->B0 | 3333 3b3b | 0 1 | (0 0) (0 0)
2874 13:57:03.141562 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 13:57:03.147963 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 13:57:03.151383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 13:57:03.154628 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 13:57:03.161471 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 13:57:03.164669 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 13:57:03.168267 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 13:57:03.174946 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 13:57:03.178189 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 13:57:03.181414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 13:57:03.188434 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 13:57:03.191718 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 13:57:03.195247 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 13:57:03.201593 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 13:57:03.204884 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:57:03.208191 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 13:57:03.214901 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 13:57:03.218248 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 13:57:03.221530 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 13:57:03.225298 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 13:57:03.232045 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 13:57:03.234895 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 13:57:03.238532 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 13:57:03.245105 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2898 13:57:03.248418 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 13:57:03.251899 Total UI for P1: 0, mck2ui 16
2900 13:57:03.255140 best dqsien dly found for B0: ( 1, 3, 26)
2901 13:57:03.258311 Total UI for P1: 0, mck2ui 16
2902 13:57:03.261607 best dqsien dly found for B1: ( 1, 3, 28)
2903 13:57:03.265113 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2904 13:57:03.268289 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2905 13:57:03.268756
2906 13:57:03.272119 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2907 13:57:03.274865 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2908 13:57:03.278431 [Gating] SW calibration Done
2909 13:57:03.278992 ==
2910 13:57:03.281449 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 13:57:03.284690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 13:57:03.288086 ==
2913 13:57:03.288546 RX Vref Scan: 0
2914 13:57:03.288910
2915 13:57:03.291670 RX Vref 0 -> 0, step: 1
2916 13:57:03.292150
2917 13:57:03.292539 RX Delay -40 -> 252, step: 8
2918 13:57:03.298866 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2919 13:57:03.301881 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2920 13:57:03.305162 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2921 13:57:03.308676 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2922 13:57:03.311860 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2923 13:57:03.318468 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2924 13:57:03.321970 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2925 13:57:03.325209 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2926 13:57:03.328437 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2927 13:57:03.332261 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2928 13:57:03.338768 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2929 13:57:03.341604 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2930 13:57:03.344890 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2931 13:57:03.348955 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2932 13:57:03.351922 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2933 13:57:03.358615 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2934 13:57:03.359192 ==
2935 13:57:03.362085 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 13:57:03.365222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 13:57:03.365803 ==
2938 13:57:03.366227 DQS Delay:
2939 13:57:03.368865 DQS0 = 0, DQS1 = 0
2940 13:57:03.369537 DQM Delay:
2941 13:57:03.371733 DQM0 = 119, DQM1 = 108
2942 13:57:03.372204 DQ Delay:
2943 13:57:03.375510 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =111
2944 13:57:03.378345 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =123
2945 13:57:03.381731 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2946 13:57:03.385455 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2947 13:57:03.385928
2948 13:57:03.386341
2949 13:57:03.386687 ==
2950 13:57:03.388369 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 13:57:03.395168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 13:57:03.395757 ==
2953 13:57:03.396133
2954 13:57:03.396476
2955 13:57:03.396808 TX Vref Scan disable
2956 13:57:03.399095 == TX Byte 0 ==
2957 13:57:03.402475 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2958 13:57:03.406119 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2959 13:57:03.409109 == TX Byte 1 ==
2960 13:57:03.412848 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2961 13:57:03.415923 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2962 13:57:03.418929 ==
2963 13:57:03.422489 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 13:57:03.426069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 13:57:03.426543 ==
2966 13:57:03.437363 TX Vref=22, minBit 2, minWin=23, winSum=402
2967 13:57:03.440640 TX Vref=24, minBit 0, minWin=24, winSum=408
2968 13:57:03.444055 TX Vref=26, minBit 3, minWin=24, winSum=408
2969 13:57:03.447606 TX Vref=28, minBit 1, minWin=24, winSum=410
2970 13:57:03.450625 TX Vref=30, minBit 3, minWin=25, winSum=419
2971 13:57:03.454124 TX Vref=32, minBit 0, minWin=25, winSum=411
2972 13:57:03.461068 [TxChooseVref] Worse bit 3, Min win 25, Win sum 419, Final Vref 30
2973 13:57:03.461638
2974 13:57:03.464234 Final TX Range 1 Vref 30
2975 13:57:03.464706
2976 13:57:03.465076 ==
2977 13:57:03.467503 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 13:57:03.470435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 13:57:03.470908 ==
2980 13:57:03.471341
2981 13:57:03.471703
2982 13:57:03.473994 TX Vref Scan disable
2983 13:57:03.477296 == TX Byte 0 ==
2984 13:57:03.480576 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2985 13:57:03.484392 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2986 13:57:03.487329 == TX Byte 1 ==
2987 13:57:03.490762 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2988 13:57:03.493920 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2989 13:57:03.494429
2990 13:57:03.497221 [DATLAT]
2991 13:57:03.497733 Freq=1200, CH0 RK1
2992 13:57:03.498180
2993 13:57:03.500894 DATLAT Default: 0xd
2994 13:57:03.501474 0, 0xFFFF, sum = 0
2995 13:57:03.504036 1, 0xFFFF, sum = 0
2996 13:57:03.504606 2, 0xFFFF, sum = 0
2997 13:57:03.507528 3, 0xFFFF, sum = 0
2998 13:57:03.508097 4, 0xFFFF, sum = 0
2999 13:57:03.510853 5, 0xFFFF, sum = 0
3000 13:57:03.511408 6, 0xFFFF, sum = 0
3001 13:57:03.514693 7, 0xFFFF, sum = 0
3002 13:57:03.515321 8, 0xFFFF, sum = 0
3003 13:57:03.517567 9, 0xFFFF, sum = 0
3004 13:57:03.520522 10, 0xFFFF, sum = 0
3005 13:57:03.521049 11, 0xFFFF, sum = 0
3006 13:57:03.523757 12, 0x0, sum = 1
3007 13:57:03.524225 13, 0x0, sum = 2
3008 13:57:03.524600 14, 0x0, sum = 3
3009 13:57:03.527414 15, 0x0, sum = 4
3010 13:57:03.527985 best_step = 13
3011 13:57:03.528352
3012 13:57:03.530480 ==
3013 13:57:03.530940 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 13:57:03.537478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 13:57:03.538092 ==
3016 13:57:03.538469 RX Vref Scan: 0
3017 13:57:03.538808
3018 13:57:03.540699 RX Vref 0 -> 0, step: 1
3019 13:57:03.541161
3020 13:57:03.544079 RX Delay -21 -> 252, step: 4
3021 13:57:03.547669 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3022 13:57:03.550442 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3023 13:57:03.557528 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3024 13:57:03.560845 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3025 13:57:03.564235 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3026 13:57:03.567393 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3027 13:57:03.570731 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3028 13:57:03.577653 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3029 13:57:03.580398 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3030 13:57:03.584191 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3031 13:57:03.587276 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3032 13:57:03.590671 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3033 13:57:03.597411 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3034 13:57:03.600636 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3035 13:57:03.604260 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3036 13:57:03.607331 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3037 13:57:03.607899 ==
3038 13:57:03.610467 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 13:57:03.617884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 13:57:03.618524 ==
3041 13:57:03.618948 DQS Delay:
3042 13:57:03.619292 DQS0 = 0, DQS1 = 0
3043 13:57:03.620467 DQM Delay:
3044 13:57:03.620926 DQM0 = 119, DQM1 = 108
3045 13:57:03.623804 DQ Delay:
3046 13:57:03.627630 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3047 13:57:03.631293 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3048 13:57:03.634245 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3049 13:57:03.637566 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =114
3050 13:57:03.638187
3051 13:57:03.638595
3052 13:57:03.644134 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3053 13:57:03.647393 CH0 RK1: MR19=403, MR18=BF3
3054 13:57:03.654251 CH0_RK1: MR19=0x403, MR18=0xBF3, DQSOSC=405, MR23=63, INC=39, DEC=26
3055 13:57:03.657475 [RxdqsGatingPostProcess] freq 1200
3056 13:57:03.664132 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 13:57:03.664685 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 13:57:03.667518 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 13:57:03.670890 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 13:57:03.674093 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 13:57:03.677460 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 13:57:03.681189 best DQS1 dly(2T, 0.5T) = (0, 11)
3063 13:57:03.684321 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 13:57:03.687952 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3065 13:57:03.690890 Pre-setting of DQS Precalculation
3066 13:57:03.694593 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 13:57:03.697543 ==
3068 13:57:03.698048 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 13:57:03.704068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 13:57:03.704637 ==
3071 13:57:03.707552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 13:57:03.714049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3073 13:57:03.723289 [CA 0] Center 37 (7~67) winsize 61
3074 13:57:03.726284 [CA 1] Center 37 (7~68) winsize 62
3075 13:57:03.730162 [CA 2] Center 34 (4~65) winsize 62
3076 13:57:03.733068 [CA 3] Center 33 (3~64) winsize 62
3077 13:57:03.736910 [CA 4] Center 33 (3~64) winsize 62
3078 13:57:03.739728 [CA 5] Center 33 (3~63) winsize 61
3079 13:57:03.740194
3080 13:57:03.743117 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3081 13:57:03.743701
3082 13:57:03.746836 [CATrainingPosCal] consider 1 rank data
3083 13:57:03.750228 u2DelayCellTimex100 = 270/100 ps
3084 13:57:03.753264 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3085 13:57:03.756750 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 13:57:03.763388 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3087 13:57:03.766698 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3088 13:57:03.770371 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3089 13:57:03.773459 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3090 13:57:03.774078
3091 13:57:03.776671 CA PerBit enable=1, Macro0, CA PI delay=33
3092 13:57:03.777157
3093 13:57:03.780132 [CBTSetCACLKResult] CA Dly = 33
3094 13:57:03.780696 CS Dly: 5 (0~36)
3095 13:57:03.781067 ==
3096 13:57:03.783623 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 13:57:03.790127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 13:57:03.790691 ==
3099 13:57:03.793221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 13:57:03.799652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3101 13:57:03.808920 [CA 0] Center 37 (7~68) winsize 62
3102 13:57:03.812183 [CA 1] Center 37 (7~68) winsize 62
3103 13:57:03.815196 [CA 2] Center 35 (5~66) winsize 62
3104 13:57:03.818899 [CA 3] Center 34 (4~64) winsize 61
3105 13:57:03.822024 [CA 4] Center 34 (4~64) winsize 61
3106 13:57:03.825378 [CA 5] Center 33 (3~64) winsize 62
3107 13:57:03.825842
3108 13:57:03.828891 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 13:57:03.829447
3110 13:57:03.832160 [CATrainingPosCal] consider 2 rank data
3111 13:57:03.835805 u2DelayCellTimex100 = 270/100 ps
3112 13:57:03.838635 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3113 13:57:03.842111 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3114 13:57:03.848957 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3115 13:57:03.852443 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 13:57:03.855597 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3117 13:57:03.858862 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3118 13:57:03.859431
3119 13:57:03.862411 CA PerBit enable=1, Macro0, CA PI delay=33
3120 13:57:03.862983
3121 13:57:03.865591 [CBTSetCACLKResult] CA Dly = 33
3122 13:57:03.866195 CS Dly: 6 (0~38)
3123 13:57:03.866572
3124 13:57:03.868991 ----->DramcWriteLeveling(PI) begin...
3125 13:57:03.869568 ==
3126 13:57:03.872192 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 13:57:03.879209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 13:57:03.879777 ==
3129 13:57:03.882604 Write leveling (Byte 0): 23 => 23
3130 13:57:03.885856 Write leveling (Byte 1): 28 => 28
3131 13:57:03.886476 DramcWriteLeveling(PI) end<-----
3132 13:57:03.886846
3133 13:57:03.888975 ==
3134 13:57:03.892478 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 13:57:03.895861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 13:57:03.896428 ==
3137 13:57:03.898809 [Gating] SW mode calibration
3138 13:57:03.905631 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 13:57:03.909035 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 13:57:03.915499 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 13:57:03.919118 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 13:57:03.922159 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 13:57:03.929428 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 13:57:03.932437 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 13:57:03.935579 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3146 13:57:03.942107 0 15 24 | B1->B0 | 3131 2828 | 0 0 | (0 0) (0 0)
3147 13:57:03.945436 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3148 13:57:03.948760 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 13:57:03.955738 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 13:57:03.958822 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 13:57:03.962197 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 13:57:03.968894 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 13:57:03.972469 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 13:57:03.975731 1 0 24 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
3155 13:57:03.982271 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 13:57:03.985252 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 13:57:03.989103 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 13:57:03.995207 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 13:57:03.998738 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 13:57:04.001647 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 13:57:04.004635 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3162 13:57:04.011611 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 13:57:04.015035 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3164 13:57:04.018330 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 13:57:04.024870 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 13:57:04.028187 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 13:57:04.031808 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 13:57:04.038668 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 13:57:04.041652 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 13:57:04.045407 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 13:57:04.052279 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 13:57:04.055536 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 13:57:04.059169 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 13:57:04.065435 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 13:57:04.069302 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 13:57:04.072346 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 13:57:04.075297 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 13:57:04.082395 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3179 13:57:04.085558 Total UI for P1: 0, mck2ui 16
3180 13:57:04.088868 best dqsien dly found for B0: ( 1, 3, 20)
3181 13:57:04.092426 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 13:57:04.095651 Total UI for P1: 0, mck2ui 16
3183 13:57:04.099287 best dqsien dly found for B1: ( 1, 3, 24)
3184 13:57:04.102346 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3185 13:57:04.105897 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3186 13:57:04.106496
3187 13:57:04.109305 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3188 13:57:04.112479 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3189 13:57:04.115749 [Gating] SW calibration Done
3190 13:57:04.116250 ==
3191 13:57:04.118941 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 13:57:04.122316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 13:57:04.125922 ==
3194 13:57:04.126435 RX Vref Scan: 0
3195 13:57:04.126815
3196 13:57:04.128806 RX Vref 0 -> 0, step: 1
3197 13:57:04.129275
3198 13:57:04.132270 RX Delay -40 -> 252, step: 8
3199 13:57:04.135714 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3200 13:57:04.138836 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3201 13:57:04.142781 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3202 13:57:04.146033 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3203 13:57:04.152443 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3204 13:57:04.156328 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3205 13:57:04.159183 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3206 13:57:04.162808 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3207 13:57:04.165733 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 13:57:04.169455 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3209 13:57:04.175953 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3210 13:57:04.179263 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 13:57:04.182678 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3212 13:57:04.185701 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3213 13:57:04.189371 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3214 13:57:04.196132 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3215 13:57:04.196706 ==
3216 13:57:04.199440 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 13:57:04.202834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 13:57:04.203420 ==
3219 13:57:04.203802 DQS Delay:
3220 13:57:04.205727 DQS0 = 0, DQS1 = 0
3221 13:57:04.206242 DQM Delay:
3222 13:57:04.209522 DQM0 = 120, DQM1 = 113
3223 13:57:04.210137 DQ Delay:
3224 13:57:04.212549 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3225 13:57:04.215688 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3226 13:57:04.219505 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3227 13:57:04.222746 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3228 13:57:04.223315
3229 13:57:04.223685
3230 13:57:04.226057 ==
3231 13:57:04.226734 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 13:57:04.232728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 13:57:04.233315 ==
3234 13:57:04.233692
3235 13:57:04.234081
3236 13:57:04.235602 TX Vref Scan disable
3237 13:57:04.236074 == TX Byte 0 ==
3238 13:57:04.239389 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3239 13:57:04.245901 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3240 13:57:04.246404 == TX Byte 1 ==
3241 13:57:04.249462 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3242 13:57:04.256130 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3243 13:57:04.256696 ==
3244 13:57:04.259414 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 13:57:04.262381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 13:57:04.262847 ==
3247 13:57:04.274815 TX Vref=22, minBit 3, minWin=24, winSum=401
3248 13:57:04.278125 TX Vref=24, minBit 1, minWin=24, winSum=405
3249 13:57:04.281414 TX Vref=26, minBit 10, minWin=24, winSum=406
3250 13:57:04.284549 TX Vref=28, minBit 8, minWin=25, winSum=414
3251 13:57:04.288085 TX Vref=30, minBit 10, minWin=25, winSum=419
3252 13:57:04.294657 TX Vref=32, minBit 10, minWin=25, winSum=418
3253 13:57:04.298223 [TxChooseVref] Worse bit 10, Min win 25, Win sum 419, Final Vref 30
3254 13:57:04.298788
3255 13:57:04.301408 Final TX Range 1 Vref 30
3256 13:57:04.302017
3257 13:57:04.302394 ==
3258 13:57:04.304570 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 13:57:04.308176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 13:57:04.311319 ==
3261 13:57:04.311788
3262 13:57:04.312155
3263 13:57:04.312515 TX Vref Scan disable
3264 13:57:04.314633 == TX Byte 0 ==
3265 13:57:04.318018 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3266 13:57:04.321217 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3267 13:57:04.324866 == TX Byte 1 ==
3268 13:57:04.328015 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3269 13:57:04.331188 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3270 13:57:04.334679
3271 13:57:04.335148 [DATLAT]
3272 13:57:04.335522 Freq=1200, CH1 RK0
3273 13:57:04.335871
3274 13:57:04.338053 DATLAT Default: 0xd
3275 13:57:04.338527 0, 0xFFFF, sum = 0
3276 13:57:04.341535 1, 0xFFFF, sum = 0
3277 13:57:04.342162 2, 0xFFFF, sum = 0
3278 13:57:04.344826 3, 0xFFFF, sum = 0
3279 13:57:04.345305 4, 0xFFFF, sum = 0
3280 13:57:04.348028 5, 0xFFFF, sum = 0
3281 13:57:04.348508 6, 0xFFFF, sum = 0
3282 13:57:04.351231 7, 0xFFFF, sum = 0
3283 13:57:04.351745 8, 0xFFFF, sum = 0
3284 13:57:04.354789 9, 0xFFFF, sum = 0
3285 13:57:04.358096 10, 0xFFFF, sum = 0
3286 13:57:04.358568 11, 0xFFFF, sum = 0
3287 13:57:04.361582 12, 0x0, sum = 1
3288 13:57:04.362098 13, 0x0, sum = 2
3289 13:57:04.362530 14, 0x0, sum = 3
3290 13:57:04.364682 15, 0x0, sum = 4
3291 13:57:04.365155 best_step = 13
3292 13:57:04.365521
3293 13:57:04.368263 ==
3294 13:57:04.368711 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 13:57:04.374628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 13:57:04.375087 ==
3297 13:57:04.375448 RX Vref Scan: 1
3298 13:57:04.375747
3299 13:57:04.378269 Set Vref Range= 32 -> 127
3300 13:57:04.378677
3301 13:57:04.381477 RX Vref 32 -> 127, step: 1
3302 13:57:04.381769
3303 13:57:04.384751 RX Delay -13 -> 252, step: 4
3304 13:57:04.385040
3305 13:57:04.387813 Set Vref, RX VrefLevel [Byte0]: 32
3306 13:57:04.390983 [Byte1]: 32
3307 13:57:04.391202
3308 13:57:04.394604 Set Vref, RX VrefLevel [Byte0]: 33
3309 13:57:04.397846 [Byte1]: 33
3310 13:57:04.398069
3311 13:57:04.401191 Set Vref, RX VrefLevel [Byte0]: 34
3312 13:57:04.404518 [Byte1]: 34
3313 13:57:04.409172
3314 13:57:04.409432 Set Vref, RX VrefLevel [Byte0]: 35
3315 13:57:04.412044 [Byte1]: 35
3316 13:57:04.416729
3317 13:57:04.417026 Set Vref, RX VrefLevel [Byte0]: 36
3318 13:57:04.419815 [Byte1]: 36
3319 13:57:04.424400
3320 13:57:04.424786 Set Vref, RX VrefLevel [Byte0]: 37
3321 13:57:04.427905 [Byte1]: 37
3322 13:57:04.432077
3323 13:57:04.432525 Set Vref, RX VrefLevel [Byte0]: 38
3324 13:57:04.435579 [Byte1]: 38
3325 13:57:04.439970
3326 13:57:04.440295 Set Vref, RX VrefLevel [Byte0]: 39
3327 13:57:04.443505 [Byte1]: 39
3328 13:57:04.448184
3329 13:57:04.448512 Set Vref, RX VrefLevel [Byte0]: 40
3330 13:57:04.451273 [Byte1]: 40
3331 13:57:04.456159
3332 13:57:04.456482 Set Vref, RX VrefLevel [Byte0]: 41
3333 13:57:04.458958 [Byte1]: 41
3334 13:57:04.463489
3335 13:57:04.463574 Set Vref, RX VrefLevel [Byte0]: 42
3336 13:57:04.466712 [Byte1]: 42
3337 13:57:04.471671
3338 13:57:04.471779 Set Vref, RX VrefLevel [Byte0]: 43
3339 13:57:04.474949 [Byte1]: 43
3340 13:57:04.479432
3341 13:57:04.479517 Set Vref, RX VrefLevel [Byte0]: 44
3342 13:57:04.482452 [Byte1]: 44
3343 13:57:04.486960
3344 13:57:04.487085 Set Vref, RX VrefLevel [Byte0]: 45
3345 13:57:04.490359 [Byte1]: 45
3346 13:57:04.495322
3347 13:57:04.495436 Set Vref, RX VrefLevel [Byte0]: 46
3348 13:57:04.498507 [Byte1]: 46
3349 13:57:04.503086
3350 13:57:04.503269 Set Vref, RX VrefLevel [Byte0]: 47
3351 13:57:04.506370 [Byte1]: 47
3352 13:57:04.511032
3353 13:57:04.511232 Set Vref, RX VrefLevel [Byte0]: 48
3354 13:57:04.514496 [Byte1]: 48
3355 13:57:04.518762
3356 13:57:04.518942 Set Vref, RX VrefLevel [Byte0]: 49
3357 13:57:04.522077 [Byte1]: 49
3358 13:57:04.527063
3359 13:57:04.527266 Set Vref, RX VrefLevel [Byte0]: 50
3360 13:57:04.529935 [Byte1]: 50
3361 13:57:04.534505
3362 13:57:04.534707 Set Vref, RX VrefLevel [Byte0]: 51
3363 13:57:04.537935 [Byte1]: 51
3364 13:57:04.542480
3365 13:57:04.542676 Set Vref, RX VrefLevel [Byte0]: 52
3366 13:57:04.545865 [Byte1]: 52
3367 13:57:04.550410
3368 13:57:04.550562 Set Vref, RX VrefLevel [Byte0]: 53
3369 13:57:04.553743 [Byte1]: 53
3370 13:57:04.558443
3371 13:57:04.558611 Set Vref, RX VrefLevel [Byte0]: 54
3372 13:57:04.561518 [Byte1]: 54
3373 13:57:04.566062
3374 13:57:04.566194 Set Vref, RX VrefLevel [Byte0]: 55
3375 13:57:04.569568 [Byte1]: 55
3376 13:57:04.573971
3377 13:57:04.574101 Set Vref, RX VrefLevel [Byte0]: 56
3378 13:57:04.577342 [Byte1]: 56
3379 13:57:04.581885
3380 13:57:04.582040 Set Vref, RX VrefLevel [Byte0]: 57
3381 13:57:04.585257 [Byte1]: 57
3382 13:57:04.589677
3383 13:57:04.589861 Set Vref, RX VrefLevel [Byte0]: 58
3384 13:57:04.593208 [Byte1]: 58
3385 13:57:04.597853
3386 13:57:04.598025 Set Vref, RX VrefLevel [Byte0]: 59
3387 13:57:04.601209 [Byte1]: 59
3388 13:57:04.605974
3389 13:57:04.606122 Set Vref, RX VrefLevel [Byte0]: 60
3390 13:57:04.609299 [Byte1]: 60
3391 13:57:04.613612
3392 13:57:04.613898 Set Vref, RX VrefLevel [Byte0]: 61
3393 13:57:04.616787 [Byte1]: 61
3394 13:57:04.621499
3395 13:57:04.621808 Set Vref, RX VrefLevel [Byte0]: 62
3396 13:57:04.625145 [Byte1]: 62
3397 13:57:04.629583
3398 13:57:04.629976 Set Vref, RX VrefLevel [Byte0]: 63
3399 13:57:04.632862 [Byte1]: 63
3400 13:57:04.637461
3401 13:57:04.637845 Set Vref, RX VrefLevel [Byte0]: 64
3402 13:57:04.640637 [Byte1]: 64
3403 13:57:04.644740
3404 13:57:04.644824 Set Vref, RX VrefLevel [Byte0]: 65
3405 13:57:04.648548 [Byte1]: 65
3406 13:57:04.653122
3407 13:57:04.653206 Set Vref, RX VrefLevel [Byte0]: 66
3408 13:57:04.656167 [Byte1]: 66
3409 13:57:04.661109
3410 13:57:04.661194 Set Vref, RX VrefLevel [Byte0]: 67
3411 13:57:04.664031 [Byte1]: 67
3412 13:57:04.668623
3413 13:57:04.668739 Final RX Vref Byte 0 = 53 to rank0
3414 13:57:04.671955 Final RX Vref Byte 1 = 52 to rank0
3415 13:57:04.675515 Final RX Vref Byte 0 = 53 to rank1
3416 13:57:04.678786 Final RX Vref Byte 1 = 52 to rank1==
3417 13:57:04.682110 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 13:57:04.685517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 13:57:04.688524 ==
3420 13:57:04.688637 DQS Delay:
3421 13:57:04.688738 DQS0 = 0, DQS1 = 0
3422 13:57:04.692212 DQM Delay:
3423 13:57:04.692297 DQM0 = 119, DQM1 = 112
3424 13:57:04.695287 DQ Delay:
3425 13:57:04.698836 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3426 13:57:04.701985 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3427 13:57:04.705590 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3428 13:57:04.708757 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3429 13:57:04.708870
3430 13:57:04.708953
3431 13:57:04.715611 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3432 13:57:04.718770 CH1 RK0: MR19=304, MR18=FE11
3433 13:57:04.725495 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3434 13:57:04.725579
3435 13:57:04.729056 ----->DramcWriteLeveling(PI) begin...
3436 13:57:04.729142 ==
3437 13:57:04.732208 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 13:57:04.735679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 13:57:04.735796 ==
3440 13:57:04.739128 Write leveling (Byte 0): 25 => 25
3441 13:57:04.742198 Write leveling (Byte 1): 29 => 29
3442 13:57:04.745566 DramcWriteLeveling(PI) end<-----
3443 13:57:04.745704
3444 13:57:04.745829 ==
3445 13:57:04.748794 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 13:57:04.755495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 13:57:04.755620 ==
3448 13:57:04.755747 [Gating] SW mode calibration
3449 13:57:04.765669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 13:57:04.769072 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 13:57:04.772618 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 13:57:04.778915 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 13:57:04.782274 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 13:57:04.785769 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 13:57:04.792237 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 13:57:04.795549 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3457 13:57:04.799314 0 15 24 | B1->B0 | 2b2b 3434 | 0 1 | (1 0) (1 0)
3458 13:57:04.806037 0 15 28 | B1->B0 | 2323 2d2d | 0 0 | (1 0) (1 0)
3459 13:57:04.809151 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 13:57:04.812662 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 13:57:04.819010 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 13:57:04.822506 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 13:57:04.825968 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 13:57:04.832306 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 13:57:04.835859 1 0 24 | B1->B0 | 3636 2424 | 0 0 | (0 0) (0 0)
3466 13:57:04.839092 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 13:57:04.842844 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 13:57:04.849327 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 13:57:04.852589 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 13:57:04.855591 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 13:57:04.862807 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 13:57:04.866052 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 13:57:04.869163 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 13:57:04.876286 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3475 13:57:04.879165 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 13:57:04.882902 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 13:57:04.889132 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 13:57:04.892387 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 13:57:04.895900 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 13:57:04.902477 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 13:57:04.906075 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 13:57:04.909359 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 13:57:04.916167 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 13:57:04.919345 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:57:04.922646 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:57:04.928913 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:57:04.932311 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:57:04.935637 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:57:04.942633 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3490 13:57:04.945590 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3491 13:57:04.948921 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 13:57:04.952340 Total UI for P1: 0, mck2ui 16
3493 13:57:04.955694 best dqsien dly found for B0: ( 1, 3, 26)
3494 13:57:04.958876 Total UI for P1: 0, mck2ui 16
3495 13:57:04.962413 best dqsien dly found for B1: ( 1, 3, 26)
3496 13:57:04.965368 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3497 13:57:04.968959 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3498 13:57:04.969510
3499 13:57:04.972253 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3500 13:57:04.979390 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3501 13:57:04.979982 [Gating] SW calibration Done
3502 13:57:04.980370 ==
3503 13:57:04.982090 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 13:57:04.988603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 13:57:04.989213 ==
3506 13:57:04.989758 RX Vref Scan: 0
3507 13:57:04.990198
3508 13:57:04.992352 RX Vref 0 -> 0, step: 1
3509 13:57:04.992916
3510 13:57:04.995537 RX Delay -40 -> 252, step: 8
3511 13:57:04.998919 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3512 13:57:05.002136 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3513 13:57:05.005629 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3514 13:57:05.012146 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3515 13:57:05.015880 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3516 13:57:05.018625 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3517 13:57:05.022144 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3518 13:57:05.025748 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3519 13:57:05.032371 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3520 13:57:05.035814 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3521 13:57:05.039005 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3522 13:57:05.041998 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3523 13:57:05.045686 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3524 13:57:05.052200 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3525 13:57:05.055221 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3526 13:57:05.059242 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3527 13:57:05.059820 ==
3528 13:57:05.062126 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 13:57:05.065323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 13:57:05.065912 ==
3531 13:57:05.068499 DQS Delay:
3532 13:57:05.069065 DQS0 = 0, DQS1 = 0
3533 13:57:05.071653 DQM Delay:
3534 13:57:05.072269 DQM0 = 120, DQM1 = 113
3535 13:57:05.074911 DQ Delay:
3536 13:57:05.078680 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3537 13:57:05.081766 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3538 13:57:05.085146 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3539 13:57:05.088403 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3540 13:57:05.088875
3541 13:57:05.089249
3542 13:57:05.089664 ==
3543 13:57:05.091830 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 13:57:05.095086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 13:57:05.095566 ==
3546 13:57:05.095939
3547 13:57:05.096285
3548 13:57:05.098152 TX Vref Scan disable
3549 13:57:05.102042 == TX Byte 0 ==
3550 13:57:05.104875 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3551 13:57:05.108368 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3552 13:57:05.111936 == TX Byte 1 ==
3553 13:57:05.114914 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3554 13:57:05.118464 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3555 13:57:05.119044 ==
3556 13:57:05.121790 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 13:57:05.127907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 13:57:05.128482 ==
3559 13:57:05.138645 TX Vref=22, minBit 1, minWin=25, winSum=412
3560 13:57:05.141832 TX Vref=24, minBit 1, minWin=25, winSum=417
3561 13:57:05.145329 TX Vref=26, minBit 9, minWin=24, winSum=424
3562 13:57:05.148341 TX Vref=28, minBit 11, minWin=25, winSum=420
3563 13:57:05.151975 TX Vref=30, minBit 1, minWin=25, winSum=425
3564 13:57:05.158890 TX Vref=32, minBit 3, minWin=25, winSum=422
3565 13:57:05.161920 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 30
3566 13:57:05.162426
3567 13:57:05.165237 Final TX Range 1 Vref 30
3568 13:57:05.165862
3569 13:57:05.166279 ==
3570 13:57:05.168443 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 13:57:05.171573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 13:57:05.172049 ==
3573 13:57:05.175219
3574 13:57:05.175791
3575 13:57:05.176166 TX Vref Scan disable
3576 13:57:05.178416 == TX Byte 0 ==
3577 13:57:05.181783 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3578 13:57:05.188522 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3579 13:57:05.189290 == TX Byte 1 ==
3580 13:57:05.191893 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3581 13:57:05.198397 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3582 13:57:05.198885
3583 13:57:05.199363 [DATLAT]
3584 13:57:05.199814 Freq=1200, CH1 RK1
3585 13:57:05.200261
3586 13:57:05.201433 DATLAT Default: 0xd
3587 13:57:05.201915 0, 0xFFFF, sum = 0
3588 13:57:05.204614 1, 0xFFFF, sum = 0
3589 13:57:05.208599 2, 0xFFFF, sum = 0
3590 13:57:05.209181 3, 0xFFFF, sum = 0
3591 13:57:05.211484 4, 0xFFFF, sum = 0
3592 13:57:05.211962 5, 0xFFFF, sum = 0
3593 13:57:05.215086 6, 0xFFFF, sum = 0
3594 13:57:05.215561 7, 0xFFFF, sum = 0
3595 13:57:05.218162 8, 0xFFFF, sum = 0
3596 13:57:05.218637 9, 0xFFFF, sum = 0
3597 13:57:05.221755 10, 0xFFFF, sum = 0
3598 13:57:05.222373 11, 0xFFFF, sum = 0
3599 13:57:05.225021 12, 0x0, sum = 1
3600 13:57:05.225590 13, 0x0, sum = 2
3601 13:57:05.227966 14, 0x0, sum = 3
3602 13:57:05.228440 15, 0x0, sum = 4
3603 13:57:05.231303 best_step = 13
3604 13:57:05.231767
3605 13:57:05.232137 ==
3606 13:57:05.234684 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 13:57:05.238384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 13:57:05.238955 ==
3609 13:57:05.239330 RX Vref Scan: 0
3610 13:57:05.241404
3611 13:57:05.241993 RX Vref 0 -> 0, step: 1
3612 13:57:05.242377
3613 13:57:05.244400 RX Delay -13 -> 252, step: 4
3614 13:57:05.251536 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3615 13:57:05.254474 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3616 13:57:05.257901 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3617 13:57:05.261110 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3618 13:57:05.264459 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3619 13:57:05.271438 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3620 13:57:05.274676 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3621 13:57:05.278111 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3622 13:57:05.280765 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3623 13:57:05.284221 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3624 13:57:05.287623 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3625 13:57:05.294379 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3626 13:57:05.297397 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3627 13:57:05.300919 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3628 13:57:05.304373 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3629 13:57:05.311222 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3630 13:57:05.311777 ==
3631 13:57:05.314321 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 13:57:05.317593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 13:57:05.318106 ==
3634 13:57:05.318486 DQS Delay:
3635 13:57:05.320823 DQS0 = 0, DQS1 = 0
3636 13:57:05.321289 DQM Delay:
3637 13:57:05.323812 DQM0 = 119, DQM1 = 113
3638 13:57:05.324365 DQ Delay:
3639 13:57:05.327340 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3640 13:57:05.330547 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3641 13:57:05.334022 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3642 13:57:05.337364 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3643 13:57:05.337824
3644 13:57:05.338237
3645 13:57:05.347351 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3646 13:57:05.350569 CH1 RK1: MR19=403, MR18=8ED
3647 13:57:05.353999 CH1_RK1: MR19=0x403, MR18=0x8ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3648 13:57:05.357728 [RxdqsGatingPostProcess] freq 1200
3649 13:57:05.364309 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 13:57:05.367681 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 13:57:05.370930 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 13:57:05.374248 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 13:57:05.377514 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 13:57:05.380843 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 13:57:05.384314 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 13:57:05.387544 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 13:57:05.390434 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 13:57:05.390949 Pre-setting of DQS Precalculation
3659 13:57:05.397376 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 13:57:05.404291 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 13:57:05.411029 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 13:57:05.411613
3663 13:57:05.412091
3664 13:57:05.414095 [Calibration Summary] 2400 Mbps
3665 13:57:05.417265 CH 0, Rank 0
3666 13:57:05.417797 SW Impedance : PASS
3667 13:57:05.420868 DUTY Scan : NO K
3668 13:57:05.424265 ZQ Calibration : PASS
3669 13:57:05.424898 Jitter Meter : NO K
3670 13:57:05.427056 CBT Training : PASS
3671 13:57:05.430375 Write leveling : PASS
3672 13:57:05.430885 RX DQS gating : PASS
3673 13:57:05.433836 RX DQ/DQS(RDDQC) : PASS
3674 13:57:05.434367 TX DQ/DQS : PASS
3675 13:57:05.437238 RX DATLAT : PASS
3676 13:57:05.440922 RX DQ/DQS(Engine): PASS
3677 13:57:05.441483 TX OE : NO K
3678 13:57:05.443945 All Pass.
3679 13:57:05.444511
3680 13:57:05.444877 CH 0, Rank 1
3681 13:57:05.447356 SW Impedance : PASS
3682 13:57:05.447927 DUTY Scan : NO K
3683 13:57:05.450472 ZQ Calibration : PASS
3684 13:57:05.454167 Jitter Meter : NO K
3685 13:57:05.454734 CBT Training : PASS
3686 13:57:05.457154 Write leveling : PASS
3687 13:57:05.460571 RX DQS gating : PASS
3688 13:57:05.461140 RX DQ/DQS(RDDQC) : PASS
3689 13:57:05.464039 TX DQ/DQS : PASS
3690 13:57:05.466829 RX DATLAT : PASS
3691 13:57:05.467293 RX DQ/DQS(Engine): PASS
3692 13:57:05.470645 TX OE : NO K
3693 13:57:05.471213 All Pass.
3694 13:57:05.471583
3695 13:57:05.473920 CH 1, Rank 0
3696 13:57:05.474514 SW Impedance : PASS
3697 13:57:05.476890 DUTY Scan : NO K
3698 13:57:05.480459 ZQ Calibration : PASS
3699 13:57:05.481051 Jitter Meter : NO K
3700 13:57:05.483708 CBT Training : PASS
3701 13:57:05.487554 Write leveling : PASS
3702 13:57:05.488123 RX DQS gating : PASS
3703 13:57:05.490537 RX DQ/DQS(RDDQC) : PASS
3704 13:57:05.490997 TX DQ/DQS : PASS
3705 13:57:05.493609 RX DATLAT : PASS
3706 13:57:05.497009 RX DQ/DQS(Engine): PASS
3707 13:57:05.497582 TX OE : NO K
3708 13:57:05.500352 All Pass.
3709 13:57:05.500959
3710 13:57:05.501329 CH 1, Rank 1
3711 13:57:05.504113 SW Impedance : PASS
3712 13:57:05.504730 DUTY Scan : NO K
3713 13:57:05.506640 ZQ Calibration : PASS
3714 13:57:05.510159 Jitter Meter : NO K
3715 13:57:05.510736 CBT Training : PASS
3716 13:57:05.513691 Write leveling : PASS
3717 13:57:05.516719 RX DQS gating : PASS
3718 13:57:05.517325 RX DQ/DQS(RDDQC) : PASS
3719 13:57:05.520180 TX DQ/DQS : PASS
3720 13:57:05.523390 RX DATLAT : PASS
3721 13:57:05.523854 RX DQ/DQS(Engine): PASS
3722 13:57:05.526597 TX OE : NO K
3723 13:57:05.527062 All Pass.
3724 13:57:05.527427
3725 13:57:05.530113 DramC Write-DBI off
3726 13:57:05.533311 PER_BANK_REFRESH: Hybrid Mode
3727 13:57:05.533775 TX_TRACKING: ON
3728 13:57:05.543018 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 13:57:05.546831 [FAST_K] Save calibration result to emmc
3730 13:57:05.549936 dramc_set_vcore_voltage set vcore to 650000
3731 13:57:05.553338 Read voltage for 600, 5
3732 13:57:05.553911 Vio18 = 0
3733 13:57:05.554340 Vcore = 650000
3734 13:57:05.556536 Vdram = 0
3735 13:57:05.557115 Vddq = 0
3736 13:57:05.557488 Vmddr = 0
3737 13:57:05.563272 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 13:57:05.566817 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 13:57:05.570120 MEM_TYPE=3, freq_sel=19
3740 13:57:05.573157 sv_algorithm_assistance_LP4_1600
3741 13:57:05.576439 ============ PULL DRAM RESETB DOWN ============
3742 13:57:05.580073 ========== PULL DRAM RESETB DOWN end =========
3743 13:57:05.586393 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 13:57:05.589755 ===================================
3745 13:57:05.590407 LPDDR4 DRAM CONFIGURATION
3746 13:57:05.593382 ===================================
3747 13:57:05.596448 EX_ROW_EN[0] = 0x0
3748 13:57:05.599696 EX_ROW_EN[1] = 0x0
3749 13:57:05.600162 LP4Y_EN = 0x0
3750 13:57:05.603094 WORK_FSP = 0x0
3751 13:57:05.603688 WL = 0x2
3752 13:57:05.606334 RL = 0x2
3753 13:57:05.606902 BL = 0x2
3754 13:57:05.609473 RPST = 0x0
3755 13:57:05.609972 RD_PRE = 0x0
3756 13:57:05.612996 WR_PRE = 0x1
3757 13:57:05.613626 WR_PST = 0x0
3758 13:57:05.616218 DBI_WR = 0x0
3759 13:57:05.616687 DBI_RD = 0x0
3760 13:57:05.620004 OTF = 0x1
3761 13:57:05.622947 ===================================
3762 13:57:05.626364 ===================================
3763 13:57:05.626837 ANA top config
3764 13:57:05.629567 ===================================
3765 13:57:05.632967 DLL_ASYNC_EN = 0
3766 13:57:05.636420 ALL_SLAVE_EN = 1
3767 13:57:05.639547 NEW_RANK_MODE = 1
3768 13:57:05.640018 DLL_IDLE_MODE = 1
3769 13:57:05.643296 LP45_APHY_COMB_EN = 1
3770 13:57:05.646199 TX_ODT_DIS = 1
3771 13:57:05.649676 NEW_8X_MODE = 1
3772 13:57:05.653225 ===================================
3773 13:57:05.656388 ===================================
3774 13:57:05.659824 data_rate = 1200
3775 13:57:05.660396 CKR = 1
3776 13:57:05.663034 DQ_P2S_RATIO = 8
3777 13:57:05.666387 ===================================
3778 13:57:05.669449 CA_P2S_RATIO = 8
3779 13:57:05.673023 DQ_CA_OPEN = 0
3780 13:57:05.676018 DQ_SEMI_OPEN = 0
3781 13:57:05.679923 CA_SEMI_OPEN = 0
3782 13:57:05.680501 CA_FULL_RATE = 0
3783 13:57:05.682727 DQ_CKDIV4_EN = 1
3784 13:57:05.686096 CA_CKDIV4_EN = 1
3785 13:57:05.689412 CA_PREDIV_EN = 0
3786 13:57:05.692500 PH8_DLY = 0
3787 13:57:05.696067 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 13:57:05.696575 DQ_AAMCK_DIV = 4
3789 13:57:05.699089 CA_AAMCK_DIV = 4
3790 13:57:05.702360 CA_ADMCK_DIV = 4
3791 13:57:05.705926 DQ_TRACK_CA_EN = 0
3792 13:57:05.709185 CA_PICK = 600
3793 13:57:05.712587 CA_MCKIO = 600
3794 13:57:05.715592 MCKIO_SEMI = 0
3795 13:57:05.716259 PLL_FREQ = 2288
3796 13:57:05.719067 DQ_UI_PI_RATIO = 32
3797 13:57:05.722410 CA_UI_PI_RATIO = 0
3798 13:57:05.725593 ===================================
3799 13:57:05.729180 ===================================
3800 13:57:05.732055 memory_type:LPDDR4
3801 13:57:05.732523 GP_NUM : 10
3802 13:57:05.735628 SRAM_EN : 1
3803 13:57:05.739083 MD32_EN : 0
3804 13:57:05.741981 ===================================
3805 13:57:05.742461 [ANA_INIT] >>>>>>>>>>>>>>
3806 13:57:05.745578 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 13:57:05.748764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 13:57:05.752139 ===================================
3809 13:57:05.755449 data_rate = 1200,PCW = 0X5800
3810 13:57:05.758632 ===================================
3811 13:57:05.762256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 13:57:05.769058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 13:57:05.772264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 13:57:05.778633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 13:57:05.782048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 13:57:05.785622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 13:57:05.788629 [ANA_INIT] flow start
3818 13:57:05.789095 [ANA_INIT] PLL >>>>>>>>
3819 13:57:05.792105 [ANA_INIT] PLL <<<<<<<<
3820 13:57:05.795514 [ANA_INIT] MIDPI >>>>>>>>
3821 13:57:05.796003 [ANA_INIT] MIDPI <<<<<<<<
3822 13:57:05.798736 [ANA_INIT] DLL >>>>>>>>
3823 13:57:05.801933 [ANA_INIT] flow end
3824 13:57:05.805660 ============ LP4 DIFF to SE enter ============
3825 13:57:05.808845 ============ LP4 DIFF to SE exit ============
3826 13:57:05.812062 [ANA_INIT] <<<<<<<<<<<<<
3827 13:57:05.815297 [Flow] Enable top DCM control >>>>>
3828 13:57:05.818819 [Flow] Enable top DCM control <<<<<
3829 13:57:05.821917 Enable DLL master slave shuffle
3830 13:57:05.825571 ==============================================================
3831 13:57:05.828396 Gating Mode config
3832 13:57:05.831752 ==============================================================
3833 13:57:05.835145 Config description:
3834 13:57:05.845150 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 13:57:05.851634 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 13:57:05.854849 SELPH_MODE 0: By rank 1: By Phase
3837 13:57:05.861620 ==============================================================
3838 13:57:05.864740 GAT_TRACK_EN = 1
3839 13:57:05.868420 RX_GATING_MODE = 2
3840 13:57:05.871702 RX_GATING_TRACK_MODE = 2
3841 13:57:05.875000 SELPH_MODE = 1
3842 13:57:05.878357 PICG_EARLY_EN = 1
3843 13:57:05.881855 VALID_LAT_VALUE = 1
3844 13:57:05.884982 ==============================================================
3845 13:57:05.888294 Enter into Gating configuration >>>>
3846 13:57:05.891355 Exit from Gating configuration <<<<
3847 13:57:05.895030 Enter into DVFS_PRE_config >>>>>
3848 13:57:05.908311 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 13:57:05.908900 Exit from DVFS_PRE_config <<<<<
3850 13:57:05.911543 Enter into PICG configuration >>>>
3851 13:57:05.914878 Exit from PICG configuration <<<<
3852 13:57:05.918032 [RX_INPUT] configuration >>>>>
3853 13:57:05.921265 [RX_INPUT] configuration <<<<<
3854 13:57:05.928042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 13:57:05.931151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 13:57:05.938094 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 13:57:05.944556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 13:57:05.951040 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 13:57:05.957822 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 13:57:05.961092 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 13:57:05.964540 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 13:57:05.967340 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 13:57:05.974468 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 13:57:05.977755 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 13:57:05.980972 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 13:57:05.984208 ===================================
3867 13:57:05.987511 LPDDR4 DRAM CONFIGURATION
3868 13:57:05.990896 ===================================
3869 13:57:05.991453 EX_ROW_EN[0] = 0x0
3870 13:57:05.994167 EX_ROW_EN[1] = 0x0
3871 13:57:05.997755 LP4Y_EN = 0x0
3872 13:57:05.998264 WORK_FSP = 0x0
3873 13:57:06.001289 WL = 0x2
3874 13:57:06.001839 RL = 0x2
3875 13:57:06.004574 BL = 0x2
3876 13:57:06.005133 RPST = 0x0
3877 13:57:06.007704 RD_PRE = 0x0
3878 13:57:06.008256 WR_PRE = 0x1
3879 13:57:06.010550 WR_PST = 0x0
3880 13:57:06.011013 DBI_WR = 0x0
3881 13:57:06.014093 DBI_RD = 0x0
3882 13:57:06.014653 OTF = 0x1
3883 13:57:06.017194 ===================================
3884 13:57:06.020883 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 13:57:06.027268 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 13:57:06.030777 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 13:57:06.034169 ===================================
3888 13:57:06.037471 LPDDR4 DRAM CONFIGURATION
3889 13:57:06.041052 ===================================
3890 13:57:06.041617 EX_ROW_EN[0] = 0x10
3891 13:57:06.043957 EX_ROW_EN[1] = 0x0
3892 13:57:06.044422 LP4Y_EN = 0x0
3893 13:57:06.047666 WORK_FSP = 0x0
3894 13:57:06.051078 WL = 0x2
3895 13:57:06.051547 RL = 0x2
3896 13:57:06.053889 BL = 0x2
3897 13:57:06.054396 RPST = 0x0
3898 13:57:06.057223 RD_PRE = 0x0
3899 13:57:06.057685 WR_PRE = 0x1
3900 13:57:06.060578 WR_PST = 0x0
3901 13:57:06.061046 DBI_WR = 0x0
3902 13:57:06.064162 DBI_RD = 0x0
3903 13:57:06.064728 OTF = 0x1
3904 13:57:06.067244 ===================================
3905 13:57:06.073882 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 13:57:06.078235 nWR fixed to 30
3907 13:57:06.081538 [ModeRegInit_LP4] CH0 RK0
3908 13:57:06.082123 [ModeRegInit_LP4] CH0 RK1
3909 13:57:06.084762 [ModeRegInit_LP4] CH1 RK0
3910 13:57:06.087993 [ModeRegInit_LP4] CH1 RK1
3911 13:57:06.088557 match AC timing 17
3912 13:57:06.094412 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 13:57:06.097564 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 13:57:06.101149 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 13:57:06.107820 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 13:57:06.110854 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 13:57:06.111419 ==
3918 13:57:06.114373 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 13:57:06.117401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 13:57:06.117868 ==
3921 13:57:06.124745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 13:57:06.130963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3923 13:57:06.134091 [CA 0] Center 36 (5~67) winsize 63
3924 13:57:06.137640 [CA 1] Center 36 (6~67) winsize 62
3925 13:57:06.141462 [CA 2] Center 34 (4~65) winsize 62
3926 13:57:06.144628 [CA 3] Center 34 (3~65) winsize 63
3927 13:57:06.147624 [CA 4] Center 33 (3~64) winsize 62
3928 13:57:06.150900 [CA 5] Center 33 (3~64) winsize 62
3929 13:57:06.151385
3930 13:57:06.154272 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3931 13:57:06.154739
3932 13:57:06.157655 [CATrainingPosCal] consider 1 rank data
3933 13:57:06.161011 u2DelayCellTimex100 = 270/100 ps
3934 13:57:06.164452 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3935 13:57:06.167636 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 13:57:06.171440 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 13:57:06.174399 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3938 13:57:06.177647 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 13:57:06.180915 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3940 13:57:06.184101
3941 13:57:06.188104 CA PerBit enable=1, Macro0, CA PI delay=33
3942 13:57:06.188662
3943 13:57:06.190985 [CBTSetCACLKResult] CA Dly = 33
3944 13:57:06.191541 CS Dly: 5 (0~36)
3945 13:57:06.191914 ==
3946 13:57:06.194241 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 13:57:06.197511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 13:57:06.198134 ==
3949 13:57:06.204227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 13:57:06.210808 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3951 13:57:06.214235 [CA 0] Center 36 (6~67) winsize 62
3952 13:57:06.217487 [CA 1] Center 36 (6~67) winsize 62
3953 13:57:06.220905 [CA 2] Center 34 (4~65) winsize 62
3954 13:57:06.224079 [CA 3] Center 34 (4~65) winsize 62
3955 13:57:06.227283 [CA 4] Center 34 (3~65) winsize 63
3956 13:57:06.230879 [CA 5] Center 33 (3~64) winsize 62
3957 13:57:06.231435
3958 13:57:06.234079 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3959 13:57:06.234548
3960 13:57:06.237499 [CATrainingPosCal] consider 2 rank data
3961 13:57:06.241189 u2DelayCellTimex100 = 270/100 ps
3962 13:57:06.244088 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3963 13:57:06.247439 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 13:57:06.250995 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 13:57:06.254100 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 13:57:06.260863 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 13:57:06.263831 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 13:57:06.264301
3969 13:57:06.267306 CA PerBit enable=1, Macro0, CA PI delay=33
3970 13:57:06.267873
3971 13:57:06.270630 [CBTSetCACLKResult] CA Dly = 33
3972 13:57:06.271098 CS Dly: 5 (0~36)
3973 13:57:06.271463
3974 13:57:06.274031 ----->DramcWriteLeveling(PI) begin...
3975 13:57:06.274602 ==
3976 13:57:06.277388 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 13:57:06.283826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 13:57:06.284299 ==
3979 13:57:06.287315 Write leveling (Byte 0): 33 => 33
3980 13:57:06.287782 Write leveling (Byte 1): 29 => 29
3981 13:57:06.290454 DramcWriteLeveling(PI) end<-----
3982 13:57:06.290920
3983 13:57:06.291284 ==
3984 13:57:06.294161 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 13:57:06.300801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 13:57:06.301368 ==
3987 13:57:06.303831 [Gating] SW mode calibration
3988 13:57:06.310597 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 13:57:06.313769 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 13:57:06.320976 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 13:57:06.324281 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 13:57:06.327033 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3993 13:57:06.333876 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
3994 13:57:06.337366 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
3995 13:57:06.340722 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 13:57:06.347075 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 13:57:06.350258 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 13:57:06.353801 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 13:57:06.357199 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 13:57:06.363890 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 13:57:06.367013 0 10 12 | B1->B0 | 2b2b 3c3c | 0 0 | (0 0) (0 0)
4002 13:57:06.370037 0 10 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
4003 13:57:06.377315 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 13:57:06.380155 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 13:57:06.383339 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 13:57:06.389879 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 13:57:06.393041 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 13:57:06.396669 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 13:57:06.403147 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4010 13:57:06.406746 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4011 13:57:06.410314 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 13:57:06.416711 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 13:57:06.419908 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 13:57:06.423641 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 13:57:06.429800 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 13:57:06.433637 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 13:57:06.436639 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 13:57:06.443208 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:57:06.446288 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:57:06.449848 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:57:06.456476 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:57:06.459898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:57:06.462912 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:57:06.469636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:57:06.473457 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:57:06.476142 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 13:57:06.479812 Total UI for P1: 0, mck2ui 16
4028 13:57:06.483180 best dqsien dly found for B0: ( 0, 13, 14)
4029 13:57:06.486258 Total UI for P1: 0, mck2ui 16
4030 13:57:06.489332 best dqsien dly found for B1: ( 0, 13, 14)
4031 13:57:06.492889 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4032 13:57:06.496269 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4033 13:57:06.496739
4034 13:57:06.502851 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4035 13:57:06.506180 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4036 13:57:06.509444 [Gating] SW calibration Done
4037 13:57:06.509918 ==
4038 13:57:06.512853 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 13:57:06.515843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 13:57:06.516319 ==
4041 13:57:06.516716 RX Vref Scan: 0
4042 13:57:06.517066
4043 13:57:06.519393 RX Vref 0 -> 0, step: 1
4044 13:57:06.519968
4045 13:57:06.523102 RX Delay -230 -> 252, step: 16
4046 13:57:06.525855 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4047 13:57:06.529392 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4048 13:57:06.536150 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4049 13:57:06.539776 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4050 13:57:06.542407 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4051 13:57:06.546162 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4052 13:57:06.552483 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4053 13:57:06.556156 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4054 13:57:06.559206 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4055 13:57:06.562921 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4056 13:57:06.566123 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4057 13:57:06.572799 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4058 13:57:06.576302 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4059 13:57:06.579091 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4060 13:57:06.582429 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4061 13:57:06.589471 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4062 13:57:06.590108 ==
4063 13:57:06.592365 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 13:57:06.595446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 13:57:06.595919 ==
4066 13:57:06.596291 DQS Delay:
4067 13:57:06.598793 DQS0 = 0, DQS1 = 0
4068 13:57:06.599262 DQM Delay:
4069 13:57:06.602367 DQM0 = 50, DQM1 = 41
4070 13:57:06.602835 DQ Delay:
4071 13:57:06.605429 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4072 13:57:06.608918 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4073 13:57:06.612554 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4074 13:57:06.615905 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4075 13:57:06.616380
4076 13:57:06.616751
4077 13:57:06.617096 ==
4078 13:57:06.618830 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 13:57:06.622542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 13:57:06.623016 ==
4081 13:57:06.626109
4082 13:57:06.626666
4083 13:57:06.627038 TX Vref Scan disable
4084 13:57:06.629069 == TX Byte 0 ==
4085 13:57:06.632439 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4086 13:57:06.635715 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4087 13:57:06.639164 == TX Byte 1 ==
4088 13:57:06.642162 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4089 13:57:06.646200 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4090 13:57:06.649102 ==
4091 13:57:06.651872 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 13:57:06.655998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 13:57:06.656579 ==
4094 13:57:06.656958
4095 13:57:06.657303
4096 13:57:06.658801 TX Vref Scan disable
4097 13:57:06.659313 == TX Byte 0 ==
4098 13:57:06.665551 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4099 13:57:06.669207 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4100 13:57:06.669779 == TX Byte 1 ==
4101 13:57:06.675474 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4102 13:57:06.679074 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4103 13:57:06.679657
4104 13:57:06.680031 [DATLAT]
4105 13:57:06.682290 Freq=600, CH0 RK0
4106 13:57:06.682852
4107 13:57:06.683221 DATLAT Default: 0x9
4108 13:57:06.685501 0, 0xFFFF, sum = 0
4109 13:57:06.686011 1, 0xFFFF, sum = 0
4110 13:57:06.689048 2, 0xFFFF, sum = 0
4111 13:57:06.689617 3, 0xFFFF, sum = 0
4112 13:57:06.692311 4, 0xFFFF, sum = 0
4113 13:57:06.695625 5, 0xFFFF, sum = 0
4114 13:57:06.696105 6, 0xFFFF, sum = 0
4115 13:57:06.698866 7, 0xFFFF, sum = 0
4116 13:57:06.699344 8, 0x0, sum = 1
4117 13:57:06.699723 9, 0x0, sum = 2
4118 13:57:06.701857 10, 0x0, sum = 3
4119 13:57:06.702403 11, 0x0, sum = 4
4120 13:57:06.705346 best_step = 9
4121 13:57:06.705924
4122 13:57:06.706350 ==
4123 13:57:06.708792 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 13:57:06.711970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 13:57:06.712440 ==
4126 13:57:06.715638 RX Vref Scan: 1
4127 13:57:06.716205
4128 13:57:06.716597 RX Vref 0 -> 0, step: 1
4129 13:57:06.716939
4130 13:57:06.718397 RX Delay -179 -> 252, step: 8
4131 13:57:06.718863
4132 13:57:06.721872 Set Vref, RX VrefLevel [Byte0]: 60
4133 13:57:06.724926 [Byte1]: 50
4134 13:57:06.728924
4135 13:57:06.729390 Final RX Vref Byte 0 = 60 to rank0
4136 13:57:06.732521 Final RX Vref Byte 1 = 50 to rank0
4137 13:57:06.735794 Final RX Vref Byte 0 = 60 to rank1
4138 13:57:06.739007 Final RX Vref Byte 1 = 50 to rank1==
4139 13:57:06.742017 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 13:57:06.748831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 13:57:06.749471 ==
4142 13:57:06.750294 DQS Delay:
4143 13:57:06.750992 DQS0 = 0, DQS1 = 0
4144 13:57:06.752178 DQM Delay:
4145 13:57:06.752683 DQM0 = 49, DQM1 = 37
4146 13:57:06.755629 DQ Delay:
4147 13:57:06.759165 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4148 13:57:06.762237 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4149 13:57:06.762712 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4150 13:57:06.769727 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4151 13:57:06.770367
4152 13:57:06.770862
4153 13:57:06.775800 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4154 13:57:06.778749 CH0 RK0: MR19=808, MR18=5D57
4155 13:57:06.785308 CH0_RK0: MR19=0x808, MR18=0x5D57, DQSOSC=392, MR23=63, INC=170, DEC=113
4156 13:57:06.785791
4157 13:57:06.789110 ----->DramcWriteLeveling(PI) begin...
4158 13:57:06.789582 ==
4159 13:57:06.791939 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 13:57:06.795131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 13:57:06.795606 ==
4162 13:57:06.798730 Write leveling (Byte 0): 34 => 34
4163 13:57:06.802069 Write leveling (Byte 1): 30 => 30
4164 13:57:06.805077 DramcWriteLeveling(PI) end<-----
4165 13:57:06.805548
4166 13:57:06.805914 ==
4167 13:57:06.808444 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 13:57:06.811900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 13:57:06.812476 ==
4170 13:57:06.815281 [Gating] SW mode calibration
4171 13:57:06.821523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4172 13:57:06.828408 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4173 13:57:06.831691 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 13:57:06.834942 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 13:57:06.841798 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 13:57:06.845157 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 1)
4177 13:57:06.848621 0 9 16 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
4178 13:57:06.855023 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 13:57:06.858412 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 13:57:06.861376 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 13:57:06.868390 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 13:57:06.871755 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 13:57:06.874979 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 13:57:06.881670 0 10 12 | B1->B0 | 2c2b 2f2f | 1 0 | (0 0) (0 0)
4185 13:57:06.885001 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4186 13:57:06.887986 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 13:57:06.895179 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 13:57:06.898119 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 13:57:06.901189 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 13:57:06.907920 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 13:57:06.911427 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 13:57:06.914855 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4193 13:57:06.921447 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4194 13:57:06.924682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 13:57:06.928162 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 13:57:06.934678 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 13:57:06.938087 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 13:57:06.941372 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 13:57:06.947971 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 13:57:06.951128 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 13:57:06.954724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 13:57:06.961127 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:57:06.964375 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:57:06.968032 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:57:06.974265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:57:06.977513 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:57:06.981322 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:57:06.984242 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4209 13:57:06.988050 Total UI for P1: 0, mck2ui 16
4210 13:57:06.991005 best dqsien dly found for B0: ( 0, 13, 10)
4211 13:57:06.997907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 13:57:06.998038 Total UI for P1: 0, mck2ui 16
4213 13:57:07.004934 best dqsien dly found for B1: ( 0, 13, 12)
4214 13:57:07.008264 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4215 13:57:07.011487 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4216 13:57:07.011730
4217 13:57:07.014558 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4218 13:57:07.017773 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4219 13:57:07.021090 [Gating] SW calibration Done
4220 13:57:07.021291 ==
4221 13:57:07.024583 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 13:57:07.028012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 13:57:07.028379 ==
4224 13:57:07.031180 RX Vref Scan: 0
4225 13:57:07.031616
4226 13:57:07.034865 RX Vref 0 -> 0, step: 1
4227 13:57:07.035164
4228 13:57:07.035400 RX Delay -230 -> 252, step: 16
4229 13:57:07.041519 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4230 13:57:07.044519 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4231 13:57:07.048335 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4232 13:57:07.051524 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4233 13:57:07.057777 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4234 13:57:07.061712 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4235 13:57:07.064560 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4236 13:57:07.068174 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4237 13:57:07.071230 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4238 13:57:07.077668 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4239 13:57:07.081408 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4240 13:57:07.084390 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4241 13:57:07.088133 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4242 13:57:07.094741 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4243 13:57:07.098219 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4244 13:57:07.101346 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4245 13:57:07.101915 ==
4246 13:57:07.104713 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 13:57:07.107747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 13:57:07.110928 ==
4249 13:57:07.111496 DQS Delay:
4250 13:57:07.111866 DQS0 = 0, DQS1 = 0
4251 13:57:07.114547 DQM Delay:
4252 13:57:07.115057 DQM0 = 51, DQM1 = 42
4253 13:57:07.117494 DQ Delay:
4254 13:57:07.118038 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4255 13:57:07.120634 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4256 13:57:07.124102 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4257 13:57:07.127515 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4258 13:57:07.128083
4259 13:57:07.130790
4260 13:57:07.131253 ==
4261 13:57:07.134251 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 13:57:07.137663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 13:57:07.138325 ==
4264 13:57:07.138714
4265 13:57:07.139058
4266 13:57:07.141028 TX Vref Scan disable
4267 13:57:07.141491 == TX Byte 0 ==
4268 13:57:07.147469 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4269 13:57:07.150474 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4270 13:57:07.150942 == TX Byte 1 ==
4271 13:57:07.157677 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4272 13:57:07.160865 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4273 13:57:07.161438 ==
4274 13:57:07.164409 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 13:57:07.167816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 13:57:07.168406 ==
4277 13:57:07.168780
4278 13:57:07.169120
4279 13:57:07.170611 TX Vref Scan disable
4280 13:57:07.174176 == TX Byte 0 ==
4281 13:57:07.177492 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4282 13:57:07.181247 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4283 13:57:07.184025 == TX Byte 1 ==
4284 13:57:07.187631 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4285 13:57:07.191067 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4286 13:57:07.193975
4287 13:57:07.194551 [DATLAT]
4288 13:57:07.194923 Freq=600, CH0 RK1
4289 13:57:07.195268
4290 13:57:07.197344 DATLAT Default: 0x9
4291 13:57:07.197921 0, 0xFFFF, sum = 0
4292 13:57:07.200356 1, 0xFFFF, sum = 0
4293 13:57:07.200820 2, 0xFFFF, sum = 0
4294 13:57:07.203873 3, 0xFFFF, sum = 0
4295 13:57:07.204418 4, 0xFFFF, sum = 0
4296 13:57:07.207200 5, 0xFFFF, sum = 0
4297 13:57:07.210060 6, 0xFFFF, sum = 0
4298 13:57:07.210525 7, 0xFFFF, sum = 0
4299 13:57:07.213760 8, 0x0, sum = 1
4300 13:57:07.214268 9, 0x0, sum = 2
4301 13:57:07.214638 10, 0x0, sum = 3
4302 13:57:07.216784 11, 0x0, sum = 4
4303 13:57:07.217244 best_step = 9
4304 13:57:07.217601
4305 13:57:07.217932 ==
4306 13:57:07.220447 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 13:57:07.226829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 13:57:07.227524 ==
4309 13:57:07.227970 RX Vref Scan: 0
4310 13:57:07.228310
4311 13:57:07.230011 RX Vref 0 -> 0, step: 1
4312 13:57:07.230463
4313 13:57:07.233733 RX Delay -179 -> 252, step: 8
4314 13:57:07.236925 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4315 13:57:07.243442 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4316 13:57:07.246758 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4317 13:57:07.249828 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4318 13:57:07.253331 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4319 13:57:07.256768 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4320 13:57:07.263364 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4321 13:57:07.266753 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4322 13:57:07.269731 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4323 13:57:07.273727 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4324 13:57:07.276866 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4325 13:57:07.283489 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4326 13:57:07.286494 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4327 13:57:07.289988 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4328 13:57:07.293434 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4329 13:57:07.299954 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4330 13:57:07.300414 ==
4331 13:57:07.303344 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 13:57:07.306680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 13:57:07.307243 ==
4334 13:57:07.307607 DQS Delay:
4335 13:57:07.310067 DQS0 = 0, DQS1 = 0
4336 13:57:07.310629 DQM Delay:
4337 13:57:07.313457 DQM0 = 48, DQM1 = 42
4338 13:57:07.314054 DQ Delay:
4339 13:57:07.316606 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4340 13:57:07.319782 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4341 13:57:07.322933 DQ8 =32, DQ9 =28, DQ10 =44, DQ11 =32
4342 13:57:07.326832 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4343 13:57:07.327389
4344 13:57:07.327808
4345 13:57:07.333111 [DQSOSCAuto] RK1, (LSB)MR18= 0x6633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4346 13:57:07.336687 CH0 RK1: MR19=808, MR18=6633
4347 13:57:07.343111 CH0_RK1: MR19=0x808, MR18=0x6633, DQSOSC=390, MR23=63, INC=172, DEC=114
4348 13:57:07.346676 [RxdqsGatingPostProcess] freq 600
4349 13:57:07.353269 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4350 13:57:07.353823 Pre-setting of DQS Precalculation
4351 13:57:07.360280 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4352 13:57:07.360859 ==
4353 13:57:07.363528 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 13:57:07.366656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 13:57:07.367123 ==
4356 13:57:07.373298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 13:57:07.379913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4358 13:57:07.383406 [CA 0] Center 35 (5~66) winsize 62
4359 13:57:07.386500 [CA 1] Center 35 (5~66) winsize 62
4360 13:57:07.389615 [CA 2] Center 34 (4~65) winsize 62
4361 13:57:07.393112 [CA 3] Center 33 (3~64) winsize 62
4362 13:57:07.396433 [CA 4] Center 34 (3~65) winsize 63
4363 13:57:07.399767 [CA 5] Center 33 (3~64) winsize 62
4364 13:57:07.400245
4365 13:57:07.403148 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4366 13:57:07.403702
4367 13:57:07.406306 [CATrainingPosCal] consider 1 rank data
4368 13:57:07.409701 u2DelayCellTimex100 = 270/100 ps
4369 13:57:07.413184 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 13:57:07.416389 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 13:57:07.419649 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 13:57:07.423067 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4373 13:57:07.426605 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4374 13:57:07.429926 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 13:57:07.432795
4376 13:57:07.436352 CA PerBit enable=1, Macro0, CA PI delay=33
4377 13:57:07.436908
4378 13:57:07.439542 [CBTSetCACLKResult] CA Dly = 33
4379 13:57:07.440011 CS Dly: 5 (0~36)
4380 13:57:07.440366 ==
4381 13:57:07.442708 Dram Type= 6, Freq= 0, CH_1, rank 1
4382 13:57:07.446116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 13:57:07.446672 ==
4384 13:57:07.452506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 13:57:07.459145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4386 13:57:07.462571 [CA 0] Center 35 (5~66) winsize 62
4387 13:57:07.465729 [CA 1] Center 36 (5~67) winsize 63
4388 13:57:07.469357 [CA 2] Center 34 (4~65) winsize 62
4389 13:57:07.472674 [CA 3] Center 34 (4~65) winsize 62
4390 13:57:07.475800 [CA 4] Center 34 (4~65) winsize 62
4391 13:57:07.479331 [CA 5] Center 34 (4~64) winsize 61
4392 13:57:07.479962
4393 13:57:07.482714 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4394 13:57:07.483176
4395 13:57:07.486118 [CATrainingPosCal] consider 2 rank data
4396 13:57:07.489207 u2DelayCellTimex100 = 270/100 ps
4397 13:57:07.492540 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4398 13:57:07.495812 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4399 13:57:07.499530 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4400 13:57:07.502611 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4401 13:57:07.505884 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4402 13:57:07.512669 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4403 13:57:07.513420
4404 13:57:07.515456 CA PerBit enable=1, Macro0, CA PI delay=34
4405 13:57:07.516116
4406 13:57:07.518801 [CBTSetCACLKResult] CA Dly = 34
4407 13:57:07.519439 CS Dly: 5 (0~36)
4408 13:57:07.520014
4409 13:57:07.522605 ----->DramcWriteLeveling(PI) begin...
4410 13:57:07.523057 ==
4411 13:57:07.525894 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 13:57:07.532363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 13:57:07.532962 ==
4414 13:57:07.535672 Write leveling (Byte 0): 28 => 28
4415 13:57:07.536266 Write leveling (Byte 1): 33 => 33
4416 13:57:07.539301 DramcWriteLeveling(PI) end<-----
4417 13:57:07.539894
4418 13:57:07.540387 ==
4419 13:57:07.542204 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 13:57:07.548969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 13:57:07.549577 ==
4422 13:57:07.552279 [Gating] SW mode calibration
4423 13:57:07.558566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4424 13:57:07.562206 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4425 13:57:07.569045 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 13:57:07.571891 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 13:57:07.575633 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 13:57:07.582148 0 9 12 | B1->B0 | 2727 2c2c | 1 1 | (1 0) (1 0)
4429 13:57:07.585429 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 13:57:07.588628 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 13:57:07.595085 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 13:57:07.598388 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 13:57:07.601841 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 13:57:07.608584 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 13:57:07.611758 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4436 13:57:07.615106 0 10 12 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
4437 13:57:07.618328 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 13:57:07.624977 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 13:57:07.628820 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 13:57:07.632180 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 13:57:07.638606 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 13:57:07.641664 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 13:57:07.645186 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4444 13:57:07.651572 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4445 13:57:07.655215 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 13:57:07.658677 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 13:57:07.665329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 13:57:07.668701 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 13:57:07.671630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 13:57:07.678187 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 13:57:07.681722 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 13:57:07.685179 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 13:57:07.691767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 13:57:07.695118 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:57:07.698405 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:57:07.705048 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:57:07.708403 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:57:07.711511 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:57:07.718376 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4460 13:57:07.721258 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4461 13:57:07.724761 Total UI for P1: 0, mck2ui 16
4462 13:57:07.728047 best dqsien dly found for B0: ( 0, 13, 8)
4463 13:57:07.731637 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 13:57:07.735332 Total UI for P1: 0, mck2ui 16
4465 13:57:07.738498 best dqsien dly found for B1: ( 0, 13, 12)
4466 13:57:07.741598 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4467 13:57:07.744945 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4468 13:57:07.745509
4469 13:57:07.748306 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4470 13:57:07.754657 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4471 13:57:07.755232 [Gating] SW calibration Done
4472 13:57:07.755611 ==
4473 13:57:07.757937 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 13:57:07.764411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 13:57:07.764962 ==
4476 13:57:07.765359 RX Vref Scan: 0
4477 13:57:07.765762
4478 13:57:07.767728 RX Vref 0 -> 0, step: 1
4479 13:57:07.768134
4480 13:57:07.771412 RX Delay -230 -> 252, step: 16
4481 13:57:07.774422 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4482 13:57:07.777715 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4483 13:57:07.784365 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4484 13:57:07.787516 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4485 13:57:07.791553 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4486 13:57:07.794453 iDelay=218, Bit 5, Center 65 (-70 ~ 201) 272
4487 13:57:07.797589 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4488 13:57:07.804710 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4489 13:57:07.807739 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4490 13:57:07.810694 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4491 13:57:07.814845 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4492 13:57:07.820936 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4493 13:57:07.824322 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4494 13:57:07.827430 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4495 13:57:07.830556 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4496 13:57:07.837937 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4497 13:57:07.838539 ==
4498 13:57:07.840737 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 13:57:07.843871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 13:57:07.844337 ==
4501 13:57:07.844704 DQS Delay:
4502 13:57:07.847395 DQS0 = 0, DQS1 = 0
4503 13:57:07.847978 DQM Delay:
4504 13:57:07.850957 DQM0 = 53, DQM1 = 41
4505 13:57:07.851418 DQ Delay:
4506 13:57:07.853780 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4507 13:57:07.857761 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4508 13:57:07.860793 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4509 13:57:07.863985 DQ12 =57, DQ13 =57, DQ14 =41, DQ15 =41
4510 13:57:07.864452
4511 13:57:07.864815
4512 13:57:07.865152 ==
4513 13:57:07.867531 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 13:57:07.870997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 13:57:07.871570 ==
4516 13:57:07.871944
4517 13:57:07.872313
4518 13:57:07.874262 TX Vref Scan disable
4519 13:57:07.877028 == TX Byte 0 ==
4520 13:57:07.880520 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4521 13:57:07.883804 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4522 13:57:07.887126 == TX Byte 1 ==
4523 13:57:07.890537 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4524 13:57:07.893890 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4525 13:57:07.894674 ==
4526 13:57:07.897031 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 13:57:07.903607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 13:57:07.904178 ==
4529 13:57:07.904558
4530 13:57:07.904900
4531 13:57:07.905229 TX Vref Scan disable
4532 13:57:07.908436 == TX Byte 0 ==
4533 13:57:07.911722 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4534 13:57:07.918257 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4535 13:57:07.918838 == TX Byte 1 ==
4536 13:57:07.921511 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4537 13:57:07.928620 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4538 13:57:07.929190
4539 13:57:07.929560 [DATLAT]
4540 13:57:07.929907 Freq=600, CH1 RK0
4541 13:57:07.930280
4542 13:57:07.931252 DATLAT Default: 0x9
4543 13:57:07.931720 0, 0xFFFF, sum = 0
4544 13:57:07.935030 1, 0xFFFF, sum = 0
4545 13:57:07.935605 2, 0xFFFF, sum = 0
4546 13:57:07.938127 3, 0xFFFF, sum = 0
4547 13:57:07.941859 4, 0xFFFF, sum = 0
4548 13:57:07.942706 5, 0xFFFF, sum = 0
4549 13:57:07.945013 6, 0xFFFF, sum = 0
4550 13:57:07.945581 7, 0xFFFF, sum = 0
4551 13:57:07.948175 8, 0x0, sum = 1
4552 13:57:07.948650 9, 0x0, sum = 2
4553 13:57:07.949029 10, 0x0, sum = 3
4554 13:57:07.951426 11, 0x0, sum = 4
4555 13:57:07.951901 best_step = 9
4556 13:57:07.952270
4557 13:57:07.952660 ==
4558 13:57:07.954831 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 13:57:07.961654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 13:57:07.962271 ==
4561 13:57:07.962652 RX Vref Scan: 1
4562 13:57:07.962998
4563 13:57:07.964661 RX Vref 0 -> 0, step: 1
4564 13:57:07.965122
4565 13:57:07.968075 RX Delay -179 -> 252, step: 8
4566 13:57:07.968641
4567 13:57:07.971606 Set Vref, RX VrefLevel [Byte0]: 53
4568 13:57:07.974623 [Byte1]: 52
4569 13:57:07.975192
4570 13:57:07.978044 Final RX Vref Byte 0 = 53 to rank0
4571 13:57:07.981310 Final RX Vref Byte 1 = 52 to rank0
4572 13:57:07.985207 Final RX Vref Byte 0 = 53 to rank1
4573 13:57:07.987707 Final RX Vref Byte 1 = 52 to rank1==
4574 13:57:07.991265 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 13:57:07.994544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 13:57:07.995015 ==
4577 13:57:07.997737 DQS Delay:
4578 13:57:07.998336 DQS0 = 0, DQS1 = 0
4579 13:57:08.001114 DQM Delay:
4580 13:57:08.001577 DQM0 = 48, DQM1 = 41
4581 13:57:08.001975 DQ Delay:
4582 13:57:08.004621 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4583 13:57:08.007493 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4584 13:57:08.011370 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4585 13:57:08.014310 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4586 13:57:08.014781
4587 13:57:08.015148
4588 13:57:08.024564 [DQSOSCAuto] RK0, (LSB)MR18= 0x466d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4589 13:57:08.027867 CH1 RK0: MR19=808, MR18=466D
4590 13:57:08.030962 CH1_RK0: MR19=0x808, MR18=0x466D, DQSOSC=389, MR23=63, INC=173, DEC=115
4591 13:57:08.034534
4592 13:57:08.037842 ----->DramcWriteLeveling(PI) begin...
4593 13:57:08.038439 ==
4594 13:57:08.041136 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 13:57:08.044147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 13:57:08.044634 ==
4597 13:57:08.047330 Write leveling (Byte 0): 30 => 30
4598 13:57:08.051333 Write leveling (Byte 1): 30 => 30
4599 13:57:08.054583 DramcWriteLeveling(PI) end<-----
4600 13:57:08.055151
4601 13:57:08.055523 ==
4602 13:57:08.058237 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 13:57:08.061253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 13:57:08.061825 ==
4605 13:57:08.064248 [Gating] SW mode calibration
4606 13:57:08.070717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4607 13:57:08.077575 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4608 13:57:08.081317 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 13:57:08.084290 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 13:57:08.091111 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4611 13:57:08.093998 0 9 12 | B1->B0 | 2b2b 3131 | 0 1 | (1 0) (1 0)
4612 13:57:08.097672 0 9 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4613 13:57:08.103858 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 13:57:08.107290 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 13:57:08.110532 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 13:57:08.117255 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 13:57:08.120451 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 13:57:08.124078 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 13:57:08.130270 0 10 12 | B1->B0 | 3838 2828 | 0 0 | (0 0) (0 0)
4620 13:57:08.133893 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 13:57:08.137028 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 13:57:08.143653 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 13:57:08.147101 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 13:57:08.150753 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 13:57:08.157228 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 13:57:08.160788 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 13:57:08.163956 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4628 13:57:08.167194 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 13:57:08.173531 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 13:57:08.177210 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 13:57:08.180621 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 13:57:08.186630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 13:57:08.190798 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 13:57:08.193458 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 13:57:08.199989 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 13:57:08.203421 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 13:57:08.206735 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 13:57:08.213282 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 13:57:08.216793 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:57:08.219914 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:57:08.226749 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:57:08.229679 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:57:08.233265 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4644 13:57:08.239862 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 13:57:08.240438 Total UI for P1: 0, mck2ui 16
4646 13:57:08.246449 best dqsien dly found for B0: ( 0, 13, 12)
4647 13:57:08.247011 Total UI for P1: 0, mck2ui 16
4648 13:57:08.253367 best dqsien dly found for B1: ( 0, 13, 12)
4649 13:57:08.256646 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4650 13:57:08.259501 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4651 13:57:08.259972
4652 13:57:08.263596 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4653 13:57:08.266255 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4654 13:57:08.269844 [Gating] SW calibration Done
4655 13:57:08.270462 ==
4656 13:57:08.273026 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 13:57:08.276632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 13:57:08.277211 ==
4659 13:57:08.279807 RX Vref Scan: 0
4660 13:57:08.280285
4661 13:57:08.280787 RX Vref 0 -> 0, step: 1
4662 13:57:08.281159
4663 13:57:08.282790 RX Delay -230 -> 252, step: 16
4664 13:57:08.289788 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4665 13:57:08.293174 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4666 13:57:08.296550 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4667 13:57:08.299664 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4668 13:57:08.302644 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4669 13:57:08.309435 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4670 13:57:08.312656 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4671 13:57:08.316661 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4672 13:57:08.319230 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4673 13:57:08.325631 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4674 13:57:08.329271 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4675 13:57:08.332460 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4676 13:57:08.336105 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4677 13:57:08.342589 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4678 13:57:08.345476 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4679 13:57:08.349539 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4680 13:57:08.350170 ==
4681 13:57:08.352477 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 13:57:08.355736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 13:57:08.356206 ==
4684 13:57:08.358832 DQS Delay:
4685 13:57:08.359293 DQS0 = 0, DQS1 = 0
4686 13:57:08.362541 DQM Delay:
4687 13:57:08.363177 DQM0 = 51, DQM1 = 47
4688 13:57:08.363546 DQ Delay:
4689 13:57:08.365882 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4690 13:57:08.369366 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4691 13:57:08.372648 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4692 13:57:08.375729 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4693 13:57:08.376190
4694 13:57:08.376554
4695 13:57:08.379348 ==
4696 13:57:08.382821 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 13:57:08.385714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 13:57:08.386233 ==
4699 13:57:08.386602
4700 13:57:08.386938
4701 13:57:08.389098 TX Vref Scan disable
4702 13:57:08.389679 == TX Byte 0 ==
4703 13:57:08.395493 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 13:57:08.399292 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 13:57:08.399882 == TX Byte 1 ==
4706 13:57:08.405618 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 13:57:08.408852 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 13:57:08.409420 ==
4709 13:57:08.412749 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 13:57:08.415296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 13:57:08.415765 ==
4712 13:57:08.416130
4713 13:57:08.416467
4714 13:57:08.418562 TX Vref Scan disable
4715 13:57:08.422328 == TX Byte 0 ==
4716 13:57:08.425159 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4717 13:57:08.428519 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4718 13:57:08.431918 == TX Byte 1 ==
4719 13:57:08.435370 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4720 13:57:08.438696 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4721 13:57:08.439265
4722 13:57:08.441796 [DATLAT]
4723 13:57:08.442297 Freq=600, CH1 RK1
4724 13:57:08.442674
4725 13:57:08.445306 DATLAT Default: 0x9
4726 13:57:08.445847 0, 0xFFFF, sum = 0
4727 13:57:08.448662 1, 0xFFFF, sum = 0
4728 13:57:08.449141 2, 0xFFFF, sum = 0
4729 13:57:08.452112 3, 0xFFFF, sum = 0
4730 13:57:08.452737 4, 0xFFFF, sum = 0
4731 13:57:08.455111 5, 0xFFFF, sum = 0
4732 13:57:08.455596 6, 0xFFFF, sum = 0
4733 13:57:08.458679 7, 0xFFFF, sum = 0
4734 13:57:08.459157 8, 0x0, sum = 1
4735 13:57:08.461867 9, 0x0, sum = 2
4736 13:57:08.462512 10, 0x0, sum = 3
4737 13:57:08.465503 11, 0x0, sum = 4
4738 13:57:08.466135 best_step = 9
4739 13:57:08.466518
4740 13:57:08.466886 ==
4741 13:57:08.468553 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 13:57:08.472649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 13:57:08.475300 ==
4744 13:57:08.475877 RX Vref Scan: 0
4745 13:57:08.476271
4746 13:57:08.478580 RX Vref 0 -> 0, step: 1
4747 13:57:08.479049
4748 13:57:08.481497 RX Delay -163 -> 252, step: 8
4749 13:57:08.485243 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4750 13:57:08.488301 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4751 13:57:08.495258 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4752 13:57:08.498624 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4753 13:57:08.502046 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4754 13:57:08.505231 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4755 13:57:08.508804 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4756 13:57:08.514900 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4757 13:57:08.518150 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4758 13:57:08.521795 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4759 13:57:08.525370 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4760 13:57:08.528285 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4761 13:57:08.534983 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4762 13:57:08.538200 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4763 13:57:08.541813 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4764 13:57:08.544779 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4765 13:57:08.545254 ==
4766 13:57:08.548265 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 13:57:08.554972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 13:57:08.555470 ==
4769 13:57:08.555863 DQS Delay:
4770 13:57:08.558110 DQS0 = 0, DQS1 = 0
4771 13:57:08.558596 DQM Delay:
4772 13:57:08.559137 DQM0 = 49, DQM1 = 43
4773 13:57:08.561607 DQ Delay:
4774 13:57:08.565189 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4775 13:57:08.567928 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4776 13:57:08.571220 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4777 13:57:08.574912 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4778 13:57:08.575482
4779 13:57:08.575858
4780 13:57:08.581779 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4781 13:57:08.584631 CH1 RK1: MR19=808, MR18=5B22
4782 13:57:08.591444 CH1_RK1: MR19=0x808, MR18=0x5B22, DQSOSC=392, MR23=63, INC=170, DEC=113
4783 13:57:08.594834 [RxdqsGatingPostProcess] freq 600
4784 13:57:08.597972 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4785 13:57:08.601258 Pre-setting of DQS Precalculation
4786 13:57:08.607864 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4787 13:57:08.614840 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4788 13:57:08.621563 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4789 13:57:08.622183
4790 13:57:08.622561
4791 13:57:08.624525 [Calibration Summary] 1200 Mbps
4792 13:57:08.625094 CH 0, Rank 0
4793 13:57:08.627962 SW Impedance : PASS
4794 13:57:08.631269 DUTY Scan : NO K
4795 13:57:08.631833 ZQ Calibration : PASS
4796 13:57:08.634191 Jitter Meter : NO K
4797 13:57:08.637915 CBT Training : PASS
4798 13:57:08.638516 Write leveling : PASS
4799 13:57:08.641053 RX DQS gating : PASS
4800 13:57:08.644346 RX DQ/DQS(RDDQC) : PASS
4801 13:57:08.644910 TX DQ/DQS : PASS
4802 13:57:08.648026 RX DATLAT : PASS
4803 13:57:08.650798 RX DQ/DQS(Engine): PASS
4804 13:57:08.651276 TX OE : NO K
4805 13:57:08.651652 All Pass.
4806 13:57:08.654407
4807 13:57:08.654872 CH 0, Rank 1
4808 13:57:08.657744 SW Impedance : PASS
4809 13:57:08.658212 DUTY Scan : NO K
4810 13:57:08.660994 ZQ Calibration : PASS
4811 13:57:08.664135 Jitter Meter : NO K
4812 13:57:08.664606 CBT Training : PASS
4813 13:57:08.667765 Write leveling : PASS
4814 13:57:08.668231 RX DQS gating : PASS
4815 13:57:08.671022 RX DQ/DQS(RDDQC) : PASS
4816 13:57:08.674461 TX DQ/DQS : PASS
4817 13:57:08.675030 RX DATLAT : PASS
4818 13:57:08.678334 RX DQ/DQS(Engine): PASS
4819 13:57:08.681200 TX OE : NO K
4820 13:57:08.681766 All Pass.
4821 13:57:08.682168
4822 13:57:08.682518 CH 1, Rank 0
4823 13:57:08.684523 SW Impedance : PASS
4824 13:57:08.687832 DUTY Scan : NO K
4825 13:57:08.688304 ZQ Calibration : PASS
4826 13:57:08.691453 Jitter Meter : NO K
4827 13:57:08.694857 CBT Training : PASS
4828 13:57:08.695426 Write leveling : PASS
4829 13:57:08.697852 RX DQS gating : PASS
4830 13:57:08.701314 RX DQ/DQS(RDDQC) : PASS
4831 13:57:08.701882 TX DQ/DQS : PASS
4832 13:57:08.704367 RX DATLAT : PASS
4833 13:57:08.704935 RX DQ/DQS(Engine): PASS
4834 13:57:08.707597 TX OE : NO K
4835 13:57:08.708073 All Pass.
4836 13:57:08.708447
4837 13:57:08.711199 CH 1, Rank 1
4838 13:57:08.711764 SW Impedance : PASS
4839 13:57:08.714355 DUTY Scan : NO K
4840 13:57:08.717987 ZQ Calibration : PASS
4841 13:57:08.718459 Jitter Meter : NO K
4842 13:57:08.720973 CBT Training : PASS
4843 13:57:08.724245 Write leveling : PASS
4844 13:57:08.724712 RX DQS gating : PASS
4845 13:57:08.727776 RX DQ/DQS(RDDQC) : PASS
4846 13:57:08.730949 TX DQ/DQS : PASS
4847 13:57:08.731419 RX DATLAT : PASS
4848 13:57:08.734204 RX DQ/DQS(Engine): PASS
4849 13:57:08.738029 TX OE : NO K
4850 13:57:08.738588 All Pass.
4851 13:57:08.738958
4852 13:57:08.739303 DramC Write-DBI off
4853 13:57:08.740821 PER_BANK_REFRESH: Hybrid Mode
4854 13:57:08.744297 TX_TRACKING: ON
4855 13:57:08.751144 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4856 13:57:08.753935 [FAST_K] Save calibration result to emmc
4857 13:57:08.761002 dramc_set_vcore_voltage set vcore to 662500
4858 13:57:08.761586 Read voltage for 933, 3
4859 13:57:08.764167 Vio18 = 0
4860 13:57:08.764646 Vcore = 662500
4861 13:57:08.765122 Vdram = 0
4862 13:57:08.765572 Vddq = 0
4863 13:57:08.767361 Vmddr = 0
4864 13:57:08.770787 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4865 13:57:08.777720 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4866 13:57:08.780942 MEM_TYPE=3, freq_sel=17
4867 13:57:08.781525 sv_algorithm_assistance_LP4_1600
4868 13:57:08.787725 ============ PULL DRAM RESETB DOWN ============
4869 13:57:08.790673 ========== PULL DRAM RESETB DOWN end =========
4870 13:57:08.793889 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 13:57:08.797550 ===================================
4872 13:57:08.800424 LPDDR4 DRAM CONFIGURATION
4873 13:57:08.803551 ===================================
4874 13:57:08.806677 EX_ROW_EN[0] = 0x0
4875 13:57:08.806761 EX_ROW_EN[1] = 0x0
4876 13:57:08.809871 LP4Y_EN = 0x0
4877 13:57:08.810016 WORK_FSP = 0x0
4878 13:57:08.813749 WL = 0x3
4879 13:57:08.814249 RL = 0x3
4880 13:57:08.817272 BL = 0x2
4881 13:57:08.817840 RPST = 0x0
4882 13:57:08.820635 RD_PRE = 0x0
4883 13:57:08.821107 WR_PRE = 0x1
4884 13:57:08.823847 WR_PST = 0x0
4885 13:57:08.824322 DBI_WR = 0x0
4886 13:57:08.827205 DBI_RD = 0x0
4887 13:57:08.830431 OTF = 0x1
4888 13:57:08.830908 ===================================
4889 13:57:08.833800 ===================================
4890 13:57:08.837360 ANA top config
4891 13:57:08.840928 ===================================
4892 13:57:08.844062 DLL_ASYNC_EN = 0
4893 13:57:08.844630 ALL_SLAVE_EN = 1
4894 13:57:08.847191 NEW_RANK_MODE = 1
4895 13:57:08.850396 DLL_IDLE_MODE = 1
4896 13:57:08.853601 LP45_APHY_COMB_EN = 1
4897 13:57:08.857273 TX_ODT_DIS = 1
4898 13:57:08.857838 NEW_8X_MODE = 1
4899 13:57:08.860690 ===================================
4900 13:57:08.863585 ===================================
4901 13:57:08.866975 data_rate = 1866
4902 13:57:08.870521 CKR = 1
4903 13:57:08.873701 DQ_P2S_RATIO = 8
4904 13:57:08.877282 ===================================
4905 13:57:08.880294 CA_P2S_RATIO = 8
4906 13:57:08.883538 DQ_CA_OPEN = 0
4907 13:57:08.884007 DQ_SEMI_OPEN = 0
4908 13:57:08.886794 CA_SEMI_OPEN = 0
4909 13:57:08.890043 CA_FULL_RATE = 0
4910 13:57:08.893647 DQ_CKDIV4_EN = 1
4911 13:57:08.897272 CA_CKDIV4_EN = 1
4912 13:57:08.900599 CA_PREDIV_EN = 0
4913 13:57:08.901172 PH8_DLY = 0
4914 13:57:08.903297 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4915 13:57:08.906822 DQ_AAMCK_DIV = 4
4916 13:57:08.910386 CA_AAMCK_DIV = 4
4917 13:57:08.913590 CA_ADMCK_DIV = 4
4918 13:57:08.916783 DQ_TRACK_CA_EN = 0
4919 13:57:08.917354 CA_PICK = 933
4920 13:57:08.920379 CA_MCKIO = 933
4921 13:57:08.923621 MCKIO_SEMI = 0
4922 13:57:08.926852 PLL_FREQ = 3732
4923 13:57:08.930102 DQ_UI_PI_RATIO = 32
4924 13:57:08.933417 CA_UI_PI_RATIO = 0
4925 13:57:08.936951 ===================================
4926 13:57:08.940131 ===================================
4927 13:57:08.940700 memory_type:LPDDR4
4928 13:57:08.943269 GP_NUM : 10
4929 13:57:08.946720 SRAM_EN : 1
4930 13:57:08.947193 MD32_EN : 0
4931 13:57:08.950134 ===================================
4932 13:57:08.953180 [ANA_INIT] >>>>>>>>>>>>>>
4933 13:57:08.956773 <<<<<< [CONFIGURE PHASE]: ANA_TX
4934 13:57:08.960225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4935 13:57:08.963063 ===================================
4936 13:57:08.966687 data_rate = 1866,PCW = 0X8f00
4937 13:57:08.970059 ===================================
4938 13:57:08.973612 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4939 13:57:08.977169 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 13:57:08.983523 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 13:57:08.986481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4942 13:57:08.989559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4943 13:57:08.993217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4944 13:57:08.996345 [ANA_INIT] flow start
4945 13:57:08.999786 [ANA_INIT] PLL >>>>>>>>
4946 13:57:09.000257 [ANA_INIT] PLL <<<<<<<<
4947 13:57:09.003130 [ANA_INIT] MIDPI >>>>>>>>
4948 13:57:09.006659 [ANA_INIT] MIDPI <<<<<<<<
4949 13:57:09.009842 [ANA_INIT] DLL >>>>>>>>
4950 13:57:09.010455 [ANA_INIT] flow end
4951 13:57:09.013061 ============ LP4 DIFF to SE enter ============
4952 13:57:09.019567 ============ LP4 DIFF to SE exit ============
4953 13:57:09.020134 [ANA_INIT] <<<<<<<<<<<<<
4954 13:57:09.022931 [Flow] Enable top DCM control >>>>>
4955 13:57:09.026145 [Flow] Enable top DCM control <<<<<
4956 13:57:09.029645 Enable DLL master slave shuffle
4957 13:57:09.036480 ==============================================================
4958 13:57:09.037050 Gating Mode config
4959 13:57:09.042867 ==============================================================
4960 13:57:09.046396 Config description:
4961 13:57:09.056119 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4962 13:57:09.062899 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4963 13:57:09.066366 SELPH_MODE 0: By rank 1: By Phase
4964 13:57:09.072847 ==============================================================
4965 13:57:09.076235 GAT_TRACK_EN = 1
4966 13:57:09.076712 RX_GATING_MODE = 2
4967 13:57:09.080036 RX_GATING_TRACK_MODE = 2
4968 13:57:09.082704 SELPH_MODE = 1
4969 13:57:09.086353 PICG_EARLY_EN = 1
4970 13:57:09.089343 VALID_LAT_VALUE = 1
4971 13:57:09.096066 ==============================================================
4972 13:57:09.099200 Enter into Gating configuration >>>>
4973 13:57:09.102438 Exit from Gating configuration <<<<
4974 13:57:09.105660 Enter into DVFS_PRE_config >>>>>
4975 13:57:09.116121 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4976 13:57:09.119444 Exit from DVFS_PRE_config <<<<<
4977 13:57:09.122510 Enter into PICG configuration >>>>
4978 13:57:09.125988 Exit from PICG configuration <<<<
4979 13:57:09.129477 [RX_INPUT] configuration >>>>>
4980 13:57:09.133042 [RX_INPUT] configuration <<<<<
4981 13:57:09.136345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4982 13:57:09.142846 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4983 13:57:09.149090 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 13:57:09.152619 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 13:57:09.159057 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 13:57:09.165972 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 13:57:09.169171 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4988 13:57:09.175660 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4989 13:57:09.178861 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4990 13:57:09.182506 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4991 13:57:09.185779 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4992 13:57:09.192568 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 13:57:09.195829 ===================================
4994 13:57:09.196398 LPDDR4 DRAM CONFIGURATION
4995 13:57:09.198754 ===================================
4996 13:57:09.202017 EX_ROW_EN[0] = 0x0
4997 13:57:09.205403 EX_ROW_EN[1] = 0x0
4998 13:57:09.205999 LP4Y_EN = 0x0
4999 13:57:09.208798 WORK_FSP = 0x0
5000 13:57:09.209271 WL = 0x3
5001 13:57:09.212207 RL = 0x3
5002 13:57:09.212804 BL = 0x2
5003 13:57:09.215457 RPST = 0x0
5004 13:57:09.216020 RD_PRE = 0x0
5005 13:57:09.219187 WR_PRE = 0x1
5006 13:57:09.219764 WR_PST = 0x0
5007 13:57:09.221867 DBI_WR = 0x0
5008 13:57:09.222369 DBI_RD = 0x0
5009 13:57:09.225558 OTF = 0x1
5010 13:57:09.228621 ===================================
5011 13:57:09.231885 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5012 13:57:09.235639 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5013 13:57:09.242474 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5014 13:57:09.245538 ===================================
5015 13:57:09.246143 LPDDR4 DRAM CONFIGURATION
5016 13:57:09.248615 ===================================
5017 13:57:09.252413 EX_ROW_EN[0] = 0x10
5018 13:57:09.255334 EX_ROW_EN[1] = 0x0
5019 13:57:09.255804 LP4Y_EN = 0x0
5020 13:57:09.258747 WORK_FSP = 0x0
5021 13:57:09.259318 WL = 0x3
5022 13:57:09.261790 RL = 0x3
5023 13:57:09.262314 BL = 0x2
5024 13:57:09.265425 RPST = 0x0
5025 13:57:09.266052 RD_PRE = 0x0
5026 13:57:09.268694 WR_PRE = 0x1
5027 13:57:09.269164 WR_PST = 0x0
5028 13:57:09.272093 DBI_WR = 0x0
5029 13:57:09.272659 DBI_RD = 0x0
5030 13:57:09.275522 OTF = 0x1
5031 13:57:09.278742 ===================================
5032 13:57:09.284998 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5033 13:57:09.288792 nWR fixed to 30
5034 13:57:09.289364 [ModeRegInit_LP4] CH0 RK0
5035 13:57:09.291957 [ModeRegInit_LP4] CH0 RK1
5036 13:57:09.295118 [ModeRegInit_LP4] CH1 RK0
5037 13:57:09.295687 [ModeRegInit_LP4] CH1 RK1
5038 13:57:09.298533 match AC timing 9
5039 13:57:09.302127 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5040 13:57:09.304931 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5041 13:57:09.311801 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5042 13:57:09.315319 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5043 13:57:09.321501 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5044 13:57:09.322095 ==
5045 13:57:09.325222 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 13:57:09.328433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 13:57:09.328906 ==
5048 13:57:09.335186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 13:57:09.338322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5050 13:57:09.342780 [CA 0] Center 37 (7~68) winsize 62
5051 13:57:09.346083 [CA 1] Center 37 (7~68) winsize 62
5052 13:57:09.349866 [CA 2] Center 35 (5~66) winsize 62
5053 13:57:09.352948 [CA 3] Center 34 (4~65) winsize 62
5054 13:57:09.355888 [CA 4] Center 34 (4~64) winsize 61
5055 13:57:09.359529 [CA 5] Center 33 (3~64) winsize 62
5056 13:57:09.360103
5057 13:57:09.362777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5058 13:57:09.363342
5059 13:57:09.366258 [CATrainingPosCal] consider 1 rank data
5060 13:57:09.369746 u2DelayCellTimex100 = 270/100 ps
5061 13:57:09.373002 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5062 13:57:09.376240 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5063 13:57:09.382549 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5064 13:57:09.386028 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5065 13:57:09.389567 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5066 13:57:09.392856 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5067 13:57:09.393330
5068 13:57:09.395524 CA PerBit enable=1, Macro0, CA PI delay=33
5069 13:57:09.395609
5070 13:57:09.399258 [CBTSetCACLKResult] CA Dly = 33
5071 13:57:09.399423 CS Dly: 7 (0~38)
5072 13:57:09.402488 ==
5073 13:57:09.402653 Dram Type= 6, Freq= 0, CH_0, rank 1
5074 13:57:09.408744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 13:57:09.408913 ==
5076 13:57:09.412394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 13:57:09.418490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5078 13:57:09.422702 [CA 0] Center 38 (7~69) winsize 63
5079 13:57:09.426190 [CA 1] Center 38 (8~69) winsize 62
5080 13:57:09.429611 [CA 2] Center 36 (6~66) winsize 61
5081 13:57:09.432832 [CA 3] Center 35 (5~66) winsize 62
5082 13:57:09.435859 [CA 4] Center 34 (4~65) winsize 62
5083 13:57:09.439281 [CA 5] Center 34 (4~64) winsize 61
5084 13:57:09.439851
5085 13:57:09.442773 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5086 13:57:09.443343
5087 13:57:09.445867 [CATrainingPosCal] consider 2 rank data
5088 13:57:09.449591 u2DelayCellTimex100 = 270/100 ps
5089 13:57:09.452680 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5090 13:57:09.459843 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5091 13:57:09.462545 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5092 13:57:09.466064 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5093 13:57:09.469607 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5094 13:57:09.472766 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5095 13:57:09.473334
5096 13:57:09.476066 CA PerBit enable=1, Macro0, CA PI delay=34
5097 13:57:09.476638
5098 13:57:09.479138 [CBTSetCACLKResult] CA Dly = 34
5099 13:57:09.479705 CS Dly: 7 (0~39)
5100 13:57:09.482467
5101 13:57:09.486101 ----->DramcWriteLeveling(PI) begin...
5102 13:57:09.486668 ==
5103 13:57:09.489245 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 13:57:09.492302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 13:57:09.492875 ==
5106 13:57:09.495824 Write leveling (Byte 0): 31 => 31
5107 13:57:09.498911 Write leveling (Byte 1): 30 => 30
5108 13:57:09.502631 DramcWriteLeveling(PI) end<-----
5109 13:57:09.503343
5110 13:57:09.503761 ==
5111 13:57:09.505865 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 13:57:09.509378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 13:57:09.509987 ==
5114 13:57:09.512230 [Gating] SW mode calibration
5115 13:57:09.519401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5116 13:57:09.525690 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5117 13:57:09.528909 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5118 13:57:09.532491 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 13:57:09.538999 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 13:57:09.542112 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 13:57:09.545467 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 13:57:09.551908 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 13:57:09.555545 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5124 13:57:09.558701 0 14 28 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5125 13:57:09.565704 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5126 13:57:09.568937 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 13:57:09.572020 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 13:57:09.575470 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 13:57:09.582176 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 13:57:09.585463 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 13:57:09.589121 0 15 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5132 13:57:09.595267 0 15 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
5133 13:57:09.598743 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 13:57:09.602443 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 13:57:09.608525 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 13:57:09.612015 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 13:57:09.615559 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 13:57:09.621914 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 13:57:09.625512 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 13:57:09.628392 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5141 13:57:09.635042 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5142 13:57:09.638454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 13:57:09.642054 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 13:57:09.648790 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 13:57:09.651503 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 13:57:09.654858 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 13:57:09.662166 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 13:57:09.665304 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 13:57:09.668711 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 13:57:09.675167 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 13:57:09.678454 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 13:57:09.682236 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 13:57:09.688360 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:57:09.691534 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:57:09.694857 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5156 13:57:09.701727 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5157 13:57:09.704986 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 13:57:09.708279 Total UI for P1: 0, mck2ui 16
5159 13:57:09.711569 best dqsien dly found for B0: ( 1, 2, 26)
5160 13:57:09.715231 Total UI for P1: 0, mck2ui 16
5161 13:57:09.718211 best dqsien dly found for B1: ( 1, 2, 28)
5162 13:57:09.721912 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5163 13:57:09.725065 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5164 13:57:09.725536
5165 13:57:09.728406 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5166 13:57:09.731600 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5167 13:57:09.735011 [Gating] SW calibration Done
5168 13:57:09.735577 ==
5169 13:57:09.738322 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 13:57:09.741366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 13:57:09.741984 ==
5172 13:57:09.744651 RX Vref Scan: 0
5173 13:57:09.745322
5174 13:57:09.747844 RX Vref 0 -> 0, step: 1
5175 13:57:09.748403
5176 13:57:09.748777 RX Delay -80 -> 252, step: 8
5177 13:57:09.754866 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5178 13:57:09.758321 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5179 13:57:09.761436 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5180 13:57:09.764522 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5181 13:57:09.768017 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5182 13:57:09.774640 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5183 13:57:09.777871 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5184 13:57:09.781184 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5185 13:57:09.784565 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5186 13:57:09.788342 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5187 13:57:09.791325 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5188 13:57:09.797755 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5189 13:57:09.801007 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5190 13:57:09.804677 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5191 13:57:09.807722 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5192 13:57:09.811105 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5193 13:57:09.811616 ==
5194 13:57:09.814362 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 13:57:09.820844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 13:57:09.821622 ==
5197 13:57:09.822299 DQS Delay:
5198 13:57:09.824318 DQS0 = 0, DQS1 = 0
5199 13:57:09.825081 DQM Delay:
5200 13:57:09.825780 DQM0 = 106, DQM1 = 92
5201 13:57:09.827335 DQ Delay:
5202 13:57:09.830986 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5203 13:57:09.834105 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5204 13:57:09.837447 DQ8 =83, DQ9 =79, DQ10 =95, DQ11 =91
5205 13:57:09.840770 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5206 13:57:09.841233
5207 13:57:09.841595
5208 13:57:09.841928 ==
5209 13:57:09.844441 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 13:57:09.847526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 13:57:09.847993 ==
5212 13:57:09.848363
5213 13:57:09.848700
5214 13:57:09.851040 TX Vref Scan disable
5215 13:57:09.854338 == TX Byte 0 ==
5216 13:57:09.857396 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5217 13:57:09.860757 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5218 13:57:09.864087 == TX Byte 1 ==
5219 13:57:09.867957 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5220 13:57:09.870572 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5221 13:57:09.871049 ==
5222 13:57:09.874110 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 13:57:09.877616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 13:57:09.880958 ==
5225 13:57:09.881551
5226 13:57:09.881931
5227 13:57:09.882339 TX Vref Scan disable
5228 13:57:09.884627 == TX Byte 0 ==
5229 13:57:09.887711 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5230 13:57:09.894520 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5231 13:57:09.895102 == TX Byte 1 ==
5232 13:57:09.898130 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5233 13:57:09.904137 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5234 13:57:09.904746
5235 13:57:09.905139 [DATLAT]
5236 13:57:09.905485 Freq=933, CH0 RK0
5237 13:57:09.905817
5238 13:57:09.907474 DATLAT Default: 0xd
5239 13:57:09.907944 0, 0xFFFF, sum = 0
5240 13:57:09.911402 1, 0xFFFF, sum = 0
5241 13:57:09.911981 2, 0xFFFF, sum = 0
5242 13:57:09.914250 3, 0xFFFF, sum = 0
5243 13:57:09.917828 4, 0xFFFF, sum = 0
5244 13:57:09.918441 5, 0xFFFF, sum = 0
5245 13:57:09.921188 6, 0xFFFF, sum = 0
5246 13:57:09.921764 7, 0xFFFF, sum = 0
5247 13:57:09.924328 8, 0xFFFF, sum = 0
5248 13:57:09.924805 9, 0xFFFF, sum = 0
5249 13:57:09.927220 10, 0x0, sum = 1
5250 13:57:09.927698 11, 0x0, sum = 2
5251 13:57:09.930895 12, 0x0, sum = 3
5252 13:57:09.931473 13, 0x0, sum = 4
5253 13:57:09.931857 best_step = 11
5254 13:57:09.932203
5255 13:57:09.933897 ==
5256 13:57:09.937855 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 13:57:09.941090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 13:57:09.941659 ==
5259 13:57:09.942092 RX Vref Scan: 1
5260 13:57:09.942452
5261 13:57:09.944232 RX Vref 0 -> 0, step: 1
5262 13:57:09.944801
5263 13:57:09.947929 RX Delay -53 -> 252, step: 4
5264 13:57:09.948399
5265 13:57:09.951026 Set Vref, RX VrefLevel [Byte0]: 60
5266 13:57:09.954413 [Byte1]: 50
5267 13:57:09.955037
5268 13:57:09.957584 Final RX Vref Byte 0 = 60 to rank0
5269 13:57:09.960817 Final RX Vref Byte 1 = 50 to rank0
5270 13:57:09.964270 Final RX Vref Byte 0 = 60 to rank1
5271 13:57:09.967729 Final RX Vref Byte 1 = 50 to rank1==
5272 13:57:09.970692 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 13:57:09.974243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 13:57:09.974810 ==
5275 13:57:09.977440 DQS Delay:
5276 13:57:09.978039 DQS0 = 0, DQS1 = 0
5277 13:57:09.980719 DQM Delay:
5278 13:57:09.981184 DQM0 = 108, DQM1 = 92
5279 13:57:09.981553 DQ Delay:
5280 13:57:09.987568 DQ0 =106, DQ1 =106, DQ2 =106, DQ3 =106
5281 13:57:09.990660 DQ4 =108, DQ5 =100, DQ6 =116, DQ7 =116
5282 13:57:09.994249 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =92
5283 13:57:09.997438 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5284 13:57:09.998038
5285 13:57:09.998417
5286 13:57:10.004168 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5287 13:57:10.007398 CH0 RK0: MR19=505, MR18=2521
5288 13:57:10.014000 CH0_RK0: MR19=0x505, MR18=0x2521, DQSOSC=410, MR23=63, INC=64, DEC=42
5289 13:57:10.014556
5290 13:57:10.017436 ----->DramcWriteLeveling(PI) begin...
5291 13:57:10.018060 ==
5292 13:57:10.020333 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 13:57:10.023898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 13:57:10.024369 ==
5295 13:57:10.026854 Write leveling (Byte 0): 32 => 32
5296 13:57:10.030371 Write leveling (Byte 1): 31 => 31
5297 13:57:10.033582 DramcWriteLeveling(PI) end<-----
5298 13:57:10.034078
5299 13:57:10.034442 ==
5300 13:57:10.036802 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 13:57:10.040120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 13:57:10.040580 ==
5303 13:57:10.043885 [Gating] SW mode calibration
5304 13:57:10.050252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5305 13:57:10.056859 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5306 13:57:10.060120 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 13:57:10.066779 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 13:57:10.069768 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 13:57:10.073194 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 13:57:10.080061 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 13:57:10.083243 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 13:57:10.086422 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5313 13:57:10.092888 0 14 28 | B1->B0 | 2929 2525 | 1 0 | (0 0) (1 0)
5314 13:57:10.097029 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5315 13:57:10.099793 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 13:57:10.106606 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 13:57:10.110108 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 13:57:10.113363 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 13:57:10.119932 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 13:57:10.122904 0 15 24 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
5321 13:57:10.126426 0 15 28 | B1->B0 | 4040 4444 | 0 0 | (0 0) (0 0)
5322 13:57:10.133259 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 13:57:10.136186 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 13:57:10.140203 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 13:57:10.143332 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 13:57:10.150196 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 13:57:10.153004 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 13:57:10.156618 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 13:57:10.163437 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5330 13:57:10.166242 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5331 13:57:10.170055 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 13:57:10.176428 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 13:57:10.179552 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 13:57:10.182813 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 13:57:10.189402 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 13:57:10.192763 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 13:57:10.196441 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 13:57:10.202803 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 13:57:10.206275 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 13:57:10.209783 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 13:57:10.216101 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 13:57:10.219383 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:57:10.222856 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:57:10.229123 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5345 13:57:10.233155 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5346 13:57:10.235991 Total UI for P1: 0, mck2ui 16
5347 13:57:10.239379 best dqsien dly found for B1: ( 1, 2, 24)
5348 13:57:10.242602 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 13:57:10.246227 Total UI for P1: 0, mck2ui 16
5350 13:57:10.249469 best dqsien dly found for B0: ( 1, 2, 28)
5351 13:57:10.253015 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5352 13:57:10.256388 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5353 13:57:10.257000
5354 13:57:10.259480 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5355 13:57:10.266360 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5356 13:57:10.266916 [Gating] SW calibration Done
5357 13:57:10.267275 ==
5358 13:57:10.269395 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 13:57:10.276009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 13:57:10.276572 ==
5361 13:57:10.276932 RX Vref Scan: 0
5362 13:57:10.277261
5363 13:57:10.279067 RX Vref 0 -> 0, step: 1
5364 13:57:10.279766
5365 13:57:10.282313 RX Delay -80 -> 252, step: 8
5366 13:57:10.285588 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5367 13:57:10.288952 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5368 13:57:10.292241 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5369 13:57:10.299186 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5370 13:57:10.302323 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5371 13:57:10.305562 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5372 13:57:10.308630 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5373 13:57:10.312666 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5374 13:57:10.315455 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5375 13:57:10.322446 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5376 13:57:10.325108 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5377 13:57:10.329047 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5378 13:57:10.332041 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5379 13:57:10.335481 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5380 13:57:10.341871 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5381 13:57:10.345180 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5382 13:57:10.345729 ==
5383 13:57:10.348283 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 13:57:10.351682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 13:57:10.352237 ==
5386 13:57:10.352600 DQS Delay:
5387 13:57:10.355424 DQS0 = 0, DQS1 = 0
5388 13:57:10.355970 DQM Delay:
5389 13:57:10.358254 DQM0 = 104, DQM1 = 90
5390 13:57:10.358705 DQ Delay:
5391 13:57:10.362012 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5392 13:57:10.365039 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5393 13:57:10.368512 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5394 13:57:10.371362 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5395 13:57:10.371819
5396 13:57:10.372172
5397 13:57:10.372499 ==
5398 13:57:10.374795 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 13:57:10.381401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 13:57:10.381996 ==
5401 13:57:10.382415
5402 13:57:10.382984
5403 13:57:10.383321 TX Vref Scan disable
5404 13:57:10.385157 == TX Byte 0 ==
5405 13:57:10.388441 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5406 13:57:10.394916 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5407 13:57:10.395486 == TX Byte 1 ==
5408 13:57:10.398620 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5409 13:57:10.401598 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5410 13:57:10.405033 ==
5411 13:57:10.408485 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 13:57:10.411913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 13:57:10.412474 ==
5414 13:57:10.412844
5415 13:57:10.413186
5416 13:57:10.414870 TX Vref Scan disable
5417 13:57:10.415331 == TX Byte 0 ==
5418 13:57:10.422052 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5419 13:57:10.424755 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5420 13:57:10.425216 == TX Byte 1 ==
5421 13:57:10.431589 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5422 13:57:10.435142 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5423 13:57:10.435607
5424 13:57:10.435970 [DATLAT]
5425 13:57:10.438671 Freq=933, CH0 RK1
5426 13:57:10.439243
5427 13:57:10.439609 DATLAT Default: 0xb
5428 13:57:10.441573 0, 0xFFFF, sum = 0
5429 13:57:10.442120 1, 0xFFFF, sum = 0
5430 13:57:10.444979 2, 0xFFFF, sum = 0
5431 13:57:10.445572 3, 0xFFFF, sum = 0
5432 13:57:10.448397 4, 0xFFFF, sum = 0
5433 13:57:10.448866 5, 0xFFFF, sum = 0
5434 13:57:10.451580 6, 0xFFFF, sum = 0
5435 13:57:10.455086 7, 0xFFFF, sum = 0
5436 13:57:10.455660 8, 0xFFFF, sum = 0
5437 13:57:10.457983 9, 0xFFFF, sum = 0
5438 13:57:10.458455 10, 0x0, sum = 1
5439 13:57:10.458829 11, 0x0, sum = 2
5440 13:57:10.461665 12, 0x0, sum = 3
5441 13:57:10.462285 13, 0x0, sum = 4
5442 13:57:10.464781 best_step = 11
5443 13:57:10.465344
5444 13:57:10.465706 ==
5445 13:57:10.468324 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 13:57:10.471554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 13:57:10.472021 ==
5448 13:57:10.475065 RX Vref Scan: 0
5449 13:57:10.475631
5450 13:57:10.475995 RX Vref 0 -> 0, step: 1
5451 13:57:10.478220
5452 13:57:10.478785 RX Delay -53 -> 252, step: 4
5453 13:57:10.485678 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5454 13:57:10.488713 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5455 13:57:10.492393 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5456 13:57:10.495526 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5457 13:57:10.498696 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5458 13:57:10.505218 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5459 13:57:10.508997 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5460 13:57:10.511978 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5461 13:57:10.515052 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5462 13:57:10.518382 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5463 13:57:10.522579 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5464 13:57:10.528382 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5465 13:57:10.532163 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5466 13:57:10.535205 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5467 13:57:10.538492 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5468 13:57:10.542008 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5469 13:57:10.545292 ==
5470 13:57:10.548883 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 13:57:10.552175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 13:57:10.552750 ==
5473 13:57:10.553120 DQS Delay:
5474 13:57:10.555163 DQS0 = 0, DQS1 = 0
5475 13:57:10.555734 DQM Delay:
5476 13:57:10.558420 DQM0 = 103, DQM1 = 91
5477 13:57:10.558885 DQ Delay:
5478 13:57:10.561910 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =98
5479 13:57:10.565076 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5480 13:57:10.568291 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5481 13:57:10.571814 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5482 13:57:10.572282
5483 13:57:10.572644
5484 13:57:10.581763 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5485 13:57:10.582378 CH0 RK1: MR19=505, MR18=2A0B
5486 13:57:10.588346 CH0_RK1: MR19=0x505, MR18=0x2A0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5487 13:57:10.591702 [RxdqsGatingPostProcess] freq 933
5488 13:57:10.598107 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5489 13:57:10.601459 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 13:57:10.604615 best DQS1 dly(2T, 0.5T) = (0, 10)
5491 13:57:10.608379 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 13:57:10.611179 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5493 13:57:10.614667 best DQS0 dly(2T, 0.5T) = (0, 10)
5494 13:57:10.615248 best DQS1 dly(2T, 0.5T) = (0, 10)
5495 13:57:10.617847 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5496 13:57:10.621286 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5497 13:57:10.624707 Pre-setting of DQS Precalculation
5498 13:57:10.631255 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5499 13:57:10.631721 ==
5500 13:57:10.634437 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 13:57:10.637589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 13:57:10.638212 ==
5503 13:57:10.644267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5504 13:57:10.650985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5505 13:57:10.654075 [CA 0] Center 37 (7~68) winsize 62
5506 13:57:10.657544 [CA 1] Center 37 (7~68) winsize 62
5507 13:57:10.660790 [CA 2] Center 35 (5~66) winsize 62
5508 13:57:10.664656 [CA 3] Center 34 (4~65) winsize 62
5509 13:57:10.667636 [CA 4] Center 35 (5~66) winsize 62
5510 13:57:10.670898 [CA 5] Center 34 (4~65) winsize 62
5511 13:57:10.671361
5512 13:57:10.674681 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5513 13:57:10.675247
5514 13:57:10.678082 [CATrainingPosCal] consider 1 rank data
5515 13:57:10.680749 u2DelayCellTimex100 = 270/100 ps
5516 13:57:10.684292 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5517 13:57:10.688117 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5518 13:57:10.691109 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5519 13:57:10.694589 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5520 13:57:10.698036 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5521 13:57:10.701129 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5522 13:57:10.701699
5523 13:57:10.704895 CA PerBit enable=1, Macro0, CA PI delay=34
5524 13:57:10.705460
5525 13:57:10.707822 [CBTSetCACLKResult] CA Dly = 34
5526 13:57:10.710970 CS Dly: 6 (0~37)
5527 13:57:10.711535 ==
5528 13:57:10.714239 Dram Type= 6, Freq= 0, CH_1, rank 1
5529 13:57:10.718059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 13:57:10.718618 ==
5531 13:57:10.724471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5532 13:57:10.731011 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5533 13:57:10.734347 [CA 0] Center 37 (7~68) winsize 62
5534 13:57:10.737246 [CA 1] Center 38 (7~69) winsize 63
5535 13:57:10.740527 [CA 2] Center 36 (6~66) winsize 61
5536 13:57:10.744175 [CA 3] Center 35 (6~65) winsize 60
5537 13:57:10.747392 [CA 4] Center 35 (5~65) winsize 61
5538 13:57:10.751054 [CA 5] Center 34 (4~64) winsize 61
5539 13:57:10.751618
5540 13:57:10.754204 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5541 13:57:10.754666
5542 13:57:10.757583 [CATrainingPosCal] consider 2 rank data
5543 13:57:10.760810 u2DelayCellTimex100 = 270/100 ps
5544 13:57:10.764150 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5545 13:57:10.767579 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5546 13:57:10.770951 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5547 13:57:10.774461 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5548 13:57:10.777664 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5549 13:57:10.781095 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5550 13:57:10.781662
5551 13:57:10.787553 CA PerBit enable=1, Macro0, CA PI delay=34
5552 13:57:10.788124
5553 13:57:10.788497 [CBTSetCACLKResult] CA Dly = 34
5554 13:57:10.791083 CS Dly: 7 (0~39)
5555 13:57:10.791649
5556 13:57:10.794276 ----->DramcWriteLeveling(PI) begin...
5557 13:57:10.794852 ==
5558 13:57:10.797449 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 13:57:10.800757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 13:57:10.801325 ==
5561 13:57:10.804265 Write leveling (Byte 0): 26 => 26
5562 13:57:10.807334 Write leveling (Byte 1): 29 => 29
5563 13:57:10.810723 DramcWriteLeveling(PI) end<-----
5564 13:57:10.811291
5565 13:57:10.811659 ==
5566 13:57:10.813906 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 13:57:10.817169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 13:57:10.820737 ==
5569 13:57:10.821303 [Gating] SW mode calibration
5570 13:57:10.830447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5571 13:57:10.833665 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5572 13:57:10.837426 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 13:57:10.843721 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 13:57:10.847070 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 13:57:10.850360 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 13:57:10.856875 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 13:57:10.860204 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5578 13:57:10.863738 0 14 24 | B1->B0 | 3131 3030 | 1 0 | (1 0) (0 1)
5579 13:57:10.869868 0 14 28 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
5580 13:57:10.873379 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 13:57:10.876616 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 13:57:10.883225 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 13:57:10.886751 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 13:57:10.890031 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 13:57:10.896754 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 13:57:10.899886 0 15 24 | B1->B0 | 2929 3131 | 0 0 | (0 0) (1 1)
5587 13:57:10.903184 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5588 13:57:10.909988 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 13:57:10.913384 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 13:57:10.916311 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 13:57:10.922870 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 13:57:10.926616 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 13:57:10.929489 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5594 13:57:10.936426 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5595 13:57:10.939477 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 13:57:10.942726 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 13:57:10.949760 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 13:57:10.952900 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 13:57:10.956444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 13:57:10.962885 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 13:57:10.966050 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 13:57:10.969401 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 13:57:10.976036 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 13:57:10.979616 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 13:57:10.982934 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 13:57:10.989313 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 13:57:10.992724 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 13:57:10.996164 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 13:57:11.002840 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5610 13:57:11.005775 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5611 13:57:11.009366 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5612 13:57:11.012577 Total UI for P1: 0, mck2ui 16
5613 13:57:11.015941 best dqsien dly found for B0: ( 1, 2, 22)
5614 13:57:11.019392 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 13:57:11.022503 Total UI for P1: 0, mck2ui 16
5616 13:57:11.025931 best dqsien dly found for B1: ( 1, 2, 26)
5617 13:57:11.029303 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5618 13:57:11.035868 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5619 13:57:11.036438
5620 13:57:11.038914 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5621 13:57:11.042737 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5622 13:57:11.045737 [Gating] SW calibration Done
5623 13:57:11.046359 ==
5624 13:57:11.048937 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 13:57:11.052267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 13:57:11.052742 ==
5627 13:57:11.053118 RX Vref Scan: 0
5628 13:57:11.055616
5629 13:57:11.056173 RX Vref 0 -> 0, step: 1
5630 13:57:11.056560
5631 13:57:11.059004 RX Delay -80 -> 252, step: 8
5632 13:57:11.062113 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5633 13:57:11.065976 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5634 13:57:11.072691 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5635 13:57:11.075903 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5636 13:57:11.078929 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5637 13:57:11.082248 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5638 13:57:11.085611 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5639 13:57:11.088819 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5640 13:57:11.095960 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5641 13:57:11.099089 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5642 13:57:11.102586 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5643 13:57:11.105445 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5644 13:57:11.108667 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5645 13:57:11.115541 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5646 13:57:11.118812 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5647 13:57:11.122430 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5648 13:57:11.122900 ==
5649 13:57:11.125449 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 13:57:11.128541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 13:57:11.129016 ==
5652 13:57:11.131811 DQS Delay:
5653 13:57:11.132275 DQS0 = 0, DQS1 = 0
5654 13:57:11.132643 DQM Delay:
5655 13:57:11.135641 DQM0 = 101, DQM1 = 95
5656 13:57:11.136107 DQ Delay:
5657 13:57:11.138970 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5658 13:57:11.142315 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5659 13:57:11.145607 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5660 13:57:11.148910 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5661 13:57:11.149476
5662 13:57:11.149844
5663 13:57:11.152124 ==
5664 13:57:11.155196 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 13:57:11.158746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 13:57:11.159214 ==
5667 13:57:11.159600
5668 13:57:11.159936
5669 13:57:11.161591 TX Vref Scan disable
5670 13:57:11.162106 == TX Byte 0 ==
5671 13:57:11.165249 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5672 13:57:11.171849 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5673 13:57:11.172315 == TX Byte 1 ==
5674 13:57:11.175005 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5675 13:57:11.182187 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5676 13:57:11.182821 ==
5677 13:57:11.185221 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 13:57:11.188446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 13:57:11.189035 ==
5680 13:57:11.189406
5681 13:57:11.189748
5682 13:57:11.191803 TX Vref Scan disable
5683 13:57:11.194830 == TX Byte 0 ==
5684 13:57:11.198185 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5685 13:57:11.201817 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5686 13:57:11.205242 == TX Byte 1 ==
5687 13:57:11.208166 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5688 13:57:11.211711 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5689 13:57:11.212280
5690 13:57:11.215347 [DATLAT]
5691 13:57:11.215916 Freq=933, CH1 RK0
5692 13:57:11.216290
5693 13:57:11.218430 DATLAT Default: 0xd
5694 13:57:11.218890 0, 0xFFFF, sum = 0
5695 13:57:11.221459 1, 0xFFFF, sum = 0
5696 13:57:11.221929 2, 0xFFFF, sum = 0
5697 13:57:11.224680 3, 0xFFFF, sum = 0
5698 13:57:11.225146 4, 0xFFFF, sum = 0
5699 13:57:11.227885 5, 0xFFFF, sum = 0
5700 13:57:11.228354 6, 0xFFFF, sum = 0
5701 13:57:11.231388 7, 0xFFFF, sum = 0
5702 13:57:11.231855 8, 0xFFFF, sum = 0
5703 13:57:11.234571 9, 0xFFFF, sum = 0
5704 13:57:11.235037 10, 0x0, sum = 1
5705 13:57:11.238233 11, 0x0, sum = 2
5706 13:57:11.238813 12, 0x0, sum = 3
5707 13:57:11.241362 13, 0x0, sum = 4
5708 13:57:11.241986 best_step = 11
5709 13:57:11.242376
5710 13:57:11.242721 ==
5711 13:57:11.244664 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 13:57:11.248439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 13:57:11.251413 ==
5714 13:57:11.252003 RX Vref Scan: 1
5715 13:57:11.252384
5716 13:57:11.254475 RX Vref 0 -> 0, step: 1
5717 13:57:11.254994
5718 13:57:11.257998 RX Delay -53 -> 252, step: 4
5719 13:57:11.258571
5720 13:57:11.261100 Set Vref, RX VrefLevel [Byte0]: 53
5721 13:57:11.264232 [Byte1]: 52
5722 13:57:11.264698
5723 13:57:11.267558 Final RX Vref Byte 0 = 53 to rank0
5724 13:57:11.270936 Final RX Vref Byte 1 = 52 to rank0
5725 13:57:11.274388 Final RX Vref Byte 0 = 53 to rank1
5726 13:57:11.277823 Final RX Vref Byte 1 = 52 to rank1==
5727 13:57:11.280940 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 13:57:11.284503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 13:57:11.284980 ==
5730 13:57:11.287630 DQS Delay:
5731 13:57:11.288111 DQS0 = 0, DQS1 = 0
5732 13:57:11.288505 DQM Delay:
5733 13:57:11.291141 DQM0 = 104, DQM1 = 97
5734 13:57:11.291722 DQ Delay:
5735 13:57:11.294291 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5736 13:57:11.297491 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5737 13:57:11.301006 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92
5738 13:57:11.304517 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =102
5739 13:57:11.307362
5740 13:57:11.307873
5741 13:57:11.314499 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5742 13:57:11.317609 CH1 RK0: MR19=505, MR18=162E
5743 13:57:11.324097 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5744 13:57:11.324663
5745 13:57:11.327111 ----->DramcWriteLeveling(PI) begin...
5746 13:57:11.327590 ==
5747 13:57:11.331228 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 13:57:11.334253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 13:57:11.334726 ==
5750 13:57:11.337335 Write leveling (Byte 0): 25 => 25
5751 13:57:11.340766 Write leveling (Byte 1): 29 => 29
5752 13:57:11.344014 DramcWriteLeveling(PI) end<-----
5753 13:57:11.344575
5754 13:57:11.344943 ==
5755 13:57:11.347798 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 13:57:11.350721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 13:57:11.351290 ==
5758 13:57:11.354367 [Gating] SW mode calibration
5759 13:57:11.360455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5760 13:57:11.367396 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5761 13:57:11.370301 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 13:57:11.374235 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 13:57:11.380517 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 13:57:11.383643 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 13:57:11.387241 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 13:57:11.393765 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 13:57:11.396922 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
5768 13:57:11.400648 0 14 28 | B1->B0 | 2525 2c2c | 0 0 | (1 0) (1 0)
5769 13:57:11.407175 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 13:57:11.410934 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 13:57:11.414308 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 13:57:11.420273 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 13:57:11.423762 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 13:57:11.427034 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 13:57:11.433857 0 15 24 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
5776 13:57:11.437144 0 15 28 | B1->B0 | 4141 3636 | 0 0 | (0 0) (0 0)
5777 13:57:11.440297 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 13:57:11.447009 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 13:57:11.450315 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 13:57:11.453593 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 13:57:11.460132 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 13:57:11.463333 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 13:57:11.466952 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5784 13:57:11.473463 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5785 13:57:11.477031 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 13:57:11.480335 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 13:57:11.483551 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 13:57:11.490312 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 13:57:11.493581 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 13:57:11.497010 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 13:57:11.503390 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 13:57:11.507119 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 13:57:11.510047 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 13:57:11.516739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 13:57:11.520044 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 13:57:11.523359 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 13:57:11.530355 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:57:11.533517 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:57:11.536896 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:57:11.543601 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5801 13:57:11.546498 Total UI for P1: 0, mck2ui 16
5802 13:57:11.549714 best dqsien dly found for B1: ( 1, 2, 26)
5803 13:57:11.553131 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 13:57:11.556560 Total UI for P1: 0, mck2ui 16
5805 13:57:11.559773 best dqsien dly found for B0: ( 1, 2, 28)
5806 13:57:11.562956 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5807 13:57:11.566279 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5808 13:57:11.566751
5809 13:57:11.569718 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5810 13:57:11.572936 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5811 13:57:11.576614 [Gating] SW calibration Done
5812 13:57:11.577185 ==
5813 13:57:11.579574 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 13:57:11.586092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 13:57:11.586669 ==
5816 13:57:11.587064 RX Vref Scan: 0
5817 13:57:11.587436
5818 13:57:11.589663 RX Vref 0 -> 0, step: 1
5819 13:57:11.590158
5820 13:57:11.593479 RX Delay -80 -> 252, step: 8
5821 13:57:11.596216 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5822 13:57:11.599733 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5823 13:57:11.603029 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5824 13:57:11.606373 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5825 13:57:11.609680 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5826 13:57:11.616681 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5827 13:57:11.619416 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5828 13:57:11.622699 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5829 13:57:11.626126 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5830 13:57:11.629510 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5831 13:57:11.636460 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5832 13:57:11.639236 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5833 13:57:11.642691 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5834 13:57:11.646372 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5835 13:57:11.649387 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5836 13:57:11.653053 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5837 13:57:11.656003 ==
5838 13:57:11.659218 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 13:57:11.662256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 13:57:11.662728 ==
5841 13:57:11.663099 DQS Delay:
5842 13:57:11.665816 DQS0 = 0, DQS1 = 0
5843 13:57:11.666373 DQM Delay:
5844 13:57:11.669010 DQM0 = 101, DQM1 = 95
5845 13:57:11.669585 DQ Delay:
5846 13:57:11.672635 DQ0 =103, DQ1 =99, DQ2 =87, DQ3 =99
5847 13:57:11.675713 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5848 13:57:11.679384 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5849 13:57:11.682315 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5850 13:57:11.682924
5851 13:57:11.683306
5852 13:57:11.683648 ==
5853 13:57:11.685862 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 13:57:11.688999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 13:57:11.692711 ==
5856 13:57:11.693293
5857 13:57:11.693665
5858 13:57:11.694051 TX Vref Scan disable
5859 13:57:11.695418 == TX Byte 0 ==
5860 13:57:11.698505 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5861 13:57:11.702259 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5862 13:57:11.705548 == TX Byte 1 ==
5863 13:57:11.708877 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5864 13:57:11.712279 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5865 13:57:11.715333 ==
5866 13:57:11.718312 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 13:57:11.721694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 13:57:11.722286 ==
5869 13:57:11.722885
5870 13:57:11.723270
5871 13:57:11.724929 TX Vref Scan disable
5872 13:57:11.725432 == TX Byte 0 ==
5873 13:57:11.731942 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5874 13:57:11.735076 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5875 13:57:11.735544 == TX Byte 1 ==
5876 13:57:11.741866 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5877 13:57:11.745492 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5878 13:57:11.746100
5879 13:57:11.746477 [DATLAT]
5880 13:57:11.748641 Freq=933, CH1 RK1
5881 13:57:11.749217
5882 13:57:11.749587 DATLAT Default: 0xb
5883 13:57:11.751803 0, 0xFFFF, sum = 0
5884 13:57:11.752276 1, 0xFFFF, sum = 0
5885 13:57:11.754969 2, 0xFFFF, sum = 0
5886 13:57:11.755441 3, 0xFFFF, sum = 0
5887 13:57:11.758190 4, 0xFFFF, sum = 0
5888 13:57:11.758660 5, 0xFFFF, sum = 0
5889 13:57:11.761806 6, 0xFFFF, sum = 0
5890 13:57:11.765005 7, 0xFFFF, sum = 0
5891 13:57:11.765577 8, 0xFFFF, sum = 0
5892 13:57:11.768265 9, 0xFFFF, sum = 0
5893 13:57:11.768842 10, 0x0, sum = 1
5894 13:57:11.771678 11, 0x0, sum = 2
5895 13:57:11.772151 12, 0x0, sum = 3
5896 13:57:11.772525 13, 0x0, sum = 4
5897 13:57:11.775069 best_step = 11
5898 13:57:11.775817
5899 13:57:11.776205 ==
5900 13:57:11.778237 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 13:57:11.781752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 13:57:11.782379 ==
5903 13:57:11.785121 RX Vref Scan: 0
5904 13:57:11.785689
5905 13:57:11.788243 RX Vref 0 -> 0, step: 1
5906 13:57:11.788812
5907 13:57:11.789182 RX Delay -53 -> 252, step: 4
5908 13:57:11.795725 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5909 13:57:11.799126 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5910 13:57:11.802397 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5911 13:57:11.805920 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5912 13:57:11.808974 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5913 13:57:11.816331 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5914 13:57:11.819599 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5915 13:57:11.822276 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5916 13:57:11.825547 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5917 13:57:11.829210 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5918 13:57:11.832318 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5919 13:57:11.838758 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5920 13:57:11.842396 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5921 13:57:11.845766 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5922 13:57:11.849200 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5923 13:57:11.855515 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5924 13:57:11.856082 ==
5925 13:57:11.859307 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 13:57:11.862306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 13:57:11.862875 ==
5928 13:57:11.863253 DQS Delay:
5929 13:57:11.865370 DQS0 = 0, DQS1 = 0
5930 13:57:11.865840 DQM Delay:
5931 13:57:11.868866 DQM0 = 104, DQM1 = 97
5932 13:57:11.869357 DQ Delay:
5933 13:57:11.872484 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5934 13:57:11.875317 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5935 13:57:11.878985 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =92
5936 13:57:11.882021 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =108
5937 13:57:11.882756
5938 13:57:11.883346
5939 13:57:11.892159 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5940 13:57:11.892629 CH1 RK1: MR19=504, MR18=20FD
5941 13:57:11.898489 CH1_RK1: MR19=0x504, MR18=0x20FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5942 13:57:11.901860 [RxdqsGatingPostProcess] freq 933
5943 13:57:11.908765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5944 13:57:11.911925 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 13:57:11.915157 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 13:57:11.918462 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 13:57:11.922065 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 13:57:11.925105 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 13:57:11.925570 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 13:57:11.928736 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 13:57:11.931729 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 13:57:11.935135 Pre-setting of DQS Precalculation
5953 13:57:11.941803 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5954 13:57:11.948465 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5955 13:57:11.955218 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5956 13:57:11.955778
5957 13:57:11.956148
5958 13:57:11.958481 [Calibration Summary] 1866 Mbps
5959 13:57:11.958949 CH 0, Rank 0
5960 13:57:11.961704 SW Impedance : PASS
5961 13:57:11.965183 DUTY Scan : NO K
5962 13:57:11.965680 ZQ Calibration : PASS
5963 13:57:11.968633 Jitter Meter : NO K
5964 13:57:11.972082 CBT Training : PASS
5965 13:57:11.972647 Write leveling : PASS
5966 13:57:11.975001 RX DQS gating : PASS
5967 13:57:11.978356 RX DQ/DQS(RDDQC) : PASS
5968 13:57:11.978918 TX DQ/DQS : PASS
5969 13:57:11.981608 RX DATLAT : PASS
5970 13:57:11.985012 RX DQ/DQS(Engine): PASS
5971 13:57:11.985480 TX OE : NO K
5972 13:57:11.988126 All Pass.
5973 13:57:11.988588
5974 13:57:11.988956 CH 0, Rank 1
5975 13:57:11.991764 SW Impedance : PASS
5976 13:57:11.992230 DUTY Scan : NO K
5977 13:57:11.994995 ZQ Calibration : PASS
5978 13:57:11.998298 Jitter Meter : NO K
5979 13:57:11.998766 CBT Training : PASS
5980 13:57:12.001278 Write leveling : PASS
5981 13:57:12.005307 RX DQS gating : PASS
5982 13:57:12.005872 RX DQ/DQS(RDDQC) : PASS
5983 13:57:12.008273 TX DQ/DQS : PASS
5984 13:57:12.011787 RX DATLAT : PASS
5985 13:57:12.012353 RX DQ/DQS(Engine): PASS
5986 13:57:12.014602 TX OE : NO K
5987 13:57:12.015070 All Pass.
5988 13:57:12.015438
5989 13:57:12.018215 CH 1, Rank 0
5990 13:57:12.018776 SW Impedance : PASS
5991 13:57:12.021380 DUTY Scan : NO K
5992 13:57:12.021981 ZQ Calibration : PASS
5993 13:57:12.024509 Jitter Meter : NO K
5994 13:57:12.028023 CBT Training : PASS
5995 13:57:12.028493 Write leveling : PASS
5996 13:57:12.031291 RX DQS gating : PASS
5997 13:57:12.034494 RX DQ/DQS(RDDQC) : PASS
5998 13:57:12.034956 TX DQ/DQS : PASS
5999 13:57:12.038126 RX DATLAT : PASS
6000 13:57:12.041356 RX DQ/DQS(Engine): PASS
6001 13:57:12.041821 TX OE : NO K
6002 13:57:12.044545 All Pass.
6003 13:57:12.045007
6004 13:57:12.045371 CH 1, Rank 1
6005 13:57:12.048009 SW Impedance : PASS
6006 13:57:12.048477 DUTY Scan : NO K
6007 13:57:12.051468 ZQ Calibration : PASS
6008 13:57:12.054493 Jitter Meter : NO K
6009 13:57:12.055055 CBT Training : PASS
6010 13:57:12.058133 Write leveling : PASS
6011 13:57:12.061262 RX DQS gating : PASS
6012 13:57:12.061728 RX DQ/DQS(RDDQC) : PASS
6013 13:57:12.064496 TX DQ/DQS : PASS
6014 13:57:12.065062 RX DATLAT : PASS
6015 13:57:12.067914 RX DQ/DQS(Engine): PASS
6016 13:57:12.071288 TX OE : NO K
6017 13:57:12.071853 All Pass.
6018 13:57:12.072223
6019 13:57:12.074537 DramC Write-DBI off
6020 13:57:12.075101 PER_BANK_REFRESH: Hybrid Mode
6021 13:57:12.077685 TX_TRACKING: ON
6022 13:57:12.087867 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6023 13:57:12.091478 [FAST_K] Save calibration result to emmc
6024 13:57:12.094805 dramc_set_vcore_voltage set vcore to 650000
6025 13:57:12.095370 Read voltage for 400, 6
6026 13:57:12.097843 Vio18 = 0
6027 13:57:12.098338 Vcore = 650000
6028 13:57:12.098708 Vdram = 0
6029 13:57:12.101435 Vddq = 0
6030 13:57:12.101897 Vmddr = 0
6031 13:57:12.108036 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6032 13:57:12.111129 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6033 13:57:12.114472 MEM_TYPE=3, freq_sel=20
6034 13:57:12.117760 sv_algorithm_assistance_LP4_800
6035 13:57:12.120880 ============ PULL DRAM RESETB DOWN ============
6036 13:57:12.124629 ========== PULL DRAM RESETB DOWN end =========
6037 13:57:12.131046 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6038 13:57:12.134173 ===================================
6039 13:57:12.134642 LPDDR4 DRAM CONFIGURATION
6040 13:57:12.137406 ===================================
6041 13:57:12.140972 EX_ROW_EN[0] = 0x0
6042 13:57:12.141589 EX_ROW_EN[1] = 0x0
6043 13:57:12.144086 LP4Y_EN = 0x0
6044 13:57:12.144548 WORK_FSP = 0x0
6045 13:57:12.147549 WL = 0x2
6046 13:57:12.151025 RL = 0x2
6047 13:57:12.151489 BL = 0x2
6048 13:57:12.154012 RPST = 0x0
6049 13:57:12.154478 RD_PRE = 0x0
6050 13:57:12.158063 WR_PRE = 0x1
6051 13:57:12.158640 WR_PST = 0x0
6052 13:57:12.160942 DBI_WR = 0x0
6053 13:57:12.161405 DBI_RD = 0x0
6054 13:57:12.164183 OTF = 0x1
6055 13:57:12.167740 ===================================
6056 13:57:12.171060 ===================================
6057 13:57:12.171626 ANA top config
6058 13:57:12.174398 ===================================
6059 13:57:12.177456 DLL_ASYNC_EN = 0
6060 13:57:12.181000 ALL_SLAVE_EN = 1
6061 13:57:12.181466 NEW_RANK_MODE = 1
6062 13:57:12.184497 DLL_IDLE_MODE = 1
6063 13:57:12.188065 LP45_APHY_COMB_EN = 1
6064 13:57:12.191137 TX_ODT_DIS = 1
6065 13:57:12.194053 NEW_8X_MODE = 1
6066 13:57:12.194526 ===================================
6067 13:57:12.197516 ===================================
6068 13:57:12.200769 data_rate = 800
6069 13:57:12.204433 CKR = 1
6070 13:57:12.207354 DQ_P2S_RATIO = 4
6071 13:57:12.210979 ===================================
6072 13:57:12.214378 CA_P2S_RATIO = 4
6073 13:57:12.217692 DQ_CA_OPEN = 0
6074 13:57:12.220979 DQ_SEMI_OPEN = 1
6075 13:57:12.221546 CA_SEMI_OPEN = 1
6076 13:57:12.223795 CA_FULL_RATE = 0
6077 13:57:12.227220 DQ_CKDIV4_EN = 0
6078 13:57:12.230558 CA_CKDIV4_EN = 1
6079 13:57:12.233893 CA_PREDIV_EN = 0
6080 13:57:12.237133 PH8_DLY = 0
6081 13:57:12.237602 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6082 13:57:12.240564 DQ_AAMCK_DIV = 0
6083 13:57:12.243574 CA_AAMCK_DIV = 0
6084 13:57:12.247415 CA_ADMCK_DIV = 4
6085 13:57:12.250409 DQ_TRACK_CA_EN = 0
6086 13:57:12.253766 CA_PICK = 800
6087 13:57:12.254263 CA_MCKIO = 400
6088 13:57:12.256900 MCKIO_SEMI = 400
6089 13:57:12.260302 PLL_FREQ = 3016
6090 13:57:12.263701 DQ_UI_PI_RATIO = 32
6091 13:57:12.267548 CA_UI_PI_RATIO = 32
6092 13:57:12.270634 ===================================
6093 13:57:12.273821 ===================================
6094 13:57:12.277019 memory_type:LPDDR4
6095 13:57:12.277580 GP_NUM : 10
6096 13:57:12.280185 SRAM_EN : 1
6097 13:57:12.283422 MD32_EN : 0
6098 13:57:12.286664 ===================================
6099 13:57:12.287129 [ANA_INIT] >>>>>>>>>>>>>>
6100 13:57:12.290185 <<<<<< [CONFIGURE PHASE]: ANA_TX
6101 13:57:12.293674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6102 13:57:12.296949 ===================================
6103 13:57:12.300393 data_rate = 800,PCW = 0X7400
6104 13:57:12.303469 ===================================
6105 13:57:12.306843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6106 13:57:12.313378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 13:57:12.323559 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 13:57:12.330050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6109 13:57:12.333359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6110 13:57:12.336295 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6111 13:57:12.336869 [ANA_INIT] flow start
6112 13:57:12.339803 [ANA_INIT] PLL >>>>>>>>
6113 13:57:12.343268 [ANA_INIT] PLL <<<<<<<<
6114 13:57:12.343832 [ANA_INIT] MIDPI >>>>>>>>
6115 13:57:12.346434 [ANA_INIT] MIDPI <<<<<<<<
6116 13:57:12.349797 [ANA_INIT] DLL >>>>>>>>
6117 13:57:12.350329 [ANA_INIT] flow end
6118 13:57:12.353031 ============ LP4 DIFF to SE enter ============
6119 13:57:12.360101 ============ LP4 DIFF to SE exit ============
6120 13:57:12.360670 [ANA_INIT] <<<<<<<<<<<<<
6121 13:57:12.363177 [Flow] Enable top DCM control >>>>>
6122 13:57:12.366501 [Flow] Enable top DCM control <<<<<
6123 13:57:12.369604 Enable DLL master slave shuffle
6124 13:57:12.376375 ==============================================================
6125 13:57:12.379628 Gating Mode config
6126 13:57:12.382875 ==============================================================
6127 13:57:12.386523 Config description:
6128 13:57:12.396170 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6129 13:57:12.402756 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6130 13:57:12.406365 SELPH_MODE 0: By rank 1: By Phase
6131 13:57:12.412749 ==============================================================
6132 13:57:12.416293 GAT_TRACK_EN = 0
6133 13:57:12.419756 RX_GATING_MODE = 2
6134 13:57:12.422828 RX_GATING_TRACK_MODE = 2
6135 13:57:12.423395 SELPH_MODE = 1
6136 13:57:12.425716 PICG_EARLY_EN = 1
6137 13:57:12.429290 VALID_LAT_VALUE = 1
6138 13:57:12.436035 ==============================================================
6139 13:57:12.439381 Enter into Gating configuration >>>>
6140 13:57:12.442674 Exit from Gating configuration <<<<
6141 13:57:12.445689 Enter into DVFS_PRE_config >>>>>
6142 13:57:12.456139 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6143 13:57:12.459091 Exit from DVFS_PRE_config <<<<<
6144 13:57:12.462535 Enter into PICG configuration >>>>
6145 13:57:12.465579 Exit from PICG configuration <<<<
6146 13:57:12.468875 [RX_INPUT] configuration >>>>>
6147 13:57:12.472555 [RX_INPUT] configuration <<<<<
6148 13:57:12.476022 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6149 13:57:12.482436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6150 13:57:12.488867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 13:57:12.496040 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 13:57:12.499096 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 13:57:12.505890 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 13:57:12.508814 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6155 13:57:12.515708 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6156 13:57:12.519487 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6157 13:57:12.522533 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6158 13:57:12.525532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6159 13:57:12.532041 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 13:57:12.535904 ===================================
6161 13:57:12.539119 LPDDR4 DRAM CONFIGURATION
6162 13:57:12.539688 ===================================
6163 13:57:12.542087 EX_ROW_EN[0] = 0x0
6164 13:57:12.545527 EX_ROW_EN[1] = 0x0
6165 13:57:12.546137 LP4Y_EN = 0x0
6166 13:57:12.549197 WORK_FSP = 0x0
6167 13:57:12.549760 WL = 0x2
6168 13:57:12.552177 RL = 0x2
6169 13:57:12.552735 BL = 0x2
6170 13:57:12.555366 RPST = 0x0
6171 13:57:12.555971 RD_PRE = 0x0
6172 13:57:12.558722 WR_PRE = 0x1
6173 13:57:12.559315 WR_PST = 0x0
6174 13:57:12.561897 DBI_WR = 0x0
6175 13:57:12.562408 DBI_RD = 0x0
6176 13:57:12.565507 OTF = 0x1
6177 13:57:12.568678 ===================================
6178 13:57:12.572220 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6179 13:57:12.575587 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6180 13:57:12.581964 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 13:57:12.585586 ===================================
6182 13:57:12.586195 LPDDR4 DRAM CONFIGURATION
6183 13:57:12.588751 ===================================
6184 13:57:12.592216 EX_ROW_EN[0] = 0x10
6185 13:57:12.595628 EX_ROW_EN[1] = 0x0
6186 13:57:12.596197 LP4Y_EN = 0x0
6187 13:57:12.598569 WORK_FSP = 0x0
6188 13:57:12.599033 WL = 0x2
6189 13:57:12.602250 RL = 0x2
6190 13:57:12.602821 BL = 0x2
6191 13:57:12.605561 RPST = 0x0
6192 13:57:12.606162 RD_PRE = 0x0
6193 13:57:12.609288 WR_PRE = 0x1
6194 13:57:12.609856 WR_PST = 0x0
6195 13:57:12.612440 DBI_WR = 0x0
6196 13:57:12.613013 DBI_RD = 0x0
6197 13:57:12.615567 OTF = 0x1
6198 13:57:12.618866 ===================================
6199 13:57:12.625372 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6200 13:57:12.628367 nWR fixed to 30
6201 13:57:12.628839 [ModeRegInit_LP4] CH0 RK0
6202 13:57:12.631770 [ModeRegInit_LP4] CH0 RK1
6203 13:57:12.634980 [ModeRegInit_LP4] CH1 RK0
6204 13:57:12.638631 [ModeRegInit_LP4] CH1 RK1
6205 13:57:12.639099 match AC timing 19
6206 13:57:12.645614 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6207 13:57:12.648544 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6208 13:57:12.652424 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6209 13:57:12.655395 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6210 13:57:12.661762 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6211 13:57:12.662356 ==
6212 13:57:12.665225 Dram Type= 6, Freq= 0, CH_0, rank 0
6213 13:57:12.668615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6214 13:57:12.669083 ==
6215 13:57:12.675269 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6216 13:57:12.681920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6217 13:57:12.685120 [CA 0] Center 36 (8~64) winsize 57
6218 13:57:12.685684 [CA 1] Center 36 (8~64) winsize 57
6219 13:57:12.688235 [CA 2] Center 36 (8~64) winsize 57
6220 13:57:12.691559 [CA 3] Center 36 (8~64) winsize 57
6221 13:57:12.694882 [CA 4] Center 36 (8~64) winsize 57
6222 13:57:12.698577 [CA 5] Center 36 (8~64) winsize 57
6223 13:57:12.699139
6224 13:57:12.701658 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6225 13:57:12.702280
6226 13:57:12.705174 [CATrainingPosCal] consider 1 rank data
6227 13:57:12.708633 u2DelayCellTimex100 = 270/100 ps
6228 13:57:12.711683 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 13:57:12.718560 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 13:57:12.722016 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 13:57:12.725184 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 13:57:12.728156 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 13:57:12.731685 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 13:57:12.732150
6235 13:57:12.735166 CA PerBit enable=1, Macro0, CA PI delay=36
6236 13:57:12.735631
6237 13:57:12.737910 [CBTSetCACLKResult] CA Dly = 36
6238 13:57:12.738417 CS Dly: 1 (0~32)
6239 13:57:12.741544 ==
6240 13:57:12.744791 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 13:57:12.748327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6242 13:57:12.748893 ==
6243 13:57:12.751709 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6244 13:57:12.758192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6245 13:57:12.761149 [CA 0] Center 36 (8~64) winsize 57
6246 13:57:12.764620 [CA 1] Center 36 (8~64) winsize 57
6247 13:57:12.768041 [CA 2] Center 36 (8~64) winsize 57
6248 13:57:12.771089 [CA 3] Center 36 (8~64) winsize 57
6249 13:57:12.774613 [CA 4] Center 36 (8~64) winsize 57
6250 13:57:12.777770 [CA 5] Center 36 (8~64) winsize 57
6251 13:57:12.778279
6252 13:57:12.781532 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6253 13:57:12.782273
6254 13:57:12.784779 [CATrainingPosCal] consider 2 rank data
6255 13:57:12.787988 u2DelayCellTimex100 = 270/100 ps
6256 13:57:12.791238 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 13:57:12.794524 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 13:57:12.798189 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 13:57:12.801205 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 13:57:12.808230 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 13:57:12.811110 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 13:57:12.811611
6263 13:57:12.814719 CA PerBit enable=1, Macro0, CA PI delay=36
6264 13:57:12.815284
6265 13:57:12.817634 [CBTSetCACLKResult] CA Dly = 36
6266 13:57:12.818121 CS Dly: 1 (0~32)
6267 13:57:12.818492
6268 13:57:12.821679 ----->DramcWriteLeveling(PI) begin...
6269 13:57:12.822284 ==
6270 13:57:12.824504 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 13:57:12.831254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 13:57:12.831729 ==
6273 13:57:12.832098 Write leveling (Byte 0): 40 => 8
6274 13:57:12.834869 Write leveling (Byte 1): 32 => 0
6275 13:57:12.837831 DramcWriteLeveling(PI) end<-----
6276 13:57:12.838326
6277 13:57:12.838694 ==
6278 13:57:12.841332 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 13:57:12.848073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 13:57:12.848641 ==
6281 13:57:12.851187 [Gating] SW mode calibration
6282 13:57:12.858019 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6283 13:57:12.861487 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6284 13:57:12.867750 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 13:57:12.871093 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 13:57:12.874541 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 13:57:12.881120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 13:57:12.884649 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 13:57:12.887672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 13:57:12.891314 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 13:57:12.897516 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 13:57:12.900993 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 13:57:12.904325 Total UI for P1: 0, mck2ui 16
6294 13:57:12.907583 best dqsien dly found for B0: ( 0, 14, 24)
6295 13:57:12.910820 Total UI for P1: 0, mck2ui 16
6296 13:57:12.914084 best dqsien dly found for B1: ( 0, 14, 24)
6297 13:57:12.917195 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6298 13:57:12.920915 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6299 13:57:12.921369
6300 13:57:12.924134 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 13:57:12.927728 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 13:57:12.931100 [Gating] SW calibration Done
6303 13:57:12.931614 ==
6304 13:57:12.934556 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 13:57:12.940810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 13:57:12.941445 ==
6307 13:57:12.941814 RX Vref Scan: 0
6308 13:57:12.942191
6309 13:57:12.944548 RX Vref 0 -> 0, step: 1
6310 13:57:12.944993
6311 13:57:12.947513 RX Delay -410 -> 252, step: 16
6312 13:57:12.950790 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6313 13:57:12.954560 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6314 13:57:12.960769 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6315 13:57:12.963969 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6316 13:57:12.968009 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6317 13:57:12.970744 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6318 13:57:12.977720 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6319 13:57:12.980801 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6320 13:57:12.984049 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6321 13:57:12.987349 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6322 13:57:12.990743 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6323 13:57:12.997382 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6324 13:57:13.001139 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6325 13:57:13.004125 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6326 13:57:13.010536 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6327 13:57:13.014275 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6328 13:57:13.014837 ==
6329 13:57:13.017208 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 13:57:13.021065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 13:57:13.021636 ==
6332 13:57:13.024251 DQS Delay:
6333 13:57:13.024806 DQS0 = 27, DQS1 = 43
6334 13:57:13.025163 DQM Delay:
6335 13:57:13.027393 DQM0 = 12, DQM1 = 13
6336 13:57:13.027953 DQ Delay:
6337 13:57:13.030764 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6338 13:57:13.034180 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6339 13:57:13.037415 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6340 13:57:13.040576 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6341 13:57:13.041222
6342 13:57:13.041588
6343 13:57:13.041920 ==
6344 13:57:13.043758 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 13:57:13.047440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 13:57:13.050345 ==
6347 13:57:13.050799
6348 13:57:13.051157
6349 13:57:13.051487 TX Vref Scan disable
6350 13:57:13.053904 == TX Byte 0 ==
6351 13:57:13.057430 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 13:57:13.060610 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 13:57:13.063582 == TX Byte 1 ==
6354 13:57:13.067167 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6355 13:57:13.070788 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6356 13:57:13.071393 ==
6357 13:57:13.073598 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 13:57:13.080644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 13:57:13.081204 ==
6360 13:57:13.081568
6361 13:57:13.081900
6362 13:57:13.082337 TX Vref Scan disable
6363 13:57:13.084192 == TX Byte 0 ==
6364 13:57:13.087233 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 13:57:13.090324 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 13:57:13.093745 == TX Byte 1 ==
6367 13:57:13.097057 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6368 13:57:13.100195 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6369 13:57:13.100666
6370 13:57:13.103672 [DATLAT]
6371 13:57:13.104137 Freq=400, CH0 RK0
6372 13:57:13.104506
6373 13:57:13.106964 DATLAT Default: 0xf
6374 13:57:13.107523 0, 0xFFFF, sum = 0
6375 13:57:13.110255 1, 0xFFFF, sum = 0
6376 13:57:13.110857 2, 0xFFFF, sum = 0
6377 13:57:13.113445 3, 0xFFFF, sum = 0
6378 13:57:13.113920 4, 0xFFFF, sum = 0
6379 13:57:13.117006 5, 0xFFFF, sum = 0
6380 13:57:13.117593 6, 0xFFFF, sum = 0
6381 13:57:13.120266 7, 0xFFFF, sum = 0
6382 13:57:13.120739 8, 0xFFFF, sum = 0
6383 13:57:13.123502 9, 0xFFFF, sum = 0
6384 13:57:13.126851 10, 0xFFFF, sum = 0
6385 13:57:13.127430 11, 0xFFFF, sum = 0
6386 13:57:13.130191 12, 0xFFFF, sum = 0
6387 13:57:13.130717 13, 0x0, sum = 1
6388 13:57:13.133398 14, 0x0, sum = 2
6389 13:57:13.133869 15, 0x0, sum = 3
6390 13:57:13.134295 16, 0x0, sum = 4
6391 13:57:13.136817 best_step = 14
6392 13:57:13.137280
6393 13:57:13.137644 ==
6394 13:57:13.140354 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 13:57:13.143464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 13:57:13.144046 ==
6397 13:57:13.146471 RX Vref Scan: 1
6398 13:57:13.146935
6399 13:57:13.150001 RX Vref 0 -> 0, step: 1
6400 13:57:13.150469
6401 13:57:13.150836 RX Delay -327 -> 252, step: 8
6402 13:57:13.151181
6403 13:57:13.153250 Set Vref, RX VrefLevel [Byte0]: 60
6404 13:57:13.156460 [Byte1]: 50
6405 13:57:13.161830
6406 13:57:13.162429 Final RX Vref Byte 0 = 60 to rank0
6407 13:57:13.165124 Final RX Vref Byte 1 = 50 to rank0
6408 13:57:13.168523 Final RX Vref Byte 0 = 60 to rank1
6409 13:57:13.171671 Final RX Vref Byte 1 = 50 to rank1==
6410 13:57:13.175230 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 13:57:13.181909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 13:57:13.182528 ==
6413 13:57:13.182901 DQS Delay:
6414 13:57:13.185135 DQS0 = 28, DQS1 = 48
6415 13:57:13.185704 DQM Delay:
6416 13:57:13.186131 DQM0 = 13, DQM1 = 14
6417 13:57:13.188357 DQ Delay:
6418 13:57:13.191664 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =8
6419 13:57:13.195022 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6420 13:57:13.195607 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6421 13:57:13.198348 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6422 13:57:13.202089
6423 13:57:13.202719
6424 13:57:13.208552 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6425 13:57:13.211577 CH0 RK0: MR19=C0C, MR18=A9A2
6426 13:57:13.218050 CH0_RK0: MR19=0xC0C, MR18=0xA9A2, DQSOSC=388, MR23=63, INC=392, DEC=261
6427 13:57:13.218605 ==
6428 13:57:13.221553 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 13:57:13.225243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 13:57:13.226034 ==
6431 13:57:13.228466 [Gating] SW mode calibration
6432 13:57:13.234909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6433 13:57:13.241739 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6434 13:57:13.244720 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 13:57:13.248241 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 13:57:13.254795 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 13:57:13.258016 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 13:57:13.261511 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 13:57:13.268325 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 13:57:13.271408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 13:57:13.275294 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 13:57:13.278116 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 13:57:13.281320 Total UI for P1: 0, mck2ui 16
6444 13:57:13.284401 best dqsien dly found for B0: ( 0, 14, 24)
6445 13:57:13.288157 Total UI for P1: 0, mck2ui 16
6446 13:57:13.291747 best dqsien dly found for B1: ( 0, 14, 24)
6447 13:57:13.294708 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6448 13:57:13.301213 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6449 13:57:13.301831
6450 13:57:13.305538 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 13:57:13.307888 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 13:57:13.311629 [Gating] SW calibration Done
6453 13:57:13.312109 ==
6454 13:57:13.314745 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 13:57:13.318056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 13:57:13.318521 ==
6457 13:57:13.318886 RX Vref Scan: 0
6458 13:57:13.321499
6459 13:57:13.322161 RX Vref 0 -> 0, step: 1
6460 13:57:13.322583
6461 13:57:13.324713 RX Delay -410 -> 252, step: 16
6462 13:57:13.327569 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6463 13:57:13.334557 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6464 13:57:13.338030 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6465 13:57:13.340930 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6466 13:57:13.344324 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6467 13:57:13.350935 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6468 13:57:13.354604 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6469 13:57:13.358041 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6470 13:57:13.360957 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6471 13:57:13.367939 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6472 13:57:13.371190 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6473 13:57:13.374427 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6474 13:57:13.378138 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6475 13:57:13.384517 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6476 13:57:13.387502 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6477 13:57:13.390836 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6478 13:57:13.391358 ==
6479 13:57:13.394835 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 13:57:13.400908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 13:57:13.401478 ==
6482 13:57:13.401848 DQS Delay:
6483 13:57:13.404666 DQS0 = 27, DQS1 = 43
6484 13:57:13.405340 DQM Delay:
6485 13:57:13.405719 DQM0 = 9, DQM1 = 16
6486 13:57:13.407854 DQ Delay:
6487 13:57:13.410866 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6488 13:57:13.411434 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6489 13:57:13.414262 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6490 13:57:13.417366 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6491 13:57:13.417922
6492 13:57:13.420554
6493 13:57:13.421018 ==
6494 13:57:13.424061 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 13:57:13.427307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 13:57:13.427876 ==
6497 13:57:13.428249
6498 13:57:13.428586
6499 13:57:13.430435 TX Vref Scan disable
6500 13:57:13.430930 == TX Byte 0 ==
6501 13:57:13.433750 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6502 13:57:13.440294 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6503 13:57:13.440757 == TX Byte 1 ==
6504 13:57:13.443945 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6505 13:57:13.450432 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6506 13:57:13.450899 ==
6507 13:57:13.453669 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 13:57:13.457212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 13:57:13.457778 ==
6510 13:57:13.458239
6511 13:57:13.458594
6512 13:57:13.460550 TX Vref Scan disable
6513 13:57:13.461013 == TX Byte 0 ==
6514 13:57:13.463873 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6515 13:57:13.470519 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6516 13:57:13.471096 == TX Byte 1 ==
6517 13:57:13.473414 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6518 13:57:13.480729 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6519 13:57:13.481304
6520 13:57:13.481671 [DATLAT]
6521 13:57:13.482063 Freq=400, CH0 RK1
6522 13:57:13.483852
6523 13:57:13.484419 DATLAT Default: 0xe
6524 13:57:13.486762 0, 0xFFFF, sum = 0
6525 13:57:13.487237 1, 0xFFFF, sum = 0
6526 13:57:13.490047 2, 0xFFFF, sum = 0
6527 13:57:13.490515 3, 0xFFFF, sum = 0
6528 13:57:13.493352 4, 0xFFFF, sum = 0
6529 13:57:13.493821 5, 0xFFFF, sum = 0
6530 13:57:13.497158 6, 0xFFFF, sum = 0
6531 13:57:13.497734 7, 0xFFFF, sum = 0
6532 13:57:13.500190 8, 0xFFFF, sum = 0
6533 13:57:13.500682 9, 0xFFFF, sum = 0
6534 13:57:13.503697 10, 0xFFFF, sum = 0
6535 13:57:13.504280 11, 0xFFFF, sum = 0
6536 13:57:13.506751 12, 0xFFFF, sum = 0
6537 13:57:13.507229 13, 0x0, sum = 1
6538 13:57:13.510507 14, 0x0, sum = 2
6539 13:57:13.511085 15, 0x0, sum = 3
6540 13:57:13.513388 16, 0x0, sum = 4
6541 13:57:13.513863 best_step = 14
6542 13:57:13.514266
6543 13:57:13.514606 ==
6544 13:57:13.516554 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 13:57:13.523663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 13:57:13.524130 ==
6547 13:57:13.524498 RX Vref Scan: 0
6548 13:57:13.524840
6549 13:57:13.527194 RX Vref 0 -> 0, step: 1
6550 13:57:13.527768
6551 13:57:13.530171 RX Delay -327 -> 252, step: 8
6552 13:57:13.536640 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6553 13:57:13.539791 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6554 13:57:13.543111 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6555 13:57:13.546291 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6556 13:57:13.553529 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6557 13:57:13.556738 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6558 13:57:13.560444 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6559 13:57:13.563301 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6560 13:57:13.569918 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6561 13:57:13.573443 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6562 13:57:13.576562 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6563 13:57:13.580091 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6564 13:57:13.586822 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6565 13:57:13.589863 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6566 13:57:13.592945 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6567 13:57:13.596597 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6568 13:57:13.597174 ==
6569 13:57:13.600349 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 13:57:13.606675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 13:57:13.607256 ==
6572 13:57:13.607634 DQS Delay:
6573 13:57:13.610266 DQS0 = 24, DQS1 = 44
6574 13:57:13.610841 DQM Delay:
6575 13:57:13.613302 DQM0 = 7, DQM1 = 16
6576 13:57:13.613879 DQ Delay:
6577 13:57:13.616586 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =0
6578 13:57:13.620044 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6579 13:57:13.620619 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6580 13:57:13.623195 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6581 13:57:13.626507
6582 13:57:13.627069
6583 13:57:13.633112 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6584 13:57:13.636727 CH0 RK1: MR19=C0C, MR18=BC6F
6585 13:57:13.642802 CH0_RK1: MR19=0xC0C, MR18=0xBC6F, DQSOSC=386, MR23=63, INC=396, DEC=264
6586 13:57:13.646152 [RxdqsGatingPostProcess] freq 400
6587 13:57:13.649836 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6588 13:57:13.653045 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 13:57:13.656576 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 13:57:13.659773 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 13:57:13.663120 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 13:57:13.666139 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 13:57:13.669866 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 13:57:13.672940 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 13:57:13.676257 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 13:57:13.679956 Pre-setting of DQS Precalculation
6597 13:57:13.683306 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6598 13:57:13.683873 ==
6599 13:57:13.685997 Dram Type= 6, Freq= 0, CH_1, rank 0
6600 13:57:13.693240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 13:57:13.693808 ==
6602 13:57:13.696099 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6603 13:57:13.702760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6604 13:57:13.706398 [CA 0] Center 36 (8~64) winsize 57
6605 13:57:13.709900 [CA 1] Center 36 (8~64) winsize 57
6606 13:57:13.712872 [CA 2] Center 36 (8~64) winsize 57
6607 13:57:13.716424 [CA 3] Center 36 (8~64) winsize 57
6608 13:57:13.719515 [CA 4] Center 36 (8~64) winsize 57
6609 13:57:13.722611 [CA 5] Center 36 (8~64) winsize 57
6610 13:57:13.723082
6611 13:57:13.726051 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6612 13:57:13.726610
6613 13:57:13.729550 [CATrainingPosCal] consider 1 rank data
6614 13:57:13.732635 u2DelayCellTimex100 = 270/100 ps
6615 13:57:13.735873 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 13:57:13.739196 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 13:57:13.742534 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 13:57:13.745844 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 13:57:13.749283 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 13:57:13.752716 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 13:57:13.753244
6622 13:57:13.759228 CA PerBit enable=1, Macro0, CA PI delay=36
6623 13:57:13.759776
6624 13:57:13.762593 [CBTSetCACLKResult] CA Dly = 36
6625 13:57:13.763056 CS Dly: 1 (0~32)
6626 13:57:13.763423 ==
6627 13:57:13.765689 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 13:57:13.768897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 13:57:13.769359 ==
6630 13:57:13.776009 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6631 13:57:13.782585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6632 13:57:13.786010 [CA 0] Center 36 (8~64) winsize 57
6633 13:57:13.789502 [CA 1] Center 36 (8~64) winsize 57
6634 13:57:13.792619 [CA 2] Center 36 (8~64) winsize 57
6635 13:57:13.796048 [CA 3] Center 36 (8~64) winsize 57
6636 13:57:13.796624 [CA 4] Center 36 (8~64) winsize 57
6637 13:57:13.799309 [CA 5] Center 36 (8~64) winsize 57
6638 13:57:13.799881
6639 13:57:13.805834 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6640 13:57:13.806436
6641 13:57:13.809445 [CATrainingPosCal] consider 2 rank data
6642 13:57:13.812375 u2DelayCellTimex100 = 270/100 ps
6643 13:57:13.816380 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 13:57:13.818809 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 13:57:13.822437 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 13:57:13.825901 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 13:57:13.829467 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 13:57:13.832652 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 13:57:13.833225
6650 13:57:13.835320 CA PerBit enable=1, Macro0, CA PI delay=36
6651 13:57:13.835789
6652 13:57:13.838685 [CBTSetCACLKResult] CA Dly = 36
6653 13:57:13.842185 CS Dly: 1 (0~32)
6654 13:57:13.842666
6655 13:57:13.845618 ----->DramcWriteLeveling(PI) begin...
6656 13:57:13.846247 ==
6657 13:57:13.849042 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 13:57:13.852228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 13:57:13.852818 ==
6660 13:57:13.855161 Write leveling (Byte 0): 40 => 8
6661 13:57:13.858637 Write leveling (Byte 1): 32 => 0
6662 13:57:13.861989 DramcWriteLeveling(PI) end<-----
6663 13:57:13.862456
6664 13:57:13.862822 ==
6665 13:57:13.865405 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 13:57:13.868594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 13:57:13.869064 ==
6668 13:57:13.871887 [Gating] SW mode calibration
6669 13:57:13.878650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6670 13:57:13.885173 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6671 13:57:13.888572 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 13:57:13.891968 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 13:57:13.898803 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 13:57:13.902142 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 13:57:13.905307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 13:57:13.911775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 13:57:13.915128 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 13:57:13.918500 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 13:57:13.925335 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 13:57:13.928259 Total UI for P1: 0, mck2ui 16
6681 13:57:13.931960 best dqsien dly found for B0: ( 0, 14, 24)
6682 13:57:13.932533 Total UI for P1: 0, mck2ui 16
6683 13:57:13.938178 best dqsien dly found for B1: ( 0, 14, 24)
6684 13:57:13.941278 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6685 13:57:13.944944 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6686 13:57:13.945409
6687 13:57:13.948010 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 13:57:13.951858 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 13:57:13.954792 [Gating] SW calibration Done
6690 13:57:13.955467 ==
6691 13:57:13.958302 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 13:57:13.961348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 13:57:13.961982 ==
6694 13:57:13.964717 RX Vref Scan: 0
6695 13:57:13.965198
6696 13:57:13.965578 RX Vref 0 -> 0, step: 1
6697 13:57:13.968334
6698 13:57:13.968797 RX Delay -410 -> 252, step: 16
6699 13:57:13.975044 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6700 13:57:13.978136 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6701 13:57:13.981419 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6702 13:57:13.984995 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6703 13:57:13.991528 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6704 13:57:13.994571 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6705 13:57:13.998176 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6706 13:57:14.001604 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6707 13:57:14.008127 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6708 13:57:14.011265 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6709 13:57:14.014778 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6710 13:57:14.018289 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6711 13:57:14.025207 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6712 13:57:14.028085 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6713 13:57:14.031803 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6714 13:57:14.038176 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6715 13:57:14.038749 ==
6716 13:57:14.041301 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 13:57:14.044463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 13:57:14.045074 ==
6719 13:57:14.045451 DQS Delay:
6720 13:57:14.047640 DQS0 = 27, DQS1 = 43
6721 13:57:14.048207 DQM Delay:
6722 13:57:14.051208 DQM0 = 6, DQM1 = 17
6723 13:57:14.051781 DQ Delay:
6724 13:57:14.054349 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6725 13:57:14.058059 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =0
6726 13:57:14.061124 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6727 13:57:14.064913 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6728 13:57:14.065493
6729 13:57:14.065866
6730 13:57:14.066240 ==
6731 13:57:14.067414 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 13:57:14.071042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 13:57:14.071617 ==
6734 13:57:14.071990
6735 13:57:14.072332
6736 13:57:14.074053 TX Vref Scan disable
6737 13:57:14.074520 == TX Byte 0 ==
6738 13:57:14.081326 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 13:57:14.084273 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 13:57:14.084740 == TX Byte 1 ==
6741 13:57:14.090606 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6742 13:57:14.093843 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6743 13:57:14.094364 ==
6744 13:57:14.097433 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 13:57:14.100759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 13:57:14.101333 ==
6747 13:57:14.101704
6748 13:57:14.102124
6749 13:57:14.104093 TX Vref Scan disable
6750 13:57:14.107716 == TX Byte 0 ==
6751 13:57:14.110850 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 13:57:14.114255 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 13:57:14.114725 == TX Byte 1 ==
6754 13:57:14.120671 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6755 13:57:14.124174 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6756 13:57:14.124746
6757 13:57:14.125113 [DATLAT]
6758 13:57:14.127263 Freq=400, CH1 RK0
6759 13:57:14.127837
6760 13:57:14.128208 DATLAT Default: 0xf
6761 13:57:14.130934 0, 0xFFFF, sum = 0
6762 13:57:14.131516 1, 0xFFFF, sum = 0
6763 13:57:14.134300 2, 0xFFFF, sum = 0
6764 13:57:14.134917 3, 0xFFFF, sum = 0
6765 13:57:14.137438 4, 0xFFFF, sum = 0
6766 13:57:14.141182 5, 0xFFFF, sum = 0
6767 13:57:14.141773 6, 0xFFFF, sum = 0
6768 13:57:14.143991 7, 0xFFFF, sum = 0
6769 13:57:14.144461 8, 0xFFFF, sum = 0
6770 13:57:14.147802 9, 0xFFFF, sum = 0
6771 13:57:14.148384 10, 0xFFFF, sum = 0
6772 13:57:14.150741 11, 0xFFFF, sum = 0
6773 13:57:14.151215 12, 0xFFFF, sum = 0
6774 13:57:14.154206 13, 0x0, sum = 1
6775 13:57:14.154791 14, 0x0, sum = 2
6776 13:57:14.157344 15, 0x0, sum = 3
6777 13:57:14.157921 16, 0x0, sum = 4
6778 13:57:14.160507 best_step = 14
6779 13:57:14.161082
6780 13:57:14.161452 ==
6781 13:57:14.164214 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 13:57:14.167093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 13:57:14.167564 ==
6784 13:57:14.167934 RX Vref Scan: 1
6785 13:57:14.168278
6786 13:57:14.170365 RX Vref 0 -> 0, step: 1
6787 13:57:14.170829
6788 13:57:14.173704 RX Delay -327 -> 252, step: 8
6789 13:57:14.174201
6790 13:57:14.177252 Set Vref, RX VrefLevel [Byte0]: 53
6791 13:57:14.180700 [Byte1]: 52
6792 13:57:14.184793
6793 13:57:14.185289 Final RX Vref Byte 0 = 53 to rank0
6794 13:57:14.187834 Final RX Vref Byte 1 = 52 to rank0
6795 13:57:14.190937 Final RX Vref Byte 0 = 53 to rank1
6796 13:57:14.194639 Final RX Vref Byte 1 = 52 to rank1==
6797 13:57:14.197993 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 13:57:14.204220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 13:57:14.204692 ==
6800 13:57:14.205064 DQS Delay:
6801 13:57:14.207931 DQS0 = 28, DQS1 = 40
6802 13:57:14.208693 DQM Delay:
6803 13:57:14.209094 DQM0 = 8, DQM1 = 13
6804 13:57:14.210835 DQ Delay:
6805 13:57:14.213998 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6806 13:57:14.214467 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6807 13:57:14.217773 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6808 13:57:14.221028 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6809 13:57:14.221598
6810 13:57:14.222000
6811 13:57:14.231074 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6812 13:57:14.234252 CH1 RK0: MR19=C0C, MR18=8DC8
6813 13:57:14.241223 CH1_RK0: MR19=0xC0C, MR18=0x8DC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6814 13:57:14.241867 ==
6815 13:57:14.243912 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 13:57:14.247339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 13:57:14.247917 ==
6818 13:57:14.251173 [Gating] SW mode calibration
6819 13:57:14.257555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6820 13:57:14.260848 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6821 13:57:14.267708 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 13:57:14.270811 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 13:57:14.274604 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 13:57:14.280698 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 13:57:14.283741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 13:57:14.287221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 13:57:14.294199 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 13:57:14.297315 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 13:57:14.300734 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 13:57:14.303656 Total UI for P1: 0, mck2ui 16
6831 13:57:14.307233 best dqsien dly found for B0: ( 0, 14, 24)
6832 13:57:14.310694 Total UI for P1: 0, mck2ui 16
6833 13:57:14.314094 best dqsien dly found for B1: ( 0, 14, 24)
6834 13:57:14.317279 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6835 13:57:14.320694 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6836 13:57:14.321277
6837 13:57:14.327401 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 13:57:14.330316 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 13:57:14.333708 [Gating] SW calibration Done
6840 13:57:14.334332 ==
6841 13:57:14.336936 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 13:57:14.340427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 13:57:14.341001 ==
6844 13:57:14.341375 RX Vref Scan: 0
6845 13:57:14.343558
6846 13:57:14.344021 RX Vref 0 -> 0, step: 1
6847 13:57:14.344388
6848 13:57:14.346872 RX Delay -410 -> 252, step: 16
6849 13:57:14.350055 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6850 13:57:14.357082 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6851 13:57:14.359851 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6852 13:57:14.363417 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6853 13:57:14.366552 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6854 13:57:14.373433 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6855 13:57:14.376671 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6856 13:57:14.379949 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6857 13:57:14.383141 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6858 13:57:14.389905 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6859 13:57:14.393280 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6860 13:57:14.396129 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6861 13:57:14.399547 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6862 13:57:14.406187 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6863 13:57:14.409461 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6864 13:57:14.412692 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6865 13:57:14.413251 ==
6866 13:57:14.416133 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 13:57:14.422552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 13:57:14.422854 ==
6869 13:57:14.423132 DQS Delay:
6870 13:57:14.425747 DQS0 = 35, DQS1 = 35
6871 13:57:14.426051 DQM Delay:
6872 13:57:14.426317 DQM0 = 18, DQM1 = 12
6873 13:57:14.429177 DQ Delay:
6874 13:57:14.432721 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6875 13:57:14.435812 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6876 13:57:14.439343 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6877 13:57:14.442393 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6878 13:57:14.442551
6879 13:57:14.442676
6880 13:57:14.442792 ==
6881 13:57:14.445961 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 13:57:14.449148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 13:57:14.449396 ==
6884 13:57:14.449536
6885 13:57:14.449666
6886 13:57:14.452377 TX Vref Scan disable
6887 13:57:14.452621 == TX Byte 0 ==
6888 13:57:14.459291 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6889 13:57:14.462441 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6890 13:57:14.462644 == TX Byte 1 ==
6891 13:57:14.465520 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6892 13:57:14.472291 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6893 13:57:14.472568 ==
6894 13:57:14.475367 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 13:57:14.478597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 13:57:14.478908 ==
6897 13:57:14.479092
6898 13:57:14.479267
6899 13:57:14.482313 TX Vref Scan disable
6900 13:57:14.482665 == TX Byte 0 ==
6901 13:57:14.488914 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6902 13:57:14.492388 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6903 13:57:14.492923 == TX Byte 1 ==
6904 13:57:14.499110 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6905 13:57:14.502209 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6906 13:57:14.502677
6907 13:57:14.503067 [DATLAT]
6908 13:57:14.505305 Freq=400, CH1 RK1
6909 13:57:14.505768
6910 13:57:14.506184 DATLAT Default: 0xe
6911 13:57:14.509040 0, 0xFFFF, sum = 0
6912 13:57:14.509624 1, 0xFFFF, sum = 0
6913 13:57:14.512001 2, 0xFFFF, sum = 0
6914 13:57:14.512473 3, 0xFFFF, sum = 0
6915 13:57:14.515471 4, 0xFFFF, sum = 0
6916 13:57:14.515943 5, 0xFFFF, sum = 0
6917 13:57:14.518521 6, 0xFFFF, sum = 0
6918 13:57:14.518990 7, 0xFFFF, sum = 0
6919 13:57:14.522087 8, 0xFFFF, sum = 0
6920 13:57:14.522657 9, 0xFFFF, sum = 0
6921 13:57:14.525291 10, 0xFFFF, sum = 0
6922 13:57:14.528952 11, 0xFFFF, sum = 0
6923 13:57:14.529528 12, 0xFFFF, sum = 0
6924 13:57:14.531930 13, 0x0, sum = 1
6925 13:57:14.532403 14, 0x0, sum = 2
6926 13:57:14.532780 15, 0x0, sum = 3
6927 13:57:14.534941 16, 0x0, sum = 4
6928 13:57:14.535413 best_step = 14
6929 13:57:14.535804
6930 13:57:14.538464 ==
6931 13:57:14.538931 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 13:57:14.544997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 13:57:14.545470 ==
6934 13:57:14.545842 RX Vref Scan: 0
6935 13:57:14.546236
6936 13:57:14.548545 RX Vref 0 -> 0, step: 1
6937 13:57:14.549011
6938 13:57:14.551829 RX Delay -311 -> 252, step: 8
6939 13:57:14.558662 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6940 13:57:14.561843 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6941 13:57:14.565606 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6942 13:57:14.568275 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6943 13:57:14.574953 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6944 13:57:14.578367 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6945 13:57:14.582039 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6946 13:57:14.585204 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6947 13:57:14.591829 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6948 13:57:14.595337 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6949 13:57:14.598734 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6950 13:57:14.605123 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6951 13:57:14.608117 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6952 13:57:14.611475 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6953 13:57:14.614878 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6954 13:57:14.621343 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6955 13:57:14.621906 ==
6956 13:57:14.624891 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 13:57:14.628108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 13:57:14.628697 ==
6959 13:57:14.629076 DQS Delay:
6960 13:57:14.631147 DQS0 = 28, DQS1 = 36
6961 13:57:14.631617 DQM Delay:
6962 13:57:14.634679 DQM0 = 9, DQM1 = 11
6963 13:57:14.635166 DQ Delay:
6964 13:57:14.637845 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6965 13:57:14.640921 DQ4 =12, DQ5 =16, DQ6 =12, DQ7 =8
6966 13:57:14.644678 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6967 13:57:14.647763 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6968 13:57:14.648229
6969 13:57:14.648594
6970 13:57:14.654799 [DQSOSCAuto] RK1, (LSB)MR18= 0xae56, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6971 13:57:14.658136 CH1 RK1: MR19=C0C, MR18=AE56
6972 13:57:14.664652 CH1_RK1: MR19=0xC0C, MR18=0xAE56, DQSOSC=388, MR23=63, INC=392, DEC=261
6973 13:57:14.667549 [RxdqsGatingPostProcess] freq 400
6974 13:57:14.674174 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6975 13:57:14.677661 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 13:57:14.680502 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 13:57:14.684343 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 13:57:14.684910 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 13:57:14.687539 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 13:57:14.690938 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 13:57:14.694115 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 13:57:14.697387 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 13:57:14.700621 Pre-setting of DQS Precalculation
6984 13:57:14.707538 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6985 13:57:14.713871 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6986 13:57:14.720645 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6987 13:57:14.721212
6988 13:57:14.721580
6989 13:57:14.723912 [Calibration Summary] 800 Mbps
6990 13:57:14.724493 CH 0, Rank 0
6991 13:57:14.727252 SW Impedance : PASS
6992 13:57:14.730813 DUTY Scan : NO K
6993 13:57:14.731375 ZQ Calibration : PASS
6994 13:57:14.733793 Jitter Meter : NO K
6995 13:57:14.736772 CBT Training : PASS
6996 13:57:14.737241 Write leveling : PASS
6997 13:57:14.740122 RX DQS gating : PASS
6998 13:57:14.743532 RX DQ/DQS(RDDQC) : PASS
6999 13:57:14.744039 TX DQ/DQS : PASS
7000 13:57:14.747280 RX DATLAT : PASS
7001 13:57:14.750319 RX DQ/DQS(Engine): PASS
7002 13:57:14.750788 TX OE : NO K
7003 13:57:14.751156 All Pass.
7004 13:57:14.751499
7005 13:57:14.753720 CH 0, Rank 1
7006 13:57:14.754270 SW Impedance : PASS
7007 13:57:14.757177 DUTY Scan : NO K
7008 13:57:14.760467 ZQ Calibration : PASS
7009 13:57:14.761032 Jitter Meter : NO K
7010 13:57:14.764009 CBT Training : PASS
7011 13:57:14.767111 Write leveling : NO K
7012 13:57:14.767680 RX DQS gating : PASS
7013 13:57:14.770537 RX DQ/DQS(RDDQC) : PASS
7014 13:57:14.773922 TX DQ/DQS : PASS
7015 13:57:14.774513 RX DATLAT : PASS
7016 13:57:14.777257 RX DQ/DQS(Engine): PASS
7017 13:57:14.780527 TX OE : NO K
7018 13:57:14.781235 All Pass.
7019 13:57:14.781635
7020 13:57:14.782025 CH 1, Rank 0
7021 13:57:14.783539 SW Impedance : PASS
7022 13:57:14.787352 DUTY Scan : NO K
7023 13:57:14.787917 ZQ Calibration : PASS
7024 13:57:14.790841 Jitter Meter : NO K
7025 13:57:14.794067 CBT Training : PASS
7026 13:57:14.794627 Write leveling : PASS
7027 13:57:14.797218 RX DQS gating : PASS
7028 13:57:14.797781 RX DQ/DQS(RDDQC) : PASS
7029 13:57:14.800219 TX DQ/DQS : PASS
7030 13:57:14.803556 RX DATLAT : PASS
7031 13:57:14.804020 RX DQ/DQS(Engine): PASS
7032 13:57:14.807333 TX OE : NO K
7033 13:57:14.807895 All Pass.
7034 13:57:14.808265
7035 13:57:14.810835 CH 1, Rank 1
7036 13:57:14.811400 SW Impedance : PASS
7037 13:57:14.814031 DUTY Scan : NO K
7038 13:57:14.817192 ZQ Calibration : PASS
7039 13:57:14.817749 Jitter Meter : NO K
7040 13:57:14.820114 CBT Training : PASS
7041 13:57:14.823807 Write leveling : NO K
7042 13:57:14.824269 RX DQS gating : PASS
7043 13:57:14.827062 RX DQ/DQS(RDDQC) : PASS
7044 13:57:14.830581 TX DQ/DQS : PASS
7045 13:57:14.831219 RX DATLAT : PASS
7046 13:57:14.833745 RX DQ/DQS(Engine): PASS
7047 13:57:14.836795 TX OE : NO K
7048 13:57:14.837257 All Pass.
7049 13:57:14.837673
7050 13:57:14.838063 DramC Write-DBI off
7051 13:57:14.840130 PER_BANK_REFRESH: Hybrid Mode
7052 13:57:14.843676 TX_TRACKING: ON
7053 13:57:14.850069 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7054 13:57:14.853363 [FAST_K] Save calibration result to emmc
7055 13:57:14.860505 dramc_set_vcore_voltage set vcore to 725000
7056 13:57:14.861102 Read voltage for 1600, 0
7057 13:57:14.863779 Vio18 = 0
7058 13:57:14.864355 Vcore = 725000
7059 13:57:14.864730 Vdram = 0
7060 13:57:14.865076 Vddq = 0
7061 13:57:14.867143 Vmddr = 0
7062 13:57:14.870612 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7063 13:57:14.877061 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7064 13:57:14.880655 MEM_TYPE=3, freq_sel=13
7065 13:57:14.881235 sv_algorithm_assistance_LP4_3733
7066 13:57:14.886962 ============ PULL DRAM RESETB DOWN ============
7067 13:57:14.890350 ========== PULL DRAM RESETB DOWN end =========
7068 13:57:14.893983 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7069 13:57:14.897114 ===================================
7070 13:57:14.900838 LPDDR4 DRAM CONFIGURATION
7071 13:57:14.903520 ===================================
7072 13:57:14.906876 EX_ROW_EN[0] = 0x0
7073 13:57:14.907450 EX_ROW_EN[1] = 0x0
7074 13:57:14.910095 LP4Y_EN = 0x0
7075 13:57:14.910673 WORK_FSP = 0x1
7076 13:57:14.913609 WL = 0x5
7077 13:57:14.914105 RL = 0x5
7078 13:57:14.916849 BL = 0x2
7079 13:57:14.917422 RPST = 0x0
7080 13:57:14.920087 RD_PRE = 0x0
7081 13:57:14.920663 WR_PRE = 0x1
7082 13:57:14.923771 WR_PST = 0x1
7083 13:57:14.924351 DBI_WR = 0x0
7084 13:57:14.927079 DBI_RD = 0x0
7085 13:57:14.927652 OTF = 0x1
7086 13:57:14.930451 ===================================
7087 13:57:14.933125 ===================================
7088 13:57:14.936697 ANA top config
7089 13:57:14.939851 ===================================
7090 13:57:14.943167 DLL_ASYNC_EN = 0
7091 13:57:14.943658 ALL_SLAVE_EN = 0
7092 13:57:14.946574 NEW_RANK_MODE = 1
7093 13:57:14.950096 DLL_IDLE_MODE = 1
7094 13:57:14.953301 LP45_APHY_COMB_EN = 1
7095 13:57:14.953795 TX_ODT_DIS = 0
7096 13:57:14.956528 NEW_8X_MODE = 1
7097 13:57:14.959952 ===================================
7098 13:57:14.963075 ===================================
7099 13:57:14.966748 data_rate = 3200
7100 13:57:14.969765 CKR = 1
7101 13:57:14.973059 DQ_P2S_RATIO = 8
7102 13:57:14.976237 ===================================
7103 13:57:14.979611 CA_P2S_RATIO = 8
7104 13:57:14.980082 DQ_CA_OPEN = 0
7105 13:57:14.983194 DQ_SEMI_OPEN = 0
7106 13:57:14.986571 CA_SEMI_OPEN = 0
7107 13:57:14.989503 CA_FULL_RATE = 0
7108 13:57:14.993014 DQ_CKDIV4_EN = 0
7109 13:57:14.996336 CA_CKDIV4_EN = 0
7110 13:57:14.997068 CA_PREDIV_EN = 0
7111 13:57:14.999749 PH8_DLY = 12
7112 13:57:15.002986 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7113 13:57:15.006405 DQ_AAMCK_DIV = 4
7114 13:57:15.009736 CA_AAMCK_DIV = 4
7115 13:57:15.012801 CA_ADMCK_DIV = 4
7116 13:57:15.013227 DQ_TRACK_CA_EN = 0
7117 13:57:15.016326 CA_PICK = 1600
7118 13:57:15.019673 CA_MCKIO = 1600
7119 13:57:15.022770 MCKIO_SEMI = 0
7120 13:57:15.026465 PLL_FREQ = 3068
7121 13:57:15.029479 DQ_UI_PI_RATIO = 32
7122 13:57:15.032974 CA_UI_PI_RATIO = 0
7123 13:57:15.036328 ===================================
7124 13:57:15.039775 ===================================
7125 13:57:15.040208 memory_type:LPDDR4
7126 13:57:15.043042 GP_NUM : 10
7127 13:57:15.046240 SRAM_EN : 1
7128 13:57:15.046665 MD32_EN : 0
7129 13:57:15.049837 ===================================
7130 13:57:15.053007 [ANA_INIT] >>>>>>>>>>>>>>
7131 13:57:15.056251 <<<<<< [CONFIGURE PHASE]: ANA_TX
7132 13:57:15.059469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7133 13:57:15.062885 ===================================
7134 13:57:15.066296 data_rate = 3200,PCW = 0X7600
7135 13:57:15.069195 ===================================
7136 13:57:15.072540 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7137 13:57:15.075888 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 13:57:15.082798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 13:57:15.086145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7140 13:57:15.089873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7141 13:57:15.093015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7142 13:57:15.096632 [ANA_INIT] flow start
7143 13:57:15.099312 [ANA_INIT] PLL >>>>>>>>
7144 13:57:15.099774 [ANA_INIT] PLL <<<<<<<<
7145 13:57:15.102441 [ANA_INIT] MIDPI >>>>>>>>
7146 13:57:15.106056 [ANA_INIT] MIDPI <<<<<<<<
7147 13:57:15.109840 [ANA_INIT] DLL >>>>>>>>
7148 13:57:15.110451 [ANA_INIT] DLL <<<<<<<<
7149 13:57:15.112456 [ANA_INIT] flow end
7150 13:57:15.115503 ============ LP4 DIFF to SE enter ============
7151 13:57:15.119183 ============ LP4 DIFF to SE exit ============
7152 13:57:15.122591 [ANA_INIT] <<<<<<<<<<<<<
7153 13:57:15.125744 [Flow] Enable top DCM control >>>>>
7154 13:57:15.129498 [Flow] Enable top DCM control <<<<<
7155 13:57:15.132358 Enable DLL master slave shuffle
7156 13:57:15.136228 ==============================================================
7157 13:57:15.139193 Gating Mode config
7158 13:57:15.145927 ==============================================================
7159 13:57:15.146545 Config description:
7160 13:57:15.156088 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7161 13:57:15.162528 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7162 13:57:15.169241 SELPH_MODE 0: By rank 1: By Phase
7163 13:57:15.172501 ==============================================================
7164 13:57:15.175591 GAT_TRACK_EN = 1
7165 13:57:15.179337 RX_GATING_MODE = 2
7166 13:57:15.182352 RX_GATING_TRACK_MODE = 2
7167 13:57:15.185558 SELPH_MODE = 1
7168 13:57:15.189244 PICG_EARLY_EN = 1
7169 13:57:15.192314 VALID_LAT_VALUE = 1
7170 13:57:15.195754 ==============================================================
7171 13:57:15.198877 Enter into Gating configuration >>>>
7172 13:57:15.202418 Exit from Gating configuration <<<<
7173 13:57:15.205982 Enter into DVFS_PRE_config >>>>>
7174 13:57:15.219104 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7175 13:57:15.222466 Exit from DVFS_PRE_config <<<<<
7176 13:57:15.225728 Enter into PICG configuration >>>>
7177 13:57:15.226227 Exit from PICG configuration <<<<
7178 13:57:15.229100 [RX_INPUT] configuration >>>>>
7179 13:57:15.232255 [RX_INPUT] configuration <<<<<
7180 13:57:15.238532 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7181 13:57:15.241861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7182 13:57:15.248809 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 13:57:15.255532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 13:57:15.262361 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 13:57:15.268847 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 13:57:15.272186 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7187 13:57:15.275244 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7188 13:57:15.278568 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7189 13:57:15.285474 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7190 13:57:15.288442 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7191 13:57:15.291702 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 13:57:15.295324 ===================================
7193 13:57:15.298403 LPDDR4 DRAM CONFIGURATION
7194 13:57:15.301719 ===================================
7195 13:57:15.304974 EX_ROW_EN[0] = 0x0
7196 13:57:15.305540 EX_ROW_EN[1] = 0x0
7197 13:57:15.308733 LP4Y_EN = 0x0
7198 13:57:15.309310 WORK_FSP = 0x1
7199 13:57:15.312039 WL = 0x5
7200 13:57:15.312609 RL = 0x5
7201 13:57:15.315253 BL = 0x2
7202 13:57:15.315741 RPST = 0x0
7203 13:57:15.318751 RD_PRE = 0x0
7204 13:57:15.319323 WR_PRE = 0x1
7205 13:57:15.321988 WR_PST = 0x1
7206 13:57:15.322565 DBI_WR = 0x0
7207 13:57:15.325267 DBI_RD = 0x0
7208 13:57:15.325835 OTF = 0x1
7209 13:57:15.328496 ===================================
7210 13:57:15.335236 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7211 13:57:15.338190 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7212 13:57:15.341698 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 13:57:15.344728 ===================================
7214 13:57:15.347935 LPDDR4 DRAM CONFIGURATION
7215 13:57:15.351501 ===================================
7216 13:57:15.355039 EX_ROW_EN[0] = 0x10
7217 13:57:15.355616 EX_ROW_EN[1] = 0x0
7218 13:57:15.358003 LP4Y_EN = 0x0
7219 13:57:15.358471 WORK_FSP = 0x1
7220 13:57:15.361556 WL = 0x5
7221 13:57:15.362169 RL = 0x5
7222 13:57:15.364754 BL = 0x2
7223 13:57:15.365330 RPST = 0x0
7224 13:57:15.368062 RD_PRE = 0x0
7225 13:57:15.368555 WR_PRE = 0x1
7226 13:57:15.371275 WR_PST = 0x1
7227 13:57:15.371740 DBI_WR = 0x0
7228 13:57:15.375191 DBI_RD = 0x0
7229 13:57:15.375767 OTF = 0x1
7230 13:57:15.378301 ===================================
7231 13:57:15.384546 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7232 13:57:15.385256 ==
7233 13:57:15.387918 Dram Type= 6, Freq= 0, CH_0, rank 0
7234 13:57:15.394602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7235 13:57:15.395149 ==
7236 13:57:15.395699 [Duty_Offset_Calibration]
7237 13:57:15.397879 B0:2 B1:0 CA:1
7238 13:57:15.398381
7239 13:57:15.401040 [DutyScan_Calibration_Flow] k_type=0
7240 13:57:15.409905
7241 13:57:15.410518 ==CLK 0==
7242 13:57:15.413136 Final CLK duty delay cell = -4
7243 13:57:15.416026 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7244 13:57:15.419849 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7245 13:57:15.422784 [-4] AVG Duty = 4922%(X100)
7246 13:57:15.423361
7247 13:57:15.426399 CH0 CLK Duty spec in!! Max-Min= 218%
7248 13:57:15.429723 [DutyScan_Calibration_Flow] ====Done====
7249 13:57:15.430377
7250 13:57:15.433495 [DutyScan_Calibration_Flow] k_type=1
7251 13:57:15.449415
7252 13:57:15.450022 ==DQS 0 ==
7253 13:57:15.452719 Final DQS duty delay cell = 0
7254 13:57:15.456180 [0] MAX Duty = 5249%(X100), DQS PI = 32
7255 13:57:15.459165 [0] MIN Duty = 4969%(X100), DQS PI = 0
7256 13:57:15.459744 [0] AVG Duty = 5109%(X100)
7257 13:57:15.462598
7258 13:57:15.463064 ==DQS 1 ==
7259 13:57:15.466222 Final DQS duty delay cell = -4
7260 13:57:15.469145 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7261 13:57:15.472617 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7262 13:57:15.475925 [-4] AVG Duty = 4969%(X100)
7263 13:57:15.476396
7264 13:57:15.479444 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7265 13:57:15.480024
7266 13:57:15.482313 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7267 13:57:15.485457 [DutyScan_Calibration_Flow] ====Done====
7268 13:57:15.485926
7269 13:57:15.489159 [DutyScan_Calibration_Flow] k_type=3
7270 13:57:15.506565
7271 13:57:15.507138 ==DQM 0 ==
7272 13:57:15.509568 Final DQM duty delay cell = 0
7273 13:57:15.513478 [0] MAX Duty = 5093%(X100), DQS PI = 26
7274 13:57:15.516466 [0] MIN Duty = 4813%(X100), DQS PI = 50
7275 13:57:15.520224 [0] AVG Duty = 4953%(X100)
7276 13:57:15.520801
7277 13:57:15.521176 ==DQM 1 ==
7278 13:57:15.523278 Final DQM duty delay cell = 0
7279 13:57:15.526760 [0] MAX Duty = 5249%(X100), DQS PI = 30
7280 13:57:15.529848 [0] MIN Duty = 5000%(X100), DQS PI = 20
7281 13:57:15.533664 [0] AVG Duty = 5124%(X100)
7282 13:57:15.534275
7283 13:57:15.536587 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7284 13:57:15.537164
7285 13:57:15.539839 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7286 13:57:15.543021 [DutyScan_Calibration_Flow] ====Done====
7287 13:57:15.543489
7288 13:57:15.546382 [DutyScan_Calibration_Flow] k_type=2
7289 13:57:15.564869
7290 13:57:15.565443 ==DQ 0 ==
7291 13:57:15.567822 Final DQ duty delay cell = 0
7292 13:57:15.570942 [0] MAX Duty = 5124%(X100), DQS PI = 32
7293 13:57:15.574526 [0] MIN Duty = 5000%(X100), DQS PI = 0
7294 13:57:15.574984 [0] AVG Duty = 5062%(X100)
7295 13:57:15.575345
7296 13:57:15.578039 ==DQ 1 ==
7297 13:57:15.581227 Final DQ duty delay cell = 4
7298 13:57:15.584479 [4] MAX Duty = 5125%(X100), DQS PI = 4
7299 13:57:15.587757 [4] MIN Duty = 5062%(X100), DQS PI = 0
7300 13:57:15.588216 [4] AVG Duty = 5093%(X100)
7301 13:57:15.588575
7302 13:57:15.590998 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7303 13:57:15.591458
7304 13:57:15.594719 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7305 13:57:15.601262 [DutyScan_Calibration_Flow] ====Done====
7306 13:57:15.601825 ==
7307 13:57:15.604205 Dram Type= 6, Freq= 0, CH_1, rank 0
7308 13:57:15.607605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 13:57:15.608325 ==
7310 13:57:15.610904 [Duty_Offset_Calibration]
7311 13:57:15.611363 B0:0 B1:-1 CA:2
7312 13:57:15.611845
7313 13:57:15.614058 [DutyScan_Calibration_Flow] k_type=0
7314 13:57:15.624454
7315 13:57:15.625015 ==CLK 0==
7316 13:57:15.628088 Final CLK duty delay cell = 0
7317 13:57:15.631538 [0] MAX Duty = 5156%(X100), DQS PI = 10
7318 13:57:15.634728 [0] MIN Duty = 4906%(X100), DQS PI = 46
7319 13:57:15.637736 [0] AVG Duty = 5031%(X100)
7320 13:57:15.638218
7321 13:57:15.640924 CH1 CLK Duty spec in!! Max-Min= 250%
7322 13:57:15.644330 [DutyScan_Calibration_Flow] ====Done====
7323 13:57:15.644787
7324 13:57:15.647461 [DutyScan_Calibration_Flow] k_type=1
7325 13:57:15.664719
7326 13:57:15.665281 ==DQS 0 ==
7327 13:57:15.667708 Final DQS duty delay cell = 0
7328 13:57:15.670903 [0] MAX Duty = 5093%(X100), DQS PI = 24
7329 13:57:15.674576 [0] MIN Duty = 4969%(X100), DQS PI = 16
7330 13:57:15.677736 [0] AVG Duty = 5031%(X100)
7331 13:57:15.678342
7332 13:57:15.678709 ==DQS 1 ==
7333 13:57:15.681292 Final DQS duty delay cell = 0
7334 13:57:15.684458 [0] MAX Duty = 5187%(X100), DQS PI = 62
7335 13:57:15.687590 [0] MIN Duty = 4844%(X100), DQS PI = 34
7336 13:57:15.690905 [0] AVG Duty = 5015%(X100)
7337 13:57:15.691465
7338 13:57:15.694235 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7339 13:57:15.694797
7340 13:57:15.698000 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7341 13:57:15.700962 [DutyScan_Calibration_Flow] ====Done====
7342 13:57:15.701523
7343 13:57:15.703982 [DutyScan_Calibration_Flow] k_type=3
7344 13:57:15.722123
7345 13:57:15.722708 ==DQM 0 ==
7346 13:57:15.725731 Final DQM duty delay cell = 4
7347 13:57:15.729002 [4] MAX Duty = 5156%(X100), DQS PI = 24
7348 13:57:15.732178 [4] MIN Duty = 5000%(X100), DQS PI = 30
7349 13:57:15.735220 [4] AVG Duty = 5078%(X100)
7350 13:57:15.735678
7351 13:57:15.736035 ==DQM 1 ==
7352 13:57:15.738409 Final DQM duty delay cell = 0
7353 13:57:15.741923 [0] MAX Duty = 5281%(X100), DQS PI = 58
7354 13:57:15.745446 [0] MIN Duty = 4844%(X100), DQS PI = 34
7355 13:57:15.748578 [0] AVG Duty = 5062%(X100)
7356 13:57:15.749144
7357 13:57:15.751966 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7358 13:57:15.752531
7359 13:57:15.755687 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7360 13:57:15.758783 [DutyScan_Calibration_Flow] ====Done====
7361 13:57:15.759347
7362 13:57:15.761554 [DutyScan_Calibration_Flow] k_type=2
7363 13:57:15.779131
7364 13:57:15.779689 ==DQ 0 ==
7365 13:57:15.782551 Final DQ duty delay cell = 0
7366 13:57:15.786098 [0] MAX Duty = 5093%(X100), DQS PI = 20
7367 13:57:15.789201 [0] MIN Duty = 4969%(X100), DQS PI = 46
7368 13:57:15.789765 [0] AVG Duty = 5031%(X100)
7369 13:57:15.792059
7370 13:57:15.792515 ==DQ 1 ==
7371 13:57:15.795929 Final DQ duty delay cell = 0
7372 13:57:15.799195 [0] MAX Duty = 5062%(X100), DQS PI = 2
7373 13:57:15.802604 [0] MIN Duty = 4813%(X100), DQS PI = 34
7374 13:57:15.803165 [0] AVG Duty = 4937%(X100)
7375 13:57:15.803532
7376 13:57:15.809108 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7377 13:57:15.809672
7378 13:57:15.812355 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7379 13:57:15.815559 [DutyScan_Calibration_Flow] ====Done====
7380 13:57:15.818973 nWR fixed to 30
7381 13:57:15.819438 [ModeRegInit_LP4] CH0 RK0
7382 13:57:15.822099 [ModeRegInit_LP4] CH0 RK1
7383 13:57:15.825597 [ModeRegInit_LP4] CH1 RK0
7384 13:57:15.828831 [ModeRegInit_LP4] CH1 RK1
7385 13:57:15.829579 match AC timing 5
7386 13:57:15.835613 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7387 13:57:15.838932 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7388 13:57:15.842324 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7389 13:57:15.848603 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7390 13:57:15.852456 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7391 13:57:15.853022 [MiockJmeterHQA]
7392 13:57:15.853389
7393 13:57:15.855486 [DramcMiockJmeter] u1RxGatingPI = 0
7394 13:57:15.858895 0 : 4252, 4027
7395 13:57:15.859469 4 : 4258, 4029
7396 13:57:15.859841 8 : 4252, 4027
7397 13:57:15.862300 12 : 4252, 4027
7398 13:57:15.862877 16 : 4253, 4027
7399 13:57:15.865173 20 : 4252, 4027
7400 13:57:15.865638 24 : 4253, 4027
7401 13:57:15.868562 28 : 4363, 4137
7402 13:57:15.869025 32 : 4255, 4029
7403 13:57:15.872084 36 : 4252, 4026
7404 13:57:15.872666 40 : 4252, 4027
7405 13:57:15.873053 44 : 4253, 4027
7406 13:57:15.875055 48 : 4253, 4027
7407 13:57:15.875566 52 : 4363, 4137
7408 13:57:15.878695 56 : 4363, 4137
7409 13:57:15.879175 60 : 4255, 4029
7410 13:57:15.882011 64 : 4253, 4027
7411 13:57:15.882596 68 : 4252, 4026
7412 13:57:15.885037 72 : 4252, 4027
7413 13:57:15.885514 76 : 4250, 4027
7414 13:57:15.885886 80 : 4361, 4138
7415 13:57:15.888319 84 : 4255, 4029
7416 13:57:15.888795 88 : 4250, 3672
7417 13:57:15.892110 92 : 4252, 0
7418 13:57:15.892684 96 : 4250, 0
7419 13:57:15.893069 100 : 4253, 0
7420 13:57:15.895245 104 : 4252, 0
7421 13:57:15.895819 108 : 4253, 0
7422 13:57:15.898539 112 : 4250, 0
7423 13:57:15.899113 116 : 4252, 0
7424 13:57:15.899496 120 : 4361, 0
7425 13:57:15.901913 124 : 4250, 0
7426 13:57:15.902422 128 : 4250, 0
7427 13:57:15.904762 132 : 4250, 0
7428 13:57:15.905238 136 : 4252, 0
7429 13:57:15.905618 140 : 4363, 0
7430 13:57:15.908643 144 : 4250, 0
7431 13:57:15.909222 148 : 4250, 0
7432 13:57:15.912171 152 : 4250, 0
7433 13:57:15.912744 156 : 4253, 0
7434 13:57:15.913126 160 : 4250, 0
7435 13:57:15.915435 164 : 4250, 0
7436 13:57:15.915913 168 : 4253, 0
7437 13:57:15.916298 172 : 4361, 0
7438 13:57:15.918261 176 : 4250, 0
7439 13:57:15.918738 180 : 4250, 0
7440 13:57:15.922027 184 : 4250, 0
7441 13:57:15.922597 188 : 4360, 0
7442 13:57:15.922975 192 : 4360, 0
7443 13:57:15.925161 196 : 4250, 0
7444 13:57:15.925731 200 : 4250, 9
7445 13:57:15.928535 204 : 4250, 2607
7446 13:57:15.929105 208 : 4250, 4026
7447 13:57:15.931502 212 : 4361, 4138
7448 13:57:15.932000 216 : 4250, 4027
7449 13:57:15.932384 220 : 4250, 4027
7450 13:57:15.934923 224 : 4361, 4138
7451 13:57:15.935403 228 : 4250, 4027
7452 13:57:15.938518 232 : 4250, 4026
7453 13:57:15.939065 236 : 4361, 4137
7454 13:57:15.941394 240 : 4250, 4027
7455 13:57:15.941907 244 : 4252, 4027
7456 13:57:15.944946 248 : 4250, 4026
7457 13:57:15.945424 252 : 4250, 4027
7458 13:57:15.948234 256 : 4250, 4026
7459 13:57:15.948721 260 : 4250, 4027
7460 13:57:15.951526 264 : 4360, 4137
7461 13:57:15.952031 268 : 4250, 4027
7462 13:57:15.955140 272 : 4250, 4027
7463 13:57:15.955713 276 : 4361, 4137
7464 13:57:15.958140 280 : 4250, 4027
7465 13:57:15.958700 284 : 4250, 4027
7466 13:57:15.959089 288 : 4361, 4137
7467 13:57:15.961505 292 : 4250, 4026
7468 13:57:15.962125 296 : 4250, 4027
7469 13:57:15.965164 300 : 4252, 4027
7470 13:57:15.965735 304 : 4250, 4027
7471 13:57:15.968054 308 : 4250, 4027
7472 13:57:15.968530 312 : 4250, 3938
7473 13:57:15.971577 316 : 4360, 2168
7474 13:57:15.972153
7475 13:57:15.972528 MIOCK jitter meter ch=0
7476 13:57:15.972873
7477 13:57:15.975234 1T = (316-92) = 224 dly cells
7478 13:57:15.981514 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7479 13:57:15.982121 ==
7480 13:57:15.984893 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 13:57:15.988328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7482 13:57:15.988801 ==
7483 13:57:15.995039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7484 13:57:15.998569 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7485 13:57:16.001921 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7486 13:57:16.007869 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7487 13:57:16.017689 [CA 0] Center 42 (12~72) winsize 61
7488 13:57:16.021092 [CA 1] Center 42 (12~72) winsize 61
7489 13:57:16.024340 [CA 2] Center 37 (7~67) winsize 61
7490 13:57:16.027522 [CA 3] Center 37 (7~67) winsize 61
7491 13:57:16.030935 [CA 4] Center 36 (6~66) winsize 61
7492 13:57:16.034497 [CA 5] Center 35 (5~65) winsize 61
7493 13:57:16.034969
7494 13:57:16.037783 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7495 13:57:16.038298
7496 13:57:16.041053 [CATrainingPosCal] consider 1 rank data
7497 13:57:16.044363 u2DelayCellTimex100 = 290/100 ps
7498 13:57:16.047586 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7499 13:57:16.054375 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7500 13:57:16.057784 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7501 13:57:16.061169 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7502 13:57:16.064373 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7503 13:57:16.067673 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7504 13:57:16.068150
7505 13:57:16.070938 CA PerBit enable=1, Macro0, CA PI delay=35
7506 13:57:16.071409
7507 13:57:16.074279 [CBTSetCACLKResult] CA Dly = 35
7508 13:57:16.077514 CS Dly: 9 (0~40)
7509 13:57:16.081112 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7510 13:57:16.084332 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7511 13:57:16.084900 ==
7512 13:57:16.087629 Dram Type= 6, Freq= 0, CH_0, rank 1
7513 13:57:16.091190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 13:57:16.091774 ==
7515 13:57:16.097515 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 13:57:16.101313 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 13:57:16.107665 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 13:57:16.110911 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 13:57:16.121591 [CA 0] Center 43 (13~74) winsize 62
7520 13:57:16.124632 [CA 1] Center 43 (13~73) winsize 61
7521 13:57:16.127799 [CA 2] Center 38 (9~68) winsize 60
7522 13:57:16.131239 [CA 3] Center 38 (9~68) winsize 60
7523 13:57:16.134286 [CA 4] Center 37 (7~67) winsize 61
7524 13:57:16.137829 [CA 5] Center 36 (6~66) winsize 61
7525 13:57:16.138440
7526 13:57:16.141482 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 13:57:16.142099
7528 13:57:16.144259 [CATrainingPosCal] consider 2 rank data
7529 13:57:16.147628 u2DelayCellTimex100 = 290/100 ps
7530 13:57:16.150743 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7531 13:57:16.157547 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7532 13:57:16.160854 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7533 13:57:16.164147 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7534 13:57:16.167334 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7535 13:57:16.170632 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7536 13:57:16.171101
7537 13:57:16.174394 CA PerBit enable=1, Macro0, CA PI delay=35
7538 13:57:16.174958
7539 13:57:16.178098 [CBTSetCACLKResult] CA Dly = 35
7540 13:57:16.181300 CS Dly: 10 (0~43)
7541 13:57:16.184677 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 13:57:16.187656 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 13:57:16.188239
7544 13:57:16.190780 ----->DramcWriteLeveling(PI) begin...
7545 13:57:16.191259 ==
7546 13:57:16.194227 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 13:57:16.200951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 13:57:16.201525 ==
7549 13:57:16.204508 Write leveling (Byte 0): 37 => 37
7550 13:57:16.205074 Write leveling (Byte 1): 32 => 32
7551 13:57:16.207230 DramcWriteLeveling(PI) end<-----
7552 13:57:16.207715
7553 13:57:16.208089 ==
7554 13:57:16.211183 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 13:57:16.217383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 13:57:16.217987 ==
7557 13:57:16.221264 [Gating] SW mode calibration
7558 13:57:16.227730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7559 13:57:16.230859 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7560 13:57:16.237517 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 13:57:16.240945 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 13:57:16.244100 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7563 13:57:16.250913 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7564 13:57:16.254184 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7565 13:57:16.257697 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7566 13:57:16.264060 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 13:57:16.267484 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 13:57:16.270227 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 13:57:16.277047 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 13:57:16.280247 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7571 13:57:16.284065 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7572 13:57:16.287051 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7573 13:57:16.294269 1 5 20 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
7574 13:57:16.297467 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 13:57:16.300954 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 13:57:16.307182 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 13:57:16.310407 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 13:57:16.313816 1 6 8 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
7579 13:57:16.320540 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7580 13:57:16.323801 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7581 13:57:16.327121 1 6 20 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
7582 13:57:16.333992 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 13:57:16.337056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 13:57:16.340024 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 13:57:16.346818 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 13:57:16.350748 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 13:57:16.353604 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 13:57:16.360495 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7589 13:57:16.363316 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 13:57:16.366640 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 13:57:16.373340 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 13:57:16.376667 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 13:57:16.380362 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 13:57:16.386120 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 13:57:16.389532 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 13:57:16.393204 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 13:57:16.399598 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 13:57:16.403212 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 13:57:16.406359 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 13:57:16.413197 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 13:57:16.416525 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 13:57:16.419537 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 13:57:16.426593 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 13:57:16.429895 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7605 13:57:16.432961 Total UI for P1: 0, mck2ui 16
7606 13:57:16.436504 best dqsien dly found for B0: ( 1, 9, 10)
7607 13:57:16.439385 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7608 13:57:16.446214 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 13:57:16.446784 Total UI for P1: 0, mck2ui 16
7610 13:57:16.452675 best dqsien dly found for B1: ( 1, 9, 18)
7611 13:57:16.456183 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7612 13:57:16.459548 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7613 13:57:16.460111
7614 13:57:16.462419 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7615 13:57:16.466166 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7616 13:57:16.469338 [Gating] SW calibration Done
7617 13:57:16.469997 ==
7618 13:57:16.472813 Dram Type= 6, Freq= 0, CH_0, rank 0
7619 13:57:16.476283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7620 13:57:16.476873 ==
7621 13:57:16.479394 RX Vref Scan: 0
7622 13:57:16.479865
7623 13:57:16.480234 RX Vref 0 -> 0, step: 1
7624 13:57:16.480581
7625 13:57:16.482822 RX Delay 0 -> 252, step: 8
7626 13:57:16.486201 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7627 13:57:16.492816 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7628 13:57:16.496021 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7629 13:57:16.499459 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7630 13:57:16.502475 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7631 13:57:16.505846 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7632 13:57:16.509142 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7633 13:57:16.515617 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7634 13:57:16.519251 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7635 13:57:16.522686 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7636 13:57:16.525819 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7637 13:57:16.532396 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7638 13:57:16.535855 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7639 13:57:16.539123 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7640 13:57:16.542385 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7641 13:57:16.545394 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7642 13:57:16.546011 ==
7643 13:57:16.548944 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 13:57:16.555361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 13:57:16.555936 ==
7646 13:57:16.556314 DQS Delay:
7647 13:57:16.558820 DQS0 = 0, DQS1 = 0
7648 13:57:16.559387 DQM Delay:
7649 13:57:16.562082 DQM0 = 138, DQM1 = 126
7650 13:57:16.562641 DQ Delay:
7651 13:57:16.565439 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7652 13:57:16.568947 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7653 13:57:16.571771 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7654 13:57:16.575506 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7655 13:57:16.576073
7656 13:57:16.576444
7657 13:57:16.576788 ==
7658 13:57:16.578567 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 13:57:16.585254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 13:57:16.585821 ==
7661 13:57:16.586257
7662 13:57:16.586611
7663 13:57:16.586944 TX Vref Scan disable
7664 13:57:16.588505 == TX Byte 0 ==
7665 13:57:16.592236 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7666 13:57:16.598479 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7667 13:57:16.598954 == TX Byte 1 ==
7668 13:57:16.602155 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7669 13:57:16.608745 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7670 13:57:16.609310 ==
7671 13:57:16.611530 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 13:57:16.615152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 13:57:16.615722 ==
7674 13:57:16.628148
7675 13:57:16.631339 TX Vref early break, caculate TX vref
7676 13:57:16.634614 TX Vref=16, minBit 4, minWin=23, winSum=379
7677 13:57:16.637562 TX Vref=18, minBit 6, minWin=23, winSum=384
7678 13:57:16.641485 TX Vref=20, minBit 7, minWin=23, winSum=398
7679 13:57:16.644460 TX Vref=22, minBit 7, minWin=24, winSum=409
7680 13:57:16.647596 TX Vref=24, minBit 0, minWin=25, winSum=416
7681 13:57:16.654896 TX Vref=26, minBit 0, minWin=26, winSum=424
7682 13:57:16.657733 TX Vref=28, minBit 0, minWin=26, winSum=429
7683 13:57:16.661410 TX Vref=30, minBit 0, minWin=25, winSum=421
7684 13:57:16.664631 TX Vref=32, minBit 0, minWin=25, winSum=411
7685 13:57:16.667774 TX Vref=34, minBit 2, minWin=24, winSum=403
7686 13:57:16.674357 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
7687 13:57:16.674926
7688 13:57:16.677464 Final TX Range 0 Vref 28
7689 13:57:16.678055
7690 13:57:16.678427 ==
7691 13:57:16.680987 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 13:57:16.684373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 13:57:16.684844 ==
7694 13:57:16.685213
7695 13:57:16.685556
7696 13:57:16.687745 TX Vref Scan disable
7697 13:57:16.694081 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7698 13:57:16.694546 == TX Byte 0 ==
7699 13:57:16.697240 u2DelayCellOfst[0]=10 cells (3 PI)
7700 13:57:16.700876 u2DelayCellOfst[1]=16 cells (5 PI)
7701 13:57:16.704286 u2DelayCellOfst[2]=10 cells (3 PI)
7702 13:57:16.707720 u2DelayCellOfst[3]=10 cells (3 PI)
7703 13:57:16.710796 u2DelayCellOfst[4]=6 cells (2 PI)
7704 13:57:16.713930 u2DelayCellOfst[5]=0 cells (0 PI)
7705 13:57:16.717276 u2DelayCellOfst[6]=16 cells (5 PI)
7706 13:57:16.720726 u2DelayCellOfst[7]=13 cells (4 PI)
7707 13:57:16.724436 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7708 13:57:16.727429 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7709 13:57:16.730859 == TX Byte 1 ==
7710 13:57:16.731422 u2DelayCellOfst[8]=0 cells (0 PI)
7711 13:57:16.734155 u2DelayCellOfst[9]=3 cells (1 PI)
7712 13:57:16.737427 u2DelayCellOfst[10]=10 cells (3 PI)
7713 13:57:16.740984 u2DelayCellOfst[11]=3 cells (1 PI)
7714 13:57:16.744006 u2DelayCellOfst[12]=13 cells (4 PI)
7715 13:57:16.747123 u2DelayCellOfst[13]=13 cells (4 PI)
7716 13:57:16.750387 u2DelayCellOfst[14]=16 cells (5 PI)
7717 13:57:16.754033 u2DelayCellOfst[15]=13 cells (4 PI)
7718 13:57:16.757468 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7719 13:57:16.763900 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7720 13:57:16.764476 DramC Write-DBI on
7721 13:57:16.764848 ==
7722 13:57:16.767226 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 13:57:16.770417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 13:57:16.773865 ==
7725 13:57:16.774464
7726 13:57:16.774836
7727 13:57:16.775175 TX Vref Scan disable
7728 13:57:16.777621 == TX Byte 0 ==
7729 13:57:16.780696 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7730 13:57:16.784342 == TX Byte 1 ==
7731 13:57:16.788704 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7732 13:57:16.790505 DramC Write-DBI off
7733 13:57:16.790966
7734 13:57:16.791331 [DATLAT]
7735 13:57:16.791671 Freq=1600, CH0 RK0
7736 13:57:16.792004
7737 13:57:16.794042 DATLAT Default: 0xf
7738 13:57:16.794511 0, 0xFFFF, sum = 0
7739 13:57:16.797559 1, 0xFFFF, sum = 0
7740 13:57:16.798200 2, 0xFFFF, sum = 0
7741 13:57:16.800823 3, 0xFFFF, sum = 0
7742 13:57:16.803980 4, 0xFFFF, sum = 0
7743 13:57:16.804555 5, 0xFFFF, sum = 0
7744 13:57:16.807168 6, 0xFFFF, sum = 0
7745 13:57:16.807649 7, 0xFFFF, sum = 0
7746 13:57:16.810750 8, 0xFFFF, sum = 0
7747 13:57:16.811228 9, 0xFFFF, sum = 0
7748 13:57:16.813890 10, 0xFFFF, sum = 0
7749 13:57:16.814527 11, 0xFFFF, sum = 0
7750 13:57:16.817228 12, 0xFFFF, sum = 0
7751 13:57:16.817710 13, 0xFFFF, sum = 0
7752 13:57:16.820436 14, 0x0, sum = 1
7753 13:57:16.820939 15, 0x0, sum = 2
7754 13:57:16.824012 16, 0x0, sum = 3
7755 13:57:16.824589 17, 0x0, sum = 4
7756 13:57:16.826909 best_step = 15
7757 13:57:16.827379
7758 13:57:16.827751 ==
7759 13:57:16.830259 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 13:57:16.834074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 13:57:16.834640 ==
7762 13:57:16.837300 RX Vref Scan: 1
7763 13:57:16.837870
7764 13:57:16.838304 Set Vref Range= 24 -> 127
7765 13:57:16.838655
7766 13:57:16.840560 RX Vref 24 -> 127, step: 1
7767 13:57:16.841043
7768 13:57:16.843749 RX Delay 19 -> 252, step: 4
7769 13:57:16.844212
7770 13:57:16.846872 Set Vref, RX VrefLevel [Byte0]: 24
7771 13:57:16.850248 [Byte1]: 24
7772 13:57:16.850717
7773 13:57:16.853654 Set Vref, RX VrefLevel [Byte0]: 25
7774 13:57:16.857220 [Byte1]: 25
7775 13:57:16.857776
7776 13:57:16.860570 Set Vref, RX VrefLevel [Byte0]: 26
7777 13:57:16.863987 [Byte1]: 26
7778 13:57:16.867512
7779 13:57:16.867979 Set Vref, RX VrefLevel [Byte0]: 27
7780 13:57:16.870859 [Byte1]: 27
7781 13:57:16.875169
7782 13:57:16.875723 Set Vref, RX VrefLevel [Byte0]: 28
7783 13:57:16.878413 [Byte1]: 28
7784 13:57:16.883078
7785 13:57:16.883634 Set Vref, RX VrefLevel [Byte0]: 29
7786 13:57:16.886123 [Byte1]: 29
7787 13:57:16.890493
7788 13:57:16.891050 Set Vref, RX VrefLevel [Byte0]: 30
7789 13:57:16.893305 [Byte1]: 30
7790 13:57:16.898037
7791 13:57:16.898597 Set Vref, RX VrefLevel [Byte0]: 31
7792 13:57:16.901432 [Byte1]: 31
7793 13:57:16.905846
7794 13:57:16.906464 Set Vref, RX VrefLevel [Byte0]: 32
7795 13:57:16.908935 [Byte1]: 32
7796 13:57:16.913275
7797 13:57:16.913826 Set Vref, RX VrefLevel [Byte0]: 33
7798 13:57:16.916594 [Byte1]: 33
7799 13:57:16.920723
7800 13:57:16.921279 Set Vref, RX VrefLevel [Byte0]: 34
7801 13:57:16.923638 [Byte1]: 34
7802 13:57:16.928252
7803 13:57:16.928829 Set Vref, RX VrefLevel [Byte0]: 35
7804 13:57:16.931212 [Byte1]: 35
7805 13:57:16.935636
7806 13:57:16.936102 Set Vref, RX VrefLevel [Byte0]: 36
7807 13:57:16.938806 [Byte1]: 36
7808 13:57:16.943161
7809 13:57:16.943625 Set Vref, RX VrefLevel [Byte0]: 37
7810 13:57:16.946625 [Byte1]: 37
7811 13:57:16.950781
7812 13:57:16.951243 Set Vref, RX VrefLevel [Byte0]: 38
7813 13:57:16.954082 [Byte1]: 38
7814 13:57:16.958225
7815 13:57:16.958688 Set Vref, RX VrefLevel [Byte0]: 39
7816 13:57:16.961964 [Byte1]: 39
7817 13:57:16.966050
7818 13:57:16.966604 Set Vref, RX VrefLevel [Byte0]: 40
7819 13:57:16.969569 [Byte1]: 40
7820 13:57:16.973731
7821 13:57:16.974335 Set Vref, RX VrefLevel [Byte0]: 41
7822 13:57:16.976738 [Byte1]: 41
7823 13:57:16.981369
7824 13:57:16.981925 Set Vref, RX VrefLevel [Byte0]: 42
7825 13:57:16.984657 [Byte1]: 42
7826 13:57:16.989174
7827 13:57:16.989743 Set Vref, RX VrefLevel [Byte0]: 43
7828 13:57:16.991809 [Byte1]: 43
7829 13:57:16.996090
7830 13:57:16.996556 Set Vref, RX VrefLevel [Byte0]: 44
7831 13:57:17.000028 [Byte1]: 44
7832 13:57:17.004120
7833 13:57:17.004677 Set Vref, RX VrefLevel [Byte0]: 45
7834 13:57:17.007103 [Byte1]: 45
7835 13:57:17.011624
7836 13:57:17.012177 Set Vref, RX VrefLevel [Byte0]: 46
7837 13:57:17.014832 [Byte1]: 46
7838 13:57:17.018933
7839 13:57:17.019491 Set Vref, RX VrefLevel [Byte0]: 47
7840 13:57:17.022582 [Byte1]: 47
7841 13:57:17.026704
7842 13:57:17.027261 Set Vref, RX VrefLevel [Byte0]: 48
7843 13:57:17.030139 [Byte1]: 48
7844 13:57:17.034412
7845 13:57:17.035148 Set Vref, RX VrefLevel [Byte0]: 49
7846 13:57:17.037315 [Byte1]: 49
7847 13:57:17.041685
7848 13:57:17.042199 Set Vref, RX VrefLevel [Byte0]: 50
7849 13:57:17.044816 [Byte1]: 50
7850 13:57:17.049184
7851 13:57:17.049651 Set Vref, RX VrefLevel [Byte0]: 51
7852 13:57:17.052454 [Byte1]: 51
7853 13:57:17.056820
7854 13:57:17.057282 Set Vref, RX VrefLevel [Byte0]: 52
7855 13:57:17.060060 [Byte1]: 52
7856 13:57:17.064225
7857 13:57:17.064690 Set Vref, RX VrefLevel [Byte0]: 53
7858 13:57:17.067740 [Byte1]: 53
7859 13:57:17.072054
7860 13:57:17.072585 Set Vref, RX VrefLevel [Byte0]: 54
7861 13:57:17.075267 [Byte1]: 54
7862 13:57:17.079846
7863 13:57:17.080373 Set Vref, RX VrefLevel [Byte0]: 55
7864 13:57:17.083053 [Byte1]: 55
7865 13:57:17.087113
7866 13:57:17.087645 Set Vref, RX VrefLevel [Byte0]: 56
7867 13:57:17.090796 [Byte1]: 56
7868 13:57:17.094645
7869 13:57:17.095068 Set Vref, RX VrefLevel [Byte0]: 57
7870 13:57:17.098317 [Byte1]: 57
7871 13:57:17.102680
7872 13:57:17.103216 Set Vref, RX VrefLevel [Byte0]: 58
7873 13:57:17.105778 [Byte1]: 58
7874 13:57:17.110138
7875 13:57:17.110665 Set Vref, RX VrefLevel [Byte0]: 59
7876 13:57:17.113223 [Byte1]: 59
7877 13:57:17.117586
7878 13:57:17.118187 Set Vref, RX VrefLevel [Byte0]: 60
7879 13:57:17.120735 [Byte1]: 60
7880 13:57:17.125499
7881 13:57:17.126085 Set Vref, RX VrefLevel [Byte0]: 61
7882 13:57:17.128697 [Byte1]: 61
7883 13:57:17.132857
7884 13:57:17.133422 Set Vref, RX VrefLevel [Byte0]: 62
7885 13:57:17.136091 [Byte1]: 62
7886 13:57:17.140429
7887 13:57:17.140990 Set Vref, RX VrefLevel [Byte0]: 63
7888 13:57:17.143639 [Byte1]: 63
7889 13:57:17.147884
7890 13:57:17.148466 Set Vref, RX VrefLevel [Byte0]: 64
7891 13:57:17.150799 [Byte1]: 64
7892 13:57:17.155267
7893 13:57:17.155729 Set Vref, RX VrefLevel [Byte0]: 65
7894 13:57:17.158576 [Byte1]: 65
7895 13:57:17.162944
7896 13:57:17.163501 Set Vref, RX VrefLevel [Byte0]: 66
7897 13:57:17.166077 [Byte1]: 66
7898 13:57:17.170627
7899 13:57:17.171217 Set Vref, RX VrefLevel [Byte0]: 67
7900 13:57:17.174109 [Byte1]: 67
7901 13:57:17.178151
7902 13:57:17.178720 Set Vref, RX VrefLevel [Byte0]: 68
7903 13:57:17.181674 [Byte1]: 68
7904 13:57:17.185734
7905 13:57:17.186341 Set Vref, RX VrefLevel [Byte0]: 69
7906 13:57:17.189125 [Byte1]: 69
7907 13:57:17.193548
7908 13:57:17.194358 Set Vref, RX VrefLevel [Byte0]: 70
7909 13:57:17.196672 [Byte1]: 70
7910 13:57:17.201154
7911 13:57:17.201717 Set Vref, RX VrefLevel [Byte0]: 71
7912 13:57:17.204019 [Byte1]: 71
7913 13:57:17.208273
7914 13:57:17.211945 Set Vref, RX VrefLevel [Byte0]: 72
7915 13:57:17.214853 [Byte1]: 72
7916 13:57:17.215429
7917 13:57:17.218165 Set Vref, RX VrefLevel [Byte0]: 73
7918 13:57:17.221630 [Byte1]: 73
7919 13:57:17.222245
7920 13:57:17.224890 Set Vref, RX VrefLevel [Byte0]: 74
7921 13:57:17.228420 [Byte1]: 74
7922 13:57:17.228986
7923 13:57:17.231676 Set Vref, RX VrefLevel [Byte0]: 75
7924 13:57:17.234842 [Byte1]: 75
7925 13:57:17.238849
7926 13:57:17.239414 Set Vref, RX VrefLevel [Byte0]: 76
7927 13:57:17.242027 [Byte1]: 76
7928 13:57:17.246106
7929 13:57:17.246586 Set Vref, RX VrefLevel [Byte0]: 77
7930 13:57:17.249339 [Byte1]: 77
7931 13:57:17.253817
7932 13:57:17.254424 Set Vref, RX VrefLevel [Byte0]: 78
7933 13:57:17.257165 [Byte1]: 78
7934 13:57:17.261221
7935 13:57:17.261786 Final RX Vref Byte 0 = 57 to rank0
7936 13:57:17.264836 Final RX Vref Byte 1 = 62 to rank0
7937 13:57:17.267799 Final RX Vref Byte 0 = 57 to rank1
7938 13:57:17.271629 Final RX Vref Byte 1 = 62 to rank1==
7939 13:57:17.274507 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 13:57:17.281160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 13:57:17.281721 ==
7942 13:57:17.282160 DQS Delay:
7943 13:57:17.282519 DQS0 = 0, DQS1 = 0
7944 13:57:17.284210 DQM Delay:
7945 13:57:17.284687 DQM0 = 135, DQM1 = 124
7946 13:57:17.287915 DQ Delay:
7947 13:57:17.291465 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7948 13:57:17.294453 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
7949 13:57:17.297755 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7950 13:57:17.301081 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7951 13:57:17.301646
7952 13:57:17.302064
7953 13:57:17.302416
7954 13:57:17.304662 [DramC_TX_OE_Calibration] TA2
7955 13:57:17.308034 Original DQ_B0 (3 6) =30, OEN = 27
7956 13:57:17.310812 Original DQ_B1 (3 6) =30, OEN = 27
7957 13:57:17.314289 24, 0x0, End_B0=24 End_B1=24
7958 13:57:17.314861 25, 0x0, End_B0=25 End_B1=25
7959 13:57:17.317793 26, 0x0, End_B0=26 End_B1=26
7960 13:57:17.321068 27, 0x0, End_B0=27 End_B1=27
7961 13:57:17.324547 28, 0x0, End_B0=28 End_B1=28
7962 13:57:17.327764 29, 0x0, End_B0=29 End_B1=29
7963 13:57:17.328338 30, 0x0, End_B0=30 End_B1=30
7964 13:57:17.330591 31, 0x4141, End_B0=30 End_B1=30
7965 13:57:17.334523 Byte0 end_step=30 best_step=27
7966 13:57:17.337743 Byte1 end_step=30 best_step=27
7967 13:57:17.341237 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 13:57:17.344117 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 13:57:17.344584
7970 13:57:17.344954
7971 13:57:17.351031 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7972 13:57:17.354085 CH0 RK0: MR19=303, MR18=1C1A
7973 13:57:17.361164 CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15
7974 13:57:17.361736
7975 13:57:17.364283 ----->DramcWriteLeveling(PI) begin...
7976 13:57:17.364852 ==
7977 13:57:17.367364 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 13:57:17.370823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 13:57:17.371289 ==
7980 13:57:17.374133 Write leveling (Byte 0): 39 => 39
7981 13:57:17.377843 Write leveling (Byte 1): 30 => 30
7982 13:57:17.380551 DramcWriteLeveling(PI) end<-----
7983 13:57:17.381019
7984 13:57:17.381383 ==
7985 13:57:17.383779 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 13:57:17.387478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 13:57:17.388057 ==
7988 13:57:17.390626 [Gating] SW mode calibration
7989 13:57:17.397353 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 13:57:17.403730 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 13:57:17.407624 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 13:57:17.414492 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 13:57:17.417327 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 13:57:17.420288 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7995 13:57:17.423952 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 13:57:17.430528 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 13:57:17.434083 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 13:57:17.437370 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 13:57:17.443799 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 13:57:17.447009 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 13:57:17.450260 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 13:57:17.457339 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 1)
8003 13:57:17.460340 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8004 13:57:17.463679 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 13:57:17.470306 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 13:57:17.473762 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 13:57:17.476948 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 13:57:17.483871 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 13:57:17.486836 1 6 8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
8010 13:57:17.490385 1 6 12 | B1->B0 | 2f2f 4545 | 0 1 | (0 0) (0 0)
8011 13:57:17.497095 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8012 13:57:17.500490 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 13:57:17.503596 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 13:57:17.510592 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 13:57:17.513731 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 13:57:17.517192 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 13:57:17.523940 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 13:57:17.527343 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8019 13:57:17.530193 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8020 13:57:17.537022 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 13:57:17.540411 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 13:57:17.543601 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 13:57:17.550060 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 13:57:17.553582 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 13:57:17.556817 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 13:57:17.560246 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 13:57:17.567024 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 13:57:17.570049 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 13:57:17.573215 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 13:57:17.580136 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 13:57:17.583377 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 13:57:17.586620 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 13:57:17.593292 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 13:57:17.596229 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8035 13:57:17.599763 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8036 13:57:17.602917 Total UI for P1: 0, mck2ui 16
8037 13:57:17.606464 best dqsien dly found for B0: ( 1, 9, 10)
8038 13:57:17.613130 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 13:57:17.613700 Total UI for P1: 0, mck2ui 16
8040 13:57:17.619847 best dqsien dly found for B1: ( 1, 9, 14)
8041 13:57:17.623280 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8042 13:57:17.626880 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8043 13:57:17.627449
8044 13:57:17.629850 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8045 13:57:17.633085 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8046 13:57:17.636692 [Gating] SW calibration Done
8047 13:57:17.637264 ==
8048 13:57:17.639754 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 13:57:17.643301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 13:57:17.643872 ==
8051 13:57:17.646178 RX Vref Scan: 0
8052 13:57:17.646648
8053 13:57:17.647018 RX Vref 0 -> 0, step: 1
8054 13:57:17.649678
8055 13:57:17.650375 RX Delay 0 -> 252, step: 8
8056 13:57:17.656369 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8057 13:57:17.659687 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8058 13:57:17.663176 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8059 13:57:17.666294 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8060 13:57:17.669509 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8061 13:57:17.672883 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8062 13:57:17.679276 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8063 13:57:17.682783 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8064 13:57:17.685878 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8065 13:57:17.689482 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8066 13:57:17.692994 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8067 13:57:17.699434 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8068 13:57:17.702579 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8069 13:57:17.706217 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8070 13:57:17.709356 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8071 13:57:17.716124 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8072 13:57:17.716692 ==
8073 13:57:17.719424 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 13:57:17.722411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 13:57:17.722880 ==
8076 13:57:17.723248 DQS Delay:
8077 13:57:17.726101 DQS0 = 0, DQS1 = 0
8078 13:57:17.726856 DQM Delay:
8079 13:57:17.729277 DQM0 = 136, DQM1 = 126
8080 13:57:17.729842 DQ Delay:
8081 13:57:17.732795 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8082 13:57:17.735994 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8083 13:57:17.739025 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8084 13:57:17.742846 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8085 13:57:17.743484
8086 13:57:17.743862
8087 13:57:17.745738 ==
8088 13:57:17.746229 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 13:57:17.752734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 13:57:17.753298 ==
8091 13:57:17.753670
8092 13:57:17.754061
8093 13:57:17.755794 TX Vref Scan disable
8094 13:57:17.756252 == TX Byte 0 ==
8095 13:57:17.759416 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8096 13:57:17.766085 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8097 13:57:17.766655 == TX Byte 1 ==
8098 13:57:17.769219 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8099 13:57:17.776213 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8100 13:57:17.776755 ==
8101 13:57:17.779096 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 13:57:17.782658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 13:57:17.783220 ==
8104 13:57:17.796386
8105 13:57:17.799561 TX Vref early break, caculate TX vref
8106 13:57:17.802735 TX Vref=16, minBit 2, minWin=23, winSum=392
8107 13:57:17.806286 TX Vref=18, minBit 0, minWin=24, winSum=402
8108 13:57:17.809495 TX Vref=20, minBit 8, minWin=23, winSum=410
8109 13:57:17.812703 TX Vref=22, minBit 0, minWin=25, winSum=420
8110 13:57:17.816371 TX Vref=24, minBit 0, minWin=25, winSum=423
8111 13:57:17.822958 TX Vref=26, minBit 0, minWin=26, winSum=437
8112 13:57:17.825937 TX Vref=28, minBit 0, minWin=26, winSum=431
8113 13:57:17.829513 TX Vref=30, minBit 0, minWin=26, winSum=425
8114 13:57:17.832409 TX Vref=32, minBit 0, minWin=25, winSum=419
8115 13:57:17.836096 TX Vref=34, minBit 0, minWin=25, winSum=409
8116 13:57:17.842438 [TxChooseVref] Worse bit 0, Min win 26, Win sum 437, Final Vref 26
8117 13:57:17.843047
8118 13:57:17.845698 Final TX Range 0 Vref 26
8119 13:57:17.846206
8120 13:57:17.846573 ==
8121 13:57:17.849187 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 13:57:17.852809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 13:57:17.853376 ==
8124 13:57:17.853742
8125 13:57:17.854150
8126 13:57:17.855837 TX Vref Scan disable
8127 13:57:17.862715 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8128 13:57:17.863277 == TX Byte 0 ==
8129 13:57:17.865653 u2DelayCellOfst[0]=13 cells (4 PI)
8130 13:57:17.869154 u2DelayCellOfst[1]=20 cells (6 PI)
8131 13:57:17.872442 u2DelayCellOfst[2]=13 cells (4 PI)
8132 13:57:17.875835 u2DelayCellOfst[3]=13 cells (4 PI)
8133 13:57:17.878902 u2DelayCellOfst[4]=10 cells (3 PI)
8134 13:57:17.882556 u2DelayCellOfst[5]=0 cells (0 PI)
8135 13:57:17.885709 u2DelayCellOfst[6]=20 cells (6 PI)
8136 13:57:17.889356 u2DelayCellOfst[7]=16 cells (5 PI)
8137 13:57:17.892541 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8138 13:57:17.895844 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8139 13:57:17.898954 == TX Byte 1 ==
8140 13:57:17.902153 u2DelayCellOfst[8]=0 cells (0 PI)
8141 13:57:17.905573 u2DelayCellOfst[9]=3 cells (1 PI)
8142 13:57:17.906078 u2DelayCellOfst[10]=10 cells (3 PI)
8143 13:57:17.908766 u2DelayCellOfst[11]=6 cells (2 PI)
8144 13:57:17.911794 u2DelayCellOfst[12]=13 cells (4 PI)
8145 13:57:17.915032 u2DelayCellOfst[13]=13 cells (4 PI)
8146 13:57:17.918525 u2DelayCellOfst[14]=16 cells (5 PI)
8147 13:57:17.922113 u2DelayCellOfst[15]=13 cells (4 PI)
8148 13:57:17.928722 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8149 13:57:17.932085 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8150 13:57:17.932680 DramC Write-DBI on
8151 13:57:17.933059 ==
8152 13:57:17.935363 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 13:57:17.941630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 13:57:17.942206 ==
8155 13:57:17.942586
8156 13:57:17.942926
8157 13:57:17.943250 TX Vref Scan disable
8158 13:57:17.945737 == TX Byte 0 ==
8159 13:57:17.949009 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8160 13:57:17.952686 == TX Byte 1 ==
8161 13:57:17.955804 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8162 13:57:17.958915 DramC Write-DBI off
8163 13:57:17.959374
8164 13:57:17.959735 [DATLAT]
8165 13:57:17.960077 Freq=1600, CH0 RK1
8166 13:57:17.960403
8167 13:57:17.962792 DATLAT Default: 0xf
8168 13:57:17.963346 0, 0xFFFF, sum = 0
8169 13:57:17.966000 1, 0xFFFF, sum = 0
8170 13:57:17.966473 2, 0xFFFF, sum = 0
8171 13:57:17.969701 3, 0xFFFF, sum = 0
8172 13:57:17.972898 4, 0xFFFF, sum = 0
8173 13:57:17.973458 5, 0xFFFF, sum = 0
8174 13:57:17.975931 6, 0xFFFF, sum = 0
8175 13:57:17.976491 7, 0xFFFF, sum = 0
8176 13:57:17.979435 8, 0xFFFF, sum = 0
8177 13:57:17.979996 9, 0xFFFF, sum = 0
8178 13:57:17.982598 10, 0xFFFF, sum = 0
8179 13:57:17.983162 11, 0xFFFF, sum = 0
8180 13:57:17.986154 12, 0xFFFF, sum = 0
8181 13:57:17.986722 13, 0xFFFF, sum = 0
8182 13:57:17.989295 14, 0x0, sum = 1
8183 13:57:17.989762 15, 0x0, sum = 2
8184 13:57:17.992590 16, 0x0, sum = 3
8185 13:57:17.993154 17, 0x0, sum = 4
8186 13:57:17.996063 best_step = 15
8187 13:57:17.996616
8188 13:57:17.996980 ==
8189 13:57:17.999179 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 13:57:18.002421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 13:57:18.002886 ==
8192 13:57:18.003252 RX Vref Scan: 0
8193 13:57:18.005486
8194 13:57:18.005969 RX Vref 0 -> 0, step: 1
8195 13:57:18.006355
8196 13:57:18.009193 RX Delay 11 -> 252, step: 4
8197 13:57:18.012478 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8198 13:57:18.019679 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8199 13:57:18.022208 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8200 13:57:18.025796 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8201 13:57:18.029461 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8202 13:57:18.032822 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8203 13:57:18.035858 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8204 13:57:18.042660 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8205 13:57:18.045713 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8206 13:57:18.049221 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8207 13:57:18.052308 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8208 13:57:18.055745 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8209 13:57:18.062307 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8210 13:57:18.065756 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8211 13:57:18.069121 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8212 13:57:18.072514 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8213 13:57:18.073086 ==
8214 13:57:18.075538 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 13:57:18.082297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 13:57:18.082767 ==
8217 13:57:18.083194 DQS Delay:
8218 13:57:18.085308 DQS0 = 0, DQS1 = 0
8219 13:57:18.085770 DQM Delay:
8220 13:57:18.088679 DQM0 = 133, DQM1 = 123
8221 13:57:18.089141 DQ Delay:
8222 13:57:18.092411 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8223 13:57:18.095656 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8224 13:57:18.098733 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8225 13:57:18.102356 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8226 13:57:18.102843
8227 13:57:18.103205
8228 13:57:18.103539
8229 13:57:18.105246 [DramC_TX_OE_Calibration] TA2
8230 13:57:18.108950 Original DQ_B0 (3 6) =30, OEN = 27
8231 13:57:18.112331 Original DQ_B1 (3 6) =30, OEN = 27
8232 13:57:18.115390 24, 0x0, End_B0=24 End_B1=24
8233 13:57:18.118951 25, 0x0, End_B0=25 End_B1=25
8234 13:57:18.119520 26, 0x0, End_B0=26 End_B1=26
8235 13:57:18.122202 27, 0x0, End_B0=27 End_B1=27
8236 13:57:18.125717 28, 0x0, End_B0=28 End_B1=28
8237 13:57:18.128877 29, 0x0, End_B0=29 End_B1=29
8238 13:57:18.129449 30, 0x0, End_B0=30 End_B1=30
8239 13:57:18.131926 31, 0x4141, End_B0=30 End_B1=30
8240 13:57:18.135288 Byte0 end_step=30 best_step=27
8241 13:57:18.138947 Byte1 end_step=30 best_step=27
8242 13:57:18.142113 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 13:57:18.145071 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 13:57:18.145536
8245 13:57:18.145900
8246 13:57:18.151842 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 395 ps
8247 13:57:18.155223 CH0 RK1: MR19=303, MR18=1D0B
8248 13:57:18.161698 CH0_RK1: MR19=0x303, MR18=0x1D0B, DQSOSC=395, MR23=63, INC=23, DEC=15
8249 13:57:18.165549 [RxdqsGatingPostProcess] freq 1600
8250 13:57:18.168792 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8251 13:57:18.171657 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 13:57:18.175407 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 13:57:18.178677 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 13:57:18.181836 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 13:57:18.185136 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 13:57:18.188769 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 13:57:18.191756 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 13:57:18.195258 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 13:57:18.198551 Pre-setting of DQS Precalculation
8260 13:57:18.201465 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8261 13:57:18.201936 ==
8262 13:57:18.205127 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 13:57:18.208616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 13:57:18.211551 ==
8265 13:57:18.215352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 13:57:18.218556 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 13:57:18.225259 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 13:57:18.231968 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 13:57:18.238873 [CA 0] Center 40 (11~70) winsize 60
8270 13:57:18.242151 [CA 1] Center 41 (11~71) winsize 61
8271 13:57:18.245206 [CA 2] Center 37 (8~67) winsize 60
8272 13:57:18.248793 [CA 3] Center 36 (7~66) winsize 60
8273 13:57:18.251812 [CA 4] Center 37 (7~67) winsize 61
8274 13:57:18.255687 [CA 5] Center 36 (6~66) winsize 61
8275 13:57:18.256160
8276 13:57:18.259002 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8277 13:57:18.259467
8278 13:57:18.262272 [CATrainingPosCal] consider 1 rank data
8279 13:57:18.265553 u2DelayCellTimex100 = 290/100 ps
8280 13:57:18.268843 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8281 13:57:18.275574 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8282 13:57:18.279198 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8283 13:57:18.281995 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8284 13:57:18.285303 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8285 13:57:18.288782 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8286 13:57:18.289356
8287 13:57:18.292419 CA PerBit enable=1, Macro0, CA PI delay=36
8288 13:57:18.292992
8289 13:57:18.295252 [CBTSetCACLKResult] CA Dly = 36
8290 13:57:18.295745 CS Dly: 9 (0~40)
8291 13:57:18.302093 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 13:57:18.305246 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 13:57:18.305722 ==
8294 13:57:18.308752 Dram Type= 6, Freq= 0, CH_1, rank 1
8295 13:57:18.311917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 13:57:18.312378 ==
8297 13:57:18.318675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 13:57:18.321780 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 13:57:18.329060 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 13:57:18.332339 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 13:57:18.342061 [CA 0] Center 42 (12~72) winsize 61
8302 13:57:18.345245 [CA 1] Center 42 (12~72) winsize 61
8303 13:57:18.348388 [CA 2] Center 37 (8~67) winsize 60
8304 13:57:18.351839 [CA 3] Center 37 (8~66) winsize 59
8305 13:57:18.354955 [CA 4] Center 37 (8~66) winsize 59
8306 13:57:18.358411 [CA 5] Center 36 (7~66) winsize 60
8307 13:57:18.358873
8308 13:57:18.361619 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8309 13:57:18.362119
8310 13:57:18.365181 [CATrainingPosCal] consider 2 rank data
8311 13:57:18.368445 u2DelayCellTimex100 = 290/100 ps
8312 13:57:18.371807 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8313 13:57:18.378606 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8314 13:57:18.382070 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8315 13:57:18.385074 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8316 13:57:18.388176 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8317 13:57:18.391898 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8318 13:57:18.392452
8319 13:57:18.394907 CA PerBit enable=1, Macro0, CA PI delay=36
8320 13:57:18.395450
8321 13:57:18.398595 [CBTSetCACLKResult] CA Dly = 36
8322 13:57:18.401466 CS Dly: 10 (0~42)
8323 13:57:18.404927 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 13:57:18.408432 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 13:57:18.408990
8326 13:57:18.411748 ----->DramcWriteLeveling(PI) begin...
8327 13:57:18.412308 ==
8328 13:57:18.414862 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 13:57:18.418507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 13:57:18.421866 ==
8331 13:57:18.422632 Write leveling (Byte 0): 26 => 26
8332 13:57:18.424935 Write leveling (Byte 1): 27 => 27
8333 13:57:18.428685 DramcWriteLeveling(PI) end<-----
8334 13:57:18.429237
8335 13:57:18.429597 ==
8336 13:57:18.431550 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 13:57:18.438274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 13:57:18.438815 ==
8339 13:57:18.441588 [Gating] SW mode calibration
8340 13:57:18.448113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8341 13:57:18.451967 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8342 13:57:18.458109 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 13:57:18.461315 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 13:57:18.464847 1 4 8 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
8345 13:57:18.471508 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 13:57:18.474590 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 13:57:18.478053 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 13:57:18.481583 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 13:57:18.488105 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 13:57:18.491367 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 13:57:18.494232 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 13:57:18.501147 1 5 8 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (1 0)
8353 13:57:18.504592 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8354 13:57:18.508164 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 13:57:18.514353 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 13:57:18.518264 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 13:57:18.521433 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 13:57:18.527966 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 13:57:18.531068 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8360 13:57:18.534802 1 6 8 | B1->B0 | 3434 4141 | 1 0 | (0 0) (0 0)
8361 13:57:18.541231 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 13:57:18.544702 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 13:57:18.548049 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 13:57:18.554752 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 13:57:18.557846 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 13:57:18.561334 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 13:57:18.567742 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 13:57:18.570928 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8369 13:57:18.574221 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8370 13:57:18.581020 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 13:57:18.584331 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 13:57:18.587817 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 13:57:18.594101 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 13:57:18.597526 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 13:57:18.601016 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 13:57:18.608009 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 13:57:18.610893 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 13:57:18.614157 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 13:57:18.621055 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 13:57:18.624203 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 13:57:18.627486 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 13:57:18.633637 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 13:57:18.637022 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8384 13:57:18.640561 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8385 13:57:18.646920 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8386 13:57:18.647475 Total UI for P1: 0, mck2ui 16
8387 13:57:18.650456 best dqsien dly found for B0: ( 1, 9, 6)
8388 13:57:18.657339 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 13:57:18.660475 Total UI for P1: 0, mck2ui 16
8390 13:57:18.663834 best dqsien dly found for B1: ( 1, 9, 10)
8391 13:57:18.667250 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8392 13:57:18.670713 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8393 13:57:18.671281
8394 13:57:18.673989 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8395 13:57:18.677082 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8396 13:57:18.680607 [Gating] SW calibration Done
8397 13:57:18.681177 ==
8398 13:57:18.683507 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 13:57:18.686905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 13:57:18.687443 ==
8401 13:57:18.690436 RX Vref Scan: 0
8402 13:57:18.690899
8403 13:57:18.693581 RX Vref 0 -> 0, step: 1
8404 13:57:18.694169
8405 13:57:18.694744 RX Delay 0 -> 252, step: 8
8406 13:57:18.696815 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8407 13:57:18.703503 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8408 13:57:18.707091 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8409 13:57:18.710608 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8410 13:57:18.713730 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8411 13:57:18.717131 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8412 13:57:18.723726 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8413 13:57:18.727142 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8414 13:57:18.730462 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8415 13:57:18.734029 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8416 13:57:18.736976 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8417 13:57:18.744603 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8418 13:57:18.746991 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8419 13:57:18.750109 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8420 13:57:18.753826 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8421 13:57:18.757223 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8422 13:57:18.760160 ==
8423 13:57:18.760627 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 13:57:18.766820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 13:57:18.767389 ==
8426 13:57:18.767762 DQS Delay:
8427 13:57:18.770388 DQS0 = 0, DQS1 = 0
8428 13:57:18.770976 DQM Delay:
8429 13:57:18.773686 DQM0 = 138, DQM1 = 130
8430 13:57:18.774290 DQ Delay:
8431 13:57:18.776859 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8432 13:57:18.780398 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8433 13:57:18.783271 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8434 13:57:18.786714 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8435 13:57:18.787248
8436 13:57:18.787625
8437 13:57:18.787963 ==
8438 13:57:18.790119 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 13:57:18.797194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 13:57:18.797758 ==
8441 13:57:18.798184
8442 13:57:18.798527
8443 13:57:18.798852 TX Vref Scan disable
8444 13:57:18.800569 == TX Byte 0 ==
8445 13:57:18.803348 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8446 13:57:18.810416 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8447 13:57:18.810981 == TX Byte 1 ==
8448 13:57:18.813241 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8449 13:57:18.820279 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8450 13:57:18.820848 ==
8451 13:57:18.823660 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 13:57:18.826549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 13:57:18.827125 ==
8454 13:57:18.839007
8455 13:57:18.841842 TX Vref early break, caculate TX vref
8456 13:57:18.845497 TX Vref=16, minBit 10, minWin=22, winSum=371
8457 13:57:18.848912 TX Vref=18, minBit 10, minWin=23, winSum=385
8458 13:57:18.852087 TX Vref=20, minBit 0, minWin=23, winSum=393
8459 13:57:18.855430 TX Vref=22, minBit 1, minWin=24, winSum=402
8460 13:57:18.858770 TX Vref=24, minBit 1, minWin=25, winSum=410
8461 13:57:18.865607 TX Vref=26, minBit 10, minWin=25, winSum=421
8462 13:57:18.869001 TX Vref=28, minBit 14, minWin=25, winSum=423
8463 13:57:18.872165 TX Vref=30, minBit 6, minWin=25, winSum=414
8464 13:57:18.875646 TX Vref=32, minBit 8, minWin=24, winSum=403
8465 13:57:18.878799 TX Vref=34, minBit 6, minWin=23, winSum=392
8466 13:57:18.885591 [TxChooseVref] Worse bit 14, Min win 25, Win sum 423, Final Vref 28
8467 13:57:18.886202
8468 13:57:18.888543 Final TX Range 0 Vref 28
8469 13:57:18.889109
8470 13:57:18.889472 ==
8471 13:57:18.892107 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 13:57:18.895265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 13:57:18.895853 ==
8474 13:57:18.896235
8475 13:57:18.896577
8476 13:57:18.898431 TX Vref Scan disable
8477 13:57:18.905499 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8478 13:57:18.906032 == TX Byte 0 ==
8479 13:57:18.908621 u2DelayCellOfst[0]=13 cells (4 PI)
8480 13:57:18.911896 u2DelayCellOfst[1]=10 cells (3 PI)
8481 13:57:18.915299 u2DelayCellOfst[2]=0 cells (0 PI)
8482 13:57:18.918413 u2DelayCellOfst[3]=3 cells (1 PI)
8483 13:57:18.921844 u2DelayCellOfst[4]=6 cells (2 PI)
8484 13:57:18.925058 u2DelayCellOfst[5]=16 cells (5 PI)
8485 13:57:18.928671 u2DelayCellOfst[6]=16 cells (5 PI)
8486 13:57:18.932053 u2DelayCellOfst[7]=3 cells (1 PI)
8487 13:57:18.935107 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8488 13:57:18.938522 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8489 13:57:18.941902 == TX Byte 1 ==
8490 13:57:18.942513 u2DelayCellOfst[8]=0 cells (0 PI)
8491 13:57:18.945583 u2DelayCellOfst[9]=3 cells (1 PI)
8492 13:57:18.948417 u2DelayCellOfst[10]=13 cells (4 PI)
8493 13:57:18.951899 u2DelayCellOfst[11]=3 cells (1 PI)
8494 13:57:18.954766 u2DelayCellOfst[12]=16 cells (5 PI)
8495 13:57:18.958114 u2DelayCellOfst[13]=20 cells (6 PI)
8496 13:57:18.961612 u2DelayCellOfst[14]=20 cells (6 PI)
8497 13:57:18.964937 u2DelayCellOfst[15]=16 cells (5 PI)
8498 13:57:18.968643 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8499 13:57:18.975040 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8500 13:57:18.975532 DramC Write-DBI on
8501 13:57:18.975915 ==
8502 13:57:18.977916 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 13:57:18.982007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 13:57:18.984744 ==
8505 13:57:18.985218
8506 13:57:18.985589
8507 13:57:18.985933 TX Vref Scan disable
8508 13:57:18.988738 == TX Byte 0 ==
8509 13:57:18.991783 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8510 13:57:18.994911 == TX Byte 1 ==
8511 13:57:18.998737 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8512 13:57:19.001502 DramC Write-DBI off
8513 13:57:19.002102
8514 13:57:19.002480 [DATLAT]
8515 13:57:19.002824 Freq=1600, CH1 RK0
8516 13:57:19.003182
8517 13:57:19.004974 DATLAT Default: 0xf
8518 13:57:19.005438 0, 0xFFFF, sum = 0
8519 13:57:19.008815 1, 0xFFFF, sum = 0
8520 13:57:19.009404 2, 0xFFFF, sum = 0
8521 13:57:19.011678 3, 0xFFFF, sum = 0
8522 13:57:19.015024 4, 0xFFFF, sum = 0
8523 13:57:19.015497 5, 0xFFFF, sum = 0
8524 13:57:19.018400 6, 0xFFFF, sum = 0
8525 13:57:19.018991 7, 0xFFFF, sum = 0
8526 13:57:19.021406 8, 0xFFFF, sum = 0
8527 13:57:19.021879 9, 0xFFFF, sum = 0
8528 13:57:19.024729 10, 0xFFFF, sum = 0
8529 13:57:19.025202 11, 0xFFFF, sum = 0
8530 13:57:19.028398 12, 0xFFFF, sum = 0
8531 13:57:19.029009 13, 0xFFFF, sum = 0
8532 13:57:19.031391 14, 0x0, sum = 1
8533 13:57:19.031864 15, 0x0, sum = 2
8534 13:57:19.035336 16, 0x0, sum = 3
8535 13:57:19.035952 17, 0x0, sum = 4
8536 13:57:19.038364 best_step = 15
8537 13:57:19.038828
8538 13:57:19.039192 ==
8539 13:57:19.041758 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 13:57:19.045208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 13:57:19.045778 ==
8542 13:57:19.046281 RX Vref Scan: 1
8543 13:57:19.048183
8544 13:57:19.048781 Set Vref Range= 24 -> 127
8545 13:57:19.049168
8546 13:57:19.051806 RX Vref 24 -> 127, step: 1
8547 13:57:19.052369
8548 13:57:19.055127 RX Delay 19 -> 252, step: 4
8549 13:57:19.055702
8550 13:57:19.058399 Set Vref, RX VrefLevel [Byte0]: 24
8551 13:57:19.061333 [Byte1]: 24
8552 13:57:19.061896
8553 13:57:19.064779 Set Vref, RX VrefLevel [Byte0]: 25
8554 13:57:19.068694 [Byte1]: 25
8555 13:57:19.069264
8556 13:57:19.071852 Set Vref, RX VrefLevel [Byte0]: 26
8557 13:57:19.074850 [Byte1]: 26
8558 13:57:19.078700
8559 13:57:19.079263 Set Vref, RX VrefLevel [Byte0]: 27
8560 13:57:19.082192 [Byte1]: 27
8561 13:57:19.086458
8562 13:57:19.087018 Set Vref, RX VrefLevel [Byte0]: 28
8563 13:57:19.089586 [Byte1]: 28
8564 13:57:19.094073
8565 13:57:19.094627 Set Vref, RX VrefLevel [Byte0]: 29
8566 13:57:19.097140 [Byte1]: 29
8567 13:57:19.101423
8568 13:57:19.101985 Set Vref, RX VrefLevel [Byte0]: 30
8569 13:57:19.104732 [Byte1]: 30
8570 13:57:19.109094
8571 13:57:19.109605 Set Vref, RX VrefLevel [Byte0]: 31
8572 13:57:19.111857 [Byte1]: 31
8573 13:57:19.116620
8574 13:57:19.117085 Set Vref, RX VrefLevel [Byte0]: 32
8575 13:57:19.119468 [Byte1]: 32
8576 13:57:19.123827
8577 13:57:19.124287 Set Vref, RX VrefLevel [Byte0]: 33
8578 13:57:19.127272 [Byte1]: 33
8579 13:57:19.131616
8580 13:57:19.132074 Set Vref, RX VrefLevel [Byte0]: 34
8581 13:57:19.134786 [Byte1]: 34
8582 13:57:19.139644
8583 13:57:19.140223 Set Vref, RX VrefLevel [Byte0]: 35
8584 13:57:19.142325 [Byte1]: 35
8585 13:57:19.146749
8586 13:57:19.147218 Set Vref, RX VrefLevel [Byte0]: 36
8587 13:57:19.149805 [Byte1]: 36
8588 13:57:19.154298
8589 13:57:19.154833 Set Vref, RX VrefLevel [Byte0]: 37
8590 13:57:19.157834 [Byte1]: 37
8591 13:57:19.161872
8592 13:57:19.162384 Set Vref, RX VrefLevel [Byte0]: 38
8593 13:57:19.165317 [Byte1]: 38
8594 13:57:19.169545
8595 13:57:19.170146 Set Vref, RX VrefLevel [Byte0]: 39
8596 13:57:19.172786 [Byte1]: 39
8597 13:57:19.176911
8598 13:57:19.177490 Set Vref, RX VrefLevel [Byte0]: 40
8599 13:57:19.180007 [Byte1]: 40
8600 13:57:19.184505
8601 13:57:19.184999 Set Vref, RX VrefLevel [Byte0]: 41
8602 13:57:19.188252 [Byte1]: 41
8603 13:57:19.192570
8604 13:57:19.193146 Set Vref, RX VrefLevel [Byte0]: 42
8605 13:57:19.195546 [Byte1]: 42
8606 13:57:19.200131
8607 13:57:19.200697 Set Vref, RX VrefLevel [Byte0]: 43
8608 13:57:19.203282 [Byte1]: 43
8609 13:57:19.207278
8610 13:57:19.207855 Set Vref, RX VrefLevel [Byte0]: 44
8611 13:57:19.210408 [Byte1]: 44
8612 13:57:19.214868
8613 13:57:19.215334 Set Vref, RX VrefLevel [Byte0]: 45
8614 13:57:19.218087 [Byte1]: 45
8615 13:57:19.222847
8616 13:57:19.223450 Set Vref, RX VrefLevel [Byte0]: 46
8617 13:57:19.225789 [Byte1]: 46
8618 13:57:19.230151
8619 13:57:19.230713 Set Vref, RX VrefLevel [Byte0]: 47
8620 13:57:19.233564 [Byte1]: 47
8621 13:57:19.237848
8622 13:57:19.238370 Set Vref, RX VrefLevel [Byte0]: 48
8623 13:57:19.241151 [Byte1]: 48
8624 13:57:19.245637
8625 13:57:19.246273 Set Vref, RX VrefLevel [Byte0]: 49
8626 13:57:19.248485 [Byte1]: 49
8627 13:57:19.252817
8628 13:57:19.253283 Set Vref, RX VrefLevel [Byte0]: 50
8629 13:57:19.256034 [Byte1]: 50
8630 13:57:19.260377
8631 13:57:19.260954 Set Vref, RX VrefLevel [Byte0]: 51
8632 13:57:19.263823 [Byte1]: 51
8633 13:57:19.267964
8634 13:57:19.268532 Set Vref, RX VrefLevel [Byte0]: 52
8635 13:57:19.271616 [Byte1]: 52
8636 13:57:19.275574
8637 13:57:19.276043 Set Vref, RX VrefLevel [Byte0]: 53
8638 13:57:19.278942 [Byte1]: 53
8639 13:57:19.283196
8640 13:57:19.283665 Set Vref, RX VrefLevel [Byte0]: 54
8641 13:57:19.286398 [Byte1]: 54
8642 13:57:19.291020
8643 13:57:19.291582 Set Vref, RX VrefLevel [Byte0]: 55
8644 13:57:19.294018 [Byte1]: 55
8645 13:57:19.298570
8646 13:57:19.299132 Set Vref, RX VrefLevel [Byte0]: 56
8647 13:57:19.301585 [Byte1]: 56
8648 13:57:19.305625
8649 13:57:19.306265 Set Vref, RX VrefLevel [Byte0]: 57
8650 13:57:19.309151 [Byte1]: 57
8651 13:57:19.313521
8652 13:57:19.314133 Set Vref, RX VrefLevel [Byte0]: 58
8653 13:57:19.316836 [Byte1]: 58
8654 13:57:19.321419
8655 13:57:19.322026 Set Vref, RX VrefLevel [Byte0]: 59
8656 13:57:19.324518 [Byte1]: 59
8657 13:57:19.328289
8658 13:57:19.328776 Set Vref, RX VrefLevel [Byte0]: 60
8659 13:57:19.331792 [Byte1]: 60
8660 13:57:19.336398
8661 13:57:19.337134 Set Vref, RX VrefLevel [Byte0]: 61
8662 13:57:19.339370 [Byte1]: 61
8663 13:57:19.344016
8664 13:57:19.344630 Set Vref, RX VrefLevel [Byte0]: 62
8665 13:57:19.347253 [Byte1]: 62
8666 13:57:19.351539
8667 13:57:19.352106 Set Vref, RX VrefLevel [Byte0]: 63
8668 13:57:19.354365 [Byte1]: 63
8669 13:57:19.358644
8670 13:57:19.359103 Set Vref, RX VrefLevel [Byte0]: 64
8671 13:57:19.361934 [Byte1]: 64
8672 13:57:19.366421
8673 13:57:19.366884 Set Vref, RX VrefLevel [Byte0]: 65
8674 13:57:19.369760 [Byte1]: 65
8675 13:57:19.374235
8676 13:57:19.374799 Set Vref, RX VrefLevel [Byte0]: 66
8677 13:57:19.377656 [Byte1]: 66
8678 13:57:19.381797
8679 13:57:19.382683 Set Vref, RX VrefLevel [Byte0]: 67
8680 13:57:19.384739 [Byte1]: 67
8681 13:57:19.389278
8682 13:57:19.389842 Set Vref, RX VrefLevel [Byte0]: 68
8683 13:57:19.392879 [Byte1]: 68
8684 13:57:19.396851
8685 13:57:19.397415 Set Vref, RX VrefLevel [Byte0]: 69
8686 13:57:19.400520 [Byte1]: 69
8687 13:57:19.404500
8688 13:57:19.405060 Set Vref, RX VrefLevel [Byte0]: 70
8689 13:57:19.407947 [Byte1]: 70
8690 13:57:19.411907
8691 13:57:19.412469 Set Vref, RX VrefLevel [Byte0]: 71
8692 13:57:19.415214 [Byte1]: 71
8693 13:57:19.419380
8694 13:57:19.419942 Set Vref, RX VrefLevel [Byte0]: 72
8695 13:57:19.422683 [Byte1]: 72
8696 13:57:19.427056
8697 13:57:19.427518 Set Vref, RX VrefLevel [Byte0]: 73
8698 13:57:19.430174 [Byte1]: 73
8699 13:57:19.434859
8700 13:57:19.435420 Set Vref, RX VrefLevel [Byte0]: 74
8701 13:57:19.438063 [Byte1]: 74
8702 13:57:19.442162
8703 13:57:19.442748 Set Vref, RX VrefLevel [Byte0]: 75
8704 13:57:19.445268 [Byte1]: 75
8705 13:57:19.449486
8706 13:57:19.449986 Final RX Vref Byte 0 = 53 to rank0
8707 13:57:19.452950 Final RX Vref Byte 1 = 60 to rank0
8708 13:57:19.456093 Final RX Vref Byte 0 = 53 to rank1
8709 13:57:19.459592 Final RX Vref Byte 1 = 60 to rank1==
8710 13:57:19.462838 Dram Type= 6, Freq= 0, CH_1, rank 0
8711 13:57:19.469781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8712 13:57:19.470412 ==
8713 13:57:19.470791 DQS Delay:
8714 13:57:19.471211 DQS0 = 0, DQS1 = 0
8715 13:57:19.472996 DQM Delay:
8716 13:57:19.473463 DQM0 = 133, DQM1 = 129
8717 13:57:19.476167 DQ Delay:
8718 13:57:19.479842 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8719 13:57:19.482787 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8720 13:57:19.486239 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8721 13:57:19.489672 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8722 13:57:19.490298
8723 13:57:19.490676
8724 13:57:19.491016
8725 13:57:19.492785 [DramC_TX_OE_Calibration] TA2
8726 13:57:19.496714 Original DQ_B0 (3 6) =30, OEN = 27
8727 13:57:19.499911 Original DQ_B1 (3 6) =30, OEN = 27
8728 13:57:19.503067 24, 0x0, End_B0=24 End_B1=24
8729 13:57:19.503637 25, 0x0, End_B0=25 End_B1=25
8730 13:57:19.506111 26, 0x0, End_B0=26 End_B1=26
8731 13:57:19.509314 27, 0x0, End_B0=27 End_B1=27
8732 13:57:19.512631 28, 0x0, End_B0=28 End_B1=28
8733 13:57:19.516019 29, 0x0, End_B0=29 End_B1=29
8734 13:57:19.516491 30, 0x0, End_B0=30 End_B1=30
8735 13:57:19.519981 31, 0x4545, End_B0=30 End_B1=30
8736 13:57:19.522794 Byte0 end_step=30 best_step=27
8737 13:57:19.526181 Byte1 end_step=30 best_step=27
8738 13:57:19.529362 Byte0 TX OE(2T, 0.5T) = (3, 3)
8739 13:57:19.533019 Byte1 TX OE(2T, 0.5T) = (3, 3)
8740 13:57:19.533589
8741 13:57:19.534125
8742 13:57:19.539302 [DQSOSCAuto] RK0, (LSB)MR18= 0x1625, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8743 13:57:19.542862 CH1 RK0: MR19=303, MR18=1625
8744 13:57:19.549087 CH1_RK0: MR19=0x303, MR18=0x1625, DQSOSC=391, MR23=63, INC=24, DEC=16
8745 13:57:19.549555
8746 13:57:19.553269 ----->DramcWriteLeveling(PI) begin...
8747 13:57:19.553902 ==
8748 13:57:19.556009 Dram Type= 6, Freq= 0, CH_1, rank 1
8749 13:57:19.559583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 13:57:19.560191 ==
8751 13:57:19.562818 Write leveling (Byte 0): 26 => 26
8752 13:57:19.566226 Write leveling (Byte 1): 28 => 28
8753 13:57:19.569141 DramcWriteLeveling(PI) end<-----
8754 13:57:19.569727
8755 13:57:19.570155 ==
8756 13:57:19.572442 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 13:57:19.575667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 13:57:19.576131 ==
8759 13:57:19.578907 [Gating] SW mode calibration
8760 13:57:19.586066 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8761 13:57:19.592757 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8762 13:57:19.595772 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 13:57:19.599373 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
8764 13:57:19.606277 1 4 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
8765 13:57:19.608917 1 4 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8766 13:57:19.612399 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8767 13:57:19.619204 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 13:57:19.622646 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 13:57:19.625659 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 13:57:19.632363 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 13:57:19.635404 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8772 13:57:19.639143 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 0)
8773 13:57:19.645739 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8774 13:57:19.649040 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 13:57:19.652225 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 13:57:19.659186 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 13:57:19.662244 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 13:57:19.665617 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 13:57:19.672705 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 13:57:19.675980 1 6 8 | B1->B0 | 4444 2a2a | 0 0 | (0 0) (0 0)
8781 13:57:19.679203 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
8782 13:57:19.685570 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 13:57:19.689077 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 13:57:19.692203 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 13:57:19.699220 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 13:57:19.702306 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 13:57:19.705924 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 13:57:19.709047 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8789 13:57:19.715814 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8790 13:57:19.718874 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 13:57:19.722619 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 13:57:19.728958 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 13:57:19.732462 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 13:57:19.735691 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 13:57:19.742517 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 13:57:19.745535 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 13:57:19.748599 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 13:57:19.755380 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 13:57:19.758652 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 13:57:19.762396 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 13:57:19.769133 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 13:57:19.771760 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 13:57:19.775470 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 13:57:19.781924 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8805 13:57:19.785246 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8806 13:57:19.788512 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 13:57:19.791522 Total UI for P1: 0, mck2ui 16
8808 13:57:19.795377 best dqsien dly found for B0: ( 1, 9, 10)
8809 13:57:19.798654 Total UI for P1: 0, mck2ui 16
8810 13:57:19.802078 best dqsien dly found for B1: ( 1, 9, 10)
8811 13:57:19.805304 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8812 13:57:19.808226 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8813 13:57:19.808708
8814 13:57:19.814897 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8815 13:57:19.818891 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8816 13:57:19.821907 [Gating] SW calibration Done
8817 13:57:19.822517 ==
8818 13:57:19.824957 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 13:57:19.828476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 13:57:19.829061 ==
8821 13:57:19.829550 RX Vref Scan: 0
8822 13:57:19.830049
8823 13:57:19.831919 RX Vref 0 -> 0, step: 1
8824 13:57:19.832499
8825 13:57:19.835348 RX Delay 0 -> 252, step: 8
8826 13:57:19.838655 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8827 13:57:19.841794 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8828 13:57:19.844965 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8829 13:57:19.851499 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8830 13:57:19.854859 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8831 13:57:19.857919 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8832 13:57:19.861740 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8833 13:57:19.864903 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8834 13:57:19.871585 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8835 13:57:19.874516 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8836 13:57:19.878034 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8837 13:57:19.882023 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8838 13:57:19.884691 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8839 13:57:19.891567 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8840 13:57:19.894762 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8841 13:57:19.897896 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8842 13:57:19.898413 ==
8843 13:57:19.901680 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 13:57:19.904999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 13:57:19.905581 ==
8846 13:57:19.908046 DQS Delay:
8847 13:57:19.908545 DQS0 = 0, DQS1 = 0
8848 13:57:19.911483 DQM Delay:
8849 13:57:19.912089 DQM0 = 137, DQM1 = 132
8850 13:57:19.912478 DQ Delay:
8851 13:57:19.918142 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8852 13:57:19.921589 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8853 13:57:19.924573 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8854 13:57:19.928409 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8855 13:57:19.928990
8856 13:57:19.929368
8857 13:57:19.929712 ==
8858 13:57:19.931719 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 13:57:19.934616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 13:57:19.935089 ==
8861 13:57:19.935463
8862 13:57:19.935809
8863 13:57:19.938112 TX Vref Scan disable
8864 13:57:19.941531 == TX Byte 0 ==
8865 13:57:19.945183 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8866 13:57:19.947949 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8867 13:57:19.951225 == TX Byte 1 ==
8868 13:57:19.954761 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8869 13:57:19.958103 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8870 13:57:19.958682 ==
8871 13:57:19.961480 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 13:57:19.964658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 13:57:19.968043 ==
8874 13:57:19.979318
8875 13:57:19.982926 TX Vref early break, caculate TX vref
8876 13:57:19.985625 TX Vref=16, minBit 10, minWin=22, winSum=386
8877 13:57:19.989090 TX Vref=18, minBit 9, minWin=23, winSum=391
8878 13:57:19.992691 TX Vref=20, minBit 8, minWin=24, winSum=402
8879 13:57:19.995686 TX Vref=22, minBit 12, minWin=24, winSum=411
8880 13:57:19.998794 TX Vref=24, minBit 10, minWin=24, winSum=414
8881 13:57:20.005573 TX Vref=26, minBit 1, minWin=25, winSum=417
8882 13:57:20.008769 TX Vref=28, minBit 15, minWin=24, winSum=413
8883 13:57:20.011951 TX Vref=30, minBit 8, minWin=24, winSum=406
8884 13:57:20.015203 TX Vref=32, minBit 8, minWin=24, winSum=402
8885 13:57:20.018578 TX Vref=34, minBit 8, minWin=23, winSum=392
8886 13:57:20.025441 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 26
8887 13:57:20.025914
8888 13:57:20.028474 Final TX Range 0 Vref 26
8889 13:57:20.028945
8890 13:57:20.029318 ==
8891 13:57:20.031963 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 13:57:20.035671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 13:57:20.036249 ==
8894 13:57:20.036630
8895 13:57:20.036976
8896 13:57:20.038561 TX Vref Scan disable
8897 13:57:20.045700 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8898 13:57:20.046328 == TX Byte 0 ==
8899 13:57:20.048556 u2DelayCellOfst[0]=16 cells (5 PI)
8900 13:57:20.052021 u2DelayCellOfst[1]=10 cells (3 PI)
8901 13:57:20.054990 u2DelayCellOfst[2]=0 cells (0 PI)
8902 13:57:20.058649 u2DelayCellOfst[3]=6 cells (2 PI)
8903 13:57:20.062048 u2DelayCellOfst[4]=6 cells (2 PI)
8904 13:57:20.065347 u2DelayCellOfst[5]=20 cells (6 PI)
8905 13:57:20.068372 u2DelayCellOfst[6]=20 cells (6 PI)
8906 13:57:20.071832 u2DelayCellOfst[7]=6 cells (2 PI)
8907 13:57:20.074764 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8908 13:57:20.078406 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8909 13:57:20.081827 == TX Byte 1 ==
8910 13:57:20.082440 u2DelayCellOfst[8]=0 cells (0 PI)
8911 13:57:20.084900 u2DelayCellOfst[9]=3 cells (1 PI)
8912 13:57:20.088349 u2DelayCellOfst[10]=10 cells (3 PI)
8913 13:57:20.091890 u2DelayCellOfst[11]=3 cells (1 PI)
8914 13:57:20.095042 u2DelayCellOfst[12]=16 cells (5 PI)
8915 13:57:20.098405 u2DelayCellOfst[13]=16 cells (5 PI)
8916 13:57:20.101989 u2DelayCellOfst[14]=20 cells (6 PI)
8917 13:57:20.105114 u2DelayCellOfst[15]=20 cells (6 PI)
8918 13:57:20.108280 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8919 13:57:20.114762 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 13:57:20.115327 DramC Write-DBI on
8921 13:57:20.115704 ==
8922 13:57:20.118138 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 13:57:20.124764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 13:57:20.125361 ==
8925 13:57:20.125763
8926 13:57:20.126169
8927 13:57:20.126507 TX Vref Scan disable
8928 13:57:20.128282 == TX Byte 0 ==
8929 13:57:20.132030 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8930 13:57:20.134818 == TX Byte 1 ==
8931 13:57:20.138283 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8932 13:57:20.141770 DramC Write-DBI off
8933 13:57:20.142388
8934 13:57:20.142766 [DATLAT]
8935 13:57:20.143117 Freq=1600, CH1 RK1
8936 13:57:20.143451
8937 13:57:20.145108 DATLAT Default: 0xf
8938 13:57:20.145576 0, 0xFFFF, sum = 0
8939 13:57:20.148608 1, 0xFFFF, sum = 0
8940 13:57:20.149091 2, 0xFFFF, sum = 0
8941 13:57:20.151757 3, 0xFFFF, sum = 0
8942 13:57:20.154957 4, 0xFFFF, sum = 0
8943 13:57:20.155439 5, 0xFFFF, sum = 0
8944 13:57:20.158024 6, 0xFFFF, sum = 0
8945 13:57:20.158505 7, 0xFFFF, sum = 0
8946 13:57:20.161625 8, 0xFFFF, sum = 0
8947 13:57:20.162130 9, 0xFFFF, sum = 0
8948 13:57:20.164765 10, 0xFFFF, sum = 0
8949 13:57:20.165218 11, 0xFFFF, sum = 0
8950 13:57:20.168575 12, 0xFFFF, sum = 0
8951 13:57:20.169009 13, 0xFFFF, sum = 0
8952 13:57:20.171450 14, 0x0, sum = 1
8953 13:57:20.171926 15, 0x0, sum = 2
8954 13:57:20.174776 16, 0x0, sum = 3
8955 13:57:20.175211 17, 0x0, sum = 4
8956 13:57:20.178402 best_step = 15
8957 13:57:20.178826
8958 13:57:20.179165 ==
8959 13:57:20.181660 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 13:57:20.185100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 13:57:20.185641 ==
8962 13:57:20.186005 RX Vref Scan: 0
8963 13:57:20.186324
8964 13:57:20.188434 RX Vref 0 -> 0, step: 1
8965 13:57:20.188972
8966 13:57:20.192036 RX Delay 19 -> 252, step: 4
8967 13:57:20.195144 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8968 13:57:20.202014 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
8969 13:57:20.205079 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8970 13:57:20.208281 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8971 13:57:20.211434 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8972 13:57:20.215298 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8973 13:57:20.218405 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8974 13:57:20.224876 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
8975 13:57:20.228338 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8976 13:57:20.231409 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8977 13:57:20.234934 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8978 13:57:20.238412 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8979 13:57:20.245120 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8980 13:57:20.248149 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8981 13:57:20.251142 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8982 13:57:20.254569 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8983 13:57:20.255109 ==
8984 13:57:20.258284 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 13:57:20.264575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 13:57:20.265121 ==
8987 13:57:20.265471 DQS Delay:
8988 13:57:20.268004 DQS0 = 0, DQS1 = 0
8989 13:57:20.268429 DQM Delay:
8990 13:57:20.268767 DQM0 = 134, DQM1 = 130
8991 13:57:20.271255 DQ Delay:
8992 13:57:20.274850 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
8993 13:57:20.278063 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
8994 13:57:20.280798 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8995 13:57:20.284265 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8996 13:57:20.284690
8997 13:57:20.285028
8998 13:57:20.285338
8999 13:57:20.287493 [DramC_TX_OE_Calibration] TA2
9000 13:57:20.291515 Original DQ_B0 (3 6) =30, OEN = 27
9001 13:57:20.294757 Original DQ_B1 (3 6) =30, OEN = 27
9002 13:57:20.297925 24, 0x0, End_B0=24 End_B1=24
9003 13:57:20.298503 25, 0x0, End_B0=25 End_B1=25
9004 13:57:20.301373 26, 0x0, End_B0=26 End_B1=26
9005 13:57:20.304634 27, 0x0, End_B0=27 End_B1=27
9006 13:57:20.307837 28, 0x0, End_B0=28 End_B1=28
9007 13:57:20.310786 29, 0x0, End_B0=29 End_B1=29
9008 13:57:20.311288 30, 0x0, End_B0=30 End_B1=30
9009 13:57:20.314402 31, 0x5151, End_B0=30 End_B1=30
9010 13:57:20.317553 Byte0 end_step=30 best_step=27
9011 13:57:20.321012 Byte1 end_step=30 best_step=27
9012 13:57:20.324338 Byte0 TX OE(2T, 0.5T) = (3, 3)
9013 13:57:20.327250 Byte1 TX OE(2T, 0.5T) = (3, 3)
9014 13:57:20.327683
9015 13:57:20.328023
9016 13:57:20.334203 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9017 13:57:20.337403 CH1 RK1: MR19=303, MR18=1B05
9018 13:57:20.344051 CH1_RK1: MR19=0x303, MR18=0x1B05, DQSOSC=396, MR23=63, INC=23, DEC=15
9019 13:57:20.347625 [RxdqsGatingPostProcess] freq 1600
9020 13:57:20.350755 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9021 13:57:20.354055 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 13:57:20.357157 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 13:57:20.360745 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 13:57:20.363978 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 13:57:20.367310 best DQS0 dly(2T, 0.5T) = (1, 1)
9026 13:57:20.370445 best DQS1 dly(2T, 0.5T) = (1, 1)
9027 13:57:20.374279 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9028 13:57:20.377556 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9029 13:57:20.380573 Pre-setting of DQS Precalculation
9030 13:57:20.384006 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9031 13:57:20.390818 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9032 13:57:20.400835 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9033 13:57:20.401372
9034 13:57:20.401754
9035 13:57:20.402118 [Calibration Summary] 3200 Mbps
9036 13:57:20.404160 CH 0, Rank 0
9037 13:57:20.404725 SW Impedance : PASS
9038 13:57:20.407469 DUTY Scan : NO K
9039 13:57:20.410643 ZQ Calibration : PASS
9040 13:57:20.411076 Jitter Meter : NO K
9041 13:57:20.414002 CBT Training : PASS
9042 13:57:20.417024 Write leveling : PASS
9043 13:57:20.417557 RX DQS gating : PASS
9044 13:57:20.420819 RX DQ/DQS(RDDQC) : PASS
9045 13:57:20.423964 TX DQ/DQS : PASS
9046 13:57:20.424499 RX DATLAT : PASS
9047 13:57:20.427239 RX DQ/DQS(Engine): PASS
9048 13:57:20.430896 TX OE : PASS
9049 13:57:20.431451 All Pass.
9050 13:57:20.431836
9051 13:57:20.432154 CH 0, Rank 1
9052 13:57:20.434009 SW Impedance : PASS
9053 13:57:20.437259 DUTY Scan : NO K
9054 13:57:20.437826 ZQ Calibration : PASS
9055 13:57:20.440512 Jitter Meter : NO K
9056 13:57:20.443659 CBT Training : PASS
9057 13:57:20.444216 Write leveling : PASS
9058 13:57:20.447364 RX DQS gating : PASS
9059 13:57:20.450152 RX DQ/DQS(RDDQC) : PASS
9060 13:57:20.450584 TX DQ/DQS : PASS
9061 13:57:20.453560 RX DATLAT : PASS
9062 13:57:20.454025 RX DQ/DQS(Engine): PASS
9063 13:57:20.457381 TX OE : PASS
9064 13:57:20.457863 All Pass.
9065 13:57:20.458241
9066 13:57:20.460641 CH 1, Rank 0
9067 13:57:20.461171 SW Impedance : PASS
9068 13:57:20.463949 DUTY Scan : NO K
9069 13:57:20.467075 ZQ Calibration : PASS
9070 13:57:20.467613 Jitter Meter : NO K
9071 13:57:20.470239 CBT Training : PASS
9072 13:57:20.473907 Write leveling : PASS
9073 13:57:20.474481 RX DQS gating : PASS
9074 13:57:20.477186 RX DQ/DQS(RDDQC) : PASS
9075 13:57:20.480094 TX DQ/DQS : PASS
9076 13:57:20.480531 RX DATLAT : PASS
9077 13:57:20.483639 RX DQ/DQS(Engine): PASS
9078 13:57:20.487260 TX OE : PASS
9079 13:57:20.487796 All Pass.
9080 13:57:20.488139
9081 13:57:20.488456 CH 1, Rank 1
9082 13:57:20.490381 SW Impedance : PASS
9083 13:57:20.493979 DUTY Scan : NO K
9084 13:57:20.494524 ZQ Calibration : PASS
9085 13:57:20.497341 Jitter Meter : NO K
9086 13:57:20.500404 CBT Training : PASS
9087 13:57:20.500940 Write leveling : PASS
9088 13:57:20.503388 RX DQS gating : PASS
9089 13:57:20.503814 RX DQ/DQS(RDDQC) : PASS
9090 13:57:20.506723 TX DQ/DQS : PASS
9091 13:57:20.510305 RX DATLAT : PASS
9092 13:57:20.510839 RX DQ/DQS(Engine): PASS
9093 13:57:20.513627 TX OE : PASS
9094 13:57:20.514091 All Pass.
9095 13:57:20.514439
9096 13:57:20.517147 DramC Write-DBI on
9097 13:57:20.520352 PER_BANK_REFRESH: Hybrid Mode
9098 13:57:20.520907 TX_TRACKING: ON
9099 13:57:20.530432 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9100 13:57:20.536858 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9101 13:57:20.543704 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 13:57:20.550012 [FAST_K] Save calibration result to emmc
9103 13:57:20.550528 sync common calibartion params.
9104 13:57:20.553220 sync cbt_mode0:1, 1:1
9105 13:57:20.556838 dram_init: ddr_geometry: 2
9106 13:57:20.557372 dram_init: ddr_geometry: 2
9107 13:57:20.560132 dram_init: ddr_geometry: 2
9108 13:57:20.563362 0:dram_rank_size:100000000
9109 13:57:20.566794 1:dram_rank_size:100000000
9110 13:57:20.569728 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9111 13:57:20.573454 DFS_SHUFFLE_HW_MODE: ON
9112 13:57:20.576765 dramc_set_vcore_voltage set vcore to 725000
9113 13:57:20.580180 Read voltage for 1600, 0
9114 13:57:20.580718 Vio18 = 0
9115 13:57:20.583342 Vcore = 725000
9116 13:57:20.583882 Vdram = 0
9117 13:57:20.584231 Vddq = 0
9118 13:57:20.584552 Vmddr = 0
9119 13:57:20.586256 switch to 3200 Mbps bootup
9120 13:57:20.589916 [DramcRunTimeConfig]
9121 13:57:20.590361 PHYPLL
9122 13:57:20.590701 DPM_CONTROL_AFTERK: ON
9123 13:57:20.593285 PER_BANK_REFRESH: ON
9124 13:57:20.596632 REFRESH_OVERHEAD_REDUCTION: ON
9125 13:57:20.599995 CMD_PICG_NEW_MODE: OFF
9126 13:57:20.600531 XRTWTW_NEW_MODE: ON
9127 13:57:20.603217 XRTRTR_NEW_MODE: ON
9128 13:57:20.603756 TX_TRACKING: ON
9129 13:57:20.606364 RDSEL_TRACKING: OFF
9130 13:57:20.606790 DQS Precalculation for DVFS: ON
9131 13:57:20.609708 RX_TRACKING: OFF
9132 13:57:20.610281 HW_GATING DBG: ON
9133 13:57:20.612701 ZQCS_ENABLE_LP4: ON
9134 13:57:20.616540 RX_PICG_NEW_MODE: ON
9135 13:57:20.617076 TX_PICG_NEW_MODE: ON
9136 13:57:20.619627 ENABLE_RX_DCM_DPHY: ON
9137 13:57:20.623216 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9138 13:57:20.623748 DUMMY_READ_FOR_TRACKING: OFF
9139 13:57:20.626347 !!! SPM_CONTROL_AFTERK: OFF
9140 13:57:20.630197 !!! SPM could not control APHY
9141 13:57:20.633163 IMPEDANCE_TRACKING: ON
9142 13:57:20.633700 TEMP_SENSOR: ON
9143 13:57:20.636595 HW_SAVE_FOR_SR: OFF
9144 13:57:20.637130 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9145 13:57:20.642878 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9146 13:57:20.643413 Read ODT Tracking: ON
9147 13:57:20.646306 Refresh Rate DeBounce: ON
9148 13:57:20.649873 DFS_NO_QUEUE_FLUSH: ON
9149 13:57:20.652986 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9150 13:57:20.653414 ENABLE_DFS_RUNTIME_MRW: OFF
9151 13:57:20.656141 DDR_RESERVE_NEW_MODE: ON
9152 13:57:20.659413 MR_CBT_SWITCH_FREQ: ON
9153 13:57:20.659858 =========================
9154 13:57:20.678939 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9155 13:57:20.682535 dram_init: ddr_geometry: 2
9156 13:57:20.701032 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9157 13:57:20.703942 dram_init: dram init end (result: 0)
9158 13:57:20.710941 DRAM-K: Full calibration passed in 24520 msecs
9159 13:57:20.714066 MRC: failed to locate region type 0.
9160 13:57:20.714539 DRAM rank0 size:0x100000000,
9161 13:57:20.717535 DRAM rank1 size=0x100000000
9162 13:57:20.727605 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9163 13:57:20.734354 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9164 13:57:20.740744 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9165 13:57:20.747632 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9166 13:57:20.750395 DRAM rank0 size:0x100000000,
9167 13:57:20.753883 DRAM rank1 size=0x100000000
9168 13:57:20.754491 CBMEM:
9169 13:57:20.757234 IMD: root @ 0xfffff000 254 entries.
9170 13:57:20.760642 IMD: root @ 0xffffec00 62 entries.
9171 13:57:20.763999 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9172 13:57:20.766791 WARNING: RO_VPD is uninitialized or empty.
9173 13:57:20.773502 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9174 13:57:20.780464 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9175 13:57:20.793736 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9176 13:57:20.805006 BS: romstage times (exec / console): total (unknown) / 24017 ms
9177 13:57:20.805579
9178 13:57:20.805988
9179 13:57:20.815081 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9180 13:57:20.818536 ARM64: Exception handlers installed.
9181 13:57:20.821582 ARM64: Testing exception
9182 13:57:20.825104 ARM64: Done test exception
9183 13:57:20.825674 Enumerating buses...
9184 13:57:20.828042 Show all devs... Before device enumeration.
9185 13:57:20.831441 Root Device: enabled 1
9186 13:57:20.834926 CPU_CLUSTER: 0: enabled 1
9187 13:57:20.835469 CPU: 00: enabled 1
9188 13:57:20.837991 Compare with tree...
9189 13:57:20.838465 Root Device: enabled 1
9190 13:57:20.841149 CPU_CLUSTER: 0: enabled 1
9191 13:57:20.844747 CPU: 00: enabled 1
9192 13:57:20.845319 Root Device scanning...
9193 13:57:20.848004 scan_static_bus for Root Device
9194 13:57:20.851460 CPU_CLUSTER: 0 enabled
9195 13:57:20.854756 scan_static_bus for Root Device done
9196 13:57:20.858317 scan_bus: bus Root Device finished in 8 msecs
9197 13:57:20.858886 done
9198 13:57:20.864981 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9199 13:57:20.868106 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9200 13:57:20.874538 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9201 13:57:20.878066 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9202 13:57:20.881192 Allocating resources...
9203 13:57:20.885209 Reading resources...
9204 13:57:20.887824 Root Device read_resources bus 0 link: 0
9205 13:57:20.888342 DRAM rank0 size:0x100000000,
9206 13:57:20.891061 DRAM rank1 size=0x100000000
9207 13:57:20.894834 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9208 13:57:20.897712 CPU: 00 missing read_resources
9209 13:57:20.901422 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9210 13:57:20.907999 Root Device read_resources bus 0 link: 0 done
9211 13:57:20.908572 Done reading resources.
9212 13:57:20.914661 Show resources in subtree (Root Device)...After reading.
9213 13:57:20.917839 Root Device child on link 0 CPU_CLUSTER: 0
9214 13:57:20.921256 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 13:57:20.930930 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 13:57:20.931513 CPU: 00
9217 13:57:20.934330 Root Device assign_resources, bus 0 link: 0
9218 13:57:20.937734 CPU_CLUSTER: 0 missing set_resources
9219 13:57:20.944432 Root Device assign_resources, bus 0 link: 0 done
9220 13:57:20.945011 Done setting resources.
9221 13:57:20.951192 Show resources in subtree (Root Device)...After assigning values.
9222 13:57:20.954320 Root Device child on link 0 CPU_CLUSTER: 0
9223 13:57:20.957450 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 13:57:20.967588 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 13:57:20.968175 CPU: 00
9226 13:57:20.970536 Done allocating resources.
9227 13:57:20.973821 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9228 13:57:20.977764 Enabling resources...
9229 13:57:20.978374 done.
9230 13:57:20.984125 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9231 13:57:20.984710 Initializing devices...
9232 13:57:20.987045 Root Device init
9233 13:57:20.987518 init hardware done!
9234 13:57:20.991034 0x00000018: ctrlr->caps
9235 13:57:20.994063 52.000 MHz: ctrlr->f_max
9236 13:57:20.994552 0.400 MHz: ctrlr->f_min
9237 13:57:20.997427 0x40ff8080: ctrlr->voltages
9238 13:57:20.997906 sclk: 390625
9239 13:57:21.000761 Bus Width = 1
9240 13:57:21.001228 sclk: 390625
9241 13:57:21.004427 Bus Width = 1
9242 13:57:21.005006 Early init status = 3
9243 13:57:21.010466 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9244 13:57:21.014118 in-header: 03 fc 00 00 01 00 00 00
9245 13:57:21.014690 in-data: 00
9246 13:57:21.020789 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9247 13:57:21.024083 in-header: 03 fd 00 00 00 00 00 00
9248 13:57:21.027369 in-data:
9249 13:57:21.030412 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9250 13:57:21.033573 in-header: 03 fc 00 00 01 00 00 00
9251 13:57:21.037557 in-data: 00
9252 13:57:21.040548 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9253 13:57:21.044807 in-header: 03 fd 00 00 00 00 00 00
9254 13:57:21.048484 in-data:
9255 13:57:21.051498 [SSUSB] Setting up USB HOST controller...
9256 13:57:21.054856 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9257 13:57:21.058390 [SSUSB] phy power-on done.
9258 13:57:21.061479 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9259 13:57:21.068273 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9260 13:57:21.071477 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9261 13:57:21.078199 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9262 13:57:21.084682 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9263 13:57:21.091593 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9264 13:57:21.098411 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9265 13:57:21.104960 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9266 13:57:21.108062 SPM: binary array size = 0x9dc
9267 13:57:21.111359 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9268 13:57:21.118057 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9269 13:57:21.124946 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9270 13:57:21.128052 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9271 13:57:21.134708 configure_display: Starting display init
9272 13:57:21.168113 anx7625_power_on_init: Init interface.
9273 13:57:21.171666 anx7625_disable_pd_protocol: Disabled PD feature.
9274 13:57:21.175151 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9275 13:57:21.202837 anx7625_start_dp_work: Secure OCM version=00
9276 13:57:21.206099 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9277 13:57:21.220801 sp_tx_get_edid_block: EDID Block = 1
9278 13:57:21.323147 Extracted contents:
9279 13:57:21.326849 header: 00 ff ff ff ff ff ff 00
9280 13:57:21.329975 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9281 13:57:21.333455 version: 01 04
9282 13:57:21.336954 basic params: 95 1f 11 78 0a
9283 13:57:21.340102 chroma info: 76 90 94 55 54 90 27 21 50 54
9284 13:57:21.343299 established: 00 00 00
9285 13:57:21.350234 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9286 13:57:21.353145 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9287 13:57:21.360196 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9288 13:57:21.366835 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9289 13:57:21.372984 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9290 13:57:21.376462 extensions: 00
9291 13:57:21.377027 checksum: fb
9292 13:57:21.377400
9293 13:57:21.379601 Manufacturer: IVO Model 57d Serial Number 0
9294 13:57:21.383049 Made week 0 of 2020
9295 13:57:21.383527 EDID version: 1.4
9296 13:57:21.386220 Digital display
9297 13:57:21.389495 6 bits per primary color channel
9298 13:57:21.389995 DisplayPort interface
9299 13:57:21.392642 Maximum image size: 31 cm x 17 cm
9300 13:57:21.396062 Gamma: 220%
9301 13:57:21.396521 Check DPMS levels
9302 13:57:21.399167 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9303 13:57:21.402821 First detailed timing is preferred timing
9304 13:57:21.405809 Established timings supported:
9305 13:57:21.410049 Standard timings supported:
9306 13:57:21.412969 Detailed timings
9307 13:57:21.416195 Hex of detail: 383680a07038204018303c0035ae10000019
9308 13:57:21.419546 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9309 13:57:21.425914 0780 0798 07c8 0820 hborder 0
9310 13:57:21.428951 0438 043b 0447 0458 vborder 0
9311 13:57:21.432512 -hsync -vsync
9312 13:57:21.433088 Did detailed timing
9313 13:57:21.439177 Hex of detail: 000000000000000000000000000000000000
9314 13:57:21.439733 Manufacturer-specified data, tag 0
9315 13:57:21.445653 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9316 13:57:21.448968 ASCII string: InfoVision
9317 13:57:21.452238 Hex of detail: 000000fe00523134304e574635205248200a
9318 13:57:21.455706 ASCII string: R140NWF5 RH
9319 13:57:21.456164 Checksum
9320 13:57:21.458892 Checksum: 0xfb (valid)
9321 13:57:21.462476 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9322 13:57:21.465712 DSI data_rate: 832800000 bps
9323 13:57:21.472542 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9324 13:57:21.475702 anx7625_parse_edid: pixelclock(138800).
9325 13:57:21.478888 hactive(1920), hsync(48), hfp(24), hbp(88)
9326 13:57:21.482377 vactive(1080), vsync(12), vfp(3), vbp(17)
9327 13:57:21.485581 anx7625_dsi_config: config dsi.
9328 13:57:21.492461 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9329 13:57:21.506023 anx7625_dsi_config: success to config DSI
9330 13:57:21.508932 anx7625_dp_start: MIPI phy setup OK.
9331 13:57:21.511990 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9332 13:57:21.515360 mtk_ddp_mode_set invalid vrefresh 60
9333 13:57:21.518441 main_disp_path_setup
9334 13:57:21.518901 ovl_layer_smi_id_en
9335 13:57:21.521988 ovl_layer_smi_id_en
9336 13:57:21.522562 ccorr_config
9337 13:57:21.522953 aal_config
9338 13:57:21.525478 gamma_config
9339 13:57:21.526096 postmask_config
9340 13:57:21.528204 dither_config
9341 13:57:21.531583 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9342 13:57:21.537984 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9343 13:57:21.541912 Root Device init finished in 551 msecs
9344 13:57:21.544745 CPU_CLUSTER: 0 init
9345 13:57:21.551220 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9346 13:57:21.558382 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9347 13:57:21.558936 APU_MBOX 0x190000b0 = 0x10001
9348 13:57:21.561825 APU_MBOX 0x190001b0 = 0x10001
9349 13:57:21.564599 APU_MBOX 0x190005b0 = 0x10001
9350 13:57:21.567799 APU_MBOX 0x190006b0 = 0x10001
9351 13:57:21.574611 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9352 13:57:21.584081 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9353 13:57:21.597303 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9354 13:57:21.603550 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9355 13:57:21.615301 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9356 13:57:21.624357 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9357 13:57:21.627640 CPU_CLUSTER: 0 init finished in 81 msecs
9358 13:57:21.630968 Devices initialized
9359 13:57:21.634037 Show all devs... After init.
9360 13:57:21.634526 Root Device: enabled 1
9361 13:57:21.637143 CPU_CLUSTER: 0: enabled 1
9362 13:57:21.640762 CPU: 00: enabled 1
9363 13:57:21.643958 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9364 13:57:21.646906 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9365 13:57:21.650315 ELOG: NV offset 0x57f000 size 0x1000
9366 13:57:21.657168 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9367 13:57:21.664043 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9368 13:57:21.667210 ELOG: Event(17) added with size 13 at 2024-02-01 13:56:41 UTC
9369 13:57:21.670632 out: cmd=0x121: 03 db 21 01 00 00 00 00
9370 13:57:21.675016 in-header: 03 20 00 00 2c 00 00 00
9371 13:57:21.688447 in-data: 3f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9372 13:57:21.695077 ELOG: Event(A1) added with size 10 at 2024-02-01 13:56:41 UTC
9373 13:57:21.702046 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9374 13:57:21.708435 ELOG: Event(A0) added with size 9 at 2024-02-01 13:56:41 UTC
9375 13:57:21.711636 elog_add_boot_reason: Logged dev mode boot
9376 13:57:21.714785 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9377 13:57:21.717916 Finalize devices...
9378 13:57:21.718431 Devices finalized
9379 13:57:21.725074 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9380 13:57:21.728250 Writing coreboot table at 0xffe64000
9381 13:57:21.731176 0. 000000000010a000-0000000000113fff: RAMSTAGE
9382 13:57:21.734830 1. 0000000040000000-00000000400fffff: RAM
9383 13:57:21.741302 2. 0000000040100000-000000004032afff: RAMSTAGE
9384 13:57:21.744480 3. 000000004032b000-00000000545fffff: RAM
9385 13:57:21.747950 4. 0000000054600000-000000005465ffff: BL31
9386 13:57:21.751456 5. 0000000054660000-00000000ffe63fff: RAM
9387 13:57:21.758245 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9388 13:57:21.761315 7. 0000000100000000-000000023fffffff: RAM
9389 13:57:21.761790 Passing 5 GPIOs to payload:
9390 13:57:21.768043 NAME | PORT | POLARITY | VALUE
9391 13:57:21.771163 EC in RW | 0x000000aa | low | undefined
9392 13:57:21.778021 EC interrupt | 0x00000005 | low | undefined
9393 13:57:21.781139 TPM interrupt | 0x000000ab | high | undefined
9394 13:57:21.787972 SD card detect | 0x00000011 | high | undefined
9395 13:57:21.791372 speaker enable | 0x00000093 | high | undefined
9396 13:57:21.794776 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9397 13:57:21.798172 in-header: 03 f9 00 00 02 00 00 00
9398 13:57:21.798731 in-data: 02 00
9399 13:57:21.801232 ADC[4]: Raw value=901770 ID=7
9400 13:57:21.804713 ADC[3]: Raw value=213179 ID=1
9401 13:57:21.807908 RAM Code: 0x71
9402 13:57:21.808479 ADC[6]: Raw value=74502 ID=0
9403 13:57:21.810910 ADC[5]: Raw value=212072 ID=1
9404 13:57:21.814462 SKU Code: 0x1
9405 13:57:21.817765 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4f3d
9406 13:57:21.821035 coreboot table: 964 bytes.
9407 13:57:21.824704 IMD ROOT 0. 0xfffff000 0x00001000
9408 13:57:21.827573 IMD SMALL 1. 0xffffe000 0x00001000
9409 13:57:21.830540 RO MCACHE 2. 0xffffc000 0x00001104
9410 13:57:21.834409 CONSOLE 3. 0xfff7c000 0x00080000
9411 13:57:21.837505 FMAP 4. 0xfff7b000 0x00000452
9412 13:57:21.841140 TIME STAMP 5. 0xfff7a000 0x00000910
9413 13:57:21.844498 VBOOT WORK 6. 0xfff66000 0x00014000
9414 13:57:21.847526 RAMOOPS 7. 0xffe66000 0x00100000
9415 13:57:21.850757 COREBOOT 8. 0xffe64000 0x00002000
9416 13:57:21.851346 IMD small region:
9417 13:57:21.854056 IMD ROOT 0. 0xffffec00 0x00000400
9418 13:57:21.857410 VPD 1. 0xffffeb80 0x0000006c
9419 13:57:21.860602 MMC STATUS 2. 0xffffeb60 0x00000004
9420 13:57:21.867110 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9421 13:57:21.870784 Probing TPM: done!
9422 13:57:21.874396 Connected to device vid:did:rid of 1ae0:0028:00
9423 13:57:21.883882 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9424 13:57:21.888168 Initialized TPM device CR50 revision 0
9425 13:57:21.891503 Checking cr50 for pending updates
9426 13:57:21.894857 Reading cr50 TPM mode
9427 13:57:21.903116 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9428 13:57:21.909734 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9429 13:57:21.950217 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9430 13:57:21.953115 Checking segment from ROM address 0x40100000
9431 13:57:21.956825 Checking segment from ROM address 0x4010001c
9432 13:57:21.963238 Loading segment from ROM address 0x40100000
9433 13:57:21.963826 code (compression=0)
9434 13:57:21.973036 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9435 13:57:21.979899 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9436 13:57:21.980370 it's not compressed!
9437 13:57:21.986407 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9438 13:57:21.989768 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9439 13:57:22.010631 Loading segment from ROM address 0x4010001c
9440 13:57:22.011202 Entry Point 0x80000000
9441 13:57:22.013643 Loaded segments
9442 13:57:22.017413 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9443 13:57:22.023945 Jumping to boot code at 0x80000000(0xffe64000)
9444 13:57:22.030360 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9445 13:57:22.037129 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9446 13:57:22.045379 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9447 13:57:22.047982 Checking segment from ROM address 0x40100000
9448 13:57:22.051570 Checking segment from ROM address 0x4010001c
9449 13:57:22.058126 Loading segment from ROM address 0x40100000
9450 13:57:22.058700 code (compression=1)
9451 13:57:22.064769 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9452 13:57:22.074695 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9453 13:57:22.075251 using LZMA
9454 13:57:22.083407 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9455 13:57:22.089711 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9456 13:57:22.093124 Loading segment from ROM address 0x4010001c
9457 13:57:22.093724 Entry Point 0x54601000
9458 13:57:22.096704 Loaded segments
9459 13:57:22.099954 NOTICE: MT8192 bl31_setup
9460 13:57:22.107127 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9461 13:57:22.110448 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9462 13:57:22.113645 WARNING: region 0:
9463 13:57:22.117105 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 13:57:22.117673 WARNING: region 1:
9465 13:57:22.123506 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9466 13:57:22.126519 WARNING: region 2:
9467 13:57:22.130229 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9468 13:57:22.133338 WARNING: region 3:
9469 13:57:22.136998 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 13:57:22.140184 WARNING: region 4:
9471 13:57:22.147138 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9472 13:57:22.147710 WARNING: region 5:
9473 13:57:22.150022 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 13:57:22.153495 WARNING: region 6:
9475 13:57:22.156809 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 13:57:22.159844 WARNING: region 7:
9477 13:57:22.163487 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 13:57:22.169755 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9479 13:57:22.173368 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9480 13:57:22.176658 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9481 13:57:22.183212 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9482 13:57:22.186738 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9483 13:57:22.189815 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9484 13:57:22.196476 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9485 13:57:22.199852 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9486 13:57:22.206562 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9487 13:57:22.210111 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9488 13:57:22.213295 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9489 13:57:22.220038 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9490 13:57:22.223391 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9491 13:57:22.227091 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9492 13:57:22.233597 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9493 13:57:22.236904 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9494 13:57:22.240429 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9495 13:57:22.247018 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9496 13:57:22.250316 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9497 13:57:22.253580 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9498 13:57:22.260621 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9499 13:57:22.263721 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9500 13:57:22.270537 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9501 13:57:22.274102 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9502 13:57:22.277003 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9503 13:57:22.283522 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9504 13:57:22.287071 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9505 13:57:22.293576 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9506 13:57:22.296926 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9507 13:57:22.300147 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9508 13:57:22.306774 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9509 13:57:22.310408 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9510 13:57:22.313632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9511 13:57:22.320198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9512 13:57:22.323871 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9513 13:57:22.327109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9514 13:57:22.330785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9515 13:57:22.337352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9516 13:57:22.340796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9517 13:57:22.343745 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9518 13:57:22.347410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9519 13:57:22.354101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9520 13:57:22.356865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9521 13:57:22.360416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9522 13:57:22.363922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9523 13:57:22.370347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9524 13:57:22.373795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9525 13:57:22.377643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9526 13:57:22.383690 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9527 13:57:22.386858 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9528 13:57:22.390214 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9529 13:57:22.396994 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9530 13:57:22.400623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9531 13:57:22.407036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9532 13:57:22.410408 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9533 13:57:22.417127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9534 13:57:22.420546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9535 13:57:22.423577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9536 13:57:22.430653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9537 13:57:22.433800 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9538 13:57:22.440369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9539 13:57:22.443847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9540 13:57:22.450296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9541 13:57:22.453624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9542 13:57:22.460611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9543 13:57:22.463922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9544 13:57:22.467369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9545 13:57:22.473684 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9546 13:57:22.477237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9547 13:57:22.483608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9548 13:57:22.486773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9549 13:57:22.493554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9550 13:57:22.496697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9551 13:57:22.500445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9552 13:57:22.506705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9553 13:57:22.510032 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9554 13:57:22.516786 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9555 13:57:22.520154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9556 13:57:22.526923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9557 13:57:22.530665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9558 13:57:22.534103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9559 13:57:22.540587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9560 13:57:22.544231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9561 13:57:22.550433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9562 13:57:22.553751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9563 13:57:22.560711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9564 13:57:22.563672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9565 13:57:22.566703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9566 13:57:22.573708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9567 13:57:22.576983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9568 13:57:22.583637 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9569 13:57:22.587121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9570 13:57:22.593967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9571 13:57:22.597226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9572 13:57:22.600337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9573 13:57:22.606995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9574 13:57:22.610388 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9575 13:57:22.613783 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9576 13:57:22.620075 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9577 13:57:22.623205 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9578 13:57:22.626714 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9579 13:57:22.633476 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9580 13:57:22.636805 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9581 13:57:22.640479 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9582 13:57:22.646857 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9583 13:57:22.650176 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9584 13:57:22.657104 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9585 13:57:22.660217 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9586 13:57:22.663296 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9587 13:57:22.670631 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9588 13:57:22.673413 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9589 13:57:22.679949 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9590 13:57:22.683583 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9591 13:57:22.686955 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9592 13:57:22.694310 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9593 13:57:22.697247 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9594 13:57:22.700516 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9595 13:57:22.706900 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9596 13:57:22.710429 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9597 13:57:22.713702 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9598 13:57:22.716968 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9599 13:57:22.723982 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9600 13:57:22.726831 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9601 13:57:22.730421 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9602 13:57:22.737100 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9603 13:57:22.740492 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9604 13:57:22.744015 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9605 13:57:22.750458 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9606 13:57:22.754032 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9607 13:57:22.760360 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9608 13:57:22.763556 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9609 13:57:22.767130 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9610 13:57:22.773893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9611 13:57:22.777330 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9612 13:57:22.780147 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9613 13:57:22.786898 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9614 13:57:22.790798 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9615 13:57:22.797255 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9616 13:57:22.800609 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9617 13:57:22.803807 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9618 13:57:22.810211 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9619 13:57:22.813918 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9620 13:57:22.820266 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9621 13:57:22.823799 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9622 13:57:22.827104 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9623 13:57:22.833595 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9624 13:57:22.837365 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9625 13:57:22.840226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9626 13:57:22.847747 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9627 13:57:22.850688 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9628 13:57:22.857251 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9629 13:57:22.860672 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9630 13:57:22.863886 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9631 13:57:22.870542 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9632 13:57:22.874151 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9633 13:57:22.877286 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9634 13:57:22.883468 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9635 13:57:22.887089 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9636 13:57:22.893622 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9637 13:57:22.897041 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9638 13:57:22.900337 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9639 13:57:22.906733 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9640 13:57:22.910264 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9641 13:57:22.917067 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9642 13:57:22.920244 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9643 13:57:22.923461 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9644 13:57:22.930339 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9645 13:57:22.933555 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9646 13:57:22.939988 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9647 13:57:22.943820 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9648 13:57:22.946496 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9649 13:57:22.952990 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9650 13:57:22.956478 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9651 13:57:22.963156 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9652 13:57:22.966370 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9653 13:57:22.969641 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9654 13:57:22.976567 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9655 13:57:22.979804 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9656 13:57:22.986200 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9657 13:57:22.989296 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9658 13:57:22.993009 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9659 13:57:22.999408 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9660 13:57:23.002674 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9661 13:57:23.009599 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9662 13:57:23.012483 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9663 13:57:23.015851 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9664 13:57:23.023038 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9665 13:57:23.026109 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9666 13:57:23.033140 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9667 13:57:23.036181 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9668 13:57:23.039600 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9669 13:57:23.046237 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9670 13:57:23.049840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9671 13:57:23.055714 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9672 13:57:23.059254 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9673 13:57:23.063085 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9674 13:57:23.069414 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9675 13:57:23.072731 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9676 13:57:23.079126 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9677 13:57:23.082704 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9678 13:57:23.089489 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9679 13:57:23.092317 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9680 13:57:23.095928 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9681 13:57:23.102565 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9682 13:57:23.105880 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9683 13:57:23.112709 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9684 13:57:23.115807 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9685 13:57:23.119073 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9686 13:57:23.125558 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9687 13:57:23.128772 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9688 13:57:23.135826 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9689 13:57:23.138985 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9690 13:57:23.145788 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9691 13:57:23.149210 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9692 13:57:23.152237 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9693 13:57:23.158910 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9694 13:57:23.162943 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9695 13:57:23.168960 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9696 13:57:23.172272 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9697 13:57:23.175388 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9698 13:57:23.182246 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9699 13:57:23.185657 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9700 13:57:23.192055 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9701 13:57:23.195349 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9702 13:57:23.198737 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9703 13:57:23.205423 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9704 13:57:23.209137 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9705 13:57:23.215483 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9706 13:57:23.218611 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9707 13:57:23.221592 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9708 13:57:23.228456 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9709 13:57:23.231680 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9710 13:57:23.234881 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9711 13:57:23.238435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9712 13:57:23.244962 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9713 13:57:23.248241 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9714 13:57:23.251550 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9715 13:57:23.257834 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9716 13:57:23.261665 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9717 13:57:23.268203 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9718 13:57:23.271843 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9719 13:57:23.274878 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9720 13:57:23.281424 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9721 13:57:23.284902 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9722 13:57:23.288134 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9723 13:57:23.294558 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9724 13:57:23.297926 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9725 13:57:23.305092 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9726 13:57:23.307769 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9727 13:57:23.311285 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9728 13:57:23.317721 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9729 13:57:23.320867 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9730 13:57:23.324395 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9731 13:57:23.331141 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9732 13:57:23.334445 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9733 13:57:23.337988 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9734 13:57:23.344290 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9735 13:57:23.347571 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9736 13:57:23.354333 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9737 13:57:23.357250 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9738 13:57:23.360727 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9739 13:57:23.367761 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9740 13:57:23.370491 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9741 13:57:23.374021 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9742 13:57:23.380957 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9743 13:57:23.384233 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9744 13:57:23.390556 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9745 13:57:23.394260 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9746 13:57:23.397411 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9747 13:57:23.400731 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9748 13:57:23.407705 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9749 13:57:23.410581 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9750 13:57:23.413797 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9751 13:57:23.416981 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9752 13:57:23.424127 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9753 13:57:23.427457 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9754 13:57:23.430368 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9755 13:57:23.433896 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9756 13:57:23.440550 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9757 13:57:23.443949 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9758 13:57:23.447605 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9759 13:57:23.450886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9760 13:57:23.457387 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9761 13:57:23.460863 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9762 13:57:23.467011 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9763 13:57:23.470351 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9764 13:57:23.477100 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9765 13:57:23.480697 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9766 13:57:23.483639 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9767 13:57:23.490463 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9768 13:57:23.493581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9769 13:57:23.500757 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9770 13:57:23.503829 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9771 13:57:23.506847 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9772 13:57:23.513904 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9773 13:57:23.517261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9774 13:57:23.523487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9775 13:57:23.527102 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9776 13:57:23.530237 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9777 13:57:23.537180 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9778 13:57:23.540259 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9779 13:57:23.546838 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9780 13:57:23.550122 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9781 13:57:23.556943 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9782 13:57:23.560201 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9783 13:57:23.563149 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9784 13:57:23.570013 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9785 13:57:23.573658 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9786 13:57:23.576900 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9787 13:57:23.583946 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9788 13:57:23.586813 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9789 13:57:23.593540 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9790 13:57:23.596803 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9791 13:57:23.600054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9792 13:57:23.606672 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9793 13:57:23.610463 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9794 13:57:23.616466 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9795 13:57:23.620051 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9796 13:57:23.626493 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9797 13:57:23.629846 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9798 13:57:23.633589 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9799 13:57:23.639659 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9800 13:57:23.642802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9801 13:57:23.649207 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9802 13:57:23.653356 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9803 13:57:23.656564 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9804 13:57:23.662977 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9805 13:57:23.666495 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9806 13:57:23.672599 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9807 13:57:23.676300 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9808 13:57:23.679283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9809 13:57:23.686033 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9810 13:57:23.689091 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9811 13:57:23.695864 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9812 13:57:23.699285 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9813 13:57:23.706024 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9814 13:57:23.709325 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9815 13:57:23.712720 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9816 13:57:23.719039 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9817 13:57:23.722526 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9818 13:57:23.729326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9819 13:57:23.732541 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9820 13:57:23.735929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9821 13:57:23.742664 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9822 13:57:23.746042 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9823 13:57:23.752368 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9824 13:57:23.755757 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9825 13:57:23.758756 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9826 13:57:23.765496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9827 13:57:23.768873 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9828 13:57:23.775545 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9829 13:57:23.778900 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9830 13:57:23.785178 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9831 13:57:23.788768 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9832 13:57:23.791982 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9833 13:57:23.798695 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9834 13:57:23.801724 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9835 13:57:23.808374 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9836 13:57:23.811344 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9837 13:57:23.818481 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9838 13:57:23.821577 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9839 13:57:23.824774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9840 13:57:23.831347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9841 13:57:23.834771 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9842 13:57:23.841438 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9843 13:57:23.844838 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9844 13:57:23.851711 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9845 13:57:23.854563 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9846 13:57:23.861313 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9847 13:57:23.864498 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9848 13:57:23.868122 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9849 13:57:23.874646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9850 13:57:23.878072 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9851 13:57:23.884658 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9852 13:57:23.887648 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9853 13:57:23.894422 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9854 13:57:23.897622 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9855 13:57:23.904359 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9856 13:57:23.907269 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9857 13:57:23.910409 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9858 13:57:23.917232 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9859 13:57:23.920678 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9860 13:57:23.927159 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9861 13:57:23.930671 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9862 13:57:23.937126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9863 13:57:23.940453 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9864 13:57:23.947375 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9865 13:57:23.950318 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9866 13:57:23.954025 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9867 13:57:23.960220 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9868 13:57:23.963740 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9869 13:57:23.970783 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9870 13:57:23.974047 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9871 13:57:23.980421 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9872 13:57:23.983634 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9873 13:57:23.987417 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9874 13:57:23.993849 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9875 13:57:23.997065 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9876 13:57:24.003587 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9877 13:57:24.006564 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9878 13:57:24.013469 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9879 13:57:24.016837 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9880 13:57:24.019907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9881 13:57:24.026862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9882 13:57:24.030448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9883 13:57:24.036933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9884 13:57:24.039726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9885 13:57:24.046846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9886 13:57:24.050125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9887 13:57:24.056936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9888 13:57:24.059812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9889 13:57:24.066721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9890 13:57:24.070085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9891 13:57:24.076600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9892 13:57:24.079758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9893 13:57:24.086536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9894 13:57:24.089767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9895 13:57:24.096095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9896 13:57:24.099923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9897 13:57:24.103188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9898 13:57:24.109984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9899 13:57:24.113306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9900 13:57:24.119577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9901 13:57:24.122995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9902 13:57:24.129434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9903 13:57:24.133046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9904 13:57:24.139798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9905 13:57:24.145866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9906 13:57:24.149524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9907 13:57:24.156290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9908 13:57:24.159337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9909 13:57:24.166141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9910 13:57:24.169634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9911 13:57:24.176000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9912 13:57:24.179734 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9913 13:57:24.180302 INFO: [APUAPC] vio 0
9914 13:57:24.186427 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9915 13:57:24.190192 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9916 13:57:24.193283 INFO: [APUAPC] D0_APC_0: 0x400510
9917 13:57:24.196850 INFO: [APUAPC] D0_APC_1: 0x0
9918 13:57:24.199875 INFO: [APUAPC] D0_APC_2: 0x1540
9919 13:57:24.203190 INFO: [APUAPC] D0_APC_3: 0x0
9920 13:57:24.206631 INFO: [APUAPC] D1_APC_0: 0xffffffff
9921 13:57:24.209881 INFO: [APUAPC] D1_APC_1: 0xffffffff
9922 13:57:24.213510 INFO: [APUAPC] D1_APC_2: 0x3fffff
9923 13:57:24.216495 INFO: [APUAPC] D1_APC_3: 0x0
9924 13:57:24.219545 INFO: [APUAPC] D2_APC_0: 0xffffffff
9925 13:57:24.223227 INFO: [APUAPC] D2_APC_1: 0xffffffff
9926 13:57:24.226390 INFO: [APUAPC] D2_APC_2: 0x3fffff
9927 13:57:24.229719 INFO: [APUAPC] D2_APC_3: 0x0
9928 13:57:24.233056 INFO: [APUAPC] D3_APC_0: 0xffffffff
9929 13:57:24.236199 INFO: [APUAPC] D3_APC_1: 0xffffffff
9930 13:57:24.239632 INFO: [APUAPC] D3_APC_2: 0x3fffff
9931 13:57:24.243160 INFO: [APUAPC] D3_APC_3: 0x0
9932 13:57:24.246087 INFO: [APUAPC] D4_APC_0: 0xffffffff
9933 13:57:24.249427 INFO: [APUAPC] D4_APC_1: 0xffffffff
9934 13:57:24.252623 INFO: [APUAPC] D4_APC_2: 0x3fffff
9935 13:57:24.253138 INFO: [APUAPC] D4_APC_3: 0x0
9936 13:57:24.256336 INFO: [APUAPC] D5_APC_0: 0xffffffff
9937 13:57:24.259237 INFO: [APUAPC] D5_APC_1: 0xffffffff
9938 13:57:24.263094 INFO: [APUAPC] D5_APC_2: 0x3fffff
9939 13:57:24.266105 INFO: [APUAPC] D5_APC_3: 0x0
9940 13:57:24.269607 INFO: [APUAPC] D6_APC_0: 0xffffffff
9941 13:57:24.272785 INFO: [APUAPC] D6_APC_1: 0xffffffff
9942 13:57:24.276411 INFO: [APUAPC] D6_APC_2: 0x3fffff
9943 13:57:24.279761 INFO: [APUAPC] D6_APC_3: 0x0
9944 13:57:24.282778 INFO: [APUAPC] D7_APC_0: 0xffffffff
9945 13:57:24.286467 INFO: [APUAPC] D7_APC_1: 0xffffffff
9946 13:57:24.289359 INFO: [APUAPC] D7_APC_2: 0x3fffff
9947 13:57:24.292755 INFO: [APUAPC] D7_APC_3: 0x0
9948 13:57:24.296262 INFO: [APUAPC] D8_APC_0: 0xffffffff
9949 13:57:24.299403 INFO: [APUAPC] D8_APC_1: 0xffffffff
9950 13:57:24.302929 INFO: [APUAPC] D8_APC_2: 0x3fffff
9951 13:57:24.306316 INFO: [APUAPC] D8_APC_3: 0x0
9952 13:57:24.309552 INFO: [APUAPC] D9_APC_0: 0xffffffff
9953 13:57:24.313026 INFO: [APUAPC] D9_APC_1: 0xffffffff
9954 13:57:24.316159 INFO: [APUAPC] D9_APC_2: 0x3fffff
9955 13:57:24.319472 INFO: [APUAPC] D9_APC_3: 0x0
9956 13:57:24.322828 INFO: [APUAPC] D10_APC_0: 0xffffffff
9957 13:57:24.326054 INFO: [APUAPC] D10_APC_1: 0xffffffff
9958 13:57:24.329364 INFO: [APUAPC] D10_APC_2: 0x3fffff
9959 13:57:24.332750 INFO: [APUAPC] D10_APC_3: 0x0
9960 13:57:24.335553 INFO: [APUAPC] D11_APC_0: 0xffffffff
9961 13:57:24.338927 INFO: [APUAPC] D11_APC_1: 0xffffffff
9962 13:57:24.342484 INFO: [APUAPC] D11_APC_2: 0x3fffff
9963 13:57:24.345668 INFO: [APUAPC] D11_APC_3: 0x0
9964 13:57:24.349245 INFO: [APUAPC] D12_APC_0: 0xffffffff
9965 13:57:24.352253 INFO: [APUAPC] D12_APC_1: 0xffffffff
9966 13:57:24.355456 INFO: [APUAPC] D12_APC_2: 0x3fffff
9967 13:57:24.358824 INFO: [APUAPC] D12_APC_3: 0x0
9968 13:57:24.362262 INFO: [APUAPC] D13_APC_0: 0xffffffff
9969 13:57:24.365396 INFO: [APUAPC] D13_APC_1: 0xffffffff
9970 13:57:24.369081 INFO: [APUAPC] D13_APC_2: 0x3fffff
9971 13:57:24.372145 INFO: [APUAPC] D13_APC_3: 0x0
9972 13:57:24.375472 INFO: [APUAPC] D14_APC_0: 0xffffffff
9973 13:57:24.379122 INFO: [APUAPC] D14_APC_1: 0xffffffff
9974 13:57:24.382510 INFO: [APUAPC] D14_APC_2: 0x3fffff
9975 13:57:24.385466 INFO: [APUAPC] D14_APC_3: 0x0
9976 13:57:24.388566 INFO: [APUAPC] D15_APC_0: 0xffffffff
9977 13:57:24.392523 INFO: [APUAPC] D15_APC_1: 0xffffffff
9978 13:57:24.395445 INFO: [APUAPC] D15_APC_2: 0x3fffff
9979 13:57:24.398720 INFO: [APUAPC] D15_APC_3: 0x0
9980 13:57:24.401923 INFO: [APUAPC] APC_CON: 0x4
9981 13:57:24.405772 INFO: [NOCDAPC] D0_APC_0: 0x0
9982 13:57:24.408858 INFO: [NOCDAPC] D0_APC_1: 0x0
9983 13:57:24.411880 INFO: [NOCDAPC] D1_APC_0: 0x0
9984 13:57:24.415653 INFO: [NOCDAPC] D1_APC_1: 0xfff
9985 13:57:24.418695 INFO: [NOCDAPC] D2_APC_0: 0x0
9986 13:57:24.419267 INFO: [NOCDAPC] D2_APC_1: 0xfff
9987 13:57:24.421902 INFO: [NOCDAPC] D3_APC_0: 0x0
9988 13:57:24.425358 INFO: [NOCDAPC] D3_APC_1: 0xfff
9989 13:57:24.428653 INFO: [NOCDAPC] D4_APC_0: 0x0
9990 13:57:24.431641 INFO: [NOCDAPC] D4_APC_1: 0xfff
9991 13:57:24.435020 INFO: [NOCDAPC] D5_APC_0: 0x0
9992 13:57:24.438777 INFO: [NOCDAPC] D5_APC_1: 0xfff
9993 13:57:24.441622 INFO: [NOCDAPC] D6_APC_0: 0x0
9994 13:57:24.444973 INFO: [NOCDAPC] D6_APC_1: 0xfff
9995 13:57:24.448120 INFO: [NOCDAPC] D7_APC_0: 0x0
9996 13:57:24.451611 INFO: [NOCDAPC] D7_APC_1: 0xfff
9997 13:57:24.452085 INFO: [NOCDAPC] D8_APC_0: 0x0
9998 13:57:24.454950 INFO: [NOCDAPC] D8_APC_1: 0xfff
9999 13:57:24.458412 INFO: [NOCDAPC] D9_APC_0: 0x0
10000 13:57:24.461288 INFO: [NOCDAPC] D9_APC_1: 0xfff
10001 13:57:24.464675 INFO: [NOCDAPC] D10_APC_0: 0x0
10002 13:57:24.467833 INFO: [NOCDAPC] D10_APC_1: 0xfff
10003 13:57:24.471185 INFO: [NOCDAPC] D11_APC_0: 0x0
10004 13:57:24.474838 INFO: [NOCDAPC] D11_APC_1: 0xfff
10005 13:57:24.478027 INFO: [NOCDAPC] D12_APC_0: 0x0
10006 13:57:24.481270 INFO: [NOCDAPC] D12_APC_1: 0xfff
10007 13:57:24.484520 INFO: [NOCDAPC] D13_APC_0: 0x0
10008 13:57:24.487699 INFO: [NOCDAPC] D13_APC_1: 0xfff
10009 13:57:24.491494 INFO: [NOCDAPC] D14_APC_0: 0x0
10010 13:57:24.494559 INFO: [NOCDAPC] D14_APC_1: 0xfff
10011 13:57:24.494939 INFO: [NOCDAPC] D15_APC_0: 0x0
10012 13:57:24.498338 INFO: [NOCDAPC] D15_APC_1: 0xfff
10013 13:57:24.501604 INFO: [NOCDAPC] APC_CON: 0x4
10014 13:57:24.504824 INFO: [APUAPC] set_apusys_apc done
10015 13:57:24.508328 INFO: [DEVAPC] devapc_init done
10016 13:57:24.514668 INFO: GICv3 without legacy support detected.
10017 13:57:24.517708 INFO: ARM GICv3 driver initialized in EL3
10018 13:57:24.521164 INFO: Maximum SPI INTID supported: 639
10019 13:57:24.525046 INFO: BL31: Initializing runtime services
10020 13:57:24.530953 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10021 13:57:24.534129 INFO: SPM: enable CPC mode
10022 13:57:24.537894 INFO: mcdi ready for mcusys-off-idle and system suspend
10023 13:57:24.544451 INFO: BL31: Preparing for EL3 exit to normal world
10024 13:57:24.547922 INFO: Entry point address = 0x80000000
10025 13:57:24.548498 INFO: SPSR = 0x8
10026 13:57:24.554715
10027 13:57:24.555274
10028 13:57:24.555647
10029 13:57:24.557836 Starting depthcharge on Spherion...
10030 13:57:24.558471
10031 13:57:24.558931 Wipe memory regions:
10032 13:57:24.559288
10033 13:57:24.561698 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10034 13:57:24.562289 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10035 13:57:24.562738 Setting prompt string to ['asurada:']
10036 13:57:24.563220 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10037 13:57:24.563978 [0x00000040000000, 0x00000054600000)
10038 13:57:24.683284
10039 13:57:24.683858 [0x00000054660000, 0x00000080000000)
10040 13:57:24.944023
10041 13:57:24.944595 [0x000000821a7280, 0x000000ffe64000)
10042 13:57:25.688598
10043 13:57:25.689203 [0x00000100000000, 0x00000240000000)
10044 13:57:27.578223
10045 13:57:27.581451 Initializing XHCI USB controller at 0x11200000.
10046 13:57:28.619123
10047 13:57:28.622400 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10048 13:57:28.622876
10049 13:57:28.623243
10050 13:57:28.623586
10051 13:57:28.624358 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 13:57:28.725721 asurada: tftpboot 192.168.201.1 12682956/tftp-deploy-melxan2z/kernel/image.itb 12682956/tftp-deploy-melxan2z/kernel/cmdline
10054 13:57:28.726453 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10055 13:57:28.726959 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10056 13:57:28.731505 tftpboot 192.168.201.1 12682956/tftp-deploy-melxan2z/kernel/image.ittp-deploy-melxan2z/kernel/cmdline
10057 13:57:28.732114
10058 13:57:28.732568 Waiting for link
10059 13:57:28.892363
10060 13:57:28.892933 R8152: Initializing
10061 13:57:28.893309
10062 13:57:28.895235 Version 9 (ocp_data = 6010)
10063 13:57:28.895700
10064 13:57:28.898672 R8152: Done initializing
10065 13:57:28.899243
10066 13:57:28.899617 Adding net device
10067 13:57:30.840279
10068 13:57:30.840849 done.
10069 13:57:30.841222
10070 13:57:30.841566 MAC: 00:e0:4c:72:2d:d6
10071 13:57:30.841900
10072 13:57:30.843569 Sending DHCP discover... done.
10073 13:57:30.844140
10074 13:57:30.847010 Waiting for reply... done.
10075 13:57:30.847479
10076 13:57:30.850351 Sending DHCP request... done.
10077 13:57:30.850820
10078 13:57:30.851189 Waiting for reply... done.
10079 13:57:30.853710
10080 13:57:30.854245 My ip is 192.168.201.21
10081 13:57:30.854623
10082 13:57:30.856786 The DHCP server ip is 192.168.201.1
10083 13:57:30.857255
10084 13:57:30.860432 TFTP server IP predefined by user: 192.168.201.1
10085 13:57:30.860903
10086 13:57:30.867054 Bootfile predefined by user: 12682956/tftp-deploy-melxan2z/kernel/image.itb
10087 13:57:30.867616
10088 13:57:30.870277 Sending tftp read request... done.
10089 13:57:30.870745
10090 13:57:30.877510 Waiting for the transfer...
10091 13:57:30.878017
10092 13:57:31.178666 00000000 ################################################################
10093 13:57:31.178816
10094 13:57:31.467421 00080000 ################################################################
10095 13:57:31.467569
10096 13:57:31.761523 00100000 ################################################################
10097 13:57:31.761691
10098 13:57:32.051371 00180000 ################################################################
10099 13:57:32.051534
10100 13:57:32.346758 00200000 ################################################################
10101 13:57:32.346909
10102 13:57:32.728177 00280000 ################################################################
10103 13:57:32.728797
10104 13:57:33.130807 00300000 ################################################################
10105 13:57:33.131321
10106 13:57:33.506107 00380000 ################################################################
10107 13:57:33.506628
10108 13:57:33.812355 00400000 ################################################################
10109 13:57:33.812505
10110 13:57:34.103869 00480000 ################################################################
10111 13:57:34.104002
10112 13:57:34.396053 00500000 ################################################################
10113 13:57:34.396223
10114 13:57:34.681043 00580000 ################################################################
10115 13:57:34.681189
10116 13:57:34.952819 00600000 ################################################################
10117 13:57:34.952992
10118 13:57:35.268692 00680000 ################################################################
10119 13:57:35.268838
10120 13:57:35.526279 00700000 ################################################################
10121 13:57:35.526418
10122 13:57:35.774356 00780000 ################################################################
10123 13:57:35.774517
10124 13:57:36.047798 00800000 ################################################################
10125 13:57:36.047938
10126 13:57:36.323280 00880000 ################################################################
10127 13:57:36.323426
10128 13:57:36.618337 00900000 ################################################################
10129 13:57:36.618481
10130 13:57:36.872087 00980000 ################################################################
10131 13:57:36.872230
10132 13:57:37.126670 00a00000 ################################################################
10133 13:57:37.126806
10134 13:57:37.425302 00a80000 ################################################################
10135 13:57:37.425442
10136 13:57:37.720787 00b00000 ################################################################
10137 13:57:37.720935
10138 13:57:38.012177 00b80000 ################################################################
10139 13:57:38.012319
10140 13:57:38.301276 00c00000 ################################################################
10141 13:57:38.301418
10142 13:57:38.568391 00c80000 ################################################################
10143 13:57:38.568598
10144 13:57:38.825216 00d00000 ################################################################
10145 13:57:38.825359
10146 13:57:39.092391 00d80000 ################################################################
10147 13:57:39.092578
10148 13:57:39.357164 00e00000 ################################################################
10149 13:57:39.357316
10150 13:57:39.620736 00e80000 ################################################################
10151 13:57:39.620899
10152 13:57:39.875615 00f00000 ################################################################
10153 13:57:39.875771
10154 13:57:40.140141 00f80000 ################################################################
10155 13:57:40.140347
10156 13:57:40.403456 01000000 ################################################################
10157 13:57:40.403677
10158 13:57:40.658654 01080000 ################################################################
10159 13:57:40.658834
10160 13:57:40.915798 01100000 ################################################################
10161 13:57:40.915953
10162 13:57:41.197636 01180000 ################################################################
10163 13:57:41.197833
10164 13:57:41.453922 01200000 ################################################################
10165 13:57:41.454083
10166 13:57:41.716741 01280000 ################################################################
10167 13:57:41.716931
10168 13:57:41.977813 01300000 ################################################################
10169 13:57:41.978022
10170 13:57:42.240436 01380000 ################################################################
10171 13:57:42.240632
10172 13:57:42.502629 01400000 ################################################################
10173 13:57:42.502821
10174 13:57:42.763149 01480000 ################################################################
10175 13:57:42.763350
10176 13:57:43.032630 01500000 ################################################################
10177 13:57:43.032828
10178 13:57:43.288781 01580000 ################################################################
10179 13:57:43.288975
10180 13:57:43.538546 01600000 ################################################################
10181 13:57:43.538725
10182 13:57:43.784689 01680000 ################################################################
10183 13:57:43.784886
10184 13:57:44.043508 01700000 ################################################################
10185 13:57:44.043666
10186 13:57:44.297237 01780000 ################################################################
10187 13:57:44.297441
10188 13:57:44.550910 01800000 ################################################################
10189 13:57:44.551107
10190 13:57:44.805294 01880000 ################################################################
10191 13:57:44.805535
10192 13:57:45.064284 01900000 ################################################################
10193 13:57:45.064487
10194 13:57:45.325910 01980000 ################################################################
10195 13:57:45.326118
10196 13:57:45.576884 01a00000 ################################################################
10197 13:57:45.577077
10198 13:57:45.853287 01a80000 ################################################################
10199 13:57:45.853471
10200 13:57:46.131940 01b00000 ################################################################
10201 13:57:46.132171
10202 13:57:46.401039 01b80000 ################################################################
10203 13:57:46.401232
10204 13:57:46.662861 01c00000 ################################################################
10205 13:57:46.663014
10206 13:57:46.938682 01c80000 ################################################################
10207 13:57:46.938899
10208 13:57:47.203030 01d00000 ################################################################
10209 13:57:47.203253
10210 13:57:47.465246 01d80000 ################################################################
10211 13:57:47.465479
10212 13:57:47.728447 01e00000 ################################################################
10213 13:57:47.728612
10214 13:57:47.985226 01e80000 ################################################################
10215 13:57:47.985380
10216 13:57:48.245829 01f00000 ################################################################
10217 13:57:48.246031
10218 13:57:48.512611 01f80000 ################################################################
10219 13:57:48.512765
10220 13:57:48.768545 02000000 ################################################################
10221 13:57:48.768694
10222 13:57:49.019055 02080000 ################################################################
10223 13:57:49.019211
10224 13:57:49.255242 02100000 ################################################################
10225 13:57:49.255454
10226 13:57:49.513197 02180000 ################################################################
10227 13:57:49.513374
10228 13:57:49.781703 02200000 ################################################################
10229 13:57:49.781859
10230 13:57:50.022194 02280000 ################################################################
10231 13:57:50.022367
10232 13:57:50.261673 02300000 ################################################################
10233 13:57:50.261844
10234 13:57:50.521050 02380000 ################################################################
10235 13:57:50.521241
10236 13:57:50.807711 02400000 ################################################################
10237 13:57:50.807879
10238 13:57:51.093978 02480000 ################################################################
10239 13:57:51.094129
10240 13:57:51.392930 02500000 ################################################################
10241 13:57:51.393087
10242 13:57:51.687476 02580000 ################################################################
10243 13:57:51.687705
10244 13:57:51.978655 02600000 ################################################################
10245 13:57:51.978813
10246 13:57:52.260673 02680000 ################################################################
10247 13:57:52.260869
10248 13:57:52.528148 02700000 ################################################################
10249 13:57:52.528298
10250 13:57:52.818148 02780000 ################################################################
10251 13:57:52.818303
10252 13:57:53.102314 02800000 ################################################################
10253 13:57:53.102470
10254 13:57:53.368923 02880000 ################################################################
10255 13:57:53.369073
10256 13:57:53.645538 02900000 ################################################################
10257 13:57:53.645695
10258 13:57:53.924297 02980000 ################################################################
10259 13:57:53.924449
10260 13:57:54.211306 02a00000 ################################################################
10261 13:57:54.211456
10262 13:57:54.488513 02a80000 ################################################################
10263 13:57:54.488647
10264 13:57:54.754437 02b00000 ################################################################
10265 13:57:54.754599
10266 13:57:55.029871 02b80000 ################################################################
10267 13:57:55.030092
10268 13:57:55.311795 02c00000 ################################################################
10269 13:57:55.311941
10270 13:57:55.593628 02c80000 ################################################################
10271 13:57:55.593782
10272 13:57:55.892078 02d00000 ################################################################
10273 13:57:55.892316
10274 13:57:56.185039 02d80000 ################################################################
10275 13:57:56.185191
10276 13:57:56.464800 02e00000 ################################################################
10277 13:57:56.464946
10278 13:57:56.751194 02e80000 ################################################################
10279 13:57:56.751332
10280 13:57:57.046301 02f00000 ################################################################
10281 13:57:57.046441
10282 13:57:57.332392 02f80000 ################################################################
10283 13:57:57.332571
10284 13:57:57.621184 03000000 ################################################################
10285 13:57:57.621323
10286 13:57:57.895581 03080000 ################################################################
10287 13:57:57.895716
10288 13:57:57.939374 03100000 ########### done.
10289 13:57:57.942501
10290 13:57:57.942593 The bootfile was 51468274 bytes long.
10291 13:57:57.946148
10292 13:57:57.946235 Sending tftp read request... done.
10293 13:57:57.946303
10294 13:57:57.949513 Waiting for the transfer...
10295 13:57:57.949598
10296 13:57:57.952612 00000000 # done.
10297 13:57:57.952698
10298 13:57:57.959191 Command line loaded dynamically from TFTP file: 12682956/tftp-deploy-melxan2z/kernel/cmdline
10299 13:57:57.959276
10300 13:57:57.972795 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10301 13:57:57.972907
10302 13:57:57.975709 Loading FIT.
10303 13:57:57.975813
10304 13:57:57.979364 Image ramdisk-1 has 39372104 bytes.
10305 13:57:57.979477
10306 13:57:57.979566 Image fdt-1 has 47278 bytes.
10307 13:57:57.979650
10308 13:57:57.982268 Image kernel-1 has 12046857 bytes.
10309 13:57:57.982398
10310 13:57:57.992445 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10311 13:57:57.992533
10312 13:57:58.009284 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10313 13:57:58.009376
10314 13:57:58.015389 Choosing best match conf-1 for compat google,spherion-rev2.
10315 13:57:58.019396
10316 13:57:58.023804 Connected to device vid:did:rid of 1ae0:0028:00
10317 13:57:58.031719
10318 13:57:58.035207 tpm_get_response: command 0x17b, return code 0x0
10319 13:57:58.035293
10320 13:57:58.038602 ec_init: CrosEC protocol v3 supported (256, 248)
10321 13:57:58.042360
10322 13:57:58.046213 tpm_cleanup: add release locality here.
10323 13:57:58.046298
10324 13:57:58.046370 Shutting down all USB controllers.
10325 13:57:58.046435
10326 13:57:58.049425 Removing current net device
10327 13:57:58.049509
10328 13:57:58.055939 Exiting depthcharge with code 4 at timestamp: 62816782
10329 13:57:58.056023
10330 13:57:58.059373 LZMA decompressing kernel-1 to 0x821a6718
10331 13:57:58.059457
10332 13:57:58.062685 LZMA decompressing kernel-1 to 0x40000000
10333 13:57:59.563533
10334 13:57:59.563674 jumping to kernel
10335 13:57:59.564183 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10336 13:57:59.564283 start: 2.2.5 auto-login-action (timeout 00:03:50) [common]
10337 13:57:59.564359 Setting prompt string to ['Linux version [0-9]']
10338 13:57:59.564479 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10339 13:57:59.564601 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10340 13:57:59.645243
10341 13:57:59.648683 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10342 13:57:59.652496 start: 2.2.5.1 login-action (timeout 00:03:50) [common]
10343 13:57:59.652590 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10344 13:57:59.652663 Setting prompt string to []
10345 13:57:59.652742 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10346 13:57:59.652818 Using line separator: #'\n'#
10347 13:57:59.652879 No login prompt set.
10348 13:57:59.652940 Parsing kernel messages
10349 13:57:59.652996 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10350 13:57:59.653096 [login-action] Waiting for messages, (timeout 00:03:50)
10351 13:57:59.671779 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10352 13:57:59.675065 [ 0.000000] random: crng init done
10353 13:57:59.681412 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10354 13:57:59.685150 [ 0.000000] efi: UEFI not found.
10355 13:57:59.691605 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10356 13:57:59.701168 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10357 13:57:59.707924 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10358 13:57:59.718258 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10359 13:57:59.724542 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10360 13:57:59.731185 [ 0.000000] printk: bootconsole [mtk8250] enabled
10361 13:57:59.737745 [ 0.000000] NUMA: No NUMA configuration found
10362 13:57:59.744215 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10363 13:57:59.750743 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10364 13:57:59.750833 [ 0.000000] Zone ranges:
10365 13:57:59.757562 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10366 13:57:59.760593 [ 0.000000] DMA32 empty
10367 13:57:59.767283 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10368 13:57:59.770536 [ 0.000000] Movable zone start for each node
10369 13:57:59.773864 [ 0.000000] Early memory node ranges
10370 13:57:59.780520 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10371 13:57:59.787229 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10372 13:57:59.793821 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10373 13:57:59.800053 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10374 13:57:59.806692 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10375 13:57:59.813377 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10376 13:57:59.870184 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10377 13:57:59.876629 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10378 13:57:59.883868 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10379 13:57:59.886780 [ 0.000000] psci: probing for conduit method from DT.
10380 13:57:59.893318 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10381 13:57:59.896458 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10382 13:57:59.903187 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10383 13:57:59.906544 [ 0.000000] psci: SMC Calling Convention v1.2
10384 13:57:59.913173 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10385 13:57:59.916504 [ 0.000000] Detected VIPT I-cache on CPU0
10386 13:57:59.922850 [ 0.000000] CPU features: detected: GIC system register CPU interface
10387 13:57:59.929971 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10388 13:57:59.936657 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10389 13:57:59.943110 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10390 13:57:59.949724 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10391 13:57:59.956470 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10392 13:57:59.963090 [ 0.000000] alternatives: applying boot alternatives
10393 13:57:59.966224 [ 0.000000] Fallback order for Node 0: 0
10394 13:57:59.976450 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10395 13:57:59.979497 [ 0.000000] Policy zone: Normal
10396 13:57:59.992794 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10397 13:58:00.002469 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10398 13:58:00.014026 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10399 13:58:00.024500 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10400 13:58:00.031198 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10401 13:58:00.033931 <6>[ 0.000000] software IO TLB: area num 8.
10402 13:58:00.091121 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10403 13:58:00.239700 <6>[ 0.000000] Memory: 7928804K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 423964K reserved, 32768K cma-reserved)
10404 13:58:00.246648 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10405 13:58:00.253177 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10406 13:58:00.256260 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10407 13:58:00.262910 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10408 13:58:00.269653 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10409 13:58:00.273075 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10410 13:58:00.282787 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10411 13:58:00.289592 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10412 13:58:00.296188 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10413 13:58:00.302965 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10414 13:58:00.305944 <6>[ 0.000000] GICv3: 608 SPIs implemented
10415 13:58:00.309470 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10416 13:58:00.316102 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10417 13:58:00.319451 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10418 13:58:00.326087 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10419 13:58:00.339662 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10420 13:58:00.349466 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10421 13:58:00.359120 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10422 13:58:00.366934 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10423 13:58:00.380065 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10424 13:58:00.386372 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10425 13:58:00.393130 <6>[ 0.009182] Console: colour dummy device 80x25
10426 13:58:00.403167 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10427 13:58:00.406557 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10428 13:58:00.413024 <6>[ 0.029279] LSM: Security Framework initializing
10429 13:58:00.419640 <6>[ 0.034218] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10430 13:58:00.429780 <6>[ 0.042032] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10431 13:58:00.436246 <6>[ 0.051482] cblist_init_generic: Setting adjustable number of callback queues.
10432 13:58:00.443271 <6>[ 0.058924] cblist_init_generic: Setting shift to 3 and lim to 1.
10433 13:58:00.452686 <6>[ 0.065263] cblist_init_generic: Setting adjustable number of callback queues.
10434 13:58:00.456253 <6>[ 0.072690] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 13:58:00.462784 <6>[ 0.079130] rcu: Hierarchical SRCU implementation.
10436 13:58:00.469633 <6>[ 0.084145] rcu: Max phase no-delay instances is 1000.
10437 13:58:00.476283 <6>[ 0.091171] EFI services will not be available.
10438 13:58:00.479367 <6>[ 0.096125] smp: Bringing up secondary CPUs ...
10439 13:58:00.487577 <6>[ 0.101205] Detected VIPT I-cache on CPU1
10440 13:58:00.494261 <6>[ 0.101275] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10441 13:58:00.500739 <6>[ 0.101306] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10442 13:58:00.503638 <6>[ 0.101646] Detected VIPT I-cache on CPU2
10443 13:58:00.513787 <6>[ 0.101698] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10444 13:58:00.520411 <6>[ 0.101716] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10445 13:58:00.523452 <6>[ 0.101977] Detected VIPT I-cache on CPU3
10446 13:58:00.530139 <6>[ 0.102024] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10447 13:58:00.536679 <6>[ 0.102038] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10448 13:58:00.540051 <6>[ 0.102346] CPU features: detected: Spectre-v4
10449 13:58:00.547024 <6>[ 0.102353] CPU features: detected: Spectre-BHB
10450 13:58:00.550314 <6>[ 0.102358] Detected PIPT I-cache on CPU4
10451 13:58:00.556834 <6>[ 0.102415] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10452 13:58:00.563092 <6>[ 0.102431] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10453 13:58:00.569713 <6>[ 0.102725] Detected PIPT I-cache on CPU5
10454 13:58:00.576828 <6>[ 0.102787] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10455 13:58:00.583032 <6>[ 0.102806] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10456 13:58:00.586805 <6>[ 0.103089] Detected PIPT I-cache on CPU6
10457 13:58:00.593358 <6>[ 0.103152] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10458 13:58:00.600017 <6>[ 0.103171] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10459 13:58:00.606527 <6>[ 0.103467] Detected PIPT I-cache on CPU7
10460 13:58:00.613061 <6>[ 0.103532] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10461 13:58:00.619580 <6>[ 0.103549] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10462 13:58:00.623191 <6>[ 0.103596] smp: Brought up 1 node, 8 CPUs
10463 13:58:00.629790 <6>[ 0.245071] SMP: Total of 8 processors activated.
10464 13:58:00.633252 <6>[ 0.250022] CPU features: detected: 32-bit EL0 Support
10465 13:58:00.643156 <6>[ 0.255418] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10466 13:58:00.649793 <6>[ 0.264273] CPU features: detected: Common not Private translations
10467 13:58:00.655949 <6>[ 0.270749] CPU features: detected: CRC32 instructions
10468 13:58:00.659384 <6>[ 0.276100] CPU features: detected: RCpc load-acquire (LDAPR)
10469 13:58:00.665895 <6>[ 0.282097] CPU features: detected: LSE atomic instructions
10470 13:58:00.672633 <6>[ 0.287914] CPU features: detected: Privileged Access Never
10471 13:58:00.679312 <6>[ 0.293730] CPU features: detected: RAS Extension Support
10472 13:58:00.685814 <6>[ 0.299339] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10473 13:58:00.689291 <6>[ 0.306559] CPU: All CPU(s) started at EL2
10474 13:58:00.695964 <6>[ 0.310903] alternatives: applying system-wide alternatives
10475 13:58:00.705227 <6>[ 0.321613] devtmpfs: initialized
10476 13:58:00.717719 <6>[ 0.330590] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10477 13:58:00.727763 <6>[ 0.340554] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10478 13:58:00.730862 <6>[ 0.348157] pinctrl core: initialized pinctrl subsystem
10479 13:58:00.738578 <6>[ 0.354806] DMI not present or invalid.
10480 13:58:00.745010 <6>[ 0.359218] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10481 13:58:00.751999 <6>[ 0.366092] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10482 13:58:00.761753 <6>[ 0.373677] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10483 13:58:00.768496 <6>[ 0.381905] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10484 13:58:00.775299 <6>[ 0.390147] audit: initializing netlink subsys (disabled)
10485 13:58:00.781775 <5>[ 0.395838] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10486 13:58:00.788676 <6>[ 0.396531] thermal_sys: Registered thermal governor 'step_wise'
10487 13:58:00.795142 <6>[ 0.403808] thermal_sys: Registered thermal governor 'power_allocator'
10488 13:58:00.798221 <6>[ 0.410063] cpuidle: using governor menu
10489 13:58:00.804857 <6>[ 0.421024] NET: Registered PF_QIPCRTR protocol family
10490 13:58:00.811815 <6>[ 0.426501] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10491 13:58:00.818462 <6>[ 0.433603] ASID allocator initialised with 32768 entries
10492 13:58:00.824633 <6>[ 0.440161] Serial: AMBA PL011 UART driver
10493 13:58:00.832637 <4>[ 0.448946] Trying to register duplicate clock ID: 134
10494 13:58:00.888600 <6>[ 0.508374] KASLR enabled
10495 13:58:00.903279 <6>[ 0.516084] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10496 13:58:00.909437 <6>[ 0.523097] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10497 13:58:00.916047 <6>[ 0.529586] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10498 13:58:00.922668 <6>[ 0.536593] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10499 13:58:00.929556 <6>[ 0.543081] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10500 13:58:00.936203 <6>[ 0.550087] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10501 13:58:00.942631 <6>[ 0.556574] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10502 13:58:00.949394 <6>[ 0.563577] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10503 13:58:00.952417 <6>[ 0.571038] ACPI: Interpreter disabled.
10504 13:58:00.961317 <6>[ 0.577456] iommu: Default domain type: Translated
10505 13:58:00.967828 <6>[ 0.582590] iommu: DMA domain TLB invalidation policy: strict mode
10506 13:58:00.971136 <5>[ 0.589250] SCSI subsystem initialized
10507 13:58:00.977658 <6>[ 0.593498] usbcore: registered new interface driver usbfs
10508 13:58:00.984450 <6>[ 0.599230] usbcore: registered new interface driver hub
10509 13:58:00.987580 <6>[ 0.604784] usbcore: registered new device driver usb
10510 13:58:00.994644 <6>[ 0.610908] pps_core: LinuxPPS API ver. 1 registered
10511 13:58:01.004334 <6>[ 0.616104] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10512 13:58:01.007853 <6>[ 0.625447] PTP clock support registered
10513 13:58:01.011326 <6>[ 0.629690] EDAC MC: Ver: 3.0.0
10514 13:58:01.018477 <6>[ 0.634881] FPGA manager framework
10515 13:58:01.025192 <6>[ 0.638559] Advanced Linux Sound Architecture Driver Initialized.
10516 13:58:01.028556 <6>[ 0.645327] vgaarb: loaded
10517 13:58:01.034924 <6>[ 0.648474] clocksource: Switched to clocksource arch_sys_counter
10518 13:58:01.038551 <5>[ 0.654922] VFS: Disk quotas dquot_6.6.0
10519 13:58:01.044666 <6>[ 0.659110] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10520 13:58:01.048108 <6>[ 0.666284] pnp: PnP ACPI: disabled
10521 13:58:01.056679 <6>[ 0.673038] NET: Registered PF_INET protocol family
10522 13:58:01.066398 <6>[ 0.678621] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10523 13:58:01.077714 <6>[ 0.690936] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10524 13:58:01.087846 <6>[ 0.699747] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10525 13:58:01.094805 <6>[ 0.707718] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10526 13:58:01.101146 <6>[ 0.716376] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10527 13:58:01.113158 <6>[ 0.726121] TCP: Hash tables configured (established 65536 bind 65536)
10528 13:58:01.119651 <6>[ 0.732981] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10529 13:58:01.126180 <6>[ 0.740180] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10530 13:58:01.133144 <6>[ 0.747882] NET: Registered PF_UNIX/PF_LOCAL protocol family
10531 13:58:01.139527 <6>[ 0.754049] RPC: Registered named UNIX socket transport module.
10532 13:58:01.143155 <6>[ 0.760206] RPC: Registered udp transport module.
10533 13:58:01.149674 <6>[ 0.765138] RPC: Registered tcp transport module.
10534 13:58:01.156108 <6>[ 0.770071] RPC: Registered tcp NFSv4.1 backchannel transport module.
10535 13:58:01.159666 <6>[ 0.776739] PCI: CLS 0 bytes, default 64
10536 13:58:01.163085 <6>[ 0.781203] Unpacking initramfs...
10537 13:58:01.172933 <6>[ 0.784931] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10538 13:58:01.179590 <6>[ 0.793600] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10539 13:58:01.186169 <6>[ 0.802457] kvm [1]: IPA Size Limit: 40 bits
10540 13:58:01.189400 <6>[ 0.806985] kvm [1]: GICv3: no GICV resource entry
10541 13:58:01.196075 <6>[ 0.812008] kvm [1]: disabling GICv2 emulation
10542 13:58:01.202788 <6>[ 0.816697] kvm [1]: GIC system register CPU interface enabled
10543 13:58:01.205810 <6>[ 0.822869] kvm [1]: vgic interrupt IRQ18
10544 13:58:01.212757 <6>[ 0.828531] kvm [1]: VHE mode initialized successfully
10545 13:58:01.219245 <5>[ 0.834873] Initialise system trusted keyrings
10546 13:58:01.225848 <6>[ 0.839668] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10547 13:58:01.233522 <6>[ 0.849685] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10548 13:58:01.239849 <5>[ 0.856064] NFS: Registering the id_resolver key type
10549 13:58:01.243156 <5>[ 0.861367] Key type id_resolver registered
10550 13:58:01.249847 <5>[ 0.865784] Key type id_legacy registered
10551 13:58:01.256337 <6>[ 0.870065] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10552 13:58:01.263167 <6>[ 0.876988] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10553 13:58:01.269838 <6>[ 0.884720] 9p: Installing v9fs 9p2000 file system support
10554 13:58:01.306720 <5>[ 0.922901] Key type asymmetric registered
10555 13:58:01.309867 <5>[ 0.927230] Asymmetric key parser 'x509' registered
10556 13:58:01.319879 <6>[ 0.932375] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10557 13:58:01.323404 <6>[ 0.939990] io scheduler mq-deadline registered
10558 13:58:01.326451 <6>[ 0.944751] io scheduler kyber registered
10559 13:58:01.345399 <6>[ 0.961813] EINJ: ACPI disabled.
10560 13:58:01.378068 <4>[ 0.987427] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10561 13:58:01.387767 <4>[ 0.998071] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 13:58:01.402510 <6>[ 1.018742] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10563 13:58:01.410595 <6>[ 1.026830] printk: console [ttyS0] disabled
10564 13:58:01.438208 <6>[ 1.051483] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10565 13:58:01.445245 <6>[ 1.060987] printk: console [ttyS0] enabled
10566 13:58:01.448508 <6>[ 1.060987] printk: console [ttyS0] enabled
10567 13:58:01.455236 <6>[ 1.069904] printk: bootconsole [mtk8250] disabled
10568 13:58:01.458150 <6>[ 1.069904] printk: bootconsole [mtk8250] disabled
10569 13:58:01.464666 <6>[ 1.081200] SuperH (H)SCI(F) driver initialized
10570 13:58:01.468276 <6>[ 1.086496] msm_serial: driver initialized
10571 13:58:01.482618 <6>[ 1.095465] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10572 13:58:01.492511 <6>[ 1.104014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10573 13:58:01.498992 <6>[ 1.112558] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10574 13:58:01.509059 <6>[ 1.121188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10575 13:58:01.519159 <6>[ 1.129895] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10576 13:58:01.525386 <6>[ 1.138611] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10577 13:58:01.535799 <6>[ 1.147152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10578 13:58:01.542298 <6>[ 1.155963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10579 13:58:01.552078 <6>[ 1.164510] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10580 13:58:01.563589 <6>[ 1.180159] loop: module loaded
10581 13:58:01.570230 <6>[ 1.186113] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10582 13:58:01.593038 <4>[ 1.209599] mtk-pmic-keys: Failed to locate of_node [id: -1]
10583 13:58:01.599999 <6>[ 1.216523] megasas: 07.719.03.00-rc1
10584 13:58:01.609539 <6>[ 1.226149] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10585 13:58:01.619844 <6>[ 1.235857] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10586 13:58:01.635580 <6>[ 1.251829] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10587 13:58:01.691463 <6>[ 1.300888] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10588 13:58:02.756292 <6>[ 2.373046] Freeing initrd memory: 38448K
10589 13:58:02.766680 <6>[ 2.383280] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10590 13:58:02.778042 <6>[ 2.394447] tun: Universal TUN/TAP device driver, 1.6
10591 13:58:02.781260 <6>[ 2.400535] thunder_xcv, ver 1.0
10592 13:58:02.784844 <6>[ 2.404034] thunder_bgx, ver 1.0
10593 13:58:02.787666 <6>[ 2.407531] nicpf, ver 1.0
10594 13:58:02.798611 <6>[ 2.411562] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10595 13:58:02.801835 <6>[ 2.419038] hns3: Copyright (c) 2017 Huawei Corporation.
10596 13:58:02.808307 <6>[ 2.424625] hclge is initializing
10597 13:58:02.811900 <6>[ 2.428202] e1000: Intel(R) PRO/1000 Network Driver
10598 13:58:02.817978 <6>[ 2.433331] e1000: Copyright (c) 1999-2006 Intel Corporation.
10599 13:58:02.821667 <6>[ 2.439344] e1000e: Intel(R) PRO/1000 Network Driver
10600 13:58:02.828216 <6>[ 2.444560] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10601 13:58:02.834907 <6>[ 2.450746] igb: Intel(R) Gigabit Ethernet Network Driver
10602 13:58:02.841458 <6>[ 2.456396] igb: Copyright (c) 2007-2014 Intel Corporation.
10603 13:58:02.848101 <6>[ 2.462235] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10604 13:58:02.854735 <6>[ 2.468754] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10605 13:58:02.858214 <6>[ 2.475216] sky2: driver version 1.30
10606 13:58:02.864696 <6>[ 2.480210] VFIO - User Level meta-driver version: 0.3
10607 13:58:02.871815 <6>[ 2.488435] usbcore: registered new interface driver usb-storage
10608 13:58:02.878379 <6>[ 2.494887] usbcore: registered new device driver onboard-usb-hub
10609 13:58:02.887398 <6>[ 2.504090] mt6397-rtc mt6359-rtc: registered as rtc0
10610 13:58:02.897650 <6>[ 2.509556] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:57:23 UTC (1706795843)
10611 13:58:02.900839 <6>[ 2.519127] i2c_dev: i2c /dev entries driver
10612 13:58:02.917712 <6>[ 2.530989] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10613 13:58:02.937793 <6>[ 2.553985] cpu cpu0: EM: created perf domain
10614 13:58:02.940829 <6>[ 2.558908] cpu cpu4: EM: created perf domain
10615 13:58:02.947926 <6>[ 2.564522] sdhci: Secure Digital Host Controller Interface driver
10616 13:58:02.954584 <6>[ 2.570952] sdhci: Copyright(c) Pierre Ossman
10617 13:58:02.961205 <6>[ 2.575910] Synopsys Designware Multimedia Card Interface Driver
10618 13:58:02.968267 <6>[ 2.582545] sdhci-pltfm: SDHCI platform and OF driver helper
10619 13:58:02.971270 <6>[ 2.582685] mmc0: CQHCI version 5.10
10620 13:58:02.977900 <6>[ 2.592559] ledtrig-cpu: registered to indicate activity on CPUs
10621 13:58:02.984588 <6>[ 2.599450] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10622 13:58:02.991106 <6>[ 2.606518] usbcore: registered new interface driver usbhid
10623 13:58:02.994519 <6>[ 2.612341] usbhid: USB HID core driver
10624 13:58:03.001020 <6>[ 2.616548] spi_master spi0: will run message pump with realtime priority
10625 13:58:03.044012 <6>[ 2.654054] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10626 13:58:03.063762 <6>[ 2.670347] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10627 13:58:03.071425 <6>[ 2.686235] cros-ec-spi spi0.0: Chrome EC device registered
10628 13:58:03.074344 <6>[ 2.692242] mmc0: Command Queue Engine enabled
10629 13:58:03.081147 <6>[ 2.696989] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10630 13:58:03.088142 <6>[ 2.704570] mmcblk0: mmc0:0001 DA4128 116 GiB
10631 13:58:03.096525 <6>[ 2.713113] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10632 13:58:03.104122 <6>[ 2.720507] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10633 13:58:03.113823 <6>[ 2.725281] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10634 13:58:03.117217 <6>[ 2.726415] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10635 13:58:03.123945 <6>[ 2.736281] NET: Registered PF_PACKET protocol family
10636 13:58:03.130399 <6>[ 2.740932] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10637 13:58:03.133947 <6>[ 2.745656] 9pnet: Installing 9P2000 support
10638 13:58:03.140301 <5>[ 2.756646] Key type dns_resolver registered
10639 13:58:03.143926 <6>[ 2.761472] registered taskstats version 1
10640 13:58:03.149931 <5>[ 2.765859] Loading compiled-in X.509 certificates
10641 13:58:03.179379 <4>[ 2.789162] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 13:58:03.189164 <4>[ 2.799888] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 13:58:03.195585 <3>[ 2.810418] debugfs: File 'uA_load' in directory '/' already present!
10644 13:58:03.202621 <3>[ 2.817175] debugfs: File 'min_uV' in directory '/' already present!
10645 13:58:03.209266 <3>[ 2.823791] debugfs: File 'max_uV' in directory '/' already present!
10646 13:58:03.215486 <3>[ 2.830403] debugfs: File 'constraint_flags' in directory '/' already present!
10647 13:58:03.226774 <3>[ 2.840124] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10648 13:58:03.236284 <6>[ 2.852851] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10649 13:58:03.243317 <6>[ 2.859757] xhci-mtk 11200000.usb: xHCI Host Controller
10650 13:58:03.249614 <6>[ 2.865259] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10651 13:58:03.259683 <6>[ 2.873117] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10652 13:58:03.266427 <6>[ 2.882548] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10653 13:58:03.273080 <6>[ 2.888631] xhci-mtk 11200000.usb: xHCI Host Controller
10654 13:58:03.279586 <6>[ 2.894110] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10655 13:58:03.286144 <6>[ 2.901779] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10656 13:58:03.293191 <6>[ 2.909492] hub 1-0:1.0: USB hub found
10657 13:58:03.296292 <6>[ 2.913511] hub 1-0:1.0: 1 port detected
10658 13:58:03.306224 <6>[ 2.917779] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10659 13:58:03.309275 <6>[ 2.926373] hub 2-0:1.0: USB hub found
10660 13:58:03.312768 <6>[ 2.930380] hub 2-0:1.0: 1 port detected
10661 13:58:03.321581 <6>[ 2.938356] mtk-msdc 11f70000.mmc: Got CD GPIO
10662 13:58:03.333812 <6>[ 2.946785] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10663 13:58:03.340336 <6>[ 2.954813] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10664 13:58:03.350214 <4>[ 2.962718] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10665 13:58:03.360159 <6>[ 2.972243] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10666 13:58:03.366654 <6>[ 2.980320] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10667 13:58:03.373313 <6>[ 2.988411] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10668 13:58:03.383339 <6>[ 2.996353] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10669 13:58:03.389786 <6>[ 3.004174] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10670 13:58:03.399582 <6>[ 3.011994] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10671 13:58:03.409614 <6>[ 3.022456] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10672 13:58:03.416187 <6>[ 3.030819] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10673 13:58:03.426165 <6>[ 3.039158] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10674 13:58:03.433012 <6>[ 3.047496] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10675 13:58:03.442784 <6>[ 3.055835] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10676 13:58:03.449377 <6>[ 3.064173] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10677 13:58:03.459072 <6>[ 3.072511] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10678 13:58:03.469067 <6>[ 3.080850] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10679 13:58:03.475591 <6>[ 3.089190] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10680 13:58:03.485504 <6>[ 3.097533] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10681 13:58:03.492177 <6>[ 3.105872] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10682 13:58:03.502310 <6>[ 3.114211] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10683 13:58:03.508840 <6>[ 3.122548] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10684 13:58:03.518987 <6>[ 3.130886] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10685 13:58:03.525134 <6>[ 3.139227] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10686 13:58:03.532033 <6>[ 3.147981] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10687 13:58:03.538546 <6>[ 3.155148] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10688 13:58:03.545198 <6>[ 3.161899] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10689 13:58:03.555209 <6>[ 3.168674] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10690 13:58:03.562102 <6>[ 3.175613] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10691 13:58:03.568636 <6>[ 3.182455] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10692 13:58:03.578816 <6>[ 3.191582] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10693 13:58:03.588413 <6>[ 3.200711] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10694 13:58:03.598618 <6>[ 3.210006] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10695 13:58:03.608231 <6>[ 3.219473] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10696 13:58:03.614965 <6>[ 3.228938] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10697 13:58:03.625137 <6>[ 3.238057] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10698 13:58:03.635656 <6>[ 3.247524] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10699 13:58:03.644892 <6>[ 3.256658] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10700 13:58:03.654584 <6>[ 3.265952] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10701 13:58:03.664436 <6>[ 3.276113] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10702 13:58:03.674593 <6>[ 3.287830] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10703 13:58:03.703748 <6>[ 3.316998] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10704 13:58:03.731232 <6>[ 3.347582] hub 2-1:1.0: USB hub found
10705 13:58:03.734295 <6>[ 3.351996] hub 2-1:1.0: 3 ports detected
10706 13:58:03.742266 <6>[ 3.358838] hub 2-1:1.0: USB hub found
10707 13:58:03.745746 <6>[ 3.363325] hub 2-1:1.0: 3 ports detected
10708 13:58:03.855728 <6>[ 3.468767] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10709 13:58:04.010507 <6>[ 3.626930] hub 1-1:1.0: USB hub found
10710 13:58:04.013542 <6>[ 3.631435] hub 1-1:1.0: 4 ports detected
10711 13:58:04.024103 <6>[ 3.640641] hub 1-1:1.0: USB hub found
10712 13:58:04.027078 <6>[ 3.645140] hub 1-1:1.0: 4 ports detected
10713 13:58:04.095473 <6>[ 3.708850] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10714 13:58:04.347696 <6>[ 3.960892] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10715 13:58:04.480215 <6>[ 4.096667] hub 1-1.4:1.0: USB hub found
10716 13:58:04.483268 <6>[ 4.101321] hub 1-1.4:1.0: 2 ports detected
10717 13:58:04.493465 <6>[ 4.109862] hub 1-1.4:1.0: USB hub found
10718 13:58:04.496607 <6>[ 4.114498] hub 1-1.4:1.0: 2 ports detected
10719 13:58:04.795142 <6>[ 4.408772] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10720 13:58:04.987452 <6>[ 4.600771] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10721 13:58:15.952418 <6>[ 15.573839] ALSA device list:
10722 13:58:15.958798 <6>[ 15.577136] No soundcards found.
10723 13:58:15.967388 <6>[ 15.585281] Freeing unused kernel memory: 8448K
10724 13:58:15.970290 <6>[ 15.590323] Run /init as init process
10725 13:58:16.022714 <6>[ 15.640669] NET: Registered PF_INET6 protocol family
10726 13:58:16.029077 <6>[ 15.646954] Segment Routing with IPv6
10727 13:58:16.032623 <6>[ 15.650922] In-situ OAM (IOAM) with IPv6
10728 13:58:16.066867 <30>[ 15.665244] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10729 13:58:16.069889 <30>[ 15.689165] systemd[1]: Detected architecture arm64.
10730 13:58:16.073226
10731 13:58:16.076553 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10732 13:58:16.076636
10733 13:58:16.090459 <30>[ 15.708785] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10734 13:58:16.226088 <30>[ 15.841057] systemd[1]: Queued start job for default target Graphical Interface.
10735 13:58:16.263441 <30>[ 15.881685] systemd[1]: Created slice system-getty.slice.
10736 13:58:16.270021 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10737 13:58:16.287231 <30>[ 15.905244] systemd[1]: Created slice system-modprobe.slice.
10738 13:58:16.293828 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10739 13:58:16.311446 <30>[ 15.929425] systemd[1]: Created slice system-serial\x2dgetty.slice.
10740 13:58:16.321179 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10741 13:58:16.334976 <30>[ 15.953310] systemd[1]: Created slice User and Session Slice.
10742 13:58:16.341825 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10743 13:58:16.362402 <30>[ 15.977373] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10744 13:58:16.372315 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10745 13:58:16.390376 <30>[ 16.005423] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10746 13:58:16.397389 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10747 13:58:16.421617 <30>[ 16.033229] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10748 13:58:16.428595 <30>[ 16.045492] systemd[1]: Reached target Local Encrypted Volumes.
10749 13:58:16.434918 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10750 13:58:16.451556 <30>[ 16.069332] systemd[1]: Reached target Paths.
10751 13:58:16.454693 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10752 13:58:16.470610 <30>[ 16.088809] systemd[1]: Reached target Remote File Systems.
10753 13:58:16.477352 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10754 13:58:16.495036 <30>[ 16.113143] systemd[1]: Reached target Slices.
10755 13:58:16.501346 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10756 13:58:16.514942 <30>[ 16.132839] systemd[1]: Reached target Swap.
10757 13:58:16.518056 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10758 13:58:16.538332 <30>[ 16.153348] systemd[1]: Listening on initctl Compatibility Named Pipe.
10759 13:58:16.545293 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10760 13:58:16.551605 <30>[ 16.168701] systemd[1]: Listening on Journal Audit Socket.
10761 13:58:16.558255 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10762 13:58:16.570887 <30>[ 16.189344] systemd[1]: Listening on Journal Socket (/dev/log).
10763 13:58:16.577798 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10764 13:58:16.596226 <30>[ 16.214104] systemd[1]: Listening on Journal Socket.
10765 13:58:16.602689 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10766 13:58:16.618854 <30>[ 16.233594] systemd[1]: Listening on Network Service Netlink Socket.
10767 13:58:16.625347 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10768 13:58:16.640260 <30>[ 16.258115] systemd[1]: Listening on udev Control Socket.
10769 13:58:16.646463 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10770 13:58:16.663594 <30>[ 16.281938] systemd[1]: Listening on udev Kernel Socket.
10771 13:58:16.670416 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10772 13:58:16.710827 <30>[ 16.328941] systemd[1]: Mounting Huge Pages File System...
10773 13:58:16.717421 Mounting [0;1;39mHuge Pages File System[0m...
10774 13:58:16.734969 <30>[ 16.353008] systemd[1]: Mounting POSIX Message Queue File System...
10775 13:58:16.741901 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10776 13:58:16.790588 <30>[ 16.408954] systemd[1]: Mounting Kernel Debug File System...
10777 13:58:16.797519 Mounting [0;1;39mKernel Debug File System[0m...
10778 13:58:16.813908 <30>[ 16.428916] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10779 13:58:16.827295 <30>[ 16.442387] systemd[1]: Starting Create list of static device nodes for the current kernel...
10780 13:58:16.833964 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10781 13:58:16.855631 <30>[ 16.473696] systemd[1]: Starting Load Kernel Module configfs...
10782 13:58:16.861877 Starting [0;1;39mLoad Kernel Module configfs[0m...
10783 13:58:16.879275 <30>[ 16.497299] systemd[1]: Starting Load Kernel Module drm...
10784 13:58:16.885609 Starting [0;1;39mLoad Kernel Module drm[0m...
10785 13:58:16.901902 <30>[ 16.516859] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10786 13:58:16.938959 <30>[ 16.557290] systemd[1]: Starting Journal Service...
10787 13:58:16.942437 Starting [0;1;39mJournal Service[0m...
10788 13:58:16.961629 <30>[ 16.579782] systemd[1]: Starting Load Kernel Modules...
10789 13:58:16.967981 Starting [0;1;39mLoad Kernel Modules[0m...
10790 13:58:16.987992 <30>[ 16.603001] systemd[1]: Starting Remount Root and Kernel File Systems...
10791 13:58:16.994357 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10792 13:58:17.010424 <30>[ 16.628177] systemd[1]: Starting Coldplug All udev Devices...
10793 13:58:17.016816 Starting [0;1;39mColdplug All udev Devices[0m...
10794 13:58:17.033829 <30>[ 16.652103] systemd[1]: Started Journal Service.
10795 13:58:17.040267 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10796 13:58:17.057714 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10797 13:58:17.075363 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10798 13:58:17.091744 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10799 13:58:17.112498 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10800 13:58:17.129141 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10801 13:58:17.148596 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10802 13:58:17.169346 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10803 13:58:17.189172 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10804 13:58:17.202960 See 'systemctl status systemd-remount-fs.service' for details.
10805 13:58:17.247755 Mounting [0;1;39mKernel Configuration File System[0m...
10806 13:58:17.272144 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10807 13:58:17.284853 <46>[ 16.899890] systemd-journald[175]: Received client request to flush runtime journal.
10808 13:58:17.296214 Starting [0;1;39mLoad/Save Random Seed[0m...
10809 13:58:17.317668 Starting [0;1;39mApply Kernel Variables[0m...
10810 13:58:17.335692 Starting [0;1;39mCreate System Users[0m...
10811 13:58:17.356784 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10812 13:58:17.371908 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10813 13:58:17.395589 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10814 13:58:17.408410 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10815 13:58:17.424541 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10816 13:58:17.438907 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10817 13:58:17.491156 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10818 13:58:17.511860 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10819 13:58:17.527250 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10820 13:58:17.546901 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10821 13:58:17.599459 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10822 13:58:17.626753 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10823 13:58:17.647273 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10824 13:58:17.673557 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10825 13:58:17.728680 Starting [0;1;39mNetwork Service[0m...
10826 13:58:17.751281 Starting [0;1;39mNetwork Time Synchronization[0m...
10827 13:58:17.773475 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10828 13:58:17.811373 <6>[ 17.426471] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10829 13:58:17.814743 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10830 13:58:17.824676 <6>[ 17.439162] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10831 13:58:17.828009 <6>[ 17.440433] remoteproc remoteproc0: scp is available
10832 13:58:17.838267 <6>[ 17.447788] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10833 13:58:17.844570 <6>[ 17.453714] remoteproc remoteproc0: powering up scp
10834 13:58:17.851030 <6>[ 17.461388] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10835 13:58:17.861333 <6>[ 17.467862] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10836 13:58:17.867830 <6>[ 17.483834] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10837 13:58:17.874401 <3>[ 17.488004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 13:58:17.884313 [[0;32m OK [<3>[ 17.497894] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 13:58:17.894387 0m] Started [0;<3>[ 17.507861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 13:58:17.897579 1;39mNetwork Time Synchronization[0m.
10841 13:58:17.907530 <3>[ 17.522214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 13:58:17.913920 <3>[ 17.530405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 13:58:17.924301 <3>[ 17.538498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 13:58:17.930816 <3>[ 17.538506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10845 13:58:17.940454 <3>[ 17.538512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 13:58:17.947352 [[0;32m OK [0m] Found device<6>[ 17.565481] mc: Linux media interface: v0.10
10847 13:58:17.953714 <6>[ 17.568544] usbcore: registered new device driver r8152-cfgselector
10848 13:58:17.963755 [0;1;39m/dev/t<3>[ 17.576905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 13:58:17.963842 tyS0[0m.
10850 13:58:17.973525 <3>[ 17.587554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 13:58:17.980123 <4>[ 17.587756] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10852 13:58:17.987042 <3>[ 17.595834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 13:58:17.996714 <3>[ 17.611172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 13:58:18.003486 <6>[ 17.611843] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10855 13:58:18.010342 <4>[ 17.611873] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10856 13:58:18.019969 <6>[ 17.619357] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10857 13:58:18.026736 <6>[ 17.619370] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10858 13:58:18.033577 <3>[ 17.619786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10859 13:58:18.043418 <3>[ 17.619794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 13:58:18.049842 <3>[ 17.619797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 13:58:18.056555 <3>[ 17.619802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 13:58:18.066659 <3>[ 17.619805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 13:58:18.074008 <3>[ 17.619833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 13:58:18.080851 <6>[ 17.620184] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10865 13:58:18.087485 <6>[ 17.626485] pci_bus 0000:00: root bus resource [bus 00-ff]
10866 13:58:18.094074 <6>[ 17.631603] videodev: Linux video capture interface: v2.00
10867 13:58:18.100908 <6>[ 17.633557] remoteproc remoteproc0: remote processor scp is now up
10868 13:58:18.107624 <4>[ 17.646953] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10869 13:58:18.113929 <4>[ 17.646953] Fallback method does not support PEC.
10870 13:58:18.120704 <6>[ 17.649123] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10871 13:58:18.130601 <6>[ 17.661036] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10872 13:58:18.140598 <6>[ 17.665590] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10873 13:58:18.150531 <6>[ 17.674370] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10874 13:58:18.157285 <6>[ 17.681615] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10875 13:58:18.163555 <3>[ 17.698559] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 13:58:18.173318 <6>[ 17.705843] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10877 13:58:18.180042 <6>[ 17.717422] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10878 13:58:18.187277 <6>[ 17.723496] pci 0000:00:00.0: supports D1 D2
10879 13:58:18.193998 <6>[ 17.723506] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10880 13:58:18.203916 <6>[ 17.738288] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10881 13:58:18.210596 <6>[ 17.744223] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10882 13:58:18.216984 <6>[ 17.745674] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10883 13:58:18.227545 <6>[ 17.758212] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10884 13:58:18.234340 <4>[ 17.760324] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10885 13:58:18.244844 <4>[ 17.760332] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10886 13:58:18.247899 <6>[ 17.764549] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10887 13:58:18.254974 <6>[ 17.765120] Bluetooth: Core ver 2.22
10888 13:58:18.257946 <6>[ 17.765187] NET: Registered PF_BLUETOOTH protocol family
10889 13:58:18.264581 <6>[ 17.765190] Bluetooth: HCI device and connection manager initialized
10890 13:58:18.271373 <6>[ 17.765208] Bluetooth: HCI socket layer initialized
10891 13:58:18.274663 <6>[ 17.765213] Bluetooth: L2CAP socket layer initialized
10892 13:58:18.281747 <6>[ 17.765219] Bluetooth: SCO socket layer initialized
10893 13:58:18.288653 <6>[ 17.805116] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10894 13:58:18.295246 <6>[ 17.808839] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10895 13:58:18.308685 <6>[ 17.819201] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10896 13:58:18.311972 <6>[ 17.820584] r8152 2-1.3:1.0 eth0: v1.12.13
10897 13:58:18.318319 <6>[ 17.820656] usbcore: registered new interface driver r8152
10898 13:58:18.325004 <6>[ 17.826370] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10899 13:58:18.331939 <6>[ 17.827102] usbcore: registered new interface driver btusb
10900 13:58:18.341850 <4>[ 17.828325] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10901 13:58:18.348296 <3>[ 17.828337] Bluetooth: hci0: Failed to load firmware file (-2)
10902 13:58:18.355050 <3>[ 17.828358] Bluetooth: hci0: Failed to set up firmware (-2)
10903 13:58:18.364964 <4>[ 17.828362] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10904 13:58:18.371290 <6>[ 17.833456] usbcore: registered new interface driver uvcvideo
10905 13:58:18.378362 <6>[ 17.841485] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10906 13:58:18.384873 <6>[ 17.841846] usbcore: registered new interface driver cdc_ether
10907 13:58:18.391279 <6>[ 17.850043] usbcore: registered new interface driver r8153_ecm
10908 13:58:18.394398 <6>[ 17.858880] pci 0000:01:00.0: supports D1 D2
10909 13:58:18.401046 <6>[ 17.859472] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10910 13:58:18.407948 <3>[ 17.861351] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10911 13:58:18.417967 <3>[ 17.863902] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 13:58:18.428122 <3>[ 17.870263] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 13:58:18.434292 <6>[ 17.873114] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10914 13:58:18.441061 <6>[ 17.885003] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10915 13:58:18.447470 <3>[ 17.889160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10916 13:58:18.454178 <6>[ 17.892672] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10917 13:58:18.464185 <6>[ 17.892705] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10918 13:58:18.471020 <6>[ 17.892708] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10919 13:58:18.480783 <6>[ 17.892716] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10920 13:58:18.486999 <6>[ 17.892729] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10921 13:58:18.494121 <6>[ 17.892742] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10922 13:58:18.500368 <6>[ 17.892754] pci 0000:00:00.0: PCI bridge to [bus 01]
10923 13:58:18.507115 <6>[ 17.892759] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10924 13:58:18.513613 <6>[ 17.892908] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10925 13:58:18.520474 <6>[ 17.893430] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10926 13:58:18.527359 <6>[ 17.893912] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10927 13:58:18.536720 <3>[ 17.909948] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 13:58:18.543878 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10929 13:58:18.557041 <5>[ 18.171139] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10930 13:58:18.567245 [[0;32m OK [<3>[ 18.181351] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 13:58:18.573729 <5>[ 18.189951] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10932 13:58:18.584031 0m] Reached targ<5>[ 18.197803] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10933 13:58:18.593905 et [0;1;39mSyst<4>[ 18.207273] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10934 13:58:18.603908 em Time Set[0m.<3>[ 18.211158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 13:58:18.610670 <6>[ 18.217457] cfg80211: failed to load regulatory.db
10936 13:58:18.610762
10937 13:58:18.633555 <3>[ 18.248639] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 13:58:18.640297 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10939 13:58:18.660893 <6>[ 18.275186] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10940 13:58:18.664440 <6>[ 18.282686] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10941 13:58:18.674378 <3>[ 18.284166] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 13:58:18.691698 Startin<6>[ 18.309381] mt7921e 0000:01:00.0: ASIC revision: 79610010
10943 13:58:18.698638 g [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10944 13:58:18.720299 Starting [0;1;39mNetwork Name Resolution[0m...
10945 13:58:18.737536 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10946 13:58:18.760619 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10947 13:58:18.777434 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10948 13:58:18.793232 <6>[ 18.408084] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10949 13:58:18.793330 <6>[ 18.408084]
10950 13:58:18.912747 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10951 13:58:18.926297 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10952 13:58:18.945475 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10953 13:58:18.958867 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10954 13:58:18.978176 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10955 13:58:18.993913 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10956 13:58:19.006465 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10957 13:58:19.026526 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10958 13:58:19.042686 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10959 13:58:19.060263 <6>[ 18.675348] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10960 13:58:19.067101 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10961 13:58:19.090738 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10962 13:58:19.135698 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10963 13:58:19.169920 Starting [0;1;39mUser Login Management[0m...
10964 13:58:19.188180 Starting [0;1;39mPermit User Sessions[0m...
10965 13:58:19.206473 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10966 13:58:19.219706 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10967 13:58:19.243482 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10968 13:58:19.262918 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10969 13:58:19.287289 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10970 13:58:19.307383 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10971 13:58:19.328141 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10972 13:58:19.348301 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10973 13:58:19.362931 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10974 13:58:19.415375 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10975 13:58:19.448859 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10976 13:58:19.498773
10977 13:58:19.498888
10978 13:58:19.502085 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10979 13:58:19.502169
10980 13:58:19.505290 debian-bullseye-arm64 login: root (automatic login)
10981 13:58:19.505374
10982 13:58:19.505439
10983 13:58:19.520939 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
10984 13:58:19.521030
10985 13:58:19.527684 The programs included with the Debian GNU/Linux system are free software;
10986 13:58:19.534078 the exact distribution terms for each program are described in the
10987 13:58:19.537741 individual files in /usr/share/doc/*/copyright.
10988 13:58:19.537825
10989 13:58:19.544378 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10990 13:58:19.547588 permitted by applicable law.
10991 13:58:19.547967 Matched prompt #10: / #
10993 13:58:19.548172 Setting prompt string to ['/ #']
10994 13:58:19.548266 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10996 13:58:19.548454 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10997 13:58:19.548545 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
10998 13:58:19.548612 Setting prompt string to ['/ #']
10999 13:58:19.548673 Forcing a shell prompt, looking for ['/ #']
11001 13:58:19.598857 / #
11002 13:58:19.598989 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11003 13:58:19.599071 Waiting using forced prompt support (timeout 00:02:30)
11004 13:58:19.603668
11005 13:58:19.603948 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11006 13:58:19.604043 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11007 13:58:19.604137 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11008 13:58:19.604225 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11009 13:58:19.604307 end: 2 depthcharge-action (duration 00:01:30) [common]
11010 13:58:19.604393 start: 3 lava-test-retry (timeout 00:08:11) [common]
11011 13:58:19.604478 start: 3.1 lava-test-shell (timeout 00:08:11) [common]
11012 13:58:19.604549 Using namespace: common
11014 13:58:19.704953 / # #
11015 13:58:19.705098 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11016 13:58:19.709806 #
11017 13:58:19.710093 Using /lava-12682956
11019 13:58:19.810455 / # export SHELL=/bin/sh
11020 13:58:19.815956 export SHELL=/bin/sh
11022 13:58:19.916500 / # . /lava-12682956/environment
11023 13:58:19.916687 <6>[ 19.474836] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11024 13:58:19.916777 <6>[ 19.482630] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11025 13:58:19.916845 . /lava-12682956/environment<6>[ 19.522933] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11026 13:58:19.921485
11028 13:58:20.022099 / # /lava-12682956/bin/lava-test-runner /lava-12682956/0
11029 13:58:20.022238 Test shell timeout: 10s (minimum of the action and connection timeout)
11030 13:58:20.027647 /lava-12682956/bin/lava-test-runner /lava-12682956/0
11031 13:58:20.051799 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11032 13:58:20.058614 + cd /lava-12682956/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11033 13:58:20.058710 + cat uuid
11034 13:58:20.061870 + UUID=12682956_1.5.2.3.1
11035 13:58:20.062025 + set +x
11036 13:58:20.068321 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12682956_1.5.2.3.1>
11037 13:58:20.068618 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12682956_1.5.2.3.1
11038 13:58:20.068720 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12682956_1.5.2.3.1)
11039 13:58:20.068837 Skipping test definition patterns.
11040 13:58:20.071556 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11041 13:58:20.078043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11042 13:58:20.078294 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11044 13:58:20.087847 device: /dev/video2<4>[ 19.701123] use of bytesused == 0 is deprecated and will be removed in the future,
11045 13:58:20.087956
11046 13:58:20.091559 <4>[ 19.710309] use the actual size instead.
11047 13:58:20.105609 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11048 13:58:20.115857 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11049 13:58:20.122360
11050 13:58:20.135879 Compliance test for mtk-vcodec-enc device /dev/video2:
11051 13:58:20.141643
11052 13:58:20.153858 Driver Info:
11053 13:58:20.168789 Driver name : mtk-vcodec-enc
11054 13:58:20.184040 Card type : MT8192 video encoder
11055 13:58:20.194773 Bus info : platform:17020000.vcodec
11056 13:58:20.202235 Driver version : 6.1.72
11057 13:58:20.212535 Capabilities : 0x84204000
11058 13:58:20.227529 Video Memory-to-Memory Multiplanar
11059 13:58:20.238571 Streaming
11060 13:58:20.248143 Extended Pix Format
11061 13:58:20.262985 Device Capabilities
11062 13:58:20.273721 Device Caps : 0x04204000
11063 13:58:20.287049 Video Memory-to-Memory Multiplanar
11064 13:58:20.298449 Streaming
11065 13:58:20.308673 Extended Pix Format
11066 13:58:20.325554 Detected Stateful Encoder
11067 13:58:20.335479
11068 13:58:20.351421 Required ioctls:
11069 13:58:20.366142 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11070 13:58:20.366237 test VIDIOC_QUERYCAP: OK
11071 13:58:20.366479 Received signal: <TESTSET> START Required-ioctls
11072 13:58:20.366555 Starting test_set Required-ioctls
11073 13:58:20.393467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11074 13:58:20.393729 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11076 13:58:20.396379 test invalid ioctls: OK
11077 13:58:20.419948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11078 13:58:20.420075
11079 13:58:20.420312 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11081 13:58:20.430949 Allow for multiple opens:
11082 13:58:20.438592 <LAVA_SIGNAL_TESTSET STOP>
11083 13:58:20.438846 Received signal: <TESTSET> STOP
11084 13:58:20.438921 Closing test_set Required-ioctls
11085 13:58:20.447605 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11086 13:58:20.447862 Received signal: <TESTSET> START Allow-for-multiple-opens
11087 13:58:20.447936 Starting test_set Allow-for-multiple-opens
11088 13:58:20.450827 test second /dev/video2 open: OK
11089 13:58:20.472548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11090 13:58:20.472814 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11092 13:58:20.475845 test VIDIOC_QUERYCAP: OK
11093 13:58:20.497372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11094 13:58:20.497670 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11096 13:58:20.500416 test VIDIOC_G/S_PRIORITY: OK
11097 13:58:20.521440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11098 13:58:20.521712 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11100 13:58:20.524562 test for unlimited opens: OK
11101 13:58:20.547164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11102 13:58:20.547256
11103 13:58:20.547491 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11105 13:58:20.558343 Debug ioctls:
11106 13:58:20.565821 <LAVA_SIGNAL_TESTSET STOP>
11107 13:58:20.566104 Received signal: <TESTSET> STOP
11108 13:58:20.566178 Closing test_set Allow-for-multiple-opens
11109 13:58:20.575199 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11110 13:58:20.575454 Received signal: <TESTSET> START Debug-ioctls
11111 13:58:20.575527 Starting test_set Debug-ioctls
11112 13:58:20.578332 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11113 13:58:20.598931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11114 13:58:20.599186 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11116 13:58:20.605498 test VIDIOC_LOG_STATUS: OK (Not Supported)
11117 13:58:20.624234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11118 13:58:20.624325
11119 13:58:20.624562 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11121 13:58:20.640592 Input ioctls:
11122 13:58:20.647190 <LAVA_SIGNAL_TESTSET STOP>
11123 13:58:20.647445 Received signal: <TESTSET> STOP
11124 13:58:20.647514 Closing test_set Debug-ioctls
11125 13:58:20.656914 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11126 13:58:20.657171 Received signal: <TESTSET> START Input-ioctls
11127 13:58:20.657243 Starting test_set Input-ioctls
11128 13:58:20.660224 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11129 13:58:20.684534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11130 13:58:20.684791 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11132 13:58:20.687709 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11133 13:58:20.705851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11134 13:58:20.706160 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11136 13:58:20.712099 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11137 13:58:20.733226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11138 13:58:20.733481 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11140 13:58:20.739821 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11141 13:58:20.757624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11142 13:58:20.757907 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11144 13:58:20.760532 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11145 13:58:20.782482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11146 13:58:20.782736 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11148 13:58:20.785742 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11149 13:58:20.806921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11150 13:58:20.807175 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11152 13:58:20.810312 Inputs: 0 Audio Inputs: 0 Tuners: 0
11153 13:58:20.818240
11154 13:58:20.837556 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11155 13:58:20.862746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11156 13:58:20.863008 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11158 13:58:20.868866 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11159 13:58:20.888541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11160 13:58:20.888823 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11162 13:58:20.894922 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11163 13:58:20.918540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11164 13:58:20.918896 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11166 13:58:20.924997 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11167 13:58:20.941958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11168 13:58:20.942255 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11170 13:58:20.948388 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11171 13:58:20.967357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11172 13:58:20.967473
11173 13:58:20.967746 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11175 13:58:20.986760 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11176 13:58:21.008363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11177 13:58:21.008655 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11179 13:58:21.014773 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11180 13:58:21.036238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11181 13:58:21.036512 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11183 13:58:21.039610 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11184 13:58:21.060363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11185 13:58:21.060644 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11187 13:58:21.067272 test VIDIOC_G/S_EDID: OK (Not Supported)
11188 13:58:21.084918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11189 13:58:21.085116
11190 13:58:21.085432 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11192 13:58:21.095652 Control ioctls:
11193 13:58:21.103097 <LAVA_SIGNAL_TESTSET STOP>
11194 13:58:21.103391 Received signal: <TESTSET> STOP
11195 13:58:21.103464 Closing test_set Input-ioctls
11196 13:58:21.112853 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11197 13:58:21.113196 Received signal: <TESTSET> START Control-ioctls
11198 13:58:21.113271 Starting test_set Control-ioctls
11199 13:58:21.115944 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11200 13:58:21.142246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11201 13:58:21.142411 test VIDIOC_QUERYCTRL: OK
11202 13:58:21.142674 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11204 13:58:21.164060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11205 13:58:21.164388 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11207 13:58:21.167328 test VIDIOC_G/S_CTRL: OK
11208 13:58:21.196436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11209 13:58:21.196779 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11211 13:58:21.199307 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11212 13:58:21.221802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11213 13:58:21.222122 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11215 13:58:21.231392 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11216 13:58:21.235108 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11217 13:58:21.260752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11218 13:58:21.261086 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11220 13:58:21.264002 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11221 13:58:21.280537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11222 13:58:21.280859 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11224 13:58:21.283814 Standard Controls: 16 Private Controls: 0
11225 13:58:21.291384
11226 13:58:21.304118 Format ioctls:
11227 13:58:21.313009 <LAVA_SIGNAL_TESTSET STOP>
11228 13:58:21.313346 Received signal: <TESTSET> STOP
11229 13:58:21.313486 Closing test_set Control-ioctls
11230 13:58:21.322436 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11231 13:58:21.322784 Received signal: <TESTSET> START Format-ioctls
11232 13:58:21.322913 Starting test_set Format-ioctls
11233 13:58:21.325541 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11234 13:58:21.350908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11235 13:58:21.351232 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11237 13:58:21.354173 test VIDIOC_G/S_PARM: OK
11238 13:58:21.372771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11239 13:58:21.373089 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11241 13:58:21.376017 test VIDIOC_G_FBUF: OK (Not Supported)
11242 13:58:21.398975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11243 13:58:21.399309 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11245 13:58:21.402109 test VIDIOC_G_FMT: OK
11246 13:58:21.423173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11247 13:58:21.423505 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11249 13:58:21.426757 test VIDIOC_TRY_FMT: OK
11250 13:58:21.447267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11251 13:58:21.447556 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11253 13:58:21.457473 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11254 13:58:21.460722 test VIDIOC_S_FMT: FAIL
11255 13:58:21.484426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11256 13:58:21.484742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11258 13:58:21.487714 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11259 13:58:21.517029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11260 13:58:21.517347 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11262 13:58:21.520443 test Cropping: OK
11263 13:58:21.542915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11264 13:58:21.543216 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11266 13:58:21.546007 test Composing: OK (Not Supported)
11267 13:58:21.565554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11268 13:58:21.565827 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11270 13:58:21.568795 test Scaling: OK (Not Supported)
11271 13:58:21.589125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11272 13:58:21.589255
11273 13:58:21.589503 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11275 13:58:21.598053 Codec ioctls:
11276 13:58:21.605371 <LAVA_SIGNAL_TESTSET STOP>
11277 13:58:21.605647 Received signal: <TESTSET> STOP
11278 13:58:21.605719 Closing test_set Format-ioctls
11279 13:58:21.615059 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11280 13:58:21.615320 Received signal: <TESTSET> START Codec-ioctls
11281 13:58:21.615393 Starting test_set Codec-ioctls
11282 13:58:21.618589 test VIDIOC_(TRY_)ENCODER_CMD: OK
11283 13:58:21.639486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11284 13:58:21.639750 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11286 13:58:21.646366 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11287 13:58:21.665048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11288 13:58:21.665322 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11290 13:58:21.671137 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11291 13:58:21.690658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11292 13:58:21.690794
11293 13:58:21.691038 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11295 13:58:21.701422 Buffer ioctls:
11296 13:58:21.708672 <LAVA_SIGNAL_TESTSET STOP>
11297 13:58:21.708956 Received signal: <TESTSET> STOP
11298 13:58:21.709058 Closing test_set Codec-ioctls
11299 13:58:21.718550 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11300 13:58:21.718811 Received signal: <TESTSET> START Buffer-ioctls
11301 13:58:21.718883 Starting test_set Buffer-ioctls
11302 13:58:21.721551 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11303 13:58:21.747555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11304 13:58:21.747660 test VIDIOC_EXPBUF: OK
11305 13:58:21.747925 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11307 13:58:21.768472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11308 13:58:21.768787 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11310 13:58:21.771634 test Requests: OK (Not Supported)
11311 13:58:21.794163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11312 13:58:21.794300
11313 13:58:21.794564 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11315 13:58:21.807336 Test input 0:
11316 13:58:21.820976
11317 13:58:21.838238 Streaming ioctls:
11318 13:58:21.844601 <LAVA_SIGNAL_TESTSET STOP>
11319 13:58:21.844868 Received signal: <TESTSET> STOP
11320 13:58:21.844942 Closing test_set Buffer-ioctls
11321 13:58:21.853894 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11322 13:58:21.854166 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11323 13:58:21.854245 Starting test_set Streaming-ioctls_Test-input-0
11324 13:58:21.857230 test read/write: OK (Not Supported)
11325 13:58:21.880501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11326 13:58:21.880809 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11328 13:58:21.887032 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11329 13:58:21.902943 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11330 13:58:21.921436 test blocking wait: FAIL
11331 13:58:21.960254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11332 13:58:21.960668 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11334 13:58:21.970174 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11335 13:58:21.970376 test MMAP (select): FAIL
11336 13:58:22.000339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11337 13:58:22.000661 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11339 13:58:22.006703 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11340 13:58:22.013117 test MMAP (epoll): FAIL
11341 13:58:22.037115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11342 13:58:22.037475 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11344 13:58:22.046659 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11345 13:58:22.053099 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11346 13:58:22.057462 test USERPTR (select): FAIL
11347 13:58:22.082374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11348 13:58:22.082706 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11350 13:58:22.089274 test DMABUF: Cannot test, specify --expbuf-device
11351 13:58:22.092594
11352 13:58:22.108861 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11353 13:58:22.112131 <LAVA_TEST_RUNNER EXIT>
11354 13:58:22.112400 ok: lava_test_shell seems to have completed
11355 13:58:22.112476 Marking unfinished test run as failed
11357 13:58:22.113406 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11358 13:58:22.113535 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11359 13:58:22.113626 end: 3 lava-test-retry (duration 00:00:03) [common]
11360 13:58:22.113713 start: 4 finalize (timeout 00:08:08) [common]
11361 13:58:22.113810 start: 4.1 power-off (timeout 00:00:30) [common]
11362 13:58:22.113976 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11363 13:58:22.190488 >> Command sent successfully.
11364 13:58:22.192920 Returned 0 in 0 seconds
11365 13:58:22.293327 end: 4.1 power-off (duration 00:00:00) [common]
11367 13:58:22.293659 start: 4.2 read-feedback (timeout 00:08:08) [common]
11368 13:58:22.293925 Listened to connection for namespace 'common' for up to 1s
11369 13:58:23.294033 Finalising connection for namespace 'common'
11370 13:58:23.294199 Disconnecting from shell: Finalise
11371 13:58:23.294285 / #
11372 13:58:23.394583 end: 4.2 read-feedback (duration 00:00:01) [common]
11373 13:58:23.394746 end: 4 finalize (duration 00:00:01) [common]
11374 13:58:23.394879 Cleaning after the job
11375 13:58:23.394979 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/ramdisk
11376 13:58:23.399400 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/kernel
11377 13:58:23.406104 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/dtb
11378 13:58:23.406290 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682956/tftp-deploy-melxan2z/modules
11379 13:58:23.411829 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682956
11380 13:58:23.466598 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682956
11381 13:58:23.466772 Job finished correctly