Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 16
- Kernel Errors: 32
1 13:59:20.543427 lava-dispatcher, installed at version: 2023.10
2 13:59:20.543651 start: 0 validate
3 13:59:20.543808 Start time: 2024-02-01 13:59:20.543796+00:00 (UTC)
4 13:59:20.543947 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:59:20.544084 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:59:20.804078 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:59:20.804289 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:59:21.064004 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:59:21.064182 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:59:21.334823 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:59:21.335002 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:59:21.602667 validate duration: 1.06
14 13:59:21.602945 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:59:21.603040 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:59:21.603130 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:59:21.603256 Not decompressing ramdisk as can be used compressed.
18 13:59:21.603343 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 13:59:21.603410 saving as /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/ramdisk/rootfs.cpio.gz
20 13:59:21.603476 total size: 26246609 (25 MB)
21 13:59:21.604546 progress 0 % (0 MB)
22 13:59:21.611885 progress 5 % (1 MB)
23 13:59:21.618998 progress 10 % (2 MB)
24 13:59:21.626308 progress 15 % (3 MB)
25 13:59:21.633519 progress 20 % (5 MB)
26 13:59:21.640916 progress 25 % (6 MB)
27 13:59:21.648151 progress 30 % (7 MB)
28 13:59:21.655583 progress 35 % (8 MB)
29 13:59:21.662692 progress 40 % (10 MB)
30 13:59:21.669759 progress 45 % (11 MB)
31 13:59:21.676814 progress 50 % (12 MB)
32 13:59:21.683951 progress 55 % (13 MB)
33 13:59:21.691018 progress 60 % (15 MB)
34 13:59:21.698081 progress 65 % (16 MB)
35 13:59:21.705155 progress 70 % (17 MB)
36 13:59:21.712358 progress 75 % (18 MB)
37 13:59:21.719520 progress 80 % (20 MB)
38 13:59:21.726460 progress 85 % (21 MB)
39 13:59:21.733228 progress 90 % (22 MB)
40 13:59:21.740149 progress 95 % (23 MB)
41 13:59:21.747053 progress 100 % (25 MB)
42 13:59:21.747328 25 MB downloaded in 0.14 s (174.01 MB/s)
43 13:59:21.747491 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:59:21.747735 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:59:21.747823 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:59:21.747905 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:59:21.748042 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:59:21.748116 saving as /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/kernel/Image
50 13:59:21.748177 total size: 51532288 (49 MB)
51 13:59:21.748237 No compression specified
52 13:59:21.749391 progress 0 % (0 MB)
53 13:59:21.763033 progress 5 % (2 MB)
54 13:59:21.776792 progress 10 % (4 MB)
55 13:59:21.791240 progress 15 % (7 MB)
56 13:59:21.805364 progress 20 % (9 MB)
57 13:59:21.819060 progress 25 % (12 MB)
58 13:59:21.832605 progress 30 % (14 MB)
59 13:59:21.846245 progress 35 % (17 MB)
60 13:59:21.860413 progress 40 % (19 MB)
61 13:59:21.874003 progress 45 % (22 MB)
62 13:59:21.887644 progress 50 % (24 MB)
63 13:59:21.901819 progress 55 % (27 MB)
64 13:59:21.915634 progress 60 % (29 MB)
65 13:59:21.929438 progress 65 % (31 MB)
66 13:59:21.943090 progress 70 % (34 MB)
67 13:59:21.956636 progress 75 % (36 MB)
68 13:59:21.970299 progress 80 % (39 MB)
69 13:59:21.983970 progress 85 % (41 MB)
70 13:59:21.997611 progress 90 % (44 MB)
71 13:59:22.011105 progress 95 % (46 MB)
72 13:59:22.024429 progress 100 % (49 MB)
73 13:59:22.024675 49 MB downloaded in 0.28 s (177.74 MB/s)
74 13:59:22.024830 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:59:22.025063 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:59:22.025148 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:59:22.025234 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:59:22.025376 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:59:22.025449 saving as /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/dtb/mt8192-asurada-spherion-r0.dtb
81 13:59:22.025561 total size: 47278 (0 MB)
82 13:59:22.025623 No compression specified
83 13:59:22.026757 progress 69 % (0 MB)
84 13:59:22.027065 progress 100 % (0 MB)
85 13:59:22.027220 0 MB downloaded in 0.00 s (27.22 MB/s)
86 13:59:22.027341 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:59:22.027579 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:59:22.027712 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:59:22.027793 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:59:22.027910 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:59:22.027980 saving as /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/modules/modules.tar
93 13:59:22.028043 total size: 8623988 (8 MB)
94 13:59:22.028103 Using unxz to decompress xz
95 13:59:22.032338 progress 0 % (0 MB)
96 13:59:22.054182 progress 5 % (0 MB)
97 13:59:22.078423 progress 10 % (0 MB)
98 13:59:22.103106 progress 15 % (1 MB)
99 13:59:22.127138 progress 20 % (1 MB)
100 13:59:22.152201 progress 25 % (2 MB)
101 13:59:22.179852 progress 30 % (2 MB)
102 13:59:22.208456 progress 35 % (2 MB)
103 13:59:22.232398 progress 40 % (3 MB)
104 13:59:22.257843 progress 45 % (3 MB)
105 13:59:22.285065 progress 50 % (4 MB)
106 13:59:22.311701 progress 55 % (4 MB)
107 13:59:22.339495 progress 60 % (4 MB)
108 13:59:22.372088 progress 65 % (5 MB)
109 13:59:22.400944 progress 70 % (5 MB)
110 13:59:22.426875 progress 75 % (6 MB)
111 13:59:22.456925 progress 80 % (6 MB)
112 13:59:22.486382 progress 85 % (7 MB)
113 13:59:22.515404 progress 90 % (7 MB)
114 13:59:22.551948 progress 95 % (7 MB)
115 13:59:22.583911 progress 100 % (8 MB)
116 13:59:22.589289 8 MB downloaded in 0.56 s (14.65 MB/s)
117 13:59:22.589579 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:59:22.589851 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:59:22.589947 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:59:22.590044 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:59:22.590127 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:59:22.590227 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:59:22.590479 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp
125 13:59:22.590618 makedir: /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin
126 13:59:22.590725 makedir: /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/tests
127 13:59:22.590826 makedir: /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/results
128 13:59:22.590948 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-add-keys
129 13:59:22.591100 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-add-sources
130 13:59:22.591235 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-background-process-start
131 13:59:22.591369 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-background-process-stop
132 13:59:22.591498 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-common-functions
133 13:59:22.591627 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-echo-ipv4
134 13:59:22.591759 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-install-packages
135 13:59:22.591886 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-installed-packages
136 13:59:22.592013 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-os-build
137 13:59:22.592144 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-probe-channel
138 13:59:22.592272 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-probe-ip
139 13:59:22.592399 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-target-ip
140 13:59:22.592527 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-target-mac
141 13:59:22.592654 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-target-storage
142 13:59:22.592787 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-test-case
143 13:59:22.592919 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-test-event
144 13:59:22.593057 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-test-feedback
145 13:59:22.593229 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-test-raise
146 13:59:22.593408 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-test-reference
147 13:59:22.593575 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-test-runner
148 13:59:22.593717 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-test-set
149 13:59:22.593866 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-test-shell
150 13:59:22.594001 Updating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-install-packages (oe)
151 13:59:22.594168 Updating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/bin/lava-installed-packages (oe)
152 13:59:22.594307 Creating /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/environment
153 13:59:22.594414 LAVA metadata
154 13:59:22.594508 - LAVA_JOB_ID=12682970
155 13:59:22.594576 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:59:22.594685 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:59:22.594754 skipped lava-vland-overlay
158 13:59:22.594838 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:59:22.594925 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:59:22.594993 skipped lava-multinode-overlay
161 13:59:22.595081 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:59:22.595167 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:59:22.595290 Loading test definitions
164 13:59:22.595423 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:59:22.595530 Using /lava-12682970 at stage 0
166 13:59:22.595962 uuid=12682970_1.5.2.3.1 testdef=None
167 13:59:22.596086 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:59:22.596205 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:59:22.596874 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:59:22.597219 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:59:22.597971 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:59:22.598227 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:59:22.599092 runner path: /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/0/tests/0_v4l2-compliance-uvc test_uuid 12682970_1.5.2.3.1
176 13:59:22.599305 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:59:22.599656 Creating lava-test-runner.conf files
179 13:59:22.599765 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682970/lava-overlay-uca_ursp/lava-12682970/0 for stage 0
180 13:59:22.599896 - 0_v4l2-compliance-uvc
181 13:59:22.600027 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:59:22.600151 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:59:22.608427 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:59:22.608589 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:59:22.608683 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:59:22.608771 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:59:22.608861 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:59:23.384431 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:59:23.384860 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:59:23.384985 extracting modules file /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682970/extract-overlay-ramdisk-iko0o0u3/ramdisk
191 13:59:23.629792 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:59:23.629954 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:59:23.630052 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682970/compress-overlay-7x1ng0kg/overlay-1.5.2.4.tar.gz to ramdisk
194 13:59:23.630125 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682970/compress-overlay-7x1ng0kg/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682970/extract-overlay-ramdisk-iko0o0u3/ramdisk
195 13:59:23.636842 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:59:23.636971 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:59:23.637065 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:59:23.637158 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:59:23.637239 Building ramdisk /var/lib/lava/dispatcher/tmp/12682970/extract-overlay-ramdisk-iko0o0u3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682970/extract-overlay-ramdisk-iko0o0u3/ramdisk
200 13:59:24.316055 >> 228442 blocks
201 13:59:28.336712 rename /var/lib/lava/dispatcher/tmp/12682970/extract-overlay-ramdisk-iko0o0u3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/ramdisk/ramdisk.cpio.gz
202 13:59:28.337144 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 13:59:28.337273 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 13:59:28.337379 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 13:59:28.337514 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/kernel/Image'
206 13:59:41.570080 Returned 0 in 13 seconds
207 13:59:41.670723 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/kernel/image.itb
208 13:59:42.366752 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:59:42.367129 output: Created: Thu Feb 1 13:59:42 2024
210 13:59:42.367207 output: Image 0 (kernel-1)
211 13:59:42.367279 output: Description:
212 13:59:42.367344 output: Created: Thu Feb 1 13:59:42 2024
213 13:59:42.367411 output: Type: Kernel Image
214 13:59:42.367474 output: Compression: lzma compressed
215 13:59:42.367536 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
216 13:59:42.367595 output: Architecture: AArch64
217 13:59:42.367656 output: OS: Linux
218 13:59:42.367714 output: Load Address: 0x00000000
219 13:59:42.367770 output: Entry Point: 0x00000000
220 13:59:42.367827 output: Hash algo: crc32
221 13:59:42.367887 output: Hash value: 5aa40db2
222 13:59:42.367944 output: Image 1 (fdt-1)
223 13:59:42.368011 output: Description: mt8192-asurada-spherion-r0
224 13:59:42.368068 output: Created: Thu Feb 1 13:59:42 2024
225 13:59:42.368123 output: Type: Flat Device Tree
226 13:59:42.368178 output: Compression: uncompressed
227 13:59:42.368232 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:59:42.368286 output: Architecture: AArch64
229 13:59:42.368340 output: Hash algo: crc32
230 13:59:42.368393 output: Hash value: cc4352de
231 13:59:42.368447 output: Image 2 (ramdisk-1)
232 13:59:42.368501 output: Description: unavailable
233 13:59:42.368555 output: Created: Thu Feb 1 13:59:42 2024
234 13:59:42.368609 output: Type: RAMDisk Image
235 13:59:42.368663 output: Compression: Unknown Compression
236 13:59:42.368721 output: Data Size: 39353583 Bytes = 38431.23 KiB = 37.53 MiB
237 13:59:42.368777 output: Architecture: AArch64
238 13:59:42.368831 output: OS: Linux
239 13:59:42.368885 output: Load Address: unavailable
240 13:59:42.368940 output: Entry Point: unavailable
241 13:59:42.368993 output: Hash algo: crc32
242 13:59:42.369047 output: Hash value: 2ed1b57e
243 13:59:42.369101 output: Default Configuration: 'conf-1'
244 13:59:42.369155 output: Configuration 0 (conf-1)
245 13:59:42.369214 output: Description: mt8192-asurada-spherion-r0
246 13:59:42.369268 output: Kernel: kernel-1
247 13:59:42.369322 output: Init Ramdisk: ramdisk-1
248 13:59:42.369375 output: FDT: fdt-1
249 13:59:42.369428 output: Loadables: kernel-1
250 13:59:42.369496 output:
251 13:59:42.369754 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:59:42.369858 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:59:42.369966 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 13:59:42.370101 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 13:59:42.370212 No LXC device requested
256 13:59:42.370301 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:59:42.370395 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 13:59:42.370475 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:59:42.370549 Checking files for TFTP limit of 4294967296 bytes.
260 13:59:42.371068 end: 1 tftp-deploy (duration 00:00:21) [common]
261 13:59:42.371177 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:59:42.371270 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:59:42.371398 substitutions:
264 13:59:42.371467 - {DTB}: 12682970/tftp-deploy-3sk4mi01/dtb/mt8192-asurada-spherion-r0.dtb
265 13:59:42.371533 - {INITRD}: 12682970/tftp-deploy-3sk4mi01/ramdisk/ramdisk.cpio.gz
266 13:59:42.371593 - {KERNEL}: 12682970/tftp-deploy-3sk4mi01/kernel/Image
267 13:59:42.371654 - {LAVA_MAC}: None
268 13:59:42.371713 - {PRESEED_CONFIG}: None
269 13:59:42.371769 - {PRESEED_LOCAL}: None
270 13:59:42.371825 - {RAMDISK}: 12682970/tftp-deploy-3sk4mi01/ramdisk/ramdisk.cpio.gz
271 13:59:42.371882 - {ROOT_PART}: None
272 13:59:42.371952 - {ROOT}: None
273 13:59:42.372008 - {SERVER_IP}: 192.168.201.1
274 13:59:42.372063 - {TEE}: None
275 13:59:42.372118 Parsed boot commands:
276 13:59:42.372182 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:59:42.372368 Parsed boot commands: tftpboot 192.168.201.1 12682970/tftp-deploy-3sk4mi01/kernel/image.itb 12682970/tftp-deploy-3sk4mi01/kernel/cmdline
278 13:59:42.372459 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:59:42.372550 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:59:42.372652 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:59:42.372769 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:59:42.372870 Not connected, no need to disconnect.
283 13:59:42.372977 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:59:42.373088 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:59:42.373183 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 13:59:42.377390 Setting prompt string to ['lava-test: # ']
287 13:59:42.377787 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:59:42.377931 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:59:42.378067 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:59:42.378194 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:59:42.378526 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 13:59:47.510525 >> Command sent successfully.
293 13:59:47.513224 Returned 0 in 5 seconds
294 13:59:47.613665 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:59:47.614336 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:59:47.614567 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:59:47.614766 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:59:47.614944 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:59:47.615127 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:59:47.615697 [Enter `^Ec?' for help]
302 13:59:47.787059
303 13:59:47.787647
304 13:59:47.788034 F0: 102B 0000
305 13:59:47.788373
306 13:59:47.788751 F3: 1001 0000 [0200]
307 13:59:47.789978
308 13:59:47.790416 F3: 1001 0000
309 13:59:47.790876
310 13:59:47.791370 F7: 102D 0000
311 13:59:47.791703
312 13:59:47.793471 F1: 0000 0000
313 13:59:47.793943
314 13:59:47.794307 V0: 0000 0000 [0001]
315 13:59:47.794640
316 13:59:47.796828 00: 0007 8000
317 13:59:47.797342
318 13:59:47.797812 01: 0000 0000
319 13:59:47.798263
320 13:59:47.800440 BP: 0C00 0209 [0000]
321 13:59:47.800912
322 13:59:47.801385 G0: 1182 0000
323 13:59:47.801829
324 13:59:47.803473 EC: 0000 0021 [4000]
325 13:59:47.803982
326 13:59:47.804417 S7: 0000 0000 [0000]
327 13:59:47.804854
328 13:59:47.807357 CC: 0000 0000 [0001]
329 13:59:47.808013
330 13:59:47.808561 T0: 0000 0040 [010F]
331 13:59:47.809063
332 13:59:47.809592 Jump to BL
333 13:59:47.810625
334 13:59:47.834161
335 13:59:47.834615
336 13:59:47.835057
337 13:59:47.841938 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:59:47.845705 ARM64: Exception handlers installed.
339 13:59:47.848912 ARM64: Testing exception
340 13:59:47.851934 ARM64: Done test exception
341 13:59:47.858659 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:59:47.869141 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:59:47.875931 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:59:47.885978 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:59:47.892576 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:59:47.899328 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:59:47.910831 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:59:47.917398 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:59:47.936964 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:59:47.940427 WDT: Last reset was cold boot
351 13:59:47.943525 SPI1(PAD0) initialized at 2873684 Hz
352 13:59:47.947031 SPI5(PAD0) initialized at 992727 Hz
353 13:59:47.950227 VBOOT: Loading verstage.
354 13:59:47.956981 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:59:47.960404 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:59:47.963646 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:59:47.966761 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:59:47.974452 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:59:47.981104 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:59:47.991930 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 13:59:47.992359
362 13:59:47.992813
363 13:59:48.001854 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:59:48.005344 ARM64: Exception handlers installed.
365 13:59:48.008634 ARM64: Testing exception
366 13:59:48.009066 ARM64: Done test exception
367 13:59:48.015120 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:59:48.018825 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:59:48.033063 Probing TPM: . done!
370 13:59:48.033524 TPM ready after 0 ms
371 13:59:48.039301 Connected to device vid:did:rid of 1ae0:0028:00
372 13:59:48.046625 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 13:59:48.085355 Initialized TPM device CR50 revision 0
374 13:59:48.097462 tlcl_send_startup: Startup return code is 0
375 13:59:48.098045 TPM: setup succeeded
376 13:59:48.108638 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:59:48.117379 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:59:48.128675 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:59:48.139075 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:59:48.142159 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:59:48.146340 in-header: 03 07 00 00 08 00 00 00
382 13:59:48.149831 in-data: aa e4 47 04 13 02 00 00
383 13:59:48.153549 Chrome EC: UHEPI supported
384 13:59:48.160250 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:59:48.163904 in-header: 03 9d 00 00 08 00 00 00
386 13:59:48.167794 in-data: 10 20 20 08 00 00 00 00
387 13:59:48.168228 Phase 1
388 13:59:48.171309 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:59:48.178596 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:59:48.185974 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:59:48.186436 Recovery requested (1009000e)
392 13:59:48.195255 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:59:48.200653 tlcl_extend: response is 0
394 13:59:48.211195 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:59:48.214289 tlcl_extend: response is 0
396 13:59:48.220817 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:59:48.241802 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 13:59:48.248997 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:59:48.249420
400 13:59:48.249801
401 13:59:48.256502 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:59:48.260342 ARM64: Exception handlers installed.
403 13:59:48.264021 ARM64: Testing exception
404 13:59:48.267267 ARM64: Done test exception
405 13:59:48.284019 pmic_efuse_setting: Set efuses in 11 msecs
406 13:59:48.289138 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:59:48.296348 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:59:48.300329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:59:48.304162 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:59:48.311558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:59:48.314748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:59:48.318127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:59:48.325545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:59:48.329220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:59:48.332508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:59:48.339448 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:59:48.342818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:59:48.349243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:59:48.352460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:59:48.359248 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:59:48.365782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:59:48.369194 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:59:48.375565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:59:48.382669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:59:48.386119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:59:48.393527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:59:48.397128 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:59:48.404436 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:59:48.410715 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:59:48.414616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:59:48.421799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:59:48.424961 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:59:48.431768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:59:48.435698 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:59:48.439356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:59:48.445879 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:59:48.449106 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:59:48.456491 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:59:48.459699 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:59:48.467009 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:59:48.470717 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:59:48.474463 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:59:48.481046 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:59:48.484331 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:59:48.490756 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:59:48.494031 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:59:48.497189 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:59:48.504118 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:59:48.507330 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:59:48.510921 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:59:48.517404 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:59:48.520764 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:59:48.524145 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:59:48.527463 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:59:48.534227 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:59:48.537596 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:59:48.540764 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:59:48.550545 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:59:48.557221 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:59:48.560516 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:59:48.570909 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:59:48.577296 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:59:48.583937 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:59:48.587421 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:59:48.590466 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:59:48.598855 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xf
467 13:59:48.605486 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:59:48.608867 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 13:59:48.612097 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:59:48.623412 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 13:59:48.627018 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 13:59:48.633375 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 13:59:48.636719 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 13:59:48.640091 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 13:59:48.643279 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 13:59:48.646641 ADC[4]: Raw value=897780 ID=7
477 13:59:48.650043 ADC[3]: Raw value=213070 ID=1
478 13:59:48.653295 RAM Code: 0x71
479 13:59:48.656898 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 13:59:48.660032 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 13:59:48.670072 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 13:59:48.677247 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 13:59:48.680542 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 13:59:48.683809 in-header: 03 07 00 00 08 00 00 00
485 13:59:48.687417 in-data: aa e4 47 04 13 02 00 00
486 13:59:48.687491 Chrome EC: UHEPI supported
487 13:59:48.694002 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 13:59:48.698390 in-header: 03 d5 00 00 08 00 00 00
489 13:59:48.701622 in-data: 98 20 60 08 00 00 00 00
490 13:59:48.705182 MRC: failed to locate region type 0.
491 13:59:48.712454 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 13:59:48.716216 DRAM-K: Running full calibration
493 13:59:48.722777 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 13:59:48.722860 header.status = 0x0
495 13:59:48.725945 header.version = 0x6 (expected: 0x6)
496 13:59:48.729437 header.size = 0xd00 (expected: 0xd00)
497 13:59:48.733136 header.flags = 0x0
498 13:59:48.736825 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 13:59:48.755562 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 13:59:48.762268 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 13:59:48.765328 dram_init: ddr_geometry: 2
502 13:59:48.768977 [EMI] MDL number = 2
503 13:59:48.769137 [EMI] Get MDL freq = 0
504 13:59:48.771956 dram_init: ddr_type: 0
505 13:59:48.772102 is_discrete_lpddr4: 1
506 13:59:48.775488 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 13:59:48.775662
508 13:59:48.775800
509 13:59:48.778792 [Bian_co] ETT version 0.0.0.1
510 13:59:48.785739 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 13:59:48.785843
512 13:59:48.788952 dramc_set_vcore_voltage set vcore to 650000
513 13:59:48.789083 Read voltage for 800, 4
514 13:59:48.792414 Vio18 = 0
515 13:59:48.792515 Vcore = 650000
516 13:59:48.792607 Vdram = 0
517 13:59:48.795584 Vddq = 0
518 13:59:48.795660 Vmddr = 0
519 13:59:48.799171 dram_init: config_dvfs: 1
520 13:59:48.802121 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 13:59:48.808853 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 13:59:48.812185 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 13:59:48.815493 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 13:59:48.818673 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 13:59:48.822417 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 13:59:48.825710 MEM_TYPE=3, freq_sel=18
527 13:59:48.829016 sv_algorithm_assistance_LP4_1600
528 13:59:48.832108 ============ PULL DRAM RESETB DOWN ============
529 13:59:48.835499 ========== PULL DRAM RESETB DOWN end =========
530 13:59:48.842080 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 13:59:48.845875 ===================================
532 13:59:48.845977 LPDDR4 DRAM CONFIGURATION
533 13:59:48.849197 ===================================
534 13:59:48.852398 EX_ROW_EN[0] = 0x0
535 13:59:48.855661 EX_ROW_EN[1] = 0x0
536 13:59:48.855768 LP4Y_EN = 0x0
537 13:59:48.859182 WORK_FSP = 0x0
538 13:59:48.859284 WL = 0x2
539 13:59:48.862383 RL = 0x2
540 13:59:48.862480 BL = 0x2
541 13:59:48.865661 RPST = 0x0
542 13:59:48.865737 RD_PRE = 0x0
543 13:59:48.869143 WR_PRE = 0x1
544 13:59:48.869233 WR_PST = 0x0
545 13:59:48.872358 DBI_WR = 0x0
546 13:59:48.872466 DBI_RD = 0x0
547 13:59:48.875930 OTF = 0x1
548 13:59:48.878927 ===================================
549 13:59:48.883166 ===================================
550 13:59:48.883257 ANA top config
551 13:59:48.886492 ===================================
552 13:59:48.890137 DLL_ASYNC_EN = 0
553 13:59:48.890213 ALL_SLAVE_EN = 1
554 13:59:48.893939 NEW_RANK_MODE = 1
555 13:59:48.897414 DLL_IDLE_MODE = 1
556 13:59:48.901397 LP45_APHY_COMB_EN = 1
557 13:59:48.901539 TX_ODT_DIS = 1
558 13:59:48.904962 NEW_8X_MODE = 1
559 13:59:48.908526 ===================================
560 13:59:48.912691 ===================================
561 13:59:48.912775 data_rate = 1600
562 13:59:48.916168 CKR = 1
563 13:59:48.919818 DQ_P2S_RATIO = 8
564 13:59:48.923624 ===================================
565 13:59:48.927315 CA_P2S_RATIO = 8
566 13:59:48.927395 DQ_CA_OPEN = 0
567 13:59:48.930917 DQ_SEMI_OPEN = 0
568 13:59:48.934694 CA_SEMI_OPEN = 0
569 13:59:48.938372 CA_FULL_RATE = 0
570 13:59:48.938451 DQ_CKDIV4_EN = 1
571 13:59:48.941872 CA_CKDIV4_EN = 1
572 13:59:48.946099 CA_PREDIV_EN = 0
573 13:59:48.946175 PH8_DLY = 0
574 13:59:48.949657 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 13:59:48.953836 DQ_AAMCK_DIV = 4
576 13:59:48.957206 CA_AAMCK_DIV = 4
577 13:59:48.957283 CA_ADMCK_DIV = 4
578 13:59:48.961182 DQ_TRACK_CA_EN = 0
579 13:59:48.965010 CA_PICK = 800
580 13:59:48.968414 CA_MCKIO = 800
581 13:59:48.968497 MCKIO_SEMI = 0
582 13:59:48.971850 PLL_FREQ = 3068
583 13:59:48.975299 DQ_UI_PI_RATIO = 32
584 13:59:48.978614 CA_UI_PI_RATIO = 0
585 13:59:48.981726 ===================================
586 13:59:48.985209 ===================================
587 13:59:48.988387 memory_type:LPDDR4
588 13:59:48.988499 GP_NUM : 10
589 13:59:48.991983 SRAM_EN : 1
590 13:59:48.995327 MD32_EN : 0
591 13:59:48.998605 ===================================
592 13:59:48.998742 [ANA_INIT] >>>>>>>>>>>>>>
593 13:59:49.001852 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 13:59:49.005413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 13:59:49.008583 ===================================
596 13:59:49.012043 data_rate = 1600,PCW = 0X7600
597 13:59:49.015547 ===================================
598 13:59:49.018658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 13:59:49.025368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 13:59:49.028763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 13:59:49.035610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 13:59:49.039198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 13:59:49.042936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 13:59:49.043401 [ANA_INIT] flow start
605 13:59:49.045978 [ANA_INIT] PLL >>>>>>>>
606 13:59:49.049942 [ANA_INIT] PLL <<<<<<<<
607 13:59:49.050405 [ANA_INIT] MIDPI >>>>>>>>
608 13:59:49.053691 [ANA_INIT] MIDPI <<<<<<<<
609 13:59:49.054140 [ANA_INIT] DLL >>>>>>>>
610 13:59:49.057232 [ANA_INIT] flow end
611 13:59:49.060886 ============ LP4 DIFF to SE enter ============
612 13:59:49.064821 ============ LP4 DIFF to SE exit ============
613 13:59:49.068670 [ANA_INIT] <<<<<<<<<<<<<
614 13:59:49.072331 [Flow] Enable top DCM control >>>>>
615 13:59:49.072754 [Flow] Enable top DCM control <<<<<
616 13:59:49.076264 Enable DLL master slave shuffle
617 13:59:49.083465 ==============================================================
618 13:59:49.083887 Gating Mode config
619 13:59:49.090167 ==============================================================
620 13:59:49.093338 Config description:
621 13:59:49.100133 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 13:59:49.106888 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 13:59:49.113622 SELPH_MODE 0: By rank 1: By Phase
624 13:59:49.116577 ==============================================================
625 13:59:49.120137 GAT_TRACK_EN = 1
626 13:59:49.123498 RX_GATING_MODE = 2
627 13:59:49.126888 RX_GATING_TRACK_MODE = 2
628 13:59:49.130179 SELPH_MODE = 1
629 13:59:49.133367 PICG_EARLY_EN = 1
630 13:59:49.136610 VALID_LAT_VALUE = 1
631 13:59:49.143433 ==============================================================
632 13:59:49.146631 Enter into Gating configuration >>>>
633 13:59:49.150121 Exit from Gating configuration <<<<
634 13:59:49.153414 Enter into DVFS_PRE_config >>>>>
635 13:59:49.163523 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 13:59:49.166702 Exit from DVFS_PRE_config <<<<<
637 13:59:49.170062 Enter into PICG configuration >>>>
638 13:59:49.173273 Exit from PICG configuration <<<<
639 13:59:49.173776 [RX_INPUT] configuration >>>>>
640 13:59:49.176523 [RX_INPUT] configuration <<<<<
641 13:59:49.183264 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 13:59:49.186830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 13:59:49.193641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 13:59:49.199957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 13:59:49.207107 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 13:59:49.213439 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 13:59:49.216778 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 13:59:49.219905 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 13:59:49.226658 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 13:59:49.230155 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 13:59:49.233256 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 13:59:49.236463 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 13:59:49.239817 ===================================
654 13:59:49.243607 LPDDR4 DRAM CONFIGURATION
655 13:59:49.246616 ===================================
656 13:59:49.250178 EX_ROW_EN[0] = 0x0
657 13:59:49.250633 EX_ROW_EN[1] = 0x0
658 13:59:49.253265 LP4Y_EN = 0x0
659 13:59:49.253733 WORK_FSP = 0x0
660 13:59:49.256657 WL = 0x2
661 13:59:49.257080 RL = 0x2
662 13:59:49.259923 BL = 0x2
663 13:59:49.260344 RPST = 0x0
664 13:59:49.263300 RD_PRE = 0x0
665 13:59:49.263719 WR_PRE = 0x1
666 13:59:49.266662 WR_PST = 0x0
667 13:59:49.267083 DBI_WR = 0x0
668 13:59:49.270120 DBI_RD = 0x0
669 13:59:49.270541 OTF = 0x1
670 13:59:49.273466 ===================================
671 13:59:49.279988 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 13:59:49.283627 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 13:59:49.286744 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 13:59:49.290402 ===================================
675 13:59:49.293604 LPDDR4 DRAM CONFIGURATION
676 13:59:49.296739 ===================================
677 13:59:49.297163 EX_ROW_EN[0] = 0x10
678 13:59:49.300366 EX_ROW_EN[1] = 0x0
679 13:59:49.303779 LP4Y_EN = 0x0
680 13:59:49.304201 WORK_FSP = 0x0
681 13:59:49.307126 WL = 0x2
682 13:59:49.307545 RL = 0x2
683 13:59:49.310356 BL = 0x2
684 13:59:49.310777 RPST = 0x0
685 13:59:49.313556 RD_PRE = 0x0
686 13:59:49.313980 WR_PRE = 0x1
687 13:59:49.316957 WR_PST = 0x0
688 13:59:49.317375 DBI_WR = 0x0
689 13:59:49.320480 DBI_RD = 0x0
690 13:59:49.320899 OTF = 0x1
691 13:59:49.323847 ===================================
692 13:59:49.330295 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 13:59:49.334052 nWR fixed to 40
694 13:59:49.337540 [ModeRegInit_LP4] CH0 RK0
695 13:59:49.338103 [ModeRegInit_LP4] CH0 RK1
696 13:59:49.340757 [ModeRegInit_LP4] CH1 RK0
697 13:59:49.344214 [ModeRegInit_LP4] CH1 RK1
698 13:59:49.344636 match AC timing 13
699 13:59:49.350697 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 13:59:49.354008 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 13:59:49.357236 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 13:59:49.363975 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 13:59:49.367359 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 13:59:49.367522 [EMI DOE] emi_dcm 0
705 13:59:49.373848 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 13:59:49.374000 ==
707 13:59:49.377135 Dram Type= 6, Freq= 0, CH_0, rank 0
708 13:59:49.380598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 13:59:49.380680 ==
710 13:59:49.387247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 13:59:49.393603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 13:59:49.401337 [CA 0] Center 38 (7~69) winsize 63
713 13:59:49.404601 [CA 1] Center 37 (7~68) winsize 62
714 13:59:49.408153 [CA 2] Center 35 (5~66) winsize 62
715 13:59:49.411546 [CA 3] Center 35 (5~66) winsize 62
716 13:59:49.414655 [CA 4] Center 34 (4~65) winsize 62
717 13:59:49.418609 [CA 5] Center 34 (3~65) winsize 63
718 13:59:49.418690
719 13:59:49.422182 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 13:59:49.422263
721 13:59:49.425837 [CATrainingPosCal] consider 1 rank data
722 13:59:49.429394 u2DelayCellTimex100 = 270/100 ps
723 13:59:49.433072 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 13:59:49.436494 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 13:59:49.440321 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 13:59:49.443938 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 13:59:49.447524 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 13:59:49.450972 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
729 13:59:49.451053
730 13:59:49.454986 CA PerBit enable=1, Macro0, CA PI delay=34
731 13:59:49.455076
732 13:59:49.458355 [CBTSetCACLKResult] CA Dly = 34
733 13:59:49.458432 CS Dly: 6 (0~37)
734 13:59:49.458499 ==
735 13:59:49.462460 Dram Type= 6, Freq= 0, CH_0, rank 1
736 13:59:49.466002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 13:59:49.466120 ==
738 13:59:49.473094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 13:59:49.476921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 13:59:49.487571 [CA 0] Center 38 (7~69) winsize 63
741 13:59:49.491870 [CA 1] Center 37 (7~68) winsize 62
742 13:59:49.495449 [CA 2] Center 35 (5~66) winsize 62
743 13:59:49.499171 [CA 3] Center 35 (5~66) winsize 62
744 13:59:49.502849 [CA 4] Center 34 (4~65) winsize 62
745 13:59:49.502923 [CA 5] Center 34 (4~64) winsize 61
746 13:59:49.506610
747 13:59:49.510313 [CmdBusTrainingLP45] Vref(ca) range 1: 30
748 13:59:49.510438
749 13:59:49.514032 [CATrainingPosCal] consider 2 rank data
750 13:59:49.514108 u2DelayCellTimex100 = 270/100 ps
751 13:59:49.517386 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 13:59:49.521090 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 13:59:49.524850 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 13:59:49.528512 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 13:59:49.532235 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 13:59:49.535618 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 13:59:49.535726
758 13:59:49.543286 CA PerBit enable=1, Macro0, CA PI delay=34
759 13:59:49.543375
760 13:59:49.543442 [CBTSetCACLKResult] CA Dly = 34
761 13:59:49.546916 CS Dly: 6 (0~37)
762 13:59:49.546997
763 13:59:49.550597 ----->DramcWriteLeveling(PI) begin...
764 13:59:49.550683 ==
765 13:59:49.554141 Dram Type= 6, Freq= 0, CH_0, rank 0
766 13:59:49.557833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 13:59:49.557919 ==
768 13:59:49.561145 Write leveling (Byte 0): 32 => 32
769 13:59:49.564972 Write leveling (Byte 1): 32 => 32
770 13:59:49.565054 DramcWriteLeveling(PI) end<-----
771 13:59:49.565118
772 13:59:49.565178 ==
773 13:59:49.568910 Dram Type= 6, Freq= 0, CH_0, rank 0
774 13:59:49.572386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 13:59:49.576029 ==
776 13:59:49.576112 [Gating] SW mode calibration
777 13:59:49.583276 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 13:59:49.590983 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 13:59:49.594450 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 13:59:49.598282 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 13:59:49.601907 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
782 13:59:49.605620 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 13:59:49.612184 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 13:59:49.615876 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 13:59:49.619863 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 13:59:49.623523 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 13:59:49.627217 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 13:59:49.634686 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:59:49.638334 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:59:49.641925 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:59:49.645624 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:59:49.649232 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:59:49.656601 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:59:49.659907 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:59:49.663996 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:59:49.667464 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 13:59:49.670864 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
798 13:59:49.678396 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:59:49.682105 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:59:49.685934 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:59:49.689357 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:59:49.693228 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:59:49.700635 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:59:49.704330 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:59:49.708363 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:59:49.712032 0 9 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
807 13:59:49.715387 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 13:59:49.722866 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 13:59:49.726385 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 13:59:49.730223 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 13:59:49.733950 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 13:59:49.737730 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 13:59:49.741988 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
814 13:59:49.748538 0 10 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
815 13:59:49.751900 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:59:49.755216 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:59:49.762165 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:59:49.765395 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 13:59:49.768643 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:59:49.772090 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 13:59:49.778508 0 11 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
822 13:59:49.781728 0 11 12 | B1->B0 | 3333 4040 | 0 0 | (0 0) (0 0)
823 13:59:49.785235 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 13:59:49.792001 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 13:59:49.795054 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 13:59:49.798887 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 13:59:49.805196 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 13:59:49.808566 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 13:59:49.811966 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
830 13:59:49.818463 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
831 13:59:49.821960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 13:59:49.825181 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 13:59:49.832148 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 13:59:49.835209 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 13:59:49.838550 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 13:59:49.845173 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:59:49.848554 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:59:49.852012 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:59:49.858920 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:59:49.862136 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:59:49.865318 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:59:49.869064 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:59:49.875415 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:59:49.878650 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 13:59:49.882275 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
846 13:59:49.885300 Total UI for P1: 0, mck2ui 16
847 13:59:49.889007 best dqsien dly found for B0: ( 0, 14, 4)
848 13:59:49.895414 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 13:59:49.898526 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 13:59:49.901929 Total UI for P1: 0, mck2ui 16
851 13:59:49.905585 best dqsien dly found for B1: ( 0, 14, 12)
852 13:59:49.909023 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
853 13:59:49.912328 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 13:59:49.912410
855 13:59:49.915311 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
856 13:59:49.918541 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 13:59:49.921911 [Gating] SW calibration Done
858 13:59:49.921994 ==
859 13:59:49.925230 Dram Type= 6, Freq= 0, CH_0, rank 0
860 13:59:49.928381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 13:59:49.931899 ==
862 13:59:49.931981 RX Vref Scan: 0
863 13:59:49.932047
864 13:59:49.935270 RX Vref 0 -> 0, step: 1
865 13:59:49.935352
866 13:59:49.938785 RX Delay -130 -> 252, step: 16
867 13:59:49.942029 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 13:59:49.945363 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 13:59:49.948611 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 13:59:49.951844 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 13:59:49.958539 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 13:59:49.961974 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 13:59:49.965208 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 13:59:49.968483 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 13:59:49.971782 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 13:59:49.978588 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 13:59:49.981721 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 13:59:49.985320 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 13:59:49.988658 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 13:59:49.991877 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 13:59:49.998331 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 13:59:50.001925 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 13:59:50.002008 ==
884 13:59:50.005066 Dram Type= 6, Freq= 0, CH_0, rank 0
885 13:59:50.008449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 13:59:50.008532 ==
887 13:59:50.011746 DQS Delay:
888 13:59:50.011828 DQS0 = 0, DQS1 = 0
889 13:59:50.011894 DQM Delay:
890 13:59:50.015474 DQM0 = 81, DQM1 = 69
891 13:59:50.015556 DQ Delay:
892 13:59:50.018621 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
893 13:59:50.021869 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 13:59:50.025076 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 13:59:50.028422 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 13:59:50.028504
897 13:59:50.028569
898 13:59:50.028629 ==
899 13:59:50.031567 Dram Type= 6, Freq= 0, CH_0, rank 0
900 13:59:50.035437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 13:59:50.039009 ==
902 13:59:50.039091
903 13:59:50.039157
904 13:59:50.039218 TX Vref Scan disable
905 13:59:50.042278 == TX Byte 0 ==
906 13:59:50.045628 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 13:59:50.048686 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 13:59:50.052269 == TX Byte 1 ==
909 13:59:50.055394 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
910 13:59:50.058991 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
911 13:59:50.062226 ==
912 13:59:50.062309 Dram Type= 6, Freq= 0, CH_0, rank 0
913 13:59:50.068729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 13:59:50.068812 ==
915 13:59:50.080743 TX Vref=22, minBit 14, minWin=26, winSum=434
916 13:59:50.084119 TX Vref=24, minBit 14, minWin=26, winSum=438
917 13:59:50.087243 TX Vref=26, minBit 1, minWin=27, winSum=441
918 13:59:50.090842 TX Vref=28, minBit 9, minWin=27, winSum=446
919 13:59:50.094308 TX Vref=30, minBit 2, minWin=27, winSum=441
920 13:59:50.100947 TX Vref=32, minBit 1, minWin=27, winSum=438
921 13:59:50.104164 [TxChooseVref] Worse bit 9, Min win 27, Win sum 446, Final Vref 28
922 13:59:50.104277
923 13:59:50.107380 Final TX Range 1 Vref 28
924 13:59:50.107483
925 13:59:50.107577 ==
926 13:59:50.110574 Dram Type= 6, Freq= 0, CH_0, rank 0
927 13:59:50.113951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 13:59:50.114024 ==
929 13:59:50.117565
930 13:59:50.117641
931 13:59:50.117704 TX Vref Scan disable
932 13:59:50.121098 == TX Byte 0 ==
933 13:59:50.124052 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
934 13:59:50.127756 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
935 13:59:50.131010 == TX Byte 1 ==
936 13:59:50.134354 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 13:59:50.137631 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 13:59:50.140686
939 13:59:50.140768 [DATLAT]
940 13:59:50.140832 Freq=800, CH0 RK0
941 13:59:50.140894
942 13:59:50.144051 DATLAT Default: 0xa
943 13:59:50.144138 0, 0xFFFF, sum = 0
944 13:59:50.147396 1, 0xFFFF, sum = 0
945 13:59:50.147480 2, 0xFFFF, sum = 0
946 13:59:50.150862 3, 0xFFFF, sum = 0
947 13:59:50.150946 4, 0xFFFF, sum = 0
948 13:59:50.154478 5, 0xFFFF, sum = 0
949 13:59:50.154561 6, 0xFFFF, sum = 0
950 13:59:50.157409 7, 0xFFFF, sum = 0
951 13:59:50.161010 8, 0xFFFF, sum = 0
952 13:59:50.161153 9, 0x0, sum = 1
953 13:59:50.161249 10, 0x0, sum = 2
954 13:59:50.164348 11, 0x0, sum = 3
955 13:59:50.164432 12, 0x0, sum = 4
956 13:59:50.167577 best_step = 10
957 13:59:50.167659
958 13:59:50.167723 ==
959 13:59:50.171119 Dram Type= 6, Freq= 0, CH_0, rank 0
960 13:59:50.174182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 13:59:50.174269 ==
962 13:59:50.177692 RX Vref Scan: 1
963 13:59:50.177774
964 13:59:50.177838 Set Vref Range= 32 -> 127
965 13:59:50.177898
966 13:59:50.180643 RX Vref 32 -> 127, step: 1
967 13:59:50.180725
968 13:59:50.183987 RX Delay -111 -> 252, step: 8
969 13:59:50.184070
970 13:59:50.187648 Set Vref, RX VrefLevel [Byte0]: 32
971 13:59:50.190923 [Byte1]: 32
972 13:59:50.191033
973 13:59:50.194258 Set Vref, RX VrefLevel [Byte0]: 33
974 13:59:50.197378 [Byte1]: 33
975 13:59:50.201318
976 13:59:50.201400 Set Vref, RX VrefLevel [Byte0]: 34
977 13:59:50.207603 [Byte1]: 34
978 13:59:50.207685
979 13:59:50.210771 Set Vref, RX VrefLevel [Byte0]: 35
980 13:59:50.214374 [Byte1]: 35
981 13:59:50.214456
982 13:59:50.217593 Set Vref, RX VrefLevel [Byte0]: 36
983 13:59:50.221160 [Byte1]: 36
984 13:59:50.224367
985 13:59:50.224449 Set Vref, RX VrefLevel [Byte0]: 37
986 13:59:50.227735 [Byte1]: 37
987 13:59:50.232179
988 13:59:50.232619 Set Vref, RX VrefLevel [Byte0]: 38
989 13:59:50.235390 [Byte1]: 38
990 13:59:50.239936
991 13:59:50.240358 Set Vref, RX VrefLevel [Byte0]: 39
992 13:59:50.243251 [Byte1]: 39
993 13:59:50.247467
994 13:59:50.247889 Set Vref, RX VrefLevel [Byte0]: 40
995 13:59:50.250710 [Byte1]: 40
996 13:59:50.255300
997 13:59:50.255721 Set Vref, RX VrefLevel [Byte0]: 41
998 13:59:50.258494 [Byte1]: 41
999 13:59:50.262943
1000 13:59:50.263366 Set Vref, RX VrefLevel [Byte0]: 42
1001 13:59:50.266103 [Byte1]: 42
1002 13:59:50.270573
1003 13:59:50.270998 Set Vref, RX VrefLevel [Byte0]: 43
1004 13:59:50.273668 [Byte1]: 43
1005 13:59:50.277984
1006 13:59:50.278407 Set Vref, RX VrefLevel [Byte0]: 44
1007 13:59:50.281276 [Byte1]: 44
1008 13:59:50.285621
1009 13:59:50.286044 Set Vref, RX VrefLevel [Byte0]: 45
1010 13:59:50.289308 [Byte1]: 45
1011 13:59:50.293564
1012 13:59:50.293992 Set Vref, RX VrefLevel [Byte0]: 46
1013 13:59:50.296729 [Byte1]: 46
1014 13:59:50.301174
1015 13:59:50.301639 Set Vref, RX VrefLevel [Byte0]: 47
1016 13:59:50.304445 [Byte1]: 47
1017 13:59:50.308289
1018 13:59:50.308753 Set Vref, RX VrefLevel [Byte0]: 48
1019 13:59:50.312224 [Byte1]: 48
1020 13:59:50.315983
1021 13:59:50.319761 Set Vref, RX VrefLevel [Byte0]: 49
1022 13:59:50.320202 [Byte1]: 49
1023 13:59:50.324242
1024 13:59:50.324665 Set Vref, RX VrefLevel [Byte0]: 50
1025 13:59:50.327109 [Byte1]: 50
1026 13:59:50.331379
1027 13:59:50.331884 Set Vref, RX VrefLevel [Byte0]: 51
1028 13:59:50.335021 [Byte1]: 51
1029 13:59:50.339119
1030 13:59:50.339533 Set Vref, RX VrefLevel [Byte0]: 52
1031 13:59:50.342572 [Byte1]: 52
1032 13:59:50.346782
1033 13:59:50.347214 Set Vref, RX VrefLevel [Byte0]: 53
1034 13:59:50.350336 [Byte1]: 53
1035 13:59:50.354454
1036 13:59:50.354869 Set Vref, RX VrefLevel [Byte0]: 54
1037 13:59:50.357868 [Byte1]: 54
1038 13:59:50.362106
1039 13:59:50.362602 Set Vref, RX VrefLevel [Byte0]: 55
1040 13:59:50.365561 [Byte1]: 55
1041 13:59:50.369558
1042 13:59:50.373219 Set Vref, RX VrefLevel [Byte0]: 56
1043 13:59:50.373749 [Byte1]: 56
1044 13:59:50.377247
1045 13:59:50.377762 Set Vref, RX VrefLevel [Byte0]: 57
1046 13:59:50.380774 [Byte1]: 57
1047 13:59:50.385115
1048 13:59:50.385586 Set Vref, RX VrefLevel [Byte0]: 58
1049 13:59:50.388313 [Byte1]: 58
1050 13:59:50.392603
1051 13:59:50.393015 Set Vref, RX VrefLevel [Byte0]: 59
1052 13:59:50.396106 [Byte1]: 59
1053 13:59:50.400353
1054 13:59:50.400800 Set Vref, RX VrefLevel [Byte0]: 60
1055 13:59:50.403699 [Byte1]: 60
1056 13:59:50.407902
1057 13:59:50.408429 Set Vref, RX VrefLevel [Byte0]: 61
1058 13:59:50.411076 [Byte1]: 61
1059 13:59:50.415881
1060 13:59:50.416293 Set Vref, RX VrefLevel [Byte0]: 62
1061 13:59:50.419197 [Byte1]: 62
1062 13:59:50.423500
1063 13:59:50.423913 Set Vref, RX VrefLevel [Byte0]: 63
1064 13:59:50.426734 [Byte1]: 63
1065 13:59:50.431178
1066 13:59:50.431594 Set Vref, RX VrefLevel [Byte0]: 64
1067 13:59:50.434364 [Byte1]: 64
1068 13:59:50.438476
1069 13:59:50.438891 Set Vref, RX VrefLevel [Byte0]: 65
1070 13:59:50.441761 [Byte1]: 65
1071 13:59:50.446257
1072 13:59:50.446706 Set Vref, RX VrefLevel [Byte0]: 66
1073 13:59:50.449441 [Byte1]: 66
1074 13:59:50.453727
1075 13:59:50.454098 Set Vref, RX VrefLevel [Byte0]: 67
1076 13:59:50.457007 [Byte1]: 67
1077 13:59:50.461331
1078 13:59:50.461920 Set Vref, RX VrefLevel [Byte0]: 68
1079 13:59:50.464702 [Byte1]: 68
1080 13:59:50.468938
1081 13:59:50.469324 Set Vref, RX VrefLevel [Byte0]: 69
1082 13:59:50.472126 [Byte1]: 69
1083 13:59:50.476728
1084 13:59:50.476913 Set Vref, RX VrefLevel [Byte0]: 70
1085 13:59:50.480067 [Byte1]: 70
1086 13:59:50.484490
1087 13:59:50.484726 Set Vref, RX VrefLevel [Byte0]: 71
1088 13:59:50.487711 [Byte1]: 71
1089 13:59:50.491733
1090 13:59:50.491955 Set Vref, RX VrefLevel [Byte0]: 72
1091 13:59:50.495065 [Byte1]: 72
1092 13:59:50.499559
1093 13:59:50.499715 Set Vref, RX VrefLevel [Byte0]: 73
1094 13:59:50.503027 [Byte1]: 73
1095 13:59:50.507319
1096 13:59:50.507564 Set Vref, RX VrefLevel [Byte0]: 74
1097 13:59:50.510586 [Byte1]: 74
1098 13:59:50.514875
1099 13:59:50.515312 Set Vref, RX VrefLevel [Byte0]: 75
1100 13:59:50.518475 [Byte1]: 75
1101 13:59:50.522673
1102 13:59:50.523118 Set Vref, RX VrefLevel [Byte0]: 76
1103 13:59:50.525956 [Byte1]: 76
1104 13:59:50.530392
1105 13:59:50.530784 Set Vref, RX VrefLevel [Byte0]: 77
1106 13:59:50.533812 [Byte1]: 77
1107 13:59:50.537995
1108 13:59:50.538397 Final RX Vref Byte 0 = 60 to rank0
1109 13:59:50.541636 Final RX Vref Byte 1 = 55 to rank0
1110 13:59:50.544555 Final RX Vref Byte 0 = 60 to rank1
1111 13:59:50.547978 Final RX Vref Byte 1 = 55 to rank1==
1112 13:59:50.551678 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 13:59:50.558028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 13:59:50.558442 ==
1115 13:59:50.558767 DQS Delay:
1116 13:59:50.559072 DQS0 = 0, DQS1 = 0
1117 13:59:50.561422 DQM Delay:
1118 13:59:50.561879 DQM0 = 81, DQM1 = 68
1119 13:59:50.564830 DQ Delay:
1120 13:59:50.567754 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1121 13:59:50.568298 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1122 13:59:50.571371 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1123 13:59:50.578090 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =76
1124 13:59:50.578654
1125 13:59:50.579120
1126 13:59:50.584641 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1127 13:59:50.587956 CH0 RK0: MR19=606, MR18=2525
1128 13:59:50.594332 CH0_RK0: MR19=0x606, MR18=0x2525, DQSOSC=400, MR23=63, INC=92, DEC=61
1129 13:59:50.594741
1130 13:59:50.598003 ----->DramcWriteLeveling(PI) begin...
1131 13:59:50.598416 ==
1132 13:59:50.600833 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 13:59:50.604554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 13:59:50.604963 ==
1135 13:59:50.607634 Write leveling (Byte 0): 31 => 31
1136 13:59:50.611146 Write leveling (Byte 1): 30 => 30
1137 13:59:50.614677 DramcWriteLeveling(PI) end<-----
1138 13:59:50.615085
1139 13:59:50.615405 ==
1140 13:59:50.617738 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 13:59:50.621381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 13:59:50.621984 ==
1143 13:59:50.624423 [Gating] SW mode calibration
1144 13:59:50.631150 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 13:59:50.638164 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 13:59:50.641007 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 13:59:50.644325 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1148 13:59:50.651280 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1149 13:59:50.654305 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:59:50.657822 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 13:59:50.664443 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 13:59:50.667838 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:59:50.670876 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:59:50.677690 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:59:50.681271 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:59:50.684692 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:59:50.691029 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:59:50.694287 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:59:50.697562 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:59:50.704275 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:59:50.707850 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:59:50.751805 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:59:50.752354 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1164 13:59:50.752849 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1165 13:59:50.753303 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:59:50.753719 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:59:50.754348 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:59:50.754661 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:59:50.754946 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:59:50.755226 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:59:50.755498 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:59:50.764829 0 9 8 | B1->B0 | 2323 3030 | 1 1 | (0 0) (1 1)
1173 13:59:50.765449 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1174 13:59:50.765904 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 13:59:50.767974 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 13:59:50.774765 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 13:59:50.777927 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 13:59:50.781403 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:59:50.787893 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1180 13:59:50.791096 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1181 13:59:50.794743 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1182 13:59:50.797660 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:59:50.804422 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:59:50.807743 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:59:50.811033 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:59:50.817588 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:59:50.820733 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1188 13:59:50.824160 0 11 8 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (1 1)
1189 13:59:50.831125 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 13:59:50.834151 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 13:59:50.837494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 13:59:50.844493 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 13:59:50.847402 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:59:50.850945 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:59:50.857385 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1196 13:59:50.860758 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1197 13:59:50.864123 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1198 13:59:50.868301 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:59:50.875975 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:59:50.879616 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:59:50.883077 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:59:50.886458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:59:50.893542 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:59:50.896879 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:59:50.900277 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:59:50.903745 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:59:50.910211 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:59:50.913417 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:59:50.916925 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:59:50.923369 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:59:50.927015 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:59:50.930128 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1213 13:59:50.936961 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 13:59:50.937550 Total UI for P1: 0, mck2ui 16
1215 13:59:50.943474 best dqsien dly found for B0: ( 0, 14, 8)
1216 13:59:50.943849 Total UI for P1: 0, mck2ui 16
1217 13:59:50.950140 best dqsien dly found for B1: ( 0, 14, 10)
1218 13:59:50.953841 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1219 13:59:50.957019 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1220 13:59:50.957394
1221 13:59:50.960312 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1222 13:59:50.963420 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1223 13:59:50.966943 [Gating] SW calibration Done
1224 13:59:50.967334 ==
1225 13:59:50.970546 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 13:59:50.973644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1227 13:59:50.974044 ==
1228 13:59:50.977004 RX Vref Scan: 0
1229 13:59:50.977616
1230 13:59:50.978049 RX Vref 0 -> 0, step: 1
1231 13:59:50.978353
1232 13:59:50.980318 RX Delay -130 -> 252, step: 16
1233 13:59:50.983898 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1234 13:59:50.990261 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1235 13:59:50.993516 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1236 13:59:50.997048 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1237 13:59:51.000497 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1238 13:59:51.003980 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1239 13:59:51.006912 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1240 13:59:51.013742 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1241 13:59:51.016864 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1242 13:59:51.020347 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1243 13:59:51.023567 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1244 13:59:51.027219 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1245 13:59:51.033863 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1246 13:59:51.037192 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1247 13:59:51.040318 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1248 13:59:51.043864 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1249 13:59:51.044424 ==
1250 13:59:51.047132 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 13:59:51.054107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 13:59:51.054485 ==
1253 13:59:51.054780 DQS Delay:
1254 13:59:51.055054 DQS0 = 0, DQS1 = 0
1255 13:59:51.057297 DQM Delay:
1256 13:59:51.057733 DQM0 = 80, DQM1 = 69
1257 13:59:51.060723 DQ Delay:
1258 13:59:51.064092 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1259 13:59:51.067416 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1260 13:59:51.067821 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1261 13:59:51.074368 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1262 13:59:51.074740
1263 13:59:51.075033
1264 13:59:51.075303 ==
1265 13:59:51.077345 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 13:59:51.080796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 13:59:51.081170 ==
1268 13:59:51.081464
1269 13:59:51.081834
1270 13:59:51.084027 TX Vref Scan disable
1271 13:59:51.084399 == TX Byte 0 ==
1272 13:59:51.090771 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1273 13:59:51.093948 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1274 13:59:51.094323 == TX Byte 1 ==
1275 13:59:51.100743 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1276 13:59:51.103919 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1277 13:59:51.104293 ==
1278 13:59:51.107347 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 13:59:51.110696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 13:59:51.111071 ==
1281 13:59:51.124389 TX Vref=22, minBit 13, minWin=26, winSum=434
1282 13:59:51.127696 TX Vref=24, minBit 1, minWin=27, winSum=441
1283 13:59:51.131177 TX Vref=26, minBit 2, minWin=27, winSum=440
1284 13:59:51.134412 TX Vref=28, minBit 8, minWin=27, winSum=443
1285 13:59:51.137952 TX Vref=30, minBit 3, minWin=27, winSum=447
1286 13:59:51.141158 TX Vref=32, minBit 8, minWin=27, winSum=444
1287 13:59:51.147693 [TxChooseVref] Worse bit 3, Min win 27, Win sum 447, Final Vref 30
1288 13:59:51.148102
1289 13:59:51.151066 Final TX Range 1 Vref 30
1290 13:59:51.151473
1291 13:59:51.151793 ==
1292 13:59:51.154485 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 13:59:51.157576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 13:59:51.157981 ==
1295 13:59:51.158298
1296 13:59:51.160754
1297 13:59:51.161169 TX Vref Scan disable
1298 13:59:51.164439 == TX Byte 0 ==
1299 13:59:51.167437 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1300 13:59:51.170909 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1301 13:59:51.174537 == TX Byte 1 ==
1302 13:59:51.177773 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1303 13:59:51.180998 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1304 13:59:51.184210
1305 13:59:51.184613 [DATLAT]
1306 13:59:51.184931 Freq=800, CH0 RK1
1307 13:59:51.185230
1308 13:59:51.187626 DATLAT Default: 0xa
1309 13:59:51.188027 0, 0xFFFF, sum = 0
1310 13:59:51.191040 1, 0xFFFF, sum = 0
1311 13:59:51.191569 2, 0xFFFF, sum = 0
1312 13:59:51.194131 3, 0xFFFF, sum = 0
1313 13:59:51.197591 4, 0xFFFF, sum = 0
1314 13:59:51.198005 5, 0xFFFF, sum = 0
1315 13:59:51.200815 6, 0xFFFF, sum = 0
1316 13:59:51.201225 7, 0xFFFF, sum = 0
1317 13:59:51.204303 8, 0xFFFF, sum = 0
1318 13:59:51.204773 9, 0x0, sum = 1
1319 13:59:51.205101 10, 0x0, sum = 2
1320 13:59:51.207359 11, 0x0, sum = 3
1321 13:59:51.207769 12, 0x0, sum = 4
1322 13:59:51.210951 best_step = 10
1323 13:59:51.211350
1324 13:59:51.211662 ==
1325 13:59:51.214111 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 13:59:51.217864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 13:59:51.218296 ==
1328 13:59:51.221120 RX Vref Scan: 0
1329 13:59:51.221563
1330 13:59:51.221888 RX Vref 0 -> 0, step: 1
1331 13:59:51.222227
1332 13:59:51.224137 RX Delay -111 -> 252, step: 8
1333 13:59:51.231109 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1334 13:59:51.234390 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1335 13:59:51.237757 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1336 13:59:51.241264 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1337 13:59:51.244243 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1338 13:59:51.250849 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1339 13:59:51.254162 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1340 13:59:51.257646 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1341 13:59:51.260989 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1342 13:59:51.264485 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1343 13:59:51.270870 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1344 13:59:51.274462 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1345 13:59:51.277542 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1346 13:59:51.280738 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1347 13:59:51.284357 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1348 13:59:51.290719 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1349 13:59:51.291127 ==
1350 13:59:51.294325 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 13:59:51.297506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 13:59:51.297924 ==
1353 13:59:51.298241 DQS Delay:
1354 13:59:51.300785 DQS0 = 0, DQS1 = 0
1355 13:59:51.301204 DQM Delay:
1356 13:59:51.304371 DQM0 = 78, DQM1 = 70
1357 13:59:51.304786 DQ Delay:
1358 13:59:51.307457 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1359 13:59:51.310988 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1360 13:59:51.313954 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1361 13:59:51.317625 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =76
1362 13:59:51.318028
1363 13:59:51.318341
1364 13:59:51.327389 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1365 13:59:51.327797 CH0 RK1: MR19=606, MR18=4A26
1366 13:59:51.333979 CH0_RK1: MR19=0x606, MR18=0x4A26, DQSOSC=391, MR23=63, INC=96, DEC=64
1367 13:59:51.337541 [RxdqsGatingPostProcess] freq 800
1368 13:59:51.344012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1369 13:59:51.347579 Pre-setting of DQS Precalculation
1370 13:59:51.350671 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1371 13:59:51.351084 ==
1372 13:59:51.354158 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 13:59:51.357584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 13:59:51.357996 ==
1375 13:59:51.364305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1376 13:59:51.370611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1377 13:59:51.379276 [CA 0] Center 36 (6~66) winsize 61
1378 13:59:51.382589 [CA 1] Center 36 (6~67) winsize 62
1379 13:59:51.385948 [CA 2] Center 34 (4~64) winsize 61
1380 13:59:51.389140 [CA 3] Center 34 (4~64) winsize 61
1381 13:59:51.392466 [CA 4] Center 35 (5~65) winsize 61
1382 13:59:51.396076 [CA 5] Center 34 (4~64) winsize 61
1383 13:59:51.396482
1384 13:59:51.399323 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1385 13:59:51.399733
1386 13:59:51.402495 [CATrainingPosCal] consider 1 rank data
1387 13:59:51.405709 u2DelayCellTimex100 = 270/100 ps
1388 13:59:51.409065 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1389 13:59:51.415591 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1390 13:59:51.419006 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1391 13:59:51.422249 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1392 13:59:51.425836 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1393 13:59:51.429044 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1394 13:59:51.429529
1395 13:59:51.432197 CA PerBit enable=1, Macro0, CA PI delay=34
1396 13:59:51.432754
1397 13:59:51.435818 [CBTSetCACLKResult] CA Dly = 34
1398 13:59:51.436224 CS Dly: 5 (0~36)
1399 13:59:51.438982 ==
1400 13:59:51.442602 Dram Type= 6, Freq= 0, CH_1, rank 1
1401 13:59:51.445668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 13:59:51.446078 ==
1403 13:59:51.449304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 13:59:51.455837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 13:59:51.465319 [CA 0] Center 37 (7~67) winsize 61
1406 13:59:51.468813 [CA 1] Center 36 (6~67) winsize 62
1407 13:59:51.472128 [CA 2] Center 34 (4~65) winsize 62
1408 13:59:51.475657 [CA 3] Center 34 (4~64) winsize 61
1409 13:59:51.478839 [CA 4] Center 34 (4~65) winsize 62
1410 13:59:51.482033 [CA 5] Center 33 (3~64) winsize 62
1411 13:59:51.482458
1412 13:59:51.485437 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1413 13:59:51.485892
1414 13:59:51.488837 [CATrainingPosCal] consider 2 rank data
1415 13:59:51.492212 u2DelayCellTimex100 = 270/100 ps
1416 13:59:51.495594 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1417 13:59:51.499171 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1418 13:59:51.502429 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1419 13:59:51.508817 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1420 13:59:51.512374 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1421 13:59:51.515664 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1422 13:59:51.516082
1423 13:59:51.519287 CA PerBit enable=1, Macro0, CA PI delay=34
1424 13:59:51.519707
1425 13:59:51.522425 [CBTSetCACLKResult] CA Dly = 34
1426 13:59:51.522844 CS Dly: 6 (0~38)
1427 13:59:51.523171
1428 13:59:51.525684 ----->DramcWriteLeveling(PI) begin...
1429 13:59:51.526191 ==
1430 13:59:51.529631 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 13:59:51.533052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 13:59:51.537070 ==
1433 13:59:51.537527 Write leveling (Byte 0): 29 => 29
1434 13:59:51.540957 Write leveling (Byte 1): 30 => 30
1435 13:59:51.544729 DramcWriteLeveling(PI) end<-----
1436 13:59:51.545147
1437 13:59:51.545595 ==
1438 13:59:51.548063 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 13:59:51.552191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 13:59:51.552609 ==
1441 13:59:51.555738 [Gating] SW mode calibration
1442 13:59:51.563223 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1443 13:59:51.566468 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1444 13:59:51.569780 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1445 13:59:51.576590 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1446 13:59:51.579696 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 13:59:51.583087 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:59:51.590022 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:59:51.593435 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 13:59:51.596773 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:59:51.603091 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:59:51.606537 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:59:51.609867 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:59:51.616630 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:59:51.619941 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:59:51.623129 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:59:51.629878 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:59:51.633018 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:59:51.636319 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:59:51.639490 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:59:51.645944 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1462 13:59:51.649643 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1463 13:59:51.652687 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:59:51.659549 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:59:51.662559 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:59:51.665929 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:59:51.672851 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:59:51.676139 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:59:51.679644 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:59:51.686186 0 9 8 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
1471 13:59:51.689376 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 13:59:51.692633 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 13:59:51.699536 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 13:59:51.702864 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 13:59:51.705909 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:59:51.712894 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:59:51.716122 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1478 13:59:51.719343 0 10 8 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
1479 13:59:51.725953 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:59:51.729264 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:59:51.732557 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:59:51.739501 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:59:51.742773 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:59:51.746017 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:59:51.749462 0 11 4 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
1486 13:59:51.756227 0 11 8 | B1->B0 | 3939 3a3a | 0 0 | (0 0) (0 0)
1487 13:59:51.759609 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 13:59:51.762780 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 13:59:51.769658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 13:59:51.772887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 13:59:51.776089 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:59:51.782920 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:59:51.786052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:59:51.789614 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1495 13:59:51.796102 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1496 13:59:51.799412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 13:59:51.802797 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:59:51.809338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:59:51.812609 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:59:51.816277 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:59:51.822746 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:59:51.826207 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:59:51.829373 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:59:51.833014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:59:51.839511 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:59:51.843047 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:59:51.846127 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:59:51.852942 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:59:51.856141 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:59:51.859296 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 13:59:51.862613 Total UI for P1: 0, mck2ui 16
1512 13:59:51.865993 best dqsien dly found for B0: ( 0, 14, 6)
1513 13:59:51.869282 Total UI for P1: 0, mck2ui 16
1514 13:59:51.872596 best dqsien dly found for B1: ( 0, 14, 6)
1515 13:59:51.876086 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1516 13:59:51.879191 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1517 13:59:51.879301
1518 13:59:51.886174 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1519 13:59:51.889351 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1520 13:59:51.889454 [Gating] SW calibration Done
1521 13:59:51.892650 ==
1522 13:59:51.895946 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 13:59:51.899233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 13:59:51.899345 ==
1525 13:59:51.899439 RX Vref Scan: 0
1526 13:59:51.899531
1527 13:59:51.902635 RX Vref 0 -> 0, step: 1
1528 13:59:51.902738
1529 13:59:51.905990 RX Delay -130 -> 252, step: 16
1530 13:59:51.909250 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1531 13:59:51.912835 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1532 13:59:51.916016 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1533 13:59:51.922868 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1534 13:59:51.926267 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1535 13:59:51.929675 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1536 13:59:51.932897 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1537 13:59:51.936287 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1538 13:59:51.942640 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1539 13:59:51.946056 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1540 13:59:51.949634 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1541 13:59:51.952597 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1542 13:59:51.955884 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1543 13:59:51.962508 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1544 13:59:51.965786 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1545 13:59:51.969250 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1546 13:59:51.969377 ==
1547 13:59:51.972433 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 13:59:51.975919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1549 13:59:51.979289 ==
1550 13:59:51.979402 DQS Delay:
1551 13:59:51.979501 DQS0 = 0, DQS1 = 0
1552 13:59:51.982506 DQM Delay:
1553 13:59:51.982581 DQM0 = 81, DQM1 = 70
1554 13:59:51.985800 DQ Delay:
1555 13:59:51.985917 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1556 13:59:51.989272 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1557 13:59:51.992596 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1558 13:59:51.995820 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1559 13:59:51.995936
1560 13:59:51.999151
1561 13:59:51.999254 ==
1562 13:59:52.002537 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 13:59:52.005899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 13:59:52.005981 ==
1565 13:59:52.006045
1566 13:59:52.006105
1567 13:59:52.009216 TX Vref Scan disable
1568 13:59:52.009332 == TX Byte 0 ==
1569 13:59:52.015817 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1570 13:59:52.019153 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1571 13:59:52.019236 == TX Byte 1 ==
1572 13:59:52.025912 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1573 13:59:52.029079 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1574 13:59:52.029193 ==
1575 13:59:52.032468 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 13:59:52.035813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 13:59:52.035932 ==
1578 13:59:52.049277 TX Vref=22, minBit 1, minWin=26, winSum=438
1579 13:59:52.052571 TX Vref=24, minBit 1, minWin=26, winSum=440
1580 13:59:52.055879 TX Vref=26, minBit 1, minWin=27, winSum=444
1581 13:59:52.059195 TX Vref=28, minBit 1, minWin=27, winSum=444
1582 13:59:52.062288 TX Vref=30, minBit 4, minWin=27, winSum=447
1583 13:59:52.068992 TX Vref=32, minBit 0, minWin=27, winSum=445
1584 13:59:52.072443 [TxChooseVref] Worse bit 4, Min win 27, Win sum 447, Final Vref 30
1585 13:59:52.072529
1586 13:59:52.075929 Final TX Range 1 Vref 30
1587 13:59:52.076014
1588 13:59:52.076080 ==
1589 13:59:52.079063 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 13:59:52.082531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 13:59:52.082615 ==
1592 13:59:52.082680
1593 13:59:52.085690
1594 13:59:52.085772 TX Vref Scan disable
1595 13:59:52.089205 == TX Byte 0 ==
1596 13:59:52.092567 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1597 13:59:52.099080 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1598 13:59:52.099164 == TX Byte 1 ==
1599 13:59:52.102657 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1600 13:59:52.105756 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1601 13:59:52.105839
1602 13:59:52.109391 [DATLAT]
1603 13:59:52.109479 Freq=800, CH1 RK0
1604 13:59:52.109547
1605 13:59:52.113006 DATLAT Default: 0xa
1606 13:59:52.113089 0, 0xFFFF, sum = 0
1607 13:59:52.116221 1, 0xFFFF, sum = 0
1608 13:59:52.116305 2, 0xFFFF, sum = 0
1609 13:59:52.119495 3, 0xFFFF, sum = 0
1610 13:59:52.119579 4, 0xFFFF, sum = 0
1611 13:59:52.122859 5, 0xFFFF, sum = 0
1612 13:59:52.122943 6, 0xFFFF, sum = 0
1613 13:59:52.126528 7, 0xFFFF, sum = 0
1614 13:59:52.126611 8, 0xFFFF, sum = 0
1615 13:59:52.129399 9, 0x0, sum = 1
1616 13:59:52.129492 10, 0x0, sum = 2
1617 13:59:52.133020 11, 0x0, sum = 3
1618 13:59:52.133104 12, 0x0, sum = 4
1619 13:59:52.136179 best_step = 10
1620 13:59:52.136262
1621 13:59:52.136327 ==
1622 13:59:52.139543 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 13:59:52.143055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 13:59:52.143138 ==
1625 13:59:52.146203 RX Vref Scan: 1
1626 13:59:52.146285
1627 13:59:52.146349 Set Vref Range= 32 -> 127
1628 13:59:52.146410
1629 13:59:52.149586 RX Vref 32 -> 127, step: 1
1630 13:59:52.149668
1631 13:59:52.152766 RX Delay -111 -> 252, step: 8
1632 13:59:52.152848
1633 13:59:52.156019 Set Vref, RX VrefLevel [Byte0]: 32
1634 13:59:52.159626 [Byte1]: 32
1635 13:59:52.159733
1636 13:59:52.162858 Set Vref, RX VrefLevel [Byte0]: 33
1637 13:59:52.166367 [Byte1]: 33
1638 13:59:52.169560
1639 13:59:52.169648 Set Vref, RX VrefLevel [Byte0]: 34
1640 13:59:52.172936 [Byte1]: 34
1641 13:59:52.177196
1642 13:59:52.177278 Set Vref, RX VrefLevel [Byte0]: 35
1643 13:59:52.180513 [Byte1]: 35
1644 13:59:52.184693
1645 13:59:52.184805 Set Vref, RX VrefLevel [Byte0]: 36
1646 13:59:52.188141 [Byte1]: 36
1647 13:59:52.192563
1648 13:59:52.192664 Set Vref, RX VrefLevel [Byte0]: 37
1649 13:59:52.195799 [Byte1]: 37
1650 13:59:52.199899
1651 13:59:52.199997 Set Vref, RX VrefLevel [Byte0]: 38
1652 13:59:52.203397 [Byte1]: 38
1653 13:59:52.207722
1654 13:59:52.207801 Set Vref, RX VrefLevel [Byte0]: 39
1655 13:59:52.211339 [Byte1]: 39
1656 13:59:52.215374
1657 13:59:52.215473 Set Vref, RX VrefLevel [Byte0]: 40
1658 13:59:52.218983 [Byte1]: 40
1659 13:59:52.222981
1660 13:59:52.223058 Set Vref, RX VrefLevel [Byte0]: 41
1661 13:59:52.226655 [Byte1]: 41
1662 13:59:52.230589
1663 13:59:52.230662 Set Vref, RX VrefLevel [Byte0]: 42
1664 13:59:52.233858 [Byte1]: 42
1665 13:59:52.238612
1666 13:59:52.238681 Set Vref, RX VrefLevel [Byte0]: 43
1667 13:59:52.241879 [Byte1]: 43
1668 13:59:52.246101
1669 13:59:52.246170 Set Vref, RX VrefLevel [Byte0]: 44
1670 13:59:52.249449 [Byte1]: 44
1671 13:59:52.253615
1672 13:59:52.253688 Set Vref, RX VrefLevel [Byte0]: 45
1673 13:59:52.256763 [Byte1]: 45
1674 13:59:52.261349
1675 13:59:52.261455 Set Vref, RX VrefLevel [Byte0]: 46
1676 13:59:52.264712 [Byte1]: 46
1677 13:59:52.268982
1678 13:59:52.269069 Set Vref, RX VrefLevel [Byte0]: 47
1679 13:59:52.275440 [Byte1]: 47
1680 13:59:52.275521
1681 13:59:52.278736 Set Vref, RX VrefLevel [Byte0]: 48
1682 13:59:52.282012 [Byte1]: 48
1683 13:59:52.282092
1684 13:59:52.285431 Set Vref, RX VrefLevel [Byte0]: 49
1685 13:59:52.288775 [Byte1]: 49
1686 13:59:52.288856
1687 13:59:52.292029 Set Vref, RX VrefLevel [Byte0]: 50
1688 13:59:52.295341 [Byte1]: 50
1689 13:59:52.299561
1690 13:59:52.299641 Set Vref, RX VrefLevel [Byte0]: 51
1691 13:59:52.302664 [Byte1]: 51
1692 13:59:52.307170
1693 13:59:52.307250 Set Vref, RX VrefLevel [Byte0]: 52
1694 13:59:52.310443 [Byte1]: 52
1695 13:59:52.314775
1696 13:59:52.314873 Set Vref, RX VrefLevel [Byte0]: 53
1697 13:59:52.318254 [Byte1]: 53
1698 13:59:52.322471
1699 13:59:52.322551 Set Vref, RX VrefLevel [Byte0]: 54
1700 13:59:52.325948 [Byte1]: 54
1701 13:59:52.330195
1702 13:59:52.330275 Set Vref, RX VrefLevel [Byte0]: 55
1703 13:59:52.333375 [Byte1]: 55
1704 13:59:52.337874
1705 13:59:52.337960 Set Vref, RX VrefLevel [Byte0]: 56
1706 13:59:52.341062 [Byte1]: 56
1707 13:59:52.345423
1708 13:59:52.345526 Set Vref, RX VrefLevel [Byte0]: 57
1709 13:59:52.348659 [Byte1]: 57
1710 13:59:52.353124
1711 13:59:52.353230 Set Vref, RX VrefLevel [Byte0]: 58
1712 13:59:52.356245 [Byte1]: 58
1713 13:59:52.360803
1714 13:59:52.360883 Set Vref, RX VrefLevel [Byte0]: 59
1715 13:59:52.364133 [Byte1]: 59
1716 13:59:52.368515
1717 13:59:52.368596 Set Vref, RX VrefLevel [Byte0]: 60
1718 13:59:52.371876 [Byte1]: 60
1719 13:59:52.375857
1720 13:59:52.375937 Set Vref, RX VrefLevel [Byte0]: 61
1721 13:59:52.379140 [Byte1]: 61
1722 13:59:52.383530
1723 13:59:52.383610 Set Vref, RX VrefLevel [Byte0]: 62
1724 13:59:52.387328 [Byte1]: 62
1725 13:59:52.391249
1726 13:59:52.391329 Set Vref, RX VrefLevel [Byte0]: 63
1727 13:59:52.394492 [Byte1]: 63
1728 13:59:52.399222
1729 13:59:52.399302 Set Vref, RX VrefLevel [Byte0]: 64
1730 13:59:52.402414 [Byte1]: 64
1731 13:59:52.406446
1732 13:59:52.406525 Set Vref, RX VrefLevel [Byte0]: 65
1733 13:59:52.410030 [Byte1]: 65
1734 13:59:52.414216
1735 13:59:52.414296 Set Vref, RX VrefLevel [Byte0]: 66
1736 13:59:52.417686 [Byte1]: 66
1737 13:59:52.421992
1738 13:59:52.422073 Set Vref, RX VrefLevel [Byte0]: 67
1739 13:59:52.425052 [Byte1]: 67
1740 13:59:52.429337
1741 13:59:52.429451 Set Vref, RX VrefLevel [Byte0]: 68
1742 13:59:52.432933 [Byte1]: 68
1743 13:59:52.437225
1744 13:59:52.437305 Set Vref, RX VrefLevel [Byte0]: 69
1745 13:59:52.440605 [Byte1]: 69
1746 13:59:52.444685
1747 13:59:52.444765 Set Vref, RX VrefLevel [Byte0]: 70
1748 13:59:52.448442 [Byte1]: 70
1749 13:59:52.452530
1750 13:59:52.452610 Set Vref, RX VrefLevel [Byte0]: 71
1751 13:59:52.456034 [Byte1]: 71
1752 13:59:52.460111
1753 13:59:52.460190 Set Vref, RX VrefLevel [Byte0]: 72
1754 13:59:52.463445 [Byte1]: 72
1755 13:59:52.467767
1756 13:59:52.467848 Set Vref, RX VrefLevel [Byte0]: 73
1757 13:59:52.471064 [Byte1]: 73
1758 13:59:52.475594
1759 13:59:52.475674 Set Vref, RX VrefLevel [Byte0]: 74
1760 13:59:52.478778 [Byte1]: 74
1761 13:59:52.483209
1762 13:59:52.483288 Set Vref, RX VrefLevel [Byte0]: 75
1763 13:59:52.486410 [Byte1]: 75
1764 13:59:52.490938
1765 13:59:52.491018 Set Vref, RX VrefLevel [Byte0]: 76
1766 13:59:52.494187 [Byte1]: 76
1767 13:59:52.498182
1768 13:59:52.498269 Set Vref, RX VrefLevel [Byte0]: 77
1769 13:59:52.501751 [Byte1]: 77
1770 13:59:52.505856
1771 13:59:52.505936 Final RX Vref Byte 0 = 57 to rank0
1772 13:59:52.509303 Final RX Vref Byte 1 = 56 to rank0
1773 13:59:52.513017 Final RX Vref Byte 0 = 57 to rank1
1774 13:59:52.515985 Final RX Vref Byte 1 = 56 to rank1==
1775 13:59:52.519689 Dram Type= 6, Freq= 0, CH_1, rank 0
1776 13:59:52.526231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1777 13:59:52.526341 ==
1778 13:59:52.526433 DQS Delay:
1779 13:59:52.526502 DQS0 = 0, DQS1 = 0
1780 13:59:52.529425 DQM Delay:
1781 13:59:52.529620 DQM0 = 81, DQM1 = 71
1782 13:59:52.532338 DQ Delay:
1783 13:59:52.535841 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1784 13:59:52.535922 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1785 13:59:52.539147 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1786 13:59:52.546131 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1787 13:59:52.546212
1788 13:59:52.546276
1789 13:59:52.552577 [DQSOSCAuto] RK0, (LSB)MR18= 0x151f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1790 13:59:52.556066 CH1 RK0: MR19=606, MR18=151F
1791 13:59:52.562590 CH1_RK0: MR19=0x606, MR18=0x151F, DQSOSC=402, MR23=63, INC=91, DEC=60
1792 13:59:52.562671
1793 13:59:52.566219 ----->DramcWriteLeveling(PI) begin...
1794 13:59:52.566302 ==
1795 13:59:52.569384 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 13:59:52.572976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 13:59:52.573058 ==
1798 13:59:52.575963 Write leveling (Byte 0): 27 => 27
1799 13:59:52.579541 Write leveling (Byte 1): 27 => 27
1800 13:59:52.582704 DramcWriteLeveling(PI) end<-----
1801 13:59:52.582785
1802 13:59:52.582848 ==
1803 13:59:52.586172 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 13:59:52.589367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 13:59:52.589480 ==
1806 13:59:52.593078 [Gating] SW mode calibration
1807 13:59:52.599461 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1808 13:59:52.605971 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1809 13:59:52.609565 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1810 13:59:52.612492 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1811 13:59:52.619469 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:59:52.622639 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:59:52.625935 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:59:52.632727 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:59:52.635874 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:59:52.639232 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:59:52.646029 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:59:52.649400 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:59:52.652420 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:59:52.659461 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:59:52.662983 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:59:52.666044 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:59:52.669463 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:59:52.675844 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:59:52.679331 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:59:52.682867 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1827 13:59:52.689376 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1828 13:59:52.692564 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:59:52.696034 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:59:52.702703 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:59:52.705901 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:59:52.709397 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:59:52.716012 0 9 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1834 13:59:52.719347 0 9 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1835 13:59:52.722853 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1836 13:59:52.729408 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 13:59:52.732611 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 13:59:52.736098 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 13:59:52.742523 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 13:59:52.746063 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 13:59:52.749372 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1842 13:59:52.756031 0 10 4 | B1->B0 | 3131 2828 | 1 1 | (1 0) (1 0)
1843 13:59:52.759185 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1844 13:59:52.762709 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:59:52.766048 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:59:52.772590 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:59:52.775927 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:59:52.779233 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:59:52.785826 0 11 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1850 13:59:52.788942 0 11 4 | B1->B0 | 2d2d 3939 | 1 0 | (0 0) (0 0)
1851 13:59:52.792324 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1852 13:59:52.799045 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 13:59:52.802211 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 13:59:52.805655 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 13:59:52.812378 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 13:59:52.815826 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 13:59:52.818932 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 13:59:52.825798 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1859 13:59:52.829055 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1860 13:59:52.832292 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:59:52.838771 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:59:52.842585 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:59:52.845573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:59:52.852551 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:59:52.855472 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:59:52.858884 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:59:52.865689 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:59:52.868824 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:59:52.872337 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:59:52.878822 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:59:52.882105 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:59:52.885514 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:59:52.892098 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:59:52.895626 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1875 13:59:52.898935 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1876 13:59:52.902148 Total UI for P1: 0, mck2ui 16
1877 13:59:52.905439 best dqsien dly found for B0: ( 0, 14, 4)
1878 13:59:52.908749 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 13:59:52.912203 Total UI for P1: 0, mck2ui 16
1880 13:59:52.915445 best dqsien dly found for B1: ( 0, 14, 6)
1881 13:59:52.918921 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1882 13:59:52.922047 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1883 13:59:52.925409
1884 13:59:52.928738 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1885 13:59:52.932226 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1886 13:59:52.935772 [Gating] SW calibration Done
1887 13:59:52.935869 ==
1888 13:59:52.939010 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 13:59:52.942198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 13:59:52.942279 ==
1891 13:59:52.942343 RX Vref Scan: 0
1892 13:59:52.942403
1893 13:59:52.945455 RX Vref 0 -> 0, step: 1
1894 13:59:52.945574
1895 13:59:52.948948 RX Delay -130 -> 252, step: 16
1896 13:59:52.952546 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1897 13:59:52.955765 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1898 13:59:52.958982 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1899 13:59:52.965745 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1900 13:59:52.968977 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1901 13:59:52.972230 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1902 13:59:52.975497 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1903 13:59:52.979180 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1904 13:59:52.985614 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1905 13:59:52.988834 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1906 13:59:52.992368 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1907 13:59:52.995627 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1908 13:59:52.998812 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1909 13:59:53.005430 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1910 13:59:53.008951 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1911 13:59:53.012267 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1912 13:59:53.012351 ==
1913 13:59:53.015505 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 13:59:53.019098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 13:59:53.022224 ==
1916 13:59:53.022307 DQS Delay:
1917 13:59:53.022392 DQS0 = 0, DQS1 = 0
1918 13:59:53.025455 DQM Delay:
1919 13:59:53.025582 DQM0 = 80, DQM1 = 77
1920 13:59:53.029018 DQ Delay:
1921 13:59:53.029101 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1922 13:59:53.032099 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1923 13:59:53.035627 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =69
1924 13:59:53.038795 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1925 13:59:53.038879
1926 13:59:53.042299
1927 13:59:53.042381 ==
1928 13:59:53.045734 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 13:59:53.048927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 13:59:53.049011 ==
1931 13:59:53.049096
1932 13:59:53.049176
1933 13:59:53.052227 TX Vref Scan disable
1934 13:59:53.052421 == TX Byte 0 ==
1935 13:59:53.058922 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1936 13:59:53.062237 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1937 13:59:53.062322 == TX Byte 1 ==
1938 13:59:53.069029 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1939 13:59:53.072301 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1940 13:59:53.072385 ==
1941 13:59:53.075712 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 13:59:53.079005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 13:59:53.079089 ==
1944 13:59:53.092020 TX Vref=22, minBit 1, minWin=28, winSum=450
1945 13:59:53.095308 TX Vref=24, minBit 6, minWin=27, winSum=454
1946 13:59:53.098974 TX Vref=26, minBit 0, minWin=28, winSum=455
1947 13:59:53.102163 TX Vref=28, minBit 5, minWin=27, winSum=457
1948 13:59:53.105220 TX Vref=30, minBit 1, minWin=28, winSum=463
1949 13:59:53.108751 TX Vref=32, minBit 1, minWin=27, winSum=455
1950 13:59:53.115386 [TxChooseVref] Worse bit 1, Min win 28, Win sum 463, Final Vref 30
1951 13:59:53.115492
1952 13:59:53.118863 Final TX Range 1 Vref 30
1953 13:59:53.118946
1954 13:59:53.119030 ==
1955 13:59:53.122099 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 13:59:53.125686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 13:59:53.125770 ==
1958 13:59:53.125855
1959 13:59:53.128706
1960 13:59:53.128789 TX Vref Scan disable
1961 13:59:53.131976 == TX Byte 0 ==
1962 13:59:53.135502 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1963 13:59:53.138455 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1964 13:59:53.142110 == TX Byte 1 ==
1965 13:59:53.145332 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1966 13:59:53.148631 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1967 13:59:53.152140
1968 13:59:53.152223 [DATLAT]
1969 13:59:53.152307 Freq=800, CH1 RK1
1970 13:59:53.152387
1971 13:59:53.155264 DATLAT Default: 0xa
1972 13:59:53.155346 0, 0xFFFF, sum = 0
1973 13:59:53.158746 1, 0xFFFF, sum = 0
1974 13:59:53.158830 2, 0xFFFF, sum = 0
1975 13:59:53.161833 3, 0xFFFF, sum = 0
1976 13:59:53.161918 4, 0xFFFF, sum = 0
1977 13:59:53.165600 5, 0xFFFF, sum = 0
1978 13:59:53.165684 6, 0xFFFF, sum = 0
1979 13:59:53.168701 7, 0xFFFF, sum = 0
1980 13:59:53.168786 8, 0xFFFF, sum = 0
1981 13:59:53.171948 9, 0x0, sum = 1
1982 13:59:53.172033 10, 0x0, sum = 2
1983 13:59:53.175592 11, 0x0, sum = 3
1984 13:59:53.175677 12, 0x0, sum = 4
1985 13:59:53.178874 best_step = 10
1986 13:59:53.178957
1987 13:59:53.179041 ==
1988 13:59:53.182099 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 13:59:53.185212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 13:59:53.185297 ==
1991 13:59:53.188800 RX Vref Scan: 0
1992 13:59:53.188883
1993 13:59:53.188967 RX Vref 0 -> 0, step: 1
1994 13:59:53.189047
1995 13:59:53.191904 RX Delay -111 -> 252, step: 8
1996 13:59:53.198679 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1997 13:59:53.202159 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1998 13:59:53.205255 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1999 13:59:53.208928 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2000 13:59:53.212124 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2001 13:59:53.218393 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2002 13:59:53.221876 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2003 13:59:53.225129 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2004 13:59:53.228623 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2005 13:59:53.232038 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2006 13:59:53.238642 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2007 13:59:53.241885 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2008 13:59:53.245373 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2009 13:59:53.248872 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2010 13:59:53.252024 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2011 13:59:53.258723 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2012 13:59:53.258796 ==
2013 13:59:53.262266 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 13:59:53.265386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 13:59:53.265530 ==
2016 13:59:53.265617 DQS Delay:
2017 13:59:53.268817 DQS0 = 0, DQS1 = 0
2018 13:59:53.268905 DQM Delay:
2019 13:59:53.272250 DQM0 = 77, DQM1 = 74
2020 13:59:53.272335 DQ Delay:
2021 13:59:53.275697 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2022 13:59:53.278810 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2023 13:59:53.282367 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =64
2024 13:59:53.285421 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2025 13:59:53.285560
2026 13:59:53.285639
2027 13:59:53.292126 [DQSOSCAuto] RK1, (LSB)MR18= 0x2038, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2028 13:59:53.295695 CH1 RK1: MR19=606, MR18=2038
2029 13:59:53.302327 CH1_RK1: MR19=0x606, MR18=0x2038, DQSOSC=395, MR23=63, INC=94, DEC=63
2030 13:59:53.305746 [RxdqsGatingPostProcess] freq 800
2031 13:59:53.312435 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2032 13:59:53.312543 Pre-setting of DQS Precalculation
2033 13:59:53.318922 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2034 13:59:53.325363 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2035 13:59:53.332382 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2036 13:59:53.332466
2037 13:59:53.332531
2038 13:59:53.335434 [Calibration Summary] 1600 Mbps
2039 13:59:53.338855 CH 0, Rank 0
2040 13:59:53.338936 SW Impedance : PASS
2041 13:59:53.342247 DUTY Scan : NO K
2042 13:59:53.345215 ZQ Calibration : PASS
2043 13:59:53.345295 Jitter Meter : NO K
2044 13:59:53.348858 CBT Training : PASS
2045 13:59:53.352212 Write leveling : PASS
2046 13:59:53.352310 RX DQS gating : PASS
2047 13:59:53.355288 RX DQ/DQS(RDDQC) : PASS
2048 13:59:53.355367 TX DQ/DQS : PASS
2049 13:59:53.358911 RX DATLAT : PASS
2050 13:59:53.362050 RX DQ/DQS(Engine): PASS
2051 13:59:53.362130 TX OE : NO K
2052 13:59:53.365208 All Pass.
2053 13:59:53.365287
2054 13:59:53.365349 CH 0, Rank 1
2055 13:59:53.368765 SW Impedance : PASS
2056 13:59:53.368847 DUTY Scan : NO K
2057 13:59:53.371957 ZQ Calibration : PASS
2058 13:59:53.375516 Jitter Meter : NO K
2059 13:59:53.375596 CBT Training : PASS
2060 13:59:53.378626 Write leveling : PASS
2061 13:59:53.381859 RX DQS gating : PASS
2062 13:59:53.381939 RX DQ/DQS(RDDQC) : PASS
2063 13:59:53.385263 TX DQ/DQS : PASS
2064 13:59:53.388554 RX DATLAT : PASS
2065 13:59:53.388645 RX DQ/DQS(Engine): PASS
2066 13:59:53.391835 TX OE : NO K
2067 13:59:53.391917 All Pass.
2068 13:59:53.391980
2069 13:59:53.395453 CH 1, Rank 0
2070 13:59:53.395533 SW Impedance : PASS
2071 13:59:53.398524 DUTY Scan : NO K
2072 13:59:53.402045 ZQ Calibration : PASS
2073 13:59:53.402124 Jitter Meter : NO K
2074 13:59:53.405250 CBT Training : PASS
2075 13:59:53.405330 Write leveling : PASS
2076 13:59:53.408723 RX DQS gating : PASS
2077 13:59:53.412141 RX DQ/DQS(RDDQC) : PASS
2078 13:59:53.412220 TX DQ/DQS : PASS
2079 13:59:53.415269 RX DATLAT : PASS
2080 13:59:53.418410 RX DQ/DQS(Engine): PASS
2081 13:59:53.418489 TX OE : NO K
2082 13:59:53.421860 All Pass.
2083 13:59:53.421939
2084 13:59:53.422001 CH 1, Rank 1
2085 13:59:53.425349 SW Impedance : PASS
2086 13:59:53.425428 DUTY Scan : NO K
2087 13:59:53.428750 ZQ Calibration : PASS
2088 13:59:53.431979 Jitter Meter : NO K
2089 13:59:53.432058 CBT Training : PASS
2090 13:59:53.435315 Write leveling : PASS
2091 13:59:53.438481 RX DQS gating : PASS
2092 13:59:53.438559 RX DQ/DQS(RDDQC) : PASS
2093 13:59:53.442117 TX DQ/DQS : PASS
2094 13:59:53.445005 RX DATLAT : PASS
2095 13:59:53.445083 RX DQ/DQS(Engine): PASS
2096 13:59:53.448549 TX OE : NO K
2097 13:59:53.448629 All Pass.
2098 13:59:53.448691
2099 13:59:53.451821 DramC Write-DBI off
2100 13:59:53.455324 PER_BANK_REFRESH: Hybrid Mode
2101 13:59:53.455403 TX_TRACKING: ON
2102 13:59:53.458464 [GetDramInforAfterCalByMRR] Vendor 6.
2103 13:59:53.461930 [GetDramInforAfterCalByMRR] Revision 606.
2104 13:59:53.465264 [GetDramInforAfterCalByMRR] Revision 2 0.
2105 13:59:53.468493 MR0 0x3b3b
2106 13:59:53.468601 MR8 0x5151
2107 13:59:53.471666 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 13:59:53.471745
2109 13:59:53.471827 MR0 0x3b3b
2110 13:59:53.475232 MR8 0x5151
2111 13:59:53.478586 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 13:59:53.478666
2113 13:59:53.485313 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2114 13:59:53.491672 [FAST_K] Save calibration result to emmc
2115 13:59:53.495060 [FAST_K] Save calibration result to emmc
2116 13:59:53.495139 dram_init: config_dvfs: 1
2117 13:59:53.498431 dramc_set_vcore_voltage set vcore to 662500
2118 13:59:53.501714 Read voltage for 1200, 2
2119 13:59:53.501793 Vio18 = 0
2120 13:59:53.504980 Vcore = 662500
2121 13:59:53.505063 Vdram = 0
2122 13:59:53.505157 Vddq = 0
2123 13:59:53.508464 Vmddr = 0
2124 13:59:53.511723 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2125 13:59:53.518471 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2126 13:59:53.518553 MEM_TYPE=3, freq_sel=15
2127 13:59:53.521659 sv_algorithm_assistance_LP4_1600
2128 13:59:53.528301 ============ PULL DRAM RESETB DOWN ============
2129 13:59:53.531730 ========== PULL DRAM RESETB DOWN end =========
2130 13:59:53.534866 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2131 13:59:53.538409 ===================================
2132 13:59:53.541594 LPDDR4 DRAM CONFIGURATION
2133 13:59:53.545182 ===================================
2134 13:59:53.548478 EX_ROW_EN[0] = 0x0
2135 13:59:53.548560 EX_ROW_EN[1] = 0x0
2136 13:59:53.551705 LP4Y_EN = 0x0
2137 13:59:53.551787 WORK_FSP = 0x0
2138 13:59:53.554945 WL = 0x4
2139 13:59:53.555028 RL = 0x4
2140 13:59:53.558211 BL = 0x2
2141 13:59:53.558289 RPST = 0x0
2142 13:59:53.561739 RD_PRE = 0x0
2143 13:59:53.561813 WR_PRE = 0x1
2144 13:59:53.565250 WR_PST = 0x0
2145 13:59:53.565344 DBI_WR = 0x0
2146 13:59:53.568183 DBI_RD = 0x0
2147 13:59:53.568271 OTF = 0x1
2148 13:59:53.571932 ===================================
2149 13:59:53.574936 ===================================
2150 13:59:53.578435 ANA top config
2151 13:59:53.581685 ===================================
2152 13:59:53.581799 DLL_ASYNC_EN = 0
2153 13:59:53.584971 ALL_SLAVE_EN = 0
2154 13:59:53.588488 NEW_RANK_MODE = 1
2155 13:59:53.591577 DLL_IDLE_MODE = 1
2156 13:59:53.595163 LP45_APHY_COMB_EN = 1
2157 13:59:53.595250 TX_ODT_DIS = 1
2158 13:59:53.598438 NEW_8X_MODE = 1
2159 13:59:53.601845 ===================================
2160 13:59:53.605028 ===================================
2161 13:59:53.608463 data_rate = 2400
2162 13:59:53.611879 CKR = 1
2163 13:59:53.615056 DQ_P2S_RATIO = 8
2164 13:59:53.618441 ===================================
2165 13:59:53.618521 CA_P2S_RATIO = 8
2166 13:59:53.621878 DQ_CA_OPEN = 0
2167 13:59:53.625079 DQ_SEMI_OPEN = 0
2168 13:59:53.628445 CA_SEMI_OPEN = 0
2169 13:59:53.631949 CA_FULL_RATE = 0
2170 13:59:53.635251 DQ_CKDIV4_EN = 0
2171 13:59:53.635330 CA_CKDIV4_EN = 0
2172 13:59:53.638524 CA_PREDIV_EN = 0
2173 13:59:53.641749 PH8_DLY = 17
2174 13:59:53.645140 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2175 13:59:53.648355 DQ_AAMCK_DIV = 4
2176 13:59:53.651973 CA_AAMCK_DIV = 4
2177 13:59:53.652053 CA_ADMCK_DIV = 4
2178 13:59:53.655129 DQ_TRACK_CA_EN = 0
2179 13:59:53.658625 CA_PICK = 1200
2180 13:59:53.662054 CA_MCKIO = 1200
2181 13:59:53.665097 MCKIO_SEMI = 0
2182 13:59:53.668595 PLL_FREQ = 2366
2183 13:59:53.671890 DQ_UI_PI_RATIO = 32
2184 13:59:53.671970 CA_UI_PI_RATIO = 0
2185 13:59:53.675010 ===================================
2186 13:59:53.678636 ===================================
2187 13:59:53.681761 memory_type:LPDDR4
2188 13:59:53.685021 GP_NUM : 10
2189 13:59:53.685103 SRAM_EN : 1
2190 13:59:53.688692 MD32_EN : 0
2191 13:59:53.691729 ===================================
2192 13:59:53.695136 [ANA_INIT] >>>>>>>>>>>>>>
2193 13:59:53.698423 <<<<<< [CONFIGURE PHASE]: ANA_TX
2194 13:59:53.702131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2195 13:59:53.705302 ===================================
2196 13:59:53.705385 data_rate = 2400,PCW = 0X5b00
2197 13:59:53.708471 ===================================
2198 13:59:53.712171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2199 13:59:53.718796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 13:59:53.725124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 13:59:53.728803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2202 13:59:53.731953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2203 13:59:53.735199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2204 13:59:53.738525 [ANA_INIT] flow start
2205 13:59:53.738624 [ANA_INIT] PLL >>>>>>>>
2206 13:59:53.741720 [ANA_INIT] PLL <<<<<<<<
2207 13:59:53.745263 [ANA_INIT] MIDPI >>>>>>>>
2208 13:59:53.745357 [ANA_INIT] MIDPI <<<<<<<<
2209 13:59:53.748427 [ANA_INIT] DLL >>>>>>>>
2210 13:59:53.751725 [ANA_INIT] DLL <<<<<<<<
2211 13:59:53.751824 [ANA_INIT] flow end
2212 13:59:53.758366 ============ LP4 DIFF to SE enter ============
2213 13:59:53.761677 ============ LP4 DIFF to SE exit ============
2214 13:59:53.765202 [ANA_INIT] <<<<<<<<<<<<<
2215 13:59:53.768355 [Flow] Enable top DCM control >>>>>
2216 13:59:53.771566 [Flow] Enable top DCM control <<<<<
2217 13:59:53.771667 Enable DLL master slave shuffle
2218 13:59:53.778447 ==============================================================
2219 13:59:53.781919 Gating Mode config
2220 13:59:53.784932 ==============================================================
2221 13:59:53.788210 Config description:
2222 13:59:53.798354 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2223 13:59:53.804812 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2224 13:59:53.808398 SELPH_MODE 0: By rank 1: By Phase
2225 13:59:53.815154 ==============================================================
2226 13:59:53.818362 GAT_TRACK_EN = 1
2227 13:59:53.821716 RX_GATING_MODE = 2
2228 13:59:53.825121 RX_GATING_TRACK_MODE = 2
2229 13:59:53.828370 SELPH_MODE = 1
2230 13:59:53.828441 PICG_EARLY_EN = 1
2231 13:59:53.831409 VALID_LAT_VALUE = 1
2232 13:59:53.838192 ==============================================================
2233 13:59:53.841507 Enter into Gating configuration >>>>
2234 13:59:53.845149 Exit from Gating configuration <<<<
2235 13:59:53.848245 Enter into DVFS_PRE_config >>>>>
2236 13:59:53.858282 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2237 13:59:53.861664 Exit from DVFS_PRE_config <<<<<
2238 13:59:53.865057 Enter into PICG configuration >>>>
2239 13:59:53.868118 Exit from PICG configuration <<<<
2240 13:59:53.871691 [RX_INPUT] configuration >>>>>
2241 13:59:53.874907 [RX_INPUT] configuration <<<<<
2242 13:59:53.878420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2243 13:59:53.885169 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2244 13:59:53.891505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 13:59:53.898371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 13:59:53.901620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 13:59:53.908424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 13:59:53.911741 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2249 13:59:53.918119 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2250 13:59:53.921671 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2251 13:59:53.924978 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2252 13:59:53.928358 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2253 13:59:53.934917 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2254 13:59:53.938313 ===================================
2255 13:59:53.938384 LPDDR4 DRAM CONFIGURATION
2256 13:59:53.941857 ===================================
2257 13:59:53.945003 EX_ROW_EN[0] = 0x0
2258 13:59:53.948345 EX_ROW_EN[1] = 0x0
2259 13:59:53.948413 LP4Y_EN = 0x0
2260 13:59:53.951733 WORK_FSP = 0x0
2261 13:59:53.951827 WL = 0x4
2262 13:59:53.955134 RL = 0x4
2263 13:59:53.955202 BL = 0x2
2264 13:59:53.958270 RPST = 0x0
2265 13:59:53.958341 RD_PRE = 0x0
2266 13:59:53.961560 WR_PRE = 0x1
2267 13:59:53.961655 WR_PST = 0x0
2268 13:59:53.965200 DBI_WR = 0x0
2269 13:59:53.965339 DBI_RD = 0x0
2270 13:59:53.968768 OTF = 0x1
2271 13:59:53.971884 ===================================
2272 13:59:53.975355 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2273 13:59:53.978639 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2274 13:59:53.984985 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 13:59:53.988683 ===================================
2276 13:59:53.988774 LPDDR4 DRAM CONFIGURATION
2277 13:59:53.991709 ===================================
2278 13:59:53.995422 EX_ROW_EN[0] = 0x10
2279 13:59:53.995516 EX_ROW_EN[1] = 0x0
2280 13:59:53.998525 LP4Y_EN = 0x0
2281 13:59:53.998622 WORK_FSP = 0x0
2282 13:59:54.001872 WL = 0x4
2283 13:59:54.005218 RL = 0x4
2284 13:59:54.005312 BL = 0x2
2285 13:59:54.008722 RPST = 0x0
2286 13:59:54.008815 RD_PRE = 0x0
2287 13:59:54.012239 WR_PRE = 0x1
2288 13:59:54.012307 WR_PST = 0x0
2289 13:59:54.015408 DBI_WR = 0x0
2290 13:59:54.015499 DBI_RD = 0x0
2291 13:59:54.018440 OTF = 0x1
2292 13:59:54.021694 ===================================
2293 13:59:54.025331 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2294 13:59:54.028742 ==
2295 13:59:54.028814 Dram Type= 6, Freq= 0, CH_0, rank 0
2296 13:59:54.035408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2297 13:59:54.035501 ==
2298 13:59:54.038754 [Duty_Offset_Calibration]
2299 13:59:54.038826 B0:2 B1:0 CA:4
2300 13:59:54.038886
2301 13:59:54.041890 [DutyScan_Calibration_Flow] k_type=0
2302 13:59:54.051301
2303 13:59:54.051370 ==CLK 0==
2304 13:59:54.054533 Final CLK duty delay cell = 0
2305 13:59:54.057913 [0] MAX Duty = 5031%(X100), DQS PI = 12
2306 13:59:54.061408 [0] MIN Duty = 4907%(X100), DQS PI = 6
2307 13:59:54.061482 [0] AVG Duty = 4969%(X100)
2308 13:59:54.064861
2309 13:59:54.064928 CH0 CLK Duty spec in!! Max-Min= 124%
2310 13:59:54.071408 [DutyScan_Calibration_Flow] ====Done====
2311 13:59:54.071571
2312 13:59:54.074690 [DutyScan_Calibration_Flow] k_type=1
2313 13:59:54.089746
2314 13:59:54.089816 ==DQS 0 ==
2315 13:59:54.093199 Final DQS duty delay cell = 0
2316 13:59:54.096289 [0] MAX Duty = 5062%(X100), DQS PI = 12
2317 13:59:54.099840 [0] MIN Duty = 4907%(X100), DQS PI = 46
2318 13:59:54.102991 [0] AVG Duty = 4984%(X100)
2319 13:59:54.103060
2320 13:59:54.103117 ==DQS 1 ==
2321 13:59:54.106490 Final DQS duty delay cell = -4
2322 13:59:54.109835 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2323 13:59:54.113048 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2324 13:59:54.116525 [-4] AVG Duty = 4938%(X100)
2325 13:59:54.116618
2326 13:59:54.119691 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2327 13:59:54.119786
2328 13:59:54.123144 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2329 13:59:54.126363 [DutyScan_Calibration_Flow] ====Done====
2330 13:59:54.126456
2331 13:59:54.129378 [DutyScan_Calibration_Flow] k_type=3
2332 13:59:54.146977
2333 13:59:54.147064 ==DQM 0 ==
2334 13:59:54.150507 Final DQM duty delay cell = 0
2335 13:59:54.153932 [0] MAX Duty = 5124%(X100), DQS PI = 28
2336 13:59:54.157247 [0] MIN Duty = 4876%(X100), DQS PI = 0
2337 13:59:54.157316 [0] AVG Duty = 5000%(X100)
2338 13:59:54.160601
2339 13:59:54.160668 ==DQM 1 ==
2340 13:59:54.163636 Final DQM duty delay cell = 4
2341 13:59:54.167218 [4] MAX Duty = 5124%(X100), DQS PI = 50
2342 13:59:54.170439 [4] MIN Duty = 5000%(X100), DQS PI = 42
2343 13:59:54.173974 [4] AVG Duty = 5062%(X100)
2344 13:59:54.174072
2345 13:59:54.177205 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2346 13:59:54.177301
2347 13:59:54.180633 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2348 13:59:54.183815 [DutyScan_Calibration_Flow] ====Done====
2349 13:59:54.183909
2350 13:59:54.186848 [DutyScan_Calibration_Flow] k_type=2
2351 13:59:54.201926
2352 13:59:54.202005 ==DQ 0 ==
2353 13:59:54.205437 Final DQ duty delay cell = -4
2354 13:59:54.208623 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2355 13:59:54.212120 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2356 13:59:54.215510 [-4] AVG Duty = 4969%(X100)
2357 13:59:54.215610
2358 13:59:54.215699 ==DQ 1 ==
2359 13:59:54.218721 Final DQ duty delay cell = -4
2360 13:59:54.222237 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2361 13:59:54.225321 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2362 13:59:54.229082 [-4] AVG Duty = 4922%(X100)
2363 13:59:54.229154
2364 13:59:54.232456 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2365 13:59:54.232558
2366 13:59:54.235547 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2367 13:59:54.239081 [DutyScan_Calibration_Flow] ====Done====
2368 13:59:54.239180 ==
2369 13:59:54.242109 Dram Type= 6, Freq= 0, CH_1, rank 0
2370 13:59:54.245703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 13:59:54.245803 ==
2372 13:59:54.248713 [Duty_Offset_Calibration]
2373 13:59:54.248791 B0:1 B1:-2 CA:0
2374 13:59:54.248880
2375 13:59:54.252169 [DutyScan_Calibration_Flow] k_type=0
2376 13:59:54.262397
2377 13:59:54.262472 ==CLK 0==
2378 13:59:54.265820 Final CLK duty delay cell = 0
2379 13:59:54.269043 [0] MAX Duty = 5031%(X100), DQS PI = 18
2380 13:59:54.272539 [0] MIN Duty = 4844%(X100), DQS PI = 58
2381 13:59:54.272636 [0] AVG Duty = 4937%(X100)
2382 13:59:54.275634
2383 13:59:54.279197 CH1 CLK Duty spec in!! Max-Min= 187%
2384 13:59:54.282371 [DutyScan_Calibration_Flow] ====Done====
2385 13:59:54.282441
2386 13:59:54.285816 [DutyScan_Calibration_Flow] k_type=1
2387 13:59:54.301073
2388 13:59:54.301149 ==DQS 0 ==
2389 13:59:54.304303 Final DQS duty delay cell = -4
2390 13:59:54.307446 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2391 13:59:54.310966 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2392 13:59:54.314199 [-4] AVG Duty = 4953%(X100)
2393 13:59:54.314269
2394 13:59:54.314350 ==DQS 1 ==
2395 13:59:54.317542 Final DQS duty delay cell = 0
2396 13:59:54.321086 [0] MAX Duty = 5093%(X100), DQS PI = 0
2397 13:59:54.324212 [0] MIN Duty = 4844%(X100), DQS PI = 26
2398 13:59:54.327800 [0] AVG Duty = 4968%(X100)
2399 13:59:54.327870
2400 13:59:54.331351 CH1 DQS 0 Duty spec in!! Max-Min= 155%
2401 13:59:54.331448
2402 13:59:54.334307 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2403 13:59:54.338180 [DutyScan_Calibration_Flow] ====Done====
2404 13:59:54.338261
2405 13:59:54.341216 [DutyScan_Calibration_Flow] k_type=3
2406 13:59:54.357960
2407 13:59:54.358067 ==DQM 0 ==
2408 13:59:54.361005 Final DQM duty delay cell = 0
2409 13:59:54.364026 [0] MAX Duty = 5000%(X100), DQS PI = 24
2410 13:59:54.367504 [0] MIN Duty = 4844%(X100), DQS PI = 56
2411 13:59:54.371061 [0] AVG Duty = 4922%(X100)
2412 13:59:54.371143
2413 13:59:54.371226 ==DQM 1 ==
2414 13:59:54.374135 Final DQM duty delay cell = 0
2415 13:59:54.377692 [0] MAX Duty = 5031%(X100), DQS PI = 36
2416 13:59:54.380933 [0] MIN Duty = 4907%(X100), DQS PI = 4
2417 13:59:54.384104 [0] AVG Duty = 4969%(X100)
2418 13:59:54.384186
2419 13:59:54.387624 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2420 13:59:54.387706
2421 13:59:54.390800 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2422 13:59:54.394299 [DutyScan_Calibration_Flow] ====Done====
2423 13:59:54.394380
2424 13:59:54.397586 [DutyScan_Calibration_Flow] k_type=2
2425 13:59:54.414073
2426 13:59:54.414163 ==DQ 0 ==
2427 13:59:54.417297 Final DQ duty delay cell = 0
2428 13:59:54.420982 [0] MAX Duty = 5062%(X100), DQS PI = 12
2429 13:59:54.423883 [0] MIN Duty = 4938%(X100), DQS PI = 52
2430 13:59:54.423962 [0] AVG Duty = 5000%(X100)
2431 13:59:54.427628
2432 13:59:54.427721 ==DQ 1 ==
2433 13:59:54.430665 Final DQ duty delay cell = 0
2434 13:59:54.434013 [0] MAX Duty = 5125%(X100), DQS PI = 36
2435 13:59:54.437428 [0] MIN Duty = 4938%(X100), DQS PI = 26
2436 13:59:54.437513 [0] AVG Duty = 5031%(X100)
2437 13:59:54.437576
2438 13:59:54.440635 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2439 13:59:54.444291
2440 13:59:54.447480 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2441 13:59:54.450673 [DutyScan_Calibration_Flow] ====Done====
2442 13:59:54.453970 nWR fixed to 30
2443 13:59:54.454064 [ModeRegInit_LP4] CH0 RK0
2444 13:59:54.457542 [ModeRegInit_LP4] CH0 RK1
2445 13:59:54.460615 [ModeRegInit_LP4] CH1 RK0
2446 13:59:54.460695 [ModeRegInit_LP4] CH1 RK1
2447 13:59:54.463967 match AC timing 7
2448 13:59:54.467156 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2449 13:59:54.470582 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2450 13:59:54.477241 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2451 13:59:54.480485 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2452 13:59:54.487273 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2453 13:59:54.487378 ==
2454 13:59:54.490809 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 13:59:54.494189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 13:59:54.494285 ==
2457 13:59:54.500789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2458 13:59:54.503942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2459 13:59:54.513987 [CA 0] Center 40 (10~71) winsize 62
2460 13:59:54.517666 [CA 1] Center 39 (9~70) winsize 62
2461 13:59:54.520860 [CA 2] Center 36 (6~66) winsize 61
2462 13:59:54.524199 [CA 3] Center 35 (5~66) winsize 62
2463 13:59:54.527272 [CA 4] Center 34 (4~65) winsize 62
2464 13:59:54.531005 [CA 5] Center 33 (3~63) winsize 61
2465 13:59:54.531087
2466 13:59:54.534212 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2467 13:59:54.534293
2468 13:59:54.537683 [CATrainingPosCal] consider 1 rank data
2469 13:59:54.540924 u2DelayCellTimex100 = 270/100 ps
2470 13:59:54.544276 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2471 13:59:54.550675 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2472 13:59:54.553988 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2473 13:59:54.557432 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2474 13:59:54.560533 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2475 13:59:54.564090 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2476 13:59:54.564173
2477 13:59:54.567233 CA PerBit enable=1, Macro0, CA PI delay=33
2478 13:59:54.567315
2479 13:59:54.570612 [CBTSetCACLKResult] CA Dly = 33
2480 13:59:54.570700 CS Dly: 7 (0~38)
2481 13:59:54.573848 ==
2482 13:59:54.577253 Dram Type= 6, Freq= 0, CH_0, rank 1
2483 13:59:54.580842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 13:59:54.580923 ==
2485 13:59:54.583975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 13:59:54.590663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2487 13:59:54.600434 [CA 0] Center 40 (10~70) winsize 61
2488 13:59:54.603586 [CA 1] Center 39 (9~70) winsize 62
2489 13:59:54.606859 [CA 2] Center 35 (5~66) winsize 62
2490 13:59:54.610273 [CA 3] Center 35 (5~66) winsize 62
2491 13:59:54.613738 [CA 4] Center 34 (3~65) winsize 63
2492 13:59:54.616991 [CA 5] Center 33 (3~64) winsize 62
2493 13:59:54.617072
2494 13:59:54.620354 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 13:59:54.620435
2496 13:59:54.623626 [CATrainingPosCal] consider 2 rank data
2497 13:59:54.626867 u2DelayCellTimex100 = 270/100 ps
2498 13:59:54.630474 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2499 13:59:54.633608 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2500 13:59:54.640359 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2501 13:59:54.643755 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 13:59:54.647281 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2503 13:59:54.650466 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2504 13:59:54.650548
2505 13:59:54.653742 CA PerBit enable=1, Macro0, CA PI delay=33
2506 13:59:54.653824
2507 13:59:54.657018 [CBTSetCACLKResult] CA Dly = 33
2508 13:59:54.657100 CS Dly: 8 (0~40)
2509 13:59:54.657164
2510 13:59:54.660396 ----->DramcWriteLeveling(PI) begin...
2511 13:59:54.663751 ==
2512 13:59:54.667082 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 13:59:54.670394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 13:59:54.670477 ==
2515 13:59:54.673914 Write leveling (Byte 0): 33 => 33
2516 13:59:54.677159 Write leveling (Byte 1): 30 => 30
2517 13:59:54.680501 DramcWriteLeveling(PI) end<-----
2518 13:59:54.680582
2519 13:59:54.680646 ==
2520 13:59:54.683613 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 13:59:54.686957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 13:59:54.687038 ==
2523 13:59:54.690592 [Gating] SW mode calibration
2524 13:59:54.697166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2525 13:59:54.700448 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2526 13:59:54.707123 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2527 13:59:54.710547 0 15 4 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
2528 13:59:54.713949 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 13:59:54.720444 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 13:59:54.724140 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 13:59:54.727393 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 13:59:54.733956 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 13:59:54.737390 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2534 13:59:54.740470 1 0 0 | B1->B0 | 3232 2727 | 1 0 | (1 0) (0 1)
2535 13:59:54.747273 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2536 13:59:54.750622 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 13:59:54.753742 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 13:59:54.760179 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 13:59:54.763635 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 13:59:54.767147 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 13:59:54.773661 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
2542 13:59:54.777111 1 1 0 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (0 0)
2543 13:59:54.780277 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2544 13:59:54.787066 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 13:59:54.790323 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 13:59:54.793331 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 13:59:54.799987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 13:59:54.803579 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 13:59:54.806706 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 13:59:54.813668 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2551 13:59:54.816681 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 13:59:54.820264 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:59:54.823424 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:59:54.830241 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:59:54.833394 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:59:54.836685 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:59:54.843358 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:59:54.846940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:59:54.850007 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:59:54.856664 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:59:54.859949 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:59:54.863541 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:59:54.870250 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:59:54.873372 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:59:54.876824 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 13:59:54.883725 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2567 13:59:54.886980 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2568 13:59:54.890362 Total UI for P1: 0, mck2ui 16
2569 13:59:54.893500 best dqsien dly found for B0: ( 1, 3, 30)
2570 13:59:54.897068 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 13:59:54.900229 Total UI for P1: 0, mck2ui 16
2572 13:59:54.903506 best dqsien dly found for B1: ( 1, 4, 2)
2573 13:59:54.906772 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2574 13:59:54.910082 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2575 13:59:54.910161
2576 13:59:54.913397 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2577 13:59:54.920112 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2578 13:59:54.920218 [Gating] SW calibration Done
2579 13:59:54.920310 ==
2580 13:59:54.923574 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 13:59:54.929857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 13:59:54.929958 ==
2583 13:59:54.930051 RX Vref Scan: 0
2584 13:59:54.930137
2585 13:59:54.933281 RX Vref 0 -> 0, step: 1
2586 13:59:54.933386
2587 13:59:54.936423 RX Delay -40 -> 252, step: 8
2588 13:59:54.939961 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2589 13:59:54.943357 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2590 13:59:54.946515 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2591 13:59:54.953206 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2592 13:59:54.956588 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2593 13:59:54.960045 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2594 13:59:54.963267 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2595 13:59:54.966808 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2596 13:59:54.970137 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2597 13:59:54.976692 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2598 13:59:54.979827 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2599 13:59:54.983537 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2600 13:59:54.986689 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2601 13:59:54.989881 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2602 13:59:54.996534 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2603 13:59:55.000026 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2604 13:59:55.000127 ==
2605 13:59:55.003158 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 13:59:55.006576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 13:59:55.006671 ==
2608 13:59:55.009842 DQS Delay:
2609 13:59:55.009936 DQS0 = 0, DQS1 = 0
2610 13:59:55.010025 DQM Delay:
2611 13:59:55.013295 DQM0 = 112, DQM1 = 102
2612 13:59:55.013391 DQ Delay:
2613 13:59:55.016585 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2614 13:59:55.020106 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2615 13:59:55.023436 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2616 13:59:55.026838 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2617 13:59:55.026934
2618 13:59:55.030162
2619 13:59:55.030260 ==
2620 13:59:55.033553 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 13:59:55.036800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 13:59:55.036905 ==
2623 13:59:55.036995
2624 13:59:55.037081
2625 13:59:55.039984 TX Vref Scan disable
2626 13:59:55.040082 == TX Byte 0 ==
2627 13:59:55.043606 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2628 13:59:55.050108 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2629 13:59:55.050188 == TX Byte 1 ==
2630 13:59:55.053384 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2631 13:59:55.059911 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2632 13:59:55.060012 ==
2633 13:59:55.063472 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 13:59:55.066849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 13:59:55.066954 ==
2636 13:59:55.078932 TX Vref=22, minBit 7, minWin=25, winSum=414
2637 13:59:55.082587 TX Vref=24, minBit 1, minWin=26, winSum=421
2638 13:59:55.085825 TX Vref=26, minBit 7, minWin=25, winSum=426
2639 13:59:55.088837 TX Vref=28, minBit 12, minWin=26, winSum=433
2640 13:59:55.092409 TX Vref=30, minBit 8, minWin=26, winSum=431
2641 13:59:55.098903 TX Vref=32, minBit 1, minWin=26, winSum=428
2642 13:59:55.102110 [TxChooseVref] Worse bit 12, Min win 26, Win sum 433, Final Vref 28
2643 13:59:55.102231
2644 13:59:55.105597 Final TX Range 1 Vref 28
2645 13:59:55.105721
2646 13:59:55.105829 ==
2647 13:59:55.108700 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 13:59:55.112159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 13:59:55.112281 ==
2650 13:59:55.115288
2651 13:59:55.115405
2652 13:59:55.115512 TX Vref Scan disable
2653 13:59:55.119006 == TX Byte 0 ==
2654 13:59:55.122234 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2655 13:59:55.125410 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2656 13:59:55.129004 == TX Byte 1 ==
2657 13:59:55.132144 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2658 13:59:55.138771 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2659 13:59:55.138870
2660 13:59:55.138958 [DATLAT]
2661 13:59:55.139043 Freq=1200, CH0 RK0
2662 13:59:55.139130
2663 13:59:55.142097 DATLAT Default: 0xd
2664 13:59:55.142176 0, 0xFFFF, sum = 0
2665 13:59:55.145392 1, 0xFFFF, sum = 0
2666 13:59:55.145519 2, 0xFFFF, sum = 0
2667 13:59:55.148646 3, 0xFFFF, sum = 0
2668 13:59:55.152171 4, 0xFFFF, sum = 0
2669 13:59:55.152268 5, 0xFFFF, sum = 0
2670 13:59:55.155510 6, 0xFFFF, sum = 0
2671 13:59:55.155606 7, 0xFFFF, sum = 0
2672 13:59:55.159075 8, 0xFFFF, sum = 0
2673 13:59:55.159156 9, 0xFFFF, sum = 0
2674 13:59:55.162074 10, 0xFFFF, sum = 0
2675 13:59:55.162155 11, 0xFFFF, sum = 0
2676 13:59:55.165336 12, 0x0, sum = 1
2677 13:59:55.165451 13, 0x0, sum = 2
2678 13:59:55.168697 14, 0x0, sum = 3
2679 13:59:55.168797 15, 0x0, sum = 4
2680 13:59:55.168886 best_step = 13
2681 13:59:55.168970
2682 13:59:55.172100 ==
2683 13:59:55.175224 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 13:59:55.178935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 13:59:55.179038 ==
2686 13:59:55.179128 RX Vref Scan: 1
2687 13:59:55.179217
2688 13:59:55.182094 Set Vref Range= 32 -> 127
2689 13:59:55.182185
2690 13:59:55.185405 RX Vref 32 -> 127, step: 1
2691 13:59:55.185531
2692 13:59:55.188845 RX Delay -37 -> 252, step: 4
2693 13:59:55.188953
2694 13:59:55.191981 Set Vref, RX VrefLevel [Byte0]: 32
2695 13:59:55.195225 [Byte1]: 32
2696 13:59:55.195321
2697 13:59:55.198850 Set Vref, RX VrefLevel [Byte0]: 33
2698 13:59:55.202088 [Byte1]: 33
2699 13:59:55.205706
2700 13:59:55.205785 Set Vref, RX VrefLevel [Byte0]: 34
2701 13:59:55.208895 [Byte1]: 34
2702 13:59:55.213342
2703 13:59:55.213447 Set Vref, RX VrefLevel [Byte0]: 35
2704 13:59:55.216932 [Byte1]: 35
2705 13:59:55.221317
2706 13:59:55.221416 Set Vref, RX VrefLevel [Byte0]: 36
2707 13:59:55.224923 [Byte1]: 36
2708 13:59:55.229283
2709 13:59:55.229404 Set Vref, RX VrefLevel [Byte0]: 37
2710 13:59:55.232634 [Byte1]: 37
2711 13:59:55.237654
2712 13:59:55.237774 Set Vref, RX VrefLevel [Byte0]: 38
2713 13:59:55.240824 [Byte1]: 38
2714 13:59:55.245359
2715 13:59:55.245465 Set Vref, RX VrefLevel [Byte0]: 39
2716 13:59:55.248923 [Byte1]: 39
2717 13:59:55.253307
2718 13:59:55.253412 Set Vref, RX VrefLevel [Byte0]: 40
2719 13:59:55.256927 [Byte1]: 40
2720 13:59:55.261368
2721 13:59:55.261471 Set Vref, RX VrefLevel [Byte0]: 41
2722 13:59:55.264813 [Byte1]: 41
2723 13:59:55.269284
2724 13:59:55.269382 Set Vref, RX VrefLevel [Byte0]: 42
2725 13:59:55.272828 [Byte1]: 42
2726 13:59:55.277326
2727 13:59:55.277427 Set Vref, RX VrefLevel [Byte0]: 43
2728 13:59:55.280899 [Byte1]: 43
2729 13:59:55.285461
2730 13:59:55.285583 Set Vref, RX VrefLevel [Byte0]: 44
2731 13:59:55.288674 [Byte1]: 44
2732 13:59:55.293339
2733 13:59:55.293444 Set Vref, RX VrefLevel [Byte0]: 45
2734 13:59:55.297044 [Byte1]: 45
2735 13:59:55.301401
2736 13:59:55.301542 Set Vref, RX VrefLevel [Byte0]: 46
2737 13:59:55.304530 [Byte1]: 46
2738 13:59:55.309407
2739 13:59:55.309547 Set Vref, RX VrefLevel [Byte0]: 47
2740 13:59:55.313005 [Byte1]: 47
2741 13:59:55.317436
2742 13:59:55.317533 Set Vref, RX VrefLevel [Byte0]: 48
2743 13:59:55.320997 [Byte1]: 48
2744 13:59:55.325533
2745 13:59:55.325616 Set Vref, RX VrefLevel [Byte0]: 49
2746 13:59:55.328660 [Byte1]: 49
2747 13:59:55.333363
2748 13:59:55.333446 Set Vref, RX VrefLevel [Byte0]: 50
2749 13:59:55.336943 [Byte1]: 50
2750 13:59:55.341492
2751 13:59:55.341576 Set Vref, RX VrefLevel [Byte0]: 51
2752 13:59:55.344691 [Byte1]: 51
2753 13:59:55.349552
2754 13:59:55.349636 Set Vref, RX VrefLevel [Byte0]: 52
2755 13:59:55.352630 [Byte1]: 52
2756 13:59:55.357400
2757 13:59:55.357514 Set Vref, RX VrefLevel [Byte0]: 53
2758 13:59:55.360892 [Byte1]: 53
2759 13:59:55.365465
2760 13:59:55.365608 Set Vref, RX VrefLevel [Byte0]: 54
2761 13:59:55.368838 [Byte1]: 54
2762 13:59:55.373718
2763 13:59:55.373801 Set Vref, RX VrefLevel [Byte0]: 55
2764 13:59:55.376929 [Byte1]: 55
2765 13:59:55.381692
2766 13:59:55.381775 Set Vref, RX VrefLevel [Byte0]: 56
2767 13:59:55.387973 [Byte1]: 56
2768 13:59:55.388057
2769 13:59:55.391428 Set Vref, RX VrefLevel [Byte0]: 57
2770 13:59:55.394562 [Byte1]: 57
2771 13:59:55.394646
2772 13:59:55.398184 Set Vref, RX VrefLevel [Byte0]: 58
2773 13:59:55.401345 [Byte1]: 58
2774 13:59:55.405519
2775 13:59:55.405602 Set Vref, RX VrefLevel [Byte0]: 59
2776 13:59:55.409036 [Byte1]: 59
2777 13:59:55.413737
2778 13:59:55.413819 Set Vref, RX VrefLevel [Byte0]: 60
2779 13:59:55.416990 [Byte1]: 60
2780 13:59:55.421729
2781 13:59:55.421812 Set Vref, RX VrefLevel [Byte0]: 61
2782 13:59:55.424933 [Byte1]: 61
2783 13:59:55.429525
2784 13:59:55.429608 Set Vref, RX VrefLevel [Byte0]: 62
2785 13:59:55.432879 [Byte1]: 62
2786 13:59:55.437353
2787 13:59:55.437435 Set Vref, RX VrefLevel [Byte0]: 63
2788 13:59:55.440699 [Byte1]: 63
2789 13:59:55.445583
2790 13:59:55.445666 Set Vref, RX VrefLevel [Byte0]: 64
2791 13:59:55.448655 [Byte1]: 64
2792 13:59:55.453663
2793 13:59:55.453746 Set Vref, RX VrefLevel [Byte0]: 65
2794 13:59:55.456744 [Byte1]: 65
2795 13:59:55.461765
2796 13:59:55.461849 Set Vref, RX VrefLevel [Byte0]: 66
2797 13:59:55.464773 [Byte1]: 66
2798 13:59:55.469711
2799 13:59:55.469800 Set Vref, RX VrefLevel [Byte0]: 67
2800 13:59:55.472785 [Byte1]: 67
2801 13:59:55.477455
2802 13:59:55.477571 Set Vref, RX VrefLevel [Byte0]: 68
2803 13:59:55.480820 [Byte1]: 68
2804 13:59:55.485449
2805 13:59:55.485621 Set Vref, RX VrefLevel [Byte0]: 69
2806 13:59:55.488796 [Byte1]: 69
2807 13:59:55.493518
2808 13:59:55.493655 Set Vref, RX VrefLevel [Byte0]: 70
2809 13:59:55.497141 [Byte1]: 70
2810 13:59:55.501914
2811 13:59:55.502385 Set Vref, RX VrefLevel [Byte0]: 71
2812 13:59:55.505025 [Byte1]: 71
2813 13:59:55.510300
2814 13:59:55.510892 Set Vref, RX VrefLevel [Byte0]: 72
2815 13:59:55.513409 [Byte1]: 72
2816 13:59:55.517951
2817 13:59:55.518426 Set Vref, RX VrefLevel [Byte0]: 73
2818 13:59:55.521401 [Byte1]: 73
2819 13:59:55.526005
2820 13:59:55.526494 Set Vref, RX VrefLevel [Byte0]: 74
2821 13:59:55.529274 [Byte1]: 74
2822 13:59:55.533975
2823 13:59:55.534488 Final RX Vref Byte 0 = 60 to rank0
2824 13:59:55.537236 Final RX Vref Byte 1 = 48 to rank0
2825 13:59:55.540574 Final RX Vref Byte 0 = 60 to rank1
2826 13:59:55.544009 Final RX Vref Byte 1 = 48 to rank1==
2827 13:59:55.547269 Dram Type= 6, Freq= 0, CH_0, rank 0
2828 13:59:55.550788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 13:59:55.554009 ==
2830 13:59:55.554506 DQS Delay:
2831 13:59:55.554886 DQS0 = 0, DQS1 = 0
2832 13:59:55.557361 DQM Delay:
2833 13:59:55.557877 DQM0 = 111, DQM1 = 99
2834 13:59:55.560744 DQ Delay:
2835 13:59:55.564158 DQ0 =110, DQ1 =112, DQ2 =110, DQ3 =108
2836 13:59:55.567084 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2837 13:59:55.570731 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =92
2838 13:59:55.573872 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =108
2839 13:59:55.574328
2840 13:59:55.574688
2841 13:59:55.580539 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
2842 13:59:55.584048 CH0 RK0: MR19=303, MR18=FCFB
2843 13:59:55.590744 CH0_RK0: MR19=0x303, MR18=0xFCFB, DQSOSC=411, MR23=63, INC=38, DEC=25
2844 13:59:55.591225
2845 13:59:55.594335 ----->DramcWriteLeveling(PI) begin...
2846 13:59:55.594835 ==
2847 13:59:55.597757 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 13:59:55.601053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 13:59:55.601615 ==
2850 13:59:55.604130 Write leveling (Byte 0): 33 => 33
2851 13:59:55.607201 Write leveling (Byte 1): 30 => 30
2852 13:59:55.610942 DramcWriteLeveling(PI) end<-----
2853 13:59:55.611519
2854 13:59:55.611883 ==
2855 13:59:55.614285 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 13:59:55.617388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 13:59:55.620544 ==
2858 13:59:55.621000 [Gating] SW mode calibration
2859 13:59:55.627562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2860 13:59:55.634338 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2861 13:59:55.637625 0 15 0 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
2862 13:59:55.644210 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 13:59:55.647492 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 13:59:55.650875 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 13:59:55.657470 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 13:59:55.661079 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 13:59:55.664435 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2868 13:59:55.671183 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2869 13:59:55.674121 1 0 0 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
2870 13:59:55.677645 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 13:59:55.680757 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 13:59:55.687556 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 13:59:55.691056 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 13:59:55.694418 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 13:59:55.700778 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2876 13:59:55.704438 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2877 13:59:55.707675 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2878 13:59:55.714442 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 13:59:55.717788 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 13:59:55.721239 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 13:59:55.727761 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 13:59:55.731197 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 13:59:55.734402 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 13:59:55.741091 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2885 13:59:55.744578 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2886 13:59:55.747640 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 13:59:55.754303 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 13:59:55.757779 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:59:55.761040 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 13:59:55.764739 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 13:59:55.771168 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 13:59:55.774276 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 13:59:55.777951 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 13:59:55.784372 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 13:59:55.787696 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 13:59:55.791439 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 13:59:55.797980 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 13:59:55.801088 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 13:59:55.804335 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 13:59:55.811285 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2901 13:59:55.814416 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2902 13:59:55.817649 Total UI for P1: 0, mck2ui 16
2903 13:59:55.821105 best dqsien dly found for B0: ( 1, 3, 28)
2904 13:59:55.824479 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 13:59:55.827813 Total UI for P1: 0, mck2ui 16
2906 13:59:55.830985 best dqsien dly found for B1: ( 1, 4, 0)
2907 13:59:55.834572 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2908 13:59:55.837883 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2909 13:59:55.838524
2910 13:59:55.841058 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2911 13:59:55.848015 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2912 13:59:55.848477 [Gating] SW calibration Done
2913 13:59:55.848843 ==
2914 13:59:55.851031 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 13:59:55.857639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 13:59:55.858104 ==
2917 13:59:55.858469 RX Vref Scan: 0
2918 13:59:55.858808
2919 13:59:55.860995 RX Vref 0 -> 0, step: 1
2920 13:59:55.861463
2921 13:59:55.864461 RX Delay -40 -> 252, step: 8
2922 13:59:55.867985 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2923 13:59:55.871042 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2924 13:59:55.874246 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2925 13:59:55.881103 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2926 13:59:55.884418 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2927 13:59:55.887975 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2928 13:59:55.891141 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2929 13:59:55.894515 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2930 13:59:55.897777 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2931 13:59:55.904607 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2932 13:59:55.907856 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2933 13:59:55.910991 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2934 13:59:55.914234 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2935 13:59:55.917669 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2936 13:59:55.924761 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2937 13:59:55.927737 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2938 13:59:55.928158 ==
2939 13:59:55.931072 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 13:59:55.934274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 13:59:55.934653 ==
2942 13:59:55.937784 DQS Delay:
2943 13:59:55.938226 DQS0 = 0, DQS1 = 0
2944 13:59:55.938706 DQM Delay:
2945 13:59:55.941238 DQM0 = 113, DQM1 = 101
2946 13:59:55.941715 DQ Delay:
2947 13:59:55.944497 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2948 13:59:55.947882 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2949 13:59:55.951142 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2950 13:59:55.957828 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2951 13:59:55.958394
2952 13:59:55.958789
2953 13:59:55.959149 ==
2954 13:59:55.961222 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 13:59:55.964464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 13:59:55.965089 ==
2957 13:59:55.965655
2958 13:59:55.966048
2959 13:59:55.967599 TX Vref Scan disable
2960 13:59:55.968219 == TX Byte 0 ==
2961 13:59:55.974593 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2962 13:59:55.977798 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2963 13:59:55.978298 == TX Byte 1 ==
2964 13:59:55.984473 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2965 13:59:55.987643 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2966 13:59:55.988250 ==
2967 13:59:55.990907 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 13:59:55.994339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 13:59:55.994772 ==
2970 13:59:56.007059 TX Vref=22, minBit 1, minWin=26, winSum=421
2971 13:59:56.010357 TX Vref=24, minBit 1, minWin=26, winSum=424
2972 13:59:56.013879 TX Vref=26, minBit 0, minWin=26, winSum=432
2973 13:59:56.017141 TX Vref=28, minBit 2, minWin=26, winSum=436
2974 13:59:56.020710 TX Vref=30, minBit 1, minWin=26, winSum=436
2975 13:59:56.023688 TX Vref=32, minBit 8, minWin=26, winSum=434
2976 13:59:56.030480 [TxChooseVref] Worse bit 2, Min win 26, Win sum 436, Final Vref 28
2977 13:59:56.031014
2978 13:59:56.033699 Final TX Range 1 Vref 28
2979 13:59:56.034140
2980 13:59:56.034511 ==
2981 13:59:56.036819 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 13:59:56.040470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 13:59:56.041004 ==
2984 13:59:56.041394
2985 13:59:56.044030
2986 13:59:56.044555 TX Vref Scan disable
2987 13:59:56.047004 == TX Byte 0 ==
2988 13:59:56.050503 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2989 13:59:56.053601 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2990 13:59:56.057087 == TX Byte 1 ==
2991 13:59:56.060664 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2992 13:59:56.063608 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2993 13:59:56.064037
2994 13:59:56.066977 [DATLAT]
2995 13:59:56.067413 Freq=1200, CH0 RK1
2996 13:59:56.067748
2997 13:59:56.070250 DATLAT Default: 0xd
2998 13:59:56.070663 0, 0xFFFF, sum = 0
2999 13:59:56.073878 1, 0xFFFF, sum = 0
3000 13:59:56.074460 2, 0xFFFF, sum = 0
3001 13:59:56.077043 3, 0xFFFF, sum = 0
3002 13:59:56.077660 4, 0xFFFF, sum = 0
3003 13:59:56.080339 5, 0xFFFF, sum = 0
3004 13:59:56.080828 6, 0xFFFF, sum = 0
3005 13:59:56.083703 7, 0xFFFF, sum = 0
3006 13:59:56.084278 8, 0xFFFF, sum = 0
3007 13:59:56.086987 9, 0xFFFF, sum = 0
3008 13:59:56.087426 10, 0xFFFF, sum = 0
3009 13:59:56.090502 11, 0xFFFF, sum = 0
3010 13:59:56.090965 12, 0x0, sum = 1
3011 13:59:56.093717 13, 0x0, sum = 2
3012 13:59:56.094149 14, 0x0, sum = 3
3013 13:59:56.097032 15, 0x0, sum = 4
3014 13:59:56.097459 best_step = 13
3015 13:59:56.097879
3016 13:59:56.098195 ==
3017 13:59:56.100589 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 13:59:56.106997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 13:59:56.107460 ==
3020 13:59:56.107808 RX Vref Scan: 0
3021 13:59:56.108277
3022 13:59:56.110413 RX Vref 0 -> 0, step: 1
3023 13:59:56.110866
3024 13:59:56.114086 RX Delay -37 -> 252, step: 4
3025 13:59:56.117126 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3026 13:59:56.120796 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3027 13:59:56.127671 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3028 13:59:56.130800 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3029 13:59:56.133973 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3030 13:59:56.137086 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3031 13:59:56.140608 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3032 13:59:56.147132 iDelay=195, Bit 7, Center 116 (43 ~ 190) 148
3033 13:59:56.150450 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3034 13:59:56.153824 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3035 13:59:56.157172 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3036 13:59:56.160723 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3037 13:59:56.167184 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3038 13:59:56.170239 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3039 13:59:56.173740 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3040 13:59:56.176870 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3041 13:59:56.177287 ==
3042 13:59:56.180024 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 13:59:56.186832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 13:59:56.187251 ==
3045 13:59:56.187580 DQS Delay:
3046 13:59:56.187951 DQS0 = 0, DQS1 = 0
3047 13:59:56.190343 DQM Delay:
3048 13:59:56.190757 DQM0 = 110, DQM1 = 100
3049 13:59:56.193576 DQ Delay:
3050 13:59:56.196982 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3051 13:59:56.200297 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =116
3052 13:59:56.203499 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =94
3053 13:59:56.206993 DQ12 =108, DQ13 =108, DQ14 =112, DQ15 =108
3054 13:59:56.207408
3055 13:59:56.207735
3056 13:59:56.213347 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3057 13:59:56.216907 CH0 RK1: MR19=403, MR18=10F8
3058 13:59:56.223287 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3059 13:59:56.226709 [RxdqsGatingPostProcess] freq 1200
3060 13:59:56.233368 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3061 13:59:56.236632 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 13:59:56.239683 best DQS1 dly(2T, 0.5T) = (0, 12)
3063 13:59:56.242990 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 13:59:56.246618 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3065 13:59:56.247036 best DQS0 dly(2T, 0.5T) = (0, 11)
3066 13:59:56.249573 best DQS1 dly(2T, 0.5T) = (0, 12)
3067 13:59:56.253197 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3068 13:59:56.256413 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3069 13:59:56.259632 Pre-setting of DQS Precalculation
3070 13:59:56.266567 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3071 13:59:56.266986 ==
3072 13:59:56.269768 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 13:59:56.273283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 13:59:56.273736 ==
3075 13:59:56.279669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 13:59:56.283246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3077 13:59:56.293076 [CA 0] Center 37 (7~67) winsize 61
3078 13:59:56.296267 [CA 1] Center 37 (7~68) winsize 62
3079 13:59:56.299409 [CA 2] Center 34 (4~64) winsize 61
3080 13:59:56.302923 [CA 3] Center 34 (4~64) winsize 61
3081 13:59:56.306319 [CA 4] Center 34 (4~65) winsize 62
3082 13:59:56.309596 [CA 5] Center 33 (3~63) winsize 61
3083 13:59:56.310013
3084 13:59:56.313015 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3085 13:59:56.313433
3086 13:59:56.316326 [CATrainingPosCal] consider 1 rank data
3087 13:59:56.319528 u2DelayCellTimex100 = 270/100 ps
3088 13:59:56.322690 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3089 13:59:56.326484 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 13:59:56.333111 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 13:59:56.336326 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 13:59:56.339323 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3093 13:59:56.342978 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3094 13:59:56.343492
3095 13:59:56.346270 CA PerBit enable=1, Macro0, CA PI delay=33
3096 13:59:56.346888
3097 13:59:56.349277 [CBTSetCACLKResult] CA Dly = 33
3098 13:59:56.349855 CS Dly: 6 (0~37)
3099 13:59:56.350407 ==
3100 13:59:56.352779 Dram Type= 6, Freq= 0, CH_1, rank 1
3101 13:59:56.359384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 13:59:56.359842 ==
3103 13:59:56.363001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3104 13:59:56.369439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3105 13:59:56.378190 [CA 0] Center 37 (7~67) winsize 61
3106 13:59:56.381858 [CA 1] Center 37 (7~68) winsize 62
3107 13:59:56.385142 [CA 2] Center 34 (4~65) winsize 62
3108 13:59:56.388511 [CA 3] Center 33 (3~64) winsize 62
3109 13:59:56.391609 [CA 4] Center 34 (4~65) winsize 62
3110 13:59:56.395127 [CA 5] Center 33 (3~63) winsize 61
3111 13:59:56.395545
3112 13:59:56.398248 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3113 13:59:56.398667
3114 13:59:56.401958 [CATrainingPosCal] consider 2 rank data
3115 13:59:56.405027 u2DelayCellTimex100 = 270/100 ps
3116 13:59:56.408318 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3117 13:59:56.414666 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3118 13:59:56.418302 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 13:59:56.421577 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 13:59:56.424992 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3121 13:59:56.428367 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3122 13:59:56.428803
3123 13:59:56.431575 CA PerBit enable=1, Macro0, CA PI delay=33
3124 13:59:56.431990
3125 13:59:56.434746 [CBTSetCACLKResult] CA Dly = 33
3126 13:59:56.435162 CS Dly: 7 (0~40)
3127 13:59:56.435493
3128 13:59:56.438258 ----->DramcWriteLeveling(PI) begin...
3129 13:59:56.441706 ==
3130 13:59:56.444841 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 13:59:56.448541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 13:59:56.448960 ==
3133 13:59:56.451707 Write leveling (Byte 0): 25 => 25
3134 13:59:56.454897 Write leveling (Byte 1): 29 => 29
3135 13:59:56.458339 DramcWriteLeveling(PI) end<-----
3136 13:59:56.458754
3137 13:59:56.459078 ==
3138 13:59:56.461799 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 13:59:56.465152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 13:59:56.465638 ==
3141 13:59:56.468477 [Gating] SW mode calibration
3142 13:59:56.474976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3143 13:59:56.478126 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3144 13:59:56.484848 0 15 0 | B1->B0 | 2d2d 2828 | 1 1 | (0 0) (0 0)
3145 13:59:56.488448 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 13:59:56.491508 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 13:59:56.498380 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 13:59:56.501576 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 13:59:56.504742 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 13:59:56.511655 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 13:59:56.514896 0 15 28 | B1->B0 | 2727 2828 | 1 1 | (1 1) (1 0)
3152 13:59:56.518545 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3153 13:59:56.524875 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 13:59:56.528374 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 13:59:56.531474 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 13:59:56.538228 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 13:59:56.541410 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 13:59:56.544945 1 0 24 | B1->B0 | 2424 2525 | 1 0 | (0 0) (0 0)
3159 13:59:56.551695 1 0 28 | B1->B0 | 3c3c 3535 | 0 0 | (0 0) (1 1)
3160 13:59:56.554784 1 1 0 | B1->B0 | 4545 4343 | 0 1 | (0 0) (0 0)
3161 13:59:56.558091 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 13:59:56.564836 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 13:59:56.568217 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 13:59:56.571615 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 13:59:56.578172 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 13:59:56.581448 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3167 13:59:56.584547 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3168 13:59:56.591238 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3169 13:59:56.594831 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 13:59:56.598022 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 13:59:56.604661 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 13:59:56.607795 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 13:59:56.611383 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 13:59:56.614639 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 13:59:56.621146 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 13:59:56.624770 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 13:59:56.627977 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 13:59:56.634546 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 13:59:56.638138 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 13:59:56.641139 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 13:59:56.648216 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 13:59:56.651374 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3183 13:59:56.654433 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3184 13:59:56.661266 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 13:59:56.661711 Total UI for P1: 0, mck2ui 16
3186 13:59:56.668003 best dqsien dly found for B0: ( 1, 3, 28)
3187 13:59:56.668446 Total UI for P1: 0, mck2ui 16
3188 13:59:56.674403 best dqsien dly found for B1: ( 1, 3, 30)
3189 13:59:56.677661 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3190 13:59:56.681374 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3191 13:59:56.681844
3192 13:59:56.684341 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3193 13:59:56.687848 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3194 13:59:56.691247 [Gating] SW calibration Done
3195 13:59:56.691661 ==
3196 13:59:56.694575 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 13:59:56.697895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 13:59:56.698338 ==
3199 13:59:56.701058 RX Vref Scan: 0
3200 13:59:56.701502
3201 13:59:56.701858 RX Vref 0 -> 0, step: 1
3202 13:59:56.702173
3203 13:59:56.704625 RX Delay -40 -> 252, step: 8
3204 13:59:56.708016 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3205 13:59:56.714676 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3206 13:59:56.717904 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3207 13:59:56.721153 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3208 13:59:56.724636 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3209 13:59:56.727752 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3210 13:59:56.731303 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3211 13:59:56.738070 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3212 13:59:56.741449 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3213 13:59:56.744628 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3214 13:59:56.748300 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3215 13:59:56.751857 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3216 13:59:56.758212 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3217 13:59:56.761570 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3218 13:59:56.764704 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3219 13:59:56.767924 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3220 13:59:56.768344 ==
3221 13:59:56.771675 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 13:59:56.777867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 13:59:56.778294 ==
3224 13:59:56.778629 DQS Delay:
3225 13:59:56.779098 DQS0 = 0, DQS1 = 0
3226 13:59:56.781432 DQM Delay:
3227 13:59:56.781892 DQM0 = 114, DQM1 = 107
3228 13:59:56.784890 DQ Delay:
3229 13:59:56.788152 DQ0 =119, DQ1 =111, DQ2 =99, DQ3 =115
3230 13:59:56.791181 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3231 13:59:56.794621 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =107
3232 13:59:56.798024 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3233 13:59:56.798603
3234 13:59:56.799067
3235 13:59:56.799485 ==
3236 13:59:56.801397 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 13:59:56.804786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 13:59:56.805205 ==
3239 13:59:56.805578
3240 13:59:56.807983
3241 13:59:56.808403 TX Vref Scan disable
3242 13:59:56.811605 == TX Byte 0 ==
3243 13:59:56.814766 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3244 13:59:56.818326 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3245 13:59:56.821653 == TX Byte 1 ==
3246 13:59:56.824957 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3247 13:59:56.828121 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3248 13:59:56.828629 ==
3249 13:59:56.831484 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 13:59:56.837758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 13:59:56.838299 ==
3252 13:59:56.848643 TX Vref=22, minBit 8, minWin=24, winSum=411
3253 13:59:56.852021 TX Vref=24, minBit 2, minWin=25, winSum=417
3254 13:59:56.855330 TX Vref=26, minBit 8, minWin=25, winSum=421
3255 13:59:56.858565 TX Vref=28, minBit 9, minWin=25, winSum=424
3256 13:59:56.861784 TX Vref=30, minBit 3, minWin=25, winSum=425
3257 13:59:56.865213 TX Vref=32, minBit 9, minWin=25, winSum=423
3258 13:59:56.872173 [TxChooseVref] Worse bit 3, Min win 25, Win sum 425, Final Vref 30
3259 13:59:56.872724
3260 13:59:56.875368 Final TX Range 1 Vref 30
3261 13:59:56.875830
3262 13:59:56.876206 ==
3263 13:59:56.878457 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 13:59:56.881793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 13:59:56.882258 ==
3266 13:59:56.882625
3267 13:59:56.885350
3268 13:59:56.885861 TX Vref Scan disable
3269 13:59:56.888487 == TX Byte 0 ==
3270 13:59:56.892138 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3271 13:59:56.895659 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3272 13:59:56.898606 == TX Byte 1 ==
3273 13:59:56.902055 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3274 13:59:56.905182 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3275 13:59:56.905684
3276 13:59:56.908727 [DATLAT]
3277 13:59:56.909188 Freq=1200, CH1 RK0
3278 13:59:56.909589
3279 13:59:56.911881 DATLAT Default: 0xd
3280 13:59:56.912342 0, 0xFFFF, sum = 0
3281 13:59:56.915684 1, 0xFFFF, sum = 0
3282 13:59:56.916257 2, 0xFFFF, sum = 0
3283 13:59:56.918390 3, 0xFFFF, sum = 0
3284 13:59:56.918859 4, 0xFFFF, sum = 0
3285 13:59:56.922090 5, 0xFFFF, sum = 0
3286 13:59:56.922647 6, 0xFFFF, sum = 0
3287 13:59:56.925385 7, 0xFFFF, sum = 0
3288 13:59:56.925992 8, 0xFFFF, sum = 0
3289 13:59:56.929024 9, 0xFFFF, sum = 0
3290 13:59:56.932323 10, 0xFFFF, sum = 0
3291 13:59:56.932931 11, 0xFFFF, sum = 0
3292 13:59:56.935253 12, 0x0, sum = 1
3293 13:59:56.935717 13, 0x0, sum = 2
3294 13:59:56.936103 14, 0x0, sum = 3
3295 13:59:56.938766 15, 0x0, sum = 4
3296 13:59:56.939229 best_step = 13
3297 13:59:56.939587
3298 13:59:56.939991 ==
3299 13:59:56.942035 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 13:59:56.948491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 13:59:56.948951 ==
3302 13:59:56.949347 RX Vref Scan: 1
3303 13:59:56.949799
3304 13:59:56.951658 Set Vref Range= 32 -> 127
3305 13:59:56.952110
3306 13:59:56.955095 RX Vref 32 -> 127, step: 1
3307 13:59:56.955550
3308 13:59:56.958524 RX Delay -21 -> 252, step: 4
3309 13:59:56.958937
3310 13:59:56.961747 Set Vref, RX VrefLevel [Byte0]: 32
3311 13:59:56.965457 [Byte1]: 32
3312 13:59:56.966056
3313 13:59:56.968546 Set Vref, RX VrefLevel [Byte0]: 33
3314 13:59:56.971972 [Byte1]: 33
3315 13:59:56.972518
3316 13:59:56.974878 Set Vref, RX VrefLevel [Byte0]: 34
3317 13:59:56.978177 [Byte1]: 34
3318 13:59:56.982609
3319 13:59:56.983069 Set Vref, RX VrefLevel [Byte0]: 35
3320 13:59:56.985774 [Byte1]: 35
3321 13:59:56.990858
3322 13:59:56.991374 Set Vref, RX VrefLevel [Byte0]: 36
3323 13:59:56.993722 [Byte1]: 36
3324 13:59:56.998303
3325 13:59:56.998712 Set Vref, RX VrefLevel [Byte0]: 37
3326 13:59:57.005155 [Byte1]: 37
3327 13:59:57.005707
3328 13:59:57.008258 Set Vref, RX VrefLevel [Byte0]: 38
3329 13:59:57.011712 [Byte1]: 38
3330 13:59:57.012172
3331 13:59:57.015062 Set Vref, RX VrefLevel [Byte0]: 39
3332 13:59:57.018309 [Byte1]: 39
3333 13:59:57.022287
3334 13:59:57.022825 Set Vref, RX VrefLevel [Byte0]: 40
3335 13:59:57.025852 [Byte1]: 40
3336 13:59:57.030411
3337 13:59:57.030965 Set Vref, RX VrefLevel [Byte0]: 41
3338 13:59:57.033631 [Byte1]: 41
3339 13:59:57.038334
3340 13:59:57.038879 Set Vref, RX VrefLevel [Byte0]: 42
3341 13:59:57.041666 [Byte1]: 42
3342 13:59:57.046250
3343 13:59:57.046795 Set Vref, RX VrefLevel [Byte0]: 43
3344 13:59:57.049465 [Byte1]: 43
3345 13:59:57.054179
3346 13:59:57.054720 Set Vref, RX VrefLevel [Byte0]: 44
3347 13:59:57.057538 [Byte1]: 44
3348 13:59:57.062339
3349 13:59:57.062883 Set Vref, RX VrefLevel [Byte0]: 45
3350 13:59:57.065303 [Byte1]: 45
3351 13:59:57.069677
3352 13:59:57.070215 Set Vref, RX VrefLevel [Byte0]: 46
3353 13:59:57.073294 [Byte1]: 46
3354 13:59:57.077578
3355 13:59:57.078034 Set Vref, RX VrefLevel [Byte0]: 47
3356 13:59:57.081205 [Byte1]: 47
3357 13:59:57.085787
3358 13:59:57.086331 Set Vref, RX VrefLevel [Byte0]: 48
3359 13:59:57.088864 [Byte1]: 48
3360 13:59:57.093656
3361 13:59:57.094193 Set Vref, RX VrefLevel [Byte0]: 49
3362 13:59:57.096717 [Byte1]: 49
3363 13:59:57.101726
3364 13:59:57.102273 Set Vref, RX VrefLevel [Byte0]: 50
3365 13:59:57.104686 [Byte1]: 50
3366 13:59:57.109850
3367 13:59:57.110399 Set Vref, RX VrefLevel [Byte0]: 51
3368 13:59:57.112982 [Byte1]: 51
3369 13:59:57.117664
3370 13:59:57.118225 Set Vref, RX VrefLevel [Byte0]: 52
3371 13:59:57.120479 [Byte1]: 52
3372 13:59:57.125698
3373 13:59:57.126268 Set Vref, RX VrefLevel [Byte0]: 53
3374 13:59:57.128604 [Byte1]: 53
3375 13:59:57.133591
3376 13:59:57.134126 Set Vref, RX VrefLevel [Byte0]: 54
3377 13:59:57.136651 [Byte1]: 54
3378 13:59:57.141222
3379 13:59:57.141810 Set Vref, RX VrefLevel [Byte0]: 55
3380 13:59:57.144867 [Byte1]: 55
3381 13:59:57.149251
3382 13:59:57.149893 Set Vref, RX VrefLevel [Byte0]: 56
3383 13:59:57.152527 [Byte1]: 56
3384 13:59:57.157331
3385 13:59:57.157904 Set Vref, RX VrefLevel [Byte0]: 57
3386 13:59:57.160618 [Byte1]: 57
3387 13:59:57.165297
3388 13:59:57.165887 Set Vref, RX VrefLevel [Byte0]: 58
3389 13:59:57.168456 [Byte1]: 58
3390 13:59:57.172996
3391 13:59:57.173573 Set Vref, RX VrefLevel [Byte0]: 59
3392 13:59:57.176376 [Byte1]: 59
3393 13:59:57.180638
3394 13:59:57.181095 Set Vref, RX VrefLevel [Byte0]: 60
3395 13:59:57.183946 [Byte1]: 60
3396 13:59:57.188933
3397 13:59:57.189617 Set Vref, RX VrefLevel [Byte0]: 61
3398 13:59:57.192193 [Byte1]: 61
3399 13:59:57.196496
3400 13:59:57.196952 Set Vref, RX VrefLevel [Byte0]: 62
3401 13:59:57.200003 [Byte1]: 62
3402 13:59:57.204681
3403 13:59:57.205225 Set Vref, RX VrefLevel [Byte0]: 63
3404 13:59:57.207706 [Byte1]: 63
3405 13:59:57.212394
3406 13:59:57.212850 Set Vref, RX VrefLevel [Byte0]: 64
3407 13:59:57.215663 [Byte1]: 64
3408 13:59:57.220237
3409 13:59:57.220693 Set Vref, RX VrefLevel [Byte0]: 65
3410 13:59:57.223918 [Byte1]: 65
3411 13:59:57.228234
3412 13:59:57.228796 Set Vref, RX VrefLevel [Byte0]: 66
3413 13:59:57.231996 [Byte1]: 66
3414 13:59:57.236075
3415 13:59:57.236666 Set Vref, RX VrefLevel [Byte0]: 67
3416 13:59:57.239410 [Byte1]: 67
3417 13:59:57.244318
3418 13:59:57.244775 Final RX Vref Byte 0 = 60 to rank0
3419 13:59:57.247726 Final RX Vref Byte 1 = 54 to rank0
3420 13:59:57.250923 Final RX Vref Byte 0 = 60 to rank1
3421 13:59:57.254443 Final RX Vref Byte 1 = 54 to rank1==
3422 13:59:57.257685 Dram Type= 6, Freq= 0, CH_1, rank 0
3423 13:59:57.264250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 13:59:57.264791 ==
3425 13:59:57.265157 DQS Delay:
3426 13:59:57.265547 DQS0 = 0, DQS1 = 0
3427 13:59:57.267735 DQM Delay:
3428 13:59:57.268285 DQM0 = 114, DQM1 = 107
3429 13:59:57.271071 DQ Delay:
3430 13:59:57.274445 DQ0 =118, DQ1 =108, DQ2 =108, DQ3 =112
3431 13:59:57.277553 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3432 13:59:57.280619 DQ8 =92, DQ9 =96, DQ10 =106, DQ11 =102
3433 13:59:57.284114 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3434 13:59:57.284572
3435 13:59:57.284931
3436 13:59:57.291394 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3437 13:59:57.294485 CH1 RK0: MR19=303, MR18=F2F9
3438 13:59:57.301073 CH1_RK0: MR19=0x303, MR18=0xF2F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3439 13:59:57.301677
3440 13:59:57.304543 ----->DramcWriteLeveling(PI) begin...
3441 13:59:57.305117 ==
3442 13:59:57.308089 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 13:59:57.311095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 13:59:57.311559 ==
3445 13:59:57.314711 Write leveling (Byte 0): 24 => 24
3446 13:59:57.318105 Write leveling (Byte 1): 25 => 25
3447 13:59:57.321058 DramcWriteLeveling(PI) end<-----
3448 13:59:57.321656
3449 13:59:57.322058 ==
3450 13:59:57.324540 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 13:59:57.328123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 13:59:57.331386 ==
3453 13:59:57.331936 [Gating] SW mode calibration
3454 13:59:57.337853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3455 13:59:57.344874 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3456 13:59:57.347679 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 13:59:57.354488 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 13:59:57.357930 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 13:59:57.361166 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 13:59:57.367946 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 13:59:57.370620 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3462 13:59:57.374328 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (1 0) (0 0)
3463 13:59:57.380830 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
3464 13:59:57.384446 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 13:59:57.387934 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 13:59:57.394209 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 13:59:57.397254 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 13:59:57.401014 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 13:59:57.407742 1 0 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3470 13:59:57.411318 1 0 24 | B1->B0 | 2928 4646 | 1 0 | (0 0) (0 0)
3471 13:59:57.414411 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 13:59:57.418076 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 13:59:57.424374 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 13:59:57.427964 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 13:59:57.434083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 13:59:57.437141 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 13:59:57.440597 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 13:59:57.444081 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3479 13:59:57.450450 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3480 13:59:57.453546 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 13:59:57.457181 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 13:59:57.463874 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 13:59:57.466957 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 13:59:57.470203 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:59:57.476650 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:59:57.479971 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:59:57.483282 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:59:57.490132 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:59:57.493531 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 13:59:57.496964 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 13:59:57.503192 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 13:59:57.507228 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 13:59:57.510173 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 13:59:57.517142 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3495 13:59:57.520388 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 13:59:57.523970 Total UI for P1: 0, mck2ui 16
3497 13:59:57.526858 best dqsien dly found for B0: ( 1, 3, 24)
3498 13:59:57.530244 Total UI for P1: 0, mck2ui 16
3499 13:59:57.534064 best dqsien dly found for B1: ( 1, 3, 24)
3500 13:59:57.536825 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3501 13:59:57.540470 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3502 13:59:57.540973
3503 13:59:57.543734 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3504 13:59:57.547206 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3505 13:59:57.550180 [Gating] SW calibration Done
3506 13:59:57.550689 ==
3507 13:59:57.553440 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 13:59:57.556877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 13:59:57.560257 ==
3510 13:59:57.560674 RX Vref Scan: 0
3511 13:59:57.561006
3512 13:59:57.563544 RX Vref 0 -> 0, step: 1
3513 13:59:57.563959
3514 13:59:57.566819 RX Delay -40 -> 252, step: 8
3515 13:59:57.570049 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3516 13:59:57.573838 iDelay=200, Bit 1, Center 107 (40 ~ 175) 136
3517 13:59:57.576783 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3518 13:59:57.580024 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3519 13:59:57.583454 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3520 13:59:57.589966 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3521 13:59:57.593637 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3522 13:59:57.596651 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3523 13:59:57.600070 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3524 13:59:57.603684 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3525 13:59:57.609682 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3526 13:59:57.613400 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3527 13:59:57.616518 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3528 13:59:57.619887 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3529 13:59:57.626714 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3530 13:59:57.630111 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3531 13:59:57.630616 ==
3532 13:59:57.633343 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 13:59:57.636511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 13:59:57.637018 ==
3535 13:59:57.637357 DQS Delay:
3536 13:59:57.639740 DQS0 = 0, DQS1 = 0
3537 13:59:57.640159 DQM Delay:
3538 13:59:57.643250 DQM0 = 111, DQM1 = 109
3539 13:59:57.643758 DQ Delay:
3540 13:59:57.646881 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =111
3541 13:59:57.649603 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =111
3542 13:59:57.653375 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3543 13:59:57.656688 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3544 13:59:57.657138
3545 13:59:57.659528
3546 13:59:57.659946 ==
3547 13:59:57.663176 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 13:59:57.666192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 13:59:57.666615 ==
3550 13:59:57.666946
3551 13:59:57.667253
3552 13:59:57.669697 TX Vref Scan disable
3553 13:59:57.670156 == TX Byte 0 ==
3554 13:59:57.676044 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3555 13:59:57.679498 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3556 13:59:57.679931 == TX Byte 1 ==
3557 13:59:57.686163 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3558 13:59:57.689364 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3559 13:59:57.689818 ==
3560 13:59:57.692766 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 13:59:57.696183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 13:59:57.696691 ==
3563 13:59:57.708767 TX Vref=22, minBit 1, minWin=25, winSum=419
3564 13:59:57.712183 TX Vref=24, minBit 9, minWin=25, winSum=423
3565 13:59:57.715203 TX Vref=26, minBit 0, minWin=26, winSum=427
3566 13:59:57.718688 TX Vref=28, minBit 9, minWin=26, winSum=432
3567 13:59:57.721698 TX Vref=30, minBit 11, minWin=26, winSum=431
3568 13:59:57.728288 TX Vref=32, minBit 0, minWin=26, winSum=429
3569 13:59:57.732064 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3570 13:59:57.732616
3571 13:59:57.734879 Final TX Range 1 Vref 28
3572 13:59:57.735342
3573 13:59:57.735704 ==
3574 13:59:57.738170 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 13:59:57.741257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 13:59:57.744855 ==
3577 13:59:57.745297
3578 13:59:57.745662
3579 13:59:57.745968 TX Vref Scan disable
3580 13:59:57.748305 == TX Byte 0 ==
3581 13:59:57.751776 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3582 13:59:57.755150 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3583 13:59:57.758234 == TX Byte 1 ==
3584 13:59:57.761542 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3585 13:59:57.768220 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3586 13:59:57.768736
3587 13:59:57.769071 [DATLAT]
3588 13:59:57.769373 Freq=1200, CH1 RK1
3589 13:59:57.769731
3590 13:59:57.771325 DATLAT Default: 0xd
3591 13:59:57.771735 0, 0xFFFF, sum = 0
3592 13:59:57.774741 1, 0xFFFF, sum = 0
3593 13:59:57.778032 2, 0xFFFF, sum = 0
3594 13:59:57.778545 3, 0xFFFF, sum = 0
3595 13:59:57.781425 4, 0xFFFF, sum = 0
3596 13:59:57.781877 5, 0xFFFF, sum = 0
3597 13:59:57.784517 6, 0xFFFF, sum = 0
3598 13:59:57.784934 7, 0xFFFF, sum = 0
3599 13:59:57.788306 8, 0xFFFF, sum = 0
3600 13:59:57.788853 9, 0xFFFF, sum = 0
3601 13:59:57.791402 10, 0xFFFF, sum = 0
3602 13:59:57.791916 11, 0xFFFF, sum = 0
3603 13:59:57.794593 12, 0x0, sum = 1
3604 13:59:57.795133 13, 0x0, sum = 2
3605 13:59:57.797789 14, 0x0, sum = 3
3606 13:59:57.798210 15, 0x0, sum = 4
3607 13:59:57.801109 best_step = 13
3608 13:59:57.801679
3609 13:59:57.802016 ==
3610 13:59:57.804968 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 13:59:57.808161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 13:59:57.808666 ==
3613 13:59:57.808999 RX Vref Scan: 0
3614 13:59:57.809308
3615 13:59:57.811284 RX Vref 0 -> 0, step: 1
3616 13:59:57.811696
3617 13:59:57.814694 RX Delay -21 -> 252, step: 4
3618 13:59:57.821404 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3619 13:59:57.824753 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3620 13:59:57.827625 iDelay=195, Bit 2, Center 104 (35 ~ 174) 140
3621 13:59:57.831071 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3622 13:59:57.834405 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3623 13:59:57.838163 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3624 13:59:57.844713 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3625 13:59:57.847802 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3626 13:59:57.851363 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3627 13:59:57.854621 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3628 13:59:57.857585 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3629 13:59:57.864241 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3630 13:59:57.867634 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3631 13:59:57.870819 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3632 13:59:57.874306 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3633 13:59:57.880983 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3634 13:59:57.881542 ==
3635 13:59:57.883903 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 13:59:57.887777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 13:59:57.888285 ==
3638 13:59:57.888616 DQS Delay:
3639 13:59:57.890661 DQS0 = 0, DQS1 = 0
3640 13:59:57.891074 DQM Delay:
3641 13:59:57.893905 DQM0 = 111, DQM1 = 110
3642 13:59:57.894319 DQ Delay:
3643 13:59:57.897554 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =108
3644 13:59:57.900760 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =110
3645 13:59:57.904155 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3646 13:59:57.907506 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3647 13:59:57.908016
3648 13:59:57.908339
3649 13:59:57.917523 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3650 13:59:57.920595 CH1 RK1: MR19=304, MR18=FC0C
3651 13:59:57.924232 CH1_RK1: MR19=0x304, MR18=0xFC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3652 13:59:57.927137 [RxdqsGatingPostProcess] freq 1200
3653 13:59:57.933661 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3654 13:59:57.937245 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 13:59:57.940591 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 13:59:57.944067 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 13:59:57.947620 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 13:59:57.950661 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 13:59:57.954053 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 13:59:57.957161 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 13:59:57.960808 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 13:59:57.963873 Pre-setting of DQS Precalculation
3663 13:59:57.966775 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3664 13:59:57.973573 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3665 13:59:57.980461 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3666 13:59:57.983547
3667 13:59:57.984072
3668 13:59:57.984542 [Calibration Summary] 2400 Mbps
3669 13:59:57.986710 CH 0, Rank 0
3670 13:59:57.987176 SW Impedance : PASS
3671 13:59:57.990064 DUTY Scan : NO K
3672 13:59:57.993294 ZQ Calibration : PASS
3673 13:59:57.993760 Jitter Meter : NO K
3674 13:59:57.996826 CBT Training : PASS
3675 13:59:58.000246 Write leveling : PASS
3676 13:59:58.000771 RX DQS gating : PASS
3677 13:59:58.003666 RX DQ/DQS(RDDQC) : PASS
3678 13:59:58.006702 TX DQ/DQS : PASS
3679 13:59:58.007136 RX DATLAT : PASS
3680 13:59:58.010379 RX DQ/DQS(Engine): PASS
3681 13:59:58.013577 TX OE : NO K
3682 13:59:58.014014 All Pass.
3683 13:59:58.014449
3684 13:59:58.014863 CH 0, Rank 1
3685 13:59:58.016771 SW Impedance : PASS
3686 13:59:58.020128 DUTY Scan : NO K
3687 13:59:58.020575 ZQ Calibration : PASS
3688 13:59:58.023267 Jitter Meter : NO K
3689 13:59:58.026954 CBT Training : PASS
3690 13:59:58.027478 Write leveling : PASS
3691 13:59:58.030417 RX DQS gating : PASS
3692 13:59:58.030942 RX DQ/DQS(RDDQC) : PASS
3693 13:59:58.033414 TX DQ/DQS : PASS
3694 13:59:58.036773 RX DATLAT : PASS
3695 13:59:58.037303 RX DQ/DQS(Engine): PASS
3696 13:59:58.039801 TX OE : NO K
3697 13:59:58.040287 All Pass.
3698 13:59:58.040728
3699 13:59:58.043658 CH 1, Rank 0
3700 13:59:58.044356 SW Impedance : PASS
3701 13:59:58.046819 DUTY Scan : NO K
3702 13:59:58.049818 ZQ Calibration : PASS
3703 13:59:58.050333 Jitter Meter : NO K
3704 13:59:58.053697 CBT Training : PASS
3705 13:59:58.056473 Write leveling : PASS
3706 13:59:58.056907 RX DQS gating : PASS
3707 13:59:58.059975 RX DQ/DQS(RDDQC) : PASS
3708 13:59:58.063369 TX DQ/DQS : PASS
3709 13:59:58.063805 RX DATLAT : PASS
3710 13:59:58.066502 RX DQ/DQS(Engine): PASS
3711 13:59:58.070068 TX OE : NO K
3712 13:59:58.070588 All Pass.
3713 13:59:58.071037
3714 13:59:58.071452 CH 1, Rank 1
3715 13:59:58.072911 SW Impedance : PASS
3716 13:59:58.076627 DUTY Scan : NO K
3717 13:59:58.077161 ZQ Calibration : PASS
3718 13:59:58.080020 Jitter Meter : NO K
3719 13:59:58.083170 CBT Training : PASS
3720 13:59:58.083604 Write leveling : PASS
3721 13:59:58.086280 RX DQS gating : PASS
3722 13:59:58.089764 RX DQ/DQS(RDDQC) : PASS
3723 13:59:58.090177 TX DQ/DQS : PASS
3724 13:59:58.093206 RX DATLAT : PASS
3725 13:59:58.093766 RX DQ/DQS(Engine): PASS
3726 13:59:58.096140 TX OE : NO K
3727 13:59:58.096559 All Pass.
3728 13:59:58.096888
3729 13:59:58.099392 DramC Write-DBI off
3730 13:59:58.102787 PER_BANK_REFRESH: Hybrid Mode
3731 13:59:58.103203 TX_TRACKING: ON
3732 13:59:58.112916 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3733 13:59:58.116157 [FAST_K] Save calibration result to emmc
3734 13:59:58.119391 dramc_set_vcore_voltage set vcore to 650000
3735 13:59:58.122973 Read voltage for 600, 5
3736 13:59:58.123386 Vio18 = 0
3737 13:59:58.123715 Vcore = 650000
3738 13:59:58.126144 Vdram = 0
3739 13:59:58.126554 Vddq = 0
3740 13:59:58.126936 Vmddr = 0
3741 13:59:58.132816 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3742 13:59:58.135905 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3743 13:59:58.139161 MEM_TYPE=3, freq_sel=19
3744 13:59:58.142844 sv_algorithm_assistance_LP4_1600
3745 13:59:58.145930 ============ PULL DRAM RESETB DOWN ============
3746 13:59:58.153067 ========== PULL DRAM RESETB DOWN end =========
3747 13:59:58.156299 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 13:59:58.159436 ===================================
3749 13:59:58.162431 LPDDR4 DRAM CONFIGURATION
3750 13:59:58.165966 ===================================
3751 13:59:58.166380 EX_ROW_EN[0] = 0x0
3752 13:59:58.169026 EX_ROW_EN[1] = 0x0
3753 13:59:58.169430 LP4Y_EN = 0x0
3754 13:59:58.172923 WORK_FSP = 0x0
3755 13:59:58.173437 WL = 0x2
3756 13:59:58.176007 RL = 0x2
3757 13:59:58.176518 BL = 0x2
3758 13:59:58.178988 RPST = 0x0
3759 13:59:58.179403 RD_PRE = 0x0
3760 13:59:58.182600 WR_PRE = 0x1
3761 13:59:58.185611 WR_PST = 0x0
3762 13:59:58.186098 DBI_WR = 0x0
3763 13:59:58.188884 DBI_RD = 0x0
3764 13:59:58.189295 OTF = 0x1
3765 13:59:58.192413 ===================================
3766 13:59:58.195867 ===================================
3767 13:59:58.196402 ANA top config
3768 13:59:58.198950 ===================================
3769 13:59:58.202014 DLL_ASYNC_EN = 0
3770 13:59:58.205632 ALL_SLAVE_EN = 1
3771 13:59:58.208875 NEW_RANK_MODE = 1
3772 13:59:58.212353 DLL_IDLE_MODE = 1
3773 13:59:58.212889 LP45_APHY_COMB_EN = 1
3774 13:59:58.215605 TX_ODT_DIS = 1
3775 13:59:58.218616 NEW_8X_MODE = 1
3776 13:59:58.221944 ===================================
3777 13:59:58.225957 ===================================
3778 13:59:58.229078 data_rate = 1200
3779 13:59:58.232448 CKR = 1
3780 13:59:58.232963 DQ_P2S_RATIO = 8
3781 13:59:58.235523 ===================================
3782 13:59:58.238713 CA_P2S_RATIO = 8
3783 13:59:58.241937 DQ_CA_OPEN = 0
3784 13:59:58.245539 DQ_SEMI_OPEN = 0
3785 13:59:58.248775 CA_SEMI_OPEN = 0
3786 13:59:58.252424 CA_FULL_RATE = 0
3787 13:59:58.252948 DQ_CKDIV4_EN = 1
3788 13:59:58.255541 CA_CKDIV4_EN = 1
3789 13:59:58.258623 CA_PREDIV_EN = 0
3790 13:59:58.261795 PH8_DLY = 0
3791 13:59:58.264999 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3792 13:59:58.268831 DQ_AAMCK_DIV = 4
3793 13:59:58.271784 CA_AAMCK_DIV = 4
3794 13:59:58.272221 CA_ADMCK_DIV = 4
3795 13:59:58.275381 DQ_TRACK_CA_EN = 0
3796 13:59:58.278255 CA_PICK = 600
3797 13:59:58.281881 CA_MCKIO = 600
3798 13:59:58.285150 MCKIO_SEMI = 0
3799 13:59:58.288467 PLL_FREQ = 2288
3800 13:59:58.291743 DQ_UI_PI_RATIO = 32
3801 13:59:58.292245 CA_UI_PI_RATIO = 0
3802 13:59:58.294781 ===================================
3803 13:59:58.298091 ===================================
3804 13:59:58.301637 memory_type:LPDDR4
3805 13:59:58.304890 GP_NUM : 10
3806 13:59:58.305392 SRAM_EN : 1
3807 13:59:58.308070 MD32_EN : 0
3808 13:59:58.311508 ===================================
3809 13:59:58.314639 [ANA_INIT] >>>>>>>>>>>>>>
3810 13:59:58.317884 <<<<<< [CONFIGURE PHASE]: ANA_TX
3811 13:59:58.321243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3812 13:59:58.324627 ===================================
3813 13:59:58.325157 data_rate = 1200,PCW = 0X5800
3814 13:59:58.327972 ===================================
3815 13:59:58.331260 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3816 13:59:58.337924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 13:59:58.344299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 13:59:58.347632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3819 13:59:58.351022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3820 13:59:58.354402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3821 13:59:58.357540 [ANA_INIT] flow start
3822 13:59:58.360794 [ANA_INIT] PLL >>>>>>>>
3823 13:59:58.361225 [ANA_INIT] PLL <<<<<<<<
3824 13:59:58.364175 [ANA_INIT] MIDPI >>>>>>>>
3825 13:59:58.367939 [ANA_INIT] MIDPI <<<<<<<<
3826 13:59:58.368467 [ANA_INIT] DLL >>>>>>>>
3827 13:59:58.370786 [ANA_INIT] flow end
3828 13:59:58.374271 ============ LP4 DIFF to SE enter ============
3829 13:59:58.377701 ============ LP4 DIFF to SE exit ============
3830 13:59:58.380774 [ANA_INIT] <<<<<<<<<<<<<
3831 13:59:58.384086 [Flow] Enable top DCM control >>>>>
3832 13:59:58.387514 [Flow] Enable top DCM control <<<<<
3833 13:59:58.390777 Enable DLL master slave shuffle
3834 13:59:58.397507 ==============================================================
3835 13:59:58.398031 Gating Mode config
3836 13:59:58.403747 ==============================================================
3837 13:59:58.404177 Config description:
3838 13:59:58.413940 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3839 13:59:58.420386 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3840 13:59:58.427035 SELPH_MODE 0: By rank 1: By Phase
3841 13:59:58.430780 ==============================================================
3842 13:59:58.433623 GAT_TRACK_EN = 1
3843 13:59:58.437340 RX_GATING_MODE = 2
3844 13:59:58.440518 RX_GATING_TRACK_MODE = 2
3845 13:59:58.443515 SELPH_MODE = 1
3846 13:59:58.447443 PICG_EARLY_EN = 1
3847 13:59:58.450378 VALID_LAT_VALUE = 1
3848 13:59:58.457016 ==============================================================
3849 13:59:58.460619 Enter into Gating configuration >>>>
3850 13:59:58.463414 Exit from Gating configuration <<<<
3851 13:59:58.466944 Enter into DVFS_PRE_config >>>>>
3852 13:59:58.477312 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3853 13:59:58.480449 Exit from DVFS_PRE_config <<<<<
3854 13:59:58.483590 Enter into PICG configuration >>>>
3855 13:59:58.487046 Exit from PICG configuration <<<<
3856 13:59:58.489841 [RX_INPUT] configuration >>>>>
3857 13:59:58.490272 [RX_INPUT] configuration <<<<<
3858 13:59:58.496628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3859 13:59:58.503544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3860 13:59:58.506831 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 13:59:58.513168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 13:59:58.519956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 13:59:58.526306 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 13:59:58.529378 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3865 13:59:58.533064 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3866 13:59:58.539724 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3867 13:59:58.542869 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3868 13:59:58.546128 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3869 13:59:58.552825 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 13:59:58.555973 ===================================
3871 13:59:58.556386 LPDDR4 DRAM CONFIGURATION
3872 13:59:58.559483 ===================================
3873 13:59:58.562717 EX_ROW_EN[0] = 0x0
3874 13:59:58.565953 EX_ROW_EN[1] = 0x0
3875 13:59:58.566405 LP4Y_EN = 0x0
3876 13:59:58.569406 WORK_FSP = 0x0
3877 13:59:58.569871 WL = 0x2
3878 13:59:58.572653 RL = 0x2
3879 13:59:58.573071 BL = 0x2
3880 13:59:58.575782 RPST = 0x0
3881 13:59:58.576196 RD_PRE = 0x0
3882 13:59:58.579160 WR_PRE = 0x1
3883 13:59:58.579611 WR_PST = 0x0
3884 13:59:58.582503 DBI_WR = 0x0
3885 13:59:58.582928 DBI_RD = 0x0
3886 13:59:58.585558 OTF = 0x1
3887 13:59:58.589027 ===================================
3888 13:59:58.592563 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3889 13:59:58.595415 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3890 13:59:58.602288 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3891 13:59:58.605449 ===================================
3892 13:59:58.605915 LPDDR4 DRAM CONFIGURATION
3893 13:59:58.608650 ===================================
3894 13:59:58.612107 EX_ROW_EN[0] = 0x10
3895 13:59:58.615331 EX_ROW_EN[1] = 0x0
3896 13:59:58.615854 LP4Y_EN = 0x0
3897 13:59:58.618777 WORK_FSP = 0x0
3898 13:59:58.619209 WL = 0x2
3899 13:59:58.621964 RL = 0x2
3900 13:59:58.622395 BL = 0x2
3901 13:59:58.625222 RPST = 0x0
3902 13:59:58.625807 RD_PRE = 0x0
3903 13:59:58.628513 WR_PRE = 0x1
3904 13:59:58.628948 WR_PST = 0x0
3905 13:59:58.631788 DBI_WR = 0x0
3906 13:59:58.632311 DBI_RD = 0x0
3907 13:59:58.635094 OTF = 0x1
3908 13:59:58.638610 ===================================
3909 13:59:58.645055 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3910 13:59:58.648494 nWR fixed to 30
3911 13:59:58.651555 [ModeRegInit_LP4] CH0 RK0
3912 13:59:58.651988 [ModeRegInit_LP4] CH0 RK1
3913 13:59:58.654976 [ModeRegInit_LP4] CH1 RK0
3914 13:59:58.658021 [ModeRegInit_LP4] CH1 RK1
3915 13:59:58.658450 match AC timing 17
3916 13:59:58.664929 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3917 13:59:58.668328 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3918 13:59:58.671436 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3919 13:59:58.678010 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3920 13:59:58.681290 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3921 13:59:58.681751 ==
3922 13:59:58.684989 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 13:59:58.688215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3924 13:59:58.688653 ==
3925 13:59:58.694420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3926 13:59:58.701264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3927 13:59:58.704530 [CA 0] Center 37 (7~67) winsize 61
3928 13:59:58.707675 [CA 1] Center 36 (6~67) winsize 62
3929 13:59:58.711045 [CA 2] Center 35 (5~65) winsize 61
3930 13:59:58.714677 [CA 3] Center 35 (5~65) winsize 61
3931 13:59:58.718067 [CA 4] Center 34 (4~65) winsize 62
3932 13:59:58.721211 [CA 5] Center 34 (4~64) winsize 61
3933 13:59:58.721784
3934 13:59:58.724419 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3935 13:59:58.724831
3936 13:59:58.728238 [CATrainingPosCal] consider 1 rank data
3937 13:59:58.731265 u2DelayCellTimex100 = 270/100 ps
3938 13:59:58.734307 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3939 13:59:58.737754 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3940 13:59:58.741146 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3941 13:59:58.744187 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3942 13:59:58.747725 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3943 13:59:58.751029 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3944 13:59:58.754393
3945 13:59:58.757646 CA PerBit enable=1, Macro0, CA PI delay=34
3946 13:59:58.758098
3947 13:59:58.760980 [CBTSetCACLKResult] CA Dly = 34
3948 13:59:58.761436 CS Dly: 5 (0~36)
3949 13:59:58.761839 ==
3950 13:59:58.764530 Dram Type= 6, Freq= 0, CH_0, rank 1
3951 13:59:58.767845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 13:59:58.768267 ==
3953 13:59:58.774561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 13:59:58.780763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3955 13:59:58.784249 [CA 0] Center 37 (7~67) winsize 61
3956 13:59:58.787626 [CA 1] Center 37 (7~67) winsize 61
3957 13:59:58.791079 [CA 2] Center 35 (5~65) winsize 61
3958 13:59:58.794315 [CA 3] Center 34 (4~65) winsize 62
3959 13:59:58.797743 [CA 4] Center 34 (4~64) winsize 61
3960 13:59:58.800918 [CA 5] Center 33 (3~64) winsize 62
3961 13:59:58.801327
3962 13:59:58.804250 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3963 13:59:58.804739
3964 13:59:58.807319 [CATrainingPosCal] consider 2 rank data
3965 13:59:58.810882 u2DelayCellTimex100 = 270/100 ps
3966 13:59:58.814182 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3967 13:59:58.817564 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3968 13:59:58.820716 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3969 13:59:58.824002 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3970 13:59:58.830796 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3971 13:59:58.834000 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3972 13:59:58.834503
3973 13:59:58.837465 CA PerBit enable=1, Macro0, CA PI delay=34
3974 13:59:58.837927
3975 13:59:58.840660 [CBTSetCACLKResult] CA Dly = 34
3976 13:59:58.841072 CS Dly: 6 (0~38)
3977 13:59:58.841399
3978 13:59:58.843878 ----->DramcWriteLeveling(PI) begin...
3979 13:59:58.844390 ==
3980 13:59:58.847334 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 13:59:58.853909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 13:59:58.854375 ==
3983 13:59:58.857563 Write leveling (Byte 0): 32 => 32
3984 13:59:58.858053 Write leveling (Byte 1): 32 => 32
3985 13:59:58.860419 DramcWriteLeveling(PI) end<-----
3986 13:59:58.860829
3987 13:59:58.864102 ==
3988 13:59:58.864522 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 13:59:58.870841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 13:59:58.871349 ==
3991 13:59:58.873817 [Gating] SW mode calibration
3992 13:59:58.880423 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3993 13:59:58.883724 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3994 13:59:58.890302 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 13:59:58.893725 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 13:59:58.897089 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 13:59:58.903603 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
3998 13:59:58.907495 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (1 1) (1 1)
3999 13:59:58.910311 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 13:59:58.916877 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 13:59:58.919985 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 13:59:58.923487 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 13:59:58.930195 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 13:59:58.933343 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 13:59:58.936907 0 10 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
4006 13:59:58.943263 0 10 16 | B1->B0 | 2f2f 3a3a | 0 1 | (0 0) (0 0)
4007 13:59:58.946642 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 13:59:58.950271 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 13:59:58.956648 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 13:59:58.959987 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 13:59:58.963163 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 13:59:58.970052 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 13:59:58.973306 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4014 13:59:58.976271 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4015 13:59:58.979954 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 13:59:58.986320 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 13:59:58.989583 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 13:59:58.992917 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:59:58.999735 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:59:59.002813 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:59:59.006337 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:59:59.012802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:59:59.016069 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:59:59.019531 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:59:59.026175 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:59:59.029425 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:59:59.032752 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 13:59:59.039239 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 13:59:59.042335 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4030 13:59:59.045917 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4031 13:59:59.052441 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 13:59:59.055960 Total UI for P1: 0, mck2ui 16
4033 13:59:59.059199 best dqsien dly found for B0: ( 0, 13, 14)
4034 13:59:59.062375 Total UI for P1: 0, mck2ui 16
4035 13:59:59.065662 best dqsien dly found for B1: ( 0, 13, 18)
4036 13:59:59.069257 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4037 13:59:59.072462 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4038 13:59:59.072874
4039 13:59:59.075978 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4040 13:59:59.078938 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4041 13:59:59.082453 [Gating] SW calibration Done
4042 13:59:59.082866 ==
4043 13:59:59.085718 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 13:59:59.089211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 13:59:59.089667 ==
4046 13:59:59.092454 RX Vref Scan: 0
4047 13:59:59.092863
4048 13:59:59.095583 RX Vref 0 -> 0, step: 1
4049 13:59:59.095997
4050 13:59:59.096322 RX Delay -230 -> 252, step: 16
4051 13:59:59.102230 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4052 13:59:59.105380 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4053 13:59:59.109124 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4054 13:59:59.111932 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4055 13:59:59.118982 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4056 13:59:59.122068 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4057 13:59:59.125519 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4058 13:59:59.128591 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4059 13:59:59.131914 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4060 13:59:59.138743 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4061 13:59:59.142063 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4062 13:59:59.145665 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4063 13:59:59.149010 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4064 13:59:59.155537 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4065 13:59:59.158835 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4066 13:59:59.162015 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4067 13:59:59.162426 ==
4068 13:59:59.165533 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 13:59:59.168721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 13:59:59.171917 ==
4071 13:59:59.172326 DQS Delay:
4072 13:59:59.172652 DQS0 = 0, DQS1 = 0
4073 13:59:59.175468 DQM Delay:
4074 13:59:59.175985 DQM0 = 38, DQM1 = 29
4075 13:59:59.178619 DQ Delay:
4076 13:59:59.182096 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4077 13:59:59.182628 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4078 13:59:59.185287 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4079 13:59:59.191753 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4080 13:59:59.192164
4081 13:59:59.192488
4082 13:59:59.192785 ==
4083 13:59:59.194928 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 13:59:59.198200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 13:59:59.198641 ==
4086 13:59:59.198974
4087 13:59:59.199282
4088 13:59:59.201751 TX Vref Scan disable
4089 13:59:59.202165 == TX Byte 0 ==
4090 13:59:59.208093 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4091 13:59:59.211229 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4092 13:59:59.211647 == TX Byte 1 ==
4093 13:59:59.218383 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4094 13:59:59.221398 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4095 13:59:59.221961 ==
4096 13:59:59.224689 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 13:59:59.227834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 13:59:59.228268 ==
4099 13:59:59.228596
4100 13:59:59.231212
4101 13:59:59.231712 TX Vref Scan disable
4102 13:59:59.234691 == TX Byte 0 ==
4103 13:59:59.237977 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4104 13:59:59.244535 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4105 13:59:59.245191 == TX Byte 1 ==
4106 13:59:59.247899 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4107 13:59:59.254447 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4108 13:59:59.255079
4109 13:59:59.255522 [DATLAT]
4110 13:59:59.255842 Freq=600, CH0 RK0
4111 13:59:59.256145
4112 13:59:59.257912 DATLAT Default: 0x9
4113 13:59:59.258412 0, 0xFFFF, sum = 0
4114 13:59:59.261107 1, 0xFFFF, sum = 0
4115 13:59:59.264534 2, 0xFFFF, sum = 0
4116 13:59:59.265120 3, 0xFFFF, sum = 0
4117 13:59:59.267635 4, 0xFFFF, sum = 0
4118 13:59:59.268198 5, 0xFFFF, sum = 0
4119 13:59:59.271479 6, 0xFFFF, sum = 0
4120 13:59:59.271921 7, 0xFFFF, sum = 0
4121 13:59:59.274152 8, 0x0, sum = 1
4122 13:59:59.274725 9, 0x0, sum = 2
4123 13:59:59.275251 10, 0x0, sum = 3
4124 13:59:59.277689 11, 0x0, sum = 4
4125 13:59:59.278262 best_step = 9
4126 13:59:59.278684
4127 13:59:59.280784 ==
4128 13:59:59.281350 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 13:59:59.287411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 13:59:59.287896 ==
4131 13:59:59.288226 RX Vref Scan: 1
4132 13:59:59.288533
4133 13:59:59.290949 RX Vref 0 -> 0, step: 1
4134 13:59:59.291440
4135 13:59:59.293961 RX Delay -195 -> 252, step: 8
4136 13:59:59.294377
4137 13:59:59.297374 Set Vref, RX VrefLevel [Byte0]: 60
4138 13:59:59.300670 [Byte1]: 48
4139 13:59:59.301196
4140 13:59:59.304306 Final RX Vref Byte 0 = 60 to rank0
4141 13:59:59.307454 Final RX Vref Byte 1 = 48 to rank0
4142 13:59:59.310804 Final RX Vref Byte 0 = 60 to rank1
4143 13:59:59.314387 Final RX Vref Byte 1 = 48 to rank1==
4144 13:59:59.317656 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 13:59:59.320829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 13:59:59.321334 ==
4147 13:59:59.323943 DQS Delay:
4148 13:59:59.324358 DQS0 = 0, DQS1 = 0
4149 13:59:59.327293 DQM Delay:
4150 13:59:59.327711 DQM0 = 35, DQM1 = 29
4151 13:59:59.328046 DQ Delay:
4152 13:59:59.330801 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4153 13:59:59.334016 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4154 13:59:59.337255 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4155 13:59:59.340881 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4156 13:59:59.341304
4157 13:59:59.341688
4158 13:59:59.350567 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4159 13:59:59.353949 CH0 RK0: MR19=808, MR18=3A39
4160 13:59:59.360653 CH0_RK0: MR19=0x808, MR18=0x3A39, DQSOSC=398, MR23=63, INC=165, DEC=110
4161 13:59:59.361075
4162 13:59:59.364025 ----->DramcWriteLeveling(PI) begin...
4163 13:59:59.364449 ==
4164 13:59:59.367362 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 13:59:59.370760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 13:59:59.371184 ==
4167 13:59:59.373977 Write leveling (Byte 0): 33 => 33
4168 13:59:59.377461 Write leveling (Byte 1): 30 => 30
4169 13:59:59.380205 DramcWriteLeveling(PI) end<-----
4170 13:59:59.380678
4171 13:59:59.381051 ==
4172 13:59:59.383660 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 13:59:59.387124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 13:59:59.387544 ==
4175 13:59:59.390445 [Gating] SW mode calibration
4176 13:59:59.396814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4177 13:59:59.403835 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4178 13:59:59.407069 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 13:59:59.410046 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 13:59:59.416465 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 13:59:59.420104 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
4182 13:59:59.423065 0 9 16 | B1->B0 | 2d2d 2424 | 1 0 | (0 0) (0 0)
4183 13:59:59.429806 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 13:59:59.433158 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 13:59:59.436506 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 13:59:59.443042 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 13:59:59.446425 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 13:59:59.449547 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 13:59:59.456393 0 10 12 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
4190 13:59:59.459499 0 10 16 | B1->B0 | 3535 4545 | 0 0 | (1 1) (1 1)
4191 13:59:59.463337 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 13:59:59.469432 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 13:59:59.473296 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 13:59:59.476306 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 13:59:59.482899 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 13:59:59.486041 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 13:59:59.489541 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4198 13:59:59.495914 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4199 13:59:59.499606 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 13:59:59.502497 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 13:59:59.509361 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 13:59:59.512703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:59:59.515832 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:59:59.522683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:59:59.525885 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:59:59.529068 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:59:59.535607 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:59:59.539224 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:59:59.541972 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 13:59:59.548743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 13:59:59.552119 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 13:59:59.555343 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 13:59:59.561937 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 13:59:59.565347 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4215 13:59:59.568594 Total UI for P1: 0, mck2ui 16
4216 13:59:59.572015 best dqsien dly found for B0: ( 0, 13, 14)
4217 13:59:59.575309 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 13:59:59.578577 Total UI for P1: 0, mck2ui 16
4219 13:59:59.581698 best dqsien dly found for B1: ( 0, 13, 16)
4220 13:59:59.585362 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4221 13:59:59.588496 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4222 13:59:59.588990
4223 13:59:59.595260 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4224 13:59:59.598484 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4225 13:59:59.601810 [Gating] SW calibration Done
4226 13:59:59.602301 ==
4227 13:59:59.605177 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 13:59:59.608487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 13:59:59.609002 ==
4230 13:59:59.609339 RX Vref Scan: 0
4231 13:59:59.609716
4232 13:59:59.611662 RX Vref 0 -> 0, step: 1
4233 13:59:59.612080
4234 13:59:59.614939 RX Delay -230 -> 252, step: 16
4235 13:59:59.618355 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4236 13:59:59.621516 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4237 13:59:59.628167 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4238 13:59:59.631563 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4239 13:59:59.635133 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4240 13:59:59.638398 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4241 13:59:59.645147 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4242 13:59:59.648407 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4243 13:59:59.651424 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4244 13:59:59.655038 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4245 13:59:59.658009 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4246 13:59:59.664947 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4247 13:59:59.668330 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4248 13:59:59.671474 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4249 13:59:59.674477 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4250 13:59:59.681181 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4251 13:59:59.681698 ==
4252 13:59:59.684576 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 13:59:59.687778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 13:59:59.688198 ==
4255 13:59:59.688528 DQS Delay:
4256 13:59:59.691174 DQS0 = 0, DQS1 = 0
4257 13:59:59.691721 DQM Delay:
4258 13:59:59.694507 DQM0 = 34, DQM1 = 27
4259 13:59:59.695066 DQ Delay:
4260 13:59:59.697787 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =25
4261 13:59:59.701120 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4262 13:59:59.704234 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4263 13:59:59.707700 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4264 13:59:59.708299
4265 13:59:59.708820
4266 13:59:59.709148 ==
4267 13:59:59.711024 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 13:59:59.714382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 13:59:59.717747 ==
4270 13:59:59.718325
4271 13:59:59.718879
4272 13:59:59.719354 TX Vref Scan disable
4273 13:59:59.721008 == TX Byte 0 ==
4274 13:59:59.724194 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4275 13:59:59.727607 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4276 13:59:59.730876 == TX Byte 1 ==
4277 13:59:59.734417 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4278 13:59:59.737616 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4279 13:59:59.740648 ==
4280 13:59:59.744275 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 13:59:59.747580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 13:59:59.748178 ==
4283 13:59:59.748698
4284 13:59:59.749194
4285 13:59:59.750628 TX Vref Scan disable
4286 13:59:59.751085 == TX Byte 0 ==
4287 13:59:59.757428 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4288 13:59:59.760725 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4289 13:59:59.761318 == TX Byte 1 ==
4290 13:59:59.767537 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4291 13:59:59.770640 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4292 13:59:59.771064
4293 13:59:59.771393 [DATLAT]
4294 13:59:59.774111 Freq=600, CH0 RK1
4295 13:59:59.774708
4296 13:59:59.775233 DATLAT Default: 0x9
4297 13:59:59.777512 0, 0xFFFF, sum = 0
4298 13:59:59.777947 1, 0xFFFF, sum = 0
4299 13:59:59.780495 2, 0xFFFF, sum = 0
4300 13:59:59.784157 3, 0xFFFF, sum = 0
4301 13:59:59.784737 4, 0xFFFF, sum = 0
4302 13:59:59.787378 5, 0xFFFF, sum = 0
4303 13:59:59.787976 6, 0xFFFF, sum = 0
4304 13:59:59.790821 7, 0xFFFF, sum = 0
4305 13:59:59.791413 8, 0x0, sum = 1
4306 13:59:59.791816 9, 0x0, sum = 2
4307 13:59:59.793877 10, 0x0, sum = 3
4308 13:59:59.794380 11, 0x0, sum = 4
4309 13:59:59.796996 best_step = 9
4310 13:59:59.797225
4311 13:59:59.797399 ==
4312 13:59:59.800251 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 13:59:59.803857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 13:59:59.804106 ==
4315 13:59:59.807060 RX Vref Scan: 0
4316 13:59:59.807281
4317 13:59:59.807424 RX Vref 0 -> 0, step: 1
4318 13:59:59.807558
4319 13:59:59.810312 RX Delay -195 -> 252, step: 8
4320 13:59:59.817445 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4321 13:59:59.821141 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4322 13:59:59.824132 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4323 13:59:59.827464 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4324 13:59:59.834151 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4325 13:59:59.837707 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4326 13:59:59.840822 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4327 13:59:59.844138 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4328 13:59:59.847644 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4329 13:59:59.854254 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4330 13:59:59.857409 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4331 13:59:59.860768 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4332 13:59:59.864299 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4333 13:59:59.870813 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4334 13:59:59.874381 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4335 13:59:59.877712 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4336 13:59:59.878263 ==
4337 13:59:59.880931 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 13:59:59.887354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 13:59:59.887812 ==
4340 13:59:59.888142 DQS Delay:
4341 13:59:59.888447 DQS0 = 0, DQS1 = 0
4342 13:59:59.890837 DQM Delay:
4343 13:59:59.891250 DQM0 = 33, DQM1 = 28
4344 13:59:59.894225 DQ Delay:
4345 13:59:59.897380 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4346 13:59:59.897841 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4347 13:59:59.900745 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4348 13:59:59.907529 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4349 13:59:59.908039
4350 13:59:59.908372
4351 13:59:59.914018 [DQSOSCAuto] RK1, (LSB)MR18= 0x6837, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4352 13:59:59.917175 CH0 RK1: MR19=808, MR18=6837
4353 13:59:59.924089 CH0_RK1: MR19=0x808, MR18=0x6837, DQSOSC=390, MR23=63, INC=172, DEC=114
4354 13:59:59.927360 [RxdqsGatingPostProcess] freq 600
4355 13:59:59.930478 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4356 13:59:59.933832 Pre-setting of DQS Precalculation
4357 13:59:59.940694 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4358 13:59:59.941176 ==
4359 13:59:59.943769 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 13:59:59.947289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 13:59:59.947780 ==
4362 13:59:59.953888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4363 13:59:59.957044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4364 13:59:59.961419 [CA 0] Center 36 (6~66) winsize 61
4365 13:59:59.964872 [CA 1] Center 36 (6~66) winsize 61
4366 13:59:59.968296 [CA 2] Center 34 (4~65) winsize 62
4367 13:59:59.971384 [CA 3] Center 34 (4~65) winsize 62
4368 13:59:59.974578 [CA 4] Center 34 (4~65) winsize 62
4369 13:59:59.978110 [CA 5] Center 34 (4~64) winsize 61
4370 13:59:59.978526
4371 13:59:59.981151 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4372 13:59:59.981720
4373 13:59:59.984518 [CATrainingPosCal] consider 1 rank data
4374 13:59:59.988314 u2DelayCellTimex100 = 270/100 ps
4375 13:59:59.991125 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4376 13:59:59.997858 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4377 14:00:00.001364 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4378 14:00:00.004423 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 14:00:00.007603 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4380 14:00:00.010824 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4381 14:00:00.011171
4382 14:00:00.014202 CA PerBit enable=1, Macro0, CA PI delay=34
4383 14:00:00.014433
4384 14:00:00.017398 [CBTSetCACLKResult] CA Dly = 34
4385 14:00:00.017641 CS Dly: 4 (0~35)
4386 14:00:00.020995 ==
4387 14:00:00.024271 Dram Type= 6, Freq= 0, CH_1, rank 1
4388 14:00:00.027417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 14:00:00.027570 ==
4390 14:00:00.033962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 14:00:00.037179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4392 14:00:00.041251 [CA 0] Center 36 (6~66) winsize 61
4393 14:00:00.044443 [CA 1] Center 36 (5~67) winsize 63
4394 14:00:00.048110 [CA 2] Center 34 (4~65) winsize 62
4395 14:00:00.051057 [CA 3] Center 34 (3~65) winsize 63
4396 14:00:00.054478 [CA 4] Center 34 (4~65) winsize 62
4397 14:00:00.057658 [CA 5] Center 34 (3~65) winsize 63
4398 14:00:00.057747
4399 14:00:00.061214 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4400 14:00:00.061300
4401 14:00:00.064352 [CATrainingPosCal] consider 2 rank data
4402 14:00:00.067583 u2DelayCellTimex100 = 270/100 ps
4403 14:00:00.071045 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4404 14:00:00.077511 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4405 14:00:00.080678 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4406 14:00:00.084559 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 14:00:00.087288 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4408 14:00:00.090622 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4409 14:00:00.090714
4410 14:00:00.093899 CA PerBit enable=1, Macro0, CA PI delay=34
4411 14:00:00.093983
4412 14:00:00.097515 [CBTSetCACLKResult] CA Dly = 34
4413 14:00:00.100524 CS Dly: 5 (0~38)
4414 14:00:00.100612
4415 14:00:00.103919 ----->DramcWriteLeveling(PI) begin...
4416 14:00:00.104016 ==
4417 14:00:00.107150 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 14:00:00.110535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 14:00:00.110635 ==
4420 14:00:00.113911 Write leveling (Byte 0): 30 => 30
4421 14:00:00.117063 Write leveling (Byte 1): 30 => 30
4422 14:00:00.120392 DramcWriteLeveling(PI) end<-----
4423 14:00:00.120486
4424 14:00:00.120574 ==
4425 14:00:00.123597 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 14:00:00.126988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 14:00:00.127080 ==
4428 14:00:00.130348 [Gating] SW mode calibration
4429 14:00:00.137214 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4430 14:00:00.143889 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4431 14:00:00.147151 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 14:00:00.150443 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 14:00:00.156914 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 14:00:00.160307 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 1) (1 1)
4435 14:00:00.163431 0 9 16 | B1->B0 | 2828 2828 | 0 0 | (1 1) (1 1)
4436 14:00:00.170195 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 14:00:00.173637 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 14:00:00.176676 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 14:00:00.183528 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 14:00:00.186707 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 14:00:00.189918 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 14:00:00.196535 0 10 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4443 14:00:00.200110 0 10 16 | B1->B0 | 4444 4444 | 0 0 | (0 0) (0 0)
4444 14:00:00.203505 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 14:00:00.209864 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 14:00:00.213360 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 14:00:00.216700 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 14:00:00.223106 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 14:00:00.226789 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 14:00:00.229860 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4451 14:00:00.236585 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4452 14:00:00.240113 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 14:00:00.243140 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 14:00:00.246650 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 14:00:00.253542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 14:00:00.256675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 14:00:00.259961 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 14:00:00.266511 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 14:00:00.269659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 14:00:00.273263 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 14:00:00.280005 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 14:00:00.283002 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 14:00:00.286210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 14:00:00.292817 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 14:00:00.296258 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 14:00:00.299517 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 14:00:00.305937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4468 14:00:00.309524 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 14:00:00.312646 Total UI for P1: 0, mck2ui 16
4470 14:00:00.316065 best dqsien dly found for B0: ( 0, 13, 16)
4471 14:00:00.319361 Total UI for P1: 0, mck2ui 16
4472 14:00:00.322584 best dqsien dly found for B1: ( 0, 13, 18)
4473 14:00:00.325709 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4474 14:00:00.329413 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4475 14:00:00.329605
4476 14:00:00.332745 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4477 14:00:00.335860 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4478 14:00:00.339057 [Gating] SW calibration Done
4479 14:00:00.339254 ==
4480 14:00:00.342653 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 14:00:00.349212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 14:00:00.349395 ==
4483 14:00:00.349496 RX Vref Scan: 0
4484 14:00:00.349563
4485 14:00:00.352523 RX Vref 0 -> 0, step: 1
4486 14:00:00.352632
4487 14:00:00.355949 RX Delay -230 -> 252, step: 16
4488 14:00:00.359302 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4489 14:00:00.362235 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4490 14:00:00.365729 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4491 14:00:00.372297 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4492 14:00:00.375983 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4493 14:00:00.379201 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4494 14:00:00.382436 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4495 14:00:00.385884 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4496 14:00:00.392311 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4497 14:00:00.395453 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4498 14:00:00.398658 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4499 14:00:00.402246 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4500 14:00:00.408994 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4501 14:00:00.412147 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4502 14:00:00.415358 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4503 14:00:00.418934 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4504 14:00:00.422206 ==
4505 14:00:00.425161 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 14:00:00.428757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 14:00:00.428855 ==
4508 14:00:00.428933 DQS Delay:
4509 14:00:00.431861 DQS0 = 0, DQS1 = 0
4510 14:00:00.431988 DQM Delay:
4511 14:00:00.435215 DQM0 = 43, DQM1 = 33
4512 14:00:00.435321 DQ Delay:
4513 14:00:00.438530 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4514 14:00:00.441723 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4515 14:00:00.445278 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4516 14:00:00.448452 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4517 14:00:00.448555
4518 14:00:00.448640
4519 14:00:00.448746 ==
4520 14:00:00.451720 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 14:00:00.455327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 14:00:00.455440 ==
4523 14:00:00.455531
4524 14:00:00.455621
4525 14:00:00.458585 TX Vref Scan disable
4526 14:00:00.461754 == TX Byte 0 ==
4527 14:00:00.465091 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4528 14:00:00.468730 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4529 14:00:00.471595 == TX Byte 1 ==
4530 14:00:00.475098 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4531 14:00:00.478649 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4532 14:00:00.478942 ==
4533 14:00:00.481853 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 14:00:00.488152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 14:00:00.488548 ==
4536 14:00:00.488816
4537 14:00:00.489147
4538 14:00:00.489585 TX Vref Scan disable
4539 14:00:00.492795 == TX Byte 0 ==
4540 14:00:00.496165 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4541 14:00:00.502667 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4542 14:00:00.503116 == TX Byte 1 ==
4543 14:00:00.505936 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 14:00:00.512709 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 14:00:00.513133
4546 14:00:00.513466 [DATLAT]
4547 14:00:00.513856 Freq=600, CH1 RK0
4548 14:00:00.514165
4549 14:00:00.515953 DATLAT Default: 0x9
4550 14:00:00.516372 0, 0xFFFF, sum = 0
4551 14:00:00.519574 1, 0xFFFF, sum = 0
4552 14:00:00.522720 2, 0xFFFF, sum = 0
4553 14:00:00.523149 3, 0xFFFF, sum = 0
4554 14:00:00.526043 4, 0xFFFF, sum = 0
4555 14:00:00.526465 5, 0xFFFF, sum = 0
4556 14:00:00.529461 6, 0xFFFF, sum = 0
4557 14:00:00.529933 7, 0xFFFF, sum = 0
4558 14:00:00.532338 8, 0x0, sum = 1
4559 14:00:00.532936 9, 0x0, sum = 2
4560 14:00:00.535667 10, 0x0, sum = 3
4561 14:00:00.536232 11, 0x0, sum = 4
4562 14:00:00.536585 best_step = 9
4563 14:00:00.536898
4564 14:00:00.539001 ==
4565 14:00:00.539534 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 14:00:00.545713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 14:00:00.546249 ==
4568 14:00:00.546590 RX Vref Scan: 1
4569 14:00:00.546902
4570 14:00:00.549111 RX Vref 0 -> 0, step: 1
4571 14:00:00.549702
4572 14:00:00.552696 RX Delay -195 -> 252, step: 8
4573 14:00:00.553115
4574 14:00:00.555577 Set Vref, RX VrefLevel [Byte0]: 60
4575 14:00:00.558999 [Byte1]: 54
4576 14:00:00.559417
4577 14:00:00.562327 Final RX Vref Byte 0 = 60 to rank0
4578 14:00:00.565543 Final RX Vref Byte 1 = 54 to rank0
4579 14:00:00.568859 Final RX Vref Byte 0 = 60 to rank1
4580 14:00:00.572496 Final RX Vref Byte 1 = 54 to rank1==
4581 14:00:00.575507 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 14:00:00.579153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 14:00:00.579671 ==
4584 14:00:00.582177 DQS Delay:
4585 14:00:00.582596 DQS0 = 0, DQS1 = 0
4586 14:00:00.585446 DQM Delay:
4587 14:00:00.585902 DQM0 = 38, DQM1 = 28
4588 14:00:00.588612 DQ Delay:
4589 14:00:00.589072 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4590 14:00:00.592100 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4591 14:00:00.595564 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4592 14:00:00.598516 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4593 14:00:00.599017
4594 14:00:00.602005
4595 14:00:00.608316 [DQSOSCAuto] RK0, (LSB)MR18= 0x2331, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4596 14:00:00.612027 CH1 RK0: MR19=808, MR18=2331
4597 14:00:00.618650 CH1_RK0: MR19=0x808, MR18=0x2331, DQSOSC=400, MR23=63, INC=163, DEC=109
4598 14:00:00.619327
4599 14:00:00.621902 ----->DramcWriteLeveling(PI) begin...
4600 14:00:00.622423 ==
4601 14:00:00.625018 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 14:00:00.628581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 14:00:00.629194 ==
4604 14:00:00.631771 Write leveling (Byte 0): 28 => 28
4605 14:00:00.634910 Write leveling (Byte 1): 29 => 29
4606 14:00:00.638393 DramcWriteLeveling(PI) end<-----
4607 14:00:00.638938
4608 14:00:00.639436 ==
4609 14:00:00.641771 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 14:00:00.645021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 14:00:00.645669 ==
4612 14:00:00.648265 [Gating] SW mode calibration
4613 14:00:00.654927 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4614 14:00:00.661764 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4615 14:00:00.664977 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 14:00:00.668369 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 14:00:00.674737 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4618 14:00:00.678393 0 9 12 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
4619 14:00:00.681437 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4620 14:00:00.688013 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 14:00:00.691455 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 14:00:00.695100 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 14:00:00.701383 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 14:00:00.705078 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 14:00:00.707855 0 10 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
4626 14:00:00.714694 0 10 12 | B1->B0 | 3030 3a3a | 0 0 | (1 1) (0 0)
4627 14:00:00.717978 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4628 14:00:00.720992 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 14:00:00.727639 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 14:00:00.731276 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 14:00:00.734499 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 14:00:00.740952 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 14:00:00.744441 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 14:00:00.747666 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4635 14:00:00.754330 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 14:00:00.757457 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 14:00:00.761055 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 14:00:00.767751 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 14:00:00.770807 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 14:00:00.774054 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 14:00:00.780872 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 14:00:00.784032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 14:00:00.787495 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 14:00:00.793904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 14:00:00.797472 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 14:00:00.800585 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 14:00:00.806921 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 14:00:00.810505 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 14:00:00.813608 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4650 14:00:00.820322 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4651 14:00:00.823513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 14:00:00.827237 Total UI for P1: 0, mck2ui 16
4653 14:00:00.830474 best dqsien dly found for B0: ( 0, 13, 12)
4654 14:00:00.833626 Total UI for P1: 0, mck2ui 16
4655 14:00:00.837087 best dqsien dly found for B1: ( 0, 13, 10)
4656 14:00:00.840283 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4657 14:00:00.843647 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4658 14:00:00.843944
4659 14:00:00.846650 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4660 14:00:00.850408 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4661 14:00:00.853331 [Gating] SW calibration Done
4662 14:00:00.853665 ==
4663 14:00:00.856829 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 14:00:00.860222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 14:00:00.863258 ==
4666 14:00:00.863548 RX Vref Scan: 0
4667 14:00:00.863779
4668 14:00:00.866622 RX Vref 0 -> 0, step: 1
4669 14:00:00.866910
4670 14:00:00.870177 RX Delay -230 -> 252, step: 16
4671 14:00:00.873461 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4672 14:00:00.876800 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4673 14:00:00.879948 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4674 14:00:00.883177 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4675 14:00:00.890055 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4676 14:00:00.893505 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4677 14:00:00.896590 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4678 14:00:00.900110 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4679 14:00:00.906869 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4680 14:00:00.910230 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4681 14:00:00.913338 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4682 14:00:00.916525 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4683 14:00:00.923344 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4684 14:00:00.926548 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4685 14:00:00.929766 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4686 14:00:00.933238 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4687 14:00:00.933776 ==
4688 14:00:00.936751 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 14:00:00.943368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 14:00:00.943852 ==
4691 14:00:00.944189 DQS Delay:
4692 14:00:00.946387 DQS0 = 0, DQS1 = 0
4693 14:00:00.946898 DQM Delay:
4694 14:00:00.947236 DQM0 = 36, DQM1 = 30
4695 14:00:00.949861 DQ Delay:
4696 14:00:00.953322 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4697 14:00:00.956527 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4698 14:00:00.959500 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4699 14:00:00.962857 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =41
4700 14:00:00.963276
4701 14:00:00.963630
4702 14:00:00.964009 ==
4703 14:00:00.966389 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 14:00:00.969419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 14:00:00.969875 ==
4706 14:00:00.970224
4707 14:00:00.970567
4708 14:00:00.972642 TX Vref Scan disable
4709 14:00:00.976040 == TX Byte 0 ==
4710 14:00:00.979435 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 14:00:00.982788 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 14:00:00.985977 == TX Byte 1 ==
4713 14:00:00.989192 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4714 14:00:00.992520 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4715 14:00:00.992931 ==
4716 14:00:00.996031 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 14:00:00.999157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 14:00:01.002607 ==
4719 14:00:01.003056
4720 14:00:01.003379
4721 14:00:01.003693 TX Vref Scan disable
4722 14:00:01.006238 == TX Byte 0 ==
4723 14:00:01.009646 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4724 14:00:01.016341 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4725 14:00:01.016865 == TX Byte 1 ==
4726 14:00:01.019498 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4727 14:00:01.025867 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4728 14:00:01.026276
4729 14:00:01.026618 [DATLAT]
4730 14:00:01.027009 Freq=600, CH1 RK1
4731 14:00:01.027313
4732 14:00:01.029473 DATLAT Default: 0x9
4733 14:00:01.029958 0, 0xFFFF, sum = 0
4734 14:00:01.032646 1, 0xFFFF, sum = 0
4735 14:00:01.036084 2, 0xFFFF, sum = 0
4736 14:00:01.036500 3, 0xFFFF, sum = 0
4737 14:00:01.039459 4, 0xFFFF, sum = 0
4738 14:00:01.039948 5, 0xFFFF, sum = 0
4739 14:00:01.042667 6, 0xFFFF, sum = 0
4740 14:00:01.043094 7, 0xFFFF, sum = 0
4741 14:00:01.045759 8, 0x0, sum = 1
4742 14:00:01.046176 9, 0x0, sum = 2
4743 14:00:01.046546 10, 0x0, sum = 3
4744 14:00:01.049551 11, 0x0, sum = 4
4745 14:00:01.050059 best_step = 9
4746 14:00:01.050496
4747 14:00:01.052572 ==
4748 14:00:01.052982 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 14:00:01.059347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 14:00:01.059818 ==
4751 14:00:01.060230 RX Vref Scan: 0
4752 14:00:01.060558
4753 14:00:01.062582 RX Vref 0 -> 0, step: 1
4754 14:00:01.063011
4755 14:00:01.065862 RX Delay -195 -> 252, step: 8
4756 14:00:01.072343 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4757 14:00:01.075629 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4758 14:00:01.079159 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4759 14:00:01.082223 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4760 14:00:01.085668 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4761 14:00:01.092155 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4762 14:00:01.095799 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4763 14:00:01.098907 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4764 14:00:01.102325 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4765 14:00:01.109055 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4766 14:00:01.112333 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4767 14:00:01.115626 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4768 14:00:01.119161 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4769 14:00:01.125268 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4770 14:00:01.129040 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4771 14:00:01.131970 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4772 14:00:01.132399 ==
4773 14:00:01.135914 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 14:00:01.138814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 14:00:01.139229 ==
4776 14:00:01.141943 DQS Delay:
4777 14:00:01.142351 DQS0 = 0, DQS1 = 0
4778 14:00:01.145334 DQM Delay:
4779 14:00:01.145766 DQM0 = 35, DQM1 = 29
4780 14:00:01.146096 DQ Delay:
4781 14:00:01.148582 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4782 14:00:01.151871 DQ4 =32, DQ5 =44, DQ6 =44, DQ7 =36
4783 14:00:01.155549 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4784 14:00:01.158476 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4785 14:00:01.158892
4786 14:00:01.161784
4787 14:00:01.168425 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4788 14:00:01.171717 CH1 RK1: MR19=808, MR18=3C5C
4789 14:00:01.178286 CH1_RK1: MR19=0x808, MR18=0x3C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4790 14:00:01.181462 [RxdqsGatingPostProcess] freq 600
4791 14:00:01.185010 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4792 14:00:01.188165 Pre-setting of DQS Precalculation
4793 14:00:01.195052 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4794 14:00:01.201341 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4795 14:00:01.207975 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4796 14:00:01.208551
4797 14:00:01.208910
4798 14:00:01.211399 [Calibration Summary] 1200 Mbps
4799 14:00:01.211828 CH 0, Rank 0
4800 14:00:01.214469 SW Impedance : PASS
4801 14:00:01.217931 DUTY Scan : NO K
4802 14:00:01.218358 ZQ Calibration : PASS
4803 14:00:01.221252 Jitter Meter : NO K
4804 14:00:01.224264 CBT Training : PASS
4805 14:00:01.224691 Write leveling : PASS
4806 14:00:01.227714 RX DQS gating : PASS
4807 14:00:01.228142 RX DQ/DQS(RDDQC) : PASS
4808 14:00:01.231197 TX DQ/DQS : PASS
4809 14:00:01.234262 RX DATLAT : PASS
4810 14:00:01.234673 RX DQ/DQS(Engine): PASS
4811 14:00:01.237567 TX OE : NO K
4812 14:00:01.237980 All Pass.
4813 14:00:01.238383
4814 14:00:01.240926 CH 0, Rank 1
4815 14:00:01.241333 SW Impedance : PASS
4816 14:00:01.243986 DUTY Scan : NO K
4817 14:00:01.247407 ZQ Calibration : PASS
4818 14:00:01.247817 Jitter Meter : NO K
4819 14:00:01.250734 CBT Training : PASS
4820 14:00:01.254040 Write leveling : PASS
4821 14:00:01.254539 RX DQS gating : PASS
4822 14:00:01.257585 RX DQ/DQS(RDDQC) : PASS
4823 14:00:01.261018 TX DQ/DQS : PASS
4824 14:00:01.261602 RX DATLAT : PASS
4825 14:00:01.263928 RX DQ/DQS(Engine): PASS
4826 14:00:01.267792 TX OE : NO K
4827 14:00:01.268322 All Pass.
4828 14:00:01.268767
4829 14:00:01.269183 CH 1, Rank 0
4830 14:00:01.270542 SW Impedance : PASS
4831 14:00:01.273672 DUTY Scan : NO K
4832 14:00:01.274100 ZQ Calibration : PASS
4833 14:00:01.277037 Jitter Meter : NO K
4834 14:00:01.280317 CBT Training : PASS
4835 14:00:01.280744 Write leveling : PASS
4836 14:00:01.283543 RX DQS gating : PASS
4837 14:00:01.287182 RX DQ/DQS(RDDQC) : PASS
4838 14:00:01.287758 TX DQ/DQS : PASS
4839 14:00:01.290153 RX DATLAT : PASS
4840 14:00:01.293735 RX DQ/DQS(Engine): PASS
4841 14:00:01.294160 TX OE : NO K
4842 14:00:01.294626 All Pass.
4843 14:00:01.296763
4844 14:00:01.297189 CH 1, Rank 1
4845 14:00:01.300207 SW Impedance : PASS
4846 14:00:01.300615 DUTY Scan : NO K
4847 14:00:01.303508 ZQ Calibration : PASS
4848 14:00:01.303988 Jitter Meter : NO K
4849 14:00:01.306817 CBT Training : PASS
4850 14:00:01.310049 Write leveling : PASS
4851 14:00:01.310460 RX DQS gating : PASS
4852 14:00:01.313415 RX DQ/DQS(RDDQC) : PASS
4853 14:00:01.316773 TX DQ/DQS : PASS
4854 14:00:01.317186 RX DATLAT : PASS
4855 14:00:01.320302 RX DQ/DQS(Engine): PASS
4856 14:00:01.323252 TX OE : NO K
4857 14:00:01.323544 All Pass.
4858 14:00:01.323774
4859 14:00:01.326525 DramC Write-DBI off
4860 14:00:01.326751 PER_BANK_REFRESH: Hybrid Mode
4861 14:00:01.329522 TX_TRACKING: ON
4862 14:00:01.339517 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4863 14:00:01.342808 [FAST_K] Save calibration result to emmc
4864 14:00:01.346007 dramc_set_vcore_voltage set vcore to 662500
4865 14:00:01.346136 Read voltage for 933, 3
4866 14:00:01.349595 Vio18 = 0
4867 14:00:01.349707 Vcore = 662500
4868 14:00:01.349795 Vdram = 0
4869 14:00:01.352631 Vddq = 0
4870 14:00:01.352751 Vmddr = 0
4871 14:00:01.356121 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4872 14:00:01.362470 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4873 14:00:01.366004 MEM_TYPE=3, freq_sel=17
4874 14:00:01.369082 sv_algorithm_assistance_LP4_1600
4875 14:00:01.372694 ============ PULL DRAM RESETB DOWN ============
4876 14:00:01.376000 ========== PULL DRAM RESETB DOWN end =========
4877 14:00:01.382483 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4878 14:00:01.385995 ===================================
4879 14:00:01.386080 LPDDR4 DRAM CONFIGURATION
4880 14:00:01.389199 ===================================
4881 14:00:01.392549 EX_ROW_EN[0] = 0x0
4882 14:00:01.395467 EX_ROW_EN[1] = 0x0
4883 14:00:01.395548 LP4Y_EN = 0x0
4884 14:00:01.399012 WORK_FSP = 0x0
4885 14:00:01.399092 WL = 0x3
4886 14:00:01.402327 RL = 0x3
4887 14:00:01.402410 BL = 0x2
4888 14:00:01.405770 RPST = 0x0
4889 14:00:01.405851 RD_PRE = 0x0
4890 14:00:01.408774 WR_PRE = 0x1
4891 14:00:01.408854 WR_PST = 0x0
4892 14:00:01.412336 DBI_WR = 0x0
4893 14:00:01.412416 DBI_RD = 0x0
4894 14:00:01.415415 OTF = 0x1
4895 14:00:01.418881 ===================================
4896 14:00:01.422179 ===================================
4897 14:00:01.422264 ANA top config
4898 14:00:01.425278 ===================================
4899 14:00:01.428680 DLL_ASYNC_EN = 0
4900 14:00:01.432039 ALL_SLAVE_EN = 1
4901 14:00:01.435260 NEW_RANK_MODE = 1
4902 14:00:01.435343 DLL_IDLE_MODE = 1
4903 14:00:01.438538 LP45_APHY_COMB_EN = 1
4904 14:00:01.441821 TX_ODT_DIS = 1
4905 14:00:01.445221 NEW_8X_MODE = 1
4906 14:00:01.448566 ===================================
4907 14:00:01.451735 ===================================
4908 14:00:01.455322 data_rate = 1866
4909 14:00:01.455404 CKR = 1
4910 14:00:01.458362 DQ_P2S_RATIO = 8
4911 14:00:01.461515 ===================================
4912 14:00:01.464982 CA_P2S_RATIO = 8
4913 14:00:01.468275 DQ_CA_OPEN = 0
4914 14:00:01.471544 DQ_SEMI_OPEN = 0
4915 14:00:01.475182 CA_SEMI_OPEN = 0
4916 14:00:01.475288 CA_FULL_RATE = 0
4917 14:00:01.478358 DQ_CKDIV4_EN = 1
4918 14:00:01.481585 CA_CKDIV4_EN = 1
4919 14:00:01.484741 CA_PREDIV_EN = 0
4920 14:00:01.488087 PH8_DLY = 0
4921 14:00:01.491265 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4922 14:00:01.491354 DQ_AAMCK_DIV = 4
4923 14:00:01.494856 CA_AAMCK_DIV = 4
4924 14:00:01.498092 CA_ADMCK_DIV = 4
4925 14:00:01.501239 DQ_TRACK_CA_EN = 0
4926 14:00:01.504860 CA_PICK = 933
4927 14:00:01.508022 CA_MCKIO = 933
4928 14:00:01.508108 MCKIO_SEMI = 0
4929 14:00:01.511416 PLL_FREQ = 3732
4930 14:00:01.515221 DQ_UI_PI_RATIO = 32
4931 14:00:01.517802 CA_UI_PI_RATIO = 0
4932 14:00:01.521273 ===================================
4933 14:00:01.524528 ===================================
4934 14:00:01.527660 memory_type:LPDDR4
4935 14:00:01.527779 GP_NUM : 10
4936 14:00:01.531085 SRAM_EN : 1
4937 14:00:01.534530 MD32_EN : 0
4938 14:00:01.537630 ===================================
4939 14:00:01.537745 [ANA_INIT] >>>>>>>>>>>>>>
4940 14:00:01.540993 <<<<<< [CONFIGURE PHASE]: ANA_TX
4941 14:00:01.544484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4942 14:00:01.547599 ===================================
4943 14:00:01.551121 data_rate = 1866,PCW = 0X8f00
4944 14:00:01.554359 ===================================
4945 14:00:01.557830 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4946 14:00:01.564190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 14:00:01.567686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 14:00:01.574028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4949 14:00:01.577625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4950 14:00:01.580856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4951 14:00:01.584152 [ANA_INIT] flow start
4952 14:00:01.584266 [ANA_INIT] PLL >>>>>>>>
4953 14:00:01.587174 [ANA_INIT] PLL <<<<<<<<
4954 14:00:01.590433 [ANA_INIT] MIDPI >>>>>>>>
4955 14:00:01.590547 [ANA_INIT] MIDPI <<<<<<<<
4956 14:00:01.593862 [ANA_INIT] DLL >>>>>>>>
4957 14:00:01.597079 [ANA_INIT] flow end
4958 14:00:01.600553 ============ LP4 DIFF to SE enter ============
4959 14:00:01.604072 ============ LP4 DIFF to SE exit ============
4960 14:00:01.607202 [ANA_INIT] <<<<<<<<<<<<<
4961 14:00:01.610341 [Flow] Enable top DCM control >>>>>
4962 14:00:01.613946 [Flow] Enable top DCM control <<<<<
4963 14:00:01.617063 Enable DLL master slave shuffle
4964 14:00:01.620197 ==============================================================
4965 14:00:01.623455 Gating Mode config
4966 14:00:01.630213 ==============================================================
4967 14:00:01.630332 Config description:
4968 14:00:01.640210 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4969 14:00:01.646649 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4970 14:00:01.653339 SELPH_MODE 0: By rank 1: By Phase
4971 14:00:01.656481 ==============================================================
4972 14:00:01.660088 GAT_TRACK_EN = 1
4973 14:00:01.663190 RX_GATING_MODE = 2
4974 14:00:01.666730 RX_GATING_TRACK_MODE = 2
4975 14:00:01.669951 SELPH_MODE = 1
4976 14:00:01.673353 PICG_EARLY_EN = 1
4977 14:00:01.676541 VALID_LAT_VALUE = 1
4978 14:00:01.679900 ==============================================================
4979 14:00:01.683270 Enter into Gating configuration >>>>
4980 14:00:01.686411 Exit from Gating configuration <<<<
4981 14:00:01.689495 Enter into DVFS_PRE_config >>>>>
4982 14:00:01.702734 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4983 14:00:01.706251 Exit from DVFS_PRE_config <<<<<
4984 14:00:01.709528 Enter into PICG configuration >>>>
4985 14:00:01.712662 Exit from PICG configuration <<<<
4986 14:00:01.712748 [RX_INPUT] configuration >>>>>
4987 14:00:01.716272 [RX_INPUT] configuration <<<<<
4988 14:00:01.722584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4989 14:00:01.726063 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4990 14:00:01.732395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 14:00:01.739150 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 14:00:01.745695 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 14:00:01.752351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 14:00:01.755537 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4995 14:00:01.758957 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4996 14:00:01.765343 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4997 14:00:01.768677 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4998 14:00:01.772297 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4999 14:00:01.775400 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 14:00:01.778665 ===================================
5001 14:00:01.782087 LPDDR4 DRAM CONFIGURATION
5002 14:00:01.785178 ===================================
5003 14:00:01.788667 EX_ROW_EN[0] = 0x0
5004 14:00:01.788779 EX_ROW_EN[1] = 0x0
5005 14:00:01.791788 LP4Y_EN = 0x0
5006 14:00:01.791899 WORK_FSP = 0x0
5007 14:00:01.795066 WL = 0x3
5008 14:00:01.798433 RL = 0x3
5009 14:00:01.798542 BL = 0x2
5010 14:00:01.801682 RPST = 0x0
5011 14:00:01.801792 RD_PRE = 0x0
5012 14:00:01.804786 WR_PRE = 0x1
5013 14:00:01.804899 WR_PST = 0x0
5014 14:00:01.808299 DBI_WR = 0x0
5015 14:00:01.808412 DBI_RD = 0x0
5016 14:00:01.811604 OTF = 0x1
5017 14:00:01.814907 ===================================
5018 14:00:01.818200 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5019 14:00:01.821332 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5020 14:00:01.827923 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5021 14:00:01.831553 ===================================
5022 14:00:01.831670 LPDDR4 DRAM CONFIGURATION
5023 14:00:01.834615 ===================================
5024 14:00:01.837881 EX_ROW_EN[0] = 0x10
5025 14:00:01.837995 EX_ROW_EN[1] = 0x0
5026 14:00:01.841335 LP4Y_EN = 0x0
5027 14:00:01.841447 WORK_FSP = 0x0
5028 14:00:01.844559 WL = 0x3
5029 14:00:01.847803 RL = 0x3
5030 14:00:01.847916 BL = 0x2
5031 14:00:01.850996 RPST = 0x0
5032 14:00:01.851106 RD_PRE = 0x0
5033 14:00:01.854623 WR_PRE = 0x1
5034 14:00:01.854735 WR_PST = 0x0
5035 14:00:01.857779 DBI_WR = 0x0
5036 14:00:01.857889 DBI_RD = 0x0
5037 14:00:01.861102 OTF = 0x1
5038 14:00:01.864279 ===================================
5039 14:00:01.870985 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5040 14:00:01.874234 nWR fixed to 30
5041 14:00:01.874349 [ModeRegInit_LP4] CH0 RK0
5042 14:00:01.877618 [ModeRegInit_LP4] CH0 RK1
5043 14:00:01.880868 [ModeRegInit_LP4] CH1 RK0
5044 14:00:01.880983 [ModeRegInit_LP4] CH1 RK1
5045 14:00:01.884269 match AC timing 9
5046 14:00:01.887610 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5047 14:00:01.890883 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5048 14:00:01.897635 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5049 14:00:01.900850 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5050 14:00:01.907297 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5051 14:00:01.907428 ==
5052 14:00:01.910493 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 14:00:01.914050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5054 14:00:01.914163 ==
5055 14:00:01.920513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5056 14:00:01.927082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5057 14:00:01.930342 [CA 0] Center 38 (8~69) winsize 62
5058 14:00:01.933678 [CA 1] Center 38 (7~69) winsize 63
5059 14:00:01.936910 [CA 2] Center 35 (6~65) winsize 60
5060 14:00:01.940354 [CA 3] Center 35 (5~65) winsize 61
5061 14:00:01.943622 [CA 4] Center 34 (4~65) winsize 62
5062 14:00:01.946850 [CA 5] Center 34 (4~64) winsize 61
5063 14:00:01.946938
5064 14:00:01.950412 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5065 14:00:01.950494
5066 14:00:01.953534 [CATrainingPosCal] consider 1 rank data
5067 14:00:01.957054 u2DelayCellTimex100 = 270/100 ps
5068 14:00:01.960311 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5069 14:00:01.963454 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5070 14:00:01.966963 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5071 14:00:01.970274 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5072 14:00:01.973482 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5073 14:00:01.976979 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5074 14:00:01.977061
5075 14:00:01.983168 CA PerBit enable=1, Macro0, CA PI delay=34
5076 14:00:01.983253
5077 14:00:01.983352 [CBTSetCACLKResult] CA Dly = 34
5078 14:00:01.986554 CS Dly: 7 (0~38)
5079 14:00:01.986663 ==
5080 14:00:01.989704 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 14:00:01.993239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 14:00:01.993339 ==
5083 14:00:01.999926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5084 14:00:02.006580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5085 14:00:02.009711 [CA 0] Center 38 (8~69) winsize 62
5086 14:00:02.012817 [CA 1] Center 38 (7~69) winsize 63
5087 14:00:02.016384 [CA 2] Center 35 (5~66) winsize 62
5088 14:00:02.019673 [CA 3] Center 35 (5~65) winsize 61
5089 14:00:02.022824 [CA 4] Center 34 (4~65) winsize 62
5090 14:00:02.026303 [CA 5] Center 34 (3~65) winsize 63
5091 14:00:02.026391
5092 14:00:02.029417 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5093 14:00:02.029526
5094 14:00:02.033001 [CATrainingPosCal] consider 2 rank data
5095 14:00:02.036047 u2DelayCellTimex100 = 270/100 ps
5096 14:00:02.039495 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5097 14:00:02.042936 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5098 14:00:02.046149 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5099 14:00:02.049370 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5100 14:00:02.052681 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5101 14:00:02.059171 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5102 14:00:02.059255
5103 14:00:02.062686 CA PerBit enable=1, Macro0, CA PI delay=34
5104 14:00:02.062769
5105 14:00:02.065852 [CBTSetCACLKResult] CA Dly = 34
5106 14:00:02.065935 CS Dly: 7 (0~38)
5107 14:00:02.066000
5108 14:00:02.069104 ----->DramcWriteLeveling(PI) begin...
5109 14:00:02.069187 ==
5110 14:00:02.072736 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 14:00:02.079047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 14:00:02.079132 ==
5113 14:00:02.082368 Write leveling (Byte 0): 32 => 32
5114 14:00:02.082450 Write leveling (Byte 1): 30 => 30
5115 14:00:02.085748 DramcWriteLeveling(PI) end<-----
5116 14:00:02.085830
5117 14:00:02.089106 ==
5118 14:00:02.089188 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 14:00:02.095299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 14:00:02.095417 ==
5121 14:00:02.098885 [Gating] SW mode calibration
5122 14:00:02.105448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5123 14:00:02.108711 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5124 14:00:02.115347 0 14 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5125 14:00:02.118466 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5126 14:00:02.121999 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 14:00:02.128412 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 14:00:02.131658 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 14:00:02.135173 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 14:00:02.141894 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 14:00:02.144987 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5132 14:00:02.148113 0 15 0 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
5133 14:00:02.154964 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5134 14:00:02.158350 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 14:00:02.161588 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 14:00:02.168330 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 14:00:02.171469 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 14:00:02.174719 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 14:00:02.181114 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5140 14:00:02.184361 1 0 0 | B1->B0 | 2b2b 3e3e | 0 0 | (1 1) (0 0)
5141 14:00:02.187883 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5142 14:00:02.194576 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 14:00:02.197646 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 14:00:02.201329 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 14:00:02.207654 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 14:00:02.211104 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 14:00:02.214228 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5148 14:00:02.221050 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5149 14:00:02.224376 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5150 14:00:02.227555 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 14:00:02.234259 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 14:00:02.237313 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 14:00:02.240843 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 14:00:02.247444 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 14:00:02.250533 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 14:00:02.253939 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 14:00:02.260588 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 14:00:02.263814 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 14:00:02.267195 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 14:00:02.273811 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 14:00:02.277125 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 14:00:02.280267 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 14:00:02.286845 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 14:00:02.290285 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5165 14:00:02.293658 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5166 14:00:02.296906 Total UI for P1: 0, mck2ui 16
5167 14:00:02.300214 best dqsien dly found for B0: ( 1, 3, 0)
5168 14:00:02.306823 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 14:00:02.306937 Total UI for P1: 0, mck2ui 16
5170 14:00:02.310428 best dqsien dly found for B1: ( 1, 3, 6)
5171 14:00:02.313585 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5172 14:00:02.320308 best DQS1 dly(MCK, UI, PI) = (1, 3, 6)
5173 14:00:02.320393
5174 14:00:02.323526 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5175 14:00:02.326931 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 6)
5176 14:00:02.330185 [Gating] SW calibration Done
5177 14:00:02.330267 ==
5178 14:00:02.333602 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 14:00:02.336881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 14:00:02.336962 ==
5181 14:00:02.337026 RX Vref Scan: 0
5182 14:00:02.340081
5183 14:00:02.340161 RX Vref 0 -> 0, step: 1
5184 14:00:02.340225
5185 14:00:02.343415 RX Delay -80 -> 252, step: 8
5186 14:00:02.346906 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5187 14:00:02.350213 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5188 14:00:02.353200 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5189 14:00:02.360147 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5190 14:00:02.363339 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5191 14:00:02.366472 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5192 14:00:02.369902 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5193 14:00:02.373207 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5194 14:00:02.379800 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5195 14:00:02.383376 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5196 14:00:02.386472 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5197 14:00:02.389691 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5198 14:00:02.393039 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5199 14:00:02.399802 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5200 14:00:02.402888 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5201 14:00:02.406506 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5202 14:00:02.406589 ==
5203 14:00:02.409725 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 14:00:02.412857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 14:00:02.412938 ==
5206 14:00:02.416213 DQS Delay:
5207 14:00:02.416294 DQS0 = 0, DQS1 = 0
5208 14:00:02.419534 DQM Delay:
5209 14:00:02.419615 DQM0 = 95, DQM1 = 83
5210 14:00:02.419679 DQ Delay:
5211 14:00:02.422895 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5212 14:00:02.426340 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5213 14:00:02.429434 DQ8 =79, DQ9 =67, DQ10 =83, DQ11 =75
5214 14:00:02.433068 DQ12 =87, DQ13 =87, DQ14 =95, DQ15 =91
5215 14:00:02.433163
5216 14:00:02.433228
5217 14:00:02.436278 ==
5218 14:00:02.439365 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 14:00:02.442815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 14:00:02.442920 ==
5221 14:00:02.443016
5222 14:00:02.443089
5223 14:00:02.446002 TX Vref Scan disable
5224 14:00:02.446101 == TX Byte 0 ==
5225 14:00:02.452815 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5226 14:00:02.455871 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5227 14:00:02.455957 == TX Byte 1 ==
5228 14:00:02.462499 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5229 14:00:02.465961 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5230 14:00:02.466058 ==
5231 14:00:02.469082 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 14:00:02.472843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 14:00:02.472957 ==
5234 14:00:02.473057
5235 14:00:02.473150
5236 14:00:02.475847 TX Vref Scan disable
5237 14:00:02.479293 == TX Byte 0 ==
5238 14:00:02.482817 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5239 14:00:02.485954 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5240 14:00:02.489120 == TX Byte 1 ==
5241 14:00:02.492659 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5242 14:00:02.495997 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5243 14:00:02.496108
5244 14:00:02.499052 [DATLAT]
5245 14:00:02.499161 Freq=933, CH0 RK0
5246 14:00:02.499263
5247 14:00:02.502618 DATLAT Default: 0xd
5248 14:00:02.502730 0, 0xFFFF, sum = 0
5249 14:00:02.505976 1, 0xFFFF, sum = 0
5250 14:00:02.506095 2, 0xFFFF, sum = 0
5251 14:00:02.509215 3, 0xFFFF, sum = 0
5252 14:00:02.509326 4, 0xFFFF, sum = 0
5253 14:00:02.512500 5, 0xFFFF, sum = 0
5254 14:00:02.512611 6, 0xFFFF, sum = 0
5255 14:00:02.515640 7, 0xFFFF, sum = 0
5256 14:00:02.515756 8, 0xFFFF, sum = 0
5257 14:00:02.519251 9, 0xFFFF, sum = 0
5258 14:00:02.519363 10, 0x0, sum = 1
5259 14:00:02.522452 11, 0x0, sum = 2
5260 14:00:02.522564 12, 0x0, sum = 3
5261 14:00:02.525496 13, 0x0, sum = 4
5262 14:00:02.525624 best_step = 11
5263 14:00:02.525722
5264 14:00:02.525815 ==
5265 14:00:02.529106 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 14:00:02.535598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 14:00:02.535713 ==
5268 14:00:02.535811 RX Vref Scan: 1
5269 14:00:02.535907
5270 14:00:02.538731 RX Vref 0 -> 0, step: 1
5271 14:00:02.538843
5272 14:00:02.542041 RX Delay -77 -> 252, step: 4
5273 14:00:02.542154
5274 14:00:02.545452 Set Vref, RX VrefLevel [Byte0]: 60
5275 14:00:02.548770 [Byte1]: 48
5276 14:00:02.548881
5277 14:00:02.551806 Final RX Vref Byte 0 = 60 to rank0
5278 14:00:02.555324 Final RX Vref Byte 1 = 48 to rank0
5279 14:00:02.558596 Final RX Vref Byte 0 = 60 to rank1
5280 14:00:02.561918 Final RX Vref Byte 1 = 48 to rank1==
5281 14:00:02.565229 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 14:00:02.568507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 14:00:02.568593 ==
5284 14:00:02.571897 DQS Delay:
5285 14:00:02.572004 DQS0 = 0, DQS1 = 0
5286 14:00:02.575078 DQM Delay:
5287 14:00:02.575164 DQM0 = 95, DQM1 = 82
5288 14:00:02.575229 DQ Delay:
5289 14:00:02.578459 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5290 14:00:02.581819 DQ4 =96, DQ5 =86, DQ6 =102, DQ7 =106
5291 14:00:02.584951 DQ8 =74, DQ9 =70, DQ10 =84, DQ11 =76
5292 14:00:02.588523 DQ12 =86, DQ13 =88, DQ14 =92, DQ15 =90
5293 14:00:02.588604
5294 14:00:02.588667
5295 14:00:02.598354 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5296 14:00:02.601464 CH0 RK0: MR19=505, MR18=1312
5297 14:00:02.605182 CH0_RK0: MR19=0x505, MR18=0x1312, DQSOSC=415, MR23=63, INC=62, DEC=41
5298 14:00:02.608199
5299 14:00:02.611792 ----->DramcWriteLeveling(PI) begin...
5300 14:00:02.611875 ==
5301 14:00:02.615047 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 14:00:02.618161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 14:00:02.618243 ==
5304 14:00:02.621389 Write leveling (Byte 0): 30 => 30
5305 14:00:02.625000 Write leveling (Byte 1): 28 => 28
5306 14:00:02.627982 DramcWriteLeveling(PI) end<-----
5307 14:00:02.628055
5308 14:00:02.628116 ==
5309 14:00:02.631513 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 14:00:02.635016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 14:00:02.635097 ==
5312 14:00:02.638198 [Gating] SW mode calibration
5313 14:00:02.644816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5314 14:00:02.651318 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5315 14:00:02.654838 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5316 14:00:02.657960 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 14:00:02.664630 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 14:00:02.667849 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 14:00:02.671266 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 14:00:02.677895 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 14:00:02.681159 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 14:00:02.684336 0 14 28 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (1 1)
5323 14:00:02.691253 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5324 14:00:02.694555 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 14:00:02.697555 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 14:00:02.704294 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 14:00:02.707813 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 14:00:02.710916 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 14:00:02.717644 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 14:00:02.720898 0 15 28 | B1->B0 | 2626 3131 | 0 1 | (0 0) (0 0)
5331 14:00:02.724090 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5332 14:00:02.730654 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 14:00:02.734102 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 14:00:02.737581 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 14:00:02.744118 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 14:00:02.747512 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 14:00:02.750931 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 14:00:02.757247 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5339 14:00:02.760885 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5340 14:00:02.763894 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 14:00:02.770613 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 14:00:02.773658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 14:00:02.777247 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 14:00:02.780439 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 14:00:02.786905 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 14:00:02.790398 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 14:00:02.793572 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 14:00:02.800245 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 14:00:02.803516 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 14:00:02.806877 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 14:00:02.813463 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 14:00:02.817104 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 14:00:02.820264 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 14:00:02.826589 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5355 14:00:02.830207 Total UI for P1: 0, mck2ui 16
5356 14:00:02.833265 best dqsien dly found for B0: ( 1, 2, 26)
5357 14:00:02.836837 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5358 14:00:02.839920 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 14:00:02.843217 Total UI for P1: 0, mck2ui 16
5360 14:00:02.846606 best dqsien dly found for B1: ( 1, 2, 30)
5361 14:00:02.849871 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5362 14:00:02.853240 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5363 14:00:02.856695
5364 14:00:02.859866 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5365 14:00:02.863012 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5366 14:00:02.866404 [Gating] SW calibration Done
5367 14:00:02.866486 ==
5368 14:00:02.869792 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 14:00:02.872776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 14:00:02.872858 ==
5371 14:00:02.876225 RX Vref Scan: 0
5372 14:00:02.876332
5373 14:00:02.876420 RX Vref 0 -> 0, step: 1
5374 14:00:02.876484
5375 14:00:02.879434 RX Delay -80 -> 252, step: 8
5376 14:00:02.882754 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5377 14:00:02.886238 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5378 14:00:02.892875 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5379 14:00:02.895984 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5380 14:00:02.899235 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5381 14:00:02.902806 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5382 14:00:02.905829 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5383 14:00:02.912609 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5384 14:00:02.915957 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5385 14:00:02.919355 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5386 14:00:02.922795 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5387 14:00:02.925967 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5388 14:00:02.932626 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5389 14:00:02.935793 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5390 14:00:02.939268 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5391 14:00:02.942889 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5392 14:00:02.942972 ==
5393 14:00:02.945960 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 14:00:02.949149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 14:00:02.952639 ==
5396 14:00:02.952722 DQS Delay:
5397 14:00:02.952786 DQS0 = 0, DQS1 = 0
5398 14:00:02.955842 DQM Delay:
5399 14:00:02.955924 DQM0 = 92, DQM1 = 82
5400 14:00:02.959304 DQ Delay:
5401 14:00:02.959416 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5402 14:00:02.962510 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5403 14:00:02.965738 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =71
5404 14:00:02.972220 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5405 14:00:02.972330
5406 14:00:02.972422
5407 14:00:02.972509 ==
5408 14:00:02.975709 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 14:00:02.978947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 14:00:02.979031 ==
5411 14:00:02.979095
5412 14:00:02.979153
5413 14:00:02.982091 TX Vref Scan disable
5414 14:00:02.982202 == TX Byte 0 ==
5415 14:00:02.988660 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5416 14:00:02.991970 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5417 14:00:02.992066 == TX Byte 1 ==
5418 14:00:02.998836 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5419 14:00:03.002000 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5420 14:00:03.002084 ==
5421 14:00:03.005410 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 14:00:03.008512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 14:00:03.008602 ==
5424 14:00:03.008666
5425 14:00:03.008726
5426 14:00:03.012072 TX Vref Scan disable
5427 14:00:03.015135 == TX Byte 0 ==
5428 14:00:03.018623 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5429 14:00:03.021803 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5430 14:00:03.025334 == TX Byte 1 ==
5431 14:00:03.028363 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5432 14:00:03.031781 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5433 14:00:03.035108
5434 14:00:03.035190 [DATLAT]
5435 14:00:03.035255 Freq=933, CH0 RK1
5436 14:00:03.035316
5437 14:00:03.038342 DATLAT Default: 0xb
5438 14:00:03.038423 0, 0xFFFF, sum = 0
5439 14:00:03.041545 1, 0xFFFF, sum = 0
5440 14:00:03.041627 2, 0xFFFF, sum = 0
5441 14:00:03.045149 3, 0xFFFF, sum = 0
5442 14:00:03.045231 4, 0xFFFF, sum = 0
5443 14:00:03.048530 5, 0xFFFF, sum = 0
5444 14:00:03.048621 6, 0xFFFF, sum = 0
5445 14:00:03.051704 7, 0xFFFF, sum = 0
5446 14:00:03.055216 8, 0xFFFF, sum = 0
5447 14:00:03.055301 9, 0xFFFF, sum = 0
5448 14:00:03.055367 10, 0x0, sum = 1
5449 14:00:03.058335 11, 0x0, sum = 2
5450 14:00:03.058417 12, 0x0, sum = 3
5451 14:00:03.061862 13, 0x0, sum = 4
5452 14:00:03.061944 best_step = 11
5453 14:00:03.062008
5454 14:00:03.062066 ==
5455 14:00:03.064932 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 14:00:03.071541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 14:00:03.071628 ==
5458 14:00:03.071692 RX Vref Scan: 0
5459 14:00:03.071752
5460 14:00:03.074684 RX Vref 0 -> 0, step: 1
5461 14:00:03.074765
5462 14:00:03.078260 RX Delay -77 -> 252, step: 4
5463 14:00:03.081682 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5464 14:00:03.088009 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5465 14:00:03.091268 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5466 14:00:03.094771 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5467 14:00:03.097951 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5468 14:00:03.101492 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5469 14:00:03.104789 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5470 14:00:03.111275 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5471 14:00:03.114615 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5472 14:00:03.117843 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5473 14:00:03.121407 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5474 14:00:03.124669 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5475 14:00:03.130958 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5476 14:00:03.134567 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5477 14:00:03.137724 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5478 14:00:03.140864 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5479 14:00:03.140946 ==
5480 14:00:03.144429 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 14:00:03.150917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 14:00:03.151001 ==
5483 14:00:03.151066 DQS Delay:
5484 14:00:03.154161 DQS0 = 0, DQS1 = 0
5485 14:00:03.154242 DQM Delay:
5486 14:00:03.154306 DQM0 = 92, DQM1 = 84
5487 14:00:03.157643 DQ Delay:
5488 14:00:03.160663 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5489 14:00:03.164259 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5490 14:00:03.167258 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5491 14:00:03.170943 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5492 14:00:03.171026
5493 14:00:03.171090
5494 14:00:03.177211 [DQSOSCAuto] RK1, (LSB)MR18= 0x3214, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5495 14:00:03.180582 CH0 RK1: MR19=505, MR18=3214
5496 14:00:03.187311 CH0_RK1: MR19=0x505, MR18=0x3214, DQSOSC=406, MR23=63, INC=65, DEC=43
5497 14:00:03.190363 [RxdqsGatingPostProcess] freq 933
5498 14:00:03.193946 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5499 14:00:03.197154 best DQS0 dly(2T, 0.5T) = (0, 11)
5500 14:00:03.200415 best DQS1 dly(2T, 0.5T) = (0, 11)
5501 14:00:03.203608 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5502 14:00:03.207056 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5503 14:00:03.210237 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 14:00:03.213837 best DQS1 dly(2T, 0.5T) = (0, 10)
5505 14:00:03.216883 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 14:00:03.220424 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5507 14:00:03.223710 Pre-setting of DQS Precalculation
5508 14:00:03.226866 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5509 14:00:03.230506 ==
5510 14:00:03.233409 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 14:00:03.236657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 14:00:03.236740 ==
5513 14:00:03.239963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5514 14:00:03.246725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5515 14:00:03.250597 [CA 0] Center 37 (7~67) winsize 61
5516 14:00:03.253664 [CA 1] Center 37 (7~68) winsize 62
5517 14:00:03.257070 [CA 2] Center 34 (5~64) winsize 60
5518 14:00:03.260461 [CA 3] Center 34 (5~64) winsize 60
5519 14:00:03.263696 [CA 4] Center 35 (5~65) winsize 61
5520 14:00:03.267187 [CA 5] Center 34 (4~64) winsize 61
5521 14:00:03.267269
5522 14:00:03.270465 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5523 14:00:03.270547
5524 14:00:03.273652 [CATrainingPosCal] consider 1 rank data
5525 14:00:03.277101 u2DelayCellTimex100 = 270/100 ps
5526 14:00:03.280410 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5527 14:00:03.283557 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5528 14:00:03.290300 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5529 14:00:03.293426 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5530 14:00:03.297072 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5531 14:00:03.300315 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5532 14:00:03.300399
5533 14:00:03.303527 CA PerBit enable=1, Macro0, CA PI delay=34
5534 14:00:03.303609
5535 14:00:03.306867 [CBTSetCACLKResult] CA Dly = 34
5536 14:00:03.306952 CS Dly: 6 (0~37)
5537 14:00:03.310327 ==
5538 14:00:03.310410 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 14:00:03.316654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 14:00:03.316740 ==
5541 14:00:03.320282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 14:00:03.326771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5543 14:00:03.330308 [CA 0] Center 37 (8~67) winsize 60
5544 14:00:03.333868 [CA 1] Center 37 (7~68) winsize 62
5545 14:00:03.336901 [CA 2] Center 35 (5~65) winsize 61
5546 14:00:03.340261 [CA 3] Center 34 (4~65) winsize 62
5547 14:00:03.343748 [CA 4] Center 35 (5~65) winsize 61
5548 14:00:03.347052 [CA 5] Center 34 (3~65) winsize 63
5549 14:00:03.347133
5550 14:00:03.350202 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5551 14:00:03.350282
5552 14:00:03.353712 [CATrainingPosCal] consider 2 rank data
5553 14:00:03.356929 u2DelayCellTimex100 = 270/100 ps
5554 14:00:03.360221 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5555 14:00:03.367056 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5556 14:00:03.370296 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5557 14:00:03.373406 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5558 14:00:03.376497 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5559 14:00:03.380105 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5560 14:00:03.380187
5561 14:00:03.383366 CA PerBit enable=1, Macro0, CA PI delay=34
5562 14:00:03.383447
5563 14:00:03.386552 [CBTSetCACLKResult] CA Dly = 34
5564 14:00:03.386633 CS Dly: 6 (0~38)
5565 14:00:03.390019
5566 14:00:03.393315 ----->DramcWriteLeveling(PI) begin...
5567 14:00:03.393399 ==
5568 14:00:03.396618 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 14:00:03.399845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 14:00:03.399927 ==
5571 14:00:03.403191 Write leveling (Byte 0): 24 => 24
5572 14:00:03.406573 Write leveling (Byte 1): 27 => 27
5573 14:00:03.409986 DramcWriteLeveling(PI) end<-----
5574 14:00:03.410068
5575 14:00:03.410131 ==
5576 14:00:03.413024 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 14:00:03.416338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 14:00:03.416420 ==
5579 14:00:03.419868 [Gating] SW mode calibration
5580 14:00:03.426319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5581 14:00:03.433127 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5582 14:00:03.436345 0 14 0 | B1->B0 | 3131 3232 | 0 1 | (0 0) (1 1)
5583 14:00:03.439499 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 14:00:03.446063 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 14:00:03.449339 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 14:00:03.452995 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 14:00:03.459290 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 14:00:03.462839 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 14:00:03.466253 0 14 28 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 1)
5590 14:00:03.472685 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 14:00:03.475815 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 14:00:03.479324 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 14:00:03.485925 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 14:00:03.489105 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 14:00:03.492748 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 14:00:03.499200 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 14:00:03.502680 0 15 28 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
5598 14:00:03.505862 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 14:00:03.512600 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 14:00:03.515830 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 14:00:03.519069 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 14:00:03.525399 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 14:00:03.528947 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 14:00:03.532112 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 14:00:03.538586 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5606 14:00:03.541786 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5607 14:00:03.545262 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 14:00:03.551921 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 14:00:03.555397 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 14:00:03.558606 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 14:00:03.565302 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 14:00:03.568278 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 14:00:03.571918 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 14:00:03.578278 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 14:00:03.581828 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 14:00:03.584957 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 14:00:03.591406 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 14:00:03.594878 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 14:00:03.598266 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 14:00:03.601570 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5621 14:00:03.608007 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5622 14:00:03.611292 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 14:00:03.614810 Total UI for P1: 0, mck2ui 16
5624 14:00:03.618242 best dqsien dly found for B0: ( 1, 2, 26)
5625 14:00:03.621466 Total UI for P1: 0, mck2ui 16
5626 14:00:03.624666 best dqsien dly found for B1: ( 1, 2, 28)
5627 14:00:03.627912 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5628 14:00:03.631263 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5629 14:00:03.631345
5630 14:00:03.634893 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5631 14:00:03.641167 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5632 14:00:03.641250 [Gating] SW calibration Done
5633 14:00:03.641315 ==
5634 14:00:03.644537 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 14:00:03.651124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 14:00:03.651209 ==
5637 14:00:03.651275 RX Vref Scan: 0
5638 14:00:03.651335
5639 14:00:03.654567 RX Vref 0 -> 0, step: 1
5640 14:00:03.654648
5641 14:00:03.658104 RX Delay -80 -> 252, step: 8
5642 14:00:03.661423 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5643 14:00:03.664574 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5644 14:00:03.667747 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5645 14:00:03.671141 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5646 14:00:03.678040 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5647 14:00:03.681210 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5648 14:00:03.684703 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5649 14:00:03.687840 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5650 14:00:03.691047 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5651 14:00:03.697720 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5652 14:00:03.700842 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5653 14:00:03.704216 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5654 14:00:03.707383 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5655 14:00:03.710719 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5656 14:00:03.717752 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5657 14:00:03.720918 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5658 14:00:03.721002 ==
5659 14:00:03.724282 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 14:00:03.727330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 14:00:03.727413 ==
5662 14:00:03.727479 DQS Delay:
5663 14:00:03.730934 DQS0 = 0, DQS1 = 0
5664 14:00:03.731017 DQM Delay:
5665 14:00:03.734064 DQM0 = 94, DQM1 = 86
5666 14:00:03.734146 DQ Delay:
5667 14:00:03.737289 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5668 14:00:03.740870 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5669 14:00:03.743938 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5670 14:00:03.747345 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5671 14:00:03.747428
5672 14:00:03.747491
5673 14:00:03.747551 ==
5674 14:00:03.750498 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 14:00:03.757317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 14:00:03.757403 ==
5677 14:00:03.757467
5678 14:00:03.757572
5679 14:00:03.757631 TX Vref Scan disable
5680 14:00:03.760654 == TX Byte 0 ==
5681 14:00:03.763866 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5682 14:00:03.770533 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5683 14:00:03.770614 == TX Byte 1 ==
5684 14:00:03.773849 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5685 14:00:03.780146 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5686 14:00:03.780232 ==
5687 14:00:03.783819 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 14:00:03.786991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 14:00:03.787079 ==
5690 14:00:03.787164
5691 14:00:03.787244
5692 14:00:03.790190 TX Vref Scan disable
5693 14:00:03.790273 == TX Byte 0 ==
5694 14:00:03.796880 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5695 14:00:03.800113 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5696 14:00:03.800197 == TX Byte 1 ==
5697 14:00:03.806714 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5698 14:00:03.810191 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5699 14:00:03.810275
5700 14:00:03.810359 [DATLAT]
5701 14:00:03.813594 Freq=933, CH1 RK0
5702 14:00:03.813678
5703 14:00:03.813763 DATLAT Default: 0xd
5704 14:00:03.816715 0, 0xFFFF, sum = 0
5705 14:00:03.816799 1, 0xFFFF, sum = 0
5706 14:00:03.820246 2, 0xFFFF, sum = 0
5707 14:00:03.823276 3, 0xFFFF, sum = 0
5708 14:00:03.823360 4, 0xFFFF, sum = 0
5709 14:00:03.826841 5, 0xFFFF, sum = 0
5710 14:00:03.826926 6, 0xFFFF, sum = 0
5711 14:00:03.829887 7, 0xFFFF, sum = 0
5712 14:00:03.829972 8, 0xFFFF, sum = 0
5713 14:00:03.833371 9, 0xFFFF, sum = 0
5714 14:00:03.833455 10, 0x0, sum = 1
5715 14:00:03.836520 11, 0x0, sum = 2
5716 14:00:03.836604 12, 0x0, sum = 3
5717 14:00:03.839704 13, 0x0, sum = 4
5718 14:00:03.839788 best_step = 11
5719 14:00:03.839872
5720 14:00:03.839951 ==
5721 14:00:03.843236 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 14:00:03.846432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 14:00:03.846516 ==
5724 14:00:03.849709 RX Vref Scan: 1
5725 14:00:03.849819
5726 14:00:03.853218 RX Vref 0 -> 0, step: 1
5727 14:00:03.853316
5728 14:00:03.853398 RX Delay -61 -> 252, step: 4
5729 14:00:03.853501
5730 14:00:03.856234 Set Vref, RX VrefLevel [Byte0]: 60
5731 14:00:03.859879 [Byte1]: 54
5732 14:00:03.864546
5733 14:00:03.864629 Final RX Vref Byte 0 = 60 to rank0
5734 14:00:03.867935 Final RX Vref Byte 1 = 54 to rank0
5735 14:00:03.871121 Final RX Vref Byte 0 = 60 to rank1
5736 14:00:03.874417 Final RX Vref Byte 1 = 54 to rank1==
5737 14:00:03.877738 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 14:00:03.884158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 14:00:03.884257 ==
5740 14:00:03.884340 DQS Delay:
5741 14:00:03.887866 DQS0 = 0, DQS1 = 0
5742 14:00:03.887949 DQM Delay:
5743 14:00:03.888033 DQM0 = 96, DQM1 = 89
5744 14:00:03.890855 DQ Delay:
5745 14:00:03.894034 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =92
5746 14:00:03.897389 DQ4 =94, DQ5 =104, DQ6 =104, DQ7 =94
5747 14:00:03.900854 DQ8 =76, DQ9 =82, DQ10 =88, DQ11 =82
5748 14:00:03.904032 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5749 14:00:03.904113
5750 14:00:03.904178
5751 14:00:03.910740 [DQSOSCAuto] RK0, (LSB)MR18= 0x8, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5752 14:00:03.913914 CH1 RK0: MR19=505, MR18=8
5753 14:00:03.920666 CH1_RK0: MR19=0x505, MR18=0x8, DQSOSC=419, MR23=63, INC=61, DEC=41
5754 14:00:03.920759
5755 14:00:03.924111 ----->DramcWriteLeveling(PI) begin...
5756 14:00:03.924194 ==
5757 14:00:03.927224 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 14:00:03.930524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 14:00:03.930607 ==
5760 14:00:03.933850 Write leveling (Byte 0): 25 => 25
5761 14:00:03.937109 Write leveling (Byte 1): 26 => 26
5762 14:00:03.940649 DramcWriteLeveling(PI) end<-----
5763 14:00:03.940730
5764 14:00:03.940794 ==
5765 14:00:03.943861 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 14:00:03.947079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 14:00:03.947162 ==
5768 14:00:03.950632 [Gating] SW mode calibration
5769 14:00:03.956979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5770 14:00:03.963674 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5771 14:00:03.966830 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5772 14:00:03.970283 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 14:00:03.977125 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 14:00:03.980264 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 14:00:03.983412 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 14:00:03.990050 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5777 14:00:03.993343 0 14 24 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 1)
5778 14:00:03.996802 0 14 28 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
5779 14:00:04.003364 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 14:00:04.006624 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 14:00:04.010170 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 14:00:04.016811 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 14:00:04.019800 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 14:00:04.023338 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 14:00:04.029919 0 15 24 | B1->B0 | 2828 3636 | 0 1 | (0 0) (0 0)
5786 14:00:04.033204 0 15 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5787 14:00:04.036664 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 14:00:04.043225 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 14:00:04.046740 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 14:00:04.049635 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 14:00:04.056294 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 14:00:04.059666 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 14:00:04.063212 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5794 14:00:04.069610 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5795 14:00:04.073179 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 14:00:04.076181 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 14:00:04.083093 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 14:00:04.086259 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 14:00:04.089499 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 14:00:04.096334 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 14:00:04.099460 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 14:00:04.102640 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 14:00:04.109442 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 14:00:04.112580 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 14:00:04.115935 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 14:00:04.122868 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 14:00:04.125966 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 14:00:04.129436 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 14:00:04.136191 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5810 14:00:04.139126 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5811 14:00:04.142572 Total UI for P1: 0, mck2ui 16
5812 14:00:04.145709 best dqsien dly found for B0: ( 1, 2, 24)
5813 14:00:04.149167 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 14:00:04.152504 Total UI for P1: 0, mck2ui 16
5815 14:00:04.155644 best dqsien dly found for B1: ( 1, 2, 28)
5816 14:00:04.159120 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5817 14:00:04.162380 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5818 14:00:04.162465
5819 14:00:04.165687 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5820 14:00:04.172388 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5821 14:00:04.172472 [Gating] SW calibration Done
5822 14:00:04.172538 ==
5823 14:00:04.175460 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 14:00:04.182321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 14:00:04.182407 ==
5826 14:00:04.182473 RX Vref Scan: 0
5827 14:00:04.182534
5828 14:00:04.185486 RX Vref 0 -> 0, step: 1
5829 14:00:04.185582
5830 14:00:04.188774 RX Delay -80 -> 252, step: 8
5831 14:00:04.192226 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5832 14:00:04.195426 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5833 14:00:04.198890 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5834 14:00:04.205509 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5835 14:00:04.209015 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5836 14:00:04.212157 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5837 14:00:04.216029 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5838 14:00:04.218852 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5839 14:00:04.222138 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5840 14:00:04.228775 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5841 14:00:04.231918 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5842 14:00:04.235317 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5843 14:00:04.238514 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5844 14:00:04.242002 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5845 14:00:04.248422 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5846 14:00:04.251550 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5847 14:00:04.251633 ==
5848 14:00:04.254966 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 14:00:04.258465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 14:00:04.258547 ==
5851 14:00:04.261754 DQS Delay:
5852 14:00:04.261835 DQS0 = 0, DQS1 = 0
5853 14:00:04.261899 DQM Delay:
5854 14:00:04.264892 DQM0 = 93, DQM1 = 88
5855 14:00:04.264973 DQ Delay:
5856 14:00:04.268463 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5857 14:00:04.271636 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5858 14:00:04.274959 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5859 14:00:04.278462 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =95
5860 14:00:04.278545
5861 14:00:04.278610
5862 14:00:04.278669 ==
5863 14:00:04.281646 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 14:00:04.288098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 14:00:04.288233 ==
5866 14:00:04.288333
5867 14:00:04.288439
5868 14:00:04.288512 TX Vref Scan disable
5869 14:00:04.291638 == TX Byte 0 ==
5870 14:00:04.295199 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5871 14:00:04.301731 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5872 14:00:04.301812 == TX Byte 1 ==
5873 14:00:04.305111 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5874 14:00:04.311408 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5875 14:00:04.311492 ==
5876 14:00:04.315101 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 14:00:04.318298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 14:00:04.318381 ==
5879 14:00:04.318445
5880 14:00:04.318505
5881 14:00:04.321392 TX Vref Scan disable
5882 14:00:04.321480 == TX Byte 0 ==
5883 14:00:04.327938 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5884 14:00:04.331311 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5885 14:00:04.334648 == TX Byte 1 ==
5886 14:00:04.338050 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5887 14:00:04.341153 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5888 14:00:04.341235
5889 14:00:04.341299 [DATLAT]
5890 14:00:04.344653 Freq=933, CH1 RK1
5891 14:00:04.344764
5892 14:00:04.344859 DATLAT Default: 0xb
5893 14:00:04.347829 0, 0xFFFF, sum = 0
5894 14:00:04.350973 1, 0xFFFF, sum = 0
5895 14:00:04.351057 2, 0xFFFF, sum = 0
5896 14:00:04.354251 3, 0xFFFF, sum = 0
5897 14:00:04.354336 4, 0xFFFF, sum = 0
5898 14:00:04.357592 5, 0xFFFF, sum = 0
5899 14:00:04.357677 6, 0xFFFF, sum = 0
5900 14:00:04.360859 7, 0xFFFF, sum = 0
5901 14:00:04.360943 8, 0xFFFF, sum = 0
5902 14:00:04.364315 9, 0xFFFF, sum = 0
5903 14:00:04.364399 10, 0x0, sum = 1
5904 14:00:04.367526 11, 0x0, sum = 2
5905 14:00:04.367610 12, 0x0, sum = 3
5906 14:00:04.370619 13, 0x0, sum = 4
5907 14:00:04.370704 best_step = 11
5908 14:00:04.370787
5909 14:00:04.370865 ==
5910 14:00:04.374151 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 14:00:04.377663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 14:00:04.380669 ==
5913 14:00:04.380777 RX Vref Scan: 0
5914 14:00:04.380862
5915 14:00:04.384180 RX Vref 0 -> 0, step: 1
5916 14:00:04.384262
5917 14:00:04.384347 RX Delay -69 -> 252, step: 4
5918 14:00:04.392237 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5919 14:00:04.395349 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5920 14:00:04.398890 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5921 14:00:04.402189 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5922 14:00:04.405656 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5923 14:00:04.412279 iDelay=203, Bit 5, Center 102 (3 ~ 202) 200
5924 14:00:04.415455 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5925 14:00:04.418602 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5926 14:00:04.422115 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5927 14:00:04.425341 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5928 14:00:04.428573 iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196
5929 14:00:04.435287 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5930 14:00:04.438810 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5931 14:00:04.441915 iDelay=203, Bit 13, Center 98 (3 ~ 194) 192
5932 14:00:04.445243 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5933 14:00:04.448729 iDelay=203, Bit 15, Center 98 (3 ~ 194) 192
5934 14:00:04.448813 ==
5935 14:00:04.451859 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 14:00:04.458381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 14:00:04.458462 ==
5938 14:00:04.458526 DQS Delay:
5939 14:00:04.461927 DQS0 = 0, DQS1 = 0
5940 14:00:04.462007 DQM Delay:
5941 14:00:04.462069 DQM0 = 92, DQM1 = 91
5942 14:00:04.464948 DQ Delay:
5943 14:00:04.468560 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =90
5944 14:00:04.471830 DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88
5945 14:00:04.475055 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5946 14:00:04.478381 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =98
5947 14:00:04.478462
5948 14:00:04.478525
5949 14:00:04.485060 [DQSOSCAuto] RK1, (LSB)MR18= 0x1125, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5950 14:00:04.488268 CH1 RK1: MR19=505, MR18=1125
5951 14:00:04.494630 CH1_RK1: MR19=0x505, MR18=0x1125, DQSOSC=410, MR23=63, INC=64, DEC=42
5952 14:00:04.497922 [RxdqsGatingPostProcess] freq 933
5953 14:00:04.504552 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5954 14:00:04.504637 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 14:00:04.507991 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 14:00:04.511106 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 14:00:04.514545 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 14:00:04.518001 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 14:00:04.521261 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 14:00:04.524743 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 14:00:04.527824 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 14:00:04.531051 Pre-setting of DQS Precalculation
5963 14:00:04.537658 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5964 14:00:04.544564 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5965 14:00:04.551284 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5966 14:00:04.551368
5967 14:00:04.551454
5968 14:00:04.554580 [Calibration Summary] 1866 Mbps
5969 14:00:04.554664 CH 0, Rank 0
5970 14:00:04.557826 SW Impedance : PASS
5971 14:00:04.560860 DUTY Scan : NO K
5972 14:00:04.560943 ZQ Calibration : PASS
5973 14:00:04.564196 Jitter Meter : NO K
5974 14:00:04.564280 CBT Training : PASS
5975 14:00:04.567643 Write leveling : PASS
5976 14:00:04.570862 RX DQS gating : PASS
5977 14:00:04.570945 RX DQ/DQS(RDDQC) : PASS
5978 14:00:04.574376 TX DQ/DQS : PASS
5979 14:00:04.577730 RX DATLAT : PASS
5980 14:00:04.577816 RX DQ/DQS(Engine): PASS
5981 14:00:04.580729 TX OE : NO K
5982 14:00:04.580812 All Pass.
5983 14:00:04.580896
5984 14:00:04.584157 CH 0, Rank 1
5985 14:00:04.584239 SW Impedance : PASS
5986 14:00:04.587418 DUTY Scan : NO K
5987 14:00:04.590660 ZQ Calibration : PASS
5988 14:00:04.590743 Jitter Meter : NO K
5989 14:00:04.593859 CBT Training : PASS
5990 14:00:04.597362 Write leveling : PASS
5991 14:00:04.597471 RX DQS gating : PASS
5992 14:00:04.600499 RX DQ/DQS(RDDQC) : PASS
5993 14:00:04.603951 TX DQ/DQS : PASS
5994 14:00:04.604031 RX DATLAT : PASS
5995 14:00:04.607488 RX DQ/DQS(Engine): PASS
5996 14:00:04.610666 TX OE : NO K
5997 14:00:04.610748 All Pass.
5998 14:00:04.610811
5999 14:00:04.610870 CH 1, Rank 0
6000 14:00:04.613858 SW Impedance : PASS
6001 14:00:04.617175 DUTY Scan : NO K
6002 14:00:04.617255 ZQ Calibration : PASS
6003 14:00:04.620369 Jitter Meter : NO K
6004 14:00:04.623838 CBT Training : PASS
6005 14:00:04.623936 Write leveling : PASS
6006 14:00:04.627086 RX DQS gating : PASS
6007 14:00:04.627170 RX DQ/DQS(RDDQC) : PASS
6008 14:00:04.630359 TX DQ/DQS : PASS
6009 14:00:04.633809 RX DATLAT : PASS
6010 14:00:04.633889 RX DQ/DQS(Engine): PASS
6011 14:00:04.637274 TX OE : NO K
6012 14:00:04.637353 All Pass.
6013 14:00:04.637416
6014 14:00:04.640398 CH 1, Rank 1
6015 14:00:04.640478 SW Impedance : PASS
6016 14:00:04.643808 DUTY Scan : NO K
6017 14:00:04.646884 ZQ Calibration : PASS
6018 14:00:04.646968 Jitter Meter : NO K
6019 14:00:04.650399 CBT Training : PASS
6020 14:00:04.653628 Write leveling : PASS
6021 14:00:04.653711 RX DQS gating : PASS
6022 14:00:04.656917 RX DQ/DQS(RDDQC) : PASS
6023 14:00:04.660045 TX DQ/DQS : PASS
6024 14:00:04.660129 RX DATLAT : PASS
6025 14:00:04.663299 RX DQ/DQS(Engine): PASS
6026 14:00:04.666846 TX OE : NO K
6027 14:00:04.666930 All Pass.
6028 14:00:04.667015
6029 14:00:04.667095 DramC Write-DBI off
6030 14:00:04.670209 PER_BANK_REFRESH: Hybrid Mode
6031 14:00:04.673709 TX_TRACKING: ON
6032 14:00:04.679953 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6033 14:00:04.683315 [FAST_K] Save calibration result to emmc
6034 14:00:04.690122 dramc_set_vcore_voltage set vcore to 650000
6035 14:00:04.690233 Read voltage for 400, 6
6036 14:00:04.693329 Vio18 = 0
6037 14:00:04.693409 Vcore = 650000
6038 14:00:04.693472 Vdram = 0
6039 14:00:04.696965 Vddq = 0
6040 14:00:04.697045 Vmddr = 0
6041 14:00:04.700050 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6042 14:00:04.706547 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6043 14:00:04.710074 MEM_TYPE=3, freq_sel=20
6044 14:00:04.710158 sv_algorithm_assistance_LP4_800
6045 14:00:04.716474 ============ PULL DRAM RESETB DOWN ============
6046 14:00:04.720063 ========== PULL DRAM RESETB DOWN end =========
6047 14:00:04.723071 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6048 14:00:04.726568 ===================================
6049 14:00:04.729969 LPDDR4 DRAM CONFIGURATION
6050 14:00:04.732995 ===================================
6051 14:00:04.736557 EX_ROW_EN[0] = 0x0
6052 14:00:04.736637 EX_ROW_EN[1] = 0x0
6053 14:00:04.739854 LP4Y_EN = 0x0
6054 14:00:04.739938 WORK_FSP = 0x0
6055 14:00:04.743165 WL = 0x2
6056 14:00:04.743246 RL = 0x2
6057 14:00:04.746436 BL = 0x2
6058 14:00:04.746517 RPST = 0x0
6059 14:00:04.749649 RD_PRE = 0x0
6060 14:00:04.749730 WR_PRE = 0x1
6061 14:00:04.752864 WR_PST = 0x0
6062 14:00:04.756483 DBI_WR = 0x0
6063 14:00:04.756564 DBI_RD = 0x0
6064 14:00:04.759711 OTF = 0x1
6065 14:00:04.763025 ===================================
6066 14:00:04.766194 ===================================
6067 14:00:04.766275 ANA top config
6068 14:00:04.769332 ===================================
6069 14:00:04.772677 DLL_ASYNC_EN = 0
6070 14:00:04.775925 ALL_SLAVE_EN = 1
6071 14:00:04.776006 NEW_RANK_MODE = 1
6072 14:00:04.779351 DLL_IDLE_MODE = 1
6073 14:00:04.782629 LP45_APHY_COMB_EN = 1
6074 14:00:04.786135 TX_ODT_DIS = 1
6075 14:00:04.786216 NEW_8X_MODE = 1
6076 14:00:04.789252 ===================================
6077 14:00:04.792824 ===================================
6078 14:00:04.796145 data_rate = 800
6079 14:00:04.799253 CKR = 1
6080 14:00:04.802433 DQ_P2S_RATIO = 4
6081 14:00:04.805998 ===================================
6082 14:00:04.809408 CA_P2S_RATIO = 4
6083 14:00:04.812456 DQ_CA_OPEN = 0
6084 14:00:04.812537 DQ_SEMI_OPEN = 1
6085 14:00:04.815743 CA_SEMI_OPEN = 1
6086 14:00:04.819180 CA_FULL_RATE = 0
6087 14:00:04.822656 DQ_CKDIV4_EN = 0
6088 14:00:04.825876 CA_CKDIV4_EN = 1
6089 14:00:04.829051 CA_PREDIV_EN = 0
6090 14:00:04.829132 PH8_DLY = 0
6091 14:00:04.832562 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6092 14:00:04.835701 DQ_AAMCK_DIV = 0
6093 14:00:04.839184 CA_AAMCK_DIV = 0
6094 14:00:04.842395 CA_ADMCK_DIV = 4
6095 14:00:04.845603 DQ_TRACK_CA_EN = 0
6096 14:00:04.845683 CA_PICK = 800
6097 14:00:04.848906 CA_MCKIO = 400
6098 14:00:04.852154 MCKIO_SEMI = 400
6099 14:00:04.855577 PLL_FREQ = 3016
6100 14:00:04.858711 DQ_UI_PI_RATIO = 32
6101 14:00:04.862297 CA_UI_PI_RATIO = 32
6102 14:00:04.865549 ===================================
6103 14:00:04.868547 ===================================
6104 14:00:04.871998 memory_type:LPDDR4
6105 14:00:04.872079 GP_NUM : 10
6106 14:00:04.875271 SRAM_EN : 1
6107 14:00:04.875351 MD32_EN : 0
6108 14:00:04.878667 ===================================
6109 14:00:04.881723 [ANA_INIT] >>>>>>>>>>>>>>
6110 14:00:04.885060 <<<<<< [CONFIGURE PHASE]: ANA_TX
6111 14:00:04.888530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6112 14:00:04.891662 ===================================
6113 14:00:04.895183 data_rate = 800,PCW = 0X7400
6114 14:00:04.898541 ===================================
6115 14:00:04.901768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6116 14:00:04.908263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6117 14:00:04.918416 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 14:00:04.922024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6119 14:00:04.925261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6120 14:00:04.928379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6121 14:00:04.931960 [ANA_INIT] flow start
6122 14:00:04.935281 [ANA_INIT] PLL >>>>>>>>
6123 14:00:04.935362 [ANA_INIT] PLL <<<<<<<<
6124 14:00:04.938408 [ANA_INIT] MIDPI >>>>>>>>
6125 14:00:04.941734 [ANA_INIT] MIDPI <<<<<<<<
6126 14:00:04.944884 [ANA_INIT] DLL >>>>>>>>
6127 14:00:04.944965 [ANA_INIT] flow end
6128 14:00:04.948443 ============ LP4 DIFF to SE enter ============
6129 14:00:04.954856 ============ LP4 DIFF to SE exit ============
6130 14:00:04.954938 [ANA_INIT] <<<<<<<<<<<<<
6131 14:00:04.958020 [Flow] Enable top DCM control >>>>>
6132 14:00:04.961472 [Flow] Enable top DCM control <<<<<
6133 14:00:04.964718 Enable DLL master slave shuffle
6134 14:00:04.971363 ==============================================================
6135 14:00:04.971448 Gating Mode config
6136 14:00:04.978008 ==============================================================
6137 14:00:04.981179 Config description:
6138 14:00:04.991008 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6139 14:00:04.997953 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6140 14:00:05.001155 SELPH_MODE 0: By rank 1: By Phase
6141 14:00:05.007903 ==============================================================
6142 14:00:05.011308 GAT_TRACK_EN = 0
6143 14:00:05.014379 RX_GATING_MODE = 2
6144 14:00:05.014463 RX_GATING_TRACK_MODE = 2
6145 14:00:05.017932 SELPH_MODE = 1
6146 14:00:05.021269 PICG_EARLY_EN = 1
6147 14:00:05.024377 VALID_LAT_VALUE = 1
6148 14:00:05.031068 ==============================================================
6149 14:00:05.034676 Enter into Gating configuration >>>>
6150 14:00:05.037919 Exit from Gating configuration <<<<
6151 14:00:05.041020 Enter into DVFS_PRE_config >>>>>
6152 14:00:05.050939 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6153 14:00:05.054392 Exit from DVFS_PRE_config <<<<<
6154 14:00:05.057807 Enter into PICG configuration >>>>
6155 14:00:05.060970 Exit from PICG configuration <<<<
6156 14:00:05.064171 [RX_INPUT] configuration >>>>>
6157 14:00:05.067342 [RX_INPUT] configuration <<<<<
6158 14:00:05.070867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6159 14:00:05.077357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6160 14:00:05.083998 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 14:00:05.090736 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 14:00:05.094073 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 14:00:05.100646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 14:00:05.104120 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6165 14:00:05.110862 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6166 14:00:05.113971 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6167 14:00:05.117356 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6168 14:00:05.120767 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6169 14:00:05.127302 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 14:00:05.130515 ===================================
6171 14:00:05.133985 LPDDR4 DRAM CONFIGURATION
6172 14:00:05.137060 ===================================
6173 14:00:05.137141 EX_ROW_EN[0] = 0x0
6174 14:00:05.140575 EX_ROW_EN[1] = 0x0
6175 14:00:05.140656 LP4Y_EN = 0x0
6176 14:00:05.143755 WORK_FSP = 0x0
6177 14:00:05.143835 WL = 0x2
6178 14:00:05.147214 RL = 0x2
6179 14:00:05.147293 BL = 0x2
6180 14:00:05.150481 RPST = 0x0
6181 14:00:05.150561 RD_PRE = 0x0
6182 14:00:05.153690 WR_PRE = 0x1
6183 14:00:05.153769 WR_PST = 0x0
6184 14:00:05.157022 DBI_WR = 0x0
6185 14:00:05.157102 DBI_RD = 0x0
6186 14:00:05.160391 OTF = 0x1
6187 14:00:05.163484 ===================================
6188 14:00:05.167068 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6189 14:00:05.170174 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6190 14:00:05.176972 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 14:00:05.180259 ===================================
6192 14:00:05.180341 LPDDR4 DRAM CONFIGURATION
6193 14:00:05.183354 ===================================
6194 14:00:05.186746 EX_ROW_EN[0] = 0x10
6195 14:00:05.190114 EX_ROW_EN[1] = 0x0
6196 14:00:05.190195 LP4Y_EN = 0x0
6197 14:00:05.193688 WORK_FSP = 0x0
6198 14:00:05.193768 WL = 0x2
6199 14:00:05.196770 RL = 0x2
6200 14:00:05.196853 BL = 0x2
6201 14:00:05.200093 RPST = 0x0
6202 14:00:05.200177 RD_PRE = 0x0
6203 14:00:05.203512 WR_PRE = 0x1
6204 14:00:05.203595 WR_PST = 0x0
6205 14:00:05.206590 DBI_WR = 0x0
6206 14:00:05.206688 DBI_RD = 0x0
6207 14:00:05.209918 OTF = 0x1
6208 14:00:05.213274 ===================================
6209 14:00:05.220028 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6210 14:00:05.223191 nWR fixed to 30
6211 14:00:05.226507 [ModeRegInit_LP4] CH0 RK0
6212 14:00:05.226599 [ModeRegInit_LP4] CH0 RK1
6213 14:00:05.229903 [ModeRegInit_LP4] CH1 RK0
6214 14:00:05.232938 [ModeRegInit_LP4] CH1 RK1
6215 14:00:05.233021 match AC timing 19
6216 14:00:05.239636 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6217 14:00:05.242844 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6218 14:00:05.246315 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6219 14:00:05.252840 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6220 14:00:05.256321 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6221 14:00:05.256402 ==
6222 14:00:05.259436 Dram Type= 6, Freq= 0, CH_0, rank 0
6223 14:00:05.262850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 14:00:05.262931 ==
6225 14:00:05.269413 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 14:00:05.276217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6227 14:00:05.279421 [CA 0] Center 36 (8~64) winsize 57
6228 14:00:05.282951 [CA 1] Center 36 (8~64) winsize 57
6229 14:00:05.286052 [CA 2] Center 36 (8~64) winsize 57
6230 14:00:05.286133 [CA 3] Center 36 (8~64) winsize 57
6231 14:00:05.289409 [CA 4] Center 36 (8~64) winsize 57
6232 14:00:05.292658 [CA 5] Center 36 (8~64) winsize 57
6233 14:00:05.292739
6234 14:00:05.299533 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6235 14:00:05.299620
6236 14:00:05.302611 [CATrainingPosCal] consider 1 rank data
6237 14:00:05.305980 u2DelayCellTimex100 = 270/100 ps
6238 14:00:05.309300 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 14:00:05.312483 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 14:00:05.316071 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 14:00:05.319050 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 14:00:05.322587 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 14:00:05.325642 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 14:00:05.325726
6245 14:00:05.329046 CA PerBit enable=1, Macro0, CA PI delay=36
6246 14:00:05.329131
6247 14:00:05.332384 [CBTSetCACLKResult] CA Dly = 36
6248 14:00:05.335703 CS Dly: 1 (0~32)
6249 14:00:05.335789 ==
6250 14:00:05.338919 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 14:00:05.342168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 14:00:05.342251 ==
6253 14:00:05.348783 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6254 14:00:05.355660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6255 14:00:05.355751 [CA 0] Center 36 (8~64) winsize 57
6256 14:00:05.358918 [CA 1] Center 36 (8~64) winsize 57
6257 14:00:05.362259 [CA 2] Center 36 (8~64) winsize 57
6258 14:00:05.365514 [CA 3] Center 36 (8~64) winsize 57
6259 14:00:05.368825 [CA 4] Center 36 (8~64) winsize 57
6260 14:00:05.372077 [CA 5] Center 36 (8~64) winsize 57
6261 14:00:05.372161
6262 14:00:05.375622 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6263 14:00:05.375707
6264 14:00:05.378895 [CATrainingPosCal] consider 2 rank data
6265 14:00:05.382090 u2DelayCellTimex100 = 270/100 ps
6266 14:00:05.385428 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 14:00:05.391816 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 14:00:05.395255 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 14:00:05.398438 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 14:00:05.401876 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 14:00:05.405082 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 14:00:05.405165
6273 14:00:05.408465 CA PerBit enable=1, Macro0, CA PI delay=36
6274 14:00:05.408580
6275 14:00:05.411826 [CBTSetCACLKResult] CA Dly = 36
6276 14:00:05.411908 CS Dly: 1 (0~32)
6277 14:00:05.415011
6278 14:00:05.418508 ----->DramcWriteLeveling(PI) begin...
6279 14:00:05.418591 ==
6280 14:00:05.421511 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 14:00:05.424959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 14:00:05.425041 ==
6283 14:00:05.428144 Write leveling (Byte 0): 40 => 8
6284 14:00:05.431561 Write leveling (Byte 1): 40 => 8
6285 14:00:05.434957 DramcWriteLeveling(PI) end<-----
6286 14:00:05.435051
6287 14:00:05.435156 ==
6288 14:00:05.438098 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 14:00:05.441611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 14:00:05.441691 ==
6291 14:00:05.444615 [Gating] SW mode calibration
6292 14:00:05.451196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6293 14:00:05.457926 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6294 14:00:05.461276 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6295 14:00:05.464611 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 14:00:05.471257 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 14:00:05.474679 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 14:00:05.477900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 14:00:05.484358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 14:00:05.487607 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 14:00:05.491049 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 14:00:05.497879 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 14:00:05.497961 Total UI for P1: 0, mck2ui 16
6304 14:00:05.504383 best dqsien dly found for B0: ( 0, 14, 24)
6305 14:00:05.504463 Total UI for P1: 0, mck2ui 16
6306 14:00:05.510911 best dqsien dly found for B1: ( 0, 14, 24)
6307 14:00:05.514324 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6308 14:00:05.517638 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6309 14:00:05.517717
6310 14:00:05.520908 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6311 14:00:05.524354 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 14:00:05.527454 [Gating] SW calibration Done
6313 14:00:05.527533 ==
6314 14:00:05.530836 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 14:00:05.533941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 14:00:05.534022 ==
6317 14:00:05.537320 RX Vref Scan: 0
6318 14:00:05.537424
6319 14:00:05.537553 RX Vref 0 -> 0, step: 1
6320 14:00:05.537613
6321 14:00:05.540866 RX Delay -410 -> 252, step: 16
6322 14:00:05.547528 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6323 14:00:05.550948 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6324 14:00:05.553933 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6325 14:00:05.557361 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6326 14:00:05.563909 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6327 14:00:05.567456 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6328 14:00:05.570463 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6329 14:00:05.573673 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6330 14:00:05.580286 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6331 14:00:05.583839 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6332 14:00:05.587052 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6333 14:00:05.590238 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6334 14:00:05.596862 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6335 14:00:05.600024 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6336 14:00:05.603597 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6337 14:00:05.610086 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6338 14:00:05.610173 ==
6339 14:00:05.613274 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 14:00:05.616859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 14:00:05.616940 ==
6342 14:00:05.617003 DQS Delay:
6343 14:00:05.619971 DQS0 = 59, DQS1 = 59
6344 14:00:05.620050 DQM Delay:
6345 14:00:05.623164 DQM0 = 18, DQM1 = 10
6346 14:00:05.623244 DQ Delay:
6347 14:00:05.626372 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6348 14:00:05.629932 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6349 14:00:05.633066 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6350 14:00:05.636510 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6351 14:00:05.636590
6352 14:00:05.636653
6353 14:00:05.636711 ==
6354 14:00:05.639688 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 14:00:05.642941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 14:00:05.643022 ==
6357 14:00:05.643086
6358 14:00:05.643145
6359 14:00:05.646351 TX Vref Scan disable
6360 14:00:05.649516 == TX Byte 0 ==
6361 14:00:05.653025 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 14:00:05.656326 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 14:00:05.659702 == TX Byte 1 ==
6364 14:00:05.663000 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 14:00:05.666264 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 14:00:05.666355 ==
6367 14:00:05.669560 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 14:00:05.672978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 14:00:05.673063 ==
6370 14:00:05.673194
6371 14:00:05.675996
6372 14:00:05.676075 TX Vref Scan disable
6373 14:00:05.679445 == TX Byte 0 ==
6374 14:00:05.682894 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 14:00:05.686201 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 14:00:05.689408 == TX Byte 1 ==
6377 14:00:05.692628 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 14:00:05.696157 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 14:00:05.696237
6380 14:00:05.696301 [DATLAT]
6381 14:00:05.699232 Freq=400, CH0 RK0
6382 14:00:05.699327
6383 14:00:05.699391 DATLAT Default: 0xf
6384 14:00:05.702907 0, 0xFFFF, sum = 0
6385 14:00:05.702989 1, 0xFFFF, sum = 0
6386 14:00:05.706089 2, 0xFFFF, sum = 0
6387 14:00:05.709225 3, 0xFFFF, sum = 0
6388 14:00:05.709318 4, 0xFFFF, sum = 0
6389 14:00:05.712760 5, 0xFFFF, sum = 0
6390 14:00:05.712843 6, 0xFFFF, sum = 0
6391 14:00:05.716291 7, 0xFFFF, sum = 0
6392 14:00:05.716373 8, 0xFFFF, sum = 0
6393 14:00:05.719270 9, 0xFFFF, sum = 0
6394 14:00:05.719352 10, 0xFFFF, sum = 0
6395 14:00:05.722499 11, 0xFFFF, sum = 0
6396 14:00:05.722580 12, 0xFFFF, sum = 0
6397 14:00:05.726096 13, 0x0, sum = 1
6398 14:00:05.726177 14, 0x0, sum = 2
6399 14:00:05.729190 15, 0x0, sum = 3
6400 14:00:05.729271 16, 0x0, sum = 4
6401 14:00:05.732719 best_step = 14
6402 14:00:05.732800
6403 14:00:05.732862 ==
6404 14:00:05.736096 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 14:00:05.739143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 14:00:05.739224 ==
6407 14:00:05.739288 RX Vref Scan: 1
6408 14:00:05.742559
6409 14:00:05.742639 RX Vref 0 -> 0, step: 1
6410 14:00:05.742702
6411 14:00:05.746043 RX Delay -359 -> 252, step: 8
6412 14:00:05.746122
6413 14:00:05.749140 Set Vref, RX VrefLevel [Byte0]: 60
6414 14:00:05.752167 [Byte1]: 48
6415 14:00:05.756859
6416 14:00:05.756941 Final RX Vref Byte 0 = 60 to rank0
6417 14:00:05.759923 Final RX Vref Byte 1 = 48 to rank0
6418 14:00:05.763070 Final RX Vref Byte 0 = 60 to rank1
6419 14:00:05.766404 Final RX Vref Byte 1 = 48 to rank1==
6420 14:00:05.769912 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 14:00:05.776656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 14:00:05.776750 ==
6423 14:00:05.776816 DQS Delay:
6424 14:00:05.780047 DQS0 = 60, DQS1 = 68
6425 14:00:05.780128 DQM Delay:
6426 14:00:05.780190 DQM0 = 14, DQM1 = 13
6427 14:00:05.783387 DQ Delay:
6428 14:00:05.786600 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6429 14:00:05.786688 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6430 14:00:05.789795 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6431 14:00:05.793020 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6432 14:00:05.793100
6433 14:00:05.796410
6434 14:00:05.803052 [DQSOSCAuto] RK0, (LSB)MR18= 0x807e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6435 14:00:05.806355 CH0 RK0: MR19=C0C, MR18=807E
6436 14:00:05.813034 CH0_RK0: MR19=0xC0C, MR18=0x807E, DQSOSC=393, MR23=63, INC=382, DEC=254
6437 14:00:05.813119 ==
6438 14:00:05.816186 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 14:00:05.819544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 14:00:05.819628 ==
6441 14:00:05.822955 [Gating] SW mode calibration
6442 14:00:05.829662 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6443 14:00:05.836286 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6444 14:00:05.839511 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 14:00:05.843107 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 14:00:05.849466 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 14:00:05.852518 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 14:00:05.855750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 14:00:05.862627 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 14:00:05.865739 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 14:00:05.868804 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 14:00:05.875564 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 14:00:05.875681 Total UI for P1: 0, mck2ui 16
6454 14:00:05.882359 best dqsien dly found for B0: ( 0, 14, 24)
6455 14:00:05.882486 Total UI for P1: 0, mck2ui 16
6456 14:00:05.889099 best dqsien dly found for B1: ( 0, 14, 24)
6457 14:00:05.892442 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6458 14:00:05.895590 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6459 14:00:05.895709
6460 14:00:05.899010 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6461 14:00:05.902246 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 14:00:05.905319 [Gating] SW calibration Done
6463 14:00:05.905422 ==
6464 14:00:05.908919 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 14:00:05.912058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 14:00:05.912177 ==
6467 14:00:05.915660 RX Vref Scan: 0
6468 14:00:05.915763
6469 14:00:05.915860 RX Vref 0 -> 0, step: 1
6470 14:00:05.915938
6471 14:00:05.918775 RX Delay -410 -> 252, step: 16
6472 14:00:05.925038 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6473 14:00:05.928340 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6474 14:00:05.931941 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6475 14:00:05.935121 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6476 14:00:05.941650 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6477 14:00:05.945013 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6478 14:00:05.948213 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6479 14:00:05.951761 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6480 14:00:05.958300 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6481 14:00:05.961825 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6482 14:00:05.965090 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6483 14:00:05.968024 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6484 14:00:05.974584 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6485 14:00:05.977817 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6486 14:00:05.981312 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6487 14:00:05.987699 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6488 14:00:05.987803 ==
6489 14:00:05.990959 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 14:00:05.994657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 14:00:05.994760 ==
6492 14:00:05.994829 DQS Delay:
6493 14:00:05.997904 DQS0 = 59, DQS1 = 59
6494 14:00:05.997988 DQM Delay:
6495 14:00:06.000909 DQM0 = 15, DQM1 = 10
6496 14:00:06.000990 DQ Delay:
6497 14:00:06.004464 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6498 14:00:06.007897 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6499 14:00:06.010907 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6500 14:00:06.014517 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6501 14:00:06.014601
6502 14:00:06.014665
6503 14:00:06.014725 ==
6504 14:00:06.017662 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 14:00:06.020832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 14:00:06.020915 ==
6507 14:00:06.020981
6508 14:00:06.023994
6509 14:00:06.024074 TX Vref Scan disable
6510 14:00:06.027648 == TX Byte 0 ==
6511 14:00:06.030884 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6512 14:00:06.034291 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6513 14:00:06.037543 == TX Byte 1 ==
6514 14:00:06.040742 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6515 14:00:06.044131 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6516 14:00:06.044211 ==
6517 14:00:06.047305 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 14:00:06.050641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 14:00:06.053862 ==
6520 14:00:06.053948
6521 14:00:06.054012
6522 14:00:06.054076 TX Vref Scan disable
6523 14:00:06.057177 == TX Byte 0 ==
6524 14:00:06.060815 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6525 14:00:06.063939 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6526 14:00:06.067345 == TX Byte 1 ==
6527 14:00:06.070441 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6528 14:00:06.073798 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6529 14:00:06.073879
6530 14:00:06.073943 [DATLAT]
6531 14:00:06.077074 Freq=400, CH0 RK1
6532 14:00:06.077156
6533 14:00:06.080382 DATLAT Default: 0xe
6534 14:00:06.080483 0, 0xFFFF, sum = 0
6535 14:00:06.083472 1, 0xFFFF, sum = 0
6536 14:00:06.083557 2, 0xFFFF, sum = 0
6537 14:00:06.087127 3, 0xFFFF, sum = 0
6538 14:00:06.087211 4, 0xFFFF, sum = 0
6539 14:00:06.090215 5, 0xFFFF, sum = 0
6540 14:00:06.090322 6, 0xFFFF, sum = 0
6541 14:00:06.093624 7, 0xFFFF, sum = 0
6542 14:00:06.093726 8, 0xFFFF, sum = 0
6543 14:00:06.096993 9, 0xFFFF, sum = 0
6544 14:00:06.097086 10, 0xFFFF, sum = 0
6545 14:00:06.100199 11, 0xFFFF, sum = 0
6546 14:00:06.100300 12, 0xFFFF, sum = 0
6547 14:00:06.103633 13, 0x0, sum = 1
6548 14:00:06.103720 14, 0x0, sum = 2
6549 14:00:06.106654 15, 0x0, sum = 3
6550 14:00:06.106742 16, 0x0, sum = 4
6551 14:00:06.110093 best_step = 14
6552 14:00:06.110215
6553 14:00:06.110313 ==
6554 14:00:06.113236 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 14:00:06.116467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 14:00:06.116555 ==
6557 14:00:06.120120 RX Vref Scan: 0
6558 14:00:06.120200
6559 14:00:06.120263 RX Vref 0 -> 0, step: 1
6560 14:00:06.120321
6561 14:00:06.123249 RX Delay -359 -> 252, step: 8
6562 14:00:06.131456 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6563 14:00:06.134790 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6564 14:00:06.137892 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6565 14:00:06.141189 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6566 14:00:06.148017 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6567 14:00:06.151059 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6568 14:00:06.154638 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6569 14:00:06.157975 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6570 14:00:06.164950 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6571 14:00:06.168069 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6572 14:00:06.171260 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6573 14:00:06.174792 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6574 14:00:06.181027 iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504
6575 14:00:06.184389 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6576 14:00:06.187848 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6577 14:00:06.194423 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6578 14:00:06.194507 ==
6579 14:00:06.197682 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 14:00:06.200986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 14:00:06.201070 ==
6582 14:00:06.201135 DQS Delay:
6583 14:00:06.204517 DQS0 = 60, DQS1 = 72
6584 14:00:06.204599 DQM Delay:
6585 14:00:06.207620 DQM0 = 11, DQM1 = 17
6586 14:00:06.207701 DQ Delay:
6587 14:00:06.211145 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6588 14:00:06.214502 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6589 14:00:06.217701 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6590 14:00:06.221229 DQ12 =20, DQ13 =28, DQ14 =28, DQ15 =24
6591 14:00:06.221337
6592 14:00:06.221429
6593 14:00:06.227589 [DQSOSCAuto] RK1, (LSB)MR18= 0xc479, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6594 14:00:06.230998 CH0 RK1: MR19=C0C, MR18=C479
6595 14:00:06.237688 CH0_RK1: MR19=0xC0C, MR18=0xC479, DQSOSC=385, MR23=63, INC=398, DEC=265
6596 14:00:06.240941 [RxdqsGatingPostProcess] freq 400
6597 14:00:06.247433 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6598 14:00:06.247517 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 14:00:06.250679 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 14:00:06.254181 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 14:00:06.257618 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 14:00:06.260709 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 14:00:06.264058 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 14:00:06.267511 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 14:00:06.270847 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 14:00:06.274085 Pre-setting of DQS Precalculation
6607 14:00:06.280673 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6608 14:00:06.280764 ==
6609 14:00:06.284007 Dram Type= 6, Freq= 0, CH_1, rank 0
6610 14:00:06.287417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 14:00:06.287500 ==
6612 14:00:06.294113 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 14:00:06.297311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6614 14:00:06.300613 [CA 0] Center 36 (8~64) winsize 57
6615 14:00:06.304080 [CA 1] Center 36 (8~64) winsize 57
6616 14:00:06.307482 [CA 2] Center 36 (8~64) winsize 57
6617 14:00:06.310898 [CA 3] Center 36 (8~64) winsize 57
6618 14:00:06.314002 [CA 4] Center 36 (8~64) winsize 57
6619 14:00:06.317472 [CA 5] Center 36 (8~64) winsize 57
6620 14:00:06.317591
6621 14:00:06.320588 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6622 14:00:06.320669
6623 14:00:06.323860 [CATrainingPosCal] consider 1 rank data
6624 14:00:06.327106 u2DelayCellTimex100 = 270/100 ps
6625 14:00:06.330677 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 14:00:06.333727 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 14:00:06.337013 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 14:00:06.343833 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 14:00:06.346975 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 14:00:06.350282 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 14:00:06.350362
6632 14:00:06.353931 CA PerBit enable=1, Macro0, CA PI delay=36
6633 14:00:06.354011
6634 14:00:06.357126 [CBTSetCACLKResult] CA Dly = 36
6635 14:00:06.357206 CS Dly: 1 (0~32)
6636 14:00:06.357270 ==
6637 14:00:06.360300 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 14:00:06.367099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 14:00:06.367180 ==
6640 14:00:06.370266 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6641 14:00:06.376850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6642 14:00:06.380165 [CA 0] Center 36 (8~64) winsize 57
6643 14:00:06.383583 [CA 1] Center 36 (8~64) winsize 57
6644 14:00:06.386923 [CA 2] Center 36 (8~64) winsize 57
6645 14:00:06.390453 [CA 3] Center 36 (8~64) winsize 57
6646 14:00:06.393637 [CA 4] Center 36 (8~64) winsize 57
6647 14:00:06.396725 [CA 5] Center 36 (8~64) winsize 57
6648 14:00:06.396804
6649 14:00:06.400137 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6650 14:00:06.400218
6651 14:00:06.403482 [CATrainingPosCal] consider 2 rank data
6652 14:00:06.406896 u2DelayCellTimex100 = 270/100 ps
6653 14:00:06.409999 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 14:00:06.413462 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 14:00:06.416516 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 14:00:06.419895 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 14:00:06.423231 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 14:00:06.426844 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 14:00:06.426926
6660 14:00:06.433230 CA PerBit enable=1, Macro0, CA PI delay=36
6661 14:00:06.433320
6662 14:00:06.436514 [CBTSetCACLKResult] CA Dly = 36
6663 14:00:06.436595 CS Dly: 1 (0~32)
6664 14:00:06.436659
6665 14:00:06.439928 ----->DramcWriteLeveling(PI) begin...
6666 14:00:06.440011 ==
6667 14:00:06.442949 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 14:00:06.446427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 14:00:06.449665 ==
6670 14:00:06.449750 Write leveling (Byte 0): 40 => 8
6671 14:00:06.453252 Write leveling (Byte 1): 40 => 8
6672 14:00:06.456434 DramcWriteLeveling(PI) end<-----
6673 14:00:06.456536
6674 14:00:06.456625 ==
6675 14:00:06.459974 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 14:00:06.466506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 14:00:06.466595 ==
6678 14:00:06.466660 [Gating] SW mode calibration
6679 14:00:06.475886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6680 14:00:06.479373 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6681 14:00:06.486245 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6682 14:00:06.489218 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 14:00:06.492680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 14:00:06.495888 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 14:00:06.502644 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 14:00:06.505710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 14:00:06.509121 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 14:00:06.515794 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 14:00:06.519008 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 14:00:06.522466 Total UI for P1: 0, mck2ui 16
6691 14:00:06.525852 best dqsien dly found for B0: ( 0, 14, 24)
6692 14:00:06.529000 Total UI for P1: 0, mck2ui 16
6693 14:00:06.532334 best dqsien dly found for B1: ( 0, 14, 24)
6694 14:00:06.535550 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6695 14:00:06.538690 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6696 14:00:06.538770
6697 14:00:06.542091 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6698 14:00:06.548631 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 14:00:06.548711 [Gating] SW calibration Done
6700 14:00:06.548775 ==
6701 14:00:06.552180 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 14:00:06.558797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 14:00:06.558877 ==
6704 14:00:06.558941 RX Vref Scan: 0
6705 14:00:06.558999
6706 14:00:06.561874 RX Vref 0 -> 0, step: 1
6707 14:00:06.561954
6708 14:00:06.565397 RX Delay -410 -> 252, step: 16
6709 14:00:06.568528 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6710 14:00:06.571954 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6711 14:00:06.578693 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6712 14:00:06.581899 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6713 14:00:06.585018 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6714 14:00:06.588582 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6715 14:00:06.594981 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6716 14:00:06.598441 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6717 14:00:06.601866 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6718 14:00:06.604981 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6719 14:00:06.611863 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6720 14:00:06.615293 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6721 14:00:06.618284 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6722 14:00:06.625109 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6723 14:00:06.628267 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6724 14:00:06.631599 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6725 14:00:06.631679 ==
6726 14:00:06.634902 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 14:00:06.638189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 14:00:06.638269 ==
6729 14:00:06.641432 DQS Delay:
6730 14:00:06.641523 DQS0 = 51, DQS1 = 59
6731 14:00:06.644972 DQM Delay:
6732 14:00:06.645051 DQM0 = 13, DQM1 = 13
6733 14:00:06.648152 DQ Delay:
6734 14:00:06.648232 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6735 14:00:06.651406 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6736 14:00:06.654581 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6737 14:00:06.657989 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6738 14:00:06.658070
6739 14:00:06.658133
6740 14:00:06.658193 ==
6741 14:00:06.661503 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 14:00:06.667855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 14:00:06.667936 ==
6744 14:00:06.667999
6745 14:00:06.668057
6746 14:00:06.668112 TX Vref Scan disable
6747 14:00:06.671433 == TX Byte 0 ==
6748 14:00:06.674483 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 14:00:06.677867 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 14:00:06.681158 == TX Byte 1 ==
6751 14:00:06.684365 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 14:00:06.687812 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 14:00:06.690974 ==
6754 14:00:06.691058 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 14:00:06.697452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 14:00:06.697559 ==
6757 14:00:06.697624
6758 14:00:06.697682
6759 14:00:06.700859 TX Vref Scan disable
6760 14:00:06.700939 == TX Byte 0 ==
6761 14:00:06.704303 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 14:00:06.710916 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 14:00:06.711003 == TX Byte 1 ==
6764 14:00:06.714096 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 14:00:06.717825 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 14:00:06.720925
6767 14:00:06.721005 [DATLAT]
6768 14:00:06.721069 Freq=400, CH1 RK0
6769 14:00:06.721129
6770 14:00:06.724153 DATLAT Default: 0xf
6771 14:00:06.724233 0, 0xFFFF, sum = 0
6772 14:00:06.727499 1, 0xFFFF, sum = 0
6773 14:00:06.727581 2, 0xFFFF, sum = 0
6774 14:00:06.730912 3, 0xFFFF, sum = 0
6775 14:00:06.730993 4, 0xFFFF, sum = 0
6776 14:00:06.734090 5, 0xFFFF, sum = 0
6777 14:00:06.737695 6, 0xFFFF, sum = 0
6778 14:00:06.737777 7, 0xFFFF, sum = 0
6779 14:00:06.740840 8, 0xFFFF, sum = 0
6780 14:00:06.740922 9, 0xFFFF, sum = 0
6781 14:00:06.744077 10, 0xFFFF, sum = 0
6782 14:00:06.744159 11, 0xFFFF, sum = 0
6783 14:00:06.747277 12, 0xFFFF, sum = 0
6784 14:00:06.747358 13, 0x0, sum = 1
6785 14:00:06.750631 14, 0x0, sum = 2
6786 14:00:06.750712 15, 0x0, sum = 3
6787 14:00:06.754006 16, 0x0, sum = 4
6788 14:00:06.754091 best_step = 14
6789 14:00:06.754154
6790 14:00:06.754213 ==
6791 14:00:06.757050 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 14:00:06.760529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 14:00:06.764048 ==
6794 14:00:06.764129 RX Vref Scan: 1
6795 14:00:06.764192
6796 14:00:06.767310 RX Vref 0 -> 0, step: 1
6797 14:00:06.767390
6798 14:00:06.770438 RX Delay -359 -> 252, step: 8
6799 14:00:06.770518
6800 14:00:06.773696 Set Vref, RX VrefLevel [Byte0]: 60
6801 14:00:06.777034 [Byte1]: 54
6802 14:00:06.777113
6803 14:00:06.780350 Final RX Vref Byte 0 = 60 to rank0
6804 14:00:06.783591 Final RX Vref Byte 1 = 54 to rank0
6805 14:00:06.786829 Final RX Vref Byte 0 = 60 to rank1
6806 14:00:06.790399 Final RX Vref Byte 1 = 54 to rank1==
6807 14:00:06.793630 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 14:00:06.796978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 14:00:06.797059 ==
6810 14:00:06.800193 DQS Delay:
6811 14:00:06.800273 DQS0 = 56, DQS1 = 64
6812 14:00:06.803700 DQM Delay:
6813 14:00:06.803779 DQM0 = 13, DQM1 = 10
6814 14:00:06.803843 DQ Delay:
6815 14:00:06.806963 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6816 14:00:06.810280 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6817 14:00:06.813550 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6818 14:00:06.816996 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6819 14:00:06.817077
6820 14:00:06.817140
6821 14:00:06.826496 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6822 14:00:06.829859 CH1 RK0: MR19=C0C, MR18=5E71
6823 14:00:06.833170 CH1_RK0: MR19=0xC0C, MR18=0x5E71, DQSOSC=395, MR23=63, INC=378, DEC=252
6824 14:00:06.836737 ==
6825 14:00:06.836818 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 14:00:06.843096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 14:00:06.843178 ==
6828 14:00:06.846604 [Gating] SW mode calibration
6829 14:00:06.852982 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6830 14:00:06.856434 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6831 14:00:06.862805 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6832 14:00:06.866188 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 14:00:06.869413 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 14:00:06.876380 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 14:00:06.879451 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 14:00:06.882863 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 14:00:06.889573 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 14:00:06.892882 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 14:00:06.896058 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 14:00:06.899597 Total UI for P1: 0, mck2ui 16
6841 14:00:06.902697 best dqsien dly found for B0: ( 0, 14, 24)
6842 14:00:06.906108 Total UI for P1: 0, mck2ui 16
6843 14:00:06.909544 best dqsien dly found for B1: ( 0, 14, 24)
6844 14:00:06.912894 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6845 14:00:06.916392 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6846 14:00:06.916500
6847 14:00:06.922540 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6848 14:00:06.926115 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 14:00:06.926226 [Gating] SW calibration Done
6850 14:00:06.929234 ==
6851 14:00:06.932617 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 14:00:06.935750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 14:00:06.935858 ==
6854 14:00:06.935952 RX Vref Scan: 0
6855 14:00:06.936041
6856 14:00:06.939250 RX Vref 0 -> 0, step: 1
6857 14:00:06.939355
6858 14:00:06.942643 RX Delay -410 -> 252, step: 16
6859 14:00:06.945763 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6860 14:00:06.952371 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6861 14:00:06.955895 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6862 14:00:06.959035 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6863 14:00:06.962177 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6864 14:00:06.969073 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6865 14:00:06.972201 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6866 14:00:06.975585 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6867 14:00:06.978868 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6868 14:00:06.985356 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6869 14:00:06.988759 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6870 14:00:06.992163 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6871 14:00:06.995310 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6872 14:00:07.001963 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6873 14:00:07.005253 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6874 14:00:07.008789 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6875 14:00:07.008899 ==
6876 14:00:07.011695 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 14:00:07.018449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 14:00:07.018576 ==
6879 14:00:07.018675 DQS Delay:
6880 14:00:07.021836 DQS0 = 59, DQS1 = 67
6881 14:00:07.021958 DQM Delay:
6882 14:00:07.022053 DQM0 = 19, DQM1 = 22
6883 14:00:07.025188 DQ Delay:
6884 14:00:07.028485 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6885 14:00:07.032010 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6886 14:00:07.032119 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6887 14:00:07.038616 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6888 14:00:07.038723
6889 14:00:07.038818
6890 14:00:07.038910 ==
6891 14:00:07.041738 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 14:00:07.045142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 14:00:07.045253 ==
6894 14:00:07.045347
6895 14:00:07.045442
6896 14:00:07.048506 TX Vref Scan disable
6897 14:00:07.048625 == TX Byte 0 ==
6898 14:00:07.051904 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6899 14:00:07.058293 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6900 14:00:07.058405 == TX Byte 1 ==
6901 14:00:07.061956 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6902 14:00:07.068482 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6903 14:00:07.068591 ==
6904 14:00:07.071597 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 14:00:07.075169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 14:00:07.075292 ==
6907 14:00:07.075386
6908 14:00:07.075476
6909 14:00:07.078320 TX Vref Scan disable
6910 14:00:07.078459 == TX Byte 0 ==
6911 14:00:07.081619 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6912 14:00:07.088317 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6913 14:00:07.088425 == TX Byte 1 ==
6914 14:00:07.091753 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6915 14:00:07.098020 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6916 14:00:07.098128
6917 14:00:07.098221 [DATLAT]
6918 14:00:07.101343 Freq=400, CH1 RK1
6919 14:00:07.101453
6920 14:00:07.101586 DATLAT Default: 0xe
6921 14:00:07.104806 0, 0xFFFF, sum = 0
6922 14:00:07.104917 1, 0xFFFF, sum = 0
6923 14:00:07.108014 2, 0xFFFF, sum = 0
6924 14:00:07.108124 3, 0xFFFF, sum = 0
6925 14:00:07.111267 4, 0xFFFF, sum = 0
6926 14:00:07.111382 5, 0xFFFF, sum = 0
6927 14:00:07.114731 6, 0xFFFF, sum = 0
6928 14:00:07.114846 7, 0xFFFF, sum = 0
6929 14:00:07.118087 8, 0xFFFF, sum = 0
6930 14:00:07.118203 9, 0xFFFF, sum = 0
6931 14:00:07.121337 10, 0xFFFF, sum = 0
6932 14:00:07.121453 11, 0xFFFF, sum = 0
6933 14:00:07.124454 12, 0xFFFF, sum = 0
6934 14:00:07.124563 13, 0x0, sum = 1
6935 14:00:07.127763 14, 0x0, sum = 2
6936 14:00:07.127873 15, 0x0, sum = 3
6937 14:00:07.131154 16, 0x0, sum = 4
6938 14:00:07.131264 best_step = 14
6939 14:00:07.131361
6940 14:00:07.131457 ==
6941 14:00:07.134551 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 14:00:07.141219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 14:00:07.141332 ==
6944 14:00:07.141428 RX Vref Scan: 0
6945 14:00:07.141536
6946 14:00:07.144593 RX Vref 0 -> 0, step: 1
6947 14:00:07.144700
6948 14:00:07.147750 RX Delay -375 -> 252, step: 8
6949 14:00:07.154451 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6950 14:00:07.157552 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6951 14:00:07.161041 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6952 14:00:07.164343 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6953 14:00:07.170992 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6954 14:00:07.174182 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6955 14:00:07.177753 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6956 14:00:07.180896 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6957 14:00:07.187541 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6958 14:00:07.190759 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6959 14:00:07.194233 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6960 14:00:07.200955 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
6961 14:00:07.204131 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6962 14:00:07.207293 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6963 14:00:07.210557 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6964 14:00:07.217212 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6965 14:00:07.217330 ==
6966 14:00:07.220799 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 14:00:07.223788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 14:00:07.223900 ==
6969 14:00:07.224000 DQS Delay:
6970 14:00:07.227067 DQS0 = 60, DQS1 = 64
6971 14:00:07.227178 DQM Delay:
6972 14:00:07.230587 DQM0 = 13, DQM1 = 10
6973 14:00:07.230698 DQ Delay:
6974 14:00:07.233730 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6975 14:00:07.237124 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6976 14:00:07.240491 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6977 14:00:07.243768 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6978 14:00:07.243878
6979 14:00:07.243972
6980 14:00:07.250300 [DQSOSCAuto] RK1, (LSB)MR18= 0x80b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6981 14:00:07.253889 CH1 RK1: MR19=C0C, MR18=80B0
6982 14:00:07.260153 CH1_RK1: MR19=0xC0C, MR18=0x80B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6983 14:00:07.263618 [RxdqsGatingPostProcess] freq 400
6984 14:00:07.270314 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6985 14:00:07.273568 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 14:00:07.276781 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 14:00:07.276890 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 14:00:07.280178 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 14:00:07.283335 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 14:00:07.286862 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 14:00:07.290054 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 14:00:07.293296 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 14:00:07.297002 Pre-setting of DQS Precalculation
6994 14:00:07.303311 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6995 14:00:07.310030 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6996 14:00:07.316501 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6997 14:00:07.316618
6998 14:00:07.316714
6999 14:00:07.320136 [Calibration Summary] 800 Mbps
7000 14:00:07.320247 CH 0, Rank 0
7001 14:00:07.323247 SW Impedance : PASS
7002 14:00:07.326787 DUTY Scan : NO K
7003 14:00:07.326896 ZQ Calibration : PASS
7004 14:00:07.330002 Jitter Meter : NO K
7005 14:00:07.333344 CBT Training : PASS
7006 14:00:07.333453 Write leveling : PASS
7007 14:00:07.336442 RX DQS gating : PASS
7008 14:00:07.339806 RX DQ/DQS(RDDQC) : PASS
7009 14:00:07.339918 TX DQ/DQS : PASS
7010 14:00:07.343182 RX DATLAT : PASS
7011 14:00:07.343291 RX DQ/DQS(Engine): PASS
7012 14:00:07.346443 TX OE : NO K
7013 14:00:07.346557 All Pass.
7014 14:00:07.346652
7015 14:00:07.349903 CH 0, Rank 1
7016 14:00:07.352846 SW Impedance : PASS
7017 14:00:07.352958 DUTY Scan : NO K
7018 14:00:07.356228 ZQ Calibration : PASS
7019 14:00:07.356342 Jitter Meter : NO K
7020 14:00:07.359795 CBT Training : PASS
7021 14:00:07.363159 Write leveling : NO K
7022 14:00:07.363270 RX DQS gating : PASS
7023 14:00:07.366147 RX DQ/DQS(RDDQC) : PASS
7024 14:00:07.369447 TX DQ/DQS : PASS
7025 14:00:07.369546 RX DATLAT : PASS
7026 14:00:07.372780 RX DQ/DQS(Engine): PASS
7027 14:00:07.376131 TX OE : NO K
7028 14:00:07.376245 All Pass.
7029 14:00:07.376343
7030 14:00:07.376440 CH 1, Rank 0
7031 14:00:07.379701 SW Impedance : PASS
7032 14:00:07.382696 DUTY Scan : NO K
7033 14:00:07.382804 ZQ Calibration : PASS
7034 14:00:07.385968 Jitter Meter : NO K
7035 14:00:07.389378 CBT Training : PASS
7036 14:00:07.389504 Write leveling : PASS
7037 14:00:07.392848 RX DQS gating : PASS
7038 14:00:07.395989 RX DQ/DQS(RDDQC) : PASS
7039 14:00:07.396066 TX DQ/DQS : PASS
7040 14:00:07.399139 RX DATLAT : PASS
7041 14:00:07.402675 RX DQ/DQS(Engine): PASS
7042 14:00:07.402747 TX OE : NO K
7043 14:00:07.405777 All Pass.
7044 14:00:07.405846
7045 14:00:07.405907 CH 1, Rank 1
7046 14:00:07.409337 SW Impedance : PASS
7047 14:00:07.409432 DUTY Scan : NO K
7048 14:00:07.412510 ZQ Calibration : PASS
7049 14:00:07.415725 Jitter Meter : NO K
7050 14:00:07.415798 CBT Training : PASS
7051 14:00:07.419138 Write leveling : NO K
7052 14:00:07.422266 RX DQS gating : PASS
7053 14:00:07.422341 RX DQ/DQS(RDDQC) : PASS
7054 14:00:07.425495 TX DQ/DQS : PASS
7055 14:00:07.425600 RX DATLAT : PASS
7056 14:00:07.428902 RX DQ/DQS(Engine): PASS
7057 14:00:07.432545 TX OE : NO K
7058 14:00:07.432631 All Pass.
7059 14:00:07.432694
7060 14:00:07.435829 DramC Write-DBI off
7061 14:00:07.435898 PER_BANK_REFRESH: Hybrid Mode
7062 14:00:07.438897 TX_TRACKING: ON
7063 14:00:07.448802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7064 14:00:07.452199 [FAST_K] Save calibration result to emmc
7065 14:00:07.455691 dramc_set_vcore_voltage set vcore to 725000
7066 14:00:07.455766 Read voltage for 1600, 0
7067 14:00:07.458813 Vio18 = 0
7068 14:00:07.458885 Vcore = 725000
7069 14:00:07.458944 Vdram = 0
7070 14:00:07.462282 Vddq = 0
7071 14:00:07.462354 Vmddr = 0
7072 14:00:07.465812 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7073 14:00:07.472338 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7074 14:00:07.475621 MEM_TYPE=3, freq_sel=13
7075 14:00:07.478782 sv_algorithm_assistance_LP4_3733
7076 14:00:07.482091 ============ PULL DRAM RESETB DOWN ============
7077 14:00:07.485632 ========== PULL DRAM RESETB DOWN end =========
7078 14:00:07.492344 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7079 14:00:07.495398 ===================================
7080 14:00:07.495482 LPDDR4 DRAM CONFIGURATION
7081 14:00:07.498826 ===================================
7082 14:00:07.502262 EX_ROW_EN[0] = 0x0
7083 14:00:07.502344 EX_ROW_EN[1] = 0x0
7084 14:00:07.505377 LP4Y_EN = 0x0
7085 14:00:07.505486 WORK_FSP = 0x1
7086 14:00:07.508917 WL = 0x5
7087 14:00:07.512052 RL = 0x5
7088 14:00:07.512166 BL = 0x2
7089 14:00:07.515733 RPST = 0x0
7090 14:00:07.515843 RD_PRE = 0x0
7091 14:00:07.519023 WR_PRE = 0x1
7092 14:00:07.519134 WR_PST = 0x1
7093 14:00:07.522163 DBI_WR = 0x0
7094 14:00:07.522273 DBI_RD = 0x0
7095 14:00:07.525405 OTF = 0x1
7096 14:00:07.528928 ===================================
7097 14:00:07.532184 ===================================
7098 14:00:07.532294 ANA top config
7099 14:00:07.535441 ===================================
7100 14:00:07.538552 DLL_ASYNC_EN = 0
7101 14:00:07.542147 ALL_SLAVE_EN = 0
7102 14:00:07.542255 NEW_RANK_MODE = 1
7103 14:00:07.545200 DLL_IDLE_MODE = 1
7104 14:00:07.548777 LP45_APHY_COMB_EN = 1
7105 14:00:07.551795 TX_ODT_DIS = 0
7106 14:00:07.555173 NEW_8X_MODE = 1
7107 14:00:07.558501 ===================================
7108 14:00:07.561677 ===================================
7109 14:00:07.561790 data_rate = 3200
7110 14:00:07.564935 CKR = 1
7111 14:00:07.568137 DQ_P2S_RATIO = 8
7112 14:00:07.571672 ===================================
7113 14:00:07.574803 CA_P2S_RATIO = 8
7114 14:00:07.577988 DQ_CA_OPEN = 0
7115 14:00:07.581531 DQ_SEMI_OPEN = 0
7116 14:00:07.581642 CA_SEMI_OPEN = 0
7117 14:00:07.584676 CA_FULL_RATE = 0
7118 14:00:07.588065 DQ_CKDIV4_EN = 0
7119 14:00:07.591482 CA_CKDIV4_EN = 0
7120 14:00:07.594562 CA_PREDIV_EN = 0
7121 14:00:07.597928 PH8_DLY = 12
7122 14:00:07.598038 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7123 14:00:07.601331 DQ_AAMCK_DIV = 4
7124 14:00:07.604651 CA_AAMCK_DIV = 4
7125 14:00:07.608051 CA_ADMCK_DIV = 4
7126 14:00:07.611149 DQ_TRACK_CA_EN = 0
7127 14:00:07.614559 CA_PICK = 1600
7128 14:00:07.618134 CA_MCKIO = 1600
7129 14:00:07.618241 MCKIO_SEMI = 0
7130 14:00:07.621176 PLL_FREQ = 3068
7131 14:00:07.624468 DQ_UI_PI_RATIO = 32
7132 14:00:07.627523 CA_UI_PI_RATIO = 0
7133 14:00:07.631057 ===================================
7134 14:00:07.634343 ===================================
7135 14:00:07.637420 memory_type:LPDDR4
7136 14:00:07.637565 GP_NUM : 10
7137 14:00:07.641079 SRAM_EN : 1
7138 14:00:07.644246 MD32_EN : 0
7139 14:00:07.647529 ===================================
7140 14:00:07.647638 [ANA_INIT] >>>>>>>>>>>>>>
7141 14:00:07.651026 <<<<<< [CONFIGURE PHASE]: ANA_TX
7142 14:00:07.654198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7143 14:00:07.657356 ===================================
7144 14:00:07.660812 data_rate = 3200,PCW = 0X7600
7145 14:00:07.664125 ===================================
7146 14:00:07.667152 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7147 14:00:07.673872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7148 14:00:07.677125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 14:00:07.683645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7150 14:00:07.687178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7151 14:00:07.690277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7152 14:00:07.693880 [ANA_INIT] flow start
7153 14:00:07.694015 [ANA_INIT] PLL >>>>>>>>
7154 14:00:07.696889 [ANA_INIT] PLL <<<<<<<<
7155 14:00:07.700253 [ANA_INIT] MIDPI >>>>>>>>
7156 14:00:07.700390 [ANA_INIT] MIDPI <<<<<<<<
7157 14:00:07.703443 [ANA_INIT] DLL >>>>>>>>
7158 14:00:07.706769 [ANA_INIT] DLL <<<<<<<<
7159 14:00:07.706872 [ANA_INIT] flow end
7160 14:00:07.713731 ============ LP4 DIFF to SE enter ============
7161 14:00:07.716772 ============ LP4 DIFF to SE exit ============
7162 14:00:07.720388 [ANA_INIT] <<<<<<<<<<<<<
7163 14:00:07.723526 [Flow] Enable top DCM control >>>>>
7164 14:00:07.726859 [Flow] Enable top DCM control <<<<<
7165 14:00:07.726971 Enable DLL master slave shuffle
7166 14:00:07.733355 ==============================================================
7167 14:00:07.736473 Gating Mode config
7168 14:00:07.740018 ==============================================================
7169 14:00:07.743177 Config description:
7170 14:00:07.753370 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7171 14:00:07.759755 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7172 14:00:07.762892 SELPH_MODE 0: By rank 1: By Phase
7173 14:00:07.769673 ==============================================================
7174 14:00:07.772926 GAT_TRACK_EN = 1
7175 14:00:07.776023 RX_GATING_MODE = 2
7176 14:00:07.779351 RX_GATING_TRACK_MODE = 2
7177 14:00:07.782697 SELPH_MODE = 1
7178 14:00:07.785968 PICG_EARLY_EN = 1
7179 14:00:07.786088 VALID_LAT_VALUE = 1
7180 14:00:07.792775 ==============================================================
7181 14:00:07.795972 Enter into Gating configuration >>>>
7182 14:00:07.799572 Exit from Gating configuration <<<<
7183 14:00:07.802782 Enter into DVFS_PRE_config >>>>>
7184 14:00:07.812885 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7185 14:00:07.816271 Exit from DVFS_PRE_config <<<<<
7186 14:00:07.819409 Enter into PICG configuration >>>>
7187 14:00:07.822974 Exit from PICG configuration <<<<
7188 14:00:07.826120 [RX_INPUT] configuration >>>>>
7189 14:00:07.829448 [RX_INPUT] configuration <<<<<
7190 14:00:07.832732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7191 14:00:07.839102 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7192 14:00:07.845793 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 14:00:07.852344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 14:00:07.858852 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 14:00:07.865464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 14:00:07.868888 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7197 14:00:07.872398 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7198 14:00:07.875482 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7199 14:00:07.882079 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7200 14:00:07.885586 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7201 14:00:07.888860 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 14:00:07.891898 ===================================
7203 14:00:07.895170 LPDDR4 DRAM CONFIGURATION
7204 14:00:07.898833 ===================================
7205 14:00:07.898943 EX_ROW_EN[0] = 0x0
7206 14:00:07.902127 EX_ROW_EN[1] = 0x0
7207 14:00:07.905308 LP4Y_EN = 0x0
7208 14:00:07.905416 WORK_FSP = 0x1
7209 14:00:07.908493 WL = 0x5
7210 14:00:07.908602 RL = 0x5
7211 14:00:07.911905 BL = 0x2
7212 14:00:07.912030 RPST = 0x0
7213 14:00:07.915173 RD_PRE = 0x0
7214 14:00:07.915303 WR_PRE = 0x1
7215 14:00:07.918533 WR_PST = 0x1
7216 14:00:07.918659 DBI_WR = 0x0
7217 14:00:07.922051 DBI_RD = 0x0
7218 14:00:07.922176 OTF = 0x1
7219 14:00:07.925577 ===================================
7220 14:00:07.928629 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7221 14:00:07.935367 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7222 14:00:07.938577 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 14:00:07.941785 ===================================
7224 14:00:07.944996 LPDDR4 DRAM CONFIGURATION
7225 14:00:07.948662 ===================================
7226 14:00:07.948788 EX_ROW_EN[0] = 0x10
7227 14:00:07.951814 EX_ROW_EN[1] = 0x0
7228 14:00:07.951939 LP4Y_EN = 0x0
7229 14:00:07.954870 WORK_FSP = 0x1
7230 14:00:07.958521 WL = 0x5
7231 14:00:07.958644 RL = 0x5
7232 14:00:07.961862 BL = 0x2
7233 14:00:07.961972 RPST = 0x0
7234 14:00:07.965023 RD_PRE = 0x0
7235 14:00:07.965176 WR_PRE = 0x1
7236 14:00:07.968209 WR_PST = 0x1
7237 14:00:07.968351 DBI_WR = 0x0
7238 14:00:07.971705 DBI_RD = 0x0
7239 14:00:07.971815 OTF = 0x1
7240 14:00:07.975033 ===================================
7241 14:00:07.981674 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7242 14:00:07.981786 ==
7243 14:00:07.984831 Dram Type= 6, Freq= 0, CH_0, rank 0
7244 14:00:07.988371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7245 14:00:07.988484 ==
7246 14:00:07.991391 [Duty_Offset_Calibration]
7247 14:00:07.994711 B0:2 B1:0 CA:3
7248 14:00:07.994820
7249 14:00:07.998129 [DutyScan_Calibration_Flow] k_type=0
7250 14:00:08.006628
7251 14:00:08.006743 ==CLK 0==
7252 14:00:08.009955 Final CLK duty delay cell = 0
7253 14:00:08.013346 [0] MAX Duty = 5031%(X100), DQS PI = 12
7254 14:00:08.016773 [0] MIN Duty = 4907%(X100), DQS PI = 6
7255 14:00:08.016885 [0] AVG Duty = 4969%(X100)
7256 14:00:08.019796
7257 14:00:08.023097 CH0 CLK Duty spec in!! Max-Min= 124%
7258 14:00:08.026683 [DutyScan_Calibration_Flow] ====Done====
7259 14:00:08.026797
7260 14:00:08.029675 [DutyScan_Calibration_Flow] k_type=1
7261 14:00:08.046764
7262 14:00:08.046897 ==DQS 0 ==
7263 14:00:08.049810 Final DQS duty delay cell = 0
7264 14:00:08.053437 [0] MAX Duty = 5094%(X100), DQS PI = 30
7265 14:00:08.056701 [0] MIN Duty = 4875%(X100), DQS PI = 48
7266 14:00:08.056815 [0] AVG Duty = 4984%(X100)
7267 14:00:08.059888
7268 14:00:08.059999 ==DQS 1 ==
7269 14:00:08.063549 Final DQS duty delay cell = 0
7270 14:00:08.066642 [0] MAX Duty = 5156%(X100), DQS PI = 32
7271 14:00:08.069720 [0] MIN Duty = 5062%(X100), DQS PI = 8
7272 14:00:08.072883 [0] AVG Duty = 5109%(X100)
7273 14:00:08.072996
7274 14:00:08.076387 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7275 14:00:08.076498
7276 14:00:08.079816 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7277 14:00:08.082780 [DutyScan_Calibration_Flow] ====Done====
7278 14:00:08.082892
7279 14:00:08.085955 [DutyScan_Calibration_Flow] k_type=3
7280 14:00:08.104545
7281 14:00:08.104682 ==DQM 0 ==
7282 14:00:08.107697 Final DQM duty delay cell = 0
7283 14:00:08.110929 [0] MAX Duty = 5156%(X100), DQS PI = 14
7284 14:00:08.114191 [0] MIN Duty = 4875%(X100), DQS PI = 48
7285 14:00:08.117576 [0] AVG Duty = 5015%(X100)
7286 14:00:08.117686
7287 14:00:08.117784 ==DQM 1 ==
7288 14:00:08.121072 Final DQM duty delay cell = 4
7289 14:00:08.124229 [4] MAX Duty = 5187%(X100), DQS PI = 60
7290 14:00:08.127481 [4] MIN Duty = 5000%(X100), DQS PI = 14
7291 14:00:08.130930 [4] AVG Duty = 5093%(X100)
7292 14:00:08.131040
7293 14:00:08.134352 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7294 14:00:08.134463
7295 14:00:08.137391 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7296 14:00:08.140967 [DutyScan_Calibration_Flow] ====Done====
7297 14:00:08.141076
7298 14:00:08.144129 [DutyScan_Calibration_Flow] k_type=2
7299 14:00:08.161042
7300 14:00:08.161164 ==DQ 0 ==
7301 14:00:08.164255 Final DQ duty delay cell = -4
7302 14:00:08.167371 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7303 14:00:08.171017 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7304 14:00:08.174189 [-4] AVG Duty = 4938%(X100)
7305 14:00:08.174296
7306 14:00:08.174392 ==DQ 1 ==
7307 14:00:08.177737 Final DQ duty delay cell = 0
7308 14:00:08.180985 [0] MAX Duty = 5156%(X100), DQS PI = 58
7309 14:00:08.184286 [0] MIN Duty = 5000%(X100), DQS PI = 16
7310 14:00:08.187652 [0] AVG Duty = 5078%(X100)
7311 14:00:08.187772
7312 14:00:08.190764 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7313 14:00:08.190875
7314 14:00:08.194092 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7315 14:00:08.197717 [DutyScan_Calibration_Flow] ====Done====
7316 14:00:08.197826 ==
7317 14:00:08.200837 Dram Type= 6, Freq= 0, CH_1, rank 0
7318 14:00:08.204346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 14:00:08.204456 ==
7320 14:00:08.207525 [Duty_Offset_Calibration]
7321 14:00:08.207636 B0:1 B1:-2 CA:0
7322 14:00:08.207731
7323 14:00:08.210678 [DutyScan_Calibration_Flow] k_type=0
7324 14:00:08.221565
7325 14:00:08.221689 ==CLK 0==
7326 14:00:08.224846 Final CLK duty delay cell = 0
7327 14:00:08.228262 [0] MAX Duty = 5062%(X100), DQS PI = 20
7328 14:00:08.231490 [0] MIN Duty = 4844%(X100), DQS PI = 2
7329 14:00:08.231603 [0] AVG Duty = 4953%(X100)
7330 14:00:08.234738
7331 14:00:08.234850 CH1 CLK Duty spec in!! Max-Min= 218%
7332 14:00:08.241556 [DutyScan_Calibration_Flow] ====Done====
7333 14:00:08.241667
7334 14:00:08.244551 [DutyScan_Calibration_Flow] k_type=1
7335 14:00:08.260463
7336 14:00:08.260587 ==DQS 0 ==
7337 14:00:08.263506 Final DQS duty delay cell = -4
7338 14:00:08.266944 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7339 14:00:08.270094 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7340 14:00:08.273532 [-4] AVG Duty = 4906%(X100)
7341 14:00:08.273640
7342 14:00:08.273733 ==DQS 1 ==
7343 14:00:08.277083 Final DQS duty delay cell = 0
7344 14:00:08.280267 [0] MAX Duty = 5093%(X100), DQS PI = 62
7345 14:00:08.283535 [0] MIN Duty = 4813%(X100), DQS PI = 26
7346 14:00:08.286732 [0] AVG Duty = 4953%(X100)
7347 14:00:08.286842
7348 14:00:08.290430 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7349 14:00:08.290541
7350 14:00:08.293504 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7351 14:00:08.296723 [DutyScan_Calibration_Flow] ====Done====
7352 14:00:08.296832
7353 14:00:08.300187 [DutyScan_Calibration_Flow] k_type=3
7354 14:00:08.317464
7355 14:00:08.317613 ==DQM 0 ==
7356 14:00:08.320959 Final DQM duty delay cell = 0
7357 14:00:08.324119 [0] MAX Duty = 5031%(X100), DQS PI = 24
7358 14:00:08.327576 [0] MIN Duty = 4813%(X100), DQS PI = 56
7359 14:00:08.330731 [0] AVG Duty = 4922%(X100)
7360 14:00:08.330843
7361 14:00:08.330943 ==DQM 1 ==
7362 14:00:08.334048 Final DQM duty delay cell = 0
7363 14:00:08.337294 [0] MAX Duty = 5062%(X100), DQS PI = 34
7364 14:00:08.340740 [0] MIN Duty = 4875%(X100), DQS PI = 26
7365 14:00:08.343939 [0] AVG Duty = 4968%(X100)
7366 14:00:08.344023
7367 14:00:08.347315 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7368 14:00:08.347399
7369 14:00:08.350746 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7370 14:00:08.353960 [DutyScan_Calibration_Flow] ====Done====
7371 14:00:08.354043
7372 14:00:08.357128 [DutyScan_Calibration_Flow] k_type=2
7373 14:00:08.374726
7374 14:00:08.374834 ==DQ 0 ==
7375 14:00:08.377839 Final DQ duty delay cell = 0
7376 14:00:08.381160 [0] MAX Duty = 5093%(X100), DQS PI = 20
7377 14:00:08.384519 [0] MIN Duty = 4907%(X100), DQS PI = 60
7378 14:00:08.387669 [0] AVG Duty = 5000%(X100)
7379 14:00:08.387784
7380 14:00:08.387885 ==DQ 1 ==
7381 14:00:08.390848 Final DQ duty delay cell = 0
7382 14:00:08.394327 [0] MAX Duty = 5156%(X100), DQS PI = 34
7383 14:00:08.397501 [0] MIN Duty = 4969%(X100), DQS PI = 24
7384 14:00:08.400805 [0] AVG Duty = 5062%(X100)
7385 14:00:08.400913
7386 14:00:08.404240 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7387 14:00:08.404351
7388 14:00:08.407529 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7389 14:00:08.410721 [DutyScan_Calibration_Flow] ====Done====
7390 14:00:08.414032 nWR fixed to 30
7391 14:00:08.414146 [ModeRegInit_LP4] CH0 RK0
7392 14:00:08.417488 [ModeRegInit_LP4] CH0 RK1
7393 14:00:08.421041 [ModeRegInit_LP4] CH1 RK0
7394 14:00:08.424097 [ModeRegInit_LP4] CH1 RK1
7395 14:00:08.424207 match AC timing 5
7396 14:00:08.430636 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7397 14:00:08.434010 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7398 14:00:08.437328 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7399 14:00:08.443790 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7400 14:00:08.447227 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7401 14:00:08.447342 [MiockJmeterHQA]
7402 14:00:08.447440
7403 14:00:08.450470 [DramcMiockJmeter] u1RxGatingPI = 0
7404 14:00:08.453944 0 : 4255, 4029
7405 14:00:08.454058 4 : 4252, 4027
7406 14:00:08.457151 8 : 4255, 4029
7407 14:00:08.457240 12 : 4252, 4027
7408 14:00:08.457309 16 : 4363, 4137
7409 14:00:08.460379 20 : 4363, 4137
7410 14:00:08.460494 24 : 4253, 4027
7411 14:00:08.463619 28 : 4253, 4027
7412 14:00:08.463730 32 : 4252, 4027
7413 14:00:08.467222 36 : 4253, 4027
7414 14:00:08.467335 40 : 4255, 4029
7415 14:00:08.470454 44 : 4363, 4137
7416 14:00:08.470564 48 : 4253, 4026
7417 14:00:08.470661 52 : 4253, 4027
7418 14:00:08.473906 56 : 4252, 4027
7419 14:00:08.474017 60 : 4252, 4029
7420 14:00:08.477086 64 : 4250, 4027
7421 14:00:08.477196 68 : 4363, 4140
7422 14:00:08.480364 72 : 4360, 4138
7423 14:00:08.480474 76 : 4252, 4030
7424 14:00:08.483578 80 : 4250, 4026
7425 14:00:08.483689 84 : 4250, 4027
7426 14:00:08.483790 88 : 4250, 4027
7427 14:00:08.487205 92 : 4253, 4029
7428 14:00:08.487320 96 : 4360, 4138
7429 14:00:08.490441 100 : 4250, 4026
7430 14:00:08.490551 104 : 4250, 3545
7431 14:00:08.493693 108 : 4250, 1
7432 14:00:08.493804 112 : 4252, 0
7433 14:00:08.493902 116 : 4252, 0
7434 14:00:08.497082 120 : 4253, 0
7435 14:00:08.497190 124 : 4252, 0
7436 14:00:08.500307 128 : 4250, 0
7437 14:00:08.500417 132 : 4360, 0
7438 14:00:08.500515 136 : 4250, 0
7439 14:00:08.503457 140 : 4361, 0
7440 14:00:08.503566 144 : 4361, 0
7441 14:00:08.506696 148 : 4250, 0
7442 14:00:08.506806 152 : 4250, 0
7443 14:00:08.506902 156 : 4250, 0
7444 14:00:08.510317 160 : 4250, 0
7445 14:00:08.510428 164 : 4250, 0
7446 14:00:08.513532 168 : 4249, 0
7447 14:00:08.513644 172 : 4250, 0
7448 14:00:08.513743 176 : 4252, 0
7449 14:00:08.516747 180 : 4250, 0
7450 14:00:08.516860 184 : 4360, 0
7451 14:00:08.516960 188 : 4360, 0
7452 14:00:08.520177 192 : 4250, 0
7453 14:00:08.520289 196 : 4250, 0
7454 14:00:08.523248 200 : 4250, 0
7455 14:00:08.523358 204 : 4250, 0
7456 14:00:08.523458 208 : 4250, 0
7457 14:00:08.526909 212 : 4250, 0
7458 14:00:08.527020 216 : 4250, 0
7459 14:00:08.529923 220 : 4250, 0
7460 14:00:08.530035 224 : 4250, 0
7461 14:00:08.530131 228 : 4249, 0
7462 14:00:08.533409 232 : 4250, 0
7463 14:00:08.533526 236 : 4360, 1206
7464 14:00:08.536701 240 : 4250, 4027
7465 14:00:08.536813 244 : 4253, 4029
7466 14:00:08.539859 248 : 4361, 4137
7467 14:00:08.539973 252 : 4250, 4027
7468 14:00:08.543171 256 : 4250, 4027
7469 14:00:08.543281 260 : 4250, 4027
7470 14:00:08.546639 264 : 4253, 4029
7471 14:00:08.546750 268 : 4250, 4027
7472 14:00:08.546849 272 : 4250, 4027
7473 14:00:08.550065 276 : 4361, 4137
7474 14:00:08.550178 280 : 4250, 4026
7475 14:00:08.553267 284 : 4250, 4027
7476 14:00:08.553380 288 : 4360, 4138
7477 14:00:08.556625 292 : 4250, 4027
7478 14:00:08.556739 296 : 4250, 4026
7479 14:00:08.559892 300 : 4363, 4139
7480 14:00:08.560002 304 : 4250, 4027
7481 14:00:08.563065 308 : 4250, 4027
7482 14:00:08.563175 312 : 4250, 4026
7483 14:00:08.566403 316 : 4253, 4029
7484 14:00:08.566516 320 : 4250, 4027
7485 14:00:08.569939 324 : 4250, 4027
7486 14:00:08.570051 328 : 4363, 4140
7487 14:00:08.570150 332 : 4250, 4026
7488 14:00:08.573041 336 : 4250, 4027
7489 14:00:08.573151 340 : 4361, 4137
7490 14:00:08.576305 344 : 4250, 4027
7491 14:00:08.576419 348 : 4250, 4026
7492 14:00:08.579578 352 : 4363, 4127
7493 14:00:08.579688 356 : 4250, 2824
7494 14:00:08.582846 360 : 4250, 3
7495 14:00:08.582959
7496 14:00:08.583053 MIOCK jitter meter ch=0
7497 14:00:08.583149
7498 14:00:08.586214 1T = (360-108) = 252 dly cells
7499 14:00:08.593106 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7500 14:00:08.593219 ==
7501 14:00:08.596249 Dram Type= 6, Freq= 0, CH_0, rank 0
7502 14:00:08.599560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 14:00:08.599672 ==
7504 14:00:08.606321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 14:00:08.609527 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 14:00:08.616056 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 14:00:08.619653 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 14:00:08.629444 [CA 0] Center 44 (14~75) winsize 62
7509 14:00:08.632926 [CA 1] Center 43 (13~74) winsize 62
7510 14:00:08.636364 [CA 2] Center 40 (11~69) winsize 59
7511 14:00:08.639406 [CA 3] Center 39 (10~68) winsize 59
7512 14:00:08.642767 [CA 4] Center 37 (8~67) winsize 60
7513 14:00:08.645911 [CA 5] Center 37 (7~67) winsize 61
7514 14:00:08.646029
7515 14:00:08.649546 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7516 14:00:08.649655
7517 14:00:08.655836 [CATrainingPosCal] consider 1 rank data
7518 14:00:08.655945 u2DelayCellTimex100 = 258/100 ps
7519 14:00:08.662718 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7520 14:00:08.666043 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7521 14:00:08.669331 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7522 14:00:08.672520 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7523 14:00:08.675878 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7524 14:00:08.679372 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7525 14:00:08.679459
7526 14:00:08.682811 CA PerBit enable=1, Macro0, CA PI delay=37
7527 14:00:08.682894
7528 14:00:08.685730 [CBTSetCACLKResult] CA Dly = 37
7529 14:00:08.689121 CS Dly: 11 (0~42)
7530 14:00:08.692513 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 14:00:08.695893 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 14:00:08.695977 ==
7533 14:00:08.699200 Dram Type= 6, Freq= 0, CH_0, rank 1
7534 14:00:08.705935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 14:00:08.706020 ==
7536 14:00:08.709011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 14:00:08.715490 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 14:00:08.718736 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 14:00:08.725364 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 14:00:08.733367 [CA 0] Center 44 (14~75) winsize 62
7541 14:00:08.736948 [CA 1] Center 43 (13~74) winsize 62
7542 14:00:08.739906 [CA 2] Center 39 (10~69) winsize 60
7543 14:00:08.743549 [CA 3] Center 39 (10~69) winsize 60
7544 14:00:08.746791 [CA 4] Center 37 (8~67) winsize 60
7545 14:00:08.750011 [CA 5] Center 37 (7~67) winsize 61
7546 14:00:08.750117
7547 14:00:08.753204 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7548 14:00:08.753279
7549 14:00:08.760135 [CATrainingPosCal] consider 2 rank data
7550 14:00:08.760253 u2DelayCellTimex100 = 258/100 ps
7551 14:00:08.766523 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7552 14:00:08.769772 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7553 14:00:08.773328 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7554 14:00:08.776481 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7555 14:00:08.779932 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7556 14:00:08.783231 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7557 14:00:08.783330
7558 14:00:08.786576 CA PerBit enable=1, Macro0, CA PI delay=37
7559 14:00:08.786651
7560 14:00:08.789895 [CBTSetCACLKResult] CA Dly = 37
7561 14:00:08.792845 CS Dly: 11 (0~43)
7562 14:00:08.796391 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 14:00:08.799793 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 14:00:08.799892
7565 14:00:08.802828 ----->DramcWriteLeveling(PI) begin...
7566 14:00:08.802928 ==
7567 14:00:08.806118 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 14:00:08.812765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 14:00:08.812865 ==
7570 14:00:08.816030 Write leveling (Byte 0): 35 => 35
7571 14:00:08.819528 Write leveling (Byte 1): 27 => 27
7572 14:00:08.822713 DramcWriteLeveling(PI) end<-----
7573 14:00:08.822788
7574 14:00:08.822849 ==
7575 14:00:08.826133 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 14:00:08.829725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 14:00:08.829829 ==
7578 14:00:08.832700 [Gating] SW mode calibration
7579 14:00:08.839269 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7580 14:00:08.842770 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7581 14:00:08.849223 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 14:00:08.852724 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 14:00:08.856059 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 14:00:08.862466 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 14:00:08.865923 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7586 14:00:08.869243 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7587 14:00:08.875942 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
7588 14:00:08.879146 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 14:00:08.882207 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 14:00:08.889122 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 14:00:08.892123 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 14:00:08.895537 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7593 14:00:08.902079 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7594 14:00:08.905626 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7595 14:00:08.908836 1 5 24 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
7596 14:00:08.915491 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 14:00:08.918901 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 14:00:08.922176 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 14:00:08.928885 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 14:00:08.932207 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 14:00:08.935586 1 6 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7602 14:00:08.941992 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7603 14:00:08.945610 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7604 14:00:08.948677 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 14:00:08.955458 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 14:00:08.958646 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 14:00:08.961842 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 14:00:08.968643 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7609 14:00:08.971833 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 14:00:08.975287 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7611 14:00:08.981892 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7612 14:00:08.984976 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 14:00:08.988590 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 14:00:08.994944 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 14:00:08.998621 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 14:00:09.001633 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 14:00:09.008277 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 14:00:09.011791 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 14:00:09.014856 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 14:00:09.021406 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 14:00:09.024943 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 14:00:09.028010 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 14:00:09.034690 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 14:00:09.038108 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7625 14:00:09.041407 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 14:00:09.047939 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 14:00:09.051292 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7628 14:00:09.054441 Total UI for P1: 0, mck2ui 16
7629 14:00:09.057842 best dqsien dly found for B0: ( 1, 9, 16)
7630 14:00:09.061307 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 14:00:09.064424 Total UI for P1: 0, mck2ui 16
7632 14:00:09.067949 best dqsien dly found for B1: ( 1, 9, 24)
7633 14:00:09.071182 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7634 14:00:09.074319 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7635 14:00:09.074420
7636 14:00:09.077834 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7637 14:00:09.084271 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7638 14:00:09.084361 [Gating] SW calibration Done
7639 14:00:09.084425 ==
7640 14:00:09.087625 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 14:00:09.094212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 14:00:09.094296 ==
7643 14:00:09.094360 RX Vref Scan: 0
7644 14:00:09.094420
7645 14:00:09.097470 RX Vref 0 -> 0, step: 1
7646 14:00:09.097591
7647 14:00:09.101017 RX Delay 0 -> 252, step: 8
7648 14:00:09.104283 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7649 14:00:09.107487 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7650 14:00:09.110785 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7651 14:00:09.117621 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7652 14:00:09.120840 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7653 14:00:09.124101 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7654 14:00:09.127613 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7655 14:00:09.130855 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7656 14:00:09.137358 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7657 14:00:09.140617 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7658 14:00:09.144057 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7659 14:00:09.147150 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7660 14:00:09.150707 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7661 14:00:09.157252 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7662 14:00:09.160539 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7663 14:00:09.163852 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7664 14:00:09.163933 ==
7665 14:00:09.167066 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 14:00:09.170430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 14:00:09.173787 ==
7668 14:00:09.173867 DQS Delay:
7669 14:00:09.173930 DQS0 = 0, DQS1 = 0
7670 14:00:09.177217 DQM Delay:
7671 14:00:09.177296 DQM0 = 127, DQM1 = 124
7672 14:00:09.180497 DQ Delay:
7673 14:00:09.183563 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7674 14:00:09.186983 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7675 14:00:09.190565 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7676 14:00:09.193624 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7677 14:00:09.193704
7678 14:00:09.193766
7679 14:00:09.193824 ==
7680 14:00:09.197246 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 14:00:09.200409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 14:00:09.200490 ==
7683 14:00:09.200553
7684 14:00:09.200611
7685 14:00:09.203593 TX Vref Scan disable
7686 14:00:09.207206 == TX Byte 0 ==
7687 14:00:09.210409 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7688 14:00:09.213458 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7689 14:00:09.217014 == TX Byte 1 ==
7690 14:00:09.220437 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7691 14:00:09.223498 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7692 14:00:09.223578 ==
7693 14:00:09.227087 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 14:00:09.233333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 14:00:09.233414 ==
7696 14:00:09.245952
7697 14:00:09.249227 TX Vref early break, caculate TX vref
7698 14:00:09.252358 TX Vref=16, minBit 7, minWin=21, winSum=355
7699 14:00:09.255963 TX Vref=18, minBit 11, minWin=21, winSum=368
7700 14:00:09.259192 TX Vref=20, minBit 8, minWin=21, winSum=377
7701 14:00:09.262159 TX Vref=22, minBit 8, minWin=23, winSum=385
7702 14:00:09.265700 TX Vref=24, minBit 8, minWin=23, winSum=396
7703 14:00:09.272164 TX Vref=26, minBit 4, minWin=24, winSum=404
7704 14:00:09.275752 TX Vref=28, minBit 8, minWin=24, winSum=404
7705 14:00:09.279074 TX Vref=30, minBit 8, minWin=24, winSum=398
7706 14:00:09.282308 TX Vref=32, minBit 8, minWin=23, winSum=391
7707 14:00:09.285717 TX Vref=34, minBit 8, minWin=22, winSum=382
7708 14:00:09.292022 [TxChooseVref] Worse bit 4, Min win 24, Win sum 404, Final Vref 26
7709 14:00:09.292104
7710 14:00:09.295534 Final TX Range 0 Vref 26
7711 14:00:09.295614
7712 14:00:09.295678 ==
7713 14:00:09.298932 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 14:00:09.302209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 14:00:09.302290 ==
7716 14:00:09.302353
7717 14:00:09.302412
7718 14:00:09.305446 TX Vref Scan disable
7719 14:00:09.311955 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7720 14:00:09.312045 == TX Byte 0 ==
7721 14:00:09.315500 u2DelayCellOfst[0]=15 cells (4 PI)
7722 14:00:09.318817 u2DelayCellOfst[1]=18 cells (5 PI)
7723 14:00:09.321966 u2DelayCellOfst[2]=11 cells (3 PI)
7724 14:00:09.325352 u2DelayCellOfst[3]=15 cells (4 PI)
7725 14:00:09.328809 u2DelayCellOfst[4]=7 cells (2 PI)
7726 14:00:09.331927 u2DelayCellOfst[5]=0 cells (0 PI)
7727 14:00:09.335017 u2DelayCellOfst[6]=18 cells (5 PI)
7728 14:00:09.338443 u2DelayCellOfst[7]=18 cells (5 PI)
7729 14:00:09.341569 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7730 14:00:09.345230 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7731 14:00:09.348338 == TX Byte 1 ==
7732 14:00:09.351886 u2DelayCellOfst[8]=0 cells (0 PI)
7733 14:00:09.354999 u2DelayCellOfst[9]=3 cells (1 PI)
7734 14:00:09.355106 u2DelayCellOfst[10]=11 cells (3 PI)
7735 14:00:09.358230 u2DelayCellOfst[11]=7 cells (2 PI)
7736 14:00:09.361348 u2DelayCellOfst[12]=15 cells (4 PI)
7737 14:00:09.365073 u2DelayCellOfst[13]=15 cells (4 PI)
7738 14:00:09.368157 u2DelayCellOfst[14]=18 cells (5 PI)
7739 14:00:09.371525 u2DelayCellOfst[15]=15 cells (4 PI)
7740 14:00:09.377984 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7741 14:00:09.381392 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7742 14:00:09.381524 DramC Write-DBI on
7743 14:00:09.381620 ==
7744 14:00:09.384765 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 14:00:09.391515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 14:00:09.391595 ==
7747 14:00:09.391659
7748 14:00:09.391717
7749 14:00:09.391773 TX Vref Scan disable
7750 14:00:09.395677 == TX Byte 0 ==
7751 14:00:09.398889 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7752 14:00:09.402046 == TX Byte 1 ==
7753 14:00:09.405701 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7754 14:00:09.408684 DramC Write-DBI off
7755 14:00:09.408790
7756 14:00:09.408881 [DATLAT]
7757 14:00:09.408969 Freq=1600, CH0 RK0
7758 14:00:09.409054
7759 14:00:09.411973 DATLAT Default: 0xf
7760 14:00:09.412071 0, 0xFFFF, sum = 0
7761 14:00:09.415748 1, 0xFFFF, sum = 0
7762 14:00:09.418942 2, 0xFFFF, sum = 0
7763 14:00:09.419039 3, 0xFFFF, sum = 0
7764 14:00:09.422248 4, 0xFFFF, sum = 0
7765 14:00:09.422364 5, 0xFFFF, sum = 0
7766 14:00:09.425544 6, 0xFFFF, sum = 0
7767 14:00:09.425626 7, 0xFFFF, sum = 0
7768 14:00:09.428519 8, 0xFFFF, sum = 0
7769 14:00:09.428601 9, 0xFFFF, sum = 0
7770 14:00:09.431900 10, 0xFFFF, sum = 0
7771 14:00:09.431982 11, 0xFFFF, sum = 0
7772 14:00:09.435289 12, 0xFFFF, sum = 0
7773 14:00:09.435400 13, 0xEFFF, sum = 0
7774 14:00:09.438552 14, 0x0, sum = 1
7775 14:00:09.438634 15, 0x0, sum = 2
7776 14:00:09.441969 16, 0x0, sum = 3
7777 14:00:09.442050 17, 0x0, sum = 4
7778 14:00:09.445172 best_step = 15
7779 14:00:09.445252
7780 14:00:09.445316 ==
7781 14:00:09.448311 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 14:00:09.451876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 14:00:09.451957 ==
7784 14:00:09.455181 RX Vref Scan: 1
7785 14:00:09.455301
7786 14:00:09.455393 Set Vref Range= 24 -> 127
7787 14:00:09.455483
7788 14:00:09.458237 RX Vref 24 -> 127, step: 1
7789 14:00:09.458308
7790 14:00:09.461888 RX Delay 11 -> 252, step: 4
7791 14:00:09.461986
7792 14:00:09.465044 Set Vref, RX VrefLevel [Byte0]: 24
7793 14:00:09.468243 [Byte1]: 24
7794 14:00:09.468338
7795 14:00:09.471790 Set Vref, RX VrefLevel [Byte0]: 25
7796 14:00:09.474918 [Byte1]: 25
7797 14:00:09.478476
7798 14:00:09.478588 Set Vref, RX VrefLevel [Byte0]: 26
7799 14:00:09.481444 [Byte1]: 26
7800 14:00:09.485949
7801 14:00:09.486049 Set Vref, RX VrefLevel [Byte0]: 27
7802 14:00:09.489144 [Byte1]: 27
7803 14:00:09.493755
7804 14:00:09.493866 Set Vref, RX VrefLevel [Byte0]: 28
7805 14:00:09.496781 [Byte1]: 28
7806 14:00:09.501095
7807 14:00:09.501198 Set Vref, RX VrefLevel [Byte0]: 29
7808 14:00:09.504335 [Byte1]: 29
7809 14:00:09.508894
7810 14:00:09.509015 Set Vref, RX VrefLevel [Byte0]: 30
7811 14:00:09.512040 [Byte1]: 30
7812 14:00:09.516211
7813 14:00:09.516317 Set Vref, RX VrefLevel [Byte0]: 31
7814 14:00:09.519678 [Byte1]: 31
7815 14:00:09.524103
7816 14:00:09.524214 Set Vref, RX VrefLevel [Byte0]: 32
7817 14:00:09.527172 [Byte1]: 32
7818 14:00:09.531435
7819 14:00:09.531540 Set Vref, RX VrefLevel [Byte0]: 33
7820 14:00:09.534945 [Byte1]: 33
7821 14:00:09.539322
7822 14:00:09.539427 Set Vref, RX VrefLevel [Byte0]: 34
7823 14:00:09.542785 [Byte1]: 34
7824 14:00:09.546930
7825 14:00:09.547044 Set Vref, RX VrefLevel [Byte0]: 35
7826 14:00:09.550088 [Byte1]: 35
7827 14:00:09.554571
7828 14:00:09.554674 Set Vref, RX VrefLevel [Byte0]: 36
7829 14:00:09.557806 [Byte1]: 36
7830 14:00:09.562112
7831 14:00:09.562211 Set Vref, RX VrefLevel [Byte0]: 37
7832 14:00:09.565273 [Byte1]: 37
7833 14:00:09.569723
7834 14:00:09.569829 Set Vref, RX VrefLevel [Byte0]: 38
7835 14:00:09.572964 [Byte1]: 38
7836 14:00:09.577281
7837 14:00:09.577385 Set Vref, RX VrefLevel [Byte0]: 39
7838 14:00:09.580558 [Byte1]: 39
7839 14:00:09.584794
7840 14:00:09.584886 Set Vref, RX VrefLevel [Byte0]: 40
7841 14:00:09.588296 [Byte1]: 40
7842 14:00:09.592592
7843 14:00:09.592697 Set Vref, RX VrefLevel [Byte0]: 41
7844 14:00:09.595891 [Byte1]: 41
7845 14:00:09.600089
7846 14:00:09.600194 Set Vref, RX VrefLevel [Byte0]: 42
7847 14:00:09.603412 [Byte1]: 42
7848 14:00:09.607543
7849 14:00:09.607651 Set Vref, RX VrefLevel [Byte0]: 43
7850 14:00:09.610941 [Byte1]: 43
7851 14:00:09.615477
7852 14:00:09.615674 Set Vref, RX VrefLevel [Byte0]: 44
7853 14:00:09.618629 [Byte1]: 44
7854 14:00:09.623134
7855 14:00:09.623230 Set Vref, RX VrefLevel [Byte0]: 45
7856 14:00:09.626165 [Byte1]: 45
7857 14:00:09.630678
7858 14:00:09.630774 Set Vref, RX VrefLevel [Byte0]: 46
7859 14:00:09.633875 [Byte1]: 46
7860 14:00:09.638385
7861 14:00:09.638473 Set Vref, RX VrefLevel [Byte0]: 47
7862 14:00:09.641585 [Byte1]: 47
7863 14:00:09.645910
7864 14:00:09.646011 Set Vref, RX VrefLevel [Byte0]: 48
7865 14:00:09.649001 [Byte1]: 48
7866 14:00:09.653371
7867 14:00:09.653488 Set Vref, RX VrefLevel [Byte0]: 49
7868 14:00:09.656950 [Byte1]: 49
7869 14:00:09.660924
7870 14:00:09.661037 Set Vref, RX VrefLevel [Byte0]: 50
7871 14:00:09.664581 [Byte1]: 50
7872 14:00:09.668458
7873 14:00:09.668538 Set Vref, RX VrefLevel [Byte0]: 51
7874 14:00:09.672078 [Byte1]: 51
7875 14:00:09.676463
7876 14:00:09.676567 Set Vref, RX VrefLevel [Byte0]: 52
7877 14:00:09.679690 [Byte1]: 52
7878 14:00:09.684114
7879 14:00:09.684194 Set Vref, RX VrefLevel [Byte0]: 53
7880 14:00:09.687102 [Byte1]: 53
7881 14:00:09.691333
7882 14:00:09.691404 Set Vref, RX VrefLevel [Byte0]: 54
7883 14:00:09.694978 [Byte1]: 54
7884 14:00:09.699287
7885 14:00:09.699398 Set Vref, RX VrefLevel [Byte0]: 55
7886 14:00:09.702431 [Byte1]: 55
7887 14:00:09.706651
7888 14:00:09.706750 Set Vref, RX VrefLevel [Byte0]: 56
7889 14:00:09.709802 [Byte1]: 56
7890 14:00:09.714202
7891 14:00:09.714295 Set Vref, RX VrefLevel [Byte0]: 57
7892 14:00:09.717425 [Byte1]: 57
7893 14:00:09.721821
7894 14:00:09.721932 Set Vref, RX VrefLevel [Byte0]: 58
7895 14:00:09.725229 [Byte1]: 58
7896 14:00:09.729615
7897 14:00:09.729695 Set Vref, RX VrefLevel [Byte0]: 59
7898 14:00:09.732817 [Byte1]: 59
7899 14:00:09.737265
7900 14:00:09.737346 Set Vref, RX VrefLevel [Byte0]: 60
7901 14:00:09.740364 [Byte1]: 60
7902 14:00:09.744985
7903 14:00:09.745068 Set Vref, RX VrefLevel [Byte0]: 61
7904 14:00:09.747812 [Byte1]: 61
7905 14:00:09.752213
7906 14:00:09.752296 Set Vref, RX VrefLevel [Byte0]: 62
7907 14:00:09.755566 [Byte1]: 62
7908 14:00:09.759767
7909 14:00:09.759850 Set Vref, RX VrefLevel [Byte0]: 63
7910 14:00:09.763128 [Byte1]: 63
7911 14:00:09.767664
7912 14:00:09.767747 Set Vref, RX VrefLevel [Byte0]: 64
7913 14:00:09.770693 [Byte1]: 64
7914 14:00:09.775032
7915 14:00:09.775127 Set Vref, RX VrefLevel [Byte0]: 65
7916 14:00:09.778690 [Byte1]: 65
7917 14:00:09.782943
7918 14:00:09.783043 Set Vref, RX VrefLevel [Byte0]: 66
7919 14:00:09.786192 [Byte1]: 66
7920 14:00:09.790215
7921 14:00:09.790293 Set Vref, RX VrefLevel [Byte0]: 67
7922 14:00:09.793669 [Byte1]: 67
7923 14:00:09.798257
7924 14:00:09.798364 Set Vref, RX VrefLevel [Byte0]: 68
7925 14:00:09.801452 [Byte1]: 68
7926 14:00:09.805669
7927 14:00:09.805815 Set Vref, RX VrefLevel [Byte0]: 69
7928 14:00:09.808988 [Byte1]: 69
7929 14:00:09.813292
7930 14:00:09.813375 Set Vref, RX VrefLevel [Byte0]: 70
7931 14:00:09.816399 [Byte1]: 70
7932 14:00:09.820834
7933 14:00:09.820918 Set Vref, RX VrefLevel [Byte0]: 71
7934 14:00:09.823984 [Byte1]: 71
7935 14:00:09.828372
7936 14:00:09.828450 Set Vref, RX VrefLevel [Byte0]: 72
7937 14:00:09.831560 [Byte1]: 72
7938 14:00:09.836075
7939 14:00:09.836153 Set Vref, RX VrefLevel [Byte0]: 73
7940 14:00:09.839502 [Byte1]: 73
7941 14:00:09.843718
7942 14:00:09.843795 Set Vref, RX VrefLevel [Byte0]: 74
7943 14:00:09.847096 [Byte1]: 74
7944 14:00:09.851437
7945 14:00:09.851512 Set Vref, RX VrefLevel [Byte0]: 75
7946 14:00:09.854498 [Byte1]: 75
7947 14:00:09.859006
7948 14:00:09.859081 Set Vref, RX VrefLevel [Byte0]: 76
7949 14:00:09.862309 [Byte1]: 76
7950 14:00:09.866400
7951 14:00:09.866483 Final RX Vref Byte 0 = 64 to rank0
7952 14:00:09.869957 Final RX Vref Byte 1 = 62 to rank0
7953 14:00:09.873038 Final RX Vref Byte 0 = 64 to rank1
7954 14:00:09.876375 Final RX Vref Byte 1 = 62 to rank1==
7955 14:00:09.879961 Dram Type= 6, Freq= 0, CH_0, rank 0
7956 14:00:09.886576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 14:00:09.886658 ==
7958 14:00:09.886727 DQS Delay:
7959 14:00:09.886789 DQS0 = 0, DQS1 = 0
7960 14:00:09.889826 DQM Delay:
7961 14:00:09.889895 DQM0 = 126, DQM1 = 120
7962 14:00:09.892972 DQ Delay:
7963 14:00:09.896425 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7964 14:00:09.899476 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7965 14:00:09.902694 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7966 14:00:09.906298 DQ12 =124, DQ13 =126, DQ14 =132, DQ15 =126
7967 14:00:09.906378
7968 14:00:09.906467
7969 14:00:09.906549
7970 14:00:09.909436 [DramC_TX_OE_Calibration] TA2
7971 14:00:09.913045 Original DQ_B0 (3 6) =30, OEN = 27
7972 14:00:09.916129 Original DQ_B1 (3 6) =30, OEN = 27
7973 14:00:09.919763 24, 0x0, End_B0=24 End_B1=24
7974 14:00:09.919846 25, 0x0, End_B0=25 End_B1=25
7975 14:00:09.922846 26, 0x0, End_B0=26 End_B1=26
7976 14:00:09.926400 27, 0x0, End_B0=27 End_B1=27
7977 14:00:09.929566 28, 0x0, End_B0=28 End_B1=28
7978 14:00:09.933017 29, 0x0, End_B0=29 End_B1=29
7979 14:00:09.933101 30, 0x0, End_B0=30 End_B1=30
7980 14:00:09.936487 31, 0x5151, End_B0=30 End_B1=30
7981 14:00:09.939545 Byte0 end_step=30 best_step=27
7982 14:00:09.943078 Byte1 end_step=30 best_step=27
7983 14:00:09.946264 Byte0 TX OE(2T, 0.5T) = (3, 3)
7984 14:00:09.949608 Byte1 TX OE(2T, 0.5T) = (3, 3)
7985 14:00:09.949691
7986 14:00:09.949757
7987 14:00:09.956051 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7988 14:00:09.959497 CH0 RK0: MR19=303, MR18=1515
7989 14:00:09.966110 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
7990 14:00:09.966206
7991 14:00:09.969579 ----->DramcWriteLeveling(PI) begin...
7992 14:00:09.969666 ==
7993 14:00:09.972527 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 14:00:09.976103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 14:00:09.976189 ==
7996 14:00:09.979120 Write leveling (Byte 0): 32 => 32
7997 14:00:09.982701 Write leveling (Byte 1): 29 => 29
7998 14:00:09.985784 DramcWriteLeveling(PI) end<-----
7999 14:00:09.985871
8000 14:00:09.985938 ==
8001 14:00:09.989314 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 14:00:09.992626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 14:00:09.992730 ==
8004 14:00:09.995806 [Gating] SW mode calibration
8005 14:00:10.002513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8006 14:00:10.009125 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8007 14:00:10.012286 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 14:00:10.019133 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 14:00:10.022286 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8010 14:00:10.025420 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8011 14:00:10.032243 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8012 14:00:10.035473 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8013 14:00:10.039086 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 14:00:10.042166 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 14:00:10.048959 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 14:00:10.052126 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 14:00:10.055303 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8018 14:00:10.062075 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8019 14:00:10.065425 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8020 14:00:10.068730 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8021 14:00:10.075332 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 14:00:10.078748 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 14:00:10.082056 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 14:00:10.088899 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 14:00:10.092138 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8026 14:00:10.095296 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8027 14:00:10.101695 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8028 14:00:10.105332 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 14:00:10.108339 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 14:00:10.114983 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 14:00:10.118352 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 14:00:10.121975 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 14:00:10.128273 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8034 14:00:10.131474 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 14:00:10.134721 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8036 14:00:10.141485 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 14:00:10.144947 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 14:00:10.148030 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 14:00:10.154788 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 14:00:10.157945 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 14:00:10.161246 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 14:00:10.167524 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 14:00:10.171042 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 14:00:10.174395 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 14:00:10.180858 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 14:00:10.184148 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 14:00:10.187505 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 14:00:10.194009 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 14:00:10.197292 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8050 14:00:10.200663 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 14:00:10.203942 Total UI for P1: 0, mck2ui 16
8052 14:00:10.207336 best dqsien dly found for B0: ( 1, 9, 8)
8053 14:00:10.214085 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8054 14:00:10.217133 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 14:00:10.220478 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 14:00:10.223727 Total UI for P1: 0, mck2ui 16
8057 14:00:10.227111 best dqsien dly found for B1: ( 1, 9, 16)
8058 14:00:10.230316 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8059 14:00:10.233632 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8060 14:00:10.233718
8061 14:00:10.240301 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8062 14:00:10.243830 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8063 14:00:10.247025 [Gating] SW calibration Done
8064 14:00:10.247127 ==
8065 14:00:10.250231 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 14:00:10.253728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 14:00:10.253814 ==
8068 14:00:10.253879 RX Vref Scan: 0
8069 14:00:10.253944
8070 14:00:10.256811 RX Vref 0 -> 0, step: 1
8071 14:00:10.256919
8072 14:00:10.260042 RX Delay 0 -> 252, step: 8
8073 14:00:10.263295 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8074 14:00:10.266526 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8075 14:00:10.273344 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8076 14:00:10.276446 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8077 14:00:10.279926 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8078 14:00:10.283128 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8079 14:00:10.286539 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8080 14:00:10.293224 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8081 14:00:10.296356 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8082 14:00:10.299559 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8083 14:00:10.302739 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8084 14:00:10.306137 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8085 14:00:10.312871 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8086 14:00:10.315972 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8087 14:00:10.319490 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8088 14:00:10.322737 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8089 14:00:10.322842 ==
8090 14:00:10.325940 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 14:00:10.332952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 14:00:10.333071 ==
8093 14:00:10.333142 DQS Delay:
8094 14:00:10.335825 DQS0 = 0, DQS1 = 0
8095 14:00:10.335921 DQM Delay:
8096 14:00:10.338992 DQM0 = 128, DQM1 = 122
8097 14:00:10.339080 DQ Delay:
8098 14:00:10.342492 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8099 14:00:10.345780 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8100 14:00:10.349157 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8101 14:00:10.352757 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8102 14:00:10.352864
8103 14:00:10.352963
8104 14:00:10.353056 ==
8105 14:00:10.355975 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 14:00:10.362302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 14:00:10.362410 ==
8108 14:00:10.362490
8109 14:00:10.362574
8110 14:00:10.362646 TX Vref Scan disable
8111 14:00:10.365926 == TX Byte 0 ==
8112 14:00:10.369183 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8113 14:00:10.372778 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8114 14:00:10.376014 == TX Byte 1 ==
8115 14:00:10.379184 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8116 14:00:10.382733 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8117 14:00:10.385757 ==
8118 14:00:10.389300 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 14:00:10.392674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 14:00:10.392796 ==
8121 14:00:10.406119
8122 14:00:10.409287 TX Vref early break, caculate TX vref
8123 14:00:10.412546 TX Vref=16, minBit 8, minWin=22, winSum=369
8124 14:00:10.415925 TX Vref=18, minBit 8, minWin=22, winSum=375
8125 14:00:10.419274 TX Vref=20, minBit 1, minWin=23, winSum=389
8126 14:00:10.422497 TX Vref=22, minBit 1, minWin=23, winSum=397
8127 14:00:10.425736 TX Vref=24, minBit 8, minWin=23, winSum=401
8128 14:00:10.432321 TX Vref=26, minBit 0, minWin=25, winSum=409
8129 14:00:10.435738 TX Vref=28, minBit 8, minWin=25, winSum=414
8130 14:00:10.439133 TX Vref=30, minBit 0, minWin=25, winSum=408
8131 14:00:10.442274 TX Vref=32, minBit 8, minWin=22, winSum=397
8132 14:00:10.445738 TX Vref=34, minBit 3, minWin=24, winSum=396
8133 14:00:10.448961 TX Vref=36, minBit 8, minWin=22, winSum=384
8134 14:00:10.455504 [TxChooseVref] Worse bit 8, Min win 25, Win sum 414, Final Vref 28
8135 14:00:10.455617
8136 14:00:10.458947 Final TX Range 0 Vref 28
8137 14:00:10.459034
8138 14:00:10.459100 ==
8139 14:00:10.462058 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 14:00:10.465337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 14:00:10.465453 ==
8142 14:00:10.465538
8143 14:00:10.468869
8144 14:00:10.468954 TX Vref Scan disable
8145 14:00:10.475494 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8146 14:00:10.475592 == TX Byte 0 ==
8147 14:00:10.478712 u2DelayCellOfst[0]=11 cells (3 PI)
8148 14:00:10.481951 u2DelayCellOfst[1]=18 cells (5 PI)
8149 14:00:10.485487 u2DelayCellOfst[2]=7 cells (2 PI)
8150 14:00:10.488735 u2DelayCellOfst[3]=11 cells (3 PI)
8151 14:00:10.492155 u2DelayCellOfst[4]=7 cells (2 PI)
8152 14:00:10.495332 u2DelayCellOfst[5]=0 cells (0 PI)
8153 14:00:10.498531 u2DelayCellOfst[6]=18 cells (5 PI)
8154 14:00:10.501832 u2DelayCellOfst[7]=18 cells (5 PI)
8155 14:00:10.505281 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8156 14:00:10.508544 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8157 14:00:10.511740 == TX Byte 1 ==
8158 14:00:10.515216 u2DelayCellOfst[8]=0 cells (0 PI)
8159 14:00:10.518377 u2DelayCellOfst[9]=3 cells (1 PI)
8160 14:00:10.521954 u2DelayCellOfst[10]=11 cells (3 PI)
8161 14:00:10.525057 u2DelayCellOfst[11]=7 cells (2 PI)
8162 14:00:10.525177 u2DelayCellOfst[12]=15 cells (4 PI)
8163 14:00:10.528213 u2DelayCellOfst[13]=15 cells (4 PI)
8164 14:00:10.531858 u2DelayCellOfst[14]=15 cells (4 PI)
8165 14:00:10.535050 u2DelayCellOfst[15]=11 cells (3 PI)
8166 14:00:10.541552 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8167 14:00:10.544977 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8168 14:00:10.545074 DramC Write-DBI on
8169 14:00:10.548193 ==
8170 14:00:10.551648 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 14:00:10.554734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 14:00:10.554831 ==
8173 14:00:10.554898
8174 14:00:10.554960
8175 14:00:10.558264 TX Vref Scan disable
8176 14:00:10.558351 == TX Byte 0 ==
8177 14:00:10.564794 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8178 14:00:10.564910 == TX Byte 1 ==
8179 14:00:10.568082 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8180 14:00:10.571331 DramC Write-DBI off
8181 14:00:10.571449
8182 14:00:10.571543 [DATLAT]
8183 14:00:10.574911 Freq=1600, CH0 RK1
8184 14:00:10.575001
8185 14:00:10.575067 DATLAT Default: 0xf
8186 14:00:10.578048 0, 0xFFFF, sum = 0
8187 14:00:10.578140 1, 0xFFFF, sum = 0
8188 14:00:10.581230 2, 0xFFFF, sum = 0
8189 14:00:10.581321 3, 0xFFFF, sum = 0
8190 14:00:10.584621 4, 0xFFFF, sum = 0
8191 14:00:10.584717 5, 0xFFFF, sum = 0
8192 14:00:10.588088 6, 0xFFFF, sum = 0
8193 14:00:10.588185 7, 0xFFFF, sum = 0
8194 14:00:10.591281 8, 0xFFFF, sum = 0
8195 14:00:10.594561 9, 0xFFFF, sum = 0
8196 14:00:10.594657 10, 0xFFFF, sum = 0
8197 14:00:10.597743 11, 0xFFFF, sum = 0
8198 14:00:10.597837 12, 0xFFFF, sum = 0
8199 14:00:10.601280 13, 0xCFFF, sum = 0
8200 14:00:10.601401 14, 0x0, sum = 1
8201 14:00:10.604611 15, 0x0, sum = 2
8202 14:00:10.604703 16, 0x0, sum = 3
8203 14:00:10.607927 17, 0x0, sum = 4
8204 14:00:10.608022 best_step = 15
8205 14:00:10.608088
8206 14:00:10.608148 ==
8207 14:00:10.611058 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 14:00:10.614278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 14:00:10.614372 ==
8210 14:00:10.617764 RX Vref Scan: 0
8211 14:00:10.617863
8212 14:00:10.620895 RX Vref 0 -> 0, step: 1
8213 14:00:10.620983
8214 14:00:10.621049 RX Delay 3 -> 252, step: 4
8215 14:00:10.628138 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8216 14:00:10.631324 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8217 14:00:10.634880 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8218 14:00:10.638105 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8219 14:00:10.644745 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8220 14:00:10.647980 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8221 14:00:10.651202 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8222 14:00:10.654424 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8223 14:00:10.657838 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8224 14:00:10.660953 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8225 14:00:10.667558 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8226 14:00:10.670784 iDelay=191, Bit 11, Center 110 (55 ~ 166) 112
8227 14:00:10.674165 iDelay=191, Bit 12, Center 122 (67 ~ 178) 112
8228 14:00:10.677771 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8229 14:00:10.684112 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8230 14:00:10.687486 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8231 14:00:10.687575 ==
8232 14:00:10.690897 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 14:00:10.694158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 14:00:10.694269 ==
8235 14:00:10.697516 DQS Delay:
8236 14:00:10.697626 DQS0 = 0, DQS1 = 0
8237 14:00:10.697722 DQM Delay:
8238 14:00:10.700677 DQM0 = 124, DQM1 = 117
8239 14:00:10.700783 DQ Delay:
8240 14:00:10.703997 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8241 14:00:10.707502 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8242 14:00:10.710674 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =110
8243 14:00:10.717213 DQ12 =122, DQ13 =122, DQ14 =128, DQ15 =124
8244 14:00:10.717347
8245 14:00:10.717457
8246 14:00:10.717538
8247 14:00:10.720865 [DramC_TX_OE_Calibration] TA2
8248 14:00:10.724128 Original DQ_B0 (3 6) =30, OEN = 27
8249 14:00:10.724236 Original DQ_B1 (3 6) =30, OEN = 27
8250 14:00:10.727190 24, 0x0, End_B0=24 End_B1=24
8251 14:00:10.730843 25, 0x0, End_B0=25 End_B1=25
8252 14:00:10.734008 26, 0x0, End_B0=26 End_B1=26
8253 14:00:10.737271 27, 0x0, End_B0=27 End_B1=27
8254 14:00:10.737379 28, 0x0, End_B0=28 End_B1=28
8255 14:00:10.740877 29, 0x0, End_B0=29 End_B1=29
8256 14:00:10.744110 30, 0x0, End_B0=30 End_B1=30
8257 14:00:10.747475 31, 0x4545, End_B0=30 End_B1=30
8258 14:00:10.750653 Byte0 end_step=30 best_step=27
8259 14:00:10.750730 Byte1 end_step=30 best_step=27
8260 14:00:10.754065 Byte0 TX OE(2T, 0.5T) = (3, 3)
8261 14:00:10.757324 Byte1 TX OE(2T, 0.5T) = (3, 3)
8262 14:00:10.757434
8263 14:00:10.757524
8264 14:00:10.767158 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8265 14:00:10.767247 CH0 RK1: MR19=303, MR18=220F
8266 14:00:10.773975 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8267 14:00:10.777172 [RxdqsGatingPostProcess] freq 1600
8268 14:00:10.783833 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8269 14:00:10.787164 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 14:00:10.790323 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 14:00:10.793562 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 14:00:10.797046 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 14:00:10.800433 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 14:00:10.800554 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 14:00:10.803820 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 14:00:10.807152 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 14:00:10.810529 Pre-setting of DQS Precalculation
8278 14:00:10.816831 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8279 14:00:10.816949 ==
8280 14:00:10.820095 Dram Type= 6, Freq= 0, CH_1, rank 0
8281 14:00:10.823588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 14:00:10.823691 ==
8283 14:00:10.830121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8284 14:00:10.833589 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8285 14:00:10.836896 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8286 14:00:10.843553 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8287 14:00:10.852219 [CA 0] Center 41 (12~70) winsize 59
8288 14:00:10.855713 [CA 1] Center 42 (12~72) winsize 61
8289 14:00:10.859198 [CA 2] Center 37 (9~66) winsize 58
8290 14:00:10.862352 [CA 3] Center 36 (7~66) winsize 60
8291 14:00:10.865496 [CA 4] Center 37 (8~67) winsize 60
8292 14:00:10.869133 [CA 5] Center 36 (7~66) winsize 60
8293 14:00:10.869236
8294 14:00:10.872186 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8295 14:00:10.872298
8296 14:00:10.875555 [CATrainingPosCal] consider 1 rank data
8297 14:00:10.878792 u2DelayCellTimex100 = 258/100 ps
8298 14:00:10.882292 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8299 14:00:10.888805 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8300 14:00:10.892270 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8301 14:00:10.895587 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8302 14:00:10.898984 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8303 14:00:10.902066 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8304 14:00:10.902176
8305 14:00:10.905575 CA PerBit enable=1, Macro0, CA PI delay=36
8306 14:00:10.905652
8307 14:00:10.908806 [CBTSetCACLKResult] CA Dly = 36
8308 14:00:10.912239 CS Dly: 10 (0~41)
8309 14:00:10.915277 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8310 14:00:10.918915 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8311 14:00:10.919021 ==
8312 14:00:10.922106 Dram Type= 6, Freq= 0, CH_1, rank 1
8313 14:00:10.925292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 14:00:10.928905 ==
8315 14:00:10.932215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 14:00:10.935358 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 14:00:10.941837 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 14:00:10.945331 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 14:00:10.955472 [CA 0] Center 41 (12~71) winsize 60
8320 14:00:10.959001 [CA 1] Center 42 (12~72) winsize 61
8321 14:00:10.962163 [CA 2] Center 37 (8~67) winsize 60
8322 14:00:10.965327 [CA 3] Center 36 (7~66) winsize 60
8323 14:00:10.968948 [CA 4] Center 37 (7~67) winsize 61
8324 14:00:10.972046 [CA 5] Center 36 (6~66) winsize 61
8325 14:00:10.972148
8326 14:00:10.975249 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8327 14:00:10.975357
8328 14:00:10.978797 [CATrainingPosCal] consider 2 rank data
8329 14:00:10.982142 u2DelayCellTimex100 = 258/100 ps
8330 14:00:10.985430 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8331 14:00:10.992071 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8332 14:00:10.995599 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8333 14:00:10.998764 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8334 14:00:11.002185 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8335 14:00:11.005523 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8336 14:00:11.005605
8337 14:00:11.008731 CA PerBit enable=1, Macro0, CA PI delay=36
8338 14:00:11.008814
8339 14:00:11.012104 [CBTSetCACLKResult] CA Dly = 36
8340 14:00:11.015401 CS Dly: 11 (0~43)
8341 14:00:11.018785 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 14:00:11.021789 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 14:00:11.021904
8344 14:00:11.025127 ----->DramcWriteLeveling(PI) begin...
8345 14:00:11.025210 ==
8346 14:00:11.028670 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 14:00:11.034951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 14:00:11.035035 ==
8349 14:00:11.038618 Write leveling (Byte 0): 24 => 24
8350 14:00:11.038699 Write leveling (Byte 1): 31 => 31
8351 14:00:11.041786 DramcWriteLeveling(PI) end<-----
8352 14:00:11.041943
8353 14:00:11.042036 ==
8354 14:00:11.045079 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 14:00:11.051576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 14:00:11.051678 ==
8357 14:00:11.054770 [Gating] SW mode calibration
8358 14:00:11.061661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8359 14:00:11.064634 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8360 14:00:11.071377 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8361 14:00:11.074752 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 14:00:11.078159 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 14:00:11.084757 1 4 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8364 14:00:11.087935 1 4 16 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
8365 14:00:11.091167 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 14:00:11.097805 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 14:00:11.100973 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 14:00:11.104163 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 14:00:11.110855 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 14:00:11.114209 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 14:00:11.117615 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8372 14:00:11.124188 1 5 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8373 14:00:11.127218 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8374 14:00:11.130612 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 14:00:11.137234 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 14:00:11.140775 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 14:00:11.143984 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 14:00:11.150704 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 14:00:11.153911 1 6 12 | B1->B0 | 2a2a 2626 | 0 1 | (0 0) (0 0)
8380 14:00:11.157393 1 6 16 | B1->B0 | 4545 4444 | 1 0 | (0 0) (0 0)
8381 14:00:11.163992 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 14:00:11.167158 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 14:00:11.170516 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 14:00:11.177273 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 14:00:11.180361 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 14:00:11.183819 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 14:00:11.190342 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 14:00:11.193508 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8389 14:00:11.197026 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8390 14:00:11.203418 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 14:00:11.206868 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 14:00:11.209827 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 14:00:11.216489 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 14:00:11.219735 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 14:00:11.223240 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 14:00:11.229852 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 14:00:11.233190 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 14:00:11.236470 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 14:00:11.243056 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 14:00:11.246716 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 14:00:11.249805 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 14:00:11.256069 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 14:00:11.259573 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8404 14:00:11.262785 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8405 14:00:11.269331 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8406 14:00:11.269419 Total UI for P1: 0, mck2ui 16
8407 14:00:11.276191 best dqsien dly found for B0: ( 1, 9, 14)
8408 14:00:11.279418 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 14:00:11.282859 Total UI for P1: 0, mck2ui 16
8410 14:00:11.285987 best dqsien dly found for B1: ( 1, 9, 18)
8411 14:00:11.289113 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8412 14:00:11.292658 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8413 14:00:11.292741
8414 14:00:11.295887 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8415 14:00:11.299241 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8416 14:00:11.302597 [Gating] SW calibration Done
8417 14:00:11.302721 ==
8418 14:00:11.305557 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 14:00:11.309129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 14:00:11.312290 ==
8421 14:00:11.312432 RX Vref Scan: 0
8422 14:00:11.312531
8423 14:00:11.315773 RX Vref 0 -> 0, step: 1
8424 14:00:11.315906
8425 14:00:11.318993 RX Delay 0 -> 252, step: 8
8426 14:00:11.322363 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8427 14:00:11.325613 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8428 14:00:11.328759 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8429 14:00:11.332270 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8430 14:00:11.338589 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8431 14:00:11.342072 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8432 14:00:11.345512 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8433 14:00:11.348526 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8434 14:00:11.351961 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8435 14:00:11.358637 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8436 14:00:11.361758 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8437 14:00:11.365316 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8438 14:00:11.368551 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8439 14:00:11.371751 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8440 14:00:11.378208 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8441 14:00:11.381450 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8442 14:00:11.381558 ==
8443 14:00:11.384914 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 14:00:11.388277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 14:00:11.388380 ==
8446 14:00:11.391555 DQS Delay:
8447 14:00:11.391644 DQS0 = 0, DQS1 = 0
8448 14:00:11.391709 DQM Delay:
8449 14:00:11.394876 DQM0 = 130, DQM1 = 126
8450 14:00:11.394959 DQ Delay:
8451 14:00:11.398250 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8452 14:00:11.401383 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =127
8453 14:00:11.408092 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8454 14:00:11.411194 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8455 14:00:11.411305
8456 14:00:11.411381
8457 14:00:11.411441 ==
8458 14:00:11.414742 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 14:00:11.418126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 14:00:11.418212 ==
8461 14:00:11.418277
8462 14:00:11.418383
8463 14:00:11.421387 TX Vref Scan disable
8464 14:00:11.424769 == TX Byte 0 ==
8465 14:00:11.428049 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8466 14:00:11.431501 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8467 14:00:11.434510 == TX Byte 1 ==
8468 14:00:11.437816 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8469 14:00:11.441177 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8470 14:00:11.441297 ==
8471 14:00:11.444587 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 14:00:11.447861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 14:00:11.450847 ==
8474 14:00:11.462808
8475 14:00:11.465958 TX Vref early break, caculate TX vref
8476 14:00:11.469077 TX Vref=16, minBit 8, minWin=20, winSum=357
8477 14:00:11.472698 TX Vref=18, minBit 11, minWin=20, winSum=369
8478 14:00:11.475777 TX Vref=20, minBit 8, minWin=22, winSum=375
8479 14:00:11.479324 TX Vref=22, minBit 8, minWin=22, winSum=386
8480 14:00:11.482535 TX Vref=24, minBit 1, minWin=24, winSum=399
8481 14:00:11.489139 TX Vref=26, minBit 5, minWin=24, winSum=405
8482 14:00:11.492281 TX Vref=28, minBit 0, minWin=25, winSum=411
8483 14:00:11.495867 TX Vref=30, minBit 8, minWin=23, winSum=404
8484 14:00:11.499048 TX Vref=32, minBit 8, minWin=23, winSum=399
8485 14:00:11.502532 TX Vref=34, minBit 0, minWin=23, winSum=388
8486 14:00:11.508937 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 28
8487 14:00:11.509044
8488 14:00:11.512376 Final TX Range 0 Vref 28
8489 14:00:11.512450
8490 14:00:11.512538 ==
8491 14:00:11.515767 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 14:00:11.518918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 14:00:11.519003 ==
8494 14:00:11.519068
8495 14:00:11.519128
8496 14:00:11.522217 TX Vref Scan disable
8497 14:00:11.528966 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8498 14:00:11.529050 == TX Byte 0 ==
8499 14:00:11.532151 u2DelayCellOfst[0]=22 cells (6 PI)
8500 14:00:11.535280 u2DelayCellOfst[1]=18 cells (5 PI)
8501 14:00:11.538859 u2DelayCellOfst[2]=0 cells (0 PI)
8502 14:00:11.542078 u2DelayCellOfst[3]=7 cells (2 PI)
8503 14:00:11.545433 u2DelayCellOfst[4]=7 cells (2 PI)
8504 14:00:11.548677 u2DelayCellOfst[5]=26 cells (7 PI)
8505 14:00:11.552094 u2DelayCellOfst[6]=22 cells (6 PI)
8506 14:00:11.555402 u2DelayCellOfst[7]=7 cells (2 PI)
8507 14:00:11.558827 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8508 14:00:11.561847 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8509 14:00:11.565351 == TX Byte 1 ==
8510 14:00:11.565467 u2DelayCellOfst[8]=0 cells (0 PI)
8511 14:00:11.568579 u2DelayCellOfst[9]=7 cells (2 PI)
8512 14:00:11.571967 u2DelayCellOfst[10]=11 cells (3 PI)
8513 14:00:11.575128 u2DelayCellOfst[11]=3 cells (1 PI)
8514 14:00:11.578770 u2DelayCellOfst[12]=11 cells (3 PI)
8515 14:00:11.581888 u2DelayCellOfst[13]=15 cells (4 PI)
8516 14:00:11.585082 u2DelayCellOfst[14]=18 cells (5 PI)
8517 14:00:11.588633 u2DelayCellOfst[15]=15 cells (4 PI)
8518 14:00:11.591726 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8519 14:00:11.598674 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8520 14:00:11.598764 DramC Write-DBI on
8521 14:00:11.598829 ==
8522 14:00:11.601728 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 14:00:11.605248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 14:00:11.608293 ==
8525 14:00:11.608372
8526 14:00:11.608434
8527 14:00:11.608499 TX Vref Scan disable
8528 14:00:11.612098 == TX Byte 0 ==
8529 14:00:11.615423 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8530 14:00:11.618715 == TX Byte 1 ==
8531 14:00:11.622019 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8532 14:00:11.625152 DramC Write-DBI off
8533 14:00:11.625275
8534 14:00:11.625367 [DATLAT]
8535 14:00:11.625458 Freq=1600, CH1 RK0
8536 14:00:11.625541
8537 14:00:11.628501 DATLAT Default: 0xf
8538 14:00:11.628581 0, 0xFFFF, sum = 0
8539 14:00:11.631717 1, 0xFFFF, sum = 0
8540 14:00:11.635209 2, 0xFFFF, sum = 0
8541 14:00:11.635297 3, 0xFFFF, sum = 0
8542 14:00:11.638476 4, 0xFFFF, sum = 0
8543 14:00:11.638560 5, 0xFFFF, sum = 0
8544 14:00:11.641678 6, 0xFFFF, sum = 0
8545 14:00:11.641751 7, 0xFFFF, sum = 0
8546 14:00:11.645226 8, 0xFFFF, sum = 0
8547 14:00:11.645342 9, 0xFFFF, sum = 0
8548 14:00:11.648401 10, 0xFFFF, sum = 0
8549 14:00:11.648481 11, 0xFFFF, sum = 0
8550 14:00:11.651958 12, 0xFFFF, sum = 0
8551 14:00:11.652043 13, 0x8FFF, sum = 0
8552 14:00:11.655043 14, 0x0, sum = 1
8553 14:00:11.655122 15, 0x0, sum = 2
8554 14:00:11.658612 16, 0x0, sum = 3
8555 14:00:11.658694 17, 0x0, sum = 4
8556 14:00:11.661723 best_step = 15
8557 14:00:11.661805
8558 14:00:11.661866 ==
8559 14:00:11.665109 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 14:00:11.668529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 14:00:11.668619 ==
8562 14:00:11.671814 RX Vref Scan: 1
8563 14:00:11.671904
8564 14:00:11.671980 Set Vref Range= 24 -> 127
8565 14:00:11.672044
8566 14:00:11.675035 RX Vref 24 -> 127, step: 1
8567 14:00:11.675111
8568 14:00:11.678156 RX Delay 11 -> 252, step: 4
8569 14:00:11.678230
8570 14:00:11.681518 Set Vref, RX VrefLevel [Byte0]: 24
8571 14:00:11.685039 [Byte1]: 24
8572 14:00:11.685147
8573 14:00:11.688292 Set Vref, RX VrefLevel [Byte0]: 25
8574 14:00:11.691592 [Byte1]: 25
8575 14:00:11.694984
8576 14:00:11.695059 Set Vref, RX VrefLevel [Byte0]: 26
8577 14:00:11.698207 [Byte1]: 26
8578 14:00:11.702249
8579 14:00:11.702338 Set Vref, RX VrefLevel [Byte0]: 27
8580 14:00:11.705581 [Byte1]: 27
8581 14:00:11.709869
8582 14:00:11.709945 Set Vref, RX VrefLevel [Byte0]: 28
8583 14:00:11.713308 [Byte1]: 28
8584 14:00:11.717578
8585 14:00:11.717679 Set Vref, RX VrefLevel [Byte0]: 29
8586 14:00:11.720761 [Byte1]: 29
8587 14:00:11.725334
8588 14:00:11.725435 Set Vref, RX VrefLevel [Byte0]: 30
8589 14:00:11.728604 [Byte1]: 30
8590 14:00:11.732744
8591 14:00:11.732829 Set Vref, RX VrefLevel [Byte0]: 31
8592 14:00:11.736003 [Byte1]: 31
8593 14:00:11.740441
8594 14:00:11.740547 Set Vref, RX VrefLevel [Byte0]: 32
8595 14:00:11.743870 [Byte1]: 32
8596 14:00:11.748214
8597 14:00:11.748305 Set Vref, RX VrefLevel [Byte0]: 33
8598 14:00:11.751424 [Byte1]: 33
8599 14:00:11.755795
8600 14:00:11.755899 Set Vref, RX VrefLevel [Byte0]: 34
8601 14:00:11.759018 [Byte1]: 34
8602 14:00:11.763232
8603 14:00:11.763337 Set Vref, RX VrefLevel [Byte0]: 35
8604 14:00:11.766691 [Byte1]: 35
8605 14:00:11.770990
8606 14:00:11.771103 Set Vref, RX VrefLevel [Byte0]: 36
8607 14:00:11.774107 [Byte1]: 36
8608 14:00:11.778723
8609 14:00:11.778822 Set Vref, RX VrefLevel [Byte0]: 37
8610 14:00:11.781795 [Byte1]: 37
8611 14:00:11.786233
8612 14:00:11.786371 Set Vref, RX VrefLevel [Byte0]: 38
8613 14:00:11.789602 [Byte1]: 38
8614 14:00:11.793943
8615 14:00:11.794036 Set Vref, RX VrefLevel [Byte0]: 39
8616 14:00:11.797052 [Byte1]: 39
8617 14:00:11.801590
8618 14:00:11.801689 Set Vref, RX VrefLevel [Byte0]: 40
8619 14:00:11.804710 [Byte1]: 40
8620 14:00:11.809067
8621 14:00:11.809167 Set Vref, RX VrefLevel [Byte0]: 41
8622 14:00:11.812685 [Byte1]: 41
8623 14:00:11.816815
8624 14:00:11.816896 Set Vref, RX VrefLevel [Byte0]: 42
8625 14:00:11.819857 [Byte1]: 42
8626 14:00:11.824444
8627 14:00:11.824528 Set Vref, RX VrefLevel [Byte0]: 43
8628 14:00:11.827784 [Byte1]: 43
8629 14:00:11.832006
8630 14:00:11.832089 Set Vref, RX VrefLevel [Byte0]: 44
8631 14:00:11.835406 [Byte1]: 44
8632 14:00:11.839502
8633 14:00:11.839585 Set Vref, RX VrefLevel [Byte0]: 45
8634 14:00:11.842644 [Byte1]: 45
8635 14:00:11.847277
8636 14:00:11.847374 Set Vref, RX VrefLevel [Byte0]: 46
8637 14:00:11.850509 [Byte1]: 46
8638 14:00:11.854796
8639 14:00:11.854879 Set Vref, RX VrefLevel [Byte0]: 47
8640 14:00:11.857936 [Byte1]: 47
8641 14:00:11.862287
8642 14:00:11.862367 Set Vref, RX VrefLevel [Byte0]: 48
8643 14:00:11.865416 [Byte1]: 48
8644 14:00:11.869814
8645 14:00:11.869947 Set Vref, RX VrefLevel [Byte0]: 49
8646 14:00:11.873248 [Byte1]: 49
8647 14:00:11.877334
8648 14:00:11.877467 Set Vref, RX VrefLevel [Byte0]: 50
8649 14:00:11.880782 [Byte1]: 50
8650 14:00:11.885216
8651 14:00:11.885318 Set Vref, RX VrefLevel [Byte0]: 51
8652 14:00:11.888454 [Byte1]: 51
8653 14:00:11.892753
8654 14:00:11.892829 Set Vref, RX VrefLevel [Byte0]: 52
8655 14:00:11.895822 [Byte1]: 52
8656 14:00:11.900201
8657 14:00:11.900305 Set Vref, RX VrefLevel [Byte0]: 53
8658 14:00:11.903847 [Byte1]: 53
8659 14:00:11.907816
8660 14:00:11.907917 Set Vref, RX VrefLevel [Byte0]: 54
8661 14:00:11.911278 [Byte1]: 54
8662 14:00:11.915554
8663 14:00:11.915633 Set Vref, RX VrefLevel [Byte0]: 55
8664 14:00:11.919018 [Byte1]: 55
8665 14:00:11.923184
8666 14:00:11.923274 Set Vref, RX VrefLevel [Byte0]: 56
8667 14:00:11.926269 [Byte1]: 56
8668 14:00:11.930829
8669 14:00:11.930906 Set Vref, RX VrefLevel [Byte0]: 57
8670 14:00:11.934222 [Byte1]: 57
8671 14:00:11.938285
8672 14:00:11.938363 Set Vref, RX VrefLevel [Byte0]: 58
8673 14:00:11.941724 [Byte1]: 58
8674 14:00:11.946019
8675 14:00:11.946102 Set Vref, RX VrefLevel [Byte0]: 59
8676 14:00:11.949366 [Byte1]: 59
8677 14:00:11.953560
8678 14:00:11.953638 Set Vref, RX VrefLevel [Byte0]: 60
8679 14:00:11.956819 [Byte1]: 60
8680 14:00:11.961145
8681 14:00:11.961242 Set Vref, RX VrefLevel [Byte0]: 61
8682 14:00:11.964782 [Byte1]: 61
8683 14:00:11.968848
8684 14:00:11.968928 Set Vref, RX VrefLevel [Byte0]: 62
8685 14:00:11.972036 [Byte1]: 62
8686 14:00:11.976736
8687 14:00:11.976818 Set Vref, RX VrefLevel [Byte0]: 63
8688 14:00:11.979927 [Byte1]: 63
8689 14:00:11.984285
8690 14:00:11.984367 Set Vref, RX VrefLevel [Byte0]: 64
8691 14:00:11.987428 [Byte1]: 64
8692 14:00:11.991788
8693 14:00:11.991868 Set Vref, RX VrefLevel [Byte0]: 65
8694 14:00:11.994908 [Byte1]: 65
8695 14:00:11.999209
8696 14:00:11.999306 Set Vref, RX VrefLevel [Byte0]: 66
8697 14:00:12.002878 [Byte1]: 66
8698 14:00:12.006920
8699 14:00:12.007001 Set Vref, RX VrefLevel [Byte0]: 67
8700 14:00:12.010011 [Byte1]: 67
8701 14:00:12.014713
8702 14:00:12.014793 Set Vref, RX VrefLevel [Byte0]: 68
8703 14:00:12.017789 [Byte1]: 68
8704 14:00:12.022015
8705 14:00:12.022100 Set Vref, RX VrefLevel [Byte0]: 69
8706 14:00:12.025582 [Byte1]: 69
8707 14:00:12.029716
8708 14:00:12.029796 Set Vref, RX VrefLevel [Byte0]: 70
8709 14:00:12.033236 [Byte1]: 70
8710 14:00:12.037431
8711 14:00:12.037550 Set Vref, RX VrefLevel [Byte0]: 71
8712 14:00:12.040514 [Byte1]: 71
8713 14:00:12.044865
8714 14:00:12.044962 Final RX Vref Byte 0 = 57 to rank0
8715 14:00:12.048162 Final RX Vref Byte 1 = 53 to rank0
8716 14:00:12.051706 Final RX Vref Byte 0 = 57 to rank1
8717 14:00:12.055028 Final RX Vref Byte 1 = 53 to rank1==
8718 14:00:12.058129 Dram Type= 6, Freq= 0, CH_1, rank 0
8719 14:00:12.064783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 14:00:12.064865 ==
8721 14:00:12.064975 DQS Delay:
8722 14:00:12.065050 DQS0 = 0, DQS1 = 0
8723 14:00:12.068129 DQM Delay:
8724 14:00:12.068209 DQM0 = 130, DQM1 = 123
8725 14:00:12.071853 DQ Delay:
8726 14:00:12.074917 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8727 14:00:12.078113 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8728 14:00:12.081609 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8729 14:00:12.084759 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8730 14:00:12.084879
8731 14:00:12.084942
8732 14:00:12.085001
8733 14:00:12.087985 [DramC_TX_OE_Calibration] TA2
8734 14:00:12.091212 Original DQ_B0 (3 6) =30, OEN = 27
8735 14:00:12.094736 Original DQ_B1 (3 6) =30, OEN = 27
8736 14:00:12.097846 24, 0x0, End_B0=24 End_B1=24
8737 14:00:12.097930 25, 0x0, End_B0=25 End_B1=25
8738 14:00:12.101275 26, 0x0, End_B0=26 End_B1=26
8739 14:00:12.104411 27, 0x0, End_B0=27 End_B1=27
8740 14:00:12.107893 28, 0x0, End_B0=28 End_B1=28
8741 14:00:12.111399 29, 0x0, End_B0=29 End_B1=29
8742 14:00:12.111488 30, 0x0, End_B0=30 End_B1=30
8743 14:00:12.114459 31, 0x4141, End_B0=30 End_B1=30
8744 14:00:12.117758 Byte0 end_step=30 best_step=27
8745 14:00:12.121432 Byte1 end_step=30 best_step=27
8746 14:00:12.124641 Byte0 TX OE(2T, 0.5T) = (3, 3)
8747 14:00:12.127769 Byte1 TX OE(2T, 0.5T) = (3, 3)
8748 14:00:12.127846
8749 14:00:12.127929
8750 14:00:12.134638 [DQSOSCAuto] RK0, (LSB)MR18= 0x90d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8751 14:00:12.137733 CH1 RK0: MR19=303, MR18=90D
8752 14:00:12.144544 CH1_RK0: MR19=0x303, MR18=0x90D, DQSOSC=403, MR23=63, INC=22, DEC=15
8753 14:00:12.144629
8754 14:00:12.148049 ----->DramcWriteLeveling(PI) begin...
8755 14:00:12.148131 ==
8756 14:00:12.151107 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 14:00:12.154555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 14:00:12.154632 ==
8759 14:00:12.157756 Write leveling (Byte 0): 23 => 23
8760 14:00:12.161001 Write leveling (Byte 1): 30 => 30
8761 14:00:12.164536 DramcWriteLeveling(PI) end<-----
8762 14:00:12.164618
8763 14:00:12.164697 ==
8764 14:00:12.167749 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 14:00:12.171078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 14:00:12.171153 ==
8767 14:00:12.174191 [Gating] SW mode calibration
8768 14:00:12.180819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8769 14:00:12.187327 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8770 14:00:12.190902 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 14:00:12.194084 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 14:00:12.200647 1 4 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8773 14:00:12.203838 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8774 14:00:12.207272 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 14:00:12.213866 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 14:00:12.217143 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 14:00:12.220521 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 14:00:12.227173 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 14:00:12.230250 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8780 14:00:12.233803 1 5 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
8781 14:00:12.240403 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (1 0)
8782 14:00:12.243680 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 14:00:12.246970 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 14:00:12.253536 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 14:00:12.256986 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 14:00:12.260120 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 14:00:12.266838 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 14:00:12.269901 1 6 8 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
8789 14:00:12.273427 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 14:00:12.279974 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 14:00:12.283531 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 14:00:12.286556 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 14:00:12.293178 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 14:00:12.296610 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 14:00:12.299786 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 14:00:12.306329 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8797 14:00:12.309798 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8798 14:00:12.313043 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 14:00:12.319779 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 14:00:12.322819 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 14:00:12.326195 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 14:00:12.333129 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 14:00:12.336306 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 14:00:12.339575 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 14:00:12.346368 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 14:00:12.349466 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 14:00:12.352796 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 14:00:12.359291 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 14:00:12.362858 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 14:00:12.366201 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 14:00:12.372794 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 14:00:12.375970 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8813 14:00:12.379313 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8814 14:00:12.382790 Total UI for P1: 0, mck2ui 16
8815 14:00:12.385825 best dqsien dly found for B0: ( 1, 9, 6)
8816 14:00:12.392551 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 14:00:12.392655 Total UI for P1: 0, mck2ui 16
8818 14:00:12.396098 best dqsien dly found for B1: ( 1, 9, 10)
8819 14:00:12.399247 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8820 14:00:12.405900 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8821 14:00:12.405982
8822 14:00:12.409140 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8823 14:00:12.412585 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8824 14:00:12.415818 [Gating] SW calibration Done
8825 14:00:12.415894 ==
8826 14:00:12.419057 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 14:00:12.422394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 14:00:12.422478 ==
8829 14:00:12.425587 RX Vref Scan: 0
8830 14:00:12.425673
8831 14:00:12.425761 RX Vref 0 -> 0, step: 1
8832 14:00:12.425838
8833 14:00:12.428973 RX Delay 0 -> 252, step: 8
8834 14:00:12.432301 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8835 14:00:12.439027 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8836 14:00:12.442189 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8837 14:00:12.445284 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8838 14:00:12.448955 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8839 14:00:12.452127 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8840 14:00:12.458785 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8841 14:00:12.462128 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8842 14:00:12.465349 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8843 14:00:12.468497 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8844 14:00:12.471848 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8845 14:00:12.478492 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8846 14:00:12.481691 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8847 14:00:12.485283 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8848 14:00:12.488475 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8849 14:00:12.491701 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8850 14:00:12.494951 ==
8851 14:00:12.498522 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 14:00:12.501574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 14:00:12.501645 ==
8854 14:00:12.501713 DQS Delay:
8855 14:00:12.504976 DQS0 = 0, DQS1 = 0
8856 14:00:12.505043 DQM Delay:
8857 14:00:12.508365 DQM0 = 132, DQM1 = 128
8858 14:00:12.508432 DQ Delay:
8859 14:00:12.511883 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8860 14:00:12.514854 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8861 14:00:12.518214 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8862 14:00:12.521656 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8863 14:00:12.521730
8864 14:00:12.521789
8865 14:00:12.521846 ==
8866 14:00:12.524771 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 14:00:12.531710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 14:00:12.531784 ==
8869 14:00:12.531844
8870 14:00:12.531908
8871 14:00:12.531964 TX Vref Scan disable
8872 14:00:12.535262 == TX Byte 0 ==
8873 14:00:12.538722 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8874 14:00:12.545172 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8875 14:00:12.545247 == TX Byte 1 ==
8876 14:00:12.548315 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8877 14:00:12.555098 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8878 14:00:12.555180 ==
8879 14:00:12.558312 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 14:00:12.561687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 14:00:12.561761 ==
8882 14:00:12.574590
8883 14:00:12.578084 TX Vref early break, caculate TX vref
8884 14:00:12.581242 TX Vref=16, minBit 0, minWin=21, winSum=368
8885 14:00:12.584878 TX Vref=18, minBit 0, minWin=22, winSum=384
8886 14:00:12.588093 TX Vref=20, minBit 8, minWin=23, winSum=390
8887 14:00:12.591126 TX Vref=22, minBit 0, minWin=23, winSum=398
8888 14:00:12.594779 TX Vref=24, minBit 0, minWin=24, winSum=406
8889 14:00:12.601241 TX Vref=26, minBit 0, minWin=24, winSum=411
8890 14:00:12.604474 TX Vref=28, minBit 5, minWin=24, winSum=416
8891 14:00:12.607690 TX Vref=30, minBit 1, minWin=24, winSum=409
8892 14:00:12.611250 TX Vref=32, minBit 8, minWin=23, winSum=401
8893 14:00:12.614245 TX Vref=34, minBit 1, minWin=22, winSum=393
8894 14:00:12.621193 [TxChooseVref] Worse bit 5, Min win 24, Win sum 416, Final Vref 28
8895 14:00:12.621299
8896 14:00:12.624343 Final TX Range 0 Vref 28
8897 14:00:12.624435
8898 14:00:12.624526 ==
8899 14:00:12.627722 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 14:00:12.631065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 14:00:12.631142 ==
8902 14:00:12.631276
8903 14:00:12.631353
8904 14:00:12.634203 TX Vref Scan disable
8905 14:00:12.640994 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8906 14:00:12.641072 == TX Byte 0 ==
8907 14:00:12.644093 u2DelayCellOfst[0]=18 cells (5 PI)
8908 14:00:12.647330 u2DelayCellOfst[1]=15 cells (4 PI)
8909 14:00:12.650918 u2DelayCellOfst[2]=0 cells (0 PI)
8910 14:00:12.653929 u2DelayCellOfst[3]=7 cells (2 PI)
8911 14:00:12.657503 u2DelayCellOfst[4]=11 cells (3 PI)
8912 14:00:12.660769 u2DelayCellOfst[5]=22 cells (6 PI)
8913 14:00:12.664002 u2DelayCellOfst[6]=18 cells (5 PI)
8914 14:00:12.667372 u2DelayCellOfst[7]=3 cells (1 PI)
8915 14:00:12.670729 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8916 14:00:12.673892 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8917 14:00:12.677180 == TX Byte 1 ==
8918 14:00:12.680507 u2DelayCellOfst[8]=0 cells (0 PI)
8919 14:00:12.680580 u2DelayCellOfst[9]=3 cells (1 PI)
8920 14:00:12.684023 u2DelayCellOfst[10]=11 cells (3 PI)
8921 14:00:12.687040 u2DelayCellOfst[11]=3 cells (1 PI)
8922 14:00:12.690459 u2DelayCellOfst[12]=15 cells (4 PI)
8923 14:00:12.693720 u2DelayCellOfst[13]=15 cells (4 PI)
8924 14:00:12.697075 u2DelayCellOfst[14]=18 cells (5 PI)
8925 14:00:12.700506 u2DelayCellOfst[15]=18 cells (5 PI)
8926 14:00:12.703711 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8927 14:00:12.710463 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8928 14:00:12.710551 DramC Write-DBI on
8929 14:00:12.710651 ==
8930 14:00:12.713651 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 14:00:12.720093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 14:00:12.720201 ==
8933 14:00:12.720267
8934 14:00:12.720336
8935 14:00:12.720429 TX Vref Scan disable
8936 14:00:12.724332 == TX Byte 0 ==
8937 14:00:12.727529 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8938 14:00:12.730721 == TX Byte 1 ==
8939 14:00:12.734100 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8940 14:00:12.737832 DramC Write-DBI off
8941 14:00:12.737912
8942 14:00:12.737993 [DATLAT]
8943 14:00:12.738077 Freq=1600, CH1 RK1
8944 14:00:12.738153
8945 14:00:12.740677 DATLAT Default: 0xf
8946 14:00:12.740782 0, 0xFFFF, sum = 0
8947 14:00:12.744058 1, 0xFFFF, sum = 0
8948 14:00:12.744142 2, 0xFFFF, sum = 0
8949 14:00:12.747697 3, 0xFFFF, sum = 0
8950 14:00:12.750896 4, 0xFFFF, sum = 0
8951 14:00:12.750974 5, 0xFFFF, sum = 0
8952 14:00:12.754033 6, 0xFFFF, sum = 0
8953 14:00:12.754117 7, 0xFFFF, sum = 0
8954 14:00:12.757418 8, 0xFFFF, sum = 0
8955 14:00:12.757551 9, 0xFFFF, sum = 0
8956 14:00:12.761055 10, 0xFFFF, sum = 0
8957 14:00:12.761134 11, 0xFFFF, sum = 0
8958 14:00:12.764146 12, 0xFFFF, sum = 0
8959 14:00:12.764234 13, 0x8FFF, sum = 0
8960 14:00:12.767728 14, 0x0, sum = 1
8961 14:00:12.767809 15, 0x0, sum = 2
8962 14:00:12.770460 16, 0x0, sum = 3
8963 14:00:12.770541 17, 0x0, sum = 4
8964 14:00:12.774172 best_step = 15
8965 14:00:12.774256
8966 14:00:12.774344 ==
8967 14:00:12.777294 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 14:00:12.780406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 14:00:12.780485 ==
8970 14:00:12.783913 RX Vref Scan: 0
8971 14:00:12.784001
8972 14:00:12.784081 RX Vref 0 -> 0, step: 1
8973 14:00:12.784167
8974 14:00:12.787057 RX Delay 11 -> 252, step: 4
8975 14:00:12.790632 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8976 14:00:12.797195 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8977 14:00:12.800546 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8978 14:00:12.803679 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8979 14:00:12.806809 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8980 14:00:12.810524 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8981 14:00:12.816870 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8982 14:00:12.820307 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8983 14:00:12.823758 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8984 14:00:12.826814 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8985 14:00:12.830195 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8986 14:00:12.836867 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8987 14:00:12.839924 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8988 14:00:12.843173 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8989 14:00:12.846686 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8990 14:00:12.853187 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8991 14:00:12.853266 ==
8992 14:00:12.856558 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 14:00:12.859795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 14:00:12.859865 ==
8995 14:00:12.859924 DQS Delay:
8996 14:00:12.863247 DQS0 = 0, DQS1 = 0
8997 14:00:12.863314 DQM Delay:
8998 14:00:12.866288 DQM0 = 129, DQM1 = 125
8999 14:00:12.866364 DQ Delay:
9000 14:00:12.869577 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =126
9001 14:00:12.872791 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =126
9002 14:00:12.876438 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9003 14:00:12.879568 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9004 14:00:12.882872
9005 14:00:12.882945
9006 14:00:12.883006
9007 14:00:12.883072 [DramC_TX_OE_Calibration] TA2
9008 14:00:12.886129 Original DQ_B0 (3 6) =30, OEN = 27
9009 14:00:12.889565 Original DQ_B1 (3 6) =30, OEN = 27
9010 14:00:12.892721 24, 0x0, End_B0=24 End_B1=24
9011 14:00:12.896274 25, 0x0, End_B0=25 End_B1=25
9012 14:00:12.899460 26, 0x0, End_B0=26 End_B1=26
9013 14:00:12.899541 27, 0x0, End_B0=27 End_B1=27
9014 14:00:12.902606 28, 0x0, End_B0=28 End_B1=28
9015 14:00:12.905755 29, 0x0, End_B0=29 End_B1=29
9016 14:00:12.909369 30, 0x0, End_B0=30 End_B1=30
9017 14:00:12.912484 31, 0x5151, End_B0=30 End_B1=30
9018 14:00:12.915698 Byte0 end_step=30 best_step=27
9019 14:00:12.915772 Byte1 end_step=30 best_step=27
9020 14:00:12.919024 Byte0 TX OE(2T, 0.5T) = (3, 3)
9021 14:00:12.922252 Byte1 TX OE(2T, 0.5T) = (3, 3)
9022 14:00:12.922337
9023 14:00:12.922415
9024 14:00:12.932359 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9025 14:00:12.932454 CH1 RK1: MR19=303, MR18=111E
9026 14:00:12.938909 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
9027 14:00:12.942442 [RxdqsGatingPostProcess] freq 1600
9028 14:00:12.948644 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9029 14:00:12.952118 best DQS0 dly(2T, 0.5T) = (1, 1)
9030 14:00:12.955700 best DQS1 dly(2T, 0.5T) = (1, 1)
9031 14:00:12.958734 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9032 14:00:12.961920 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9033 14:00:12.962003 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 14:00:12.965566 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 14:00:12.968778 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 14:00:12.972059 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 14:00:12.975177 Pre-setting of DQS Precalculation
9038 14:00:12.981829 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9039 14:00:12.988712 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9040 14:00:12.995130 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9041 14:00:12.995220
9042 14:00:12.995302
9043 14:00:12.998696 [Calibration Summary] 3200 Mbps
9044 14:00:12.998772 CH 0, Rank 0
9045 14:00:13.001844 SW Impedance : PASS
9046 14:00:13.004920 DUTY Scan : NO K
9047 14:00:13.004994 ZQ Calibration : PASS
9048 14:00:13.008438 Jitter Meter : NO K
9049 14:00:13.011816 CBT Training : PASS
9050 14:00:13.011916 Write leveling : PASS
9051 14:00:13.015000 RX DQS gating : PASS
9052 14:00:13.018479 RX DQ/DQS(RDDQC) : PASS
9053 14:00:13.018561 TX DQ/DQS : PASS
9054 14:00:13.021659 RX DATLAT : PASS
9055 14:00:13.024840 RX DQ/DQS(Engine): PASS
9056 14:00:13.024922 TX OE : PASS
9057 14:00:13.028133 All Pass.
9058 14:00:13.028205
9059 14:00:13.028282 CH 0, Rank 1
9060 14:00:13.031696 SW Impedance : PASS
9061 14:00:13.031769 DUTY Scan : NO K
9062 14:00:13.034773 ZQ Calibration : PASS
9063 14:00:13.038175 Jitter Meter : NO K
9064 14:00:13.038257 CBT Training : PASS
9065 14:00:13.041368 Write leveling : PASS
9066 14:00:13.044673 RX DQS gating : PASS
9067 14:00:13.044748 RX DQ/DQS(RDDQC) : PASS
9068 14:00:13.047857 TX DQ/DQS : PASS
9069 14:00:13.051022 RX DATLAT : PASS
9070 14:00:13.051106 RX DQ/DQS(Engine): PASS
9071 14:00:13.054625 TX OE : PASS
9072 14:00:13.054699 All Pass.
9073 14:00:13.054785
9074 14:00:13.057854 CH 1, Rank 0
9075 14:00:13.057928 SW Impedance : PASS
9076 14:00:13.061096 DUTY Scan : NO K
9077 14:00:13.061168 ZQ Calibration : PASS
9078 14:00:13.064326 Jitter Meter : NO K
9079 14:00:13.067906 CBT Training : PASS
9080 14:00:13.067988 Write leveling : PASS
9081 14:00:13.071024 RX DQS gating : PASS
9082 14:00:13.074571 RX DQ/DQS(RDDQC) : PASS
9083 14:00:13.074652 TX DQ/DQS : PASS
9084 14:00:13.077702 RX DATLAT : PASS
9085 14:00:13.080948 RX DQ/DQS(Engine): PASS
9086 14:00:13.081022 TX OE : PASS
9087 14:00:13.084550 All Pass.
9088 14:00:13.084623
9089 14:00:13.084702 CH 1, Rank 1
9090 14:00:13.087641 SW Impedance : PASS
9091 14:00:13.087712 DUTY Scan : NO K
9092 14:00:13.090923 ZQ Calibration : PASS
9093 14:00:13.094319 Jitter Meter : NO K
9094 14:00:13.094408 CBT Training : PASS
9095 14:00:13.097543 Write leveling : PASS
9096 14:00:13.100642 RX DQS gating : PASS
9097 14:00:13.100718 RX DQ/DQS(RDDQC) : PASS
9098 14:00:13.104148 TX DQ/DQS : PASS
9099 14:00:13.107272 RX DATLAT : PASS
9100 14:00:13.107351 RX DQ/DQS(Engine): PASS
9101 14:00:13.110870 TX OE : PASS
9102 14:00:13.110939 All Pass.
9103 14:00:13.110998
9104 14:00:13.113998 DramC Write-DBI on
9105 14:00:13.117379 PER_BANK_REFRESH: Hybrid Mode
9106 14:00:13.117529 TX_TRACKING: ON
9107 14:00:13.127246 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9108 14:00:13.134050 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9109 14:00:13.140741 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9110 14:00:13.143965 [FAST_K] Save calibration result to emmc
9111 14:00:13.146975 sync common calibartion params.
9112 14:00:13.150477 sync cbt_mode0:1, 1:1
9113 14:00:13.150548 dram_init: ddr_geometry: 2
9114 14:00:13.153903 dram_init: ddr_geometry: 2
9115 14:00:13.157425 dram_init: ddr_geometry: 2
9116 14:00:13.160534 0:dram_rank_size:100000000
9117 14:00:13.160605 1:dram_rank_size:100000000
9118 14:00:13.167225 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9119 14:00:13.170602 DFS_SHUFFLE_HW_MODE: ON
9120 14:00:13.173882 dramc_set_vcore_voltage set vcore to 725000
9121 14:00:13.177099 Read voltage for 1600, 0
9122 14:00:13.177199 Vio18 = 0
9123 14:00:13.177287 Vcore = 725000
9124 14:00:13.180349 Vdram = 0
9125 14:00:13.180450 Vddq = 0
9126 14:00:13.180529 Vmddr = 0
9127 14:00:13.183575 switch to 3200 Mbps bootup
9128 14:00:13.183648 [DramcRunTimeConfig]
9129 14:00:13.186880 PHYPLL
9130 14:00:13.186965 DPM_CONTROL_AFTERK: ON
9131 14:00:13.190431 PER_BANK_REFRESH: ON
9132 14:00:13.193626 REFRESH_OVERHEAD_REDUCTION: ON
9133 14:00:13.193729 CMD_PICG_NEW_MODE: OFF
9134 14:00:13.196861 XRTWTW_NEW_MODE: ON
9135 14:00:13.196940 XRTRTR_NEW_MODE: ON
9136 14:00:13.199921 TX_TRACKING: ON
9137 14:00:13.200002 RDSEL_TRACKING: OFF
9138 14:00:13.203325 DQS Precalculation for DVFS: ON
9139 14:00:13.206467 RX_TRACKING: OFF
9140 14:00:13.206543 HW_GATING DBG: ON
9141 14:00:13.209889 ZQCS_ENABLE_LP4: ON
9142 14:00:13.209963 RX_PICG_NEW_MODE: ON
9143 14:00:13.213117 TX_PICG_NEW_MODE: ON
9144 14:00:13.216746 ENABLE_RX_DCM_DPHY: ON
9145 14:00:13.219997 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9146 14:00:13.220070 DUMMY_READ_FOR_TRACKING: OFF
9147 14:00:13.223096 !!! SPM_CONTROL_AFTERK: OFF
9148 14:00:13.226289 !!! SPM could not control APHY
9149 14:00:13.229949 IMPEDANCE_TRACKING: ON
9150 14:00:13.230026 TEMP_SENSOR: ON
9151 14:00:13.232985 HW_SAVE_FOR_SR: OFF
9152 14:00:13.233057 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9153 14:00:13.239843 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9154 14:00:13.239918 Read ODT Tracking: ON
9155 14:00:13.242988 Refresh Rate DeBounce: ON
9156 14:00:13.243060 DFS_NO_QUEUE_FLUSH: ON
9157 14:00:13.246483 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9158 14:00:13.249696 ENABLE_DFS_RUNTIME_MRW: OFF
9159 14:00:13.253017 DDR_RESERVE_NEW_MODE: ON
9160 14:00:13.253090 MR_CBT_SWITCH_FREQ: ON
9161 14:00:13.256097 =========================
9162 14:00:13.275841 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9163 14:00:13.278839 dram_init: ddr_geometry: 2
9164 14:00:13.297207 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9165 14:00:13.300581 dram_init: dram init end (result: 0)
9166 14:00:13.307330 DRAM-K: Full calibration passed in 24580 msecs
9167 14:00:13.310576 MRC: failed to locate region type 0.
9168 14:00:13.310657 DRAM rank0 size:0x100000000,
9169 14:00:13.313872 DRAM rank1 size=0x100000000
9170 14:00:13.323697 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9171 14:00:13.330289 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9172 14:00:13.337090 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9173 14:00:13.343684 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9174 14:00:13.346887 DRAM rank0 size:0x100000000,
9175 14:00:13.350537 DRAM rank1 size=0x100000000
9176 14:00:13.350620 CBMEM:
9177 14:00:13.353601 IMD: root @ 0xfffff000 254 entries.
9178 14:00:13.357002 IMD: root @ 0xffffec00 62 entries.
9179 14:00:13.360245 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9180 14:00:13.363679 WARNING: RO_VPD is uninitialized or empty.
9181 14:00:13.370064 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9182 14:00:13.377400 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9183 14:00:13.389937 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9184 14:00:13.401656 BS: romstage times (exec / console): total (unknown) / 24044 ms
9185 14:00:13.401739
9186 14:00:13.401804
9187 14:00:13.411512 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9188 14:00:13.414966 ARM64: Exception handlers installed.
9189 14:00:13.418380 ARM64: Testing exception
9190 14:00:13.421524 ARM64: Done test exception
9191 14:00:13.421639 Enumerating buses...
9192 14:00:13.424715 Show all devs... Before device enumeration.
9193 14:00:13.428271 Root Device: enabled 1
9194 14:00:13.431520 CPU_CLUSTER: 0: enabled 1
9195 14:00:13.431594 CPU: 00: enabled 1
9196 14:00:13.434662 Compare with tree...
9197 14:00:13.434745 Root Device: enabled 1
9198 14:00:13.438042 CPU_CLUSTER: 0: enabled 1
9199 14:00:13.441147 CPU: 00: enabled 1
9200 14:00:13.441221 Root Device scanning...
9201 14:00:13.444582 scan_static_bus for Root Device
9202 14:00:13.448131 CPU_CLUSTER: 0 enabled
9203 14:00:13.451239 scan_static_bus for Root Device done
9204 14:00:13.454769 scan_bus: bus Root Device finished in 8 msecs
9205 14:00:13.454850 done
9206 14:00:13.461337 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9207 14:00:13.464457 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9208 14:00:13.470960 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9209 14:00:13.474221 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9210 14:00:13.477776 Allocating resources...
9211 14:00:13.480926 Reading resources...
9212 14:00:13.484420 Root Device read_resources bus 0 link: 0
9213 14:00:13.484500 DRAM rank0 size:0x100000000,
9214 14:00:13.487876 DRAM rank1 size=0x100000000
9215 14:00:13.490830 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9216 14:00:13.494357 CPU: 00 missing read_resources
9217 14:00:13.500738 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9218 14:00:13.504027 Root Device read_resources bus 0 link: 0 done
9219 14:00:13.504133 Done reading resources.
9220 14:00:13.510804 Show resources in subtree (Root Device)...After reading.
9221 14:00:13.513981 Root Device child on link 0 CPU_CLUSTER: 0
9222 14:00:13.517238 CPU_CLUSTER: 0 child on link 0 CPU: 00
9223 14:00:13.527227 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9224 14:00:13.527306 CPU: 00
9225 14:00:13.530609 Root Device assign_resources, bus 0 link: 0
9226 14:00:13.533835 CPU_CLUSTER: 0 missing set_resources
9227 14:00:13.540610 Root Device assign_resources, bus 0 link: 0 done
9228 14:00:13.540690 Done setting resources.
9229 14:00:13.547272 Show resources in subtree (Root Device)...After assigning values.
9230 14:00:13.550406 Root Device child on link 0 CPU_CLUSTER: 0
9231 14:00:13.553723 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 14:00:13.563833 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 14:00:13.563915 CPU: 00
9234 14:00:13.567053 Done allocating resources.
9235 14:00:13.573455 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9236 14:00:13.573555 Enabling resources...
9237 14:00:13.573620 done.
9238 14:00:13.580209 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9239 14:00:13.580310 Initializing devices...
9240 14:00:13.583447 Root Device init
9241 14:00:13.586571 init hardware done!
9242 14:00:13.586640 0x00000018: ctrlr->caps
9243 14:00:13.590016 52.000 MHz: ctrlr->f_max
9244 14:00:13.590119 0.400 MHz: ctrlr->f_min
9245 14:00:13.593242 0x40ff8080: ctrlr->voltages
9246 14:00:13.596517 sclk: 390625
9247 14:00:13.596594 Bus Width = 1
9248 14:00:13.596656 sclk: 390625
9249 14:00:13.600094 Bus Width = 1
9250 14:00:13.600200 Early init status = 3
9251 14:00:13.606581 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9252 14:00:13.609806 in-header: 03 fc 00 00 01 00 00 00
9253 14:00:13.613253 in-data: 00
9254 14:00:13.616435 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9255 14:00:13.620393 in-header: 03 fd 00 00 00 00 00 00
9256 14:00:13.623948 in-data:
9257 14:00:13.627109 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9258 14:00:13.631153 in-header: 03 fc 00 00 01 00 00 00
9259 14:00:13.634374 in-data: 00
9260 14:00:13.637908 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9261 14:00:13.643189 in-header: 03 fd 00 00 00 00 00 00
9262 14:00:13.646486 in-data:
9263 14:00:13.649781 [SSUSB] Setting up USB HOST controller...
9264 14:00:13.653122 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9265 14:00:13.656459 [SSUSB] phy power-on done.
9266 14:00:13.659943 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9267 14:00:13.666258 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9268 14:00:13.669845 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9269 14:00:13.676460 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9270 14:00:13.682915 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9271 14:00:13.689417 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9272 14:00:13.696180 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9273 14:00:13.702661 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9274 14:00:13.705884 SPM: binary array size = 0x9dc
9275 14:00:13.709362 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9276 14:00:13.716082 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9277 14:00:13.722417 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9278 14:00:13.729286 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9279 14:00:13.732702 configure_display: Starting display init
9280 14:00:13.766500 anx7625_power_on_init: Init interface.
9281 14:00:13.769603 anx7625_disable_pd_protocol: Disabled PD feature.
9282 14:00:13.772884 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9283 14:00:13.800933 anx7625_start_dp_work: Secure OCM version=00
9284 14:00:13.804041 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9285 14:00:13.818760 sp_tx_get_edid_block: EDID Block = 1
9286 14:00:13.921567 Extracted contents:
9287 14:00:13.924694 header: 00 ff ff ff ff ff ff 00
9288 14:00:13.928178 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9289 14:00:13.931344 version: 01 04
9290 14:00:13.934500 basic params: 95 1f 11 78 0a
9291 14:00:13.938073 chroma info: 76 90 94 55 54 90 27 21 50 54
9292 14:00:13.941238 established: 00 00 00
9293 14:00:13.948019 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9294 14:00:13.951202 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9295 14:00:13.957934 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9296 14:00:13.964519 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9297 14:00:13.970951 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9298 14:00:13.974509 extensions: 00
9299 14:00:13.974609 checksum: fb
9300 14:00:13.974706
9301 14:00:13.977802 Manufacturer: IVO Model 57d Serial Number 0
9302 14:00:13.981076 Made week 0 of 2020
9303 14:00:13.981155 EDID version: 1.4
9304 14:00:13.984294 Digital display
9305 14:00:13.988074 6 bits per primary color channel
9306 14:00:13.988154 DisplayPort interface
9307 14:00:13.991367 Maximum image size: 31 cm x 17 cm
9308 14:00:13.994428 Gamma: 220%
9309 14:00:13.994497 Check DPMS levels
9310 14:00:13.997888 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9311 14:00:14.000966 First detailed timing is preferred timing
9312 14:00:14.004470 Established timings supported:
9313 14:00:14.007470 Standard timings supported:
9314 14:00:14.010949 Detailed timings
9315 14:00:14.014300 Hex of detail: 383680a07038204018303c0035ae10000019
9316 14:00:14.017379 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9317 14:00:14.024079 0780 0798 07c8 0820 hborder 0
9318 14:00:14.027364 0438 043b 0447 0458 vborder 0
9319 14:00:14.030820 -hsync -vsync
9320 14:00:14.030889 Did detailed timing
9321 14:00:14.037372 Hex of detail: 000000000000000000000000000000000000
9322 14:00:14.040493 Manufacturer-specified data, tag 0
9323 14:00:14.044028 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9324 14:00:14.047192 ASCII string: InfoVision
9325 14:00:14.050384 Hex of detail: 000000fe00523134304e574635205248200a
9326 14:00:14.053877 ASCII string: R140NWF5 RH
9327 14:00:14.053952 Checksum
9328 14:00:14.057263 Checksum: 0xfb (valid)
9329 14:00:14.060520 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9330 14:00:14.063720 DSI data_rate: 832800000 bps
9331 14:00:14.070433 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9332 14:00:14.073645 anx7625_parse_edid: pixelclock(138800).
9333 14:00:14.077142 hactive(1920), hsync(48), hfp(24), hbp(88)
9334 14:00:14.080182 vactive(1080), vsync(12), vfp(3), vbp(17)
9335 14:00:14.083472 anx7625_dsi_config: config dsi.
9336 14:00:14.090156 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9337 14:00:14.103769 anx7625_dsi_config: success to config DSI
9338 14:00:14.106996 anx7625_dp_start: MIPI phy setup OK.
9339 14:00:14.109938 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9340 14:00:14.113393 mtk_ddp_mode_set invalid vrefresh 60
9341 14:00:14.116796 main_disp_path_setup
9342 14:00:14.116871 ovl_layer_smi_id_en
9343 14:00:14.119976 ovl_layer_smi_id_en
9344 14:00:14.120045 ccorr_config
9345 14:00:14.120112 aal_config
9346 14:00:14.123271 gamma_config
9347 14:00:14.123351 postmask_config
9348 14:00:14.126515 dither_config
9349 14:00:14.129785 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9350 14:00:14.136563 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9351 14:00:14.139723 Root Device init finished in 553 msecs
9352 14:00:14.143225 CPU_CLUSTER: 0 init
9353 14:00:14.150060 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9354 14:00:14.153297 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9355 14:00:14.156511 APU_MBOX 0x190000b0 = 0x10001
9356 14:00:14.159558 APU_MBOX 0x190001b0 = 0x10001
9357 14:00:14.162956 APU_MBOX 0x190005b0 = 0x10001
9358 14:00:14.166492 APU_MBOX 0x190006b0 = 0x10001
9359 14:00:14.172866 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9360 14:00:14.182532 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9361 14:00:14.195014 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9362 14:00:14.201363 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9363 14:00:14.213193 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9364 14:00:14.222209 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9365 14:00:14.225408 CPU_CLUSTER: 0 init finished in 81 msecs
9366 14:00:14.228754 Devices initialized
9367 14:00:14.232181 Show all devs... After init.
9368 14:00:14.232265 Root Device: enabled 1
9369 14:00:14.235428 CPU_CLUSTER: 0: enabled 1
9370 14:00:14.238831 CPU: 00: enabled 1
9371 14:00:14.242034 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9372 14:00:14.245232 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9373 14:00:14.248480 ELOG: NV offset 0x57f000 size 0x1000
9374 14:00:14.255630 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9375 14:00:14.261859 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9376 14:00:14.265252 ELOG: Event(17) added with size 13 at 2024-02-01 14:00:14 UTC
9377 14:00:14.271914 out: cmd=0x121: 03 db 21 01 00 00 00 00
9378 14:00:14.275037 in-header: 03 56 00 00 2c 00 00 00
9379 14:00:14.284913 in-data: 08 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9380 14:00:14.291722 ELOG: Event(A1) added with size 10 at 2024-02-01 14:00:14 UTC
9381 14:00:14.298077 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9382 14:00:14.305122 ELOG: Event(A0) added with size 9 at 2024-02-01 14:00:14 UTC
9383 14:00:14.308140 elog_add_boot_reason: Logged dev mode boot
9384 14:00:14.314635 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9385 14:00:14.314715 Finalize devices...
9386 14:00:14.317871 Devices finalized
9387 14:00:14.321006 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9388 14:00:14.324689 Writing coreboot table at 0xffe64000
9389 14:00:14.327804 0. 000000000010a000-0000000000113fff: RAMSTAGE
9390 14:00:14.334458 1. 0000000040000000-00000000400fffff: RAM
9391 14:00:14.337625 2. 0000000040100000-000000004032afff: RAMSTAGE
9392 14:00:14.340973 3. 000000004032b000-00000000545fffff: RAM
9393 14:00:14.344433 4. 0000000054600000-000000005465ffff: BL31
9394 14:00:14.347632 5. 0000000054660000-00000000ffe63fff: RAM
9395 14:00:14.354068 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9396 14:00:14.357341 7. 0000000100000000-000000023fffffff: RAM
9397 14:00:14.360563 Passing 5 GPIOs to payload:
9398 14:00:14.363942 NAME | PORT | POLARITY | VALUE
9399 14:00:14.370442 EC in RW | 0x000000aa | low | undefined
9400 14:00:14.373995 EC interrupt | 0x00000005 | low | undefined
9401 14:00:14.377376 TPM interrupt | 0x000000ab | high | undefined
9402 14:00:14.384094 SD card detect | 0x00000011 | high | undefined
9403 14:00:14.387201 speaker enable | 0x00000093 | high | undefined
9404 14:00:14.390342 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9405 14:00:14.393958 in-header: 03 f9 00 00 02 00 00 00
9406 14:00:14.397102 in-data: 02 00
9407 14:00:14.400395 ADC[4]: Raw value=897040 ID=7
9408 14:00:14.403768 ADC[3]: Raw value=212700 ID=1
9409 14:00:14.403867 RAM Code: 0x71
9410 14:00:14.407181 ADC[6]: Raw value=75092 ID=0
9411 14:00:14.410230 ADC[5]: Raw value=211960 ID=1
9412 14:00:14.410372 SKU Code: 0x1
9413 14:00:14.417069 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d551
9414 14:00:14.417169 coreboot table: 964 bytes.
9415 14:00:14.420301 IMD ROOT 0. 0xfffff000 0x00001000
9416 14:00:14.423439 IMD SMALL 1. 0xffffe000 0x00001000
9417 14:00:14.426596 RO MCACHE 2. 0xffffc000 0x00001104
9418 14:00:14.430268 CONSOLE 3. 0xfff7c000 0x00080000
9419 14:00:14.433444 FMAP 4. 0xfff7b000 0x00000452
9420 14:00:14.436797 TIME STAMP 5. 0xfff7a000 0x00000910
9421 14:00:14.439917 VBOOT WORK 6. 0xfff66000 0x00014000
9422 14:00:14.443211 RAMOOPS 7. 0xffe66000 0x00100000
9423 14:00:14.446396 COREBOOT 8. 0xffe64000 0x00002000
9424 14:00:14.449821 IMD small region:
9425 14:00:14.453107 IMD ROOT 0. 0xffffec00 0x00000400
9426 14:00:14.456551 VPD 1. 0xffffeb80 0x0000006c
9427 14:00:14.459703 MMC STATUS 2. 0xffffeb60 0x00000004
9428 14:00:14.466396 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9429 14:00:14.466519 Probing TPM: done!
9430 14:00:14.472994 Connected to device vid:did:rid of 1ae0:0028:00
9431 14:00:14.479954 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9432 14:00:14.482898 Initialized TPM device CR50 revision 0
9433 14:00:14.486388 Checking cr50 for pending updates
9434 14:00:14.491923 Reading cr50 TPM mode
9435 14:00:14.500754 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9436 14:00:14.507349 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9437 14:00:14.547146 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9438 14:00:14.550760 Checking segment from ROM address 0x40100000
9439 14:00:14.553778 Checking segment from ROM address 0x4010001c
9440 14:00:14.560688 Loading segment from ROM address 0x40100000
9441 14:00:14.560769 code (compression=0)
9442 14:00:14.567276 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9443 14:00:14.577200 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9444 14:00:14.577283 it's not compressed!
9445 14:00:14.584244 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9446 14:00:14.587212 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9447 14:00:14.607866 Loading segment from ROM address 0x4010001c
9448 14:00:14.607950 Entry Point 0x80000000
9449 14:00:14.610970 Loaded segments
9450 14:00:14.614357 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9451 14:00:14.620855 Jumping to boot code at 0x80000000(0xffe64000)
9452 14:00:14.627488 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9453 14:00:14.634040 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9454 14:00:14.642267 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9455 14:00:14.645438 Checking segment from ROM address 0x40100000
9456 14:00:14.648904 Checking segment from ROM address 0x4010001c
9457 14:00:14.655337 Loading segment from ROM address 0x40100000
9458 14:00:14.655421 code (compression=1)
9459 14:00:14.661963 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9460 14:00:14.671961 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9461 14:00:14.672042 using LZMA
9462 14:00:14.680664 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9463 14:00:14.687220 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9464 14:00:14.690821 Loading segment from ROM address 0x4010001c
9465 14:00:14.690935 Entry Point 0x54601000
9466 14:00:14.694010 Loaded segments
9467 14:00:14.696958 NOTICE: MT8192 bl31_setup
9468 14:00:14.704028 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9469 14:00:14.707516 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9470 14:00:14.710683 WARNING: region 0:
9471 14:00:14.714178 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 14:00:14.714259 WARNING: region 1:
9473 14:00:14.720783 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9474 14:00:14.723899 WARNING: region 2:
9475 14:00:14.727456 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9476 14:00:14.730593 WARNING: region 3:
9477 14:00:14.734027 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 14:00:14.737327 WARNING: region 4:
9479 14:00:14.743987 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 14:00:14.744072 WARNING: region 5:
9481 14:00:14.747353 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 14:00:14.750623 WARNING: region 6:
9483 14:00:14.753876 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 14:00:14.757392 WARNING: region 7:
9485 14:00:14.760685 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 14:00:14.767214 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9487 14:00:14.770697 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9488 14:00:14.773928 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9489 14:00:14.780548 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9490 14:00:14.783940 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9491 14:00:14.786994 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9492 14:00:14.793685 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9493 14:00:14.797316 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9494 14:00:14.803876 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9495 14:00:14.807237 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9496 14:00:14.810555 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9497 14:00:14.817269 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9498 14:00:14.820596 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9499 14:00:14.823731 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9500 14:00:14.830555 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9501 14:00:14.833772 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9502 14:00:14.840753 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9503 14:00:14.843842 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9504 14:00:14.847236 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9505 14:00:14.854085 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9506 14:00:14.857279 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9507 14:00:14.860762 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9508 14:00:14.867191 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9509 14:00:14.870730 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9510 14:00:14.877358 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9511 14:00:14.880438 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9512 14:00:14.883970 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9513 14:00:14.890704 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9514 14:00:14.893801 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9515 14:00:14.900671 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9516 14:00:14.903832 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9517 14:00:14.907156 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9518 14:00:14.913974 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9519 14:00:14.917132 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9520 14:00:14.920414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9521 14:00:14.924047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9522 14:00:14.930489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9523 14:00:14.933641 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9524 14:00:14.937112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9525 14:00:14.940262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9526 14:00:14.946929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9527 14:00:14.950352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9528 14:00:14.953924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9529 14:00:14.956879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9530 14:00:14.963732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9531 14:00:14.967217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9532 14:00:14.970631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9533 14:00:14.973855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9534 14:00:14.980531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9535 14:00:14.983632 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9536 14:00:14.990275 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9537 14:00:14.993497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9538 14:00:15.000160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9539 14:00:15.003474 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9540 14:00:15.006959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9541 14:00:15.013578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9542 14:00:15.017099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9543 14:00:15.023645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9544 14:00:15.026683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9545 14:00:15.033397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9546 14:00:15.036744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9547 14:00:15.040139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9548 14:00:15.046728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9549 14:00:15.050309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9550 14:00:15.056862 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9551 14:00:15.060027 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9552 14:00:15.067020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9553 14:00:15.070273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9554 14:00:15.073384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9555 14:00:15.080222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9556 14:00:15.083743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9557 14:00:15.090223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9558 14:00:15.093653 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9559 14:00:15.100257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9560 14:00:15.103581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9561 14:00:15.107067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9562 14:00:15.113402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9563 14:00:15.116849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9564 14:00:15.123721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9565 14:00:15.126859 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9566 14:00:15.133446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9567 14:00:15.137043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9568 14:00:15.143463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9569 14:00:15.146821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9570 14:00:15.149949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9571 14:00:15.156584 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9572 14:00:15.160016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9573 14:00:15.166812 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9574 14:00:15.170053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9575 14:00:15.176615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9576 14:00:15.180335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9577 14:00:15.183655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9578 14:00:15.190231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9579 14:00:15.193271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9580 14:00:15.200103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9581 14:00:15.203607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9582 14:00:15.206909 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9583 14:00:15.213584 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9584 14:00:15.216773 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9585 14:00:15.219973 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9586 14:00:15.223513 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9587 14:00:15.229959 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9588 14:00:15.233424 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9589 14:00:15.240176 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9590 14:00:15.243428 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9591 14:00:15.246931 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9592 14:00:15.253447 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9593 14:00:15.256754 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9594 14:00:15.263292 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9595 14:00:15.266617 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9596 14:00:15.270177 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9597 14:00:15.276682 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9598 14:00:15.280075 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9599 14:00:15.286908 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9600 14:00:15.290131 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9601 14:00:15.293503 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9602 14:00:15.299966 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9603 14:00:15.303210 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9604 14:00:15.306871 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9605 14:00:15.313240 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9606 14:00:15.316769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9607 14:00:15.319848 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9608 14:00:15.323408 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9609 14:00:15.326834 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9610 14:00:15.333313 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9611 14:00:15.336636 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9612 14:00:15.343416 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9613 14:00:15.346628 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9614 14:00:15.353109 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9615 14:00:15.356530 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9616 14:00:15.359886 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9617 14:00:15.366529 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9618 14:00:15.370017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9619 14:00:15.373258 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9620 14:00:15.380020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9621 14:00:15.383074 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9622 14:00:15.390003 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9623 14:00:15.393356 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9624 14:00:15.396412 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9625 14:00:15.403067 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9626 14:00:15.406318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9627 14:00:15.409898 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9628 14:00:15.416298 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9629 14:00:15.419852 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9630 14:00:15.426304 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9631 14:00:15.429924 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9632 14:00:15.433111 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9633 14:00:15.439889 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9634 14:00:15.443105 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9635 14:00:15.449777 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9636 14:00:15.453314 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9637 14:00:15.456856 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9638 14:00:15.463504 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9639 14:00:15.466555 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9640 14:00:15.469826 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9641 14:00:15.476571 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9642 14:00:15.479976 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9643 14:00:15.486531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9644 14:00:15.489768 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9645 14:00:15.493105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9646 14:00:15.499711 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9647 14:00:15.503292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9648 14:00:15.509823 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9649 14:00:15.512865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9650 14:00:15.516406 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9651 14:00:15.522759 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9652 14:00:15.526205 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9653 14:00:15.532952 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9654 14:00:15.536070 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9655 14:00:15.539480 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9656 14:00:15.546109 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9657 14:00:15.549417 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9658 14:00:15.552739 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9659 14:00:15.559250 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9660 14:00:15.562728 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9661 14:00:15.569389 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9662 14:00:15.572533 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9663 14:00:15.578901 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9664 14:00:15.582242 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9665 14:00:15.585614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9666 14:00:15.592385 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9667 14:00:15.595579 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9668 14:00:15.602288 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9669 14:00:15.605366 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9670 14:00:15.608796 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9671 14:00:15.615647 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9672 14:00:15.618865 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9673 14:00:15.625614 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9674 14:00:15.628761 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9675 14:00:15.632077 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9676 14:00:15.638756 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9677 14:00:15.641893 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9678 14:00:15.648616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9679 14:00:15.651732 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9680 14:00:15.655062 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9681 14:00:15.661609 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9682 14:00:15.665126 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9683 14:00:15.671801 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9684 14:00:15.675046 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9685 14:00:15.681802 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9686 14:00:15.684833 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9687 14:00:15.688419 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9688 14:00:15.695045 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9689 14:00:15.698274 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9690 14:00:15.704645 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9691 14:00:15.707841 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9692 14:00:15.714659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9693 14:00:15.717925 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9694 14:00:15.721045 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9695 14:00:15.727806 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9696 14:00:15.731113 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9697 14:00:15.737909 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9698 14:00:15.741067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9699 14:00:15.747864 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9700 14:00:15.751044 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9701 14:00:15.754584 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9702 14:00:15.760985 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9703 14:00:15.764434 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9704 14:00:15.771031 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9705 14:00:15.774418 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9706 14:00:15.777816 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9707 14:00:15.784593 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9708 14:00:15.787754 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9709 14:00:15.794246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9710 14:00:15.797784 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9711 14:00:15.800860 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9712 14:00:15.807580 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9713 14:00:15.810856 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9714 14:00:15.817746 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9715 14:00:15.820833 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9716 14:00:15.823957 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9717 14:00:15.827440 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9718 14:00:15.834117 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9719 14:00:15.837255 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9720 14:00:15.840701 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9721 14:00:15.847642 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9722 14:00:15.850880 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9723 14:00:15.854083 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9724 14:00:15.860877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9725 14:00:15.863941 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9726 14:00:15.867180 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9727 14:00:15.873976 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9728 14:00:15.877155 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9729 14:00:15.880599 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9730 14:00:15.887080 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9731 14:00:15.890324 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9732 14:00:15.897171 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9733 14:00:15.900221 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9734 14:00:15.903655 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9735 14:00:15.910068 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9736 14:00:15.913499 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9737 14:00:15.920120 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9738 14:00:15.923278 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9739 14:00:15.926865 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9740 14:00:15.933408 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9741 14:00:15.936528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9742 14:00:15.939936 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9743 14:00:15.946461 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9744 14:00:15.950044 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9745 14:00:15.953121 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9746 14:00:15.959841 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9747 14:00:15.963171 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9748 14:00:15.969861 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9749 14:00:15.973112 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9750 14:00:15.976256 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9751 14:00:15.982803 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9752 14:00:15.986277 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9753 14:00:15.992950 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9754 14:00:15.996153 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9755 14:00:15.999459 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9756 14:00:16.002707 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9757 14:00:16.005990 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9758 14:00:16.012471 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9759 14:00:16.015826 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9760 14:00:16.019142 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9761 14:00:16.022549 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9762 14:00:16.029162 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9763 14:00:16.032237 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9764 14:00:16.035756 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9765 14:00:16.038960 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9766 14:00:16.045717 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9767 14:00:16.048887 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9768 14:00:16.055548 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9769 14:00:16.058708 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9770 14:00:16.062545 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9771 14:00:16.068833 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9772 14:00:16.072082 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9773 14:00:16.078825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9774 14:00:16.081929 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9775 14:00:16.085357 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9776 14:00:16.092126 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9777 14:00:16.095301 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9778 14:00:16.101695 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9779 14:00:16.105377 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9780 14:00:16.111930 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9781 14:00:16.115245 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9782 14:00:16.118334 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9783 14:00:16.125088 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9784 14:00:16.128256 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9785 14:00:16.134992 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9786 14:00:16.138368 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9787 14:00:16.141649 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9788 14:00:16.148332 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9789 14:00:16.151481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9790 14:00:16.158173 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9791 14:00:16.161646 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9792 14:00:16.164837 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9793 14:00:16.171503 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9794 14:00:16.174692 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9795 14:00:16.181280 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9796 14:00:16.184503 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9797 14:00:16.191236 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9798 14:00:16.194555 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9799 14:00:16.197778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9800 14:00:16.204408 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9801 14:00:16.207995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9802 14:00:16.214324 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9803 14:00:16.217817 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9804 14:00:16.221230 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9805 14:00:16.227846 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9806 14:00:16.231167 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9807 14:00:16.237741 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9808 14:00:16.240939 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9809 14:00:16.244299 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9810 14:00:16.250792 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9811 14:00:16.254085 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9812 14:00:16.260742 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9813 14:00:16.264063 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9814 14:00:16.270916 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9815 14:00:16.274178 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9816 14:00:16.277335 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9817 14:00:16.283991 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9818 14:00:16.287390 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9819 14:00:16.293931 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9820 14:00:16.297416 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9821 14:00:16.300588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9822 14:00:16.307281 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9823 14:00:16.310531 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9824 14:00:16.317181 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9825 14:00:16.320577 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9826 14:00:16.323933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9827 14:00:16.330513 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9828 14:00:16.334003 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9829 14:00:16.340383 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9830 14:00:16.343687 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9831 14:00:16.347429 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9832 14:00:16.353668 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9833 14:00:16.356733 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9834 14:00:16.363593 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9835 14:00:16.366916 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9836 14:00:16.373371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9837 14:00:16.376806 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9838 14:00:16.380169 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9839 14:00:16.386760 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9840 14:00:16.390082 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9841 14:00:16.396882 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9842 14:00:16.399930 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9843 14:00:16.403297 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9844 14:00:16.409994 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9845 14:00:16.413215 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9846 14:00:16.420165 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9847 14:00:16.423189 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9848 14:00:16.429828 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9849 14:00:16.432964 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9850 14:00:16.439662 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9851 14:00:16.443306 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9852 14:00:16.446511 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9853 14:00:16.453244 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9854 14:00:16.456506 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9855 14:00:16.462986 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9856 14:00:16.466133 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9857 14:00:16.473109 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9858 14:00:16.476162 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9859 14:00:16.479692 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9860 14:00:16.486143 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9861 14:00:16.489395 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9862 14:00:16.496205 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9863 14:00:16.499194 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9864 14:00:16.505837 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9865 14:00:16.509174 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9866 14:00:16.515885 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9867 14:00:16.519045 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9868 14:00:16.522442 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9869 14:00:16.528976 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9870 14:00:16.532408 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9871 14:00:16.538906 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9872 14:00:16.542467 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9873 14:00:16.549063 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9874 14:00:16.552153 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9875 14:00:16.558940 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9876 14:00:16.562346 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9877 14:00:16.565471 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9878 14:00:16.572214 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9879 14:00:16.575418 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9880 14:00:16.581877 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9881 14:00:16.585443 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9882 14:00:16.591852 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9883 14:00:16.595200 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9884 14:00:16.601939 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9885 14:00:16.605072 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9886 14:00:16.608454 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9887 14:00:16.615158 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9888 14:00:16.618359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9889 14:00:16.621515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9890 14:00:16.628553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9891 14:00:16.631437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9892 14:00:16.638379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9893 14:00:16.641532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9894 14:00:16.648158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9895 14:00:16.651347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9896 14:00:16.658206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9897 14:00:16.661330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9898 14:00:16.668084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9899 14:00:16.671026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9900 14:00:16.677672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9901 14:00:16.681184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9902 14:00:16.687814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9903 14:00:16.691143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9904 14:00:16.697706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9905 14:00:16.701102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9906 14:00:16.707488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9907 14:00:16.710935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9908 14:00:16.717587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9909 14:00:16.720717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9910 14:00:16.727568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9911 14:00:16.730685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9912 14:00:16.737364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9913 14:00:16.740503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9914 14:00:16.747113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9915 14:00:16.750399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9916 14:00:16.757234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9917 14:00:16.760562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9918 14:00:16.766914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9919 14:00:16.770484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9920 14:00:16.777081 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9921 14:00:16.777184 INFO: [APUAPC] vio 0
9922 14:00:16.783777 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9923 14:00:16.786979 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9924 14:00:16.790434 INFO: [APUAPC] D0_APC_0: 0x400510
9925 14:00:16.793881 INFO: [APUAPC] D0_APC_1: 0x0
9926 14:00:16.797101 INFO: [APUAPC] D0_APC_2: 0x1540
9927 14:00:16.800490 INFO: [APUAPC] D0_APC_3: 0x0
9928 14:00:16.803799 INFO: [APUAPC] D1_APC_0: 0xffffffff
9929 14:00:16.807160 INFO: [APUAPC] D1_APC_1: 0xffffffff
9930 14:00:16.810400 INFO: [APUAPC] D1_APC_2: 0x3fffff
9931 14:00:16.813852 INFO: [APUAPC] D1_APC_3: 0x0
9932 14:00:16.816796 INFO: [APUAPC] D2_APC_0: 0xffffffff
9933 14:00:16.820443 INFO: [APUAPC] D2_APC_1: 0xffffffff
9934 14:00:16.823719 INFO: [APUAPC] D2_APC_2: 0x3fffff
9935 14:00:16.826880 INFO: [APUAPC] D2_APC_3: 0x0
9936 14:00:16.830504 INFO: [APUAPC] D3_APC_0: 0xffffffff
9937 14:00:16.833667 INFO: [APUAPC] D3_APC_1: 0xffffffff
9938 14:00:16.837034 INFO: [APUAPC] D3_APC_2: 0x3fffff
9939 14:00:16.840235 INFO: [APUAPC] D3_APC_3: 0x0
9940 14:00:16.843538 INFO: [APUAPC] D4_APC_0: 0xffffffff
9941 14:00:16.846706 INFO: [APUAPC] D4_APC_1: 0xffffffff
9942 14:00:16.850274 INFO: [APUAPC] D4_APC_2: 0x3fffff
9943 14:00:16.850374 INFO: [APUAPC] D4_APC_3: 0x0
9944 14:00:16.853425 INFO: [APUAPC] D5_APC_0: 0xffffffff
9945 14:00:16.857042 INFO: [APUAPC] D5_APC_1: 0xffffffff
9946 14:00:16.860150 INFO: [APUAPC] D5_APC_2: 0x3fffff
9947 14:00:16.863572 INFO: [APUAPC] D5_APC_3: 0x0
9948 14:00:16.866802 INFO: [APUAPC] D6_APC_0: 0xffffffff
9949 14:00:16.870129 INFO: [APUAPC] D6_APC_1: 0xffffffff
9950 14:00:16.873281 INFO: [APUAPC] D6_APC_2: 0x3fffff
9951 14:00:16.876806 INFO: [APUAPC] D6_APC_3: 0x0
9952 14:00:16.880164 INFO: [APUAPC] D7_APC_0: 0xffffffff
9953 14:00:16.883307 INFO: [APUAPC] D7_APC_1: 0xffffffff
9954 14:00:16.886764 INFO: [APUAPC] D7_APC_2: 0x3fffff
9955 14:00:16.890001 INFO: [APUAPC] D7_APC_3: 0x0
9956 14:00:16.893500 INFO: [APUAPC] D8_APC_0: 0xffffffff
9957 14:00:16.896839 INFO: [APUAPC] D8_APC_1: 0xffffffff
9958 14:00:16.899980 INFO: [APUAPC] D8_APC_2: 0x3fffff
9959 14:00:16.903232 INFO: [APUAPC] D8_APC_3: 0x0
9960 14:00:16.906672 INFO: [APUAPC] D9_APC_0: 0xffffffff
9961 14:00:16.909750 INFO: [APUAPC] D9_APC_1: 0xffffffff
9962 14:00:16.912938 INFO: [APUAPC] D9_APC_2: 0x3fffff
9963 14:00:16.916563 INFO: [APUAPC] D9_APC_3: 0x0
9964 14:00:16.919721 INFO: [APUAPC] D10_APC_0: 0xffffffff
9965 14:00:16.923037 INFO: [APUAPC] D10_APC_1: 0xffffffff
9966 14:00:16.926448 INFO: [APUAPC] D10_APC_2: 0x3fffff
9967 14:00:16.929694 INFO: [APUAPC] D10_APC_3: 0x0
9968 14:00:16.933036 INFO: [APUAPC] D11_APC_0: 0xffffffff
9969 14:00:16.936226 INFO: [APUAPC] D11_APC_1: 0xffffffff
9970 14:00:16.939607 INFO: [APUAPC] D11_APC_2: 0x3fffff
9971 14:00:16.942674 INFO: [APUAPC] D11_APC_3: 0x0
9972 14:00:16.946190 INFO: [APUAPC] D12_APC_0: 0xffffffff
9973 14:00:16.949430 INFO: [APUAPC] D12_APC_1: 0xffffffff
9974 14:00:16.952976 INFO: [APUAPC] D12_APC_2: 0x3fffff
9975 14:00:16.955828 INFO: [APUAPC] D12_APC_3: 0x0
9976 14:00:16.959279 INFO: [APUAPC] D13_APC_0: 0xffffffff
9977 14:00:16.962488 INFO: [APUAPC] D13_APC_1: 0xffffffff
9978 14:00:16.965949 INFO: [APUAPC] D13_APC_2: 0x3fffff
9979 14:00:16.969384 INFO: [APUAPC] D13_APC_3: 0x0
9980 14:00:16.972559 INFO: [APUAPC] D14_APC_0: 0xffffffff
9981 14:00:16.975711 INFO: [APUAPC] D14_APC_1: 0xffffffff
9982 14:00:16.979074 INFO: [APUAPC] D14_APC_2: 0x3fffff
9983 14:00:16.982683 INFO: [APUAPC] D14_APC_3: 0x0
9984 14:00:16.985699 INFO: [APUAPC] D15_APC_0: 0xffffffff
9985 14:00:16.989182 INFO: [APUAPC] D15_APC_1: 0xffffffff
9986 14:00:16.992521 INFO: [APUAPC] D15_APC_2: 0x3fffff
9987 14:00:16.995588 INFO: [APUAPC] D15_APC_3: 0x0
9988 14:00:16.999003 INFO: [APUAPC] APC_CON: 0x4
9989 14:00:17.002194 INFO: [NOCDAPC] D0_APC_0: 0x0
9990 14:00:17.005816 INFO: [NOCDAPC] D0_APC_1: 0x0
9991 14:00:17.008926 INFO: [NOCDAPC] D1_APC_0: 0x0
9992 14:00:17.012437 INFO: [NOCDAPC] D1_APC_1: 0xfff
9993 14:00:17.015683 INFO: [NOCDAPC] D2_APC_0: 0x0
9994 14:00:17.018743 INFO: [NOCDAPC] D2_APC_1: 0xfff
9995 14:00:17.018854 INFO: [NOCDAPC] D3_APC_0: 0x0
9996 14:00:17.022257 INFO: [NOCDAPC] D3_APC_1: 0xfff
9997 14:00:17.025534 INFO: [NOCDAPC] D4_APC_0: 0x0
9998 14:00:17.028749 INFO: [NOCDAPC] D4_APC_1: 0xfff
9999 14:00:17.032539 INFO: [NOCDAPC] D5_APC_0: 0x0
10000 14:00:17.035629 INFO: [NOCDAPC] D5_APC_1: 0xfff
10001 14:00:17.038689 INFO: [NOCDAPC] D6_APC_0: 0x0
10002 14:00:17.042352 INFO: [NOCDAPC] D6_APC_1: 0xfff
10003 14:00:17.045320 INFO: [NOCDAPC] D7_APC_0: 0x0
10004 14:00:17.048731 INFO: [NOCDAPC] D7_APC_1: 0xfff
10005 14:00:17.052206 INFO: [NOCDAPC] D8_APC_0: 0x0
10006 14:00:17.055415 INFO: [NOCDAPC] D8_APC_1: 0xfff
10007 14:00:17.055497 INFO: [NOCDAPC] D9_APC_0: 0x0
10008 14:00:17.058734 INFO: [NOCDAPC] D9_APC_1: 0xfff
10009 14:00:17.061845 INFO: [NOCDAPC] D10_APC_0: 0x0
10010 14:00:17.065384 INFO: [NOCDAPC] D10_APC_1: 0xfff
10011 14:00:17.068787 INFO: [NOCDAPC] D11_APC_0: 0x0
10012 14:00:17.071955 INFO: [NOCDAPC] D11_APC_1: 0xfff
10013 14:00:17.075086 INFO: [NOCDAPC] D12_APC_0: 0x0
10014 14:00:17.078700 INFO: [NOCDAPC] D12_APC_1: 0xfff
10015 14:00:17.081874 INFO: [NOCDAPC] D13_APC_0: 0x0
10016 14:00:17.085020 INFO: [NOCDAPC] D13_APC_1: 0xfff
10017 14:00:17.088296 INFO: [NOCDAPC] D14_APC_0: 0x0
10018 14:00:17.091749 INFO: [NOCDAPC] D14_APC_1: 0xfff
10019 14:00:17.095001 INFO: [NOCDAPC] D15_APC_0: 0x0
10020 14:00:17.098316 INFO: [NOCDAPC] D15_APC_1: 0xfff
10021 14:00:17.098398 INFO: [NOCDAPC] APC_CON: 0x4
10022 14:00:17.101666 INFO: [APUAPC] set_apusys_apc done
10023 14:00:17.104900 INFO: [DEVAPC] devapc_init done
10024 14:00:17.111393 INFO: GICv3 without legacy support detected.
10025 14:00:17.114946 INFO: ARM GICv3 driver initialized in EL3
10026 14:00:17.118054 INFO: Maximum SPI INTID supported: 639
10027 14:00:17.121345 INFO: BL31: Initializing runtime services
10028 14:00:17.128209 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10029 14:00:17.131557 INFO: SPM: enable CPC mode
10030 14:00:17.134829 INFO: mcdi ready for mcusys-off-idle and system suspend
10031 14:00:17.141547 INFO: BL31: Preparing for EL3 exit to normal world
10032 14:00:17.144660 INFO: Entry point address = 0x80000000
10033 14:00:17.144770 INFO: SPSR = 0x8
10034 14:00:17.151756
10035 14:00:17.151868
10036 14:00:17.151962
10037 14:00:17.155390 Starting depthcharge on Spherion...
10038 14:00:17.155465
10039 14:00:17.155540 Wipe memory regions:
10040 14:00:17.155601
10041 14:00:17.156312 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10042 14:00:17.156434 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10043 14:00:17.156546 Setting prompt string to ['asurada:']
10044 14:00:17.156658 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10045 14:00:17.158508 [0x00000040000000, 0x00000054600000)
10046 14:00:17.281012
10047 14:00:17.281164 [0x00000054660000, 0x00000080000000)
10048 14:00:17.541419
10049 14:00:17.541617 [0x000000821a7280, 0x000000ffe64000)
10050 14:00:18.286958
10051 14:00:18.287503 [0x00000100000000, 0x00000240000000)
10052 14:00:20.176926
10053 14:00:20.180262 Initializing XHCI USB controller at 0x11200000.
10054 14:00:21.218389
10055 14:00:21.221324 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10056 14:00:21.221420
10057 14:00:21.221515
10058 14:00:21.221591
10059 14:00:21.221870 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 14:00:21.322200 asurada: tftpboot 192.168.201.1 12682970/tftp-deploy-3sk4mi01/kernel/image.itb 12682970/tftp-deploy-3sk4mi01/kernel/cmdline
10062 14:00:21.322347 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 14:00:21.322435 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10064 14:00:21.326430 tftpboot 192.168.201.1 12682970/tftp-deploy-3sk4mi01/kernel/image.ittp-deploy-3sk4mi01/kernel/cmdline
10065 14:00:21.326527
10066 14:00:21.326593 Waiting for link
10067 14:00:21.486888
10068 14:00:21.487021 R8152: Initializing
10069 14:00:21.487092
10070 14:00:21.489998 Version 6 (ocp_data = 5c30)
10071 14:00:21.490082
10072 14:00:21.493454 R8152: Done initializing
10073 14:00:21.493579
10074 14:00:21.493644 Adding net device
10075 14:00:23.586126
10076 14:00:23.586383 done.
10077 14:00:23.586534
10078 14:00:23.586674 MAC: 00:24:32:30:78:ff
10079 14:00:23.586811
10080 14:00:23.589506 Sending DHCP discover... done.
10081 14:00:23.589662
10082 14:00:23.592645 Waiting for reply... done.
10083 14:00:23.592796
10084 14:00:23.595830 Sending DHCP request... done.
10085 14:00:23.595983
10086 14:00:23.600541 Waiting for reply... done.
10087 14:00:23.600692
10088 14:00:23.600831 My ip is 192.168.201.21
10089 14:00:23.600967
10090 14:00:23.604077 The DHCP server ip is 192.168.201.1
10091 14:00:23.604233
10092 14:00:23.610629 TFTP server IP predefined by user: 192.168.201.1
10093 14:00:23.610787
10094 14:00:23.617149 Bootfile predefined by user: 12682970/tftp-deploy-3sk4mi01/kernel/image.itb
10095 14:00:23.617308
10096 14:00:23.620223 Sending tftp read request... done.
10097 14:00:23.620378
10098 14:00:23.624447 Waiting for the transfer...
10099 14:00:23.624604
10100 14:00:24.189137 00000000 ################################################################
10101 14:00:24.189324
10102 14:00:24.737525 00080000 ################################################################
10103 14:00:24.737674
10104 14:00:25.285386 00100000 ################################################################
10105 14:00:25.285591
10106 14:00:25.845973 00180000 ################################################################
10107 14:00:25.846158
10108 14:00:26.423364 00200000 ################################################################
10109 14:00:26.423514
10110 14:00:26.999371 00280000 ################################################################
10111 14:00:26.999514
10112 14:00:27.578162 00300000 ################################################################
10113 14:00:27.578303
10114 14:00:28.124702 00380000 ################################################################
10115 14:00:28.124845
10116 14:00:28.658717 00400000 ################################################################
10117 14:00:28.658932
10118 14:00:29.209691 00480000 ################################################################
10119 14:00:29.209835
10120 14:00:29.770543 00500000 ################################################################
10121 14:00:29.770687
10122 14:00:30.337791 00580000 ################################################################
10123 14:00:30.337937
10124 14:00:30.902738 00600000 ################################################################
10125 14:00:30.902872
10126 14:00:31.457293 00680000 ################################################################
10127 14:00:31.457433
10128 14:00:32.025801 00700000 ################################################################
10129 14:00:32.025956
10130 14:00:32.667891 00780000 ################################################################
10131 14:00:32.668068
10132 14:00:33.336873 00800000 ################################################################
10133 14:00:33.337054
10134 14:00:33.919426 00880000 ################################################################
10135 14:00:33.919570
10136 14:00:34.488360 00900000 ################################################################
10137 14:00:34.488518
10138 14:00:35.048544 00980000 ################################################################
10139 14:00:35.048754
10140 14:00:35.617650 00a00000 ################################################################
10141 14:00:35.617786
10142 14:00:36.185082 00a80000 ################################################################
10143 14:00:36.185238
10144 14:00:36.748481 00b00000 ################################################################
10145 14:00:36.748647
10146 14:00:37.302026 00b80000 ################################################################
10147 14:00:37.302165
10148 14:00:37.864644 00c00000 ################################################################
10149 14:00:37.864782
10150 14:00:38.405047 00c80000 ################################################################
10151 14:00:38.405180
10152 14:00:38.954796 00d00000 ################################################################
10153 14:00:38.954947
10154 14:00:39.490488 00d80000 ################################################################
10155 14:00:39.490642
10156 14:00:40.183729 00e00000 ################################################################
10157 14:00:40.183870
10158 14:00:40.888233 00e80000 ################################################################
10159 14:00:40.888415
10160 14:00:41.546689 00f00000 ################################################################
10161 14:00:41.546872
10162 14:00:42.227650 00f80000 ################################################################
10163 14:00:42.227796
10164 14:00:42.893730 01000000 ################################################################
10165 14:00:42.893871
10166 14:00:43.516034 01080000 ################################################################
10167 14:00:43.516174
10168 14:00:44.090648 01100000 ################################################################
10169 14:00:44.090786
10170 14:00:44.658072 01180000 ################################################################
10171 14:00:44.658213
10172 14:00:45.221887 01200000 ################################################################
10173 14:00:45.222024
10174 14:00:45.787882 01280000 ################################################################
10175 14:00:45.788015
10176 14:00:46.353938 01300000 ################################################################
10177 14:00:46.354076
10178 14:00:46.915565 01380000 ################################################################
10179 14:00:46.915702
10180 14:00:47.464081 01400000 ################################################################
10181 14:00:47.464215
10182 14:00:48.007022 01480000 ################################################################
10183 14:00:48.007161
10184 14:00:48.600010 01500000 ################################################################
10185 14:00:48.600186
10186 14:00:49.269619 01580000 ################################################################
10187 14:00:49.269750
10188 14:00:49.972782 01600000 ################################################################
10189 14:00:49.972921
10190 14:00:50.640194 01680000 ################################################################
10191 14:00:50.640358
10192 14:00:51.316293 01700000 ################################################################
10193 14:00:51.316460
10194 14:00:51.941395 01780000 ################################################################
10195 14:00:51.941575
10196 14:00:52.528101 01800000 ################################################################
10197 14:00:52.528235
10198 14:00:53.176162 01880000 ################################################################
10199 14:00:53.176308
10200 14:00:53.815377 01900000 ################################################################
10201 14:00:53.815507
10202 14:00:54.474048 01980000 ################################################################
10203 14:00:54.474192
10204 14:00:55.132814 01a00000 ################################################################
10205 14:00:55.133013
10206 14:00:55.773158 01a80000 ################################################################
10207 14:00:55.773297
10208 14:00:56.347557 01b00000 ################################################################
10209 14:00:56.347744
10210 14:00:57.012759 01b80000 ################################################################
10211 14:00:57.012906
10212 14:00:57.662878 01c00000 ################################################################
10213 14:00:57.663083
10214 14:00:58.315664 01c80000 ################################################################
10215 14:00:58.315813
10216 14:00:58.975682 01d00000 ################################################################
10217 14:00:58.975864
10218 14:00:59.646848 01d80000 ################################################################
10219 14:00:59.647011
10220 14:01:00.170142 01e00000 ################################################################
10221 14:01:00.170283
10222 14:01:00.751909 01e80000 ################################################################
10223 14:01:00.752068
10224 14:01:01.408562 01f00000 ################################################################
10225 14:01:01.408795
10226 14:01:02.077965 01f80000 ################################################################
10227 14:01:02.078114
10228 14:01:02.745020 02000000 ################################################################
10229 14:01:02.745161
10230 14:01:03.430425 02080000 ################################################################
10231 14:01:03.430572
10232 14:01:04.115126 02100000 ################################################################
10233 14:01:04.115314
10234 14:01:04.773048 02180000 ################################################################
10235 14:01:04.773181
10236 14:01:05.466960 02200000 ################################################################
10237 14:01:05.467093
10238 14:01:06.158214 02280000 ################################################################
10239 14:01:06.158389
10240 14:01:06.836467 02300000 ################################################################
10241 14:01:06.836627
10242 14:01:07.492958 02380000 ################################################################
10243 14:01:07.493106
10244 14:01:08.207666 02400000 ################################################################
10245 14:01:08.207843
10246 14:01:08.868423 02480000 ################################################################
10247 14:01:08.868567
10248 14:01:09.529953 02500000 ################################################################
10249 14:01:09.530142
10250 14:01:10.191008 02580000 ################################################################
10251 14:01:10.191154
10252 14:01:10.852682 02600000 ################################################################
10253 14:01:10.852831
10254 14:01:11.503601 02680000 ################################################################
10255 14:01:11.503759
10256 14:01:12.147121 02700000 ################################################################
10257 14:01:12.147275
10258 14:01:12.796137 02780000 ################################################################
10259 14:01:12.796282
10260 14:01:13.446375 02800000 ################################################################
10261 14:01:13.446517
10262 14:01:14.112940 02880000 ################################################################
10263 14:01:14.113104
10264 14:01:14.769102 02900000 ################################################################
10265 14:01:14.769287
10266 14:01:15.411381 02980000 ################################################################
10267 14:01:15.411516
10268 14:01:16.058359 02a00000 ################################################################
10269 14:01:16.058514
10270 14:01:16.714212 02a80000 ################################################################
10271 14:01:16.714353
10272 14:01:17.376615 02b00000 ################################################################
10273 14:01:17.376760
10274 14:01:18.047915 02b80000 ################################################################
10275 14:01:18.048052
10276 14:01:18.694137 02c00000 ################################################################
10277 14:01:18.694274
10278 14:01:19.352998 02c80000 ################################################################
10279 14:01:19.353141
10280 14:01:20.016730 02d00000 ################################################################
10281 14:01:20.016868
10282 14:01:20.673176 02d80000 ################################################################
10283 14:01:20.673365
10284 14:01:21.330482 02e00000 ################################################################
10285 14:01:21.330665
10286 14:01:21.983513 02e80000 ################################################################
10287 14:01:21.983651
10288 14:01:22.646444 02f00000 ################################################################
10289 14:01:22.646631
10290 14:01:23.294925 02f80000 ################################################################
10291 14:01:23.295131
10292 14:01:23.944829 03000000 ################################################################
10293 14:01:23.944972
10294 14:01:24.596563 03080000 ################################################################
10295 14:01:24.596694
10296 14:01:24.684656 03100000 ######### done.
10297 14:01:24.684816
10298 14:01:24.687876 The bootfile was 51449754 bytes long.
10299 14:01:24.687992
10300 14:01:24.691079 Sending tftp read request... done.
10301 14:01:24.691183
10302 14:01:24.691283 Waiting for the transfer...
10303 14:01:24.691378
10304 14:01:24.694647 00000000 # done.
10305 14:01:24.694732
10306 14:01:24.701268 Command line loaded dynamically from TFTP file: 12682970/tftp-deploy-3sk4mi01/kernel/cmdline
10307 14:01:24.701378
10308 14:01:24.714591 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10309 14:01:24.714680
10310 14:01:24.717760 Loading FIT.
10311 14:01:24.717840
10312 14:01:24.720895 Image ramdisk-1 has 39353583 bytes.
10313 14:01:24.720996
10314 14:01:24.721087 Image fdt-1 has 47278 bytes.
10315 14:01:24.721174
10316 14:01:24.724448 Image kernel-1 has 12046857 bytes.
10317 14:01:24.724553
10318 14:01:24.734469 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10319 14:01:24.734549
10320 14:01:24.750999 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10321 14:01:24.751095
10322 14:01:24.757453 Choosing best match conf-1 for compat google,spherion-rev2.
10323 14:01:24.761504
10324 14:01:24.766242 Connected to device vid:did:rid of 1ae0:0028:00
10325 14:01:24.773381
10326 14:01:24.776553 tpm_get_response: command 0x17b, return code 0x0
10327 14:01:24.776632
10328 14:01:24.779813 ec_init: CrosEC protocol v3 supported (256, 248)
10329 14:01:24.784054
10330 14:01:24.787215 tpm_cleanup: add release locality here.
10331 14:01:24.787294
10332 14:01:24.787375 Shutting down all USB controllers.
10333 14:01:24.790759
10334 14:01:24.790834 Removing current net device
10335 14:01:24.790914
10336 14:01:24.797508 Exiting depthcharge with code 4 at timestamp: 96960040
10337 14:01:24.797604
10338 14:01:24.800717 LZMA decompressing kernel-1 to 0x821a6718
10339 14:01:24.800794
10340 14:01:24.803791 LZMA decompressing kernel-1 to 0x40000000
10341 14:01:26.304510
10342 14:01:26.304662 jumping to kernel
10343 14:01:26.305703 end: 2.2.4 bootloader-commands (duration 00:01:09) [common]
10344 14:01:26.305850 start: 2.2.5 auto-login-action (timeout 00:03:16) [common]
10345 14:01:26.305962 Setting prompt string to ['Linux version [0-9]']
10346 14:01:26.306066 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10347 14:01:26.306175 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10348 14:01:26.386747
10349 14:01:26.390047 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10350 14:01:26.393602 start: 2.2.5.1 login-action (timeout 00:03:16) [common]
10351 14:01:26.393685 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10352 14:01:26.393754 Setting prompt string to []
10353 14:01:26.393835 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10354 14:01:26.393916 Using line separator: #'\n'#
10355 14:01:26.393975 No login prompt set.
10356 14:01:26.394034 Parsing kernel messages
10357 14:01:26.394087 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10358 14:01:26.394186 [login-action] Waiting for messages, (timeout 00:03:16)
10359 14:01:26.413322 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10360 14:01:26.416357 [ 0.000000] random: crng init done
10361 14:01:26.422828 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10362 14:01:26.426469 [ 0.000000] efi: UEFI not found.
10363 14:01:26.432998 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10364 14:01:26.439578 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10365 14:01:26.449490 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10366 14:01:26.459160 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10367 14:01:26.465876 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10368 14:01:26.472357 [ 0.000000] printk: bootconsole [mtk8250] enabled
10369 14:01:26.479117 [ 0.000000] NUMA: No NUMA configuration found
10370 14:01:26.485770 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10371 14:01:26.489078 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10372 14:01:26.492256 [ 0.000000] Zone ranges:
10373 14:01:26.499268 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10374 14:01:26.502467 [ 0.000000] DMA32 empty
10375 14:01:26.508862 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10376 14:01:26.512108 [ 0.000000] Movable zone start for each node
10377 14:01:26.515709 [ 0.000000] Early memory node ranges
10378 14:01:26.522400 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10379 14:01:26.528654 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10380 14:01:26.535508 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10381 14:01:26.541962 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10382 14:01:26.548547 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10383 14:01:26.555009 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10384 14:01:26.610866 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10385 14:01:26.617583 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10386 14:01:26.624347 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10387 14:01:26.627398 [ 0.000000] psci: probing for conduit method from DT.
10388 14:01:26.634239 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10389 14:01:26.637403 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10390 14:01:26.644112 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10391 14:01:26.647253 [ 0.000000] psci: SMC Calling Convention v1.2
10392 14:01:26.654037 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10393 14:01:26.657260 [ 0.000000] Detected VIPT I-cache on CPU0
10394 14:01:26.663881 [ 0.000000] CPU features: detected: GIC system register CPU interface
10395 14:01:26.670381 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10396 14:01:26.677066 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10397 14:01:26.683620 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10398 14:01:26.690254 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10399 14:01:26.700128 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10400 14:01:26.703604 [ 0.000000] alternatives: applying boot alternatives
10401 14:01:26.710390 [ 0.000000] Fallback order for Node 0: 0
10402 14:01:26.717134 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10403 14:01:26.720233 [ 0.000000] Policy zone: Normal
10404 14:01:26.733413 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10405 14:01:26.743351 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10406 14:01:26.755369 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10407 14:01:26.765201 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10408 14:01:26.771771 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10409 14:01:26.775008 <6>[ 0.000000] software IO TLB: area num 8.
10410 14:01:26.831504 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10411 14:01:26.980663 <6>[ 0.000000] Memory: 7928824K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 423944K reserved, 32768K cma-reserved)
10412 14:01:26.987419 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10413 14:01:26.993864 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10414 14:01:26.997167 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10415 14:01:27.003863 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10416 14:01:27.010359 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10417 14:01:27.014016 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10418 14:01:27.023967 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10419 14:01:27.030541 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10420 14:01:27.036920 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10421 14:01:27.043607 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10422 14:01:27.046888 <6>[ 0.000000] GICv3: 608 SPIs implemented
10423 14:01:27.050531 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10424 14:01:27.056750 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10425 14:01:27.060448 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10426 14:01:27.066974 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10427 14:01:27.080154 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10428 14:01:27.090026 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10429 14:01:27.099921 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10430 14:01:27.107216 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10431 14:01:27.120419 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10432 14:01:27.127111 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10433 14:01:27.133424 <6>[ 0.009237] Console: colour dummy device 80x25
10434 14:01:27.143631 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10435 14:01:27.150232 <6>[ 0.024466] pid_max: default: 32768 minimum: 301
10436 14:01:27.153641 <6>[ 0.029367] LSM: Security Framework initializing
10437 14:01:27.160088 <6>[ 0.034304] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10438 14:01:27.170052 <6>[ 0.042118] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 14:01:27.176965 <6>[ 0.051585] cblist_init_generic: Setting adjustable number of callback queues.
10440 14:01:27.183586 <6>[ 0.059028] cblist_init_generic: Setting shift to 3 and lim to 1.
10441 14:01:27.193275 <6>[ 0.065405] cblist_init_generic: Setting adjustable number of callback queues.
10442 14:01:27.199932 <6>[ 0.072832] cblist_init_generic: Setting shift to 3 and lim to 1.
10443 14:01:27.203534 <6>[ 0.079234] rcu: Hierarchical SRCU implementation.
10444 14:01:27.209967 <6>[ 0.084280] rcu: Max phase no-delay instances is 1000.
10445 14:01:27.216811 <6>[ 0.091307] EFI services will not be available.
10446 14:01:27.219971 <6>[ 0.096264] smp: Bringing up secondary CPUs ...
10447 14:01:27.228221 <6>[ 0.101311] Detected VIPT I-cache on CPU1
10448 14:01:27.234768 <6>[ 0.101381] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10449 14:01:27.241416 <6>[ 0.101411] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10450 14:01:27.244872 <6>[ 0.101744] Detected VIPT I-cache on CPU2
10451 14:01:27.251463 <6>[ 0.101793] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10452 14:01:27.257872 <6>[ 0.101809] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10453 14:01:27.264733 <6>[ 0.102063] Detected VIPT I-cache on CPU3
10454 14:01:27.271014 <6>[ 0.102107] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10455 14:01:27.277841 <6>[ 0.102121] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10456 14:01:27.281241 <6>[ 0.102425] CPU features: detected: Spectre-v4
10457 14:01:27.287680 <6>[ 0.102432] CPU features: detected: Spectre-BHB
10458 14:01:27.291119 <6>[ 0.102437] Detected PIPT I-cache on CPU4
10459 14:01:27.297817 <6>[ 0.102496] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10460 14:01:27.304163 <6>[ 0.102512] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10461 14:01:27.311088 <6>[ 0.102803] Detected PIPT I-cache on CPU5
10462 14:01:27.317652 <6>[ 0.102865] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10463 14:01:27.324081 <6>[ 0.102883] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10464 14:01:27.327501 <6>[ 0.103162] Detected PIPT I-cache on CPU6
10465 14:01:27.334079 <6>[ 0.103227] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10466 14:01:27.340506 <6>[ 0.103245] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10467 14:01:27.347236 <6>[ 0.103540] Detected PIPT I-cache on CPU7
10468 14:01:27.353759 <6>[ 0.103604] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10469 14:01:27.360388 <6>[ 0.103621] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10470 14:01:27.363495 <6>[ 0.103668] smp: Brought up 1 node, 8 CPUs
10471 14:01:27.370108 <6>[ 0.244932] SMP: Total of 8 processors activated.
10472 14:01:27.373772 <6>[ 0.249852] CPU features: detected: 32-bit EL0 Support
10473 14:01:27.383659 <6>[ 0.255215] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10474 14:01:27.390218 <6>[ 0.264015] CPU features: detected: Common not Private translations
10475 14:01:27.396721 <6>[ 0.270531] CPU features: detected: CRC32 instructions
10476 14:01:27.400093 <6>[ 0.275915] CPU features: detected: RCpc load-acquire (LDAPR)
10477 14:01:27.406595 <6>[ 0.281875] CPU features: detected: LSE atomic instructions
10478 14:01:27.413081 <6>[ 0.287657] CPU features: detected: Privileged Access Never
10479 14:01:27.419897 <6>[ 0.293472] CPU features: detected: RAS Extension Support
10480 14:01:27.426243 <6>[ 0.299081] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10481 14:01:27.429499 <6>[ 0.306299] CPU: All CPU(s) started at EL2
10482 14:01:27.436078 <6>[ 0.310616] alternatives: applying system-wide alternatives
10483 14:01:27.445615 <6>[ 0.321376] devtmpfs: initialized
10484 14:01:27.461094 <6>[ 0.330259] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10485 14:01:27.467618 <6>[ 0.340222] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10486 14:01:27.474468 <6>[ 0.348462] pinctrl core: initialized pinctrl subsystem
10487 14:01:27.477761 <6>[ 0.355098] DMI not present or invalid.
10488 14:01:27.484380 <6>[ 0.359509] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10489 14:01:27.494125 <6>[ 0.366374] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10490 14:01:27.500740 <6>[ 0.373959] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10491 14:01:27.510887 <6>[ 0.382196] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10492 14:01:27.514017 <6>[ 0.390437] audit: initializing netlink subsys (disabled)
10493 14:01:27.524269 <5>[ 0.396127] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10494 14:01:27.530610 <6>[ 0.396823] thermal_sys: Registered thermal governor 'step_wise'
10495 14:01:27.537456 <6>[ 0.404090] thermal_sys: Registered thermal governor 'power_allocator'
10496 14:01:27.540738 <6>[ 0.410348] cpuidle: using governor menu
10497 14:01:27.547171 <6>[ 0.421310] NET: Registered PF_QIPCRTR protocol family
10498 14:01:27.553807 <6>[ 0.426783] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10499 14:01:27.560491 <6>[ 0.433883] ASID allocator initialised with 32768 entries
10500 14:01:27.563786 <6>[ 0.440416] Serial: AMBA PL011 UART driver
10501 14:01:27.573364 <4>[ 0.449155] Trying to register duplicate clock ID: 134
10502 14:01:27.627308 <6>[ 0.506221] KASLR enabled
10503 14:01:27.641616 <6>[ 0.513976] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10504 14:01:27.648363 <6>[ 0.520987] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10505 14:01:27.654776 <6>[ 0.527475] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10506 14:01:27.661602 <6>[ 0.534482] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10507 14:01:27.667871 <6>[ 0.540971] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10508 14:01:27.674440 <6>[ 0.547977] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10509 14:01:27.681174 <6>[ 0.554464] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10510 14:01:27.687752 <6>[ 0.561472] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10511 14:01:27.691143 <6>[ 0.568930] ACPI: Interpreter disabled.
10512 14:01:27.699820 <6>[ 0.575364] iommu: Default domain type: Translated
10513 14:01:27.706162 <6>[ 0.580477] iommu: DMA domain TLB invalidation policy: strict mode
10514 14:01:27.709448 <5>[ 0.587137] SCSI subsystem initialized
10515 14:01:27.716158 <6>[ 0.591381] usbcore: registered new interface driver usbfs
10516 14:01:27.722858 <6>[ 0.597112] usbcore: registered new interface driver hub
10517 14:01:27.726002 <6>[ 0.602663] usbcore: registered new device driver usb
10518 14:01:27.733159 <6>[ 0.608781] pps_core: LinuxPPS API ver. 1 registered
10519 14:01:27.743176 <6>[ 0.613974] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10520 14:01:27.746419 <6>[ 0.623316] PTP clock support registered
10521 14:01:27.749711 <6>[ 0.627556] EDAC MC: Ver: 3.0.0
10522 14:01:27.757134 <6>[ 0.632750] FPGA manager framework
10523 14:01:27.763499 <6>[ 0.636428] Advanced Linux Sound Architecture Driver Initialized.
10524 14:01:27.767018 <6>[ 0.643197] vgaarb: loaded
10525 14:01:27.773500 <6>[ 0.646341] clocksource: Switched to clocksource arch_sys_counter
10526 14:01:27.776837 <5>[ 0.652788] VFS: Disk quotas dquot_6.6.0
10527 14:01:27.783475 <6>[ 0.656977] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10528 14:01:27.786548 <6>[ 0.664170] pnp: PnP ACPI: disabled
10529 14:01:27.795170 <6>[ 0.670888] NET: Registered PF_INET protocol family
10530 14:01:27.804924 <6>[ 0.676480] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10531 14:01:27.816616 <6>[ 0.688771] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10532 14:01:27.826319 <6>[ 0.697587] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10533 14:01:27.832792 <6>[ 0.705560] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10534 14:01:27.842650 <6>[ 0.714259] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10535 14:01:27.849342 <6>[ 0.724001] TCP: Hash tables configured (established 65536 bind 65536)
10536 14:01:27.856110 <6>[ 0.730866] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10537 14:01:27.865779 <6>[ 0.738066] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 14:01:27.872659 <6>[ 0.745772] NET: Registered PF_UNIX/PF_LOCAL protocol family
10539 14:01:27.879069 <6>[ 0.751940] RPC: Registered named UNIX socket transport module.
10540 14:01:27.882351 <6>[ 0.758091] RPC: Registered udp transport module.
10541 14:01:27.888701 <6>[ 0.763024] RPC: Registered tcp transport module.
10542 14:01:27.895563 <6>[ 0.767958] RPC: Registered tcp NFSv4.1 backchannel transport module.
10543 14:01:27.898839 <6>[ 0.774622] PCI: CLS 0 bytes, default 64
10544 14:01:27.901859 <6>[ 0.779018] Unpacking initramfs...
10545 14:01:27.925942 <6>[ 0.798450] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10546 14:01:27.936052 <6>[ 0.807129] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10547 14:01:27.939384 <6>[ 0.815976] kvm [1]: IPA Size Limit: 40 bits
10548 14:01:27.945765 <6>[ 0.820504] kvm [1]: GICv3: no GICV resource entry
10549 14:01:27.949165 <6>[ 0.825525] kvm [1]: disabling GICv2 emulation
10550 14:01:27.955950 <6>[ 0.830212] kvm [1]: GIC system register CPU interface enabled
10551 14:01:27.959244 <6>[ 0.836379] kvm [1]: vgic interrupt IRQ18
10552 14:01:27.965758 <6>[ 0.840731] kvm [1]: VHE mode initialized successfully
10553 14:01:27.972495 <5>[ 0.847221] Initialise system trusted keyrings
10554 14:01:27.978911 <6>[ 0.852006] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10555 14:01:27.986391 <6>[ 0.861961] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10556 14:01:27.992886 <5>[ 0.868354] NFS: Registering the id_resolver key type
10557 14:01:27.996409 <5>[ 0.873654] Key type id_resolver registered
10558 14:01:28.002909 <5>[ 0.878072] Key type id_legacy registered
10559 14:01:28.009437 <6>[ 0.882357] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10560 14:01:28.015999 <6>[ 0.889283] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10561 14:01:28.022551 <6>[ 0.896998] 9p: Installing v9fs 9p2000 file system support
10562 14:01:28.059532 <5>[ 0.935195] Key type asymmetric registered
10563 14:01:28.062688 <5>[ 0.939525] Asymmetric key parser 'x509' registered
10564 14:01:28.072597 <6>[ 0.944664] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10565 14:01:28.076125 <6>[ 0.952277] io scheduler mq-deadline registered
10566 14:01:28.079427 <6>[ 0.957040] io scheduler kyber registered
10567 14:01:28.098389 <6>[ 0.974161] EINJ: ACPI disabled.
10568 14:01:28.130535 <4>[ 0.999432] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 14:01:28.140188 <4>[ 1.010036] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 14:01:28.154807 <6>[ 1.030611] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10571 14:01:28.162553 <6>[ 1.038563] printk: console [ttyS0] disabled
10572 14:01:28.190779 <6>[ 1.063206] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10573 14:01:28.197592 <6>[ 1.072689] printk: console [ttyS0] enabled
10574 14:01:28.200749 <6>[ 1.072689] printk: console [ttyS0] enabled
10575 14:01:28.207367 <6>[ 1.081582] printk: bootconsole [mtk8250] disabled
10576 14:01:28.210622 <6>[ 1.081582] printk: bootconsole [mtk8250] disabled
10577 14:01:28.217432 <6>[ 1.092600] SuperH (H)SCI(F) driver initialized
10578 14:01:28.220799 <6>[ 1.097869] msm_serial: driver initialized
10579 14:01:28.234374 <6>[ 1.106803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10580 14:01:28.244496 <6>[ 1.115345] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10581 14:01:28.250966 <6>[ 1.123888] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10582 14:01:28.260668 <6>[ 1.132518] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10583 14:01:28.270773 <6>[ 1.141226] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10584 14:01:28.277401 <6>[ 1.149946] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10585 14:01:28.287288 <6>[ 1.158486] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10586 14:01:28.293798 <6>[ 1.167277] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10587 14:01:28.303926 <6>[ 1.175820] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10588 14:01:28.315660 <6>[ 1.191400] loop: module loaded
10589 14:01:28.322285 <6>[ 1.197294] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10590 14:01:28.344692 <4>[ 1.220475] mtk-pmic-keys: Failed to locate of_node [id: -1]
10591 14:01:28.351520 <6>[ 1.227290] megasas: 07.719.03.00-rc1
10592 14:01:28.361164 <6>[ 1.236908] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10593 14:01:28.374034 <6>[ 1.249713] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10594 14:01:28.390885 <6>[ 1.266437] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10595 14:01:28.447379 <6>[ 1.316470] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10596 14:01:29.490812 <6>[ 2.366775] Freeing initrd memory: 38428K
10597 14:01:29.501008 <6>[ 2.377078] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10598 14:01:29.511919 <6>[ 2.387973] tun: Universal TUN/TAP device driver, 1.6
10599 14:01:29.515428 <6>[ 2.394027] thunder_xcv, ver 1.0
10600 14:01:29.518991 <6>[ 2.397531] thunder_bgx, ver 1.0
10601 14:01:29.521913 <6>[ 2.401028] nicpf, ver 1.0
10602 14:01:29.532414 <6>[ 2.405036] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10603 14:01:29.535742 <6>[ 2.412513] hns3: Copyright (c) 2017 Huawei Corporation.
10604 14:01:29.542486 <6>[ 2.418098] hclge is initializing
10605 14:01:29.545674 <6>[ 2.421675] e1000: Intel(R) PRO/1000 Network Driver
10606 14:01:29.552461 <6>[ 2.426804] e1000: Copyright (c) 1999-2006 Intel Corporation.
10607 14:01:29.555525 <6>[ 2.432816] e1000e: Intel(R) PRO/1000 Network Driver
10608 14:01:29.562337 <6>[ 2.438031] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10609 14:01:29.569050 <6>[ 2.444218] igb: Intel(R) Gigabit Ethernet Network Driver
10610 14:01:29.575401 <6>[ 2.449869] igb: Copyright (c) 2007-2014 Intel Corporation.
10611 14:01:29.582251 <6>[ 2.455704] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10612 14:01:29.588739 <6>[ 2.462222] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10613 14:01:29.592102 <6>[ 2.468679] sky2: driver version 1.30
10614 14:01:29.598500 <6>[ 2.473661] VFIO - User Level meta-driver version: 0.3
10615 14:01:29.606082 <6>[ 2.481875] usbcore: registered new interface driver usb-storage
10616 14:01:29.612661 <6>[ 2.488320] usbcore: registered new device driver onboard-usb-hub
10617 14:01:29.621803 <6>[ 2.497485] mt6397-rtc mt6359-rtc: registered as rtc0
10618 14:01:29.631716 <6>[ 2.502952] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T14:01:29 UTC (1706796089)
10619 14:01:29.634721 <6>[ 2.512508] i2c_dev: i2c /dev entries driver
10620 14:01:29.651467 <6>[ 2.524128] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10621 14:01:29.671378 <6>[ 2.547106] cpu cpu0: EM: created perf domain
10622 14:01:29.674618 <6>[ 2.551954] cpu cpu4: EM: created perf domain
10623 14:01:29.681515 <6>[ 2.557523] sdhci: Secure Digital Host Controller Interface driver
10624 14:01:29.688200 <6>[ 2.563957] sdhci: Copyright(c) Pierre Ossman
10625 14:01:29.694899 <6>[ 2.568906] Synopsys Designware Multimedia Card Interface Driver
10626 14:01:29.701724 <6>[ 2.575538] sdhci-pltfm: SDHCI platform and OF driver helper
10627 14:01:29.704719 <6>[ 2.575670] mmc0: CQHCI version 5.10
10628 14:01:29.711676 <6>[ 2.585560] ledtrig-cpu: registered to indicate activity on CPUs
10629 14:01:29.717927 <6>[ 2.592544] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10630 14:01:29.724824 <6>[ 2.599605] usbcore: registered new interface driver usbhid
10631 14:01:29.728092 <6>[ 2.605427] usbhid: USB HID core driver
10632 14:01:29.734798 <6>[ 2.609622] spi_master spi0: will run message pump with realtime priority
10633 14:01:29.776608 <6>[ 2.646033] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10634 14:01:29.795310 <6>[ 2.661059] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10635 14:01:29.802624 <6>[ 2.675968] cros-ec-spi spi0.0: Chrome EC device registered
10636 14:01:29.805615 <6>[ 2.682033] mmc0: Command Queue Engine enabled
10637 14:01:29.812433 <6>[ 2.686775] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10638 14:01:29.818911 <6>[ 2.694272] mmcblk0: mmc0:0001 DA4128 116 GiB
10639 14:01:29.827018 <6>[ 2.702723] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10640 14:01:29.834765 <6>[ 2.710115] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10641 14:01:29.844065 <6>[ 2.715228] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10642 14:01:29.847460 <6>[ 2.716039] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10643 14:01:29.854017 <6>[ 2.725942] NET: Registered PF_PACKET protocol family
10644 14:01:29.860959 <6>[ 2.730546] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 14:01:29.864148 <6>[ 2.735265] 9pnet: Installing 9P2000 support
10646 14:01:29.870664 <5>[ 2.746245] Key type dns_resolver registered
10647 14:01:29.874120 <6>[ 2.751204] registered taskstats version 1
10648 14:01:29.880444 <5>[ 2.755586] Loading compiled-in X.509 certificates
10649 14:01:29.908354 <4>[ 2.777495] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 14:01:29.918396 <4>[ 2.788214] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 14:01:29.924710 <3>[ 2.798747] debugfs: File 'uA_load' in directory '/' already present!
10652 14:01:29.931670 <3>[ 2.805499] debugfs: File 'min_uV' in directory '/' already present!
10653 14:01:29.937970 <3>[ 2.812118] debugfs: File 'max_uV' in directory '/' already present!
10654 14:01:29.944518 <3>[ 2.818730] debugfs: File 'constraint_flags' in directory '/' already present!
10655 14:01:29.956006 <3>[ 2.828519] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10656 14:01:29.965008 <6>[ 2.840759] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10657 14:01:29.971922 <6>[ 2.847732] xhci-mtk 11200000.usb: xHCI Host Controller
10658 14:01:29.978464 <6>[ 2.853225] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10659 14:01:29.988505 <6>[ 2.861056] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10660 14:01:29.994975 <6>[ 2.870470] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10661 14:01:30.001874 <6>[ 2.876543] xhci-mtk 11200000.usb: xHCI Host Controller
10662 14:01:30.008217 <6>[ 2.882019] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10663 14:01:30.014750 <6>[ 2.889665] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10664 14:01:30.021420 <6>[ 2.897319] hub 1-0:1.0: USB hub found
10665 14:01:30.025034 <6>[ 2.901329] hub 1-0:1.0: 1 port detected
10666 14:01:30.031384 <6>[ 2.905596] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10667 14:01:30.038228 <6>[ 2.914149] hub 2-0:1.0: USB hub found
10668 14:01:30.041330 <6>[ 2.918160] hub 2-0:1.0: 1 port detected
10669 14:01:30.050142 <6>[ 2.926154] mtk-msdc 11f70000.mmc: Got CD GPIO
10670 14:01:30.061181 <6>[ 2.933633] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10671 14:01:30.067612 <6>[ 2.941662] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10672 14:01:30.077871 <4>[ 2.949574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10673 14:01:30.087528 <6>[ 2.959109] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10674 14:01:30.094265 <6>[ 2.967191] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10675 14:01:30.101010 <6>[ 2.975350] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10676 14:01:30.110800 <6>[ 2.983286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10677 14:01:30.117258 <6>[ 2.991103] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10678 14:01:30.127050 <6>[ 2.998919] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10679 14:01:30.137149 <6>[ 3.009321] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10680 14:01:30.143770 <6>[ 3.017712] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10681 14:01:30.153457 <6>[ 3.026053] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10682 14:01:30.160215 <6>[ 3.034398] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10683 14:01:30.170175 <6>[ 3.042738] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10684 14:01:30.179958 <6>[ 3.051077] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10685 14:01:30.186800 <6>[ 3.059416] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10686 14:01:30.196774 <6>[ 3.067755] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10687 14:01:30.203097 <6>[ 3.076094] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10688 14:01:30.213125 <6>[ 3.084432] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10689 14:01:30.219841 <6>[ 3.092769] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10690 14:01:30.229832 <6>[ 3.101108] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10691 14:01:30.236369 <6>[ 3.109448] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10692 14:01:30.246179 <6>[ 3.117787] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10693 14:01:30.252905 <6>[ 3.126125] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10694 14:01:30.259240 <6>[ 3.134965] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10695 14:01:30.266255 <6>[ 3.142279] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10696 14:01:30.273237 <6>[ 3.149221] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10697 14:01:30.283603 <6>[ 3.156122] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10698 14:01:30.290195 <6>[ 3.163176] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10699 14:01:30.296690 <6>[ 3.170063] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10700 14:01:30.306602 <6>[ 3.179192] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10701 14:01:30.316507 <6>[ 3.188311] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10702 14:01:30.326458 <6>[ 3.197618] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10703 14:01:30.336401 <6>[ 3.207086] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10704 14:01:30.346195 <6>[ 3.216553] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10705 14:01:30.352827 <6>[ 3.225672] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10706 14:01:30.362985 <6>[ 3.235137] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10707 14:01:30.372628 <6>[ 3.244256] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10708 14:01:30.382450 <6>[ 3.253549] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10709 14:01:30.392614 <6>[ 3.263709] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10710 14:01:30.402977 <6>[ 3.275539] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10711 14:01:30.449806 <6>[ 3.322489] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10712 14:01:30.604474 <6>[ 3.480267] hub 1-1:1.0: USB hub found
10713 14:01:30.607659 <6>[ 3.484790] hub 1-1:1.0: 4 ports detected
10714 14:01:30.617370 <6>[ 3.493308] hub 1-1:1.0: USB hub found
10715 14:01:30.620464 <6>[ 3.497644] hub 1-1:1.0: 4 ports detected
10716 14:01:30.730045 <6>[ 3.602799] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10717 14:01:30.756745 <6>[ 3.632486] hub 2-1:1.0: USB hub found
10718 14:01:30.759760 <6>[ 3.636989] hub 2-1:1.0: 3 ports detected
10719 14:01:30.769333 <6>[ 3.645426] hub 2-1:1.0: USB hub found
10720 14:01:30.772698 <6>[ 3.649827] hub 2-1:1.0: 3 ports detected
10721 14:01:30.945935 <6>[ 3.818663] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10722 14:01:31.077247 <6>[ 3.953337] hub 1-1.4:1.0: USB hub found
10723 14:01:31.080802 <6>[ 3.957864] hub 1-1.4:1.0: 2 ports detected
10724 14:01:31.089015 <6>[ 3.965065] hub 1-1.4:1.0: USB hub found
10725 14:01:31.092528 <6>[ 3.969579] hub 1-1.4:1.0: 2 ports detected
10726 14:01:31.162227 <6>[ 4.034788] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10727 14:01:31.390082 <6>[ 4.262666] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10728 14:01:31.581957 <6>[ 4.454641] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10729 14:01:42.687005 <6>[ 15.567725] ALSA device list:
10730 14:01:42.693746 <6>[ 15.571021] No soundcards found.
10731 14:01:42.701789 <6>[ 15.579156] Freeing unused kernel memory: 8448K
10732 14:01:42.705351 <6>[ 15.584230] Run /init as init process
10733 14:01:42.753764 <6>[ 15.631146] NET: Registered PF_INET6 protocol family
10734 14:01:42.760641 <6>[ 15.637746] Segment Routing with IPv6
10735 14:01:42.763545 <6>[ 15.641724] In-situ OAM (IOAM) with IPv6
10736 14:01:42.797722 <30>[ 15.655111] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10737 14:01:42.800812 <30>[ 15.678892] systemd[1]: Detected architecture arm64.
10738 14:01:42.800900
10739 14:01:42.807798 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10740 14:01:42.807886
10741 14:01:42.821427 <30>[ 15.698586] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10742 14:01:42.958171 <30>[ 15.832141] systemd[1]: Queued start job for default target Graphical Interface.
10743 14:01:43.010175 <30>[ 15.887541] systemd[1]: Created slice system-getty.slice.
10744 14:01:43.017008 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10745 14:01:43.034350 <30>[ 15.911810] systemd[1]: Created slice system-modprobe.slice.
10746 14:01:43.040940 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10747 14:01:43.061966 <30>[ 15.939268] systemd[1]: Created slice system-serial\x2dgetty.slice.
10748 14:01:43.071728 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10749 14:01:43.085903 <30>[ 15.963320] systemd[1]: Created slice User and Session Slice.
10750 14:01:43.092562 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10751 14:01:43.113526 <30>[ 15.987431] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10752 14:01:43.123318 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10753 14:01:43.141383 <30>[ 16.015426] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10754 14:01:43.148040 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10755 14:01:43.171789 <30>[ 16.042738] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10756 14:01:43.178530 <30>[ 16.054911] systemd[1]: Reached target Local Encrypted Volumes.
10757 14:01:43.185404 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10758 14:01:43.201824 <30>[ 16.079242] systemd[1]: Reached target Paths.
10759 14:01:43.205382 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10760 14:01:43.221247 <30>[ 16.098659] systemd[1]: Reached target Remote File Systems.
10761 14:01:43.227821 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10762 14:01:43.245458 <30>[ 16.123008] systemd[1]: Reached target Slices.
10763 14:01:43.252082 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10764 14:01:43.265365 <30>[ 16.142676] systemd[1]: Reached target Swap.
10765 14:01:43.268431 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10766 14:01:43.289287 <30>[ 16.163229] systemd[1]: Listening on initctl Compatibility Named Pipe.
10767 14:01:43.295705 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10768 14:01:43.302169 <30>[ 16.178556] systemd[1]: Listening on Journal Audit Socket.
10769 14:01:43.308800 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10770 14:01:43.321680 <30>[ 16.199171] systemd[1]: Listening on Journal Socket (/dev/log).
10771 14:01:43.328140 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10772 14:01:43.346590 <30>[ 16.223998] systemd[1]: Listening on Journal Socket.
10773 14:01:43.353032 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10774 14:01:43.369281 <30>[ 16.243449] systemd[1]: Listening on Network Service Netlink Socket.
10775 14:01:43.375999 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10776 14:01:43.390592 <30>[ 16.267933] systemd[1]: Listening on udev Control Socket.
10777 14:01:43.397204 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10778 14:01:43.414248 <30>[ 16.291801] systemd[1]: Listening on udev Kernel Socket.
10779 14:01:43.421123 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10780 14:01:43.461302 <30>[ 16.338804] systemd[1]: Mounting Huge Pages File System...
10781 14:01:43.467966 Mounting [0;1;39mHuge Pages File System[0m...
10782 14:01:43.483094 <30>[ 16.360347] systemd[1]: Mounting POSIX Message Queue File System...
10783 14:01:43.489795 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10784 14:01:43.537302 <30>[ 16.414693] systemd[1]: Mounting Kernel Debug File System...
10785 14:01:43.543857 Mounting [0;1;39mKernel Debug File System[0m...
10786 14:01:43.561011 <30>[ 16.435125] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10787 14:01:43.574417 <30>[ 16.448332] systemd[1]: Starting Create list of static device nodes for the current kernel...
10788 14:01:43.580697 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10789 14:01:43.601416 <30>[ 16.478766] systemd[1]: Starting Load Kernel Module configfs...
10790 14:01:43.607872 Starting [0;1;39mLoad Kernel Module configfs[0m...
10791 14:01:43.625378 <30>[ 16.502754] systemd[1]: Starting Load Kernel Module drm...
10792 14:01:43.631778 Starting [0;1;39mLoad Kernel Module drm[0m...
10793 14:01:43.648452 <30>[ 16.522758] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10794 14:01:43.685688 <30>[ 16.562994] systemd[1]: Starting Journal Service...
10795 14:01:43.688864 Starting [0;1;39mJournal Service[0m...
10796 14:01:43.708455 <30>[ 16.585739] systemd[1]: Starting Load Kernel Modules...
10797 14:01:43.714903 Starting [0;1;39mLoad Kernel Modules[0m...
10798 14:01:43.735125 <30>[ 16.609204] systemd[1]: Starting Remount Root and Kernel File Systems...
10799 14:01:43.741473 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10800 14:01:43.756340 <30>[ 16.633680] systemd[1]: Starting Coldplug All udev Devices...
10801 14:01:43.762761 Starting [0;1;39mColdplug All udev Devices[0m...
10802 14:01:43.780457 <30>[ 16.657878] systemd[1]: Started Journal Service.
10803 14:01:43.786903 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10804 14:01:43.804410 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10805 14:01:43.822668 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10806 14:01:43.838036 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10807 14:01:43.858245 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10808 14:01:43.875527 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10809 14:01:43.895521 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10810 14:01:43.915177 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10811 14:01:43.935811 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10812 14:01:43.949048 See 'systemctl status systemd-remount-fs.service' for details.
10813 14:01:43.994643 Mounting [0;1;39mKernel Configuration File System[0m...
10814 14:01:44.016527 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10815 14:01:44.029325 <46>[ 16.903510] systemd-journald[184]: Received client request to flush runtime journal.
10816 14:01:44.062871 Starting [0;1;39mLoad/Save Random Seed[0m...
10817 14:01:44.086784 Starting [0;1;39mApply Kernel Variables[0m...
10818 14:01:44.110411 Starting [0;1;39mCreate System Users[0m...
10819 14:01:44.131284 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10820 14:01:44.146175 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10821 14:01:44.170311 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10822 14:01:44.187755 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10823 14:01:44.207268 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10824 14:01:44.227465 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10825 14:01:44.282058 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10826 14:01:44.304221 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10827 14:01:44.317460 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10828 14:01:44.333203 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10829 14:01:44.369720 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10830 14:01:44.397767 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10831 14:01:44.423963 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10832 14:01:44.446862 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10833 14:01:44.506800 Starting [0;1;39mNetwork Service[0m...
10834 14:01:44.534381 Starting [0;1;39mNetwork Time Synchronization[0m...
10835 14:01:44.554217 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10836 14:01:44.565428 <6>[ 17.439767] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10837 14:01:44.588881 <4>[ 17.463089] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10838 14:01:44.592125 <6>[ 17.463478] remoteproc remoteproc0: scp is available
10839 14:01:44.602441 <6>[ 17.465054] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10840 14:01:44.608792 <6>[ 17.465102] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10841 14:01:44.618670 <6>[ 17.465112] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10842 14:01:44.625914 <4>[ 17.470869] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10843 14:01:44.631945 <6>[ 17.476214] remoteproc remoteproc0: powering up scp
10844 14:01:44.635599 <6>[ 17.501301] mc: Linux media interface: v0.10
10845 14:01:44.645168 <6>[ 17.508615] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10846 14:01:44.648447 <6>[ 17.526403] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10847 14:01:44.655182 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10848 14:01:44.664347 <6>[ 17.541929] usbcore: registered new device driver r8152-cfgselector
10849 14:01:44.679109 <3>[ 17.553049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10850 14:01:44.688863 [[0;32m OK [<3>[ 17.562705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 14:01:44.698653 0m] Found device<3>[ 17.571793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 14:01:44.708700 [0;1;39m/dev/t<6>[ 17.575896] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10853 14:01:44.718770 <3>[ 17.581246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 14:01:44.718853 tyS0[0m.
10855 14:01:44.728482 <3>[ 17.581294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 14:01:44.735183 <3>[ 17.581301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 14:01:44.744783 <3>[ 17.581318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 14:01:44.751506 <3>[ 17.581325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 14:01:44.758117 <3>[ 17.581398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 14:01:44.767965 <6>[ 17.589053] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10861 14:01:44.771534 <6>[ 17.589071] pci_bus 0000:00: root bus resource [bus 00-ff]
10862 14:01:44.781342 <6>[ 17.589085] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10863 14:01:44.791111 <6>[ 17.589091] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10864 14:01:44.794355 <6>[ 17.589166] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10865 14:01:44.804383 <6>[ 17.589188] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10866 14:01:44.807642 <6>[ 17.589290] pci 0000:00:00.0: supports D1 D2
10867 14:01:44.814432 <6>[ 17.589295] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10868 14:01:44.824163 <6>[ 17.591470] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10869 14:01:44.830780 <6>[ 17.591718] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10870 14:01:44.837310 <6>[ 17.591760] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10871 14:01:44.843910 <6>[ 17.591786] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10872 14:01:44.850457 <6>[ 17.591805] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10873 14:01:44.857372 <6>[ 17.591960] pci 0000:01:00.0: supports D1 D2
10874 14:01:44.863812 <6>[ 17.591964] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10875 14:01:44.873611 <6>[ 17.595481] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10876 14:01:44.880279 <6>[ 17.597118] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10877 14:01:44.886955 <3>[ 17.600739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 14:01:44.896833 <3>[ 17.600750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 14:01:44.903439 <3>[ 17.600754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 14:01:44.913404 <3>[ 17.600833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 14:01:44.919813 <3>[ 17.600839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 14:01:44.929838 <3>[ 17.600844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 14:01:44.936622 <3>[ 17.600848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 14:01:44.946370 <3>[ 17.600854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 14:01:44.953057 <3>[ 17.600878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 14:01:44.959404 <6>[ 17.602642] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10887 14:01:44.969486 <6>[ 17.612515] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10888 14:01:44.976054 <6>[ 17.620692] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10889 14:01:44.983085 <6>[ 17.634709] videodev: Linux video capture interface: v2.00
10890 14:01:44.990345 <6>[ 17.643197] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10891 14:01:44.993933 <6>[ 17.679564] Bluetooth: Core ver 2.22
10892 14:01:45.003634 <6>[ 17.686113] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10893 14:01:45.010196 <6>[ 17.686123] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10894 14:01:45.017668 <6>[ 17.686300] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10895 14:01:45.027869 <6>[ 17.686321] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10896 14:01:45.034209 <6>[ 17.686432] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10897 14:01:45.040966 <6>[ 17.686462] pci 0000:00:00.0: PCI bridge to [bus 01]
10898 14:01:45.047815 <6>[ 17.686478] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10899 14:01:45.054355 <6>[ 17.686865] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10900 14:01:45.060769 <6>[ 17.689347] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10901 14:01:45.064376 <6>[ 17.689586] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10902 14:01:45.071760 <6>[ 17.691011] NET: Registered PF_BLUETOOTH protocol family
10903 14:01:45.078330 <6>[ 17.691396] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10904 14:01:45.085091 <6>[ 17.697457] remoteproc remoteproc0: remote processor scp is now up
10905 14:01:45.094935 <6>[ 17.697783] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10906 14:01:45.101441 <6>[ 17.705845] Bluetooth: HCI device and connection manager initialized
10907 14:01:45.108204 <5>[ 17.708823] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10908 14:01:45.121454 <6>[ 17.713637] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10909 14:01:45.127851 <6>[ 17.713647] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10910 14:01:45.137975 <6>[ 17.715953] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10911 14:01:45.144848 <4>[ 17.716001] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10912 14:01:45.154793 <4>[ 17.716015] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10913 14:01:45.158055 <6>[ 17.719574] Bluetooth: HCI socket layer initialized
10914 14:01:45.164724 <6>[ 17.720592] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10915 14:01:45.171468 <5>[ 17.723829] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10916 14:01:45.181357 <5>[ 17.724311] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10917 14:01:45.191484 <4>[ 17.724397] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10918 14:01:45.194757 <6>[ 17.724406] cfg80211: failed to load regulatory.db
10919 14:01:45.201522 <6>[ 17.727927] usbcore: registered new interface driver uvcvideo
10920 14:01:45.208062 <6>[ 17.734586] Bluetooth: L2CAP socket layer initialized
10921 14:01:45.211409 <6>[ 17.770613] r8152 2-1.3:1.0 eth0: v1.12.13
10922 14:01:45.214666 <6>[ 17.770768] Bluetooth: SCO socket layer initialized
10923 14:01:45.221078 <6>[ 17.778951] usbcore: registered new interface driver r8152
10924 14:01:45.231061 <4>[ 17.804621] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10925 14:01:45.234353 <4>[ 17.804621] Fallback method does not support PEC.
10926 14:01:45.244049 <6>[ 17.823405] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10927 14:01:45.247651 <6>[ 17.835932] usbcore: registered new interface driver cdc_ether
10928 14:01:45.254251 <6>[ 17.842617] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10929 14:01:45.260779 <6>[ 17.852567] usbcore: registered new interface driver btusb
10930 14:01:45.270548 <4>[ 17.853141] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10931 14:01:45.277210 <3>[ 17.853150] Bluetooth: hci0: Failed to load firmware file (-2)
10932 14:01:45.283919 <3>[ 17.853153] Bluetooth: hci0: Failed to set up firmware (-2)
10933 14:01:45.293657 <4>[ 17.853157] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10934 14:01:45.300575 <6>[ 17.860151] usbcore: registered new interface driver r8153_ecm
10935 14:01:45.307080 <3>[ 17.873340] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10936 14:01:45.317000 <3>[ 17.874139] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 14:01:45.326927 <3>[ 17.874951] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 14:01:45.333458 <6>[ 17.878418] mt7921e 0000:01:00.0: ASIC revision: 79610010
10939 14:01:45.336711 <6>[ 17.893558] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10940 14:01:45.346690 <3>[ 17.902895] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 14:01:45.356454 <3>[ 17.922514] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10942 14:01:45.363377 <3>[ 17.950424] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 14:01:45.373086 <6>[ 18.003534] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10944 14:01:45.373171 <6>[ 18.003534]
10945 14:01:45.383054 <3>[ 18.033038] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 14:01:45.389467 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10947 14:01:45.417796 <3>[ 18.292275] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 14:01:45.427831 <6>[ 18.298955] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10949 14:01:45.449762 [[0;32m OK [0m] Finished [0;1;39mUpdate UTM<3>[ 18.323785] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 14:01:45.452755 P about System Boot/Shutdown[0m.
10951 14:01:45.482307 <3>[ 18.356609] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 14:01:45.583907 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10953 14:01:45.596945 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10954 14:01:45.613123 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10955 14:01:45.632161 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10956 14:01:45.648708 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10957 14:01:45.681270 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10958 14:01:45.705781 Starting [0;1;39mNetwork Name Resolution[0m...
10959 14:01:45.727669 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10960 14:01:45.741672 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10961 14:01:45.762566 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10962 14:01:45.780765 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10963 14:01:45.793344 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10964 14:01:45.813367 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10965 14:01:45.825411 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10966 14:01:45.841329 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10967 14:01:45.898391 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10968 14:01:45.932940 Starting [0;1;39mUser Login Management[0m...
10969 14:01:45.954508 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10970 14:01:45.970467 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10971 14:01:45.985820 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10972 14:01:46.001633 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10973 14:01:46.020194 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10974 14:01:46.057877 Starting [0;1;39mPermit User Sessions[0m...
10975 14:01:46.076098 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10976 14:01:46.094020 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10977 14:01:46.119313 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10978 14:01:46.166817 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10979 14:01:46.174452 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10980 14:01:46.190043 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10981 14:01:46.205876 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10982 14:01:46.258226 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10983 14:01:46.275956 <6>[ 19.153731] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10984 14:01:46.294380 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10985 14:01:46.322454
10986 14:01:46.322551
10987 14:01:46.326131 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10988 14:01:46.326216
10989 14:01:46.329363 debian-bullseye-arm64 login: root (automatic login)
10990 14:01:46.329445
10991 14:01:46.329549
10992 14:01:46.346388 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
10993 14:01:46.346472
10994 14:01:46.353087 The programs included with the Debian GNU/Linux system are free software;
10995 14:01:46.359452 the exact distribution terms for each program are described in the
10996 14:01:46.362890 individual files in /usr/share/doc/*/copyright.
10997 14:01:46.362973
10998 14:01:46.369377 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10999 14:01:46.372951 permitted by applicable law.
11000 14:01:46.373340 Matched prompt #10: / #
11002 14:01:46.373609 Setting prompt string to ['/ #']
11003 14:01:46.373702 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11005 14:01:46.373888 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11006 14:01:46.373970 start: 2.2.6 expect-shell-connection (timeout 00:02:56) [common]
11007 14:01:46.374039 Setting prompt string to ['/ #']
11008 14:01:46.374099 Forcing a shell prompt, looking for ['/ #']
11010 14:01:46.424310 / #
11011 14:01:46.424430 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11012 14:01:46.424540 Waiting using forced prompt support (timeout 00:02:30)
11013 14:01:46.429194
11014 14:01:46.429467 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11015 14:01:46.429601 start: 2.2.7 export-device-env (timeout 00:02:56) [common]
11016 14:01:46.429694 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11017 14:01:46.429777 end: 2.2 depthcharge-retry (duration 00:02:04) [common]
11018 14:01:46.429857 end: 2 depthcharge-action (duration 00:02:04) [common]
11019 14:01:46.429944 start: 3 lava-test-retry (timeout 00:07:35) [common]
11020 14:01:46.430026 start: 3.1 lava-test-shell (timeout 00:07:35) [common]
11021 14:01:46.430100 Using namespace: common
11023 14:01:46.530429 / # #
11024 14:01:46.530575 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11025 14:01:46.535464 #
11026 14:01:46.535735 Using /lava-12682970
11028 14:01:46.636049 / # export SHELL=/bin/sh
11029 14:01:46.636225 export SHELL=/bin/sh<6>[ 19.477121] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11030 14:01:46.636303 <6>[ 19.485209] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11031 14:01:46.640966
11033 14:01:46.741551 / # . /lava-12682970/environment
11034 14:01:46.747005 . /lava-12682970/environment
11036 14:01:46.847551 / # /lava-12682970/bin/lava-test-runner /lava-12682970/0
11037 14:01:46.847689 Test shell timeout: 10s (minimum of the action and connection timeout)
11038 14:01:46.852407 /lava-12682970/bin/lava-test-runner /lava-12682970/0
11039 14:01:46.875982 + export TESTRUN_ID=0_v4l2-compliance-uvc
11040 14:01:46.879153 + cd /lava-12682970/0/tests/0_v4l2-compliance-uvc
11041 14:01:46.879236 + cat uuid
11042 14:01:46.882604 + UUID=12682970_1.5.2.3.1
11043 14:01:46.882686 + set +x
11044 14:01:46.888975 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12682970_1.5.2.3.1>
11045 14:01:46.889234 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12682970_1.5.2.3.1
11046 14:01:46.889311 Starting test lava.0_v4l2-compliance-uvc (12682970_1.5.2.3.1)
11047 14:01:46.889397 Skipping test definition patterns.
11048 14:01:46.892553 + /usr/bin/v4l2-parser.sh -d uvcvideo
11049 14:01:46.899023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11050 14:01:46.899128 device: /dev/video0
11051 14:01:46.899396 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11053 14:01:53.397864 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11054 14:01:53.408963 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11055 14:01:53.420418
11056 14:01:53.439287 Compliance test for uvcvideo device /dev/video0:
11057 14:01:53.447490
11058 14:01:53.463894 Driver Info:
11059 14:01:53.478096 Driver name : uvcvideo
11060 14:01:53.495877 Card type : HD User Facing: HD User Facing
11061 14:01:53.506441 Bus info : usb-11200000.usb-1.4.1
11062 14:01:53.514269 Driver version : 6.1.72
11063 14:01:53.530631 Capabilities : 0x84a00001
11064 14:01:53.543506 Metadata Capture
11065 14:01:53.559757 Streaming
11066 14:01:53.576336 Extended Pix Format
11067 14:01:53.590722 Device Capabilities
11068 14:01:53.604143 Device Caps : 0x04200001
11069 14:01:53.617818 Streaming
11070 14:01:53.628130 Extended Pix Format
11071 14:01:53.639714 Media Driver Info:
11072 14:01:53.654503 Driver name : uvcvideo
11073 14:01:53.670121 Model : HD User Facing: HD User Facing
11074 14:01:53.678173 Serial : 200901010001
11075 14:01:53.692464 Bus info : usb-11200000.usb-1.4.1
11076 14:01:53.699390 Media version : 6.1.72
11077 14:01:53.716144 Hardware revision: 0x00009758 (38744)
11078 14:01:53.723308 Driver version : 6.1.72
11079 14:01:53.734031 Interface Info:
11080 14:01:53.748577 <LAVA_SIGNAL_TESTSET START Interface-Info>
11081 14:01:53.748669 ID : 0x03000002
11082 14:01:53.748955 Received signal: <TESTSET> START Interface-Info
11083 14:01:53.749059 Starting test_set Interface-Info
11084 14:01:53.758421 Type : V4L Video
11085 14:01:53.772628 Entity Info:
11086 14:01:53.779536 <LAVA_SIGNAL_TESTSET STOP>
11087 14:01:53.779791 Received signal: <TESTSET> STOP
11088 14:01:53.779862 Closing test_set Interface-Info
11089 14:01:53.789433 <LAVA_SIGNAL_TESTSET START Entity-Info>
11090 14:01:53.789727 Received signal: <TESTSET> START Entity-Info
11091 14:01:53.789795 Starting test_set Entity-Info
11092 14:01:53.792616 ID : 0x00000001 (1)
11093 14:01:53.808194 Name : HD User Facing: HD User Facing
11094 14:01:53.816138 Function : V4L2 I/O
11095 14:01:53.829179 Flags : default
11096 14:01:53.843165 Pad 0x01000007 : 0: Sink
11097 14:01:53.867430 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11098 14:01:53.867553
11099 14:01:53.880641 Required ioctls:
11100 14:01:53.887446 <LAVA_SIGNAL_TESTSET STOP>
11101 14:01:53.887707 Received signal: <TESTSET> STOP
11102 14:01:53.887778 Closing test_set Entity-Info
11103 14:01:53.896972 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11104 14:01:53.897245 Received signal: <TESTSET> START Required-ioctls
11105 14:01:53.897316 Starting test_set Required-ioctls
11106 14:01:53.900355 test MC information (see 'Media Driver Info' above): OK
11107 14:01:53.924249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11108 14:01:53.924536 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11110 14:01:53.927551 test VIDIOC_QUERYCAP: OK
11111 14:01:53.945824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11112 14:01:53.946093 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11114 14:01:53.949086 test invalid ioctls: OK
11115 14:01:53.975099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11116 14:01:53.975185
11117 14:01:53.975420 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11119 14:01:53.986841 Allow for multiple opens:
11120 14:01:53.994450 <LAVA_SIGNAL_TESTSET STOP>
11121 14:01:53.994705 Received signal: <TESTSET> STOP
11122 14:01:53.994775 Closing test_set Required-ioctls
11123 14:01:54.003832 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11124 14:01:54.004087 Received signal: <TESTSET> START Allow-for-multiple-opens
11125 14:01:54.004156 Starting test_set Allow-for-multiple-opens
11126 14:01:54.006945 test second /dev/video0 open: OK
11127 14:01:54.030798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11128 14:01:54.031058 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11130 14:01:54.034162 test VIDIOC_QUERYCAP: OK
11131 14:01:54.057014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11132 14:01:54.057273 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11134 14:01:54.060175 test VIDIOC_G/S_PRIORITY: OK
11135 14:01:54.081995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11136 14:01:54.082248 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11138 14:01:54.085362 test for unlimited opens: OK
11139 14:01:54.112325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11140 14:01:54.112420
11141 14:01:54.112654 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11143 14:01:54.122675 Debug ioctls:
11144 14:01:54.130917 <LAVA_SIGNAL_TESTSET STOP>
11145 14:01:54.131171 Received signal: <TESTSET> STOP
11146 14:01:54.131243 Closing test_set Allow-for-multiple-opens
11147 14:01:54.140175 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11148 14:01:54.140426 Received signal: <TESTSET> START Debug-ioctls
11149 14:01:54.140493 Starting test_set Debug-ioctls
11150 14:01:54.143498 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11151 14:01:54.164065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11152 14:01:54.164319 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11154 14:01:54.170472 test VIDIOC_LOG_STATUS: OK (Not Supported)
11155 14:01:54.190266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11156 14:01:54.190350
11157 14:01:54.190585 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11159 14:01:54.201885 Input ioctls:
11160 14:01:54.208154 <LAVA_SIGNAL_TESTSET STOP>
11161 14:01:54.208408 Received signal: <TESTSET> STOP
11162 14:01:54.208480 Closing test_set Debug-ioctls
11163 14:01:54.218101 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11164 14:01:54.218362 Received signal: <TESTSET> START Input-ioctls
11165 14:01:54.218432 Starting test_set Input-ioctls
11166 14:01:54.221526 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11167 14:01:54.245924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11168 14:01:54.246183 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11170 14:01:54.249185 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11171 14:01:54.267702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11172 14:01:54.267957 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11174 14:01:54.274540 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11175 14:01:54.293398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11176 14:01:54.293705 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11178 14:01:54.299957 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11179 14:01:54.318728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11180 14:01:54.318990 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11182 14:01:54.321848 test VIDIOC_G/S/ENUMINPUT: OK
11183 14:01:54.344629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11184 14:01:54.344898 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11186 14:01:54.351270 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11187 14:01:54.368168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11188 14:01:54.368431 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11190 14:01:54.371444 Inputs: 1 Audio Inputs: 0 Tuners: 0
11191 14:01:54.383745
11192 14:01:54.401858 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11193 14:01:54.428053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11194 14:01:54.428326 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11196 14:01:54.434498 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11197 14:01:54.461068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11198 14:01:54.461345 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11200 14:01:54.467418 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11201 14:01:54.485686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11202 14:01:54.485944 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11204 14:01:54.492477 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11205 14:01:54.517155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11206 14:01:54.517420 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11208 14:01:54.523839 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11209 14:01:54.541269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11210 14:01:54.541360
11211 14:01:54.541595 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11213 14:01:54.560737 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11214 14:01:54.584184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11215 14:01:54.584442 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11217 14:01:54.590871 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11218 14:01:54.614123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11219 14:01:54.614387 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11221 14:01:54.617410 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11222 14:01:54.637170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11223 14:01:54.637438 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11225 14:01:54.640433 test VIDIOC_G/S_EDID: OK (Not Supported)
11226 14:01:54.662404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11227 14:01:54.662488
11228 14:01:54.662723 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11230 14:01:54.674354 Control ioctls (Input 0):
11231 14:01:54.683859 <LAVA_SIGNAL_TESTSET STOP>
11232 14:01:54.684144 Received signal: <TESTSET> STOP
11233 14:01:54.684242 Closing test_set Input-ioctls
11234 14:01:54.702324 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11235 14:01:54.702584 Received signal: <TESTSET> START Control-ioctls-Input-0
11236 14:01:54.702653 Starting test_set Control-ioctls-Input-0
11237 14:01:54.705821 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11238 14:01:54.736375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11239 14:01:54.736477 test VIDIOC_QUERYCTRL: OK
11240 14:01:54.736716 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11242 14:01:54.758588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11243 14:01:54.758842 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11245 14:01:54.761893 test VIDIOC_G/S_CTRL: OK
11246 14:01:54.786622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11247 14:01:54.786878 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11249 14:01:54.789830 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11250 14:01:54.817504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11251 14:01:54.817786 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11253 14:01:54.823812 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11254 14:01:54.845596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11255 14:01:54.845878 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11257 14:01:54.848769 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11258 14:01:54.867481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11259 14:01:54.867734 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11261 14:01:54.870887 Standard Controls: 16 Private Controls: 0
11262 14:01:54.879096
11263 14:01:54.896749 Format ioctls (Input 0):
11264 14:01:54.903949 <LAVA_SIGNAL_TESTSET STOP>
11265 14:01:54.904205 Received signal: <TESTSET> STOP
11266 14:01:54.904276 Closing test_set Control-ioctls-Input-0
11267 14:01:54.913372 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11268 14:01:54.913624 Received signal: <TESTSET> START Format-ioctls-Input-0
11269 14:01:54.913695 Starting test_set Format-ioctls-Input-0
11270 14:01:54.916896 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11271 14:01:54.941977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11272 14:01:54.942260 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11274 14:01:54.945029 test VIDIOC_G/S_PARM: OK
11275 14:01:54.962938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11276 14:01:54.963198 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11278 14:01:54.966229 test VIDIOC_G_FBUF: OK (Not Supported)
11279 14:01:54.989527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11280 14:01:54.989787 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11282 14:01:54.993198 test VIDIOC_G_FMT: OK
11283 14:01:55.014059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11284 14:01:55.014320 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11286 14:01:55.017262 test VIDIOC_TRY_FMT: OK
11287 14:01:55.039427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11288 14:01:55.039716 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11290 14:01:55.046208 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11291 14:01:55.052172 test VIDIOC_S_FMT: OK
11292 14:01:55.081658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11293 14:01:55.081923 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11295 14:01:55.084591 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11296 14:01:55.108179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11297 14:01:55.108444 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11299 14:01:55.111384 test Cropping: OK (Not Supported)
11300 14:01:55.135343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11301 14:01:55.135599 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11303 14:01:55.138631 test Composing: OK (Not Supported)
11304 14:01:55.160351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11305 14:01:55.160607 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11307 14:01:55.163520 test Scaling: OK (Not Supported)
11308 14:01:55.185382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11309 14:01:55.185498
11310 14:01:55.185734 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11312 14:01:55.194473 Codec ioctls (Input 0):
11313 14:01:55.202003 <LAVA_SIGNAL_TESTSET STOP>
11314 14:01:55.202261 Received signal: <TESTSET> STOP
11315 14:01:55.202332 Closing test_set Format-ioctls-Input-0
11316 14:01:55.211896 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11317 14:01:55.212149 Received signal: <TESTSET> START Codec-ioctls-Input-0
11318 14:01:55.212217 Starting test_set Codec-ioctls-Input-0
11319 14:01:55.215290 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11320 14:01:55.237818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11321 14:01:55.238076 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11323 14:01:55.244474 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11324 14:01:55.264386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11325 14:01:55.264640 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11327 14:01:55.271042 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11328 14:01:55.289028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11329 14:01:55.289117
11330 14:01:55.289381 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11332 14:01:55.299939 Buffer ioctls (Input 0):
11333 14:01:55.309864 <LAVA_SIGNAL_TESTSET STOP>
11334 14:01:55.310114 Received signal: <TESTSET> STOP
11335 14:01:55.310182 Closing test_set Codec-ioctls-Input-0
11336 14:01:55.320592 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11337 14:01:55.320847 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11338 14:01:55.320944 Starting test_set Buffer-ioctls-Input-0
11339 14:01:55.323656 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11340 14:01:55.349629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11341 14:01:55.349714 test VIDIOC_EXPBUF: OK
11342 14:01:55.349950 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11344 14:01:55.378790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11345 14:01:55.379051 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11347 14:01:55.382019 test Requests: OK (Not Supported)
11348 14:01:55.408424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11349 14:01:55.408509
11350 14:01:55.408744 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11352 14:01:55.417727 Test input 0:
11353 14:01:55.428712
11354 14:01:55.438666 Streaming ioctls:
11355 14:01:55.445605 <LAVA_SIGNAL_TESTSET STOP>
11356 14:01:55.445858 Received signal: <TESTSET> STOP
11357 14:01:55.445929 Closing test_set Buffer-ioctls-Input-0
11358 14:01:55.455817 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11359 14:01:55.456069 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11360 14:01:55.456138 Starting test_set Streaming-ioctls_Test-input-0
11361 14:01:55.459364 test read/write: OK (Not Supported)
11362 14:01:55.480993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11363 14:01:55.481253 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11365 14:01:55.483899 test blocking wait: OK
11366 14:01:55.505856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11367 14:01:55.506112 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11369 14:01:55.515821 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11370 14:01:55.518997 test MMAP (no poll): FAIL
11371 14:01:55.541776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11372 14:01:55.542038 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11374 14:01:55.551800 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11375 14:01:55.551884 test MMAP (select): FAIL
11376 14:01:55.576720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11377 14:01:55.576976 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11379 14:01:55.586589 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11380 14:01:55.589833 test MMAP (epoll): FAIL
11381 14:01:55.617674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11382 14:01:55.617763
11383 14:01:55.618000 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11385 14:01:55.630305
11386 14:01:55.838672
11387 14:01:55.849242 test USERPTR (no poll): OK
11388 14:01:55.875069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11389 14:01:55.875158
11390 14:01:55.875397 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11392 14:01:55.889001
11393 14:01:56.090348
11394 14:01:56.102440 test USERPTR (select): OK
11395 14:01:56.127141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11396 14:01:56.127425 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11398 14:01:56.133640 test DMABUF: Cannot test, specify --expbuf-device
11399 14:01:56.138035
11400 14:01:56.160606 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11401 14:01:56.163841 <LAVA_TEST_RUNNER EXIT>
11402 14:01:56.164096 ok: lava_test_shell seems to have completed
11403 14:01:56.164265 Marking unfinished test run as failed
11405 14:01:56.165595 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11406 14:01:56.165729 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11407 14:01:56.165826 end: 3 lava-test-retry (duration 00:00:10) [common]
11408 14:01:56.165940 start: 4 finalize (timeout 00:07:25) [common]
11409 14:01:56.166070 start: 4.1 power-off (timeout 00:00:30) [common]
11410 14:01:56.166218 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11411 14:01:56.243921 >> Command sent successfully.
11412 14:01:56.247814 Returned 0 in 0 seconds
11413 14:01:56.348284 end: 4.1 power-off (duration 00:00:00) [common]
11415 14:01:56.348598 start: 4.2 read-feedback (timeout 00:07:25) [common]
11416 14:01:56.348910 Listened to connection for namespace 'common' for up to 1s
11417 14:01:57.349596 Finalising connection for namespace 'common'
11418 14:01:57.349763 Disconnecting from shell: Finalise
11419 14:01:57.349840 / #
11420 14:01:57.450162 end: 4.2 read-feedback (duration 00:00:01) [common]
11421 14:01:57.450322 end: 4 finalize (duration 00:00:01) [common]
11422 14:01:57.450433 Cleaning after the job
11423 14:01:57.450540 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/ramdisk
11424 14:01:57.456349 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/kernel
11425 14:01:57.472042 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/dtb
11426 14:01:57.472228 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682970/tftp-deploy-3sk4mi01/modules
11427 14:01:57.479659 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682970
11428 14:01:57.547338 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682970
11429 14:01:57.547499 Job finished correctly