Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 16
- Kernel Errors: 27
1 13:52:20.102204 lava-dispatcher, installed at version: 2023.10
2 13:52:20.102434 start: 0 validate
3 13:52:20.102570 Start time: 2024-02-01 13:52:20.102561+00:00 (UTC)
4 13:52:20.102705 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:52:20.102854 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:52:20.370252 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:52:20.370587 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:52:56.661807 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:52:56.662692 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:52:56.926208 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:52:56.926365 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:53:03.186582 validate duration: 43.08
14 13:53:03.186847 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:53:03.186947 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:53:03.187033 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:53:03.187160 Not decompressing ramdisk as can be used compressed.
18 13:53:03.187245 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 13:53:03.187310 saving as /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/ramdisk/rootfs.cpio.gz
20 13:53:03.187375 total size: 8181372 (7 MB)
21 13:53:03.453605 progress 0 % (0 MB)
22 13:53:03.455957 progress 5 % (0 MB)
23 13:53:03.458139 progress 10 % (0 MB)
24 13:53:03.460450 progress 15 % (1 MB)
25 13:53:03.462616 progress 20 % (1 MB)
26 13:53:03.464924 progress 25 % (1 MB)
27 13:53:03.467057 progress 30 % (2 MB)
28 13:53:03.469394 progress 35 % (2 MB)
29 13:53:03.471634 progress 40 % (3 MB)
30 13:53:03.473927 progress 45 % (3 MB)
31 13:53:03.476057 progress 50 % (3 MB)
32 13:53:03.478322 progress 55 % (4 MB)
33 13:53:03.480371 progress 60 % (4 MB)
34 13:53:03.482627 progress 65 % (5 MB)
35 13:53:03.484667 progress 70 % (5 MB)
36 13:53:03.486908 progress 75 % (5 MB)
37 13:53:03.488960 progress 80 % (6 MB)
38 13:53:03.491335 progress 85 % (6 MB)
39 13:53:03.493516 progress 90 % (7 MB)
40 13:53:03.495774 progress 95 % (7 MB)
41 13:53:03.498071 progress 100 % (7 MB)
42 13:53:03.498282 7 MB downloaded in 0.31 s (25.10 MB/s)
43 13:53:03.498436 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:53:03.498675 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:53:03.498761 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:53:03.498858 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:53:03.498997 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:53:03.499086 saving as /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/kernel/Image
50 13:53:03.499178 total size: 51532288 (49 MB)
51 13:53:03.499239 No compression specified
52 13:53:03.500437 progress 0 % (0 MB)
53 13:53:03.514038 progress 5 % (2 MB)
54 13:53:03.527733 progress 10 % (4 MB)
55 13:53:03.541399 progress 15 % (7 MB)
56 13:53:03.555089 progress 20 % (9 MB)
57 13:53:03.568802 progress 25 % (12 MB)
58 13:53:03.582281 progress 30 % (14 MB)
59 13:53:03.595981 progress 35 % (17 MB)
60 13:53:03.609720 progress 40 % (19 MB)
61 13:53:03.623282 progress 45 % (22 MB)
62 13:53:03.637011 progress 50 % (24 MB)
63 13:53:03.650687 progress 55 % (27 MB)
64 13:53:03.664712 progress 60 % (29 MB)
65 13:53:03.678328 progress 65 % (31 MB)
66 13:53:03.691753 progress 70 % (34 MB)
67 13:53:03.705364 progress 75 % (36 MB)
68 13:53:03.718795 progress 80 % (39 MB)
69 13:53:03.732147 progress 85 % (41 MB)
70 13:53:03.745799 progress 90 % (44 MB)
71 13:53:03.759232 progress 95 % (46 MB)
72 13:53:03.772770 progress 100 % (49 MB)
73 13:53:03.773017 49 MB downloaded in 0.27 s (179.46 MB/s)
74 13:53:03.773177 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:53:03.773409 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:53:03.773520 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:53:03.773623 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:53:03.773764 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:53:03.773833 saving as /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/dtb/mt8192-asurada-spherion-r0.dtb
81 13:53:03.773893 total size: 47278 (0 MB)
82 13:53:03.773954 No compression specified
83 13:53:03.775079 progress 69 % (0 MB)
84 13:53:03.775354 progress 100 % (0 MB)
85 13:53:03.775508 0 MB downloaded in 0.00 s (27.96 MB/s)
86 13:53:03.775628 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:53:03.775882 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:53:03.775968 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:53:03.776049 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:53:03.776161 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:53:03.776228 saving as /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/modules/modules.tar
93 13:53:03.776286 total size: 8623988 (8 MB)
94 13:53:03.776347 Using unxz to decompress xz
95 13:53:03.780792 progress 0 % (0 MB)
96 13:53:03.802554 progress 5 % (0 MB)
97 13:53:03.826873 progress 10 % (0 MB)
98 13:53:03.851315 progress 15 % (1 MB)
99 13:53:03.875340 progress 20 % (1 MB)
100 13:53:03.899707 progress 25 % (2 MB)
101 13:53:03.926189 progress 30 % (2 MB)
102 13:53:03.953455 progress 35 % (2 MB)
103 13:53:03.977700 progress 40 % (3 MB)
104 13:53:04.005375 progress 45 % (3 MB)
105 13:53:04.032897 progress 50 % (4 MB)
106 13:53:04.058254 progress 55 % (4 MB)
107 13:53:04.084422 progress 60 % (4 MB)
108 13:53:04.113598 progress 65 % (5 MB)
109 13:53:04.140392 progress 70 % (5 MB)
110 13:53:04.165728 progress 75 % (6 MB)
111 13:53:04.194673 progress 80 % (6 MB)
112 13:53:04.222452 progress 85 % (7 MB)
113 13:53:04.249235 progress 90 % (7 MB)
114 13:53:04.283007 progress 95 % (7 MB)
115 13:53:04.313396 progress 100 % (8 MB)
116 13:53:04.318578 8 MB downloaded in 0.54 s (15.17 MB/s)
117 13:53:04.318858 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:53:04.319153 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:53:04.319244 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:53:04.319339 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:53:04.319421 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:53:04.319504 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:53:04.319731 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt
125 13:53:04.319864 makedir: /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin
126 13:53:04.319968 makedir: /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/tests
127 13:53:04.320067 makedir: /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/results
128 13:53:04.320184 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-add-keys
129 13:53:04.320331 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-add-sources
130 13:53:04.320481 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-background-process-start
131 13:53:04.320626 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-background-process-stop
132 13:53:04.320750 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-common-functions
133 13:53:04.320948 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-echo-ipv4
134 13:53:04.321073 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-install-packages
135 13:53:04.321226 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-installed-packages
136 13:53:04.321351 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-os-build
137 13:53:04.321504 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-probe-channel
138 13:53:04.321647 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-probe-ip
139 13:53:04.321771 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-target-ip
140 13:53:04.321894 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-target-mac
141 13:53:04.322016 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-target-storage
142 13:53:04.322176 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-test-case
143 13:53:04.322301 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-test-event
144 13:53:04.322425 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-test-feedback
145 13:53:04.322548 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-test-raise
146 13:53:04.322673 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-test-reference
147 13:53:04.322886 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-test-runner
148 13:53:04.323012 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-test-set
149 13:53:04.323138 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-test-shell
150 13:53:04.323266 Updating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-install-packages (oe)
151 13:53:04.323420 Updating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/bin/lava-installed-packages (oe)
152 13:53:04.323559 Creating /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/environment
153 13:53:04.323659 LAVA metadata
154 13:53:04.323747 - LAVA_JOB_ID=12682925
155 13:53:04.323810 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:53:04.323915 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:53:04.323982 skipped lava-vland-overlay
158 13:53:04.324054 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:53:04.324137 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:53:04.324198 skipped lava-multinode-overlay
161 13:53:04.324271 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:53:04.324350 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:53:04.324425 Loading test definitions
164 13:53:04.324514 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:53:04.324586 Using /lava-12682925 at stage 0
166 13:53:04.324913 uuid=12682925_1.5.2.3.1 testdef=None
167 13:53:04.325001 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:53:04.325084 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:53:04.325666 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:53:04.325887 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:53:04.326581 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:53:04.326902 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:53:04.327711 runner path: /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/0/tests/0_dmesg test_uuid 12682925_1.5.2.3.1
176 13:53:04.327885 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:53:04.328108 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 13:53:04.328178 Using /lava-12682925 at stage 1
180 13:53:04.328481 uuid=12682925_1.5.2.3.5 testdef=None
181 13:53:04.328568 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 13:53:04.328649 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 13:53:04.329165 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 13:53:04.329379 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 13:53:04.330607 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 13:53:04.330854 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 13:53:04.331552 runner path: /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/1/tests/1_bootrr test_uuid 12682925_1.5.2.3.5
190 13:53:04.331704 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 13:53:04.331907 Creating lava-test-runner.conf files
193 13:53:04.331970 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/0 for stage 0
194 13:53:04.332060 - 0_dmesg
195 13:53:04.332141 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682925/lava-overlay-teouibxt/lava-12682925/1 for stage 1
196 13:53:04.332233 - 1_bootrr
197 13:53:04.332325 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 13:53:04.332414 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 13:53:04.341062 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 13:53:04.341217 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 13:53:04.341324 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 13:53:04.341409 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 13:53:04.341533 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 13:53:04.608081 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 13:53:04.608476 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 13:53:04.608596 extracting modules file /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682925/extract-overlay-ramdisk-i2oj0bdf/ramdisk
207 13:53:04.834637 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 13:53:04.834805 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 13:53:04.834909 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682925/compress-overlay-nq5u0a1t/overlay-1.5.2.4.tar.gz to ramdisk
210 13:53:04.834979 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682925/compress-overlay-nq5u0a1t/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682925/extract-overlay-ramdisk-i2oj0bdf/ramdisk
211 13:53:04.843382 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 13:53:04.843516 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 13:53:04.843609 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 13:53:04.843701 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 13:53:04.843780 Building ramdisk /var/lib/lava/dispatcher/tmp/12682925/extract-overlay-ramdisk-i2oj0bdf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682925/extract-overlay-ramdisk-i2oj0bdf/ramdisk
216 13:53:05.250309 >> 145326 blocks
217 13:53:07.543391 rename /var/lib/lava/dispatcher/tmp/12682925/extract-overlay-ramdisk-i2oj0bdf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/ramdisk/ramdisk.cpio.gz
218 13:53:07.543949 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 13:53:07.544122 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 13:53:07.544267 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 13:53:07.544415 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/kernel/Image'
222 13:53:21.031005 Returned 0 in 13 seconds
223 13:53:21.131749 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/kernel/image.itb
224 13:53:21.558329 output: FIT description: Kernel Image image with one or more FDT blobs
225 13:53:21.558800 output: Created: Thu Feb 1 13:53:21 2024
226 13:53:21.558924 output: Image 0 (kernel-1)
227 13:53:21.559022 output: Description:
228 13:53:21.559115 output: Created: Thu Feb 1 13:53:21 2024
229 13:53:21.559215 output: Type: Kernel Image
230 13:53:21.559309 output: Compression: lzma compressed
231 13:53:21.559406 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
232 13:53:21.559502 output: Architecture: AArch64
233 13:53:21.559596 output: OS: Linux
234 13:53:21.559687 output: Load Address: 0x00000000
235 13:53:21.559779 output: Entry Point: 0x00000000
236 13:53:21.559870 output: Hash algo: crc32
237 13:53:21.559965 output: Hash value: 5aa40db2
238 13:53:21.560057 output: Image 1 (fdt-1)
239 13:53:21.560145 output: Description: mt8192-asurada-spherion-r0
240 13:53:21.560233 output: Created: Thu Feb 1 13:53:21 2024
241 13:53:21.560322 output: Type: Flat Device Tree
242 13:53:21.560410 output: Compression: uncompressed
243 13:53:21.560498 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 13:53:21.560587 output: Architecture: AArch64
245 13:53:21.560674 output: Hash algo: crc32
246 13:53:21.560763 output: Hash value: cc4352de
247 13:53:21.560852 output: Image 2 (ramdisk-1)
248 13:53:21.560942 output: Description: unavailable
249 13:53:21.561031 output: Created: Thu Feb 1 13:53:21 2024
250 13:53:21.561121 output: Type: RAMDisk Image
251 13:53:21.561209 output: Compression: Unknown Compression
252 13:53:21.561298 output: Data Size: 21399346 Bytes = 20897.80 KiB = 20.41 MiB
253 13:53:21.561387 output: Architecture: AArch64
254 13:53:21.561485 output: OS: Linux
255 13:53:21.561607 output: Load Address: unavailable
256 13:53:21.561695 output: Entry Point: unavailable
257 13:53:21.561783 output: Hash algo: crc32
258 13:53:21.561872 output: Hash value: cd2fbd82
259 13:53:21.561960 output: Default Configuration: 'conf-1'
260 13:53:21.562049 output: Configuration 0 (conf-1)
261 13:53:21.562170 output: Description: mt8192-asurada-spherion-r0
262 13:53:21.562273 output: Kernel: kernel-1
263 13:53:21.562362 output: Init Ramdisk: ramdisk-1
264 13:53:21.562451 output: FDT: fdt-1
265 13:53:21.562540 output: Loadables: kernel-1
266 13:53:21.562628 output:
267 13:53:21.562903 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 13:53:21.563047 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 13:53:21.563194 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 13:53:21.563330 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 13:53:21.563453 No LXC device requested
272 13:53:21.563573 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 13:53:21.563699 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 13:53:21.563812 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 13:53:21.563918 Checking files for TFTP limit of 4294967296 bytes.
276 13:53:21.564601 end: 1 tftp-deploy (duration 00:00:18) [common]
277 13:53:21.564734 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 13:53:21.564860 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 13:53:21.565021 substitutions:
280 13:53:21.565116 - {DTB}: 12682925/tftp-deploy-kqtpze1w/dtb/mt8192-asurada-spherion-r0.dtb
281 13:53:21.565214 - {INITRD}: 12682925/tftp-deploy-kqtpze1w/ramdisk/ramdisk.cpio.gz
282 13:53:21.565305 - {KERNEL}: 12682925/tftp-deploy-kqtpze1w/kernel/Image
283 13:53:21.565391 - {LAVA_MAC}: None
284 13:53:21.565504 - {PRESEED_CONFIG}: None
285 13:53:21.565606 - {PRESEED_LOCAL}: None
286 13:53:21.565694 - {RAMDISK}: 12682925/tftp-deploy-kqtpze1w/ramdisk/ramdisk.cpio.gz
287 13:53:21.565782 - {ROOT_PART}: None
288 13:53:21.565872 - {ROOT}: None
289 13:53:21.565960 - {SERVER_IP}: 192.168.201.1
290 13:53:21.566047 - {TEE}: None
291 13:53:21.566134 Parsed boot commands:
292 13:53:21.566219 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 13:53:21.566467 Parsed boot commands: tftpboot 192.168.201.1 12682925/tftp-deploy-kqtpze1w/kernel/image.itb 12682925/tftp-deploy-kqtpze1w/kernel/cmdline
294 13:53:21.566601 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 13:53:21.566728 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 13:53:21.566865 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 13:53:21.566990 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 13:53:21.567098 Not connected, no need to disconnect.
299 13:53:21.567213 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 13:53:21.567336 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 13:53:21.567446 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
302 13:53:21.572279 Setting prompt string to ['lava-test: # ']
303 13:53:21.572764 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 13:53:21.572953 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 13:53:21.573122 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 13:53:21.573446 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 13:53:21.573780 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
308 13:53:26.700796 >> Command sent successfully.
309 13:53:26.703317 Returned 0 in 5 seconds
310 13:53:26.803746 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 13:53:26.804089 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 13:53:26.804187 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 13:53:26.804280 Setting prompt string to 'Starting depthcharge on Spherion...'
315 13:53:26.804350 Changing prompt to 'Starting depthcharge on Spherion...'
316 13:53:26.804415 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 13:53:26.804681 [Enter `^Ec?' for help]
318 13:53:26.978381
319 13:53:26.978544
320 13:53:26.978619 F0: 102B 0000
321 13:53:26.978688
322 13:53:26.978748 F3: 1001 0000 [0200]
323 13:53:26.978806
324 13:53:26.981813 F3: 1001 0000
325 13:53:26.981899
326 13:53:26.981965 F7: 102D 0000
327 13:53:26.982026
328 13:53:26.982084 F1: 0000 0000
329 13:53:26.982142
330 13:53:26.985631 V0: 0000 0000 [0001]
331 13:53:26.985718
332 13:53:26.985784 00: 0007 8000
333 13:53:26.985850
334 13:53:26.989413 01: 0000 0000
335 13:53:26.989542
336 13:53:26.989612 BP: 0C00 0209 [0000]
337 13:53:26.989674
338 13:53:26.989732 G0: 1182 0000
339 13:53:26.993025
340 13:53:26.993136 EC: 0000 0021 [4000]
341 13:53:26.993231
342 13:53:26.996979 S7: 0000 0000 [0000]
343 13:53:26.997065
344 13:53:26.997131 CC: 0000 0000 [0001]
345 13:53:26.997192
346 13:53:27.000317 T0: 0000 0040 [010F]
347 13:53:27.000404
348 13:53:27.000475 Jump to BL
349 13:53:27.000537
350 13:53:27.025102
351 13:53:27.025262
352 13:53:27.025333
353 13:53:27.032396 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 13:53:27.036211 ARM64: Exception handlers installed.
355 13:53:27.039940 ARM64: Testing exception
356 13:53:27.043739 ARM64: Done test exception
357 13:53:27.050859 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 13:53:27.057650 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 13:53:27.067611 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 13:53:27.077430 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 13:53:27.084421 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 13:53:27.090852 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 13:53:27.101623 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 13:53:27.108185 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 13:53:27.127929 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 13:53:27.131047 WDT: Last reset was cold boot
367 13:53:27.134393 SPI1(PAD0) initialized at 2873684 Hz
368 13:53:27.137836 SPI5(PAD0) initialized at 992727 Hz
369 13:53:27.141039 VBOOT: Loading verstage.
370 13:53:27.147868 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 13:53:27.151019 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 13:53:27.154269 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 13:53:27.157722 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 13:53:27.165031 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 13:53:27.171714 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 13:53:27.182772 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 13:53:27.182865
378 13:53:27.182933
379 13:53:27.192747 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 13:53:27.196047 ARM64: Exception handlers installed.
381 13:53:27.199432 ARM64: Testing exception
382 13:53:27.199517 ARM64: Done test exception
383 13:53:27.205981 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 13:53:27.209181 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 13:53:27.223683 Probing TPM: . done!
386 13:53:27.223789 TPM ready after 0 ms
387 13:53:27.230341 Connected to device vid:did:rid of 1ae0:0028:00
388 13:53:27.237175 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 13:53:27.277222 Initialized TPM device CR50 revision 0
390 13:53:27.289293 tlcl_send_startup: Startup return code is 0
391 13:53:27.289399 TPM: setup succeeded
392 13:53:27.300720 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 13:53:27.309488 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 13:53:27.321883 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 13:53:27.330151 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 13:53:27.333279 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 13:53:27.336977 in-header: 03 07 00 00 08 00 00 00
398 13:53:27.340921 in-data: aa e4 47 04 13 02 00 00
399 13:53:27.344294 Chrome EC: UHEPI supported
400 13:53:27.350979 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 13:53:27.355041 in-header: 03 9d 00 00 08 00 00 00
402 13:53:27.358814 in-data: 10 20 20 08 00 00 00 00
403 13:53:27.358900 Phase 1
404 13:53:27.365834 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 13:53:27.369710 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 13:53:27.377122 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 13:53:27.377225 Recovery requested (1009000e)
408 13:53:27.386057 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 13:53:27.391644 tlcl_extend: response is 0
410 13:53:27.402175 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 13:53:27.405449 tlcl_extend: response is 0
412 13:53:27.412074 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 13:53:27.432657 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 13:53:27.440080 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 13:53:27.440196
416 13:53:27.440290
417 13:53:27.447650 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 13:53:27.451339 ARM64: Exception handlers installed.
419 13:53:27.455091 ARM64: Testing exception
420 13:53:27.458338 ARM64: Done test exception
421 13:53:27.477960 pmic_efuse_setting: Set efuses in 11 msecs
422 13:53:27.481791 pmwrap_interface_init: Select PMIF_VLD_RDY
423 13:53:27.488412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 13:53:27.492023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 13:53:27.495866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 13:53:27.503601 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 13:53:27.506887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 13:53:27.510707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 13:53:27.514269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 13:53:27.521027 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 13:53:27.524475 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 13:53:27.530940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 13:53:27.534237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 13:53:27.537868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 13:53:27.544362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 13:53:27.550907 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 13:53:27.554625 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 13:53:27.561031 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 13:53:27.567681 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 13:53:27.574396 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 13:53:27.578293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 13:53:27.585384 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 13:53:27.589280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 13:53:27.596590 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 13:53:27.599775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 13:53:27.606748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 13:53:27.610744 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 13:53:27.617021 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 13:53:27.623860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 13:53:27.627222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 13:53:27.630610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 13:53:27.637434 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 13:53:27.641105 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 13:53:27.648402 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 13:53:27.652130 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 13:53:27.655919 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 13:53:27.663566 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 13:53:27.667197 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 13:53:27.670911 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 13:53:27.677512 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 13:53:27.681062 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 13:53:27.684346 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 13:53:27.690820 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 13:53:27.694334 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 13:53:27.697640 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 13:53:27.704440 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 13:53:27.707674 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 13:53:27.710976 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 13:53:27.714203 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 13:53:27.720691 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 13:53:27.724204 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 13:53:27.727720 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 13:53:27.731015 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 13:53:27.740921 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 13:53:27.747743 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 13:53:27.754166 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 13:53:27.760590 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 13:53:27.770841 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 13:53:27.774046 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 13:53:27.780873 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 13:53:27.783981 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 13:53:27.790590 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xf
483 13:53:27.797280 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 13:53:27.800816 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
485 13:53:27.803975 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 13:53:27.815013 [RTC]rtc_get_frequency_meter,154: input=15, output=795
487 13:53:27.818301 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
488 13:53:27.824791 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
489 13:53:27.828024 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
490 13:53:27.831516 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
491 13:53:27.834964 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
492 13:53:27.838542 ADC[4]: Raw value=897780 ID=7
493 13:53:27.841647 ADC[3]: Raw value=212700 ID=1
494 13:53:27.844939 RAM Code: 0x71
495 13:53:27.848351 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
496 13:53:27.851768 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
497 13:53:27.862194 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
498 13:53:27.868973 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
499 13:53:27.872451 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
500 13:53:27.875766 in-header: 03 07 00 00 08 00 00 00
501 13:53:27.879029 in-data: aa e4 47 04 13 02 00 00
502 13:53:27.879113 Chrome EC: UHEPI supported
503 13:53:27.886944 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
504 13:53:27.890183 in-header: 03 d5 00 00 08 00 00 00
505 13:53:27.893751 in-data: 98 20 60 08 00 00 00 00
506 13:53:27.897520 MRC: failed to locate region type 0.
507 13:53:27.904821 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
508 13:53:27.907989 DRAM-K: Running full calibration
509 13:53:27.915088 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
510 13:53:27.915173 header.status = 0x0
511 13:53:27.919083 header.version = 0x6 (expected: 0x6)
512 13:53:27.922504 header.size = 0xd00 (expected: 0xd00)
513 13:53:27.922589 header.flags = 0x0
514 13:53:27.929122 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
515 13:53:27.947003 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
516 13:53:27.953763 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
517 13:53:27.956991 dram_init: ddr_geometry: 2
518 13:53:27.960347 [EMI] MDL number = 2
519 13:53:27.960442 [EMI] Get MDL freq = 0
520 13:53:27.963758 dram_init: ddr_type: 0
521 13:53:27.963848 is_discrete_lpddr4: 1
522 13:53:27.966877 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
523 13:53:27.966965
524 13:53:27.967053
525 13:53:27.970556 [Bian_co] ETT version 0.0.0.1
526 13:53:27.977415 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
527 13:53:27.977627
528 13:53:27.980843 dramc_set_vcore_voltage set vcore to 650000
529 13:53:27.981005 Read voltage for 800, 4
530 13:53:27.984154 Vio18 = 0
531 13:53:27.984322 Vcore = 650000
532 13:53:27.984400 Vdram = 0
533 13:53:27.987340 Vddq = 0
534 13:53:27.987512 Vmddr = 0
535 13:53:27.990817 dram_init: config_dvfs: 1
536 13:53:27.994046 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
537 13:53:28.000586 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
538 13:53:28.003877 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
539 13:53:28.007580 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
540 13:53:28.010924 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
541 13:53:28.013916 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
542 13:53:28.017632 MEM_TYPE=3, freq_sel=18
543 13:53:28.020642 sv_algorithm_assistance_LP4_1600
544 13:53:28.024326 ============ PULL DRAM RESETB DOWN ============
545 13:53:28.027405 ========== PULL DRAM RESETB DOWN end =========
546 13:53:28.033668 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
547 13:53:28.037263 ===================================
548 13:53:28.040767 LPDDR4 DRAM CONFIGURATION
549 13:53:28.044333 ===================================
550 13:53:28.044748 EX_ROW_EN[0] = 0x0
551 13:53:28.047599 EX_ROW_EN[1] = 0x0
552 13:53:28.048109 LP4Y_EN = 0x0
553 13:53:28.050752 WORK_FSP = 0x0
554 13:53:28.051146 WL = 0x2
555 13:53:28.054158 RL = 0x2
556 13:53:28.054556 BL = 0x2
557 13:53:28.057420 RPST = 0x0
558 13:53:28.057864 RD_PRE = 0x0
559 13:53:28.061269 WR_PRE = 0x1
560 13:53:28.061880 WR_PST = 0x0
561 13:53:28.064503 DBI_WR = 0x0
562 13:53:28.065009 DBI_RD = 0x0
563 13:53:28.067277 OTF = 0x1
564 13:53:28.070592 ===================================
565 13:53:28.074050 ===================================
566 13:53:28.074462 ANA top config
567 13:53:28.077742 ===================================
568 13:53:28.081014 DLL_ASYNC_EN = 0
569 13:53:28.084521 ALL_SLAVE_EN = 1
570 13:53:28.092053 NEW_RANK_MODE = 1
571 13:53:28.092482 DLL_IDLE_MODE = 1
572 13:53:28.092899 LP45_APHY_COMB_EN = 1
573 13:53:28.094090 TX_ODT_DIS = 1
574 13:53:28.097349 NEW_8X_MODE = 1
575 13:53:28.100762 ===================================
576 13:53:28.103780 ===================================
577 13:53:28.107177 data_rate = 1600
578 13:53:28.107593 CKR = 1
579 13:53:28.110760 DQ_P2S_RATIO = 8
580 13:53:28.113971 ===================================
581 13:53:28.117122 CA_P2S_RATIO = 8
582 13:53:28.120772 DQ_CA_OPEN = 0
583 13:53:28.123764 DQ_SEMI_OPEN = 0
584 13:53:28.127312 CA_SEMI_OPEN = 0
585 13:53:28.127707 CA_FULL_RATE = 0
586 13:53:28.130883 DQ_CKDIV4_EN = 1
587 13:53:28.133965 CA_CKDIV4_EN = 1
588 13:53:28.137628 CA_PREDIV_EN = 0
589 13:53:28.141325 PH8_DLY = 0
590 13:53:28.141917 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
591 13:53:28.145455 DQ_AAMCK_DIV = 4
592 13:53:28.149074 CA_AAMCK_DIV = 4
593 13:53:28.149529 CA_ADMCK_DIV = 4
594 13:53:28.152737 DQ_TRACK_CA_EN = 0
595 13:53:28.156907 CA_PICK = 800
596 13:53:28.160481 CA_MCKIO = 800
597 13:53:28.164391 MCKIO_SEMI = 0
598 13:53:28.164896 PLL_FREQ = 3068
599 13:53:28.167752 DQ_UI_PI_RATIO = 32
600 13:53:28.171793 CA_UI_PI_RATIO = 0
601 13:53:28.175527 ===================================
602 13:53:28.176062 ===================================
603 13:53:28.179001 memory_type:LPDDR4
604 13:53:28.182831 GP_NUM : 10
605 13:53:28.183229 SRAM_EN : 1
606 13:53:28.186328 MD32_EN : 0
607 13:53:28.190084 ===================================
608 13:53:28.190474 [ANA_INIT] >>>>>>>>>>>>>>
609 13:53:28.193854 <<<<<< [CONFIGURE PHASE]: ANA_TX
610 13:53:28.197640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
611 13:53:28.201011 ===================================
612 13:53:28.204555 data_rate = 1600,PCW = 0X7600
613 13:53:28.208091 ===================================
614 13:53:28.212102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
615 13:53:28.215511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
616 13:53:28.222845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
617 13:53:28.226587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
618 13:53:28.229621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
619 13:53:28.234028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
620 13:53:28.234569 [ANA_INIT] flow start
621 13:53:28.237432 [ANA_INIT] PLL >>>>>>>>
622 13:53:28.241254 [ANA_INIT] PLL <<<<<<<<
623 13:53:28.241840 [ANA_INIT] MIDPI >>>>>>>>
624 13:53:28.244409 [ANA_INIT] MIDPI <<<<<<<<
625 13:53:28.248287 [ANA_INIT] DLL >>>>>>>>
626 13:53:28.248769 [ANA_INIT] flow end
627 13:53:28.252190 ============ LP4 DIFF to SE enter ============
628 13:53:28.255884 ============ LP4 DIFF to SE exit ============
629 13:53:28.259705 [ANA_INIT] <<<<<<<<<<<<<
630 13:53:28.263829 [Flow] Enable top DCM control >>>>>
631 13:53:28.267021 [Flow] Enable top DCM control <<<<<
632 13:53:28.267548 Enable DLL master slave shuffle
633 13:53:28.274318 ==============================================================
634 13:53:28.274890 Gating Mode config
635 13:53:28.281464 ==============================================================
636 13:53:28.284382 Config description:
637 13:53:28.294746 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
638 13:53:28.297958 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
639 13:53:28.304749 SELPH_MODE 0: By rank 1: By Phase
640 13:53:28.311631 ==============================================================
641 13:53:28.314645 GAT_TRACK_EN = 1
642 13:53:28.315226 RX_GATING_MODE = 2
643 13:53:28.318291 RX_GATING_TRACK_MODE = 2
644 13:53:28.321219 SELPH_MODE = 1
645 13:53:28.324463 PICG_EARLY_EN = 1
646 13:53:28.327478 VALID_LAT_VALUE = 1
647 13:53:28.334636 ==============================================================
648 13:53:28.338018 Enter into Gating configuration >>>>
649 13:53:28.341355 Exit from Gating configuration <<<<
650 13:53:28.344575 Enter into DVFS_PRE_config >>>>>
651 13:53:28.354253 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
652 13:53:28.357866 Exit from DVFS_PRE_config <<<<<
653 13:53:28.360947 Enter into PICG configuration >>>>
654 13:53:28.364532 Exit from PICG configuration <<<<
655 13:53:28.367794 [RX_INPUT] configuration >>>>>
656 13:53:28.368192 [RX_INPUT] configuration <<<<<
657 13:53:28.374371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
658 13:53:28.381680 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
659 13:53:28.384549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
660 13:53:28.391669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
661 13:53:28.398214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
662 13:53:28.404761 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
663 13:53:28.408064 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
664 13:53:28.411589 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
665 13:53:28.418005 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
666 13:53:28.421437 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
667 13:53:28.424405 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
668 13:53:28.428344 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
669 13:53:28.431180 ===================================
670 13:53:28.434360 LPDDR4 DRAM CONFIGURATION
671 13:53:28.438300 ===================================
672 13:53:28.441262 EX_ROW_EN[0] = 0x0
673 13:53:28.441800 EX_ROW_EN[1] = 0x0
674 13:53:28.444688 LP4Y_EN = 0x0
675 13:53:28.445191 WORK_FSP = 0x0
676 13:53:28.448003 WL = 0x2
677 13:53:28.448511 RL = 0x2
678 13:53:28.451452 BL = 0x2
679 13:53:28.451964 RPST = 0x0
680 13:53:28.454540 RD_PRE = 0x0
681 13:53:28.454950 WR_PRE = 0x1
682 13:53:28.457979 WR_PST = 0x0
683 13:53:28.458373 DBI_WR = 0x0
684 13:53:28.461071 DBI_RD = 0x0
685 13:53:28.464905 OTF = 0x1
686 13:53:28.468131 ===================================
687 13:53:28.471017 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
688 13:53:28.474907 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
689 13:53:28.477690 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 13:53:28.481111 ===================================
691 13:53:28.484738 LPDDR4 DRAM CONFIGURATION
692 13:53:28.488316 ===================================
693 13:53:28.491469 EX_ROW_EN[0] = 0x10
694 13:53:28.491980 EX_ROW_EN[1] = 0x0
695 13:53:28.494576 LP4Y_EN = 0x0
696 13:53:28.495067 WORK_FSP = 0x0
697 13:53:28.498309 WL = 0x2
698 13:53:28.498829 RL = 0x2
699 13:53:28.501365 BL = 0x2
700 13:53:28.501931 RPST = 0x0
701 13:53:28.505091 RD_PRE = 0x0
702 13:53:28.505672 WR_PRE = 0x1
703 13:53:28.508364 WR_PST = 0x0
704 13:53:28.508898 DBI_WR = 0x0
705 13:53:28.511420 DBI_RD = 0x0
706 13:53:28.511955 OTF = 0x1
707 13:53:28.514958 ===================================
708 13:53:28.521432 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
709 13:53:28.525661 nWR fixed to 40
710 13:53:28.529366 [ModeRegInit_LP4] CH0 RK0
711 13:53:28.529944 [ModeRegInit_LP4] CH0 RK1
712 13:53:28.532717 [ModeRegInit_LP4] CH1 RK0
713 13:53:28.536137 [ModeRegInit_LP4] CH1 RK1
714 13:53:28.536870 match AC timing 13
715 13:53:28.542909 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
716 13:53:28.546616 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
717 13:53:28.550151 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
718 13:53:28.553604 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
719 13:53:28.557386 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
720 13:53:28.560811 [EMI DOE] emi_dcm 0
721 13:53:28.564487 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
722 13:53:28.565025 ==
723 13:53:28.568138 Dram Type= 6, Freq= 0, CH_0, rank 0
724 13:53:28.572128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
725 13:53:28.572558 ==
726 13:53:28.579051 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
727 13:53:28.582713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
728 13:53:28.593548 [CA 0] Center 38 (7~69) winsize 63
729 13:53:28.597182 [CA 1] Center 37 (7~68) winsize 62
730 13:53:28.600363 [CA 2] Center 36 (6~66) winsize 61
731 13:53:28.604092 [CA 3] Center 35 (4~66) winsize 63
732 13:53:28.608035 [CA 4] Center 34 (4~65) winsize 62
733 13:53:28.611417 [CA 5] Center 34 (4~65) winsize 62
734 13:53:28.611849
735 13:53:28.615377 [CmdBusTrainingLP45] Vref(ca) range 1: 32
736 13:53:28.615916
737 13:53:28.618958 [CATrainingPosCal] consider 1 rank data
738 13:53:28.622638 u2DelayCellTimex100 = 270/100 ps
739 13:53:28.626507 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
740 13:53:28.629923 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
741 13:53:28.633698 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
742 13:53:28.637064 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
743 13:53:28.640839 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
744 13:53:28.644642 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
745 13:53:28.645203
746 13:53:28.648496 CA PerBit enable=1, Macro0, CA PI delay=34
747 13:53:28.649027
748 13:53:28.649468 [CBTSetCACLKResult] CA Dly = 34
749 13:53:28.651957 CS Dly: 6 (0~37)
750 13:53:28.652394 ==
751 13:53:28.656009 Dram Type= 6, Freq= 0, CH_0, rank 1
752 13:53:28.659267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 13:53:28.659717 ==
754 13:53:28.663129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 13:53:28.670402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 13:53:28.680467 [CA 0] Center 38 (7~69) winsize 63
757 13:53:28.683997 [CA 1] Center 37 (7~68) winsize 62
758 13:53:28.687723 [CA 2] Center 35 (5~66) winsize 62
759 13:53:28.691547 [CA 3] Center 35 (5~66) winsize 62
760 13:53:28.694984 [CA 4] Center 34 (4~65) winsize 62
761 13:53:28.695414 [CA 5] Center 34 (4~65) winsize 62
762 13:53:28.695756
763 13:53:28.698894 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 13:53:28.702432
765 13:53:28.706023 [CATrainingPosCal] consider 2 rank data
766 13:53:28.706458 u2DelayCellTimex100 = 270/100 ps
767 13:53:28.709992 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
768 13:53:28.713637 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
769 13:53:28.717112 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
770 13:53:28.720956 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
771 13:53:28.724462 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
772 13:53:28.728809 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
773 13:53:28.729240
774 13:53:28.732427 CA PerBit enable=1, Macro0, CA PI delay=34
775 13:53:28.732861
776 13:53:28.735765 [CBTSetCACLKResult] CA Dly = 34
777 13:53:28.739767 CS Dly: 6 (0~37)
778 13:53:28.740303
779 13:53:28.740643 ----->DramcWriteLeveling(PI) begin...
780 13:53:28.743602 ==
781 13:53:28.744132 Dram Type= 6, Freq= 0, CH_0, rank 0
782 13:53:28.747551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 13:53:28.751028 ==
784 13:53:28.751563 Write leveling (Byte 0): 32 => 32
785 13:53:28.754722 Write leveling (Byte 1): 30 => 30
786 13:53:28.758527 DramcWriteLeveling(PI) end<-----
787 13:53:28.758957
788 13:53:28.759291 ==
789 13:53:28.762049 Dram Type= 6, Freq= 0, CH_0, rank 0
790 13:53:28.765831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
791 13:53:28.766375 ==
792 13:53:28.769249 [Gating] SW mode calibration
793 13:53:28.776943 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
794 13:53:28.780087 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
795 13:53:28.787974 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
796 13:53:28.791468 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
797 13:53:28.794804 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
798 13:53:28.798791 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 13:53:28.802450 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:53:28.809559 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:53:28.813040 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:53:28.816662 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:53:28.820235 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:53:28.823894 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:53:28.831550 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:53:28.835301 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:53:28.839015 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:53:28.842528 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:53:28.846496 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:53:28.849996 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:53:28.857773 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:53:28.861548 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
813 13:53:28.865015 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
814 13:53:28.868331 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
815 13:53:28.874857 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:53:28.878284 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:53:28.881405 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:53:28.888471 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 13:53:28.892046 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:53:28.894961 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 13:53:28.898127 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:53:28.905078 0 9 12 | B1->B0 | 2424 3232 | 1 0 | (0 0) (0 0)
823 13:53:28.908543 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 13:53:28.911810 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 13:53:28.918505 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 13:53:28.921584 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
827 13:53:28.924717 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 13:53:28.931746 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
829 13:53:28.935250 0 10 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
830 13:53:28.938473 0 10 12 | B1->B0 | 2b2b 2424 | 0 0 | (1 1) (0 0)
831 13:53:28.945187 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 13:53:28.948612 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 13:53:28.951636 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 13:53:28.958467 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 13:53:28.961964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 13:53:28.965364 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 13:53:28.971737 0 11 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
838 13:53:28.974749 0 11 12 | B1->B0 | 3333 4444 | 0 0 | (0 0) (0 0)
839 13:53:28.978152 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 13:53:28.985140 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 13:53:28.988205 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 13:53:28.991633 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
843 13:53:28.994877 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 13:53:29.001691 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 13:53:29.005119 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 13:53:29.008539 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
847 13:53:29.015195 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:53:29.018382 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:53:29.021893 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:53:29.028405 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:53:29.031851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:53:29.034778 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 13:53:29.041630 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 13:53:29.045379 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 13:53:29.048747 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 13:53:29.055321 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 13:53:29.058232 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 13:53:29.061858 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 13:53:29.068383 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 13:53:29.071933 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 13:53:29.075050 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
862 13:53:29.081862 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
863 13:53:29.082433 Total UI for P1: 0, mck2ui 16
864 13:53:29.085219 best dqsien dly found for B0: ( 0, 14, 8)
865 13:53:29.091942 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 13:53:29.095492 Total UI for P1: 0, mck2ui 16
867 13:53:29.098725 best dqsien dly found for B1: ( 0, 14, 12)
868 13:53:29.101708 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
869 13:53:29.105518 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
870 13:53:29.106063
871 13:53:29.108221 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
872 13:53:29.111909 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
873 13:53:29.115093 [Gating] SW calibration Done
874 13:53:29.115633 ==
875 13:53:29.118414 Dram Type= 6, Freq= 0, CH_0, rank 0
876 13:53:29.121834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
877 13:53:29.122373 ==
878 13:53:29.125245 RX Vref Scan: 0
879 13:53:29.125727
880 13:53:29.126175 RX Vref 0 -> 0, step: 1
881 13:53:29.126592
882 13:53:29.128328 RX Delay -130 -> 252, step: 16
883 13:53:29.135006 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
884 13:53:29.138538 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
885 13:53:29.141588 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
886 13:53:29.145399 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
887 13:53:29.148923 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
888 13:53:29.152364 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
889 13:53:29.158890 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
890 13:53:29.161879 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
891 13:53:29.165253 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
892 13:53:29.168664 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
893 13:53:29.171942 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
894 13:53:29.178479 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
895 13:53:29.182448 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
896 13:53:29.185564 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
897 13:53:29.188844 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
898 13:53:29.191848 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
899 13:53:29.195390 ==
900 13:53:29.198656 Dram Type= 6, Freq= 0, CH_0, rank 0
901 13:53:29.201895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
902 13:53:29.202432 ==
903 13:53:29.202776 DQS Delay:
904 13:53:29.205337 DQS0 = 0, DQS1 = 0
905 13:53:29.205979 DQM Delay:
906 13:53:29.208961 DQM0 = 81, DQM1 = 69
907 13:53:29.209537 DQ Delay:
908 13:53:29.212077 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
909 13:53:29.215616 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
910 13:53:29.218538 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
911 13:53:29.222043 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
912 13:53:29.222585
913 13:53:29.222928
914 13:53:29.223243 ==
915 13:53:29.225632 Dram Type= 6, Freq= 0, CH_0, rank 0
916 13:53:29.229899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 13:53:29.230439 ==
918 13:53:29.230786
919 13:53:29.231105
920 13:53:29.232355 TX Vref Scan disable
921 13:53:29.232833 == TX Byte 0 ==
922 13:53:29.239377 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
923 13:53:29.242866 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
924 13:53:29.243403 == TX Byte 1 ==
925 13:53:29.249378 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
926 13:53:29.252841 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
927 13:53:29.253365 ==
928 13:53:29.256351 Dram Type= 6, Freq= 0, CH_0, rank 0
929 13:53:29.259069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 13:53:29.259676 ==
931 13:53:29.273458 TX Vref=22, minBit 12, minWin=26, winSum=437
932 13:53:29.277028 TX Vref=24, minBit 11, minWin=26, winSum=437
933 13:53:29.279770 TX Vref=26, minBit 8, minWin=27, winSum=443
934 13:53:29.283376 TX Vref=28, minBit 11, minWin=27, winSum=443
935 13:53:29.286931 TX Vref=30, minBit 9, minWin=27, winSum=442
936 13:53:29.293354 TX Vref=32, minBit 12, minWin=26, winSum=440
937 13:53:29.296532 [TxChooseVref] Worse bit 8, Min win 27, Win sum 443, Final Vref 26
938 13:53:29.296965
939 13:53:29.299703 Final TX Range 1 Vref 26
940 13:53:29.300137
941 13:53:29.300474 ==
942 13:53:29.303511 Dram Type= 6, Freq= 0, CH_0, rank 0
943 13:53:29.306892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 13:53:29.309781 ==
945 13:53:29.310215
946 13:53:29.310553
947 13:53:29.310869 TX Vref Scan disable
948 13:53:29.313577 == TX Byte 0 ==
949 13:53:29.317125 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
950 13:53:29.323570 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
951 13:53:29.324107 == TX Byte 1 ==
952 13:53:29.326861 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
953 13:53:29.330470 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
954 13:53:29.333656
955 13:53:29.334197 [DATLAT]
956 13:53:29.334541 Freq=800, CH0 RK0
957 13:53:29.334858
958 13:53:29.336635 DATLAT Default: 0xa
959 13:53:29.337064 0, 0xFFFF, sum = 0
960 13:53:29.340429 1, 0xFFFF, sum = 0
961 13:53:29.341000 2, 0xFFFF, sum = 0
962 13:53:29.343621 3, 0xFFFF, sum = 0
963 13:53:29.344163 4, 0xFFFF, sum = 0
964 13:53:29.346907 5, 0xFFFF, sum = 0
965 13:53:29.350149 6, 0xFFFF, sum = 0
966 13:53:29.350694 7, 0xFFFF, sum = 0
967 13:53:29.353576 8, 0xFFFF, sum = 0
968 13:53:29.354115 9, 0x0, sum = 1
969 13:53:29.354461 10, 0x0, sum = 2
970 13:53:29.356698 11, 0x0, sum = 3
971 13:53:29.357135 12, 0x0, sum = 4
972 13:53:29.360068 best_step = 10
973 13:53:29.360532
974 13:53:29.360870 ==
975 13:53:29.363615 Dram Type= 6, Freq= 0, CH_0, rank 0
976 13:53:29.366656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
977 13:53:29.367093 ==
978 13:53:29.369945 RX Vref Scan: 1
979 13:53:29.370392
980 13:53:29.370767 Set Vref Range= 32 -> 127
981 13:53:29.371086
982 13:53:29.373132 RX Vref 32 -> 127, step: 1
983 13:53:29.373590
984 13:53:29.376842 RX Delay -111 -> 252, step: 8
985 13:53:29.377270
986 13:53:29.380160 Set Vref, RX VrefLevel [Byte0]: 32
987 13:53:29.383599 [Byte1]: 32
988 13:53:29.384131
989 13:53:29.386580 Set Vref, RX VrefLevel [Byte0]: 33
990 13:53:29.390052 [Byte1]: 33
991 13:53:29.393946
992 13:53:29.394372 Set Vref, RX VrefLevel [Byte0]: 34
993 13:53:29.397042 [Byte1]: 34
994 13:53:29.401651
995 13:53:29.402172 Set Vref, RX VrefLevel [Byte0]: 35
996 13:53:29.404950 [Byte1]: 35
997 13:53:29.409281
998 13:53:29.409851 Set Vref, RX VrefLevel [Byte0]: 36
999 13:53:29.412831 [Byte1]: 36
1000 13:53:29.417040
1001 13:53:29.417595 Set Vref, RX VrefLevel [Byte0]: 37
1002 13:53:29.420311 [Byte1]: 37
1003 13:53:29.424571
1004 13:53:29.425132 Set Vref, RX VrefLevel [Byte0]: 38
1005 13:53:29.428190 [Byte1]: 38
1006 13:53:29.432334
1007 13:53:29.432856 Set Vref, RX VrefLevel [Byte0]: 39
1008 13:53:29.435827 [Byte1]: 39
1009 13:53:29.440180
1010 13:53:29.440715 Set Vref, RX VrefLevel [Byte0]: 40
1011 13:53:29.443444 [Byte1]: 40
1012 13:53:29.447602
1013 13:53:29.448126 Set Vref, RX VrefLevel [Byte0]: 41
1014 13:53:29.450866 [Byte1]: 41
1015 13:53:29.455106
1016 13:53:29.455624 Set Vref, RX VrefLevel [Byte0]: 42
1017 13:53:29.458552 [Byte1]: 42
1018 13:53:29.462594
1019 13:53:29.463024 Set Vref, RX VrefLevel [Byte0]: 43
1020 13:53:29.466051 [Byte1]: 43
1021 13:53:29.470057
1022 13:53:29.470483 Set Vref, RX VrefLevel [Byte0]: 44
1023 13:53:29.473749 [Byte1]: 44
1024 13:53:29.478126
1025 13:53:29.478573 Set Vref, RX VrefLevel [Byte0]: 45
1026 13:53:29.481465 [Byte1]: 45
1027 13:53:29.485790
1028 13:53:29.486396 Set Vref, RX VrefLevel [Byte0]: 46
1029 13:53:29.488913 [Byte1]: 46
1030 13:53:29.493204
1031 13:53:29.493716 Set Vref, RX VrefLevel [Byte0]: 47
1032 13:53:29.496555 [Byte1]: 47
1033 13:53:29.500949
1034 13:53:29.501371 Set Vref, RX VrefLevel [Byte0]: 48
1035 13:53:29.504252 [Byte1]: 48
1036 13:53:29.508743
1037 13:53:29.509165 Set Vref, RX VrefLevel [Byte0]: 49
1038 13:53:29.512324 [Byte1]: 49
1039 13:53:29.516620
1040 13:53:29.517143 Set Vref, RX VrefLevel [Byte0]: 50
1041 13:53:29.520064 [Byte1]: 50
1042 13:53:29.523775
1043 13:53:29.524217 Set Vref, RX VrefLevel [Byte0]: 51
1044 13:53:29.527285 [Byte1]: 51
1045 13:53:29.531895
1046 13:53:29.532426 Set Vref, RX VrefLevel [Byte0]: 52
1047 13:53:29.535038 [Byte1]: 52
1048 13:53:29.539306
1049 13:53:29.539723 Set Vref, RX VrefLevel [Byte0]: 53
1050 13:53:29.542530 [Byte1]: 53
1051 13:53:29.547165
1052 13:53:29.547692 Set Vref, RX VrefLevel [Byte0]: 54
1053 13:53:29.549960 [Byte1]: 54
1054 13:53:29.554490
1055 13:53:29.555012 Set Vref, RX VrefLevel [Byte0]: 55
1056 13:53:29.557734 [Byte1]: 55
1057 13:53:29.562082
1058 13:53:29.562552 Set Vref, RX VrefLevel [Byte0]: 56
1059 13:53:29.565240 [Byte1]: 56
1060 13:53:29.570182
1061 13:53:29.570707 Set Vref, RX VrefLevel [Byte0]: 57
1062 13:53:29.573034 [Byte1]: 57
1063 13:53:29.577431
1064 13:53:29.577909 Set Vref, RX VrefLevel [Byte0]: 58
1065 13:53:29.580534 [Byte1]: 58
1066 13:53:29.585118
1067 13:53:29.585575 Set Vref, RX VrefLevel [Byte0]: 59
1068 13:53:29.588111 [Byte1]: 59
1069 13:53:29.592978
1070 13:53:29.593401 Set Vref, RX VrefLevel [Byte0]: 60
1071 13:53:29.595733 [Byte1]: 60
1072 13:53:29.600153
1073 13:53:29.600626 Set Vref, RX VrefLevel [Byte0]: 61
1074 13:53:29.603721 [Byte1]: 61
1075 13:53:29.607705
1076 13:53:29.608122 Set Vref, RX VrefLevel [Byte0]: 62
1077 13:53:29.611149 [Byte1]: 62
1078 13:53:29.615699
1079 13:53:29.616242 Set Vref, RX VrefLevel [Byte0]: 63
1080 13:53:29.618870 [Byte1]: 63
1081 13:53:29.623002
1082 13:53:29.623390 Set Vref, RX VrefLevel [Byte0]: 64
1083 13:53:29.626461 [Byte1]: 64
1084 13:53:29.631195
1085 13:53:29.631686 Set Vref, RX VrefLevel [Byte0]: 65
1086 13:53:29.634039 [Byte1]: 65
1087 13:53:29.638575
1088 13:53:29.639095 Set Vref, RX VrefLevel [Byte0]: 66
1089 13:53:29.642111 [Byte1]: 66
1090 13:53:29.646475
1091 13:53:29.646996 Set Vref, RX VrefLevel [Byte0]: 67
1092 13:53:29.649599 [Byte1]: 67
1093 13:53:29.653929
1094 13:53:29.654450 Set Vref, RX VrefLevel [Byte0]: 68
1095 13:53:29.657578 [Byte1]: 68
1096 13:53:29.661680
1097 13:53:29.662362 Set Vref, RX VrefLevel [Byte0]: 69
1098 13:53:29.665102 [Byte1]: 69
1099 13:53:29.669318
1100 13:53:29.669924 Set Vref, RX VrefLevel [Byte0]: 70
1101 13:53:29.672262 [Byte1]: 70
1102 13:53:29.677294
1103 13:53:29.677852 Set Vref, RX VrefLevel [Byte0]: 71
1104 13:53:29.680255 [Byte1]: 71
1105 13:53:29.684736
1106 13:53:29.685286 Set Vref, RX VrefLevel [Byte0]: 72
1107 13:53:29.688116 [Byte1]: 72
1108 13:53:29.692363
1109 13:53:29.692993 Set Vref, RX VrefLevel [Byte0]: 73
1110 13:53:29.695270 [Byte1]: 73
1111 13:53:29.699845
1112 13:53:29.700279 Set Vref, RX VrefLevel [Byte0]: 74
1113 13:53:29.703354 [Byte1]: 74
1114 13:53:29.707659
1115 13:53:29.708183 Set Vref, RX VrefLevel [Byte0]: 75
1116 13:53:29.710938 [Byte1]: 75
1117 13:53:29.715199
1118 13:53:29.715724 Set Vref, RX VrefLevel [Byte0]: 76
1119 13:53:29.718546 [Byte1]: 76
1120 13:53:29.722670
1121 13:53:29.723198 Set Vref, RX VrefLevel [Byte0]: 77
1122 13:53:29.725949 [Byte1]: 77
1123 13:53:29.730214
1124 13:53:29.730650 Set Vref, RX VrefLevel [Byte0]: 78
1125 13:53:29.733710 [Byte1]: 78
1126 13:53:29.738017
1127 13:53:29.738542 Set Vref, RX VrefLevel [Byte0]: 79
1128 13:53:29.741069 [Byte1]: 79
1129 13:53:29.745577
1130 13:53:29.746095 Final RX Vref Byte 0 = 58 to rank0
1131 13:53:29.748811 Final RX Vref Byte 1 = 63 to rank0
1132 13:53:29.752071 Final RX Vref Byte 0 = 58 to rank1
1133 13:53:29.755461 Final RX Vref Byte 1 = 63 to rank1==
1134 13:53:29.759018 Dram Type= 6, Freq= 0, CH_0, rank 0
1135 13:53:29.765763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 13:53:29.766292 ==
1137 13:53:29.766759 DQS Delay:
1138 13:53:29.767179 DQS0 = 0, DQS1 = 0
1139 13:53:29.768887 DQM Delay:
1140 13:53:29.769324 DQM0 = 82, DQM1 = 68
1141 13:53:29.772047 DQ Delay:
1142 13:53:29.775474 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1143 13:53:29.775915 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1144 13:53:29.778531 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1145 13:53:29.786011 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1146 13:53:29.786541
1147 13:53:29.786995
1148 13:53:29.792480 [DQSOSCAuto] RK0, (LSB)MR18= 0x2423, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1149 13:53:29.795990 CH0 RK0: MR19=606, MR18=2423
1150 13:53:29.802204 CH0_RK0: MR19=0x606, MR18=0x2423, DQSOSC=400, MR23=63, INC=92, DEC=61
1151 13:53:29.802746
1152 13:53:29.805671 ----->DramcWriteLeveling(PI) begin...
1153 13:53:29.806195 ==
1154 13:53:29.809160 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 13:53:29.812691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 13:53:29.813261 ==
1157 13:53:29.815847 Write leveling (Byte 0): 30 => 30
1158 13:53:29.819214 Write leveling (Byte 1): 29 => 29
1159 13:53:29.822580 DramcWriteLeveling(PI) end<-----
1160 13:53:29.823098
1161 13:53:29.823424 ==
1162 13:53:29.825606 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 13:53:29.829538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 13:53:29.830052 ==
1165 13:53:29.832589 [Gating] SW mode calibration
1166 13:53:29.839201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1167 13:53:29.845690 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1168 13:53:29.849328 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1169 13:53:29.852650 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1170 13:53:29.859022 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1171 13:53:29.862074 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:53:29.865814 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:53:29.872219 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:53:29.875562 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:53:29.878740 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:53:29.885633 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:53:29.889075 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:53:29.892117 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:53:29.895720 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:53:29.943150 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:53:29.943823 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:53:29.944170 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:53:29.944484 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:53:29.945124 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:53:29.945452 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1186 13:53:29.945802 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1187 13:53:29.946090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1188 13:53:29.946351 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:53:29.946607 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:53:29.955438 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:53:29.955975 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:53:29.956539 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:53:29.958530 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:53:29.961913 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1195 13:53:29.969019 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1196 13:53:29.972046 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 13:53:29.975439 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 13:53:29.982408 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 13:53:29.985584 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 13:53:29.988734 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 13:53:29.995726 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1202 13:53:29.998917 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (1 1)
1203 13:53:30.002316 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:53:30.005986 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:53:30.012259 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:53:30.015844 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 13:53:30.019225 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:53:30.025640 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:53:30.029090 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:53:30.032784 0 11 8 | B1->B0 | 2828 3e3e | 1 0 | (0 0) (0 0)
1211 13:53:30.039352 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1212 13:53:30.042434 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 13:53:30.045641 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 13:53:30.052354 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 13:53:30.056093 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 13:53:30.059167 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 13:53:30.063048 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 13:53:30.070517 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1219 13:53:30.074561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1220 13:53:30.077656 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 13:53:30.081070 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 13:53:30.084987 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 13:53:30.092018 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 13:53:30.095801 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 13:53:30.098987 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 13:53:30.102337 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 13:53:30.108945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 13:53:30.112629 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 13:53:30.115810 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 13:53:30.122376 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 13:53:30.125733 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 13:53:30.128983 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 13:53:30.135786 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 13:53:30.139171 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1235 13:53:30.142390 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1236 13:53:30.146075 Total UI for P1: 0, mck2ui 16
1237 13:53:30.149159 best dqsien dly found for B0: ( 0, 14, 8)
1238 13:53:30.155892 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 13:53:30.156411 Total UI for P1: 0, mck2ui 16
1240 13:53:30.162304 best dqsien dly found for B1: ( 0, 14, 12)
1241 13:53:30.165340 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1242 13:53:30.169154 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1243 13:53:30.169613
1244 13:53:30.172341 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1245 13:53:30.175642 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1246 13:53:30.179396 [Gating] SW calibration Done
1247 13:53:30.179914 ==
1248 13:53:30.182243 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 13:53:30.185946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 13:53:30.186459 ==
1251 13:53:30.189094 RX Vref Scan: 0
1252 13:53:30.189590
1253 13:53:30.189927 RX Vref 0 -> 0, step: 1
1254 13:53:30.190233
1255 13:53:30.192352 RX Delay -130 -> 252, step: 16
1256 13:53:30.196141 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1257 13:53:30.202230 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1258 13:53:30.206032 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1259 13:53:30.209097 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1260 13:53:30.212119 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1261 13:53:30.216136 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1262 13:53:30.219341 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1263 13:53:30.225917 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1264 13:53:30.229656 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1265 13:53:30.232561 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1266 13:53:30.235709 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1267 13:53:30.239524 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1268 13:53:30.246090 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1269 13:53:30.249098 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1270 13:53:30.252448 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1271 13:53:30.255825 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1272 13:53:30.256350 ==
1273 13:53:30.259016 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 13:53:30.265609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 13:53:30.266204 ==
1276 13:53:30.266554 DQS Delay:
1277 13:53:30.268802 DQS0 = 0, DQS1 = 0
1278 13:53:30.269216 DQM Delay:
1279 13:53:30.269591 DQM0 = 76, DQM1 = 69
1280 13:53:30.272178 DQ Delay:
1281 13:53:30.275652 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1282 13:53:30.279289 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1283 13:53:30.282292 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1284 13:53:30.285782 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1285 13:53:30.286297
1286 13:53:30.286633
1287 13:53:30.286939 ==
1288 13:53:30.289262 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 13:53:30.292767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 13:53:30.293317 ==
1291 13:53:30.293707
1292 13:53:30.294024
1293 13:53:30.295579 TX Vref Scan disable
1294 13:53:30.295994 == TX Byte 0 ==
1295 13:53:30.302432 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1296 13:53:30.305594 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1297 13:53:30.306015 == TX Byte 1 ==
1298 13:53:30.312635 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1299 13:53:30.315925 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1300 13:53:30.316465 ==
1301 13:53:30.319032 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 13:53:30.322469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 13:53:30.322986 ==
1304 13:53:30.336378 TX Vref=22, minBit 12, minWin=26, winSum=436
1305 13:53:30.339932 TX Vref=24, minBit 1, minWin=27, winSum=440
1306 13:53:30.343232 TX Vref=26, minBit 1, minWin=27, winSum=441
1307 13:53:30.346343 TX Vref=28, minBit 1, minWin=27, winSum=440
1308 13:53:30.349508 TX Vref=30, minBit 1, minWin=27, winSum=444
1309 13:53:30.356100 TX Vref=32, minBit 2, minWin=27, winSum=442
1310 13:53:30.359606 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
1311 13:53:30.360038
1312 13:53:30.362666 Final TX Range 1 Vref 30
1313 13:53:30.363076
1314 13:53:30.363396 ==
1315 13:53:30.366168 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 13:53:30.369454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 13:53:30.369942 ==
1318 13:53:30.370268
1319 13:53:30.372677
1320 13:53:30.373086 TX Vref Scan disable
1321 13:53:30.375997 == TX Byte 0 ==
1322 13:53:30.379559 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1323 13:53:30.386139 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1324 13:53:30.386592 == TX Byte 1 ==
1325 13:53:30.389930 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1326 13:53:30.396578 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1327 13:53:30.397103
1328 13:53:30.397430 [DATLAT]
1329 13:53:30.397793 Freq=800, CH0 RK1
1330 13:53:30.398252
1331 13:53:30.399321 DATLAT Default: 0xa
1332 13:53:30.399830 0, 0xFFFF, sum = 0
1333 13:53:30.402517 1, 0xFFFF, sum = 0
1334 13:53:30.402933 2, 0xFFFF, sum = 0
1335 13:53:30.406153 3, 0xFFFF, sum = 0
1336 13:53:30.406571 4, 0xFFFF, sum = 0
1337 13:53:30.409215 5, 0xFFFF, sum = 0
1338 13:53:30.412905 6, 0xFFFF, sum = 0
1339 13:53:30.413321 7, 0xFFFF, sum = 0
1340 13:53:30.415858 8, 0xFFFF, sum = 0
1341 13:53:30.416274 9, 0x0, sum = 1
1342 13:53:30.416599 10, 0x0, sum = 2
1343 13:53:30.419426 11, 0x0, sum = 3
1344 13:53:30.419843 12, 0x0, sum = 4
1345 13:53:30.423055 best_step = 10
1346 13:53:30.423564
1347 13:53:30.423884 ==
1348 13:53:30.426101 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 13:53:30.429516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 13:53:30.430037 ==
1351 13:53:30.433128 RX Vref Scan: 0
1352 13:53:30.433684
1353 13:53:30.434024 RX Vref 0 -> 0, step: 1
1354 13:53:30.434326
1355 13:53:30.435805 RX Delay -111 -> 252, step: 8
1356 13:53:30.443179 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1357 13:53:30.446641 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1358 13:53:30.449743 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1359 13:53:30.453293 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1360 13:53:30.456432 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1361 13:53:30.463422 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1362 13:53:30.466320 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1363 13:53:30.469325 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1364 13:53:30.472867 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1365 13:53:30.476375 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1366 13:53:30.483344 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1367 13:53:30.486343 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1368 13:53:30.489609 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1369 13:53:30.493006 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1370 13:53:30.496308 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1371 13:53:30.502928 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1372 13:53:30.503423 ==
1373 13:53:30.506481 Dram Type= 6, Freq= 0, CH_0, rank 1
1374 13:53:30.509648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 13:53:30.510065 ==
1376 13:53:30.510409 DQS Delay:
1377 13:53:30.513128 DQS0 = 0, DQS1 = 0
1378 13:53:30.513689 DQM Delay:
1379 13:53:30.516663 DQM0 = 79, DQM1 = 69
1380 13:53:30.517183 DQ Delay:
1381 13:53:30.519777 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1382 13:53:30.523347 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1383 13:53:30.526542 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1384 13:53:30.529932 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =76
1385 13:53:30.530342
1386 13:53:30.530686
1387 13:53:30.536376 [DQSOSCAuto] RK1, (LSB)MR18= 0x4924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1388 13:53:30.539734 CH0 RK1: MR19=606, MR18=4924
1389 13:53:30.546350 CH0_RK1: MR19=0x606, MR18=0x4924, DQSOSC=391, MR23=63, INC=96, DEC=64
1390 13:53:30.549724 [RxdqsGatingPostProcess] freq 800
1391 13:53:30.556361 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1392 13:53:30.559828 Pre-setting of DQS Precalculation
1393 13:53:30.563383 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1394 13:53:30.563902 ==
1395 13:53:30.566408 Dram Type= 6, Freq= 0, CH_1, rank 0
1396 13:53:30.569430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 13:53:30.569903 ==
1398 13:53:30.576577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1399 13:53:30.582948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1400 13:53:30.591360 [CA 0] Center 36 (6~67) winsize 62
1401 13:53:30.594747 [CA 1] Center 36 (6~67) winsize 62
1402 13:53:30.598432 [CA 2] Center 35 (5~65) winsize 61
1403 13:53:30.601285 [CA 3] Center 34 (4~64) winsize 61
1404 13:53:30.604997 [CA 4] Center 34 (5~64) winsize 60
1405 13:53:30.607999 [CA 5] Center 34 (4~64) winsize 61
1406 13:53:30.608513
1407 13:53:30.611295 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1408 13:53:30.611814
1409 13:53:30.614298 [CATrainingPosCal] consider 1 rank data
1410 13:53:30.617912 u2DelayCellTimex100 = 270/100 ps
1411 13:53:30.621248 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1412 13:53:30.624734 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 13:53:30.631274 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1414 13:53:30.634437 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1415 13:53:30.638099 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1416 13:53:30.641328 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1417 13:53:30.641898
1418 13:53:30.644533 CA PerBit enable=1, Macro0, CA PI delay=34
1419 13:53:30.645050
1420 13:53:30.648390 [CBTSetCACLKResult] CA Dly = 34
1421 13:53:30.648918 CS Dly: 4 (0~35)
1422 13:53:30.649255 ==
1423 13:53:30.651464 Dram Type= 6, Freq= 0, CH_1, rank 1
1424 13:53:30.657912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 13:53:30.658459 ==
1426 13:53:30.661047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1427 13:53:30.668308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1428 13:53:30.677646 [CA 0] Center 37 (7~67) winsize 61
1429 13:53:30.681123 [CA 1] Center 36 (6~67) winsize 62
1430 13:53:30.684362 [CA 2] Center 35 (5~65) winsize 61
1431 13:53:30.687817 [CA 3] Center 33 (3~64) winsize 62
1432 13:53:30.690981 [CA 4] Center 35 (5~65) winsize 61
1433 13:53:30.694230 [CA 5] Center 33 (3~64) winsize 62
1434 13:53:30.694748
1435 13:53:30.697927 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1436 13:53:30.698450
1437 13:53:30.701095 [CATrainingPosCal] consider 2 rank data
1438 13:53:30.704388 u2DelayCellTimex100 = 270/100 ps
1439 13:53:30.707653 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1440 13:53:30.710504 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1441 13:53:30.717875 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1442 13:53:30.721357 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1443 13:53:30.724802 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1444 13:53:30.728504 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1445 13:53:30.728929
1446 13:53:30.732304 CA PerBit enable=1, Macro0, CA PI delay=34
1447 13:53:30.733022
1448 13:53:30.733376 [CBTSetCACLKResult] CA Dly = 34
1449 13:53:30.735525 CS Dly: 5 (0~38)
1450 13:53:30.735975
1451 13:53:30.739563 ----->DramcWriteLeveling(PI) begin...
1452 13:53:30.740278 ==
1453 13:53:30.743507 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 13:53:30.747108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 13:53:30.747831 ==
1456 13:53:30.750664 Write leveling (Byte 0): 29 => 29
1457 13:53:30.754316 Write leveling (Byte 1): 29 => 29
1458 13:53:30.754861 DramcWriteLeveling(PI) end<-----
1459 13:53:30.757406
1460 13:53:30.757864 ==
1461 13:53:30.760746 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 13:53:30.764307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 13:53:30.764818 ==
1464 13:53:30.767245 [Gating] SW mode calibration
1465 13:53:30.773931 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1466 13:53:30.777529 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1467 13:53:30.784328 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1468 13:53:30.787786 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1469 13:53:30.791110 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1470 13:53:30.797709 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:53:30.800931 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:53:30.804085 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:53:30.811015 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:53:30.814167 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:53:30.817463 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:53:30.824426 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:53:30.827232 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:53:30.830873 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:53:30.837547 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:53:30.841122 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:53:30.844166 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:53:30.850864 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:53:30.854113 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:53:30.857614 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:53:30.861090 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1486 13:53:30.867591 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:53:30.870490 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:53:30.874016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:53:30.880777 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:53:30.884039 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:53:30.887567 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:53:30.893974 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:53:30.897539 0 9 8 | B1->B0 | 2a2a 2828 | 0 1 | (0 0) (1 1)
1494 13:53:30.900595 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 13:53:30.907521 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 13:53:30.910379 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 13:53:30.913721 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 13:53:30.920663 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 13:53:30.924202 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 13:53:30.926998 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (1 1) (0 0)
1501 13:53:30.934081 0 10 8 | B1->B0 | 2f2f 2b2b | 1 0 | (1 0) (0 0)
1502 13:53:30.937211 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:53:30.941047 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 13:53:30.946972 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:53:30.950317 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:53:30.954217 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 13:53:30.960427 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:53:30.964188 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1509 13:53:30.967168 0 11 8 | B1->B0 | 3c3c 3a3a | 0 0 | (0 0) (0 0)
1510 13:53:30.970523 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 13:53:30.977165 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 13:53:30.980724 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 13:53:30.984096 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 13:53:30.990498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 13:53:30.994260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 13:53:30.997592 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 13:53:31.004401 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 13:53:31.007416 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 13:53:31.010818 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 13:53:31.017458 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 13:53:31.020985 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 13:53:31.024099 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 13:53:31.030666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 13:53:31.034227 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 13:53:31.037551 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 13:53:31.044445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 13:53:31.047733 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 13:53:31.050678 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 13:53:31.054075 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 13:53:31.060930 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 13:53:31.064471 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 13:53:31.067645 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 13:53:31.074133 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1534 13:53:31.077688 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 13:53:31.080639 Total UI for P1: 0, mck2ui 16
1536 13:53:31.084401 best dqsien dly found for B0: ( 0, 14, 8)
1537 13:53:31.087150 Total UI for P1: 0, mck2ui 16
1538 13:53:31.090579 best dqsien dly found for B1: ( 0, 14, 8)
1539 13:53:31.094078 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1540 13:53:31.097852 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1541 13:53:31.098368
1542 13:53:31.100742 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1543 13:53:31.104156 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1544 13:53:31.107709 [Gating] SW calibration Done
1545 13:53:31.108226 ==
1546 13:53:31.111069 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 13:53:31.114027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 13:53:31.117514 ==
1549 13:53:31.117958 RX Vref Scan: 0
1550 13:53:31.118288
1551 13:53:31.120927 RX Vref 0 -> 0, step: 1
1552 13:53:31.121444
1553 13:53:31.124287 RX Delay -130 -> 252, step: 16
1554 13:53:31.127402 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1555 13:53:31.130404 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1556 13:53:31.134010 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1557 13:53:31.137646 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1558 13:53:31.143914 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1559 13:53:31.147572 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1560 13:53:31.150715 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1561 13:53:31.154349 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1562 13:53:31.157635 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1563 13:53:31.160982 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1564 13:53:31.167275 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1565 13:53:31.170661 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1566 13:53:31.173946 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1567 13:53:31.176987 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1568 13:53:31.183725 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1569 13:53:31.187239 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1570 13:53:31.187898 ==
1571 13:53:31.190572 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 13:53:31.193920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 13:53:31.194344 ==
1574 13:53:31.197418 DQS Delay:
1575 13:53:31.198014 DQS0 = 0, DQS1 = 0
1576 13:53:31.198363 DQM Delay:
1577 13:53:31.200495 DQM0 = 80, DQM1 = 73
1578 13:53:31.200911 DQ Delay:
1579 13:53:31.203991 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1580 13:53:31.207402 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1581 13:53:31.210107 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1582 13:53:31.213514 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1583 13:53:31.213936
1584 13:53:31.214266
1585 13:53:31.214575 ==
1586 13:53:31.216925 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 13:53:31.223605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 13:53:31.224112 ==
1589 13:53:31.224448
1590 13:53:31.224754
1591 13:53:31.225050 TX Vref Scan disable
1592 13:53:31.226751 == TX Byte 0 ==
1593 13:53:31.230215 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1594 13:53:31.236703 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1595 13:53:31.237127 == TX Byte 1 ==
1596 13:53:31.240119 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1597 13:53:31.243736 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1598 13:53:31.247179 ==
1599 13:53:31.250450 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 13:53:31.253658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 13:53:31.254180 ==
1602 13:53:31.266025 TX Vref=22, minBit 0, minWin=27, winSum=438
1603 13:53:31.269232 TX Vref=24, minBit 0, minWin=27, winSum=439
1604 13:53:31.272383 TX Vref=26, minBit 4, minWin=27, winSum=443
1605 13:53:31.275769 TX Vref=28, minBit 5, minWin=27, winSum=446
1606 13:53:31.279073 TX Vref=30, minBit 6, minWin=27, winSum=447
1607 13:53:31.282381 TX Vref=32, minBit 4, minWin=27, winSum=448
1608 13:53:31.289240 [TxChooseVref] Worse bit 4, Min win 27, Win sum 448, Final Vref 32
1609 13:53:31.289785
1610 13:53:31.292365 Final TX Range 1 Vref 32
1611 13:53:31.292810
1612 13:53:31.293144 ==
1613 13:53:31.296445 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 13:53:31.300307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 13:53:31.300739 ==
1616 13:53:31.301068
1617 13:53:31.301370
1618 13:53:31.303266 TX Vref Scan disable
1619 13:53:31.306955 == TX Byte 0 ==
1620 13:53:31.309934 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1621 13:53:31.313328 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1622 13:53:31.317022 == TX Byte 1 ==
1623 13:53:31.320233 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1624 13:53:31.323363 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1625 13:53:31.323784
1626 13:53:31.324109 [DATLAT]
1627 13:53:31.327015 Freq=800, CH1 RK0
1628 13:53:31.327539
1629 13:53:31.330035 DATLAT Default: 0xa
1630 13:53:31.330451 0, 0xFFFF, sum = 0
1631 13:53:31.333386 1, 0xFFFF, sum = 0
1632 13:53:31.333854 2, 0xFFFF, sum = 0
1633 13:53:31.336576 3, 0xFFFF, sum = 0
1634 13:53:31.337161 4, 0xFFFF, sum = 0
1635 13:53:31.339879 5, 0xFFFF, sum = 0
1636 13:53:31.340505 6, 0xFFFF, sum = 0
1637 13:53:31.343399 7, 0xFFFF, sum = 0
1638 13:53:31.343931 8, 0xFFFF, sum = 0
1639 13:53:31.346627 9, 0x0, sum = 1
1640 13:53:31.347050 10, 0x0, sum = 2
1641 13:53:31.350263 11, 0x0, sum = 3
1642 13:53:31.350687 12, 0x0, sum = 4
1643 13:53:31.351022 best_step = 10
1644 13:53:31.353127
1645 13:53:31.353587 ==
1646 13:53:31.356862 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 13:53:31.359893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 13:53:31.360312 ==
1649 13:53:31.360639 RX Vref Scan: 1
1650 13:53:31.360945
1651 13:53:31.363279 Set Vref Range= 32 -> 127
1652 13:53:31.363694
1653 13:53:31.366612 RX Vref 32 -> 127, step: 1
1654 13:53:31.367028
1655 13:53:31.370108 RX Delay -95 -> 252, step: 8
1656 13:53:31.370615
1657 13:53:31.373050 Set Vref, RX VrefLevel [Byte0]: 32
1658 13:53:31.376503 [Byte1]: 32
1659 13:53:31.376916
1660 13:53:31.379807 Set Vref, RX VrefLevel [Byte0]: 33
1661 13:53:31.383020 [Byte1]: 33
1662 13:53:31.383436
1663 13:53:31.386560 Set Vref, RX VrefLevel [Byte0]: 34
1664 13:53:31.389919 [Byte1]: 34
1665 13:53:31.393813
1666 13:53:31.394226 Set Vref, RX VrefLevel [Byte0]: 35
1667 13:53:31.396767 [Byte1]: 35
1668 13:53:31.401177
1669 13:53:31.401806 Set Vref, RX VrefLevel [Byte0]: 36
1670 13:53:31.404305 [Byte1]: 36
1671 13:53:31.408994
1672 13:53:31.409618 Set Vref, RX VrefLevel [Byte0]: 37
1673 13:53:31.412196 [Byte1]: 37
1674 13:53:31.416516
1675 13:53:31.417192 Set Vref, RX VrefLevel [Byte0]: 38
1676 13:53:31.419497 [Byte1]: 38
1677 13:53:31.424036
1678 13:53:31.424448 Set Vref, RX VrefLevel [Byte0]: 39
1679 13:53:31.427168 [Byte1]: 39
1680 13:53:31.431731
1681 13:53:31.432149 Set Vref, RX VrefLevel [Byte0]: 40
1682 13:53:31.434835 [Byte1]: 40
1683 13:53:31.439257
1684 13:53:31.439775 Set Vref, RX VrefLevel [Byte0]: 41
1685 13:53:31.442274 [Byte1]: 41
1686 13:53:31.446839
1687 13:53:31.447344 Set Vref, RX VrefLevel [Byte0]: 42
1688 13:53:31.450087 [Byte1]: 42
1689 13:53:31.454195
1690 13:53:31.454785 Set Vref, RX VrefLevel [Byte0]: 43
1691 13:53:31.457987 [Byte1]: 43
1692 13:53:31.461971
1693 13:53:31.462448 Set Vref, RX VrefLevel [Byte0]: 44
1694 13:53:31.465515 [Byte1]: 44
1695 13:53:31.470164
1696 13:53:31.470674 Set Vref, RX VrefLevel [Byte0]: 45
1697 13:53:31.472850 [Byte1]: 45
1698 13:53:31.477207
1699 13:53:31.477718 Set Vref, RX VrefLevel [Byte0]: 46
1700 13:53:31.480583 [Byte1]: 46
1701 13:53:31.485314
1702 13:53:31.485907 Set Vref, RX VrefLevel [Byte0]: 47
1703 13:53:31.488253 [Byte1]: 47
1704 13:53:31.492801
1705 13:53:31.493320 Set Vref, RX VrefLevel [Byte0]: 48
1706 13:53:31.495730 [Byte1]: 48
1707 13:53:31.500079
1708 13:53:31.500614 Set Vref, RX VrefLevel [Byte0]: 49
1709 13:53:31.503127 [Byte1]: 49
1710 13:53:31.508000
1711 13:53:31.508511 Set Vref, RX VrefLevel [Byte0]: 50
1712 13:53:31.510827 [Byte1]: 50
1713 13:53:31.515227
1714 13:53:31.515750 Set Vref, RX VrefLevel [Byte0]: 51
1715 13:53:31.518853 [Byte1]: 51
1716 13:53:31.523084
1717 13:53:31.523609 Set Vref, RX VrefLevel [Byte0]: 52
1718 13:53:31.526428 [Byte1]: 52
1719 13:53:31.530162
1720 13:53:31.530577 Set Vref, RX VrefLevel [Byte0]: 53
1721 13:53:31.534027 [Byte1]: 53
1722 13:53:31.538199
1723 13:53:31.538742 Set Vref, RX VrefLevel [Byte0]: 54
1724 13:53:31.541299 [Byte1]: 54
1725 13:53:31.545748
1726 13:53:31.546252 Set Vref, RX VrefLevel [Byte0]: 55
1727 13:53:31.549185 [Byte1]: 55
1728 13:53:31.553589
1729 13:53:31.554102 Set Vref, RX VrefLevel [Byte0]: 56
1730 13:53:31.556630 [Byte1]: 56
1731 13:53:31.560970
1732 13:53:31.561513 Set Vref, RX VrefLevel [Byte0]: 57
1733 13:53:31.564284 [Byte1]: 57
1734 13:53:31.568754
1735 13:53:31.569279 Set Vref, RX VrefLevel [Byte0]: 58
1736 13:53:31.572063 [Byte1]: 58
1737 13:53:31.575940
1738 13:53:31.576356 Set Vref, RX VrefLevel [Byte0]: 59
1739 13:53:31.579136 [Byte1]: 59
1740 13:53:31.583781
1741 13:53:31.584316 Set Vref, RX VrefLevel [Byte0]: 60
1742 13:53:31.587186 [Byte1]: 60
1743 13:53:31.591304
1744 13:53:31.591807 Set Vref, RX VrefLevel [Byte0]: 61
1745 13:53:31.594600 [Byte1]: 61
1746 13:53:31.599126
1747 13:53:31.599636 Set Vref, RX VrefLevel [Byte0]: 62
1748 13:53:31.602481 [Byte1]: 62
1749 13:53:31.606463
1750 13:53:31.606872 Set Vref, RX VrefLevel [Byte0]: 63
1751 13:53:31.609592 [Byte1]: 63
1752 13:53:31.614250
1753 13:53:31.614764 Set Vref, RX VrefLevel [Byte0]: 64
1754 13:53:31.617221 [Byte1]: 64
1755 13:53:31.621611
1756 13:53:31.622113 Set Vref, RX VrefLevel [Byte0]: 65
1757 13:53:31.625377 [Byte1]: 65
1758 13:53:31.629395
1759 13:53:31.630110 Set Vref, RX VrefLevel [Byte0]: 66
1760 13:53:31.632710 [Byte1]: 66
1761 13:53:31.637103
1762 13:53:31.637661 Set Vref, RX VrefLevel [Byte0]: 67
1763 13:53:31.640016 [Byte1]: 67
1764 13:53:31.645009
1765 13:53:31.645557 Set Vref, RX VrefLevel [Byte0]: 68
1766 13:53:31.647641 [Byte1]: 68
1767 13:53:31.652248
1768 13:53:31.652761 Set Vref, RX VrefLevel [Byte0]: 69
1769 13:53:31.655506 [Byte1]: 69
1770 13:53:31.659863
1771 13:53:31.660595 Set Vref, RX VrefLevel [Byte0]: 70
1772 13:53:31.662969 [Byte1]: 70
1773 13:53:31.667265
1774 13:53:31.667772 Set Vref, RX VrefLevel [Byte0]: 71
1775 13:53:31.670640 [Byte1]: 71
1776 13:53:31.674804
1777 13:53:31.675218 Set Vref, RX VrefLevel [Byte0]: 72
1778 13:53:31.677952 [Byte1]: 72
1779 13:53:31.682271
1780 13:53:31.682684 Set Vref, RX VrefLevel [Byte0]: 73
1781 13:53:31.685609 [Byte1]: 73
1782 13:53:31.690220
1783 13:53:31.690780 Set Vref, RX VrefLevel [Byte0]: 74
1784 13:53:31.692898 [Byte1]: 74
1785 13:53:31.697973
1786 13:53:31.698476 Set Vref, RX VrefLevel [Byte0]: 75
1787 13:53:31.701101 [Byte1]: 75
1788 13:53:31.705224
1789 13:53:31.705818 Set Vref, RX VrefLevel [Byte0]: 76
1790 13:53:31.709015 [Byte1]: 76
1791 13:53:31.712911
1792 13:53:31.713454 Set Vref, RX VrefLevel [Byte0]: 77
1793 13:53:31.716341 [Byte1]: 77
1794 13:53:31.720662
1795 13:53:31.721209 Set Vref, RX VrefLevel [Byte0]: 78
1796 13:53:31.723650 [Byte1]: 78
1797 13:53:31.728017
1798 13:53:31.728528 Final RX Vref Byte 0 = 57 to rank0
1799 13:53:31.731348 Final RX Vref Byte 1 = 56 to rank0
1800 13:53:31.734634 Final RX Vref Byte 0 = 57 to rank1
1801 13:53:31.738158 Final RX Vref Byte 1 = 56 to rank1==
1802 13:53:31.741582 Dram Type= 6, Freq= 0, CH_1, rank 0
1803 13:53:31.745118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 13:53:31.748292 ==
1805 13:53:31.748952 DQS Delay:
1806 13:53:31.749303 DQS0 = 0, DQS1 = 0
1807 13:53:31.751925 DQM Delay:
1808 13:53:31.752435 DQM0 = 81, DQM1 = 71
1809 13:53:31.755005 DQ Delay:
1810 13:53:31.755520 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1811 13:53:31.758379 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1812 13:53:31.761430 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1813 13:53:31.765016 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1814 13:53:31.768454
1815 13:53:31.768964
1816 13:53:31.774594 [DQSOSCAuto] RK0, (LSB)MR18= 0x1721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1817 13:53:31.777796 CH1 RK0: MR19=606, MR18=1721
1818 13:53:31.784491 CH1_RK0: MR19=0x606, MR18=0x1721, DQSOSC=401, MR23=63, INC=91, DEC=61
1819 13:53:31.784977
1820 13:53:31.787668 ----->DramcWriteLeveling(PI) begin...
1821 13:53:31.788097 ==
1822 13:53:31.790913 Dram Type= 6, Freq= 0, CH_1, rank 1
1823 13:53:31.794484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1824 13:53:31.794911 ==
1825 13:53:31.797678 Write leveling (Byte 0): 24 => 24
1826 13:53:31.800960 Write leveling (Byte 1): 30 => 30
1827 13:53:31.804587 DramcWriteLeveling(PI) end<-----
1828 13:53:31.804999
1829 13:53:31.805325 ==
1830 13:53:31.807595 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 13:53:31.811373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1832 13:53:31.811900 ==
1833 13:53:31.814162 [Gating] SW mode calibration
1834 13:53:31.821009 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1835 13:53:31.827562 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1836 13:53:31.830841 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1837 13:53:31.834528 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1838 13:53:31.841042 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:53:31.844324 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:53:31.847687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:53:31.854548 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:53:31.858016 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:53:31.861532 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:53:31.868025 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:53:31.871212 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:53:31.874309 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:53:31.880965 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:53:31.884419 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:53:31.887879 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:53:31.894055 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:53:31.897618 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:53:31.901127 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:53:31.904046 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1854 13:53:31.911350 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1855 13:53:31.914330 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:53:31.917684 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:53:31.924312 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:53:31.927607 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:53:31.930907 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 13:53:31.937652 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1861 13:53:31.941100 0 9 4 | B1->B0 | 2322 2b2b | 1 0 | (0 0) (0 0)
1862 13:53:31.944409 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1863 13:53:31.950941 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 13:53:31.954139 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 13:53:31.957606 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 13:53:31.964540 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 13:53:31.967722 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 13:53:31.971308 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1869 13:53:31.977303 0 10 4 | B1->B0 | 3030 2a2a | 1 0 | (1 1) (1 0)
1870 13:53:31.980669 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1871 13:53:31.984089 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 13:53:31.991002 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:53:31.994377 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:53:31.997585 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:53:32.004463 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 13:53:32.007418 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1877 13:53:32.010899 0 11 4 | B1->B0 | 2b2b 3838 | 1 0 | (0 0) (0 0)
1878 13:53:32.017659 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1879 13:53:32.020795 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 13:53:32.024288 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 13:53:32.027382 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 13:53:32.034342 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 13:53:32.037746 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 13:53:32.040947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1885 13:53:32.047772 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1886 13:53:32.050706 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1887 13:53:32.054184 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 13:53:32.061037 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 13:53:32.064150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 13:53:32.067258 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 13:53:32.073935 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 13:53:32.077453 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 13:53:32.080841 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 13:53:32.087574 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 13:53:32.090949 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 13:53:32.094513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 13:53:32.101008 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 13:53:32.103991 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 13:53:32.107483 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 13:53:32.111092 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 13:53:32.117254 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 13:53:32.121200 Total UI for P1: 0, mck2ui 16
1903 13:53:32.123915 best dqsien dly found for B0: ( 0, 14, 2)
1904 13:53:32.127352 Total UI for P1: 0, mck2ui 16
1905 13:53:32.130927 best dqsien dly found for B1: ( 0, 14, 2)
1906 13:53:32.133962 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1907 13:53:32.137579 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1908 13:53:32.138010
1909 13:53:32.140517 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1910 13:53:32.144105 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1911 13:53:32.147371 [Gating] SW calibration Done
1912 13:53:32.147798 ==
1913 13:53:32.150371 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 13:53:32.154072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 13:53:32.154576 ==
1916 13:53:32.157420 RX Vref Scan: 0
1917 13:53:32.157892
1918 13:53:32.158328 RX Vref 0 -> 0, step: 1
1919 13:53:32.158740
1920 13:53:32.160826 RX Delay -130 -> 252, step: 16
1921 13:53:32.167659 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1922 13:53:32.170696 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1923 13:53:32.174131 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1924 13:53:32.177464 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1925 13:53:32.180948 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1926 13:53:32.184204 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1927 13:53:32.190872 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1928 13:53:32.194033 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1929 13:53:32.197535 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1930 13:53:32.200762 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1931 13:53:32.204111 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1932 13:53:32.210651 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1933 13:53:32.214238 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1934 13:53:32.217369 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1935 13:53:32.220730 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1936 13:53:32.227612 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1937 13:53:32.228157 ==
1938 13:53:32.230476 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 13:53:32.233988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 13:53:32.234422 ==
1941 13:53:32.234861 DQS Delay:
1942 13:53:32.237631 DQS0 = 0, DQS1 = 0
1943 13:53:32.238163 DQM Delay:
1944 13:53:32.240664 DQM0 = 78, DQM1 = 71
1945 13:53:32.241095 DQ Delay:
1946 13:53:32.244259 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1947 13:53:32.247307 DQ4 =77, DQ5 =85, DQ6 =85, DQ7 =77
1948 13:53:32.250816 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1949 13:53:32.253855 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1950 13:53:32.254286
1951 13:53:32.254723
1952 13:53:32.255134 ==
1953 13:53:32.257166 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 13:53:32.261073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 13:53:32.261665 ==
1956 13:53:32.262118
1957 13:53:32.262528
1958 13:53:32.263900 TX Vref Scan disable
1959 13:53:32.267699 == TX Byte 0 ==
1960 13:53:32.270857 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1961 13:53:32.274118 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1962 13:53:32.277380 == TX Byte 1 ==
1963 13:53:32.280918 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1964 13:53:32.283784 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1965 13:53:32.284222 ==
1966 13:53:32.287258 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 13:53:32.293637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 13:53:32.294071 ==
1969 13:53:32.306212 TX Vref=22, minBit 11, minWin=27, winSum=454
1970 13:53:32.309447 TX Vref=24, minBit 5, minWin=28, winSum=461
1971 13:53:32.312365 TX Vref=26, minBit 10, minWin=28, winSum=462
1972 13:53:32.315999 TX Vref=28, minBit 13, minWin=28, winSum=466
1973 13:53:32.318989 TX Vref=30, minBit 0, minWin=29, winSum=468
1974 13:53:32.325754 TX Vref=32, minBit 2, minWin=28, winSum=466
1975 13:53:32.328831 [TxChooseVref] Worse bit 0, Min win 29, Win sum 468, Final Vref 30
1976 13:53:32.329258
1977 13:53:32.332401 Final TX Range 1 Vref 30
1978 13:53:32.332825
1979 13:53:32.333168 ==
1980 13:53:32.335862 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 13:53:32.339770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 13:53:32.342976 ==
1983 13:53:32.343490
1984 13:53:32.343821
1985 13:53:32.344130 TX Vref Scan disable
1986 13:53:32.346195 == TX Byte 0 ==
1987 13:53:32.349704 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1988 13:53:32.356332 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1989 13:53:32.356848 == TX Byte 1 ==
1990 13:53:32.359618 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1991 13:53:32.366071 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1992 13:53:32.366572
1993 13:53:32.367019 [DATLAT]
1994 13:53:32.367433 Freq=800, CH1 RK1
1995 13:53:32.367839
1996 13:53:32.368946 DATLAT Default: 0xa
1997 13:53:32.369372 0, 0xFFFF, sum = 0
1998 13:53:32.372655 1, 0xFFFF, sum = 0
1999 13:53:32.375998 2, 0xFFFF, sum = 0
2000 13:53:32.376557 3, 0xFFFF, sum = 0
2001 13:53:32.379365 4, 0xFFFF, sum = 0
2002 13:53:32.379805 5, 0xFFFF, sum = 0
2003 13:53:32.382349 6, 0xFFFF, sum = 0
2004 13:53:32.382913 7, 0xFFFF, sum = 0
2005 13:53:32.385835 8, 0xFFFF, sum = 0
2006 13:53:32.386333 9, 0x0, sum = 1
2007 13:53:32.389067 10, 0x0, sum = 2
2008 13:53:32.389520 11, 0x0, sum = 3
2009 13:53:32.389869 12, 0x0, sum = 4
2010 13:53:32.392896 best_step = 10
2011 13:53:32.393416
2012 13:53:32.393819 ==
2013 13:53:32.396018 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 13:53:32.399125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 13:53:32.399549 ==
2016 13:53:32.402339 RX Vref Scan: 0
2017 13:53:32.402759
2018 13:53:32.405604 RX Vref 0 -> 0, step: 1
2019 13:53:32.406111
2020 13:53:32.406444 RX Delay -111 -> 252, step: 8
2021 13:53:32.413343 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2022 13:53:32.416801 iDelay=209, Bit 1, Center 68 (-55 ~ 192) 248
2023 13:53:32.419728 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2024 13:53:32.423441 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2025 13:53:32.426548 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2026 13:53:32.432767 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2027 13:53:32.436567 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2028 13:53:32.439667 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2029 13:53:32.443339 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2030 13:53:32.446400 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2031 13:53:32.452927 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2032 13:53:32.456111 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2033 13:53:32.460015 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2034 13:53:32.462911 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2035 13:53:32.466360 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2036 13:53:32.472906 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2037 13:53:32.473420 ==
2038 13:53:32.476395 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 13:53:32.479495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 13:53:32.479918 ==
2041 13:53:32.480250 DQS Delay:
2042 13:53:32.483050 DQS0 = 0, DQS1 = 0
2043 13:53:32.483468 DQM Delay:
2044 13:53:32.486093 DQM0 = 76, DQM1 = 74
2045 13:53:32.486587 DQ Delay:
2046 13:53:32.489725 DQ0 =80, DQ1 =68, DQ2 =64, DQ3 =72
2047 13:53:32.492955 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2048 13:53:32.496273 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2049 13:53:32.499657 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2050 13:53:32.500078
2051 13:53:32.500410
2052 13:53:32.506154 [DQSOSCAuto] RK1, (LSB)MR18= 0x273e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2053 13:53:32.509997 CH1 RK1: MR19=606, MR18=273E
2054 13:53:32.516673 CH1_RK1: MR19=0x606, MR18=0x273E, DQSOSC=394, MR23=63, INC=95, DEC=63
2055 13:53:32.519708 [RxdqsGatingPostProcess] freq 800
2056 13:53:32.526441 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2057 13:53:32.529556 Pre-setting of DQS Precalculation
2058 13:53:32.533142 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2059 13:53:32.539514 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2060 13:53:32.546166 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2061 13:53:32.546686
2062 13:53:32.547019
2063 13:53:32.549857 [Calibration Summary] 1600 Mbps
2064 13:53:32.552793 CH 0, Rank 0
2065 13:53:32.553213 SW Impedance : PASS
2066 13:53:32.556371 DUTY Scan : NO K
2067 13:53:32.559765 ZQ Calibration : PASS
2068 13:53:32.560195 Jitter Meter : NO K
2069 13:53:32.562997 CBT Training : PASS
2070 13:53:32.566240 Write leveling : PASS
2071 13:53:32.566695 RX DQS gating : PASS
2072 13:53:32.569804 RX DQ/DQS(RDDQC) : PASS
2073 13:53:32.570223 TX DQ/DQS : PASS
2074 13:53:32.572871 RX DATLAT : PASS
2075 13:53:32.576332 RX DQ/DQS(Engine): PASS
2076 13:53:32.576770 TX OE : NO K
2077 13:53:32.579536 All Pass.
2078 13:53:32.579957
2079 13:53:32.580287 CH 0, Rank 1
2080 13:53:32.582968 SW Impedance : PASS
2081 13:53:32.583554 DUTY Scan : NO K
2082 13:53:32.586094 ZQ Calibration : PASS
2083 13:53:32.589372 Jitter Meter : NO K
2084 13:53:32.589839 CBT Training : PASS
2085 13:53:32.592809 Write leveling : PASS
2086 13:53:32.596341 RX DQS gating : PASS
2087 13:53:32.596760 RX DQ/DQS(RDDQC) : PASS
2088 13:53:32.599497 TX DQ/DQS : PASS
2089 13:53:32.603199 RX DATLAT : PASS
2090 13:53:32.603615 RX DQ/DQS(Engine): PASS
2091 13:53:32.606279 TX OE : NO K
2092 13:53:32.606701 All Pass.
2093 13:53:32.607185
2094 13:53:32.609441 CH 1, Rank 0
2095 13:53:32.609913 SW Impedance : PASS
2096 13:53:32.613017 DUTY Scan : NO K
2097 13:53:32.616068 ZQ Calibration : PASS
2098 13:53:32.616567 Jitter Meter : NO K
2099 13:53:32.619635 CBT Training : PASS
2100 13:53:32.620229 Write leveling : PASS
2101 13:53:32.622662 RX DQS gating : PASS
2102 13:53:32.626300 RX DQ/DQS(RDDQC) : PASS
2103 13:53:32.626717 TX DQ/DQS : PASS
2104 13:53:32.629296 RX DATLAT : PASS
2105 13:53:32.632931 RX DQ/DQS(Engine): PASS
2106 13:53:32.633360 TX OE : NO K
2107 13:53:32.636120 All Pass.
2108 13:53:32.636600
2109 13:53:32.636933 CH 1, Rank 1
2110 13:53:32.639409 SW Impedance : PASS
2111 13:53:32.639913 DUTY Scan : NO K
2112 13:53:32.642796 ZQ Calibration : PASS
2113 13:53:32.645956 Jitter Meter : NO K
2114 13:53:32.646372 CBT Training : PASS
2115 13:53:32.649364 Write leveling : PASS
2116 13:53:32.653006 RX DQS gating : PASS
2117 13:53:32.653537 RX DQ/DQS(RDDQC) : PASS
2118 13:53:32.656144 TX DQ/DQS : PASS
2119 13:53:32.659233 RX DATLAT : PASS
2120 13:53:32.659647 RX DQ/DQS(Engine): PASS
2121 13:53:32.662383 TX OE : NO K
2122 13:53:32.662803 All Pass.
2123 13:53:32.663166
2124 13:53:32.665787 DramC Write-DBI off
2125 13:53:32.669189 PER_BANK_REFRESH: Hybrid Mode
2126 13:53:32.669848 TX_TRACKING: ON
2127 13:53:32.672364 [GetDramInforAfterCalByMRR] Vendor 6.
2128 13:53:32.675838 [GetDramInforAfterCalByMRR] Revision 606.
2129 13:53:32.679092 [GetDramInforAfterCalByMRR] Revision 2 0.
2130 13:53:32.682486 MR0 0x3b3b
2131 13:53:32.682934 MR8 0x5151
2132 13:53:32.685537 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 13:53:32.685938
2134 13:53:32.686262 MR0 0x3b3b
2135 13:53:32.688940 MR8 0x5151
2136 13:53:32.692382 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 13:53:32.692943
2138 13:53:32.698926 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2139 13:53:32.705723 [FAST_K] Save calibration result to emmc
2140 13:53:32.708892 [FAST_K] Save calibration result to emmc
2141 13:53:32.709460 dram_init: config_dvfs: 1
2142 13:53:32.715847 dramc_set_vcore_voltage set vcore to 662500
2143 13:53:32.716267 Read voltage for 1200, 2
2144 13:53:32.716592 Vio18 = 0
2145 13:53:32.718784 Vcore = 662500
2146 13:53:32.719224 Vdram = 0
2147 13:53:32.719559 Vddq = 0
2148 13:53:32.722280 Vmddr = 0
2149 13:53:32.725718 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2150 13:53:32.732130 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2151 13:53:32.735755 MEM_TYPE=3, freq_sel=15
2152 13:53:32.736050 sv_algorithm_assistance_LP4_1600
2153 13:53:32.742465 ============ PULL DRAM RESETB DOWN ============
2154 13:53:32.745451 ========== PULL DRAM RESETB DOWN end =========
2155 13:53:32.749037 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2156 13:53:32.752499 ===================================
2157 13:53:32.755808 LPDDR4 DRAM CONFIGURATION
2158 13:53:32.758893 ===================================
2159 13:53:32.762472 EX_ROW_EN[0] = 0x0
2160 13:53:32.762791 EX_ROW_EN[1] = 0x0
2161 13:53:32.766009 LP4Y_EN = 0x0
2162 13:53:32.766396 WORK_FSP = 0x0
2163 13:53:32.769552 WL = 0x4
2164 13:53:32.769950 RL = 0x4
2165 13:53:32.772426 BL = 0x2
2166 13:53:32.772811 RPST = 0x0
2167 13:53:32.775479 RD_PRE = 0x0
2168 13:53:32.775831 WR_PRE = 0x1
2169 13:53:32.779126 WR_PST = 0x0
2170 13:53:32.779417 DBI_WR = 0x0
2171 13:53:32.782320 DBI_RD = 0x0
2172 13:53:32.782614 OTF = 0x1
2173 13:53:32.785929 ===================================
2174 13:53:32.789395 ===================================
2175 13:53:32.792344 ANA top config
2176 13:53:32.795910 ===================================
2177 13:53:32.796209 DLL_ASYNC_EN = 0
2178 13:53:32.799069 ALL_SLAVE_EN = 0
2179 13:53:32.802590 NEW_RANK_MODE = 1
2180 13:53:32.805568 DLL_IDLE_MODE = 1
2181 13:53:32.808934 LP45_APHY_COMB_EN = 1
2182 13:53:32.809265 TX_ODT_DIS = 1
2183 13:53:32.812363 NEW_8X_MODE = 1
2184 13:53:32.815645 ===================================
2185 13:53:32.818984 ===================================
2186 13:53:32.822314 data_rate = 2400
2187 13:53:32.825794 CKR = 1
2188 13:53:32.828901 DQ_P2S_RATIO = 8
2189 13:53:32.832724 ===================================
2190 13:53:32.833144 CA_P2S_RATIO = 8
2191 13:53:32.836069 DQ_CA_OPEN = 0
2192 13:53:32.839216 DQ_SEMI_OPEN = 0
2193 13:53:32.842627 CA_SEMI_OPEN = 0
2194 13:53:32.846105 CA_FULL_RATE = 0
2195 13:53:32.849286 DQ_CKDIV4_EN = 0
2196 13:53:32.849936 CA_CKDIV4_EN = 0
2197 13:53:32.852513 CA_PREDIV_EN = 0
2198 13:53:32.856220 PH8_DLY = 17
2199 13:53:32.859623 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2200 13:53:32.862529 DQ_AAMCK_DIV = 4
2201 13:53:32.865901 CA_AAMCK_DIV = 4
2202 13:53:32.866340 CA_ADMCK_DIV = 4
2203 13:53:32.868905 DQ_TRACK_CA_EN = 0
2204 13:53:32.872626 CA_PICK = 1200
2205 13:53:32.875645 CA_MCKIO = 1200
2206 13:53:32.879111 MCKIO_SEMI = 0
2207 13:53:32.882574 PLL_FREQ = 2366
2208 13:53:32.885658 DQ_UI_PI_RATIO = 32
2209 13:53:32.889460 CA_UI_PI_RATIO = 0
2210 13:53:32.890077 ===================================
2211 13:53:32.892226 ===================================
2212 13:53:32.896024 memory_type:LPDDR4
2213 13:53:32.899513 GP_NUM : 10
2214 13:53:32.900045 SRAM_EN : 1
2215 13:53:32.902220 MD32_EN : 0
2216 13:53:32.905760 ===================================
2217 13:53:32.908932 [ANA_INIT] >>>>>>>>>>>>>>
2218 13:53:32.912415 <<<<<< [CONFIGURE PHASE]: ANA_TX
2219 13:53:32.916093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2220 13:53:32.919256 ===================================
2221 13:53:32.919675 data_rate = 2400,PCW = 0X5b00
2222 13:53:32.922300 ===================================
2223 13:53:32.926020 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2224 13:53:32.932551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 13:53:32.939068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2226 13:53:32.942155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2227 13:53:32.946023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2228 13:53:32.949158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2229 13:53:32.952223 [ANA_INIT] flow start
2230 13:53:32.952637 [ANA_INIT] PLL >>>>>>>>
2231 13:53:32.955666 [ANA_INIT] PLL <<<<<<<<
2232 13:53:32.959258 [ANA_INIT] MIDPI >>>>>>>>
2233 13:53:32.962434 [ANA_INIT] MIDPI <<<<<<<<
2234 13:53:32.962861 [ANA_INIT] DLL >>>>>>>>
2235 13:53:32.965824 [ANA_INIT] DLL <<<<<<<<
2236 13:53:32.969552 [ANA_INIT] flow end
2237 13:53:32.972294 ============ LP4 DIFF to SE enter ============
2238 13:53:32.975605 ============ LP4 DIFF to SE exit ============
2239 13:53:32.979095 [ANA_INIT] <<<<<<<<<<<<<
2240 13:53:32.982107 [Flow] Enable top DCM control >>>>>
2241 13:53:32.985612 [Flow] Enable top DCM control <<<<<
2242 13:53:32.988888 Enable DLL master slave shuffle
2243 13:53:32.992427 ==============================================================
2244 13:53:32.995908 Gating Mode config
2245 13:53:32.999122 ==============================================================
2246 13:53:33.002584 Config description:
2247 13:53:33.012242 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2248 13:53:33.018808 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2249 13:53:33.022202 SELPH_MODE 0: By rank 1: By Phase
2250 13:53:33.029074 ==============================================================
2251 13:53:33.031986 GAT_TRACK_EN = 1
2252 13:53:33.035601 RX_GATING_MODE = 2
2253 13:53:33.039021 RX_GATING_TRACK_MODE = 2
2254 13:53:33.042388 SELPH_MODE = 1
2255 13:53:33.045531 PICG_EARLY_EN = 1
2256 13:53:33.045943 VALID_LAT_VALUE = 1
2257 13:53:33.052084 ==============================================================
2258 13:53:33.055604 Enter into Gating configuration >>>>
2259 13:53:33.058786 Exit from Gating configuration <<<<
2260 13:53:33.062101 Enter into DVFS_PRE_config >>>>>
2261 13:53:33.072182 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2262 13:53:33.075332 Exit from DVFS_PRE_config <<<<<
2263 13:53:33.078541 Enter into PICG configuration >>>>
2264 13:53:33.082000 Exit from PICG configuration <<<<
2265 13:53:33.085275 [RX_INPUT] configuration >>>>>
2266 13:53:33.088618 [RX_INPUT] configuration <<<<<
2267 13:53:33.091719 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2268 13:53:33.098261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2269 13:53:33.105147 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2270 13:53:33.111705 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2271 13:53:33.118199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2272 13:53:33.125035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2273 13:53:33.127918 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2274 13:53:33.131575 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2275 13:53:33.134700 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2276 13:53:33.138214 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2277 13:53:33.144724 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2278 13:53:33.148370 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 13:53:33.151659 ===================================
2280 13:53:33.154819 LPDDR4 DRAM CONFIGURATION
2281 13:53:33.158328 ===================================
2282 13:53:33.158418 EX_ROW_EN[0] = 0x0
2283 13:53:33.161481 EX_ROW_EN[1] = 0x0
2284 13:53:33.161565 LP4Y_EN = 0x0
2285 13:53:33.164994 WORK_FSP = 0x0
2286 13:53:33.165072 WL = 0x4
2287 13:53:33.167940 RL = 0x4
2288 13:53:33.168017 BL = 0x2
2289 13:53:33.171412 RPST = 0x0
2290 13:53:33.171491 RD_PRE = 0x0
2291 13:53:33.175006 WR_PRE = 0x1
2292 13:53:33.175119 WR_PST = 0x0
2293 13:53:33.178271 DBI_WR = 0x0
2294 13:53:33.181335 DBI_RD = 0x0
2295 13:53:33.181417 OTF = 0x1
2296 13:53:33.184668 ===================================
2297 13:53:33.188184 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2298 13:53:33.191570 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2299 13:53:33.198311 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2300 13:53:33.201445 ===================================
2301 13:53:33.201565 LPDDR4 DRAM CONFIGURATION
2302 13:53:33.204938 ===================================
2303 13:53:33.208235 EX_ROW_EN[0] = 0x10
2304 13:53:33.211476 EX_ROW_EN[1] = 0x0
2305 13:53:33.211560 LP4Y_EN = 0x0
2306 13:53:33.214692 WORK_FSP = 0x0
2307 13:53:33.214775 WL = 0x4
2308 13:53:33.218307 RL = 0x4
2309 13:53:33.218392 BL = 0x2
2310 13:53:33.221421 RPST = 0x0
2311 13:53:33.221543 RD_PRE = 0x0
2312 13:53:33.224991 WR_PRE = 0x1
2313 13:53:33.225108 WR_PST = 0x0
2314 13:53:33.228245 DBI_WR = 0x0
2315 13:53:33.228329 DBI_RD = 0x0
2316 13:53:33.231435 OTF = 0x1
2317 13:53:33.234872 ===================================
2318 13:53:33.241876 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2319 13:53:33.241968 ==
2320 13:53:33.245221 Dram Type= 6, Freq= 0, CH_0, rank 0
2321 13:53:33.248191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2322 13:53:33.248289 ==
2323 13:53:33.251643 [Duty_Offset_Calibration]
2324 13:53:33.251740 B0:2 B1:0 CA:3
2325 13:53:33.251857
2326 13:53:33.254935 [DutyScan_Calibration_Flow] k_type=0
2327 13:53:33.265041
2328 13:53:33.265169 ==CLK 0==
2329 13:53:33.268679 Final CLK duty delay cell = 0
2330 13:53:33.271842 [0] MAX Duty = 5031%(X100), DQS PI = 12
2331 13:53:33.275339 [0] MIN Duty = 4906%(X100), DQS PI = 54
2332 13:53:33.275498 [0] AVG Duty = 4968%(X100)
2333 13:53:33.278730
2334 13:53:33.281654 CH0 CLK Duty spec in!! Max-Min= 125%
2335 13:53:33.285122 [DutyScan_Calibration_Flow] ====Done====
2336 13:53:33.285436
2337 13:53:33.288716 [DutyScan_Calibration_Flow] k_type=1
2338 13:53:33.304033
2339 13:53:33.304460 ==DQS 0 ==
2340 13:53:33.307413 Final DQS duty delay cell = 0
2341 13:53:33.310640 [0] MAX Duty = 5062%(X100), DQS PI = 12
2342 13:53:33.313924 [0] MIN Duty = 4907%(X100), DQS PI = 2
2343 13:53:33.314534 [0] AVG Duty = 4984%(X100)
2344 13:53:33.317351
2345 13:53:33.318015 ==DQS 1 ==
2346 13:53:33.320428 Final DQS duty delay cell = -4
2347 13:53:33.323882 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2348 13:53:33.327363 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2349 13:53:33.330310 [-4] AVG Duty = 4938%(X100)
2350 13:53:33.330890
2351 13:53:33.333862 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2352 13:53:33.334284
2353 13:53:33.337392 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2354 13:53:33.340808 [DutyScan_Calibration_Flow] ====Done====
2355 13:53:33.341624
2356 13:53:33.343855 [DutyScan_Calibration_Flow] k_type=3
2357 13:53:33.361440
2358 13:53:33.361960 ==DQM 0 ==
2359 13:53:33.364998 Final DQM duty delay cell = 0
2360 13:53:33.368164 [0] MAX Duty = 5124%(X100), DQS PI = 28
2361 13:53:33.371272 [0] MIN Duty = 4876%(X100), DQS PI = 0
2362 13:53:33.371696 [0] AVG Duty = 5000%(X100)
2363 13:53:33.374971
2364 13:53:33.375385 ==DQM 1 ==
2365 13:53:33.378037 Final DQM duty delay cell = 4
2366 13:53:33.381433 [4] MAX Duty = 5124%(X100), DQS PI = 50
2367 13:53:33.384754 [4] MIN Duty = 5031%(X100), DQS PI = 12
2368 13:53:33.388268 [4] AVG Duty = 5077%(X100)
2369 13:53:33.388681
2370 13:53:33.391565 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2371 13:53:33.391982
2372 13:53:33.394863 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2373 13:53:33.398054 [DutyScan_Calibration_Flow] ====Done====
2374 13:53:33.398466
2375 13:53:33.401380 [DutyScan_Calibration_Flow] k_type=2
2376 13:53:33.416724
2377 13:53:33.417240 ==DQ 0 ==
2378 13:53:33.419489 Final DQ duty delay cell = -4
2379 13:53:33.422814 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2380 13:53:33.426302 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2381 13:53:33.429824 [-4] AVG Duty = 4953%(X100)
2382 13:53:33.430238
2383 13:53:33.430562 ==DQ 1 ==
2384 13:53:33.432826 Final DQ duty delay cell = -4
2385 13:53:33.436302 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2386 13:53:33.439691 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2387 13:53:33.443050 [-4] AVG Duty = 4938%(X100)
2388 13:53:33.443545
2389 13:53:33.446270 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2390 13:53:33.446732
2391 13:53:33.449771 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2392 13:53:33.453157 [DutyScan_Calibration_Flow] ====Done====
2393 13:53:33.453699 ==
2394 13:53:33.456019 Dram Type= 6, Freq= 0, CH_1, rank 0
2395 13:53:33.459399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2396 13:53:33.459936 ==
2397 13:53:33.462827 [Duty_Offset_Calibration]
2398 13:53:33.463319 B0:1 B1:-2 CA:0
2399 13:53:33.463771
2400 13:53:33.466075 [DutyScan_Calibration_Flow] k_type=0
2401 13:53:33.476838
2402 13:53:33.477245 ==CLK 0==
2403 13:53:33.479815 Final CLK duty delay cell = 0
2404 13:53:33.483560 [0] MAX Duty = 5031%(X100), DQS PI = 16
2405 13:53:33.486840 [0] MIN Duty = 4844%(X100), DQS PI = 58
2406 13:53:33.487319 [0] AVG Duty = 4937%(X100)
2407 13:53:33.489871
2408 13:53:33.493266 CH1 CLK Duty spec in!! Max-Min= 187%
2409 13:53:33.496525 [DutyScan_Calibration_Flow] ====Done====
2410 13:53:33.497072
2411 13:53:33.500157 [DutyScan_Calibration_Flow] k_type=1
2412 13:53:33.515303
2413 13:53:33.515720 ==DQS 0 ==
2414 13:53:33.518905 Final DQS duty delay cell = -4
2415 13:53:33.521985 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2416 13:53:33.525232 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2417 13:53:33.528704 [-4] AVG Duty = 4969%(X100)
2418 13:53:33.529358
2419 13:53:33.529873 ==DQS 1 ==
2420 13:53:33.531764 Final DQS duty delay cell = 0
2421 13:53:33.535210 [0] MAX Duty = 5093%(X100), DQS PI = 0
2422 13:53:33.538492 [0] MIN Duty = 4844%(X100), DQS PI = 26
2423 13:53:33.542300 [0] AVG Duty = 4968%(X100)
2424 13:53:33.542821
2425 13:53:33.545366 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2426 13:53:33.546208
2427 13:53:33.548363 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2428 13:53:33.551801 [DutyScan_Calibration_Flow] ====Done====
2429 13:53:33.552398
2430 13:53:33.555049 [DutyScan_Calibration_Flow] k_type=3
2431 13:53:33.571766
2432 13:53:33.572366 ==DQM 0 ==
2433 13:53:33.575099 Final DQM duty delay cell = 0
2434 13:53:33.578520 [0] MAX Duty = 5000%(X100), DQS PI = 22
2435 13:53:33.581948 [0] MIN Duty = 4876%(X100), DQS PI = 50
2436 13:53:33.582525 [0] AVG Duty = 4938%(X100)
2437 13:53:33.585394
2438 13:53:33.585968 ==DQM 1 ==
2439 13:53:33.588317 Final DQM duty delay cell = 0
2440 13:53:33.591947 [0] MAX Duty = 5031%(X100), DQS PI = 34
2441 13:53:33.595470 [0] MIN Duty = 4876%(X100), DQS PI = 26
2442 13:53:33.598597 [0] AVG Duty = 4953%(X100)
2443 13:53:33.599025
2444 13:53:33.601659 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2445 13:53:33.602209
2446 13:53:33.605304 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2447 13:53:33.608553 [DutyScan_Calibration_Flow] ====Done====
2448 13:53:33.608991
2449 13:53:33.611647 [DutyScan_Calibration_Flow] k_type=2
2450 13:53:33.628350
2451 13:53:33.628768 ==DQ 0 ==
2452 13:53:33.631495 Final DQ duty delay cell = 0
2453 13:53:33.634869 [0] MAX Duty = 5062%(X100), DQS PI = 14
2454 13:53:33.638411 [0] MIN Duty = 4907%(X100), DQS PI = 56
2455 13:53:33.639007 [0] AVG Duty = 4984%(X100)
2456 13:53:33.641747
2457 13:53:33.642281 ==DQ 1 ==
2458 13:53:33.645128 Final DQ duty delay cell = 0
2459 13:53:33.648424 [0] MAX Duty = 5125%(X100), DQS PI = 34
2460 13:53:33.651881 [0] MIN Duty = 4938%(X100), DQS PI = 26
2461 13:53:33.652304 [0] AVG Duty = 5031%(X100)
2462 13:53:33.652632
2463 13:53:33.655049 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2464 13:53:33.658320
2465 13:53:33.661650 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2466 13:53:33.664917 [DutyScan_Calibration_Flow] ====Done====
2467 13:53:33.668114 nWR fixed to 30
2468 13:53:33.668364 [ModeRegInit_LP4] CH0 RK0
2469 13:53:33.671312 [ModeRegInit_LP4] CH0 RK1
2470 13:53:33.674598 [ModeRegInit_LP4] CH1 RK0
2471 13:53:33.674824 [ModeRegInit_LP4] CH1 RK1
2472 13:53:33.678213 match AC timing 7
2473 13:53:33.681286 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2474 13:53:33.684747 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2475 13:53:33.691514 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2476 13:53:33.695046 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2477 13:53:33.701308 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2478 13:53:33.701557 ==
2479 13:53:33.704861 Dram Type= 6, Freq= 0, CH_0, rank 0
2480 13:53:33.707987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 13:53:33.708310 ==
2482 13:53:33.714598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 13:53:33.721083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2484 13:53:33.727979 [CA 0] Center 40 (10~71) winsize 62
2485 13:53:33.731274 [CA 1] Center 39 (9~70) winsize 62
2486 13:53:33.734497 [CA 2] Center 36 (6~66) winsize 61
2487 13:53:33.738009 [CA 3] Center 35 (5~66) winsize 62
2488 13:53:33.741264 [CA 4] Center 34 (4~65) winsize 62
2489 13:53:33.744532 [CA 5] Center 33 (3~64) winsize 62
2490 13:53:33.744615
2491 13:53:33.748326 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2492 13:53:33.748409
2493 13:53:33.751546 [CATrainingPosCal] consider 1 rank data
2494 13:53:33.754534 u2DelayCellTimex100 = 270/100 ps
2495 13:53:33.758241 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2496 13:53:33.761301 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2497 13:53:33.767860 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2498 13:53:33.771663 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 13:53:33.774610 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2500 13:53:33.777913 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2501 13:53:33.778004
2502 13:53:33.781507 CA PerBit enable=1, Macro0, CA PI delay=33
2503 13:53:33.781602
2504 13:53:33.784755 [CBTSetCACLKResult] CA Dly = 33
2505 13:53:33.784868 CS Dly: 7 (0~38)
2506 13:53:33.787962 ==
2507 13:53:33.791445 Dram Type= 6, Freq= 0, CH_0, rank 1
2508 13:53:33.794526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 13:53:33.794624 ==
2510 13:53:33.797950 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 13:53:33.804610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2512 13:53:33.814097 [CA 0] Center 40 (10~70) winsize 61
2513 13:53:33.817123 [CA 1] Center 39 (9~70) winsize 62
2514 13:53:33.820624 [CA 2] Center 35 (5~66) winsize 62
2515 13:53:33.824114 [CA 3] Center 35 (5~66) winsize 62
2516 13:53:33.827297 [CA 4] Center 34 (4~65) winsize 62
2517 13:53:33.830948 [CA 5] Center 33 (3~63) winsize 61
2518 13:53:33.831032
2519 13:53:33.833891 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2520 13:53:33.834002
2521 13:53:33.837315 [CATrainingPosCal] consider 2 rank data
2522 13:53:33.840431 u2DelayCellTimex100 = 270/100 ps
2523 13:53:33.843972 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2524 13:53:33.850736 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2525 13:53:33.853749 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2526 13:53:33.857192 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2527 13:53:33.860564 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2528 13:53:33.863755 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2529 13:53:33.863855
2530 13:53:33.867240 CA PerBit enable=1, Macro0, CA PI delay=33
2531 13:53:33.867369
2532 13:53:33.870395 [CBTSetCACLKResult] CA Dly = 33
2533 13:53:33.873892 CS Dly: 8 (0~40)
2534 13:53:33.873974
2535 13:53:33.877225 ----->DramcWriteLeveling(PI) begin...
2536 13:53:33.877359 ==
2537 13:53:33.880596 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 13:53:33.884035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 13:53:33.884112 ==
2540 13:53:33.887169 Write leveling (Byte 0): 32 => 32
2541 13:53:33.890504 Write leveling (Byte 1): 29 => 29
2542 13:53:33.893716 DramcWriteLeveling(PI) end<-----
2543 13:53:33.893827
2544 13:53:33.893908 ==
2545 13:53:33.897248 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 13:53:33.900511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 13:53:33.900590 ==
2548 13:53:33.903796 [Gating] SW mode calibration
2549 13:53:33.910375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2550 13:53:33.917449 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2551 13:53:33.920401 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 13:53:33.923865 0 15 4 | B1->B0 | 2a2a 3333 | 1 1 | (1 1) (1 1)
2553 13:53:33.930539 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 13:53:33.934003 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 13:53:33.937311 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 13:53:33.940514 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 13:53:33.947257 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 13:53:33.950593 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2559 13:53:33.953686 1 0 0 | B1->B0 | 3232 2828 | 0 0 | (0 0) (1 0)
2560 13:53:33.960781 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 13:53:33.963805 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 13:53:33.967241 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 13:53:33.973885 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 13:53:33.977174 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 13:53:33.980414 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 13:53:33.987264 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2567 13:53:33.990443 1 1 0 | B1->B0 | 2b2b 3c3c | 0 1 | (0 0) (0 0)
2568 13:53:33.994046 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2569 13:53:34.000828 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 13:53:34.004293 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 13:53:34.007530 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 13:53:34.014292 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 13:53:34.017391 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 13:53:34.020872 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 13:53:34.027581 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2576 13:53:34.030918 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 13:53:34.033963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 13:53:34.040849 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 13:53:34.044256 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 13:53:34.047515 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 13:53:34.050836 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 13:53:34.057496 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 13:53:34.060772 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 13:53:34.063719 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 13:53:34.070233 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 13:53:34.073868 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 13:53:34.076930 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 13:53:34.083525 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 13:53:34.087216 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 13:53:34.090479 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2591 13:53:34.096934 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2592 13:53:34.097069 Total UI for P1: 0, mck2ui 16
2593 13:53:34.103591 best dqsien dly found for B0: ( 1, 3, 28)
2594 13:53:34.107004 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2595 13:53:34.110136 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 13:53:34.113525 Total UI for P1: 0, mck2ui 16
2597 13:53:34.116998 best dqsien dly found for B1: ( 1, 4, 2)
2598 13:53:34.120553 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2599 13:53:34.123684 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2600 13:53:34.123765
2601 13:53:34.127140 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2602 13:53:34.133973 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2603 13:53:34.134100 [Gating] SW calibration Done
2604 13:53:34.134200 ==
2605 13:53:34.137194 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 13:53:34.143716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 13:53:34.143831 ==
2608 13:53:34.143900 RX Vref Scan: 0
2609 13:53:34.143963
2610 13:53:34.147234 RX Vref 0 -> 0, step: 1
2611 13:53:34.147313
2612 13:53:34.150461 RX Delay -40 -> 252, step: 8
2613 13:53:34.153623 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2614 13:53:34.157185 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2615 13:53:34.160274 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2616 13:53:34.167109 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2617 13:53:34.170231 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2618 13:53:34.173813 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2619 13:53:34.176868 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2620 13:53:34.180082 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2621 13:53:34.183658 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2622 13:53:34.190322 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2623 13:53:34.193465 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2624 13:53:34.197108 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2625 13:53:34.200278 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2626 13:53:34.203466 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2627 13:53:34.210038 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2628 13:53:34.213309 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2629 13:53:34.213393 ==
2630 13:53:34.216616 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 13:53:34.220048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 13:53:34.220134 ==
2633 13:53:34.223169 DQS Delay:
2634 13:53:34.223279 DQS0 = 0, DQS1 = 0
2635 13:53:34.226387 DQM Delay:
2636 13:53:34.226498 DQM0 = 112, DQM1 = 102
2637 13:53:34.226578 DQ Delay:
2638 13:53:34.229661 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2639 13:53:34.233178 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2640 13:53:34.236402 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2641 13:53:34.243124 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2642 13:53:34.243234
2643 13:53:34.243329
2644 13:53:34.243424 ==
2645 13:53:34.246523 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 13:53:34.249845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 13:53:34.249928 ==
2648 13:53:34.250001
2649 13:53:34.250095
2650 13:53:34.253272 TX Vref Scan disable
2651 13:53:34.253377 == TX Byte 0 ==
2652 13:53:34.259962 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2653 13:53:34.263215 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2654 13:53:34.263321 == TX Byte 1 ==
2655 13:53:34.270020 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2656 13:53:34.273189 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2657 13:53:34.273261 ==
2658 13:53:34.276436 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 13:53:34.279755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 13:53:34.279840 ==
2661 13:53:34.292940 TX Vref=22, minBit 4, minWin=25, winSum=417
2662 13:53:34.296255 TX Vref=24, minBit 1, minWin=26, winSum=423
2663 13:53:34.299467 TX Vref=26, minBit 4, minWin=26, winSum=428
2664 13:53:34.302510 TX Vref=28, minBit 1, minWin=27, winSum=440
2665 13:53:34.306005 TX Vref=30, minBit 8, minWin=26, winSum=435
2666 13:53:34.309590 TX Vref=32, minBit 8, minWin=26, winSum=434
2667 13:53:34.316136 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 28
2668 13:53:34.316221
2669 13:53:34.319243 Final TX Range 1 Vref 28
2670 13:53:34.319329
2671 13:53:34.319395 ==
2672 13:53:34.322550 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 13:53:34.326143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 13:53:34.326228 ==
2675 13:53:34.326293
2676 13:53:34.329605
2677 13:53:34.329691 TX Vref Scan disable
2678 13:53:34.332591 == TX Byte 0 ==
2679 13:53:34.336210 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2680 13:53:34.339466 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2681 13:53:34.342515 == TX Byte 1 ==
2682 13:53:34.346005 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2683 13:53:34.349413 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2684 13:53:34.349539
2685 13:53:34.352649 [DATLAT]
2686 13:53:34.352758 Freq=1200, CH0 RK0
2687 13:53:34.352854
2688 13:53:34.355952 DATLAT Default: 0xd
2689 13:53:34.356036 0, 0xFFFF, sum = 0
2690 13:53:34.359599 1, 0xFFFF, sum = 0
2691 13:53:34.359710 2, 0xFFFF, sum = 0
2692 13:53:34.362700 3, 0xFFFF, sum = 0
2693 13:53:34.362785 4, 0xFFFF, sum = 0
2694 13:53:34.366157 5, 0xFFFF, sum = 0
2695 13:53:34.366268 6, 0xFFFF, sum = 0
2696 13:53:34.369235 7, 0xFFFF, sum = 0
2697 13:53:34.369349 8, 0xFFFF, sum = 0
2698 13:53:34.372737 9, 0xFFFF, sum = 0
2699 13:53:34.376269 10, 0xFFFF, sum = 0
2700 13:53:34.376364 11, 0xFFFF, sum = 0
2701 13:53:34.379364 12, 0x0, sum = 1
2702 13:53:34.379475 13, 0x0, sum = 2
2703 13:53:34.379561 14, 0x0, sum = 3
2704 13:53:34.383003 15, 0x0, sum = 4
2705 13:53:34.383109 best_step = 13
2706 13:53:34.383205
2707 13:53:34.386018 ==
2708 13:53:34.386124 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 13:53:34.392671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 13:53:34.392778 ==
2711 13:53:34.392873 RX Vref Scan: 1
2712 13:53:34.392966
2713 13:53:34.395904 Set Vref Range= 32 -> 127
2714 13:53:34.396015
2715 13:53:34.399458 RX Vref 32 -> 127, step: 1
2716 13:53:34.399536
2717 13:53:34.402535 RX Delay -37 -> 252, step: 4
2718 13:53:34.402611
2719 13:53:34.406157 Set Vref, RX VrefLevel [Byte0]: 32
2720 13:53:34.409234 [Byte1]: 32
2721 13:53:34.409317
2722 13:53:34.412809 Set Vref, RX VrefLevel [Byte0]: 33
2723 13:53:34.415886 [Byte1]: 33
2724 13:53:34.415994
2725 13:53:34.419501 Set Vref, RX VrefLevel [Byte0]: 34
2726 13:53:34.422573 [Byte1]: 34
2727 13:53:34.427122
2728 13:53:34.427204 Set Vref, RX VrefLevel [Byte0]: 35
2729 13:53:34.430493 [Byte1]: 35
2730 13:53:34.435170
2731 13:53:34.435281 Set Vref, RX VrefLevel [Byte0]: 36
2732 13:53:34.438353 [Byte1]: 36
2733 13:53:34.443261
2734 13:53:34.443370 Set Vref, RX VrefLevel [Byte0]: 37
2735 13:53:34.446552 [Byte1]: 37
2736 13:53:34.451065
2737 13:53:34.451147 Set Vref, RX VrefLevel [Byte0]: 38
2738 13:53:34.454466 [Byte1]: 38
2739 13:53:34.459286
2740 13:53:34.459392 Set Vref, RX VrefLevel [Byte0]: 39
2741 13:53:34.462537 [Byte1]: 39
2742 13:53:34.467286
2743 13:53:34.467398 Set Vref, RX VrefLevel [Byte0]: 40
2744 13:53:34.470729 [Byte1]: 40
2745 13:53:34.475249
2746 13:53:34.475364 Set Vref, RX VrefLevel [Byte0]: 41
2747 13:53:34.478579 [Byte1]: 41
2748 13:53:34.483281
2749 13:53:34.483388 Set Vref, RX VrefLevel [Byte0]: 42
2750 13:53:34.486477 [Byte1]: 42
2751 13:53:34.491212
2752 13:53:34.491298 Set Vref, RX VrefLevel [Byte0]: 43
2753 13:53:34.494512 [Byte1]: 43
2754 13:53:34.499148
2755 13:53:34.499224 Set Vref, RX VrefLevel [Byte0]: 44
2756 13:53:34.502390 [Byte1]: 44
2757 13:53:34.507136
2758 13:53:34.507235 Set Vref, RX VrefLevel [Byte0]: 45
2759 13:53:34.513495 [Byte1]: 45
2760 13:53:34.513575
2761 13:53:34.516788 Set Vref, RX VrefLevel [Byte0]: 46
2762 13:53:34.520275 [Byte1]: 46
2763 13:53:34.520379
2764 13:53:34.523539 Set Vref, RX VrefLevel [Byte0]: 47
2765 13:53:34.527018 [Byte1]: 47
2766 13:53:34.531254
2767 13:53:34.531329 Set Vref, RX VrefLevel [Byte0]: 48
2768 13:53:34.534543 [Byte1]: 48
2769 13:53:34.539322
2770 13:53:34.539407 Set Vref, RX VrefLevel [Byte0]: 49
2771 13:53:34.542819 [Byte1]: 49
2772 13:53:34.547206
2773 13:53:34.547368 Set Vref, RX VrefLevel [Byte0]: 50
2774 13:53:34.550913 [Byte1]: 50
2775 13:53:34.555483
2776 13:53:34.555665 Set Vref, RX VrefLevel [Byte0]: 51
2777 13:53:34.558771 [Byte1]: 51
2778 13:53:34.563296
2779 13:53:34.563380 Set Vref, RX VrefLevel [Byte0]: 52
2780 13:53:34.566669 [Byte1]: 52
2781 13:53:34.571284
2782 13:53:34.571393 Set Vref, RX VrefLevel [Byte0]: 53
2783 13:53:34.574428 [Byte1]: 53
2784 13:53:34.579195
2785 13:53:34.579304 Set Vref, RX VrefLevel [Byte0]: 54
2786 13:53:34.582491 [Byte1]: 54
2787 13:53:34.587106
2788 13:53:34.587217 Set Vref, RX VrefLevel [Byte0]: 55
2789 13:53:34.590444 [Byte1]: 55
2790 13:53:34.595260
2791 13:53:34.595404 Set Vref, RX VrefLevel [Byte0]: 56
2792 13:53:34.598302 [Byte1]: 56
2793 13:53:34.602966
2794 13:53:34.603109 Set Vref, RX VrefLevel [Byte0]: 57
2795 13:53:34.607007 [Byte1]: 57
2796 13:53:34.611692
2797 13:53:34.612105 Set Vref, RX VrefLevel [Byte0]: 58
2798 13:53:34.615112 [Byte1]: 58
2799 13:53:34.619771
2800 13:53:34.620287 Set Vref, RX VrefLevel [Byte0]: 59
2801 13:53:34.623111 [Byte1]: 59
2802 13:53:34.627474
2803 13:53:34.628075 Set Vref, RX VrefLevel [Byte0]: 60
2804 13:53:34.630899 [Byte1]: 60
2805 13:53:34.635652
2806 13:53:34.636114 Set Vref, RX VrefLevel [Byte0]: 61
2807 13:53:34.638824 [Byte1]: 61
2808 13:53:34.643457
2809 13:53:34.644014 Set Vref, RX VrefLevel [Byte0]: 62
2810 13:53:34.646965 [Byte1]: 62
2811 13:53:34.651444
2812 13:53:34.651863 Set Vref, RX VrefLevel [Byte0]: 63
2813 13:53:34.654659 [Byte1]: 63
2814 13:53:34.659715
2815 13:53:34.660157 Set Vref, RX VrefLevel [Byte0]: 64
2816 13:53:34.662522 [Byte1]: 64
2817 13:53:34.667161
2818 13:53:34.667241 Set Vref, RX VrefLevel [Byte0]: 65
2819 13:53:34.670666 [Byte1]: 65
2820 13:53:34.675279
2821 13:53:34.675360 Set Vref, RX VrefLevel [Byte0]: 66
2822 13:53:34.678527 [Byte1]: 66
2823 13:53:34.683155
2824 13:53:34.683236 Set Vref, RX VrefLevel [Byte0]: 67
2825 13:53:34.686341 [Byte1]: 67
2826 13:53:34.691070
2827 13:53:34.691157 Set Vref, RX VrefLevel [Byte0]: 68
2828 13:53:34.694536 [Byte1]: 68
2829 13:53:34.699243
2830 13:53:34.699337 Set Vref, RX VrefLevel [Byte0]: 69
2831 13:53:34.702344 [Byte1]: 69
2832 13:53:34.707468
2833 13:53:34.707630 Set Vref, RX VrefLevel [Byte0]: 70
2834 13:53:34.710525 [Byte1]: 70
2835 13:53:34.715177
2836 13:53:34.715281 Set Vref, RX VrefLevel [Byte0]: 71
2837 13:53:34.718353 [Byte1]: 71
2838 13:53:34.723037
2839 13:53:34.723139 Set Vref, RX VrefLevel [Byte0]: 72
2840 13:53:34.726545 [Byte1]: 72
2841 13:53:34.731238
2842 13:53:34.731347 Set Vref, RX VrefLevel [Byte0]: 73
2843 13:53:34.734417 [Byte1]: 73
2844 13:53:34.739345
2845 13:53:34.739426 Set Vref, RX VrefLevel [Byte0]: 74
2846 13:53:34.742497 [Byte1]: 74
2847 13:53:34.749413
2848 13:53:34.749546 Set Vref, RX VrefLevel [Byte0]: 75
2849 13:53:34.750415 [Byte1]: 75
2850 13:53:34.755169
2851 13:53:34.755314 Final RX Vref Byte 0 = 61 to rank0
2852 13:53:34.758826 Final RX Vref Byte 1 = 47 to rank0
2853 13:53:34.762339 Final RX Vref Byte 0 = 61 to rank1
2854 13:53:34.765360 Final RX Vref Byte 1 = 47 to rank1==
2855 13:53:34.768954 Dram Type= 6, Freq= 0, CH_0, rank 0
2856 13:53:34.775132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 13:53:34.775305 ==
2858 13:53:34.775432 DQS Delay:
2859 13:53:34.775615 DQS0 = 0, DQS1 = 0
2860 13:53:34.778643 DQM Delay:
2861 13:53:34.778874 DQM0 = 111, DQM1 = 99
2862 13:53:34.782284 DQ Delay:
2863 13:53:34.785281 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2864 13:53:34.788888 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2865 13:53:34.791970 DQ8 =90, DQ9 =84, DQ10 =100, DQ11 =90
2866 13:53:34.795564 DQ12 =106, DQ13 =106, DQ14 =112, DQ15 =108
2867 13:53:34.795765
2868 13:53:34.795920
2869 13:53:34.802084 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2870 13:53:34.806078 CH0 RK0: MR19=303, MR18=FBFA
2871 13:53:34.812260 CH0_RK0: MR19=0x303, MR18=0xFBFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2872 13:53:34.812461
2873 13:53:34.815394 ----->DramcWriteLeveling(PI) begin...
2874 13:53:34.815596 ==
2875 13:53:34.818708 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 13:53:34.822158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 13:53:34.822386 ==
2878 13:53:34.825262 Write leveling (Byte 0): 32 => 32
2879 13:53:34.828497 Write leveling (Byte 1): 29 => 29
2880 13:53:34.831862 DramcWriteLeveling(PI) end<-----
2881 13:53:34.831944
2882 13:53:34.832006 ==
2883 13:53:34.834919 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 13:53:34.841756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 13:53:34.841864 ==
2886 13:53:34.841962 [Gating] SW mode calibration
2887 13:53:34.851942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2888 13:53:34.855046 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2889 13:53:34.858666 0 15 0 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
2890 13:53:34.865183 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 13:53:34.868453 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 13:53:34.871953 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 13:53:34.878386 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 13:53:34.881870 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 13:53:34.885227 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2896 13:53:34.891705 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2897 13:53:34.895046 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2898 13:53:34.898536 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 13:53:34.905246 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 13:53:34.908598 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 13:53:34.911956 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 13:53:34.918382 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 13:53:34.922127 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2904 13:53:34.925037 1 0 28 | B1->B0 | 2424 4444 | 1 0 | (0 0) (0 0)
2905 13:53:34.931663 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2906 13:53:34.935069 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 13:53:34.938474 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 13:53:34.942021 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 13:53:34.948402 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 13:53:34.951960 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 13:53:34.955217 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2912 13:53:34.962149 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2913 13:53:34.965302 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2914 13:53:34.968725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 13:53:34.975124 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 13:53:34.978341 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 13:53:34.981422 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 13:53:34.988331 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 13:53:34.991412 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 13:53:34.994834 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 13:53:35.001665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 13:53:35.004795 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 13:53:35.008204 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 13:53:35.014887 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 13:53:35.018175 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 13:53:35.021665 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 13:53:35.028092 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 13:53:35.031400 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2929 13:53:35.034749 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 13:53:35.038120 Total UI for P1: 0, mck2ui 16
2931 13:53:35.041535 best dqsien dly found for B0: ( 1, 3, 28)
2932 13:53:35.044791 Total UI for P1: 0, mck2ui 16
2933 13:53:35.048458 best dqsien dly found for B1: ( 1, 3, 28)
2934 13:53:35.051748 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2935 13:53:35.054897 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2936 13:53:35.054998
2937 13:53:35.058321 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2938 13:53:35.061744 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2939 13:53:35.064881 [Gating] SW calibration Done
2940 13:53:35.064978 ==
2941 13:53:35.068710 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 13:53:35.074972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 13:53:35.075048 ==
2944 13:53:35.075116 RX Vref Scan: 0
2945 13:53:35.075183
2946 13:53:35.078520 RX Vref 0 -> 0, step: 1
2947 13:53:35.078614
2948 13:53:35.081646 RX Delay -40 -> 252, step: 8
2949 13:53:35.085216 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2950 13:53:35.088549 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2951 13:53:35.091875 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2952 13:53:35.095242 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2953 13:53:35.101621 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2954 13:53:35.104789 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2955 13:53:35.108138 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2956 13:53:35.111501 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2957 13:53:35.115060 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2958 13:53:35.121617 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2959 13:53:35.124852 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2960 13:53:35.128434 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2961 13:53:35.131568 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2962 13:53:35.134937 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2963 13:53:35.141778 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2964 13:53:35.145045 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2965 13:53:35.145118 ==
2966 13:53:35.148554 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 13:53:35.151721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 13:53:35.151788 ==
2969 13:53:35.151846 DQS Delay:
2970 13:53:35.155048 DQS0 = 0, DQS1 = 0
2971 13:53:35.155140 DQM Delay:
2972 13:53:35.158300 DQM0 = 111, DQM1 = 100
2973 13:53:35.158373 DQ Delay:
2974 13:53:35.161694 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2975 13:53:35.164802 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2976 13:53:35.168333 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =91
2977 13:53:35.171632 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2978 13:53:35.171700
2979 13:53:35.171759
2980 13:53:35.174938 ==
2981 13:53:35.178149 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 13:53:35.181599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 13:53:35.181672 ==
2984 13:53:35.181739
2985 13:53:35.181806
2986 13:53:35.184889 TX Vref Scan disable
2987 13:53:35.184985 == TX Byte 0 ==
2988 13:53:35.188141 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2989 13:53:35.194837 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2990 13:53:35.194939 == TX Byte 1 ==
2991 13:53:35.198156 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2992 13:53:35.204752 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2993 13:53:35.204849 ==
2994 13:53:35.208389 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 13:53:35.211438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 13:53:35.211507 ==
2997 13:53:35.224117 TX Vref=22, minBit 1, minWin=26, winSum=427
2998 13:53:35.227707 TX Vref=24, minBit 1, minWin=26, winSum=433
2999 13:53:35.230614 TX Vref=26, minBit 0, minWin=27, winSum=438
3000 13:53:35.234244 TX Vref=28, minBit 1, minWin=27, winSum=438
3001 13:53:35.237112 TX Vref=30, minBit 5, minWin=27, winSum=444
3002 13:53:35.243846 TX Vref=32, minBit 10, minWin=26, winSum=442
3003 13:53:35.247307 [TxChooseVref] Worse bit 5, Min win 27, Win sum 444, Final Vref 30
3004 13:53:35.247464
3005 13:53:35.250350 Final TX Range 1 Vref 30
3006 13:53:35.250498
3007 13:53:35.250601 ==
3008 13:53:35.253838 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 13:53:35.256916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 13:53:35.257016 ==
3011 13:53:35.260082
3012 13:53:35.260195
3013 13:53:35.260294 TX Vref Scan disable
3014 13:53:35.263709 == TX Byte 0 ==
3015 13:53:35.267170 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3016 13:53:35.270527 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3017 13:53:35.273702 == TX Byte 1 ==
3018 13:53:35.276901 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3019 13:53:35.280270 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3020 13:53:35.283714
3021 13:53:35.283883 [DATLAT]
3022 13:53:35.284046 Freq=1200, CH0 RK1
3023 13:53:35.284201
3024 13:53:35.286798 DATLAT Default: 0xd
3025 13:53:35.287009 0, 0xFFFF, sum = 0
3026 13:53:35.290573 1, 0xFFFF, sum = 0
3027 13:53:35.290797 2, 0xFFFF, sum = 0
3028 13:53:35.293646 3, 0xFFFF, sum = 0
3029 13:53:35.293875 4, 0xFFFF, sum = 0
3030 13:53:35.297136 5, 0xFFFF, sum = 0
3031 13:53:35.300547 6, 0xFFFF, sum = 0
3032 13:53:35.300810 7, 0xFFFF, sum = 0
3033 13:53:35.304187 8, 0xFFFF, sum = 0
3034 13:53:35.304425 9, 0xFFFF, sum = 0
3035 13:53:35.307427 10, 0xFFFF, sum = 0
3036 13:53:35.307667 11, 0xFFFF, sum = 0
3037 13:53:35.310613 12, 0x0, sum = 1
3038 13:53:35.310926 13, 0x0, sum = 2
3039 13:53:35.314021 14, 0x0, sum = 3
3040 13:53:35.314329 15, 0x0, sum = 4
3041 13:53:35.314596 best_step = 13
3042 13:53:35.314834
3043 13:53:35.317427 ==
3044 13:53:35.320589 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 13:53:35.324089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 13:53:35.324665 ==
3047 13:53:35.325137 RX Vref Scan: 0
3048 13:53:35.325617
3049 13:53:35.327494 RX Vref 0 -> 0, step: 1
3050 13:53:35.328040
3051 13:53:35.330758 RX Delay -37 -> 252, step: 4
3052 13:53:35.333942 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3053 13:53:35.340704 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3054 13:53:35.343891 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3055 13:53:35.347189 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3056 13:53:35.350470 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3057 13:53:35.354184 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3058 13:53:35.360712 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3059 13:53:35.363878 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3060 13:53:35.367088 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3061 13:53:35.370592 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3062 13:53:35.373930 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3063 13:53:35.377394 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3064 13:53:35.383947 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3065 13:53:35.387070 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3066 13:53:35.390754 iDelay=195, Bit 14, Center 110 (43 ~ 178) 136
3067 13:53:35.394096 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3068 13:53:35.394488 ==
3069 13:53:35.397279 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 13:53:35.404172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 13:53:35.404562 ==
3072 13:53:35.404865 DQS Delay:
3073 13:53:35.407467 DQS0 = 0, DQS1 = 0
3074 13:53:35.407852 DQM Delay:
3075 13:53:35.408154 DQM0 = 110, DQM1 = 99
3076 13:53:35.410769 DQ Delay:
3077 13:53:35.413878 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3078 13:53:35.417391 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3079 13:53:35.420667 DQ8 =88, DQ9 =82, DQ10 =100, DQ11 =90
3080 13:53:35.424252 DQ12 =108, DQ13 =108, DQ14 =110, DQ15 =108
3081 13:53:35.424638
3082 13:53:35.424935
3083 13:53:35.431014 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3084 13:53:35.434103 CH0 RK1: MR19=403, MR18=10F8
3085 13:53:35.440734 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3086 13:53:35.444037 [RxdqsGatingPostProcess] freq 1200
3087 13:53:35.451121 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3088 13:53:35.454432 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 13:53:35.454954 best DQS1 dly(2T, 0.5T) = (0, 12)
3090 13:53:35.457684 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 13:53:35.461195 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3092 13:53:35.464623 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 13:53:35.467801 best DQS1 dly(2T, 0.5T) = (0, 11)
3094 13:53:35.470566 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 13:53:35.474336 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3096 13:53:35.477207 Pre-setting of DQS Precalculation
3097 13:53:35.484335 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3098 13:53:35.484749 ==
3099 13:53:35.487566 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 13:53:35.491065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 13:53:35.491540 ==
3102 13:53:35.497532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 13:53:35.501188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3104 13:53:35.510864 [CA 0] Center 37 (7~67) winsize 61
3105 13:53:35.513880 [CA 1] Center 37 (7~68) winsize 62
3106 13:53:35.517621 [CA 2] Center 34 (5~64) winsize 60
3107 13:53:35.520303 [CA 3] Center 33 (3~64) winsize 62
3108 13:53:35.523590 [CA 4] Center 34 (4~64) winsize 61
3109 13:53:35.527120 [CA 5] Center 33 (3~63) winsize 61
3110 13:53:35.527577
3111 13:53:35.530299 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3112 13:53:35.530718
3113 13:53:35.534072 [CATrainingPosCal] consider 1 rank data
3114 13:53:35.537071 u2DelayCellTimex100 = 270/100 ps
3115 13:53:35.540812 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3116 13:53:35.544044 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3117 13:53:35.547596 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3118 13:53:35.554142 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3119 13:53:35.557470 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 13:53:35.560862 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3121 13:53:35.561421
3122 13:53:35.564151 CA PerBit enable=1, Macro0, CA PI delay=33
3123 13:53:35.564711
3124 13:53:35.567395 [CBTSetCACLKResult] CA Dly = 33
3125 13:53:35.567952 CS Dly: 5 (0~36)
3126 13:53:35.568319 ==
3127 13:53:35.570707 Dram Type= 6, Freq= 0, CH_1, rank 1
3128 13:53:35.577640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 13:53:35.578204 ==
3130 13:53:35.580653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 13:53:35.587144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3132 13:53:35.596194 [CA 0] Center 37 (8~67) winsize 60
3133 13:53:35.599616 [CA 1] Center 37 (7~68) winsize 62
3134 13:53:35.602863 [CA 2] Center 34 (4~65) winsize 62
3135 13:53:35.606133 [CA 3] Center 33 (3~64) winsize 62
3136 13:53:35.609632 [CA 4] Center 34 (4~65) winsize 62
3137 13:53:35.612545 [CA 5] Center 32 (2~63) winsize 62
3138 13:53:35.613110
3139 13:53:35.615932 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3140 13:53:35.616498
3141 13:53:35.619348 [CATrainingPosCal] consider 2 rank data
3142 13:53:35.622700 u2DelayCellTimex100 = 270/100 ps
3143 13:53:35.626399 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3144 13:53:35.629719 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3145 13:53:35.633057 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3146 13:53:35.639349 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3147 13:53:35.643234 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 13:53:35.646010 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3149 13:53:35.646470
3150 13:53:35.649371 CA PerBit enable=1, Macro0, CA PI delay=33
3151 13:53:35.649871
3152 13:53:35.653269 [CBTSetCACLKResult] CA Dly = 33
3153 13:53:35.653889 CS Dly: 6 (0~39)
3154 13:53:35.654255
3155 13:53:35.656493 ----->DramcWriteLeveling(PI) begin...
3156 13:53:35.657063 ==
3157 13:53:35.659716 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 13:53:35.666492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 13:53:35.667058 ==
3160 13:53:35.669692 Write leveling (Byte 0): 25 => 25
3161 13:53:35.672798 Write leveling (Byte 1): 29 => 29
3162 13:53:35.673336 DramcWriteLeveling(PI) end<-----
3163 13:53:35.676411
3164 13:53:35.676963 ==
3165 13:53:35.679692 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 13:53:35.682955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 13:53:35.683420 ==
3168 13:53:35.686145 [Gating] SW mode calibration
3169 13:53:35.692971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3170 13:53:35.696205 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3171 13:53:35.702532 0 15 0 | B1->B0 | 2e2e 2a29 | 1 1 | (1 1) (0 0)
3172 13:53:35.706122 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 13:53:35.709399 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 13:53:35.716388 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 13:53:35.720006 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 13:53:35.723001 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 13:53:35.729947 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 13:53:35.733058 0 15 28 | B1->B0 | 2b2b 2c2c | 0 0 | (0 1) (0 0)
3179 13:53:35.736593 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3180 13:53:35.743054 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 13:53:35.746116 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 13:53:35.749301 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 13:53:35.756199 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 13:53:35.760030 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 13:53:35.762915 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3186 13:53:35.766385 1 0 28 | B1->B0 | 4141 4141 | 0 0 | (0 0) (0 0)
3187 13:53:35.773323 1 1 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
3188 13:53:35.776216 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 13:53:35.779605 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 13:53:35.786038 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 13:53:35.789385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 13:53:35.792852 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 13:53:35.799979 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 13:53:35.803093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3195 13:53:35.806067 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3196 13:53:35.813021 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 13:53:35.816007 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 13:53:35.819808 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 13:53:35.826345 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 13:53:35.829559 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 13:53:35.832903 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 13:53:35.839587 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 13:53:35.843046 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 13:53:35.846296 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 13:53:35.852998 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 13:53:35.856369 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 13:53:35.859881 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 13:53:35.866097 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 13:53:35.869667 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 13:53:35.872880 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3211 13:53:35.876277 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3212 13:53:35.879510 Total UI for P1: 0, mck2ui 16
3213 13:53:35.882561 best dqsien dly found for B1: ( 1, 3, 28)
3214 13:53:35.889031 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 13:53:35.893041 Total UI for P1: 0, mck2ui 16
3216 13:53:35.896025 best dqsien dly found for B0: ( 1, 3, 30)
3217 13:53:35.899676 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3218 13:53:35.902562 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3219 13:53:35.902975
3220 13:53:35.906215 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3221 13:53:35.909128 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3222 13:53:35.912873 [Gating] SW calibration Done
3223 13:53:35.913389 ==
3224 13:53:35.916210 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 13:53:35.919444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 13:53:35.919986 ==
3227 13:53:35.922611 RX Vref Scan: 0
3228 13:53:35.923121
3229 13:53:35.923448 RX Vref 0 -> 0, step: 1
3230 13:53:35.926408
3231 13:53:35.926920 RX Delay -40 -> 252, step: 8
3232 13:53:35.932740 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3233 13:53:35.935869 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3234 13:53:35.939139 iDelay=208, Bit 2, Center 99 (24 ~ 175) 152
3235 13:53:35.942719 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3236 13:53:35.946336 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3237 13:53:35.949948 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3238 13:53:35.956556 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3239 13:53:35.959857 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3240 13:53:35.962886 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3241 13:53:35.966426 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3242 13:53:35.969312 iDelay=208, Bit 10, Center 103 (32 ~ 175) 144
3243 13:53:35.976324 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3244 13:53:35.979684 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3245 13:53:35.982695 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3246 13:53:35.986203 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3247 13:53:35.989598 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3248 13:53:35.990062 ==
3249 13:53:35.992863 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 13:53:35.999641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 13:53:36.000165 ==
3252 13:53:36.000501 DQS Delay:
3253 13:53:36.002483 DQS0 = 0, DQS1 = 0
3254 13:53:36.002897 DQM Delay:
3255 13:53:36.005829 DQM0 = 115, DQM1 = 106
3256 13:53:36.006246 DQ Delay:
3257 13:53:36.009200 DQ0 =123, DQ1 =107, DQ2 =99, DQ3 =115
3258 13:53:36.012407 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3259 13:53:36.016227 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3260 13:53:36.019609 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =115
3261 13:53:36.020132
3262 13:53:36.020462
3263 13:53:36.020768 ==
3264 13:53:36.022722 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 13:53:36.029177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 13:53:36.029740 ==
3267 13:53:36.030082
3268 13:53:36.030385
3269 13:53:36.030674 TX Vref Scan disable
3270 13:53:36.032576 == TX Byte 0 ==
3271 13:53:36.035707 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3272 13:53:36.042163 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3273 13:53:36.042614 == TX Byte 1 ==
3274 13:53:36.045656 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3275 13:53:36.052532 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3276 13:53:36.053055 ==
3277 13:53:36.055922 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 13:53:36.058916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 13:53:36.059336 ==
3280 13:53:36.070815 TX Vref=22, minBit 11, minWin=24, winSum=410
3281 13:53:36.073971 TX Vref=24, minBit 8, minWin=25, winSum=416
3282 13:53:36.077578 TX Vref=26, minBit 8, minWin=25, winSum=423
3283 13:53:36.080677 TX Vref=28, minBit 9, minWin=25, winSum=424
3284 13:53:36.083938 TX Vref=30, minBit 9, minWin=25, winSum=427
3285 13:53:36.090452 TX Vref=32, minBit 8, minWin=25, winSum=421
3286 13:53:36.093644 [TxChooseVref] Worse bit 9, Min win 25, Win sum 427, Final Vref 30
3287 13:53:36.094063
3288 13:53:36.097324 Final TX Range 1 Vref 30
3289 13:53:36.097903
3290 13:53:36.098236 ==
3291 13:53:36.100705 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 13:53:36.103784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 13:53:36.104357 ==
3294 13:53:36.106888
3295 13:53:36.107300
3296 13:53:36.107627 TX Vref Scan disable
3297 13:53:36.110130 == TX Byte 0 ==
3298 13:53:36.113411 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3299 13:53:36.117041 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3300 13:53:36.120662 == TX Byte 1 ==
3301 13:53:36.123704 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3302 13:53:36.126907 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3303 13:53:36.130219
3304 13:53:36.130648 [DATLAT]
3305 13:53:36.130977 Freq=1200, CH1 RK0
3306 13:53:36.131282
3307 13:53:36.133580 DATLAT Default: 0xd
3308 13:53:36.133994 0, 0xFFFF, sum = 0
3309 13:53:36.136708 1, 0xFFFF, sum = 0
3310 13:53:36.137177 2, 0xFFFF, sum = 0
3311 13:53:36.140136 3, 0xFFFF, sum = 0
3312 13:53:36.140632 4, 0xFFFF, sum = 0
3313 13:53:36.143317 5, 0xFFFF, sum = 0
3314 13:53:36.146663 6, 0xFFFF, sum = 0
3315 13:53:36.147081 7, 0xFFFF, sum = 0
3316 13:53:36.150031 8, 0xFFFF, sum = 0
3317 13:53:36.150469 9, 0xFFFF, sum = 0
3318 13:53:36.153194 10, 0xFFFF, sum = 0
3319 13:53:36.153659 11, 0xFFFF, sum = 0
3320 13:53:36.156956 12, 0x0, sum = 1
3321 13:53:36.157389 13, 0x0, sum = 2
3322 13:53:36.160425 14, 0x0, sum = 3
3323 13:53:36.160946 15, 0x0, sum = 4
3324 13:53:36.161275 best_step = 13
3325 13:53:36.163840
3326 13:53:36.164352 ==
3327 13:53:36.166605 Dram Type= 6, Freq= 0, CH_1, rank 0
3328 13:53:36.170004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3329 13:53:36.170419 ==
3330 13:53:36.170743 RX Vref Scan: 1
3331 13:53:36.171046
3332 13:53:36.173902 Set Vref Range= 32 -> 127
3333 13:53:36.174416
3334 13:53:36.176568 RX Vref 32 -> 127, step: 1
3335 13:53:36.176980
3336 13:53:36.180626 RX Delay -21 -> 252, step: 4
3337 13:53:36.181140
3338 13:53:36.183520 Set Vref, RX VrefLevel [Byte0]: 32
3339 13:53:36.187240 [Byte1]: 32
3340 13:53:36.187651
3341 13:53:36.190207 Set Vref, RX VrefLevel [Byte0]: 33
3342 13:53:36.193791 [Byte1]: 33
3343 13:53:36.194205
3344 13:53:36.196713 Set Vref, RX VrefLevel [Byte0]: 34
3345 13:53:36.200770 [Byte1]: 34
3346 13:53:36.205083
3347 13:53:36.205648 Set Vref, RX VrefLevel [Byte0]: 35
3348 13:53:36.208287 [Byte1]: 35
3349 13:53:36.212954
3350 13:53:36.213529 Set Vref, RX VrefLevel [Byte0]: 36
3351 13:53:36.216121 [Byte1]: 36
3352 13:53:36.220649
3353 13:53:36.221162 Set Vref, RX VrefLevel [Byte0]: 37
3354 13:53:36.224256 [Byte1]: 37
3355 13:53:36.228666
3356 13:53:36.229202 Set Vref, RX VrefLevel [Byte0]: 38
3357 13:53:36.231754 [Byte1]: 38
3358 13:53:36.236494
3359 13:53:36.237004 Set Vref, RX VrefLevel [Byte0]: 39
3360 13:53:36.239677 [Byte1]: 39
3361 13:53:36.244239
3362 13:53:36.244753 Set Vref, RX VrefLevel [Byte0]: 40
3363 13:53:36.247641 [Byte1]: 40
3364 13:53:36.252290
3365 13:53:36.252804 Set Vref, RX VrefLevel [Byte0]: 41
3366 13:53:36.255695 [Byte1]: 41
3367 13:53:36.260481
3368 13:53:36.263667 Set Vref, RX VrefLevel [Byte0]: 42
3369 13:53:36.266392 [Byte1]: 42
3370 13:53:36.266912
3371 13:53:36.270079 Set Vref, RX VrefLevel [Byte0]: 43
3372 13:53:36.273622 [Byte1]: 43
3373 13:53:36.274131
3374 13:53:36.276592 Set Vref, RX VrefLevel [Byte0]: 44
3375 13:53:36.279817 [Byte1]: 44
3376 13:53:36.283633
3377 13:53:36.284088 Set Vref, RX VrefLevel [Byte0]: 45
3378 13:53:36.287060 [Byte1]: 45
3379 13:53:36.291419
3380 13:53:36.291830 Set Vref, RX VrefLevel [Byte0]: 46
3381 13:53:36.294692 [Byte1]: 46
3382 13:53:36.299170
3383 13:53:36.299315 Set Vref, RX VrefLevel [Byte0]: 47
3384 13:53:36.302714 [Byte1]: 47
3385 13:53:36.307584
3386 13:53:36.307753 Set Vref, RX VrefLevel [Byte0]: 48
3387 13:53:36.310806 [Byte1]: 48
3388 13:53:36.315257
3389 13:53:36.315438 Set Vref, RX VrefLevel [Byte0]: 49
3390 13:53:36.318635 [Byte1]: 49
3391 13:53:36.323371
3392 13:53:36.323571 Set Vref, RX VrefLevel [Byte0]: 50
3393 13:53:36.326689 [Byte1]: 50
3394 13:53:36.331155
3395 13:53:36.331381 Set Vref, RX VrefLevel [Byte0]: 51
3396 13:53:36.334345 [Byte1]: 51
3397 13:53:36.338904
3398 13:53:36.339163 Set Vref, RX VrefLevel [Byte0]: 52
3399 13:53:36.342389 [Byte1]: 52
3400 13:53:36.347261
3401 13:53:36.347548 Set Vref, RX VrefLevel [Byte0]: 53
3402 13:53:36.350092 [Byte1]: 53
3403 13:53:36.355351
3404 13:53:36.355749 Set Vref, RX VrefLevel [Byte0]: 54
3405 13:53:36.358152 [Byte1]: 54
3406 13:53:36.363195
3407 13:53:36.363695 Set Vref, RX VrefLevel [Byte0]: 55
3408 13:53:36.366815 [Byte1]: 55
3409 13:53:36.371417
3410 13:53:36.371961 Set Vref, RX VrefLevel [Byte0]: 56
3411 13:53:36.374396 [Byte1]: 56
3412 13:53:36.379131
3413 13:53:36.379680 Set Vref, RX VrefLevel [Byte0]: 57
3414 13:53:36.382229 [Byte1]: 57
3415 13:53:36.386879
3416 13:53:36.387428 Set Vref, RX VrefLevel [Byte0]: 58
3417 13:53:36.389914 [Byte1]: 58
3418 13:53:36.394795
3419 13:53:36.395216 Set Vref, RX VrefLevel [Byte0]: 59
3420 13:53:36.397860 [Byte1]: 59
3421 13:53:36.402294
3422 13:53:36.402716 Set Vref, RX VrefLevel [Byte0]: 60
3423 13:53:36.405989 [Byte1]: 60
3424 13:53:36.410444
3425 13:53:36.410861 Set Vref, RX VrefLevel [Byte0]: 61
3426 13:53:36.413598 [Byte1]: 61
3427 13:53:36.418379
3428 13:53:36.418799 Set Vref, RX VrefLevel [Byte0]: 62
3429 13:53:36.421522 [Byte1]: 62
3430 13:53:36.426196
3431 13:53:36.426617 Set Vref, RX VrefLevel [Byte0]: 63
3432 13:53:36.429676 [Byte1]: 63
3433 13:53:36.434317
3434 13:53:36.434734 Set Vref, RX VrefLevel [Byte0]: 64
3435 13:53:36.437414 [Byte1]: 64
3436 13:53:36.442368
3437 13:53:36.442812 Final RX Vref Byte 0 = 52 to rank0
3438 13:53:36.445410 Final RX Vref Byte 1 = 50 to rank0
3439 13:53:36.448817 Final RX Vref Byte 0 = 52 to rank1
3440 13:53:36.451897 Final RX Vref Byte 1 = 50 to rank1==
3441 13:53:36.455554 Dram Type= 6, Freq= 0, CH_1, rank 0
3442 13:53:36.462470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 13:53:36.462997 ==
3444 13:53:36.463410 DQS Delay:
3445 13:53:36.463729 DQS0 = 0, DQS1 = 0
3446 13:53:36.465585 DQM Delay:
3447 13:53:36.466005 DQM0 = 113, DQM1 = 106
3448 13:53:36.469054 DQ Delay:
3449 13:53:36.472466 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =110
3450 13:53:36.475924 DQ4 =108, DQ5 =122, DQ6 =126, DQ7 =110
3451 13:53:36.479001 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3452 13:53:36.482426 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =114
3453 13:53:36.482954
3454 13:53:36.483288
3455 13:53:36.488946 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3456 13:53:36.492519 CH1 RK0: MR19=303, MR18=F2F9
3457 13:53:36.498664 CH1_RK0: MR19=0x303, MR18=0xF2F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3458 13:53:36.499087
3459 13:53:36.502457 ----->DramcWriteLeveling(PI) begin...
3460 13:53:36.502977 ==
3461 13:53:36.505555 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 13:53:36.509002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 13:53:36.512528 ==
3464 13:53:36.513045 Write leveling (Byte 0): 24 => 24
3465 13:53:36.515886 Write leveling (Byte 1): 26 => 26
3466 13:53:36.519137 DramcWriteLeveling(PI) end<-----
3467 13:53:36.519649
3468 13:53:36.519983 ==
3469 13:53:36.522044 Dram Type= 6, Freq= 0, CH_1, rank 1
3470 13:53:36.529349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 13:53:36.529913 ==
3472 13:53:36.530251 [Gating] SW mode calibration
3473 13:53:36.539005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3474 13:53:36.542333 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3475 13:53:36.545628 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 13:53:36.552455 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 13:53:36.555587 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 13:53:36.558821 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 13:53:36.565851 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 13:53:36.568914 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 13:53:36.572442 0 15 24 | B1->B0 | 3434 2727 | 0 0 | (0 1) (1 0)
3482 13:53:36.578817 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3483 13:53:36.582209 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 13:53:36.585724 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 13:53:36.592493 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 13:53:36.595872 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 13:53:36.598653 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 13:53:36.605638 1 0 20 | B1->B0 | 2424 2928 | 1 1 | (0 0) (0 0)
3489 13:53:36.608844 1 0 24 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
3490 13:53:36.612320 1 0 28 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
3491 13:53:36.618900 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 13:53:36.622201 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 13:53:36.625595 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 13:53:36.632276 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 13:53:36.635462 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 13:53:36.638820 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 13:53:36.645388 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3498 13:53:36.648863 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3499 13:53:36.651849 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 13:53:36.658520 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 13:53:36.662019 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 13:53:36.665238 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 13:53:36.668784 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 13:53:36.675210 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 13:53:36.678864 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 13:53:36.682359 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 13:53:36.688809 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 13:53:36.691693 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 13:53:36.695297 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 13:53:36.701793 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 13:53:36.705170 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 13:53:36.708638 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3513 13:53:36.714706 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3514 13:53:36.718768 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3515 13:53:36.721847 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 13:53:36.725130 Total UI for P1: 0, mck2ui 16
3517 13:53:36.728078 best dqsien dly found for B0: ( 1, 3, 24)
3518 13:53:36.731696 Total UI for P1: 0, mck2ui 16
3519 13:53:36.735362 best dqsien dly found for B1: ( 1, 3, 26)
3520 13:53:36.738243 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3521 13:53:36.741334 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3522 13:53:36.741796
3523 13:53:36.748359 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3524 13:53:36.751990 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3525 13:53:36.754626 [Gating] SW calibration Done
3526 13:53:36.755149 ==
3527 13:53:36.758417 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 13:53:36.761692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 13:53:36.762267 ==
3530 13:53:36.762778 RX Vref Scan: 0
3531 13:53:36.763121
3532 13:53:36.764949 RX Vref 0 -> 0, step: 1
3533 13:53:36.765506
3534 13:53:36.767734 RX Delay -40 -> 252, step: 8
3535 13:53:36.771524 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3536 13:53:36.774901 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3537 13:53:36.781423 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3538 13:53:36.784693 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3539 13:53:36.788346 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3540 13:53:36.791305 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3541 13:53:36.794499 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3542 13:53:36.801441 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3543 13:53:36.804393 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3544 13:53:36.807657 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3545 13:53:36.811106 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3546 13:53:36.814561 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3547 13:53:36.818130 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3548 13:53:36.824161 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3549 13:53:36.827846 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3550 13:53:36.831398 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3551 13:53:36.831912 ==
3552 13:53:36.834414 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 13:53:36.838071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 13:53:36.840933 ==
3555 13:53:36.841367 DQS Delay:
3556 13:53:36.841743 DQS0 = 0, DQS1 = 0
3557 13:53:36.844343 DQM Delay:
3558 13:53:36.844850 DQM0 = 110, DQM1 = 107
3559 13:53:36.847911 DQ Delay:
3560 13:53:36.851055 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3561 13:53:36.854277 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3562 13:53:36.857802 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3563 13:53:36.860744 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3564 13:53:36.861257
3565 13:53:36.861611
3566 13:53:36.861919 ==
3567 13:53:36.864497 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 13:53:36.867238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 13:53:36.867661 ==
3570 13:53:36.867993
3571 13:53:36.870465
3572 13:53:36.870981 TX Vref Scan disable
3573 13:53:36.873835 == TX Byte 0 ==
3574 13:53:36.877551 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3575 13:53:36.880771 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3576 13:53:36.883795 == TX Byte 1 ==
3577 13:53:36.886921 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3578 13:53:36.890319 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3579 13:53:36.890782 ==
3580 13:53:36.893555 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 13:53:36.900395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 13:53:36.900914 ==
3583 13:53:36.911267 TX Vref=22, minBit 3, minWin=25, winSum=417
3584 13:53:36.914077 TX Vref=24, minBit 0, minWin=25, winSum=422
3585 13:53:36.917554 TX Vref=26, minBit 0, minWin=26, winSum=428
3586 13:53:36.920656 TX Vref=28, minBit 1, minWin=26, winSum=432
3587 13:53:36.924233 TX Vref=30, minBit 10, minWin=26, winSum=435
3588 13:53:36.930755 TX Vref=32, minBit 8, minWin=26, winSum=426
3589 13:53:36.934137 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
3590 13:53:36.934556
3591 13:53:36.937653 Final TX Range 1 Vref 30
3592 13:53:36.938179
3593 13:53:36.938512 ==
3594 13:53:36.940839 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 13:53:36.944329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 13:53:36.947500 ==
3597 13:53:36.948022
3598 13:53:36.948354
3599 13:53:36.948657 TX Vref Scan disable
3600 13:53:36.951073 == TX Byte 0 ==
3601 13:53:36.954421 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3602 13:53:36.957804 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3603 13:53:36.960635 == TX Byte 1 ==
3604 13:53:36.964118 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3605 13:53:36.967551 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3606 13:53:36.970613
3607 13:53:36.971029 [DATLAT]
3608 13:53:36.971355 Freq=1200, CH1 RK1
3609 13:53:36.971663
3610 13:53:36.974018 DATLAT Default: 0xd
3611 13:53:36.974435 0, 0xFFFF, sum = 0
3612 13:53:36.977510 1, 0xFFFF, sum = 0
3613 13:53:36.977936 2, 0xFFFF, sum = 0
3614 13:53:36.980729 3, 0xFFFF, sum = 0
3615 13:53:36.984127 4, 0xFFFF, sum = 0
3616 13:53:36.984548 5, 0xFFFF, sum = 0
3617 13:53:36.987544 6, 0xFFFF, sum = 0
3618 13:53:36.987967 7, 0xFFFF, sum = 0
3619 13:53:36.990662 8, 0xFFFF, sum = 0
3620 13:53:36.991082 9, 0xFFFF, sum = 0
3621 13:53:36.993912 10, 0xFFFF, sum = 0
3622 13:53:36.994336 11, 0xFFFF, sum = 0
3623 13:53:36.997558 12, 0x0, sum = 1
3624 13:53:36.997982 13, 0x0, sum = 2
3625 13:53:37.000716 14, 0x0, sum = 3
3626 13:53:37.001157 15, 0x0, sum = 4
3627 13:53:37.001536 best_step = 13
3628 13:53:37.004168
3629 13:53:37.004598 ==
3630 13:53:37.007558 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 13:53:37.010698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 13:53:37.011135 ==
3633 13:53:37.011561 RX Vref Scan: 0
3634 13:53:37.012077
3635 13:53:37.013978 RX Vref 0 -> 0, step: 1
3636 13:53:37.014396
3637 13:53:37.017154 RX Delay -21 -> 252, step: 4
3638 13:53:37.020702 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3639 13:53:37.027492 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3640 13:53:37.030554 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3641 13:53:37.034257 iDelay=195, Bit 3, Center 106 (35 ~ 178) 144
3642 13:53:37.037273 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3643 13:53:37.040770 iDelay=195, Bit 5, Center 118 (47 ~ 190) 144
3644 13:53:37.047336 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3645 13:53:37.050593 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3646 13:53:37.054176 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3647 13:53:37.057201 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3648 13:53:37.060690 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3649 13:53:37.067244 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3650 13:53:37.070486 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3651 13:53:37.073576 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3652 13:53:37.077062 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3653 13:53:37.080194 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3654 13:53:37.083718 ==
3655 13:53:37.087025 Dram Type= 6, Freq= 0, CH_1, rank 1
3656 13:53:37.090459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3657 13:53:37.090892 ==
3658 13:53:37.091218 DQS Delay:
3659 13:53:37.093454 DQS0 = 0, DQS1 = 0
3660 13:53:37.093900 DQM Delay:
3661 13:53:37.096635 DQM0 = 110, DQM1 = 109
3662 13:53:37.097112 DQ Delay:
3663 13:53:37.100207 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =106
3664 13:53:37.103493 DQ4 =106, DQ5 =118, DQ6 =120, DQ7 =110
3665 13:53:37.106757 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =102
3666 13:53:37.110051 DQ12 =116, DQ13 =116, DQ14 =118, DQ15 =116
3667 13:53:37.110475
3668 13:53:37.110826
3669 13:53:37.119787 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3670 13:53:37.123205 CH1 RK1: MR19=304, MR18=FA0B
3671 13:53:37.126328 CH1_RK1: MR19=0x304, MR18=0xFA0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3672 13:53:37.129748 [RxdqsGatingPostProcess] freq 1200
3673 13:53:37.136339 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3674 13:53:37.139758 best DQS0 dly(2T, 0.5T) = (0, 11)
3675 13:53:37.143025 best DQS1 dly(2T, 0.5T) = (0, 11)
3676 13:53:37.146427 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3677 13:53:37.149778 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3678 13:53:37.152897 best DQS0 dly(2T, 0.5T) = (0, 11)
3679 13:53:37.156574 best DQS1 dly(2T, 0.5T) = (0, 11)
3680 13:53:37.159447 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3681 13:53:37.163268 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3682 13:53:37.166296 Pre-setting of DQS Precalculation
3683 13:53:37.169434 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3684 13:53:37.176426 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3685 13:53:37.186091 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3686 13:53:37.186612
3687 13:53:37.186982
3688 13:53:37.187295 [Calibration Summary] 2400 Mbps
3689 13:53:37.189606 CH 0, Rank 0
3690 13:53:37.190183 SW Impedance : PASS
3691 13:53:37.192635 DUTY Scan : NO K
3692 13:53:37.195967 ZQ Calibration : PASS
3693 13:53:37.196411 Jitter Meter : NO K
3694 13:53:37.199167 CBT Training : PASS
3695 13:53:37.202597 Write leveling : PASS
3696 13:53:37.203018 RX DQS gating : PASS
3697 13:53:37.205786 RX DQ/DQS(RDDQC) : PASS
3698 13:53:37.209324 TX DQ/DQS : PASS
3699 13:53:37.209835 RX DATLAT : PASS
3700 13:53:37.212350 RX DQ/DQS(Engine): PASS
3701 13:53:37.215752 TX OE : NO K
3702 13:53:37.216172 All Pass.
3703 13:53:37.216631
3704 13:53:37.216968 CH 0, Rank 1
3705 13:53:37.219435 SW Impedance : PASS
3706 13:53:37.222709 DUTY Scan : NO K
3707 13:53:37.223180 ZQ Calibration : PASS
3708 13:53:37.225832 Jitter Meter : NO K
3709 13:53:37.229141 CBT Training : PASS
3710 13:53:37.229719 Write leveling : PASS
3711 13:53:37.232392 RX DQS gating : PASS
3712 13:53:37.235570 RX DQ/DQS(RDDQC) : PASS
3713 13:53:37.236136 TX DQ/DQS : PASS
3714 13:53:37.239125 RX DATLAT : PASS
3715 13:53:37.239648 RX DQ/DQS(Engine): PASS
3716 13:53:37.242467 TX OE : NO K
3717 13:53:37.242898 All Pass.
3718 13:53:37.243222
3719 13:53:37.245809 CH 1, Rank 0
3720 13:53:37.246219 SW Impedance : PASS
3721 13:53:37.249044 DUTY Scan : NO K
3722 13:53:37.252452 ZQ Calibration : PASS
3723 13:53:37.252902 Jitter Meter : NO K
3724 13:53:37.255571 CBT Training : PASS
3725 13:53:37.258820 Write leveling : PASS
3726 13:53:37.259230 RX DQS gating : PASS
3727 13:53:37.262283 RX DQ/DQS(RDDQC) : PASS
3728 13:53:37.265609 TX DQ/DQS : PASS
3729 13:53:37.266022 RX DATLAT : PASS
3730 13:53:37.268897 RX DQ/DQS(Engine): PASS
3731 13:53:37.272112 TX OE : NO K
3732 13:53:37.272614 All Pass.
3733 13:53:37.273097
3734 13:53:37.273412 CH 1, Rank 1
3735 13:53:37.275808 SW Impedance : PASS
3736 13:53:37.278913 DUTY Scan : NO K
3737 13:53:37.279433 ZQ Calibration : PASS
3738 13:53:37.282481 Jitter Meter : NO K
3739 13:53:37.285416 CBT Training : PASS
3740 13:53:37.285902 Write leveling : PASS
3741 13:53:37.288738 RX DQS gating : PASS
3742 13:53:37.292214 RX DQ/DQS(RDDQC) : PASS
3743 13:53:37.292628 TX DQ/DQS : PASS
3744 13:53:37.295685 RX DATLAT : PASS
3745 13:53:37.296096 RX DQ/DQS(Engine): PASS
3746 13:53:37.298782 TX OE : NO K
3747 13:53:37.299195 All Pass.
3748 13:53:37.299517
3749 13:53:37.302157 DramC Write-DBI off
3750 13:53:37.305407 PER_BANK_REFRESH: Hybrid Mode
3751 13:53:37.305933 TX_TRACKING: ON
3752 13:53:37.315590 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3753 13:53:37.318596 [FAST_K] Save calibration result to emmc
3754 13:53:37.322152 dramc_set_vcore_voltage set vcore to 650000
3755 13:53:37.325304 Read voltage for 600, 5
3756 13:53:37.325806 Vio18 = 0
3757 13:53:37.328833 Vcore = 650000
3758 13:53:37.329288 Vdram = 0
3759 13:53:37.329804 Vddq = 0
3760 13:53:37.330185 Vmddr = 0
3761 13:53:37.335562 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3762 13:53:37.338630 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3763 13:53:37.341935 MEM_TYPE=3, freq_sel=19
3764 13:53:37.345348 sv_algorithm_assistance_LP4_1600
3765 13:53:37.348770 ============ PULL DRAM RESETB DOWN ============
3766 13:53:37.355312 ========== PULL DRAM RESETB DOWN end =========
3767 13:53:37.358372 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3768 13:53:37.361925 ===================================
3769 13:53:37.365278 LPDDR4 DRAM CONFIGURATION
3770 13:53:37.368740 ===================================
3771 13:53:37.369325 EX_ROW_EN[0] = 0x0
3772 13:53:37.371798 EX_ROW_EN[1] = 0x0
3773 13:53:37.372317 LP4Y_EN = 0x0
3774 13:53:37.375377 WORK_FSP = 0x0
3775 13:53:37.375911 WL = 0x2
3776 13:53:37.378656 RL = 0x2
3777 13:53:37.379069 BL = 0x2
3778 13:53:37.381544 RPST = 0x0
3779 13:53:37.384687 RD_PRE = 0x0
3780 13:53:37.385097 WR_PRE = 0x1
3781 13:53:37.388360 WR_PST = 0x0
3782 13:53:37.388770 DBI_WR = 0x0
3783 13:53:37.391337 DBI_RD = 0x0
3784 13:53:37.391779 OTF = 0x1
3785 13:53:37.395000 ===================================
3786 13:53:37.397930 ===================================
3787 13:53:37.401580 ANA top config
3788 13:53:37.402018 ===================================
3789 13:53:37.404592 DLL_ASYNC_EN = 0
3790 13:53:37.408403 ALL_SLAVE_EN = 1
3791 13:53:37.411515 NEW_RANK_MODE = 1
3792 13:53:37.414744 DLL_IDLE_MODE = 1
3793 13:53:37.415168 LP45_APHY_COMB_EN = 1
3794 13:53:37.417850 TX_ODT_DIS = 1
3795 13:53:37.420979 NEW_8X_MODE = 1
3796 13:53:37.424563 ===================================
3797 13:53:37.428123 ===================================
3798 13:53:37.431448 data_rate = 1200
3799 13:53:37.434355 CKR = 1
3800 13:53:37.437657 DQ_P2S_RATIO = 8
3801 13:53:37.441051 ===================================
3802 13:53:37.441515 CA_P2S_RATIO = 8
3803 13:53:37.444750 DQ_CA_OPEN = 0
3804 13:53:37.447881 DQ_SEMI_OPEN = 0
3805 13:53:37.451509 CA_SEMI_OPEN = 0
3806 13:53:37.454521 CA_FULL_RATE = 0
3807 13:53:37.455042 DQ_CKDIV4_EN = 1
3808 13:53:37.457878 CA_CKDIV4_EN = 1
3809 13:53:37.461391 CA_PREDIV_EN = 0
3810 13:53:37.464422 PH8_DLY = 0
3811 13:53:37.467534 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3812 13:53:37.470935 DQ_AAMCK_DIV = 4
3813 13:53:37.471354 CA_AAMCK_DIV = 4
3814 13:53:37.474486 CA_ADMCK_DIV = 4
3815 13:53:37.477554 DQ_TRACK_CA_EN = 0
3816 13:53:37.480842 CA_PICK = 600
3817 13:53:37.484231 CA_MCKIO = 600
3818 13:53:37.487543 MCKIO_SEMI = 0
3819 13:53:37.491106 PLL_FREQ = 2288
3820 13:53:37.494194 DQ_UI_PI_RATIO = 32
3821 13:53:37.494652 CA_UI_PI_RATIO = 0
3822 13:53:37.497532 ===================================
3823 13:53:37.500659 ===================================
3824 13:53:37.503901 memory_type:LPDDR4
3825 13:53:37.507624 GP_NUM : 10
3826 13:53:37.508067 SRAM_EN : 1
3827 13:53:37.510544 MD32_EN : 0
3828 13:53:37.513837 ===================================
3829 13:53:37.517274 [ANA_INIT] >>>>>>>>>>>>>>
3830 13:53:37.520408 <<<<<< [CONFIGURE PHASE]: ANA_TX
3831 13:53:37.524101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3832 13:53:37.527358 ===================================
3833 13:53:37.527810 data_rate = 1200,PCW = 0X5800
3834 13:53:37.530660 ===================================
3835 13:53:37.533981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3836 13:53:37.540639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3837 13:53:37.546940 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3838 13:53:37.550398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3839 13:53:37.553534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3840 13:53:37.556932 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3841 13:53:37.560503 [ANA_INIT] flow start
3842 13:53:37.560917 [ANA_INIT] PLL >>>>>>>>
3843 13:53:37.563691 [ANA_INIT] PLL <<<<<<<<
3844 13:53:37.566989 [ANA_INIT] MIDPI >>>>>>>>
3845 13:53:37.570464 [ANA_INIT] MIDPI <<<<<<<<
3846 13:53:37.570879 [ANA_INIT] DLL >>>>>>>>
3847 13:53:37.573468 [ANA_INIT] flow end
3848 13:53:37.576943 ============ LP4 DIFF to SE enter ============
3849 13:53:37.580084 ============ LP4 DIFF to SE exit ============
3850 13:53:37.583534 [ANA_INIT] <<<<<<<<<<<<<
3851 13:53:37.586840 [Flow] Enable top DCM control >>>>>
3852 13:53:37.590215 [Flow] Enable top DCM control <<<<<
3853 13:53:37.593730 Enable DLL master slave shuffle
3854 13:53:37.600114 ==============================================================
3855 13:53:37.600615 Gating Mode config
3856 13:53:37.607013 ==============================================================
3857 13:53:37.607513 Config description:
3858 13:53:37.616566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3859 13:53:37.623012 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3860 13:53:37.629876 SELPH_MODE 0: By rank 1: By Phase
3861 13:53:37.633170 ==============================================================
3862 13:53:37.636754 GAT_TRACK_EN = 1
3863 13:53:37.639840 RX_GATING_MODE = 2
3864 13:53:37.643077 RX_GATING_TRACK_MODE = 2
3865 13:53:37.646646 SELPH_MODE = 1
3866 13:53:37.650124 PICG_EARLY_EN = 1
3867 13:53:37.653268 VALID_LAT_VALUE = 1
3868 13:53:37.659864 ==============================================================
3869 13:53:37.663107 Enter into Gating configuration >>>>
3870 13:53:37.666169 Exit from Gating configuration <<<<
3871 13:53:37.669875 Enter into DVFS_PRE_config >>>>>
3872 13:53:37.679660 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3873 13:53:37.682975 Exit from DVFS_PRE_config <<<<<
3874 13:53:37.686029 Enter into PICG configuration >>>>
3875 13:53:37.689439 Exit from PICG configuration <<<<
3876 13:53:37.692755 [RX_INPUT] configuration >>>>>
3877 13:53:37.693196 [RX_INPUT] configuration <<<<<
3878 13:53:37.699468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3879 13:53:37.705790 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3880 13:53:37.709156 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3881 13:53:37.715953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3882 13:53:37.722376 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3883 13:53:37.729068 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3884 13:53:37.732486 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3885 13:53:37.735611 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3886 13:53:37.742081 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3887 13:53:37.745518 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3888 13:53:37.749206 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3889 13:53:37.755804 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3890 13:53:37.758797 ===================================
3891 13:53:37.759247 LPDDR4 DRAM CONFIGURATION
3892 13:53:37.762408 ===================================
3893 13:53:37.765671 EX_ROW_EN[0] = 0x0
3894 13:53:37.766113 EX_ROW_EN[1] = 0x0
3895 13:53:37.769063 LP4Y_EN = 0x0
3896 13:53:37.769546 WORK_FSP = 0x0
3897 13:53:37.772351 WL = 0x2
3898 13:53:37.775947 RL = 0x2
3899 13:53:37.776488 BL = 0x2
3900 13:53:37.778861 RPST = 0x0
3901 13:53:37.779413 RD_PRE = 0x0
3902 13:53:37.782194 WR_PRE = 0x1
3903 13:53:37.782643 WR_PST = 0x0
3904 13:53:37.785598 DBI_WR = 0x0
3905 13:53:37.786042 DBI_RD = 0x0
3906 13:53:37.788712 OTF = 0x1
3907 13:53:37.791925 ===================================
3908 13:53:37.795257 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3909 13:53:37.798771 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3910 13:53:37.805447 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3911 13:53:37.808573 ===================================
3912 13:53:37.809102 LPDDR4 DRAM CONFIGURATION
3913 13:53:37.811823 ===================================
3914 13:53:37.815386 EX_ROW_EN[0] = 0x10
3915 13:53:37.815810 EX_ROW_EN[1] = 0x0
3916 13:53:37.818383 LP4Y_EN = 0x0
3917 13:53:37.818838 WORK_FSP = 0x0
3918 13:53:37.822129 WL = 0x2
3919 13:53:37.825026 RL = 0x2
3920 13:53:37.825648 BL = 0x2
3921 13:53:37.828116 RPST = 0x0
3922 13:53:37.828537 RD_PRE = 0x0
3923 13:53:37.831763 WR_PRE = 0x1
3924 13:53:37.832204 WR_PST = 0x0
3925 13:53:37.834972 DBI_WR = 0x0
3926 13:53:37.835391 DBI_RD = 0x0
3927 13:53:37.838648 OTF = 0x1
3928 13:53:37.841753 ===================================
3929 13:53:37.848236 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3930 13:53:37.851698 nWR fixed to 30
3931 13:53:37.852141 [ModeRegInit_LP4] CH0 RK0
3932 13:53:37.855104 [ModeRegInit_LP4] CH0 RK1
3933 13:53:37.858098 [ModeRegInit_LP4] CH1 RK0
3934 13:53:37.858547 [ModeRegInit_LP4] CH1 RK1
3935 13:53:37.861420 match AC timing 17
3936 13:53:37.864761 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3937 13:53:37.868223 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3938 13:53:37.875150 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3939 13:53:37.878599 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3940 13:53:37.884468 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3941 13:53:37.884916 ==
3942 13:53:37.888100 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 13:53:37.891570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 13:53:37.892192 ==
3945 13:53:37.897857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 13:53:37.904683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3947 13:53:37.907657 [CA 0] Center 37 (7~67) winsize 61
3948 13:53:37.910961 [CA 1] Center 36 (6~67) winsize 62
3949 13:53:37.914580 [CA 2] Center 35 (5~65) winsize 61
3950 13:53:37.917652 [CA 3] Center 35 (5~65) winsize 61
3951 13:53:37.921064 [CA 4] Center 34 (4~65) winsize 62
3952 13:53:37.924519 [CA 5] Center 34 (3~65) winsize 63
3953 13:53:37.925045
3954 13:53:37.927905 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3955 13:53:37.928384
3956 13:53:37.931047 [CATrainingPosCal] consider 1 rank data
3957 13:53:37.934279 u2DelayCellTimex100 = 270/100 ps
3958 13:53:37.937839 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3959 13:53:37.940907 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3960 13:53:37.944009 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3961 13:53:37.947820 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3962 13:53:37.951150 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3963 13:53:37.954432 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
3964 13:53:37.954948
3965 13:53:37.957605 CA PerBit enable=1, Macro0, CA PI delay=34
3966 13:53:37.960712
3967 13:53:37.961156 [CBTSetCACLKResult] CA Dly = 34
3968 13:53:37.964286 CS Dly: 5 (0~36)
3969 13:53:37.964782 ==
3970 13:53:37.967650 Dram Type= 6, Freq= 0, CH_0, rank 1
3971 13:53:37.970647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 13:53:37.971173 ==
3973 13:53:37.977597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3974 13:53:37.984222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3975 13:53:37.987414 [CA 0] Center 37 (7~67) winsize 61
3976 13:53:37.991099 [CA 1] Center 36 (6~67) winsize 62
3977 13:53:37.994006 [CA 2] Center 35 (5~65) winsize 61
3978 13:53:37.997516 [CA 3] Center 35 (5~65) winsize 61
3979 13:53:38.000698 [CA 4] Center 34 (4~65) winsize 62
3980 13:53:38.003808 [CA 5] Center 33 (3~64) winsize 62
3981 13:53:38.004224
3982 13:53:38.007600 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3983 13:53:38.008032
3984 13:53:38.010483 [CATrainingPosCal] consider 2 rank data
3985 13:53:38.013967 u2DelayCellTimex100 = 270/100 ps
3986 13:53:38.017262 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3987 13:53:38.020464 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3988 13:53:38.023951 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3989 13:53:38.027067 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3990 13:53:38.030703 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3991 13:53:38.037162 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3992 13:53:38.037739
3993 13:53:38.040383 CA PerBit enable=1, Macro0, CA PI delay=33
3994 13:53:38.040797
3995 13:53:38.043842 [CBTSetCACLKResult] CA Dly = 33
3996 13:53:38.044273 CS Dly: 6 (0~38)
3997 13:53:38.044673
3998 13:53:38.047376 ----->DramcWriteLeveling(PI) begin...
3999 13:53:38.047895 ==
4000 13:53:38.050321 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 13:53:38.053782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 13:53:38.057238 ==
4003 13:53:38.057680 Write leveling (Byte 0): 33 => 33
4004 13:53:38.060568 Write leveling (Byte 1): 31 => 31
4005 13:53:38.064015 DramcWriteLeveling(PI) end<-----
4006 13:53:38.064523
4007 13:53:38.064848 ==
4008 13:53:38.066927 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 13:53:38.073585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 13:53:38.074001 ==
4011 13:53:38.076967 [Gating] SW mode calibration
4012 13:53:38.083631 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4013 13:53:38.086989 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4014 13:53:38.093416 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 13:53:38.096719 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 13:53:38.100259 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 13:53:38.103408 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4018 13:53:38.110154 0 9 16 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (0 0)
4019 13:53:38.113561 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4020 13:53:38.116964 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 13:53:38.123248 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 13:53:38.126767 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 13:53:38.129935 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 13:53:38.136649 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 13:53:38.140005 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4026 13:53:38.143204 0 10 16 | B1->B0 | 3131 3e3e | 0 0 | (0 0) (0 0)
4027 13:53:38.149998 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 13:53:38.153184 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 13:53:38.156721 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 13:53:38.163027 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 13:53:38.166567 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 13:53:38.169945 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 13:53:38.176963 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4034 13:53:38.180102 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4035 13:53:38.183775 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 13:53:38.190104 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 13:53:38.193467 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 13:53:38.196567 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 13:53:38.203043 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 13:53:38.206737 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 13:53:38.209930 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 13:53:38.216511 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 13:53:38.220008 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 13:53:38.223152 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 13:53:38.229519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 13:53:38.233040 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 13:53:38.236457 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 13:53:38.242766 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 13:53:38.246129 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 13:53:38.249449 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4051 13:53:38.252795 Total UI for P1: 0, mck2ui 16
4052 13:53:38.256053 best dqsien dly found for B0: ( 0, 13, 14)
4053 13:53:38.259426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 13:53:38.262962 Total UI for P1: 0, mck2ui 16
4055 13:53:38.265886 best dqsien dly found for B1: ( 0, 13, 16)
4056 13:53:38.272877 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4057 13:53:38.275877 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4058 13:53:38.276440
4059 13:53:38.279291 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4060 13:53:38.282718 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4061 13:53:38.285862 [Gating] SW calibration Done
4062 13:53:38.286351 ==
4063 13:53:38.289374 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 13:53:38.292274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 13:53:38.292706 ==
4066 13:53:38.296150 RX Vref Scan: 0
4067 13:53:38.296676
4068 13:53:38.297011 RX Vref 0 -> 0, step: 1
4069 13:53:38.297320
4070 13:53:38.299156 RX Delay -230 -> 252, step: 16
4071 13:53:38.305689 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4072 13:53:38.308706 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4073 13:53:38.312105 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4074 13:53:38.315592 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4075 13:53:38.318764 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4076 13:53:38.325562 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4077 13:53:38.328944 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4078 13:53:38.331932 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4079 13:53:38.335109 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4080 13:53:38.342081 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4081 13:53:38.345076 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4082 13:53:38.348307 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4083 13:53:38.351976 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4084 13:53:38.358426 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4085 13:53:38.361743 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4086 13:53:38.365229 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4087 13:53:38.365678 ==
4088 13:53:38.368465 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 13:53:38.371704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 13:53:38.374848 ==
4091 13:53:38.375300 DQS Delay:
4092 13:53:38.375633 DQS0 = 0, DQS1 = 0
4093 13:53:38.378241 DQM Delay:
4094 13:53:38.378683 DQM0 = 37, DQM1 = 28
4095 13:53:38.381522 DQ Delay:
4096 13:53:38.381936 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4097 13:53:38.385062 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4098 13:53:38.388247 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4099 13:53:38.391402 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4100 13:53:38.391852
4101 13:53:38.394748
4102 13:53:38.395199 ==
4103 13:53:38.398005 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 13:53:38.401303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 13:53:38.401751 ==
4106 13:53:38.402131
4107 13:53:38.402535
4108 13:53:38.404737 TX Vref Scan disable
4109 13:53:38.405146 == TX Byte 0 ==
4110 13:53:38.411363 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4111 13:53:38.414485 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4112 13:53:38.414900 == TX Byte 1 ==
4113 13:53:38.421145 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4114 13:53:38.424374 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4115 13:53:38.424868 ==
4116 13:53:38.427783 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 13:53:38.431024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 13:53:38.431579 ==
4119 13:53:38.431955
4120 13:53:38.432259
4121 13:53:38.434361 TX Vref Scan disable
4122 13:53:38.437737 == TX Byte 0 ==
4123 13:53:38.440995 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4124 13:53:38.444200 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4125 13:53:38.448102 == TX Byte 1 ==
4126 13:53:38.451160 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4127 13:53:38.454409 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4128 13:53:38.457589
4129 13:53:38.458122 [DATLAT]
4130 13:53:38.458563 Freq=600, CH0 RK0
4131 13:53:38.458973
4132 13:53:38.460843 DATLAT Default: 0x9
4133 13:53:38.461269 0, 0xFFFF, sum = 0
4134 13:53:38.464238 1, 0xFFFF, sum = 0
4135 13:53:38.464799 2, 0xFFFF, sum = 0
4136 13:53:38.467757 3, 0xFFFF, sum = 0
4137 13:53:38.468194 4, 0xFFFF, sum = 0
4138 13:53:38.470887 5, 0xFFFF, sum = 0
4139 13:53:38.473952 6, 0xFFFF, sum = 0
4140 13:53:38.474390 7, 0xFFFF, sum = 0
4141 13:53:38.477535 8, 0x0, sum = 1
4142 13:53:38.478078 9, 0x0, sum = 2
4143 13:53:38.478526 10, 0x0, sum = 3
4144 13:53:38.480653 11, 0x0, sum = 4
4145 13:53:38.481088 best_step = 9
4146 13:53:38.481552
4147 13:53:38.481966 ==
4148 13:53:38.483688 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 13:53:38.490380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 13:53:38.490814 ==
4151 13:53:38.491252 RX Vref Scan: 1
4152 13:53:38.491679
4153 13:53:38.493880 RX Vref 0 -> 0, step: 1
4154 13:53:38.494301
4155 13:53:38.497130 RX Delay -195 -> 252, step: 8
4156 13:53:38.497638
4157 13:53:38.500208 Set Vref, RX VrefLevel [Byte0]: 61
4158 13:53:38.503830 [Byte1]: 47
4159 13:53:38.504475
4160 13:53:38.507104 Final RX Vref Byte 0 = 61 to rank0
4161 13:53:38.510622 Final RX Vref Byte 1 = 47 to rank0
4162 13:53:38.513595 Final RX Vref Byte 0 = 61 to rank1
4163 13:53:38.517026 Final RX Vref Byte 1 = 47 to rank1==
4164 13:53:38.520559 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 13:53:38.523677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 13:53:38.524105 ==
4167 13:53:38.526796 DQS Delay:
4168 13:53:38.527223 DQS0 = 0, DQS1 = 0
4169 13:53:38.530418 DQM Delay:
4170 13:53:38.530845 DQM0 = 35, DQM1 = 29
4171 13:53:38.531283 DQ Delay:
4172 13:53:38.533444 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4173 13:53:38.536664 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =44
4174 13:53:38.539863 DQ8 =24, DQ9 =16, DQ10 =28, DQ11 =24
4175 13:53:38.543249 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4176 13:53:38.543682
4177 13:53:38.546612
4178 13:53:38.553496 [DQSOSCAuto] RK0, (LSB)MR18= 0x4644, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4179 13:53:38.556537 CH0 RK0: MR19=808, MR18=4644
4180 13:53:38.563190 CH0_RK0: MR19=0x808, MR18=0x4644, DQSOSC=396, MR23=63, INC=167, DEC=111
4181 13:53:38.563708
4182 13:53:38.566582 ----->DramcWriteLeveling(PI) begin...
4183 13:53:38.567086 ==
4184 13:53:38.569943 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 13:53:38.572804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 13:53:38.573247 ==
4187 13:53:38.576358 Write leveling (Byte 0): 32 => 32
4188 13:53:38.579554 Write leveling (Byte 1): 32 => 32
4189 13:53:38.583027 DramcWriteLeveling(PI) end<-----
4190 13:53:38.583448
4191 13:53:38.583864 ==
4192 13:53:38.586511 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 13:53:38.589572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 13:53:38.590067 ==
4195 13:53:38.592966 [Gating] SW mode calibration
4196 13:53:38.599788 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4197 13:53:38.606316 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4198 13:53:38.609420 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 13:53:38.612755 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 13:53:38.619143 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 13:53:38.622752 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
4202 13:53:38.626139 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4203 13:53:38.632419 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 13:53:38.636092 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 13:53:38.639116 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 13:53:38.646069 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 13:53:38.649093 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 13:53:38.652545 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 13:53:38.659244 0 10 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (0 0)
4210 13:53:38.662509 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4211 13:53:38.665890 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 13:53:38.672421 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 13:53:38.675740 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 13:53:38.679000 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 13:53:38.685811 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 13:53:38.688888 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 13:53:38.692060 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 13:53:38.698804 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 13:53:38.702245 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 13:53:38.705284 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 13:53:38.712312 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 13:53:38.715329 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 13:53:38.718949 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 13:53:38.725600 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 13:53:38.728621 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 13:53:38.731877 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 13:53:38.738255 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 13:53:38.741737 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 13:53:38.744812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 13:53:38.751956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 13:53:38.755484 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 13:53:38.758411 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 13:53:38.765042 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4234 13:53:38.765690 Total UI for P1: 0, mck2ui 16
4235 13:53:38.771687 best dqsien dly found for B0: ( 0, 13, 10)
4236 13:53:38.774981 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 13:53:38.778256 Total UI for P1: 0, mck2ui 16
4238 13:53:38.781450 best dqsien dly found for B1: ( 0, 13, 14)
4239 13:53:38.784555 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4240 13:53:38.788154 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4241 13:53:38.788598
4242 13:53:38.791476 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4243 13:53:38.794652 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4244 13:53:38.798168 [Gating] SW calibration Done
4245 13:53:38.798582 ==
4246 13:53:38.801175 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 13:53:38.804741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 13:53:38.808146 ==
4249 13:53:38.808557 RX Vref Scan: 0
4250 13:53:38.808880
4251 13:53:38.811399 RX Vref 0 -> 0, step: 1
4252 13:53:38.811811
4253 13:53:38.814628 RX Delay -230 -> 252, step: 16
4254 13:53:38.817964 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4255 13:53:38.821059 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4256 13:53:38.824641 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4257 13:53:38.831362 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4258 13:53:38.834547 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4259 13:53:38.837749 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4260 13:53:38.841012 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4261 13:53:38.844450 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4262 13:53:38.851002 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4263 13:53:38.854489 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4264 13:53:38.857626 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4265 13:53:38.861317 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4266 13:53:38.867964 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4267 13:53:38.870742 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4268 13:53:38.874290 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4269 13:53:38.877829 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4270 13:53:38.878241 ==
4271 13:53:38.880916 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 13:53:38.887482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 13:53:38.887898 ==
4274 13:53:38.888218 DQS Delay:
4275 13:53:38.890957 DQS0 = 0, DQS1 = 0
4276 13:53:38.891383 DQM Delay:
4277 13:53:38.891707 DQM0 = 36, DQM1 = 30
4278 13:53:38.894094 DQ Delay:
4279 13:53:38.897515 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4280 13:53:38.900992 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4281 13:53:38.904096 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4282 13:53:38.907462 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4283 13:53:38.907877
4284 13:53:38.908201
4285 13:53:38.908501 ==
4286 13:53:38.910655 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 13:53:38.914126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 13:53:38.914542 ==
4289 13:53:38.914867
4290 13:53:38.915167
4291 13:53:38.917355 TX Vref Scan disable
4292 13:53:38.917819 == TX Byte 0 ==
4293 13:53:38.924184 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4294 13:53:38.927282 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4295 13:53:38.930796 == TX Byte 1 ==
4296 13:53:38.933842 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4297 13:53:38.937341 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4298 13:53:38.937799 ==
4299 13:53:38.940869 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 13:53:38.944161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 13:53:38.944645 ==
4302 13:53:38.944992
4303 13:53:38.947477
4304 13:53:38.947885 TX Vref Scan disable
4305 13:53:38.950598 == TX Byte 0 ==
4306 13:53:38.953983 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4307 13:53:38.960657 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4308 13:53:38.961161 == TX Byte 1 ==
4309 13:53:38.963933 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4310 13:53:38.970396 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4311 13:53:38.970809
4312 13:53:38.971129 [DATLAT]
4313 13:53:38.971427 Freq=600, CH0 RK1
4314 13:53:38.971806
4315 13:53:38.973889 DATLAT Default: 0x9
4316 13:53:38.974438 0, 0xFFFF, sum = 0
4317 13:53:38.977058 1, 0xFFFF, sum = 0
4318 13:53:38.980263 2, 0xFFFF, sum = 0
4319 13:53:38.980677 3, 0xFFFF, sum = 0
4320 13:53:38.983928 4, 0xFFFF, sum = 0
4321 13:53:38.984346 5, 0xFFFF, sum = 0
4322 13:53:38.987115 6, 0xFFFF, sum = 0
4323 13:53:38.987529 7, 0xFFFF, sum = 0
4324 13:53:38.990219 8, 0x0, sum = 1
4325 13:53:38.990637 9, 0x0, sum = 2
4326 13:53:38.990959 10, 0x0, sum = 3
4327 13:53:38.993907 11, 0x0, sum = 4
4328 13:53:38.994321 best_step = 9
4329 13:53:38.994644
4330 13:53:38.996911 ==
4331 13:53:38.997323 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 13:53:39.003682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 13:53:39.004143 ==
4334 13:53:39.004465 RX Vref Scan: 0
4335 13:53:39.004765
4336 13:53:39.006752 RX Vref 0 -> 0, step: 1
4337 13:53:39.007160
4338 13:53:39.010014 RX Delay -195 -> 252, step: 8
4339 13:53:39.016617 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4340 13:53:39.020110 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4341 13:53:39.023221 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4342 13:53:39.026434 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4343 13:53:39.030247 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4344 13:53:39.036994 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4345 13:53:39.040079 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4346 13:53:39.043590 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4347 13:53:39.046741 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4348 13:53:39.050596 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4349 13:53:39.056490 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4350 13:53:39.060146 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4351 13:53:39.063283 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4352 13:53:39.066901 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4353 13:53:39.073381 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4354 13:53:39.076776 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4355 13:53:39.077287 ==
4356 13:53:39.079891 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 13:53:39.083334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 13:53:39.083764 ==
4359 13:53:39.086884 DQS Delay:
4360 13:53:39.087398 DQS0 = 0, DQS1 = 0
4361 13:53:39.089803 DQM Delay:
4362 13:53:39.090210 DQM0 = 34, DQM1 = 28
4363 13:53:39.090597 DQ Delay:
4364 13:53:39.093205 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4365 13:53:39.096357 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4366 13:53:39.099854 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4367 13:53:39.102974 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4368 13:53:39.103385
4369 13:53:39.103705
4370 13:53:39.113136 [DQSOSCAuto] RK1, (LSB)MR18= 0x7140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4371 13:53:39.116351 CH0 RK1: MR19=808, MR18=7140
4372 13:53:39.119800 CH0_RK1: MR19=0x808, MR18=0x7140, DQSOSC=388, MR23=63, INC=174, DEC=116
4373 13:53:39.123223 [RxdqsGatingPostProcess] freq 600
4374 13:53:39.129706 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4375 13:53:39.133286 Pre-setting of DQS Precalculation
4376 13:53:39.136397 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4377 13:53:39.136850 ==
4378 13:53:39.139701 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 13:53:39.146385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 13:53:39.146864 ==
4381 13:53:39.149442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4382 13:53:39.156223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4383 13:53:39.159766 [CA 0] Center 36 (6~66) winsize 61
4384 13:53:39.163439 [CA 1] Center 35 (5~66) winsize 62
4385 13:53:39.166548 [CA 2] Center 34 (4~65) winsize 62
4386 13:53:39.169680 [CA 3] Center 34 (4~65) winsize 62
4387 13:53:39.172909 [CA 4] Center 34 (4~65) winsize 62
4388 13:53:39.176320 [CA 5] Center 34 (4~64) winsize 61
4389 13:53:39.176763
4390 13:53:39.179635 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4391 13:53:39.180078
4392 13:53:39.182889 [CATrainingPosCal] consider 1 rank data
4393 13:53:39.186211 u2DelayCellTimex100 = 270/100 ps
4394 13:53:39.189618 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4395 13:53:39.196035 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4396 13:53:39.199758 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 13:53:39.203261 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4398 13:53:39.206027 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4399 13:53:39.209597 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4400 13:53:39.210011
4401 13:53:39.212745 CA PerBit enable=1, Macro0, CA PI delay=34
4402 13:53:39.213160
4403 13:53:39.216328 [CBTSetCACLKResult] CA Dly = 34
4404 13:53:39.216819 CS Dly: 4 (0~35)
4405 13:53:39.219488 ==
4406 13:53:39.222607 Dram Type= 6, Freq= 0, CH_1, rank 1
4407 13:53:39.226182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 13:53:39.226636 ==
4409 13:53:39.229647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4410 13:53:39.235943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4411 13:53:39.239532 [CA 0] Center 36 (6~66) winsize 61
4412 13:53:39.243155 [CA 1] Center 36 (6~67) winsize 62
4413 13:53:39.246482 [CA 2] Center 34 (4~65) winsize 62
4414 13:53:39.249671 [CA 3] Center 34 (3~65) winsize 63
4415 13:53:39.253266 [CA 4] Center 34 (4~65) winsize 62
4416 13:53:39.256622 [CA 5] Center 33 (3~64) winsize 62
4417 13:53:39.257058
4418 13:53:39.259626 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4419 13:53:39.260076
4420 13:53:39.263501 [CATrainingPosCal] consider 2 rank data
4421 13:53:39.266281 u2DelayCellTimex100 = 270/100 ps
4422 13:53:39.269745 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4423 13:53:39.276558 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4424 13:53:39.279687 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4425 13:53:39.283348 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4426 13:53:39.286241 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4427 13:53:39.289708 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4428 13:53:39.290142
4429 13:53:39.292892 CA PerBit enable=1, Macro0, CA PI delay=34
4430 13:53:39.293329
4431 13:53:39.296377 [CBTSetCACLKResult] CA Dly = 34
4432 13:53:39.296787 CS Dly: 4 (0~36)
4433 13:53:39.299638
4434 13:53:39.302819 ----->DramcWriteLeveling(PI) begin...
4435 13:53:39.303237 ==
4436 13:53:39.306052 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 13:53:39.309551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 13:53:39.309970 ==
4439 13:53:39.312583 Write leveling (Byte 0): 29 => 29
4440 13:53:39.316133 Write leveling (Byte 1): 30 => 30
4441 13:53:39.319185 DramcWriteLeveling(PI) end<-----
4442 13:53:39.319597
4443 13:53:39.319922 ==
4444 13:53:39.322790 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 13:53:39.326115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 13:53:39.326531 ==
4447 13:53:39.329221 [Gating] SW mode calibration
4448 13:53:39.336000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4449 13:53:39.342303 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4450 13:53:39.345765 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 13:53:39.348948 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 13:53:39.355529 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4453 13:53:39.359087 0 9 12 | B1->B0 | 2f2f 3030 | 1 1 | (1 1) (1 1)
4454 13:53:39.362207 0 9 16 | B1->B0 | 2828 2a2a | 0 1 | (1 0) (1 0)
4455 13:53:39.368552 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 13:53:39.371989 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 13:53:39.375582 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 13:53:39.381875 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 13:53:39.385166 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 13:53:39.388590 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 13:53:39.395086 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4462 13:53:39.398168 0 10 16 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
4463 13:53:39.401195 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 13:53:39.407999 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 13:53:39.411397 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 13:53:39.414559 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 13:53:39.421232 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 13:53:39.424379 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 13:53:39.427771 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 13:53:39.434334 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 13:53:39.437465 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 13:53:39.440993 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 13:53:39.447627 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 13:53:39.450803 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 13:53:39.454289 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 13:53:39.460950 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 13:53:39.463939 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 13:53:39.467546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 13:53:39.473959 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 13:53:39.477514 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 13:53:39.480713 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:53:39.487237 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 13:53:39.490425 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 13:53:39.494059 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 13:53:39.500721 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 13:53:39.503906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4487 13:53:39.507068 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 13:53:39.510450 Total UI for P1: 0, mck2ui 16
4489 13:53:39.513776 best dqsien dly found for B0: ( 0, 13, 16)
4490 13:53:39.516935 Total UI for P1: 0, mck2ui 16
4491 13:53:39.520494 best dqsien dly found for B1: ( 0, 13, 16)
4492 13:53:39.523661 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4493 13:53:39.527184 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4494 13:53:39.527268
4495 13:53:39.530190 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4496 13:53:39.536856 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4497 13:53:39.536987 [Gating] SW calibration Done
4498 13:53:39.540343 ==
4499 13:53:39.540425 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 13:53:39.546767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 13:53:39.546853 ==
4502 13:53:39.546917 RX Vref Scan: 0
4503 13:53:39.546976
4504 13:53:39.549941 RX Vref 0 -> 0, step: 1
4505 13:53:39.550047
4506 13:53:39.553471 RX Delay -230 -> 252, step: 16
4507 13:53:39.556578 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4508 13:53:39.560014 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4509 13:53:39.566573 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4510 13:53:39.569825 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4511 13:53:39.573093 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4512 13:53:39.576323 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4513 13:53:39.582994 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4514 13:53:39.586279 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4515 13:53:39.589432 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4516 13:53:39.592848 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4517 13:53:39.596219 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4518 13:53:39.603032 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4519 13:53:39.606381 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4520 13:53:39.609431 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4521 13:53:39.612628 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4522 13:53:39.619382 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4523 13:53:39.619502 ==
4524 13:53:39.622617 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 13:53:39.625921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 13:53:39.626010 ==
4527 13:53:39.626095 DQS Delay:
4528 13:53:39.629196 DQS0 = 0, DQS1 = 0
4529 13:53:39.629297 DQM Delay:
4530 13:53:39.632707 DQM0 = 39, DQM1 = 28
4531 13:53:39.632791 DQ Delay:
4532 13:53:39.635811 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4533 13:53:39.639259 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4534 13:53:39.642667 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4535 13:53:39.645910 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4536 13:53:39.645996
4537 13:53:39.646059
4538 13:53:39.646119 ==
4539 13:53:39.649378 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 13:53:39.652430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 13:53:39.655943 ==
4542 13:53:39.656029
4543 13:53:39.656096
4544 13:53:39.656156 TX Vref Scan disable
4545 13:53:39.659081 == TX Byte 0 ==
4546 13:53:39.662539 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4547 13:53:39.665760 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4548 13:53:39.669224 == TX Byte 1 ==
4549 13:53:39.672467 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4550 13:53:39.675889 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4551 13:53:39.679157 ==
4552 13:53:39.682553 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 13:53:39.685628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 13:53:39.685709 ==
4555 13:53:39.685773
4556 13:53:39.685832
4557 13:53:39.689038 TX Vref Scan disable
4558 13:53:39.689119 == TX Byte 0 ==
4559 13:53:39.695516 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4560 13:53:39.698999 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4561 13:53:39.702149 == TX Byte 1 ==
4562 13:53:39.705323 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4563 13:53:39.708634 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4564 13:53:39.708721
4565 13:53:39.708790 [DATLAT]
4566 13:53:39.712290 Freq=600, CH1 RK0
4567 13:53:39.712384
4568 13:53:39.712458 DATLAT Default: 0x9
4569 13:53:39.715574 0, 0xFFFF, sum = 0
4570 13:53:39.715670 1, 0xFFFF, sum = 0
4571 13:53:39.718705 2, 0xFFFF, sum = 0
4572 13:53:39.722265 3, 0xFFFF, sum = 0
4573 13:53:39.722378 4, 0xFFFF, sum = 0
4574 13:53:39.725508 5, 0xFFFF, sum = 0
4575 13:53:39.725622 6, 0xFFFF, sum = 0
4576 13:53:39.728742 7, 0xFFFF, sum = 0
4577 13:53:39.728865 8, 0x0, sum = 1
4578 13:53:39.728988 9, 0x0, sum = 2
4579 13:53:39.732164 10, 0x0, sum = 3
4580 13:53:39.732305 11, 0x0, sum = 4
4581 13:53:39.735548 best_step = 9
4582 13:53:39.735682
4583 13:53:39.735788 ==
4584 13:53:39.738850 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 13:53:39.742157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 13:53:39.742293 ==
4587 13:53:39.745301 RX Vref Scan: 1
4588 13:53:39.745509
4589 13:53:39.745624 RX Vref 0 -> 0, step: 1
4590 13:53:39.745726
4591 13:53:39.748492 RX Delay -195 -> 252, step: 8
4592 13:53:39.748626
4593 13:53:39.752009 Set Vref, RX VrefLevel [Byte0]: 52
4594 13:53:39.755373 [Byte1]: 50
4595 13:53:39.759633
4596 13:53:39.759767 Final RX Vref Byte 0 = 52 to rank0
4597 13:53:39.762991 Final RX Vref Byte 1 = 50 to rank0
4598 13:53:39.766706 Final RX Vref Byte 0 = 52 to rank1
4599 13:53:39.769794 Final RX Vref Byte 1 = 50 to rank1==
4600 13:53:39.772852 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 13:53:39.779540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 13:53:39.779882 ==
4603 13:53:39.780081 DQS Delay:
4604 13:53:39.783402 DQS0 = 0, DQS1 = 0
4605 13:53:39.783737 DQM Delay:
4606 13:53:39.783950 DQM0 = 36, DQM1 = 27
4607 13:53:39.786620 DQ Delay:
4608 13:53:39.789569 DQ0 =44, DQ1 =28, DQ2 =24, DQ3 =36
4609 13:53:39.792951 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =32
4610 13:53:39.796328 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4611 13:53:39.799732 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4612 13:53:39.800282
4613 13:53:39.800631
4614 13:53:39.806148 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4615 13:53:39.809379 CH1 RK0: MR19=808, MR18=2A37
4616 13:53:39.816132 CH1_RK0: MR19=0x808, MR18=0x2A37, DQSOSC=399, MR23=63, INC=164, DEC=109
4617 13:53:39.816579
4618 13:53:39.819493 ----->DramcWriteLeveling(PI) begin...
4619 13:53:39.819920 ==
4620 13:53:39.822909 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 13:53:39.826263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 13:53:39.826687 ==
4623 13:53:39.829439 Write leveling (Byte 0): 28 => 28
4624 13:53:39.832583 Write leveling (Byte 1): 29 => 29
4625 13:53:39.835914 DramcWriteLeveling(PI) end<-----
4626 13:53:39.836363
4627 13:53:39.836695 ==
4628 13:53:39.839495 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 13:53:39.842617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 13:53:39.845879 ==
4631 13:53:39.846311 [Gating] SW mode calibration
4632 13:53:39.852776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4633 13:53:39.858955 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4634 13:53:39.862484 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4635 13:53:39.869092 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4636 13:53:39.872707 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 13:53:39.875511 0 9 12 | B1->B0 | 3030 2b2b | 0 1 | (0 1) (1 0)
4638 13:53:39.882298 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4639 13:53:39.886077 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 13:53:39.888944 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 13:53:39.895469 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 13:53:39.898990 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 13:53:39.902282 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 13:53:39.908845 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 13:53:39.912376 0 10 12 | B1->B0 | 2c2c 3b3b | 1 0 | (0 0) (0 0)
4646 13:53:39.915553 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4647 13:53:39.921910 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 13:53:39.925573 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 13:53:39.928699 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 13:53:39.935338 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 13:53:39.938361 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 13:53:39.942019 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 13:53:39.948538 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4654 13:53:39.951844 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 13:53:39.955031 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 13:53:39.958435 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 13:53:39.965107 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 13:53:39.968597 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 13:53:39.971920 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 13:53:39.978356 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 13:53:39.981997 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 13:53:39.985136 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 13:53:39.991782 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 13:53:39.995014 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 13:53:39.998514 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 13:53:40.005074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 13:53:40.008388 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 13:53:40.011771 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 13:53:40.018003 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4670 13:53:40.021441 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 13:53:40.025014 Total UI for P1: 0, mck2ui 16
4672 13:53:40.028325 best dqsien dly found for B0: ( 0, 13, 12)
4673 13:53:40.031560 Total UI for P1: 0, mck2ui 16
4674 13:53:40.034936 best dqsien dly found for B1: ( 0, 13, 14)
4675 13:53:40.038206 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4676 13:53:40.041579 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4677 13:53:40.042028
4678 13:53:40.044733 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4679 13:53:40.048368 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4680 13:53:40.051628 [Gating] SW calibration Done
4681 13:53:40.052164 ==
4682 13:53:40.054718 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 13:53:40.061355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 13:53:40.061847 ==
4685 13:53:40.062185 RX Vref Scan: 0
4686 13:53:40.062496
4687 13:53:40.064930 RX Vref 0 -> 0, step: 1
4688 13:53:40.065453
4689 13:53:40.068193 RX Delay -230 -> 252, step: 16
4690 13:53:40.071120 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4691 13:53:40.074468 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4692 13:53:40.077826 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4693 13:53:40.084587 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4694 13:53:40.087729 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4695 13:53:40.091110 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4696 13:53:40.094166 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4697 13:53:40.100924 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4698 13:53:40.104344 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4699 13:53:40.107643 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4700 13:53:40.110824 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4701 13:53:40.114094 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4702 13:53:40.120780 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4703 13:53:40.123953 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4704 13:53:40.127453 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4705 13:53:40.133901 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4706 13:53:40.134333 ==
4707 13:53:40.137375 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 13:53:40.140801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 13:53:40.141220 ==
4710 13:53:40.141610 DQS Delay:
4711 13:53:40.143767 DQS0 = 0, DQS1 = 0
4712 13:53:40.144197 DQM Delay:
4713 13:53:40.147120 DQM0 = 38, DQM1 = 32
4714 13:53:40.147534 DQ Delay:
4715 13:53:40.150672 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4716 13:53:40.153799 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4717 13:53:40.157056 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4718 13:53:40.160695 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4719 13:53:40.161231
4720 13:53:40.161619
4721 13:53:40.161935 ==
4722 13:53:40.163772 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 13:53:40.167119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 13:53:40.167550 ==
4725 13:53:40.167990
4726 13:53:40.168402
4727 13:53:40.170321 TX Vref Scan disable
4728 13:53:40.173725 == TX Byte 0 ==
4729 13:53:40.176866 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4730 13:53:40.180274 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4731 13:53:40.184158 == TX Byte 1 ==
4732 13:53:40.186815 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4733 13:53:40.190233 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4734 13:53:40.190664 ==
4735 13:53:40.193431 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 13:53:40.200218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 13:53:40.200743 ==
4738 13:53:40.201207
4739 13:53:40.201752
4740 13:53:40.202166 TX Vref Scan disable
4741 13:53:40.204409 == TX Byte 0 ==
4742 13:53:40.208055 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4743 13:53:40.211380 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4744 13:53:40.214640 == TX Byte 1 ==
4745 13:53:40.218076 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4746 13:53:40.221250 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4747 13:53:40.224663
4748 13:53:40.225090 [DATLAT]
4749 13:53:40.225569 Freq=600, CH1 RK1
4750 13:53:40.226000
4751 13:53:40.228100 DATLAT Default: 0x9
4752 13:53:40.228532 0, 0xFFFF, sum = 0
4753 13:53:40.231260 1, 0xFFFF, sum = 0
4754 13:53:40.231697 2, 0xFFFF, sum = 0
4755 13:53:40.234714 3, 0xFFFF, sum = 0
4756 13:53:40.235153 4, 0xFFFF, sum = 0
4757 13:53:40.238033 5, 0xFFFF, sum = 0
4758 13:53:40.238470 6, 0xFFFF, sum = 0
4759 13:53:40.241252 7, 0xFFFF, sum = 0
4760 13:53:40.241770 8, 0x0, sum = 1
4761 13:53:40.244660 9, 0x0, sum = 2
4762 13:53:40.245113 10, 0x0, sum = 3
4763 13:53:40.247964 11, 0x0, sum = 4
4764 13:53:40.248399 best_step = 9
4765 13:53:40.248945
4766 13:53:40.249422 ==
4767 13:53:40.251181 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 13:53:40.257776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 13:53:40.258235 ==
4770 13:53:40.258668 RX Vref Scan: 0
4771 13:53:40.259077
4772 13:53:40.261250 RX Vref 0 -> 0, step: 1
4773 13:53:40.261725
4774 13:53:40.264585 RX Delay -195 -> 252, step: 8
4775 13:53:40.267769 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4776 13:53:40.274336 iDelay=205, Bit 1, Center 28 (-131 ~ 188) 320
4777 13:53:40.278000 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4778 13:53:40.281088 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4779 13:53:40.284579 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4780 13:53:40.287768 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4781 13:53:40.294319 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4782 13:53:40.297609 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4783 13:53:40.300824 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4784 13:53:40.304378 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4785 13:53:40.310905 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4786 13:53:40.314314 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4787 13:53:40.317527 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4788 13:53:40.320858 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4789 13:53:40.327255 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4790 13:53:40.330740 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4791 13:53:40.331165 ==
4792 13:53:40.333973 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 13:53:40.337392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 13:53:40.337850 ==
4795 13:53:40.340348 DQS Delay:
4796 13:53:40.340765 DQS0 = 0, DQS1 = 0
4797 13:53:40.341096 DQM Delay:
4798 13:53:40.343845 DQM0 = 35, DQM1 = 29
4799 13:53:40.344265 DQ Delay:
4800 13:53:40.347353 DQ0 =40, DQ1 =28, DQ2 =24, DQ3 =32
4801 13:53:40.350343 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4802 13:53:40.353979 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4803 13:53:40.357347 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4804 13:53:40.357798
4805 13:53:40.358127
4806 13:53:40.367059 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4807 13:53:40.370327 CH1 RK1: MR19=808, MR18=3C5C
4808 13:53:40.373472 CH1_RK1: MR19=0x808, MR18=0x3C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4809 13:53:40.377219 [RxdqsGatingPostProcess] freq 600
4810 13:53:40.383753 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4811 13:53:40.386845 Pre-setting of DQS Precalculation
4812 13:53:40.390149 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4813 13:53:40.400336 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4814 13:53:40.406887 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4815 13:53:40.407305
4816 13:53:40.407663
4817 13:53:40.410364 [Calibration Summary] 1200 Mbps
4818 13:53:40.410780 CH 0, Rank 0
4819 13:53:40.413398 SW Impedance : PASS
4820 13:53:40.413862 DUTY Scan : NO K
4821 13:53:40.416699 ZQ Calibration : PASS
4822 13:53:40.420243 Jitter Meter : NO K
4823 13:53:40.420678 CBT Training : PASS
4824 13:53:40.423671 Write leveling : PASS
4825 13:53:40.426843 RX DQS gating : PASS
4826 13:53:40.427261 RX DQ/DQS(RDDQC) : PASS
4827 13:53:40.430196 TX DQ/DQS : PASS
4828 13:53:40.433432 RX DATLAT : PASS
4829 13:53:40.433877 RX DQ/DQS(Engine): PASS
4830 13:53:40.436915 TX OE : NO K
4831 13:53:40.437334 All Pass.
4832 13:53:40.437724
4833 13:53:40.439874 CH 0, Rank 1
4834 13:53:40.440288 SW Impedance : PASS
4835 13:53:40.443432 DUTY Scan : NO K
4836 13:53:40.443848 ZQ Calibration : PASS
4837 13:53:40.446765 Jitter Meter : NO K
4838 13:53:40.449867 CBT Training : PASS
4839 13:53:40.450280 Write leveling : PASS
4840 13:53:40.453410 RX DQS gating : PASS
4841 13:53:40.456702 RX DQ/DQS(RDDQC) : PASS
4842 13:53:40.457120 TX DQ/DQS : PASS
4843 13:53:40.460164 RX DATLAT : PASS
4844 13:53:40.462995 RX DQ/DQS(Engine): PASS
4845 13:53:40.463415 TX OE : NO K
4846 13:53:40.466487 All Pass.
4847 13:53:40.466924
4848 13:53:40.467343 CH 1, Rank 0
4849 13:53:40.469959 SW Impedance : PASS
4850 13:53:40.470397 DUTY Scan : NO K
4851 13:53:40.472918 ZQ Calibration : PASS
4852 13:53:40.476436 Jitter Meter : NO K
4853 13:53:40.476864 CBT Training : PASS
4854 13:53:40.479675 Write leveling : PASS
4855 13:53:40.483023 RX DQS gating : PASS
4856 13:53:40.483500 RX DQ/DQS(RDDQC) : PASS
4857 13:53:40.486209 TX DQ/DQS : PASS
4858 13:53:40.489748 RX DATLAT : PASS
4859 13:53:40.490237 RX DQ/DQS(Engine): PASS
4860 13:53:40.492986 TX OE : NO K
4861 13:53:40.493416 All Pass.
4862 13:53:40.493800
4863 13:53:40.496134 CH 1, Rank 1
4864 13:53:40.496553 SW Impedance : PASS
4865 13:53:40.499750 DUTY Scan : NO K
4866 13:53:40.502904 ZQ Calibration : PASS
4867 13:53:40.503322 Jitter Meter : NO K
4868 13:53:40.506399 CBT Training : PASS
4869 13:53:40.506815 Write leveling : PASS
4870 13:53:40.509464 RX DQS gating : PASS
4871 13:53:40.512791 RX DQ/DQS(RDDQC) : PASS
4872 13:53:40.513406 TX DQ/DQS : PASS
4873 13:53:40.516439 RX DATLAT : PASS
4874 13:53:40.519802 RX DQ/DQS(Engine): PASS
4875 13:53:40.520217 TX OE : NO K
4876 13:53:40.523041 All Pass.
4877 13:53:40.523457
4878 13:53:40.523784 DramC Write-DBI off
4879 13:53:40.526245 PER_BANK_REFRESH: Hybrid Mode
4880 13:53:40.526659 TX_TRACKING: ON
4881 13:53:40.536208 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4882 13:53:40.539631 [FAST_K] Save calibration result to emmc
4883 13:53:40.542907 dramc_set_vcore_voltage set vcore to 662500
4884 13:53:40.546181 Read voltage for 933, 3
4885 13:53:40.546626 Vio18 = 0
4886 13:53:40.549531 Vcore = 662500
4887 13:53:40.550024 Vdram = 0
4888 13:53:40.550401 Vddq = 0
4889 13:53:40.552742 Vmddr = 0
4890 13:53:40.556270 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4891 13:53:40.562731 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4892 13:53:40.563227 MEM_TYPE=3, freq_sel=17
4893 13:53:40.565864 sv_algorithm_assistance_LP4_1600
4894 13:53:40.569470 ============ PULL DRAM RESETB DOWN ============
4895 13:53:40.576205 ========== PULL DRAM RESETB DOWN end =========
4896 13:53:40.579280 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4897 13:53:40.582584 ===================================
4898 13:53:40.585660 LPDDR4 DRAM CONFIGURATION
4899 13:53:40.589072 ===================================
4900 13:53:40.589538 EX_ROW_EN[0] = 0x0
4901 13:53:40.592471 EX_ROW_EN[1] = 0x0
4902 13:53:40.595585 LP4Y_EN = 0x0
4903 13:53:40.596058 WORK_FSP = 0x0
4904 13:53:40.598957 WL = 0x3
4905 13:53:40.599377 RL = 0x3
4906 13:53:40.602521 BL = 0x2
4907 13:53:40.602938 RPST = 0x0
4908 13:53:40.605640 RD_PRE = 0x0
4909 13:53:40.606064 WR_PRE = 0x1
4910 13:53:40.608857 WR_PST = 0x0
4911 13:53:40.609277 DBI_WR = 0x0
4912 13:53:40.612245 DBI_RD = 0x0
4913 13:53:40.612681 OTF = 0x1
4914 13:53:40.615324 ===================================
4915 13:53:40.618884 ===================================
4916 13:53:40.622350 ANA top config
4917 13:53:40.625752 ===================================
4918 13:53:40.626175 DLL_ASYNC_EN = 0
4919 13:53:40.628888 ALL_SLAVE_EN = 1
4920 13:53:40.632132 NEW_RANK_MODE = 1
4921 13:53:40.635449 DLL_IDLE_MODE = 1
4922 13:53:40.638760 LP45_APHY_COMB_EN = 1
4923 13:53:40.639206 TX_ODT_DIS = 1
4924 13:53:40.641955 NEW_8X_MODE = 1
4925 13:53:40.645387 ===================================
4926 13:53:40.648855 ===================================
4927 13:53:40.651774 data_rate = 1866
4928 13:53:40.655373 CKR = 1
4929 13:53:40.658584 DQ_P2S_RATIO = 8
4930 13:53:40.662106 ===================================
4931 13:53:40.665165 CA_P2S_RATIO = 8
4932 13:53:40.665618 DQ_CA_OPEN = 0
4933 13:53:40.668457 DQ_SEMI_OPEN = 0
4934 13:53:40.671740 CA_SEMI_OPEN = 0
4935 13:53:40.675264 CA_FULL_RATE = 0
4936 13:53:40.678307 DQ_CKDIV4_EN = 1
4937 13:53:40.681734 CA_CKDIV4_EN = 1
4938 13:53:40.682202 CA_PREDIV_EN = 0
4939 13:53:40.684792 PH8_DLY = 0
4940 13:53:40.688163 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4941 13:53:40.691727 DQ_AAMCK_DIV = 4
4942 13:53:40.694845 CA_AAMCK_DIV = 4
4943 13:53:40.698261 CA_ADMCK_DIV = 4
4944 13:53:40.698741 DQ_TRACK_CA_EN = 0
4945 13:53:40.701328 CA_PICK = 933
4946 13:53:40.704566 CA_MCKIO = 933
4947 13:53:40.707946 MCKIO_SEMI = 0
4948 13:53:40.711583 PLL_FREQ = 3732
4949 13:53:40.714622 DQ_UI_PI_RATIO = 32
4950 13:53:40.717813 CA_UI_PI_RATIO = 0
4951 13:53:40.721191 ===================================
4952 13:53:40.724331 ===================================
4953 13:53:40.724779 memory_type:LPDDR4
4954 13:53:40.727970 GP_NUM : 10
4955 13:53:40.731066 SRAM_EN : 1
4956 13:53:40.731479 MD32_EN : 0
4957 13:53:40.734498 ===================================
4958 13:53:40.737774 [ANA_INIT] >>>>>>>>>>>>>>
4959 13:53:40.740765 <<<<<< [CONFIGURE PHASE]: ANA_TX
4960 13:53:40.744546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4961 13:53:40.747850 ===================================
4962 13:53:40.751237 data_rate = 1866,PCW = 0X8f00
4963 13:53:40.754196 ===================================
4964 13:53:40.757557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4965 13:53:40.761172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4966 13:53:40.767729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4967 13:53:40.770643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4968 13:53:40.774045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4969 13:53:40.780650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4970 13:53:40.781220 [ANA_INIT] flow start
4971 13:53:40.784002 [ANA_INIT] PLL >>>>>>>>
4972 13:53:40.787361 [ANA_INIT] PLL <<<<<<<<
4973 13:53:40.787774 [ANA_INIT] MIDPI >>>>>>>>
4974 13:53:40.790473 [ANA_INIT] MIDPI <<<<<<<<
4975 13:53:40.793657 [ANA_INIT] DLL >>>>>>>>
4976 13:53:40.794070 [ANA_INIT] flow end
4977 13:53:40.797096 ============ LP4 DIFF to SE enter ============
4978 13:53:40.803700 ============ LP4 DIFF to SE exit ============
4979 13:53:40.804119 [ANA_INIT] <<<<<<<<<<<<<
4980 13:53:40.807137 [Flow] Enable top DCM control >>>>>
4981 13:53:40.810305 [Flow] Enable top DCM control <<<<<
4982 13:53:40.813861 Enable DLL master slave shuffle
4983 13:53:40.820558 ==============================================================
4984 13:53:40.821154 Gating Mode config
4985 13:53:40.827199 ==============================================================
4986 13:53:40.830421 Config description:
4987 13:53:40.840257 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4988 13:53:40.846995 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4989 13:53:40.850145 SELPH_MODE 0: By rank 1: By Phase
4990 13:53:40.856965 ==============================================================
4991 13:53:40.860379 GAT_TRACK_EN = 1
4992 13:53:40.863480 RX_GATING_MODE = 2
4993 13:53:40.866632 RX_GATING_TRACK_MODE = 2
4994 13:53:40.867049 SELPH_MODE = 1
4995 13:53:40.869991 PICG_EARLY_EN = 1
4996 13:53:40.873437 VALID_LAT_VALUE = 1
4997 13:53:40.879584 ==============================================================
4998 13:53:40.883212 Enter into Gating configuration >>>>
4999 13:53:40.886231 Exit from Gating configuration <<<<
5000 13:53:40.889762 Enter into DVFS_PRE_config >>>>>
5001 13:53:40.899496 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5002 13:53:40.903038 Exit from DVFS_PRE_config <<<<<
5003 13:53:40.906431 Enter into PICG configuration >>>>
5004 13:53:40.909669 Exit from PICG configuration <<<<
5005 13:53:40.913025 [RX_INPUT] configuration >>>>>
5006 13:53:40.916221 [RX_INPUT] configuration <<<<<
5007 13:53:40.919623 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5008 13:53:40.926355 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5009 13:53:40.933058 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5010 13:53:40.939788 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5011 13:53:40.946143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5012 13:53:40.949379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5013 13:53:40.955870 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5014 13:53:40.959339 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5015 13:53:40.962390 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5016 13:53:40.965926 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5017 13:53:40.972683 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5018 13:53:40.975626 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 13:53:40.979043 ===================================
5020 13:53:40.982493 LPDDR4 DRAM CONFIGURATION
5021 13:53:40.985612 ===================================
5022 13:53:40.986083 EX_ROW_EN[0] = 0x0
5023 13:53:40.989227 EX_ROW_EN[1] = 0x0
5024 13:53:40.989794 LP4Y_EN = 0x0
5025 13:53:40.992350 WORK_FSP = 0x0
5026 13:53:40.992810 WL = 0x3
5027 13:53:40.995900 RL = 0x3
5028 13:53:40.996464 BL = 0x2
5029 13:53:40.999155 RPST = 0x0
5030 13:53:40.999589 RD_PRE = 0x0
5031 13:53:41.002368 WR_PRE = 0x1
5032 13:53:41.005538 WR_PST = 0x0
5033 13:53:41.005988 DBI_WR = 0x0
5034 13:53:41.009013 DBI_RD = 0x0
5035 13:53:41.009462 OTF = 0x1
5036 13:53:41.012323 ===================================
5037 13:53:41.015335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5038 13:53:41.022146 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5039 13:53:41.025589 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 13:53:41.028571 ===================================
5041 13:53:41.032173 LPDDR4 DRAM CONFIGURATION
5042 13:53:41.035370 ===================================
5043 13:53:41.035887 EX_ROW_EN[0] = 0x10
5044 13:53:41.038579 EX_ROW_EN[1] = 0x0
5045 13:53:41.039002 LP4Y_EN = 0x0
5046 13:53:41.041959 WORK_FSP = 0x0
5047 13:53:41.042419 WL = 0x3
5048 13:53:41.045189 RL = 0x3
5049 13:53:41.045706 BL = 0x2
5050 13:53:41.048196 RPST = 0x0
5051 13:53:41.051536 RD_PRE = 0x0
5052 13:53:41.052003 WR_PRE = 0x1
5053 13:53:41.055112 WR_PST = 0x0
5054 13:53:41.055636 DBI_WR = 0x0
5055 13:53:41.058147 DBI_RD = 0x0
5056 13:53:41.058596 OTF = 0x1
5057 13:53:41.061804 ===================================
5058 13:53:41.068110 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5059 13:53:41.072266 nWR fixed to 30
5060 13:53:41.075455 [ModeRegInit_LP4] CH0 RK0
5061 13:53:41.075985 [ModeRegInit_LP4] CH0 RK1
5062 13:53:41.078480 [ModeRegInit_LP4] CH1 RK0
5063 13:53:41.082089 [ModeRegInit_LP4] CH1 RK1
5064 13:53:41.082524 match AC timing 9
5065 13:53:41.088693 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5066 13:53:41.092061 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5067 13:53:41.095249 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5068 13:53:41.101685 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5069 13:53:41.105038 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5070 13:53:41.105454 ==
5071 13:53:41.108463 Dram Type= 6, Freq= 0, CH_0, rank 0
5072 13:53:41.111885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5073 13:53:41.112424 ==
5074 13:53:41.118704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5075 13:53:41.125217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5076 13:53:41.128266 [CA 0] Center 38 (8~69) winsize 62
5077 13:53:41.131743 [CA 1] Center 38 (8~69) winsize 62
5078 13:53:41.135466 [CA 2] Center 35 (5~65) winsize 61
5079 13:53:41.138489 [CA 3] Center 34 (4~65) winsize 62
5080 13:53:41.141816 [CA 4] Center 34 (4~64) winsize 61
5081 13:53:41.145001 [CA 5] Center 33 (3~64) winsize 62
5082 13:53:41.145419
5083 13:53:41.148589 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5084 13:53:41.149033
5085 13:53:41.152068 [CATrainingPosCal] consider 1 rank data
5086 13:53:41.155261 u2DelayCellTimex100 = 270/100 ps
5087 13:53:41.158546 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5088 13:53:41.161769 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5089 13:53:41.165109 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5090 13:53:41.168222 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5091 13:53:41.171679 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5092 13:53:41.175231 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5093 13:53:41.178295
5094 13:53:41.181763 CA PerBit enable=1, Macro0, CA PI delay=33
5095 13:53:41.182180
5096 13:53:41.184850 [CBTSetCACLKResult] CA Dly = 33
5097 13:53:41.185267 CS Dly: 7 (0~38)
5098 13:53:41.185625 ==
5099 13:53:41.188272 Dram Type= 6, Freq= 0, CH_0, rank 1
5100 13:53:41.191309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 13:53:41.191731 ==
5102 13:53:41.198024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5103 13:53:41.205187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5104 13:53:41.208176 [CA 0] Center 38 (8~69) winsize 62
5105 13:53:41.211546 [CA 1] Center 38 (8~69) winsize 62
5106 13:53:41.214703 [CA 2] Center 35 (5~66) winsize 62
5107 13:53:41.217959 [CA 3] Center 35 (5~66) winsize 62
5108 13:53:41.221289 [CA 4] Center 34 (4~65) winsize 62
5109 13:53:41.224762 [CA 5] Center 34 (4~64) winsize 61
5110 13:53:41.225205
5111 13:53:41.227937 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5112 13:53:41.228404
5113 13:53:41.231444 [CATrainingPosCal] consider 2 rank data
5114 13:53:41.234695 u2DelayCellTimex100 = 270/100 ps
5115 13:53:41.237881 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5116 13:53:41.241447 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5117 13:53:41.244734 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5118 13:53:41.247921 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5119 13:53:41.251508 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5120 13:53:41.258079 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5121 13:53:41.258660
5122 13:53:41.261512 CA PerBit enable=1, Macro0, CA PI delay=34
5123 13:53:41.262017
5124 13:53:41.264447 [CBTSetCACLKResult] CA Dly = 34
5125 13:53:41.264944 CS Dly: 7 (0~39)
5126 13:53:41.265302
5127 13:53:41.267911 ----->DramcWriteLeveling(PI) begin...
5128 13:53:41.268334 ==
5129 13:53:41.271032 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 13:53:41.277936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 13:53:41.278455 ==
5132 13:53:41.281297 Write leveling (Byte 0): 31 => 31
5133 13:53:41.281743 Write leveling (Byte 1): 33 => 33
5134 13:53:41.284569 DramcWriteLeveling(PI) end<-----
5135 13:53:41.285091
5136 13:53:41.287631 ==
5137 13:53:41.288083 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 13:53:41.295937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 13:53:41.296649 ==
5140 13:53:41.297710 [Gating] SW mode calibration
5141 13:53:41.304386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5142 13:53:41.307813 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5143 13:53:41.314206 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5144 13:53:41.317365 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5145 13:53:41.320587 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 13:53:41.327017 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 13:53:41.330685 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 13:53:41.333882 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 13:53:41.340374 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 13:53:41.343762 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5151 13:53:41.346946 0 15 0 | B1->B0 | 3131 2626 | 1 0 | (1 1) (1 0)
5152 13:53:41.353943 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5153 13:53:41.356908 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 13:53:41.360267 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 13:53:41.366790 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 13:53:41.370175 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 13:53:41.373222 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 13:53:41.380147 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 13:53:41.383467 1 0 0 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
5160 13:53:41.386517 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 13:53:41.393520 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 13:53:41.396433 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 13:53:41.399997 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 13:53:41.403119 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 13:53:41.410021 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 13:53:41.413075 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 13:53:41.416359 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5168 13:53:41.422984 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5169 13:53:41.426373 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 13:53:41.429587 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 13:53:41.436236 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 13:53:41.439576 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 13:53:41.443128 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 13:53:41.449530 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 13:53:41.452870 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 13:53:41.456114 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 13:53:41.463000 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 13:53:41.466117 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 13:53:41.469507 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 13:53:41.476210 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 13:53:41.479393 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 13:53:41.482781 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5183 13:53:41.489362 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5184 13:53:41.489441 Total UI for P1: 0, mck2ui 16
5185 13:53:41.496062 best dqsien dly found for B0: ( 1, 2, 28)
5186 13:53:41.499461 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5187 13:53:41.502344 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 13:53:41.506015 Total UI for P1: 0, mck2ui 16
5189 13:53:41.509114 best dqsien dly found for B1: ( 1, 3, 2)
5190 13:53:41.512474 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5191 13:53:41.515952 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5192 13:53:41.516027
5193 13:53:41.522598 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5194 13:53:41.525781 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5195 13:53:41.525870 [Gating] SW calibration Done
5196 13:53:41.529090 ==
5197 13:53:41.529158 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 13:53:41.535691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 13:53:41.535762 ==
5200 13:53:41.535822 RX Vref Scan: 0
5201 13:53:41.535879
5202 13:53:41.539000 RX Vref 0 -> 0, step: 1
5203 13:53:41.539066
5204 13:53:41.542385 RX Delay -80 -> 252, step: 8
5205 13:53:41.545756 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5206 13:53:41.548915 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5207 13:53:41.552272 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5208 13:53:41.555684 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5209 13:53:41.562377 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5210 13:53:41.565663 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5211 13:53:41.568728 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5212 13:53:41.571975 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5213 13:53:41.575459 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5214 13:53:41.582004 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5215 13:53:41.585410 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5216 13:53:41.588606 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5217 13:53:41.591769 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5218 13:53:41.598409 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5219 13:53:41.601609 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5220 13:53:41.605048 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5221 13:53:41.605165 ==
5222 13:53:41.608243 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 13:53:41.611558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 13:53:41.611649 ==
5225 13:53:41.615021 DQS Delay:
5226 13:53:41.615118 DQS0 = 0, DQS1 = 0
5227 13:53:41.615210 DQM Delay:
5228 13:53:41.618317 DQM0 = 94, DQM1 = 83
5229 13:53:41.618404 DQ Delay:
5230 13:53:41.621501 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5231 13:53:41.624845 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =103
5232 13:53:41.628313 DQ8 =79, DQ9 =67, DQ10 =83, DQ11 =75
5233 13:53:41.631339 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5234 13:53:41.631418
5235 13:53:41.631487
5236 13:53:41.634702 ==
5237 13:53:41.634780 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 13:53:41.641293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 13:53:41.641372 ==
5240 13:53:41.641487
5241 13:53:41.641554
5242 13:53:41.644851 TX Vref Scan disable
5243 13:53:41.644924 == TX Byte 0 ==
5244 13:53:41.647856 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5245 13:53:41.654552 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5246 13:53:41.654637 == TX Byte 1 ==
5247 13:53:41.658030 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5248 13:53:41.664442 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5249 13:53:41.664518 ==
5250 13:53:41.667706 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 13:53:41.671095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 13:53:41.671175 ==
5253 13:53:41.671239
5254 13:53:41.671299
5255 13:53:41.674526 TX Vref Scan disable
5256 13:53:41.677663 == TX Byte 0 ==
5257 13:53:41.681084 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5258 13:53:41.684452 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5259 13:53:41.687656 == TX Byte 1 ==
5260 13:53:41.690849 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5261 13:53:41.694342 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5262 13:53:41.694415
5263 13:53:41.697578 [DATLAT]
5264 13:53:41.697653 Freq=933, CH0 RK0
5265 13:53:41.697714
5266 13:53:41.700713 DATLAT Default: 0xd
5267 13:53:41.700799 0, 0xFFFF, sum = 0
5268 13:53:41.703940 1, 0xFFFF, sum = 0
5269 13:53:41.704018 2, 0xFFFF, sum = 0
5270 13:53:41.707464 3, 0xFFFF, sum = 0
5271 13:53:41.707544 4, 0xFFFF, sum = 0
5272 13:53:41.710850 5, 0xFFFF, sum = 0
5273 13:53:41.710926 6, 0xFFFF, sum = 0
5274 13:53:41.714316 7, 0xFFFF, sum = 0
5275 13:53:41.714393 8, 0xFFFF, sum = 0
5276 13:53:41.717497 9, 0xFFFF, sum = 0
5277 13:53:41.717587 10, 0x0, sum = 1
5278 13:53:41.720564 11, 0x0, sum = 2
5279 13:53:41.720631 12, 0x0, sum = 3
5280 13:53:41.724066 13, 0x0, sum = 4
5281 13:53:41.724139 best_step = 11
5282 13:53:41.724199
5283 13:53:41.724256 ==
5284 13:53:41.727674 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 13:53:41.730709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 13:53:41.734292 ==
5287 13:53:41.734377 RX Vref Scan: 1
5288 13:53:41.734451
5289 13:53:41.737383 RX Vref 0 -> 0, step: 1
5290 13:53:41.737498
5291 13:53:41.740867 RX Delay -77 -> 252, step: 4
5292 13:53:41.740938
5293 13:53:41.743904 Set Vref, RX VrefLevel [Byte0]: 61
5294 13:53:41.747463 [Byte1]: 47
5295 13:53:41.747537
5296 13:53:41.750579 Final RX Vref Byte 0 = 61 to rank0
5297 13:53:41.754029 Final RX Vref Byte 1 = 47 to rank0
5298 13:53:41.757359 Final RX Vref Byte 0 = 61 to rank1
5299 13:53:41.760717 Final RX Vref Byte 1 = 47 to rank1==
5300 13:53:41.763920 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 13:53:41.767445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 13:53:41.767517 ==
5303 13:53:41.770502 DQS Delay:
5304 13:53:41.770612 DQS0 = 0, DQS1 = 0
5305 13:53:41.770712 DQM Delay:
5306 13:53:41.773922 DQM0 = 95, DQM1 = 82
5307 13:53:41.774025 DQ Delay:
5308 13:53:41.777126 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5309 13:53:41.780502 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5310 13:53:41.783632 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5311 13:53:41.787169 DQ12 =86, DQ13 =88, DQ14 =92, DQ15 =92
5312 13:53:41.787246
5313 13:53:41.787308
5314 13:53:41.797141 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5315 13:53:41.800224 CH0 RK0: MR19=505, MR18=1818
5316 13:53:41.803464 CH0_RK0: MR19=0x505, MR18=0x1818, DQSOSC=414, MR23=63, INC=63, DEC=42
5317 13:53:41.803534
5318 13:53:41.806900 ----->DramcWriteLeveling(PI) begin...
5319 13:53:41.810271 ==
5320 13:53:41.813633 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 13:53:41.816758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 13:53:41.816842 ==
5323 13:53:41.820258 Write leveling (Byte 0): 34 => 34
5324 13:53:41.823394 Write leveling (Byte 1): 28 => 28
5325 13:53:41.826860 DramcWriteLeveling(PI) end<-----
5326 13:53:41.826942
5327 13:53:41.827006 ==
5328 13:53:41.829980 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 13:53:41.833530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 13:53:41.833618 ==
5331 13:53:41.836680 [Gating] SW mode calibration
5332 13:53:41.843133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5333 13:53:41.850179 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5334 13:53:41.853341 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5335 13:53:41.856524 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 13:53:41.863091 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 13:53:41.866448 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 13:53:41.869977 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 13:53:41.876597 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 13:53:41.879620 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5341 13:53:41.883042 0 14 28 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (0 0)
5342 13:53:41.889690 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (1 0)
5343 13:53:41.892887 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 13:53:41.896520 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 13:53:41.902442 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 13:53:41.906091 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 13:53:41.909388 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 13:53:41.915913 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 13:53:41.919114 0 15 28 | B1->B0 | 2a2a 3c3c | 0 0 | (0 0) (0 0)
5350 13:53:41.922512 1 0 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5351 13:53:41.929097 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 13:53:41.932622 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 13:53:41.935595 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 13:53:41.942540 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 13:53:41.945681 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 13:53:41.949079 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5357 13:53:41.955622 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5358 13:53:41.959117 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5359 13:53:41.962563 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 13:53:41.965814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 13:53:41.971941 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 13:53:41.975421 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 13:53:41.981871 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 13:53:41.985241 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 13:53:41.988738 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 13:53:41.992026 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 13:53:41.998716 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 13:53:42.001742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 13:53:42.005143 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 13:53:42.011921 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 13:53:42.015060 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 13:53:42.018372 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 13:53:42.024920 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5374 13:53:42.028161 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5375 13:53:42.031537 Total UI for P1: 0, mck2ui 16
5376 13:53:42.034835 best dqsien dly found for B0: ( 1, 2, 28)
5377 13:53:42.038433 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 13:53:42.041375 Total UI for P1: 0, mck2ui 16
5379 13:53:42.044768 best dqsien dly found for B1: ( 1, 3, 0)
5380 13:53:42.048226 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5381 13:53:42.051333 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5382 13:53:42.054528
5383 13:53:42.057836 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5384 13:53:42.061382 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5385 13:53:42.064539 [Gating] SW calibration Done
5386 13:53:42.064608 ==
5387 13:53:42.067740 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 13:53:42.071160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 13:53:42.071229 ==
5390 13:53:42.074184 RX Vref Scan: 0
5391 13:53:42.074252
5392 13:53:42.074310 RX Vref 0 -> 0, step: 1
5393 13:53:42.074365
5394 13:53:42.077817 RX Delay -80 -> 252, step: 8
5395 13:53:42.080806 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5396 13:53:42.084265 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5397 13:53:42.090907 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5398 13:53:42.094105 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5399 13:53:42.097584 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5400 13:53:42.100824 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5401 13:53:42.104020 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5402 13:53:42.110638 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5403 13:53:42.113794 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5404 13:53:42.117096 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5405 13:53:42.120670 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5406 13:53:42.124036 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5407 13:53:42.130486 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5408 13:53:42.133831 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5409 13:53:42.137001 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5410 13:53:42.140439 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5411 13:53:42.140511 ==
5412 13:53:42.143608 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 13:53:42.150548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 13:53:42.150629 ==
5415 13:53:42.150692 DQS Delay:
5416 13:53:42.150781 DQS0 = 0, DQS1 = 0
5417 13:53:42.153645 DQM Delay:
5418 13:53:42.153741 DQM0 = 92, DQM1 = 81
5419 13:53:42.156830 DQ Delay:
5420 13:53:42.160176 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5421 13:53:42.163599 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5422 13:53:42.166762 DQ8 =75, DQ9 =63, DQ10 =87, DQ11 =71
5423 13:53:42.169884 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5424 13:53:42.169979
5425 13:53:42.170042
5426 13:53:42.170134 ==
5427 13:53:42.173460 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 13:53:42.176595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 13:53:42.176691 ==
5430 13:53:42.176783
5431 13:53:42.176873
5432 13:53:42.179880 TX Vref Scan disable
5433 13:53:42.183062 == TX Byte 0 ==
5434 13:53:42.186465 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5435 13:53:42.189902 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5436 13:53:42.193137 == TX Byte 1 ==
5437 13:53:42.196155 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5438 13:53:42.199767 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5439 13:53:42.199840 ==
5440 13:53:42.203107 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 13:53:42.206646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 13:53:42.206716 ==
5443 13:53:42.209679
5444 13:53:42.209748
5445 13:53:42.209805 TX Vref Scan disable
5446 13:53:42.213194 == TX Byte 0 ==
5447 13:53:42.216604 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5448 13:53:42.223110 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5449 13:53:42.223260 == TX Byte 1 ==
5450 13:53:42.226214 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5451 13:53:42.232770 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5452 13:53:42.232840
5453 13:53:42.232901 [DATLAT]
5454 13:53:42.232957 Freq=933, CH0 RK1
5455 13:53:42.233013
5456 13:53:42.235979 DATLAT Default: 0xb
5457 13:53:42.239414 0, 0xFFFF, sum = 0
5458 13:53:42.239487 1, 0xFFFF, sum = 0
5459 13:53:42.242686 2, 0xFFFF, sum = 0
5460 13:53:42.242754 3, 0xFFFF, sum = 0
5461 13:53:42.246218 4, 0xFFFF, sum = 0
5462 13:53:42.246328 5, 0xFFFF, sum = 0
5463 13:53:42.249215 6, 0xFFFF, sum = 0
5464 13:53:42.249327 7, 0xFFFF, sum = 0
5465 13:53:42.252828 8, 0xFFFF, sum = 0
5466 13:53:42.252902 9, 0xFFFF, sum = 0
5467 13:53:42.256172 10, 0x0, sum = 1
5468 13:53:42.256277 11, 0x0, sum = 2
5469 13:53:42.259493 12, 0x0, sum = 3
5470 13:53:42.259562 13, 0x0, sum = 4
5471 13:53:42.259655 best_step = 11
5472 13:53:42.262865
5473 13:53:42.262932 ==
5474 13:53:42.265938 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 13:53:42.269064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 13:53:42.269158 ==
5477 13:53:42.269222 RX Vref Scan: 0
5478 13:53:42.269311
5479 13:53:42.272486 RX Vref 0 -> 0, step: 1
5480 13:53:42.272566
5481 13:53:42.276035 RX Delay -77 -> 252, step: 4
5482 13:53:42.282634 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5483 13:53:42.285801 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5484 13:53:42.288900 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5485 13:53:42.292332 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5486 13:53:42.295723 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5487 13:53:42.298948 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5488 13:53:42.305547 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5489 13:53:42.308948 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5490 13:53:42.312276 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5491 13:53:42.315516 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5492 13:53:42.318890 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5493 13:53:42.325709 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5494 13:53:42.328900 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5495 13:53:42.331965 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5496 13:53:42.335571 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5497 13:53:42.338877 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5498 13:53:42.341924 ==
5499 13:53:42.341995 Dram Type= 6, Freq= 0, CH_0, rank 1
5500 13:53:42.348608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 13:53:42.348716 ==
5502 13:53:42.348812 DQS Delay:
5503 13:53:42.351884 DQS0 = 0, DQS1 = 0
5504 13:53:42.351983 DQM Delay:
5505 13:53:42.355313 DQM0 = 92, DQM1 = 83
5506 13:53:42.355390 DQ Delay:
5507 13:53:42.358489 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5508 13:53:42.361806 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5509 13:53:42.365177 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5510 13:53:42.368464 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5511 13:53:42.368540
5512 13:53:42.368603
5513 13:53:42.375138 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5514 13:53:42.378303 CH0 RK1: MR19=505, MR18=2E0F
5515 13:53:42.385131 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5516 13:53:42.388408 [RxdqsGatingPostProcess] freq 933
5517 13:53:42.394908 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5518 13:53:42.398199 best DQS0 dly(2T, 0.5T) = (0, 10)
5519 13:53:42.398271 best DQS1 dly(2T, 0.5T) = (0, 11)
5520 13:53:42.401690 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5521 13:53:42.404779 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5522 13:53:42.407922 best DQS0 dly(2T, 0.5T) = (0, 10)
5523 13:53:42.411370 best DQS1 dly(2T, 0.5T) = (0, 11)
5524 13:53:42.414736 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5525 13:53:42.418254 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5526 13:53:42.421237 Pre-setting of DQS Precalculation
5527 13:53:42.428124 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5528 13:53:42.428231 ==
5529 13:53:42.431106 Dram Type= 6, Freq= 0, CH_1, rank 0
5530 13:53:42.434702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 13:53:42.434778 ==
5532 13:53:42.441347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5533 13:53:42.444414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5534 13:53:42.448618 [CA 0] Center 37 (7~68) winsize 62
5535 13:53:42.452006 [CA 1] Center 37 (7~68) winsize 62
5536 13:53:42.455232 [CA 2] Center 34 (5~64) winsize 60
5537 13:53:42.458640 [CA 3] Center 34 (5~64) winsize 60
5538 13:53:42.461710 [CA 4] Center 34 (5~64) winsize 60
5539 13:53:42.465332 [CA 5] Center 34 (4~64) winsize 61
5540 13:53:42.465427
5541 13:53:42.468305 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5542 13:53:42.468403
5543 13:53:42.471967 [CATrainingPosCal] consider 1 rank data
5544 13:53:42.475112 u2DelayCellTimex100 = 270/100 ps
5545 13:53:42.478557 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5546 13:53:42.484933 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5547 13:53:42.488158 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5548 13:53:42.491603 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5549 13:53:42.494974 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5550 13:53:42.498495 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5551 13:53:42.498567
5552 13:53:42.501470 CA PerBit enable=1, Macro0, CA PI delay=34
5553 13:53:42.501560
5554 13:53:42.504796 [CBTSetCACLKResult] CA Dly = 34
5555 13:53:42.508353 CS Dly: 6 (0~37)
5556 13:53:42.508432 ==
5557 13:53:42.511616 Dram Type= 6, Freq= 0, CH_1, rank 1
5558 13:53:42.514689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 13:53:42.514763 ==
5560 13:53:42.521396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5561 13:53:42.524493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5562 13:53:42.528413 [CA 0] Center 38 (8~68) winsize 61
5563 13:53:42.531996 [CA 1] Center 37 (7~68) winsize 62
5564 13:53:42.535192 [CA 2] Center 35 (5~65) winsize 61
5565 13:53:42.538646 [CA 3] Center 34 (4~64) winsize 61
5566 13:53:42.541828 [CA 4] Center 34 (4~65) winsize 62
5567 13:53:42.545006 [CA 5] Center 33 (3~64) winsize 62
5568 13:53:42.545101
5569 13:53:42.548633 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5570 13:53:42.548704
5571 13:53:42.551801 [CATrainingPosCal] consider 2 rank data
5572 13:53:42.555194 u2DelayCellTimex100 = 270/100 ps
5573 13:53:42.558423 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5574 13:53:42.564969 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5575 13:53:42.568124 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5576 13:53:42.571673 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5577 13:53:42.575005 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5578 13:53:42.578117 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5579 13:53:42.578185
5580 13:53:42.581258 CA PerBit enable=1, Macro0, CA PI delay=34
5581 13:53:42.581353
5582 13:53:42.584882 [CBTSetCACLKResult] CA Dly = 34
5583 13:53:42.587848 CS Dly: 7 (0~39)
5584 13:53:42.587946
5585 13:53:42.591232 ----->DramcWriteLeveling(PI) begin...
5586 13:53:42.591301 ==
5587 13:53:42.594735 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 13:53:42.597935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 13:53:42.598023 ==
5590 13:53:42.601157 Write leveling (Byte 0): 28 => 28
5591 13:53:42.604332 Write leveling (Byte 1): 28 => 28
5592 13:53:42.607869 DramcWriteLeveling(PI) end<-----
5593 13:53:42.607937
5594 13:53:42.607997 ==
5595 13:53:42.611184 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 13:53:42.614322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 13:53:42.614395 ==
5598 13:53:42.617692 [Gating] SW mode calibration
5599 13:53:42.624142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5600 13:53:42.630960 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5601 13:53:42.634315 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5602 13:53:42.637451 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 13:53:42.644073 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 13:53:42.647805 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 13:53:42.651068 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 13:53:42.657680 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 13:53:42.660831 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 13:53:42.664180 0 14 28 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
5609 13:53:42.670913 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5610 13:53:42.674290 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 13:53:42.677614 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 13:53:42.684117 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 13:53:42.687275 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 13:53:42.690710 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 13:53:42.697258 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 13:53:42.700372 0 15 28 | B1->B0 | 3636 3737 | 0 1 | (0 0) (0 0)
5617 13:53:42.704066 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 13:53:42.710213 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 13:53:42.713760 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 13:53:42.716866 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 13:53:42.723693 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 13:53:42.727043 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 13:53:42.730070 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:53:42.736952 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5625 13:53:42.740050 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 13:53:42.743631 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 13:53:42.749932 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 13:53:42.753566 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 13:53:42.756579 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:53:42.763137 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:53:42.766474 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:53:42.770080 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:53:42.776440 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:53:42.779774 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:53:42.783044 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:53:42.789843 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:53:42.793147 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 13:53:42.796349 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 13:53:42.803244 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 13:53:42.806379 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 13:53:42.809854 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 13:53:42.813028 Total UI for P1: 0, mck2ui 16
5643 13:53:42.816709 best dqsien dly found for B0: ( 1, 2, 30)
5644 13:53:42.819619 Total UI for P1: 0, mck2ui 16
5645 13:53:42.823111 best dqsien dly found for B1: ( 1, 2, 30)
5646 13:53:42.826210 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5647 13:53:42.829714 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5648 13:53:42.829783
5649 13:53:42.832787 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5650 13:53:42.839469 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5651 13:53:42.839553 [Gating] SW calibration Done
5652 13:53:42.839617 ==
5653 13:53:42.842959 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 13:53:42.849496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 13:53:42.849591 ==
5656 13:53:42.849677 RX Vref Scan: 0
5657 13:53:42.849830
5658 13:53:42.852838 RX Vref 0 -> 0, step: 1
5659 13:53:42.852954
5660 13:53:42.856331 RX Delay -80 -> 252, step: 8
5661 13:53:42.859518 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5662 13:53:42.862978 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5663 13:53:42.866018 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5664 13:53:42.869210 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5665 13:53:42.876037 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5666 13:53:42.879359 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5667 13:53:42.882665 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5668 13:53:42.885982 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5669 13:53:42.889406 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5670 13:53:42.895861 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5671 13:53:42.899190 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5672 13:53:42.902471 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5673 13:53:42.905832 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5674 13:53:42.909218 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5675 13:53:42.915669 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5676 13:53:42.919269 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5677 13:53:42.919346 ==
5678 13:53:42.922368 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 13:53:42.925545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 13:53:42.925620 ==
5681 13:53:42.925688 DQS Delay:
5682 13:53:42.929085 DQS0 = 0, DQS1 = 0
5683 13:53:42.929154 DQM Delay:
5684 13:53:42.932234 DQM0 = 95, DQM1 = 85
5685 13:53:42.932302 DQ Delay:
5686 13:53:42.935801 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5687 13:53:42.938928 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5688 13:53:42.942288 DQ8 =75, DQ9 =79, DQ10 =83, DQ11 =83
5689 13:53:42.945440 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5690 13:53:42.945534
5691 13:53:42.945597
5692 13:53:42.945656 ==
5693 13:53:42.948885 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 13:53:42.955488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 13:53:42.955567 ==
5696 13:53:42.955661
5697 13:53:42.955724
5698 13:53:42.955786 TX Vref Scan disable
5699 13:53:42.958618 == TX Byte 0 ==
5700 13:53:42.961998 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5701 13:53:42.968726 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5702 13:53:42.968806 == TX Byte 1 ==
5703 13:53:42.972130 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5704 13:53:42.978617 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5705 13:53:42.978702 ==
5706 13:53:42.981704 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 13:53:42.985191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 13:53:42.985274 ==
5709 13:53:42.985338
5710 13:53:42.985398
5711 13:53:42.988601 TX Vref Scan disable
5712 13:53:42.991899 == TX Byte 0 ==
5713 13:53:42.995342 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5714 13:53:42.998428 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5715 13:53:43.001749 == TX Byte 1 ==
5716 13:53:43.005026 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5717 13:53:43.008348 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5718 13:53:43.008452
5719 13:53:43.008544 [DATLAT]
5720 13:53:43.011590 Freq=933, CH1 RK0
5721 13:53:43.011660
5722 13:53:43.011724 DATLAT Default: 0xd
5723 13:53:43.015387 0, 0xFFFF, sum = 0
5724 13:53:43.018466 1, 0xFFFF, sum = 0
5725 13:53:43.018585 2, 0xFFFF, sum = 0
5726 13:53:43.021774 3, 0xFFFF, sum = 0
5727 13:53:43.021854 4, 0xFFFF, sum = 0
5728 13:53:43.024598 5, 0xFFFF, sum = 0
5729 13:53:43.024683 6, 0xFFFF, sum = 0
5730 13:53:43.028033 7, 0xFFFF, sum = 0
5731 13:53:43.028157 8, 0xFFFF, sum = 0
5732 13:53:43.031441 9, 0xFFFF, sum = 0
5733 13:53:43.031510 10, 0x0, sum = 1
5734 13:53:43.034692 11, 0x0, sum = 2
5735 13:53:43.034798 12, 0x0, sum = 3
5736 13:53:43.038076 13, 0x0, sum = 4
5737 13:53:43.038147 best_step = 11
5738 13:53:43.038206
5739 13:53:43.038266 ==
5740 13:53:43.041261 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 13:53:43.044485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 13:53:43.048028 ==
5743 13:53:43.048128 RX Vref Scan: 1
5744 13:53:43.048216
5745 13:53:43.051132 RX Vref 0 -> 0, step: 1
5746 13:53:43.051249
5747 13:53:43.051341 RX Delay -69 -> 252, step: 4
5748 13:53:43.054691
5749 13:53:43.054782 Set Vref, RX VrefLevel [Byte0]: 52
5750 13:53:43.060883 [Byte1]: 50
5751 13:53:43.060971
5752 13:53:43.064398 Final RX Vref Byte 0 = 52 to rank0
5753 13:53:43.067687 Final RX Vref Byte 1 = 50 to rank0
5754 13:53:43.070859 Final RX Vref Byte 0 = 52 to rank1
5755 13:53:43.074191 Final RX Vref Byte 1 = 50 to rank1==
5756 13:53:43.077642 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 13:53:43.080914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 13:53:43.081010 ==
5759 13:53:43.084294 DQS Delay:
5760 13:53:43.084404 DQS0 = 0, DQS1 = 0
5761 13:53:43.084498 DQM Delay:
5762 13:53:43.087479 DQM0 = 95, DQM1 = 88
5763 13:53:43.087573 DQ Delay:
5764 13:53:43.090537 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =92
5765 13:53:43.094124 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =92
5766 13:53:43.097379 DQ8 =78, DQ9 =80, DQ10 =86, DQ11 =82
5767 13:53:43.100863 DQ12 =100, DQ13 =92, DQ14 =98, DQ15 =92
5768 13:53:43.100944
5769 13:53:43.101008
5770 13:53:43.110542 [DQSOSCAuto] RK0, (LSB)MR18= 0x20b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5771 13:53:43.113730 CH1 RK0: MR19=505, MR18=20B
5772 13:53:43.117417 CH1_RK0: MR19=0x505, MR18=0x20B, DQSOSC=418, MR23=63, INC=62, DEC=41
5773 13:53:43.117518
5774 13:53:43.120611 ----->DramcWriteLeveling(PI) begin...
5775 13:53:43.123930 ==
5776 13:53:43.127118 Dram Type= 6, Freq= 0, CH_1, rank 1
5777 13:53:43.130135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 13:53:43.130208 ==
5779 13:53:43.133435 Write leveling (Byte 0): 26 => 26
5780 13:53:43.137187 Write leveling (Byte 1): 28 => 28
5781 13:53:43.140286 DramcWriteLeveling(PI) end<-----
5782 13:53:43.140356
5783 13:53:43.140417 ==
5784 13:53:43.143478 Dram Type= 6, Freq= 0, CH_1, rank 1
5785 13:53:43.146946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 13:53:43.147022 ==
5787 13:53:43.150213 [Gating] SW mode calibration
5788 13:53:43.156843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5789 13:53:43.163583 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5790 13:53:43.166843 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 13:53:43.170027 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 13:53:43.176649 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 13:53:43.179958 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 13:53:43.183281 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 13:53:43.189917 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 13:53:43.193364 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5797 13:53:43.196567 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5798 13:53:43.202958 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 13:53:43.206401 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 13:53:43.209815 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 13:53:43.216383 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 13:53:43.219599 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 13:53:43.222793 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 13:53:43.229449 0 15 24 | B1->B0 | 2727 3232 | 0 1 | (0 0) (0 0)
5805 13:53:43.232925 0 15 28 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
5806 13:53:43.236103 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 13:53:43.242555 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 13:53:43.246125 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 13:53:43.249363 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 13:53:43.252827 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 13:53:43.259037 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 13:53:43.262452 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5813 13:53:43.268978 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5814 13:53:43.272237 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 13:53:43.275476 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 13:53:43.282163 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 13:53:43.285527 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 13:53:43.289006 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 13:53:43.292306 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 13:53:43.298989 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 13:53:43.302271 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 13:53:43.305590 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 13:53:43.312238 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 13:53:43.315330 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 13:53:43.318802 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 13:53:43.325134 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 13:53:43.328703 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5828 13:53:43.331858 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5829 13:53:43.338564 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5830 13:53:43.341817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 13:53:43.345175 Total UI for P1: 0, mck2ui 16
5832 13:53:43.348539 best dqsien dly found for B0: ( 1, 2, 24)
5833 13:53:43.351504 Total UI for P1: 0, mck2ui 16
5834 13:53:43.355010 best dqsien dly found for B1: ( 1, 2, 28)
5835 13:53:43.358243 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5836 13:53:43.361767 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5837 13:53:43.361851
5838 13:53:43.364841 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5839 13:53:43.371364 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5840 13:53:43.371448 [Gating] SW calibration Done
5841 13:53:43.371535 ==
5842 13:53:43.374913 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 13:53:43.381518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 13:53:43.381618 ==
5845 13:53:43.381704 RX Vref Scan: 0
5846 13:53:43.381801
5847 13:53:43.385060 RX Vref 0 -> 0, step: 1
5848 13:53:43.385144
5849 13:53:43.388107 RX Delay -80 -> 252, step: 8
5850 13:53:43.391436 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5851 13:53:43.394914 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5852 13:53:43.398147 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5853 13:53:43.401202 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5854 13:53:43.408033 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5855 13:53:43.411393 iDelay=208, Bit 5, Center 103 (8 ~ 199) 192
5856 13:53:43.414541 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5857 13:53:43.417935 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5858 13:53:43.421126 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5859 13:53:43.427765 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5860 13:53:43.431143 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5861 13:53:43.434467 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5862 13:53:43.437557 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5863 13:53:43.441039 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5864 13:53:43.444523 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5865 13:53:43.451063 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5866 13:53:43.451148 ==
5867 13:53:43.454241 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 13:53:43.457732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 13:53:43.457817 ==
5870 13:53:43.457904 DQS Delay:
5871 13:53:43.460865 DQS0 = 0, DQS1 = 0
5872 13:53:43.460966 DQM Delay:
5873 13:53:43.464257 DQM0 = 93, DQM1 = 88
5874 13:53:43.464341 DQ Delay:
5875 13:53:43.467417 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =91
5876 13:53:43.470863 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5877 13:53:43.474019 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5878 13:53:43.477426 DQ12 =99, DQ13 =91, DQ14 =95, DQ15 =95
5879 13:53:43.477559
5880 13:53:43.477657
5881 13:53:43.477733 ==
5882 13:53:43.480538 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 13:53:43.484061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 13:53:43.487144 ==
5885 13:53:43.487241
5886 13:53:43.487335
5887 13:53:43.487410 TX Vref Scan disable
5888 13:53:43.490689 == TX Byte 0 ==
5889 13:53:43.494111 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5890 13:53:43.497635 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5891 13:53:43.500725 == TX Byte 1 ==
5892 13:53:43.504074 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5893 13:53:43.507483 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5894 13:53:43.510538 ==
5895 13:53:43.513683 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 13:53:43.517365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 13:53:43.517448 ==
5898 13:53:43.517523
5899 13:53:43.517585
5900 13:53:43.520516 TX Vref Scan disable
5901 13:53:43.520598 == TX Byte 0 ==
5902 13:53:43.527131 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5903 13:53:43.530361 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5904 13:53:43.530444 == TX Byte 1 ==
5905 13:53:43.537176 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5906 13:53:43.540535 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5907 13:53:43.540617
5908 13:53:43.540681 [DATLAT]
5909 13:53:43.543869 Freq=933, CH1 RK1
5910 13:53:43.543952
5911 13:53:43.544016 DATLAT Default: 0xb
5912 13:53:43.546974 0, 0xFFFF, sum = 0
5913 13:53:43.547058 1, 0xFFFF, sum = 0
5914 13:53:43.550512 2, 0xFFFF, sum = 0
5915 13:53:43.550599 3, 0xFFFF, sum = 0
5916 13:53:43.553837 4, 0xFFFF, sum = 0
5917 13:53:43.553921 5, 0xFFFF, sum = 0
5918 13:53:43.556789 6, 0xFFFF, sum = 0
5919 13:53:43.556877 7, 0xFFFF, sum = 0
5920 13:53:43.560127 8, 0xFFFF, sum = 0
5921 13:53:43.563695 9, 0xFFFF, sum = 0
5922 13:53:43.563783 10, 0x0, sum = 1
5923 13:53:43.563873 11, 0x0, sum = 2
5924 13:53:43.566789 12, 0x0, sum = 3
5925 13:53:43.566877 13, 0x0, sum = 4
5926 13:53:43.570179 best_step = 11
5927 13:53:43.570264
5928 13:53:43.570352 ==
5929 13:53:43.573557 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 13:53:43.577097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 13:53:43.577185 ==
5932 13:53:43.580430 RX Vref Scan: 0
5933 13:53:43.580516
5934 13:53:43.580620 RX Vref 0 -> 0, step: 1
5935 13:53:43.580721
5936 13:53:43.583503 RX Delay -69 -> 252, step: 4
5937 13:53:43.591002 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5938 13:53:43.594258 iDelay=203, Bit 1, Center 84 (-13 ~ 182) 196
5939 13:53:43.597705 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5940 13:53:43.600768 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5941 13:53:43.604257 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5942 13:53:43.610826 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5943 13:53:43.614268 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5944 13:53:43.617598 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5945 13:53:43.620587 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5946 13:53:43.624131 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5947 13:53:43.627537 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5948 13:53:43.634040 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5949 13:53:43.637077 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5950 13:53:43.640524 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5951 13:53:43.644007 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5952 13:53:43.647139 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5953 13:53:43.647244 ==
5954 13:53:43.650331 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 13:53:43.657156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 13:53:43.657262 ==
5957 13:53:43.657357 DQS Delay:
5958 13:53:43.660313 DQS0 = 0, DQS1 = 0
5959 13:53:43.660415 DQM Delay:
5960 13:53:43.660507 DQM0 = 91, DQM1 = 90
5961 13:53:43.663845 DQ Delay:
5962 13:53:43.666881 DQ0 =96, DQ1 =84, DQ2 =82, DQ3 =88
5963 13:53:43.670579 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =88
5964 13:53:43.673555 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =84
5965 13:53:43.677012 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5966 13:53:43.677112
5967 13:53:43.677203
5968 13:53:43.684007 [DQSOSCAuto] RK1, (LSB)MR18= 0x1326, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
5969 13:53:43.687916 CH1 RK1: MR19=505, MR18=1326
5970 13:53:43.693795 CH1_RK1: MR19=0x505, MR18=0x1326, DQSOSC=409, MR23=63, INC=64, DEC=43
5971 13:53:43.696886 [RxdqsGatingPostProcess] freq 933
5972 13:53:43.700437 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5973 13:53:43.703928 best DQS0 dly(2T, 0.5T) = (0, 10)
5974 13:53:43.706961 best DQS1 dly(2T, 0.5T) = (0, 10)
5975 13:53:43.710379 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5976 13:53:43.713455 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5977 13:53:43.717101 best DQS0 dly(2T, 0.5T) = (0, 10)
5978 13:53:43.720322 best DQS1 dly(2T, 0.5T) = (0, 10)
5979 13:53:43.723466 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5980 13:53:43.727015 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5981 13:53:43.730052 Pre-setting of DQS Precalculation
5982 13:53:43.733394 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5983 13:53:43.743764 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5984 13:53:43.750106 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5985 13:53:43.750216
5986 13:53:43.750310
5987 13:53:43.753338 [Calibration Summary] 1866 Mbps
5988 13:53:43.753438 CH 0, Rank 0
5989 13:53:43.756872 SW Impedance : PASS
5990 13:53:43.756983 DUTY Scan : NO K
5991 13:53:43.759941 ZQ Calibration : PASS
5992 13:53:43.763416 Jitter Meter : NO K
5993 13:53:43.763516 CBT Training : PASS
5994 13:53:43.766533 Write leveling : PASS
5995 13:53:43.769896 RX DQS gating : PASS
5996 13:53:43.769969 RX DQ/DQS(RDDQC) : PASS
5997 13:53:43.773498 TX DQ/DQS : PASS
5998 13:53:43.776467 RX DATLAT : PASS
5999 13:53:43.776568 RX DQ/DQS(Engine): PASS
6000 13:53:43.779886 TX OE : NO K
6001 13:53:43.779989 All Pass.
6002 13:53:43.780084
6003 13:53:43.783208 CH 0, Rank 1
6004 13:53:43.783284 SW Impedance : PASS
6005 13:53:43.786806 DUTY Scan : NO K
6006 13:53:43.790157 ZQ Calibration : PASS
6007 13:53:43.790233 Jitter Meter : NO K
6008 13:53:43.793201 CBT Training : PASS
6009 13:53:43.793300 Write leveling : PASS
6010 13:53:43.796664 RX DQS gating : PASS
6011 13:53:43.800072 RX DQ/DQS(RDDQC) : PASS
6012 13:53:43.800171 TX DQ/DQS : PASS
6013 13:53:43.803462 RX DATLAT : PASS
6014 13:53:43.807134 RX DQ/DQS(Engine): PASS
6015 13:53:43.807237 TX OE : NO K
6016 13:53:43.809899 All Pass.
6017 13:53:43.810003
6018 13:53:43.810096 CH 1, Rank 0
6019 13:53:43.813070 SW Impedance : PASS
6020 13:53:43.813169 DUTY Scan : NO K
6021 13:53:43.816423 ZQ Calibration : PASS
6022 13:53:43.819936 Jitter Meter : NO K
6023 13:53:43.820040 CBT Training : PASS
6024 13:53:43.823062 Write leveling : PASS
6025 13:53:43.826423 RX DQS gating : PASS
6026 13:53:43.826504 RX DQ/DQS(RDDQC) : PASS
6027 13:53:43.829980 TX DQ/DQS : PASS
6028 13:53:43.833545 RX DATLAT : PASS
6029 13:53:43.833622 RX DQ/DQS(Engine): PASS
6030 13:53:43.836569 TX OE : NO K
6031 13:53:43.836654 All Pass.
6032 13:53:43.836717
6033 13:53:43.839641 CH 1, Rank 1
6034 13:53:43.839736 SW Impedance : PASS
6035 13:53:43.843144 DUTY Scan : NO K
6036 13:53:43.846371 ZQ Calibration : PASS
6037 13:53:43.846488 Jitter Meter : NO K
6038 13:53:43.849744 CBT Training : PASS
6039 13:53:43.849819 Write leveling : PASS
6040 13:53:43.852890 RX DQS gating : PASS
6041 13:53:43.856364 RX DQ/DQS(RDDQC) : PASS
6042 13:53:43.856466 TX DQ/DQS : PASS
6043 13:53:43.859754 RX DATLAT : PASS
6044 13:53:43.863041 RX DQ/DQS(Engine): PASS
6045 13:53:43.863127 TX OE : NO K
6046 13:53:43.866330 All Pass.
6047 13:53:43.866430
6048 13:53:43.866515 DramC Write-DBI off
6049 13:53:43.869821 PER_BANK_REFRESH: Hybrid Mode
6050 13:53:43.872864 TX_TRACKING: ON
6051 13:53:43.879423 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6052 13:53:43.882783 [FAST_K] Save calibration result to emmc
6053 13:53:43.886257 dramc_set_vcore_voltage set vcore to 650000
6054 13:53:43.889380 Read voltage for 400, 6
6055 13:53:43.889465 Vio18 = 0
6056 13:53:43.892772 Vcore = 650000
6057 13:53:43.892860 Vdram = 0
6058 13:53:43.892947 Vddq = 0
6059 13:53:43.896123 Vmddr = 0
6060 13:53:43.899211 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6061 13:53:43.905855 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6062 13:53:43.905983 MEM_TYPE=3, freq_sel=20
6063 13:53:43.909382 sv_algorithm_assistance_LP4_800
6064 13:53:43.915684 ============ PULL DRAM RESETB DOWN ============
6065 13:53:43.918951 ========== PULL DRAM RESETB DOWN end =========
6066 13:53:43.922378 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6067 13:53:43.925751 ===================================
6068 13:53:43.928946 LPDDR4 DRAM CONFIGURATION
6069 13:53:43.932359 ===================================
6070 13:53:43.935997 EX_ROW_EN[0] = 0x0
6071 13:53:43.936107 EX_ROW_EN[1] = 0x0
6072 13:53:43.938898 LP4Y_EN = 0x0
6073 13:53:43.939005 WORK_FSP = 0x0
6074 13:53:43.942207 WL = 0x2
6075 13:53:43.942312 RL = 0x2
6076 13:53:43.945785 BL = 0x2
6077 13:53:43.945891 RPST = 0x0
6078 13:53:43.948953 RD_PRE = 0x0
6079 13:53:43.949056 WR_PRE = 0x1
6080 13:53:43.952091 WR_PST = 0x0
6081 13:53:43.952210 DBI_WR = 0x0
6082 13:53:43.955538 DBI_RD = 0x0
6083 13:53:43.955645 OTF = 0x1
6084 13:53:43.958719 ===================================
6085 13:53:43.962131 ===================================
6086 13:53:43.965335 ANA top config
6087 13:53:43.968898 ===================================
6088 13:53:43.971966 DLL_ASYNC_EN = 0
6089 13:53:43.972073 ALL_SLAVE_EN = 1
6090 13:53:43.975465 NEW_RANK_MODE = 1
6091 13:53:43.978578 DLL_IDLE_MODE = 1
6092 13:53:43.982001 LP45_APHY_COMB_EN = 1
6093 13:53:43.985515 TX_ODT_DIS = 1
6094 13:53:43.985590 NEW_8X_MODE = 1
6095 13:53:43.988345 ===================================
6096 13:53:43.991756 ===================================
6097 13:53:43.995276 data_rate = 800
6098 13:53:43.998531 CKR = 1
6099 13:53:44.001698 DQ_P2S_RATIO = 4
6100 13:53:44.005215 ===================================
6101 13:53:44.008361 CA_P2S_RATIO = 4
6102 13:53:44.011529 DQ_CA_OPEN = 0
6103 13:53:44.011622 DQ_SEMI_OPEN = 1
6104 13:53:44.014977 CA_SEMI_OPEN = 1
6105 13:53:44.018456 CA_FULL_RATE = 0
6106 13:53:44.021553 DQ_CKDIV4_EN = 0
6107 13:53:44.025081 CA_CKDIV4_EN = 1
6108 13:53:44.028130 CA_PREDIV_EN = 0
6109 13:53:44.028229 PH8_DLY = 0
6110 13:53:44.031831 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6111 13:53:44.034907 DQ_AAMCK_DIV = 0
6112 13:53:44.038321 CA_AAMCK_DIV = 0
6113 13:53:44.041561 CA_ADMCK_DIV = 4
6114 13:53:44.044665 DQ_TRACK_CA_EN = 0
6115 13:53:44.044739 CA_PICK = 800
6116 13:53:44.048085 CA_MCKIO = 400
6117 13:53:44.051612 MCKIO_SEMI = 400
6118 13:53:44.054807 PLL_FREQ = 3016
6119 13:53:44.058006 DQ_UI_PI_RATIO = 32
6120 13:53:44.061332 CA_UI_PI_RATIO = 32
6121 13:53:44.064820 ===================================
6122 13:53:44.067909 ===================================
6123 13:53:44.071421 memory_type:LPDDR4
6124 13:53:44.071522 GP_NUM : 10
6125 13:53:44.074539 SRAM_EN : 1
6126 13:53:44.074612 MD32_EN : 0
6127 13:53:44.077889 ===================================
6128 13:53:44.081358 [ANA_INIT] >>>>>>>>>>>>>>
6129 13:53:44.084632 <<<<<< [CONFIGURE PHASE]: ANA_TX
6130 13:53:44.088112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6131 13:53:44.091211 ===================================
6132 13:53:44.094482 data_rate = 800,PCW = 0X7400
6133 13:53:44.097908 ===================================
6134 13:53:44.101351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6135 13:53:44.104438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6136 13:53:44.117785 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6137 13:53:44.120903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6138 13:53:44.124531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6139 13:53:44.127570 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6140 13:53:44.131053 [ANA_INIT] flow start
6141 13:53:44.134268 [ANA_INIT] PLL >>>>>>>>
6142 13:53:44.134344 [ANA_INIT] PLL <<<<<<<<
6143 13:53:44.137740 [ANA_INIT] MIDPI >>>>>>>>
6144 13:53:44.140840 [ANA_INIT] MIDPI <<<<<<<<
6145 13:53:44.140939 [ANA_INIT] DLL >>>>>>>>
6146 13:53:44.144018 [ANA_INIT] flow end
6147 13:53:44.147539 ============ LP4 DIFF to SE enter ============
6148 13:53:44.154109 ============ LP4 DIFF to SE exit ============
6149 13:53:44.154193 [ANA_INIT] <<<<<<<<<<<<<
6150 13:53:44.157413 [Flow] Enable top DCM control >>>>>
6151 13:53:44.160795 [Flow] Enable top DCM control <<<<<
6152 13:53:44.163883 Enable DLL master slave shuffle
6153 13:53:44.170500 ==============================================================
6154 13:53:44.170580 Gating Mode config
6155 13:53:44.177330 ==============================================================
6156 13:53:44.180360 Config description:
6157 13:53:44.190525 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6158 13:53:44.193643 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6159 13:53:44.200335 SELPH_MODE 0: By rank 1: By Phase
6160 13:53:44.207101 ==============================================================
6161 13:53:44.210409 GAT_TRACK_EN = 0
6162 13:53:44.210487 RX_GATING_MODE = 2
6163 13:53:44.213826 RX_GATING_TRACK_MODE = 2
6164 13:53:44.217122 SELPH_MODE = 1
6165 13:53:44.220450 PICG_EARLY_EN = 1
6166 13:53:44.223649 VALID_LAT_VALUE = 1
6167 13:53:44.230019 ==============================================================
6168 13:53:44.233555 Enter into Gating configuration >>>>
6169 13:53:44.236683 Exit from Gating configuration <<<<
6170 13:53:44.240134 Enter into DVFS_PRE_config >>>>>
6171 13:53:44.249967 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6172 13:53:44.253442 Exit from DVFS_PRE_config <<<<<
6173 13:53:44.256544 Enter into PICG configuration >>>>
6174 13:53:44.260195 Exit from PICG configuration <<<<
6175 13:53:44.263283 [RX_INPUT] configuration >>>>>
6176 13:53:44.266612 [RX_INPUT] configuration <<<<<
6177 13:53:44.270215 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6178 13:53:44.276769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6179 13:53:44.283467 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 13:53:44.286421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 13:53:44.293325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6182 13:53:44.299748 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6183 13:53:44.303064 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6184 13:53:44.309460 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6185 13:53:44.313024 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6186 13:53:44.316475 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6187 13:53:44.319443 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6188 13:53:44.326051 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 13:53:44.329539 ===================================
6190 13:53:44.329642 LPDDR4 DRAM CONFIGURATION
6191 13:53:44.332908 ===================================
6192 13:53:44.335990 EX_ROW_EN[0] = 0x0
6193 13:53:44.339494 EX_ROW_EN[1] = 0x0
6194 13:53:44.339621 LP4Y_EN = 0x0
6195 13:53:44.342784 WORK_FSP = 0x0
6196 13:53:44.342888 WL = 0x2
6197 13:53:44.345979 RL = 0x2
6198 13:53:44.346083 BL = 0x2
6199 13:53:44.349360 RPST = 0x0
6200 13:53:44.349472 RD_PRE = 0x0
6201 13:53:44.352503 WR_PRE = 0x1
6202 13:53:44.352621 WR_PST = 0x0
6203 13:53:44.355978 DBI_WR = 0x0
6204 13:53:44.356092 DBI_RD = 0x0
6205 13:53:44.359154 OTF = 0x1
6206 13:53:44.362659 ===================================
6207 13:53:44.365734 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6208 13:53:44.369070 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6209 13:53:44.375808 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6210 13:53:44.379378 ===================================
6211 13:53:44.379494 LPDDR4 DRAM CONFIGURATION
6212 13:53:44.382507 ===================================
6213 13:53:44.385865 EX_ROW_EN[0] = 0x10
6214 13:53:44.389038 EX_ROW_EN[1] = 0x0
6215 13:53:44.389125 LP4Y_EN = 0x0
6216 13:53:44.392578 WORK_FSP = 0x0
6217 13:53:44.392692 WL = 0x2
6218 13:53:44.395639 RL = 0x2
6219 13:53:44.395756 BL = 0x2
6220 13:53:44.399064 RPST = 0x0
6221 13:53:44.399177 RD_PRE = 0x0
6222 13:53:44.402204 WR_PRE = 0x1
6223 13:53:44.402318 WR_PST = 0x0
6224 13:53:44.405711 DBI_WR = 0x0
6225 13:53:44.405783 DBI_RD = 0x0
6226 13:53:44.408826 OTF = 0x1
6227 13:53:44.412106 ===================================
6228 13:53:44.418910 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6229 13:53:44.422188 nWR fixed to 30
6230 13:53:44.425606 [ModeRegInit_LP4] CH0 RK0
6231 13:53:44.425713 [ModeRegInit_LP4] CH0 RK1
6232 13:53:44.428706 [ModeRegInit_LP4] CH1 RK0
6233 13:53:44.432249 [ModeRegInit_LP4] CH1 RK1
6234 13:53:44.432349 match AC timing 19
6235 13:53:44.438518 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6236 13:53:44.442119 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6237 13:53:44.445227 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6238 13:53:44.451911 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6239 13:53:44.455463 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6240 13:53:44.455543 ==
6241 13:53:44.458485 Dram Type= 6, Freq= 0, CH_0, rank 0
6242 13:53:44.461905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 13:53:44.462009 ==
6244 13:53:44.468460 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6245 13:53:44.475062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6246 13:53:44.478534 [CA 0] Center 36 (8~64) winsize 57
6247 13:53:44.481621 [CA 1] Center 36 (8~64) winsize 57
6248 13:53:44.481702 [CA 2] Center 36 (8~64) winsize 57
6249 13:53:44.485014 [CA 3] Center 36 (8~64) winsize 57
6250 13:53:44.488440 [CA 4] Center 36 (8~64) winsize 57
6251 13:53:44.491579 [CA 5] Center 36 (8~64) winsize 57
6252 13:53:44.491684
6253 13:53:44.495138 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6254 13:53:44.498156
6255 13:53:44.501509 [CATrainingPosCal] consider 1 rank data
6256 13:53:44.501614 u2DelayCellTimex100 = 270/100 ps
6257 13:53:44.508319 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 13:53:44.511539 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 13:53:44.514707 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 13:53:44.518330 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 13:53:44.521514 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 13:53:44.524776 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 13:53:44.524854
6264 13:53:44.528097 CA PerBit enable=1, Macro0, CA PI delay=36
6265 13:53:44.528197
6266 13:53:44.531241 [CBTSetCACLKResult] CA Dly = 36
6267 13:53:44.534734 CS Dly: 1 (0~32)
6268 13:53:44.534813 ==
6269 13:53:44.538036 Dram Type= 6, Freq= 0, CH_0, rank 1
6270 13:53:44.541667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 13:53:44.541761 ==
6272 13:53:44.547838 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6273 13:53:44.551398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6274 13:53:44.554469 [CA 0] Center 36 (8~64) winsize 57
6275 13:53:44.558023 [CA 1] Center 36 (8~64) winsize 57
6276 13:53:44.561143 [CA 2] Center 36 (8~64) winsize 57
6277 13:53:44.564670 [CA 3] Center 36 (8~64) winsize 57
6278 13:53:44.567770 [CA 4] Center 36 (8~64) winsize 57
6279 13:53:44.571274 [CA 5] Center 36 (8~64) winsize 57
6280 13:53:44.571350
6281 13:53:44.574585 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6282 13:53:44.574694
6283 13:53:44.577709 [CATrainingPosCal] consider 2 rank data
6284 13:53:44.581010 u2DelayCellTimex100 = 270/100 ps
6285 13:53:44.584249 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 13:53:44.587703 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 13:53:44.594196 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 13:53:44.597452 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 13:53:44.600883 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 13:53:44.603942 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 13:53:44.604023
6292 13:53:44.607387 CA PerBit enable=1, Macro0, CA PI delay=36
6293 13:53:44.607493
6294 13:53:44.610585 [CBTSetCACLKResult] CA Dly = 36
6295 13:53:44.610690 CS Dly: 1 (0~32)
6296 13:53:44.614342
6297 13:53:44.617360 ----->DramcWriteLeveling(PI) begin...
6298 13:53:44.617515 ==
6299 13:53:44.620623 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 13:53:44.623915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 13:53:44.624039 ==
6302 13:53:44.627179 Write leveling (Byte 0): 40 => 8
6303 13:53:44.630632 Write leveling (Byte 1): 40 => 8
6304 13:53:44.634082 DramcWriteLeveling(PI) end<-----
6305 13:53:44.634185
6306 13:53:44.634275 ==
6307 13:53:44.637353 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 13:53:44.640518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 13:53:44.640632 ==
6310 13:53:44.643987 [Gating] SW mode calibration
6311 13:53:44.650542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6312 13:53:44.657305 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6313 13:53:44.660402 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6314 13:53:44.663931 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6315 13:53:44.667027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 13:53:44.673729 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 13:53:44.677341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 13:53:44.680335 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 13:53:44.687104 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 13:53:44.690190 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 13:53:44.693726 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 13:53:44.697139 Total UI for P1: 0, mck2ui 16
6323 13:53:44.700347 best dqsien dly found for B0: ( 0, 14, 24)
6324 13:53:44.703493 Total UI for P1: 0, mck2ui 16
6325 13:53:44.707026 best dqsien dly found for B1: ( 0, 14, 24)
6326 13:53:44.710275 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6327 13:53:44.716964 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6328 13:53:44.717065
6329 13:53:44.720084 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6330 13:53:44.723522 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6331 13:53:44.726777 [Gating] SW calibration Done
6332 13:53:44.726879 ==
6333 13:53:44.730207 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 13:53:44.733398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 13:53:44.733525 ==
6336 13:53:44.736873 RX Vref Scan: 0
6337 13:53:44.736969
6338 13:53:44.737056 RX Vref 0 -> 0, step: 1
6339 13:53:44.737184
6340 13:53:44.740193 RX Delay -410 -> 252, step: 16
6341 13:53:44.743459 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6342 13:53:44.750139 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6343 13:53:44.753434 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6344 13:53:44.756862 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6345 13:53:44.760065 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6346 13:53:44.766736 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6347 13:53:44.769916 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6348 13:53:44.773466 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6349 13:53:44.776979 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6350 13:53:44.783247 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6351 13:53:44.786515 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6352 13:53:44.789915 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6353 13:53:44.793149 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6354 13:53:44.799761 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6355 13:53:44.802911 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6356 13:53:44.806561 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6357 13:53:44.806670 ==
6358 13:53:44.809746 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 13:53:44.816329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 13:53:44.816440 ==
6361 13:53:44.816535 DQS Delay:
6362 13:53:44.819729 DQS0 = 59, DQS1 = 59
6363 13:53:44.819830 DQM Delay:
6364 13:53:44.819934 DQM0 = 18, DQM1 = 10
6365 13:53:44.822929 DQ Delay:
6366 13:53:44.826471 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6367 13:53:44.829544 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6368 13:53:44.829621 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6369 13:53:44.836261 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6370 13:53:44.836365
6371 13:53:44.836470
6372 13:53:44.836570 ==
6373 13:53:44.839813 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 13:53:44.842960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 13:53:44.843037 ==
6376 13:53:44.843100
6377 13:53:44.843159
6378 13:53:44.846183 TX Vref Scan disable
6379 13:53:44.846258 == TX Byte 0 ==
6380 13:53:44.849435 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 13:53:44.856087 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 13:53:44.856194 == TX Byte 1 ==
6383 13:53:44.859591 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 13:53:44.865968 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 13:53:44.866070 ==
6386 13:53:44.869506 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 13:53:44.872656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 13:53:44.872754 ==
6389 13:53:44.872847
6390 13:53:44.872933
6391 13:53:44.875907 TX Vref Scan disable
6392 13:53:44.876004 == TX Byte 0 ==
6393 13:53:44.882678 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 13:53:44.886003 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 13:53:44.886077 == TX Byte 1 ==
6396 13:53:44.892728 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 13:53:44.896075 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 13:53:44.896180
6399 13:53:44.896269 [DATLAT]
6400 13:53:44.899145 Freq=400, CH0 RK0
6401 13:53:44.899218
6402 13:53:44.899278 DATLAT Default: 0xf
6403 13:53:44.902666 0, 0xFFFF, sum = 0
6404 13:53:44.902773 1, 0xFFFF, sum = 0
6405 13:53:44.905811 2, 0xFFFF, sum = 0
6406 13:53:44.905914 3, 0xFFFF, sum = 0
6407 13:53:44.909356 4, 0xFFFF, sum = 0
6408 13:53:44.909452 5, 0xFFFF, sum = 0
6409 13:53:44.912428 6, 0xFFFF, sum = 0
6410 13:53:44.912530 7, 0xFFFF, sum = 0
6411 13:53:44.915529 8, 0xFFFF, sum = 0
6412 13:53:44.915612 9, 0xFFFF, sum = 0
6413 13:53:44.919187 10, 0xFFFF, sum = 0
6414 13:53:44.922341 11, 0xFFFF, sum = 0
6415 13:53:44.922424 12, 0xFFFF, sum = 0
6416 13:53:44.925448 13, 0x0, sum = 1
6417 13:53:44.925566 14, 0x0, sum = 2
6418 13:53:44.925645 15, 0x0, sum = 3
6419 13:53:44.928757 16, 0x0, sum = 4
6420 13:53:44.928829 best_step = 14
6421 13:53:44.928895
6422 13:53:44.928977 ==
6423 13:53:44.932209 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 13:53:44.938528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 13:53:44.938608 ==
6426 13:53:44.938672 RX Vref Scan: 1
6427 13:53:44.938730
6428 13:53:44.941933 RX Vref 0 -> 0, step: 1
6429 13:53:44.942009
6430 13:53:44.945081 RX Delay -359 -> 252, step: 8
6431 13:53:44.945181
6432 13:53:44.948645 Set Vref, RX VrefLevel [Byte0]: 61
6433 13:53:44.951656 [Byte1]: 47
6434 13:53:44.955588
6435 13:53:44.955734 Final RX Vref Byte 0 = 61 to rank0
6436 13:53:44.958817 Final RX Vref Byte 1 = 47 to rank0
6437 13:53:44.962239 Final RX Vref Byte 0 = 61 to rank1
6438 13:53:44.965748 Final RX Vref Byte 1 = 47 to rank1==
6439 13:53:44.968921 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 13:53:44.975279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 13:53:44.975387 ==
6442 13:53:44.975511 DQS Delay:
6443 13:53:44.978721 DQS0 = 60, DQS1 = 68
6444 13:53:44.978837 DQM Delay:
6445 13:53:44.978928 DQM0 = 14, DQM1 = 14
6446 13:53:44.982045 DQ Delay:
6447 13:53:44.985245 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6448 13:53:44.988799 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6449 13:53:44.988907 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6450 13:53:44.995217 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6451 13:53:44.995352
6452 13:53:44.995475
6453 13:53:45.001930 [DQSOSCAuto] RK0, (LSB)MR18= 0x8180, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6454 13:53:45.005221 CH0 RK0: MR19=C0C, MR18=8180
6455 13:53:45.011648 CH0_RK0: MR19=0xC0C, MR18=0x8180, DQSOSC=393, MR23=63, INC=382, DEC=254
6456 13:53:45.011853 ==
6457 13:53:45.015022 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 13:53:45.018220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 13:53:45.018348 ==
6460 13:53:45.021775 [Gating] SW mode calibration
6461 13:53:45.028349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6462 13:53:45.035002 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6463 13:53:45.038213 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6464 13:53:45.041462 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6465 13:53:45.048333 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 13:53:45.051481 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 13:53:45.054616 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 13:53:45.061220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 13:53:45.064790 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 13:53:45.067966 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 13:53:45.074610 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 13:53:45.074742 Total UI for P1: 0, mck2ui 16
6473 13:53:45.081343 best dqsien dly found for B0: ( 0, 14, 24)
6474 13:53:45.081451 Total UI for P1: 0, mck2ui 16
6475 13:53:45.087720 best dqsien dly found for B1: ( 0, 14, 24)
6476 13:53:45.090963 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6477 13:53:45.094559 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6478 13:53:45.094670
6479 13:53:45.097717 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6480 13:53:45.100947 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6481 13:53:45.104230 [Gating] SW calibration Done
6482 13:53:45.104336 ==
6483 13:53:45.107496 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 13:53:45.110648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 13:53:45.110786 ==
6486 13:53:45.114264 RX Vref Scan: 0
6487 13:53:45.114374
6488 13:53:45.114472 RX Vref 0 -> 0, step: 1
6489 13:53:45.117530
6490 13:53:45.117667 RX Delay -410 -> 252, step: 16
6491 13:53:45.124290 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6492 13:53:45.127399 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6493 13:53:45.130752 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6494 13:53:45.133954 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6495 13:53:45.140556 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6496 13:53:45.143881 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6497 13:53:45.147079 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6498 13:53:45.150401 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6499 13:53:45.157059 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6500 13:53:45.160522 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6501 13:53:45.163807 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6502 13:53:45.170075 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6503 13:53:45.173469 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6504 13:53:45.177064 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6505 13:53:45.180352 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6506 13:53:45.186933 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6507 13:53:45.187065 ==
6508 13:53:45.190168 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 13:53:45.193260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 13:53:45.193375 ==
6511 13:53:45.193469 DQS Delay:
6512 13:53:45.196671 DQS0 = 59, DQS1 = 59
6513 13:53:45.196772 DQM Delay:
6514 13:53:45.199840 DQM0 = 16, DQM1 = 10
6515 13:53:45.199942 DQ Delay:
6516 13:53:45.203411 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6517 13:53:45.206543 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6518 13:53:45.209874 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6519 13:53:45.213210 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6520 13:53:45.213323
6521 13:53:45.213417
6522 13:53:45.213519 ==
6523 13:53:45.216661 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 13:53:45.219991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 13:53:45.220094 ==
6526 13:53:45.223175
6527 13:53:45.223309
6528 13:53:45.223425 TX Vref Scan disable
6529 13:53:45.226357 == TX Byte 0 ==
6530 13:53:45.229921 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6531 13:53:45.233100 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6532 13:53:45.236573 == TX Byte 1 ==
6533 13:53:45.239691 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6534 13:53:45.243073 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6535 13:53:45.243183 ==
6536 13:53:45.246195 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 13:53:45.249629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 13:53:45.252865 ==
6539 13:53:45.252965
6540 13:53:45.253056
6541 13:53:45.253148 TX Vref Scan disable
6542 13:53:45.256064 == TX Byte 0 ==
6543 13:53:45.259543 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6544 13:53:45.262646 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6545 13:53:45.266183 == TX Byte 1 ==
6546 13:53:45.269363 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6547 13:53:45.272916 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6548 13:53:45.273028
6549 13:53:45.273128 [DATLAT]
6550 13:53:45.276016 Freq=400, CH0 RK1
6551 13:53:45.276120
6552 13:53:45.279495 DATLAT Default: 0xe
6553 13:53:45.279598 0, 0xFFFF, sum = 0
6554 13:53:45.282998 1, 0xFFFF, sum = 0
6555 13:53:45.283106 2, 0xFFFF, sum = 0
6556 13:53:45.286066 3, 0xFFFF, sum = 0
6557 13:53:45.286150 4, 0xFFFF, sum = 0
6558 13:53:45.289280 5, 0xFFFF, sum = 0
6559 13:53:45.289398 6, 0xFFFF, sum = 0
6560 13:53:45.292433 7, 0xFFFF, sum = 0
6561 13:53:45.292541 8, 0xFFFF, sum = 0
6562 13:53:45.295832 9, 0xFFFF, sum = 0
6563 13:53:45.295934 10, 0xFFFF, sum = 0
6564 13:53:45.299242 11, 0xFFFF, sum = 0
6565 13:53:45.299358 12, 0xFFFF, sum = 0
6566 13:53:45.302517 13, 0x0, sum = 1
6567 13:53:45.302644 14, 0x0, sum = 2
6568 13:53:45.306021 15, 0x0, sum = 3
6569 13:53:45.306136 16, 0x0, sum = 4
6570 13:53:45.309366 best_step = 14
6571 13:53:45.309493
6572 13:53:45.309597 ==
6573 13:53:45.312589 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 13:53:45.315948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 13:53:45.316093 ==
6576 13:53:45.319362 RX Vref Scan: 0
6577 13:53:45.319501
6578 13:53:45.319631 RX Vref 0 -> 0, step: 1
6579 13:53:45.319754
6580 13:53:45.322397 RX Delay -359 -> 252, step: 8
6581 13:53:45.330565 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6582 13:53:45.333835 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6583 13:53:45.337091 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6584 13:53:45.340219 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6585 13:53:45.346915 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6586 13:53:45.350426 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6587 13:53:45.353713 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6588 13:53:45.360225 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6589 13:53:45.363426 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6590 13:53:45.366783 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6591 13:53:45.370009 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6592 13:53:45.376659 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6593 13:53:45.380082 iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504
6594 13:53:45.383191 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6595 13:53:45.386515 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6596 13:53:45.393147 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6597 13:53:45.393230 ==
6598 13:53:45.396679 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 13:53:45.399779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 13:53:45.399897 ==
6601 13:53:45.399993 DQS Delay:
6602 13:53:45.403121 DQS0 = 60, DQS1 = 72
6603 13:53:45.403204 DQM Delay:
6604 13:53:45.406416 DQM0 = 11, DQM1 = 16
6605 13:53:45.406492 DQ Delay:
6606 13:53:45.410051 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6607 13:53:45.413042 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6608 13:53:45.416627 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6609 13:53:45.419928 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
6610 13:53:45.420020
6611 13:53:45.420113
6612 13:53:45.426371 [DQSOSCAuto] RK1, (LSB)MR18= 0xc57b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6613 13:53:45.429787 CH0 RK1: MR19=C0C, MR18=C57B
6614 13:53:45.436521 CH0_RK1: MR19=0xC0C, MR18=0xC57B, DQSOSC=385, MR23=63, INC=398, DEC=265
6615 13:53:45.439661 [RxdqsGatingPostProcess] freq 400
6616 13:53:45.446414 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6617 13:53:45.449887 best DQS0 dly(2T, 0.5T) = (0, 10)
6618 13:53:45.449986 best DQS1 dly(2T, 0.5T) = (0, 10)
6619 13:53:45.453016 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6620 13:53:45.456120 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6621 13:53:45.459504 best DQS0 dly(2T, 0.5T) = (0, 10)
6622 13:53:45.462796 best DQS1 dly(2T, 0.5T) = (0, 10)
6623 13:53:45.466389 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6624 13:53:45.469729 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6625 13:53:45.473215 Pre-setting of DQS Precalculation
6626 13:53:45.479464 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6627 13:53:45.479541 ==
6628 13:53:45.482676 Dram Type= 6, Freq= 0, CH_1, rank 0
6629 13:53:45.486033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 13:53:45.486142 ==
6631 13:53:45.492550 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6632 13:53:45.495750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6633 13:53:45.499234 [CA 0] Center 36 (8~64) winsize 57
6634 13:53:45.502792 [CA 1] Center 36 (8~64) winsize 57
6635 13:53:45.505915 [CA 2] Center 36 (8~64) winsize 57
6636 13:53:45.509425 [CA 3] Center 36 (8~64) winsize 57
6637 13:53:45.512417 [CA 4] Center 36 (8~64) winsize 57
6638 13:53:45.515895 [CA 5] Center 36 (8~64) winsize 57
6639 13:53:45.515975
6640 13:53:45.518978 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6641 13:53:45.519082
6642 13:53:45.522622 [CATrainingPosCal] consider 1 rank data
6643 13:53:45.525608 u2DelayCellTimex100 = 270/100 ps
6644 13:53:45.529126 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 13:53:45.532156 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 13:53:45.538955 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 13:53:45.542020 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 13:53:45.545612 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 13:53:45.548833 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 13:53:45.548930
6651 13:53:45.551976 CA PerBit enable=1, Macro0, CA PI delay=36
6652 13:53:45.552091
6653 13:53:45.555504 [CBTSetCACLKResult] CA Dly = 36
6654 13:53:45.555604 CS Dly: 1 (0~32)
6655 13:53:45.558880 ==
6656 13:53:45.558955 Dram Type= 6, Freq= 0, CH_1, rank 1
6657 13:53:45.565624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 13:53:45.565701 ==
6659 13:53:45.568944 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6660 13:53:45.575842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6661 13:53:45.578875 [CA 0] Center 36 (8~64) winsize 57
6662 13:53:45.582042 [CA 1] Center 36 (8~64) winsize 57
6663 13:53:45.585616 [CA 2] Center 36 (8~64) winsize 57
6664 13:53:45.588763 [CA 3] Center 36 (8~64) winsize 57
6665 13:53:45.592353 [CA 4] Center 36 (8~64) winsize 57
6666 13:53:45.595607 [CA 5] Center 36 (8~64) winsize 57
6667 13:53:45.595718
6668 13:53:45.598678 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6669 13:53:45.598765
6670 13:53:45.601976 [CATrainingPosCal] consider 2 rank data
6671 13:53:45.605400 u2DelayCellTimex100 = 270/100 ps
6672 13:53:45.608620 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 13:53:45.612112 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 13:53:45.615207 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 13:53:45.618444 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 13:53:45.621913 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 13:53:45.628642 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 13:53:45.628747
6679 13:53:45.631769 CA PerBit enable=1, Macro0, CA PI delay=36
6680 13:53:45.631876
6681 13:53:45.635241 [CBTSetCACLKResult] CA Dly = 36
6682 13:53:45.635347 CS Dly: 1 (0~32)
6683 13:53:45.635440
6684 13:53:45.638693 ----->DramcWriteLeveling(PI) begin...
6685 13:53:45.638797 ==
6686 13:53:45.641776 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 13:53:45.648189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 13:53:45.648295 ==
6689 13:53:45.651569 Write leveling (Byte 0): 40 => 8
6690 13:53:45.651672 Write leveling (Byte 1): 40 => 8
6691 13:53:45.654885 DramcWriteLeveling(PI) end<-----
6692 13:53:45.654986
6693 13:53:45.655086 ==
6694 13:53:45.658179 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 13:53:45.664849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 13:53:45.664930 ==
6697 13:53:45.668000 [Gating] SW mode calibration
6698 13:53:45.674643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6699 13:53:45.677754 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6700 13:53:45.684796 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6701 13:53:45.687882 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6702 13:53:45.691002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 13:53:45.697573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 13:53:45.701098 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 13:53:45.704236 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 13:53:45.710937 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 13:53:45.714615 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 13:53:45.717678 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 13:53:45.721077 Total UI for P1: 0, mck2ui 16
6710 13:53:45.724251 best dqsien dly found for B0: ( 0, 14, 24)
6711 13:53:45.727647 Total UI for P1: 0, mck2ui 16
6712 13:53:45.730818 best dqsien dly found for B1: ( 0, 14, 24)
6713 13:53:45.734367 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6714 13:53:45.737355 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6715 13:53:45.737455
6716 13:53:45.744076 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6717 13:53:45.747380 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6718 13:53:45.750590 [Gating] SW calibration Done
6719 13:53:45.750671 ==
6720 13:53:45.754054 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 13:53:45.757226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 13:53:45.757331 ==
6723 13:53:45.757425 RX Vref Scan: 0
6724 13:53:45.757525
6725 13:53:45.760392 RX Vref 0 -> 0, step: 1
6726 13:53:45.760489
6727 13:53:45.763959 RX Delay -410 -> 252, step: 16
6728 13:53:45.767209 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6729 13:53:45.773790 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6730 13:53:45.777157 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6731 13:53:45.780765 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6732 13:53:45.783923 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6733 13:53:45.790588 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6734 13:53:45.793844 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6735 13:53:45.797013 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6736 13:53:45.800165 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6737 13:53:45.806803 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6738 13:53:45.810257 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6739 13:53:45.813906 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6740 13:53:45.816999 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6741 13:53:45.823766 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6742 13:53:45.826906 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6743 13:53:45.830290 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6744 13:53:45.830392 ==
6745 13:53:45.833496 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 13:53:45.839961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 13:53:45.840064 ==
6748 13:53:45.840158 DQS Delay:
6749 13:53:45.840248 DQS0 = 51, DQS1 = 67
6750 13:53:45.843503 DQM Delay:
6751 13:53:45.843599 DQM0 = 13, DQM1 = 16
6752 13:53:45.846883 DQ Delay:
6753 13:53:45.850104 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6754 13:53:45.850204 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6755 13:53:45.853399 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6756 13:53:45.856723 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6757 13:53:45.856827
6758 13:53:45.856919
6759 13:53:45.860078 ==
6760 13:53:45.863114 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 13:53:45.866409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 13:53:45.866512 ==
6763 13:53:45.866580
6764 13:53:45.866642
6765 13:53:45.869759 TX Vref Scan disable
6766 13:53:45.869863 == TX Byte 0 ==
6767 13:53:45.873273 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 13:53:45.879581 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 13:53:45.879685 == TX Byte 1 ==
6770 13:53:45.883027 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 13:53:45.889576 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 13:53:45.889660 ==
6773 13:53:45.892769 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 13:53:45.896345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 13:53:45.896437 ==
6776 13:53:45.896529
6777 13:53:45.896617
6778 13:53:45.899554 TX Vref Scan disable
6779 13:53:45.899652 == TX Byte 0 ==
6780 13:53:45.902734 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 13:53:45.909501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 13:53:45.909605 == TX Byte 1 ==
6783 13:53:45.912581 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 13:53:45.919158 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 13:53:45.919262
6786 13:53:45.919354 [DATLAT]
6787 13:53:45.922598 Freq=400, CH1 RK0
6788 13:53:45.922696
6789 13:53:45.922788 DATLAT Default: 0xf
6790 13:53:45.926009 0, 0xFFFF, sum = 0
6791 13:53:45.926120 1, 0xFFFF, sum = 0
6792 13:53:45.929119 2, 0xFFFF, sum = 0
6793 13:53:45.929224 3, 0xFFFF, sum = 0
6794 13:53:45.932555 4, 0xFFFF, sum = 0
6795 13:53:45.932658 5, 0xFFFF, sum = 0
6796 13:53:45.935858 6, 0xFFFF, sum = 0
6797 13:53:45.935959 7, 0xFFFF, sum = 0
6798 13:53:45.938950 8, 0xFFFF, sum = 0
6799 13:53:45.939057 9, 0xFFFF, sum = 0
6800 13:53:45.942188 10, 0xFFFF, sum = 0
6801 13:53:45.942265 11, 0xFFFF, sum = 0
6802 13:53:45.945409 12, 0xFFFF, sum = 0
6803 13:53:45.948831 13, 0x0, sum = 1
6804 13:53:45.948936 14, 0x0, sum = 2
6805 13:53:45.949032 15, 0x0, sum = 3
6806 13:53:45.952134 16, 0x0, sum = 4
6807 13:53:45.952233 best_step = 14
6808 13:53:45.952325
6809 13:53:45.952415 ==
6810 13:53:45.955328 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 13:53:45.962374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 13:53:45.962478 ==
6813 13:53:45.962575 RX Vref Scan: 1
6814 13:53:45.962665
6815 13:53:45.965406 RX Vref 0 -> 0, step: 1
6816 13:53:45.965518
6817 13:53:45.968729 RX Delay -375 -> 252, step: 8
6818 13:53:45.968829
6819 13:53:45.972190 Set Vref, RX VrefLevel [Byte0]: 52
6820 13:53:45.975308 [Byte1]: 50
6821 13:53:45.978898
6822 13:53:45.978978 Final RX Vref Byte 0 = 52 to rank0
6823 13:53:45.982321 Final RX Vref Byte 1 = 50 to rank0
6824 13:53:45.985321 Final RX Vref Byte 0 = 52 to rank1
6825 13:53:45.988806 Final RX Vref Byte 1 = 50 to rank1==
6826 13:53:45.991918 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 13:53:45.998707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 13:53:45.998790 ==
6829 13:53:45.998887 DQS Delay:
6830 13:53:46.001857 DQS0 = 56, DQS1 = 68
6831 13:53:46.001956 DQM Delay:
6832 13:53:46.002047 DQM0 = 13, DQM1 = 14
6833 13:53:46.005362 DQ Delay:
6834 13:53:46.008832 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6835 13:53:46.011826 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
6836 13:53:46.011926 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6837 13:53:46.018658 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6838 13:53:46.018760
6839 13:53:46.018853
6840 13:53:46.025502 [DQSOSCAuto] RK0, (LSB)MR18= 0x6275, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6841 13:53:46.028440 CH1 RK0: MR19=C0C, MR18=6275
6842 13:53:46.035103 CH1_RK0: MR19=0xC0C, MR18=0x6275, DQSOSC=395, MR23=63, INC=378, DEC=252
6843 13:53:46.035208 ==
6844 13:53:46.038591 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 13:53:46.041696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 13:53:46.041797 ==
6847 13:53:46.044910 [Gating] SW mode calibration
6848 13:53:46.051777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6849 13:53:46.058346 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6850 13:53:46.061457 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6851 13:53:46.065016 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6852 13:53:46.071338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 13:53:46.074776 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 13:53:46.078374 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 13:53:46.084846 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 13:53:46.088157 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 13:53:46.091611 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 13:53:46.098071 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 13:53:46.098149 Total UI for P1: 0, mck2ui 16
6860 13:53:46.104403 best dqsien dly found for B0: ( 0, 14, 24)
6861 13:53:46.104516 Total UI for P1: 0, mck2ui 16
6862 13:53:46.111063 best dqsien dly found for B1: ( 0, 14, 24)
6863 13:53:46.114451 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6864 13:53:46.117787 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6865 13:53:46.117893
6866 13:53:46.121065 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6867 13:53:46.124491 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6868 13:53:46.127986 [Gating] SW calibration Done
6869 13:53:46.128090 ==
6870 13:53:46.131031 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 13:53:46.134448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 13:53:46.134546 ==
6873 13:53:46.137830 RX Vref Scan: 0
6874 13:53:46.137924
6875 13:53:46.137991 RX Vref 0 -> 0, step: 1
6876 13:53:46.138052
6877 13:53:46.141155 RX Delay -410 -> 252, step: 16
6878 13:53:46.147759 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6879 13:53:46.151160 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6880 13:53:46.154522 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6881 13:53:46.157472 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6882 13:53:46.164185 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6883 13:53:46.167621 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6884 13:53:46.170751 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6885 13:53:46.174353 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6886 13:53:46.180986 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6887 13:53:46.184128 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6888 13:53:46.187330 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6889 13:53:46.190563 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6890 13:53:46.197366 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6891 13:53:46.200545 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6892 13:53:46.203957 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6893 13:53:46.210587 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6894 13:53:46.210665 ==
6895 13:53:46.213956 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 13:53:46.217152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 13:53:46.217252 ==
6898 13:53:46.217344 DQS Delay:
6899 13:53:46.220712 DQS0 = 59, DQS1 = 59
6900 13:53:46.220815 DQM Delay:
6901 13:53:46.223985 DQM0 = 18, DQM1 = 14
6902 13:53:46.224084 DQ Delay:
6903 13:53:46.227334 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6904 13:53:46.230437 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6905 13:53:46.233967 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6906 13:53:46.237132 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6907 13:53:46.237207
6908 13:53:46.237270
6909 13:53:46.237331 ==
6910 13:53:46.240344 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 13:53:46.243705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 13:53:46.243784 ==
6913 13:53:46.243848
6914 13:53:46.243915
6915 13:53:46.247150 TX Vref Scan disable
6916 13:53:46.247227 == TX Byte 0 ==
6917 13:53:46.253597 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6918 13:53:46.257080 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6919 13:53:46.257162 == TX Byte 1 ==
6920 13:53:46.263511 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6921 13:53:46.266716 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6922 13:53:46.266817 ==
6923 13:53:46.270087 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 13:53:46.273421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 13:53:46.273535 ==
6926 13:53:46.273629
6927 13:53:46.273722
6928 13:53:46.276855 TX Vref Scan disable
6929 13:53:46.280021 == TX Byte 0 ==
6930 13:53:46.283499 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6931 13:53:46.286985 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6932 13:53:46.287059 == TX Byte 1 ==
6933 13:53:46.293535 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6934 13:53:46.296734 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6935 13:53:46.296810
6936 13:53:46.296879 [DATLAT]
6937 13:53:46.300255 Freq=400, CH1 RK1
6938 13:53:46.300348
6939 13:53:46.300412 DATLAT Default: 0xe
6940 13:53:46.303450 0, 0xFFFF, sum = 0
6941 13:53:46.303529 1, 0xFFFF, sum = 0
6942 13:53:46.310213 2, 0xFFFF, sum = 0
6943 13:53:46.310319 3, 0xFFFF, sum = 0
6944 13:53:46.310607 4, 0xFFFF, sum = 0
6945 13:53:46.310678 5, 0xFFFF, sum = 0
6946 13:53:46.313246 6, 0xFFFF, sum = 0
6947 13:53:46.316607 7, 0xFFFF, sum = 0
6948 13:53:46.316707 8, 0xFFFF, sum = 0
6949 13:53:46.320094 9, 0xFFFF, sum = 0
6950 13:53:46.320204 10, 0xFFFF, sum = 0
6951 13:53:46.323251 11, 0xFFFF, sum = 0
6952 13:53:46.323351 12, 0xFFFF, sum = 0
6953 13:53:46.326865 13, 0x0, sum = 1
6954 13:53:46.326978 14, 0x0, sum = 2
6955 13:53:46.329851 15, 0x0, sum = 3
6956 13:53:46.329952 16, 0x0, sum = 4
6957 13:53:46.330034 best_step = 14
6958 13:53:46.333375
6959 13:53:46.333472 ==
6960 13:53:46.336494 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 13:53:46.340045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 13:53:46.340144 ==
6963 13:53:46.340236 RX Vref Scan: 0
6964 13:53:46.340322
6965 13:53:46.343125 RX Vref 0 -> 0, step: 1
6966 13:53:46.343222
6967 13:53:46.346605 RX Delay -359 -> 252, step: 8
6968 13:53:46.353853 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6969 13:53:46.357100 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6970 13:53:46.360434 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6971 13:53:46.363625 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6972 13:53:46.370313 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6973 13:53:46.373635 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6974 13:53:46.376925 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6975 13:53:46.380301 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6976 13:53:46.386847 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6977 13:53:46.390025 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6978 13:53:46.393567 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6979 13:53:46.400148 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6980 13:53:46.403280 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6981 13:53:46.406803 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6982 13:53:46.409916 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6983 13:53:46.416563 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6984 13:53:46.416667 ==
6985 13:53:46.419883 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 13:53:46.423350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 13:53:46.423447 ==
6988 13:53:46.423540 DQS Delay:
6989 13:53:46.426528 DQS0 = 60, DQS1 = 64
6990 13:53:46.426664 DQM Delay:
6991 13:53:46.429726 DQM0 = 13, DQM1 = 10
6992 13:53:46.429825 DQ Delay:
6993 13:53:46.433248 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6994 13:53:46.436355 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6995 13:53:46.439864 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6996 13:53:46.442982 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6997 13:53:46.443051
6998 13:53:46.443115
6999 13:53:46.449747 [DQSOSCAuto] RK1, (LSB)MR18= 0x80b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
7000 13:53:46.453358 CH1 RK1: MR19=C0C, MR18=80B0
7001 13:53:46.459711 CH1_RK1: MR19=0xC0C, MR18=0x80B0, DQSOSC=387, MR23=63, INC=394, DEC=262
7002 13:53:46.463323 [RxdqsGatingPostProcess] freq 400
7003 13:53:46.469740 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7004 13:53:46.472923 best DQS0 dly(2T, 0.5T) = (0, 10)
7005 13:53:46.473022 best DQS1 dly(2T, 0.5T) = (0, 10)
7006 13:53:46.476518 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7007 13:53:46.480217 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7008 13:53:46.483118 best DQS0 dly(2T, 0.5T) = (0, 10)
7009 13:53:46.486595 best DQS1 dly(2T, 0.5T) = (0, 10)
7010 13:53:46.489578 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7011 13:53:46.493030 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7012 13:53:46.496375 Pre-setting of DQS Precalculation
7013 13:53:46.502802 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7014 13:53:46.509597 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7015 13:53:46.516078 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7016 13:53:46.516231
7017 13:53:46.516325
7018 13:53:46.519440 [Calibration Summary] 800 Mbps
7019 13:53:46.519537 CH 0, Rank 0
7020 13:53:46.522820 SW Impedance : PASS
7021 13:53:46.525979 DUTY Scan : NO K
7022 13:53:46.526060 ZQ Calibration : PASS
7023 13:53:46.529420 Jitter Meter : NO K
7024 13:53:46.529547 CBT Training : PASS
7025 13:53:46.532752 Write leveling : PASS
7026 13:53:46.536164 RX DQS gating : PASS
7027 13:53:46.536266 RX DQ/DQS(RDDQC) : PASS
7028 13:53:46.539353 TX DQ/DQS : PASS
7029 13:53:46.542941 RX DATLAT : PASS
7030 13:53:46.543023 RX DQ/DQS(Engine): PASS
7031 13:53:46.546168 TX OE : NO K
7032 13:53:46.546283 All Pass.
7033 13:53:46.546372
7034 13:53:46.549548 CH 0, Rank 1
7035 13:53:46.549623 SW Impedance : PASS
7036 13:53:46.552672 DUTY Scan : NO K
7037 13:53:46.555930 ZQ Calibration : PASS
7038 13:53:46.556029 Jitter Meter : NO K
7039 13:53:46.559453 CBT Training : PASS
7040 13:53:46.562530 Write leveling : NO K
7041 13:53:46.562603 RX DQS gating : PASS
7042 13:53:46.566035 RX DQ/DQS(RDDQC) : PASS
7043 13:53:46.569212 TX DQ/DQS : PASS
7044 13:53:46.569324 RX DATLAT : PASS
7045 13:53:46.572855 RX DQ/DQS(Engine): PASS
7046 13:53:46.575856 TX OE : NO K
7047 13:53:46.575955 All Pass.
7048 13:53:46.576044
7049 13:53:46.576129 CH 1, Rank 0
7050 13:53:46.579166 SW Impedance : PASS
7051 13:53:46.582438 DUTY Scan : NO K
7052 13:53:46.582508 ZQ Calibration : PASS
7053 13:53:46.585636 Jitter Meter : NO K
7054 13:53:46.589217 CBT Training : PASS
7055 13:53:46.589292 Write leveling : PASS
7056 13:53:46.592330 RX DQS gating : PASS
7057 13:53:46.592402 RX DQ/DQS(RDDQC) : PASS
7058 13:53:46.595926 TX DQ/DQS : PASS
7059 13:53:46.599212 RX DATLAT : PASS
7060 13:53:46.599310 RX DQ/DQS(Engine): PASS
7061 13:53:46.602353 TX OE : NO K
7062 13:53:46.602462 All Pass.
7063 13:53:46.602555
7064 13:53:46.605703 CH 1, Rank 1
7065 13:53:46.605804 SW Impedance : PASS
7066 13:53:46.609206 DUTY Scan : NO K
7067 13:53:46.612347 ZQ Calibration : PASS
7068 13:53:46.612458 Jitter Meter : NO K
7069 13:53:46.615482 CBT Training : PASS
7070 13:53:46.618981 Write leveling : NO K
7071 13:53:46.619086 RX DQS gating : PASS
7072 13:53:46.622247 RX DQ/DQS(RDDQC) : PASS
7073 13:53:46.625469 TX DQ/DQS : PASS
7074 13:53:46.625566 RX DATLAT : PASS
7075 13:53:46.628815 RX DQ/DQS(Engine): PASS
7076 13:53:46.632251 TX OE : NO K
7077 13:53:46.632357 All Pass.
7078 13:53:46.632450
7079 13:53:46.632539 DramC Write-DBI off
7080 13:53:46.635373 PER_BANK_REFRESH: Hybrid Mode
7081 13:53:46.638922 TX_TRACKING: ON
7082 13:53:46.645515 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7083 13:53:46.648661 [FAST_K] Save calibration result to emmc
7084 13:53:46.655424 dramc_set_vcore_voltage set vcore to 725000
7085 13:53:46.655507 Read voltage for 1600, 0
7086 13:53:46.658503 Vio18 = 0
7087 13:53:46.658601 Vcore = 725000
7088 13:53:46.658702 Vdram = 0
7089 13:53:46.661961 Vddq = 0
7090 13:53:46.662035 Vmddr = 0
7091 13:53:46.665496 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7092 13:53:46.671893 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7093 13:53:46.675389 MEM_TYPE=3, freq_sel=13
7094 13:53:46.678455 sv_algorithm_assistance_LP4_3733
7095 13:53:46.681834 ============ PULL DRAM RESETB DOWN ============
7096 13:53:46.685294 ========== PULL DRAM RESETB DOWN end =========
7097 13:53:46.691732 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7098 13:53:46.694893 ===================================
7099 13:53:46.694970 LPDDR4 DRAM CONFIGURATION
7100 13:53:46.698225 ===================================
7101 13:53:46.701755 EX_ROW_EN[0] = 0x0
7102 13:53:46.701832 EX_ROW_EN[1] = 0x0
7103 13:53:46.704967 LP4Y_EN = 0x0
7104 13:53:46.705070 WORK_FSP = 0x1
7105 13:53:46.708398 WL = 0x5
7106 13:53:46.708502 RL = 0x5
7107 13:53:46.711472 BL = 0x2
7108 13:53:46.715021 RPST = 0x0
7109 13:53:46.715097 RD_PRE = 0x0
7110 13:53:46.718165 WR_PRE = 0x1
7111 13:53:46.718241 WR_PST = 0x1
7112 13:53:46.721485 DBI_WR = 0x0
7113 13:53:46.721561 DBI_RD = 0x0
7114 13:53:46.724543 OTF = 0x1
7115 13:53:46.727903 ===================================
7116 13:53:46.731326 ===================================
7117 13:53:46.731403 ANA top config
7118 13:53:46.734559 ===================================
7119 13:53:46.737984 DLL_ASYNC_EN = 0
7120 13:53:46.741157 ALL_SLAVE_EN = 0
7121 13:53:46.741260 NEW_RANK_MODE = 1
7122 13:53:46.744362 DLL_IDLE_MODE = 1
7123 13:53:46.747687 LP45_APHY_COMB_EN = 1
7124 13:53:46.751223 TX_ODT_DIS = 0
7125 13:53:46.754577 NEW_8X_MODE = 1
7126 13:53:46.757813 ===================================
7127 13:53:46.760994 ===================================
7128 13:53:46.761074 data_rate = 3200
7129 13:53:46.764218 CKR = 1
7130 13:53:46.767747 DQ_P2S_RATIO = 8
7131 13:53:46.770945 ===================================
7132 13:53:46.774426 CA_P2S_RATIO = 8
7133 13:53:46.777575 DQ_CA_OPEN = 0
7134 13:53:46.780932 DQ_SEMI_OPEN = 0
7135 13:53:46.781008 CA_SEMI_OPEN = 0
7136 13:53:46.784228 CA_FULL_RATE = 0
7137 13:53:46.787582 DQ_CKDIV4_EN = 0
7138 13:53:46.790633 CA_CKDIV4_EN = 0
7139 13:53:46.793865 CA_PREDIV_EN = 0
7140 13:53:46.797421 PH8_DLY = 12
7141 13:53:46.800628 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7142 13:53:46.800730 DQ_AAMCK_DIV = 4
7143 13:53:46.803756 CA_AAMCK_DIV = 4
7144 13:53:46.807211 CA_ADMCK_DIV = 4
7145 13:53:46.810590 DQ_TRACK_CA_EN = 0
7146 13:53:46.813994 CA_PICK = 1600
7147 13:53:46.817108 CA_MCKIO = 1600
7148 13:53:46.817194 MCKIO_SEMI = 0
7149 13:53:46.820273 PLL_FREQ = 3068
7150 13:53:46.823776 DQ_UI_PI_RATIO = 32
7151 13:53:46.826869 CA_UI_PI_RATIO = 0
7152 13:53:46.830423 ===================================
7153 13:53:46.833643 ===================================
7154 13:53:46.836741 memory_type:LPDDR4
7155 13:53:46.836845 GP_NUM : 10
7156 13:53:46.840179 SRAM_EN : 1
7157 13:53:46.843407 MD32_EN : 0
7158 13:53:46.846933 ===================================
7159 13:53:46.847015 [ANA_INIT] >>>>>>>>>>>>>>
7160 13:53:46.850017 <<<<<< [CONFIGURE PHASE]: ANA_TX
7161 13:53:46.853425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7162 13:53:46.856645 ===================================
7163 13:53:46.859785 data_rate = 3200,PCW = 0X7600
7164 13:53:46.863354 ===================================
7165 13:53:46.866520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7166 13:53:46.873392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7167 13:53:46.879637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7168 13:53:46.883209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7169 13:53:46.886423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7170 13:53:46.889779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7171 13:53:46.892774 [ANA_INIT] flow start
7172 13:53:46.892876 [ANA_INIT] PLL >>>>>>>>
7173 13:53:46.896133 [ANA_INIT] PLL <<<<<<<<
7174 13:53:46.899725 [ANA_INIT] MIDPI >>>>>>>>
7175 13:53:46.899828 [ANA_INIT] MIDPI <<<<<<<<
7176 13:53:46.902741 [ANA_INIT] DLL >>>>>>>>
7177 13:53:46.906198 [ANA_INIT] DLL <<<<<<<<
7178 13:53:46.906275 [ANA_INIT] flow end
7179 13:53:46.912900 ============ LP4 DIFF to SE enter ============
7180 13:53:46.916122 ============ LP4 DIFF to SE exit ============
7181 13:53:46.919096 [ANA_INIT] <<<<<<<<<<<<<
7182 13:53:46.922572 [Flow] Enable top DCM control >>>>>
7183 13:53:46.925776 [Flow] Enable top DCM control <<<<<
7184 13:53:46.925851 Enable DLL master slave shuffle
7185 13:53:46.932341 ==============================================================
7186 13:53:46.935874 Gating Mode config
7187 13:53:46.938927 ==============================================================
7188 13:53:46.942368 Config description:
7189 13:53:46.952170 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7190 13:53:46.959075 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7191 13:53:46.962284 SELPH_MODE 0: By rank 1: By Phase
7192 13:53:46.968668 ==============================================================
7193 13:53:46.972197 GAT_TRACK_EN = 1
7194 13:53:46.975309 RX_GATING_MODE = 2
7195 13:53:46.978638 RX_GATING_TRACK_MODE = 2
7196 13:53:46.982086 SELPH_MODE = 1
7197 13:53:46.985394 PICG_EARLY_EN = 1
7198 13:53:46.985513 VALID_LAT_VALUE = 1
7199 13:53:46.992052 ==============================================================
7200 13:53:46.995172 Enter into Gating configuration >>>>
7201 13:53:46.998480 Exit from Gating configuration <<<<
7202 13:53:47.001815 Enter into DVFS_PRE_config >>>>>
7203 13:53:47.011874 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7204 13:53:47.015297 Exit from DVFS_PRE_config <<<<<
7205 13:53:47.018200 Enter into PICG configuration >>>>
7206 13:53:47.021618 Exit from PICG configuration <<<<
7207 13:53:47.024736 [RX_INPUT] configuration >>>>>
7208 13:53:47.028367 [RX_INPUT] configuration <<<<<
7209 13:53:47.035048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7210 13:53:47.038196 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7211 13:53:47.044959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 13:53:47.051642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 13:53:47.057902 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7214 13:53:47.064478 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7215 13:53:47.067935 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7216 13:53:47.071076 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7217 13:53:47.074583 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7218 13:53:47.081051 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7219 13:53:47.084276 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7220 13:53:47.087900 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 13:53:47.090865 ===================================
7222 13:53:47.094167 LPDDR4 DRAM CONFIGURATION
7223 13:53:47.097463 ===================================
7224 13:53:47.100904 EX_ROW_EN[0] = 0x0
7225 13:53:47.101006 EX_ROW_EN[1] = 0x0
7226 13:53:47.104120 LP4Y_EN = 0x0
7227 13:53:47.104199 WORK_FSP = 0x1
7228 13:53:47.107518 WL = 0x5
7229 13:53:47.107619 RL = 0x5
7230 13:53:47.110894 BL = 0x2
7231 13:53:47.110971 RPST = 0x0
7232 13:53:47.114073 RD_PRE = 0x0
7233 13:53:47.114153 WR_PRE = 0x1
7234 13:53:47.117235 WR_PST = 0x1
7235 13:53:47.117340 DBI_WR = 0x0
7236 13:53:47.120735 DBI_RD = 0x0
7237 13:53:47.120837 OTF = 0x1
7238 13:53:47.124106 ===================================
7239 13:53:47.130673 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7240 13:53:47.134132 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7241 13:53:47.137344 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7242 13:53:47.140500 ===================================
7243 13:53:47.144044 LPDDR4 DRAM CONFIGURATION
7244 13:53:47.147089 ===================================
7245 13:53:47.150487 EX_ROW_EN[0] = 0x10
7246 13:53:47.150591 EX_ROW_EN[1] = 0x0
7247 13:53:47.153698 LP4Y_EN = 0x0
7248 13:53:47.153771 WORK_FSP = 0x1
7249 13:53:47.156859 WL = 0x5
7250 13:53:47.156960 RL = 0x5
7251 13:53:47.160318 BL = 0x2
7252 13:53:47.160394 RPST = 0x0
7253 13:53:47.163433 RD_PRE = 0x0
7254 13:53:47.163507 WR_PRE = 0x1
7255 13:53:47.166990 WR_PST = 0x1
7256 13:53:47.167069 DBI_WR = 0x0
7257 13:53:47.170469 DBI_RD = 0x0
7258 13:53:47.170545 OTF = 0x1
7259 13:53:47.173667 ===================================
7260 13:53:47.180222 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7261 13:53:47.180303 ==
7262 13:53:47.183279 Dram Type= 6, Freq= 0, CH_0, rank 0
7263 13:53:47.189875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7264 13:53:47.189987 ==
7265 13:53:47.190080 [Duty_Offset_Calibration]
7266 13:53:47.193368 B0:2 B1:0 CA:3
7267 13:53:47.193467
7268 13:53:47.196427 [DutyScan_Calibration_Flow] k_type=0
7269 13:53:47.206010
7270 13:53:47.206092 ==CLK 0==
7271 13:53:47.209093 Final CLK duty delay cell = 0
7272 13:53:47.212627 [0] MAX Duty = 5031%(X100), DQS PI = 12
7273 13:53:47.215658 [0] MIN Duty = 4907%(X100), DQS PI = 6
7274 13:53:47.215767 [0] AVG Duty = 4969%(X100)
7275 13:53:47.219064
7276 13:53:47.222339 CH0 CLK Duty spec in!! Max-Min= 124%
7277 13:53:47.225617 [DutyScan_Calibration_Flow] ====Done====
7278 13:53:47.225722
7279 13:53:47.228839 [DutyScan_Calibration_Flow] k_type=1
7280 13:53:47.245854
7281 13:53:47.245938 ==DQS 0 ==
7282 13:53:47.249112 Final DQS duty delay cell = 0
7283 13:53:47.252304 [0] MAX Duty = 5094%(X100), DQS PI = 14
7284 13:53:47.255795 [0] MIN Duty = 4875%(X100), DQS PI = 48
7285 13:53:47.259229 [0] AVG Duty = 4984%(X100)
7286 13:53:47.259331
7287 13:53:47.259425 ==DQS 1 ==
7288 13:53:47.262372 Final DQS duty delay cell = 0
7289 13:53:47.265512 [0] MAX Duty = 5156%(X100), DQS PI = 32
7290 13:53:47.268885 [0] MIN Duty = 5031%(X100), DQS PI = 12
7291 13:53:47.272121 [0] AVG Duty = 5093%(X100)
7292 13:53:47.272199
7293 13:53:47.275661 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7294 13:53:47.275743
7295 13:53:47.279057 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7296 13:53:47.282244 [DutyScan_Calibration_Flow] ====Done====
7297 13:53:47.282331
7298 13:53:47.285357 [DutyScan_Calibration_Flow] k_type=3
7299 13:53:47.303989
7300 13:53:47.304066 ==DQM 0 ==
7301 13:53:47.307049 Final DQM duty delay cell = 0
7302 13:53:47.310408 [0] MAX Duty = 5156%(X100), DQS PI = 30
7303 13:53:47.313593 [0] MIN Duty = 4844%(X100), DQS PI = 52
7304 13:53:47.317176 [0] AVG Duty = 5000%(X100)
7305 13:53:47.317251
7306 13:53:47.317313 ==DQM 1 ==
7307 13:53:47.320393 Final DQM duty delay cell = 4
7308 13:53:47.323474 [4] MAX Duty = 5187%(X100), DQS PI = 62
7309 13:53:47.326972 [4] MIN Duty = 5031%(X100), DQS PI = 14
7310 13:53:47.330409 [4] AVG Duty = 5109%(X100)
7311 13:53:47.330489
7312 13:53:47.333674 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7313 13:53:47.333753
7314 13:53:47.337072 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7315 13:53:47.340526 [DutyScan_Calibration_Flow] ====Done====
7316 13:53:47.340634
7317 13:53:47.343438 [DutyScan_Calibration_Flow] k_type=2
7318 13:53:47.360152
7319 13:53:47.360258 ==DQ 0 ==
7320 13:53:47.363427 Final DQ duty delay cell = -4
7321 13:53:47.366812 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7322 13:53:47.370039 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7323 13:53:47.373418 [-4] AVG Duty = 4938%(X100)
7324 13:53:47.373529
7325 13:53:47.373620 ==DQ 1 ==
7326 13:53:47.376715 Final DQ duty delay cell = 0
7327 13:53:47.380119 [0] MAX Duty = 5156%(X100), DQS PI = 58
7328 13:53:47.383330 [0] MIN Duty = 5000%(X100), DQS PI = 16
7329 13:53:47.386577 [0] AVG Duty = 5078%(X100)
7330 13:53:47.386653
7331 13:53:47.390124 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7332 13:53:47.390198
7333 13:53:47.393300 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7334 13:53:47.396416 [DutyScan_Calibration_Flow] ====Done====
7335 13:53:47.396489 ==
7336 13:53:47.399817 Dram Type= 6, Freq= 0, CH_1, rank 0
7337 13:53:47.403129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7338 13:53:47.403204 ==
7339 13:53:47.406489 [Duty_Offset_Calibration]
7340 13:53:47.406587 B0:1 B1:-2 CA:1
7341 13:53:47.406680
7342 13:53:47.409675 [DutyScan_Calibration_Flow] k_type=0
7343 13:53:47.420712
7344 13:53:47.420811 ==CLK 0==
7345 13:53:47.424311 Final CLK duty delay cell = 0
7346 13:53:47.427549 [0] MAX Duty = 5062%(X100), DQS PI = 20
7347 13:53:47.430995 [0] MIN Duty = 4844%(X100), DQS PI = 4
7348 13:53:47.431072 [0] AVG Duty = 4953%(X100)
7349 13:53:47.434111
7350 13:53:47.437718 CH1 CLK Duty spec in!! Max-Min= 218%
7351 13:53:47.440683 [DutyScan_Calibration_Flow] ====Done====
7352 13:53:47.440786
7353 13:53:47.443890 [DutyScan_Calibration_Flow] k_type=1
7354 13:53:47.459704
7355 13:53:47.459784 ==DQS 0 ==
7356 13:53:47.463171 Final DQS duty delay cell = -4
7357 13:53:47.466181 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7358 13:53:47.469946 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7359 13:53:47.473039 [-4] AVG Duty = 4922%(X100)
7360 13:53:47.473118
7361 13:53:47.473183 ==DQS 1 ==
7362 13:53:47.476066 Final DQS duty delay cell = 0
7363 13:53:47.479521 [0] MAX Duty = 5093%(X100), DQS PI = 62
7364 13:53:47.483020 [0] MIN Duty = 4844%(X100), DQS PI = 26
7365 13:53:47.486036 [0] AVG Duty = 4968%(X100)
7366 13:53:47.486108
7367 13:53:47.489432 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7368 13:53:47.489552
7369 13:53:47.492854 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7370 13:53:47.495923 [DutyScan_Calibration_Flow] ====Done====
7371 13:53:47.496022
7372 13:53:47.499426 [DutyScan_Calibration_Flow] k_type=3
7373 13:53:47.516867
7374 13:53:47.516971 ==DQM 0 ==
7375 13:53:47.520401 Final DQM duty delay cell = 0
7376 13:53:47.523704 [0] MAX Duty = 5031%(X100), DQS PI = 26
7377 13:53:47.526872 [0] MIN Duty = 4813%(X100), DQS PI = 56
7378 13:53:47.530206 [0] AVG Duty = 4922%(X100)
7379 13:53:47.530282
7380 13:53:47.530344 ==DQM 1 ==
7381 13:53:47.533685 Final DQM duty delay cell = 0
7382 13:53:47.536762 [0] MAX Duty = 5062%(X100), DQS PI = 34
7383 13:53:47.540478 [0] MIN Duty = 4875%(X100), DQS PI = 26
7384 13:53:47.543496 [0] AVG Duty = 4968%(X100)
7385 13:53:47.543582
7386 13:53:47.546946 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7387 13:53:47.547037
7388 13:53:47.550086 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7389 13:53:47.553507 [DutyScan_Calibration_Flow] ====Done====
7390 13:53:47.553623
7391 13:53:47.556553 [DutyScan_Calibration_Flow] k_type=2
7392 13:53:47.573911
7393 13:53:47.573993 ==DQ 0 ==
7394 13:53:47.577124 Final DQ duty delay cell = 0
7395 13:53:47.580392 [0] MAX Duty = 5093%(X100), DQS PI = 22
7396 13:53:47.583830 [0] MIN Duty = 4907%(X100), DQS PI = 58
7397 13:53:47.583934 [0] AVG Duty = 5000%(X100)
7398 13:53:47.587466
7399 13:53:47.587624 ==DQ 1 ==
7400 13:53:47.590517 Final DQ duty delay cell = 0
7401 13:53:47.594009 [0] MAX Duty = 5125%(X100), DQS PI = 34
7402 13:53:47.597097 [0] MIN Duty = 4969%(X100), DQS PI = 24
7403 13:53:47.597173 [0] AVG Duty = 5047%(X100)
7404 13:53:47.600399
7405 13:53:47.603746 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7406 13:53:47.603852
7407 13:53:47.607191 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7408 13:53:47.610569 [DutyScan_Calibration_Flow] ====Done====
7409 13:53:47.613699 nWR fixed to 30
7410 13:53:47.613775 [ModeRegInit_LP4] CH0 RK0
7411 13:53:47.617083 [ModeRegInit_LP4] CH0 RK1
7412 13:53:47.620204 [ModeRegInit_LP4] CH1 RK0
7413 13:53:47.623672 [ModeRegInit_LP4] CH1 RK1
7414 13:53:47.623776 match AC timing 5
7415 13:53:47.630149 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7416 13:53:47.633451 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7417 13:53:47.636682 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7418 13:53:47.643262 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7419 13:53:47.646931 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7420 13:53:47.647016 [MiockJmeterHQA]
7421 13:53:47.647082
7422 13:53:47.650231 [DramcMiockJmeter] u1RxGatingPI = 0
7423 13:53:47.653375 0 : 4363, 4137
7424 13:53:47.653491 4 : 4253, 4026
7425 13:53:47.656939 8 : 4363, 4138
7426 13:53:47.657029 12 : 4252, 4027
7427 13:53:47.657096 16 : 4255, 4029
7428 13:53:47.659877 20 : 4252, 4027
7429 13:53:47.659958 24 : 4366, 4139
7430 13:53:47.663447 28 : 4253, 4026
7431 13:53:47.663554 32 : 4255, 4030
7432 13:53:47.666812 36 : 4253, 4026
7433 13:53:47.666918 40 : 4361, 4137
7434 13:53:47.670125 44 : 4252, 4026
7435 13:53:47.670215 48 : 4360, 4137
7436 13:53:47.670311 52 : 4250, 4027
7437 13:53:47.673157 56 : 4250, 4026
7438 13:53:47.673235 60 : 4250, 4026
7439 13:53:47.676564 64 : 4253, 4029
7440 13:53:47.676640 68 : 4361, 4137
7441 13:53:47.679713 72 : 4252, 4027
7442 13:53:47.679789 76 : 4360, 4137
7443 13:53:47.683179 80 : 4250, 4026
7444 13:53:47.683284 84 : 4250, 4027
7445 13:53:47.683378 88 : 4250, 4026
7446 13:53:47.686638 92 : 4361, 4137
7447 13:53:47.686740 96 : 4250, 4027
7448 13:53:47.689700 100 : 4361, 4137
7449 13:53:47.689803 104 : 4361, 3787
7450 13:53:47.692950 108 : 4250, 1
7451 13:53:47.693029 112 : 4253, 0
7452 13:53:47.693093 116 : 4255, 0
7453 13:53:47.696409 120 : 4361, 0
7454 13:53:47.696515 124 : 4250, 0
7455 13:53:47.699698 128 : 4250, 0
7456 13:53:47.699803 132 : 4250, 0
7457 13:53:47.699897 136 : 4250, 0
7458 13:53:47.703054 140 : 4360, 0
7459 13:53:47.703134 144 : 4361, 0
7460 13:53:47.706294 148 : 4250, 0
7461 13:53:47.706372 152 : 4250, 0
7462 13:53:47.706437 156 : 4250, 0
7463 13:53:47.709623 160 : 4252, 0
7464 13:53:47.709704 164 : 4250, 0
7465 13:53:47.712995 168 : 4250, 0
7466 13:53:47.713068 172 : 4253, 0
7467 13:53:47.713130 176 : 4361, 0
7468 13:53:47.716293 180 : 4250, 0
7469 13:53:47.716368 184 : 4250, 0
7470 13:53:47.716431 188 : 4250, 0
7471 13:53:47.719740 192 : 4360, 0
7472 13:53:47.719889 196 : 4361, 0
7473 13:53:47.722715 200 : 4250, 0
7474 13:53:47.722790 204 : 4250, 0
7475 13:53:47.722853 208 : 4250, 0
7476 13:53:47.726027 212 : 4252, 0
7477 13:53:47.726117 216 : 4250, 0
7478 13:53:47.729203 220 : 4250, 0
7479 13:53:47.729304 224 : 4250, 0
7480 13:53:47.729395 228 : 4361, 0
7481 13:53:47.732811 232 : 4250, 0
7482 13:53:47.732912 236 : 4250, 968
7483 13:53:47.735955 240 : 4360, 4138
7484 13:53:47.736052 244 : 4361, 4137
7485 13:53:47.739386 248 : 4247, 4025
7486 13:53:47.739482 252 : 4361, 4138
7487 13:53:47.742777 256 : 4250, 4027
7488 13:53:47.742849 260 : 4250, 4027
7489 13:53:47.742910 264 : 4250, 4027
7490 13:53:47.745928 268 : 4252, 4030
7491 13:53:47.746001 272 : 4250, 4027
7492 13:53:47.749141 276 : 4250, 4026
7493 13:53:47.749242 280 : 4250, 4027
7494 13:53:47.752749 284 : 4253, 4030
7495 13:53:47.752866 288 : 4250, 4027
7496 13:53:47.755842 292 : 4360, 4137
7497 13:53:47.755942 296 : 4361, 4137
7498 13:53:47.759393 300 : 4250, 4027
7499 13:53:47.759466 304 : 4363, 4140
7500 13:53:47.762841 308 : 4250, 4027
7501 13:53:47.762914 312 : 4250, 4026
7502 13:53:47.765827 316 : 4250, 4027
7503 13:53:47.765905 320 : 4253, 4030
7504 13:53:47.768997 324 : 4250, 4027
7505 13:53:47.769099 328 : 4250, 4026
7506 13:53:47.769188 332 : 4250, 4027
7507 13:53:47.772390 336 : 4252, 4030
7508 13:53:47.772492 340 : 4250, 4027
7509 13:53:47.775969 344 : 4360, 4138
7510 13:53:47.776079 348 : 4361, 4137
7511 13:53:47.779045 352 : 4250, 4021
7512 13:53:47.779208 356 : 4363, 2781
7513 13:53:47.782505 360 : 4250, 2
7514 13:53:47.782604
7515 13:53:47.782696 MIOCK jitter meter ch=0
7516 13:53:47.782782
7517 13:53:47.785739 1T = (360-108) = 252 dly cells
7518 13:53:47.792333 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7519 13:53:47.792411 ==
7520 13:53:47.795720 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 13:53:47.799122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 13:53:47.799197 ==
7523 13:53:47.805795 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7524 13:53:47.808886 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7525 13:53:47.812301 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7526 13:53:47.818694 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7527 13:53:47.828932 [CA 0] Center 43 (13~74) winsize 62
7528 13:53:47.832108 [CA 1] Center 43 (13~74) winsize 62
7529 13:53:47.835461 [CA 2] Center 39 (10~68) winsize 59
7530 13:53:47.838811 [CA 3] Center 39 (10~68) winsize 59
7531 13:53:47.842282 [CA 4] Center 36 (7~66) winsize 60
7532 13:53:47.845208 [CA 5] Center 36 (7~66) winsize 60
7533 13:53:47.845308
7534 13:53:47.848908 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7535 13:53:47.849008
7536 13:53:47.852003 [CATrainingPosCal] consider 1 rank data
7537 13:53:47.855442 u2DelayCellTimex100 = 258/100 ps
7538 13:53:47.862050 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7539 13:53:47.865615 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7540 13:53:47.868902 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7541 13:53:47.871873 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7542 13:53:47.875440 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7543 13:53:47.878442 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7544 13:53:47.878521
7545 13:53:47.881844 CA PerBit enable=1, Macro0, CA PI delay=36
7546 13:53:47.881922
7547 13:53:47.885369 [CBTSetCACLKResult] CA Dly = 36
7548 13:53:47.888363 CS Dly: 11 (0~42)
7549 13:53:47.891843 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7550 13:53:47.895006 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7551 13:53:47.895081 ==
7552 13:53:47.898561 Dram Type= 6, Freq= 0, CH_0, rank 1
7553 13:53:47.905133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 13:53:47.905235 ==
7555 13:53:47.908323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7556 13:53:47.914908 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7557 13:53:47.918287 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7558 13:53:47.924692 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7559 13:53:47.932911 [CA 0] Center 44 (14~75) winsize 62
7560 13:53:47.936303 [CA 1] Center 43 (13~74) winsize 62
7561 13:53:47.939438 [CA 2] Center 39 (10~69) winsize 60
7562 13:53:47.942900 [CA 3] Center 39 (10~69) winsize 60
7563 13:53:47.945876 [CA 4] Center 37 (8~67) winsize 60
7564 13:53:47.949323 [CA 5] Center 37 (7~67) winsize 61
7565 13:53:47.949421
7566 13:53:47.952788 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7567 13:53:47.952889
7568 13:53:47.956074 [CATrainingPosCal] consider 2 rank data
7569 13:53:47.959277 u2DelayCellTimex100 = 258/100 ps
7570 13:53:47.965865 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7571 13:53:47.969232 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7572 13:53:47.972517 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7573 13:53:47.975723 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7574 13:53:47.979251 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7575 13:53:47.982545 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7576 13:53:47.982641
7577 13:53:47.985697 CA PerBit enable=1, Macro0, CA PI delay=36
7578 13:53:47.985770
7579 13:53:47.989118 [CBTSetCACLKResult] CA Dly = 36
7580 13:53:47.992477 CS Dly: 11 (0~42)
7581 13:53:47.995567 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7582 13:53:47.999213 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7583 13:53:47.999286
7584 13:53:48.002219 ----->DramcWriteLeveling(PI) begin...
7585 13:53:48.002292 ==
7586 13:53:48.005710 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 13:53:48.012229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 13:53:48.012309 ==
7589 13:53:48.015543 Write leveling (Byte 0): 38 => 38
7590 13:53:48.018777 Write leveling (Byte 1): 28 => 28
7591 13:53:48.022191 DramcWriteLeveling(PI) end<-----
7592 13:53:48.022266
7593 13:53:48.022327 ==
7594 13:53:48.025618 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 13:53:48.028749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 13:53:48.028824 ==
7597 13:53:48.031794 [Gating] SW mode calibration
7598 13:53:48.038596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7599 13:53:48.045100 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7600 13:53:48.048698 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 13:53:48.051686 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 13:53:48.058527 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 13:53:48.062011 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 13:53:48.065113 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7605 13:53:48.068346 1 4 20 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7606 13:53:48.074974 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7607 13:53:48.078517 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 13:53:48.081748 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 13:53:48.088288 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 13:53:48.091672 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 13:53:48.094850 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 13:53:48.101556 1 5 16 | B1->B0 | 3434 2929 | 1 1 | (1 1) (0 1)
7613 13:53:48.105007 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7614 13:53:48.108198 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7615 13:53:48.114991 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 13:53:48.118289 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 13:53:48.121448 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 13:53:48.127928 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 13:53:48.131434 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 13:53:48.134844 1 6 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7621 13:53:48.141574 1 6 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7622 13:53:48.144685 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 13:53:48.147964 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 13:53:48.154673 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 13:53:48.158098 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 13:53:48.161313 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 13:53:48.167864 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 13:53:48.171332 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 13:53:48.174545 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7630 13:53:48.181231 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 13:53:48.184758 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 13:53:48.187802 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 13:53:48.194412 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 13:53:48.197646 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 13:53:48.201154 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 13:53:48.207576 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 13:53:48.210963 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 13:53:48.214178 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 13:53:48.220886 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 13:53:48.224404 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 13:53:48.227698 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 13:53:48.231064 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 13:53:48.237508 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 13:53:48.241072 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 13:53:48.244156 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7646 13:53:48.247335 Total UI for P1: 0, mck2ui 16
7647 13:53:48.250811 best dqsien dly found for B0: ( 1, 9, 14)
7648 13:53:48.257147 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7649 13:53:48.260588 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 13:53:48.263741 Total UI for P1: 0, mck2ui 16
7651 13:53:48.267002 best dqsien dly found for B1: ( 1, 9, 24)
7652 13:53:48.270391 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7653 13:53:48.273914 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7654 13:53:48.273989
7655 13:53:48.276858 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7656 13:53:48.283561 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7657 13:53:48.283667 [Gating] SW calibration Done
7658 13:53:48.286784 ==
7659 13:53:48.290314 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 13:53:48.293545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 13:53:48.293622 ==
7662 13:53:48.293688 RX Vref Scan: 0
7663 13:53:48.293749
7664 13:53:48.296700 RX Vref 0 -> 0, step: 1
7665 13:53:48.296812
7666 13:53:48.300142 RX Delay 0 -> 252, step: 8
7667 13:53:48.303519 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7668 13:53:48.306943 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7669 13:53:48.309997 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7670 13:53:48.316736 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7671 13:53:48.319999 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7672 13:53:48.323386 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7673 13:53:48.326917 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7674 13:53:48.329928 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7675 13:53:48.336825 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7676 13:53:48.340151 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7677 13:53:48.343443 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7678 13:53:48.346551 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7679 13:53:48.350148 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7680 13:53:48.356395 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7681 13:53:48.359959 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7682 13:53:48.363126 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7683 13:53:48.363228 ==
7684 13:53:48.366625 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 13:53:48.370077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 13:53:48.370158 ==
7687 13:53:48.373320 DQS Delay:
7688 13:53:48.373422 DQS0 = 0, DQS1 = 0
7689 13:53:48.376632 DQM Delay:
7690 13:53:48.376705 DQM0 = 128, DQM1 = 124
7691 13:53:48.379847 DQ Delay:
7692 13:53:48.383215 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7693 13:53:48.386489 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7694 13:53:48.389520 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7695 13:53:48.392993 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7696 13:53:48.393097
7697 13:53:48.393188
7698 13:53:48.393276 ==
7699 13:53:48.396460 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 13:53:48.399647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 13:53:48.399754 ==
7702 13:53:48.399851
7703 13:53:48.399939
7704 13:53:48.403163 TX Vref Scan disable
7705 13:53:48.406523 == TX Byte 0 ==
7706 13:53:48.409625 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7707 13:53:48.413021 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7708 13:53:48.416438 == TX Byte 1 ==
7709 13:53:48.419590 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7710 13:53:48.423084 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7711 13:53:48.423160 ==
7712 13:53:48.426180 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 13:53:48.432700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 13:53:48.432782 ==
7715 13:53:48.445652
7716 13:53:48.448795 TX Vref early break, caculate TX vref
7717 13:53:48.452023 TX Vref=16, minBit 8, minWin=21, winSum=368
7718 13:53:48.455363 TX Vref=18, minBit 8, minWin=22, winSum=378
7719 13:53:48.458769 TX Vref=20, minBit 8, minWin=22, winSum=383
7720 13:53:48.461750 TX Vref=22, minBit 8, minWin=23, winSum=392
7721 13:53:48.465327 TX Vref=24, minBit 8, minWin=23, winSum=399
7722 13:53:48.471981 TX Vref=26, minBit 8, minWin=24, winSum=409
7723 13:53:48.475194 TX Vref=28, minBit 10, minWin=24, winSum=409
7724 13:53:48.478631 TX Vref=30, minBit 8, minWin=23, winSum=404
7725 13:53:48.481900 TX Vref=32, minBit 8, minWin=23, winSum=396
7726 13:53:48.485116 TX Vref=34, minBit 8, minWin=22, winSum=386
7727 13:53:48.491927 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 26
7728 13:53:48.492012
7729 13:53:48.495107 Final TX Range 0 Vref 26
7730 13:53:48.495198
7731 13:53:48.495261 ==
7732 13:53:48.498542 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 13:53:48.501695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 13:53:48.501796 ==
7735 13:53:48.501862
7736 13:53:48.501921
7737 13:53:48.505109 TX Vref Scan disable
7738 13:53:48.511666 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7739 13:53:48.511773 == TX Byte 0 ==
7740 13:53:48.515172 u2DelayCellOfst[0]=11 cells (3 PI)
7741 13:53:48.518582 u2DelayCellOfst[1]=15 cells (4 PI)
7742 13:53:48.521763 u2DelayCellOfst[2]=11 cells (3 PI)
7743 13:53:48.524831 u2DelayCellOfst[3]=11 cells (3 PI)
7744 13:53:48.528365 u2DelayCellOfst[4]=7 cells (2 PI)
7745 13:53:48.531532 u2DelayCellOfst[5]=0 cells (0 PI)
7746 13:53:48.534814 u2DelayCellOfst[6]=15 cells (4 PI)
7747 13:53:48.538490 u2DelayCellOfst[7]=15 cells (4 PI)
7748 13:53:48.541456 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7749 13:53:48.544898 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7750 13:53:48.548134 == TX Byte 1 ==
7751 13:53:48.551497 u2DelayCellOfst[8]=0 cells (0 PI)
7752 13:53:48.551570 u2DelayCellOfst[9]=0 cells (0 PI)
7753 13:53:48.554486 u2DelayCellOfst[10]=7 cells (2 PI)
7754 13:53:48.557975 u2DelayCellOfst[11]=3 cells (1 PI)
7755 13:53:48.561402 u2DelayCellOfst[12]=11 cells (3 PI)
7756 13:53:48.564445 u2DelayCellOfst[13]=11 cells (3 PI)
7757 13:53:48.567752 u2DelayCellOfst[14]=15 cells (4 PI)
7758 13:53:48.571350 u2DelayCellOfst[15]=11 cells (3 PI)
7759 13:53:48.574445 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7760 13:53:48.581137 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7761 13:53:48.581221 DramC Write-DBI on
7762 13:53:48.581302 ==
7763 13:53:48.584497 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 13:53:48.590925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 13:53:48.591007 ==
7766 13:53:48.591072
7767 13:53:48.591132
7768 13:53:48.591197 TX Vref Scan disable
7769 13:53:48.595188 == TX Byte 0 ==
7770 13:53:48.598470 Update DQM dly =739 (2 ,6, 35) DQM OEN =(3 ,3)
7771 13:53:48.602039 == TX Byte 1 ==
7772 13:53:48.605073 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7773 13:53:48.605176 DramC Write-DBI off
7774 13:53:48.608486
7775 13:53:48.608563 [DATLAT]
7776 13:53:48.608626 Freq=1600, CH0 RK0
7777 13:53:48.608712
7778 13:53:48.611747 DATLAT Default: 0xf
7779 13:53:48.611821 0, 0xFFFF, sum = 0
7780 13:53:48.615202 1, 0xFFFF, sum = 0
7781 13:53:48.615311 2, 0xFFFF, sum = 0
7782 13:53:48.618538 3, 0xFFFF, sum = 0
7783 13:53:48.621658 4, 0xFFFF, sum = 0
7784 13:53:48.621735 5, 0xFFFF, sum = 0
7785 13:53:48.625033 6, 0xFFFF, sum = 0
7786 13:53:48.625108 7, 0xFFFF, sum = 0
7787 13:53:48.628420 8, 0xFFFF, sum = 0
7788 13:53:48.628497 9, 0xFFFF, sum = 0
7789 13:53:48.631689 10, 0xFFFF, sum = 0
7790 13:53:48.631769 11, 0xFFFF, sum = 0
7791 13:53:48.634845 12, 0xFFFF, sum = 0
7792 13:53:48.634927 13, 0xEFFF, sum = 0
7793 13:53:48.638148 14, 0x0, sum = 1
7794 13:53:48.638222 15, 0x0, sum = 2
7795 13:53:48.641645 16, 0x0, sum = 3
7796 13:53:48.641722 17, 0x0, sum = 4
7797 13:53:48.644709 best_step = 15
7798 13:53:48.644783
7799 13:53:48.644845 ==
7800 13:53:48.648431 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 13:53:48.651609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 13:53:48.651713 ==
7803 13:53:48.654919 RX Vref Scan: 1
7804 13:53:48.655020
7805 13:53:48.655116 Set Vref Range= 24 -> 127
7806 13:53:48.655205
7807 13:53:48.658069 RX Vref 24 -> 127, step: 1
7808 13:53:48.658144
7809 13:53:48.661557 RX Delay 11 -> 252, step: 4
7810 13:53:48.661633
7811 13:53:48.664781 Set Vref, RX VrefLevel [Byte0]: 24
7812 13:53:48.668049 [Byte1]: 24
7813 13:53:48.668123
7814 13:53:48.671462 Set Vref, RX VrefLevel [Byte0]: 25
7815 13:53:48.674711 [Byte1]: 25
7816 13:53:48.678338
7817 13:53:48.678442 Set Vref, RX VrefLevel [Byte0]: 26
7818 13:53:48.681402 [Byte1]: 26
7819 13:53:48.685382
7820 13:53:48.685488 Set Vref, RX VrefLevel [Byte0]: 27
7821 13:53:48.688879 [Byte1]: 27
7822 13:53:48.693095
7823 13:53:48.693170 Set Vref, RX VrefLevel [Byte0]: 28
7824 13:53:48.696327 [Byte1]: 28
7825 13:53:48.700767
7826 13:53:48.700874 Set Vref, RX VrefLevel [Byte0]: 29
7827 13:53:48.704361 [Byte1]: 29
7828 13:53:48.708237
7829 13:53:48.708312 Set Vref, RX VrefLevel [Byte0]: 30
7830 13:53:48.711812 [Byte1]: 30
7831 13:53:48.716195
7832 13:53:48.716269 Set Vref, RX VrefLevel [Byte0]: 31
7833 13:53:48.719408 [Byte1]: 31
7834 13:53:48.723707
7835 13:53:48.723780 Set Vref, RX VrefLevel [Byte0]: 32
7836 13:53:48.726789 [Byte1]: 32
7837 13:53:48.731162
7838 13:53:48.731237 Set Vref, RX VrefLevel [Byte0]: 33
7839 13:53:48.734320 [Byte1]: 33
7840 13:53:48.738843
7841 13:53:48.738943 Set Vref, RX VrefLevel [Byte0]: 34
7842 13:53:48.742093 [Byte1]: 34
7843 13:53:48.746294
7844 13:53:48.746370 Set Vref, RX VrefLevel [Byte0]: 35
7845 13:53:48.749861 [Byte1]: 35
7846 13:53:48.754347
7847 13:53:48.754446 Set Vref, RX VrefLevel [Byte0]: 36
7848 13:53:48.757392 [Byte1]: 36
7849 13:53:48.761758
7850 13:53:48.761836 Set Vref, RX VrefLevel [Byte0]: 37
7851 13:53:48.764904 [Byte1]: 37
7852 13:53:48.769393
7853 13:53:48.769507 Set Vref, RX VrefLevel [Byte0]: 38
7854 13:53:48.772733 [Byte1]: 38
7855 13:53:48.776929
7856 13:53:48.777053 Set Vref, RX VrefLevel [Byte0]: 39
7857 13:53:48.780160 [Byte1]: 39
7858 13:53:48.784341
7859 13:53:48.784415 Set Vref, RX VrefLevel [Byte0]: 40
7860 13:53:48.787641 [Byte1]: 40
7861 13:53:48.792054
7862 13:53:48.792136 Set Vref, RX VrefLevel [Byte0]: 41
7863 13:53:48.795510 [Byte1]: 41
7864 13:53:48.799794
7865 13:53:48.799868 Set Vref, RX VrefLevel [Byte0]: 42
7866 13:53:48.803131 [Byte1]: 42
7867 13:53:48.807111
7868 13:53:48.807187 Set Vref, RX VrefLevel [Byte0]: 43
7869 13:53:48.810636 [Byte1]: 43
7870 13:53:48.814919
7871 13:53:48.815023 Set Vref, RX VrefLevel [Byte0]: 44
7872 13:53:48.818117 [Byte1]: 44
7873 13:53:48.822783
7874 13:53:48.822859 Set Vref, RX VrefLevel [Byte0]: 45
7875 13:53:48.825857 [Byte1]: 45
7876 13:53:48.830220
7877 13:53:48.830324 Set Vref, RX VrefLevel [Byte0]: 46
7878 13:53:48.833400 [Byte1]: 46
7879 13:53:48.837751
7880 13:53:48.837830 Set Vref, RX VrefLevel [Byte0]: 47
7881 13:53:48.841088 [Byte1]: 47
7882 13:53:48.845358
7883 13:53:48.845434 Set Vref, RX VrefLevel [Byte0]: 48
7884 13:53:48.848587 [Byte1]: 48
7885 13:53:48.853049
7886 13:53:48.853128 Set Vref, RX VrefLevel [Byte0]: 49
7887 13:53:48.856163 [Byte1]: 49
7888 13:53:48.860836
7889 13:53:48.860939 Set Vref, RX VrefLevel [Byte0]: 50
7890 13:53:48.864055 [Byte1]: 50
7891 13:53:48.868172
7892 13:53:48.868281 Set Vref, RX VrefLevel [Byte0]: 51
7893 13:53:48.871344 [Byte1]: 51
7894 13:53:48.875986
7895 13:53:48.876061 Set Vref, RX VrefLevel [Byte0]: 52
7896 13:53:48.878959 [Byte1]: 52
7897 13:53:48.883439
7898 13:53:48.883514 Set Vref, RX VrefLevel [Byte0]: 53
7899 13:53:48.886628 [Byte1]: 53
7900 13:53:48.891173
7901 13:53:48.891251 Set Vref, RX VrefLevel [Byte0]: 54
7902 13:53:48.894568 [Byte1]: 54
7903 13:53:48.898786
7904 13:53:48.898865 Set Vref, RX VrefLevel [Byte0]: 55
7905 13:53:48.902071 [Byte1]: 55
7906 13:53:48.906369
7907 13:53:48.906452 Set Vref, RX VrefLevel [Byte0]: 56
7908 13:53:48.909679 [Byte1]: 56
7909 13:53:48.913962
7910 13:53:48.914043 Set Vref, RX VrefLevel [Byte0]: 57
7911 13:53:48.917040 [Byte1]: 57
7912 13:53:48.921376
7913 13:53:48.921489 Set Vref, RX VrefLevel [Byte0]: 58
7914 13:53:48.924793 [Byte1]: 58
7915 13:53:48.929115
7916 13:53:48.929220 Set Vref, RX VrefLevel [Byte0]: 59
7917 13:53:48.932582 [Byte1]: 59
7918 13:53:48.936760
7919 13:53:48.936859 Set Vref, RX VrefLevel [Byte0]: 60
7920 13:53:48.940194 [Byte1]: 60
7921 13:53:48.944407
7922 13:53:48.944517 Set Vref, RX VrefLevel [Byte0]: 61
7923 13:53:48.947501 [Byte1]: 61
7924 13:53:48.951899
7925 13:53:48.952002 Set Vref, RX VrefLevel [Byte0]: 62
7926 13:53:48.955326 [Byte1]: 62
7927 13:53:48.959427
7928 13:53:48.959508 Set Vref, RX VrefLevel [Byte0]: 63
7929 13:53:48.962962 [Byte1]: 63
7930 13:53:48.967225
7931 13:53:48.967305 Set Vref, RX VrefLevel [Byte0]: 64
7932 13:53:48.970367 [Byte1]: 64
7933 13:53:48.974902
7934 13:53:48.974979 Set Vref, RX VrefLevel [Byte0]: 65
7935 13:53:48.978059 [Byte1]: 65
7936 13:53:48.982396
7937 13:53:48.982497 Set Vref, RX VrefLevel [Byte0]: 66
7938 13:53:48.985898 [Byte1]: 66
7939 13:53:48.989868
7940 13:53:48.989968 Set Vref, RX VrefLevel [Byte0]: 67
7941 13:53:48.993360 [Byte1]: 67
7942 13:53:48.997888
7943 13:53:48.997994 Set Vref, RX VrefLevel [Byte0]: 68
7944 13:53:49.000948 [Byte1]: 68
7945 13:53:49.005395
7946 13:53:49.005503 Set Vref, RX VrefLevel [Byte0]: 69
7947 13:53:49.008556 [Byte1]: 69
7948 13:53:49.012823
7949 13:53:49.012924 Set Vref, RX VrefLevel [Byte0]: 70
7950 13:53:49.016144 [Byte1]: 70
7951 13:53:49.020412
7952 13:53:49.020523 Set Vref, RX VrefLevel [Byte0]: 71
7953 13:53:49.023802 [Byte1]: 71
7954 13:53:49.028149
7955 13:53:49.028240 Set Vref, RX VrefLevel [Byte0]: 72
7956 13:53:49.031310 [Byte1]: 72
7957 13:53:49.035496
7958 13:53:49.035572 Set Vref, RX VrefLevel [Byte0]: 73
7959 13:53:49.039089 [Byte1]: 73
7960 13:53:49.043066
7961 13:53:49.043143 Set Vref, RX VrefLevel [Byte0]: 74
7962 13:53:49.046543 [Byte1]: 74
7963 13:53:49.050826
7964 13:53:49.050901 Set Vref, RX VrefLevel [Byte0]: 75
7965 13:53:49.054158 [Byte1]: 75
7966 13:53:49.058396
7967 13:53:49.058473 Set Vref, RX VrefLevel [Byte0]: 76
7968 13:53:49.061650 [Byte1]: 76
7969 13:53:49.066331
7970 13:53:49.066415 Set Vref, RX VrefLevel [Byte0]: 77
7971 13:53:49.069553 [Byte1]: 77
7972 13:53:49.073650
7973 13:53:49.073732 Final RX Vref Byte 0 = 65 to rank0
7974 13:53:49.077289 Final RX Vref Byte 1 = 61 to rank0
7975 13:53:49.080339 Final RX Vref Byte 0 = 65 to rank1
7976 13:53:49.083920 Final RX Vref Byte 1 = 61 to rank1==
7977 13:53:49.086996 Dram Type= 6, Freq= 0, CH_0, rank 0
7978 13:53:49.093872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 13:53:49.093949 ==
7980 13:53:49.094014 DQS Delay:
7981 13:53:49.094083 DQS0 = 0, DQS1 = 0
7982 13:53:49.096982 DQM Delay:
7983 13:53:49.097081 DQM0 = 126, DQM1 = 119
7984 13:53:49.100429 DQ Delay:
7985 13:53:49.103723 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7986 13:53:49.107157 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7987 13:53:49.110416 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7988 13:53:49.113596 DQ12 =124, DQ13 =124, DQ14 =132, DQ15 =126
7989 13:53:49.113671
7990 13:53:49.113733
7991 13:53:49.113800
7992 13:53:49.116693 [DramC_TX_OE_Calibration] TA2
7993 13:53:49.120060 Original DQ_B0 (3 6) =30, OEN = 27
7994 13:53:49.123545 Original DQ_B1 (3 6) =30, OEN = 27
7995 13:53:49.126884 24, 0x0, End_B0=24 End_B1=24
7996 13:53:49.127001 25, 0x0, End_B0=25 End_B1=25
7997 13:53:49.130102 26, 0x0, End_B0=26 End_B1=26
7998 13:53:49.133306 27, 0x0, End_B0=27 End_B1=27
7999 13:53:49.136588 28, 0x0, End_B0=28 End_B1=28
8000 13:53:49.139943 29, 0x0, End_B0=29 End_B1=29
8001 13:53:49.140086 30, 0x0, End_B0=30 End_B1=30
8002 13:53:49.143332 31, 0x4101, End_B0=30 End_B1=30
8003 13:53:49.146578 Byte0 end_step=30 best_step=27
8004 13:53:49.149943 Byte1 end_step=30 best_step=27
8005 13:53:49.153438 Byte0 TX OE(2T, 0.5T) = (3, 3)
8006 13:53:49.156761 Byte1 TX OE(2T, 0.5T) = (3, 3)
8007 13:53:49.156906
8008 13:53:49.156996
8009 13:53:49.163430 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8010 13:53:49.166506 CH0 RK0: MR19=303, MR18=1514
8011 13:53:49.173155 CH0_RK0: MR19=0x303, MR18=0x1514, DQSOSC=399, MR23=63, INC=23, DEC=15
8012 13:53:49.173261
8013 13:53:49.176370 ----->DramcWriteLeveling(PI) begin...
8014 13:53:49.176474 ==
8015 13:53:49.179937 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 13:53:49.183190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 13:53:49.183268 ==
8018 13:53:49.186337 Write leveling (Byte 0): 33 => 33
8019 13:53:49.189710 Write leveling (Byte 1): 28 => 28
8020 13:53:49.193188 DramcWriteLeveling(PI) end<-----
8021 13:53:49.193259
8022 13:53:49.193321 ==
8023 13:53:49.196356 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 13:53:49.199795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 13:53:49.199869 ==
8026 13:53:49.202873 [Gating] SW mode calibration
8027 13:53:49.209815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8028 13:53:49.216349 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8029 13:53:49.219781 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 13:53:49.226174 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 13:53:49.229727 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 13:53:49.233007 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8033 13:53:49.235999 1 4 16 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
8034 13:53:49.242720 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 13:53:49.246089 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 13:53:49.249409 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 13:53:49.256260 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 13:53:49.259465 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 13:53:49.262508 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8040 13:53:49.269407 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8041 13:53:49.272452 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8042 13:53:49.275892 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8043 13:53:49.282430 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 13:53:49.285982 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 13:53:49.289320 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 13:53:49.295893 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 13:53:49.298970 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8048 13:53:49.302460 1 6 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8049 13:53:49.309141 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8050 13:53:49.312272 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8051 13:53:49.315729 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 13:53:49.322414 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 13:53:49.325721 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 13:53:49.328933 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 13:53:49.335845 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 13:53:49.339017 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8057 13:53:49.342142 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8058 13:53:49.349168 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8059 13:53:49.352391 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 13:53:49.355534 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 13:53:49.362260 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 13:53:49.365593 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 13:53:49.368764 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 13:53:49.375402 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 13:53:49.378757 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 13:53:49.381719 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 13:53:49.388648 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 13:53:49.391768 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 13:53:49.395094 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 13:53:49.401909 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 13:53:49.404871 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8072 13:53:49.408155 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8073 13:53:49.411783 Total UI for P1: 0, mck2ui 16
8074 13:53:49.414942 best dqsien dly found for B0: ( 1, 9, 8)
8075 13:53:49.421834 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8076 13:53:49.424969 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8077 13:53:49.428093 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 13:53:49.431590 Total UI for P1: 0, mck2ui 16
8079 13:53:49.434663 best dqsien dly found for B1: ( 1, 9, 20)
8080 13:53:49.438099 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8081 13:53:49.441491 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8082 13:53:49.441583
8083 13:53:49.444786 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8084 13:53:49.451399 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8085 13:53:49.451487 [Gating] SW calibration Done
8086 13:53:49.454781 ==
8087 13:53:49.454859 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 13:53:49.461499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 13:53:49.461580 ==
8090 13:53:49.461648 RX Vref Scan: 0
8091 13:53:49.461714
8092 13:53:49.464674 RX Vref 0 -> 0, step: 1
8093 13:53:49.464747
8094 13:53:49.467920 RX Delay 0 -> 252, step: 8
8095 13:53:49.471384 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8096 13:53:49.474851 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8097 13:53:49.478422 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8098 13:53:49.481488 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8099 13:53:49.488121 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8100 13:53:49.491464 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8101 13:53:49.494640 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8102 13:53:49.498138 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8103 13:53:49.501169 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8104 13:53:49.507989 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8105 13:53:49.511175 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8106 13:53:49.514638 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8107 13:53:49.517803 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8108 13:53:49.524480 iDelay=200, Bit 13, Center 123 (64 ~ 183) 120
8109 13:53:49.527715 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8110 13:53:49.531235 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8111 13:53:49.531340 ==
8112 13:53:49.534376 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 13:53:49.537494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 13:53:49.537568 ==
8115 13:53:49.541165 DQS Delay:
8116 13:53:49.541268 DQS0 = 0, DQS1 = 0
8117 13:53:49.544118 DQM Delay:
8118 13:53:49.544218 DQM0 = 127, DQM1 = 121
8119 13:53:49.547593 DQ Delay:
8120 13:53:49.550937 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8121 13:53:49.554040 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8122 13:53:49.557496 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8123 13:53:49.560618 DQ12 =127, DQ13 =123, DQ14 =131, DQ15 =127
8124 13:53:49.560726
8125 13:53:49.560820
8126 13:53:49.560884 ==
8127 13:53:49.563755 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 13:53:49.567334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 13:53:49.567419 ==
8130 13:53:49.567488
8131 13:53:49.570567
8132 13:53:49.570642 TX Vref Scan disable
8133 13:53:49.573716 == TX Byte 0 ==
8134 13:53:49.577323 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8135 13:53:49.580334 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8136 13:53:49.583729 == TX Byte 1 ==
8137 13:53:49.587244 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8138 13:53:49.590720 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8139 13:53:49.590799 ==
8140 13:53:49.593816 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 13:53:49.600215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 13:53:49.600319 ==
8143 13:53:49.612245
8144 13:53:49.615773 TX Vref early break, caculate TX vref
8145 13:53:49.619178 TX Vref=16, minBit 8, minWin=21, winSum=366
8146 13:53:49.622267 TX Vref=18, minBit 0, minWin=22, winSum=370
8147 13:53:49.625547 TX Vref=20, minBit 7, minWin=23, winSum=385
8148 13:53:49.628887 TX Vref=22, minBit 7, minWin=23, winSum=390
8149 13:53:49.632449 TX Vref=24, minBit 0, minWin=24, winSum=397
8150 13:53:49.639169 TX Vref=26, minBit 1, minWin=24, winSum=408
8151 13:53:49.642310 TX Vref=28, minBit 1, minWin=25, winSum=409
8152 13:53:49.645849 TX Vref=30, minBit 8, minWin=24, winSum=407
8153 13:53:49.649095 TX Vref=32, minBit 8, minWin=23, winSum=394
8154 13:53:49.652244 TX Vref=34, minBit 8, minWin=23, winSum=387
8155 13:53:49.658864 [TxChooseVref] Worse bit 1, Min win 25, Win sum 409, Final Vref 28
8156 13:53:49.658969
8157 13:53:49.662417 Final TX Range 0 Vref 28
8158 13:53:49.662490
8159 13:53:49.662553 ==
8160 13:53:49.665408 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 13:53:49.668902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 13:53:49.668976 ==
8163 13:53:49.669039
8164 13:53:49.669102
8165 13:53:49.672398 TX Vref Scan disable
8166 13:53:49.679022 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8167 13:53:49.679102 == TX Byte 0 ==
8168 13:53:49.682177 u2DelayCellOfst[0]=11 cells (3 PI)
8169 13:53:49.685628 u2DelayCellOfst[1]=18 cells (5 PI)
8170 13:53:49.688585 u2DelayCellOfst[2]=11 cells (3 PI)
8171 13:53:49.692109 u2DelayCellOfst[3]=11 cells (3 PI)
8172 13:53:49.695216 u2DelayCellOfst[4]=7 cells (2 PI)
8173 13:53:49.698862 u2DelayCellOfst[5]=0 cells (0 PI)
8174 13:53:49.702194 u2DelayCellOfst[6]=18 cells (5 PI)
8175 13:53:49.705629 u2DelayCellOfst[7]=15 cells (4 PI)
8176 13:53:49.708542 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8177 13:53:49.712125 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8178 13:53:49.715382 == TX Byte 1 ==
8179 13:53:49.715472 u2DelayCellOfst[8]=0 cells (0 PI)
8180 13:53:49.718639 u2DelayCellOfst[9]=0 cells (0 PI)
8181 13:53:49.721820 u2DelayCellOfst[10]=11 cells (3 PI)
8182 13:53:49.725278 u2DelayCellOfst[11]=7 cells (2 PI)
8183 13:53:49.728489 u2DelayCellOfst[12]=15 cells (4 PI)
8184 13:53:49.732156 u2DelayCellOfst[13]=11 cells (3 PI)
8185 13:53:49.735542 u2DelayCellOfst[14]=15 cells (4 PI)
8186 13:53:49.738861 u2DelayCellOfst[15]=15 cells (4 PI)
8187 13:53:49.741955 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8188 13:53:49.748570 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8189 13:53:49.748684 DramC Write-DBI on
8190 13:53:49.748807 ==
8191 13:53:49.751820 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 13:53:49.755338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 13:53:49.758544 ==
8194 13:53:49.758640
8195 13:53:49.758748
8196 13:53:49.758836 TX Vref Scan disable
8197 13:53:49.762130 == TX Byte 0 ==
8198 13:53:49.765161 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8199 13:53:49.768331 == TX Byte 1 ==
8200 13:53:49.771895 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8201 13:53:49.775345 DramC Write-DBI off
8202 13:53:49.775443
8203 13:53:49.775533 [DATLAT]
8204 13:53:49.775672 Freq=1600, CH0 RK1
8205 13:53:49.775800
8206 13:53:49.778587 DATLAT Default: 0xf
8207 13:53:49.781780 0, 0xFFFF, sum = 0
8208 13:53:49.781854 1, 0xFFFF, sum = 0
8209 13:53:49.785167 2, 0xFFFF, sum = 0
8210 13:53:49.785237 3, 0xFFFF, sum = 0
8211 13:53:49.788387 4, 0xFFFF, sum = 0
8212 13:53:49.788462 5, 0xFFFF, sum = 0
8213 13:53:49.792336 6, 0xFFFF, sum = 0
8214 13:53:49.792426 7, 0xFFFF, sum = 0
8215 13:53:49.794809 8, 0xFFFF, sum = 0
8216 13:53:49.794898 9, 0xFFFF, sum = 0
8217 13:53:49.798195 10, 0xFFFF, sum = 0
8218 13:53:49.798273 11, 0xFFFF, sum = 0
8219 13:53:49.801346 12, 0xFFFF, sum = 0
8220 13:53:49.801445 13, 0xCFFF, sum = 0
8221 13:53:49.804821 14, 0x0, sum = 1
8222 13:53:49.804897 15, 0x0, sum = 2
8223 13:53:49.808348 16, 0x0, sum = 3
8224 13:53:49.808456 17, 0x0, sum = 4
8225 13:53:49.811373 best_step = 15
8226 13:53:49.811449
8227 13:53:49.811553 ==
8228 13:53:49.814891 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 13:53:49.818015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 13:53:49.818095 ==
8231 13:53:49.821203 RX Vref Scan: 0
8232 13:53:49.821300
8233 13:53:49.821402 RX Vref 0 -> 0, step: 1
8234 13:53:49.821496
8235 13:53:49.824835 RX Delay 3 -> 252, step: 4
8236 13:53:49.831406 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8237 13:53:49.834502 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8238 13:53:49.838016 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8239 13:53:49.841343 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8240 13:53:49.844499 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8241 13:53:49.851396 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8242 13:53:49.854557 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8243 13:53:49.857671 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8244 13:53:49.861337 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8245 13:53:49.864380 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8246 13:53:49.870904 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8247 13:53:49.874394 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8248 13:53:49.877482 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8249 13:53:49.881000 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8250 13:53:49.884251 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8251 13:53:49.890861 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8252 13:53:49.890948 ==
8253 13:53:49.894377 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 13:53:49.897407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 13:53:49.897504 ==
8256 13:53:49.897593 DQS Delay:
8257 13:53:49.900986 DQS0 = 0, DQS1 = 0
8258 13:53:49.901071 DQM Delay:
8259 13:53:49.904105 DQM0 = 125, DQM1 = 117
8260 13:53:49.904201 DQ Delay:
8261 13:53:49.907590 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8262 13:53:49.910640 DQ4 =124, DQ5 =112, DQ6 =136, DQ7 =134
8263 13:53:49.914011 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8264 13:53:49.917395 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8265 13:53:49.920462
8266 13:53:49.920573
8267 13:53:49.920666
8268 13:53:49.920730 [DramC_TX_OE_Calibration] TA2
8269 13:53:49.923964 Original DQ_B0 (3 6) =30, OEN = 27
8270 13:53:49.927416 Original DQ_B1 (3 6) =30, OEN = 27
8271 13:53:49.930587 24, 0x0, End_B0=24 End_B1=24
8272 13:53:49.933804 25, 0x0, End_B0=25 End_B1=25
8273 13:53:49.937085 26, 0x0, End_B0=26 End_B1=26
8274 13:53:49.937169 27, 0x0, End_B0=27 End_B1=27
8275 13:53:49.940375 28, 0x0, End_B0=28 End_B1=28
8276 13:53:49.943507 29, 0x0, End_B0=29 End_B1=29
8277 13:53:49.946775 30, 0x0, End_B0=30 End_B1=30
8278 13:53:49.950429 31, 0x4141, End_B0=30 End_B1=30
8279 13:53:49.953793 Byte0 end_step=30 best_step=27
8280 13:53:49.953876 Byte1 end_step=30 best_step=27
8281 13:53:49.956927 Byte0 TX OE(2T, 0.5T) = (3, 3)
8282 13:53:49.960040 Byte1 TX OE(2T, 0.5T) = (3, 3)
8283 13:53:49.960124
8284 13:53:49.960189
8285 13:53:49.970144 [DQSOSCAuto] RK1, (LSB)MR18= 0x2512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8286 13:53:49.970229 CH0 RK1: MR19=303, MR18=2512
8287 13:53:49.976691 CH0_RK1: MR19=0x303, MR18=0x2512, DQSOSC=391, MR23=63, INC=24, DEC=16
8288 13:53:49.980162 [RxdqsGatingPostProcess] freq 1600
8289 13:53:49.986695 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8290 13:53:49.990143 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 13:53:49.993406 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 13:53:49.996636 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 13:53:50.000126 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 13:53:50.000204 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 13:53:50.003253 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 13:53:50.006809 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 13:53:50.009959 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 13:53:50.013527 Pre-setting of DQS Precalculation
8299 13:53:50.019975 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8300 13:53:50.020077 ==
8301 13:53:50.023484 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 13:53:50.026546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 13:53:50.026666 ==
8304 13:53:50.033426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8305 13:53:50.036399 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8306 13:53:50.039669 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8307 13:53:50.046591 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8308 13:53:50.055164 [CA 0] Center 41 (12~71) winsize 60
8309 13:53:50.058416 [CA 1] Center 42 (12~72) winsize 61
8310 13:53:50.061783 [CA 2] Center 38 (9~67) winsize 59
8311 13:53:50.064874 [CA 3] Center 37 (8~66) winsize 59
8312 13:53:50.068384 [CA 4] Center 37 (8~67) winsize 60
8313 13:53:50.071502 [CA 5] Center 36 (7~66) winsize 60
8314 13:53:50.071579
8315 13:53:50.075198 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8316 13:53:50.075271
8317 13:53:50.078253 [CATrainingPosCal] consider 1 rank data
8318 13:53:50.081719 u2DelayCellTimex100 = 258/100 ps
8319 13:53:50.084907 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8320 13:53:50.091495 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8321 13:53:50.095071 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8322 13:53:50.098109 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8323 13:53:50.101718 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8324 13:53:50.104880 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8325 13:53:50.104980
8326 13:53:50.108174 CA PerBit enable=1, Macro0, CA PI delay=36
8327 13:53:50.108271
8328 13:53:50.111331 [CBTSetCACLKResult] CA Dly = 36
8329 13:53:50.114835 CS Dly: 10 (0~41)
8330 13:53:50.117945 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8331 13:53:50.121327 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8332 13:53:50.121399 ==
8333 13:53:50.124662 Dram Type= 6, Freq= 0, CH_1, rank 1
8334 13:53:50.127960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 13:53:50.131388 ==
8336 13:53:50.134859 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 13:53:50.138032 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 13:53:50.144686 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 13:53:50.147984 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 13:53:50.158050 [CA 0] Center 41 (12~71) winsize 60
8341 13:53:50.161625 [CA 1] Center 42 (13~72) winsize 60
8342 13:53:50.165074 [CA 2] Center 37 (8~67) winsize 60
8343 13:53:50.168330 [CA 3] Center 36 (7~66) winsize 60
8344 13:53:50.171408 [CA 4] Center 37 (8~67) winsize 60
8345 13:53:50.174882 [CA 5] Center 36 (6~66) winsize 61
8346 13:53:50.174964
8347 13:53:50.178351 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8348 13:53:50.178462
8349 13:53:50.181280 [CATrainingPosCal] consider 2 rank data
8350 13:53:50.184762 u2DelayCellTimex100 = 258/100 ps
8351 13:53:50.188056 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8352 13:53:50.194832 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8353 13:53:50.198218 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8354 13:53:50.201416 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8355 13:53:50.204837 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8356 13:53:50.208143 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8357 13:53:50.208226
8358 13:53:50.211360 CA PerBit enable=1, Macro0, CA PI delay=36
8359 13:53:50.211443
8360 13:53:50.214754 [CBTSetCACLKResult] CA Dly = 36
8361 13:53:50.217969 CS Dly: 11 (0~43)
8362 13:53:50.221038 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 13:53:50.224576 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 13:53:50.224660
8365 13:53:50.227736 ----->DramcWriteLeveling(PI) begin...
8366 13:53:50.227847 ==
8367 13:53:50.231028 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 13:53:50.237748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 13:53:50.237833 ==
8370 13:53:50.241178 Write leveling (Byte 0): 25 => 25
8371 13:53:50.241273 Write leveling (Byte 1): 29 => 29
8372 13:53:50.244215 DramcWriteLeveling(PI) end<-----
8373 13:53:50.244322
8374 13:53:50.244389 ==
8375 13:53:50.247609 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 13:53:50.254428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 13:53:50.254512 ==
8378 13:53:50.257919 [Gating] SW mode calibration
8379 13:53:50.264450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8380 13:53:50.267623 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8381 13:53:50.274673 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 13:53:50.277609 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 13:53:50.280925 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 13:53:50.287448 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 13:53:50.290796 1 4 16 | B1->B0 | 3232 3131 | 1 0 | (1 1) (0 0)
8386 13:53:50.294081 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 13:53:50.300761 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 13:53:50.304048 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 13:53:50.307145 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 13:53:50.314095 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 13:53:50.317416 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 13:53:50.320563 1 5 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
8393 13:53:50.327233 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
8394 13:53:50.330793 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 13:53:50.333811 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 13:53:50.337304 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 13:53:50.344113 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 13:53:50.347258 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 13:53:50.350383 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 13:53:50.356929 1 6 12 | B1->B0 | 2a2a 2828 | 0 0 | (0 0) (1 1)
8401 13:53:50.360514 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8402 13:53:50.363640 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 13:53:50.370118 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 13:53:50.373353 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 13:53:50.376843 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 13:53:50.383736 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 13:53:50.386865 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 13:53:50.390134 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 13:53:50.396957 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8410 13:53:50.399931 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 13:53:50.403323 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 13:53:50.409871 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 13:53:50.413256 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 13:53:50.416597 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 13:53:50.423143 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 13:53:50.426513 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 13:53:50.430079 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 13:53:50.436380 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 13:53:50.439766 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 13:53:50.443300 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 13:53:50.449992 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 13:53:50.453088 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 13:53:50.456618 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 13:53:50.462878 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8425 13:53:50.466386 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8426 13:53:50.469811 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8427 13:53:50.476510 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 13:53:50.476610 Total UI for P1: 0, mck2ui 16
8429 13:53:50.482833 best dqsien dly found for B0: ( 1, 9, 16)
8430 13:53:50.482912 Total UI for P1: 0, mck2ui 16
8431 13:53:50.489562 best dqsien dly found for B1: ( 1, 9, 16)
8432 13:53:50.492801 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8433 13:53:50.496062 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8434 13:53:50.496161
8435 13:53:50.499399 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8436 13:53:50.502884 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8437 13:53:50.505978 [Gating] SW calibration Done
8438 13:53:50.506053 ==
8439 13:53:50.509333 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 13:53:50.512837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 13:53:50.512947 ==
8442 13:53:50.515851 RX Vref Scan: 0
8443 13:53:50.515932
8444 13:53:50.515994 RX Vref 0 -> 0, step: 1
8445 13:53:50.516053
8446 13:53:50.519257 RX Delay 0 -> 252, step: 8
8447 13:53:50.522490 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8448 13:53:50.529313 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8449 13:53:50.532478 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8450 13:53:50.535780 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8451 13:53:50.538860 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8452 13:53:50.542261 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8453 13:53:50.548967 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8454 13:53:50.552184 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8455 13:53:50.555427 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8456 13:53:50.558873 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8457 13:53:50.562054 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8458 13:53:50.568811 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8459 13:53:50.571893 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8460 13:53:50.575455 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8461 13:53:50.578544 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8462 13:53:50.585517 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8463 13:53:50.585601 ==
8464 13:53:50.588589 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 13:53:50.591882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 13:53:50.591966 ==
8467 13:53:50.592032 DQS Delay:
8468 13:53:50.595158 DQS0 = 0, DQS1 = 0
8469 13:53:50.595242 DQM Delay:
8470 13:53:50.598708 DQM0 = 132, DQM1 = 126
8471 13:53:50.598792 DQ Delay:
8472 13:53:50.601712 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8473 13:53:50.605435 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8474 13:53:50.608485 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8475 13:53:50.611810 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8476 13:53:50.611893
8477 13:53:50.611958
8478 13:53:50.615167 ==
8479 13:53:50.618659 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 13:53:50.621789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 13:53:50.621887 ==
8482 13:53:50.621950
8483 13:53:50.622010
8484 13:53:50.624896 TX Vref Scan disable
8485 13:53:50.624993 == TX Byte 0 ==
8486 13:53:50.631608 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8487 13:53:50.634819 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8488 13:53:50.634901 == TX Byte 1 ==
8489 13:53:50.641609 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8490 13:53:50.644726 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8491 13:53:50.644803 ==
8492 13:53:50.647973 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 13:53:50.651072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 13:53:50.651147 ==
8495 13:53:50.664608
8496 13:53:50.667883 TX Vref early break, caculate TX vref
8497 13:53:50.671506 TX Vref=16, minBit 11, minWin=20, winSum=359
8498 13:53:50.674633 TX Vref=18, minBit 8, minWin=21, winSum=366
8499 13:53:50.678113 TX Vref=20, minBit 11, minWin=22, winSum=379
8500 13:53:50.681236 TX Vref=22, minBit 8, minWin=23, winSum=387
8501 13:53:50.687928 TX Vref=24, minBit 11, minWin=23, winSum=399
8502 13:53:50.691385 TX Vref=26, minBit 5, minWin=24, winSum=403
8503 13:53:50.694567 TX Vref=28, minBit 0, minWin=25, winSum=414
8504 13:53:50.697852 TX Vref=30, minBit 1, minWin=24, winSum=409
8505 13:53:50.701166 TX Vref=32, minBit 0, minWin=24, winSum=401
8506 13:53:50.704604 TX Vref=34, minBit 1, minWin=23, winSum=391
8507 13:53:50.711144 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8508 13:53:50.711229
8509 13:53:50.714760 Final TX Range 0 Vref 28
8510 13:53:50.714852
8511 13:53:50.714927 ==
8512 13:53:50.717811 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 13:53:50.721054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 13:53:50.721162 ==
8515 13:53:50.721238
8516 13:53:50.721331
8517 13:53:50.724386 TX Vref Scan disable
8518 13:53:50.731033 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8519 13:53:50.731111 == TX Byte 0 ==
8520 13:53:50.734474 u2DelayCellOfst[0]=18 cells (5 PI)
8521 13:53:50.737899 u2DelayCellOfst[1]=15 cells (4 PI)
8522 13:53:50.740799 u2DelayCellOfst[2]=0 cells (0 PI)
8523 13:53:50.744109 u2DelayCellOfst[3]=7 cells (2 PI)
8524 13:53:50.747548 u2DelayCellOfst[4]=11 cells (3 PI)
8525 13:53:50.751037 u2DelayCellOfst[5]=22 cells (6 PI)
8526 13:53:50.754075 u2DelayCellOfst[6]=26 cells (7 PI)
8527 13:53:50.757576 u2DelayCellOfst[7]=7 cells (2 PI)
8528 13:53:50.761094 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8529 13:53:50.764089 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8530 13:53:50.767480 == TX Byte 1 ==
8531 13:53:50.770883 u2DelayCellOfst[8]=0 cells (0 PI)
8532 13:53:50.770956 u2DelayCellOfst[9]=11 cells (3 PI)
8533 13:53:50.774150 u2DelayCellOfst[10]=15 cells (4 PI)
8534 13:53:50.777454 u2DelayCellOfst[11]=11 cells (3 PI)
8535 13:53:50.780860 u2DelayCellOfst[12]=18 cells (5 PI)
8536 13:53:50.783940 u2DelayCellOfst[13]=22 cells (6 PI)
8537 13:53:50.787522 u2DelayCellOfst[14]=22 cells (6 PI)
8538 13:53:50.790654 u2DelayCellOfst[15]=22 cells (6 PI)
8539 13:53:50.797312 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8540 13:53:50.800743 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8541 13:53:50.800823 DramC Write-DBI on
8542 13:53:50.800912 ==
8543 13:53:50.803852 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 13:53:50.810716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 13:53:50.810793 ==
8546 13:53:50.810862
8547 13:53:50.810921
8548 13:53:50.810978 TX Vref Scan disable
8549 13:53:50.814609 == TX Byte 0 ==
8550 13:53:50.818065 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8551 13:53:50.821303 == TX Byte 1 ==
8552 13:53:50.824777 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8553 13:53:50.828179 DramC Write-DBI off
8554 13:53:50.828259
8555 13:53:50.828323 [DATLAT]
8556 13:53:50.828382 Freq=1600, CH1 RK0
8557 13:53:50.828440
8558 13:53:50.831082 DATLAT Default: 0xf
8559 13:53:50.831164 0, 0xFFFF, sum = 0
8560 13:53:50.834586 1, 0xFFFF, sum = 0
8561 13:53:50.834689 2, 0xFFFF, sum = 0
8562 13:53:50.837717 3, 0xFFFF, sum = 0
8563 13:53:50.841279 4, 0xFFFF, sum = 0
8564 13:53:50.841352 5, 0xFFFF, sum = 0
8565 13:53:50.844509 6, 0xFFFF, sum = 0
8566 13:53:50.844582 7, 0xFFFF, sum = 0
8567 13:53:50.847749 8, 0xFFFF, sum = 0
8568 13:53:50.847822 9, 0xFFFF, sum = 0
8569 13:53:50.851159 10, 0xFFFF, sum = 0
8570 13:53:50.851244 11, 0xFFFF, sum = 0
8571 13:53:50.854426 12, 0xFFFF, sum = 0
8572 13:53:50.854502 13, 0x8FFF, sum = 0
8573 13:53:50.857988 14, 0x0, sum = 1
8574 13:53:50.858066 15, 0x0, sum = 2
8575 13:53:50.861077 16, 0x0, sum = 3
8576 13:53:50.861191 17, 0x0, sum = 4
8577 13:53:50.864551 best_step = 15
8578 13:53:50.864628
8579 13:53:50.864691 ==
8580 13:53:50.867849 Dram Type= 6, Freq= 0, CH_1, rank 0
8581 13:53:50.871065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8582 13:53:50.871149 ==
8583 13:53:50.871212 RX Vref Scan: 1
8584 13:53:50.874281
8585 13:53:50.874361 Set Vref Range= 24 -> 127
8586 13:53:50.874423
8587 13:53:50.877664 RX Vref 24 -> 127, step: 1
8588 13:53:50.877746
8589 13:53:50.881107 RX Delay 11 -> 252, step: 4
8590 13:53:50.881181
8591 13:53:50.884211 Set Vref, RX VrefLevel [Byte0]: 24
8592 13:53:50.887728 [Byte1]: 24
8593 13:53:50.887805
8594 13:53:50.890763 Set Vref, RX VrefLevel [Byte0]: 25
8595 13:53:50.894288 [Byte1]: 25
8596 13:53:50.894365
8597 13:53:50.897417 Set Vref, RX VrefLevel [Byte0]: 26
8598 13:53:50.900832 [Byte1]: 26
8599 13:53:50.904801
8600 13:53:50.904877 Set Vref, RX VrefLevel [Byte0]: 27
8601 13:53:50.908196 [Byte1]: 27
8602 13:53:50.912514
8603 13:53:50.912612 Set Vref, RX VrefLevel [Byte0]: 28
8604 13:53:50.916053 [Byte1]: 28
8605 13:53:50.920200
8606 13:53:50.920297 Set Vref, RX VrefLevel [Byte0]: 29
8607 13:53:50.923390 [Byte1]: 29
8608 13:53:50.927827
8609 13:53:50.927918 Set Vref, RX VrefLevel [Byte0]: 30
8610 13:53:50.930987 [Byte1]: 30
8611 13:53:50.935541
8612 13:53:50.935639 Set Vref, RX VrefLevel [Byte0]: 31
8613 13:53:50.938828 [Byte1]: 31
8614 13:53:50.943093
8615 13:53:50.943186 Set Vref, RX VrefLevel [Byte0]: 32
8616 13:53:50.946337 [Byte1]: 32
8617 13:53:50.950776
8618 13:53:50.950882 Set Vref, RX VrefLevel [Byte0]: 33
8619 13:53:50.953822 [Byte1]: 33
8620 13:53:50.958041
8621 13:53:50.958141 Set Vref, RX VrefLevel [Byte0]: 34
8622 13:53:50.961306 [Byte1]: 34
8623 13:53:50.965827
8624 13:53:50.965944 Set Vref, RX VrefLevel [Byte0]: 35
8625 13:53:50.969159 [Byte1]: 35
8626 13:53:50.973299
8627 13:53:50.973387 Set Vref, RX VrefLevel [Byte0]: 36
8628 13:53:50.976805 [Byte1]: 36
8629 13:53:50.981037
8630 13:53:50.981124 Set Vref, RX VrefLevel [Byte0]: 37
8631 13:53:50.984172 [Byte1]: 37
8632 13:53:50.988767
8633 13:53:50.988854 Set Vref, RX VrefLevel [Byte0]: 38
8634 13:53:50.992043 [Byte1]: 38
8635 13:53:50.996175
8636 13:53:50.996270 Set Vref, RX VrefLevel [Byte0]: 39
8637 13:53:50.999415 [Byte1]: 39
8638 13:53:51.003981
8639 13:53:51.004071 Set Vref, RX VrefLevel [Byte0]: 40
8640 13:53:51.007163 [Byte1]: 40
8641 13:53:51.011395
8642 13:53:51.011494 Set Vref, RX VrefLevel [Byte0]: 41
8643 13:53:51.014793 [Byte1]: 41
8644 13:53:51.019267
8645 13:53:51.019362 Set Vref, RX VrefLevel [Byte0]: 42
8646 13:53:51.022629 [Byte1]: 42
8647 13:53:51.026774
8648 13:53:51.026871 Set Vref, RX VrefLevel [Byte0]: 43
8649 13:53:51.030210 [Byte1]: 43
8650 13:53:51.034495
8651 13:53:51.034609 Set Vref, RX VrefLevel [Byte0]: 44
8652 13:53:51.037462 [Byte1]: 44
8653 13:53:51.042062
8654 13:53:51.042173 Set Vref, RX VrefLevel [Byte0]: 45
8655 13:53:51.045146 [Byte1]: 45
8656 13:53:51.049737
8657 13:53:51.049856 Set Vref, RX VrefLevel [Byte0]: 46
8658 13:53:51.053009 [Byte1]: 46
8659 13:53:51.057382
8660 13:53:51.057542 Set Vref, RX VrefLevel [Byte0]: 47
8661 13:53:51.060600 [Byte1]: 47
8662 13:53:51.065023
8663 13:53:51.065120 Set Vref, RX VrefLevel [Byte0]: 48
8664 13:53:51.068369 [Byte1]: 48
8665 13:53:51.072434
8666 13:53:51.072536 Set Vref, RX VrefLevel [Byte0]: 49
8667 13:53:51.075831 [Byte1]: 49
8668 13:53:51.079954
8669 13:53:51.080061 Set Vref, RX VrefLevel [Byte0]: 50
8670 13:53:51.083483 [Byte1]: 50
8671 13:53:51.087700
8672 13:53:51.087806 Set Vref, RX VrefLevel [Byte0]: 51
8673 13:53:51.090786 [Byte1]: 51
8674 13:53:51.095434
8675 13:53:51.095537 Set Vref, RX VrefLevel [Byte0]: 52
8676 13:53:51.098479 [Byte1]: 52
8677 13:53:51.102829
8678 13:53:51.102958 Set Vref, RX VrefLevel [Byte0]: 53
8679 13:53:51.106125 [Byte1]: 53
8680 13:53:51.110596
8681 13:53:51.110671 Set Vref, RX VrefLevel [Byte0]: 54
8682 13:53:51.113962 [Byte1]: 54
8683 13:53:51.118139
8684 13:53:51.118223 Set Vref, RX VrefLevel [Byte0]: 55
8685 13:53:51.121525 [Byte1]: 55
8686 13:53:51.125803
8687 13:53:51.125892 Set Vref, RX VrefLevel [Byte0]: 56
8688 13:53:51.129040 [Byte1]: 56
8689 13:53:51.133300
8690 13:53:51.133403 Set Vref, RX VrefLevel [Byte0]: 57
8691 13:53:51.136450 [Byte1]: 57
8692 13:53:51.140978
8693 13:53:51.141051 Set Vref, RX VrefLevel [Byte0]: 58
8694 13:53:51.144050 [Byte1]: 58
8695 13:53:51.150088
8696 13:53:51.150172 Set Vref, RX VrefLevel [Byte0]: 59
8697 13:53:51.151829 [Byte1]: 59
8698 13:53:51.156274
8699 13:53:51.156373 Set Vref, RX VrefLevel [Byte0]: 60
8700 13:53:51.159508 [Byte1]: 60
8701 13:53:51.163631
8702 13:53:51.163740 Set Vref, RX VrefLevel [Byte0]: 61
8703 13:53:51.167230 [Byte1]: 61
8704 13:53:51.171559
8705 13:53:51.171657 Set Vref, RX VrefLevel [Byte0]: 62
8706 13:53:51.174715 [Byte1]: 62
8707 13:53:51.179049
8708 13:53:51.179148 Set Vref, RX VrefLevel [Byte0]: 63
8709 13:53:51.182303 [Byte1]: 63
8710 13:53:51.186555
8711 13:53:51.186662 Set Vref, RX VrefLevel [Byte0]: 64
8712 13:53:51.189934 [Byte1]: 64
8713 13:53:51.194248
8714 13:53:51.194326 Set Vref, RX VrefLevel [Byte0]: 65
8715 13:53:51.197326 [Byte1]: 65
8716 13:53:51.201687
8717 13:53:51.201768 Set Vref, RX VrefLevel [Byte0]: 66
8718 13:53:51.205247 [Byte1]: 66
8719 13:53:51.209355
8720 13:53:51.209430 Set Vref, RX VrefLevel [Byte0]: 67
8721 13:53:51.212701 [Byte1]: 67
8722 13:53:51.216922
8723 13:53:51.216998 Set Vref, RX VrefLevel [Byte0]: 68
8724 13:53:51.220365 [Byte1]: 68
8725 13:53:51.224575
8726 13:53:51.224652 Set Vref, RX VrefLevel [Byte0]: 69
8727 13:53:51.228037 [Byte1]: 69
8728 13:53:51.232405
8729 13:53:51.232510 Set Vref, RX VrefLevel [Byte0]: 70
8730 13:53:51.235558 [Byte1]: 70
8731 13:53:51.239903
8732 13:53:51.240006 Final RX Vref Byte 0 = 58 to rank0
8733 13:53:51.242977 Final RX Vref Byte 1 = 54 to rank0
8734 13:53:51.246378 Final RX Vref Byte 0 = 58 to rank1
8735 13:53:51.249809 Final RX Vref Byte 1 = 54 to rank1==
8736 13:53:51.253092 Dram Type= 6, Freq= 0, CH_1, rank 0
8737 13:53:51.259661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 13:53:51.259744 ==
8739 13:53:51.259811 DQS Delay:
8740 13:53:51.263120 DQS0 = 0, DQS1 = 0
8741 13:53:51.263196 DQM Delay:
8742 13:53:51.263260 DQM0 = 130, DQM1 = 123
8743 13:53:51.266366 DQ Delay:
8744 13:53:51.269881 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8745 13:53:51.273049 DQ4 =126, DQ5 =142, DQ6 =140, DQ7 =128
8746 13:53:51.276363 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8747 13:53:51.279403 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8748 13:53:51.279486
8749 13:53:51.279550
8750 13:53:51.279617
8751 13:53:51.282790 [DramC_TX_OE_Calibration] TA2
8752 13:53:51.286226 Original DQ_B0 (3 6) =30, OEN = 27
8753 13:53:51.289551 Original DQ_B1 (3 6) =30, OEN = 27
8754 13:53:51.292733 24, 0x0, End_B0=24 End_B1=24
8755 13:53:51.292817 25, 0x0, End_B0=25 End_B1=25
8756 13:53:51.296202 26, 0x0, End_B0=26 End_B1=26
8757 13:53:51.299520 27, 0x0, End_B0=27 End_B1=27
8758 13:53:51.302628 28, 0x0, End_B0=28 End_B1=28
8759 13:53:51.306125 29, 0x0, End_B0=29 End_B1=29
8760 13:53:51.306207 30, 0x0, End_B0=30 End_B1=30
8761 13:53:51.309300 31, 0x4141, End_B0=30 End_B1=30
8762 13:53:51.312775 Byte0 end_step=30 best_step=27
8763 13:53:51.315827 Byte1 end_step=30 best_step=27
8764 13:53:51.319473 Byte0 TX OE(2T, 0.5T) = (3, 3)
8765 13:53:51.322559 Byte1 TX OE(2T, 0.5T) = (3, 3)
8766 13:53:51.322631
8767 13:53:51.322698
8768 13:53:51.329161 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8769 13:53:51.332323 CH1 RK0: MR19=303, MR18=90E
8770 13:53:51.339078 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8771 13:53:51.339157
8772 13:53:51.342397 ----->DramcWriteLeveling(PI) begin...
8773 13:53:51.342470 ==
8774 13:53:51.345746 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 13:53:51.348894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 13:53:51.349034 ==
8777 13:53:51.352620 Write leveling (Byte 0): 25 => 25
8778 13:53:51.355656 Write leveling (Byte 1): 26 => 26
8779 13:53:51.359321 DramcWriteLeveling(PI) end<-----
8780 13:53:51.359400
8781 13:53:51.359464 ==
8782 13:53:51.362287 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 13:53:51.365863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 13:53:51.365945 ==
8785 13:53:51.369037 [Gating] SW mode calibration
8786 13:53:51.375664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8787 13:53:51.382177 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8788 13:53:51.385435 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 13:53:51.392175 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 13:53:51.395700 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8791 13:53:51.398913 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
8792 13:53:51.402146 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 13:53:51.408828 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 13:53:51.412409 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 13:53:51.415482 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 13:53:51.422406 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 13:53:51.425334 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 13:53:51.428836 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8799 13:53:51.435388 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8800 13:53:51.438879 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 13:53:51.441975 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 13:53:51.448756 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 13:53:51.452157 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 13:53:51.455340 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 13:53:51.461916 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8806 13:53:51.465209 1 6 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8807 13:53:51.468663 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 13:53:51.475107 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 13:53:51.478641 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 13:53:51.481776 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 13:53:51.488549 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 13:53:51.491833 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 13:53:51.495075 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 13:53:51.501839 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8815 13:53:51.504918 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 13:53:51.508133 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 13:53:51.514981 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 13:53:51.518116 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 13:53:51.521556 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 13:53:51.528314 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 13:53:51.531380 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 13:53:51.534628 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 13:53:51.541616 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 13:53:51.544807 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 13:53:51.547925 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 13:53:51.551449 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 13:53:51.557854 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 13:53:51.561340 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 13:53:51.564783 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8830 13:53:51.571355 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8831 13:53:51.574779 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8832 13:53:51.577930 Total UI for P1: 0, mck2ui 16
8833 13:53:51.581508 best dqsien dly found for B0: ( 1, 9, 6)
8834 13:53:51.584671 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 13:53:51.587786 Total UI for P1: 0, mck2ui 16
8836 13:53:51.591503 best dqsien dly found for B1: ( 1, 9, 10)
8837 13:53:51.594546 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8838 13:53:51.597933 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8839 13:53:51.598014
8840 13:53:51.604440 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8841 13:53:51.607695 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8842 13:53:51.611211 [Gating] SW calibration Done
8843 13:53:51.611288 ==
8844 13:53:51.614599 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 13:53:51.617826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 13:53:51.617917 ==
8847 13:53:51.617979 RX Vref Scan: 0
8848 13:53:51.620997
8849 13:53:51.621071 RX Vref 0 -> 0, step: 1
8850 13:53:51.621131
8851 13:53:51.624575 RX Delay 0 -> 252, step: 8
8852 13:53:51.627726 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8853 13:53:51.631127 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8854 13:53:51.637627 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8855 13:53:51.640548 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8856 13:53:51.644072 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8857 13:53:51.647448 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8858 13:53:51.650751 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8859 13:53:51.657392 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8860 13:53:51.660431 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8861 13:53:51.663933 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8862 13:53:51.667263 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8863 13:53:51.670692 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8864 13:53:51.676971 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8865 13:53:51.680435 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8866 13:53:51.683917 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8867 13:53:51.686933 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8868 13:53:51.687003 ==
8869 13:53:51.690307 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 13:53:51.697155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 13:53:51.697259 ==
8872 13:53:51.697322 DQS Delay:
8873 13:53:51.700136 DQS0 = 0, DQS1 = 0
8874 13:53:51.700209 DQM Delay:
8875 13:53:51.703689 DQM0 = 132, DQM1 = 128
8876 13:53:51.703788 DQ Delay:
8877 13:53:51.707006 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8878 13:53:51.710175 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8879 13:53:51.713578 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8880 13:53:51.716878 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8881 13:53:51.716953
8882 13:53:51.717015
8883 13:53:51.717072 ==
8884 13:53:51.720299 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 13:53:51.726791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 13:53:51.726868 ==
8887 13:53:51.726939
8888 13:53:51.726998
8889 13:53:51.727055 TX Vref Scan disable
8890 13:53:51.730083 == TX Byte 0 ==
8891 13:53:51.733465 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8892 13:53:51.739946 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8893 13:53:51.740027 == TX Byte 1 ==
8894 13:53:51.743455 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8895 13:53:51.749884 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8896 13:53:51.749962 ==
8897 13:53:51.753595 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 13:53:51.756567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 13:53:51.756640 ==
8900 13:53:51.769010
8901 13:53:51.772259 TX Vref early break, caculate TX vref
8902 13:53:51.775399 TX Vref=16, minBit 0, minWin=22, winSum=382
8903 13:53:51.778994 TX Vref=18, minBit 0, minWin=23, winSum=391
8904 13:53:51.782080 TX Vref=20, minBit 0, minWin=23, winSum=402
8905 13:53:51.785749 TX Vref=22, minBit 0, minWin=24, winSum=410
8906 13:53:51.788872 TX Vref=24, minBit 0, minWin=24, winSum=415
8907 13:53:51.795590 TX Vref=26, minBit 0, minWin=25, winSum=427
8908 13:53:51.798732 TX Vref=28, minBit 1, minWin=25, winSum=431
8909 13:53:51.802198 TX Vref=30, minBit 5, minWin=25, winSum=427
8910 13:53:51.805614 TX Vref=32, minBit 1, minWin=23, winSum=413
8911 13:53:51.808727 TX Vref=34, minBit 5, minWin=23, winSum=407
8912 13:53:51.815541 [TxChooseVref] Worse bit 1, Min win 25, Win sum 431, Final Vref 28
8913 13:53:51.815637
8914 13:53:51.818691 Final TX Range 0 Vref 28
8915 13:53:51.818821
8916 13:53:51.818939 ==
8917 13:53:51.822191 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 13:53:51.825450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 13:53:51.825580 ==
8920 13:53:51.825659
8921 13:53:51.825747
8922 13:53:51.828595 TX Vref Scan disable
8923 13:53:51.835375 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8924 13:53:51.835508 == TX Byte 0 ==
8925 13:53:51.838654 u2DelayCellOfst[0]=18 cells (5 PI)
8926 13:53:51.841633 u2DelayCellOfst[1]=15 cells (4 PI)
8927 13:53:51.845066 u2DelayCellOfst[2]=0 cells (0 PI)
8928 13:53:51.848459 u2DelayCellOfst[3]=7 cells (2 PI)
8929 13:53:51.851803 u2DelayCellOfst[4]=11 cells (3 PI)
8930 13:53:51.854937 u2DelayCellOfst[5]=22 cells (6 PI)
8931 13:53:51.858373 u2DelayCellOfst[6]=22 cells (6 PI)
8932 13:53:51.861883 u2DelayCellOfst[7]=7 cells (2 PI)
8933 13:53:51.864932 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 13:53:51.868406 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8935 13:53:51.871517 == TX Byte 1 ==
8936 13:53:51.871603 u2DelayCellOfst[8]=0 cells (0 PI)
8937 13:53:51.874949 u2DelayCellOfst[9]=7 cells (2 PI)
8938 13:53:51.878036 u2DelayCellOfst[10]=11 cells (3 PI)
8939 13:53:51.881656 u2DelayCellOfst[11]=7 cells (2 PI)
8940 13:53:51.885140 u2DelayCellOfst[12]=15 cells (4 PI)
8941 13:53:51.888350 u2DelayCellOfst[13]=18 cells (5 PI)
8942 13:53:51.891483 u2DelayCellOfst[14]=22 cells (6 PI)
8943 13:53:51.894624 u2DelayCellOfst[15]=18 cells (5 PI)
8944 13:53:51.898177 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8945 13:53:51.904804 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8946 13:53:51.904883 DramC Write-DBI on
8947 13:53:51.904944 ==
8948 13:53:51.907895 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 13:53:51.914482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 13:53:51.914560 ==
8951 13:53:51.914627
8952 13:53:51.914693
8953 13:53:51.914752 TX Vref Scan disable
8954 13:53:51.918108 == TX Byte 0 ==
8955 13:53:51.921394 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8956 13:53:51.924745 == TX Byte 1 ==
8957 13:53:51.928272 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8958 13:53:51.931416 DramC Write-DBI off
8959 13:53:51.931500
8960 13:53:51.931595 [DATLAT]
8961 13:53:51.931688 Freq=1600, CH1 RK1
8962 13:53:51.931776
8963 13:53:51.934923 DATLAT Default: 0xf
8964 13:53:51.938069 0, 0xFFFF, sum = 0
8965 13:53:51.938145 1, 0xFFFF, sum = 0
8966 13:53:51.941270 2, 0xFFFF, sum = 0
8967 13:53:51.941375 3, 0xFFFF, sum = 0
8968 13:53:51.944628 4, 0xFFFF, sum = 0
8969 13:53:51.944702 5, 0xFFFF, sum = 0
8970 13:53:51.948098 6, 0xFFFF, sum = 0
8971 13:53:51.948198 7, 0xFFFF, sum = 0
8972 13:53:51.951117 8, 0xFFFF, sum = 0
8973 13:53:51.951202 9, 0xFFFF, sum = 0
8974 13:53:51.954408 10, 0xFFFF, sum = 0
8975 13:53:51.954496 11, 0xFFFF, sum = 0
8976 13:53:51.957818 12, 0xFFFF, sum = 0
8977 13:53:51.957931 13, 0x8FFF, sum = 0
8978 13:53:51.961305 14, 0x0, sum = 1
8979 13:53:51.961383 15, 0x0, sum = 2
8980 13:53:51.964374 16, 0x0, sum = 3
8981 13:53:51.964458 17, 0x0, sum = 4
8982 13:53:51.967827 best_step = 15
8983 13:53:51.967902
8984 13:53:51.967964 ==
8985 13:53:51.970939 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 13:53:51.974194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 13:53:51.974270 ==
8988 13:53:51.977679 RX Vref Scan: 0
8989 13:53:51.977762
8990 13:53:51.977826 RX Vref 0 -> 0, step: 1
8991 13:53:51.977887
8992 13:53:51.980991 RX Delay 11 -> 252, step: 4
8993 13:53:51.987690 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8994 13:53:51.990822 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8995 13:53:51.994293 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8996 13:53:51.997466 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8997 13:53:52.000923 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8998 13:53:52.007684 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8999 13:53:52.010676 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9000 13:53:52.014149 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9001 13:53:52.017301 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9002 13:53:52.020745 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9003 13:53:52.027148 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9004 13:53:52.030555 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9005 13:53:52.034031 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9006 13:53:52.037294 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9007 13:53:52.040441 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9008 13:53:52.047478 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9009 13:53:52.047555 ==
9010 13:53:52.050525 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 13:53:52.053946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 13:53:52.054026 ==
9013 13:53:52.054087 DQS Delay:
9014 13:53:52.057093 DQS0 = 0, DQS1 = 0
9015 13:53:52.057171 DQM Delay:
9016 13:53:52.060486 DQM0 = 130, DQM1 = 125
9017 13:53:52.060569 DQ Delay:
9018 13:53:52.064046 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9019 13:53:52.067012 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =128
9020 13:53:52.070450 DQ8 =108, DQ9 =114, DQ10 =128, DQ11 =120
9021 13:53:52.073898 DQ12 =132, DQ13 =136, DQ14 =130, DQ15 =136
9022 13:53:52.073984
9023 13:53:52.077018
9024 13:53:52.077091
9025 13:53:52.077153 [DramC_TX_OE_Calibration] TA2
9026 13:53:52.080557 Original DQ_B0 (3 6) =30, OEN = 27
9027 13:53:52.083700 Original DQ_B1 (3 6) =30, OEN = 27
9028 13:53:52.087000 24, 0x0, End_B0=24 End_B1=24
9029 13:53:52.090353 25, 0x0, End_B0=25 End_B1=25
9030 13:53:52.093573 26, 0x0, End_B0=26 End_B1=26
9031 13:53:52.093665 27, 0x0, End_B0=27 End_B1=27
9032 13:53:52.096992 28, 0x0, End_B0=28 End_B1=28
9033 13:53:52.100348 29, 0x0, End_B0=29 End_B1=29
9034 13:53:52.103396 30, 0x0, End_B0=30 End_B1=30
9035 13:53:52.106898 31, 0x4141, End_B0=30 End_B1=30
9036 13:53:52.106974 Byte0 end_step=30 best_step=27
9037 13:53:52.110146 Byte1 end_step=30 best_step=27
9038 13:53:52.113585 Byte0 TX OE(2T, 0.5T) = (3, 3)
9039 13:53:52.116684 Byte1 TX OE(2T, 0.5T) = (3, 3)
9040 13:53:52.116759
9041 13:53:52.116840
9042 13:53:52.126546 [DQSOSCAuto] RK1, (LSB)MR18= 0x141f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
9043 13:53:52.126628 CH1 RK1: MR19=303, MR18=141F
9044 13:53:52.133596 CH1_RK1: MR19=0x303, MR18=0x141F, DQSOSC=394, MR23=63, INC=23, DEC=15
9045 13:53:52.136466 [RxdqsGatingPostProcess] freq 1600
9046 13:53:52.143431 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9047 13:53:52.146575 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 13:53:52.150074 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 13:53:52.153138 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 13:53:52.153214 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 13:53:52.156502 best DQS0 dly(2T, 0.5T) = (1, 1)
9052 13:53:52.159989 best DQS1 dly(2T, 0.5T) = (1, 1)
9053 13:53:52.163098 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9054 13:53:52.166497 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9055 13:53:52.169886 Pre-setting of DQS Precalculation
9056 13:53:52.176478 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9057 13:53:52.183009 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9058 13:53:52.189817 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9059 13:53:52.189898
9060 13:53:52.189981
9061 13:53:52.192936 [Calibration Summary] 3200 Mbps
9062 13:53:52.193014 CH 0, Rank 0
9063 13:53:52.196425 SW Impedance : PASS
9064 13:53:52.199615 DUTY Scan : NO K
9065 13:53:52.199697 ZQ Calibration : PASS
9066 13:53:52.202849 Jitter Meter : NO K
9067 13:53:52.206327 CBT Training : PASS
9068 13:53:52.206403 Write leveling : PASS
9069 13:53:52.209453 RX DQS gating : PASS
9070 13:53:52.209560 RX DQ/DQS(RDDQC) : PASS
9071 13:53:52.213138 TX DQ/DQS : PASS
9072 13:53:52.216262 RX DATLAT : PASS
9073 13:53:52.216342 RX DQ/DQS(Engine): PASS
9074 13:53:52.219736 TX OE : PASS
9075 13:53:52.219821 All Pass.
9076 13:53:52.219903
9077 13:53:52.223159 CH 0, Rank 1
9078 13:53:52.223242 SW Impedance : PASS
9079 13:53:52.226219 DUTY Scan : NO K
9080 13:53:52.229739 ZQ Calibration : PASS
9081 13:53:52.229827 Jitter Meter : NO K
9082 13:53:52.232897 CBT Training : PASS
9083 13:53:52.236301 Write leveling : PASS
9084 13:53:52.236381 RX DQS gating : PASS
9085 13:53:52.239404 RX DQ/DQS(RDDQC) : PASS
9086 13:53:52.242686 TX DQ/DQS : PASS
9087 13:53:52.242767 RX DATLAT : PASS
9088 13:53:52.246141 RX DQ/DQS(Engine): PASS
9089 13:53:52.249618 TX OE : PASS
9090 13:53:52.249698 All Pass.
9091 13:53:52.249788
9092 13:53:52.249865 CH 1, Rank 0
9093 13:53:52.252792 SW Impedance : PASS
9094 13:53:52.256349 DUTY Scan : NO K
9095 13:53:52.256425 ZQ Calibration : PASS
9096 13:53:52.259419 Jitter Meter : NO K
9097 13:53:52.259503 CBT Training : PASS
9098 13:53:52.262904 Write leveling : PASS
9099 13:53:52.265898 RX DQS gating : PASS
9100 13:53:52.265983 RX DQ/DQS(RDDQC) : PASS
9101 13:53:52.269427 TX DQ/DQS : PASS
9102 13:53:52.272746 RX DATLAT : PASS
9103 13:53:52.272822 RX DQ/DQS(Engine): PASS
9104 13:53:52.276087 TX OE : PASS
9105 13:53:52.276168 All Pass.
9106 13:53:52.276251
9107 13:53:52.279255 CH 1, Rank 1
9108 13:53:52.279332 SW Impedance : PASS
9109 13:53:52.282680 DUTY Scan : NO K
9110 13:53:52.286010 ZQ Calibration : PASS
9111 13:53:52.286089 Jitter Meter : NO K
9112 13:53:52.289364 CBT Training : PASS
9113 13:53:52.292468 Write leveling : PASS
9114 13:53:52.292548 RX DQS gating : PASS
9115 13:53:52.295848 RX DQ/DQS(RDDQC) : PASS
9116 13:53:52.299253 TX DQ/DQS : PASS
9117 13:53:52.299331 RX DATLAT : PASS
9118 13:53:52.302544 RX DQ/DQS(Engine): PASS
9119 13:53:52.305915 TX OE : PASS
9120 13:53:52.306002 All Pass.
9121 13:53:52.306085
9122 13:53:52.306164 DramC Write-DBI on
9123 13:53:52.309164 PER_BANK_REFRESH: Hybrid Mode
9124 13:53:52.312232 TX_TRACKING: ON
9125 13:53:52.318899 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9126 13:53:52.328913 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9127 13:53:52.335452 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9128 13:53:52.338575 [FAST_K] Save calibration result to emmc
9129 13:53:52.341987 sync common calibartion params.
9130 13:53:52.345483 sync cbt_mode0:1, 1:1
9131 13:53:52.345601 dram_init: ddr_geometry: 2
9132 13:53:52.348778 dram_init: ddr_geometry: 2
9133 13:53:52.351947 dram_init: ddr_geometry: 2
9134 13:53:52.352021 0:dram_rank_size:100000000
9135 13:53:52.355401 1:dram_rank_size:100000000
9136 13:53:52.362127 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9137 13:53:52.365595 DFS_SHUFFLE_HW_MODE: ON
9138 13:53:52.368699 dramc_set_vcore_voltage set vcore to 725000
9139 13:53:52.368775 Read voltage for 1600, 0
9140 13:53:52.372167 Vio18 = 0
9141 13:53:52.372247 Vcore = 725000
9142 13:53:52.372310 Vdram = 0
9143 13:53:52.375363 Vddq = 0
9144 13:53:52.375443 Vmddr = 0
9145 13:53:52.378804 switch to 3200 Mbps bootup
9146 13:53:52.378878 [DramcRunTimeConfig]
9147 13:53:52.378940 PHYPLL
9148 13:53:52.381975 DPM_CONTROL_AFTERK: ON
9149 13:53:52.385442 PER_BANK_REFRESH: ON
9150 13:53:52.385557 REFRESH_OVERHEAD_REDUCTION: ON
9151 13:53:52.388776 CMD_PICG_NEW_MODE: OFF
9152 13:53:52.391744 XRTWTW_NEW_MODE: ON
9153 13:53:52.391821 XRTRTR_NEW_MODE: ON
9154 13:53:52.395109 TX_TRACKING: ON
9155 13:53:52.395179 RDSEL_TRACKING: OFF
9156 13:53:52.398675 DQS Precalculation for DVFS: ON
9157 13:53:52.398771 RX_TRACKING: OFF
9158 13:53:52.401842 HW_GATING DBG: ON
9159 13:53:52.401938 ZQCS_ENABLE_LP4: ON
9160 13:53:52.405159 RX_PICG_NEW_MODE: ON
9161 13:53:52.408675 TX_PICG_NEW_MODE: ON
9162 13:53:52.408747 ENABLE_RX_DCM_DPHY: ON
9163 13:53:52.412048 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9164 13:53:52.415217 DUMMY_READ_FOR_TRACKING: OFF
9165 13:53:52.418356 !!! SPM_CONTROL_AFTERK: OFF
9166 13:53:52.421896 !!! SPM could not control APHY
9167 13:53:52.421971 IMPEDANCE_TRACKING: ON
9168 13:53:52.425065 TEMP_SENSOR: ON
9169 13:53:52.425138 HW_SAVE_FOR_SR: OFF
9170 13:53:52.428486 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9171 13:53:52.431788 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9172 13:53:52.435188 Read ODT Tracking: ON
9173 13:53:52.435271 Refresh Rate DeBounce: ON
9174 13:53:52.438527 DFS_NO_QUEUE_FLUSH: ON
9175 13:53:52.441843 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9176 13:53:52.445080 ENABLE_DFS_RUNTIME_MRW: OFF
9177 13:53:52.445157 DDR_RESERVE_NEW_MODE: ON
9178 13:53:52.448275 MR_CBT_SWITCH_FREQ: ON
9179 13:53:52.451560 =========================
9180 13:53:52.469619 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9181 13:53:52.473051 dram_init: ddr_geometry: 2
9182 13:53:52.491294 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9183 13:53:52.494846 dram_init: dram init end (result: 0)
9184 13:53:52.501313 DRAM-K: Full calibration passed in 24582 msecs
9185 13:53:52.504789 MRC: failed to locate region type 0.
9186 13:53:52.504892 DRAM rank0 size:0x100000000,
9187 13:53:52.508060 DRAM rank1 size=0x100000000
9188 13:53:52.517747 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9189 13:53:52.524378 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9190 13:53:52.531313 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9191 13:53:52.537586 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9192 13:53:52.540745 DRAM rank0 size:0x100000000,
9193 13:53:52.544379 DRAM rank1 size=0x100000000
9194 13:53:52.544461 CBMEM:
9195 13:53:52.547706 IMD: root @ 0xfffff000 254 entries.
9196 13:53:52.550811 IMD: root @ 0xffffec00 62 entries.
9197 13:53:52.554067 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9198 13:53:52.560703 WARNING: RO_VPD is uninitialized or empty.
9199 13:53:52.563928 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9200 13:53:52.571301 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9201 13:53:52.584275 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9202 13:53:52.595684 BS: romstage times (exec / console): total (unknown) / 24049 ms
9203 13:53:52.595769
9204 13:53:52.595834
9205 13:53:52.605525 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9206 13:53:52.609048 ARM64: Exception handlers installed.
9207 13:53:52.612218 ARM64: Testing exception
9208 13:53:52.615669 ARM64: Done test exception
9209 13:53:52.615743 Enumerating buses...
9210 13:53:52.618816 Show all devs... Before device enumeration.
9211 13:53:52.622100 Root Device: enabled 1
9212 13:53:52.625532 CPU_CLUSTER: 0: enabled 1
9213 13:53:52.625606 CPU: 00: enabled 1
9214 13:53:52.628960 Compare with tree...
9215 13:53:52.629028 Root Device: enabled 1
9216 13:53:52.632078 CPU_CLUSTER: 0: enabled 1
9217 13:53:52.635597 CPU: 00: enabled 1
9218 13:53:52.635674 Root Device scanning...
9219 13:53:52.638712 scan_static_bus for Root Device
9220 13:53:52.641812 CPU_CLUSTER: 0 enabled
9221 13:53:52.645536 scan_static_bus for Root Device done
9222 13:53:52.648702 scan_bus: bus Root Device finished in 8 msecs
9223 13:53:52.648780 done
9224 13:53:52.655369 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9225 13:53:52.658775 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9226 13:53:52.665277 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9227 13:53:52.668484 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9228 13:53:52.671863 Allocating resources...
9229 13:53:52.675344 Reading resources...
9230 13:53:52.678692 Root Device read_resources bus 0 link: 0
9231 13:53:52.678784 DRAM rank0 size:0x100000000,
9232 13:53:52.681853 DRAM rank1 size=0x100000000
9233 13:53:52.685275 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9234 13:53:52.688475 CPU: 00 missing read_resources
9235 13:53:52.691734 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9236 13:53:52.698312 Root Device read_resources bus 0 link: 0 done
9237 13:53:52.698400 Done reading resources.
9238 13:53:52.705108 Show resources in subtree (Root Device)...After reading.
9239 13:53:52.708401 Root Device child on link 0 CPU_CLUSTER: 0
9240 13:53:52.711817 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 13:53:52.721659 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 13:53:52.721741 CPU: 00
9243 13:53:52.725122 Root Device assign_resources, bus 0 link: 0
9244 13:53:52.728446 CPU_CLUSTER: 0 missing set_resources
9245 13:53:52.734879 Root Device assign_resources, bus 0 link: 0 done
9246 13:53:52.734967 Done setting resources.
9247 13:53:52.741573 Show resources in subtree (Root Device)...After assigning values.
9248 13:53:52.745211 Root Device child on link 0 CPU_CLUSTER: 0
9249 13:53:52.748224 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 13:53:52.758310 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 13:53:52.758392 CPU: 00
9252 13:53:52.761323 Done allocating resources.
9253 13:53:52.764841 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9254 13:53:52.768440 Enabling resources...
9255 13:53:52.768538 done.
9256 13:53:52.774647 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9257 13:53:52.774726 Initializing devices...
9258 13:53:52.777990 Root Device init
9259 13:53:52.778067 init hardware done!
9260 13:53:52.781359 0x00000018: ctrlr->caps
9261 13:53:52.784665 52.000 MHz: ctrlr->f_max
9262 13:53:52.784772 0.400 MHz: ctrlr->f_min
9263 13:53:52.787922 0x40ff8080: ctrlr->voltages
9264 13:53:52.788015 sclk: 390625
9265 13:53:52.791187 Bus Width = 1
9266 13:53:52.791262 sclk: 390625
9267 13:53:52.794557 Bus Width = 1
9268 13:53:52.794642 Early init status = 3
9269 13:53:52.801016 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9270 13:53:52.804406 in-header: 03 fc 00 00 01 00 00 00
9271 13:53:52.804484 in-data: 00
9272 13:53:52.811156 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9273 13:53:52.814377 in-header: 03 fd 00 00 00 00 00 00
9274 13:53:52.817891 in-data:
9275 13:53:52.821191 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9276 13:53:52.824304 in-header: 03 fc 00 00 01 00 00 00
9277 13:53:52.827777 in-data: 00
9278 13:53:52.830861 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9279 13:53:52.835748 in-header: 03 fd 00 00 00 00 00 00
9280 13:53:52.838771 in-data:
9281 13:53:52.841946 [SSUSB] Setting up USB HOST controller...
9282 13:53:52.845541 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9283 13:53:52.848616 [SSUSB] phy power-on done.
9284 13:53:52.851869 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9285 13:53:52.858656 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9286 13:53:52.861982 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9287 13:53:52.868421 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9288 13:53:52.874891 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9289 13:53:52.881758 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9290 13:53:52.888292 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9291 13:53:52.894927 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9292 13:53:52.898175 SPM: binary array size = 0x9dc
9293 13:53:52.901796 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9294 13:53:52.908140 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9295 13:53:52.914798 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9296 13:53:52.921280 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9297 13:53:52.924612 configure_display: Starting display init
9298 13:53:52.958913 anx7625_power_on_init: Init interface.
9299 13:53:52.962125 anx7625_disable_pd_protocol: Disabled PD feature.
9300 13:53:52.965723 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9301 13:53:52.993097 anx7625_start_dp_work: Secure OCM version=00
9302 13:53:52.996648 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9303 13:53:53.011244 sp_tx_get_edid_block: EDID Block = 1
9304 13:53:53.114152 Extracted contents:
9305 13:53:53.117029 header: 00 ff ff ff ff ff ff 00
9306 13:53:53.120544 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9307 13:53:53.123705 version: 01 04
9308 13:53:53.127172 basic params: 95 1f 11 78 0a
9309 13:53:53.130274 chroma info: 76 90 94 55 54 90 27 21 50 54
9310 13:53:53.133550 established: 00 00 00
9311 13:53:53.140144 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9312 13:53:53.143421 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9313 13:53:53.149988 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9314 13:53:53.156557 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9315 13:53:53.163388 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9316 13:53:53.166599 extensions: 00
9317 13:53:53.166690 checksum: fb
9318 13:53:53.166754
9319 13:53:53.173391 Manufacturer: IVO Model 57d Serial Number 0
9320 13:53:53.173502 Made week 0 of 2020
9321 13:53:53.176382 EDID version: 1.4
9322 13:53:53.176452 Digital display
9323 13:53:53.179814 6 bits per primary color channel
9324 13:53:53.179886 DisplayPort interface
9325 13:53:53.183019 Maximum image size: 31 cm x 17 cm
9326 13:53:53.186514 Gamma: 220%
9327 13:53:53.186588 Check DPMS levels
9328 13:53:53.189586 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9329 13:53:53.196633 First detailed timing is preferred timing
9330 13:53:53.196706 Established timings supported:
9331 13:53:53.199787 Standard timings supported:
9332 13:53:53.203308 Detailed timings
9333 13:53:53.206295 Hex of detail: 383680a07038204018303c0035ae10000019
9334 13:53:53.213120 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9335 13:53:53.216529 0780 0798 07c8 0820 hborder 0
9336 13:53:53.219826 0438 043b 0447 0458 vborder 0
9337 13:53:53.222903 -hsync -vsync
9338 13:53:53.222976 Did detailed timing
9339 13:53:53.229399 Hex of detail: 000000000000000000000000000000000000
9340 13:53:53.233021 Manufacturer-specified data, tag 0
9341 13:53:53.236079 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9342 13:53:53.239628 ASCII string: InfoVision
9343 13:53:53.242715 Hex of detail: 000000fe00523134304e574635205248200a
9344 13:53:53.246202 ASCII string: R140NWF5 RH
9345 13:53:53.246271 Checksum
9346 13:53:53.249411 Checksum: 0xfb (valid)
9347 13:53:53.252625 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9348 13:53:53.256132 DSI data_rate: 832800000 bps
9349 13:53:53.262530 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9350 13:53:53.265986 anx7625_parse_edid: pixelclock(138800).
9351 13:53:53.269559 hactive(1920), hsync(48), hfp(24), hbp(88)
9352 13:53:53.272380 vactive(1080), vsync(12), vfp(3), vbp(17)
9353 13:53:53.275734 anx7625_dsi_config: config dsi.
9354 13:53:53.282469 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9355 13:53:53.295764 anx7625_dsi_config: success to config DSI
9356 13:53:53.299173 anx7625_dp_start: MIPI phy setup OK.
9357 13:53:53.302813 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9358 13:53:53.305962 mtk_ddp_mode_set invalid vrefresh 60
9359 13:53:53.309341 main_disp_path_setup
9360 13:53:53.309420 ovl_layer_smi_id_en
9361 13:53:53.312474 ovl_layer_smi_id_en
9362 13:53:53.312570 ccorr_config
9363 13:53:53.312632 aal_config
9364 13:53:53.315777 gamma_config
9365 13:53:53.315882 postmask_config
9366 13:53:53.319107 dither_config
9367 13:53:53.322299 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9368 13:53:53.328994 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9369 13:53:53.332272 Root Device init finished in 551 msecs
9370 13:53:53.335641 CPU_CLUSTER: 0 init
9371 13:53:53.342430 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9372 13:53:53.345582 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9373 13:53:53.349170 APU_MBOX 0x190000b0 = 0x10001
9374 13:53:53.352388 APU_MBOX 0x190001b0 = 0x10001
9375 13:53:53.355559 APU_MBOX 0x190005b0 = 0x10001
9376 13:53:53.359076 APU_MBOX 0x190006b0 = 0x10001
9377 13:53:53.362414 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9378 13:53:53.374953 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9379 13:53:53.387323 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9380 13:53:53.393864 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9381 13:53:53.405547 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9382 13:53:53.414691 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9383 13:53:53.418222 CPU_CLUSTER: 0 init finished in 81 msecs
9384 13:53:53.421342 Devices initialized
9385 13:53:53.424469 Show all devs... After init.
9386 13:53:53.424549 Root Device: enabled 1
9387 13:53:53.428015 CPU_CLUSTER: 0: enabled 1
9388 13:53:53.431060 CPU: 00: enabled 1
9389 13:53:53.434429 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9390 13:53:53.437769 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9391 13:53:53.441005 ELOG: NV offset 0x57f000 size 0x1000
9392 13:53:53.447615 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9393 13:53:53.454339 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9394 13:53:53.457840 ELOG: Event(17) added with size 13 at 2024-02-01 13:53:54 UTC
9395 13:53:53.460995 out: cmd=0x121: 03 db 21 01 00 00 00 00
9396 13:53:53.464844 in-header: 03 55 00 00 2c 00 00 00
9397 13:53:53.478173 in-data: 09 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9398 13:53:53.484785 ELOG: Event(A1) added with size 10 at 2024-02-01 13:53:54 UTC
9399 13:53:53.491295 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9400 13:53:53.498350 ELOG: Event(A0) added with size 9 at 2024-02-01 13:53:54 UTC
9401 13:53:53.501407 elog_add_boot_reason: Logged dev mode boot
9402 13:53:53.504812 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9403 13:53:53.507902 Finalize devices...
9404 13:53:53.507983 Devices finalized
9405 13:53:53.514720 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9406 13:53:53.517874 Writing coreboot table at 0xffe64000
9407 13:53:53.521368 0. 000000000010a000-0000000000113fff: RAMSTAGE
9408 13:53:53.524514 1. 0000000040000000-00000000400fffff: RAM
9409 13:53:53.531244 2. 0000000040100000-000000004032afff: RAMSTAGE
9410 13:53:53.534347 3. 000000004032b000-00000000545fffff: RAM
9411 13:53:53.537839 4. 0000000054600000-000000005465ffff: BL31
9412 13:53:53.541013 5. 0000000054660000-00000000ffe63fff: RAM
9413 13:53:53.547678 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9414 13:53:53.550950 7. 0000000100000000-000000023fffffff: RAM
9415 13:53:53.551025 Passing 5 GPIOs to payload:
9416 13:53:53.557467 NAME | PORT | POLARITY | VALUE
9417 13:53:53.560862 EC in RW | 0x000000aa | low | undefined
9418 13:53:53.567540 EC interrupt | 0x00000005 | low | undefined
9419 13:53:53.570695 TPM interrupt | 0x000000ab | high | undefined
9420 13:53:53.577353 SD card detect | 0x00000011 | high | undefined
9421 13:53:53.580935 speaker enable | 0x00000093 | high | undefined
9422 13:53:53.584016 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9423 13:53:53.587644 in-header: 03 f9 00 00 02 00 00 00
9424 13:53:53.587729 in-data: 02 00
9425 13:53:53.590623 ADC[4]: Raw value=897780 ID=7
9426 13:53:53.594200 ADC[3]: Raw value=213440 ID=1
9427 13:53:53.597502 RAM Code: 0x71
9428 13:53:53.597583 ADC[6]: Raw value=74722 ID=0
9429 13:53:53.600550 ADC[5]: Raw value=211960 ID=1
9430 13:53:53.604129 SKU Code: 0x1
9431 13:53:53.607263 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d551
9432 13:53:53.610424 coreboot table: 964 bytes.
9433 13:53:53.613894 IMD ROOT 0. 0xfffff000 0x00001000
9434 13:53:53.617119 IMD SMALL 1. 0xffffe000 0x00001000
9435 13:53:53.620663 RO MCACHE 2. 0xffffc000 0x00001104
9436 13:53:53.623713 CONSOLE 3. 0xfff7c000 0x00080000
9437 13:53:53.627288 FMAP 4. 0xfff7b000 0x00000452
9438 13:53:53.630462 TIME STAMP 5. 0xfff7a000 0x00000910
9439 13:53:53.633897 VBOOT WORK 6. 0xfff66000 0x00014000
9440 13:53:53.637027 RAMOOPS 7. 0xffe66000 0x00100000
9441 13:53:53.640590 COREBOOT 8. 0xffe64000 0x00002000
9442 13:53:53.640692 IMD small region:
9443 13:53:53.643739 IMD ROOT 0. 0xffffec00 0x00000400
9444 13:53:53.647271 VPD 1. 0xffffeb80 0x0000006c
9445 13:53:53.650341 MMC STATUS 2. 0xffffeb60 0x00000004
9446 13:53:53.657070 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9447 13:53:53.660511 Probing TPM: done!
9448 13:53:53.663898 Connected to device vid:did:rid of 1ae0:0028:00
9449 13:53:53.673988 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9450 13:53:53.677370 Initialized TPM device CR50 revision 0
9451 13:53:53.681325 Checking cr50 for pending updates
9452 13:53:53.684358 Reading cr50 TPM mode
9453 13:53:53.692757 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9454 13:53:53.699660 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9455 13:53:53.739630 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9456 13:53:53.743132 Checking segment from ROM address 0x40100000
9457 13:53:53.746459 Checking segment from ROM address 0x4010001c
9458 13:53:53.753038 Loading segment from ROM address 0x40100000
9459 13:53:53.753132 code (compression=0)
9460 13:53:53.762855 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9461 13:53:53.769521 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9462 13:53:53.769684 it's not compressed!
9463 13:53:53.776068 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9464 13:53:53.779668 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9465 13:53:53.800065 Loading segment from ROM address 0x4010001c
9466 13:53:53.800161 Entry Point 0x80000000
9467 13:53:53.803217 Loaded segments
9468 13:53:53.806861 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9469 13:53:53.813423 Jumping to boot code at 0x80000000(0xffe64000)
9470 13:53:53.820057 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9471 13:53:53.826672 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9472 13:53:53.834561 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9473 13:53:53.837810 Checking segment from ROM address 0x40100000
9474 13:53:53.841336 Checking segment from ROM address 0x4010001c
9475 13:53:53.848006 Loading segment from ROM address 0x40100000
9476 13:53:53.848098 code (compression=1)
9477 13:53:53.854604 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9478 13:53:53.864517 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9479 13:53:53.864646 using LZMA
9480 13:53:53.872731 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9481 13:53:53.879454 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9482 13:53:53.882878 Loading segment from ROM address 0x4010001c
9483 13:53:53.882968 Entry Point 0x54601000
9484 13:53:53.886197 Loaded segments
9485 13:53:53.889300 NOTICE: MT8192 bl31_setup
9486 13:53:53.896455 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9487 13:53:53.899870 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9488 13:53:53.903071 WARNING: region 0:
9489 13:53:53.906365 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9490 13:53:53.906441 WARNING: region 1:
9491 13:53:53.913160 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9492 13:53:53.916449 WARNING: region 2:
9493 13:53:53.919763 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9494 13:53:53.923150 WARNING: region 3:
9495 13:53:53.926296 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9496 13:53:53.929491 WARNING: region 4:
9497 13:53:53.936196 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9498 13:53:53.936277 WARNING: region 5:
9499 13:53:53.939734 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 13:53:53.942948 WARNING: region 6:
9501 13:53:53.946217 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 13:53:53.949695 WARNING: region 7:
9503 13:53:53.952962 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 13:53:53.959821 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9505 13:53:53.962878 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9506 13:53:53.966506 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9507 13:53:53.973086 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9508 13:53:53.976310 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9509 13:53:53.979815 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9510 13:53:53.986415 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9511 13:53:53.989934 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9512 13:53:53.993055 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9513 13:53:53.999807 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9514 13:53:54.003300 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9515 13:53:54.009868 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9516 13:53:54.013063 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9517 13:53:54.016436 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9518 13:53:54.023144 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9519 13:53:54.026507 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9520 13:53:54.029870 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9521 13:53:54.036330 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9522 13:53:54.039839 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9523 13:53:54.046292 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9524 13:53:54.049735 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9525 13:53:54.052910 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9526 13:53:54.059613 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9527 13:53:54.063172 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9528 13:53:54.069641 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9529 13:53:54.073072 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9530 13:53:54.076428 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9531 13:53:54.082971 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9532 13:53:54.086320 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9533 13:53:54.092932 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9534 13:53:54.096288 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9535 13:53:54.099420 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9536 13:53:54.106233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9537 13:53:54.109721 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9538 13:53:54.112927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9539 13:53:54.116277 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9540 13:53:54.123085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9541 13:53:54.126076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9542 13:53:54.129447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9543 13:53:54.132725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9544 13:53:54.139381 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9545 13:53:54.142961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9546 13:53:54.146012 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9547 13:53:54.149466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9548 13:53:54.156132 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9549 13:53:54.159289 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9550 13:53:54.162776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9551 13:53:54.166150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9552 13:53:54.172853 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9553 13:53:54.176101 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9554 13:53:54.182794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9555 13:53:54.186264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9556 13:53:54.192785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9557 13:53:54.196123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9558 13:53:54.199361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9559 13:53:54.206397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9560 13:53:54.209661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9561 13:53:54.216083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9562 13:53:54.219468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9563 13:53:54.222694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9564 13:53:54.229426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9565 13:53:54.232718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9566 13:53:54.239562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9567 13:53:54.243024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9568 13:53:54.249718 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9569 13:53:54.252841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9570 13:53:54.259423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9571 13:53:54.263093 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9572 13:53:54.266197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9573 13:53:54.272710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9574 13:53:54.276532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9575 13:53:54.282714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9576 13:53:54.286370 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9577 13:53:54.289518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9578 13:53:54.296414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9579 13:53:54.299472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9580 13:53:54.306449 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9581 13:53:54.309424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9582 13:53:54.316440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9583 13:53:54.319437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9584 13:53:54.325991 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9585 13:53:54.329741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9586 13:53:54.332712 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9587 13:53:54.339450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9588 13:53:54.342819 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9589 13:53:54.349436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9590 13:53:54.352907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9591 13:53:54.359466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9592 13:53:54.362626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9593 13:53:54.366174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9594 13:53:54.372843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9595 13:53:54.376067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9596 13:53:54.382756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9597 13:53:54.386143 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9598 13:53:54.392977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9599 13:53:54.396070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9600 13:53:54.399561 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9601 13:53:54.406183 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9602 13:53:54.409318 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9603 13:53:54.412666 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9604 13:53:54.415879 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9605 13:53:54.422513 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9606 13:53:54.425926 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9607 13:53:54.432412 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9608 13:53:54.435895 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9609 13:53:54.439425 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9610 13:53:54.445729 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9611 13:53:54.449138 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9612 13:53:54.455676 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9613 13:53:54.459078 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9614 13:53:54.462393 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9615 13:53:54.469083 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9616 13:53:54.472118 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9617 13:53:54.478878 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9618 13:53:54.482446 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9619 13:53:54.485655 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9620 13:53:54.492315 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9621 13:53:54.495475 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9622 13:53:54.498964 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9623 13:53:54.505611 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9624 13:53:54.508753 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9625 13:53:54.512343 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9626 13:53:54.515384 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9627 13:53:54.522050 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9628 13:53:54.525876 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9629 13:53:54.528882 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9630 13:53:54.535493 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9631 13:53:54.538674 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9632 13:53:54.545665 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9633 13:53:54.548785 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9634 13:53:54.552333 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9635 13:53:54.558849 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9636 13:53:54.562139 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9637 13:53:54.565510 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9638 13:53:54.571987 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9639 13:53:54.575459 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9640 13:53:54.582235 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9641 13:53:54.585572 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9642 13:53:54.588743 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9643 13:53:54.595394 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9644 13:53:54.598822 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9645 13:53:54.602381 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9646 13:53:54.608982 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9647 13:53:54.612049 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9648 13:53:54.618831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9649 13:53:54.621973 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9650 13:53:54.625654 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9651 13:53:54.631915 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9652 13:53:54.635418 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9653 13:53:54.642404 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9654 13:53:54.645440 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9655 13:53:54.648884 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9656 13:53:54.655541 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9657 13:53:54.658655 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9658 13:53:54.665491 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9659 13:53:54.668709 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9660 13:53:54.672088 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9661 13:53:54.678572 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9662 13:53:54.682094 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9663 13:53:54.685186 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9664 13:53:54.691878 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9665 13:53:54.695354 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9666 13:53:54.701704 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9667 13:53:54.705114 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9668 13:53:54.708629 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9669 13:53:54.715214 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9670 13:53:54.718343 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9671 13:53:54.725008 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9672 13:53:54.728560 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9673 13:53:54.731996 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9674 13:53:54.738675 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9675 13:53:54.741776 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9676 13:53:54.748476 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9677 13:53:54.751469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9678 13:53:54.754757 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9679 13:53:54.761642 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9680 13:53:54.764874 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9681 13:53:54.771542 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9682 13:53:54.774668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9683 13:53:54.777963 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9684 13:53:54.784823 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9685 13:53:54.788117 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9686 13:53:54.794675 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9687 13:53:54.798078 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9688 13:53:54.801193 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9689 13:53:54.807826 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9690 13:53:54.811399 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9691 13:53:54.814442 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9692 13:53:54.821306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9693 13:53:54.824429 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9694 13:53:54.831205 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9695 13:53:54.834213 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9696 13:53:54.841135 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9697 13:53:54.844213 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9698 13:53:54.847735 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9699 13:53:54.854158 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9700 13:53:54.857682 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9701 13:53:54.864045 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9702 13:53:54.867446 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9703 13:53:54.874110 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9704 13:53:54.877287 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9705 13:53:54.880942 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9706 13:53:54.887506 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9707 13:53:54.890491 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9708 13:53:54.897329 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9709 13:53:54.900668 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9710 13:53:54.904145 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9711 13:53:54.910820 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9712 13:53:54.913940 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9713 13:53:54.920822 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9714 13:53:54.923765 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9715 13:53:54.930721 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9716 13:53:54.933765 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9717 13:53:54.937015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9718 13:53:54.943629 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9719 13:53:54.947113 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9720 13:53:54.953697 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9721 13:53:54.956961 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9722 13:53:54.963664 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9723 13:53:54.966826 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9724 13:53:54.970210 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9725 13:53:54.976686 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9726 13:53:54.980179 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9727 13:53:54.986739 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9728 13:53:54.990415 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9729 13:53:54.993389 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9730 13:53:54.999876 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9731 13:53:55.003465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9732 13:53:55.009710 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9733 13:53:55.013075 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9734 13:53:55.016400 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9735 13:53:55.019756 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9736 13:53:55.026381 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9737 13:53:55.029459 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9738 13:53:55.032822 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9739 13:53:55.039685 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9740 13:53:55.042820 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9741 13:53:55.046085 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9742 13:53:55.052694 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9743 13:53:55.056190 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9744 13:53:55.062742 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9745 13:53:55.066339 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9746 13:53:55.069390 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9747 13:53:55.075990 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9748 13:53:55.079358 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9749 13:53:55.082706 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9750 13:53:55.089233 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9751 13:53:55.092564 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9752 13:53:55.095706 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9753 13:53:55.102359 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9754 13:53:55.105700 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9755 13:53:55.112397 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9756 13:53:55.115479 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9757 13:53:55.118717 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9758 13:53:55.125430 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9759 13:53:55.128686 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9760 13:53:55.132155 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9761 13:53:55.138680 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9762 13:53:55.142074 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9763 13:53:55.148499 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9764 13:53:55.151906 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9765 13:53:55.155462 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9766 13:53:55.161861 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9767 13:53:55.164918 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9768 13:53:55.168448 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9769 13:53:55.174628 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9770 13:53:55.178076 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9771 13:53:55.184644 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9772 13:53:55.187869 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9773 13:53:55.191303 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9774 13:53:55.194794 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9775 13:53:55.201164 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9776 13:53:55.204708 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9777 13:53:55.207804 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9778 13:53:55.211065 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9779 13:53:55.217689 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9780 13:53:55.221132 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9781 13:53:55.224467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9782 13:53:55.227664 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9783 13:53:55.234156 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9784 13:53:55.237673 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9785 13:53:55.240734 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9786 13:53:55.247384 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9787 13:53:55.250810 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9788 13:53:55.257316 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9789 13:53:55.260513 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9790 13:53:55.263897 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9791 13:53:55.270755 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9792 13:53:55.274075 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9793 13:53:55.277620 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9794 13:53:55.284197 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9795 13:53:55.287596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9796 13:53:55.294156 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9797 13:53:55.297353 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9798 13:53:55.304110 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9799 13:53:55.307211 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9800 13:53:55.313850 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9801 13:53:55.317191 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9802 13:53:55.320187 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9803 13:53:55.327102 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9804 13:53:55.330452 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9805 13:53:55.336981 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9806 13:53:55.340150 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9807 13:53:55.343569 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9808 13:53:55.350117 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9809 13:53:55.353372 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9810 13:53:55.359976 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9811 13:53:55.363339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9812 13:53:55.366525 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9813 13:53:55.373118 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9814 13:53:55.376576 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9815 13:53:55.383364 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9816 13:53:55.386404 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9817 13:53:55.389602 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9818 13:53:55.396596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9819 13:53:55.399616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9820 13:53:55.406059 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9821 13:53:55.409787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9822 13:53:55.416011 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9823 13:53:55.419497 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9824 13:53:55.422787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9825 13:53:55.429694 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9826 13:53:55.432779 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9827 13:53:55.439414 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9828 13:53:55.442537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9829 13:53:55.445947 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9830 13:53:55.452535 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9831 13:53:55.455830 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9832 13:53:55.462347 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9833 13:53:55.465512 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9834 13:53:55.472397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9835 13:53:55.475582 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9836 13:53:55.478745 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9837 13:53:55.485522 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9838 13:53:55.488875 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9839 13:53:55.495314 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9840 13:53:55.498721 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9841 13:53:55.501957 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9842 13:53:55.508825 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9843 13:53:55.511773 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9844 13:53:55.518504 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9845 13:53:55.521951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9846 13:53:55.528341 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9847 13:53:55.531662 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9848 13:53:55.535172 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9849 13:53:55.541816 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9850 13:53:55.544922 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9851 13:53:55.551591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9852 13:53:55.555151 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9853 13:53:55.558180 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9854 13:53:55.564844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9855 13:53:55.568027 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9856 13:53:55.574967 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9857 13:53:55.578066 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9858 13:53:55.581616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9859 13:53:55.588264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9860 13:53:55.591463 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9861 13:53:55.597789 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9862 13:53:55.601294 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9863 13:53:55.607787 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9864 13:53:55.611122 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9865 13:53:55.617674 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9866 13:53:55.621161 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9867 13:53:55.624548 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9868 13:53:55.631319 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9869 13:53:55.634303 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9870 13:53:55.641162 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9871 13:53:55.644424 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9872 13:53:55.650913 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9873 13:53:55.654471 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9874 13:53:55.657646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9875 13:53:55.664389 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9876 13:53:55.667539 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9877 13:53:55.674383 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9878 13:53:55.677492 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9879 13:53:55.684227 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9880 13:53:55.687495 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9881 13:53:55.690703 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9882 13:53:55.697541 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9883 13:53:55.700493 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9884 13:53:55.707335 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9885 13:53:55.710490 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9886 13:53:55.717355 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9887 13:53:55.720796 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9888 13:53:55.727329 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9889 13:53:55.730590 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9890 13:53:55.733923 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9891 13:53:55.740462 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9892 13:53:55.743745 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9893 13:53:55.750455 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9894 13:53:55.753720 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9895 13:53:55.760517 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9896 13:53:55.763621 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9897 13:53:55.767194 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9898 13:53:55.773343 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9899 13:53:55.777044 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9900 13:53:55.783470 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9901 13:53:55.786782 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9902 13:53:55.793526 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9903 13:53:55.796695 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9904 13:53:55.803327 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9905 13:53:55.806792 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9906 13:53:55.810158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9907 13:53:55.816911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9908 13:53:55.819838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9909 13:53:55.826557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9910 13:53:55.829806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9911 13:53:55.836507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9912 13:53:55.839699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9913 13:53:55.846505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9914 13:53:55.849867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9915 13:53:55.856306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9916 13:53:55.859749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9917 13:53:55.866195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9918 13:53:55.869636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9919 13:53:55.873125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9920 13:53:55.879750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9921 13:53:55.882920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9922 13:53:55.889764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9923 13:53:55.892761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9924 13:53:55.899627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9925 13:53:55.903009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9926 13:53:55.909598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9927 13:53:55.912781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9928 13:53:55.919418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9929 13:53:55.922696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9930 13:53:55.929357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9931 13:53:55.932564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9932 13:53:55.939111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9933 13:53:55.942713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9934 13:53:55.948957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9935 13:53:55.952537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9936 13:53:55.958990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9937 13:53:55.962384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9938 13:53:55.968935 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9939 13:53:55.969010 INFO: [APUAPC] vio 0
9940 13:53:55.976170 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9941 13:53:55.979367 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9942 13:53:55.982795 INFO: [APUAPC] D0_APC_0: 0x400510
9943 13:53:55.986349 INFO: [APUAPC] D0_APC_1: 0x0
9944 13:53:55.989412 INFO: [APUAPC] D0_APC_2: 0x1540
9945 13:53:55.992970 INFO: [APUAPC] D0_APC_3: 0x0
9946 13:53:55.996034 INFO: [APUAPC] D1_APC_0: 0xffffffff
9947 13:53:55.999598 INFO: [APUAPC] D1_APC_1: 0xffffffff
9948 13:53:56.002685 INFO: [APUAPC] D1_APC_2: 0x3fffff
9949 13:53:56.006205 INFO: [APUAPC] D1_APC_3: 0x0
9950 13:53:56.009332 INFO: [APUAPC] D2_APC_0: 0xffffffff
9951 13:53:56.012692 INFO: [APUAPC] D2_APC_1: 0xffffffff
9952 13:53:56.016409 INFO: [APUAPC] D2_APC_2: 0x3fffff
9953 13:53:56.019577 INFO: [APUAPC] D2_APC_3: 0x0
9954 13:53:56.022900 INFO: [APUAPC] D3_APC_0: 0xffffffff
9955 13:53:56.026468 INFO: [APUAPC] D3_APC_1: 0xffffffff
9956 13:53:56.029384 INFO: [APUAPC] D3_APC_2: 0x3fffff
9957 13:53:56.029456 INFO: [APUAPC] D3_APC_3: 0x0
9958 13:53:56.036252 INFO: [APUAPC] D4_APC_0: 0xffffffff
9959 13:53:56.039368 INFO: [APUAPC] D4_APC_1: 0xffffffff
9960 13:53:56.042787 INFO: [APUAPC] D4_APC_2: 0x3fffff
9961 13:53:56.042869 INFO: [APUAPC] D4_APC_3: 0x0
9962 13:53:56.045978 INFO: [APUAPC] D5_APC_0: 0xffffffff
9963 13:53:56.049428 INFO: [APUAPC] D5_APC_1: 0xffffffff
9964 13:53:56.052565 INFO: [APUAPC] D5_APC_2: 0x3fffff
9965 13:53:56.056183 INFO: [APUAPC] D5_APC_3: 0x0
9966 13:53:56.059232 INFO: [APUAPC] D6_APC_0: 0xffffffff
9967 13:53:56.062574 INFO: [APUAPC] D6_APC_1: 0xffffffff
9968 13:53:56.065724 INFO: [APUAPC] D6_APC_2: 0x3fffff
9969 13:53:56.069335 INFO: [APUAPC] D6_APC_3: 0x0
9970 13:53:56.072397 INFO: [APUAPC] D7_APC_0: 0xffffffff
9971 13:53:56.075908 INFO: [APUAPC] D7_APC_1: 0xffffffff
9972 13:53:56.079042 INFO: [APUAPC] D7_APC_2: 0x3fffff
9973 13:53:56.082416 INFO: [APUAPC] D7_APC_3: 0x0
9974 13:53:56.085652 INFO: [APUAPC] D8_APC_0: 0xffffffff
9975 13:53:56.089098 INFO: [APUAPC] D8_APC_1: 0xffffffff
9976 13:53:56.092102 INFO: [APUAPC] D8_APC_2: 0x3fffff
9977 13:53:56.095598 INFO: [APUAPC] D8_APC_3: 0x0
9978 13:53:56.098876 INFO: [APUAPC] D9_APC_0: 0xffffffff
9979 13:53:56.102209 INFO: [APUAPC] D9_APC_1: 0xffffffff
9980 13:53:56.105767 INFO: [APUAPC] D9_APC_2: 0x3fffff
9981 13:53:56.108903 INFO: [APUAPC] D9_APC_3: 0x0
9982 13:53:56.112055 INFO: [APUAPC] D10_APC_0: 0xffffffff
9983 13:53:56.115533 INFO: [APUAPC] D10_APC_1: 0xffffffff
9984 13:53:56.118667 INFO: [APUAPC] D10_APC_2: 0x3fffff
9985 13:53:56.122022 INFO: [APUAPC] D10_APC_3: 0x0
9986 13:53:56.125101 INFO: [APUAPC] D11_APC_0: 0xffffffff
9987 13:53:56.128531 INFO: [APUAPC] D11_APC_1: 0xffffffff
9988 13:53:56.131957 INFO: [APUAPC] D11_APC_2: 0x3fffff
9989 13:53:56.135471 INFO: [APUAPC] D11_APC_3: 0x0
9990 13:53:56.138714 INFO: [APUAPC] D12_APC_0: 0xffffffff
9991 13:53:56.141985 INFO: [APUAPC] D12_APC_1: 0xffffffff
9992 13:53:56.145276 INFO: [APUAPC] D12_APC_2: 0x3fffff
9993 13:53:56.148770 INFO: [APUAPC] D12_APC_3: 0x0
9994 13:53:56.151835 INFO: [APUAPC] D13_APC_0: 0xffffffff
9995 13:53:56.154980 INFO: [APUAPC] D13_APC_1: 0xffffffff
9996 13:53:56.158478 INFO: [APUAPC] D13_APC_2: 0x3fffff
9997 13:53:56.161623 INFO: [APUAPC] D13_APC_3: 0x0
9998 13:53:56.165108 INFO: [APUAPC] D14_APC_0: 0xffffffff
9999 13:53:56.168389 INFO: [APUAPC] D14_APC_1: 0xffffffff
10000 13:53:56.171774 INFO: [APUAPC] D14_APC_2: 0x3fffff
10001 13:53:56.174808 INFO: [APUAPC] D14_APC_3: 0x0
10002 13:53:56.178299 INFO: [APUAPC] D15_APC_0: 0xffffffff
10003 13:53:56.181627 INFO: [APUAPC] D15_APC_1: 0xffffffff
10004 13:53:56.184774 INFO: [APUAPC] D15_APC_2: 0x3fffff
10005 13:53:56.188363 INFO: [APUAPC] D15_APC_3: 0x0
10006 13:53:56.191567 INFO: [APUAPC] APC_CON: 0x4
10007 13:53:56.194671 INFO: [NOCDAPC] D0_APC_0: 0x0
10008 13:53:56.198321 INFO: [NOCDAPC] D0_APC_1: 0x0
10009 13:53:56.201631 INFO: [NOCDAPC] D1_APC_0: 0x0
10010 13:53:56.204793 INFO: [NOCDAPC] D1_APC_1: 0xfff
10011 13:53:56.208150 INFO: [NOCDAPC] D2_APC_0: 0x0
10012 13:53:56.211237 INFO: [NOCDAPC] D2_APC_1: 0xfff
10013 13:53:56.211318 INFO: [NOCDAPC] D3_APC_0: 0x0
10014 13:53:56.214634 INFO: [NOCDAPC] D3_APC_1: 0xfff
10015 13:53:56.218125 INFO: [NOCDAPC] D4_APC_0: 0x0
10016 13:53:56.221438 INFO: [NOCDAPC] D4_APC_1: 0xfff
10017 13:53:56.224539 INFO: [NOCDAPC] D5_APC_0: 0x0
10018 13:53:56.228023 INFO: [NOCDAPC] D5_APC_1: 0xfff
10019 13:53:56.231096 INFO: [NOCDAPC] D6_APC_0: 0x0
10020 13:53:56.234603 INFO: [NOCDAPC] D6_APC_1: 0xfff
10021 13:53:56.237700 INFO: [NOCDAPC] D7_APC_0: 0x0
10022 13:53:56.240985 INFO: [NOCDAPC] D7_APC_1: 0xfff
10023 13:53:56.244316 INFO: [NOCDAPC] D8_APC_0: 0x0
10024 13:53:56.247648 INFO: [NOCDAPC] D8_APC_1: 0xfff
10025 13:53:56.247729 INFO: [NOCDAPC] D9_APC_0: 0x0
10026 13:53:56.251063 INFO: [NOCDAPC] D9_APC_1: 0xfff
10027 13:53:56.254122 INFO: [NOCDAPC] D10_APC_0: 0x0
10028 13:53:56.257814 INFO: [NOCDAPC] D10_APC_1: 0xfff
10029 13:53:56.260863 INFO: [NOCDAPC] D11_APC_0: 0x0
10030 13:53:56.264553 INFO: [NOCDAPC] D11_APC_1: 0xfff
10031 13:53:56.267578 INFO: [NOCDAPC] D12_APC_0: 0x0
10032 13:53:56.271114 INFO: [NOCDAPC] D12_APC_1: 0xfff
10033 13:53:56.274117 INFO: [NOCDAPC] D13_APC_0: 0x0
10034 13:53:56.277605 INFO: [NOCDAPC] D13_APC_1: 0xfff
10035 13:53:56.280732 INFO: [NOCDAPC] D14_APC_0: 0x0
10036 13:53:56.284323 INFO: [NOCDAPC] D14_APC_1: 0xfff
10037 13:53:56.287509 INFO: [NOCDAPC] D15_APC_0: 0x0
10038 13:53:56.290470 INFO: [NOCDAPC] D15_APC_1: 0xfff
10039 13:53:56.290551 INFO: [NOCDAPC] APC_CON: 0x4
10040 13:53:56.293934 INFO: [APUAPC] set_apusys_apc done
10041 13:53:56.297106 INFO: [DEVAPC] devapc_init done
10042 13:53:56.303925 INFO: GICv3 without legacy support detected.
10043 13:53:56.307085 INFO: ARM GICv3 driver initialized in EL3
10044 13:53:56.310740 INFO: Maximum SPI INTID supported: 639
10045 13:53:56.313872 INFO: BL31: Initializing runtime services
10046 13:53:56.320487 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10047 13:53:56.323617 INFO: SPM: enable CPC mode
10048 13:53:56.327006 INFO: mcdi ready for mcusys-off-idle and system suspend
10049 13:53:56.333905 INFO: BL31: Preparing for EL3 exit to normal world
10050 13:53:56.337010 INFO: Entry point address = 0x80000000
10051 13:53:56.337091 INFO: SPSR = 0x8
10052 13:53:56.344304
10053 13:53:56.344410
10054 13:53:56.344485
10055 13:53:56.347740 Starting depthcharge on Spherion...
10056 13:53:56.347820
10057 13:53:56.347883 Wipe memory regions:
10058 13:53:56.347942
10059 13:53:56.348589 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10060 13:53:56.348689 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10061 13:53:56.348770 Setting prompt string to ['asurada:']
10062 13:53:56.348849 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10063 13:53:56.350725 [0x00000040000000, 0x00000054600000)
10064 13:53:56.473150
10065 13:53:56.473264 [0x00000054660000, 0x00000080000000)
10066 13:53:56.733972
10067 13:53:56.734111 [0x000000821a7280, 0x000000ffe64000)
10068 13:53:57.478769
10069 13:53:57.478921 [0x00000100000000, 0x00000240000000)
10070 13:53:59.369201
10071 13:53:59.372557 Initializing XHCI USB controller at 0x11200000.
10072 13:54:00.410330
10073 13:54:00.413729 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10074 13:54:00.413821
10075 13:54:00.413886
10076 13:54:00.413947
10077 13:54:00.414227 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10079 13:54:00.514551 asurada: tftpboot 192.168.201.1 12682925/tftp-deploy-kqtpze1w/kernel/image.itb 12682925/tftp-deploy-kqtpze1w/kernel/cmdline
10080 13:54:00.514683 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 13:54:00.514771 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10082 13:54:00.518931 tftpboot 192.168.201.1 12682925/tftp-deploy-kqtpze1w/kernel/image.itbtp-deploy-kqtpze1w/kernel/cmdline
10083 13:54:00.519017
10084 13:54:00.519082 Waiting for link
10085 13:54:00.679352
10086 13:54:00.679503 R8152: Initializing
10087 13:54:00.679574
10088 13:54:00.682759 Version 6 (ocp_data = 5c30)
10089 13:54:00.682867
10090 13:54:00.686043 R8152: Done initializing
10091 13:54:00.686145
10092 13:54:00.686237 Adding net device
10093 13:54:02.589545
10094 13:54:02.589687 done.
10095 13:54:02.589761
10096 13:54:02.589824 MAC: 00:24:32:30:78:ff
10097 13:54:02.589884
10098 13:54:02.592804 Sending DHCP discover... done.
10099 13:54:02.592876
10100 13:54:02.596304 Waiting for reply... done.
10101 13:54:02.596376
10102 13:54:02.599461 Sending DHCP request... done.
10103 13:54:02.599533
10104 13:54:02.599595 Waiting for reply... done.
10105 13:54:02.599653
10106 13:54:02.602723 My ip is 192.168.201.21
10107 13:54:02.602792
10108 13:54:02.606230 The DHCP server ip is 192.168.201.1
10109 13:54:02.606302
10110 13:54:02.609299 TFTP server IP predefined by user: 192.168.201.1
10111 13:54:02.609370
10112 13:54:02.616273 Bootfile predefined by user: 12682925/tftp-deploy-kqtpze1w/kernel/image.itb
10113 13:54:02.616359
10114 13:54:02.619412 Sending tftp read request... done.
10115 13:54:02.619485
10116 13:54:02.622744 Waiting for the transfer...
10117 13:54:02.622816
10118 13:54:03.153634 00000000 ################################################################
10119 13:54:03.153778
10120 13:54:03.673997 00080000 ################################################################
10121 13:54:03.674141
10122 13:54:04.203240 00100000 ################################################################
10123 13:54:04.203386
10124 13:54:04.723480 00180000 ################################################################
10125 13:54:04.723624
10126 13:54:05.244657 00200000 ################################################################
10127 13:54:05.244790
10128 13:54:05.764887 00280000 ################################################################
10129 13:54:05.765025
10130 13:54:06.284535 00300000 ################################################################
10131 13:54:06.284672
10132 13:54:06.806285 00380000 ################################################################
10133 13:54:06.806425
10134 13:54:07.327249 00400000 ################################################################
10135 13:54:07.327403
10136 13:54:07.849924 00480000 ################################################################
10137 13:54:07.850068
10138 13:54:08.372032 00500000 ################################################################
10139 13:54:08.372205
10140 13:54:08.892462 00580000 ################################################################
10141 13:54:08.892608
10142 13:54:09.413592 00600000 ################################################################
10143 13:54:09.413727
10144 13:54:09.934295 00680000 ################################################################
10145 13:54:09.934443
10146 13:54:10.479780 00700000 ################################################################
10147 13:54:10.479945
10148 13:54:11.002920 00780000 ################################################################
10149 13:54:11.003065
10150 13:54:11.525339 00800000 ################################################################
10151 13:54:11.525548
10152 13:54:12.045712 00880000 ################################################################
10153 13:54:12.045860
10154 13:54:12.572562 00900000 ################################################################
10155 13:54:12.572700
10156 13:54:13.093116 00980000 ################################################################
10157 13:54:13.093261
10158 13:54:13.612389 00a00000 ################################################################
10159 13:54:13.612544
10160 13:54:14.133056 00a80000 ################################################################
10161 13:54:14.133233
10162 13:54:14.655585 00b00000 ################################################################
10163 13:54:14.655718
10164 13:54:15.179381 00b80000 ################################################################
10165 13:54:15.179516
10166 13:54:15.700148 00c00000 ################################################################
10167 13:54:15.700311
10168 13:54:16.221372 00c80000 ################################################################
10169 13:54:16.221516
10170 13:54:16.752128 00d00000 ################################################################
10171 13:54:16.752292
10172 13:54:17.302109 00d80000 ################################################################
10173 13:54:17.302242
10174 13:54:17.846274 00e00000 ################################################################
10175 13:54:17.846411
10176 13:54:18.417615 00e80000 ################################################################
10177 13:54:18.417748
10178 13:54:18.977660 00f00000 ################################################################
10179 13:54:18.977799
10180 13:54:19.524709 00f80000 ################################################################
10181 13:54:19.524854
10182 13:54:20.075327 01000000 ################################################################
10183 13:54:20.075464
10184 13:54:20.613381 01080000 ################################################################
10185 13:54:20.613527
10186 13:54:21.173274 01100000 ################################################################
10187 13:54:21.173412
10188 13:54:21.804741 01180000 ################################################################
10189 13:54:21.804887
10190 13:54:22.476291 01200000 ################################################################
10191 13:54:22.476435
10192 13:54:23.092003 01280000 ################################################################
10193 13:54:23.092163
10194 13:54:23.648074 01300000 ################################################################
10195 13:54:23.648207
10196 13:54:24.204181 01380000 ################################################################
10197 13:54:24.204353
10198 13:54:24.768595 01400000 ################################################################
10199 13:54:24.768787
10200 13:54:25.328683 01480000 ################################################################
10201 13:54:25.328818
10202 13:54:25.897523 01500000 ################################################################
10203 13:54:25.897696
10204 13:54:26.552843 01580000 ################################################################
10205 13:54:26.553468
10206 13:54:27.145669 01600000 ################################################################
10207 13:54:27.145839
10208 13:54:27.711194 01680000 ################################################################
10209 13:54:27.711332
10210 13:54:28.266665 01700000 ################################################################
10211 13:54:28.266800
10212 13:54:28.831722 01780000 ################################################################
10213 13:54:28.831863
10214 13:54:29.401878 01800000 ################################################################
10215 13:54:29.402021
10216 13:54:29.963934 01880000 ################################################################
10217 13:54:29.964082
10218 13:54:30.526005 01900000 ################################################################
10219 13:54:30.526155
10220 13:54:31.132511 01980000 ################################################################
10221 13:54:31.132658
10222 13:54:31.721346 01a00000 ################################################################
10223 13:54:31.721503
10224 13:54:32.395697 01a80000 ################################################################
10225 13:54:32.396241
10226 13:54:33.077905 01b00000 ################################################################
10227 13:54:33.078417
10228 13:54:33.689273 01b80000 ################################################################
10229 13:54:33.689421
10230 13:54:34.298624 01c00000 ################################################################
10231 13:54:34.298774
10232 13:54:34.991484 01c80000 ################################################################
10233 13:54:34.992154
10234 13:54:35.680257 01d00000 ################################################################
10235 13:54:35.680774
10236 13:54:36.363308 01d80000 ################################################################
10237 13:54:36.363821
10238 13:54:36.940650 01e00000 ################################################################
10239 13:54:36.940822
10240 13:54:37.522402 01e80000 ################################################################
10241 13:54:37.522545
10242 13:54:38.074378 01f00000 ################################################################
10243 13:54:38.074552
10244 13:54:38.601995 01f80000 ######################################################### done.
10245 13:54:38.602494
10246 13:54:38.605633 The bootfile was 33495518 bytes long.
10247 13:54:38.606060
10248 13:54:38.608922 Sending tftp read request... done.
10249 13:54:38.609346
10250 13:54:38.613168 Waiting for the transfer...
10251 13:54:38.613744
10252 13:54:38.614400 00000000 # done.
10253 13:54:38.614825
10254 13:54:38.619228 Command line loaded dynamically from TFTP file: 12682925/tftp-deploy-kqtpze1w/kernel/cmdline
10255 13:54:38.622798
10256 13:54:38.632889 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10257 13:54:38.636053
10258 13:54:38.636537 Loading FIT.
10259 13:54:38.636916
10260 13:54:38.639645 Image ramdisk-1 has 21399346 bytes.
10261 13:54:38.640109
10262 13:54:38.642860 Image fdt-1 has 47278 bytes.
10263 13:54:38.643410
10264 13:54:38.645841 Image kernel-1 has 12046857 bytes.
10265 13:54:38.646296
10266 13:54:38.652446 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10267 13:54:38.652892
10268 13:54:38.672340 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10269 13:54:38.672795
10270 13:54:38.675837 Choosing best match conf-1 for compat google,spherion-rev2.
10271 13:54:38.680650
10272 13:54:38.685028 Connected to device vid:did:rid of 1ae0:0028:00
10273 13:54:38.693321
10274 13:54:38.696351 tpm_get_response: command 0x17b, return code 0x0
10275 13:54:38.696796
10276 13:54:38.699884 ec_init: CrosEC protocol v3 supported (256, 248)
10277 13:54:38.704751
10278 13:54:38.708009 tpm_cleanup: add release locality here.
10279 13:54:38.708466
10280 13:54:38.709009 Shutting down all USB controllers.
10281 13:54:38.711252
10282 13:54:38.711696 Removing current net device
10283 13:54:38.712037
10284 13:54:38.717878 Exiting depthcharge with code 4 at timestamp: 71688896
10285 13:54:38.718307
10286 13:54:38.721047 LZMA decompressing kernel-1 to 0x821a6718
10287 13:54:38.721612
10288 13:54:38.724468 LZMA decompressing kernel-1 to 0x40000000
10289 13:54:40.224778
10290 13:54:40.225299 jumping to kernel
10291 13:54:40.227125 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10292 13:54:40.227692 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10293 13:54:40.228075 Setting prompt string to ['Linux version [0-9]']
10294 13:54:40.228430 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10295 13:54:40.228775 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10296 13:54:40.307083
10297 13:54:40.310562 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10298 13:54:40.314105 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10299 13:54:40.314580 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10300 13:54:40.315009 Setting prompt string to []
10301 13:54:40.315527 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10302 13:54:40.316088 Using line separator: #'\n'#
10303 13:54:40.316581 No login prompt set.
10304 13:54:40.317143 Parsing kernel messages
10305 13:54:40.317660 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10306 13:54:40.318292 [login-action] Waiting for messages, (timeout 00:03:41)
10307 13:54:40.333606 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10308 13:54:40.336607 [ 0.000000] random: crng init done
10309 13:54:40.343391 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10310 13:54:40.346813 [ 0.000000] efi: UEFI not found.
10311 13:54:40.353675 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10312 13:54:40.360081 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10313 13:54:40.370407 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10314 13:54:40.379928 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10315 13:54:40.386609 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10316 13:54:40.393173 [ 0.000000] printk: bootconsole [mtk8250] enabled
10317 13:54:40.399919 [ 0.000000] NUMA: No NUMA configuration found
10318 13:54:40.406528 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10319 13:54:40.409855 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10320 13:54:40.413012 [ 0.000000] Zone ranges:
10321 13:54:40.419750 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10322 13:54:40.423142 [ 0.000000] DMA32 empty
10323 13:54:40.429831 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10324 13:54:40.432975 [ 0.000000] Movable zone start for each node
10325 13:54:40.436384 [ 0.000000] Early memory node ranges
10326 13:54:40.443041 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10327 13:54:40.449595 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10328 13:54:40.456343 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10329 13:54:40.462850 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10330 13:54:40.466248 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10331 13:54:40.475813 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10332 13:54:40.531640 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10333 13:54:40.538249 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10334 13:54:40.544966 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10335 13:54:40.548188 [ 0.000000] psci: probing for conduit method from DT.
10336 13:54:40.554805 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10337 13:54:40.558226 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10338 13:54:40.564835 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10339 13:54:40.568283 [ 0.000000] psci: SMC Calling Convention v1.2
10340 13:54:40.574612 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10341 13:54:40.578059 [ 0.000000] Detected VIPT I-cache on CPU0
10342 13:54:40.584781 [ 0.000000] CPU features: detected: GIC system register CPU interface
10343 13:54:40.591316 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10344 13:54:40.598019 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10345 13:54:40.604687 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10346 13:54:40.611043 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10347 13:54:40.621016 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10348 13:54:40.624573 [ 0.000000] alternatives: applying boot alternatives
10349 13:54:40.630849 [ 0.000000] Fallback order for Node 0: 0
10350 13:54:40.637536 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10351 13:54:40.640869 [ 0.000000] Policy zone: Normal
10352 13:54:40.654192 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10353 13:54:40.663906 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10354 13:54:40.675939 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10355 13:54:40.686145 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10356 13:54:40.692736 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10357 13:54:40.695874 <6>[ 0.000000] software IO TLB: area num 8.
10358 13:54:40.753849 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10359 13:54:40.903034 <6>[ 0.000000] Memory: 7946356K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 406412K reserved, 32768K cma-reserved)
10360 13:54:40.909650 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10361 13:54:40.916465 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10362 13:54:40.919711 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10363 13:54:40.926192 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10364 13:54:40.932799 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10365 13:54:40.936284 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10366 13:54:40.946338 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10367 13:54:40.952688 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10368 13:54:40.959635 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10369 13:54:40.965965 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10370 13:54:40.969360 <6>[ 0.000000] GICv3: 608 SPIs implemented
10371 13:54:40.972468 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10372 13:54:40.979234 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10373 13:54:40.982479 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10374 13:54:40.989208 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10375 13:54:41.002392 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10376 13:54:41.012391 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10377 13:54:41.022122 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10378 13:54:41.029724 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10379 13:54:41.042729 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10380 13:54:41.049252 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10381 13:54:41.055740 <6>[ 0.009184] Console: colour dummy device 80x25
10382 13:54:41.065760 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10383 13:54:41.072326 <6>[ 0.024419] pid_max: default: 32768 minimum: 301
10384 13:54:41.075800 <6>[ 0.029290] LSM: Security Framework initializing
10385 13:54:41.082499 <6>[ 0.034228] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 13:54:41.092250 <6>[ 0.042042] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10387 13:54:41.102116 <6>[ 0.051456] cblist_init_generic: Setting adjustable number of callback queues.
10388 13:54:41.105688 <6>[ 0.058900] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 13:54:41.115617 <6>[ 0.065277] cblist_init_generic: Setting adjustable number of callback queues.
10390 13:54:41.122299 <6>[ 0.072704] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 13:54:41.125349 <6>[ 0.079105] rcu: Hierarchical SRCU implementation.
10392 13:54:41.132131 <6>[ 0.084151] rcu: Max phase no-delay instances is 1000.
10393 13:54:41.138617 <6>[ 0.091169] EFI services will not be available.
10394 13:54:41.141753 <6>[ 0.096123] smp: Bringing up secondary CPUs ...
10395 13:54:41.150394 <6>[ 0.101174] Detected VIPT I-cache on CPU1
10396 13:54:41.156969 <6>[ 0.101242] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10397 13:54:41.163371 <6>[ 0.101273] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10398 13:54:41.166769 <6>[ 0.101606] Detected VIPT I-cache on CPU2
10399 13:54:41.173533 <6>[ 0.101655] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10400 13:54:41.183084 <6>[ 0.101671] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10401 13:54:41.186694 <6>[ 0.101925] Detected VIPT I-cache on CPU3
10402 13:54:41.193012 <6>[ 0.101970] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10403 13:54:41.199889 <6>[ 0.101984] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10404 13:54:41.203245 <6>[ 0.102290] CPU features: detected: Spectre-v4
10405 13:54:41.210142 <6>[ 0.102297] CPU features: detected: Spectre-BHB
10406 13:54:41.213204 <6>[ 0.102302] Detected PIPT I-cache on CPU4
10407 13:54:41.219741 <6>[ 0.102358] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10408 13:54:41.226538 <6>[ 0.102375] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10409 13:54:41.233009 <6>[ 0.102667] Detected PIPT I-cache on CPU5
10410 13:54:41.239867 <6>[ 0.102731] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10411 13:54:41.246128 <6>[ 0.102749] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10412 13:54:41.249454 <6>[ 0.103032] Detected PIPT I-cache on CPU6
10413 13:54:41.256093 <6>[ 0.103098] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10414 13:54:41.262652 <6>[ 0.103115] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10415 13:54:41.269321 <6>[ 0.103411] Detected PIPT I-cache on CPU7
10416 13:54:41.275780 <6>[ 0.103474] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10417 13:54:41.282279 <6>[ 0.103491] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10418 13:54:41.285759 <6>[ 0.103539] smp: Brought up 1 node, 8 CPUs
10419 13:54:41.292458 <6>[ 0.244957] SMP: Total of 8 processors activated.
10420 13:54:41.295758 <6>[ 0.249908] CPU features: detected: 32-bit EL0 Support
10421 13:54:41.305584 <6>[ 0.255304] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10422 13:54:41.312259 <6>[ 0.264105] CPU features: detected: Common not Private translations
10423 13:54:41.318944 <6>[ 0.270580] CPU features: detected: CRC32 instructions
10424 13:54:41.322429 <6>[ 0.275931] CPU features: detected: RCpc load-acquire (LDAPR)
10425 13:54:41.328710 <6>[ 0.281891] CPU features: detected: LSE atomic instructions
10426 13:54:41.335401 <6>[ 0.287673] CPU features: detected: Privileged Access Never
10427 13:54:41.342068 <6>[ 0.293452] CPU features: detected: RAS Extension Support
10428 13:54:41.348646 <6>[ 0.299095] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10429 13:54:41.352199 <6>[ 0.306316] CPU: All CPU(s) started at EL2
10430 13:54:41.358716 <6>[ 0.310633] alternatives: applying system-wide alternatives
10431 13:54:41.367951 <6>[ 0.321347] devtmpfs: initialized
10432 13:54:41.383626 <6>[ 0.330193] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10433 13:54:41.389876 <6>[ 0.340153] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10434 13:54:41.396471 <6>[ 0.348380] pinctrl core: initialized pinctrl subsystem
10435 13:54:41.399443 <6>[ 0.355008] DMI not present or invalid.
10436 13:54:41.406224 <6>[ 0.359421] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10437 13:54:41.415981 <6>[ 0.366286] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10438 13:54:41.422918 <6>[ 0.373870] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10439 13:54:41.433006 <6>[ 0.382099] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10440 13:54:41.436180 <6>[ 0.390339] audit: initializing netlink subsys (disabled)
10441 13:54:41.446270 <5>[ 0.396033] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10442 13:54:41.452883 <6>[ 0.396730] thermal_sys: Registered thermal governor 'step_wise'
10443 13:54:41.459723 <6>[ 0.404001] thermal_sys: Registered thermal governor 'power_allocator'
10444 13:54:41.462812 <6>[ 0.410256] cpuidle: using governor menu
10445 13:54:41.469573 <6>[ 0.421216] NET: Registered PF_QIPCRTR protocol family
10446 13:54:41.475977 <6>[ 0.426690] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10447 13:54:41.482943 <6>[ 0.433795] ASID allocator initialised with 32768 entries
10448 13:54:41.485970 <6>[ 0.440353] Serial: AMBA PL011 UART driver
10449 13:54:41.495854 <4>[ 0.449086] Trying to register duplicate clock ID: 134
10450 13:54:41.549711 <6>[ 0.506142] KASLR enabled
10451 13:54:41.563695 <6>[ 0.513807] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10452 13:54:41.570287 <6>[ 0.520821] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10453 13:54:41.577021 <6>[ 0.527311] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10454 13:54:41.583580 <6>[ 0.534317] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10455 13:54:41.590305 <6>[ 0.540807] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10456 13:54:41.597000 <6>[ 0.547809] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10457 13:54:41.603445 <6>[ 0.554293] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10458 13:54:41.609934 <6>[ 0.561297] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10459 13:54:41.613655 <6>[ 0.568754] ACPI: Interpreter disabled.
10460 13:54:41.622048 <6>[ 0.575179] iommu: Default domain type: Translated
10461 13:54:41.628237 <6>[ 0.580292] iommu: DMA domain TLB invalidation policy: strict mode
10462 13:54:41.631687 <5>[ 0.586948] SCSI subsystem initialized
10463 13:54:41.638456 <6>[ 0.591197] usbcore: registered new interface driver usbfs
10464 13:54:41.644834 <6>[ 0.596924] usbcore: registered new interface driver hub
10465 13:54:41.648331 <6>[ 0.602477] usbcore: registered new device driver usb
10466 13:54:41.655378 <6>[ 0.608591] pps_core: LinuxPPS API ver. 1 registered
10467 13:54:41.665423 <6>[ 0.613785] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10468 13:54:41.668560 <6>[ 0.623129] PTP clock support registered
10469 13:54:41.671711 <6>[ 0.627371] EDAC MC: Ver: 3.0.0
10470 13:54:41.679208 <6>[ 0.632553] FPGA manager framework
10471 13:54:41.685850 <6>[ 0.636229] Advanced Linux Sound Architecture Driver Initialized.
10472 13:54:41.689003 <6>[ 0.642941] vgaarb: loaded
10473 13:54:41.695967 <6>[ 0.646085] clocksource: Switched to clocksource arch_sys_counter
10474 13:54:41.699064 <5>[ 0.652531] VFS: Disk quotas dquot_6.6.0
10475 13:54:41.705565 <6>[ 0.656719] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10476 13:54:41.708970 <6>[ 0.663908] pnp: PnP ACPI: disabled
10477 13:54:41.717445 <6>[ 0.670579] NET: Registered PF_INET protocol family
10478 13:54:41.723909 <6>[ 0.675930] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10479 13:54:41.738168 <6>[ 0.688267] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10480 13:54:41.748004 <6>[ 0.697081] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10481 13:54:41.755071 <6>[ 0.705052] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10482 13:54:41.764733 <6>[ 0.713753] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10483 13:54:41.771261 <6>[ 0.723506] TCP: Hash tables configured (established 65536 bind 65536)
10484 13:54:41.778082 <6>[ 0.730378] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10485 13:54:41.788082 <6>[ 0.737579] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10486 13:54:41.794897 <6>[ 0.745286] NET: Registered PF_UNIX/PF_LOCAL protocol family
10487 13:54:41.800803 <6>[ 0.751431] RPC: Registered named UNIX socket transport module.
10488 13:54:41.804295 <6>[ 0.757585] RPC: Registered udp transport module.
10489 13:54:41.807655 <6>[ 0.762515] RPC: Registered tcp transport module.
10490 13:54:41.817539 <6>[ 0.767449] RPC: Registered tcp NFSv4.1 backchannel transport module.
10491 13:54:41.820693 <6>[ 0.774112] PCI: CLS 0 bytes, default 64
10492 13:54:41.824557 <6>[ 0.778449] Unpacking initramfs...
10493 13:54:41.848153 <6>[ 0.798198] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10494 13:54:41.858163 <6>[ 0.806863] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10495 13:54:41.861103 <6>[ 0.815720] kvm [1]: IPA Size Limit: 40 bits
10496 13:54:41.867960 <6>[ 0.820251] kvm [1]: GICv3: no GICV resource entry
10497 13:54:41.871250 <6>[ 0.825273] kvm [1]: disabling GICv2 emulation
10498 13:54:41.877889 <6>[ 0.829958] kvm [1]: GIC system register CPU interface enabled
10499 13:54:41.881315 <6>[ 0.836121] kvm [1]: vgic interrupt IRQ18
10500 13:54:41.887870 <6>[ 0.840473] kvm [1]: VHE mode initialized successfully
10501 13:54:41.894434 <5>[ 0.846947] Initialise system trusted keyrings
10502 13:54:41.900989 <6>[ 0.851791] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10503 13:54:41.908296 <6>[ 0.861706] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10504 13:54:41.915315 <5>[ 0.868076] NFS: Registering the id_resolver key type
10505 13:54:41.918323 <5>[ 0.873374] Key type id_resolver registered
10506 13:54:41.924993 <5>[ 0.877788] Key type id_legacy registered
10507 13:54:41.931747 <6>[ 0.882065] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10508 13:54:41.938383 <6>[ 0.888986] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10509 13:54:41.944903 <6>[ 0.896681] 9p: Installing v9fs 9p2000 file system support
10510 13:54:41.981288 <5>[ 0.934821] Key type asymmetric registered
10511 13:54:41.984704 <5>[ 0.939151] Asymmetric key parser 'x509' registered
10512 13:54:41.994883 <6>[ 0.944279] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10513 13:54:41.997946 <6>[ 0.951892] io scheduler mq-deadline registered
10514 13:54:42.000975 <6>[ 0.956655] io scheduler kyber registered
10515 13:54:42.020327 <6>[ 0.973542] EINJ: ACPI disabled.
10516 13:54:42.051950 <4>[ 0.998792] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 13:54:42.061933 <4>[ 1.009436] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10518 13:54:42.076621 <6>[ 1.029949] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10519 13:54:42.084218 <6>[ 1.037845] printk: console [ttyS0] disabled
10520 13:54:42.112799 <6>[ 1.062513] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10521 13:54:42.119012 <6>[ 1.071989] printk: console [ttyS0] enabled
10522 13:54:42.122352 <6>[ 1.071989] printk: console [ttyS0] enabled
10523 13:54:42.128897 <6>[ 1.080883] printk: bootconsole [mtk8250] disabled
10524 13:54:42.132424 <6>[ 1.080883] printk: bootconsole [mtk8250] disabled
10525 13:54:42.139064 <6>[ 1.091893] SuperH (H)SCI(F) driver initialized
10526 13:54:42.142061 <6>[ 1.097153] msm_serial: driver initialized
10527 13:54:42.156089 <6>[ 1.106082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10528 13:54:42.166004 <6>[ 1.114626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10529 13:54:42.172748 <6>[ 1.123170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10530 13:54:42.182679 <6>[ 1.131801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10531 13:54:42.192378 <6>[ 1.140510] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10532 13:54:42.199006 <6>[ 1.149229] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10533 13:54:42.209333 <6>[ 1.157771] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10534 13:54:42.215725 <6>[ 1.166563] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10535 13:54:42.225394 <6>[ 1.175108] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10536 13:54:42.237094 <6>[ 1.190599] loop: module loaded
10537 13:54:42.243972 <6>[ 1.196472] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10538 13:54:42.266325 <4>[ 1.219646] mtk-pmic-keys: Failed to locate of_node [id: -1]
10539 13:54:42.273193 <6>[ 1.226455] megasas: 07.719.03.00-rc1
10540 13:54:42.282434 <6>[ 1.235994] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10541 13:54:42.292324 <6>[ 1.245457] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10542 13:54:42.308831 <6>[ 1.262128] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10543 13:54:42.365197 <6>[ 1.312039] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10544 13:54:42.730757 <6>[ 1.684255] Freeing initrd memory: 20896K
10545 13:54:42.746332 <6>[ 1.699895] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10546 13:54:42.757426 <6>[ 1.710777] tun: Universal TUN/TAP device driver, 1.6
10547 13:54:42.760696 <6>[ 1.716830] thunder_xcv, ver 1.0
10548 13:54:42.764169 <6>[ 1.720333] thunder_bgx, ver 1.0
10549 13:54:42.767230 <6>[ 1.723829] nicpf, ver 1.0
10550 13:54:42.777761 <6>[ 1.727837] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10551 13:54:42.781039 <6>[ 1.735312] hns3: Copyright (c) 2017 Huawei Corporation.
10552 13:54:42.787945 <6>[ 1.740898] hclge is initializing
10553 13:54:42.791022 <6>[ 1.744476] e1000: Intel(R) PRO/1000 Network Driver
10554 13:54:42.797668 <6>[ 1.749605] e1000: Copyright (c) 1999-2006 Intel Corporation.
10555 13:54:42.800936 <6>[ 1.755617] e1000e: Intel(R) PRO/1000 Network Driver
10556 13:54:42.807609 <6>[ 1.760833] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10557 13:54:42.814447 <6>[ 1.767021] igb: Intel(R) Gigabit Ethernet Network Driver
10558 13:54:42.820865 <6>[ 1.772672] igb: Copyright (c) 2007-2014 Intel Corporation.
10559 13:54:42.827867 <6>[ 1.778507] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10560 13:54:42.834401 <6>[ 1.785025] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10561 13:54:42.837431 <6>[ 1.791489] sky2: driver version 1.30
10562 13:54:42.844167 <6>[ 1.796471] VFIO - User Level meta-driver version: 0.3
10563 13:54:42.851238 <6>[ 1.804727] usbcore: registered new interface driver usb-storage
10564 13:54:42.858097 <6>[ 1.811171] usbcore: registered new device driver onboard-usb-hub
10565 13:54:42.867017 <6>[ 1.820316] mt6397-rtc mt6359-rtc: registered as rtc0
10566 13:54:42.876998 <6>[ 1.825791] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:54:44 UTC (1706795684)
10567 13:54:42.880402 <6>[ 1.835389] i2c_dev: i2c /dev entries driver
10568 13:54:42.896808 <6>[ 1.847070] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10569 13:54:42.916769 <6>[ 1.870047] cpu cpu0: EM: created perf domain
10570 13:54:42.920025 <6>[ 1.874997] cpu cpu4: EM: created perf domain
10571 13:54:42.927063 <6>[ 1.880551] sdhci: Secure Digital Host Controller Interface driver
10572 13:54:42.933835 <6>[ 1.886985] sdhci: Copyright(c) Pierre Ossman
10573 13:54:42.940445 <6>[ 1.891944] Synopsys Designware Multimedia Card Interface Driver
10574 13:54:42.946961 <6>[ 1.898577] sdhci-pltfm: SDHCI platform and OF driver helper
10575 13:54:42.950101 <6>[ 1.898613] mmc0: CQHCI version 5.10
10576 13:54:42.956911 <6>[ 1.908807] ledtrig-cpu: registered to indicate activity on CPUs
10577 13:54:42.963733 <6>[ 1.915820] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10578 13:54:42.970082 <6>[ 1.922876] usbcore: registered new interface driver usbhid
10579 13:54:42.973754 <6>[ 1.928699] usbhid: USB HID core driver
10580 13:54:42.979883 <6>[ 1.932873] spi_master spi0: will run message pump with realtime priority
10581 13:54:43.024878 <6>[ 1.971636] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10582 13:54:43.040572 <6>[ 1.987065] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10583 13:54:43.049454 <6>[ 2.002812] cros-ec-spi spi0.0: Chrome EC device registered
10584 13:54:43.056372 <6>[ 2.008938] mmc0: Command Queue Engine enabled
10585 13:54:43.062932 <6>[ 2.013714] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10586 13:54:43.066403 <6>[ 2.021570] mmcblk0: mmc0:0001 DA4128 116 GiB
10587 13:54:43.076417 <6>[ 2.022437] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10588 13:54:43.083119 <6>[ 2.034629] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10589 13:54:43.089631 <6>[ 2.036697] NET: Registered PF_PACKET protocol family
10590 13:54:43.093129 <6>[ 2.042489] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10591 13:54:43.099888 <6>[ 2.046912] 9pnet: Installing 9P2000 support
10592 13:54:43.102809 <6>[ 2.052762] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10593 13:54:43.106373 <5>[ 2.056586] Key type dns_resolver registered
10594 13:54:43.112899 <6>[ 2.062388] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10595 13:54:43.119445 <6>[ 2.066762] registered taskstats version 1
10596 13:54:43.122965 <5>[ 2.077195] Loading compiled-in X.509 certificates
10597 13:54:43.152271 <4>[ 2.099123] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 13:54:43.162128 <4>[ 2.109810] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 13:54:43.169042 <3>[ 2.120337] debugfs: File 'uA_load' in directory '/' already present!
10600 13:54:43.175638 <3>[ 2.127037] debugfs: File 'min_uV' in directory '/' already present!
10601 13:54:43.182323 <3>[ 2.133645] debugfs: File 'max_uV' in directory '/' already present!
10602 13:54:43.188583 <3>[ 2.140307] debugfs: File 'constraint_flags' in directory '/' already present!
10603 13:54:43.199402 <3>[ 2.149603] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10604 13:54:43.209107 <6>[ 2.162625] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10605 13:54:43.216063 <6>[ 2.169472] xhci-mtk 11200000.usb: xHCI Host Controller
10606 13:54:43.222646 <6>[ 2.174968] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10607 13:54:43.232618 <6>[ 2.182823] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10608 13:54:43.239609 <6>[ 2.192257] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10609 13:54:43.246051 <6>[ 2.198331] xhci-mtk 11200000.usb: xHCI Host Controller
10610 13:54:43.252787 <6>[ 2.203807] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10611 13:54:43.259175 <6>[ 2.211457] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10612 13:54:43.266203 <6>[ 2.219124] hub 1-0:1.0: USB hub found
10613 13:54:43.269190 <6>[ 2.223140] hub 1-0:1.0: 1 port detected
10614 13:54:43.275982 <6>[ 2.227420] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10615 13:54:43.282696 <6>[ 2.236009] hub 2-0:1.0: USB hub found
10616 13:54:43.286026 <6>[ 2.240016] hub 2-0:1.0: 1 port detected
10617 13:54:43.294632 <6>[ 2.248101] mtk-msdc 11f70000.mmc: Got CD GPIO
10618 13:54:43.305815 <6>[ 2.255858] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10619 13:54:43.312497 <6>[ 2.263907] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10620 13:54:43.322437 <4>[ 2.271827] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10621 13:54:43.332610 <6>[ 2.281354] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10622 13:54:43.339198 <6>[ 2.289434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10623 13:54:43.346107 <6>[ 2.297513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10624 13:54:43.355875 <6>[ 2.305514] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10625 13:54:43.362411 <6>[ 2.313334] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10626 13:54:43.372402 <6>[ 2.321165] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10627 13:54:43.382787 <6>[ 2.331682] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10628 13:54:43.388785 <6>[ 2.340096] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10629 13:54:43.398761 <6>[ 2.348439] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10630 13:54:43.405451 <6>[ 2.356789] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10631 13:54:43.415329 <6>[ 2.365129] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10632 13:54:43.422158 <6>[ 2.373482] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10633 13:54:43.431724 <6>[ 2.381824] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10634 13:54:43.438317 <6>[ 2.390179] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10635 13:54:43.448312 <6>[ 2.398519] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10636 13:54:43.458203 <6>[ 2.406867] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10637 13:54:43.464935 <6>[ 2.415207] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10638 13:54:43.475076 <6>[ 2.423545] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10639 13:54:43.481534 <6>[ 2.431885] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10640 13:54:43.491452 <6>[ 2.440223] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10641 13:54:43.498323 <6>[ 2.448562] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10642 13:54:43.504666 <6>[ 2.457407] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10643 13:54:43.511514 <6>[ 2.464728] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10644 13:54:43.518131 <6>[ 2.471694] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10645 13:54:43.528217 <6>[ 2.478628] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10646 13:54:43.534899 <6>[ 2.485704] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10647 13:54:43.541414 <6>[ 2.492567] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10648 13:54:43.551558 <6>[ 2.501696] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10649 13:54:43.561585 <6>[ 2.510815] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10650 13:54:43.571494 <6>[ 2.520135] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10651 13:54:43.581879 <6>[ 2.529606] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10652 13:54:43.591310 <6>[ 2.539077] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10653 13:54:43.597798 <6>[ 2.548196] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10654 13:54:43.607892 <6>[ 2.557660] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10655 13:54:43.617791 <6>[ 2.566779] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10656 13:54:43.627653 <6>[ 2.576072] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10657 13:54:43.637361 <6>[ 2.586235] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10658 13:54:43.647639 <6>[ 2.597734] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10659 13:54:43.676344 <6>[ 2.626555] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10660 13:54:43.704905 <6>[ 2.658161] hub 2-1:1.0: USB hub found
10661 13:54:43.707991 <6>[ 2.662643] hub 2-1:1.0: 3 ports detected
10662 13:54:43.716934 <6>[ 2.669958] hub 2-1:1.0: USB hub found
10663 13:54:43.720049 <6>[ 2.674317] hub 2-1:1.0: 3 ports detected
10664 13:54:43.824883 <6>[ 2.778293] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10665 13:54:43.983183 <6>[ 2.936439] hub 1-1:1.0: USB hub found
10666 13:54:43.986134 <6>[ 2.940948] hub 1-1:1.0: 4 ports detected
10667 13:54:43.996306 <6>[ 2.949669] hub 1-1:1.0: USB hub found
10668 13:54:43.999823 <6>[ 2.954040] hub 1-1:1.0: 4 ports detected
10669 13:54:44.060691 <6>[ 3.010699] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10670 13:54:44.320284 <6>[ 3.270400] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10671 13:54:44.453088 <6>[ 3.406208] hub 1-1.4:1.0: USB hub found
10672 13:54:44.455903 <6>[ 3.410868] hub 1-1.4:1.0: 2 ports detected
10673 13:54:44.466421 <6>[ 3.419769] hub 1-1.4:1.0: USB hub found
10674 13:54:44.469817 <6>[ 3.424393] hub 1-1.4:1.0: 2 ports detected
10675 13:54:44.768396 <6>[ 3.718367] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10676 13:54:44.960248 <6>[ 3.910349] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10677 13:54:55.937086 <6>[ 14.895367] ALSA device list:
10678 13:54:55.943458 <6>[ 14.898662] No soundcards found.
10679 13:54:55.951239 <6>[ 14.906600] Freeing unused kernel memory: 8448K
10680 13:54:55.954532 <6>[ 14.911588] Run /init as init process
10681 13:54:55.992921 Starting syslogd: OK
10682 13:54:55.997022 Starting klogd: OK
10683 13:54:56.003180 Running sysctl: OK
10684 13:54:56.012998 Populating /dev using udev: <30>[ 14.967071] udevd[185]: starting version 3.2.9
10685 13:54:56.021470 <27>[ 14.976027] udevd[185]: specified user 'tss' unknown
10686 13:54:56.028147 <27>[ 14.981430] udevd[185]: specified group 'tss' unknown
10687 13:54:56.031779 <30>[ 14.988042] udevd[186]: starting eudev-3.2.9
10688 13:54:56.052945 <27>[ 15.008046] udevd[186]: specified user 'tss' unknown
10689 13:54:56.059735 <27>[ 15.013462] udevd[186]: specified group 'tss' unknown
10690 13:54:56.181303 <6>[ 15.132591] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10691 13:54:56.196477 <6>[ 15.148047] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10692 13:54:56.207834 <6>[ 15.159181] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10693 13:54:56.221995 <6>[ 15.173332] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10694 13:54:56.235883 <6>[ 15.190764] remoteproc remoteproc0: scp is available
10695 13:54:56.242577 <6>[ 15.196189] remoteproc remoteproc0: powering up scp
10696 13:54:56.248941 <6>[ 15.201664] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10697 13:54:56.255527 <6>[ 15.202019] mc: Linux media interface: v0.10
10698 13:54:56.259026 <6>[ 15.210303] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10699 13:54:56.265745 <6>[ 15.211024] usbcore: registered new device driver r8152-cfgselector
10700 13:54:56.275628 <3>[ 15.222672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 13:54:56.282533 <4>[ 15.222959] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10702 13:54:56.288842 <4>[ 15.223087] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10703 13:54:56.295620 <6>[ 15.236831] videodev: Linux video capture interface: v2.00
10704 13:54:56.301828 <6>[ 15.239078] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10705 13:54:56.312198 <3>[ 15.242403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 13:54:56.318616 <3>[ 15.271237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 13:54:56.328517 <3>[ 15.279724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 13:54:56.335313 <3>[ 15.287842] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 13:54:56.344901 <3>[ 15.295983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 13:54:56.351820 <6>[ 15.296055] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10711 13:54:56.358324 <6>[ 15.298427] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10712 13:54:56.368173 <3>[ 15.304137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 13:54:56.375300 <6>[ 15.311143] pci_bus 0000:00: root bus resource [bus 00-ff]
10714 13:54:56.381649 <3>[ 15.319377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 13:54:56.391524 <4>[ 15.325710] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10716 13:54:56.398169 <4>[ 15.325721] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10717 13:54:56.404572 <6>[ 15.327479] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10718 13:54:56.414594 <3>[ 15.333272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 13:54:56.424077 <6>[ 15.334409] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10720 13:54:56.434335 <6>[ 15.341279] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10721 13:54:56.440603 <6>[ 15.341319] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10722 13:54:56.447248 <3>[ 15.350361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 13:54:56.457388 <6>[ 15.352220] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10724 13:54:56.460733 <6>[ 15.352229] remoteproc remoteproc0: remote processor scp is now up
10725 13:54:56.470673 <6>[ 15.352230] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10726 13:54:56.477298 <6>[ 15.358419] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10727 13:54:56.483668 <3>[ 15.365545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 13:54:56.493521 <6>[ 15.370957] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10729 13:54:56.503622 <6>[ 15.371467] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10730 13:54:56.506858 <6>[ 15.374526] pci 0000:00:00.0: supports D1 D2
10731 13:54:56.517232 <3>[ 15.383013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 13:54:56.524008 <6>[ 15.392913] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10733 13:54:56.527191 <6>[ 15.393006] r8152 2-1.3:1.0 eth0: v1.12.13
10734 13:54:56.534409 <6>[ 15.393130] usbcore: registered new interface driver r8152
10735 13:54:56.541320 <3>[ 15.399292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 13:54:56.544371 <6>[ 15.402577] Bluetooth: Core ver 2.22
10737 13:54:56.551040 <6>[ 15.402625] NET: Registered PF_BLUETOOTH protocol family
10738 13:54:56.557670 <6>[ 15.402626] Bluetooth: HCI device and connection manager initialized
10739 13:54:56.564237 <6>[ 15.402641] Bluetooth: HCI socket layer initialized
10740 13:54:56.567663 <6>[ 15.402645] Bluetooth: L2CAP socket layer initialized
10741 13:54:56.574051 <6>[ 15.402652] Bluetooth: SCO socket layer initialized
10742 13:54:56.580583 <6>[ 15.407615] usbcore: registered new interface driver cdc_ether
10743 13:54:56.587901 <6>[ 15.409321] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10744 13:54:56.594193 <6>[ 15.409452] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10745 13:54:56.600933 <6>[ 15.409485] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10746 13:54:56.607142 <6>[ 15.409506] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10747 13:54:56.617142 <6>[ 15.409525] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10748 13:54:56.620423 <6>[ 15.409645] pci 0000:01:00.0: supports D1 D2
10749 13:54:56.627502 <6>[ 15.409648] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10750 13:54:56.636925 <3>[ 15.415831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 13:54:56.643741 <6>[ 15.416762] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10752 13:54:56.653641 <6>[ 15.417903] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10753 13:54:56.660180 <6>[ 15.418049] usbcore: registered new interface driver uvcvideo
10754 13:54:56.666924 <6>[ 15.426231] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10755 13:54:56.676577 <6>[ 15.429357] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10756 13:54:56.683150 <3>[ 15.429364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 13:54:56.693240 <3>[ 15.429377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 13:54:56.699958 <3>[ 15.429385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 13:54:56.709805 <3>[ 15.429445] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 13:54:56.716896 <6>[ 15.436841] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10761 13:54:56.723234 <6>[ 15.437225] usbcore: registered new interface driver r8153_ecm
10762 13:54:56.733563 <4>[ 15.443868] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10763 13:54:56.736683 <4>[ 15.443868] Fallback method does not support PEC.
10764 13:54:56.743089 <6>[ 15.455842] usbcore: registered new interface driver btusb
10765 13:54:56.749401 <6>[ 15.464013] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10766 13:54:56.759302 <6>[ 15.464025] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10767 13:54:56.765822 <6>[ 15.464038] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10768 13:54:56.772319 <6>[ 15.464052] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10769 13:54:56.779271 <6>[ 15.464063] pci 0000:00:00.0: PCI bridge to [bus 01]
10770 13:54:56.785723 <6>[ 15.464599] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10771 13:54:56.795794 <4>[ 15.468993] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10772 13:54:56.805465 <6>[ 15.471520] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10773 13:54:56.812035 <6>[ 15.476664] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10774 13:54:56.818787 <6>[ 15.476811] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10775 13:54:56.828357 <3>[ 15.477988] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10776 13:54:56.835153 <3>[ 15.483566] Bluetooth: hci0: Failed to load firmware file (-2)
10777 13:54:56.838597 <6>[ 15.488376] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10778 13:54:56.845123 <3>[ 15.493659] Bluetooth: hci0: Failed to set up firmware (-2)
10779 13:54:56.854974 <3>[ 15.498545] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10780 13:54:56.861807 <6>[ 15.502091] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10781 13:54:56.871735 <4>[ 15.505620] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10782 13:54:56.878421 <5>[ 15.530948] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10783 13:54:56.913701 <5>[ 15.865156] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10784 13:54:56.919776 <5>[ 15.872255] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10785 13:54:56.930069 <4>[ 15.880663] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10786 13:54:56.933213 <6>[ 15.889555] cfg80211: failed to load regulatory.db
10787 13:54:56.975649 <6>[ 15.927114] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10788 13:54:56.982127 <6>[ 15.934611] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10789 13:54:57.006145 <6>[ 15.961275] mt7921e 0000:01:00.0: ASIC revision: 79610010
10790 13:54:57.110140 <6>[ 16.061840] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10791 13:54:57.113516 <6>[ 16.061840]
10792 13:54:57.113945 done
10793 13:54:57.124321 Saving random seed: OK
10794 13:54:57.140645 Starting network: OK
10795 13:54:57.172744 Starting dropbear sshd: <6>[ 16.127972] NET: Registered PF_INET6 protocol family
10796 13:54:57.175950 <6>[ 16.133963] Segment Routing with IPv6
10797 13:54:57.182732 <6>[ 16.137913] In-situ OAM (IOAM) with IPv6
10798 13:54:57.183157 OK
10799 13:54:57.194566 /bin/sh: can't access tty; job control turned off
10800 13:54:57.196161 Matched prompt #10: / #
10802 13:54:57.197843 Setting prompt string to ['/ #']
10803 13:54:57.198506 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10805 13:54:57.200146 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10806 13:54:57.200849 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
10807 13:54:57.201445 Setting prompt string to ['/ #']
10808 13:54:57.201981 Forcing a shell prompt, looking for ['/ #']
10810 13:54:57.253112 / #
10811 13:54:57.253491 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10812 13:54:57.253751 Waiting using forced prompt support (timeout 00:02:30)
10813 13:54:57.259031
10814 13:54:57.259720 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10815 13:54:57.260039 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
10816 13:54:57.260347 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10817 13:54:57.260645 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
10818 13:54:57.260931 end: 2 depthcharge-action (duration 00:01:36) [common]
10819 13:54:57.261220 start: 3 lava-test-retry (timeout 00:01:00) [common]
10820 13:54:57.261524 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10821 13:54:57.261777 Using namespace: common
10823 13:54:57.362638 / # #
10824 13:54:57.363203 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10825 13:54:57.368460 #
10826 13:54:57.369223 Using /lava-12682925
10828 13:54:57.470665 / # export SHELL=/bin/sh
10829 13:54:57.471621 <6>[ 16.330511] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10830 13:54:57.477099 export SHELL=/bin/sh
10832 13:54:57.578668 / # . /lava-12682925/environment
10833 13:54:57.584569 . /lava-12682925/environment
10835 13:54:57.686321 / # /lava-12682925/bin/lava-test-runner /lava-12682925/0
10836 13:54:57.686874 Test shell timeout: 10s (minimum of the action and connection timeout)
10837 13:54:57.692647 /lava-12682925/bin/lava-test-runner /lava-12682925/0
10838 13:54:57.712017 + export 'TESTRUN_ID=0_dmesg'
10839 13:54:57.718991 + c<8>[ 16.672757] <LAVA_SIGNAL_STARTRUN 0_dmesg 12682925_1.5.2.3.1>
10840 13:54:57.719687 Received signal: <STARTRUN> 0_dmesg 12682925_1.5.2.3.1
10841 13:54:57.720068 Starting test lava.0_dmesg (12682925_1.5.2.3.1)
10842 13:54:57.720470 Skipping test definition patterns.
10843 13:54:57.722215 d /lava-12682925/0/tests/0_dmesg
10844 13:54:57.722629 + cat uuid
10845 13:54:57.725359 + UUID=12682925_1.5.2.3.1
10846 13:54:57.725822 + set +x
10847 13:54:57.731892 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10848 13:54:57.738774 <8>[ 16.691367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10849 13:54:57.739571 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10851 13:54:57.758592 <8>[ 16.710618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10852 13:54:57.759349 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10854 13:54:57.777513 <8>[ 16.729439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10855 13:54:57.778194 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10857 13:54:57.780749 + set +x
10858 13:54:57.784293 <8>[ 16.738948] <LAVA_SIGNAL_ENDRUN 0_dmesg 12682925_1.5.2.3.1>
10859 13:54:57.784971 Received signal: <ENDRUN> 0_dmesg 12682925_1.5.2.3.1
10860 13:54:57.785374 Ending use of test pattern.
10861 13:54:57.785731 Ending test lava.0_dmesg (12682925_1.5.2.3.1), duration 0.07
10863 13:54:57.787995 <LAVA_TEST_RUNNER EXIT>
10864 13:54:57.788672 ok: lava_test_shell seems to have completed
10865 13:54:57.789192 alert: pass
crit: pass
emerg: pass
10866 13:54:57.789621 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10867 13:54:57.790041 end: 3 lava-test-retry (duration 00:00:01) [common]
10868 13:54:57.790454 start: 4 lava-test-retry (timeout 00:01:00) [common]
10869 13:54:57.790867 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10870 13:54:57.791192 Using namespace: common
10872 13:54:57.892281 / # #
10873 13:54:57.892873 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10874 13:54:57.893421 Using /lava-12682925
10876 13:54:57.994582 export SHELL=/bin/sh
10877 13:54:57.995343 #
10879 13:54:58.096958 / # export SHELL=/bin/sh. /lava-12682925/environment
10880 13:54:58.097743
10882 13:54:58.199316 / # . /lava-12682925/environment/lava-12682925/bin/lava-test-runner /lava-12682925/1
10883 13:54:58.199917 Test shell timeout: 10s (minimum of the action and connection timeout)
10884 13:54:58.200457
10885 13:54:58.205447 / # /lava-12682925/bin/lava-test-runner /lava-12682925/1
10886 13:54:58.222043 <6>[ 17.176848] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10887 13:54:58.236421 + export 'TESTRU<8>[ 17.189256] <LAVA_SIGNAL_STARTRUN 1_bootrr 12682925_1.5.2.3.5>
10888 13:54:58.236960 N_ID=1_bootrr'
10889 13:54:58.237596 Received signal: <STARTRUN> 1_bootrr 12682925_1.5.2.3.5
10890 13:54:58.238027 Starting test lava.1_bootrr (12682925_1.5.2.3.5)
10891 13:54:58.238419 Skipping test definition patterns.
10892 13:54:58.239815 + cd /lava-12682925/1/tests/1_bootrr
10893 13:54:58.240368 + cat uuid
10894 13:54:58.243003 + UUID=12682925_1.5.2.3.5
10895 13:54:58.243429 + set +x
10896 13:54:58.259444 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12682925/1/../bin:/sbin:/usr/sbin<8>[ 17.211764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10897 13:54:58.260231 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10899 13:54:58.262730 :/bin:/usr/bin'
10900 13:54:58.263253 + cd /opt/bootrr/libexec/bootrr
10901 13:54:58.265990 + sh helpers/bootrr-auto
10902 13:54:58.269171 /lava-12682925/1/../bin/lava-test-case
10903 13:54:58.279241 /lava-126829<8>[ 17.230053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10904 13:54:58.280053 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10906 13:54:58.282176 25/1/../bin/lava-test-case
10907 13:54:58.282609 /usr/bin/tpm2_getcap
10908 13:54:58.318246 /lava-12682925/1/../bin/lava-test-case
10909 13:54:58.324671 <8>[ 17.277701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10910 13:54:58.325532 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10912 13:54:58.343688 /lava-12682925/1/../bin/lava-test-case
10913 13:54:58.350202 <8>[ 17.302125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10914 13:54:58.351070 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10916 13:54:58.360630 /lava-12682925/1/../bin/lava-test-case
10917 13:54:58.366544 <8>[ 17.319541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10918 13:54:58.366826 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10920 13:54:58.378197 /lava-12682925/1/../bin/lava-test-case
10921 13:54:58.384856 <8>[ 17.336950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10922 13:54:58.385123 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10924 13:54:58.395843 /lava-12682925/1/../bin/lava-test-case
10925 13:54:58.402378 <8>[ 17.354820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10926 13:54:58.402730 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10928 13:54:58.414206 /lava-12682925/1/../bin/lava-test-case
10929 13:54:58.424113 <8>[ 17.374700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10930 13:54:58.424985 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10932 13:54:58.432109 /lava-12682925/1/../bin/lava-test-case
10933 13:54:58.438727 <8>[ 17.391702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10934 13:54:58.439564 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10936 13:54:58.452166 /lava-12682925/1/../bin/lava-test-case
10937 13:54:58.458331 <8>[ 17.410783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10938 13:54:58.458610 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10940 13:54:58.467765 /lava-12682925/1/../bin/lava-test-case
10941 13:54:58.474269 <8>[ 17.426734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10942 13:54:58.474571 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10944 13:54:58.485594 /lava-12682925/1/../bin/lava-test-case
10945 13:54:58.492288 <8>[ 17.445410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10946 13:54:58.492714 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10948 13:54:58.504992 /lava-12682925/1/../bin/lava-test-case
10949 13:54:58.511721 <8>[ 17.464099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10950 13:54:58.512339 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10952 13:54:58.524104 /lava-12682925/1/../bin/lava-test-case
10953 13:54:58.531143 <8>[ 17.482605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10954 13:54:58.532253 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10956 13:54:58.547521 /lava-12682925/1/../bin/lava-test-case
10957 13:54:58.553979 <8>[ 17.505509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10958 13:54:58.554701 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10960 13:54:58.570942 /lava-12682925/1/../bin/lava-tes<8>[ 17.522223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10961 13:54:58.571536 t-case
10962 13:54:58.572186 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10964 13:54:58.585054 /lava-12682925/1/../bin/lava-test-case
10965 13:54:58.591474 <8>[ 17.545480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10966 13:54:58.592178 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10968 13:54:58.601779 /lava-12682925/1/../bin/lava-test-case
10969 13:54:58.608633 <8>[ 17.559996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10970 13:54:58.609354 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10972 13:54:58.622918 /lava-12682925/1/../bin/lava-test-case
10973 13:54:58.629331 <8>[ 17.581030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10974 13:54:58.630082 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10976 13:54:58.646091 /lava-12682925/1/../bin/lava-tes<8>[ 17.597219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10977 13:54:58.646539 t-case
10978 13:54:58.647250 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10980 13:54:58.661181 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10982 13:54:58.663663 /lava-12682925/1/../bin/lava-tes<8>[ 17.615511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10983 13:54:58.663748 t-case
10984 13:54:58.674020 /lava-12682925/1/../bin/lava-test-case
10985 13:54:58.680233 <8>[ 17.632292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10986 13:54:58.680512 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10988 13:54:58.698852 /lava-12682925/1/../bin/lava-tes<8>[ 17.650587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10989 13:54:58.698936 t-case
10990 13:54:58.699172 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10992 13:54:58.709211 /lava-12682925/1/../bin/lava-test-case
10993 13:54:58.715858 <8>[ 17.667520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10994 13:54:58.716263 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10996 13:54:58.729699 /lava-12682925/1/../bin/lava-test-case
10997 13:54:58.736440 <8>[ 17.688102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10998 13:54:58.736869 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11000 13:54:58.755142 /lava-12682925/1/../bin/lava-tes<8>[ 17.706547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11001 13:54:58.755451 t-case
11002 13:54:58.755940 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11004 13:54:58.765529 /lava-12682925/1/../bin/lava-test-case
11005 13:54:58.771899 <8>[ 17.724614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11006 13:54:58.772587 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11008 13:54:58.784709 /lava-12682925/1/../bin/lava-test-case
11009 13:54:58.791336 <8>[ 17.742589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11010 13:54:58.792204 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11012 13:54:58.802698 /lava-12682925/1/../bin/lava-test-case
11013 13:54:58.809422 <8>[ 17.762302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11014 13:54:58.810266 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11016 13:54:58.828833 /lava-12682925/1/../bin/lava-tes<8>[ 17.779812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11017 13:54:58.829367 t-case
11018 13:54:58.830032 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11020 13:54:58.840256 /lava-12682925/1/../bin/lava-test-case
11021 13:54:58.847090 <8>[ 17.798793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11022 13:54:58.847902 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11024 13:54:58.858902 /lava-12682925/1/../bin/lava-test-case
11025 13:54:58.865133 <8>[ 17.817496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11026 13:54:58.865388 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11028 13:54:58.875783 /lava-12682925/1/../bin/lava-test-case
11029 13:54:58.882076 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11031 13:54:58.885047 <8>[ 17.836253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11032 13:54:58.893641 /lava-12682925/1/../bin/lava-test-case
11033 13:54:58.900242 <8>[ 17.852574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11034 13:54:58.900513 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11036 13:54:58.913368 /lava-12682925/1/../bin/lava-test-case
11037 13:54:58.920131 <8>[ 17.871829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11038 13:54:58.920453 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11040 13:54:58.939783 /lava-12682925/1/../bin/lava-tes<8>[ 17.891344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11041 13:54:58.940035 t-case
11042 13:54:58.940439 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11044 13:54:58.956923 /lava-12682925/1/../bin/lava-tes<8>[ 17.908310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11045 13:54:58.957324 t-case
11046 13:54:58.957932 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11048 13:54:58.970323 /lava-12682925/1/../bin/lava-test-case
11049 13:54:58.976840 <8>[ 17.928575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11050 13:54:58.977564 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11052 13:54:58.994464 /lava-12682925/1/../bin/lava-tes<8>[ 17.945798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11053 13:54:58.995115 t-case
11054 13:54:58.996009 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11056 13:54:59.006287 /lava-12682925/1/../bin/lava-test-case
11057 13:54:59.012958 <8>[ 17.964719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11058 13:54:59.013830 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11060 13:54:59.029112 /lava-12682925/1/../bin/lava-tes<8>[ 17.980593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11061 13:54:59.029740 t-case
11062 13:54:59.030404 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11064 13:54:59.047911 /lava-12682925/1/../bin/lava-tes<8>[ 17.999103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11065 13:54:59.048512 t-case
11066 13:54:59.049086 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11068 13:54:59.063833 /lava-12682925/1/../bin/lava-tes<8>[ 18.015259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11069 13:54:59.064132 t-case
11070 13:54:59.064631 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11072 13:54:59.077608 /lava-12682925/1/../bin/lava-test-case
11073 13:54:59.084133 <8>[ 18.035876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11074 13:54:59.084503 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11076 13:54:59.101779 /lava-12682925/1/../bin/lava-tes<8>[ 18.053457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11077 13:54:59.101888 t-case
11078 13:54:59.102128 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11080 13:54:59.111791 /lava-12682925/1/../bin/lava-test-case
11081 13:54:59.118519 <8>[ 18.072220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11082 13:54:59.119248 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11084 13:54:59.129835 /lava-12682925/1/../bin/lava-test-case
11085 13:54:59.136368 <8>[ 18.088104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11086 13:54:59.137044 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11088 13:54:59.148010 /lava-12682925/1/../bin/lava-test-case
11089 13:54:59.154785 <8>[ 18.106822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11090 13:54:59.155520 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11092 13:54:59.162201 /lava-12682925/1/../bin/lava-test-case
11093 13:54:59.168897 <8>[ 18.120489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11094 13:54:59.169617 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11096 13:54:59.191220 /lava-12682925/1/../bin/lava-tes<8>[ 18.142721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11097 13:54:59.191732 t-case
11098 13:54:59.192319 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11100 13:54:59.200935 /lava-12682925/1/../bin/lava-test-case
11101 13:54:59.207272 <8>[ 18.160692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11102 13:54:59.207958 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11104 13:54:59.218311 /lava-12682925/1/../bin/lava-test-case
11105 13:54:59.224620 <8>[ 18.176764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11106 13:54:59.225341 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11108 13:54:59.235361 /lava-12682925/1/../bin/lava-test-case
11109 13:54:59.241916 <8>[ 18.193645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11110 13:54:59.242613 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11112 13:54:59.253016 /lava-12682925/1/../bin/lava-test-case
11113 13:54:59.259800 <8>[ 18.212246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11114 13:54:59.260499 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11116 13:54:59.270922 /lava-12682925/1/../bin/lava-test-case
11117 13:54:59.277239 <8>[ 18.228822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11118 13:54:59.277972 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11120 13:54:59.290108 /lava-12682925/1/../bin/lava-test-case
11121 13:54:59.296577 <8>[ 18.249921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11122 13:54:59.297263 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11124 13:54:59.307750 /lava-12682925/1/../bin/lava-test-case
11125 13:54:59.314142 <8>[ 18.266546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11126 13:54:59.314847 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11128 13:54:59.327067 /lava-12682925/1/../bin/lava-test-case
11129 13:54:59.333757 <8>[ 18.285215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11130 13:54:59.334466 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11132 13:54:59.352710 /lava-12682925/1/../bin/lava-tes<8>[ 18.304227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11133 13:54:59.353129 t-case
11134 13:54:59.353785 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11136 13:54:59.360068 /lava-12682925/1/../bin/lava-test-case
11137 13:54:59.366750 <8>[ 18.320797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11138 13:54:59.367426 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11140 13:54:59.381063 /lava-12682925/1/../bin/lava-test-case
11141 13:54:59.387780 <8>[ 18.339317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11142 13:54:59.388450 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11144 13:54:59.401579 /lava-12682925/1/../bin/lava-test-case
11145 13:54:59.408351 <8>[ 18.361012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11146 13:54:59.409024 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11148 13:54:59.418563 /lava-12682925/1/../bin/lava-test-case
11149 13:54:59.424928 <8>[ 18.376766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11150 13:54:59.425815 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11152 13:54:59.438686 /lava-12682925/1/../bin/lava-test-case
11153 13:54:59.445172 <8>[ 18.398362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11154 13:54:59.445934 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11156 13:54:59.454339 /lava-12682925/1/../bin/lava-test-case
11157 13:54:59.461245 <8>[ 18.412288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11158 13:54:59.462043 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11160 13:54:59.476790 /lava-12682925/1/../bin/lava-test-case
11161 13:54:59.483531 <8>[ 18.434649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11162 13:54:59.484327 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11164 13:54:59.493715 /lava-12682925/1/../bin/lava-test-case
11165 13:54:59.500310 <8>[ 18.452477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11166 13:54:59.501104 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11168 13:54:59.517223 /lava-12682925/1/../bin/lava-test-case
11169 13:54:59.523679 <8>[ 18.476083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11170 13:54:59.524633 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11172 13:54:59.534548 /lava-12682925/1/../bin/lava-test-case
11173 13:54:59.541002 <8>[ 18.493299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11174 13:54:59.541686 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11176 13:54:59.558987 /lava-12682925/1/../bin/lava-tes<8>[ 18.509949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11177 13:54:59.559509 t-case
11178 13:54:59.560112 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11180 13:54:59.581308 /lava-12682925/1/../bin/lava-tes<8>[ 18.532726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11181 13:54:59.581862 t-case
11182 13:54:59.582460 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11184 13:54:59.593933 /lava-12682925/1/../bin/lava-test-case
11185 13:54:59.600138 <8>[ 18.552346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11186 13:54:59.600927 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11188 13:54:59.614045 /lava-12682925/1/../bin/lava-test-case
11189 13:54:59.620509 <8>[ 18.572850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11190 13:54:59.621273 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11192 13:54:59.634189 /lava-12682925/1/../bin/lava-test-case
11193 13:54:59.640865 <8>[ 18.594459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11194 13:54:59.641655 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11196 13:54:59.653831 /lava-12682925/1/../bin/lava-test-case
11197 13:54:59.660568 <8>[ 18.612863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11198 13:54:59.661360 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11200 13:54:59.673139 /lava-12682925/1/../bin/lava-test-case
11201 13:54:59.679344 <8>[ 18.631100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11202 13:54:59.680165 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11204 13:54:59.697868 /lava-12682925/1/../bin/lava-tes<8>[ 18.649226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11205 13:54:59.698459 t-case
11206 13:54:59.699065 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11208 13:54:59.708519 /lava-12682925/1/../bin/lava-test-case
11209 13:54:59.715230 <8>[ 18.666566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11210 13:54:59.716019 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11212 13:54:59.726825 /lava-12682925/1/../bin/lava-test-case
11213 13:54:59.732979 <8>[ 18.684893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11214 13:54:59.733705 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11216 13:54:59.748765 /lava-12682925/1/../bin/lava-test-case
11217 13:54:59.754825 <8>[ 18.707598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11218 13:54:59.755686 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11220 13:54:59.768076 /lava-12682925/1/../bin/lava-test-case
11221 13:54:59.774399 <8>[ 18.726100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11222 13:54:59.775150 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11224 13:54:59.792240 /lava-12682925/1/../bin/lava-tes<8>[ 18.743762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11225 13:54:59.792663 t-case
11226 13:54:59.793240 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11228 13:54:59.801588 /lava-12682925/1/../bin/lava-test-case
11229 13:54:59.807994 <8>[ 18.759794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11230 13:54:59.808669 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11232 13:54:59.819883 /lava-12682925/1/../bin/lava-test-case
11233 13:54:59.826465 <8>[ 18.778790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11234 13:54:59.827156 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11236 13:54:59.835680 /lava-12682925/1/../bin/lava-test-case
11237 13:54:59.842068 <8>[ 18.794994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11238 13:54:59.842774 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11240 13:54:59.862467 /lava-12682925/1/../bin/lava-tes<8>[ 18.814207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11241 13:54:59.862908 t-case
11242 13:54:59.863495 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11244 13:54:59.877427 /lava-12682925/1/../bin/lava-tes<8>[ 18.829431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11245 13:54:59.877536 t-case
11246 13:54:59.877777 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11248 13:54:59.891750 /lava-12682925/1/../bin/lava-test-case
11249 13:54:59.898432 <8>[ 18.851565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11250 13:54:59.899221 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11252 13:54:59.914717 /lava-12682925/1/../bin/lava-tes<8>[ 18.866139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11253 13:54:59.915252 t-case
11254 13:54:59.915901 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11256 13:54:59.930185 /lava-12682925/1/../bin/lava-test-case
11257 13:54:59.936691 <8>[ 18.888850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11258 13:54:59.937369 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11260 13:54:59.954196 /lava-12682925/1/../bin/lava-tes<8>[ 18.905852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11261 13:54:59.954618 t-case
11262 13:54:59.955193 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11264 13:54:59.965925 /lava-12682925/1/../bin/lava-test-case
11265 13:54:59.972527 <8>[ 18.924713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11266 13:54:59.973197 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11268 13:54:59.983604 /lava-12682925/1/../bin/lava-test-case
11269 13:54:59.990019 <8>[ 18.942922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11270 13:54:59.990691 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11272 13:55:00.011842 /lava-12682925/1/../bin/lava-tes<8>[ 18.963432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11273 13:55:00.012383 t-case
11274 13:55:00.013113 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11276 13:55:00.024626 /lava-12682925/1/../bin/lava-test-case
11277 13:55:00.031346 <8>[ 18.983669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11278 13:55:00.032018 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11280 13:55:00.042334 /lava-12682925/1/../bin/lava-test-case
11281 13:55:00.048989 <8>[ 19.000559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11282 13:55:00.049640 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11284 13:55:00.060819 /lava-12682925/1/../bin/lava-test-case
11285 13:55:00.067379 <8>[ 19.019629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11286 13:55:00.068019 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11288 13:55:00.075632 /lava-12682925/1/../bin/lava-test-case
11289 13:55:00.082051 <8>[ 19.033739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11290 13:55:00.082752 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11292 13:55:00.093806 /lava-12682925/1/../bin/lava-test-case
11293 13:55:00.100235 <8>[ 19.052486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11294 13:55:00.101021 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11296 13:55:00.108138 /lava-12682925/1/../bin/lava-test-case
11297 13:55:00.114661 <8>[ 19.067442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11298 13:55:00.115430 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11300 13:55:01.128289 /lava-12682925/1/../bin/lava-test-case
11301 13:55:01.134299 <8>[ 20.087434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11302 13:55:01.134556 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11304 13:55:01.148144 /lava-12682925/1/../bin/lava-test-case
11305 13:55:01.157886 <8>[ 20.109293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11306 13:55:01.158246 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11308 13:55:02.171437 /lava-12682925/1/../bin/lava-test-case
11309 13:55:02.177805 <8>[ 21.131447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11310 13:55:02.178600 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11312 13:55:02.189067 /lava-12682925/1/../bin/lava-test-case
11313 13:55:02.195779 <8>[ 21.147228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11314 13:55:02.196572 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11316 13:55:03.211320 /lava-12682925/1/../bin/lava-test-case
11317 13:55:03.217381 <8>[ 22.170878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11318 13:55:03.218220 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11320 13:55:03.228662 /lava-12682925/1/../bin/lava-test-case
11321 13:55:03.234987 <8>[ 22.187591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11322 13:55:03.235784 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11324 13:55:04.249509 /lava-12682925/1/../bin/lava-test-case
11325 13:55:04.255870 <8>[ 23.209598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11326 13:55:04.256655 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11328 13:55:04.265879 /lava-12682925/1/../bin/lava-test-case
11329 13:55:04.272529 <8>[ 23.225204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11330 13:55:04.273314 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11332 13:55:05.286641 /lava-12682925/1/../bin/lava-test-case
11333 13:55:05.293269 <8>[ 24.246735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11334 13:55:05.294092 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11336 13:55:05.303048 /lava-12682925/1/../bin/lava-test-case
11337 13:55:05.309728 <8>[ 24.262917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11338 13:55:05.310404 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11340 13:55:06.325604 /lava-12682925/1/../bin/lava-test-case
11341 13:55:06.331495 <8>[ 25.284723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11342 13:55:06.332170 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11344 13:55:06.344548 /lava-12682925/1/../bin/lava-test-case
11345 13:55:06.350662 <8>[ 25.304443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11346 13:55:06.351353 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11348 13:55:07.364755 /lava-12682925/1/../bin/lava-test-case
11349 13:55:07.371414 <8>[ 26.324157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11350 13:55:07.372254 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11352 13:55:07.382314 /lava-12682925/1/../bin/lava-test-case
11353 13:55:07.389096 <8>[ 26.341935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11354 13:55:07.389938 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11356 13:55:07.398885 /lava-12682925/1/../bin/lava-test-case
11357 13:55:07.405158 <8>[ 26.357576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11358 13:55:07.405988 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11360 13:55:08.423499 /lava-12682925/1/../bin/lava-test-case
11361 13:55:08.429857 <8>[ 27.384252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11362 13:55:08.430635 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11364 13:55:08.441233 /lava-12682925/1/../bin/lava-test-case
11365 13:55:08.447774 <8>[ 27.401374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11366 13:55:08.448510 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11368 13:55:08.461025 /lava-12682925/1/../bin/lava-test-case
11369 13:55:08.467536 <8>[ 27.420400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11370 13:55:08.468211 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11372 13:55:08.485319 /lava-12682925/1/../bin/lava-tes<8>[ 27.437683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11373 13:55:08.485846 t-case
11374 13:55:08.486433 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11376 13:55:08.497264 /lava-12682925/1/../bin/lava-test-case
11377 13:55:08.503816 <8>[ 27.457097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11378 13:55:08.504492 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11380 13:55:08.514186 /lava-12682925/1/../bin/lava-test-case
11381 13:55:08.520993 <8>[ 27.474688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11382 13:55:08.521678 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11384 13:55:08.542436 /lava-12682925/1/../bin/lava-tes<8>[ 27.494620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11385 13:55:08.542955 t-case
11386 13:55:08.543553 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11388 13:55:08.558697 /lava-12682925/1/../bin/lava-tes<8>[ 27.510754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11389 13:55:08.559216 t-case
11390 13:55:08.559815 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11392 13:55:08.570189 /lava-12682925/1/../bin/lava-test-case
11393 13:55:08.576481 <8>[ 27.529404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11394 13:55:08.577165 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11396 13:55:08.588674 /lava-12682925/1/../bin/lava-test-case
11397 13:55:08.595023 <8>[ 27.548090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11398 13:55:08.595712 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11400 13:55:08.604063 /lava-12682925/1/../bin/lava-test-case
11401 13:55:08.614001 <8>[ 27.565601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11402 13:55:08.614793 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11404 13:55:08.625825 /lava-12682925/1/../bin/lava-test-case
11405 13:55:08.631971 <8>[ 27.585104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11406 13:55:08.632768 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11408 13:55:08.640895 /lava-12682925/1/../bin/lava-test-case
11409 13:55:08.647477 <8>[ 27.600748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11410 13:55:08.648266 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11412 13:55:08.664148 /lava-12682925/1/../bin/lava-test-case
11413 13:55:08.670756 <8>[ 27.623448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11414 13:55:08.671873 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11416 13:55:08.688292 /lava-12682925/1/../bin/lava-tes<8>[ 27.640600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11417 13:55:08.688814 t-case
11418 13:55:08.689413 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11420 13:55:08.701307 /lava-12682925/1/../bin/lava-test-case
11421 13:55:08.708259 <8>[ 27.661174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11422 13:55:08.709046 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11424 13:55:08.718395 /lava-12682925/1/../bin/lava-test-case
11425 13:55:08.725347 <8>[ 27.677434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11426 13:55:08.726178 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11428 13:55:08.739726 /lava-12682925/1/../bin/lava-test-case
11429 13:55:08.746254 <8>[ 27.698970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11430 13:55:08.747047 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11432 13:55:08.756191 /lava-12682925/1/../bin/lava-test-case
11433 13:55:08.762859 <8>[ 27.716336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11434 13:55:08.763805 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11436 13:55:08.775939 /lava-12682925/1/../bin/lava-test-case
11437 13:55:08.782197 <8>[ 27.734941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11438 13:55:08.782871 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11440 13:55:08.798643 /lava-12682925/1/../bin/lava-tes<8>[ 27.751012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11441 13:55:08.799153 t-case
11442 13:55:08.799746 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11444 13:55:09.814070 /lava-12682925/1/../bin/lava-test-case
11445 13:55:09.820580 <8>[ 28.774650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11446 13:55:09.821379 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11448 13:55:10.834971 /lava-12682925/1/../bin/lava-test-case
11449 13:55:10.841604 <8>[ 29.796459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11450 13:55:10.842401 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11452 13:55:10.852427 /lava-12682925/1/../bin/lava-test-case
11453 13:55:10.858865 <8>[ 29.812434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11454 13:55:10.859660 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11456 13:55:10.878942 /lava-12682925/1/../bin/lava-tes<8>[ 29.831074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11457 13:55:10.879468 t-case
11458 13:55:10.880073 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11460 13:55:10.888197 /lava-12682925/1/../bin/lava-test-case
11461 13:55:10.895248 <8>[ 29.847774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11462 13:55:10.896046 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11464 13:55:10.908495 /lava-12682925/1/../bin/lava-test-case
11465 13:55:10.914853 <8>[ 29.867775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11466 13:55:10.915647 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11468 13:55:10.926183 /lava-12682925/1/../bin/lava-test-case
11469 13:55:10.932486 <8>[ 29.886165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11470 13:55:10.933279 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11472 13:55:10.944706 /lava-12682925/1/../bin/lava-test-case
11473 13:55:10.951175 <8>[ 29.903792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11474 13:55:10.951969 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11476 13:55:10.960643 /lava-12682925/1/../bin/lava-test-case
11477 13:55:10.967015 <8>[ 29.919801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11478 13:55:10.967992 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11480 13:55:10.979736 /lava-12682925/1/../bin/lava-test-case
11481 13:55:10.986016 <8>[ 29.940066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11482 13:55:10.986698 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11484 13:55:11.000986 /lava-12682925/1/../bin/lava-tes<8>[ 29.954034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11485 13:55:11.001410 t-case
11486 13:55:11.002065 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11488 13:55:11.014020 /lava-12682925/1/../bin/lava-test-case
11489 13:55:11.020613 <8>[ 29.973850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11490 13:55:11.021425 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11492 13:55:11.028662 /lava-12682925/1/../bin/lava-test-case
11493 13:55:11.035286 <8>[ 29.988426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11494 13:55:11.036009 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11496 13:55:11.050457 /lava-12682925/1/../bin/lava-test-case
11497 13:55:11.057156 <8>[ 30.011077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11498 13:55:11.057983 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11500 13:55:11.066215 /lava-12682925/1/../bin/lava-test-case
11501 13:55:11.073123 <8>[ 30.026428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11502 13:55:11.074004 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11504 13:55:11.084317 /lava-12682925/1/../bin/lava-test-case
11505 13:55:11.090955 <8>[ 30.044741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11506 13:55:11.091635 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11508 13:55:11.100137 /lava-12682925/1/../bin/lava-test-case
11509 13:55:11.106404 <8>[ 30.059837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11510 13:55:11.107138 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11512 13:55:11.117637 /lava-12682925/1/../bin/lava-test-case
11513 13:55:11.124092 <8>[ 30.078597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11514 13:55:11.124887 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11516 13:55:11.134582 /lava-12682925/1/../bin/lava-test-case
11517 13:55:11.141084 <8>[ 30.094503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11518 13:55:11.141873 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11520 13:55:11.153520 /lava-12682925/1/../bin/lava-test-case
11521 13:55:11.159933 <8>[ 30.112917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11522 13:55:11.160712 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11524 13:55:11.175836 /lava-12682925/1/../bin/lava-tes<8>[ 30.128655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11525 13:55:11.176357 t-case
11526 13:55:11.176948 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11528 13:55:11.189430 /lava-12682925/1/../bin/lava-test-case
11529 13:55:11.196230 <8>[ 30.148704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11530 13:55:11.197022 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11532 13:55:12.208762 /lava-12682925/1/../bin/lava-test-case
11533 13:55:12.215023 <8>[ 31.169655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11534 13:55:12.215702 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11536 13:55:13.228574 /lava-12682925/1/../bin/lava-test-case
11537 13:55:13.235426 <8>[ 32.190274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11538 13:55:13.236218 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11539 13:55:13.236660 Bad test result: blocked
11540 13:55:13.246550 /lava-12682925/1/../bin/lava-test-case
11541 13:55:13.252785 <8>[ 32.205898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11542 13:55:13.253617 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11544 13:55:14.266002 /lava-12682925/1/../bin/lava-test-case
11545 13:55:14.272918 <8>[ 33.226393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11546 13:55:14.273703 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11548 13:55:14.285561 /lava-12682925/1/../bin/lava-test-case
11549 13:55:14.292139 <8>[ 33.247053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11550 13:55:14.292922 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11552 13:55:14.303783 /lava-12682925/1/../bin/lava-test-case
11553 13:55:14.310187 <8>[ 33.263661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11554 13:55:14.311038 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11556 13:55:14.324720 /lava-12682925/1/../bin/lava-test-case
11557 13:55:14.331091 <8>[ 33.284391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11558 13:55:14.331880 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11560 13:55:14.341450 /lava-12682925/1/../bin/lava-test-case
11561 13:55:14.348379 <8>[ 33.301416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11562 13:55:14.349414 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11564 13:55:14.360563 /lava-12682925/1/../bin/lava-test-case
11565 13:55:14.366956 <8>[ 33.320234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11566 13:55:14.367653 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11568 13:55:14.378037 /lava-12682925/1/../bin/lava-test-case
11569 13:55:14.384348 <8>[ 33.337576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11570 13:55:14.385350 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11572 13:55:15.398092 /lava-12682925/1/../bin/lava-test-case
11573 13:55:15.404338 <8>[ 34.359415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11574 13:55:15.405130 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11576 13:55:15.422133 /lava-12682925/1/../bin/lava-tes<8>[ 34.374966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11577 13:55:15.422680 t-case
11578 13:55:15.423281 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11580 13:55:16.435189 /lava-12682925/1/../bin/lava-test-case
11581 13:55:16.441610 <8>[ 35.396534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11582 13:55:16.442441 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11584 13:55:16.451548 /lava-12682925/1/../bin/lava-test-case
11585 13:55:16.458019 <8>[ 35.412225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11586 13:55:16.458808 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11588 13:55:17.472736 /lava-12682925/1/../bin/lava-test-case
11589 13:55:17.479357 <8>[ 36.434269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11590 13:55:17.480172 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11592 13:55:17.489238 /lava-12682925/1/../bin/lava-test-case
11593 13:55:17.495986 <8>[ 36.450235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11594 13:55:17.496827 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11596 13:55:18.510562 /lava-12682925/1/../bin/lava-test-case
11597 13:55:18.517528 <8>[ 37.472595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11598 13:55:18.518318 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11600 13:55:18.528083 /lava-12682925/1/../bin/lava-test-case
11601 13:55:18.535196 <8>[ 37.489242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11602 13:55:18.536011 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11604 13:55:18.550363 /lava-12682925/1/../bin/lava-tes<8>[ 37.506956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11605 13:55:18.551171 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11607 13:55:18.553562 t-case
11608 13:55:18.563867 /lava-12682925/1/../bin/lava-test-case
11609 13:55:18.570226 <8>[ 37.523710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11610 13:55:18.571028 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11612 13:55:18.579069 /lava-12682925/1/../bin/lava-test-case
11613 13:55:18.586213 <8>[ 37.540162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11614 13:55:18.587067 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11616 13:55:18.596288 /lava-12682925/1/../bin/lava-test-case
11617 13:55:18.602808 <8>[ 37.557366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11618 13:55:18.603621 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11620 13:55:18.611605 /lava-12682925/1/../bin/lava-test-case
11621 13:55:18.618275 <8>[ 37.572711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11622 13:55:18.619052 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11624 13:55:18.630214 /lava-12682925/1/../bin/lava-test-case
11625 13:55:18.637131 <8>[ 37.590574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11626 13:55:18.637852 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11628 13:55:18.652873 /lava-12682925/1/../bin/lava-tes<8>[ 37.606494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11629 13:55:18.653381 t-case
11630 13:55:18.654030 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11632 13:55:18.665463 /lava-12682925/1/../bin/lava-test-case
11633 13:55:18.671969 <8>[ 37.625396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11634 13:55:18.672769 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11636 13:55:18.676276 + set +x
11637 13:55:18.679915 Received signal: <ENDRUN> 1_bootrr 12682925_1.5.2.3.5
11638 13:55:18.680446 Ending use of test pattern.
11639 13:55:18.680778 Ending test lava.1_bootrr (12682925_1.5.2.3.5), duration 20.44
11641 13:55:18.682577 <8>[ 37.636712] <LAVA_SIGNAL_ENDRUN 1_bootrr 12682925_1.5.2.3.5>
11642 13:55:18.685894 <LAVA_TEST_RUNNER EXIT>
11643 13:55:18.686703 ok: lava_test_shell seems to have completed
11644 13:55:18.691648 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11645 13:55:18.692345 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11646 13:55:18.692776 end: 4 lava-test-retry (duration 00:00:21) [common]
11647 13:55:18.693207 start: 5 finalize (timeout 00:07:44) [common]
11648 13:55:18.693712 start: 5.1 power-off (timeout 00:00:30) [common]
11649 13:55:18.694456 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11650 13:55:18.778610 >> Command sent successfully.
11651 13:55:18.789245 Returned 0 in 0 seconds
11652 13:55:18.890503 end: 5.1 power-off (duration 00:00:00) [common]
11654 13:55:18.891980 start: 5.2 read-feedback (timeout 00:07:44) [common]
11655 13:55:18.893413 Listened to connection for namespace 'common' for up to 1s
11656 13:55:19.893770 Finalising connection for namespace 'common'
11657 13:55:19.894496 Disconnecting from shell: Finalise
11658 13:55:19.894954 / #
11659 13:55:19.995976 end: 5.2 read-feedback (duration 00:00:01) [common]
11660 13:55:19.996740 end: 5 finalize (duration 00:00:01) [common]
11661 13:55:19.997316 Cleaning after the job
11662 13:55:19.997967 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/ramdisk
11663 13:55:20.012907 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/kernel
11664 13:55:20.038920 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/dtb
11665 13:55:20.039262 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682925/tftp-deploy-kqtpze1w/modules
11666 13:55:20.050392 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682925
11667 13:55:20.097697 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682925
11668 13:55:20.097872 Job finished correctly