Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 17
- Kernel Errors: 38
1 13:55:02.952611 lava-dispatcher, installed at version: 2023.10
2 13:55:02.952855 start: 0 validate
3 13:55:02.952995 Start time: 2024-02-01 13:55:02.952986+00:00 (UTC)
4 13:55:02.953126 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:55:02.953263 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 13:55:03.221024 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:55:03.221196 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:55:20.233660 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:55:20.234392 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:55:20.503788 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:55:20.504246 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:55:21.034941 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:55:21.035678 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:55:23.048728 validate duration: 20.10
16 13:55:23.050114 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:55:23.050674 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:55:23.051184 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:55:23.051825 Not decompressing ramdisk as can be used compressed.
20 13:55:23.052337 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 13:55:23.052738 saving as /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/ramdisk/initrd.cpio.gz
22 13:55:23.053116 total size: 4665412 (4 MB)
23 13:55:23.322427 progress 0 % (0 MB)
24 13:55:23.324006 progress 5 % (0 MB)
25 13:55:23.325432 progress 10 % (0 MB)
26 13:55:23.326730 progress 15 % (0 MB)
27 13:55:23.328089 progress 20 % (0 MB)
28 13:55:23.329433 progress 25 % (1 MB)
29 13:55:23.330716 progress 30 % (1 MB)
30 13:55:23.332090 progress 35 % (1 MB)
31 13:55:23.333399 progress 40 % (1 MB)
32 13:55:23.334815 progress 45 % (2 MB)
33 13:55:23.336207 progress 50 % (2 MB)
34 13:55:23.337524 progress 55 % (2 MB)
35 13:55:23.338799 progress 60 % (2 MB)
36 13:55:23.340183 progress 65 % (2 MB)
37 13:55:23.341450 progress 70 % (3 MB)
38 13:55:23.342690 progress 75 % (3 MB)
39 13:55:23.344044 progress 80 % (3 MB)
40 13:55:23.345487 progress 85 % (3 MB)
41 13:55:23.346713 progress 90 % (4 MB)
42 13:55:23.348100 progress 95 % (4 MB)
43 13:55:23.349507 progress 100 % (4 MB)
44 13:55:23.349670 4 MB downloaded in 0.30 s (15.00 MB/s)
45 13:55:23.349826 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:55:23.350066 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:55:23.350152 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:55:23.350235 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:55:23.350374 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:55:23.350445 saving as /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/kernel/Image
52 13:55:23.350506 total size: 51532288 (49 MB)
53 13:55:23.350622 No compression specified
54 13:55:23.352012 progress 0 % (0 MB)
55 13:55:23.366510 progress 5 % (2 MB)
56 13:55:23.381717 progress 10 % (4 MB)
57 13:55:23.396056 progress 15 % (7 MB)
58 13:55:23.410115 progress 20 % (9 MB)
59 13:55:23.424130 progress 25 % (12 MB)
60 13:55:23.438541 progress 30 % (14 MB)
61 13:55:23.452278 progress 35 % (17 MB)
62 13:55:23.466000 progress 40 % (19 MB)
63 13:55:23.479616 progress 45 % (22 MB)
64 13:55:23.493526 progress 50 % (24 MB)
65 13:55:23.507232 progress 55 % (27 MB)
66 13:55:23.521361 progress 60 % (29 MB)
67 13:55:23.535833 progress 65 % (31 MB)
68 13:55:23.550301 progress 70 % (34 MB)
69 13:55:23.564897 progress 75 % (36 MB)
70 13:55:23.579575 progress 80 % (39 MB)
71 13:55:23.593808 progress 85 % (41 MB)
72 13:55:23.607887 progress 90 % (44 MB)
73 13:55:23.622398 progress 95 % (46 MB)
74 13:55:23.636612 progress 100 % (49 MB)
75 13:55:23.636872 49 MB downloaded in 0.29 s (171.62 MB/s)
76 13:55:23.637086 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:55:23.637330 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:55:23.637419 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:55:23.637508 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:55:23.637651 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:55:23.637724 saving as /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/dtb/mt8192-asurada-spherion-r0.dtb
83 13:55:23.637792 total size: 47278 (0 MB)
84 13:55:23.637855 No compression specified
85 13:55:23.639025 progress 69 % (0 MB)
86 13:55:23.639312 progress 100 % (0 MB)
87 13:55:23.639473 0 MB downloaded in 0.00 s (26.87 MB/s)
88 13:55:23.639603 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:55:23.639835 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:55:23.639961 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:55:23.640084 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:55:23.640252 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 13:55:23.640344 saving as /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/nfsrootfs/full.rootfs.tar
95 13:55:23.640408 total size: 125290964 (119 MB)
96 13:55:23.640471 Using unxz to decompress xz
97 13:55:23.644979 progress 0 % (0 MB)
98 13:55:23.991315 progress 5 % (6 MB)
99 13:55:24.337185 progress 10 % (11 MB)
100 13:55:24.674117 progress 15 % (17 MB)
101 13:55:24.872628 progress 20 % (23 MB)
102 13:55:25.064202 progress 25 % (29 MB)
103 13:55:25.442002 progress 30 % (35 MB)
104 13:55:25.825853 progress 35 % (41 MB)
105 13:55:26.237506 progress 40 % (47 MB)
106 13:55:26.632234 progress 45 % (53 MB)
107 13:55:27.038593 progress 50 % (59 MB)
108 13:55:27.404458 progress 55 % (65 MB)
109 13:55:27.783977 progress 60 % (71 MB)
110 13:55:28.141099 progress 65 % (77 MB)
111 13:55:28.528622 progress 70 % (83 MB)
112 13:55:28.934349 progress 75 % (89 MB)
113 13:55:29.370830 progress 80 % (95 MB)
114 13:55:29.803704 progress 85 % (101 MB)
115 13:55:30.061210 progress 90 % (107 MB)
116 13:55:30.426341 progress 95 % (113 MB)
117 13:55:30.831207 progress 100 % (119 MB)
118 13:55:30.839310 119 MB downloaded in 7.20 s (16.60 MB/s)
119 13:55:30.839723 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:55:30.840130 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:55:30.840263 start: 1.5 download-retry (timeout 00:09:52) [common]
123 13:55:30.840411 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 13:55:30.840637 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:55:30.840748 saving as /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/modules/modules.tar
126 13:55:30.840843 total size: 8623988 (8 MB)
127 13:55:30.840943 Using unxz to decompress xz
128 13:55:30.846600 progress 0 % (0 MB)
129 13:55:30.868477 progress 5 % (0 MB)
130 13:55:30.892856 progress 10 % (0 MB)
131 13:55:30.917382 progress 15 % (1 MB)
132 13:55:30.941954 progress 20 % (1 MB)
133 13:55:30.966943 progress 25 % (2 MB)
134 13:55:30.994054 progress 30 % (2 MB)
135 13:55:31.023023 progress 35 % (2 MB)
136 13:55:31.047376 progress 40 % (3 MB)
137 13:55:31.072921 progress 45 % (3 MB)
138 13:55:31.099144 progress 50 % (4 MB)
139 13:55:31.124486 progress 55 % (4 MB)
140 13:55:31.150296 progress 60 % (4 MB)
141 13:55:31.179154 progress 65 % (5 MB)
142 13:55:31.206111 progress 70 % (5 MB)
143 13:55:31.231991 progress 75 % (6 MB)
144 13:55:31.261330 progress 80 % (6 MB)
145 13:55:31.288883 progress 85 % (7 MB)
146 13:55:31.314837 progress 90 % (7 MB)
147 13:55:31.347635 progress 95 % (7 MB)
148 13:55:31.376735 progress 100 % (8 MB)
149 13:55:31.381799 8 MB downloaded in 0.54 s (15.20 MB/s)
150 13:55:31.382207 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:55:31.382621 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:55:31.382759 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 13:55:31.382902 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 13:55:33.681795 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12682934/extract-nfsrootfs-rmbfr8up
156 13:55:33.682005 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:55:33.682104 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 13:55:33.682280 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8
159 13:55:33.682456 makedir: /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin
160 13:55:33.682559 makedir: /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/tests
161 13:55:33.682658 makedir: /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/results
162 13:55:33.682763 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-add-keys
163 13:55:33.682913 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-add-sources
164 13:55:33.683075 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-background-process-start
165 13:55:33.683204 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-background-process-stop
166 13:55:33.683331 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-common-functions
167 13:55:33.683457 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-echo-ipv4
168 13:55:33.683584 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-install-packages
169 13:55:33.683709 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-installed-packages
170 13:55:33.683836 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-os-build
171 13:55:33.683961 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-probe-channel
172 13:55:33.684087 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-probe-ip
173 13:55:33.684211 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-target-ip
174 13:55:33.684387 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-target-mac
175 13:55:33.684516 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-target-storage
176 13:55:33.684646 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-test-case
177 13:55:33.684777 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-test-event
178 13:55:33.684903 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-test-feedback
179 13:55:33.685028 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-test-raise
180 13:55:33.685153 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-test-reference
181 13:55:33.685278 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-test-runner
182 13:55:33.685403 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-test-set
183 13:55:33.685527 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-test-shell
184 13:55:33.685653 Updating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-install-packages (oe)
185 13:55:33.685809 Updating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/bin/lava-installed-packages (oe)
186 13:55:33.685932 Creating /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/environment
187 13:55:33.686030 LAVA metadata
188 13:55:33.686101 - LAVA_JOB_ID=12682934
189 13:55:33.686164 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:55:33.686276 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 13:55:33.686343 skipped lava-vland-overlay
192 13:55:33.686467 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:55:33.686627 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 13:55:33.686724 skipped lava-multinode-overlay
195 13:55:33.686813 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:55:33.686893 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 13:55:33.686970 Loading test definitions
198 13:55:33.687062 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 13:55:33.687132 Using /lava-12682934 at stage 0
200 13:55:33.687450 uuid=12682934_1.6.2.3.1 testdef=None
201 13:55:33.687540 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:55:33.687623 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 13:55:33.688134 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:55:33.688448 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 13:55:33.689274 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:55:33.689512 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 13:55:33.690141 runner path: /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/0/tests/0_dmesg test_uuid 12682934_1.6.2.3.1
210 13:55:33.690300 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:55:33.690646 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 13:55:33.690763 Using /lava-12682934 at stage 1
214 13:55:33.691171 uuid=12682934_1.6.2.3.5 testdef=None
215 13:55:33.691272 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 13:55:33.691373 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 13:55:33.691869 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 13:55:33.692205 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 13:55:33.693176 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 13:55:33.693435 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 13:55:33.694080 runner path: /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/1/tests/1_bootrr test_uuid 12682934_1.6.2.3.5
224 13:55:33.694248 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 13:55:33.694481 Creating lava-test-runner.conf files
227 13:55:33.694582 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/0 for stage 0
228 13:55:33.694719 - 0_dmesg
229 13:55:33.694835 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682934/lava-overlay-nswwoxc8/lava-12682934/1 for stage 1
230 13:55:33.694970 - 1_bootrr
231 13:55:33.695107 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 13:55:33.695231 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 13:55:33.703953 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 13:55:33.704149 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 13:55:33.704315 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 13:55:33.704477 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 13:55:33.704619 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 13:55:33.829736 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 13:55:33.830147 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 13:55:33.830291 extracting modules file /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682934/extract-nfsrootfs-rmbfr8up
241 13:55:34.065433 extracting modules file /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682934/extract-overlay-ramdisk-umw1fl_u/ramdisk
242 13:55:34.307932 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 13:55:34.308118 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 13:55:34.308213 [common] Applying overlay to NFS
245 13:55:34.308312 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682934/compress-overlay-aotlp_s7/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682934/extract-nfsrootfs-rmbfr8up
246 13:55:34.316769 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 13:55:34.316999 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 13:55:34.317097 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 13:55:34.317187 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 13:55:34.317284 Building ramdisk /var/lib/lava/dispatcher/tmp/12682934/extract-overlay-ramdisk-umw1fl_u/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682934/extract-overlay-ramdisk-umw1fl_u/ramdisk
251 13:55:34.660196 >> 119414 blocks
252 13:55:36.686701 rename /var/lib/lava/dispatcher/tmp/12682934/extract-overlay-ramdisk-umw1fl_u/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/ramdisk/ramdisk.cpio.gz
253 13:55:36.687171 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 13:55:36.687300 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
255 13:55:36.687405 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
256 13:55:36.687512 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/kernel/Image'
257 13:55:50.452494 Returned 0 in 13 seconds
258 13:55:50.553273 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/kernel/image.itb
259 13:55:50.943792 output: FIT description: Kernel Image image with one or more FDT blobs
260 13:55:50.944308 output: Created: Thu Feb 1 13:55:50 2024
261 13:55:50.944429 output: Image 0 (kernel-1)
262 13:55:50.944537 output: Description:
263 13:55:50.944632 output: Created: Thu Feb 1 13:55:50 2024
264 13:55:50.944726 output: Type: Kernel Image
265 13:55:50.944821 output: Compression: lzma compressed
266 13:55:50.944911 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
267 13:55:50.945002 output: Architecture: AArch64
268 13:55:50.945092 output: OS: Linux
269 13:55:50.945193 output: Load Address: 0x00000000
270 13:55:50.945286 output: Entry Point: 0x00000000
271 13:55:50.945398 output: Hash algo: crc32
272 13:55:50.945497 output: Hash value: 5aa40db2
273 13:55:50.945592 output: Image 1 (fdt-1)
274 13:55:50.945680 output: Description: mt8192-asurada-spherion-r0
275 13:55:50.945771 output: Created: Thu Feb 1 13:55:50 2024
276 13:55:50.945861 output: Type: Flat Device Tree
277 13:55:50.945950 output: Compression: uncompressed
278 13:55:50.946040 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 13:55:50.946129 output: Architecture: AArch64
280 13:55:50.946218 output: Hash algo: crc32
281 13:55:50.946319 output: Hash value: cc4352de
282 13:55:50.946419 output: Image 2 (ramdisk-1)
283 13:55:50.946510 output: Description: unavailable
284 13:55:50.946598 output: Created: Thu Feb 1 13:55:50 2024
285 13:55:50.946698 output: Type: RAMDisk Image
286 13:55:50.946789 output: Compression: Unknown Compression
287 13:55:50.946879 output: Data Size: 17799409 Bytes = 17382.24 KiB = 16.97 MiB
288 13:55:50.946969 output: Architecture: AArch64
289 13:55:50.947058 output: OS: Linux
290 13:55:50.947146 output: Load Address: unavailable
291 13:55:50.947235 output: Entry Point: unavailable
292 13:55:50.947342 output: Hash algo: crc32
293 13:55:50.947448 output: Hash value: e4ac8d76
294 13:55:50.947540 output: Default Configuration: 'conf-1'
295 13:55:50.947629 output: Configuration 0 (conf-1)
296 13:55:50.947717 output: Description: mt8192-asurada-spherion-r0
297 13:55:50.947816 output: Kernel: kernel-1
298 13:55:50.947915 output: Init Ramdisk: ramdisk-1
299 13:55:50.948022 output: FDT: fdt-1
300 13:55:50.948112 output: Loadables: kernel-1
301 13:55:50.948199 output:
302 13:55:50.948486 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 13:55:50.948649 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 13:55:50.948805 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
305 13:55:50.948946 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:32) [common]
306 13:55:50.949069 No LXC device requested
307 13:55:50.949189 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 13:55:50.949320 start: 1.8 deploy-device-env (timeout 00:09:32) [common]
309 13:55:50.949465 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 13:55:50.949571 Checking files for TFTP limit of 4294967296 bytes.
311 13:55:50.950298 end: 1 tftp-deploy (duration 00:00:28) [common]
312 13:55:50.950442 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 13:55:50.950579 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 13:55:50.950762 substitutions:
315 13:55:50.950865 - {DTB}: 12682934/tftp-deploy-4nfmyslk/dtb/mt8192-asurada-spherion-r0.dtb
316 13:55:50.950983 - {INITRD}: 12682934/tftp-deploy-4nfmyslk/ramdisk/ramdisk.cpio.gz
317 13:55:50.951079 - {KERNEL}: 12682934/tftp-deploy-4nfmyslk/kernel/Image
318 13:55:50.951171 - {LAVA_MAC}: None
319 13:55:50.951263 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12682934/extract-nfsrootfs-rmbfr8up
320 13:55:50.951360 - {NFS_SERVER_IP}: 192.168.201.1
321 13:55:50.951465 - {PRESEED_CONFIG}: None
322 13:55:50.951567 - {PRESEED_LOCAL}: None
323 13:55:50.951657 - {RAMDISK}: 12682934/tftp-deploy-4nfmyslk/ramdisk/ramdisk.cpio.gz
324 13:55:50.951751 - {ROOT_PART}: None
325 13:55:50.951841 - {ROOT}: None
326 13:55:50.951931 - {SERVER_IP}: 192.168.201.1
327 13:55:50.952029 - {TEE}: None
328 13:55:50.952135 Parsed boot commands:
329 13:55:50.952226 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 13:55:50.952496 Parsed boot commands: tftpboot 192.168.201.1 12682934/tftp-deploy-4nfmyslk/kernel/image.itb 12682934/tftp-deploy-4nfmyslk/kernel/cmdline
331 13:55:50.952636 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 13:55:50.952762 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 13:55:50.952900 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 13:55:50.953035 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 13:55:50.953142 Not connected, no need to disconnect.
336 13:55:50.953259 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 13:55:50.953414 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 13:55:50.953531 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
339 13:55:50.958459 Setting prompt string to ['lava-test: # ']
340 13:55:50.958959 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 13:55:50.959123 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 13:55:50.959260 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 13:55:50.959406 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 13:55:50.959696 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
345 13:55:56.093587 >> Command sent successfully.
346 13:55:56.096036 Returned 0 in 5 seconds
347 13:55:56.196451 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 13:55:56.196929 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 13:55:56.197069 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 13:55:56.197197 Setting prompt string to 'Starting depthcharge on Spherion...'
352 13:55:56.197359 Changing prompt to 'Starting depthcharge on Spherion...'
353 13:55:56.197466 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 13:55:56.197836 [Enter `^Ec?' for help]
355 13:55:56.373426
356 13:55:56.373627
357 13:55:56.373732 F0: 102B 0000
358 13:55:56.373829
359 13:55:56.373919 F3: 1001 0000 [0200]
360 13:55:56.376556
361 13:55:56.376684 F3: 1001 0000
362 13:55:56.376781
363 13:55:56.376872 F7: 102D 0000
364 13:55:56.376963
365 13:55:56.380469 F1: 0000 0000
366 13:55:56.380580
367 13:55:56.380674 V0: 0000 0000 [0001]
368 13:55:56.380780
369 13:55:56.383754 00: 0007 8000
370 13:55:56.383867
371 13:55:56.383962 01: 0000 0000
372 13:55:56.384057
373 13:55:56.386863 BP: 0C00 0209 [0000]
374 13:55:56.386971
375 13:55:56.387066 G0: 1182 0000
376 13:55:56.387157
377 13:55:56.390525 EC: 0000 0021 [4000]
378 13:55:56.390637
379 13:55:56.390741 S7: 0000 0000 [0000]
380 13:55:56.390833
381 13:55:56.394134 CC: 0000 0000 [0001]
382 13:55:56.394247
383 13:55:56.394343 T0: 0000 0040 [010F]
384 13:55:56.394435
385 13:55:56.394525 Jump to BL
386 13:55:56.394615
387 13:55:56.420141
388 13:55:56.420342
389 13:55:56.420444
390 13:55:56.427377 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 13:55:56.430931 ARM64: Exception handlers installed.
392 13:55:56.434538 ARM64: Testing exception
393 13:55:56.437587 ARM64: Done test exception
394 13:55:56.444413 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 13:55:56.454394 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 13:55:56.461262 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 13:55:56.471455 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 13:55:56.478244 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 13:55:56.488317 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 13:55:56.499222 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 13:55:56.505669 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 13:55:56.523658 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 13:55:56.526917 WDT: Last reset was cold boot
404 13:55:56.529906 SPI1(PAD0) initialized at 2873684 Hz
405 13:55:56.533043 SPI5(PAD0) initialized at 992727 Hz
406 13:55:56.536559 VBOOT: Loading verstage.
407 13:55:56.543122 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 13:55:56.546906 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 13:55:56.549955 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 13:55:56.553237 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 13:55:56.560502 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 13:55:56.567805 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 13:55:56.578812 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 13:55:56.579004
415 13:55:56.579106
416 13:55:56.589271 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 13:55:56.592648 ARM64: Exception handlers installed.
418 13:55:56.592795 ARM64: Testing exception
419 13:55:56.595859 ARM64: Done test exception
420 13:55:56.599237 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 13:55:56.605782 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 13:55:56.619499 Probing TPM: . done!
423 13:55:56.619685 TPM ready after 0 ms
424 13:55:56.626393 Connected to device vid:did:rid of 1ae0:0028:00
425 13:55:56.665343 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 13:55:56.692233 Initialized TPM device CR50 revision 0
427 13:55:56.704507 tlcl_send_startup: Startup return code is 0
428 13:55:56.704694 TPM: setup succeeded
429 13:55:56.715740 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 13:55:56.724669 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 13:55:56.736782 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 13:55:56.747067 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 13:55:56.750775 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 13:55:56.754313 in-header: 03 07 00 00 08 00 00 00
435 13:55:56.758449 in-data: aa e4 47 04 13 02 00 00
436 13:55:56.758587 Chrome EC: UHEPI supported
437 13:55:56.765326 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 13:55:56.769392 in-header: 03 95 00 00 08 00 00 00
439 13:55:56.773085 in-data: 18 20 20 08 00 00 00 00
440 13:55:56.773219 Phase 1
441 13:55:56.777010 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 13:55:56.784283 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 13:55:56.791984 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 13:55:56.792149 Recovery requested (1009000e)
445 13:55:56.804805 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 13:55:56.808100 tlcl_extend: response is 0
447 13:55:56.817442 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 13:55:56.822707 tlcl_extend: response is 0
449 13:55:56.829800 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 13:55:56.849917 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 13:55:56.856270 BS: bootblock times (exec / console): total (unknown) / 149 ms
452 13:55:56.856498
453 13:55:56.856607
454 13:55:56.866167 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 13:55:56.869826 ARM64: Exception handlers installed.
456 13:55:56.872951 ARM64: Testing exception
457 13:55:56.873082 ARM64: Done test exception
458 13:55:56.895497 pmic_efuse_setting: Set efuses in 11 msecs
459 13:55:56.898530 pmwrap_interface_init: Select PMIF_VLD_RDY
460 13:55:56.905245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 13:55:56.908434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 13:55:56.916085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 13:55:56.919345 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 13:55:56.922717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 13:55:56.930708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 13:55:56.933969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 13:55:56.937821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 13:55:56.941855 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 13:55:56.948903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 13:55:56.952729 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 13:55:56.956301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 13:55:56.959498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 13:55:56.967881 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 13:55:56.975254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 13:55:56.978894 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 13:55:56.985871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 13:55:56.989582 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 13:55:56.997351 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 13:55:57.001052 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 13:55:57.008105 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 13:55:57.011903 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 13:55:57.019099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 13:55:57.023138 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 13:55:57.030388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 13:55:57.033495 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 13:55:57.040722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 13:55:57.044798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 13:55:57.048074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 13:55:57.055891 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 13:55:57.059806 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 13:55:57.063017 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 13:55:57.071096 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 13:55:57.074925 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 13:55:57.078876 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 13:55:57.085589 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 13:55:57.089806 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 13:55:57.093593 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 13:55:57.100502 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 13:55:57.104451 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 13:55:57.107736 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 13:55:57.111492 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 13:55:57.115528 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 13:55:57.119433 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 13:55:57.126807 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 13:55:57.130652 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 13:55:57.134214 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 13:55:57.137573 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 13:55:57.141825 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 13:55:57.145215 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 13:55:57.149211 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 13:55:57.159595 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 13:55:57.167388 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 13:55:57.170692 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 13:55:57.178236 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 13:55:57.189307 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 13:55:57.193130 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 13:55:57.196810 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 13:55:57.200308 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 13:55:57.208265 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x8
520 13:55:57.212162 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 13:55:57.220930 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 13:55:57.224173 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 13:55:57.233288 [RTC]rtc_get_frequency_meter,154: input=15, output=760
524 13:55:57.242501 [RTC]rtc_get_frequency_meter,154: input=23, output=941
525 13:55:57.251991 [RTC]rtc_get_frequency_meter,154: input=19, output=850
526 13:55:57.261589 [RTC]rtc_get_frequency_meter,154: input=17, output=806
527 13:55:57.271507 [RTC]rtc_get_frequency_meter,154: input=16, output=781
528 13:55:57.280542 [RTC]rtc_get_frequency_meter,154: input=16, output=781
529 13:55:57.290664 [RTC]rtc_get_frequency_meter,154: input=17, output=805
530 13:55:57.294329 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
531 13:55:57.301326 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
532 13:55:57.301463 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 13:55:57.308176 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 13:55:57.312241 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 13:55:57.316554 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 13:55:57.320264 ADC[4]: Raw value=906942 ID=7
537 13:55:57.320396 ADC[3]: Raw value=213441 ID=1
538 13:55:57.323725 RAM Code: 0x71
539 13:55:57.327431 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 13:55:57.334537 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 13:55:57.341805 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 13:55:57.349080 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 13:55:57.352469 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 13:55:57.356338 in-header: 03 07 00 00 08 00 00 00
545 13:55:57.356449 in-data: aa e4 47 04 13 02 00 00
546 13:55:57.359958 Chrome EC: UHEPI supported
547 13:55:57.367654 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 13:55:57.371169 in-header: 03 95 00 00 08 00 00 00
549 13:55:57.375294 in-data: 18 20 20 08 00 00 00 00
550 13:55:57.378709 MRC: failed to locate region type 0.
551 13:55:57.382638 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 13:55:57.385992 DRAM-K: Running full calibration
553 13:55:57.393573 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 13:55:57.393711 header.status = 0x0
555 13:55:57.397394 header.version = 0x6 (expected: 0x6)
556 13:55:57.401156 header.size = 0xd00 (expected: 0xd00)
557 13:55:57.405345 header.flags = 0x0
558 13:55:57.408598 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 13:55:57.427595 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 13:55:57.435437 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 13:55:57.435582 dram_init: ddr_geometry: 2
562 13:55:57.439682 [EMI] MDL number = 2
563 13:55:57.439801 [EMI] Get MDL freq = 0
564 13:55:57.443486 dram_init: ddr_type: 0
565 13:55:57.443604 is_discrete_lpddr4: 1
566 13:55:57.446795 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 13:55:57.446922
568 13:55:57.446996
569 13:55:57.450804 [Bian_co] ETT version 0.0.0.1
570 13:55:57.454114 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 13:55:57.454263
572 13:55:57.458093 dramc_set_vcore_voltage set vcore to 650000
573 13:55:57.462105 Read voltage for 800, 4
574 13:55:57.462250 Vio18 = 0
575 13:55:57.465269 Vcore = 650000
576 13:55:57.465388 Vdram = 0
577 13:55:57.465488 Vddq = 0
578 13:55:57.465582 Vmddr = 0
579 13:55:57.469152 dram_init: config_dvfs: 1
580 13:55:57.472688 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 13:55:57.480139 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 13:55:57.484410 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
583 13:55:57.487793 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
584 13:55:57.491659 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
585 13:55:57.495334 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
586 13:55:57.498951 MEM_TYPE=3, freq_sel=18
587 13:55:57.499094 sv_algorithm_assistance_LP4_1600
588 13:55:57.505710 ============ PULL DRAM RESETB DOWN ============
589 13:55:57.509588 ========== PULL DRAM RESETB DOWN end =========
590 13:55:57.512489 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 13:55:57.516388 ===================================
592 13:55:57.520410 LPDDR4 DRAM CONFIGURATION
593 13:55:57.523500 ===================================
594 13:55:57.523620 EX_ROW_EN[0] = 0x0
595 13:55:57.527380 EX_ROW_EN[1] = 0x0
596 13:55:57.527469 LP4Y_EN = 0x0
597 13:55:57.530986 WORK_FSP = 0x0
598 13:55:57.531104 WL = 0x2
599 13:55:57.531211 RL = 0x2
600 13:55:57.534285 BL = 0x2
601 13:55:57.538223 RPST = 0x0
602 13:55:57.538317 RD_PRE = 0x0
603 13:55:57.540997 WR_PRE = 0x1
604 13:55:57.541075 WR_PST = 0x0
605 13:55:57.544639 DBI_WR = 0x0
606 13:55:57.544742 DBI_RD = 0x0
607 13:55:57.548154 OTF = 0x1
608 13:55:57.551066 ===================================
609 13:55:57.554362 ===================================
610 13:55:57.554467 ANA top config
611 13:55:57.557734 ===================================
612 13:55:57.561008 DLL_ASYNC_EN = 0
613 13:55:57.561110 ALL_SLAVE_EN = 1
614 13:55:57.564985 NEW_RANK_MODE = 1
615 13:55:57.568224 DLL_IDLE_MODE = 1
616 13:55:57.571459 LP45_APHY_COMB_EN = 1
617 13:55:57.575210 TX_ODT_DIS = 1
618 13:55:57.575323 NEW_8X_MODE = 1
619 13:55:57.578480 ===================================
620 13:55:57.581770 ===================================
621 13:55:57.585759 data_rate = 1600
622 13:55:57.588915 CKR = 1
623 13:55:57.591962 DQ_P2S_RATIO = 8
624 13:55:57.595702 ===================================
625 13:55:57.595855 CA_P2S_RATIO = 8
626 13:55:57.599030 DQ_CA_OPEN = 0
627 13:55:57.602056 DQ_SEMI_OPEN = 0
628 13:55:57.605659 CA_SEMI_OPEN = 0
629 13:55:57.608616 CA_FULL_RATE = 0
630 13:55:57.612108 DQ_CKDIV4_EN = 1
631 13:55:57.612233 CA_CKDIV4_EN = 1
632 13:55:57.615642 CA_PREDIV_EN = 0
633 13:55:57.618646 PH8_DLY = 0
634 13:55:57.622168 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 13:55:57.625840 DQ_AAMCK_DIV = 4
636 13:55:57.629064 CA_AAMCK_DIV = 4
637 13:55:57.629192 CA_ADMCK_DIV = 4
638 13:55:57.632416 DQ_TRACK_CA_EN = 0
639 13:55:57.635374 CA_PICK = 800
640 13:55:57.639116 CA_MCKIO = 800
641 13:55:57.643085 MCKIO_SEMI = 0
642 13:55:57.643228 PLL_FREQ = 3068
643 13:55:57.646339 DQ_UI_PI_RATIO = 32
644 13:55:57.650302 CA_UI_PI_RATIO = 0
645 13:55:57.653991 ===================================
646 13:55:57.658268 ===================================
647 13:55:57.658381 memory_type:LPDDR4
648 13:55:57.661959 GP_NUM : 10
649 13:55:57.662050 SRAM_EN : 1
650 13:55:57.665930 MD32_EN : 0
651 13:55:57.669687 ===================================
652 13:55:57.669787 [ANA_INIT] >>>>>>>>>>>>>>
653 13:55:57.672947 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 13:55:57.676835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 13:55:57.680040 ===================================
656 13:55:57.683343 data_rate = 1600,PCW = 0X7600
657 13:55:57.686691 ===================================
658 13:55:57.690016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 13:55:57.696505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 13:55:57.700226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 13:55:57.706842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 13:55:57.710086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 13:55:57.713414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 13:55:57.713515 [ANA_INIT] flow start
665 13:55:57.717005 [ANA_INIT] PLL >>>>>>>>
666 13:55:57.719905 [ANA_INIT] PLL <<<<<<<<
667 13:55:57.720017 [ANA_INIT] MIDPI >>>>>>>>
668 13:55:57.723670 [ANA_INIT] MIDPI <<<<<<<<
669 13:55:57.726670 [ANA_INIT] DLL >>>>>>>>
670 13:55:57.726766 [ANA_INIT] flow end
671 13:55:57.733487 ============ LP4 DIFF to SE enter ============
672 13:55:57.736928 ============ LP4 DIFF to SE exit ============
673 13:55:57.737028 [ANA_INIT] <<<<<<<<<<<<<
674 13:55:57.739969 [Flow] Enable top DCM control >>>>>
675 13:55:57.743414 [Flow] Enable top DCM control <<<<<
676 13:55:57.746582 Enable DLL master slave shuffle
677 13:55:57.753681 ==============================================================
678 13:55:57.756830 Gating Mode config
679 13:55:57.759871 ==============================================================
680 13:55:57.763946 Config description:
681 13:55:57.773216 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 13:55:57.780501 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 13:55:57.783744 SELPH_MODE 0: By rank 1: By Phase
684 13:55:57.790319 ==============================================================
685 13:55:57.793677 GAT_TRACK_EN = 1
686 13:55:57.796929 RX_GATING_MODE = 2
687 13:55:57.797019 RX_GATING_TRACK_MODE = 2
688 13:55:57.800310 SELPH_MODE = 1
689 13:55:57.803686 PICG_EARLY_EN = 1
690 13:55:57.806721 VALID_LAT_VALUE = 1
691 13:55:57.813295 ==============================================================
692 13:55:57.816507 Enter into Gating configuration >>>>
693 13:55:57.820367 Exit from Gating configuration <<<<
694 13:55:57.823756 Enter into DVFS_PRE_config >>>>>
695 13:55:57.833430 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 13:55:57.837234 Exit from DVFS_PRE_config <<<<<
697 13:55:57.840264 Enter into PICG configuration >>>>
698 13:55:57.843509 Exit from PICG configuration <<<<
699 13:55:57.846703 [RX_INPUT] configuration >>>>>
700 13:55:57.850321 [RX_INPUT] configuration <<<<<
701 13:55:57.853318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 13:55:57.860053 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 13:55:57.866966 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 13:55:57.870156 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 13:55:57.876686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 13:55:57.883835 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 13:55:57.886955 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 13:55:57.890229 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 13:55:57.896892 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 13:55:57.900185 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 13:55:57.903583 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 13:55:57.910106 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 13:55:57.913901 ===================================
714 13:55:57.914020 LPDDR4 DRAM CONFIGURATION
715 13:55:57.917191 ===================================
716 13:55:57.920486 EX_ROW_EN[0] = 0x0
717 13:55:57.920584 EX_ROW_EN[1] = 0x0
718 13:55:57.923634 LP4Y_EN = 0x0
719 13:55:57.923711 WORK_FSP = 0x0
720 13:55:57.926897 WL = 0x2
721 13:55:57.926982 RL = 0x2
722 13:55:57.930134 BL = 0x2
723 13:55:57.933327 RPST = 0x0
724 13:55:57.933407 RD_PRE = 0x0
725 13:55:57.936947 WR_PRE = 0x1
726 13:55:57.937027 WR_PST = 0x0
727 13:55:57.940429 DBI_WR = 0x0
728 13:55:57.940519 DBI_RD = 0x0
729 13:55:57.943602 OTF = 0x1
730 13:55:57.947189 ===================================
731 13:55:57.950437 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 13:55:57.953855 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 13:55:57.957164 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 13:55:57.960187 ===================================
735 13:55:57.963899 LPDDR4 DRAM CONFIGURATION
736 13:55:57.967005 ===================================
737 13:55:57.970229 EX_ROW_EN[0] = 0x10
738 13:55:57.970321 EX_ROW_EN[1] = 0x0
739 13:55:57.973999 LP4Y_EN = 0x0
740 13:55:57.974097 WORK_FSP = 0x0
741 13:55:57.977070 WL = 0x2
742 13:55:57.977154 RL = 0x2
743 13:55:57.980728 BL = 0x2
744 13:55:57.980820 RPST = 0x0
745 13:55:57.983880 RD_PRE = 0x0
746 13:55:57.983963 WR_PRE = 0x1
747 13:55:57.987139 WR_PST = 0x0
748 13:55:57.987220 DBI_WR = 0x0
749 13:55:57.990621 DBI_RD = 0x0
750 13:55:57.990744 OTF = 0x1
751 13:55:57.993941 ===================================
752 13:55:58.000398 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 13:55:58.005089 nWR fixed to 40
754 13:55:58.008408 [ModeRegInit_LP4] CH0 RK0
755 13:55:58.008502 [ModeRegInit_LP4] CH0 RK1
756 13:55:58.011646 [ModeRegInit_LP4] CH1 RK0
757 13:55:58.015615 [ModeRegInit_LP4] CH1 RK1
758 13:55:58.015739 match AC timing 13
759 13:55:58.021791 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 13:55:58.025644 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 13:55:58.028861 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 13:55:58.035562 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 13:55:58.038841 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 13:55:58.038935 [EMI DOE] emi_dcm 0
765 13:55:58.045102 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 13:55:58.045256 ==
767 13:55:58.048673 Dram Type= 6, Freq= 0, CH_0, rank 0
768 13:55:58.052356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 13:55:58.052459 ==
770 13:55:58.058616 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 13:55:58.062344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 13:55:58.072844 [CA 0] Center 36 (6~67) winsize 62
773 13:55:58.075854 [CA 1] Center 36 (6~67) winsize 62
774 13:55:58.079337 [CA 2] Center 34 (4~65) winsize 62
775 13:55:58.082332 [CA 3] Center 33 (3~64) winsize 62
776 13:55:58.085910 [CA 4] Center 33 (3~63) winsize 61
777 13:55:58.089553 [CA 5] Center 32 (2~62) winsize 61
778 13:55:58.089671
779 13:55:58.093190 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 13:55:58.093285
781 13:55:58.096139 [CATrainingPosCal] consider 1 rank data
782 13:55:58.099169 u2DelayCellTimex100 = 270/100 ps
783 13:55:58.102824 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
784 13:55:58.106165 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
785 13:55:58.109557 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
786 13:55:58.116008 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
787 13:55:58.119303 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
788 13:55:58.122563 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
789 13:55:58.122656
790 13:55:58.126206 CA PerBit enable=1, Macro0, CA PI delay=32
791 13:55:58.126295
792 13:55:58.129263 [CBTSetCACLKResult] CA Dly = 32
793 13:55:58.129352 CS Dly: 5 (0~36)
794 13:55:58.129425 ==
795 13:55:58.132556 Dram Type= 6, Freq= 0, CH_0, rank 1
796 13:55:58.139722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 13:55:58.139853 ==
798 13:55:58.143036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 13:55:58.149730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 13:55:58.159047 [CA 0] Center 36 (6~67) winsize 62
801 13:55:58.162098 [CA 1] Center 36 (6~67) winsize 62
802 13:55:58.165829 [CA 2] Center 34 (3~65) winsize 63
803 13:55:58.168917 [CA 3] Center 33 (3~64) winsize 62
804 13:55:58.172106 [CA 4] Center 32 (2~63) winsize 62
805 13:55:58.175483 [CA 5] Center 32 (2~63) winsize 62
806 13:55:58.175604
807 13:55:58.178713 [CmdBusTrainingLP45] Vref(ca) range 1: 32
808 13:55:58.178800
809 13:55:58.182455 [CATrainingPosCal] consider 2 rank data
810 13:55:58.185369 u2DelayCellTimex100 = 270/100 ps
811 13:55:58.189067 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
812 13:55:58.192270 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
813 13:55:58.198838 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
814 13:55:58.202456 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
815 13:55:58.206009 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
816 13:55:58.209082 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
817 13:55:58.209167
818 13:55:58.212138 CA PerBit enable=1, Macro0, CA PI delay=32
819 13:55:58.212270
820 13:55:58.216102 [CBTSetCACLKResult] CA Dly = 32
821 13:55:58.216198 CS Dly: 5 (0~36)
822 13:55:58.216277
823 13:55:58.219398 ----->DramcWriteLeveling(PI) begin...
824 13:55:58.219508 ==
825 13:55:58.222635 Dram Type= 6, Freq= 0, CH_0, rank 0
826 13:55:58.226505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 13:55:58.226623 ==
828 13:55:58.230406 Write leveling (Byte 0): 32 => 32
829 13:55:58.234275 Write leveling (Byte 1): 30 => 30
830 13:55:58.238005 DramcWriteLeveling(PI) end<-----
831 13:55:58.238113
832 13:55:58.238194 ==
833 13:55:58.241233 Dram Type= 6, Freq= 0, CH_0, rank 0
834 13:55:58.244535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 13:55:58.244644 ==
836 13:55:58.247834 [Gating] SW mode calibration
837 13:55:58.255160 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 13:55:58.262201 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 13:55:58.265211 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 13:55:58.268792 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 13:55:58.271715 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 13:55:58.278536 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
843 13:55:58.281836 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 13:55:58.285049 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 13:55:58.291974 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 13:55:58.295509 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 13:55:58.298417 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 13:55:58.305709 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 13:55:58.308933 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 13:55:58.312043 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 13:55:58.318622 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 13:55:58.321771 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 13:55:58.325551 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:55:58.332167 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:55:58.335325 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
856 13:55:58.338671 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 13:55:58.341873 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
858 13:55:58.348906 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:55:58.352349 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:55:58.355387 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:55:58.362014 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:55:58.365421 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:55:58.369066 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:55:58.375512 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:55:58.379176 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
866 13:55:58.382367 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
867 13:55:58.389244 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 13:55:58.392442 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 13:55:58.395720 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 13:55:58.401982 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 13:55:58.405680 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 13:55:58.409215 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
873 13:55:58.415746 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
874 13:55:58.418927 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 13:55:58.422775 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:55:58.425858 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 13:55:58.432555 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 13:55:58.435806 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 13:55:58.438975 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 13:55:58.446219 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
881 13:55:58.449362 0 11 8 | B1->B0 | 2d2d 3d3d | 1 0 | (1 1) (0 0)
882 13:55:58.452648 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
883 13:55:58.459055 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 13:55:58.462357 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 13:55:58.465664 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 13:55:58.472612 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 13:55:58.475926 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 13:55:58.479213 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 13:55:58.486093 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
890 13:55:58.489177 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 13:55:58.493159 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 13:55:58.496006 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 13:55:58.502516 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 13:55:58.505747 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 13:55:58.509730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 13:55:58.516047 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 13:55:58.519698 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 13:55:58.522593 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 13:55:58.529492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 13:55:58.532833 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 13:55:58.536314 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 13:55:58.542593 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:55:58.546224 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:55:58.549355 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:55:58.556437 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
906 13:55:58.556571 Total UI for P1: 0, mck2ui 16
907 13:55:58.562889 best dqsien dly found for B0: ( 0, 14, 6)
908 13:55:58.566330 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
909 13:55:58.569542 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
910 13:55:58.572767 Total UI for P1: 0, mck2ui 16
911 13:55:58.576688 best dqsien dly found for B1: ( 0, 14, 12)
912 13:55:58.580017 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
913 13:55:58.583290 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
914 13:55:58.583372
915 13:55:58.586485 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
916 13:55:58.590057 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
917 13:55:58.593286 [Gating] SW calibration Done
918 13:55:58.593373 ==
919 13:55:58.597132 Dram Type= 6, Freq= 0, CH_0, rank 0
920 13:55:58.600306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 13:55:58.603421 ==
922 13:55:58.603498 RX Vref Scan: 0
923 13:55:58.603569
924 13:55:58.606611 RX Vref 0 -> 0, step: 1
925 13:55:58.606708
926 13:55:58.609956 RX Delay -130 -> 252, step: 16
927 13:55:58.613281 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
928 13:55:58.617163 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
929 13:55:58.620461 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
930 13:55:58.623748 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
931 13:55:58.626980 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
932 13:55:58.633588 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
933 13:55:58.636730 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
934 13:55:58.639855 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
935 13:55:58.643185 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
936 13:55:58.646936 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
937 13:55:58.653407 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
938 13:55:58.656977 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
939 13:55:58.659838 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
940 13:55:58.663509 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
941 13:55:58.670117 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
942 13:55:58.673387 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
943 13:55:58.673468 ==
944 13:55:58.676833 Dram Type= 6, Freq= 0, CH_0, rank 0
945 13:55:58.680615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 13:55:58.680711 ==
947 13:55:58.680823 DQS Delay:
948 13:55:58.683895 DQS0 = 0, DQS1 = 0
949 13:55:58.683975 DQM Delay:
950 13:55:58.687195 DQM0 = 90, DQM1 = 82
951 13:55:58.687269 DQ Delay:
952 13:55:58.690464 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
953 13:55:58.693669 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
954 13:55:58.697287 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
955 13:55:58.700300 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
956 13:55:58.700378
957 13:55:58.700443
958 13:55:58.700519 ==
959 13:55:58.703444 Dram Type= 6, Freq= 0, CH_0, rank 0
960 13:55:58.707211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 13:55:58.707298 ==
962 13:55:58.710438
963 13:55:58.710520
964 13:55:58.710615 TX Vref Scan disable
965 13:55:58.713619 == TX Byte 0 ==
966 13:55:58.716913 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
967 13:55:58.720132 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
968 13:55:58.723995 == TX Byte 1 ==
969 13:55:58.727294 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
970 13:55:58.730753 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
971 13:55:58.730831 ==
972 13:55:58.733983 Dram Type= 6, Freq= 0, CH_0, rank 0
973 13:55:58.740671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 13:55:58.740787 ==
975 13:55:58.752243 TX Vref=22, minBit 7, minWin=27, winSum=447
976 13:55:58.755483 TX Vref=24, minBit 5, minWin=27, winSum=451
977 13:55:58.759420 TX Vref=26, minBit 10, minWin=27, winSum=454
978 13:55:58.762564 TX Vref=28, minBit 8, minWin=28, winSum=461
979 13:55:58.765808 TX Vref=30, minBit 8, minWin=28, winSum=459
980 13:55:58.772541 TX Vref=32, minBit 11, minWin=27, winSum=459
981 13:55:58.776123 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28
982 13:55:58.776221
983 13:55:58.779064 Final TX Range 1 Vref 28
984 13:55:58.779162
985 13:55:58.779260 ==
986 13:55:58.782444 Dram Type= 6, Freq= 0, CH_0, rank 0
987 13:55:58.786082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 13:55:58.786168 ==
989 13:55:58.786264
990 13:55:58.789295
991 13:55:58.789378 TX Vref Scan disable
992 13:55:58.792663 == TX Byte 0 ==
993 13:55:58.795875 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
994 13:55:58.799037 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
995 13:55:58.802757 == TX Byte 1 ==
996 13:55:58.805887 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
997 13:55:58.809151 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
998 13:55:58.812857
999 13:55:58.812984 [DATLAT]
1000 13:55:58.813110 Freq=800, CH0 RK0
1001 13:55:58.813215
1002 13:55:58.816200 DATLAT Default: 0xa
1003 13:55:58.816292 0, 0xFFFF, sum = 0
1004 13:55:58.819344 1, 0xFFFF, sum = 0
1005 13:55:58.819432 2, 0xFFFF, sum = 0
1006 13:55:58.822705 3, 0xFFFF, sum = 0
1007 13:55:58.822789 4, 0xFFFF, sum = 0
1008 13:55:58.826035 5, 0xFFFF, sum = 0
1009 13:55:58.826119 6, 0xFFFF, sum = 0
1010 13:55:58.829289 7, 0xFFFF, sum = 0
1011 13:55:58.829374 8, 0xFFFF, sum = 0
1012 13:55:58.833221 9, 0x0, sum = 1
1013 13:55:58.833305 10, 0x0, sum = 2
1014 13:55:58.836388 11, 0x0, sum = 3
1015 13:55:58.836474 12, 0x0, sum = 4
1016 13:55:58.839775 best_step = 10
1017 13:55:58.839857
1018 13:55:58.839923 ==
1019 13:55:58.843073 Dram Type= 6, Freq= 0, CH_0, rank 0
1020 13:55:58.846257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1021 13:55:58.846350 ==
1022 13:55:58.849794 RX Vref Scan: 1
1023 13:55:58.849875
1024 13:55:58.849942 Set Vref Range= 32 -> 127
1025 13:55:58.850008
1026 13:55:58.852932 RX Vref 32 -> 127, step: 1
1027 13:55:58.853011
1028 13:55:58.856514 RX Delay -95 -> 252, step: 8
1029 13:55:58.856599
1030 13:55:58.859558 Set Vref, RX VrefLevel [Byte0]: 32
1031 13:55:58.862756 [Byte1]: 32
1032 13:55:58.862874
1033 13:55:58.865925 Set Vref, RX VrefLevel [Byte0]: 33
1034 13:55:58.869680 [Byte1]: 33
1035 13:55:58.872972
1036 13:55:58.873053 Set Vref, RX VrefLevel [Byte0]: 34
1037 13:55:58.876016 [Byte1]: 34
1038 13:55:58.880471
1039 13:55:58.880554 Set Vref, RX VrefLevel [Byte0]: 35
1040 13:55:58.883781 [Byte1]: 35
1041 13:55:58.888282
1042 13:55:58.888389 Set Vref, RX VrefLevel [Byte0]: 36
1043 13:55:58.891835 [Byte1]: 36
1044 13:55:58.895918
1045 13:55:58.896001 Set Vref, RX VrefLevel [Byte0]: 37
1046 13:55:58.899394 [Byte1]: 37
1047 13:55:58.903392
1048 13:55:58.903474 Set Vref, RX VrefLevel [Byte0]: 38
1049 13:55:58.906676 [Byte1]: 38
1050 13:55:58.911012
1051 13:55:58.911093 Set Vref, RX VrefLevel [Byte0]: 39
1052 13:55:58.914127 [Byte1]: 39
1053 13:55:58.918501
1054 13:55:58.918583 Set Vref, RX VrefLevel [Byte0]: 40
1055 13:55:58.922128 [Byte1]: 40
1056 13:55:58.925977
1057 13:55:58.926061 Set Vref, RX VrefLevel [Byte0]: 41
1058 13:55:58.929218 [Byte1]: 41
1059 13:55:58.933875
1060 13:55:58.933956 Set Vref, RX VrefLevel [Byte0]: 42
1061 13:55:58.937147 [Byte1]: 42
1062 13:55:58.941110
1063 13:55:58.941192 Set Vref, RX VrefLevel [Byte0]: 43
1064 13:55:58.944468 [Byte1]: 43
1065 13:55:58.948999
1066 13:55:58.949086 Set Vref, RX VrefLevel [Byte0]: 44
1067 13:55:58.952166 [Byte1]: 44
1068 13:55:58.956766
1069 13:55:58.956845 Set Vref, RX VrefLevel [Byte0]: 45
1070 13:55:58.960024 [Byte1]: 45
1071 13:55:58.964262
1072 13:55:58.964411 Set Vref, RX VrefLevel [Byte0]: 46
1073 13:55:58.967271 [Byte1]: 46
1074 13:55:58.971759
1075 13:55:58.971862 Set Vref, RX VrefLevel [Byte0]: 47
1076 13:55:58.974758 [Byte1]: 47
1077 13:55:58.979093
1078 13:55:58.979194 Set Vref, RX VrefLevel [Byte0]: 48
1079 13:55:58.982285 [Byte1]: 48
1080 13:55:58.986663
1081 13:55:58.986778 Set Vref, RX VrefLevel [Byte0]: 49
1082 13:55:58.989872 [Byte1]: 49
1083 13:55:58.994557
1084 13:55:58.994685 Set Vref, RX VrefLevel [Byte0]: 50
1085 13:55:58.997945 [Byte1]: 50
1086 13:55:59.001800
1087 13:55:59.001882 Set Vref, RX VrefLevel [Byte0]: 51
1088 13:55:59.005648 [Byte1]: 51
1089 13:55:59.009414
1090 13:55:59.009494 Set Vref, RX VrefLevel [Byte0]: 52
1091 13:55:59.012912 [Byte1]: 52
1092 13:55:59.017143
1093 13:55:59.017225 Set Vref, RX VrefLevel [Byte0]: 53
1094 13:55:59.020269 [Byte1]: 53
1095 13:55:59.024967
1096 13:55:59.025063 Set Vref, RX VrefLevel [Byte0]: 54
1097 13:55:59.027994 [Byte1]: 54
1098 13:55:59.032113
1099 13:55:59.032225 Set Vref, RX VrefLevel [Byte0]: 55
1100 13:55:59.035812 [Byte1]: 55
1101 13:55:59.040179
1102 13:55:59.040294 Set Vref, RX VrefLevel [Byte0]: 56
1103 13:55:59.043579 [Byte1]: 56
1104 13:55:59.047477
1105 13:55:59.047577 Set Vref, RX VrefLevel [Byte0]: 57
1106 13:55:59.050795 [Byte1]: 57
1107 13:55:59.055220
1108 13:55:59.055310 Set Vref, RX VrefLevel [Byte0]: 58
1109 13:55:59.058398 [Byte1]: 58
1110 13:55:59.063077
1111 13:55:59.063153 Set Vref, RX VrefLevel [Byte0]: 59
1112 13:55:59.066372 [Byte1]: 59
1113 13:55:59.070309
1114 13:55:59.070390 Set Vref, RX VrefLevel [Byte0]: 60
1115 13:55:59.073538 [Byte1]: 60
1116 13:55:59.077941
1117 13:55:59.078017 Set Vref, RX VrefLevel [Byte0]: 61
1118 13:55:59.080997 [Byte1]: 61
1119 13:55:59.085610
1120 13:55:59.085687 Set Vref, RX VrefLevel [Byte0]: 62
1121 13:55:59.088872 [Byte1]: 62
1122 13:55:59.093156
1123 13:55:59.093236 Set Vref, RX VrefLevel [Byte0]: 63
1124 13:55:59.096213 [Byte1]: 63
1125 13:55:59.100625
1126 13:55:59.100717 Set Vref, RX VrefLevel [Byte0]: 64
1127 13:55:59.103803 [Byte1]: 64
1128 13:55:59.108326
1129 13:55:59.108403 Set Vref, RX VrefLevel [Byte0]: 65
1130 13:55:59.111489 [Byte1]: 65
1131 13:55:59.116017
1132 13:55:59.116104 Set Vref, RX VrefLevel [Byte0]: 66
1133 13:55:59.119059 [Byte1]: 66
1134 13:55:59.124059
1135 13:55:59.124140 Set Vref, RX VrefLevel [Byte0]: 67
1136 13:55:59.127215 [Byte1]: 67
1137 13:55:59.131609
1138 13:55:59.131693 Set Vref, RX VrefLevel [Byte0]: 68
1139 13:55:59.134651 [Byte1]: 68
1140 13:55:59.138673
1141 13:55:59.138755 Set Vref, RX VrefLevel [Byte0]: 69
1142 13:55:59.142251 [Byte1]: 69
1143 13:55:59.146304
1144 13:55:59.146403 Set Vref, RX VrefLevel [Byte0]: 70
1145 13:55:59.149419 [Byte1]: 70
1146 13:55:59.154112
1147 13:55:59.154197 Set Vref, RX VrefLevel [Byte0]: 71
1148 13:55:59.157375 [Byte1]: 71
1149 13:55:59.161607
1150 13:55:59.161689 Set Vref, RX VrefLevel [Byte0]: 72
1151 13:55:59.164987 [Byte1]: 72
1152 13:55:59.168887
1153 13:55:59.168966 Set Vref, RX VrefLevel [Byte0]: 73
1154 13:55:59.172360 [Byte1]: 73
1155 13:55:59.176871
1156 13:55:59.176949 Set Vref, RX VrefLevel [Byte0]: 74
1157 13:55:59.180021 [Byte1]: 74
1158 13:55:59.184616
1159 13:55:59.184700 Set Vref, RX VrefLevel [Byte0]: 75
1160 13:55:59.187859 [Byte1]: 75
1161 13:55:59.191692
1162 13:55:59.191771 Set Vref, RX VrefLevel [Byte0]: 76
1163 13:55:59.195379 [Byte1]: 76
1164 13:55:59.199641
1165 13:55:59.199730 Set Vref, RX VrefLevel [Byte0]: 77
1166 13:55:59.202878 [Byte1]: 77
1167 13:55:59.206842
1168 13:55:59.206928 Set Vref, RX VrefLevel [Byte0]: 78
1169 13:55:59.210382 [Byte1]: 78
1170 13:55:59.214978
1171 13:55:59.215071 Final RX Vref Byte 0 = 53 to rank0
1172 13:55:59.217895 Final RX Vref Byte 1 = 62 to rank0
1173 13:55:59.221785 Final RX Vref Byte 0 = 53 to rank1
1174 13:55:59.224892 Final RX Vref Byte 1 = 62 to rank1==
1175 13:55:59.228154 Dram Type= 6, Freq= 0, CH_0, rank 0
1176 13:55:59.231570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 13:55:59.234645 ==
1178 13:55:59.234732 DQS Delay:
1179 13:55:59.234797 DQS0 = 0, DQS1 = 0
1180 13:55:59.238619 DQM Delay:
1181 13:55:59.238704 DQM0 = 91, DQM1 = 86
1182 13:55:59.241854 DQ Delay:
1183 13:55:59.241938 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1184 13:55:59.245117 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1185 13:55:59.248145 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1186 13:55:59.251697 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1187 13:55:59.255078
1188 13:55:59.255166
1189 13:55:59.261961 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1190 13:55:59.265161 CH0 RK0: MR19=606, MR18=4B41
1191 13:55:59.271809 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1192 13:55:59.271902
1193 13:55:59.275097 ----->DramcWriteLeveling(PI) begin...
1194 13:55:59.275197 ==
1195 13:55:59.278329 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 13:55:59.281560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 13:55:59.281649 ==
1198 13:55:59.285396 Write leveling (Byte 0): 34 => 34
1199 13:55:59.288653 Write leveling (Byte 1): 30 => 30
1200 13:55:59.291849 DramcWriteLeveling(PI) end<-----
1201 13:55:59.291994
1202 13:55:59.292063 ==
1203 13:55:59.295251 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 13:55:59.339169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 13:55:59.339352 ==
1206 13:55:59.339502 [Gating] SW mode calibration
1207 13:55:59.340041 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1208 13:55:59.340356 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1209 13:55:59.340454 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1210 13:55:59.340956 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 13:55:59.341209 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1212 13:55:59.341285 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:55:59.341533 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:55:59.341599 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 13:55:59.383396 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 13:55:59.383822 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 13:55:59.383913 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 13:55:59.383991 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 13:55:59.384051 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 13:55:59.384152 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:55:59.384211 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:55:59.384457 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 13:55:59.384559 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:55:59.384665 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:55:59.410407 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:55:59.411054 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:55:59.411685 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1228 13:55:59.412307 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1229 13:55:59.412399 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:55:59.412644 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:55:59.415029 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 13:55:59.418852 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 13:55:59.425514 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 13:55:59.428730 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 13:55:59.432216 0 9 8 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 1)
1236 13:55:59.435125 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 13:55:59.441820 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 13:55:59.445013 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 13:55:59.448533 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 13:55:59.455063 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 13:55:59.458420 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 13:55:59.461892 0 10 4 | B1->B0 | 3131 3333 | 1 1 | (0 0) (1 0)
1243 13:55:59.469520 0 10 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 1)
1244 13:55:59.472682 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 13:55:59.476780 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 13:55:59.480356 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 13:55:59.483966 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 13:55:59.490403 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 13:55:59.494085 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 13:55:59.498113 0 11 4 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
1251 13:55:59.504125 0 11 8 | B1->B0 | 4141 4242 | 0 0 | (0 0) (0 0)
1252 13:55:59.507939 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 13:55:59.511269 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 13:55:59.514478 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 13:55:59.521213 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 13:55:59.524359 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 13:55:59.528117 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 13:55:59.534410 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 13:55:59.537763 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1260 13:55:59.540970 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 13:55:59.547975 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 13:55:59.551180 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 13:55:59.554354 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 13:55:59.560968 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 13:55:59.564205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 13:55:59.567941 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 13:55:59.574649 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 13:55:59.577704 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 13:55:59.581433 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 13:55:59.587821 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 13:55:59.591169 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 13:55:59.594853 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 13:55:59.597894 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 13:55:59.604757 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 13:55:59.608150 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1276 13:55:59.611289 Total UI for P1: 0, mck2ui 16
1277 13:55:59.614802 best dqsien dly found for B0: ( 0, 14, 6)
1278 13:55:59.618152 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 13:55:59.621303 Total UI for P1: 0, mck2ui 16
1280 13:55:59.624604 best dqsien dly found for B1: ( 0, 14, 8)
1281 13:55:59.627978 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1282 13:55:59.631168 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1283 13:55:59.631240
1284 13:55:59.638212 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1285 13:55:59.641516 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1286 13:55:59.641601 [Gating] SW calibration Done
1287 13:55:59.641666 ==
1288 13:55:59.644653 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 13:55:59.651758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 13:55:59.651857 ==
1291 13:55:59.651934 RX Vref Scan: 0
1292 13:55:59.652027
1293 13:55:59.654973 RX Vref 0 -> 0, step: 1
1294 13:55:59.655070
1295 13:55:59.658339 RX Delay -130 -> 252, step: 16
1296 13:55:59.661392 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1297 13:55:59.664739 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1298 13:55:59.668526 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1299 13:55:59.674968 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1300 13:55:59.678127 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1301 13:55:59.681950 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1302 13:55:59.684880 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1303 13:55:59.688523 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1304 13:55:59.691782 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1305 13:55:59.698197 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1306 13:55:59.701602 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1307 13:55:59.704821 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1308 13:55:59.708142 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1309 13:55:59.714991 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1310 13:55:59.718086 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1311 13:55:59.722002 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1312 13:55:59.722090 ==
1313 13:55:59.725012 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 13:55:59.728808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 13:55:59.728892 ==
1316 13:55:59.731489 DQS Delay:
1317 13:55:59.731571 DQS0 = 0, DQS1 = 0
1318 13:55:59.731637 DQM Delay:
1319 13:55:59.734895 DQM0 = 88, DQM1 = 83
1320 13:55:59.734977 DQ Delay:
1321 13:55:59.738069 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1322 13:55:59.741783 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1323 13:55:59.745069 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1324 13:55:59.748470 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1325 13:55:59.748560
1326 13:55:59.748626
1327 13:55:59.748687 ==
1328 13:55:59.751722 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 13:55:59.757979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 13:55:59.758067 ==
1331 13:55:59.758134
1332 13:55:59.758195
1333 13:55:59.758253 TX Vref Scan disable
1334 13:55:59.761882 == TX Byte 0 ==
1335 13:55:59.765824 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1336 13:55:59.768874 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1337 13:55:59.771993 == TX Byte 1 ==
1338 13:55:59.775452 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1339 13:55:59.778703 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1340 13:55:59.781823 ==
1341 13:55:59.785830 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 13:55:59.788988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 13:55:59.789076 ==
1344 13:55:59.801943 TX Vref=22, minBit 8, minWin=27, winSum=446
1345 13:55:59.805140 TX Vref=24, minBit 1, minWin=28, winSum=455
1346 13:55:59.808421 TX Vref=26, minBit 1, minWin=28, winSum=455
1347 13:55:59.811712 TX Vref=28, minBit 8, minWin=27, winSum=456
1348 13:55:59.814981 TX Vref=30, minBit 5, minWin=28, winSum=456
1349 13:55:59.818392 TX Vref=32, minBit 1, minWin=28, winSum=451
1350 13:55:59.825472 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 30
1351 13:55:59.825604
1352 13:55:59.828740 Final TX Range 1 Vref 30
1353 13:55:59.828860
1354 13:55:59.828951 ==
1355 13:55:59.832163 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 13:55:59.834905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 13:55:59.834990 ==
1358 13:55:59.835079
1359 13:55:59.835170
1360 13:55:59.838688 TX Vref Scan disable
1361 13:55:59.841761 == TX Byte 0 ==
1362 13:55:59.845369 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1363 13:55:59.848645 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1364 13:55:59.851908 == TX Byte 1 ==
1365 13:55:59.855276 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1366 13:55:59.858700 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1367 13:55:59.858813
1368 13:55:59.861794 [DATLAT]
1369 13:55:59.861908 Freq=800, CH0 RK1
1370 13:55:59.862001
1371 13:55:59.865525 DATLAT Default: 0xa
1372 13:55:59.865620 0, 0xFFFF, sum = 0
1373 13:55:59.868737 1, 0xFFFF, sum = 0
1374 13:55:59.868823 2, 0xFFFF, sum = 0
1375 13:55:59.872074 3, 0xFFFF, sum = 0
1376 13:55:59.872191 4, 0xFFFF, sum = 0
1377 13:55:59.875168 5, 0xFFFF, sum = 0
1378 13:55:59.875266 6, 0xFFFF, sum = 0
1379 13:55:59.878352 7, 0xFFFF, sum = 0
1380 13:55:59.878450 8, 0xFFFF, sum = 0
1381 13:55:59.881676 9, 0x0, sum = 1
1382 13:55:59.881759 10, 0x0, sum = 2
1383 13:55:59.885479 11, 0x0, sum = 3
1384 13:55:59.885594 12, 0x0, sum = 4
1385 13:55:59.888618 best_step = 10
1386 13:55:59.888700
1387 13:55:59.888763 ==
1388 13:55:59.891964 Dram Type= 6, Freq= 0, CH_0, rank 1
1389 13:55:59.895262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 13:55:59.895345 ==
1391 13:55:59.898624 RX Vref Scan: 0
1392 13:55:59.898707
1393 13:55:59.898785 RX Vref 0 -> 0, step: 1
1394 13:55:59.898845
1395 13:55:59.902168 RX Delay -79 -> 252, step: 8
1396 13:55:59.908744 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1397 13:55:59.912087 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1398 13:55:59.915242 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1399 13:55:59.918589 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1400 13:55:59.921923 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1401 13:55:59.925019 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1402 13:55:59.931644 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1403 13:55:59.935603 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1404 13:55:59.938911 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1405 13:55:59.942157 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1406 13:55:59.945573 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1407 13:55:59.952154 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1408 13:55:59.955410 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1409 13:55:59.958547 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1410 13:55:59.961691 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1411 13:55:59.965638 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1412 13:55:59.968884 ==
1413 13:55:59.972245 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 13:55:59.975414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 13:55:59.975504 ==
1416 13:55:59.975569 DQS Delay:
1417 13:55:59.978928 DQS0 = 0, DQS1 = 0
1418 13:55:59.979012 DQM Delay:
1419 13:55:59.982232 DQM0 = 93, DQM1 = 83
1420 13:55:59.982301 DQ Delay:
1421 13:55:59.985751 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1422 13:55:59.988854 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1423 13:55:59.991744 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1424 13:55:59.995364 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =88
1425 13:55:59.995443
1426 13:55:59.995521
1427 13:56:00.002045 [DQSOSCAuto] RK1, (LSB)MR18= 0x4617, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1428 13:56:00.005397 CH0 RK1: MR19=606, MR18=4617
1429 13:56:00.011717 CH0_RK1: MR19=0x606, MR18=0x4617, DQSOSC=392, MR23=63, INC=96, DEC=64
1430 13:56:00.015023 [RxdqsGatingPostProcess] freq 800
1431 13:56:00.021915 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1432 13:56:00.022049 Pre-setting of DQS Precalculation
1433 13:56:00.028761 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1434 13:56:00.028858 ==
1435 13:56:00.031918 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 13:56:00.034986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 13:56:00.035103 ==
1438 13:56:00.041639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1439 13:56:00.048277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1440 13:56:00.056231 [CA 0] Center 36 (6~67) winsize 62
1441 13:56:00.060119 [CA 1] Center 36 (6~67) winsize 62
1442 13:56:00.063319 [CA 2] Center 34 (4~65) winsize 62
1443 13:56:00.066611 [CA 3] Center 34 (4~65) winsize 62
1444 13:56:00.069947 [CA 4] Center 34 (4~65) winsize 62
1445 13:56:00.073289 [CA 5] Center 34 (4~64) winsize 61
1446 13:56:00.073390
1447 13:56:00.076708 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1448 13:56:00.076789
1449 13:56:00.079916 [CATrainingPosCal] consider 1 rank data
1450 13:56:00.083062 u2DelayCellTimex100 = 270/100 ps
1451 13:56:00.086692 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 13:56:00.089939 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1453 13:56:00.093486 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 13:56:00.099744 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1455 13:56:00.103436 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 13:56:00.106668 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1457 13:56:00.106771
1458 13:56:00.109949 CA PerBit enable=1, Macro0, CA PI delay=34
1459 13:56:00.110025
1460 13:56:00.113066 [CBTSetCACLKResult] CA Dly = 34
1461 13:56:00.113169 CS Dly: 6 (0~37)
1462 13:56:00.113260 ==
1463 13:56:00.116639 Dram Type= 6, Freq= 0, CH_1, rank 1
1464 13:56:00.123305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 13:56:00.123391 ==
1466 13:56:00.127039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 13:56:00.133845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 13:56:00.142441 [CA 0] Center 36 (6~67) winsize 62
1469 13:56:00.146366 [CA 1] Center 36 (6~67) winsize 62
1470 13:56:00.149722 [CA 2] Center 35 (4~66) winsize 63
1471 13:56:00.153674 [CA 3] Center 35 (5~65) winsize 61
1472 13:56:00.157748 [CA 4] Center 35 (5~66) winsize 62
1473 13:56:00.161593 [CA 5] Center 34 (4~65) winsize 62
1474 13:56:00.161701
1475 13:56:00.164819 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1476 13:56:00.164931
1477 13:56:00.168180 [CATrainingPosCal] consider 2 rank data
1478 13:56:00.171510 u2DelayCellTimex100 = 270/100 ps
1479 13:56:00.174853 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 13:56:00.178189 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 13:56:00.181615 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 13:56:00.184790 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1483 13:56:00.188193 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1484 13:56:00.192222 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1485 13:56:00.192322
1486 13:56:00.195413 CA PerBit enable=1, Macro0, CA PI delay=34
1487 13:56:00.195499
1488 13:56:00.198400 [CBTSetCACLKResult] CA Dly = 34
1489 13:56:00.201787 CS Dly: 6 (0~38)
1490 13:56:00.201908
1491 13:56:00.204952 ----->DramcWriteLeveling(PI) begin...
1492 13:56:00.205076 ==
1493 13:56:00.208206 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 13:56:00.211785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1495 13:56:00.211890 ==
1496 13:56:00.215403 Write leveling (Byte 0): 27 => 27
1497 13:56:00.218446 Write leveling (Byte 1): 28 => 28
1498 13:56:00.221906 DramcWriteLeveling(PI) end<-----
1499 13:56:00.222008
1500 13:56:00.222088 ==
1501 13:56:00.225150 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 13:56:00.228483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1503 13:56:00.228584 ==
1504 13:56:00.232122 [Gating] SW mode calibration
1505 13:56:00.238701 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1506 13:56:00.245582 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1507 13:56:00.248490 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1508 13:56:00.252106 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1509 13:56:00.258893 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 13:56:00.262276 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 13:56:00.265460 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 13:56:00.271797 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 13:56:00.275159 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 13:56:00.278425 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 13:56:00.281772 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 13:56:00.288366 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 13:56:00.291728 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:56:00.294990 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:56:00.302254 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:56:00.305494 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:56:00.308498 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:56:00.315556 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:56:00.318873 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1524 13:56:00.321837 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1525 13:56:00.328938 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:56:00.332015 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:56:00.335249 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:56:00.342143 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:56:00.345346 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:56:00.348398 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 13:56:00.355261 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 13:56:00.358619 0 9 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
1533 13:56:00.361757 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1534 13:56:00.368737 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 13:56:00.372134 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 13:56:00.375437 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 13:56:00.378323 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 13:56:00.385172 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 13:56:00.388424 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1540 13:56:00.392271 0 10 4 | B1->B0 | 3030 2a2a | 0 1 | (0 1) (1 0)
1541 13:56:00.398806 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1542 13:56:00.402083 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 13:56:00.405530 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 13:56:00.412093 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 13:56:00.415392 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 13:56:00.418584 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 13:56:00.425709 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 13:56:00.429224 0 11 4 | B1->B0 | 2626 3939 | 0 0 | (0 0) (0 0)
1549 13:56:00.432073 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 13:56:00.438613 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 13:56:00.442340 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 13:56:00.445477 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 13:56:00.452170 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 13:56:00.455297 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 13:56:00.459102 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 13:56:00.462239 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1557 13:56:00.469053 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 13:56:00.472060 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 13:56:00.475718 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 13:56:00.482315 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 13:56:00.485592 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 13:56:00.489039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 13:56:00.495598 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 13:56:00.498623 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 13:56:00.501976 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 13:56:00.508662 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 13:56:00.511986 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 13:56:00.515918 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 13:56:00.521921 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 13:56:00.525878 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 13:56:00.529120 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1572 13:56:00.535934 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1573 13:56:00.539045 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 13:56:00.541921 Total UI for P1: 0, mck2ui 16
1575 13:56:00.545676 best dqsien dly found for B0: ( 0, 14, 4)
1576 13:56:00.548699 Total UI for P1: 0, mck2ui 16
1577 13:56:00.552306 best dqsien dly found for B1: ( 0, 14, 2)
1578 13:56:00.555895 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1579 13:56:00.559142 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1580 13:56:00.559247
1581 13:56:00.562784 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1582 13:56:00.565373 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1583 13:56:00.569260 [Gating] SW calibration Done
1584 13:56:00.569344 ==
1585 13:56:00.572580 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 13:56:00.575874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 13:56:00.575983 ==
1588 13:56:00.579222 RX Vref Scan: 0
1589 13:56:00.579324
1590 13:56:00.579424 RX Vref 0 -> 0, step: 1
1591 13:56:00.579488
1592 13:56:00.582605 RX Delay -130 -> 252, step: 16
1593 13:56:00.589123 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1594 13:56:00.592380 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1595 13:56:00.595630 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1596 13:56:00.598753 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1597 13:56:00.602360 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1598 13:56:00.605767 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1599 13:56:00.612280 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1600 13:56:00.615808 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1601 13:56:00.619008 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1602 13:56:00.622694 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1603 13:56:00.625612 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1604 13:56:00.632227 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1605 13:56:00.635565 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1606 13:56:00.638900 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1607 13:56:00.642261 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1608 13:56:00.645594 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1609 13:56:00.649444 ==
1610 13:56:00.652600 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 13:56:00.655891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 13:56:00.655976 ==
1613 13:56:00.656057 DQS Delay:
1614 13:56:00.658965 DQS0 = 0, DQS1 = 0
1615 13:56:00.659066 DQM Delay:
1616 13:56:00.662367 DQM0 = 93, DQM1 = 89
1617 13:56:00.662466 DQ Delay:
1618 13:56:00.665941 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1619 13:56:00.669030 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1620 13:56:00.672229 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1621 13:56:00.675616 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1622 13:56:00.675716
1623 13:56:00.675812
1624 13:56:00.675903 ==
1625 13:56:00.678982 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 13:56:00.682198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 13:56:00.682302 ==
1628 13:56:00.682383
1629 13:56:00.682488
1630 13:56:00.685675 TX Vref Scan disable
1631 13:56:00.688916 == TX Byte 0 ==
1632 13:56:00.692268 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1633 13:56:00.695589 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1634 13:56:00.698982 == TX Byte 1 ==
1635 13:56:00.702827 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1636 13:56:00.705638 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1637 13:56:00.705723 ==
1638 13:56:00.709721 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 13:56:00.712900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 13:56:00.712986 ==
1641 13:56:00.726636 TX Vref=22, minBit 1, minWin=26, winSum=438
1642 13:56:00.730195 TX Vref=24, minBit 1, minWin=26, winSum=444
1643 13:56:00.733714 TX Vref=26, minBit 1, minWin=26, winSum=445
1644 13:56:00.736932 TX Vref=28, minBit 1, minWin=27, winSum=447
1645 13:56:00.740230 TX Vref=30, minBit 1, minWin=27, winSum=452
1646 13:56:00.743682 TX Vref=32, minBit 1, minWin=27, winSum=451
1647 13:56:00.750474 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1648 13:56:00.750579
1649 13:56:00.753936 Final TX Range 1 Vref 30
1650 13:56:00.754043
1651 13:56:00.754136 ==
1652 13:56:00.757177 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 13:56:00.760476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 13:56:00.760581 ==
1655 13:56:00.760672
1656 13:56:00.760771
1657 13:56:00.763673 TX Vref Scan disable
1658 13:56:00.766909 == TX Byte 0 ==
1659 13:56:00.770705 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1660 13:56:00.773878 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1661 13:56:00.777089 == TX Byte 1 ==
1662 13:56:00.780181 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1663 13:56:00.783728 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1664 13:56:00.783820
1665 13:56:00.786877 [DATLAT]
1666 13:56:00.786965 Freq=800, CH1 RK0
1667 13:56:00.787054
1668 13:56:00.790160 DATLAT Default: 0xa
1669 13:56:00.790248 0, 0xFFFF, sum = 0
1670 13:56:00.793711 1, 0xFFFF, sum = 0
1671 13:56:00.793801 2, 0xFFFF, sum = 0
1672 13:56:00.796887 3, 0xFFFF, sum = 0
1673 13:56:00.796973 4, 0xFFFF, sum = 0
1674 13:56:00.800575 5, 0xFFFF, sum = 0
1675 13:56:00.800664 6, 0xFFFF, sum = 0
1676 13:56:00.803764 7, 0xFFFF, sum = 0
1677 13:56:00.803852 8, 0xFFFF, sum = 0
1678 13:56:00.807028 9, 0x0, sum = 1
1679 13:56:00.807114 10, 0x0, sum = 2
1680 13:56:00.810336 11, 0x0, sum = 3
1681 13:56:00.810422 12, 0x0, sum = 4
1682 13:56:00.813508 best_step = 10
1683 13:56:00.813593
1684 13:56:00.813659 ==
1685 13:56:00.816825 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 13:56:00.820072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 13:56:00.820159 ==
1688 13:56:00.823585 RX Vref Scan: 1
1689 13:56:00.823674
1690 13:56:00.823762 Set Vref Range= 32 -> 127
1691 13:56:00.823845
1692 13:56:00.826600 RX Vref 32 -> 127, step: 1
1693 13:56:00.826704
1694 13:56:00.830522 RX Delay -63 -> 252, step: 8
1695 13:56:00.830615
1696 13:56:00.833803 Set Vref, RX VrefLevel [Byte0]: 32
1697 13:56:00.836948 [Byte1]: 32
1698 13:56:00.837038
1699 13:56:00.840130 Set Vref, RX VrefLevel [Byte0]: 33
1700 13:56:00.843415 [Byte1]: 33
1701 13:56:00.846979
1702 13:56:00.847071 Set Vref, RX VrefLevel [Byte0]: 34
1703 13:56:00.850017 [Byte1]: 34
1704 13:56:00.854284
1705 13:56:00.854390 Set Vref, RX VrefLevel [Byte0]: 35
1706 13:56:00.857738 [Byte1]: 35
1707 13:56:00.862034
1708 13:56:00.862127 Set Vref, RX VrefLevel [Byte0]: 36
1709 13:56:00.865399 [Byte1]: 36
1710 13:56:00.869297
1711 13:56:00.869386 Set Vref, RX VrefLevel [Byte0]: 37
1712 13:56:00.872615 [Byte1]: 37
1713 13:56:00.876995
1714 13:56:00.877083 Set Vref, RX VrefLevel [Byte0]: 38
1715 13:56:00.880204 [Byte1]: 38
1716 13:56:00.884195
1717 13:56:00.884294 Set Vref, RX VrefLevel [Byte0]: 39
1718 13:56:00.887442 [Byte1]: 39
1719 13:56:00.892055
1720 13:56:00.892148 Set Vref, RX VrefLevel [Byte0]: 40
1721 13:56:00.895010 [Byte1]: 40
1722 13:56:00.899466
1723 13:56:00.899556 Set Vref, RX VrefLevel [Byte0]: 41
1724 13:56:00.902505 [Byte1]: 41
1725 13:56:00.906605
1726 13:56:00.906695 Set Vref, RX VrefLevel [Byte0]: 42
1727 13:56:00.910301 [Byte1]: 42
1728 13:56:00.914212
1729 13:56:00.914309 Set Vref, RX VrefLevel [Byte0]: 43
1730 13:56:00.917757 [Byte1]: 43
1731 13:56:00.921825
1732 13:56:00.921950 Set Vref, RX VrefLevel [Byte0]: 44
1733 13:56:00.925010 [Byte1]: 44
1734 13:56:00.929692
1735 13:56:00.929781 Set Vref, RX VrefLevel [Byte0]: 45
1736 13:56:00.932791 [Byte1]: 45
1737 13:56:00.936951
1738 13:56:00.937060 Set Vref, RX VrefLevel [Byte0]: 46
1739 13:56:00.940112 [Byte1]: 46
1740 13:56:00.944611
1741 13:56:00.944696 Set Vref, RX VrefLevel [Byte0]: 47
1742 13:56:00.947850 [Byte1]: 47
1743 13:56:00.951703
1744 13:56:00.951790 Set Vref, RX VrefLevel [Byte0]: 48
1745 13:56:00.954827 [Byte1]: 48
1746 13:56:00.959404
1747 13:56:00.959490 Set Vref, RX VrefLevel [Byte0]: 49
1748 13:56:00.962400 [Byte1]: 49
1749 13:56:00.966825
1750 13:56:00.966910 Set Vref, RX VrefLevel [Byte0]: 50
1751 13:56:00.970346 [Byte1]: 50
1752 13:56:00.974105
1753 13:56:00.974192 Set Vref, RX VrefLevel [Byte0]: 51
1754 13:56:00.977330 [Byte1]: 51
1755 13:56:00.981880
1756 13:56:00.981968 Set Vref, RX VrefLevel [Byte0]: 52
1757 13:56:00.985023 [Byte1]: 52
1758 13:56:00.989639
1759 13:56:00.989740 Set Vref, RX VrefLevel [Byte0]: 53
1760 13:56:00.992895 [Byte1]: 53
1761 13:56:00.996887
1762 13:56:00.996993 Set Vref, RX VrefLevel [Byte0]: 54
1763 13:56:01.000102 [Byte1]: 54
1764 13:56:01.004012
1765 13:56:01.004113 Set Vref, RX VrefLevel [Byte0]: 55
1766 13:56:01.008013 [Byte1]: 55
1767 13:56:01.011814
1768 13:56:01.011915 Set Vref, RX VrefLevel [Byte0]: 56
1769 13:56:01.015014 [Byte1]: 56
1770 13:56:01.019318
1771 13:56:01.019418 Set Vref, RX VrefLevel [Byte0]: 57
1772 13:56:01.022429 [Byte1]: 57
1773 13:56:01.026676
1774 13:56:01.026777 Set Vref, RX VrefLevel [Byte0]: 58
1775 13:56:01.030133 [Byte1]: 58
1776 13:56:01.034362
1777 13:56:01.034463 Set Vref, RX VrefLevel [Byte0]: 59
1778 13:56:01.037732 [Byte1]: 59
1779 13:56:01.041485
1780 13:56:01.041570 Set Vref, RX VrefLevel [Byte0]: 60
1781 13:56:01.044801 [Byte1]: 60
1782 13:56:01.049244
1783 13:56:01.049334 Set Vref, RX VrefLevel [Byte0]: 61
1784 13:56:01.052778 [Byte1]: 61
1785 13:56:01.056646
1786 13:56:01.056730 Set Vref, RX VrefLevel [Byte0]: 62
1787 13:56:01.060428 [Byte1]: 62
1788 13:56:01.064359
1789 13:56:01.064444 Set Vref, RX VrefLevel [Byte0]: 63
1790 13:56:01.067714 [Byte1]: 63
1791 13:56:01.071663
1792 13:56:01.071749 Set Vref, RX VrefLevel [Byte0]: 64
1793 13:56:01.074793 [Byte1]: 64
1794 13:56:01.079050
1795 13:56:01.079138 Set Vref, RX VrefLevel [Byte0]: 65
1796 13:56:01.082912 [Byte1]: 65
1797 13:56:01.086844
1798 13:56:01.086937 Set Vref, RX VrefLevel [Byte0]: 66
1799 13:56:01.089959 [Byte1]: 66
1800 13:56:01.094360
1801 13:56:01.094452 Set Vref, RX VrefLevel [Byte0]: 67
1802 13:56:01.097544 [Byte1]: 67
1803 13:56:01.101672
1804 13:56:01.101762 Set Vref, RX VrefLevel [Byte0]: 68
1805 13:56:01.104900 [Byte1]: 68
1806 13:56:01.109486
1807 13:56:01.109574 Set Vref, RX VrefLevel [Byte0]: 69
1808 13:56:01.112761 [Byte1]: 69
1809 13:56:01.116620
1810 13:56:01.116707 Set Vref, RX VrefLevel [Byte0]: 70
1811 13:56:01.119917 [Byte1]: 70
1812 13:56:01.124448
1813 13:56:01.124542 Set Vref, RX VrefLevel [Byte0]: 71
1814 13:56:01.127635 [Byte1]: 71
1815 13:56:01.131581
1816 13:56:01.131670 Set Vref, RX VrefLevel [Byte0]: 72
1817 13:56:01.134856 [Byte1]: 72
1818 13:56:01.139226
1819 13:56:01.139313 Set Vref, RX VrefLevel [Byte0]: 73
1820 13:56:01.142681 [Byte1]: 73
1821 13:56:01.146505
1822 13:56:01.146596 Final RX Vref Byte 0 = 59 to rank0
1823 13:56:01.150389 Final RX Vref Byte 1 = 57 to rank0
1824 13:56:01.153422 Final RX Vref Byte 0 = 59 to rank1
1825 13:56:01.156955 Final RX Vref Byte 1 = 57 to rank1==
1826 13:56:01.160220 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 13:56:01.163537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 13:56:01.166695 ==
1829 13:56:01.166810 DQS Delay:
1830 13:56:01.166905 DQS0 = 0, DQS1 = 0
1831 13:56:01.170272 DQM Delay:
1832 13:56:01.170381 DQM0 = 95, DQM1 = 90
1833 13:56:01.173942 DQ Delay:
1834 13:56:01.174022 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1835 13:56:01.177087 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1836 13:56:01.180345 DQ8 =80, DQ9 =84, DQ10 =88, DQ11 =84
1837 13:56:01.186877 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1838 13:56:01.186971
1839 13:56:01.187038
1840 13:56:01.193517 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1841 13:56:01.197101 CH1 RK0: MR19=606, MR18=304D
1842 13:56:01.203380 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1843 13:56:01.203485
1844 13:56:01.206666 ----->DramcWriteLeveling(PI) begin...
1845 13:56:01.206761 ==
1846 13:56:01.210723 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 13:56:01.213876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 13:56:01.213966 ==
1849 13:56:01.217024 Write leveling (Byte 0): 28 => 28
1850 13:56:01.220352 Write leveling (Byte 1): 27 => 27
1851 13:56:01.223661 DramcWriteLeveling(PI) end<-----
1852 13:56:01.223749
1853 13:56:01.223815 ==
1854 13:56:01.226933 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 13:56:01.230255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 13:56:01.230342 ==
1857 13:56:01.233492 [Gating] SW mode calibration
1858 13:56:01.240059 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 13:56:01.247186 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 13:56:01.250456 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1861 13:56:01.253668 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1862 13:56:01.260376 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:56:01.263694 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:56:01.266724 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:56:01.273680 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:56:01.277127 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:56:01.280520 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 13:56:01.287217 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 13:56:01.290830 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 13:56:01.293656 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 13:56:01.296902 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 13:56:01.303872 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:56:01.306997 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:56:01.310555 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:56:01.317314 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 13:56:01.320713 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 13:56:01.324025 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1878 13:56:01.330653 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:56:01.334486 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 13:56:01.337850 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:56:01.344158 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:56:01.347418 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:56:01.350649 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 13:56:01.357269 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 13:56:01.360624 0 9 4 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
1886 13:56:01.363955 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
1887 13:56:01.367859 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 13:56:01.374206 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 13:56:01.377328 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 13:56:01.380622 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 13:56:01.387746 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 13:56:01.390712 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 13:56:01.394212 0 10 4 | B1->B0 | 2727 2f2f | 1 1 | (1 0) (1 0)
1894 13:56:01.401303 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1895 13:56:01.404072 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 13:56:01.407381 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 13:56:01.414133 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 13:56:01.417353 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 13:56:01.420644 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 13:56:01.427768 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1901 13:56:01.431153 0 11 4 | B1->B0 | 3d3d 2929 | 0 0 | (0 0) (0 0)
1902 13:56:01.434354 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 13:56:01.441378 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 13:56:01.444674 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 13:56:01.447861 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 13:56:01.450927 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 13:56:01.457853 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 13:56:01.461170 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 13:56:01.464448 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1910 13:56:01.470890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1911 13:56:01.474167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 13:56:01.477983 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 13:56:01.484625 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 13:56:01.487787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 13:56:01.490932 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 13:56:01.498270 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 13:56:01.501120 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 13:56:01.504249 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 13:56:01.511346 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 13:56:01.514391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 13:56:01.518225 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 13:56:01.521201 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 13:56:01.528080 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 13:56:01.531198 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1925 13:56:01.535012 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1926 13:56:01.541485 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 13:56:01.545179 Total UI for P1: 0, mck2ui 16
1928 13:56:01.548187 best dqsien dly found for B0: ( 0, 14, 4)
1929 13:56:01.548321 Total UI for P1: 0, mck2ui 16
1930 13:56:01.555041 best dqsien dly found for B1: ( 0, 14, 2)
1931 13:56:01.558247 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1932 13:56:01.561802 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1933 13:56:01.561887
1934 13:56:01.564840 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1935 13:56:01.568146 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1936 13:56:01.571329 [Gating] SW calibration Done
1937 13:56:01.571429 ==
1938 13:56:01.574506 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 13:56:01.577854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 13:56:01.577937 ==
1941 13:56:01.581632 RX Vref Scan: 0
1942 13:56:01.581715
1943 13:56:01.581780 RX Vref 0 -> 0, step: 1
1944 13:56:01.581868
1945 13:56:01.584966 RX Delay -130 -> 252, step: 16
1946 13:56:01.588113 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1947 13:56:01.594642 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1948 13:56:01.597982 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1949 13:56:01.601297 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1950 13:56:01.605285 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1951 13:56:01.608466 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1952 13:56:01.611432 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1953 13:56:01.618589 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1954 13:56:01.621821 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1955 13:56:01.625029 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1956 13:56:01.628385 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1957 13:56:01.631475 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1958 13:56:01.638506 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1959 13:56:01.641535 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1960 13:56:01.645037 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1961 13:56:01.648357 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1962 13:56:01.648466 ==
1963 13:56:01.652024 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 13:56:01.658477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 13:56:01.658601 ==
1966 13:56:01.658701 DQS Delay:
1967 13:56:01.661367 DQS0 = 0, DQS1 = 0
1968 13:56:01.661444 DQM Delay:
1969 13:56:01.661535 DQM0 = 93, DQM1 = 89
1970 13:56:01.664723 DQ Delay:
1971 13:56:01.668182 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1972 13:56:01.671851 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1973 13:56:01.675067 DQ8 =85, DQ9 =77, DQ10 =85, DQ11 =85
1974 13:56:01.678214 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1975 13:56:01.678333
1976 13:56:01.678398
1977 13:56:01.678458 ==
1978 13:56:01.681963 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 13:56:01.685278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 13:56:01.685377 ==
1981 13:56:01.685442
1982 13:56:01.685533
1983 13:56:01.688459 TX Vref Scan disable
1984 13:56:01.691754 == TX Byte 0 ==
1985 13:56:01.695126 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1986 13:56:01.698326 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1987 13:56:01.701636 == TX Byte 1 ==
1988 13:56:01.704910 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1989 13:56:01.708234 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1990 13:56:01.708359 ==
1991 13:56:01.711432 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 13:56:01.715244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 13:56:01.715391 ==
1994 13:56:01.729246 TX Vref=22, minBit 0, minWin=27, winSum=443
1995 13:56:01.732537 TX Vref=24, minBit 2, minWin=27, winSum=446
1996 13:56:01.735929 TX Vref=26, minBit 2, minWin=27, winSum=448
1997 13:56:01.739126 TX Vref=28, minBit 2, minWin=27, winSum=450
1998 13:56:01.743052 TX Vref=30, minBit 2, minWin=27, winSum=450
1999 13:56:01.746280 TX Vref=32, minBit 2, minWin=27, winSum=449
2000 13:56:01.753200 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
2001 13:56:01.753313
2002 13:56:01.756058 Final TX Range 1 Vref 28
2003 13:56:01.756163
2004 13:56:01.756262 ==
2005 13:56:01.759586 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 13:56:01.762918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 13:56:01.763029 ==
2008 13:56:01.763123
2009 13:56:01.763213
2010 13:56:01.766049 TX Vref Scan disable
2011 13:56:01.769725 == TX Byte 0 ==
2012 13:56:01.773056 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2013 13:56:01.776376 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2014 13:56:01.779552 == TX Byte 1 ==
2015 13:56:01.782747 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2016 13:56:01.786351 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2017 13:56:01.786448
2018 13:56:01.789245 [DATLAT]
2019 13:56:01.789351 Freq=800, CH1 RK1
2020 13:56:01.789440
2021 13:56:01.792634 DATLAT Default: 0xa
2022 13:56:01.792718 0, 0xFFFF, sum = 0
2023 13:56:01.796440 1, 0xFFFF, sum = 0
2024 13:56:01.796526 2, 0xFFFF, sum = 0
2025 13:56:01.800105 3, 0xFFFF, sum = 0
2026 13:56:01.800190 4, 0xFFFF, sum = 0
2027 13:56:01.802976 5, 0xFFFF, sum = 0
2028 13:56:01.803062 6, 0xFFFF, sum = 0
2029 13:56:01.806321 7, 0xFFFF, sum = 0
2030 13:56:01.806406 8, 0xFFFF, sum = 0
2031 13:56:01.809830 9, 0x0, sum = 1
2032 13:56:01.809916 10, 0x0, sum = 2
2033 13:56:01.812969 11, 0x0, sum = 3
2034 13:56:01.813055 12, 0x0, sum = 4
2035 13:56:01.816366 best_step = 10
2036 13:56:01.816451
2037 13:56:01.816518 ==
2038 13:56:01.819618 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 13:56:01.822667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 13:56:01.822752 ==
2041 13:56:01.826394 RX Vref Scan: 0
2042 13:56:01.826477
2043 13:56:01.826545 RX Vref 0 -> 0, step: 1
2044 13:56:01.826607
2045 13:56:01.829992 RX Delay -79 -> 252, step: 8
2046 13:56:01.833415 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
2047 13:56:01.839933 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2048 13:56:01.843321 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2049 13:56:01.846704 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2050 13:56:01.849900 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2051 13:56:01.853249 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2052 13:56:01.856579 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2053 13:56:01.863130 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2054 13:56:01.866399 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2055 13:56:01.869673 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2056 13:56:01.873351 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2057 13:56:01.876187 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2058 13:56:01.882922 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2059 13:56:01.886275 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2060 13:56:01.889893 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2061 13:56:01.893236 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2062 13:56:01.893326 ==
2063 13:56:01.896439 Dram Type= 6, Freq= 0, CH_1, rank 1
2064 13:56:01.902913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2065 13:56:01.902999 ==
2066 13:56:01.903068 DQS Delay:
2067 13:56:01.905946 DQS0 = 0, DQS1 = 0
2068 13:56:01.906031 DQM Delay:
2069 13:56:01.906095 DQM0 = 97, DQM1 = 91
2070 13:56:01.909597 DQ Delay:
2071 13:56:01.912737 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2072 13:56:01.916260 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2073 13:56:01.919997 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2074 13:56:01.923091 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2075 13:56:01.923176
2076 13:56:01.923245
2077 13:56:01.929373 [DQSOSCAuto] RK1, (LSB)MR18= 0x450e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2078 13:56:01.933178 CH1 RK1: MR19=606, MR18=450E
2079 13:56:01.939659 CH1_RK1: MR19=0x606, MR18=0x450E, DQSOSC=392, MR23=63, INC=96, DEC=64
2080 13:56:01.942774 [RxdqsGatingPostProcess] freq 800
2081 13:56:01.946176 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2082 13:56:01.949455 Pre-setting of DQS Precalculation
2083 13:56:01.956518 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2084 13:56:01.963007 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2085 13:56:01.969708 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2086 13:56:01.969796
2087 13:56:01.969862
2088 13:56:01.972981 [Calibration Summary] 1600 Mbps
2089 13:56:01.973063 CH 0, Rank 0
2090 13:56:01.976253 SW Impedance : PASS
2091 13:56:01.979536 DUTY Scan : NO K
2092 13:56:01.979619 ZQ Calibration : PASS
2093 13:56:01.983537 Jitter Meter : NO K
2094 13:56:01.986623 CBT Training : PASS
2095 13:56:01.986753 Write leveling : PASS
2096 13:56:01.989614 RX DQS gating : PASS
2097 13:56:01.993200 RX DQ/DQS(RDDQC) : PASS
2098 13:56:01.993315 TX DQ/DQS : PASS
2099 13:56:01.996604 RX DATLAT : PASS
2100 13:56:01.999916 RX DQ/DQS(Engine): PASS
2101 13:56:01.999998 TX OE : NO K
2102 13:56:02.000071 All Pass.
2103 13:56:02.003138
2104 13:56:02.003282 CH 0, Rank 1
2105 13:56:02.003378 SW Impedance : PASS
2106 13:56:02.006352 DUTY Scan : NO K
2107 13:56:02.010032 ZQ Calibration : PASS
2108 13:56:02.010116 Jitter Meter : NO K
2109 13:56:02.013400 CBT Training : PASS
2110 13:56:02.016621 Write leveling : PASS
2111 13:56:02.016703 RX DQS gating : PASS
2112 13:56:02.019901 RX DQ/DQS(RDDQC) : PASS
2113 13:56:02.023476 TX DQ/DQS : PASS
2114 13:56:02.023561 RX DATLAT : PASS
2115 13:56:02.026623 RX DQ/DQS(Engine): PASS
2116 13:56:02.030112 TX OE : NO K
2117 13:56:02.030196 All Pass.
2118 13:56:02.030262
2119 13:56:02.030323 CH 1, Rank 0
2120 13:56:02.033074 SW Impedance : PASS
2121 13:56:02.036461 DUTY Scan : NO K
2122 13:56:02.036544 ZQ Calibration : PASS
2123 13:56:02.040183 Jitter Meter : NO K
2124 13:56:02.040301 CBT Training : PASS
2125 13:56:02.043214 Write leveling : PASS
2126 13:56:02.046528 RX DQS gating : PASS
2127 13:56:02.046652 RX DQ/DQS(RDDQC) : PASS
2128 13:56:02.050173 TX DQ/DQS : PASS
2129 13:56:02.053018 RX DATLAT : PASS
2130 13:56:02.053102 RX DQ/DQS(Engine): PASS
2131 13:56:02.056515 TX OE : NO K
2132 13:56:02.056645 All Pass.
2133 13:56:02.056712
2134 13:56:02.060317 CH 1, Rank 1
2135 13:56:02.060414 SW Impedance : PASS
2136 13:56:02.063757 DUTY Scan : NO K
2137 13:56:02.066969 ZQ Calibration : PASS
2138 13:56:02.067071 Jitter Meter : NO K
2139 13:56:02.070286 CBT Training : PASS
2140 13:56:02.073589 Write leveling : PASS
2141 13:56:02.073704 RX DQS gating : PASS
2142 13:56:02.076722 RX DQ/DQS(RDDQC) : PASS
2143 13:56:02.080204 TX DQ/DQS : PASS
2144 13:56:02.080334 RX DATLAT : PASS
2145 13:56:02.083420 RX DQ/DQS(Engine): PASS
2146 13:56:02.083504 TX OE : NO K
2147 13:56:02.086741 All Pass.
2148 13:56:02.086824
2149 13:56:02.086888 DramC Write-DBI off
2150 13:56:02.090099 PER_BANK_REFRESH: Hybrid Mode
2151 13:56:02.093367 TX_TRACKING: ON
2152 13:56:02.096682 [GetDramInforAfterCalByMRR] Vendor 6.
2153 13:56:02.099915 [GetDramInforAfterCalByMRR] Revision 606.
2154 13:56:02.103244 [GetDramInforAfterCalByMRR] Revision 2 0.
2155 13:56:02.103350 MR0 0x3b3b
2156 13:56:02.103417 MR8 0x5151
2157 13:56:02.110159 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2158 13:56:02.110243
2159 13:56:02.110346 MR0 0x3b3b
2160 13:56:02.110406 MR8 0x5151
2161 13:56:02.113081 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 13:56:02.113164
2163 13:56:02.122941 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2164 13:56:02.126865 [FAST_K] Save calibration result to emmc
2165 13:56:02.129587 [FAST_K] Save calibration result to emmc
2166 13:56:02.132905 dram_init: config_dvfs: 1
2167 13:56:02.136674 dramc_set_vcore_voltage set vcore to 662500
2168 13:56:02.140071 Read voltage for 1200, 2
2169 13:56:02.140155 Vio18 = 0
2170 13:56:02.140241 Vcore = 662500
2171 13:56:02.142983 Vdram = 0
2172 13:56:02.143060 Vddq = 0
2173 13:56:02.143147 Vmddr = 0
2174 13:56:02.149642 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2175 13:56:02.153031 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2176 13:56:02.156688 MEM_TYPE=3, freq_sel=15
2177 13:56:02.159750 sv_algorithm_assistance_LP4_1600
2178 13:56:02.163250 ============ PULL DRAM RESETB DOWN ============
2179 13:56:02.166258 ========== PULL DRAM RESETB DOWN end =========
2180 13:56:02.173001 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2181 13:56:02.176744 ===================================
2182 13:56:02.179916 LPDDR4 DRAM CONFIGURATION
2183 13:56:02.183177 ===================================
2184 13:56:02.183263 EX_ROW_EN[0] = 0x0
2185 13:56:02.186479 EX_ROW_EN[1] = 0x0
2186 13:56:02.186564 LP4Y_EN = 0x0
2187 13:56:02.189762 WORK_FSP = 0x0
2188 13:56:02.189847 WL = 0x4
2189 13:56:02.193061 RL = 0x4
2190 13:56:02.193145 BL = 0x2
2191 13:56:02.196399 RPST = 0x0
2192 13:56:02.196483 RD_PRE = 0x0
2193 13:56:02.199721 WR_PRE = 0x1
2194 13:56:02.199806 WR_PST = 0x0
2195 13:56:02.202981 DBI_WR = 0x0
2196 13:56:02.203066 DBI_RD = 0x0
2197 13:56:02.206286 OTF = 0x1
2198 13:56:02.209642 ===================================
2199 13:56:02.212902 ===================================
2200 13:56:02.212987 ANA top config
2201 13:56:02.216197 ===================================
2202 13:56:02.219664 DLL_ASYNC_EN = 0
2203 13:56:02.223392 ALL_SLAVE_EN = 0
2204 13:56:02.226636 NEW_RANK_MODE = 1
2205 13:56:02.226722 DLL_IDLE_MODE = 1
2206 13:56:02.229730 LP45_APHY_COMB_EN = 1
2207 13:56:02.233426 TX_ODT_DIS = 1
2208 13:56:02.236316 NEW_8X_MODE = 1
2209 13:56:02.239831 ===================================
2210 13:56:02.243253 ===================================
2211 13:56:02.246445 data_rate = 2400
2212 13:56:02.246529 CKR = 1
2213 13:56:02.249598 DQ_P2S_RATIO = 8
2214 13:56:02.253351 ===================================
2215 13:56:02.256469 CA_P2S_RATIO = 8
2216 13:56:02.259836 DQ_CA_OPEN = 0
2217 13:56:02.263278 DQ_SEMI_OPEN = 0
2218 13:56:02.266248 CA_SEMI_OPEN = 0
2219 13:56:02.266337 CA_FULL_RATE = 0
2220 13:56:02.270075 DQ_CKDIV4_EN = 0
2221 13:56:02.273402 CA_CKDIV4_EN = 0
2222 13:56:02.276569 CA_PREDIV_EN = 0
2223 13:56:02.280052 PH8_DLY = 17
2224 13:56:02.283018 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2225 13:56:02.283104 DQ_AAMCK_DIV = 4
2226 13:56:02.286606 CA_AAMCK_DIV = 4
2227 13:56:02.290182 CA_ADMCK_DIV = 4
2228 13:56:02.293181 DQ_TRACK_CA_EN = 0
2229 13:56:02.296596 CA_PICK = 1200
2230 13:56:02.299837 CA_MCKIO = 1200
2231 13:56:02.299920 MCKIO_SEMI = 0
2232 13:56:02.303075 PLL_FREQ = 2366
2233 13:56:02.307037 DQ_UI_PI_RATIO = 32
2234 13:56:02.309655 CA_UI_PI_RATIO = 0
2235 13:56:02.313595 ===================================
2236 13:56:02.316977 ===================================
2237 13:56:02.320329 memory_type:LPDDR4
2238 13:56:02.320409 GP_NUM : 10
2239 13:56:02.323693 SRAM_EN : 1
2240 13:56:02.326923 MD32_EN : 0
2241 13:56:02.330033 ===================================
2242 13:56:02.330111 [ANA_INIT] >>>>>>>>>>>>>>
2243 13:56:02.333238 <<<<<< [CONFIGURE PHASE]: ANA_TX
2244 13:56:02.336631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2245 13:56:02.339715 ===================================
2246 13:56:02.343441 data_rate = 2400,PCW = 0X5b00
2247 13:56:02.346782 ===================================
2248 13:56:02.350113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2249 13:56:02.356884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 13:56:02.359626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 13:56:02.366731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2252 13:56:02.370242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2253 13:56:02.373315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2254 13:56:02.373395 [ANA_INIT] flow start
2255 13:56:02.376415 [ANA_INIT] PLL >>>>>>>>
2256 13:56:02.379802 [ANA_INIT] PLL <<<<<<<<
2257 13:56:02.379878 [ANA_INIT] MIDPI >>>>>>>>
2258 13:56:02.382986 [ANA_INIT] MIDPI <<<<<<<<
2259 13:56:02.386743 [ANA_INIT] DLL >>>>>>>>
2260 13:56:02.390152 [ANA_INIT] DLL <<<<<<<<
2261 13:56:02.390230 [ANA_INIT] flow end
2262 13:56:02.393322 ============ LP4 DIFF to SE enter ============
2263 13:56:02.399601 ============ LP4 DIFF to SE exit ============
2264 13:56:02.399684 [ANA_INIT] <<<<<<<<<<<<<
2265 13:56:02.403078 [Flow] Enable top DCM control >>>>>
2266 13:56:02.406949 [Flow] Enable top DCM control <<<<<
2267 13:56:02.409616 Enable DLL master slave shuffle
2268 13:56:02.416818 ==============================================================
2269 13:56:02.416924 Gating Mode config
2270 13:56:02.423291 ==============================================================
2271 13:56:02.426675 Config description:
2272 13:56:02.433096 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2273 13:56:02.439640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2274 13:56:02.446695 SELPH_MODE 0: By rank 1: By Phase
2275 13:56:02.453202 ==============================================================
2276 13:56:02.453304 GAT_TRACK_EN = 1
2277 13:56:02.456432 RX_GATING_MODE = 2
2278 13:56:02.459572 RX_GATING_TRACK_MODE = 2
2279 13:56:02.463131 SELPH_MODE = 1
2280 13:56:02.466255 PICG_EARLY_EN = 1
2281 13:56:02.469598 VALID_LAT_VALUE = 1
2282 13:56:02.476722 ==============================================================
2283 13:56:02.480025 Enter into Gating configuration >>>>
2284 13:56:02.483234 Exit from Gating configuration <<<<
2285 13:56:02.483316 Enter into DVFS_PRE_config >>>>>
2286 13:56:02.496789 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2287 13:56:02.499858 Exit from DVFS_PRE_config <<<<<
2288 13:56:02.503467 Enter into PICG configuration >>>>
2289 13:56:02.506733 Exit from PICG configuration <<<<
2290 13:56:02.506814 [RX_INPUT] configuration >>>>>
2291 13:56:02.510003 [RX_INPUT] configuration <<<<<
2292 13:56:02.516652 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2293 13:56:02.520154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2294 13:56:02.526709 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 13:56:02.533213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 13:56:02.540254 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 13:56:02.546835 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 13:56:02.550075 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2299 13:56:02.553211 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2300 13:56:02.557012 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2301 13:56:02.563581 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2302 13:56:02.566592 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2303 13:56:02.570432 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 13:56:02.573410 ===================================
2305 13:56:02.576647 LPDDR4 DRAM CONFIGURATION
2306 13:56:02.580009 ===================================
2307 13:56:02.583930 EX_ROW_EN[0] = 0x0
2308 13:56:02.584030 EX_ROW_EN[1] = 0x0
2309 13:56:02.587264 LP4Y_EN = 0x0
2310 13:56:02.587341 WORK_FSP = 0x0
2311 13:56:02.590434 WL = 0x4
2312 13:56:02.590531 RL = 0x4
2313 13:56:02.593648 BL = 0x2
2314 13:56:02.593740 RPST = 0x0
2315 13:56:02.597373 RD_PRE = 0x0
2316 13:56:02.597454 WR_PRE = 0x1
2317 13:56:02.600400 WR_PST = 0x0
2318 13:56:02.600484 DBI_WR = 0x0
2319 13:56:02.604075 DBI_RD = 0x0
2320 13:56:02.604158 OTF = 0x1
2321 13:56:02.607202 ===================================
2322 13:56:02.610624 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2323 13:56:02.616841 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2324 13:56:02.620237 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 13:56:02.623557 ===================================
2326 13:56:02.627348 LPDDR4 DRAM CONFIGURATION
2327 13:56:02.630416 ===================================
2328 13:56:02.630494 EX_ROW_EN[0] = 0x10
2329 13:56:02.634016 EX_ROW_EN[1] = 0x0
2330 13:56:02.634092 LP4Y_EN = 0x0
2331 13:56:02.637028 WORK_FSP = 0x0
2332 13:56:02.637110 WL = 0x4
2333 13:56:02.640893 RL = 0x4
2334 13:56:02.643935 BL = 0x2
2335 13:56:02.644015 RPST = 0x0
2336 13:56:02.646933 RD_PRE = 0x0
2337 13:56:02.647012 WR_PRE = 0x1
2338 13:56:02.650408 WR_PST = 0x0
2339 13:56:02.650511 DBI_WR = 0x0
2340 13:56:02.653692 DBI_RD = 0x0
2341 13:56:02.653781 OTF = 0x1
2342 13:56:02.657293 ===================================
2343 13:56:02.664138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2344 13:56:02.664230 ==
2345 13:56:02.667424 Dram Type= 6, Freq= 0, CH_0, rank 0
2346 13:56:02.670885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2347 13:56:02.670985 ==
2348 13:56:02.673783 [Duty_Offset_Calibration]
2349 13:56:02.673868 B0:2 B1:1 CA:1
2350 13:56:02.677416
2351 13:56:02.680564 [DutyScan_Calibration_Flow] k_type=0
2352 13:56:02.688478
2353 13:56:02.688560 ==CLK 0==
2354 13:56:02.691693 Final CLK duty delay cell = 0
2355 13:56:02.694892 [0] MAX Duty = 5187%(X100), DQS PI = 24
2356 13:56:02.698270 [0] MIN Duty = 4875%(X100), DQS PI = 0
2357 13:56:02.698347 [0] AVG Duty = 5031%(X100)
2358 13:56:02.698433
2359 13:56:02.701449 CH0 CLK Duty spec in!! Max-Min= 312%
2360 13:56:02.708242 [DutyScan_Calibration_Flow] ====Done====
2361 13:56:02.708370
2362 13:56:02.711423 [DutyScan_Calibration_Flow] k_type=1
2363 13:56:02.726779
2364 13:56:02.726893 ==DQS 0 ==
2365 13:56:02.730010 Final DQS duty delay cell = -4
2366 13:56:02.733177 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2367 13:56:02.736578 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2368 13:56:02.739849 [-4] AVG Duty = 4937%(X100)
2369 13:56:02.739924
2370 13:56:02.739992 ==DQS 1 ==
2371 13:56:02.743240 Final DQS duty delay cell = 0
2372 13:56:02.746469 [0] MAX Duty = 5156%(X100), DQS PI = 0
2373 13:56:02.750331 [0] MIN Duty = 5000%(X100), DQS PI = 36
2374 13:56:02.753414 [0] AVG Duty = 5078%(X100)
2375 13:56:02.753502
2376 13:56:02.757121 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2377 13:56:02.757199
2378 13:56:02.760387 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2379 13:56:02.763304 [DutyScan_Calibration_Flow] ====Done====
2380 13:56:02.763379
2381 13:56:02.766655 [DutyScan_Calibration_Flow] k_type=3
2382 13:56:02.783338
2383 13:56:02.783475 ==DQM 0 ==
2384 13:56:02.786749 Final DQM duty delay cell = 0
2385 13:56:02.790061 [0] MAX Duty = 5156%(X100), DQS PI = 30
2386 13:56:02.793450 [0] MIN Duty = 4906%(X100), DQS PI = 50
2387 13:56:02.793554 [0] AVG Duty = 5031%(X100)
2388 13:56:02.796877
2389 13:56:02.796960 ==DQM 1 ==
2390 13:56:02.800561 Final DQM duty delay cell = 0
2391 13:56:02.803880 [0] MAX Duty = 5093%(X100), DQS PI = 0
2392 13:56:02.807216 [0] MIN Duty = 5031%(X100), DQS PI = 14
2393 13:56:02.807321 [0] AVG Duty = 5062%(X100)
2394 13:56:02.810502
2395 13:56:02.813727 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2396 13:56:02.813824
2397 13:56:02.816760 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2398 13:56:02.820621 [DutyScan_Calibration_Flow] ====Done====
2399 13:56:02.820697
2400 13:56:02.823823 [DutyScan_Calibration_Flow] k_type=2
2401 13:56:02.840117
2402 13:56:02.840258 ==DQ 0 ==
2403 13:56:02.843357 Final DQ duty delay cell = 0
2404 13:56:02.846658 [0] MAX Duty = 5031%(X100), DQS PI = 26
2405 13:56:02.849932 [0] MIN Duty = 4844%(X100), DQS PI = 62
2406 13:56:02.850004 [0] AVG Duty = 4937%(X100)
2407 13:56:02.850066
2408 13:56:02.853279 ==DQ 1 ==
2409 13:56:02.856393 Final DQ duty delay cell = 0
2410 13:56:02.859903 [0] MAX Duty = 5093%(X100), DQS PI = 10
2411 13:56:02.863030 [0] MIN Duty = 4938%(X100), DQS PI = 34
2412 13:56:02.863133 [0] AVG Duty = 5015%(X100)
2413 13:56:02.863231
2414 13:56:02.866935 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2415 13:56:02.867023
2416 13:56:02.870066 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2417 13:56:02.876436 [DutyScan_Calibration_Flow] ====Done====
2418 13:56:02.876528 ==
2419 13:56:02.880319 Dram Type= 6, Freq= 0, CH_1, rank 0
2420 13:56:02.883454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2421 13:56:02.883561 ==
2422 13:56:02.886987 [Duty_Offset_Calibration]
2423 13:56:02.887089 B0:1 B1:0 CA:0
2424 13:56:02.887179
2425 13:56:02.890016 [DutyScan_Calibration_Flow] k_type=0
2426 13:56:02.899646
2427 13:56:02.899858 ==CLK 0==
2428 13:56:02.902461 Final CLK duty delay cell = -4
2429 13:56:02.905625 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2430 13:56:02.909385 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2431 13:56:02.912687 [-4] AVG Duty = 4953%(X100)
2432 13:56:02.912769
2433 13:56:02.915553 CH1 CLK Duty spec in!! Max-Min= 156%
2434 13:56:02.919086 [DutyScan_Calibration_Flow] ====Done====
2435 13:56:02.919185
2436 13:56:02.922434 [DutyScan_Calibration_Flow] k_type=1
2437 13:56:02.939135
2438 13:56:02.939259 ==DQS 0 ==
2439 13:56:02.942121 Final DQS duty delay cell = 0
2440 13:56:02.946005 [0] MAX Duty = 5094%(X100), DQS PI = 26
2441 13:56:02.949183 [0] MIN Duty = 4875%(X100), DQS PI = 0
2442 13:56:02.949308 [0] AVG Duty = 4984%(X100)
2443 13:56:02.952646
2444 13:56:02.952762 ==DQS 1 ==
2445 13:56:02.955885 Final DQS duty delay cell = 0
2446 13:56:02.959130 [0] MAX Duty = 5187%(X100), DQS PI = 18
2447 13:56:02.962319 [0] MIN Duty = 4938%(X100), DQS PI = 10
2448 13:56:02.962427 [0] AVG Duty = 5062%(X100)
2449 13:56:02.965688
2450 13:56:02.968842 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2451 13:56:02.968934
2452 13:56:02.972048 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2453 13:56:02.975268 [DutyScan_Calibration_Flow] ====Done====
2454 13:56:02.975365
2455 13:56:02.978598 [DutyScan_Calibration_Flow] k_type=3
2456 13:56:02.995815
2457 13:56:02.996013 ==DQM 0 ==
2458 13:56:02.999126 Final DQM duty delay cell = 0
2459 13:56:03.002420 [0] MAX Duty = 5156%(X100), DQS PI = 8
2460 13:56:03.005819 [0] MIN Duty = 5031%(X100), DQS PI = 0
2461 13:56:03.005903 [0] AVG Duty = 5093%(X100)
2462 13:56:03.008962
2463 13:56:03.009044 ==DQM 1 ==
2464 13:56:03.012577 Final DQM duty delay cell = 0
2465 13:56:03.015493 [0] MAX Duty = 5031%(X100), DQS PI = 16
2466 13:56:03.019044 [0] MIN Duty = 4907%(X100), DQS PI = 36
2467 13:56:03.019127 [0] AVG Duty = 4969%(X100)
2468 13:56:03.022187
2469 13:56:03.025793 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2470 13:56:03.025879
2471 13:56:03.028805 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2472 13:56:03.032199 [DutyScan_Calibration_Flow] ====Done====
2473 13:56:03.032351
2474 13:56:03.035142 [DutyScan_Calibration_Flow] k_type=2
2475 13:56:03.051480
2476 13:56:03.051625 ==DQ 0 ==
2477 13:56:03.055065 Final DQ duty delay cell = -4
2478 13:56:03.057765 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2479 13:56:03.061378 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2480 13:56:03.064700 [-4] AVG Duty = 4984%(X100)
2481 13:56:03.064817
2482 13:56:03.064913 ==DQ 1 ==
2483 13:56:03.068212 Final DQ duty delay cell = 0
2484 13:56:03.071542 [0] MAX Duty = 5125%(X100), DQS PI = 20
2485 13:56:03.074851 [0] MIN Duty = 4969%(X100), DQS PI = 12
2486 13:56:03.074976 [0] AVG Duty = 5047%(X100)
2487 13:56:03.078216
2488 13:56:03.081625 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2489 13:56:03.081736
2490 13:56:03.084726 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2491 13:56:03.087939 [DutyScan_Calibration_Flow] ====Done====
2492 13:56:03.091179 nWR fixed to 30
2493 13:56:03.091282 [ModeRegInit_LP4] CH0 RK0
2494 13:56:03.094594 [ModeRegInit_LP4] CH0 RK1
2495 13:56:03.097706 [ModeRegInit_LP4] CH1 RK0
2496 13:56:03.101612 [ModeRegInit_LP4] CH1 RK1
2497 13:56:03.101686 match AC timing 7
2498 13:56:03.104896 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2499 13:56:03.111468 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2500 13:56:03.114773 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2501 13:56:03.118119 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2502 13:56:03.125333 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2503 13:56:03.125427 ==
2504 13:56:03.128258 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 13:56:03.131871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 13:56:03.132036 ==
2507 13:56:03.138111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2508 13:56:03.141350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2509 13:56:03.151751 [CA 0] Center 39 (8~70) winsize 63
2510 13:56:03.155046 [CA 1] Center 39 (8~70) winsize 63
2511 13:56:03.158325 [CA 2] Center 35 (4~66) winsize 63
2512 13:56:03.161914 [CA 3] Center 34 (4~65) winsize 62
2513 13:56:03.164866 [CA 4] Center 33 (3~64) winsize 62
2514 13:56:03.168624 [CA 5] Center 32 (3~62) winsize 60
2515 13:56:03.168729
2516 13:56:03.171425 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2517 13:56:03.171513
2518 13:56:03.174845 [CATrainingPosCal] consider 1 rank data
2519 13:56:03.178094 u2DelayCellTimex100 = 270/100 ps
2520 13:56:03.181443 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2521 13:56:03.184598 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2522 13:56:03.191797 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2523 13:56:03.194928 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2524 13:56:03.198063 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2525 13:56:03.201322 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2526 13:56:03.201443
2527 13:56:03.204681 CA PerBit enable=1, Macro0, CA PI delay=32
2528 13:56:03.204787
2529 13:56:03.208632 [CBTSetCACLKResult] CA Dly = 32
2530 13:56:03.208718 CS Dly: 6 (0~37)
2531 13:56:03.208812 ==
2532 13:56:03.211876 Dram Type= 6, Freq= 0, CH_0, rank 1
2533 13:56:03.218591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 13:56:03.218695 ==
2535 13:56:03.221839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 13:56:03.228555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2537 13:56:03.237469 [CA 0] Center 38 (8~69) winsize 62
2538 13:56:03.240409 [CA 1] Center 38 (8~69) winsize 62
2539 13:56:03.243837 [CA 2] Center 35 (4~66) winsize 63
2540 13:56:03.247183 [CA 3] Center 34 (4~65) winsize 62
2541 13:56:03.250433 [CA 4] Center 33 (3~64) winsize 62
2542 13:56:03.253739 [CA 5] Center 32 (3~62) winsize 60
2543 13:56:03.253865
2544 13:56:03.257325 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2545 13:56:03.257438
2546 13:56:03.261079 [CATrainingPosCal] consider 2 rank data
2547 13:56:03.264337 u2DelayCellTimex100 = 270/100 ps
2548 13:56:03.267568 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2549 13:56:03.270687 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2550 13:56:03.277153 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2551 13:56:03.280415 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2552 13:56:03.284275 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2553 13:56:03.287450 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2554 13:56:03.287576
2555 13:56:03.290567 CA PerBit enable=1, Macro0, CA PI delay=32
2556 13:56:03.290677
2557 13:56:03.294089 [CBTSetCACLKResult] CA Dly = 32
2558 13:56:03.294200 CS Dly: 6 (0~38)
2559 13:56:03.294293
2560 13:56:03.297438 ----->DramcWriteLeveling(PI) begin...
2561 13:56:03.300856 ==
2562 13:56:03.300960 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 13:56:03.307209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 13:56:03.307305 ==
2565 13:56:03.310597 Write leveling (Byte 0): 33 => 33
2566 13:56:03.314058 Write leveling (Byte 1): 30 => 30
2567 13:56:03.314145 DramcWriteLeveling(PI) end<-----
2568 13:56:03.317744
2569 13:56:03.317832 ==
2570 13:56:03.321116 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 13:56:03.323833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 13:56:03.323920 ==
2573 13:56:03.327613 [Gating] SW mode calibration
2574 13:56:03.334205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2575 13:56:03.337409 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2576 13:56:03.344049 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 0)
2577 13:56:03.347336 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2578 13:56:03.351056 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 13:56:03.357285 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 13:56:03.360850 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 13:56:03.364000 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 13:56:03.370802 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2583 13:56:03.374383 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2584 13:56:03.377432 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2585 13:56:03.383881 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 13:56:03.387673 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 13:56:03.390999 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 13:56:03.397610 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 13:56:03.400718 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 13:56:03.404025 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2591 13:56:03.410404 1 0 28 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
2592 13:56:03.414129 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2593 13:56:03.417627 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 13:56:03.421073 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 13:56:03.427142 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 13:56:03.430627 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 13:56:03.433827 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 13:56:03.440469 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 13:56:03.443658 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2600 13:56:03.447598 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2601 13:56:03.454023 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 13:56:03.457437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 13:56:03.460504 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 13:56:03.467022 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 13:56:03.470428 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 13:56:03.474272 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 13:56:03.480522 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 13:56:03.484083 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 13:56:03.487573 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 13:56:03.494164 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 13:56:03.497215 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 13:56:03.500607 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 13:56:03.507778 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 13:56:03.510929 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2615 13:56:03.514248 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2616 13:56:03.517605 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2617 13:56:03.520890 Total UI for P1: 0, mck2ui 16
2618 13:56:03.524249 best dqsien dly found for B0: ( 1, 3, 26)
2619 13:56:03.530824 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 13:56:03.530947 Total UI for P1: 0, mck2ui 16
2621 13:56:03.537405 best dqsien dly found for B1: ( 1, 4, 0)
2622 13:56:03.540691 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2623 13:56:03.544064 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2624 13:56:03.544181
2625 13:56:03.547734 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2626 13:56:03.551154 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2627 13:56:03.554337 [Gating] SW calibration Done
2628 13:56:03.554422 ==
2629 13:56:03.557587 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 13:56:03.560832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 13:56:03.560937 ==
2632 13:56:03.564467 RX Vref Scan: 0
2633 13:56:03.564545
2634 13:56:03.564626 RX Vref 0 -> 0, step: 1
2635 13:56:03.564701
2636 13:56:03.567923 RX Delay -40 -> 252, step: 8
2637 13:56:03.571020 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2638 13:56:03.577806 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2639 13:56:03.580879 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2640 13:56:03.584198 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2641 13:56:03.587930 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2642 13:56:03.591182 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2643 13:56:03.594409 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2644 13:56:03.600963 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2645 13:56:03.604436 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2646 13:56:03.607781 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2647 13:56:03.611301 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2648 13:56:03.614493 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2649 13:56:03.621544 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2650 13:56:03.624819 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2651 13:56:03.628144 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2652 13:56:03.631646 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2653 13:56:03.631747 ==
2654 13:56:03.634774 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 13:56:03.641435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 13:56:03.641611 ==
2657 13:56:03.641761 DQS Delay:
2658 13:56:03.641850 DQS0 = 0, DQS1 = 0
2659 13:56:03.644680 DQM Delay:
2660 13:56:03.644761 DQM0 = 121, DQM1 = 114
2661 13:56:03.648370 DQ Delay:
2662 13:56:03.651203 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2663 13:56:03.654639 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2664 13:56:03.657750 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2665 13:56:03.661372 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2666 13:56:03.661478
2667 13:56:03.661622
2668 13:56:03.661730 ==
2669 13:56:03.664848 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 13:56:03.668150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 13:56:03.668254 ==
2672 13:56:03.671378
2673 13:56:03.671479
2674 13:56:03.671571 TX Vref Scan disable
2675 13:56:03.674772 == TX Byte 0 ==
2676 13:56:03.677755 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2677 13:56:03.681371 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2678 13:56:03.684694 == TX Byte 1 ==
2679 13:56:03.688137 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2680 13:56:03.691149 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2681 13:56:03.691245 ==
2682 13:56:03.694788 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 13:56:03.701376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 13:56:03.701486 ==
2685 13:56:03.712159 TX Vref=22, minBit 0, minWin=25, winSum=408
2686 13:56:03.715524 TX Vref=24, minBit 1, minWin=25, winSum=414
2687 13:56:03.718789 TX Vref=26, minBit 3, minWin=25, winSum=419
2688 13:56:03.722305 TX Vref=28, minBit 10, minWin=25, winSum=422
2689 13:56:03.725687 TX Vref=30, minBit 13, minWin=25, winSum=422
2690 13:56:03.728985 TX Vref=32, minBit 0, minWin=26, winSum=424
2691 13:56:03.735454 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
2692 13:56:03.735575
2693 13:56:03.738642 Final TX Range 1 Vref 32
2694 13:56:03.738746
2695 13:56:03.738835 ==
2696 13:56:03.742012 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 13:56:03.745318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 13:56:03.745402 ==
2699 13:56:03.745465
2700 13:56:03.749057
2701 13:56:03.749152 TX Vref Scan disable
2702 13:56:03.752200 == TX Byte 0 ==
2703 13:56:03.755313 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2704 13:56:03.758711 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2705 13:56:03.762422 == TX Byte 1 ==
2706 13:56:03.765492 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2707 13:56:03.769271 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2708 13:56:03.769373
2709 13:56:03.772108 [DATLAT]
2710 13:56:03.772222 Freq=1200, CH0 RK0
2711 13:56:03.772362
2712 13:56:03.775786 DATLAT Default: 0xd
2713 13:56:03.775861 0, 0xFFFF, sum = 0
2714 13:56:03.778850 1, 0xFFFF, sum = 0
2715 13:56:03.778951 2, 0xFFFF, sum = 0
2716 13:56:03.782209 3, 0xFFFF, sum = 0
2717 13:56:03.782315 4, 0xFFFF, sum = 0
2718 13:56:03.785318 5, 0xFFFF, sum = 0
2719 13:56:03.785423 6, 0xFFFF, sum = 0
2720 13:56:03.789347 7, 0xFFFF, sum = 0
2721 13:56:03.789446 8, 0xFFFF, sum = 0
2722 13:56:03.792551 9, 0xFFFF, sum = 0
2723 13:56:03.792699 10, 0xFFFF, sum = 0
2724 13:56:03.795659 11, 0xFFFF, sum = 0
2725 13:56:03.795767 12, 0x0, sum = 1
2726 13:56:03.799174 13, 0x0, sum = 2
2727 13:56:03.799275 14, 0x0, sum = 3
2728 13:56:03.802749 15, 0x0, sum = 4
2729 13:56:03.802854 best_step = 13
2730 13:56:03.802945
2731 13:56:03.803030 ==
2732 13:56:03.805859 Dram Type= 6, Freq= 0, CH_0, rank 0
2733 13:56:03.812383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2734 13:56:03.812460 ==
2735 13:56:03.812524 RX Vref Scan: 1
2736 13:56:03.812583
2737 13:56:03.815631 Set Vref Range= 32 -> 127
2738 13:56:03.815726
2739 13:56:03.818880 RX Vref 32 -> 127, step: 1
2740 13:56:03.818978
2741 13:56:03.819066 RX Delay -13 -> 252, step: 4
2742 13:56:03.822621
2743 13:56:03.822693 Set Vref, RX VrefLevel [Byte0]: 32
2744 13:56:03.825756 [Byte1]: 32
2745 13:56:03.830427
2746 13:56:03.830527 Set Vref, RX VrefLevel [Byte0]: 33
2747 13:56:03.833533 [Byte1]: 33
2748 13:56:03.838364
2749 13:56:03.838460 Set Vref, RX VrefLevel [Byte0]: 34
2750 13:56:03.841843 [Byte1]: 34
2751 13:56:03.846159
2752 13:56:03.846267 Set Vref, RX VrefLevel [Byte0]: 35
2753 13:56:03.849373 [Byte1]: 35
2754 13:56:03.853880
2755 13:56:03.853962 Set Vref, RX VrefLevel [Byte0]: 36
2756 13:56:03.857474 [Byte1]: 36
2757 13:56:03.861888
2758 13:56:03.862000 Set Vref, RX VrefLevel [Byte0]: 37
2759 13:56:03.865154 [Byte1]: 37
2760 13:56:03.869739
2761 13:56:03.869819 Set Vref, RX VrefLevel [Byte0]: 38
2762 13:56:03.872914 [Byte1]: 38
2763 13:56:03.877373
2764 13:56:03.877480 Set Vref, RX VrefLevel [Byte0]: 39
2765 13:56:03.880931 [Byte1]: 39
2766 13:56:03.885681
2767 13:56:03.885788 Set Vref, RX VrefLevel [Byte0]: 40
2768 13:56:03.888841 [Byte1]: 40
2769 13:56:03.893343
2770 13:56:03.893443 Set Vref, RX VrefLevel [Byte0]: 41
2771 13:56:03.896599 [Byte1]: 41
2772 13:56:03.901238
2773 13:56:03.901339 Set Vref, RX VrefLevel [Byte0]: 42
2774 13:56:03.904828 [Byte1]: 42
2775 13:56:03.909371
2776 13:56:03.909462 Set Vref, RX VrefLevel [Byte0]: 43
2777 13:56:03.912276 [Byte1]: 43
2778 13:56:03.917416
2779 13:56:03.917521 Set Vref, RX VrefLevel [Byte0]: 44
2780 13:56:03.920791 [Byte1]: 44
2781 13:56:03.925307
2782 13:56:03.925395 Set Vref, RX VrefLevel [Byte0]: 45
2783 13:56:03.928511 [Byte1]: 45
2784 13:56:03.932814
2785 13:56:03.932925 Set Vref, RX VrefLevel [Byte0]: 46
2786 13:56:03.935984 [Byte1]: 46
2787 13:56:03.940637
2788 13:56:03.940733 Set Vref, RX VrefLevel [Byte0]: 47
2789 13:56:03.943872 [Byte1]: 47
2790 13:56:03.948749
2791 13:56:03.948843 Set Vref, RX VrefLevel [Byte0]: 48
2792 13:56:03.952099 [Byte1]: 48
2793 13:56:03.956404
2794 13:56:03.956506 Set Vref, RX VrefLevel [Byte0]: 49
2795 13:56:03.960179 [Byte1]: 49
2796 13:56:03.964697
2797 13:56:03.964821 Set Vref, RX VrefLevel [Byte0]: 50
2798 13:56:03.967884 [Byte1]: 50
2799 13:56:03.972143
2800 13:56:03.972256 Set Vref, RX VrefLevel [Byte0]: 51
2801 13:56:03.975887 [Byte1]: 51
2802 13:56:03.980516
2803 13:56:03.980602 Set Vref, RX VrefLevel [Byte0]: 52
2804 13:56:03.983793 [Byte1]: 52
2805 13:56:03.988376
2806 13:56:03.988465 Set Vref, RX VrefLevel [Byte0]: 53
2807 13:56:03.991412 [Byte1]: 53
2808 13:56:03.996087
2809 13:56:03.996164 Set Vref, RX VrefLevel [Byte0]: 54
2810 13:56:03.999382 [Byte1]: 54
2811 13:56:04.003589
2812 13:56:04.003673 Set Vref, RX VrefLevel [Byte0]: 55
2813 13:56:04.007360 [Byte1]: 55
2814 13:56:04.011700
2815 13:56:04.011785 Set Vref, RX VrefLevel [Byte0]: 56
2816 13:56:04.015320 [Byte1]: 56
2817 13:56:04.019639
2818 13:56:04.019725 Set Vref, RX VrefLevel [Byte0]: 57
2819 13:56:04.023282 [Byte1]: 57
2820 13:56:04.027261
2821 13:56:04.027347 Set Vref, RX VrefLevel [Byte0]: 58
2822 13:56:04.031218 [Byte1]: 58
2823 13:56:04.035730
2824 13:56:04.035831 Set Vref, RX VrefLevel [Byte0]: 59
2825 13:56:04.038886 [Byte1]: 59
2826 13:56:04.043473
2827 13:56:04.043554 Set Vref, RX VrefLevel [Byte0]: 60
2828 13:56:04.046732 [Byte1]: 60
2829 13:56:04.051272
2830 13:56:04.051378 Set Vref, RX VrefLevel [Byte0]: 61
2831 13:56:04.054609 [Byte1]: 61
2832 13:56:04.058952
2833 13:56:04.059032 Set Vref, RX VrefLevel [Byte0]: 62
2834 13:56:04.062514 [Byte1]: 62
2835 13:56:04.067310
2836 13:56:04.067407 Set Vref, RX VrefLevel [Byte0]: 63
2837 13:56:04.070385 [Byte1]: 63
2838 13:56:04.075134
2839 13:56:04.075216 Set Vref, RX VrefLevel [Byte0]: 64
2840 13:56:04.078098 [Byte1]: 64
2841 13:56:04.082964
2842 13:56:04.083080 Set Vref, RX VrefLevel [Byte0]: 65
2843 13:56:04.086307 [Byte1]: 65
2844 13:56:04.090301
2845 13:56:04.090406 Set Vref, RX VrefLevel [Byte0]: 66
2846 13:56:04.093684 [Byte1]: 66
2847 13:56:04.098288
2848 13:56:04.098365 Set Vref, RX VrefLevel [Byte0]: 67
2849 13:56:04.101672 [Byte1]: 67
2850 13:56:04.106136
2851 13:56:04.106215 Set Vref, RX VrefLevel [Byte0]: 68
2852 13:56:04.109719 [Byte1]: 68
2853 13:56:04.114668
2854 13:56:04.114753 Set Vref, RX VrefLevel [Byte0]: 69
2855 13:56:04.117399 [Byte1]: 69
2856 13:56:04.122129
2857 13:56:04.122234 Set Vref, RX VrefLevel [Byte0]: 70
2858 13:56:04.125327 [Byte1]: 70
2859 13:56:04.130016
2860 13:56:04.130110 Final RX Vref Byte 0 = 58 to rank0
2861 13:56:04.133576 Final RX Vref Byte 1 = 47 to rank0
2862 13:56:04.136572 Final RX Vref Byte 0 = 58 to rank1
2863 13:56:04.140458 Final RX Vref Byte 1 = 47 to rank1==
2864 13:56:04.143656 Dram Type= 6, Freq= 0, CH_0, rank 0
2865 13:56:04.146737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 13:56:04.150060 ==
2867 13:56:04.150146 DQS Delay:
2868 13:56:04.150213 DQS0 = 0, DQS1 = 0
2869 13:56:04.153325 DQM Delay:
2870 13:56:04.153409 DQM0 = 120, DQM1 = 111
2871 13:56:04.156646 DQ Delay:
2872 13:56:04.160009 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2873 13:56:04.163272 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2874 13:56:04.167019 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
2875 13:56:04.169922 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2876 13:56:04.170013
2877 13:56:04.170078
2878 13:56:04.176898 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2879 13:56:04.179886 CH0 RK0: MR19=404, MR18=120B
2880 13:56:04.186873 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2881 13:56:04.186979
2882 13:56:04.190444 ----->DramcWriteLeveling(PI) begin...
2883 13:56:04.190522 ==
2884 13:56:04.193713 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 13:56:04.197038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 13:56:04.200224 ==
2887 13:56:04.200317 Write leveling (Byte 0): 34 => 34
2888 13:56:04.203639 Write leveling (Byte 1): 29 => 29
2889 13:56:04.206927 DramcWriteLeveling(PI) end<-----
2890 13:56:04.207011
2891 13:56:04.207077 ==
2892 13:56:04.210170 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 13:56:04.216769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 13:56:04.216854 ==
2895 13:56:04.216921 [Gating] SW mode calibration
2896 13:56:04.226604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2897 13:56:04.229841 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2898 13:56:04.233658 0 15 0 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
2899 13:56:04.240065 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 13:56:04.243265 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 13:56:04.247001 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 13:56:04.253395 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 13:56:04.257221 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 13:56:04.260220 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2905 13:56:04.267128 0 15 28 | B1->B0 | 2e2e 2b2b | 0 0 | (1 0) (1 0)
2906 13:56:04.270379 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2907 13:56:04.273488 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 13:56:04.280485 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 13:56:04.283899 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 13:56:04.287008 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 13:56:04.293346 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 13:56:04.297054 1 0 24 | B1->B0 | 2626 2524 | 0 1 | (0 0) (0 0)
2913 13:56:04.299956 1 0 28 | B1->B0 | 3b3b 3939 | 0 0 | (0 0) (0 0)
2914 13:56:04.306680 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 13:56:04.310474 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 13:56:04.313732 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 13:56:04.320402 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 13:56:04.323608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 13:56:04.326725 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 13:56:04.329968 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 13:56:04.336753 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2922 13:56:04.339970 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2923 13:56:04.343321 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 13:56:04.350477 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 13:56:04.353672 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 13:56:04.356912 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 13:56:04.363634 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 13:56:04.366893 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 13:56:04.370242 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 13:56:04.377068 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 13:56:04.380744 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 13:56:04.383970 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 13:56:04.390334 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 13:56:04.393808 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 13:56:04.396761 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 13:56:04.403940 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2937 13:56:04.407045 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2938 13:56:04.410123 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2939 13:56:04.413649 Total UI for P1: 0, mck2ui 16
2940 13:56:04.416853 best dqsien dly found for B0: ( 1, 3, 26)
2941 13:56:04.420068 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 13:56:04.423288 Total UI for P1: 0, mck2ui 16
2943 13:56:04.427273 best dqsien dly found for B1: ( 1, 3, 28)
2944 13:56:04.430300 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2945 13:56:04.433649 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2946 13:56:04.436938
2947 13:56:04.440435 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2948 13:56:04.444156 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2949 13:56:04.446784 [Gating] SW calibration Done
2950 13:56:04.446886 ==
2951 13:56:04.450082 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 13:56:04.453874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 13:56:04.454011 ==
2954 13:56:04.454112 RX Vref Scan: 0
2955 13:56:04.454212
2956 13:56:04.457233 RX Vref 0 -> 0, step: 1
2957 13:56:04.457351
2958 13:56:04.460442 RX Delay -40 -> 252, step: 8
2959 13:56:04.463762 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2960 13:56:04.467000 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2961 13:56:04.470252 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2962 13:56:04.476939 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2963 13:56:04.480675 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2964 13:56:04.483919 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2965 13:56:04.487016 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2966 13:56:04.490790 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2967 13:56:04.497496 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2968 13:56:04.500326 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2969 13:56:04.503732 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2970 13:56:04.507441 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2971 13:56:04.510606 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2972 13:56:04.517524 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2973 13:56:04.521182 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2974 13:56:04.524271 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2975 13:56:04.524389 ==
2976 13:56:04.527883 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 13:56:04.530820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 13:56:04.530926 ==
2979 13:56:04.534619 DQS Delay:
2980 13:56:04.534729 DQS0 = 0, DQS1 = 0
2981 13:56:04.534830 DQM Delay:
2982 13:56:04.537870 DQM0 = 123, DQM1 = 112
2983 13:56:04.537972 DQ Delay:
2984 13:56:04.541344 DQ0 =123, DQ1 =123, DQ2 =123, DQ3 =119
2985 13:56:04.544616 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2986 13:56:04.550554 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2987 13:56:04.553820 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2988 13:56:04.553901
2989 13:56:04.553987
2990 13:56:04.554091 ==
2991 13:56:04.557564 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 13:56:04.560878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 13:56:04.560967 ==
2994 13:56:04.561055
2995 13:56:04.561157
2996 13:56:04.564149 TX Vref Scan disable
2997 13:56:04.567449 == TX Byte 0 ==
2998 13:56:04.570852 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2999 13:56:04.574129 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3000 13:56:04.577536 == TX Byte 1 ==
3001 13:56:04.580742 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3002 13:56:04.583821 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3003 13:56:04.583927 ==
3004 13:56:04.587519 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 13:56:04.590662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 13:56:04.590779 ==
3007 13:56:04.604196 TX Vref=22, minBit 2, minWin=25, winSum=413
3008 13:56:04.607425 TX Vref=24, minBit 13, minWin=25, winSum=416
3009 13:56:04.610753 TX Vref=26, minBit 4, minWin=25, winSum=420
3010 13:56:04.614151 TX Vref=28, minBit 1, minWin=26, winSum=424
3011 13:56:04.617759 TX Vref=30, minBit 1, minWin=26, winSum=424
3012 13:56:04.621327 TX Vref=32, minBit 0, minWin=26, winSum=419
3013 13:56:04.628027 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 28
3014 13:56:04.628139
3015 13:56:04.631147 Final TX Range 1 Vref 28
3016 13:56:04.631249
3017 13:56:04.631349 ==
3018 13:56:04.634358 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 13:56:04.638086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 13:56:04.638189 ==
3021 13:56:04.638292
3022 13:56:04.638392
3023 13:56:04.640969 TX Vref Scan disable
3024 13:56:04.644521 == TX Byte 0 ==
3025 13:56:04.647878 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3026 13:56:04.651246 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3027 13:56:04.654656 == TX Byte 1 ==
3028 13:56:04.657781 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3029 13:56:04.661710 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3030 13:56:04.661813
3031 13:56:04.664770 [DATLAT]
3032 13:56:04.664846 Freq=1200, CH0 RK1
3033 13:56:04.664910
3034 13:56:04.668003 DATLAT Default: 0xd
3035 13:56:04.668106 0, 0xFFFF, sum = 0
3036 13:56:04.671614 1, 0xFFFF, sum = 0
3037 13:56:04.671718 2, 0xFFFF, sum = 0
3038 13:56:04.674824 3, 0xFFFF, sum = 0
3039 13:56:04.674896 4, 0xFFFF, sum = 0
3040 13:56:04.678050 5, 0xFFFF, sum = 0
3041 13:56:04.678148 6, 0xFFFF, sum = 0
3042 13:56:04.681291 7, 0xFFFF, sum = 0
3043 13:56:04.681366 8, 0xFFFF, sum = 0
3044 13:56:04.684713 9, 0xFFFF, sum = 0
3045 13:56:04.684856 10, 0xFFFF, sum = 0
3046 13:56:04.687959 11, 0xFFFF, sum = 0
3047 13:56:04.688131 12, 0x0, sum = 1
3048 13:56:04.691726 13, 0x0, sum = 2
3049 13:56:04.691892 14, 0x0, sum = 3
3050 13:56:04.694851 15, 0x0, sum = 4
3051 13:56:04.694943 best_step = 13
3052 13:56:04.695011
3053 13:56:04.695071 ==
3054 13:56:04.697952 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 13:56:04.704772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 13:56:04.704909 ==
3057 13:56:04.705001 RX Vref Scan: 0
3058 13:56:04.705065
3059 13:56:04.707982 RX Vref 0 -> 0, step: 1
3060 13:56:04.708089
3061 13:56:04.711401 RX Delay -13 -> 252, step: 4
3062 13:56:04.714714 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3063 13:56:04.717872 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3064 13:56:04.724458 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3065 13:56:04.727774 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3066 13:56:04.731064 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3067 13:56:04.734992 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3068 13:56:04.738061 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3069 13:56:04.744584 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3070 13:56:04.748328 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3071 13:56:04.751307 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3072 13:56:04.754782 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3073 13:56:04.758136 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3074 13:56:04.761533 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3075 13:56:04.768219 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3076 13:56:04.771590 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3077 13:56:04.774627 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3078 13:56:04.774731 ==
3079 13:56:04.777953 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 13:56:04.781691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 13:56:04.784600 ==
3082 13:56:04.784718 DQS Delay:
3083 13:56:04.784815 DQS0 = 0, DQS1 = 0
3084 13:56:04.788510 DQM Delay:
3085 13:56:04.788618 DQM0 = 120, DQM1 = 109
3086 13:56:04.791781 DQ Delay:
3087 13:56:04.795016 DQ0 =120, DQ1 =120, DQ2 =116, DQ3 =118
3088 13:56:04.798170 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3089 13:56:04.801501 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3090 13:56:04.804604 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3091 13:56:04.804714
3092 13:56:04.804817
3093 13:56:04.811317 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3094 13:56:04.814645 CH0 RK1: MR19=403, MR18=11F2
3095 13:56:04.821649 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3096 13:56:04.825182 [RxdqsGatingPostProcess] freq 1200
3097 13:56:04.831191 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3098 13:56:04.835189 best DQS0 dly(2T, 0.5T) = (0, 11)
3099 13:56:04.835298 best DQS1 dly(2T, 0.5T) = (0, 12)
3100 13:56:04.837821 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3101 13:56:04.841769 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3102 13:56:04.844942 best DQS0 dly(2T, 0.5T) = (0, 11)
3103 13:56:04.848043 best DQS1 dly(2T, 0.5T) = (0, 11)
3104 13:56:04.851715 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3105 13:56:04.854928 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3106 13:56:04.858198 Pre-setting of DQS Precalculation
3107 13:56:04.861441 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3108 13:56:04.864680 ==
3109 13:56:04.868425 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 13:56:04.871414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 13:56:04.871521 ==
3112 13:56:04.875214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3113 13:56:04.881231 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3114 13:56:04.890957 [CA 0] Center 37 (7~68) winsize 62
3115 13:56:04.893780 [CA 1] Center 37 (7~68) winsize 62
3116 13:56:04.897805 [CA 2] Center 35 (5~65) winsize 61
3117 13:56:04.900694 [CA 3] Center 34 (4~64) winsize 61
3118 13:56:04.903820 [CA 4] Center 34 (4~64) winsize 61
3119 13:56:04.907634 [CA 5] Center 33 (3~63) winsize 61
3120 13:56:04.907726
3121 13:56:04.910710 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3122 13:56:04.910824
3123 13:56:04.913886 [CATrainingPosCal] consider 1 rank data
3124 13:56:04.917563 u2DelayCellTimex100 = 270/100 ps
3125 13:56:04.920668 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3126 13:56:04.924387 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3127 13:56:04.931131 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3128 13:56:04.933755 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3129 13:56:04.937121 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3130 13:56:04.940998 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3131 13:56:04.941109
3132 13:56:04.944245 CA PerBit enable=1, Macro0, CA PI delay=33
3133 13:56:04.944360
3134 13:56:04.947624 [CBTSetCACLKResult] CA Dly = 33
3135 13:56:04.947733 CS Dly: 8 (0~39)
3136 13:56:04.947829 ==
3137 13:56:04.950803 Dram Type= 6, Freq= 0, CH_1, rank 1
3138 13:56:04.957580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 13:56:04.957701 ==
3140 13:56:04.960717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3141 13:56:04.967280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3142 13:56:04.976312 [CA 0] Center 37 (7~68) winsize 62
3143 13:56:04.979816 [CA 1] Center 37 (7~68) winsize 62
3144 13:56:04.982879 [CA 2] Center 35 (5~66) winsize 62
3145 13:56:04.986156 [CA 3] Center 34 (4~65) winsize 62
3146 13:56:04.989471 [CA 4] Center 35 (5~65) winsize 61
3147 13:56:04.992730 [CA 5] Center 34 (4~64) winsize 61
3148 13:56:04.992836
3149 13:56:04.996085 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3150 13:56:04.996187
3151 13:56:04.999355 [CATrainingPosCal] consider 2 rank data
3152 13:56:05.003134 u2DelayCellTimex100 = 270/100 ps
3153 13:56:05.006173 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3154 13:56:05.009400 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3155 13:56:05.016083 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3156 13:56:05.019653 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 13:56:05.023360 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3158 13:56:05.026203 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3159 13:56:05.026309
3160 13:56:05.030001 CA PerBit enable=1, Macro0, CA PI delay=33
3161 13:56:05.030113
3162 13:56:05.033267 [CBTSetCACLKResult] CA Dly = 33
3163 13:56:05.033361 CS Dly: 9 (0~41)
3164 13:56:05.033430
3165 13:56:05.036308 ----->DramcWriteLeveling(PI) begin...
3166 13:56:05.036390 ==
3167 13:56:05.039967 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 13:56:05.046408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 13:56:05.046515 ==
3170 13:56:05.049743 Write leveling (Byte 0): 27 => 27
3171 13:56:05.053008 Write leveling (Byte 1): 26 => 26
3172 13:56:05.053127 DramcWriteLeveling(PI) end<-----
3173 13:56:05.053231
3174 13:56:05.056896 ==
3175 13:56:05.060073 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 13:56:05.063125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 13:56:05.063250 ==
3178 13:56:05.066921 [Gating] SW mode calibration
3179 13:56:05.073281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3180 13:56:05.076636 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3181 13:56:05.083186 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3182 13:56:05.086399 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 13:56:05.090118 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 13:56:05.096336 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 13:56:05.099877 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 13:56:05.103240 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3187 13:56:05.110242 0 15 24 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 1)
3188 13:56:05.113623 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 13:56:05.116981 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 13:56:05.120279 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 13:56:05.126837 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 13:56:05.130179 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 13:56:05.133492 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 13:56:05.140403 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 13:56:05.143447 1 0 24 | B1->B0 | 3232 4040 | 1 0 | (1 1) (0 0)
3196 13:56:05.147119 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 13:56:05.153941 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 13:56:05.157082 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 13:56:05.160622 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 13:56:05.166819 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 13:56:05.170492 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 13:56:05.173140 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 13:56:05.180429 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3204 13:56:05.183879 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3205 13:56:05.186597 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 13:56:05.193216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 13:56:05.197050 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 13:56:05.200226 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 13:56:05.206671 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 13:56:05.209947 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 13:56:05.213729 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 13:56:05.217024 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 13:56:05.223495 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 13:56:05.226871 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 13:56:05.230166 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 13:56:05.236691 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 13:56:05.240084 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 13:56:05.243404 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 13:56:05.250637 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3220 13:56:05.253308 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 13:56:05.256688 Total UI for P1: 0, mck2ui 16
3222 13:56:05.260714 best dqsien dly found for B0: ( 1, 3, 24)
3223 13:56:05.263232 Total UI for P1: 0, mck2ui 16
3224 13:56:05.267010 best dqsien dly found for B1: ( 1, 3, 24)
3225 13:56:05.270366 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3226 13:56:05.273372 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3227 13:56:05.273471
3228 13:56:05.276708 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3229 13:56:05.280271 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3230 13:56:05.283350 [Gating] SW calibration Done
3231 13:56:05.283452 ==
3232 13:56:05.286571 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 13:56:05.290132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 13:56:05.290240 ==
3235 13:56:05.293369 RX Vref Scan: 0
3236 13:56:05.293472
3237 13:56:05.296574 RX Vref 0 -> 0, step: 1
3238 13:56:05.296680
3239 13:56:05.296772 RX Delay -40 -> 252, step: 8
3240 13:56:05.303846 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3241 13:56:05.307076 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3242 13:56:05.310749 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3243 13:56:05.313723 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3244 13:56:05.317711 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3245 13:56:05.323590 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3246 13:56:05.327576 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3247 13:56:05.330870 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3248 13:56:05.333625 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3249 13:56:05.337553 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3250 13:56:05.344102 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3251 13:56:05.347551 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3252 13:56:05.350792 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3253 13:56:05.353992 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3254 13:56:05.357332 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3255 13:56:05.364001 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3256 13:56:05.364106 ==
3257 13:56:05.367220 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 13:56:05.370567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 13:56:05.370679 ==
3260 13:56:05.370778 DQS Delay:
3261 13:56:05.373875 DQS0 = 0, DQS1 = 0
3262 13:56:05.373976 DQM Delay:
3263 13:56:05.377134 DQM0 = 120, DQM1 = 116
3264 13:56:05.377246 DQ Delay:
3265 13:56:05.381056 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3266 13:56:05.384418 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3267 13:56:05.387694 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3268 13:56:05.391005 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3269 13:56:05.391088
3270 13:56:05.391154
3271 13:56:05.391215 ==
3272 13:56:05.394228 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 13:56:05.401069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 13:56:05.401153 ==
3275 13:56:05.401219
3276 13:56:05.401279
3277 13:56:05.401338 TX Vref Scan disable
3278 13:56:05.404440 == TX Byte 0 ==
3279 13:56:05.407848 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3280 13:56:05.414496 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3281 13:56:05.414579 == TX Byte 1 ==
3282 13:56:05.417608 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3283 13:56:05.424327 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3284 13:56:05.424410 ==
3285 13:56:05.427803 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 13:56:05.430804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 13:56:05.430914 ==
3288 13:56:05.442249 TX Vref=22, minBit 12, minWin=24, winSum=410
3289 13:56:05.445479 TX Vref=24, minBit 1, minWin=25, winSum=418
3290 13:56:05.449060 TX Vref=26, minBit 0, minWin=26, winSum=423
3291 13:56:05.452060 TX Vref=28, minBit 10, minWin=25, winSum=427
3292 13:56:05.455502 TX Vref=30, minBit 1, minWin=26, winSum=430
3293 13:56:05.462254 TX Vref=32, minBit 10, minWin=25, winSum=431
3294 13:56:05.465701 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3295 13:56:05.465810
3296 13:56:05.469007 Final TX Range 1 Vref 30
3297 13:56:05.469081
3298 13:56:05.469147 ==
3299 13:56:05.472298 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 13:56:05.475646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 13:56:05.475747 ==
3302 13:56:05.478930
3303 13:56:05.479027
3304 13:56:05.479124 TX Vref Scan disable
3305 13:56:05.482250 == TX Byte 0 ==
3306 13:56:05.485613 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3307 13:56:05.488865 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3308 13:56:05.492217 == TX Byte 1 ==
3309 13:56:05.495685 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3310 13:56:05.499033 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3311 13:56:05.502486
3312 13:56:05.502569 [DATLAT]
3313 13:56:05.502635 Freq=1200, CH1 RK0
3314 13:56:05.502696
3315 13:56:05.505763 DATLAT Default: 0xd
3316 13:56:05.505846 0, 0xFFFF, sum = 0
3317 13:56:05.508483 1, 0xFFFF, sum = 0
3318 13:56:05.508567 2, 0xFFFF, sum = 0
3319 13:56:05.512179 3, 0xFFFF, sum = 0
3320 13:56:05.515433 4, 0xFFFF, sum = 0
3321 13:56:05.515517 5, 0xFFFF, sum = 0
3322 13:56:05.518746 6, 0xFFFF, sum = 0
3323 13:56:05.518830 7, 0xFFFF, sum = 0
3324 13:56:05.521940 8, 0xFFFF, sum = 0
3325 13:56:05.522024 9, 0xFFFF, sum = 0
3326 13:56:05.525339 10, 0xFFFF, sum = 0
3327 13:56:05.525424 11, 0xFFFF, sum = 0
3328 13:56:05.528722 12, 0x0, sum = 1
3329 13:56:05.528806 13, 0x0, sum = 2
3330 13:56:05.532063 14, 0x0, sum = 3
3331 13:56:05.532146 15, 0x0, sum = 4
3332 13:56:05.532213 best_step = 13
3333 13:56:05.535227
3334 13:56:05.535309 ==
3335 13:56:05.538924 Dram Type= 6, Freq= 0, CH_1, rank 0
3336 13:56:05.541903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3337 13:56:05.541986 ==
3338 13:56:05.542052 RX Vref Scan: 1
3339 13:56:05.542114
3340 13:56:05.545241 Set Vref Range= 32 -> 127
3341 13:56:05.545324
3342 13:56:05.548900 RX Vref 32 -> 127, step: 1
3343 13:56:05.548983
3344 13:56:05.552009 RX Delay -5 -> 252, step: 4
3345 13:56:05.552092
3346 13:56:05.555276 Set Vref, RX VrefLevel [Byte0]: 32
3347 13:56:05.558602 [Byte1]: 32
3348 13:56:05.558686
3349 13:56:05.562077 Set Vref, RX VrefLevel [Byte0]: 33
3350 13:56:05.565152 [Byte1]: 33
3351 13:56:05.565235
3352 13:56:05.568712 Set Vref, RX VrefLevel [Byte0]: 34
3353 13:56:05.572404 [Byte1]: 34
3354 13:56:05.576245
3355 13:56:05.576337 Set Vref, RX VrefLevel [Byte0]: 35
3356 13:56:05.579330 [Byte1]: 35
3357 13:56:05.583898
3358 13:56:05.583980 Set Vref, RX VrefLevel [Byte0]: 36
3359 13:56:05.587206 [Byte1]: 36
3360 13:56:05.592244
3361 13:56:05.592346 Set Vref, RX VrefLevel [Byte0]: 37
3362 13:56:05.594896 [Byte1]: 37
3363 13:56:05.599675
3364 13:56:05.599757 Set Vref, RX VrefLevel [Byte0]: 38
3365 13:56:05.602970 [Byte1]: 38
3366 13:56:05.607687
3367 13:56:05.607789 Set Vref, RX VrefLevel [Byte0]: 39
3368 13:56:05.610989 [Byte1]: 39
3369 13:56:05.615731
3370 13:56:05.615839 Set Vref, RX VrefLevel [Byte0]: 40
3371 13:56:05.618895 [Byte1]: 40
3372 13:56:05.623471
3373 13:56:05.623545 Set Vref, RX VrefLevel [Byte0]: 41
3374 13:56:05.626824 [Byte1]: 41
3375 13:56:05.631536
3376 13:56:05.631642 Set Vref, RX VrefLevel [Byte0]: 42
3377 13:56:05.634735 [Byte1]: 42
3378 13:56:05.638724
3379 13:56:05.638830 Set Vref, RX VrefLevel [Byte0]: 43
3380 13:56:05.642058 [Byte1]: 43
3381 13:56:05.646819
3382 13:56:05.646925 Set Vref, RX VrefLevel [Byte0]: 44
3383 13:56:05.650081 [Byte1]: 44
3384 13:56:05.654679
3385 13:56:05.654779 Set Vref, RX VrefLevel [Byte0]: 45
3386 13:56:05.657799 [Byte1]: 45
3387 13:56:05.662580
3388 13:56:05.662656 Set Vref, RX VrefLevel [Byte0]: 46
3389 13:56:05.666149 [Byte1]: 46
3390 13:56:05.670678
3391 13:56:05.670759 Set Vref, RX VrefLevel [Byte0]: 47
3392 13:56:05.673899 [Byte1]: 47
3393 13:56:05.677962
3394 13:56:05.678069 Set Vref, RX VrefLevel [Byte0]: 48
3395 13:56:05.681232 [Byte1]: 48
3396 13:56:05.686030
3397 13:56:05.686140 Set Vref, RX VrefLevel [Byte0]: 49
3398 13:56:05.689352 [Byte1]: 49
3399 13:56:05.693650
3400 13:56:05.693754 Set Vref, RX VrefLevel [Byte0]: 50
3401 13:56:05.697257 [Byte1]: 50
3402 13:56:05.701727
3403 13:56:05.701835 Set Vref, RX VrefLevel [Byte0]: 51
3404 13:56:05.705400 [Byte1]: 51
3405 13:56:05.710017
3406 13:56:05.710124 Set Vref, RX VrefLevel [Byte0]: 52
3407 13:56:05.713068 [Byte1]: 52
3408 13:56:05.717722
3409 13:56:05.717830 Set Vref, RX VrefLevel [Byte0]: 53
3410 13:56:05.720727 [Byte1]: 53
3411 13:56:05.725097
3412 13:56:05.725171 Set Vref, RX VrefLevel [Byte0]: 54
3413 13:56:05.728491 [Byte1]: 54
3414 13:56:05.733043
3415 13:56:05.733150 Set Vref, RX VrefLevel [Byte0]: 55
3416 13:56:05.736281 [Byte1]: 55
3417 13:56:05.740965
3418 13:56:05.741036 Set Vref, RX VrefLevel [Byte0]: 56
3419 13:56:05.744268 [Byte1]: 56
3420 13:56:05.748818
3421 13:56:05.748887 Set Vref, RX VrefLevel [Byte0]: 57
3422 13:56:05.752127 [Byte1]: 57
3423 13:56:05.756670
3424 13:56:05.756756 Set Vref, RX VrefLevel [Byte0]: 58
3425 13:56:05.759903 [Byte1]: 58
3426 13:56:05.764571
3427 13:56:05.764672 Set Vref, RX VrefLevel [Byte0]: 59
3428 13:56:05.767744 [Byte1]: 59
3429 13:56:05.772651
3430 13:56:05.772753 Set Vref, RX VrefLevel [Byte0]: 60
3431 13:56:05.775637 [Byte1]: 60
3432 13:56:05.780570
3433 13:56:05.780644 Set Vref, RX VrefLevel [Byte0]: 61
3434 13:56:05.783457 [Byte1]: 61
3435 13:56:05.788192
3436 13:56:05.788269 Set Vref, RX VrefLevel [Byte0]: 62
3437 13:56:05.791305 [Byte1]: 62
3438 13:56:05.796201
3439 13:56:05.796313 Set Vref, RX VrefLevel [Byte0]: 63
3440 13:56:05.799370 [Byte1]: 63
3441 13:56:05.804011
3442 13:56:05.804126 Set Vref, RX VrefLevel [Byte0]: 64
3443 13:56:05.807303 [Byte1]: 64
3444 13:56:05.811820
3445 13:56:05.811920 Set Vref, RX VrefLevel [Byte0]: 65
3446 13:56:05.815089 [Byte1]: 65
3447 13:56:05.819595
3448 13:56:05.819668 Set Vref, RX VrefLevel [Byte0]: 66
3449 13:56:05.822655 [Byte1]: 66
3450 13:56:05.827617
3451 13:56:05.827721 Set Vref, RX VrefLevel [Byte0]: 67
3452 13:56:05.830433 [Byte1]: 67
3453 13:56:05.835194
3454 13:56:05.835291 Set Vref, RX VrefLevel [Byte0]: 68
3455 13:56:05.838396 [Byte1]: 68
3456 13:56:05.843147
3457 13:56:05.843230 Set Vref, RX VrefLevel [Byte0]: 69
3458 13:56:05.846660 [Byte1]: 69
3459 13:56:05.851278
3460 13:56:05.851361 Set Vref, RX VrefLevel [Byte0]: 70
3461 13:56:05.854022 [Byte1]: 70
3462 13:56:05.858740
3463 13:56:05.858824 Set Vref, RX VrefLevel [Byte0]: 71
3464 13:56:05.862127 [Byte1]: 71
3465 13:56:05.866745
3466 13:56:05.866828 Final RX Vref Byte 0 = 53 to rank0
3467 13:56:05.870080 Final RX Vref Byte 1 = 47 to rank0
3468 13:56:05.873353 Final RX Vref Byte 0 = 53 to rank1
3469 13:56:05.876698 Final RX Vref Byte 1 = 47 to rank1==
3470 13:56:05.879865 Dram Type= 6, Freq= 0, CH_1, rank 0
3471 13:56:05.887156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 13:56:05.887240 ==
3473 13:56:05.887308 DQS Delay:
3474 13:56:05.887370 DQS0 = 0, DQS1 = 0
3475 13:56:05.890216 DQM Delay:
3476 13:56:05.890303 DQM0 = 120, DQM1 = 116
3477 13:56:05.893386 DQ Delay:
3478 13:56:05.896919 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =118
3479 13:56:05.899928 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3480 13:56:05.903353 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3481 13:56:05.906730 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3482 13:56:05.906819
3483 13:56:05.906887
3484 13:56:05.913370 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3485 13:56:05.916615 CH1 RK0: MR19=404, MR18=13
3486 13:56:05.923307 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3487 13:56:05.923391
3488 13:56:05.926606 ----->DramcWriteLeveling(PI) begin...
3489 13:56:05.926691 ==
3490 13:56:05.929951 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 13:56:05.933395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 13:56:05.933478 ==
3493 13:56:05.936700 Write leveling (Byte 0): 26 => 26
3494 13:56:05.939830 Write leveling (Byte 1): 30 => 30
3495 13:56:05.943434 DramcWriteLeveling(PI) end<-----
3496 13:56:05.943531
3497 13:56:05.943596 ==
3498 13:56:05.947184 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 13:56:05.950459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 13:56:05.950570 ==
3501 13:56:05.953523 [Gating] SW mode calibration
3502 13:56:05.960099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3503 13:56:05.966827 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3504 13:56:05.970580 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 13:56:05.976894 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 13:56:05.980195 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 13:56:05.983395 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 13:56:05.990093 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 13:56:05.993445 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 13:56:05.996652 0 15 24 | B1->B0 | 3131 3434 | 0 1 | (1 0) (1 0)
3511 13:56:05.999965 0 15 28 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 0)
3512 13:56:06.007005 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 13:56:06.010244 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 13:56:06.013649 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 13:56:06.020249 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 13:56:06.023542 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 13:56:06.026926 1 0 20 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
3518 13:56:06.033387 1 0 24 | B1->B0 | 4444 2c2c | 0 0 | (1 1) (0 0)
3519 13:56:06.036740 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 13:56:06.040114 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 13:56:06.046878 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 13:56:06.050084 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 13:56:06.053270 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 13:56:06.059883 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 13:56:06.063282 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 13:56:06.066652 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3527 13:56:06.073410 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3528 13:56:06.076606 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 13:56:06.079991 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 13:56:06.086579 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 13:56:06.089703 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 13:56:06.093266 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 13:56:06.099669 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 13:56:06.102696 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 13:56:06.106250 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 13:56:06.112531 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 13:56:06.116318 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 13:56:06.119599 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 13:56:06.126232 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 13:56:06.129341 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 13:56:06.132453 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3542 13:56:06.139421 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3543 13:56:06.142593 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3544 13:56:06.145922 Total UI for P1: 0, mck2ui 16
3545 13:56:06.149155 best dqsien dly found for B1: ( 1, 3, 22)
3546 13:56:06.152469 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 13:56:06.155646 Total UI for P1: 0, mck2ui 16
3548 13:56:06.158955 best dqsien dly found for B0: ( 1, 3, 26)
3549 13:56:06.162903 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3550 13:56:06.165665 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3551 13:56:06.165743
3552 13:56:06.169613 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3553 13:56:06.175637 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3554 13:56:06.175721 [Gating] SW calibration Done
3555 13:56:06.175787 ==
3556 13:56:06.179620 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 13:56:06.186118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 13:56:06.186221 ==
3559 13:56:06.186312 RX Vref Scan: 0
3560 13:56:06.186409
3561 13:56:06.189534 RX Vref 0 -> 0, step: 1
3562 13:56:06.189632
3563 13:56:06.192334 RX Delay -40 -> 252, step: 8
3564 13:56:06.195613 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3565 13:56:06.198901 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3566 13:56:06.202241 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3567 13:56:06.208789 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3568 13:56:06.212747 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3569 13:56:06.215855 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3570 13:56:06.219203 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3571 13:56:06.222316 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3572 13:56:06.228723 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3573 13:56:06.232450 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3574 13:56:06.235554 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3575 13:56:06.239024 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3576 13:56:06.242281 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3577 13:56:06.248662 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3578 13:56:06.252036 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3579 13:56:06.255428 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3580 13:56:06.255535 ==
3581 13:56:06.259048 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 13:56:06.262374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 13:56:06.265436 ==
3584 13:56:06.265514 DQS Delay:
3585 13:56:06.265578 DQS0 = 0, DQS1 = 0
3586 13:56:06.268890 DQM Delay:
3587 13:56:06.268993 DQM0 = 121, DQM1 = 118
3588 13:56:06.271920 DQ Delay:
3589 13:56:06.275519 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3590 13:56:06.278834 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3591 13:56:06.282159 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3592 13:56:06.285487 DQ12 =127, DQ13 =127, DQ14 =119, DQ15 =127
3593 13:56:06.285586
3594 13:56:06.285685
3595 13:56:06.285789 ==
3596 13:56:06.288898 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 13:56:06.292251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 13:56:06.292378 ==
3599 13:56:06.292455
3600 13:56:06.294987
3601 13:56:06.295086 TX Vref Scan disable
3602 13:56:06.298295 == TX Byte 0 ==
3603 13:56:06.302247 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3604 13:56:06.305004 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3605 13:56:06.308320 == TX Byte 1 ==
3606 13:56:06.311670 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3607 13:56:06.315143 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3608 13:56:06.315225 ==
3609 13:56:06.318493 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 13:56:06.325101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 13:56:06.325183 ==
3612 13:56:06.335779 TX Vref=22, minBit 9, minWin=25, winSum=418
3613 13:56:06.339106 TX Vref=24, minBit 1, minWin=26, winSum=425
3614 13:56:06.342445 TX Vref=26, minBit 1, minWin=26, winSum=430
3615 13:56:06.345685 TX Vref=28, minBit 9, minWin=26, winSum=434
3616 13:56:06.348865 TX Vref=30, minBit 9, minWin=26, winSum=434
3617 13:56:06.352481 TX Vref=32, minBit 9, minWin=26, winSum=436
3618 13:56:06.359307 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3619 13:56:06.359391
3620 13:56:06.362283 Final TX Range 1 Vref 32
3621 13:56:06.362411
3622 13:56:06.362508 ==
3623 13:56:06.365727 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 13:56:06.368820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 13:56:06.368905 ==
3626 13:56:06.368971
3627 13:56:06.372787
3628 13:56:06.372894 TX Vref Scan disable
3629 13:56:06.375653 == TX Byte 0 ==
3630 13:56:06.379147 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3631 13:56:06.382125 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3632 13:56:06.385793 == TX Byte 1 ==
3633 13:56:06.388802 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3634 13:56:06.392340 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3635 13:56:06.392429
3636 13:56:06.395587 [DATLAT]
3637 13:56:06.395662 Freq=1200, CH1 RK1
3638 13:56:06.395725
3639 13:56:06.398982 DATLAT Default: 0xd
3640 13:56:06.399057 0, 0xFFFF, sum = 0
3641 13:56:06.402180 1, 0xFFFF, sum = 0
3642 13:56:06.402256 2, 0xFFFF, sum = 0
3643 13:56:06.405454 3, 0xFFFF, sum = 0
3644 13:56:06.405534 4, 0xFFFF, sum = 0
3645 13:56:06.408716 5, 0xFFFF, sum = 0
3646 13:56:06.408845 6, 0xFFFF, sum = 0
3647 13:56:06.412497 7, 0xFFFF, sum = 0
3648 13:56:06.415710 8, 0xFFFF, sum = 0
3649 13:56:06.415824 9, 0xFFFF, sum = 0
3650 13:56:06.419044 10, 0xFFFF, sum = 0
3651 13:56:06.419158 11, 0xFFFF, sum = 0
3652 13:56:06.422389 12, 0x0, sum = 1
3653 13:56:06.422463 13, 0x0, sum = 2
3654 13:56:06.425708 14, 0x0, sum = 3
3655 13:56:06.425795 15, 0x0, sum = 4
3656 13:56:06.425861 best_step = 13
3657 13:56:06.425920
3658 13:56:06.428927 ==
3659 13:56:06.432374 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 13:56:06.435066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 13:56:06.435162 ==
3662 13:56:06.435268 RX Vref Scan: 0
3663 13:56:06.435355
3664 13:56:06.439050 RX Vref 0 -> 0, step: 1
3665 13:56:06.439123
3666 13:56:06.441710 RX Delay -5 -> 252, step: 4
3667 13:56:06.445170 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3668 13:56:06.451713 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3669 13:56:06.455703 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3670 13:56:06.458204 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3671 13:56:06.462083 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3672 13:56:06.465260 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3673 13:56:06.472034 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3674 13:56:06.475272 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3675 13:56:06.478646 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3676 13:56:06.482070 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3677 13:56:06.484767 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3678 13:56:06.492231 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3679 13:56:06.495172 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3680 13:56:06.498387 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3681 13:56:06.501726 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3682 13:56:06.504921 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3683 13:56:06.508123 ==
3684 13:56:06.508205 Dram Type= 6, Freq= 0, CH_1, rank 1
3685 13:56:06.515005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3686 13:56:06.515124 ==
3687 13:56:06.515189 DQS Delay:
3688 13:56:06.518027 DQS0 = 0, DQS1 = 0
3689 13:56:06.518139 DQM Delay:
3690 13:56:06.521543 DQM0 = 120, DQM1 = 116
3691 13:56:06.521639 DQ Delay:
3692 13:56:06.524931 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3693 13:56:06.528333 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3694 13:56:06.532064 DQ8 =104, DQ9 =104, DQ10 =116, DQ11 =110
3695 13:56:06.535082 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3696 13:56:06.535164
3697 13:56:06.535229
3698 13:56:06.544558 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3699 13:56:06.547871 CH1 RK1: MR19=403, MR18=14F1
3700 13:56:06.551317 CH1_RK1: MR19=0x403, MR18=0x14F1, DQSOSC=402, MR23=63, INC=40, DEC=27
3701 13:56:06.554583 [RxdqsGatingPostProcess] freq 1200
3702 13:56:06.561564 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3703 13:56:06.564748 best DQS0 dly(2T, 0.5T) = (0, 11)
3704 13:56:06.568131 best DQS1 dly(2T, 0.5T) = (0, 11)
3705 13:56:06.571437 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3706 13:56:06.574923 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3707 13:56:06.578265 best DQS0 dly(2T, 0.5T) = (0, 11)
3708 13:56:06.581604 best DQS1 dly(2T, 0.5T) = (0, 11)
3709 13:56:06.584999 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3710 13:56:06.588342 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3711 13:56:06.588439 Pre-setting of DQS Precalculation
3712 13:56:06.595211 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3713 13:56:06.601435 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3714 13:56:06.607929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3715 13:56:06.608013
3716 13:56:06.608086
3717 13:56:06.611213 [Calibration Summary] 2400 Mbps
3718 13:56:06.614567 CH 0, Rank 0
3719 13:56:06.614642 SW Impedance : PASS
3720 13:56:06.617903 DUTY Scan : NO K
3721 13:56:06.621266 ZQ Calibration : PASS
3722 13:56:06.621367 Jitter Meter : NO K
3723 13:56:06.624620 CBT Training : PASS
3724 13:56:06.627828 Write leveling : PASS
3725 13:56:06.627925 RX DQS gating : PASS
3726 13:56:06.631241 RX DQ/DQS(RDDQC) : PASS
3727 13:56:06.631323 TX DQ/DQS : PASS
3728 13:56:06.634432 RX DATLAT : PASS
3729 13:56:06.637614 RX DQ/DQS(Engine): PASS
3730 13:56:06.637697 TX OE : NO K
3731 13:56:06.641431 All Pass.
3732 13:56:06.641516
3733 13:56:06.641582 CH 0, Rank 1
3734 13:56:06.644180 SW Impedance : PASS
3735 13:56:06.644298 DUTY Scan : NO K
3736 13:56:06.647661 ZQ Calibration : PASS
3737 13:56:06.651140 Jitter Meter : NO K
3738 13:56:06.651224 CBT Training : PASS
3739 13:56:06.654648 Write leveling : PASS
3740 13:56:06.657460 RX DQS gating : PASS
3741 13:56:06.657543 RX DQ/DQS(RDDQC) : PASS
3742 13:56:06.660706 TX DQ/DQS : PASS
3743 13:56:06.664681 RX DATLAT : PASS
3744 13:56:06.664764 RX DQ/DQS(Engine): PASS
3745 13:56:06.667780 TX OE : NO K
3746 13:56:06.667882 All Pass.
3747 13:56:06.667975
3748 13:56:06.670944 CH 1, Rank 0
3749 13:56:06.671050 SW Impedance : PASS
3750 13:56:06.674007 DUTY Scan : NO K
3751 13:56:06.677547 ZQ Calibration : PASS
3752 13:56:06.677650 Jitter Meter : NO K
3753 13:56:06.681120 CBT Training : PASS
3754 13:56:06.684132 Write leveling : PASS
3755 13:56:06.684237 RX DQS gating : PASS
3756 13:56:06.687642 RX DQ/DQS(RDDQC) : PASS
3757 13:56:06.687721 TX DQ/DQS : PASS
3758 13:56:06.691034 RX DATLAT : PASS
3759 13:56:06.694384 RX DQ/DQS(Engine): PASS
3760 13:56:06.694484 TX OE : NO K
3761 13:56:06.697764 All Pass.
3762 13:56:06.697865
3763 13:56:06.697960 CH 1, Rank 1
3764 13:56:06.701069 SW Impedance : PASS
3765 13:56:06.701147 DUTY Scan : NO K
3766 13:56:06.704323 ZQ Calibration : PASS
3767 13:56:06.707455 Jitter Meter : NO K
3768 13:56:06.707530 CBT Training : PASS
3769 13:56:06.710691 Write leveling : PASS
3770 13:56:06.714096 RX DQS gating : PASS
3771 13:56:06.714171 RX DQ/DQS(RDDQC) : PASS
3772 13:56:06.717545 TX DQ/DQS : PASS
3773 13:56:06.720910 RX DATLAT : PASS
3774 13:56:06.720985 RX DQ/DQS(Engine): PASS
3775 13:56:06.724297 TX OE : NO K
3776 13:56:06.724375 All Pass.
3777 13:56:06.724440
3778 13:56:06.727696 DramC Write-DBI off
3779 13:56:06.730925 PER_BANK_REFRESH: Hybrid Mode
3780 13:56:06.731003 TX_TRACKING: ON
3781 13:56:06.740881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3782 13:56:06.744331 [FAST_K] Save calibration result to emmc
3783 13:56:06.747687 dramc_set_vcore_voltage set vcore to 650000
3784 13:56:06.750836 Read voltage for 600, 5
3785 13:56:06.750912 Vio18 = 0
3786 13:56:06.750980 Vcore = 650000
3787 13:56:06.753929 Vdram = 0
3788 13:56:06.754028 Vddq = 0
3789 13:56:06.754095 Vmddr = 0
3790 13:56:06.761032 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3791 13:56:06.764408 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3792 13:56:06.767674 MEM_TYPE=3, freq_sel=19
3793 13:56:06.770975 sv_algorithm_assistance_LP4_1600
3794 13:56:06.774125 ============ PULL DRAM RESETB DOWN ============
3795 13:56:06.777503 ========== PULL DRAM RESETB DOWN end =========
3796 13:56:06.783942 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3797 13:56:06.787069 ===================================
3798 13:56:06.787175 LPDDR4 DRAM CONFIGURATION
3799 13:56:06.790560 ===================================
3800 13:56:06.794040 EX_ROW_EN[0] = 0x0
3801 13:56:06.797246 EX_ROW_EN[1] = 0x0
3802 13:56:06.797351 LP4Y_EN = 0x0
3803 13:56:06.800652 WORK_FSP = 0x0
3804 13:56:06.800729 WL = 0x2
3805 13:56:06.803644 RL = 0x2
3806 13:56:06.803721 BL = 0x2
3807 13:56:06.806979 RPST = 0x0
3808 13:56:06.807064 RD_PRE = 0x0
3809 13:56:06.810249 WR_PRE = 0x1
3810 13:56:06.810334 WR_PST = 0x0
3811 13:56:06.813939 DBI_WR = 0x0
3812 13:56:06.814015 DBI_RD = 0x0
3813 13:56:06.817241 OTF = 0x1
3814 13:56:06.820693 ===================================
3815 13:56:06.823736 ===================================
3816 13:56:06.823814 ANA top config
3817 13:56:06.826924 ===================================
3818 13:56:06.830164 DLL_ASYNC_EN = 0
3819 13:56:06.833514 ALL_SLAVE_EN = 1
3820 13:56:06.837513 NEW_RANK_MODE = 1
3821 13:56:06.837597 DLL_IDLE_MODE = 1
3822 13:56:06.840719 LP45_APHY_COMB_EN = 1
3823 13:56:06.843606 TX_ODT_DIS = 1
3824 13:56:06.846937 NEW_8X_MODE = 1
3825 13:56:06.850811 ===================================
3826 13:56:06.854139 ===================================
3827 13:56:06.854249 data_rate = 1200
3828 13:56:06.857395 CKR = 1
3829 13:56:06.860631 DQ_P2S_RATIO = 8
3830 13:56:06.863773 ===================================
3831 13:56:06.867501 CA_P2S_RATIO = 8
3832 13:56:06.870346 DQ_CA_OPEN = 0
3833 13:56:06.873509 DQ_SEMI_OPEN = 0
3834 13:56:06.873619 CA_SEMI_OPEN = 0
3835 13:56:06.876854 CA_FULL_RATE = 0
3836 13:56:06.880055 DQ_CKDIV4_EN = 1
3837 13:56:06.883455 CA_CKDIV4_EN = 1
3838 13:56:06.886774 CA_PREDIV_EN = 0
3839 13:56:06.890050 PH8_DLY = 0
3840 13:56:06.890126 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3841 13:56:06.893424 DQ_AAMCK_DIV = 4
3842 13:56:06.896792 CA_AAMCK_DIV = 4
3843 13:56:06.900233 CA_ADMCK_DIV = 4
3844 13:56:06.903490 DQ_TRACK_CA_EN = 0
3845 13:56:06.906874 CA_PICK = 600
3846 13:56:06.910230 CA_MCKIO = 600
3847 13:56:06.910314 MCKIO_SEMI = 0
3848 13:56:06.913375 PLL_FREQ = 2288
3849 13:56:06.916949 DQ_UI_PI_RATIO = 32
3850 13:56:06.920165 CA_UI_PI_RATIO = 0
3851 13:56:06.923187 ===================================
3852 13:56:06.926582 ===================================
3853 13:56:06.929835 memory_type:LPDDR4
3854 13:56:06.929918 GP_NUM : 10
3855 13:56:06.933476 SRAM_EN : 1
3856 13:56:06.936639 MD32_EN : 0
3857 13:56:06.939762 ===================================
3858 13:56:06.939845 [ANA_INIT] >>>>>>>>>>>>>>
3859 13:56:06.943255 <<<<<< [CONFIGURE PHASE]: ANA_TX
3860 13:56:06.946510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3861 13:56:06.950086 ===================================
3862 13:56:06.953323 data_rate = 1200,PCW = 0X5800
3863 13:56:06.956791 ===================================
3864 13:56:06.959830 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3865 13:56:06.966406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3866 13:56:06.969796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3867 13:56:06.976209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3868 13:56:06.979818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3869 13:56:06.982911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3870 13:56:06.983019 [ANA_INIT] flow start
3871 13:56:06.986498 [ANA_INIT] PLL >>>>>>>>
3872 13:56:06.989788 [ANA_INIT] PLL <<<<<<<<
3873 13:56:06.989867 [ANA_INIT] MIDPI >>>>>>>>
3874 13:56:06.992919 [ANA_INIT] MIDPI <<<<<<<<
3875 13:56:06.996173 [ANA_INIT] DLL >>>>>>>>
3876 13:56:06.996275 [ANA_INIT] flow end
3877 13:56:07.003032 ============ LP4 DIFF to SE enter ============
3878 13:56:07.006284 ============ LP4 DIFF to SE exit ============
3879 13:56:07.009415 [ANA_INIT] <<<<<<<<<<<<<
3880 13:56:07.012780 [Flow] Enable top DCM control >>>>>
3881 13:56:07.016106 [Flow] Enable top DCM control <<<<<
3882 13:56:07.019472 Enable DLL master slave shuffle
3883 13:56:07.022670 ==============================================================
3884 13:56:07.026048 Gating Mode config
3885 13:56:07.029387 ==============================================================
3886 13:56:07.032939 Config description:
3887 13:56:07.042795 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3888 13:56:07.049442 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3889 13:56:07.053097 SELPH_MODE 0: By rank 1: By Phase
3890 13:56:07.059398 ==============================================================
3891 13:56:07.062986 GAT_TRACK_EN = 1
3892 13:56:07.083399 RX_GATING_MODE = 2
3893 13:56:07.083570 RX_GATING_TRACK_MODE = 2
3894 13:56:07.083668 SELPH_MODE = 1
3895 13:56:07.083764 PICG_EARLY_EN = 1
3896 13:56:07.083839 VALID_LAT_VALUE = 1
3897 13:56:07.083928 ==============================================================
3898 13:56:07.086232 Enter into Gating configuration >>>>
3899 13:56:07.089755 Exit from Gating configuration <<<<
3900 13:56:07.092783 Enter into DVFS_PRE_config >>>>>
3901 13:56:07.102911 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3902 13:56:07.106065 Exit from DVFS_PRE_config <<<<<
3903 13:56:07.109463 Enter into PICG configuration >>>>
3904 13:56:07.112899 Exit from PICG configuration <<<<
3905 13:56:07.116221 [RX_INPUT] configuration >>>>>
3906 13:56:07.119599 [RX_INPUT] configuration <<<<<
3907 13:56:07.122896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3908 13:56:07.129399 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3909 13:56:07.135973 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 13:56:07.142452 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 13:56:07.149611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 13:56:07.152948 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 13:56:07.159363 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3914 13:56:07.162558 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3915 13:56:07.165937 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3916 13:56:07.169267 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3917 13:56:07.175795 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3918 13:56:07.179065 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 13:56:07.182507 ===================================
3920 13:56:07.185811 LPDDR4 DRAM CONFIGURATION
3921 13:56:07.188989 ===================================
3922 13:56:07.189085 EX_ROW_EN[0] = 0x0
3923 13:56:07.192738 EX_ROW_EN[1] = 0x0
3924 13:56:07.192815 LP4Y_EN = 0x0
3925 13:56:07.195722 WORK_FSP = 0x0
3926 13:56:07.195835 WL = 0x2
3927 13:56:07.199118 RL = 0x2
3928 13:56:07.199218 BL = 0x2
3929 13:56:07.202655 RPST = 0x0
3930 13:56:07.202733 RD_PRE = 0x0
3931 13:56:07.205928 WR_PRE = 0x1
3932 13:56:07.206011 WR_PST = 0x0
3933 13:56:07.209086 DBI_WR = 0x0
3934 13:56:07.212289 DBI_RD = 0x0
3935 13:56:07.212372 OTF = 0x1
3936 13:56:07.215484 ===================================
3937 13:56:07.218889 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3938 13:56:07.222507 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3939 13:56:07.229079 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3940 13:56:07.232411 ===================================
3941 13:56:07.235739 LPDDR4 DRAM CONFIGURATION
3942 13:56:07.238974 ===================================
3943 13:56:07.239056 EX_ROW_EN[0] = 0x10
3944 13:56:07.242332 EX_ROW_EN[1] = 0x0
3945 13:56:07.242434 LP4Y_EN = 0x0
3946 13:56:07.245809 WORK_FSP = 0x0
3947 13:56:07.245910 WL = 0x2
3948 13:56:07.248912 RL = 0x2
3949 13:56:07.249000 BL = 0x2
3950 13:56:07.252223 RPST = 0x0
3951 13:56:07.252347 RD_PRE = 0x0
3952 13:56:07.255525 WR_PRE = 0x1
3953 13:56:07.255619 WR_PST = 0x0
3954 13:56:07.258913 DBI_WR = 0x0
3955 13:56:07.259035 DBI_RD = 0x0
3956 13:56:07.262325 OTF = 0x1
3957 13:56:07.265446 ===================================
3958 13:56:07.272588 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3959 13:56:07.275770 nWR fixed to 30
3960 13:56:07.278964 [ModeRegInit_LP4] CH0 RK0
3961 13:56:07.279066 [ModeRegInit_LP4] CH0 RK1
3962 13:56:07.282268 [ModeRegInit_LP4] CH1 RK0
3963 13:56:07.285663 [ModeRegInit_LP4] CH1 RK1
3964 13:56:07.285738 match AC timing 17
3965 13:56:07.292269 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3966 13:56:07.295549 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3967 13:56:07.298935 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3968 13:56:07.305401 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3969 13:56:07.308810 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3970 13:56:07.308888 ==
3971 13:56:07.312235 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 13:56:07.315309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 13:56:07.315409 ==
3974 13:56:07.322271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3975 13:56:07.328717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3976 13:56:07.332027 [CA 0] Center 35 (5~66) winsize 62
3977 13:56:07.335390 [CA 1] Center 35 (5~66) winsize 62
3978 13:56:07.338784 [CA 2] Center 33 (3~64) winsize 62
3979 13:56:07.341959 [CA 3] Center 33 (2~64) winsize 63
3980 13:56:07.345931 [CA 4] Center 33 (2~64) winsize 63
3981 13:56:07.348611 [CA 5] Center 32 (2~63) winsize 62
3982 13:56:07.348692
3983 13:56:07.352119 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3984 13:56:07.352226
3985 13:56:07.355157 [CATrainingPosCal] consider 1 rank data
3986 13:56:07.358576 u2DelayCellTimex100 = 270/100 ps
3987 13:56:07.362172 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3988 13:56:07.365544 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3989 13:56:07.368621 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3990 13:56:07.371967 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3991 13:56:07.375218 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3992 13:56:07.378408 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3993 13:56:07.381580
3994 13:56:07.385324 CA PerBit enable=1, Macro0, CA PI delay=32
3995 13:56:07.385430
3996 13:56:07.388628 [CBTSetCACLKResult] CA Dly = 32
3997 13:56:07.388704 CS Dly: 5 (0~36)
3998 13:56:07.388802 ==
3999 13:56:07.391864 Dram Type= 6, Freq= 0, CH_0, rank 1
4000 13:56:07.395251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 13:56:07.395354 ==
4002 13:56:07.401830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4003 13:56:07.408328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4004 13:56:07.411594 [CA 0] Center 35 (5~66) winsize 62
4005 13:56:07.414869 [CA 1] Center 35 (5~66) winsize 62
4006 13:56:07.418278 [CA 2] Center 34 (3~65) winsize 63
4007 13:56:07.421448 [CA 3] Center 34 (3~65) winsize 63
4008 13:56:07.425294 [CA 4] Center 33 (2~64) winsize 63
4009 13:56:07.427916 [CA 5] Center 32 (2~63) winsize 62
4010 13:56:07.428022
4011 13:56:07.431934 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4012 13:56:07.432013
4013 13:56:07.435298 [CATrainingPosCal] consider 2 rank data
4014 13:56:07.438543 u2DelayCellTimex100 = 270/100 ps
4015 13:56:07.441747 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4016 13:56:07.444958 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4017 13:56:07.448580 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4018 13:56:07.451760 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4019 13:56:07.454662 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4020 13:56:07.461656 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4021 13:56:07.461759
4022 13:56:07.464797 CA PerBit enable=1, Macro0, CA PI delay=32
4023 13:56:07.464872
4024 13:56:07.468443 [CBTSetCACLKResult] CA Dly = 32
4025 13:56:07.468535 CS Dly: 5 (0~36)
4026 13:56:07.468612
4027 13:56:07.471294 ----->DramcWriteLeveling(PI) begin...
4028 13:56:07.471401 ==
4029 13:56:07.474990 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 13:56:07.478491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 13:56:07.481426 ==
4032 13:56:07.481501 Write leveling (Byte 0): 34 => 34
4033 13:56:07.484722 Write leveling (Byte 1): 31 => 31
4034 13:56:07.488435 DramcWriteLeveling(PI) end<-----
4035 13:56:07.488508
4036 13:56:07.488570 ==
4037 13:56:07.491413 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 13:56:07.498203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 13:56:07.498281 ==
4040 13:56:07.501722 [Gating] SW mode calibration
4041 13:56:07.508319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4042 13:56:07.511616 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4043 13:56:07.518196 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 13:56:07.521358 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 13:56:07.524804 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 13:56:07.527869 0 9 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
4047 13:56:07.534535 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
4048 13:56:07.537902 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 13:56:07.541146 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 13:56:07.547638 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 13:56:07.551485 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 13:56:07.554722 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 13:56:07.561422 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 13:56:07.564791 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
4055 13:56:07.568023 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4056 13:56:07.574849 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 13:56:07.577971 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 13:56:07.581108 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 13:56:07.588013 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 13:56:07.591177 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 13:56:07.594764 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 13:56:07.601219 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4063 13:56:07.604616 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:56:07.607680 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:56:07.614910 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 13:56:07.617593 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 13:56:07.620927 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 13:56:07.628022 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 13:56:07.631341 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 13:56:07.634613 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:56:07.641112 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:56:07.644300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:56:07.648181 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 13:56:07.651571 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 13:56:07.657562 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 13:56:07.660880 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 13:56:07.664134 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 13:56:07.670978 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4079 13:56:07.674241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4080 13:56:07.677372 Total UI for P1: 0, mck2ui 16
4081 13:56:07.680665 best dqsien dly found for B0: ( 0, 13, 12)
4082 13:56:07.684298 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 13:56:07.687847 Total UI for P1: 0, mck2ui 16
4084 13:56:07.691114 best dqsien dly found for B1: ( 0, 13, 18)
4085 13:56:07.694524 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4086 13:56:07.701010 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4087 13:56:07.701098
4088 13:56:07.704308 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4089 13:56:07.707536 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4090 13:56:07.710684 [Gating] SW calibration Done
4091 13:56:07.710761 ==
4092 13:56:07.713876 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 13:56:07.717183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 13:56:07.717260 ==
4095 13:56:07.720665 RX Vref Scan: 0
4096 13:56:07.720762
4097 13:56:07.720831 RX Vref 0 -> 0, step: 1
4098 13:56:07.720892
4099 13:56:07.723991 RX Delay -230 -> 252, step: 16
4100 13:56:07.727661 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4101 13:56:07.734109 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4102 13:56:07.736956 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4103 13:56:07.740637 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4104 13:56:07.743730 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4105 13:56:07.747487 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4106 13:56:07.754081 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4107 13:56:07.757404 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4108 13:56:07.760676 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4109 13:56:07.763901 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4110 13:56:07.770636 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4111 13:56:07.774043 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4112 13:56:07.776783 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4113 13:56:07.780670 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4114 13:56:07.787305 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4115 13:56:07.790615 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4116 13:56:07.790692 ==
4117 13:56:07.793641 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 13:56:07.797214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 13:56:07.797318 ==
4120 13:56:07.800221 DQS Delay:
4121 13:56:07.800359 DQS0 = 0, DQS1 = 0
4122 13:56:07.800471 DQM Delay:
4123 13:56:07.803913 DQM0 = 51, DQM1 = 46
4124 13:56:07.804021 DQ Delay:
4125 13:56:07.807244 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4126 13:56:07.810562 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4127 13:56:07.813878 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4128 13:56:07.816987 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4129 13:56:07.817086
4130 13:56:07.817184
4131 13:56:07.817277 ==
4132 13:56:07.820329 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 13:56:07.823708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 13:56:07.826987 ==
4135 13:56:07.827065
4136 13:56:07.827135
4137 13:56:07.827227 TX Vref Scan disable
4138 13:56:07.830212 == TX Byte 0 ==
4139 13:56:07.833551 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4140 13:56:07.840308 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4141 13:56:07.840403 == TX Byte 1 ==
4142 13:56:07.843903 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4143 13:56:07.850617 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4144 13:56:07.850698 ==
4145 13:56:07.853810 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 13:56:07.857025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 13:56:07.857104 ==
4148 13:56:07.857169
4149 13:56:07.857260
4150 13:56:07.860519 TX Vref Scan disable
4151 13:56:07.863564 == TX Byte 0 ==
4152 13:56:07.866814 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4153 13:56:07.870124 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4154 13:56:07.873204 == TX Byte 1 ==
4155 13:56:07.876612 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4156 13:56:07.879947 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4157 13:56:07.880022
4158 13:56:07.880086 [DATLAT]
4159 13:56:07.883232 Freq=600, CH0 RK0
4160 13:56:07.883310
4161 13:56:07.886994 DATLAT Default: 0x9
4162 13:56:07.887072 0, 0xFFFF, sum = 0
4163 13:56:07.889751 1, 0xFFFF, sum = 0
4164 13:56:07.889828 2, 0xFFFF, sum = 0
4165 13:56:07.893076 3, 0xFFFF, sum = 0
4166 13:56:07.893151 4, 0xFFFF, sum = 0
4167 13:56:07.896440 5, 0xFFFF, sum = 0
4168 13:56:07.896515 6, 0xFFFF, sum = 0
4169 13:56:07.899738 7, 0xFFFF, sum = 0
4170 13:56:07.899840 8, 0x0, sum = 1
4171 13:56:07.903031 9, 0x0, sum = 2
4172 13:56:07.903132 10, 0x0, sum = 3
4173 13:56:07.903228 11, 0x0, sum = 4
4174 13:56:07.906897 best_step = 9
4175 13:56:07.906998
4176 13:56:07.907076 ==
4177 13:56:07.909872 Dram Type= 6, Freq= 0, CH_0, rank 0
4178 13:56:07.913087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 13:56:07.913165 ==
4180 13:56:07.916416 RX Vref Scan: 1
4181 13:56:07.916516
4182 13:56:07.916609 RX Vref 0 -> 0, step: 1
4183 13:56:07.916697
4184 13:56:07.919669 RX Delay -163 -> 252, step: 8
4185 13:56:07.919744
4186 13:56:07.923019 Set Vref, RX VrefLevel [Byte0]: 58
4187 13:56:07.926389 [Byte1]: 47
4188 13:56:07.931009
4189 13:56:07.931084 Final RX Vref Byte 0 = 58 to rank0
4190 13:56:07.934362 Final RX Vref Byte 1 = 47 to rank0
4191 13:56:07.937769 Final RX Vref Byte 0 = 58 to rank1
4192 13:56:07.940364 Final RX Vref Byte 1 = 47 to rank1==
4193 13:56:07.943714 Dram Type= 6, Freq= 0, CH_0, rank 0
4194 13:56:07.950725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 13:56:07.950829 ==
4196 13:56:07.950921 DQS Delay:
4197 13:56:07.951013 DQS0 = 0, DQS1 = 0
4198 13:56:07.954078 DQM Delay:
4199 13:56:07.954176 DQM0 = 53, DQM1 = 47
4200 13:56:07.957296 DQ Delay:
4201 13:56:07.960377 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4202 13:56:07.964302 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =64
4203 13:56:07.964393 DQ8 =36, DQ9 =36, DQ10 =52, DQ11 =40
4204 13:56:07.970562 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4205 13:56:07.970667
4206 13:56:07.970759
4207 13:56:07.977229 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f63, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4208 13:56:07.980775 CH0 RK0: MR19=808, MR18=6F63
4209 13:56:07.987342 CH0_RK0: MR19=0x808, MR18=0x6F63, DQSOSC=389, MR23=63, INC=173, DEC=115
4210 13:56:07.987446
4211 13:56:07.990671 ----->DramcWriteLeveling(PI) begin...
4212 13:56:07.990774 ==
4213 13:56:07.994052 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 13:56:07.997254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 13:56:07.997336 ==
4216 13:56:08.000571 Write leveling (Byte 0): 34 => 34
4217 13:56:08.003891 Write leveling (Byte 1): 31 => 31
4218 13:56:08.007118 DramcWriteLeveling(PI) end<-----
4219 13:56:08.007197
4220 13:56:08.007261 ==
4221 13:56:08.010383 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 13:56:08.013564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 13:56:08.013642 ==
4224 13:56:08.016892 [Gating] SW mode calibration
4225 13:56:08.023883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4226 13:56:08.030271 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4227 13:56:08.033680 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 13:56:08.036897 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 13:56:08.043647 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 13:56:08.046962 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
4231 13:56:08.050349 0 9 16 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)
4232 13:56:08.056847 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 13:56:08.060148 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 13:56:08.063459 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 13:56:08.070634 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 13:56:08.073958 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 13:56:08.076700 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 13:56:08.083844 0 10 12 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4239 13:56:08.087242 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4240 13:56:08.090514 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 13:56:08.096843 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 13:56:08.100486 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 13:56:08.103683 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 13:56:08.110150 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 13:56:08.112981 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 13:56:08.116447 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 13:56:08.122979 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 13:56:08.126745 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 13:56:08.129963 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 13:56:08.136805 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 13:56:08.140047 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 13:56:08.143347 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 13:56:08.149451 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 13:56:08.152726 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 13:56:08.156066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 13:56:08.162903 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 13:56:08.166619 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 13:56:08.169278 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 13:56:08.175977 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 13:56:08.179099 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 13:56:08.182440 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 13:56:08.189698 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4263 13:56:08.192987 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 13:56:08.196206 Total UI for P1: 0, mck2ui 16
4265 13:56:08.199645 best dqsien dly found for B0: ( 0, 13, 14)
4266 13:56:08.202946 Total UI for P1: 0, mck2ui 16
4267 13:56:08.206213 best dqsien dly found for B1: ( 0, 13, 12)
4268 13:56:08.209508 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4269 13:56:08.212804 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4270 13:56:08.212910
4271 13:56:08.216008 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4272 13:56:08.219144 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4273 13:56:08.223032 [Gating] SW calibration Done
4274 13:56:08.223115 ==
4275 13:56:08.226108 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 13:56:08.228994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 13:56:08.232736 ==
4278 13:56:08.232839 RX Vref Scan: 0
4279 13:56:08.232932
4280 13:56:08.235619 RX Vref 0 -> 0, step: 1
4281 13:56:08.235695
4282 13:56:08.238861 RX Delay -230 -> 252, step: 16
4283 13:56:08.242606 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4284 13:56:08.245588 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4285 13:56:08.249251 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4286 13:56:08.252735 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4287 13:56:08.259386 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4288 13:56:08.262753 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4289 13:56:08.265436 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4290 13:56:08.268696 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4291 13:56:08.275907 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4292 13:56:08.279285 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4293 13:56:08.282545 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4294 13:56:08.285743 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4295 13:56:08.292243 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4296 13:56:08.295335 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4297 13:56:08.298661 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4298 13:56:08.301921 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4299 13:56:08.302026 ==
4300 13:56:08.305260 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 13:56:08.311788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 13:56:08.311895 ==
4303 13:56:08.311989 DQS Delay:
4304 13:56:08.312081 DQS0 = 0, DQS1 = 0
4305 13:56:08.315182 DQM Delay:
4306 13:56:08.315301 DQM0 = 54, DQM1 = 43
4307 13:56:08.318525 DQ Delay:
4308 13:56:08.321807 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4309 13:56:08.325652 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4310 13:56:08.328931 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4311 13:56:08.332197 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4312 13:56:08.332308
4313 13:56:08.332378
4314 13:56:08.332448 ==
4315 13:56:08.335622 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 13:56:08.338894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 13:56:08.338998 ==
4318 13:56:08.339091
4319 13:56:08.339183
4320 13:56:08.342223 TX Vref Scan disable
4321 13:56:08.342324 == TX Byte 0 ==
4322 13:56:08.348909 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4323 13:56:08.351822 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4324 13:56:08.351907 == TX Byte 1 ==
4325 13:56:08.358822 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4326 13:56:08.362247 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4327 13:56:08.362361 ==
4328 13:56:08.365353 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 13:56:08.368812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 13:56:08.368920 ==
4331 13:56:08.369015
4332 13:56:08.369105
4333 13:56:08.371738 TX Vref Scan disable
4334 13:56:08.375144 == TX Byte 0 ==
4335 13:56:08.378816 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4336 13:56:08.381825 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4337 13:56:08.385660 == TX Byte 1 ==
4338 13:56:08.388959 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4339 13:56:08.392239 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4340 13:56:08.395514
4341 13:56:08.395623 [DATLAT]
4342 13:56:08.395721 Freq=600, CH0 RK1
4343 13:56:08.395813
4344 13:56:08.398720 DATLAT Default: 0x9
4345 13:56:08.398825 0, 0xFFFF, sum = 0
4346 13:56:08.401895 1, 0xFFFF, sum = 0
4347 13:56:08.402007 2, 0xFFFF, sum = 0
4348 13:56:08.405220 3, 0xFFFF, sum = 0
4349 13:56:08.408576 4, 0xFFFF, sum = 0
4350 13:56:08.408655 5, 0xFFFF, sum = 0
4351 13:56:08.411894 6, 0xFFFF, sum = 0
4352 13:56:08.412000 7, 0xFFFF, sum = 0
4353 13:56:08.415179 8, 0x0, sum = 1
4354 13:56:08.415289 9, 0x0, sum = 2
4355 13:56:08.415384 10, 0x0, sum = 3
4356 13:56:08.418512 11, 0x0, sum = 4
4357 13:56:08.418612 best_step = 9
4358 13:56:08.418706
4359 13:56:08.418794 ==
4360 13:56:08.421812 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 13:56:08.428438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 13:56:08.428519 ==
4363 13:56:08.428588 RX Vref Scan: 0
4364 13:56:08.428650
4365 13:56:08.431741 RX Vref 0 -> 0, step: 1
4366 13:56:08.431840
4367 13:56:08.434981 RX Delay -163 -> 252, step: 8
4368 13:56:08.438341 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4369 13:56:08.444917 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4370 13:56:08.448221 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4371 13:56:08.451575 iDelay=205, Bit 3, Center 48 (-99 ~ 196) 296
4372 13:56:08.454916 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4373 13:56:08.458232 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4374 13:56:08.464637 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4375 13:56:08.468038 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4376 13:56:08.471466 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4377 13:56:08.474633 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4378 13:56:08.478287 iDelay=205, Bit 10, Center 52 (-83 ~ 188) 272
4379 13:56:08.484709 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4380 13:56:08.488004 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4381 13:56:08.491348 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4382 13:56:08.494968 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4383 13:56:08.497892 iDelay=205, Bit 15, Center 56 (-83 ~ 196) 280
4384 13:56:08.501408 ==
4385 13:56:08.501517 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 13:56:08.508313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 13:56:08.508423 ==
4388 13:56:08.508521 DQS Delay:
4389 13:56:08.511819 DQS0 = 0, DQS1 = 0
4390 13:56:08.511903 DQM Delay:
4391 13:56:08.511969 DQM0 = 52, DQM1 = 47
4392 13:56:08.514925 DQ Delay:
4393 13:56:08.518286 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =48
4394 13:56:08.521738 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4395 13:56:08.524675 DQ8 =40, DQ9 =32, DQ10 =52, DQ11 =40
4396 13:56:08.528528 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4397 13:56:08.528607
4398 13:56:08.528672
4399 13:56:08.535049 [DQSOSCAuto] RK1, (LSB)MR18= 0x6122, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4400 13:56:08.538253 CH0 RK1: MR19=808, MR18=6122
4401 13:56:08.545025 CH0_RK1: MR19=0x808, MR18=0x6122, DQSOSC=391, MR23=63, INC=171, DEC=114
4402 13:56:08.548341 [RxdqsGatingPostProcess] freq 600
4403 13:56:08.551576 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4404 13:56:08.554970 Pre-setting of DQS Precalculation
4405 13:56:08.561712 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4406 13:56:08.561840 ==
4407 13:56:08.564987 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 13:56:08.568309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 13:56:08.568398 ==
4410 13:56:08.574944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4411 13:56:08.581657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4412 13:56:08.584405 [CA 0] Center 35 (5~66) winsize 62
4413 13:56:08.588322 [CA 1] Center 35 (5~66) winsize 62
4414 13:56:08.591705 [CA 2] Center 34 (4~65) winsize 62
4415 13:56:08.595036 [CA 3] Center 34 (4~65) winsize 62
4416 13:56:08.598178 [CA 4] Center 34 (4~65) winsize 62
4417 13:56:08.601220 [CA 5] Center 34 (4~64) winsize 61
4418 13:56:08.601319
4419 13:56:08.604940 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4420 13:56:08.605041
4421 13:56:08.607995 [CATrainingPosCal] consider 1 rank data
4422 13:56:08.611079 u2DelayCellTimex100 = 270/100 ps
4423 13:56:08.614459 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4424 13:56:08.617834 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4425 13:56:08.621128 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4426 13:56:08.624814 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4427 13:56:08.627627 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4428 13:56:08.631083 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4429 13:56:08.631228
4430 13:56:08.634592 CA PerBit enable=1, Macro0, CA PI delay=34
4431 13:56:08.634714
4432 13:56:08.637807 [CBTSetCACLKResult] CA Dly = 34
4433 13:56:08.641405 CS Dly: 5 (0~36)
4434 13:56:08.641500 ==
4435 13:56:08.644790 Dram Type= 6, Freq= 0, CH_1, rank 1
4436 13:56:08.647890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 13:56:08.647992 ==
4438 13:56:08.654279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4439 13:56:08.660935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4440 13:56:08.664172 [CA 0] Center 36 (5~67) winsize 63
4441 13:56:08.667451 [CA 1] Center 36 (5~67) winsize 63
4442 13:56:08.671252 [CA 2] Center 34 (4~65) winsize 62
4443 13:56:08.674561 [CA 3] Center 34 (4~65) winsize 62
4444 13:56:08.677898 [CA 4] Center 34 (4~65) winsize 62
4445 13:56:08.680635 [CA 5] Center 34 (3~65) winsize 63
4446 13:56:08.680749
4447 13:56:08.684070 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4448 13:56:08.684181
4449 13:56:08.687343 [CATrainingPosCal] consider 2 rank data
4450 13:56:08.690662 u2DelayCellTimex100 = 270/100 ps
4451 13:56:08.694086 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4452 13:56:08.697254 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4453 13:56:08.700618 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4454 13:56:08.703906 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4455 13:56:08.707658 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4456 13:56:08.710739 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4457 13:56:08.710865
4458 13:56:08.717643 CA PerBit enable=1, Macro0, CA PI delay=34
4459 13:56:08.717783
4460 13:56:08.717881 [CBTSetCACLKResult] CA Dly = 34
4461 13:56:08.720792 CS Dly: 5 (0~37)
4462 13:56:08.720887
4463 13:56:08.724030 ----->DramcWriteLeveling(PI) begin...
4464 13:56:08.724134 ==
4465 13:56:08.727617 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 13:56:08.730547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 13:56:08.730654 ==
4468 13:56:08.734182 Write leveling (Byte 0): 29 => 29
4469 13:56:08.737268 Write leveling (Byte 1): 30 => 30
4470 13:56:08.740619 DramcWriteLeveling(PI) end<-----
4471 13:56:08.740731
4472 13:56:08.740827 ==
4473 13:56:08.743922 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 13:56:08.747225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 13:56:08.750527 ==
4476 13:56:08.750644 [Gating] SW mode calibration
4477 13:56:08.760634 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4478 13:56:08.763531 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4479 13:56:08.766845 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 13:56:08.773537 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 13:56:08.777003 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 13:56:08.780239 0 9 12 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (0 0)
4483 13:56:08.787474 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
4484 13:56:08.790752 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 13:56:08.794179 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 13:56:08.800225 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 13:56:08.803612 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 13:56:08.806913 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 13:56:08.813454 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4490 13:56:08.817245 0 10 12 | B1->B0 | 3939 3737 | 0 0 | (0 0) (0 0)
4491 13:56:08.820670 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 13:56:08.827229 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 13:56:08.830642 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 13:56:08.833871 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 13:56:08.840744 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 13:56:08.843600 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 13:56:08.846960 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 13:56:08.853496 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4499 13:56:08.857155 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 13:56:08.860357 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 13:56:08.863646 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 13:56:08.870324 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 13:56:08.873606 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 13:56:08.877110 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:56:08.883497 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 13:56:08.886745 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 13:56:08.890441 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 13:56:08.896481 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 13:56:08.900142 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 13:56:08.903700 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 13:56:08.909960 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 13:56:08.913344 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 13:56:08.916547 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4514 13:56:08.922995 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4515 13:56:08.926332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 13:56:08.930403 Total UI for P1: 0, mck2ui 16
4517 13:56:08.933766 best dqsien dly found for B0: ( 0, 13, 10)
4518 13:56:08.936441 Total UI for P1: 0, mck2ui 16
4519 13:56:08.940471 best dqsien dly found for B1: ( 0, 13, 10)
4520 13:56:08.943120 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4521 13:56:08.946490 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4522 13:56:08.946592
4523 13:56:08.949722 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4524 13:56:08.953571 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4525 13:56:08.956703 [Gating] SW calibration Done
4526 13:56:08.956807 ==
4527 13:56:08.959688 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 13:56:08.963133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 13:56:08.966658 ==
4530 13:56:08.966772 RX Vref Scan: 0
4531 13:56:08.966867
4532 13:56:08.969689 RX Vref 0 -> 0, step: 1
4533 13:56:08.969795
4534 13:56:08.973142 RX Delay -230 -> 252, step: 16
4535 13:56:08.976435 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4536 13:56:08.979742 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4537 13:56:08.982895 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4538 13:56:08.989973 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4539 13:56:08.993208 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4540 13:56:08.996305 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4541 13:56:08.999574 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4542 13:56:09.002757 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4543 13:56:09.009780 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4544 13:56:09.013123 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4545 13:56:09.016095 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4546 13:56:09.019686 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4547 13:56:09.026297 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4548 13:56:09.029416 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4549 13:56:09.032754 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4550 13:56:09.036139 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4551 13:56:09.039502 ==
4552 13:56:09.039607 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 13:56:09.045647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 13:56:09.045752 ==
4555 13:56:09.045848 DQS Delay:
4556 13:56:09.049031 DQS0 = 0, DQS1 = 0
4557 13:56:09.049134 DQM Delay:
4558 13:56:09.052372 DQM0 = 49, DQM1 = 46
4559 13:56:09.052450 DQ Delay:
4560 13:56:09.055598 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4561 13:56:09.058912 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =49
4562 13:56:09.062263 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4563 13:56:09.065486 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4564 13:56:09.065594
4565 13:56:09.065699
4566 13:56:09.065791 ==
4567 13:56:09.068847 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 13:56:09.072582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 13:56:09.072697 ==
4570 13:56:09.072794
4571 13:56:09.072896
4572 13:56:09.075656 TX Vref Scan disable
4573 13:56:09.078813 == TX Byte 0 ==
4574 13:56:09.082271 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4575 13:56:09.085624 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4576 13:56:09.088783 == TX Byte 1 ==
4577 13:56:09.092030 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4578 13:56:09.095434 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4579 13:56:09.095555 ==
4580 13:56:09.098905 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 13:56:09.105464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 13:56:09.105579 ==
4583 13:56:09.105676
4584 13:56:09.105771
4585 13:56:09.105863 TX Vref Scan disable
4586 13:56:09.109172 == TX Byte 0 ==
4587 13:56:09.112818 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4588 13:56:09.119123 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4589 13:56:09.119233 == TX Byte 1 ==
4590 13:56:09.122436 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4591 13:56:09.129149 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4592 13:56:09.129256
4593 13:56:09.129351 [DATLAT]
4594 13:56:09.129445 Freq=600, CH1 RK0
4595 13:56:09.129535
4596 13:56:09.132754 DATLAT Default: 0x9
4597 13:56:09.132854 0, 0xFFFF, sum = 0
4598 13:56:09.135666 1, 0xFFFF, sum = 0
4599 13:56:09.139267 2, 0xFFFF, sum = 0
4600 13:56:09.139379 3, 0xFFFF, sum = 0
4601 13:56:09.142589 4, 0xFFFF, sum = 0
4602 13:56:09.142693 5, 0xFFFF, sum = 0
4603 13:56:09.145963 6, 0xFFFF, sum = 0
4604 13:56:09.146067 7, 0xFFFF, sum = 0
4605 13:56:09.149340 8, 0x0, sum = 1
4606 13:56:09.149443 9, 0x0, sum = 2
4607 13:56:09.149554 10, 0x0, sum = 3
4608 13:56:09.152730 11, 0x0, sum = 4
4609 13:56:09.152837 best_step = 9
4610 13:56:09.152928
4611 13:56:09.153018 ==
4612 13:56:09.155931 Dram Type= 6, Freq= 0, CH_1, rank 0
4613 13:56:09.162710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 13:56:09.162822 ==
4615 13:56:09.162929 RX Vref Scan: 1
4616 13:56:09.163032
4617 13:56:09.166000 RX Vref 0 -> 0, step: 1
4618 13:56:09.166106
4619 13:56:09.169388 RX Delay -163 -> 252, step: 8
4620 13:56:09.169505
4621 13:56:09.172772 Set Vref, RX VrefLevel [Byte0]: 53
4622 13:56:09.175916 [Byte1]: 47
4623 13:56:09.176024
4624 13:56:09.179329 Final RX Vref Byte 0 = 53 to rank0
4625 13:56:09.182742 Final RX Vref Byte 1 = 47 to rank0
4626 13:56:09.185957 Final RX Vref Byte 0 = 53 to rank1
4627 13:56:09.189240 Final RX Vref Byte 1 = 47 to rank1==
4628 13:56:09.192363 Dram Type= 6, Freq= 0, CH_1, rank 0
4629 13:56:09.195858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 13:56:09.195963 ==
4631 13:56:09.198842 DQS Delay:
4632 13:56:09.198947 DQS0 = 0, DQS1 = 0
4633 13:56:09.202441 DQM Delay:
4634 13:56:09.202548 DQM0 = 48, DQM1 = 46
4635 13:56:09.202655 DQ Delay:
4636 13:56:09.205346 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4637 13:56:09.208797 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4638 13:56:09.212233 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4639 13:56:09.215605 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4640 13:56:09.215714
4641 13:56:09.215816
4642 13:56:09.225472 [DQSOSCAuto] RK0, (LSB)MR18= 0x486e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4643 13:56:09.229406 CH1 RK0: MR19=808, MR18=486E
4644 13:56:09.232246 CH1_RK0: MR19=0x808, MR18=0x486E, DQSOSC=389, MR23=63, INC=173, DEC=115
4645 13:56:09.235795
4646 13:56:09.238921 ----->DramcWriteLeveling(PI) begin...
4647 13:56:09.239032 ==
4648 13:56:09.242704 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 13:56:09.245772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 13:56:09.245878 ==
4651 13:56:09.249340 Write leveling (Byte 0): 31 => 31
4652 13:56:09.252626 Write leveling (Byte 1): 32 => 32
4653 13:56:09.255277 DramcWriteLeveling(PI) end<-----
4654 13:56:09.255380
4655 13:56:09.255482 ==
4656 13:56:09.260266 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 13:56:09.262341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 13:56:09.262450 ==
4659 13:56:09.265721 [Gating] SW mode calibration
4660 13:56:09.272614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4661 13:56:09.279331 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4662 13:56:09.282705 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4663 13:56:09.285377 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4664 13:56:09.288750 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4665 13:56:09.296069 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (1 1)
4666 13:56:09.299333 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4667 13:56:09.302629 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 13:56:09.309330 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 13:56:09.312475 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 13:56:09.315498 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 13:56:09.322436 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 13:56:09.325558 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 13:56:09.328899 0 10 12 | B1->B0 | 3d3d 3535 | 0 0 | (1 1) (0 0)
4674 13:56:09.335752 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 13:56:09.339280 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 13:56:09.342233 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 13:56:09.348966 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 13:56:09.352538 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 13:56:09.355641 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 13:56:09.362053 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 13:56:09.365708 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4682 13:56:09.369075 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 13:56:09.375868 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 13:56:09.378812 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 13:56:09.382656 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 13:56:09.385831 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 13:56:09.392491 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 13:56:09.395814 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 13:56:09.399131 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 13:56:09.405755 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 13:56:09.409086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 13:56:09.412428 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 13:56:09.419077 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 13:56:09.422217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 13:56:09.425306 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 13:56:09.432095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4697 13:56:09.435214 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4698 13:56:09.439139 Total UI for P1: 0, mck2ui 16
4699 13:56:09.441898 best dqsien dly found for B1: ( 0, 13, 8)
4700 13:56:09.445248 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 13:56:09.448581 Total UI for P1: 0, mck2ui 16
4702 13:56:09.451885 best dqsien dly found for B0: ( 0, 13, 10)
4703 13:56:09.455700 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4704 13:56:09.458788 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4705 13:56:09.458895
4706 13:56:09.465169 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4707 13:56:09.468687 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4708 13:56:09.468793 [Gating] SW calibration Done
4709 13:56:09.471779 ==
4710 13:56:09.475710 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 13:56:09.478931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 13:56:09.479043 ==
4713 13:56:09.479139 RX Vref Scan: 0
4714 13:56:09.479230
4715 13:56:09.482090 RX Vref 0 -> 0, step: 1
4716 13:56:09.482197
4717 13:56:09.485052 RX Delay -230 -> 252, step: 16
4718 13:56:09.488453 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4719 13:56:09.492046 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4720 13:56:09.498367 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4721 13:56:09.501749 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4722 13:56:09.505049 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4723 13:56:09.508348 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4724 13:56:09.515091 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4725 13:56:09.518667 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4726 13:56:09.521948 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4727 13:56:09.525181 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4728 13:56:09.528421 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4729 13:56:09.534922 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4730 13:56:09.538170 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4731 13:56:09.542060 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4732 13:56:09.544998 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4733 13:56:09.551470 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4734 13:56:09.551576 ==
4735 13:56:09.554852 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 13:56:09.558280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 13:56:09.558384 ==
4738 13:56:09.558489 DQS Delay:
4739 13:56:09.561684 DQS0 = 0, DQS1 = 0
4740 13:56:09.561790 DQM Delay:
4741 13:56:09.564898 DQM0 = 49, DQM1 = 46
4742 13:56:09.565012 DQ Delay:
4743 13:56:09.568153 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4744 13:56:09.571780 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4745 13:56:09.574818 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4746 13:56:09.577992 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4747 13:56:09.578100
4748 13:56:09.578193
4749 13:56:09.578295 ==
4750 13:56:09.581672 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 13:56:09.584651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 13:56:09.584752 ==
4753 13:56:09.588406
4754 13:56:09.588511
4755 13:56:09.588608 TX Vref Scan disable
4756 13:56:09.591726 == TX Byte 0 ==
4757 13:56:09.594861 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4758 13:56:09.598421 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4759 13:56:09.601364 == TX Byte 1 ==
4760 13:56:09.604602 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4761 13:56:09.608193 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4762 13:56:09.608301 ==
4763 13:56:09.611118 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 13:56:09.618043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 13:56:09.618125 ==
4766 13:56:09.618192
4767 13:56:09.618253
4768 13:56:09.621262 TX Vref Scan disable
4769 13:56:09.621334 == TX Byte 0 ==
4770 13:56:09.627983 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4771 13:56:09.631227 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4772 13:56:09.631328 == TX Byte 1 ==
4773 13:56:09.637885 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4774 13:56:09.641113 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4775 13:56:09.641200
4776 13:56:09.641264 [DATLAT]
4777 13:56:09.644147 Freq=600, CH1 RK1
4778 13:56:09.644248
4779 13:56:09.644345 DATLAT Default: 0x9
4780 13:56:09.648003 0, 0xFFFF, sum = 0
4781 13:56:09.648115 1, 0xFFFF, sum = 0
4782 13:56:09.651162 2, 0xFFFF, sum = 0
4783 13:56:09.651264 3, 0xFFFF, sum = 0
4784 13:56:09.654379 4, 0xFFFF, sum = 0
4785 13:56:09.654502 5, 0xFFFF, sum = 0
4786 13:56:09.657987 6, 0xFFFF, sum = 0
4787 13:56:09.658092 7, 0xFFFF, sum = 0
4788 13:56:09.661249 8, 0x0, sum = 1
4789 13:56:09.661352 9, 0x0, sum = 2
4790 13:56:09.664715 10, 0x0, sum = 3
4791 13:56:09.664795 11, 0x0, sum = 4
4792 13:56:09.667398 best_step = 9
4793 13:56:09.667493
4794 13:56:09.667556 ==
4795 13:56:09.670668 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 13:56:09.673953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 13:56:09.674054 ==
4798 13:56:09.677854 RX Vref Scan: 0
4799 13:56:09.677952
4800 13:56:09.678041 RX Vref 0 -> 0, step: 1
4801 13:56:09.678153
4802 13:56:09.681066 RX Delay -163 -> 252, step: 8
4803 13:56:09.688020 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4804 13:56:09.691271 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4805 13:56:09.694445 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4806 13:56:09.697906 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4807 13:56:09.701481 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4808 13:56:09.707833 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4809 13:56:09.711140 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4810 13:56:09.714491 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4811 13:56:09.717618 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4812 13:56:09.724120 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4813 13:56:09.727629 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4814 13:56:09.730743 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4815 13:56:09.734728 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4816 13:56:09.737442 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4817 13:56:09.744442 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4818 13:56:09.747799 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4819 13:56:09.747904 ==
4820 13:56:09.751087 Dram Type= 6, Freq= 0, CH_1, rank 1
4821 13:56:09.754330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4822 13:56:09.754433 ==
4823 13:56:09.757635 DQS Delay:
4824 13:56:09.757739 DQS0 = 0, DQS1 = 0
4825 13:56:09.757836 DQM Delay:
4826 13:56:09.760928 DQM0 = 49, DQM1 = 44
4827 13:56:09.761033 DQ Delay:
4828 13:56:09.764312 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4829 13:56:09.767227 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4830 13:56:09.770493 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4831 13:56:09.773760 DQ12 =56, DQ13 =52, DQ14 =48, DQ15 =52
4832 13:56:09.773866
4833 13:56:09.773968
4834 13:56:09.783912 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4835 13:56:09.787164 CH1 RK1: MR19=808, MR18=6B22
4836 13:56:09.790887 CH1_RK1: MR19=0x808, MR18=0x6B22, DQSOSC=389, MR23=63, INC=173, DEC=115
4837 13:56:09.794212 [RxdqsGatingPostProcess] freq 600
4838 13:56:09.800346 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4839 13:56:09.803594 Pre-setting of DQS Precalculation
4840 13:56:09.807245 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4841 13:56:09.817036 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4842 13:56:09.823950 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4843 13:56:09.824058
4844 13:56:09.824156
4845 13:56:09.827069 [Calibration Summary] 1200 Mbps
4846 13:56:09.827175 CH 0, Rank 0
4847 13:56:09.830728 SW Impedance : PASS
4848 13:56:09.830839 DUTY Scan : NO K
4849 13:56:09.833887 ZQ Calibration : PASS
4850 13:56:09.837458 Jitter Meter : NO K
4851 13:56:09.837563 CBT Training : PASS
4852 13:56:09.840602 Write leveling : PASS
4853 13:56:09.843998 RX DQS gating : PASS
4854 13:56:09.844107 RX DQ/DQS(RDDQC) : PASS
4855 13:56:09.847185 TX DQ/DQS : PASS
4856 13:56:09.847293 RX DATLAT : PASS
4857 13:56:09.850336 RX DQ/DQS(Engine): PASS
4858 13:56:09.853520 TX OE : NO K
4859 13:56:09.853628 All Pass.
4860 13:56:09.853723
4861 13:56:09.853830 CH 0, Rank 1
4862 13:56:09.856959 SW Impedance : PASS
4863 13:56:09.860214 DUTY Scan : NO K
4864 13:56:09.860333 ZQ Calibration : PASS
4865 13:56:09.863660 Jitter Meter : NO K
4866 13:56:09.867037 CBT Training : PASS
4867 13:56:09.867142 Write leveling : PASS
4868 13:56:09.870302 RX DQS gating : PASS
4869 13:56:09.873371 RX DQ/DQS(RDDQC) : PASS
4870 13:56:09.873476 TX DQ/DQS : PASS
4871 13:56:09.877137 RX DATLAT : PASS
4872 13:56:09.880428 RX DQ/DQS(Engine): PASS
4873 13:56:09.880541 TX OE : NO K
4874 13:56:09.883744 All Pass.
4875 13:56:09.883848
4876 13:56:09.883942 CH 1, Rank 0
4877 13:56:09.886958 SW Impedance : PASS
4878 13:56:09.887071 DUTY Scan : NO K
4879 13:56:09.890401 ZQ Calibration : PASS
4880 13:56:09.893634 Jitter Meter : NO K
4881 13:56:09.893743 CBT Training : PASS
4882 13:56:09.896815 Write leveling : PASS
4883 13:56:09.899956 RX DQS gating : PASS
4884 13:56:09.900060 RX DQ/DQS(RDDQC) : PASS
4885 13:56:09.903243 TX DQ/DQS : PASS
4886 13:56:09.903348 RX DATLAT : PASS
4887 13:56:09.906445 RX DQ/DQS(Engine): PASS
4888 13:56:09.909906 TX OE : NO K
4889 13:56:09.910010 All Pass.
4890 13:56:09.910112
4891 13:56:09.910207 CH 1, Rank 1
4892 13:56:09.913837 SW Impedance : PASS
4893 13:56:09.916586 DUTY Scan : NO K
4894 13:56:09.916667 ZQ Calibration : PASS
4895 13:56:09.920303 Jitter Meter : NO K
4896 13:56:09.923467 CBT Training : PASS
4897 13:56:09.923583 Write leveling : PASS
4898 13:56:09.926460 RX DQS gating : PASS
4899 13:56:09.929909 RX DQ/DQS(RDDQC) : PASS
4900 13:56:09.930021 TX DQ/DQS : PASS
4901 13:56:09.933168 RX DATLAT : PASS
4902 13:56:09.936911 RX DQ/DQS(Engine): PASS
4903 13:56:09.937010 TX OE : NO K
4904 13:56:09.940170 All Pass.
4905 13:56:09.940275
4906 13:56:09.940389 DramC Write-DBI off
4907 13:56:09.943349 PER_BANK_REFRESH: Hybrid Mode
4908 13:56:09.943461 TX_TRACKING: ON
4909 13:56:09.953506 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4910 13:56:09.957107 [FAST_K] Save calibration result to emmc
4911 13:56:09.959827 dramc_set_vcore_voltage set vcore to 662500
4912 13:56:09.963390 Read voltage for 933, 3
4913 13:56:09.963506 Vio18 = 0
4914 13:56:09.967078 Vcore = 662500
4915 13:56:09.967191 Vdram = 0
4916 13:56:09.967284 Vddq = 0
4917 13:56:09.967384 Vmddr = 0
4918 13:56:09.973606 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4919 13:56:09.980055 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4920 13:56:09.980172 MEM_TYPE=3, freq_sel=17
4921 13:56:09.983592 sv_algorithm_assistance_LP4_1600
4922 13:56:09.986719 ============ PULL DRAM RESETB DOWN ============
4923 13:56:09.993308 ========== PULL DRAM RESETB DOWN end =========
4924 13:56:09.996670 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4925 13:56:10.000139 ===================================
4926 13:56:10.003397 LPDDR4 DRAM CONFIGURATION
4927 13:56:10.006596 ===================================
4928 13:56:10.006706 EX_ROW_EN[0] = 0x0
4929 13:56:10.009677 EX_ROW_EN[1] = 0x0
4930 13:56:10.009782 LP4Y_EN = 0x0
4931 13:56:10.012956 WORK_FSP = 0x0
4932 13:56:10.013055 WL = 0x3
4933 13:56:10.016331 RL = 0x3
4934 13:56:10.016440 BL = 0x2
4935 13:56:10.019694 RPST = 0x0
4936 13:56:10.023012 RD_PRE = 0x0
4937 13:56:10.023124 WR_PRE = 0x1
4938 13:56:10.026343 WR_PST = 0x0
4939 13:56:10.026454 DBI_WR = 0x0
4940 13:56:10.029610 DBI_RD = 0x0
4941 13:56:10.029720 OTF = 0x1
4942 13:56:10.032988 ===================================
4943 13:56:10.036258 ===================================
4944 13:56:10.039509 ANA top config
4945 13:56:10.043104 ===================================
4946 13:56:10.043217 DLL_ASYNC_EN = 0
4947 13:56:10.046085 ALL_SLAVE_EN = 1
4948 13:56:10.049458 NEW_RANK_MODE = 1
4949 13:56:10.052728 DLL_IDLE_MODE = 1
4950 13:56:10.052839 LP45_APHY_COMB_EN = 1
4951 13:56:10.056244 TX_ODT_DIS = 1
4952 13:56:10.059455 NEW_8X_MODE = 1
4953 13:56:10.062450 ===================================
4954 13:56:10.066276 ===================================
4955 13:56:10.069777 data_rate = 1866
4956 13:56:10.072696 CKR = 1
4957 13:56:10.076108 DQ_P2S_RATIO = 8
4958 13:56:10.079488 ===================================
4959 13:56:10.079595 CA_P2S_RATIO = 8
4960 13:56:10.082679 DQ_CA_OPEN = 0
4961 13:56:10.085835 DQ_SEMI_OPEN = 0
4962 13:56:10.089612 CA_SEMI_OPEN = 0
4963 13:56:10.092720 CA_FULL_RATE = 0
4964 13:56:10.095930 DQ_CKDIV4_EN = 1
4965 13:56:10.096029 CA_CKDIV4_EN = 1
4966 13:56:10.099154 CA_PREDIV_EN = 0
4967 13:56:10.102631 PH8_DLY = 0
4968 13:56:10.105918 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4969 13:56:10.109222 DQ_AAMCK_DIV = 4
4970 13:56:10.109360 CA_AAMCK_DIV = 4
4971 13:56:10.112472 CA_ADMCK_DIV = 4
4972 13:56:10.116217 DQ_TRACK_CA_EN = 0
4973 13:56:10.119140 CA_PICK = 933
4974 13:56:10.122539 CA_MCKIO = 933
4975 13:56:10.126002 MCKIO_SEMI = 0
4976 13:56:10.129477 PLL_FREQ = 3732
4977 13:56:10.129596 DQ_UI_PI_RATIO = 32
4978 13:56:10.133053 CA_UI_PI_RATIO = 0
4979 13:56:10.135717 ===================================
4980 13:56:10.139181 ===================================
4981 13:56:10.142598 memory_type:LPDDR4
4982 13:56:10.145826 GP_NUM : 10
4983 13:56:10.145932 SRAM_EN : 1
4984 13:56:10.149306 MD32_EN : 0
4985 13:56:10.152543 ===================================
4986 13:56:10.155802 [ANA_INIT] >>>>>>>>>>>>>>
4987 13:56:10.155906 <<<<<< [CONFIGURE PHASE]: ANA_TX
4988 13:56:10.158848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4989 13:56:10.162539 ===================================
4990 13:56:10.165537 data_rate = 1866,PCW = 0X8f00
4991 13:56:10.169310 ===================================
4992 13:56:10.172200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4993 13:56:10.178819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4994 13:56:10.185620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4995 13:56:10.189249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4996 13:56:10.192388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4997 13:56:10.195378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4998 13:56:10.198855 [ANA_INIT] flow start
4999 13:56:10.198971 [ANA_INIT] PLL >>>>>>>>
5000 13:56:10.202597 [ANA_INIT] PLL <<<<<<<<
5001 13:56:10.205615 [ANA_INIT] MIDPI >>>>>>>>
5002 13:56:10.209123 [ANA_INIT] MIDPI <<<<<<<<
5003 13:56:10.209204 [ANA_INIT] DLL >>>>>>>>
5004 13:56:10.212130 [ANA_INIT] flow end
5005 13:56:10.215167 ============ LP4 DIFF to SE enter ============
5006 13:56:10.218567 ============ LP4 DIFF to SE exit ============
5007 13:56:10.222040 [ANA_INIT] <<<<<<<<<<<<<
5008 13:56:10.225158 [Flow] Enable top DCM control >>>>>
5009 13:56:10.229035 [Flow] Enable top DCM control <<<<<
5010 13:56:10.232424 Enable DLL master slave shuffle
5011 13:56:10.235370 ==============================================================
5012 13:56:10.238662 Gating Mode config
5013 13:56:10.245558 ==============================================================
5014 13:56:10.245675 Config description:
5015 13:56:10.255490 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5016 13:56:10.262400 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5017 13:56:10.269025 SELPH_MODE 0: By rank 1: By Phase
5018 13:56:10.272408 ==============================================================
5019 13:56:10.275129 GAT_TRACK_EN = 1
5020 13:56:10.279002 RX_GATING_MODE = 2
5021 13:56:10.282049 RX_GATING_TRACK_MODE = 2
5022 13:56:10.285682 SELPH_MODE = 1
5023 13:56:10.288826 PICG_EARLY_EN = 1
5024 13:56:10.291893 VALID_LAT_VALUE = 1
5025 13:56:10.295179 ==============================================================
5026 13:56:10.298450 Enter into Gating configuration >>>>
5027 13:56:10.301854 Exit from Gating configuration <<<<
5028 13:56:10.305169 Enter into DVFS_PRE_config >>>>>
5029 13:56:10.318421 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5030 13:56:10.322056 Exit from DVFS_PRE_config <<<<<
5031 13:56:10.322165 Enter into PICG configuration >>>>
5032 13:56:10.325396 Exit from PICG configuration <<<<
5033 13:56:10.328476 [RX_INPUT] configuration >>>>>
5034 13:56:10.331729 [RX_INPUT] configuration <<<<<
5035 13:56:10.339146 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5036 13:56:10.341666 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5037 13:56:10.348695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 13:56:10.355450 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 13:56:10.361587 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 13:56:10.368268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 13:56:10.371517 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5042 13:56:10.375236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5043 13:56:10.378471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5044 13:56:10.384952 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5045 13:56:10.388344 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5046 13:56:10.391557 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 13:56:10.395035 ===================================
5048 13:56:10.398247 LPDDR4 DRAM CONFIGURATION
5049 13:56:10.401966 ===================================
5050 13:56:10.405183 EX_ROW_EN[0] = 0x0
5051 13:56:10.405289 EX_ROW_EN[1] = 0x0
5052 13:56:10.408650 LP4Y_EN = 0x0
5053 13:56:10.408758 WORK_FSP = 0x0
5054 13:56:10.411922 WL = 0x3
5055 13:56:10.412024 RL = 0x3
5056 13:56:10.415140 BL = 0x2
5057 13:56:10.415242 RPST = 0x0
5058 13:56:10.418459 RD_PRE = 0x0
5059 13:56:10.418558 WR_PRE = 0x1
5060 13:56:10.421277 WR_PST = 0x0
5061 13:56:10.421383 DBI_WR = 0x0
5062 13:56:10.424669 DBI_RD = 0x0
5063 13:56:10.424769 OTF = 0x1
5064 13:56:10.428021 ===================================
5065 13:56:10.434709 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5066 13:56:10.437962 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5067 13:56:10.441184 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 13:56:10.444998 ===================================
5069 13:56:10.448228 LPDDR4 DRAM CONFIGURATION
5070 13:56:10.451212 ===================================
5071 13:56:10.451321 EX_ROW_EN[0] = 0x10
5072 13:56:10.454837 EX_ROW_EN[1] = 0x0
5073 13:56:10.457948 LP4Y_EN = 0x0
5074 13:56:10.458055 WORK_FSP = 0x0
5075 13:56:10.461611 WL = 0x3
5076 13:56:10.461714 RL = 0x3
5077 13:56:10.464788 BL = 0x2
5078 13:56:10.464906 RPST = 0x0
5079 13:56:10.468320 RD_PRE = 0x0
5080 13:56:10.468396 WR_PRE = 0x1
5081 13:56:10.471085 WR_PST = 0x0
5082 13:56:10.471189 DBI_WR = 0x0
5083 13:56:10.474499 DBI_RD = 0x0
5084 13:56:10.474610 OTF = 0x1
5085 13:56:10.477824 ===================================
5086 13:56:10.484633 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5087 13:56:10.489206 nWR fixed to 30
5088 13:56:10.492612 [ModeRegInit_LP4] CH0 RK0
5089 13:56:10.492724 [ModeRegInit_LP4] CH0 RK1
5090 13:56:10.495911 [ModeRegInit_LP4] CH1 RK0
5091 13:56:10.499206 [ModeRegInit_LP4] CH1 RK1
5092 13:56:10.499309 match AC timing 9
5093 13:56:10.505313 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5094 13:56:10.508570 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5095 13:56:10.512138 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5096 13:56:10.518620 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5097 13:56:10.522009 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5098 13:56:10.522094 ==
5099 13:56:10.525419 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 13:56:10.528723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 13:56:10.528835 ==
5102 13:56:10.535414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5103 13:56:10.541915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5104 13:56:10.545342 [CA 0] Center 37 (6~68) winsize 63
5105 13:56:10.548607 [CA 1] Center 37 (7~68) winsize 62
5106 13:56:10.552577 [CA 2] Center 34 (4~65) winsize 62
5107 13:56:10.555205 [CA 3] Center 33 (3~64) winsize 62
5108 13:56:10.558616 [CA 4] Center 33 (3~64) winsize 62
5109 13:56:10.561925 [CA 5] Center 32 (2~62) winsize 61
5110 13:56:10.562009
5111 13:56:10.565345 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5112 13:56:10.565429
5113 13:56:10.568662 [CATrainingPosCal] consider 1 rank data
5114 13:56:10.571783 u2DelayCellTimex100 = 270/100 ps
5115 13:56:10.575176 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5116 13:56:10.578306 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5117 13:56:10.581978 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5118 13:56:10.585191 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5119 13:56:10.588635 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5120 13:56:10.594849 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5121 13:56:10.594933
5122 13:56:10.598537 CA PerBit enable=1, Macro0, CA PI delay=32
5123 13:56:10.598621
5124 13:56:10.601734 [CBTSetCACLKResult] CA Dly = 32
5125 13:56:10.601817 CS Dly: 5 (0~36)
5126 13:56:10.601884 ==
5127 13:56:10.604556 Dram Type= 6, Freq= 0, CH_0, rank 1
5128 13:56:10.608161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 13:56:10.611217 ==
5130 13:56:10.614910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5131 13:56:10.621257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5132 13:56:10.625058 [CA 0] Center 37 (6~68) winsize 63
5133 13:56:10.628349 [CA 1] Center 37 (7~68) winsize 62
5134 13:56:10.631116 [CA 2] Center 34 (4~65) winsize 62
5135 13:56:10.635165 [CA 3] Center 34 (3~65) winsize 63
5136 13:56:10.638320 [CA 4] Center 32 (2~63) winsize 62
5137 13:56:10.641700 [CA 5] Center 32 (2~62) winsize 61
5138 13:56:10.641774
5139 13:56:10.644305 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5140 13:56:10.644377
5141 13:56:10.647691 [CATrainingPosCal] consider 2 rank data
5142 13:56:10.651019 u2DelayCellTimex100 = 270/100 ps
5143 13:56:10.654399 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5144 13:56:10.658125 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5145 13:56:10.661598 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5146 13:56:10.664277 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5147 13:56:10.671204 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5148 13:56:10.674694 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5149 13:56:10.674796
5150 13:56:10.678203 CA PerBit enable=1, Macro0, CA PI delay=32
5151 13:56:10.678310
5152 13:56:10.680987 [CBTSetCACLKResult] CA Dly = 32
5153 13:56:10.681084 CS Dly: 5 (0~37)
5154 13:56:10.681177
5155 13:56:10.684390 ----->DramcWriteLeveling(PI) begin...
5156 13:56:10.684467 ==
5157 13:56:10.687708 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 13:56:10.694469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 13:56:10.694566 ==
5160 13:56:10.697863 Write leveling (Byte 0): 31 => 31
5161 13:56:10.701222 Write leveling (Byte 1): 28 => 28
5162 13:56:10.701304 DramcWriteLeveling(PI) end<-----
5163 13:56:10.701372
5164 13:56:10.704896 ==
5165 13:56:10.707751 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 13:56:10.710879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 13:56:10.710952 ==
5168 13:56:10.714663 [Gating] SW mode calibration
5169 13:56:10.720825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5170 13:56:10.724252 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5171 13:56:10.730996 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5172 13:56:10.734405 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 13:56:10.737742 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 13:56:10.744041 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 13:56:10.747741 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 13:56:10.750647 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 13:56:10.757854 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5178 13:56:10.761076 0 14 28 | B1->B0 | 3333 2828 | 1 0 | (1 1) (1 0)
5179 13:56:10.764371 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5180 13:56:10.770917 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 13:56:10.774311 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 13:56:10.777340 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 13:56:10.784159 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 13:56:10.787704 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 13:56:10.790400 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5186 13:56:10.797181 0 15 28 | B1->B0 | 2525 3b3b | 0 1 | (0 0) (0 0)
5187 13:56:10.800684 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5188 13:56:10.804110 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 13:56:10.810365 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 13:56:10.813655 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 13:56:10.817651 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 13:56:10.823504 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 13:56:10.826872 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5194 13:56:10.830153 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5195 13:56:10.833702 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5196 13:56:10.840443 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 13:56:10.844087 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 13:56:10.846975 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 13:56:10.853467 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 13:56:10.857015 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 13:56:10.860473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 13:56:10.866770 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:56:10.870207 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 13:56:10.873834 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 13:56:10.880050 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 13:56:10.883525 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 13:56:10.886741 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 13:56:10.893855 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 13:56:10.896663 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5210 13:56:10.900619 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5211 13:56:10.903383 Total UI for P1: 0, mck2ui 16
5212 13:56:10.906723 best dqsien dly found for B0: ( 1, 2, 24)
5213 13:56:10.913376 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5214 13:56:10.916921 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 13:56:10.920277 Total UI for P1: 0, mck2ui 16
5216 13:56:10.923737 best dqsien dly found for B1: ( 1, 3, 0)
5217 13:56:10.926986 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5218 13:56:10.930262 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5219 13:56:10.930337
5220 13:56:10.933557 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5221 13:56:10.936906 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5222 13:56:10.940255 [Gating] SW calibration Done
5223 13:56:10.940363 ==
5224 13:56:10.943068 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 13:56:10.946887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 13:56:10.946961 ==
5227 13:56:10.949794 RX Vref Scan: 0
5228 13:56:10.949865
5229 13:56:10.952982 RX Vref 0 -> 0, step: 1
5230 13:56:10.953057
5231 13:56:10.953122 RX Delay -80 -> 252, step: 8
5232 13:56:10.959966 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5233 13:56:10.963192 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5234 13:56:10.966537 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5235 13:56:10.969807 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5236 13:56:10.973069 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5237 13:56:10.976399 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5238 13:56:10.983312 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5239 13:56:10.986456 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5240 13:56:10.990220 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5241 13:56:10.993272 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5242 13:56:10.996950 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5243 13:56:11.000057 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5244 13:56:11.006526 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5245 13:56:11.010013 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5246 13:56:11.013166 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5247 13:56:11.016802 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5248 13:56:11.016886 ==
5249 13:56:11.020381 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 13:56:11.023343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 13:56:11.026725 ==
5252 13:56:11.026832 DQS Delay:
5253 13:56:11.026939 DQS0 = 0, DQS1 = 0
5254 13:56:11.030543 DQM Delay:
5255 13:56:11.030647 DQM0 = 104, DQM1 = 95
5256 13:56:11.033814 DQ Delay:
5257 13:56:11.036607 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5258 13:56:11.040103 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5259 13:56:11.043581 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5260 13:56:11.046979 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5261 13:56:11.047081
5262 13:56:11.047172
5263 13:56:11.047272 ==
5264 13:56:11.049681 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 13:56:11.053050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 13:56:11.053127 ==
5267 13:56:11.053190
5268 13:56:11.053250
5269 13:56:11.056296 TX Vref Scan disable
5270 13:56:11.059611 == TX Byte 0 ==
5271 13:56:11.063404 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5272 13:56:11.066618 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5273 13:56:11.069836 == TX Byte 1 ==
5274 13:56:11.073175 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5275 13:56:11.076658 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5276 13:56:11.076737 ==
5277 13:56:11.080073 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 13:56:11.083362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 13:56:11.086146 ==
5280 13:56:11.086249
5281 13:56:11.086343
5282 13:56:11.086431 TX Vref Scan disable
5283 13:56:11.090008 == TX Byte 0 ==
5284 13:56:11.093537 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5285 13:56:11.096791 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5286 13:56:11.100031 == TX Byte 1 ==
5287 13:56:11.103057 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5288 13:56:11.106487 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5289 13:56:11.109732
5290 13:56:11.109807 [DATLAT]
5291 13:56:11.109873 Freq=933, CH0 RK0
5292 13:56:11.109934
5293 13:56:11.112969 DATLAT Default: 0xd
5294 13:56:11.113068 0, 0xFFFF, sum = 0
5295 13:56:11.116932 1, 0xFFFF, sum = 0
5296 13:56:11.117005 2, 0xFFFF, sum = 0
5297 13:56:11.119619 3, 0xFFFF, sum = 0
5298 13:56:11.122936 4, 0xFFFF, sum = 0
5299 13:56:11.123008 5, 0xFFFF, sum = 0
5300 13:56:11.126295 6, 0xFFFF, sum = 0
5301 13:56:11.126366 7, 0xFFFF, sum = 0
5302 13:56:11.129588 8, 0xFFFF, sum = 0
5303 13:56:11.129674 9, 0xFFFF, sum = 0
5304 13:56:11.133263 10, 0x0, sum = 1
5305 13:56:11.133346 11, 0x0, sum = 2
5306 13:56:11.136245 12, 0x0, sum = 3
5307 13:56:11.136356 13, 0x0, sum = 4
5308 13:56:11.136441 best_step = 11
5309 13:56:11.136526
5310 13:56:11.139569 ==
5311 13:56:11.142925 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 13:56:11.146037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 13:56:11.146120 ==
5314 13:56:11.146204 RX Vref Scan: 1
5315 13:56:11.146288
5316 13:56:11.149847 RX Vref 0 -> 0, step: 1
5317 13:56:11.149930
5318 13:56:11.152731 RX Delay -53 -> 252, step: 4
5319 13:56:11.152817
5320 13:56:11.156280 Set Vref, RX VrefLevel [Byte0]: 58
5321 13:56:11.159933 [Byte1]: 47
5322 13:56:11.160045
5323 13:56:11.163200 Final RX Vref Byte 0 = 58 to rank0
5324 13:56:11.166476 Final RX Vref Byte 1 = 47 to rank0
5325 13:56:11.169784 Final RX Vref Byte 0 = 58 to rank1
5326 13:56:11.172824 Final RX Vref Byte 1 = 47 to rank1==
5327 13:56:11.176604 Dram Type= 6, Freq= 0, CH_0, rank 0
5328 13:56:11.179744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 13:56:11.179831 ==
5330 13:56:11.182998 DQS Delay:
5331 13:56:11.183074 DQS0 = 0, DQS1 = 0
5332 13:56:11.186354 DQM Delay:
5333 13:56:11.186431 DQM0 = 104, DQM1 = 94
5334 13:56:11.189610 DQ Delay:
5335 13:56:11.192871 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5336 13:56:11.196168 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5337 13:56:11.199394 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5338 13:56:11.202677 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =102
5339 13:56:11.202748
5340 13:56:11.202810
5341 13:56:11.209736 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5342 13:56:11.212730 CH0 RK0: MR19=505, MR18=3028
5343 13:56:11.219848 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5344 13:56:11.219930
5345 13:56:11.222621 ----->DramcWriteLeveling(PI) begin...
5346 13:56:11.222719 ==
5347 13:56:11.225909 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 13:56:11.229273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 13:56:11.229360 ==
5350 13:56:11.232738 Write leveling (Byte 0): 31 => 31
5351 13:56:11.236203 Write leveling (Byte 1): 29 => 29
5352 13:56:11.239574 DramcWriteLeveling(PI) end<-----
5353 13:56:11.239648
5354 13:56:11.239711 ==
5355 13:56:11.242931 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 13:56:11.245912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 13:56:11.246019 ==
5358 13:56:11.249411 [Gating] SW mode calibration
5359 13:56:11.255865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5360 13:56:11.263169 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5361 13:56:11.266046 0 14 0 | B1->B0 | 2e2e 2f2e | 1 1 | (0 0) (0 0)
5362 13:56:11.272440 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 13:56:11.275884 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 13:56:11.279253 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 13:56:11.285708 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 13:56:11.289222 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 13:56:11.292549 0 14 24 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
5368 13:56:11.298993 0 14 28 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (1 0)
5369 13:56:11.302481 0 15 0 | B1->B0 | 2424 2626 | 0 0 | (0 0) (1 0)
5370 13:56:11.306054 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 13:56:11.309090 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 13:56:11.315822 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 13:56:11.319142 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 13:56:11.322302 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 13:56:11.328938 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5376 13:56:11.332331 0 15 28 | B1->B0 | 3c3c 3737 | 0 0 | (0 0) (0 0)
5377 13:56:11.335608 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5378 13:56:11.342304 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 13:56:11.345818 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 13:56:11.349121 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 13:56:11.355652 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 13:56:11.358904 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 13:56:11.362293 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 13:56:11.369111 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5385 13:56:11.372630 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5386 13:56:11.375220 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 13:56:11.382301 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 13:56:11.385604 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 13:56:11.389008 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 13:56:11.395519 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 13:56:11.398605 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 13:56:11.402459 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 13:56:11.409040 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 13:56:11.412295 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 13:56:11.415482 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 13:56:11.421985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 13:56:11.425521 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 13:56:11.429012 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 13:56:11.435261 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 13:56:11.438688 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5401 13:56:11.442098 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 13:56:11.445686 Total UI for P1: 0, mck2ui 16
5403 13:56:11.448670 best dqsien dly found for B0: ( 1, 2, 28)
5404 13:56:11.452150 Total UI for P1: 0, mck2ui 16
5405 13:56:11.455374 best dqsien dly found for B1: ( 1, 2, 28)
5406 13:56:11.458612 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5407 13:56:11.462056 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5408 13:56:11.462144
5409 13:56:11.465362 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5410 13:56:11.472170 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5411 13:56:11.472283 [Gating] SW calibration Done
5412 13:56:11.472362 ==
5413 13:56:11.475616 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 13:56:11.482342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 13:56:11.482453 ==
5416 13:56:11.482548 RX Vref Scan: 0
5417 13:56:11.482652
5418 13:56:11.485084 RX Vref 0 -> 0, step: 1
5419 13:56:11.485168
5420 13:56:11.488466 RX Delay -80 -> 252, step: 8
5421 13:56:11.491832 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5422 13:56:11.495334 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5423 13:56:11.498664 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5424 13:56:11.505218 iDelay=208, Bit 3, Center 107 (16 ~ 199) 184
5425 13:56:11.508585 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5426 13:56:11.511965 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5427 13:56:11.515389 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5428 13:56:11.518781 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5429 13:56:11.521597 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5430 13:56:11.528296 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5431 13:56:11.532524 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5432 13:56:11.534884 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5433 13:56:11.538792 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5434 13:56:11.541924 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5435 13:56:11.545476 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5436 13:56:11.551579 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5437 13:56:11.551661 ==
5438 13:56:11.555089 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 13:56:11.558440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 13:56:11.558553 ==
5441 13:56:11.558651 DQS Delay:
5442 13:56:11.561666 DQS0 = 0, DQS1 = 0
5443 13:56:11.561749 DQM Delay:
5444 13:56:11.565216 DQM0 = 107, DQM1 = 95
5445 13:56:11.565317 DQ Delay:
5446 13:56:11.568572 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =107
5447 13:56:11.571842 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5448 13:56:11.575065 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5449 13:56:11.578405 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5450 13:56:11.578493
5451 13:56:11.578596
5452 13:56:11.578702 ==
5453 13:56:11.581999 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 13:56:11.588547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 13:56:11.588655 ==
5456 13:56:11.588763
5457 13:56:11.588864
5458 13:56:11.588961 TX Vref Scan disable
5459 13:56:11.591853 == TX Byte 0 ==
5460 13:56:11.595376 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5461 13:56:11.601877 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5462 13:56:11.601990 == TX Byte 1 ==
5463 13:56:11.605293 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5464 13:56:11.612075 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5465 13:56:11.612180 ==
5466 13:56:11.615550 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 13:56:11.618844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 13:56:11.618947 ==
5469 13:56:11.619039
5470 13:56:11.619139
5471 13:56:11.621684 TX Vref Scan disable
5472 13:56:11.621763 == TX Byte 0 ==
5473 13:56:11.628603 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5474 13:56:11.631898 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5475 13:56:11.632002 == TX Byte 1 ==
5476 13:56:11.638494 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5477 13:56:11.641904 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5478 13:56:11.641979
5479 13:56:11.642042 [DATLAT]
5480 13:56:11.645299 Freq=933, CH0 RK1
5481 13:56:11.645404
5482 13:56:11.645494 DATLAT Default: 0xb
5483 13:56:11.648605 0, 0xFFFF, sum = 0
5484 13:56:11.648679 1, 0xFFFF, sum = 0
5485 13:56:11.651661 2, 0xFFFF, sum = 0
5486 13:56:11.651746 3, 0xFFFF, sum = 0
5487 13:56:11.654895 4, 0xFFFF, sum = 0
5488 13:56:11.658116 5, 0xFFFF, sum = 0
5489 13:56:11.658201 6, 0xFFFF, sum = 0
5490 13:56:11.661589 7, 0xFFFF, sum = 0
5491 13:56:11.661693 8, 0xFFFF, sum = 0
5492 13:56:11.664892 9, 0xFFFF, sum = 0
5493 13:56:11.664977 10, 0x0, sum = 1
5494 13:56:11.668240 11, 0x0, sum = 2
5495 13:56:11.668336 12, 0x0, sum = 3
5496 13:56:11.668404 13, 0x0, sum = 4
5497 13:56:11.671642 best_step = 11
5498 13:56:11.671725
5499 13:56:11.671791 ==
5500 13:56:11.674995 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 13:56:11.678244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 13:56:11.678354 ==
5503 13:56:11.681279 RX Vref Scan: 0
5504 13:56:11.681355
5505 13:56:11.681418 RX Vref 0 -> 0, step: 1
5506 13:56:11.684954
5507 13:56:11.685028 RX Delay -45 -> 252, step: 4
5508 13:56:11.692308 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5509 13:56:11.695463 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5510 13:56:11.699068 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5511 13:56:11.702240 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5512 13:56:11.705846 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5513 13:56:11.712521 iDelay=199, Bit 5, Center 100 (11 ~ 190) 180
5514 13:56:11.715629 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5515 13:56:11.718941 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5516 13:56:11.722317 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5517 13:56:11.725647 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5518 13:56:11.732077 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5519 13:56:11.735289 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5520 13:56:11.738578 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5521 13:56:11.741982 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5522 13:56:11.745332 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5523 13:56:11.751960 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5524 13:56:11.752067 ==
5525 13:56:11.755380 Dram Type= 6, Freq= 0, CH_0, rank 1
5526 13:56:11.758551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 13:56:11.758656 ==
5528 13:56:11.758750 DQS Delay:
5529 13:56:11.762537 DQS0 = 0, DQS1 = 0
5530 13:56:11.762638 DQM Delay:
5531 13:56:11.765540 DQM0 = 105, DQM1 = 93
5532 13:56:11.765643 DQ Delay:
5533 13:56:11.768305 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5534 13:56:11.771662 DQ4 =106, DQ5 =100, DQ6 =110, DQ7 =112
5535 13:56:11.775070 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5536 13:56:11.778252 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5537 13:56:11.778358
5538 13:56:11.778454
5539 13:56:11.788542 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5540 13:56:11.791563 CH0 RK1: MR19=505, MR18=2A03
5541 13:56:11.794681 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5542 13:56:11.798439 [RxdqsGatingPostProcess] freq 933
5543 13:56:11.804957 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5544 13:56:11.808205 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 13:56:11.811431 best DQS1 dly(2T, 0.5T) = (0, 11)
5546 13:56:11.814741 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 13:56:11.818182 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5548 13:56:11.821422 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 13:56:11.824693 best DQS1 dly(2T, 0.5T) = (0, 10)
5550 13:56:11.827931 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 13:56:11.831490 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5552 13:56:11.831595 Pre-setting of DQS Precalculation
5553 13:56:11.837715 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5554 13:56:11.837822 ==
5555 13:56:11.841290 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 13:56:11.844611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 13:56:11.844713 ==
5558 13:56:11.851056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 13:56:11.857824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5560 13:56:11.861323 [CA 0] Center 36 (6~67) winsize 62
5561 13:56:11.864472 [CA 1] Center 36 (6~67) winsize 62
5562 13:56:11.868042 [CA 2] Center 34 (4~65) winsize 62
5563 13:56:11.871257 [CA 3] Center 34 (4~65) winsize 62
5564 13:56:11.874490 [CA 4] Center 34 (4~64) winsize 61
5565 13:56:11.877639 [CA 5] Center 33 (3~63) winsize 61
5566 13:56:11.877743
5567 13:56:11.881643 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5568 13:56:11.881747
5569 13:56:11.884953 [CATrainingPosCal] consider 1 rank data
5570 13:56:11.888321 u2DelayCellTimex100 = 270/100 ps
5571 13:56:11.891552 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5572 13:56:11.894785 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5573 13:56:11.897875 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5574 13:56:11.900993 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5575 13:56:11.904692 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5576 13:56:11.907795 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5577 13:56:11.907903
5578 13:56:11.914340 CA PerBit enable=1, Macro0, CA PI delay=33
5579 13:56:11.914446
5580 13:56:11.917880 [CBTSetCACLKResult] CA Dly = 33
5581 13:56:11.917982 CS Dly: 7 (0~38)
5582 13:56:11.918077 ==
5583 13:56:11.921182 Dram Type= 6, Freq= 0, CH_1, rank 1
5584 13:56:11.924612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 13:56:11.924716 ==
5586 13:56:11.931323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5587 13:56:11.937874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5588 13:56:11.941646 [CA 0] Center 36 (6~67) winsize 62
5589 13:56:11.944940 [CA 1] Center 37 (7~68) winsize 62
5590 13:56:11.948315 [CA 2] Center 35 (4~66) winsize 63
5591 13:56:11.951747 [CA 3] Center 34 (4~65) winsize 62
5592 13:56:11.954982 [CA 4] Center 34 (4~65) winsize 62
5593 13:56:11.958318 [CA 5] Center 34 (4~64) winsize 61
5594 13:56:11.958426
5595 13:56:11.961578 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5596 13:56:11.961683
5597 13:56:11.964800 [CATrainingPosCal] consider 2 rank data
5598 13:56:11.968352 u2DelayCellTimex100 = 270/100 ps
5599 13:56:11.971590 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5600 13:56:11.974910 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5601 13:56:11.978283 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5602 13:56:11.981670 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5603 13:56:11.984693 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5604 13:56:11.988458 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5605 13:56:11.988540
5606 13:56:11.991703 CA PerBit enable=1, Macro0, CA PI delay=33
5607 13:56:11.994861
5608 13:56:11.994969 [CBTSetCACLKResult] CA Dly = 33
5609 13:56:11.998085 CS Dly: 8 (0~40)
5610 13:56:11.998168
5611 13:56:12.001404 ----->DramcWriteLeveling(PI) begin...
5612 13:56:12.001481 ==
5613 13:56:12.004740 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 13:56:12.008554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 13:56:12.008654 ==
5616 13:56:12.011786 Write leveling (Byte 0): 24 => 24
5617 13:56:12.014771 Write leveling (Byte 1): 28 => 28
5618 13:56:12.018416 DramcWriteLeveling(PI) end<-----
5619 13:56:12.018535
5620 13:56:12.018643 ==
5621 13:56:12.021806 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 13:56:12.025152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 13:56:12.025269 ==
5624 13:56:12.028635 [Gating] SW mode calibration
5625 13:56:12.034767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5626 13:56:12.041584 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5627 13:56:12.044920 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 13:56:12.051439 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 13:56:12.054777 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 13:56:12.058311 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 13:56:12.065101 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 13:56:12.067876 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5633 13:56:12.071297 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5634 13:56:12.078249 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5635 13:56:12.081535 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 13:56:12.084813 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 13:56:12.088118 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 13:56:12.094560 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 13:56:12.098356 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 13:56:12.101577 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 13:56:12.108201 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5642 13:56:12.111333 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
5643 13:56:12.114807 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 13:56:12.121650 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 13:56:12.124616 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 13:56:12.127931 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 13:56:12.134597 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 13:56:12.138087 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5649 13:56:12.141785 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5650 13:56:12.147978 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5651 13:56:12.151324 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 13:56:12.154687 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 13:56:12.161388 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 13:56:12.164762 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 13:56:12.168123 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 13:56:12.174270 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 13:56:12.178122 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 13:56:12.181587 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 13:56:12.187717 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 13:56:12.190912 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 13:56:12.194733 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 13:56:12.201120 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 13:56:12.204642 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 13:56:12.207954 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 13:56:12.211416 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5666 13:56:12.214739 Total UI for P1: 0, mck2ui 16
5667 13:56:12.218025 best dqsien dly found for B1: ( 1, 2, 22)
5668 13:56:12.224746 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5669 13:56:12.227843 Total UI for P1: 0, mck2ui 16
5670 13:56:12.230988 best dqsien dly found for B0: ( 1, 2, 24)
5671 13:56:12.234485 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5672 13:56:12.238081 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5673 13:56:12.238185
5674 13:56:12.241190 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5675 13:56:12.244797 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5676 13:56:12.247752 [Gating] SW calibration Done
5677 13:56:12.247858 ==
5678 13:56:12.251577 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 13:56:12.254693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 13:56:12.254806 ==
5681 13:56:12.257672 RX Vref Scan: 0
5682 13:56:12.257776
5683 13:56:12.257873 RX Vref 0 -> 0, step: 1
5684 13:56:12.257968
5685 13:56:12.261035 RX Delay -80 -> 252, step: 8
5686 13:56:12.267744 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5687 13:56:12.271311 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5688 13:56:12.274393 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5689 13:56:12.277902 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5690 13:56:12.281332 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5691 13:56:12.284786 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5692 13:56:12.288165 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5693 13:56:12.294235 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5694 13:56:12.297658 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5695 13:56:12.301124 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5696 13:56:12.304364 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5697 13:56:12.307378 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5698 13:56:12.314082 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5699 13:56:12.317543 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5700 13:56:12.320971 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5701 13:56:12.324462 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5702 13:56:12.324566 ==
5703 13:56:12.327828 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 13:56:12.331237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 13:56:12.334461 ==
5706 13:56:12.334571 DQS Delay:
5707 13:56:12.334668 DQS0 = 0, DQS1 = 0
5708 13:56:12.337469 DQM Delay:
5709 13:56:12.337578 DQM0 = 102, DQM1 = 99
5710 13:56:12.340808 DQ Delay:
5711 13:56:12.344130 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5712 13:56:12.347742 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5713 13:56:12.350827 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5714 13:56:12.354122 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5715 13:56:12.354236
5716 13:56:12.354358
5717 13:56:12.354476 ==
5718 13:56:12.357451 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 13:56:12.360777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 13:56:12.360891 ==
5721 13:56:12.361011
5722 13:56:12.361107
5723 13:56:12.363908 TX Vref Scan disable
5724 13:56:12.367577 == TX Byte 0 ==
5725 13:56:12.370474 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5726 13:56:12.373881 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5727 13:56:12.377604 == TX Byte 1 ==
5728 13:56:12.380718 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5729 13:56:12.384267 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5730 13:56:12.384395 ==
5731 13:56:12.387110 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 13:56:12.390705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 13:56:12.390816 ==
5734 13:56:12.393793
5735 13:56:12.393895
5736 13:56:12.393991 TX Vref Scan disable
5737 13:56:12.397208 == TX Byte 0 ==
5738 13:56:12.401126 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5739 13:56:12.407499 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5740 13:56:12.407630 == TX Byte 1 ==
5741 13:56:12.410836 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5742 13:56:12.417371 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5743 13:56:12.417457
5744 13:56:12.417530 [DATLAT]
5745 13:56:12.417593 Freq=933, CH1 RK0
5746 13:56:12.417653
5747 13:56:12.420798 DATLAT Default: 0xd
5748 13:56:12.420871 0, 0xFFFF, sum = 0
5749 13:56:12.424120 1, 0xFFFF, sum = 0
5750 13:56:12.424218 2, 0xFFFF, sum = 0
5751 13:56:12.427473 3, 0xFFFF, sum = 0
5752 13:56:12.430779 4, 0xFFFF, sum = 0
5753 13:56:12.430878 5, 0xFFFF, sum = 0
5754 13:56:12.433569 6, 0xFFFF, sum = 0
5755 13:56:12.433659 7, 0xFFFF, sum = 0
5756 13:56:12.436892 8, 0xFFFF, sum = 0
5757 13:56:12.436970 9, 0xFFFF, sum = 0
5758 13:56:12.440275 10, 0x0, sum = 1
5759 13:56:12.440369 11, 0x0, sum = 2
5760 13:56:12.443685 12, 0x0, sum = 3
5761 13:56:12.443787 13, 0x0, sum = 4
5762 13:56:12.443878 best_step = 11
5763 13:56:12.443966
5764 13:56:12.447033 ==
5765 13:56:12.451007 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 13:56:12.453848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 13:56:12.453931 ==
5768 13:56:12.453995 RX Vref Scan: 1
5769 13:56:12.454055
5770 13:56:12.457239 RX Vref 0 -> 0, step: 1
5771 13:56:12.457348
5772 13:56:12.460391 RX Delay -45 -> 252, step: 4
5773 13:56:12.460505
5774 13:56:12.463591 Set Vref, RX VrefLevel [Byte0]: 53
5775 13:56:12.467004 [Byte1]: 47
5776 13:56:12.467110
5777 13:56:12.470215 Final RX Vref Byte 0 = 53 to rank0
5778 13:56:12.473683 Final RX Vref Byte 1 = 47 to rank0
5779 13:56:12.477154 Final RX Vref Byte 0 = 53 to rank1
5780 13:56:12.480355 Final RX Vref Byte 1 = 47 to rank1==
5781 13:56:12.483675 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 13:56:12.486539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 13:56:12.490292 ==
5784 13:56:12.490405 DQS Delay:
5785 13:56:12.490500 DQS0 = 0, DQS1 = 0
5786 13:56:12.493585 DQM Delay:
5787 13:56:12.493695 DQM0 = 103, DQM1 = 99
5788 13:56:12.496978 DQ Delay:
5789 13:56:12.499915 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5790 13:56:12.503424 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5791 13:56:12.506968 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =90
5792 13:56:12.509961 DQ12 =106, DQ13 =106, DQ14 =108, DQ15 =108
5793 13:56:12.510068
5794 13:56:12.510161
5795 13:56:12.516739 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5796 13:56:12.520045 CH1 RK0: MR19=505, MR18=1A32
5797 13:56:12.526391 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5798 13:56:12.526507
5799 13:56:12.529908 ----->DramcWriteLeveling(PI) begin...
5800 13:56:12.530021 ==
5801 13:56:12.533338 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 13:56:12.536727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 13:56:12.536842 ==
5804 13:56:12.540269 Write leveling (Byte 0): 28 => 28
5805 13:56:12.542933 Write leveling (Byte 1): 30 => 30
5806 13:56:12.546298 DramcWriteLeveling(PI) end<-----
5807 13:56:12.546400
5808 13:56:12.546503 ==
5809 13:56:12.549725 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 13:56:12.553043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 13:56:12.556204 ==
5812 13:56:12.556318 [Gating] SW mode calibration
5813 13:56:12.566467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5814 13:56:12.569652 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5815 13:56:12.573206 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 13:56:12.579736 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 13:56:12.583068 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 13:56:12.586375 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 13:56:12.592410 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 13:56:12.595687 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5821 13:56:12.599286 0 14 24 | B1->B0 | 2e2e 3030 | 1 0 | (1 1) (0 1)
5822 13:56:12.605892 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5823 13:56:12.609248 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 13:56:12.612574 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 13:56:12.619094 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 13:56:12.622396 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 13:56:12.625446 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 13:56:12.632101 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 13:56:12.635439 0 15 24 | B1->B0 | 3939 2828 | 0 0 | (0 0) (0 0)
5830 13:56:12.638759 0 15 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5831 13:56:12.645534 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 13:56:12.649095 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 13:56:12.652607 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 13:56:12.659182 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 13:56:12.662485 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 13:56:12.665716 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 13:56:12.672110 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5838 13:56:12.675389 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5839 13:56:12.679195 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 13:56:12.685423 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 13:56:12.688815 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 13:56:12.692029 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 13:56:12.698579 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 13:56:12.702550 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 13:56:12.705441 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 13:56:12.708940 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 13:56:12.715586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 13:56:12.718875 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 13:56:12.722301 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 13:56:12.728401 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 13:56:12.732397 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 13:56:12.735103 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5853 13:56:12.742104 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5854 13:56:12.745561 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 13:56:12.748672 Total UI for P1: 0, mck2ui 16
5856 13:56:12.751737 best dqsien dly found for B0: ( 1, 2, 26)
5857 13:56:12.755373 Total UI for P1: 0, mck2ui 16
5858 13:56:12.758357 best dqsien dly found for B1: ( 1, 2, 22)
5859 13:56:12.761756 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5860 13:56:12.765472 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5861 13:56:12.765575
5862 13:56:12.768265 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5863 13:56:12.771848 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5864 13:56:12.774852 [Gating] SW calibration Done
5865 13:56:12.774956 ==
5866 13:56:12.778641 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 13:56:12.785185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 13:56:12.785288 ==
5869 13:56:12.785356 RX Vref Scan: 0
5870 13:56:12.785418
5871 13:56:12.788589 RX Vref 0 -> 0, step: 1
5872 13:56:12.788672
5873 13:56:12.791641 RX Delay -80 -> 252, step: 8
5874 13:56:12.795442 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5875 13:56:12.797970 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5876 13:56:12.801877 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5877 13:56:12.805354 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5878 13:56:12.808028 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5879 13:56:12.814768 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5880 13:56:12.818406 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5881 13:56:12.821945 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5882 13:56:12.825079 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5883 13:56:12.828355 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5884 13:56:12.831802 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5885 13:56:12.838341 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5886 13:56:12.841614 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5887 13:56:12.844901 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5888 13:56:12.847908 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5889 13:56:12.851207 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5890 13:56:12.854609 ==
5891 13:56:12.858027 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 13:56:12.861305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 13:56:12.861391 ==
5894 13:56:12.861468 DQS Delay:
5895 13:56:12.864607 DQS0 = 0, DQS1 = 0
5896 13:56:12.864689 DQM Delay:
5897 13:56:12.867924 DQM0 = 102, DQM1 = 97
5898 13:56:12.868031 DQ Delay:
5899 13:56:12.871600 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5900 13:56:12.874752 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5901 13:56:12.878286 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5902 13:56:12.881164 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5903 13:56:12.881252
5904 13:56:12.881334
5905 13:56:12.881396 ==
5906 13:56:12.884982 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 13:56:12.887810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 13:56:12.887885 ==
5909 13:56:12.891225
5910 13:56:12.891322
5911 13:56:12.891387 TX Vref Scan disable
5912 13:56:12.894960 == TX Byte 0 ==
5913 13:56:12.898700 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5914 13:56:12.901394 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5915 13:56:12.904525 == TX Byte 1 ==
5916 13:56:12.907947 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5917 13:56:12.911414 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5918 13:56:12.911523 ==
5919 13:56:12.914637 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 13:56:12.921379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 13:56:12.921497 ==
5922 13:56:12.921591
5923 13:56:12.921695
5924 13:56:12.921785 TX Vref Scan disable
5925 13:56:12.925953 == TX Byte 0 ==
5926 13:56:12.929020 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5927 13:56:12.935561 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5928 13:56:12.935641 == TX Byte 1 ==
5929 13:56:12.938719 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5930 13:56:12.945348 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5931 13:56:12.945426
5932 13:56:12.945490 [DATLAT]
5933 13:56:12.945557 Freq=933, CH1 RK1
5934 13:56:12.945617
5935 13:56:12.948721 DATLAT Default: 0xb
5936 13:56:12.948795 0, 0xFFFF, sum = 0
5937 13:56:12.951838 1, 0xFFFF, sum = 0
5938 13:56:12.955525 2, 0xFFFF, sum = 0
5939 13:56:12.955610 3, 0xFFFF, sum = 0
5940 13:56:12.958692 4, 0xFFFF, sum = 0
5941 13:56:12.958770 5, 0xFFFF, sum = 0
5942 13:56:12.961965 6, 0xFFFF, sum = 0
5943 13:56:12.962042 7, 0xFFFF, sum = 0
5944 13:56:12.965406 8, 0xFFFF, sum = 0
5945 13:56:12.965481 9, 0xFFFF, sum = 0
5946 13:56:12.968833 10, 0x0, sum = 1
5947 13:56:12.968911 11, 0x0, sum = 2
5948 13:56:12.972142 12, 0x0, sum = 3
5949 13:56:12.972217 13, 0x0, sum = 4
5950 13:56:12.972308 best_step = 11
5951 13:56:12.972390
5952 13:56:12.975388 ==
5953 13:56:12.978628 Dram Type= 6, Freq= 0, CH_1, rank 1
5954 13:56:12.982141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5955 13:56:12.982215 ==
5956 13:56:12.982277 RX Vref Scan: 0
5957 13:56:12.982345
5958 13:56:12.985283 RX Vref 0 -> 0, step: 1
5959 13:56:12.985358
5960 13:56:12.988427 RX Delay -45 -> 252, step: 4
5961 13:56:12.991643 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5962 13:56:12.998834 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5963 13:56:13.001900 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5964 13:56:13.005344 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5965 13:56:13.008769 iDelay=203, Bit 4, Center 98 (19 ~ 178) 160
5966 13:56:13.012045 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5967 13:56:13.018458 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5968 13:56:13.021704 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5969 13:56:13.025133 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5970 13:56:13.028528 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5971 13:56:13.031809 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5972 13:56:13.035197 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5973 13:56:13.041794 iDelay=203, Bit 12, Center 110 (27 ~ 194) 168
5974 13:56:13.044907 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5975 13:56:13.048403 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5976 13:56:13.051822 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5977 13:56:13.051938 ==
5978 13:56:13.055210 Dram Type= 6, Freq= 0, CH_1, rank 1
5979 13:56:13.061687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5980 13:56:13.061781 ==
5981 13:56:13.061893 DQS Delay:
5982 13:56:13.064797 DQS0 = 0, DQS1 = 0
5983 13:56:13.064900 DQM Delay:
5984 13:56:13.068249 DQM0 = 104, DQM1 = 100
5985 13:56:13.068374 DQ Delay:
5986 13:56:13.071459 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5987 13:56:13.074852 DQ4 =98, DQ5 =118, DQ6 =114, DQ7 =102
5988 13:56:13.078049 DQ8 =90, DQ9 =90, DQ10 =102, DQ11 =94
5989 13:56:13.081402 DQ12 =110, DQ13 =104, DQ14 =106, DQ15 =110
5990 13:56:13.081479
5991 13:56:13.081542
5992 13:56:13.088163 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5993 13:56:13.091516 CH1 RK1: MR19=505, MR18=2F03
5994 13:56:13.097963 CH1_RK1: MR19=0x505, MR18=0x2F03, DQSOSC=407, MR23=63, INC=65, DEC=43
5995 13:56:13.101950 [RxdqsGatingPostProcess] freq 933
5996 13:56:13.108087 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5997 13:56:13.111428 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 13:56:13.111529 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 13:56:13.115203 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 13:56:13.118260 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 13:56:13.121798 best DQS0 dly(2T, 0.5T) = (0, 10)
6002 13:56:13.124896 best DQS1 dly(2T, 0.5T) = (0, 10)
6003 13:56:13.127911 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6004 13:56:13.131410 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6005 13:56:13.134889 Pre-setting of DQS Precalculation
6006 13:56:13.141351 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6007 13:56:13.148405 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6008 13:56:13.154891 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6009 13:56:13.155001
6010 13:56:13.155093
6011 13:56:13.158004 [Calibration Summary] 1866 Mbps
6012 13:56:13.158079 CH 0, Rank 0
6013 13:56:13.161422 SW Impedance : PASS
6014 13:56:13.164882 DUTY Scan : NO K
6015 13:56:13.164959 ZQ Calibration : PASS
6016 13:56:13.168006 Jitter Meter : NO K
6017 13:56:13.171027 CBT Training : PASS
6018 13:56:13.171135 Write leveling : PASS
6019 13:56:13.174557 RX DQS gating : PASS
6020 13:56:13.177762 RX DQ/DQS(RDDQC) : PASS
6021 13:56:13.177866 TX DQ/DQS : PASS
6022 13:56:13.180981 RX DATLAT : PASS
6023 13:56:13.181056 RX DQ/DQS(Engine): PASS
6024 13:56:13.184848 TX OE : NO K
6025 13:56:13.184949 All Pass.
6026 13:56:13.185045
6027 13:56:13.187648 CH 0, Rank 1
6028 13:56:13.187759 SW Impedance : PASS
6029 13:56:13.190864 DUTY Scan : NO K
6030 13:56:13.194777 ZQ Calibration : PASS
6031 13:56:13.194861 Jitter Meter : NO K
6032 13:56:13.197939 CBT Training : PASS
6033 13:56:13.201258 Write leveling : PASS
6034 13:56:13.201336 RX DQS gating : PASS
6035 13:56:13.204587 RX DQ/DQS(RDDQC) : PASS
6036 13:56:13.207892 TX DQ/DQS : PASS
6037 13:56:13.207978 RX DATLAT : PASS
6038 13:56:13.211145 RX DQ/DQS(Engine): PASS
6039 13:56:13.214488 TX OE : NO K
6040 13:56:13.214574 All Pass.
6041 13:56:13.214634
6042 13:56:13.214699 CH 1, Rank 0
6043 13:56:13.217860 SW Impedance : PASS
6044 13:56:13.221124 DUTY Scan : NO K
6045 13:56:13.221203 ZQ Calibration : PASS
6046 13:56:13.224445 Jitter Meter : NO K
6047 13:56:13.227765 CBT Training : PASS
6048 13:56:13.227833 Write leveling : PASS
6049 13:56:13.231076 RX DQS gating : PASS
6050 13:56:13.234202 RX DQ/DQS(RDDQC) : PASS
6051 13:56:13.234271 TX DQ/DQS : PASS
6052 13:56:13.237776 RX DATLAT : PASS
6053 13:56:13.237847 RX DQ/DQS(Engine): PASS
6054 13:56:13.241170 TX OE : NO K
6055 13:56:13.241240 All Pass.
6056 13:56:13.241337
6057 13:56:13.244255 CH 1, Rank 1
6058 13:56:13.244362 SW Impedance : PASS
6059 13:56:13.247731 DUTY Scan : NO K
6060 13:56:13.250907 ZQ Calibration : PASS
6061 13:56:13.250981 Jitter Meter : NO K
6062 13:56:13.254134 CBT Training : PASS
6063 13:56:13.257546 Write leveling : PASS
6064 13:56:13.257615 RX DQS gating : PASS
6065 13:56:13.261051 RX DQ/DQS(RDDQC) : PASS
6066 13:56:13.264162 TX DQ/DQS : PASS
6067 13:56:13.264266 RX DATLAT : PASS
6068 13:56:13.267939 RX DQ/DQS(Engine): PASS
6069 13:56:13.271032 TX OE : NO K
6070 13:56:13.271135 All Pass.
6071 13:56:13.271227
6072 13:56:13.271318 DramC Write-DBI off
6073 13:56:13.274113 PER_BANK_REFRESH: Hybrid Mode
6074 13:56:13.277699 TX_TRACKING: ON
6075 13:56:13.283998 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6076 13:56:13.287754 [FAST_K] Save calibration result to emmc
6077 13:56:13.294443 dramc_set_vcore_voltage set vcore to 650000
6078 13:56:13.294528 Read voltage for 400, 6
6079 13:56:13.297775 Vio18 = 0
6080 13:56:13.297851 Vcore = 650000
6081 13:56:13.297916 Vdram = 0
6082 13:56:13.301077 Vddq = 0
6083 13:56:13.301148 Vmddr = 0
6084 13:56:13.304424 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6085 13:56:13.310984 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6086 13:56:13.314322 MEM_TYPE=3, freq_sel=20
6087 13:56:13.314396 sv_algorithm_assistance_LP4_800
6088 13:56:13.320424 ============ PULL DRAM RESETB DOWN ============
6089 13:56:13.323751 ========== PULL DRAM RESETB DOWN end =========
6090 13:56:13.327072 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6091 13:56:13.330457 ===================================
6092 13:56:13.333737 LPDDR4 DRAM CONFIGURATION
6093 13:56:13.337150 ===================================
6094 13:56:13.340535 EX_ROW_EN[0] = 0x0
6095 13:56:13.340610 EX_ROW_EN[1] = 0x0
6096 13:56:13.343681 LP4Y_EN = 0x0
6097 13:56:13.343750 WORK_FSP = 0x0
6098 13:56:13.346904 WL = 0x2
6099 13:56:13.346978 RL = 0x2
6100 13:56:13.350086 BL = 0x2
6101 13:56:13.350161 RPST = 0x0
6102 13:56:13.353455 RD_PRE = 0x0
6103 13:56:13.356820 WR_PRE = 0x1
6104 13:56:13.356891 WR_PST = 0x0
6105 13:56:13.360013 DBI_WR = 0x0
6106 13:56:13.360081 DBI_RD = 0x0
6107 13:56:13.363657 OTF = 0x1
6108 13:56:13.366654 ===================================
6109 13:56:13.370154 ===================================
6110 13:56:13.370231 ANA top config
6111 13:56:13.373556 ===================================
6112 13:56:13.377077 DLL_ASYNC_EN = 0
6113 13:56:13.380491 ALL_SLAVE_EN = 1
6114 13:56:13.380569 NEW_RANK_MODE = 1
6115 13:56:13.383282 DLL_IDLE_MODE = 1
6116 13:56:13.386605 LP45_APHY_COMB_EN = 1
6117 13:56:13.390206 TX_ODT_DIS = 1
6118 13:56:13.390287 NEW_8X_MODE = 1
6119 13:56:13.393724 ===================================
6120 13:56:13.396898 ===================================
6121 13:56:13.400232 data_rate = 800
6122 13:56:13.403577 CKR = 1
6123 13:56:13.406954 DQ_P2S_RATIO = 4
6124 13:56:13.410313 ===================================
6125 13:56:13.413333 CA_P2S_RATIO = 4
6126 13:56:13.417121 DQ_CA_OPEN = 0
6127 13:56:13.417231 DQ_SEMI_OPEN = 1
6128 13:56:13.420390 CA_SEMI_OPEN = 1
6129 13:56:13.423821 CA_FULL_RATE = 0
6130 13:56:13.426605 DQ_CKDIV4_EN = 0
6131 13:56:13.429998 CA_CKDIV4_EN = 1
6132 13:56:13.433466 CA_PREDIV_EN = 0
6133 13:56:13.433536 PH8_DLY = 0
6134 13:56:13.436729 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6135 13:56:13.440050 DQ_AAMCK_DIV = 0
6136 13:56:13.443547 CA_AAMCK_DIV = 0
6137 13:56:13.446785 CA_ADMCK_DIV = 4
6138 13:56:13.450231 DQ_TRACK_CA_EN = 0
6139 13:56:13.450306 CA_PICK = 800
6140 13:56:13.453411 CA_MCKIO = 400
6141 13:56:13.456747 MCKIO_SEMI = 400
6142 13:56:13.460159 PLL_FREQ = 3016
6143 13:56:13.463561 DQ_UI_PI_RATIO = 32
6144 13:56:13.466874 CA_UI_PI_RATIO = 32
6145 13:56:13.470089 ===================================
6146 13:56:13.473410 ===================================
6147 13:56:13.476730 memory_type:LPDDR4
6148 13:56:13.476806 GP_NUM : 10
6149 13:56:13.480121 SRAM_EN : 1
6150 13:56:13.480189 MD32_EN : 0
6151 13:56:13.483239 ===================================
6152 13:56:13.486793 [ANA_INIT] >>>>>>>>>>>>>>
6153 13:56:13.489831 <<<<<< [CONFIGURE PHASE]: ANA_TX
6154 13:56:13.493409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6155 13:56:13.496572 ===================================
6156 13:56:13.499747 data_rate = 800,PCW = 0X7400
6157 13:56:13.502915 ===================================
6158 13:56:13.506757 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6159 13:56:13.509945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6160 13:56:13.522795 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 13:56:13.526332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6162 13:56:13.529984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6163 13:56:13.533161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6164 13:56:13.536551 [ANA_INIT] flow start
6165 13:56:13.539957 [ANA_INIT] PLL >>>>>>>>
6166 13:56:13.540029 [ANA_INIT] PLL <<<<<<<<
6167 13:56:13.543386 [ANA_INIT] MIDPI >>>>>>>>
6168 13:56:13.546608 [ANA_INIT] MIDPI <<<<<<<<
6169 13:56:13.546705 [ANA_INIT] DLL >>>>>>>>
6170 13:56:13.549901 [ANA_INIT] flow end
6171 13:56:13.553320 ============ LP4 DIFF to SE enter ============
6172 13:56:13.556569 ============ LP4 DIFF to SE exit ============
6173 13:56:13.559744 [ANA_INIT] <<<<<<<<<<<<<
6174 13:56:13.562923 [Flow] Enable top DCM control >>>>>
6175 13:56:13.566363 [Flow] Enable top DCM control <<<<<
6176 13:56:13.569763 Enable DLL master slave shuffle
6177 13:56:13.576156 ==============================================================
6178 13:56:13.576280 Gating Mode config
6179 13:56:13.582745 ==============================================================
6180 13:56:13.582846 Config description:
6181 13:56:13.592594 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6182 13:56:13.599788 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6183 13:56:13.606186 SELPH_MODE 0: By rank 1: By Phase
6184 13:56:13.609404 ==============================================================
6185 13:56:13.612913 GAT_TRACK_EN = 0
6186 13:56:13.616137 RX_GATING_MODE = 2
6187 13:56:13.619218 RX_GATING_TRACK_MODE = 2
6188 13:56:13.622965 SELPH_MODE = 1
6189 13:56:13.626207 PICG_EARLY_EN = 1
6190 13:56:13.629554 VALID_LAT_VALUE = 1
6191 13:56:13.635829 ==============================================================
6192 13:56:13.639357 Enter into Gating configuration >>>>
6193 13:56:13.642942 Exit from Gating configuration <<<<
6194 13:56:13.645929 Enter into DVFS_PRE_config >>>>>
6195 13:56:13.655864 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6196 13:56:13.659232 Exit from DVFS_PRE_config <<<<<
6197 13:56:13.662682 Enter into PICG configuration >>>>
6198 13:56:13.665831 Exit from PICG configuration <<<<
6199 13:56:13.669548 [RX_INPUT] configuration >>>>>
6200 13:56:13.669626 [RX_INPUT] configuration <<<<<
6201 13:56:13.676110 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6202 13:56:13.682600 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6203 13:56:13.685726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 13:56:13.692402 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 13:56:13.699432 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6206 13:56:13.705944 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6207 13:56:13.709163 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6208 13:56:13.712447 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6209 13:56:13.719215 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6210 13:56:13.722281 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6211 13:56:13.725927 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6212 13:56:13.728860 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6213 13:56:13.732225 ===================================
6214 13:56:13.736097 LPDDR4 DRAM CONFIGURATION
6215 13:56:13.739412 ===================================
6216 13:56:13.742406 EX_ROW_EN[0] = 0x0
6217 13:56:13.742508 EX_ROW_EN[1] = 0x0
6218 13:56:13.745393 LP4Y_EN = 0x0
6219 13:56:13.745492 WORK_FSP = 0x0
6220 13:56:13.749206 WL = 0x2
6221 13:56:13.749283 RL = 0x2
6222 13:56:13.752149 BL = 0x2
6223 13:56:13.755436 RPST = 0x0
6224 13:56:13.755508 RD_PRE = 0x0
6225 13:56:13.758673 WR_PRE = 0x1
6226 13:56:13.758748 WR_PST = 0x0
6227 13:56:13.762304 DBI_WR = 0x0
6228 13:56:13.762399 DBI_RD = 0x0
6229 13:56:13.765632 OTF = 0x1
6230 13:56:13.768969 ===================================
6231 13:56:13.772230 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6232 13:56:13.775434 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6233 13:56:13.778716 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6234 13:56:13.782071 ===================================
6235 13:56:13.785387 LPDDR4 DRAM CONFIGURATION
6236 13:56:13.788503 ===================================
6237 13:56:13.791773 EX_ROW_EN[0] = 0x10
6238 13:56:13.791907 EX_ROW_EN[1] = 0x0
6239 13:56:13.795166 LP4Y_EN = 0x0
6240 13:56:13.795263 WORK_FSP = 0x0
6241 13:56:13.798505 WL = 0x2
6242 13:56:13.798600 RL = 0x2
6243 13:56:13.801910 BL = 0x2
6244 13:56:13.801981 RPST = 0x0
6245 13:56:13.805559 RD_PRE = 0x0
6246 13:56:13.805656 WR_PRE = 0x1
6247 13:56:13.808867 WR_PST = 0x0
6248 13:56:13.812151 DBI_WR = 0x0
6249 13:56:13.812231 DBI_RD = 0x0
6250 13:56:13.815497 OTF = 0x1
6251 13:56:13.818906 ===================================
6252 13:56:13.822194 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6253 13:56:13.826806 nWR fixed to 30
6254 13:56:13.830191 [ModeRegInit_LP4] CH0 RK0
6255 13:56:13.830264 [ModeRegInit_LP4] CH0 RK1
6256 13:56:13.833516 [ModeRegInit_LP4] CH1 RK0
6257 13:56:13.836838 [ModeRegInit_LP4] CH1 RK1
6258 13:56:13.836915 match AC timing 19
6259 13:56:13.843778 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6260 13:56:13.846715 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6261 13:56:13.850204 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6262 13:56:13.857068 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6263 13:56:13.860103 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6264 13:56:13.860183 ==
6265 13:56:13.863875 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 13:56:13.866816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 13:56:13.866900 ==
6268 13:56:13.873844 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6269 13:56:13.880119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6270 13:56:13.883698 [CA 0] Center 36 (8~64) winsize 57
6271 13:56:13.887065 [CA 1] Center 36 (8~64) winsize 57
6272 13:56:13.890186 [CA 2] Center 36 (8~64) winsize 57
6273 13:56:13.893464 [CA 3] Center 36 (8~64) winsize 57
6274 13:56:13.893539 [CA 4] Center 36 (8~64) winsize 57
6275 13:56:13.896735 [CA 5] Center 36 (8~64) winsize 57
6276 13:56:13.896810
6277 13:56:13.903400 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6278 13:56:13.903479
6279 13:56:13.906698 [CATrainingPosCal] consider 1 rank data
6280 13:56:13.909788 u2DelayCellTimex100 = 270/100 ps
6281 13:56:13.913147 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 13:56:13.916458 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 13:56:13.920322 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 13:56:13.923622 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 13:56:13.926985 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 13:56:13.930322 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 13:56:13.930397
6288 13:56:13.933711 CA PerBit enable=1, Macro0, CA PI delay=36
6289 13:56:13.933791
6290 13:56:13.936455 [CBTSetCACLKResult] CA Dly = 36
6291 13:56:13.939877 CS Dly: 1 (0~32)
6292 13:56:13.939949 ==
6293 13:56:13.943098 Dram Type= 6, Freq= 0, CH_0, rank 1
6294 13:56:13.946529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 13:56:13.946638 ==
6296 13:56:13.953169 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6297 13:56:13.956278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6298 13:56:13.960123 [CA 0] Center 36 (8~64) winsize 57
6299 13:56:13.963112 [CA 1] Center 36 (8~64) winsize 57
6300 13:56:13.966704 [CA 2] Center 36 (8~64) winsize 57
6301 13:56:13.969754 [CA 3] Center 36 (8~64) winsize 57
6302 13:56:13.973012 [CA 4] Center 36 (8~64) winsize 57
6303 13:56:13.976280 [CA 5] Center 36 (8~64) winsize 57
6304 13:56:13.976421
6305 13:56:13.979524 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6306 13:56:13.979600
6307 13:56:13.983139 [CATrainingPosCal] consider 2 rank data
6308 13:56:13.986747 u2DelayCellTimex100 = 270/100 ps
6309 13:56:13.989668 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 13:56:13.993404 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 13:56:13.996344 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 13:56:14.003194 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 13:56:14.006582 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 13:56:14.009892 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 13:56:14.009971
6316 13:56:14.013056 CA PerBit enable=1, Macro0, CA PI delay=36
6317 13:56:14.013156
6318 13:56:14.016718 [CBTSetCACLKResult] CA Dly = 36
6319 13:56:14.016796 CS Dly: 1 (0~32)
6320 13:56:14.016862
6321 13:56:14.019689 ----->DramcWriteLeveling(PI) begin...
6322 13:56:14.019760 ==
6323 13:56:14.023465 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 13:56:14.029585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 13:56:14.029689 ==
6326 13:56:14.032913 Write leveling (Byte 0): 40 => 8
6327 13:56:14.036166 Write leveling (Byte 1): 40 => 8
6328 13:56:14.036236 DramcWriteLeveling(PI) end<-----
6329 13:56:14.036344
6330 13:56:14.040155 ==
6331 13:56:14.043583 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 13:56:14.046280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 13:56:14.046354 ==
6334 13:56:14.049618 [Gating] SW mode calibration
6335 13:56:14.056322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6336 13:56:14.059780 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6337 13:56:14.066494 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6338 13:56:14.069588 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 13:56:14.073200 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 13:56:14.079731 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 13:56:14.082724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 13:56:14.086634 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 13:56:14.093265 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 13:56:14.096499 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 13:56:14.099616 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 13:56:14.102835 Total UI for P1: 0, mck2ui 16
6347 13:56:14.106002 best dqsien dly found for B0: ( 0, 14, 24)
6348 13:56:14.109318 Total UI for P1: 0, mck2ui 16
6349 13:56:14.112647 best dqsien dly found for B1: ( 0, 14, 24)
6350 13:56:14.116290 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6351 13:56:14.119288 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6352 13:56:14.119362
6353 13:56:14.125910 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6354 13:56:14.129162 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 13:56:14.129242 [Gating] SW calibration Done
6356 13:56:14.132674 ==
6357 13:56:14.136398 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 13:56:14.139245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 13:56:14.139356 ==
6360 13:56:14.139447 RX Vref Scan: 0
6361 13:56:14.139540
6362 13:56:14.142518 RX Vref 0 -> 0, step: 1
6363 13:56:14.142594
6364 13:56:14.145780 RX Delay -410 -> 252, step: 16
6365 13:56:14.149131 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6366 13:56:14.152521 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6367 13:56:14.159296 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6368 13:56:14.162542 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6369 13:56:14.165896 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6370 13:56:14.169161 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6371 13:56:14.175705 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6372 13:56:14.179010 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6373 13:56:14.182836 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6374 13:56:14.186025 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6375 13:56:14.192674 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6376 13:56:14.195785 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6377 13:56:14.199011 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6378 13:56:14.202953 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6379 13:56:14.209172 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6380 13:56:14.212532 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6381 13:56:14.212609 ==
6382 13:56:14.216137 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 13:56:14.218812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 13:56:14.218891 ==
6385 13:56:14.222288 DQS Delay:
6386 13:56:14.222363 DQS0 = 27, DQS1 = 35
6387 13:56:14.225786 DQM Delay:
6388 13:56:14.225864 DQM0 = 9, DQM1 = 12
6389 13:56:14.225952 DQ Delay:
6390 13:56:14.229045 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6391 13:56:14.232327 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6392 13:56:14.236096 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6393 13:56:14.239174 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6394 13:56:14.239266
6395 13:56:14.239364
6396 13:56:14.239469 ==
6397 13:56:14.242780 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 13:56:14.246327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 13:56:14.249248 ==
6400 13:56:14.249346
6401 13:56:14.249412
6402 13:56:14.249471 TX Vref Scan disable
6403 13:56:14.252577 == TX Byte 0 ==
6404 13:56:14.255728 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 13:56:14.259044 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 13:56:14.262669 == TX Byte 1 ==
6407 13:56:14.265899 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 13:56:14.269188 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 13:56:14.269287 ==
6410 13:56:14.272611 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 13:56:14.279258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 13:56:14.279370 ==
6413 13:56:14.279462
6414 13:56:14.279559
6415 13:56:14.279646 TX Vref Scan disable
6416 13:56:14.282557 == TX Byte 0 ==
6417 13:56:14.285766 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 13:56:14.288997 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 13:56:14.292438 == TX Byte 1 ==
6420 13:56:14.295685 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 13:56:14.298703 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 13:56:14.298802
6423 13:56:14.302369 [DATLAT]
6424 13:56:14.302474 Freq=400, CH0 RK0
6425 13:56:14.302564
6426 13:56:14.305422 DATLAT Default: 0xf
6427 13:56:14.305506 0, 0xFFFF, sum = 0
6428 13:56:14.308723 1, 0xFFFF, sum = 0
6429 13:56:14.308818 2, 0xFFFF, sum = 0
6430 13:56:14.311985 3, 0xFFFF, sum = 0
6431 13:56:14.312091 4, 0xFFFF, sum = 0
6432 13:56:14.315052 5, 0xFFFF, sum = 0
6433 13:56:14.315167 6, 0xFFFF, sum = 0
6434 13:56:14.319047 7, 0xFFFF, sum = 0
6435 13:56:14.319152 8, 0xFFFF, sum = 0
6436 13:56:14.321784 9, 0xFFFF, sum = 0
6437 13:56:14.325264 10, 0xFFFF, sum = 0
6438 13:56:14.325358 11, 0xFFFF, sum = 0
6439 13:56:14.328540 12, 0xFFFF, sum = 0
6440 13:56:14.328634 13, 0x0, sum = 1
6441 13:56:14.331886 14, 0x0, sum = 2
6442 13:56:14.331985 15, 0x0, sum = 3
6443 13:56:14.332074 16, 0x0, sum = 4
6444 13:56:14.335249 best_step = 14
6445 13:56:14.335355
6446 13:56:14.335456 ==
6447 13:56:14.338576 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 13:56:14.341896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 13:56:14.341972 ==
6450 13:56:14.345240 RX Vref Scan: 1
6451 13:56:14.345329
6452 13:56:14.348444 RX Vref 0 -> 0, step: 1
6453 13:56:14.348518
6454 13:56:14.348578 RX Delay -311 -> 252, step: 8
6455 13:56:14.348636
6456 13:56:14.351696 Set Vref, RX VrefLevel [Byte0]: 58
6457 13:56:14.354905 [Byte1]: 47
6458 13:56:14.360213
6459 13:56:14.360320 Final RX Vref Byte 0 = 58 to rank0
6460 13:56:14.363910 Final RX Vref Byte 1 = 47 to rank0
6461 13:56:14.366772 Final RX Vref Byte 0 = 58 to rank1
6462 13:56:14.370426 Final RX Vref Byte 1 = 47 to rank1==
6463 13:56:14.373523 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 13:56:14.380240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 13:56:14.380373 ==
6466 13:56:14.380477 DQS Delay:
6467 13:56:14.383493 DQS0 = 24, DQS1 = 36
6468 13:56:14.383575 DQM Delay:
6469 13:56:14.383654 DQM0 = 7, DQM1 = 13
6470 13:56:14.386739 DQ Delay:
6471 13:56:14.386846 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6472 13:56:14.389963 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6473 13:56:14.393701 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6474 13:56:14.396992 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6475 13:56:14.397102
6476 13:56:14.397207
6477 13:56:14.406805 [DQSOSCAuto] RK0, (LSB)MR18= 0xcfbd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6478 13:56:14.410049 CH0 RK0: MR19=C0C, MR18=CFBD
6479 13:56:14.416750 CH0_RK0: MR19=0xC0C, MR18=0xCFBD, DQSOSC=384, MR23=63, INC=400, DEC=267
6480 13:56:14.416831 ==
6481 13:56:14.419886 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 13:56:14.423126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 13:56:14.423204 ==
6484 13:56:14.427090 [Gating] SW mode calibration
6485 13:56:14.433302 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6486 13:56:14.436680 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6487 13:56:14.443310 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6488 13:56:14.446707 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 13:56:14.450087 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 13:56:14.456614 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 13:56:14.459851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 13:56:14.463087 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 13:56:14.469839 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 13:56:14.473017 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 13:56:14.476282 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 13:56:14.479653 Total UI for P1: 0, mck2ui 16
6497 13:56:14.483351 best dqsien dly found for B0: ( 0, 14, 24)
6498 13:56:14.486288 Total UI for P1: 0, mck2ui 16
6499 13:56:14.489429 best dqsien dly found for B1: ( 0, 14, 24)
6500 13:56:14.493278 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6501 13:56:14.496653 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6502 13:56:14.496736
6503 13:56:14.502758 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6504 13:56:14.506441 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 13:56:14.509562 [Gating] SW calibration Done
6506 13:56:14.509641 ==
6507 13:56:14.512883 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 13:56:14.516239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 13:56:14.516354 ==
6510 13:56:14.516426 RX Vref Scan: 0
6511 13:56:14.516489
6512 13:56:14.519626 RX Vref 0 -> 0, step: 1
6513 13:56:14.519697
6514 13:56:14.523265 RX Delay -410 -> 252, step: 16
6515 13:56:14.526397 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6516 13:56:14.532947 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6517 13:56:14.536192 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6518 13:56:14.539921 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6519 13:56:14.543027 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6520 13:56:14.549671 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6521 13:56:14.553036 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6522 13:56:14.555792 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6523 13:56:14.559557 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6524 13:56:14.566310 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6525 13:56:14.569651 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6526 13:56:14.573040 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6527 13:56:14.576214 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6528 13:56:14.582854 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6529 13:56:14.586296 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6530 13:56:14.589647 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6531 13:56:14.589722 ==
6532 13:56:14.592886 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 13:56:14.596120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 13:56:14.599354 ==
6535 13:56:14.599451 DQS Delay:
6536 13:56:14.599517 DQS0 = 27, DQS1 = 35
6537 13:56:14.602795 DQM Delay:
6538 13:56:14.602868 DQM0 = 11, DQM1 = 11
6539 13:56:14.605843 DQ Delay:
6540 13:56:14.605915 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6541 13:56:14.609755 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6542 13:56:14.612838 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6543 13:56:14.616281 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6544 13:56:14.616394
6545 13:56:14.616457
6546 13:56:14.616516 ==
6547 13:56:14.619374 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 13:56:14.626197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 13:56:14.626273 ==
6550 13:56:14.626343
6551 13:56:14.626402
6552 13:56:14.626459 TX Vref Scan disable
6553 13:56:14.629359 == TX Byte 0 ==
6554 13:56:14.632713 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6555 13:56:14.635739 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6556 13:56:14.639605 == TX Byte 1 ==
6557 13:56:14.642395 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6558 13:56:14.646124 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6559 13:56:14.646231 ==
6560 13:56:14.649517 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 13:56:14.656042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 13:56:14.656122 ==
6563 13:56:14.656186
6564 13:56:14.656253
6565 13:56:14.659358 TX Vref Scan disable
6566 13:56:14.659433 == TX Byte 0 ==
6567 13:56:14.662817 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6568 13:56:14.666113 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6569 13:56:14.669332 == TX Byte 1 ==
6570 13:56:14.672617 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6571 13:56:14.675911 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6572 13:56:14.679204
6573 13:56:14.679286 [DATLAT]
6574 13:56:14.679352 Freq=400, CH0 RK1
6575 13:56:14.679412
6576 13:56:14.682614 DATLAT Default: 0xe
6577 13:56:14.682695 0, 0xFFFF, sum = 0
6578 13:56:14.685904 1, 0xFFFF, sum = 0
6579 13:56:14.685986 2, 0xFFFF, sum = 0
6580 13:56:14.688674 3, 0xFFFF, sum = 0
6581 13:56:14.688757 4, 0xFFFF, sum = 0
6582 13:56:14.691945 5, 0xFFFF, sum = 0
6583 13:56:14.695329 6, 0xFFFF, sum = 0
6584 13:56:14.695442 7, 0xFFFF, sum = 0
6585 13:56:14.698636 8, 0xFFFF, sum = 0
6586 13:56:14.698724 9, 0xFFFF, sum = 0
6587 13:56:14.701953 10, 0xFFFF, sum = 0
6588 13:56:14.702035 11, 0xFFFF, sum = 0
6589 13:56:14.705778 12, 0xFFFF, sum = 0
6590 13:56:14.705860 13, 0x0, sum = 1
6591 13:56:14.708931 14, 0x0, sum = 2
6592 13:56:14.709039 15, 0x0, sum = 3
6593 13:56:14.712220 16, 0x0, sum = 4
6594 13:56:14.712351 best_step = 14
6595 13:56:14.712419
6596 13:56:14.712479 ==
6597 13:56:14.715591 Dram Type= 6, Freq= 0, CH_0, rank 1
6598 13:56:14.718879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 13:56:14.718961 ==
6600 13:56:14.722158 RX Vref Scan: 0
6601 13:56:14.722259
6602 13:56:14.725484 RX Vref 0 -> 0, step: 1
6603 13:56:14.725583
6604 13:56:14.725649 RX Delay -311 -> 252, step: 8
6605 13:56:14.734148 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6606 13:56:14.737262 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6607 13:56:14.740779 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6608 13:56:14.744174 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6609 13:56:14.750563 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6610 13:56:14.753900 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6611 13:56:14.757355 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6612 13:56:14.760820 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6613 13:56:14.767261 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6614 13:56:14.770701 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6615 13:56:14.773885 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6616 13:56:14.777212 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6617 13:56:14.783765 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6618 13:56:14.787492 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6619 13:56:14.790638 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6620 13:56:14.797277 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6621 13:56:14.797380 ==
6622 13:56:14.800641 Dram Type= 6, Freq= 0, CH_0, rank 1
6623 13:56:14.804095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 13:56:14.804187 ==
6625 13:56:14.804259 DQS Delay:
6626 13:56:14.807446 DQS0 = 24, DQS1 = 36
6627 13:56:14.807527 DQM Delay:
6628 13:56:14.810132 DQM0 = 8, DQM1 = 13
6629 13:56:14.810205 DQ Delay:
6630 13:56:14.813882 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6631 13:56:14.817060 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6632 13:56:14.820442 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6633 13:56:14.823897 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6634 13:56:14.823996
6635 13:56:14.824092
6636 13:56:14.830321 [DQSOSCAuto] RK1, (LSB)MR18= 0xb657, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6637 13:56:14.833746 CH0 RK1: MR19=C0C, MR18=B657
6638 13:56:14.840417 CH0_RK1: MR19=0xC0C, MR18=0xB657, DQSOSC=387, MR23=63, INC=394, DEC=262
6639 13:56:14.843701 [RxdqsGatingPostProcess] freq 400
6640 13:56:14.846974 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6641 13:56:14.850419 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 13:56:14.853629 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 13:56:14.856746 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 13:56:14.860380 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 13:56:14.863378 best DQS0 dly(2T, 0.5T) = (0, 10)
6646 13:56:14.866928 best DQS1 dly(2T, 0.5T) = (0, 10)
6647 13:56:14.870589 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6648 13:56:14.873901 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6649 13:56:14.876945 Pre-setting of DQS Precalculation
6650 13:56:14.879906 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6651 13:56:14.883430 ==
6652 13:56:14.886653 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 13:56:14.889930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 13:56:14.890028 ==
6655 13:56:14.893319 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6656 13:56:14.900217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6657 13:56:14.903525 [CA 0] Center 36 (8~64) winsize 57
6658 13:56:14.906739 [CA 1] Center 36 (8~64) winsize 57
6659 13:56:14.909986 [CA 2] Center 36 (8~64) winsize 57
6660 13:56:14.913425 [CA 3] Center 36 (8~64) winsize 57
6661 13:56:14.916667 [CA 4] Center 36 (8~64) winsize 57
6662 13:56:14.919965 [CA 5] Center 36 (8~64) winsize 57
6663 13:56:14.920047
6664 13:56:14.923761 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6665 13:56:14.923843
6666 13:56:14.926866 [CATrainingPosCal] consider 1 rank data
6667 13:56:14.930305 u2DelayCellTimex100 = 270/100 ps
6668 13:56:14.933637 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 13:56:14.937123 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 13:56:14.940582 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 13:56:14.943100 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 13:56:14.946507 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 13:56:14.953192 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 13:56:14.953274
6675 13:56:14.956583 CA PerBit enable=1, Macro0, CA PI delay=36
6676 13:56:14.956704
6677 13:56:14.959764 [CBTSetCACLKResult] CA Dly = 36
6678 13:56:14.959846 CS Dly: 1 (0~32)
6679 13:56:14.959911 ==
6680 13:56:14.963088 Dram Type= 6, Freq= 0, CH_1, rank 1
6681 13:56:14.966397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 13:56:14.969648 ==
6683 13:56:14.972928 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6684 13:56:14.979891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6685 13:56:14.982926 [CA 0] Center 36 (8~64) winsize 57
6686 13:56:14.986291 [CA 1] Center 36 (8~64) winsize 57
6687 13:56:14.990148 [CA 2] Center 36 (8~64) winsize 57
6688 13:56:14.993444 [CA 3] Center 36 (8~64) winsize 57
6689 13:56:14.996260 [CA 4] Center 36 (8~64) winsize 57
6690 13:56:14.999731 [CA 5] Center 36 (8~64) winsize 57
6691 13:56:14.999813
6692 13:56:15.002754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6693 13:56:15.002844
6694 13:56:15.006177 [CATrainingPosCal] consider 2 rank data
6695 13:56:15.009474 u2DelayCellTimex100 = 270/100 ps
6696 13:56:15.013127 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 13:56:15.016201 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 13:56:15.019729 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 13:56:15.022807 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 13:56:15.025978 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 13:56:15.029358 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 13:56:15.029435
6703 13:56:15.036148 CA PerBit enable=1, Macro0, CA PI delay=36
6704 13:56:15.036259
6705 13:56:15.036391 [CBTSetCACLKResult] CA Dly = 36
6706 13:56:15.039052 CS Dly: 1 (0~32)
6707 13:56:15.039148
6708 13:56:15.042766 ----->DramcWriteLeveling(PI) begin...
6709 13:56:15.042875 ==
6710 13:56:15.046167 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 13:56:15.049670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 13:56:15.049777 ==
6713 13:56:15.052392 Write leveling (Byte 0): 40 => 8
6714 13:56:15.056394 Write leveling (Byte 1): 40 => 8
6715 13:56:15.059036 DramcWriteLeveling(PI) end<-----
6716 13:56:15.059151
6717 13:56:15.059252 ==
6718 13:56:15.062423 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 13:56:15.065750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 13:56:15.069074 ==
6721 13:56:15.069198 [Gating] SW mode calibration
6722 13:56:15.075656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6723 13:56:15.082256 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6724 13:56:15.085641 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6725 13:56:15.092087 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 13:56:15.095682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 13:56:15.098983 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 13:56:15.105403 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 13:56:15.108955 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 13:56:15.112302 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 13:56:15.119006 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 13:56:15.122442 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 13:56:15.125836 Total UI for P1: 0, mck2ui 16
6734 13:56:15.128956 best dqsien dly found for B0: ( 0, 14, 24)
6735 13:56:15.132223 Total UI for P1: 0, mck2ui 16
6736 13:56:15.135385 best dqsien dly found for B1: ( 0, 14, 24)
6737 13:56:15.138949 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6738 13:56:15.142668 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6739 13:56:15.142751
6740 13:56:15.145452 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6741 13:56:15.149040 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 13:56:15.152435 [Gating] SW calibration Done
6743 13:56:15.152514 ==
6744 13:56:15.155351 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 13:56:15.158776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 13:56:15.158855 ==
6747 13:56:15.161966 RX Vref Scan: 0
6748 13:56:15.162040
6749 13:56:15.165396 RX Vref 0 -> 0, step: 1
6750 13:56:15.165468
6751 13:56:15.168880 RX Delay -410 -> 252, step: 16
6752 13:56:15.171953 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6753 13:56:15.175262 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6754 13:56:15.178532 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6755 13:56:15.185159 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6756 13:56:15.188951 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6757 13:56:15.191742 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6758 13:56:15.195630 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6759 13:56:15.202004 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6760 13:56:15.205208 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6761 13:56:15.208476 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6762 13:56:15.211745 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6763 13:56:15.218575 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6764 13:56:15.221761 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6765 13:56:15.225262 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6766 13:56:15.228220 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6767 13:56:15.234864 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6768 13:56:15.234952 ==
6769 13:56:15.238209 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 13:56:15.241596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 13:56:15.241671 ==
6772 13:56:15.241733 DQS Delay:
6773 13:56:15.245582 DQS0 = 35, DQS1 = 35
6774 13:56:15.245659 DQM Delay:
6775 13:56:15.248736 DQM0 = 18, DQM1 = 13
6776 13:56:15.248815 DQ Delay:
6777 13:56:15.252176 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6778 13:56:15.255335 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6779 13:56:15.258900 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6780 13:56:15.261592 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6781 13:56:15.261679
6782 13:56:15.261764
6783 13:56:15.261826 ==
6784 13:56:15.265327 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 13:56:15.268206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 13:56:15.268377 ==
6787 13:56:15.268462
6788 13:56:15.271808
6789 13:56:15.271895 TX Vref Scan disable
6790 13:56:15.274815 == TX Byte 0 ==
6791 13:56:15.278116 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 13:56:15.281310 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 13:56:15.284678 == TX Byte 1 ==
6794 13:56:15.288164 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 13:56:15.291483 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 13:56:15.291569 ==
6797 13:56:15.294788 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 13:56:15.298042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 13:56:15.301395 ==
6800 13:56:15.301473
6801 13:56:15.301536
6802 13:56:15.301594 TX Vref Scan disable
6803 13:56:15.304564 == TX Byte 0 ==
6804 13:56:15.308314 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 13:56:15.311399 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 13:56:15.314661 == TX Byte 1 ==
6807 13:56:15.317886 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 13:56:15.321290 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 13:56:15.321369
6810 13:56:15.321439 [DATLAT]
6811 13:56:15.324984 Freq=400, CH1 RK0
6812 13:56:15.325077
6813 13:56:15.328113 DATLAT Default: 0xf
6814 13:56:15.328189 0, 0xFFFF, sum = 0
6815 13:56:15.331289 1, 0xFFFF, sum = 0
6816 13:56:15.331375 2, 0xFFFF, sum = 0
6817 13:56:15.334912 3, 0xFFFF, sum = 0
6818 13:56:15.334989 4, 0xFFFF, sum = 0
6819 13:56:15.338126 5, 0xFFFF, sum = 0
6820 13:56:15.338202 6, 0xFFFF, sum = 0
6821 13:56:15.341351 7, 0xFFFF, sum = 0
6822 13:56:15.341429 8, 0xFFFF, sum = 0
6823 13:56:15.344668 9, 0xFFFF, sum = 0
6824 13:56:15.344750 10, 0xFFFF, sum = 0
6825 13:56:15.348106 11, 0xFFFF, sum = 0
6826 13:56:15.348189 12, 0xFFFF, sum = 0
6827 13:56:15.351191 13, 0x0, sum = 1
6828 13:56:15.351269 14, 0x0, sum = 2
6829 13:56:15.354520 15, 0x0, sum = 3
6830 13:56:15.354614 16, 0x0, sum = 4
6831 13:56:15.357871 best_step = 14
6832 13:56:15.357946
6833 13:56:15.358015 ==
6834 13:56:15.361190 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 13:56:15.364497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 13:56:15.364583 ==
6837 13:56:15.367721 RX Vref Scan: 1
6838 13:56:15.367838
6839 13:56:15.367918 RX Vref 0 -> 0, step: 1
6840 13:56:15.367982
6841 13:56:15.371669 RX Delay -311 -> 252, step: 8
6842 13:56:15.371768
6843 13:56:15.375151 Set Vref, RX VrefLevel [Byte0]: 53
6844 13:56:15.378064 [Byte1]: 47
6845 13:56:15.382327
6846 13:56:15.382402 Final RX Vref Byte 0 = 53 to rank0
6847 13:56:15.385505 Final RX Vref Byte 1 = 47 to rank0
6848 13:56:15.388901 Final RX Vref Byte 0 = 53 to rank1
6849 13:56:15.392231 Final RX Vref Byte 1 = 47 to rank1==
6850 13:56:15.395260 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 13:56:15.401941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 13:56:15.402023 ==
6853 13:56:15.402087 DQS Delay:
6854 13:56:15.405266 DQS0 = 32, DQS1 = 32
6855 13:56:15.405372 DQM Delay:
6856 13:56:15.405463 DQM0 = 13, DQM1 = 12
6857 13:56:15.408621 DQ Delay:
6858 13:56:15.411795 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6859 13:56:15.415102 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6860 13:56:15.415206 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6861 13:56:15.419101 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6862 13:56:15.421913
6863 13:56:15.421990
6864 13:56:15.428427 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6865 13:56:15.432214 CH1 RK0: MR19=C0C, MR18=8EC7
6866 13:56:15.438805 CH1_RK0: MR19=0xC0C, MR18=0x8EC7, DQSOSC=385, MR23=63, INC=398, DEC=265
6867 13:56:15.438912 ==
6868 13:56:15.441950 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 13:56:15.445544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 13:56:15.445648 ==
6871 13:56:15.448686 [Gating] SW mode calibration
6872 13:56:15.455419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6873 13:56:15.461931 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6874 13:56:15.465363 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6875 13:56:15.468730 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 13:56:15.475143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 13:56:15.478326 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 13:56:15.482164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 13:56:15.485449 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 13:56:15.492131 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 13:56:15.495236 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 13:56:15.498389 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 13:56:15.502009 Total UI for P1: 0, mck2ui 16
6884 13:56:15.504922 best dqsien dly found for B0: ( 0, 14, 24)
6885 13:56:15.508436 Total UI for P1: 0, mck2ui 16
6886 13:56:15.511690 best dqsien dly found for B1: ( 0, 14, 24)
6887 13:56:15.515117 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6888 13:56:15.521821 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6889 13:56:15.521900
6890 13:56:15.524983 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6891 13:56:15.528277 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 13:56:15.531621 [Gating] SW calibration Done
6893 13:56:15.531694 ==
6894 13:56:15.535002 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 13:56:15.538790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 13:56:15.538902 ==
6897 13:56:15.541964 RX Vref Scan: 0
6898 13:56:15.542038
6899 13:56:15.542100 RX Vref 0 -> 0, step: 1
6900 13:56:15.542163
6901 13:56:15.544686 RX Delay -410 -> 252, step: 16
6902 13:56:15.548572 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6903 13:56:15.554855 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6904 13:56:15.558552 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6905 13:56:15.561695 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6906 13:56:15.565089 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6907 13:56:15.571861 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6908 13:56:15.574600 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6909 13:56:15.577854 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6910 13:56:15.581793 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6911 13:56:15.588158 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6912 13:56:15.591477 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6913 13:56:15.594884 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6914 13:56:15.598260 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6915 13:56:15.604942 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6916 13:56:15.608367 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6917 13:56:15.611579 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6918 13:56:15.611709 ==
6919 13:56:15.614703 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 13:56:15.618349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 13:56:15.621292 ==
6922 13:56:15.621415 DQS Delay:
6923 13:56:15.621537 DQS0 = 27, DQS1 = 35
6924 13:56:15.624756 DQM Delay:
6925 13:56:15.624879 DQM0 = 13, DQM1 = 20
6926 13:56:15.628260 DQ Delay:
6927 13:56:15.628399 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6928 13:56:15.631417 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6929 13:56:15.634954 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6930 13:56:15.638262 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6931 13:56:15.638373
6932 13:56:15.638468
6933 13:56:15.641586 ==
6934 13:56:15.641666 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 13:56:15.647835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 13:56:15.647948 ==
6937 13:56:15.648047
6938 13:56:15.648136
6939 13:56:15.651768 TX Vref Scan disable
6940 13:56:15.651847 == TX Byte 0 ==
6941 13:56:15.655110 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6942 13:56:15.658390 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6943 13:56:15.661808 == TX Byte 1 ==
6944 13:56:15.664782 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6945 13:56:15.668058 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6946 13:56:15.671797 ==
6947 13:56:15.671933 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 13:56:15.678173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 13:56:15.678260 ==
6950 13:56:15.678333
6951 13:56:15.678403
6952 13:56:15.681617 TX Vref Scan disable
6953 13:56:15.681695 == TX Byte 0 ==
6954 13:56:15.684396 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6955 13:56:15.688248 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6956 13:56:15.691433 == TX Byte 1 ==
6957 13:56:15.694537 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6958 13:56:15.698140 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6959 13:56:15.698228
6960 13:56:15.701525 [DATLAT]
6961 13:56:15.701607 Freq=400, CH1 RK1
6962 13:56:15.701680
6963 13:56:15.704828 DATLAT Default: 0xe
6964 13:56:15.704909 0, 0xFFFF, sum = 0
6965 13:56:15.708092 1, 0xFFFF, sum = 0
6966 13:56:15.708178 2, 0xFFFF, sum = 0
6967 13:56:15.711367 3, 0xFFFF, sum = 0
6968 13:56:15.711451 4, 0xFFFF, sum = 0
6969 13:56:15.714982 5, 0xFFFF, sum = 0
6970 13:56:15.715060 6, 0xFFFF, sum = 0
6971 13:56:15.718233 7, 0xFFFF, sum = 0
6972 13:56:15.718315 8, 0xFFFF, sum = 0
6973 13:56:15.721571 9, 0xFFFF, sum = 0
6974 13:56:15.724920 10, 0xFFFF, sum = 0
6975 13:56:15.725004 11, 0xFFFF, sum = 0
6976 13:56:15.728230 12, 0xFFFF, sum = 0
6977 13:56:15.728330 13, 0x0, sum = 1
6978 13:56:15.731447 14, 0x0, sum = 2
6979 13:56:15.731528 15, 0x0, sum = 3
6980 13:56:15.734524 16, 0x0, sum = 4
6981 13:56:15.734600 best_step = 14
6982 13:56:15.734672
6983 13:56:15.734736 ==
6984 13:56:15.738084 Dram Type= 6, Freq= 0, CH_1, rank 1
6985 13:56:15.741056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6986 13:56:15.741131 ==
6987 13:56:15.744413 RX Vref Scan: 0
6988 13:56:15.744495
6989 13:56:15.747859 RX Vref 0 -> 0, step: 1
6990 13:56:15.747943
6991 13:56:15.748008 RX Delay -311 -> 252, step: 8
6992 13:56:15.756213 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6993 13:56:15.759861 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6994 13:56:15.763276 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6995 13:56:15.766590 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6996 13:56:15.773185 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6997 13:56:15.776478 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6998 13:56:15.779562 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6999 13:56:15.782797 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7000 13:56:15.789585 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7001 13:56:15.792954 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7002 13:56:15.796309 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
7003 13:56:15.799743 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7004 13:56:15.806346 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7005 13:56:15.809522 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7006 13:56:15.812819 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7007 13:56:15.816147 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
7008 13:56:15.819516 ==
7009 13:56:15.822909 Dram Type= 6, Freq= 0, CH_1, rank 1
7010 13:56:15.826065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7011 13:56:15.826149 ==
7012 13:56:15.826216 DQS Delay:
7013 13:56:15.829410 DQS0 = 28, DQS1 = 36
7014 13:56:15.829494 DQM Delay:
7015 13:56:15.832817 DQM0 = 11, DQM1 = 15
7016 13:56:15.832900 DQ Delay:
7017 13:56:15.836204 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7018 13:56:15.839650 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
7019 13:56:15.842811 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
7020 13:56:15.846128 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
7021 13:56:15.846212
7022 13:56:15.846278
7023 13:56:15.852489 [DQSOSCAuto] RK1, (LSB)MR18= 0xc657, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7024 13:56:15.855985 CH1 RK1: MR19=C0C, MR18=C657
7025 13:56:15.862393 CH1_RK1: MR19=0xC0C, MR18=0xC657, DQSOSC=385, MR23=63, INC=398, DEC=265
7026 13:56:15.866037 [RxdqsGatingPostProcess] freq 400
7027 13:56:15.872591 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7028 13:56:15.872677 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 13:56:15.875591 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 13:56:15.879306 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 13:56:15.882654 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 13:56:15.885919 best DQS0 dly(2T, 0.5T) = (0, 10)
7033 13:56:15.889314 best DQS1 dly(2T, 0.5T) = (0, 10)
7034 13:56:15.892472 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7035 13:56:15.896125 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7036 13:56:15.899189 Pre-setting of DQS Precalculation
7037 13:56:15.902396 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7038 13:56:15.912736 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7039 13:56:15.919104 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7040 13:56:15.919189
7041 13:56:15.919256
7042 13:56:15.922356 [Calibration Summary] 800 Mbps
7043 13:56:15.922440 CH 0, Rank 0
7044 13:56:15.925724 SW Impedance : PASS
7045 13:56:15.925808 DUTY Scan : NO K
7046 13:56:15.929014 ZQ Calibration : PASS
7047 13:56:15.932465 Jitter Meter : NO K
7048 13:56:15.932549 CBT Training : PASS
7049 13:56:15.935735 Write leveling : PASS
7050 13:56:15.939126 RX DQS gating : PASS
7051 13:56:15.939209 RX DQ/DQS(RDDQC) : PASS
7052 13:56:15.942390 TX DQ/DQS : PASS
7053 13:56:15.945771 RX DATLAT : PASS
7054 13:56:15.945856 RX DQ/DQS(Engine): PASS
7055 13:56:15.948950 TX OE : NO K
7056 13:56:15.949034 All Pass.
7057 13:56:15.949101
7058 13:56:15.952317 CH 0, Rank 1
7059 13:56:15.952401 SW Impedance : PASS
7060 13:56:15.955725 DUTY Scan : NO K
7061 13:56:15.959011 ZQ Calibration : PASS
7062 13:56:15.959094 Jitter Meter : NO K
7063 13:56:15.962207 CBT Training : PASS
7064 13:56:15.962291 Write leveling : NO K
7065 13:56:15.965351 RX DQS gating : PASS
7066 13:56:15.969075 RX DQ/DQS(RDDQC) : PASS
7067 13:56:15.969159 TX DQ/DQS : PASS
7068 13:56:15.972206 RX DATLAT : PASS
7069 13:56:15.975320 RX DQ/DQS(Engine): PASS
7070 13:56:15.975404 TX OE : NO K
7071 13:56:15.978639 All Pass.
7072 13:56:15.978722
7073 13:56:15.978788 CH 1, Rank 0
7074 13:56:15.982272 SW Impedance : PASS
7075 13:56:15.982356 DUTY Scan : NO K
7076 13:56:15.985322 ZQ Calibration : PASS
7077 13:56:15.988888 Jitter Meter : NO K
7078 13:56:15.988972 CBT Training : PASS
7079 13:56:15.992085 Write leveling : PASS
7080 13:56:15.995724 RX DQS gating : PASS
7081 13:56:15.995809 RX DQ/DQS(RDDQC) : PASS
7082 13:56:15.998386 TX DQ/DQS : PASS
7083 13:56:16.001761 RX DATLAT : PASS
7084 13:56:16.001845 RX DQ/DQS(Engine): PASS
7085 13:56:16.005129 TX OE : NO K
7086 13:56:16.005214 All Pass.
7087 13:56:16.005280
7088 13:56:16.008776 CH 1, Rank 1
7089 13:56:16.008859 SW Impedance : PASS
7090 13:56:16.011891 DUTY Scan : NO K
7091 13:56:16.011975 ZQ Calibration : PASS
7092 13:56:16.015645 Jitter Meter : NO K
7093 13:56:16.018735 CBT Training : PASS
7094 13:56:16.018820 Write leveling : NO K
7095 13:56:16.021970 RX DQS gating : PASS
7096 13:56:16.025578 RX DQ/DQS(RDDQC) : PASS
7097 13:56:16.025689 TX DQ/DQS : PASS
7098 13:56:16.028968 RX DATLAT : PASS
7099 13:56:16.032184 RX DQ/DQS(Engine): PASS
7100 13:56:16.032267 TX OE : NO K
7101 13:56:16.035329 All Pass.
7102 13:56:16.035412
7103 13:56:16.035487 DramC Write-DBI off
7104 13:56:16.038741 PER_BANK_REFRESH: Hybrid Mode
7105 13:56:16.038816 TX_TRACKING: ON
7106 13:56:16.048805 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7107 13:56:16.052113 [FAST_K] Save calibration result to emmc
7108 13:56:16.055320 dramc_set_vcore_voltage set vcore to 725000
7109 13:56:16.059342 Read voltage for 1600, 0
7110 13:56:16.059419 Vio18 = 0
7111 13:56:16.061994 Vcore = 725000
7112 13:56:16.062069 Vdram = 0
7113 13:56:16.062132 Vddq = 0
7114 13:56:16.066267 Vmddr = 0
7115 13:56:16.068794 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7116 13:56:16.075491 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7117 13:56:16.075585 MEM_TYPE=3, freq_sel=13
7118 13:56:16.079245 sv_algorithm_assistance_LP4_3733
7119 13:56:16.082464 ============ PULL DRAM RESETB DOWN ============
7120 13:56:16.088634 ========== PULL DRAM RESETB DOWN end =========
7121 13:56:16.091946 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7122 13:56:16.095378 ===================================
7123 13:56:16.098606 LPDDR4 DRAM CONFIGURATION
7124 13:56:16.102459 ===================================
7125 13:56:16.102545 EX_ROW_EN[0] = 0x0
7126 13:56:16.105317 EX_ROW_EN[1] = 0x0
7127 13:56:16.108760 LP4Y_EN = 0x0
7128 13:56:16.108836 WORK_FSP = 0x1
7129 13:56:16.111945 WL = 0x5
7130 13:56:16.112062 RL = 0x5
7131 13:56:16.115068 BL = 0x2
7132 13:56:16.115170 RPST = 0x0
7133 13:56:16.118258 RD_PRE = 0x0
7134 13:56:16.118344 WR_PRE = 0x1
7135 13:56:16.121871 WR_PST = 0x1
7136 13:56:16.121950 DBI_WR = 0x0
7137 13:56:16.125303 DBI_RD = 0x0
7138 13:56:16.125396 OTF = 0x1
7139 13:56:16.128719 ===================================
7140 13:56:16.131819 ===================================
7141 13:56:16.135288 ANA top config
7142 13:56:16.138410 ===================================
7143 13:56:16.138489 DLL_ASYNC_EN = 0
7144 13:56:16.142085 ALL_SLAVE_EN = 0
7145 13:56:16.144954 NEW_RANK_MODE = 1
7146 13:56:16.148193 DLL_IDLE_MODE = 1
7147 13:56:16.151583 LP45_APHY_COMB_EN = 1
7148 13:56:16.151667 TX_ODT_DIS = 0
7149 13:56:16.154965 NEW_8X_MODE = 1
7150 13:56:16.158355 ===================================
7151 13:56:16.161375 ===================================
7152 13:56:16.164664 data_rate = 3200
7153 13:56:16.167987 CKR = 1
7154 13:56:16.171400 DQ_P2S_RATIO = 8
7155 13:56:16.175263 ===================================
7156 13:56:16.175348 CA_P2S_RATIO = 8
7157 13:56:16.178152 DQ_CA_OPEN = 0
7158 13:56:16.181512 DQ_SEMI_OPEN = 0
7159 13:56:16.184623 CA_SEMI_OPEN = 0
7160 13:56:16.188225 CA_FULL_RATE = 0
7161 13:56:16.191450 DQ_CKDIV4_EN = 0
7162 13:56:16.191527 CA_CKDIV4_EN = 0
7163 13:56:16.194797 CA_PREDIV_EN = 0
7164 13:56:16.198200 PH8_DLY = 12
7165 13:56:16.201473 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7166 13:56:16.204883 DQ_AAMCK_DIV = 4
7167 13:56:16.208189 CA_AAMCK_DIV = 4
7168 13:56:16.208267 CA_ADMCK_DIV = 4
7169 13:56:16.211450 DQ_TRACK_CA_EN = 0
7170 13:56:16.214664 CA_PICK = 1600
7171 13:56:16.218357 CA_MCKIO = 1600
7172 13:56:16.221254 MCKIO_SEMI = 0
7173 13:56:16.224668 PLL_FREQ = 3068
7174 13:56:16.228012 DQ_UI_PI_RATIO = 32
7175 13:56:16.231322 CA_UI_PI_RATIO = 0
7176 13:56:16.234578 ===================================
7177 13:56:16.237728 ===================================
7178 13:56:16.237816 memory_type:LPDDR4
7179 13:56:16.241292 GP_NUM : 10
7180 13:56:16.241399 SRAM_EN : 1
7181 13:56:16.244848 MD32_EN : 0
7182 13:56:16.248120 ===================================
7183 13:56:16.251283 [ANA_INIT] >>>>>>>>>>>>>>
7184 13:56:16.254324 <<<<<< [CONFIGURE PHASE]: ANA_TX
7185 13:56:16.258078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7186 13:56:16.261358 ===================================
7187 13:56:16.261449 data_rate = 3200,PCW = 0X7600
7188 13:56:16.264648 ===================================
7189 13:56:16.271025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7190 13:56:16.274342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7191 13:56:16.280956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 13:56:16.284790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7193 13:56:16.287939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7194 13:56:16.290914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7195 13:56:16.294111 [ANA_INIT] flow start
7196 13:56:16.297819 [ANA_INIT] PLL >>>>>>>>
7197 13:56:16.297915 [ANA_INIT] PLL <<<<<<<<
7198 13:56:16.301174 [ANA_INIT] MIDPI >>>>>>>>
7199 13:56:16.304595 [ANA_INIT] MIDPI <<<<<<<<
7200 13:56:16.304731 [ANA_INIT] DLL >>>>>>>>
7201 13:56:16.307337 [ANA_INIT] DLL <<<<<<<<
7202 13:56:16.310642 [ANA_INIT] flow end
7203 13:56:16.314157 ============ LP4 DIFF to SE enter ============
7204 13:56:16.317413 ============ LP4 DIFF to SE exit ============
7205 13:56:16.320817 [ANA_INIT] <<<<<<<<<<<<<
7206 13:56:16.323973 [Flow] Enable top DCM control >>>>>
7207 13:56:16.327216 [Flow] Enable top DCM control <<<<<
7208 13:56:16.331019 Enable DLL master slave shuffle
7209 13:56:16.333941 ==============================================================
7210 13:56:16.337411 Gating Mode config
7211 13:56:16.343770 ==============================================================
7212 13:56:16.343861 Config description:
7213 13:56:16.353725 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7214 13:56:16.360530 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7215 13:56:16.366959 SELPH_MODE 0: By rank 1: By Phase
7216 13:56:16.370686 ==============================================================
7217 13:56:16.373983 GAT_TRACK_EN = 1
7218 13:56:16.377308 RX_GATING_MODE = 2
7219 13:56:16.380447 RX_GATING_TRACK_MODE = 2
7220 13:56:16.383644 SELPH_MODE = 1
7221 13:56:16.386866 PICG_EARLY_EN = 1
7222 13:56:16.390797 VALID_LAT_VALUE = 1
7223 13:56:16.393908 ==============================================================
7224 13:56:16.397219 Enter into Gating configuration >>>>
7225 13:56:16.400437 Exit from Gating configuration <<<<
7226 13:56:16.403964 Enter into DVFS_PRE_config >>>>>
7227 13:56:16.417149 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7228 13:56:16.420576 Exit from DVFS_PRE_config <<<<<
7229 13:56:16.420671 Enter into PICG configuration >>>>
7230 13:56:16.423930 Exit from PICG configuration <<<<
7231 13:56:16.427256 [RX_INPUT] configuration >>>>>
7232 13:56:16.429940 [RX_INPUT] configuration <<<<<
7233 13:56:16.436796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7234 13:56:16.439936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7235 13:56:16.447022 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 13:56:16.453218 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 13:56:16.460278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7238 13:56:16.466901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7239 13:56:16.470193 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7240 13:56:16.473436 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7241 13:56:16.476639 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7242 13:56:16.483177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7243 13:56:16.486774 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7244 13:56:16.490174 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7245 13:56:16.493301 ===================================
7246 13:56:16.496156 LPDDR4 DRAM CONFIGURATION
7247 13:56:16.499826 ===================================
7248 13:56:16.503189 EX_ROW_EN[0] = 0x0
7249 13:56:16.503268 EX_ROW_EN[1] = 0x0
7250 13:56:16.506686 LP4Y_EN = 0x0
7251 13:56:16.506758 WORK_FSP = 0x1
7252 13:56:16.509404 WL = 0x5
7253 13:56:16.509486 RL = 0x5
7254 13:56:16.512998 BL = 0x2
7255 13:56:16.513110 RPST = 0x0
7256 13:56:16.516621 RD_PRE = 0x0
7257 13:56:16.516715 WR_PRE = 0x1
7258 13:56:16.519684 WR_PST = 0x1
7259 13:56:16.519786 DBI_WR = 0x0
7260 13:56:16.522985 DBI_RD = 0x0
7261 13:56:16.523061 OTF = 0x1
7262 13:56:16.526231 ===================================
7263 13:56:16.532956 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7264 13:56:16.536451 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7265 13:56:16.539773 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7266 13:56:16.543134 ===================================
7267 13:56:16.545836 LPDDR4 DRAM CONFIGURATION
7268 13:56:16.549275 ===================================
7269 13:56:16.553071 EX_ROW_EN[0] = 0x10
7270 13:56:16.553149 EX_ROW_EN[1] = 0x0
7271 13:56:16.556194 LP4Y_EN = 0x0
7272 13:56:16.556305 WORK_FSP = 0x1
7273 13:56:16.559765 WL = 0x5
7274 13:56:16.559870 RL = 0x5
7275 13:56:16.562870 BL = 0x2
7276 13:56:16.562977 RPST = 0x0
7277 13:56:16.565982 RD_PRE = 0x0
7278 13:56:16.566065 WR_PRE = 0x1
7279 13:56:16.569461 WR_PST = 0x1
7280 13:56:16.569539 DBI_WR = 0x0
7281 13:56:16.573175 DBI_RD = 0x0
7282 13:56:16.573260 OTF = 0x1
7283 13:56:16.576474 ===================================
7284 13:56:16.582958 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7285 13:56:16.583067 ==
7286 13:56:16.586242 Dram Type= 6, Freq= 0, CH_0, rank 0
7287 13:56:16.589665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7288 13:56:16.592971 ==
7289 13:56:16.593050 [Duty_Offset_Calibration]
7290 13:56:16.596303 B0:2 B1:1 CA:1
7291 13:56:16.596415
7292 13:56:16.599666 [DutyScan_Calibration_Flow] k_type=0
7293 13:56:16.608340
7294 13:56:16.608453 ==CLK 0==
7295 13:56:16.611992 Final CLK duty delay cell = 0
7296 13:56:16.615049 [0] MAX Duty = 5156%(X100), DQS PI = 22
7297 13:56:16.618474 [0] MIN Duty = 4907%(X100), DQS PI = 0
7298 13:56:16.618579 [0] AVG Duty = 5031%(X100)
7299 13:56:16.621882
7300 13:56:16.624718 CH0 CLK Duty spec in!! Max-Min= 249%
7301 13:56:16.628522 [DutyScan_Calibration_Flow] ====Done====
7302 13:56:16.628607
7303 13:56:16.631612 [DutyScan_Calibration_Flow] k_type=1
7304 13:56:16.647694
7305 13:56:16.647780 ==DQS 0 ==
7306 13:56:16.651067 Final DQS duty delay cell = -4
7307 13:56:16.654456 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7308 13:56:16.657166 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7309 13:56:16.660482 [-4] AVG Duty = 4906%(X100)
7310 13:56:16.660555
7311 13:56:16.660617 ==DQS 1 ==
7312 13:56:16.664406 Final DQS duty delay cell = 0
7313 13:56:16.667589 [0] MAX Duty = 5218%(X100), DQS PI = 22
7314 13:56:16.670685 [0] MIN Duty = 5031%(X100), DQS PI = 52
7315 13:56:16.673700 [0] AVG Duty = 5124%(X100)
7316 13:56:16.673777
7317 13:56:16.677535 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7318 13:56:16.677617
7319 13:56:16.680692 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7320 13:56:16.683892 [DutyScan_Calibration_Flow] ====Done====
7321 13:56:16.683969
7322 13:56:16.687081 [DutyScan_Calibration_Flow] k_type=3
7323 13:56:16.703934
7324 13:56:16.704021 ==DQM 0 ==
7325 13:56:16.707312 Final DQM duty delay cell = 0
7326 13:56:16.711203 [0] MAX Duty = 5218%(X100), DQS PI = 32
7327 13:56:16.714356 [0] MIN Duty = 4875%(X100), DQS PI = 60
7328 13:56:16.714434 [0] AVG Duty = 5046%(X100)
7329 13:56:16.714506
7330 13:56:16.717661 ==DQM 1 ==
7331 13:56:16.720939 Final DQM duty delay cell = -4
7332 13:56:16.724680 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7333 13:56:16.727978 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7334 13:56:16.731194 [-4] AVG Duty = 4891%(X100)
7335 13:56:16.731282
7336 13:56:16.734581 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7337 13:56:16.734669
7338 13:56:16.738023 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7339 13:56:16.740695 [DutyScan_Calibration_Flow] ====Done====
7340 13:56:16.740769
7341 13:56:16.744405 [DutyScan_Calibration_Flow] k_type=2
7342 13:56:16.761672
7343 13:56:16.761815 ==DQ 0 ==
7344 13:56:16.764821 Final DQ duty delay cell = 0
7345 13:56:16.768143 [0] MAX Duty = 5062%(X100), DQS PI = 24
7346 13:56:16.771390 [0] MIN Duty = 4907%(X100), DQS PI = 0
7347 13:56:16.771469 [0] AVG Duty = 4984%(X100)
7348 13:56:16.771532
7349 13:56:16.775111 ==DQ 1 ==
7350 13:56:16.778165 Final DQ duty delay cell = 0
7351 13:56:16.781320 [0] MAX Duty = 5125%(X100), DQS PI = 6
7352 13:56:16.784659 [0] MIN Duty = 4907%(X100), DQS PI = 34
7353 13:56:16.784736 [0] AVG Duty = 5016%(X100)
7354 13:56:16.784802
7355 13:56:16.788589 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7356 13:56:16.788664
7357 13:56:16.794866 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7358 13:56:16.798089 [DutyScan_Calibration_Flow] ====Done====
7359 13:56:16.798164 ==
7360 13:56:16.801460 Dram Type= 6, Freq= 0, CH_1, rank 0
7361 13:56:16.804971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7362 13:56:16.805047 ==
7363 13:56:16.808351 [Duty_Offset_Calibration]
7364 13:56:16.808422 B0:1 B1:0 CA:0
7365 13:56:16.808483
7366 13:56:16.811586 [DutyScan_Calibration_Flow] k_type=0
7367 13:56:16.820900
7368 13:56:16.821016 ==CLK 0==
7369 13:56:16.824142 Final CLK duty delay cell = -4
7370 13:56:16.827382 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7371 13:56:16.830585 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7372 13:56:16.834417 [-4] AVG Duty = 4906%(X100)
7373 13:56:16.834490
7374 13:56:16.837769 CH1 CLK Duty spec in!! Max-Min= 125%
7375 13:56:16.840595 [DutyScan_Calibration_Flow] ====Done====
7376 13:56:16.840671
7377 13:56:16.843893 [DutyScan_Calibration_Flow] k_type=1
7378 13:56:16.861073
7379 13:56:16.861152 ==DQS 0 ==
7380 13:56:16.864243 Final DQS duty delay cell = 0
7381 13:56:16.867401 [0] MAX Duty = 5094%(X100), DQS PI = 20
7382 13:56:16.871039 [0] MIN Duty = 4844%(X100), DQS PI = 48
7383 13:56:16.873997 [0] AVG Duty = 4969%(X100)
7384 13:56:16.874107
7385 13:56:16.874173 ==DQS 1 ==
7386 13:56:16.877449 Final DQS duty delay cell = 0
7387 13:56:16.880770 [0] MAX Duty = 5249%(X100), DQS PI = 16
7388 13:56:16.884027 [0] MIN Duty = 4938%(X100), DQS PI = 10
7389 13:56:16.887281 [0] AVG Duty = 5093%(X100)
7390 13:56:16.887385
7391 13:56:16.890947 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7392 13:56:16.891052
7393 13:56:16.893969 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7394 13:56:16.897623 [DutyScan_Calibration_Flow] ====Done====
7395 13:56:16.897707
7396 13:56:16.900481 [DutyScan_Calibration_Flow] k_type=3
7397 13:56:16.917894
7398 13:56:16.917984 ==DQM 0 ==
7399 13:56:16.921204 Final DQM duty delay cell = 0
7400 13:56:16.924451 [0] MAX Duty = 5187%(X100), DQS PI = 10
7401 13:56:16.927756 [0] MIN Duty = 4969%(X100), DQS PI = 48
7402 13:56:16.930899 [0] AVG Duty = 5078%(X100)
7403 13:56:16.930978
7404 13:56:16.931052 ==DQM 1 ==
7405 13:56:16.934728 Final DQM duty delay cell = 0
7406 13:56:16.937940 [0] MAX Duty = 5093%(X100), DQS PI = 16
7407 13:56:16.941351 [0] MIN Duty = 4907%(X100), DQS PI = 50
7408 13:56:16.944087 [0] AVG Duty = 5000%(X100)
7409 13:56:16.944161
7410 13:56:16.947627 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7411 13:56:16.947715
7412 13:56:16.951028 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7413 13:56:16.954453 [DutyScan_Calibration_Flow] ====Done====
7414 13:56:16.954531
7415 13:56:16.957894 [DutyScan_Calibration_Flow] k_type=2
7416 13:56:16.973816
7417 13:56:16.973900 ==DQ 0 ==
7418 13:56:16.977251 Final DQ duty delay cell = -4
7419 13:56:16.980767 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7420 13:56:16.983982 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7421 13:56:16.987398 [-4] AVG Duty = 4953%(X100)
7422 13:56:16.987504
7423 13:56:16.987598 ==DQ 1 ==
7424 13:56:16.990749 Final DQ duty delay cell = 0
7425 13:56:16.994024 [0] MAX Duty = 5093%(X100), DQS PI = 16
7426 13:56:16.997310 [0] MIN Duty = 4938%(X100), DQS PI = 8
7427 13:56:16.997389 [0] AVG Duty = 5015%(X100)
7428 13:56:17.001022
7429 13:56:17.004401 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7430 13:56:17.004475
7431 13:56:17.007318 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7432 13:56:17.010356 [DutyScan_Calibration_Flow] ====Done====
7433 13:56:17.013973 nWR fixed to 30
7434 13:56:17.014050 [ModeRegInit_LP4] CH0 RK0
7435 13:56:17.017235 [ModeRegInit_LP4] CH0 RK1
7436 13:56:17.020379 [ModeRegInit_LP4] CH1 RK0
7437 13:56:17.023746 [ModeRegInit_LP4] CH1 RK1
7438 13:56:17.023859 match AC timing 5
7439 13:56:17.030322 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7440 13:56:17.034024 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7441 13:56:17.037276 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7442 13:56:17.043825 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7443 13:56:17.046889 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7444 13:56:17.047006 [MiockJmeterHQA]
7445 13:56:17.047102
7446 13:56:17.050439 [DramcMiockJmeter] u1RxGatingPI = 0
7447 13:56:17.054138 0 : 4363, 4138
7448 13:56:17.054249 4 : 4255, 4029
7449 13:56:17.057356 8 : 4253, 4027
7450 13:56:17.057469 12 : 4252, 4027
7451 13:56:17.057566 16 : 4252, 4027
7452 13:56:17.060134 20 : 4363, 4137
7453 13:56:17.060240 24 : 4361, 4137
7454 13:56:17.063475 28 : 4252, 4027
7455 13:56:17.063560 32 : 4252, 4027
7456 13:56:17.066839 36 : 4253, 4026
7457 13:56:17.066942 40 : 4252, 4027
7458 13:56:17.070354 44 : 4258, 4032
7459 13:56:17.070458 48 : 4250, 4026
7460 13:56:17.070550 52 : 4252, 4027
7461 13:56:17.073651 56 : 4363, 4140
7462 13:56:17.073734 60 : 4250, 4027
7463 13:56:17.076820 64 : 4253, 4029
7464 13:56:17.076904 68 : 4250, 4026
7465 13:56:17.080205 72 : 4360, 4138
7466 13:56:17.080313 76 : 4249, 4027
7467 13:56:17.083521 80 : 4250, 4026
7468 13:56:17.083603 84 : 4250, 4026
7469 13:56:17.083669 88 : 4250, 124
7470 13:56:17.086866 92 : 4250, 0
7471 13:56:17.086948 96 : 4252, 0
7472 13:56:17.087014 100 : 4363, 0
7473 13:56:17.090129 104 : 4363, 0
7474 13:56:17.090212 108 : 4249, 0
7475 13:56:17.093372 112 : 4252, 0
7476 13:56:17.093454 116 : 4255, 0
7477 13:56:17.093521 120 : 4250, 0
7478 13:56:17.096653 124 : 4250, 0
7479 13:56:17.096735 128 : 4253, 0
7480 13:56:17.100821 132 : 4253, 0
7481 13:56:17.100904 136 : 4360, 0
7482 13:56:17.100970 140 : 4250, 0
7483 13:56:17.103396 144 : 4250, 0
7484 13:56:17.103479 148 : 4251, 0
7485 13:56:17.106611 152 : 4361, 0
7486 13:56:17.106716 156 : 4250, 0
7487 13:56:17.106807 160 : 4249, 0
7488 13:56:17.109995 164 : 4250, 0
7489 13:56:17.110077 168 : 4253, 0
7490 13:56:17.113312 172 : 4250, 0
7491 13:56:17.113395 176 : 4250, 0
7492 13:56:17.113461 180 : 4250, 0
7493 13:56:17.116662 184 : 4253, 0
7494 13:56:17.116745 188 : 4360, 0
7495 13:56:17.116812 192 : 4250, 0
7496 13:56:17.119922 196 : 4250, 0
7497 13:56:17.120005 200 : 4249, 0
7498 13:56:17.123303 204 : 4360, 1203
7499 13:56:17.123386 208 : 4361, 4120
7500 13:56:17.126592 212 : 4253, 4027
7501 13:56:17.126675 216 : 4366, 4142
7502 13:56:17.129799 220 : 4250, 4026
7503 13:56:17.129881 224 : 4250, 4026
7504 13:56:17.133134 228 : 4250, 4027
7505 13:56:17.133217 232 : 4252, 4029
7506 13:56:17.133282 236 : 4250, 4027
7507 13:56:17.136263 240 : 4250, 4027
7508 13:56:17.136368 244 : 4250, 4027
7509 13:56:17.140159 248 : 4254, 4032
7510 13:56:17.140268 252 : 4250, 4027
7511 13:56:17.143147 256 : 4366, 4140
7512 13:56:17.143229 260 : 4361, 4137
7513 13:56:17.146706 264 : 4250, 4027
7514 13:56:17.146803 268 : 4249, 4027
7515 13:56:17.150262 272 : 4253, 4026
7516 13:56:17.150344 276 : 4250, 4026
7517 13:56:17.152979 280 : 4249, 4027
7518 13:56:17.153061 284 : 4252, 4029
7519 13:56:17.156312 288 : 4250, 4026
7520 13:56:17.156469 292 : 4250, 4026
7521 13:56:17.156568 296 : 4250, 4027
7522 13:56:17.159770 300 : 4252, 4029
7523 13:56:17.159852 304 : 4250, 4027
7524 13:56:17.163333 308 : 4361, 4105
7525 13:56:17.163423 312 : 4360, 2245
7526 13:56:17.166458 316 : 4248, 5
7527 13:56:17.166591
7528 13:56:17.166694 MIOCK jitter meter ch=0
7529 13:56:17.166793
7530 13:56:17.169725 1T = (316-88) = 228 dly cells
7531 13:56:17.176132 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7532 13:56:17.176244 ==
7533 13:56:17.179624 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 13:56:17.182885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 13:56:17.182969 ==
7536 13:56:17.190084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 13:56:17.193293 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 13:56:17.199836 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 13:56:17.203248 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 13:56:17.212884 [CA 0] Center 43 (13~74) winsize 62
7541 13:56:17.216245 [CA 1] Center 43 (12~74) winsize 63
7542 13:56:17.219658 [CA 2] Center 38 (9~68) winsize 60
7543 13:56:17.222900 [CA 3] Center 38 (8~68) winsize 61
7544 13:56:17.226249 [CA 4] Center 37 (7~67) winsize 61
7545 13:56:17.229610 [CA 5] Center 35 (6~65) winsize 60
7546 13:56:17.229692
7547 13:56:17.232921 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7548 13:56:17.233003
7549 13:56:17.236213 [CATrainingPosCal] consider 1 rank data
7550 13:56:17.239448 u2DelayCellTimex100 = 285/100 ps
7551 13:56:17.242874 CA0 delay=43 (13~74),Diff = 8 PI (27 cell)
7552 13:56:17.249400 CA1 delay=43 (12~74),Diff = 8 PI (27 cell)
7553 13:56:17.252689 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7554 13:56:17.255948 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7555 13:56:17.259249 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7556 13:56:17.263070 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7557 13:56:17.263152
7558 13:56:17.266020 CA PerBit enable=1, Macro0, CA PI delay=35
7559 13:56:17.266103
7560 13:56:17.269719 [CBTSetCACLKResult] CA Dly = 35
7561 13:56:17.272762 CS Dly: 9 (0~40)
7562 13:56:17.275987 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 13:56:17.279194 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 13:56:17.279276 ==
7565 13:56:17.283001 Dram Type= 6, Freq= 0, CH_0, rank 1
7566 13:56:17.286178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 13:56:17.289303 ==
7568 13:56:17.292432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7569 13:56:17.295833 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7570 13:56:17.302735 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7571 13:56:17.308995 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7572 13:56:17.316620 [CA 0] Center 43 (13~73) winsize 61
7573 13:56:17.319929 [CA 1] Center 43 (13~73) winsize 61
7574 13:56:17.323190 [CA 2] Center 38 (8~68) winsize 61
7575 13:56:17.326587 [CA 3] Center 38 (8~68) winsize 61
7576 13:56:17.329829 [CA 4] Center 36 (6~66) winsize 61
7577 13:56:17.332579 [CA 5] Center 35 (6~65) winsize 60
7578 13:56:17.332658
7579 13:56:17.335985 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7580 13:56:17.336061
7581 13:56:17.339343 [CATrainingPosCal] consider 2 rank data
7582 13:56:17.343214 u2DelayCellTimex100 = 285/100 ps
7583 13:56:17.349208 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7584 13:56:17.352654 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7585 13:56:17.355992 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7586 13:56:17.359354 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7587 13:56:17.362601 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7588 13:56:17.366039 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7589 13:56:17.366122
7590 13:56:17.369213 CA PerBit enable=1, Macro0, CA PI delay=35
7591 13:56:17.369297
7592 13:56:17.373033 [CBTSetCACLKResult] CA Dly = 35
7593 13:56:17.376095 CS Dly: 9 (0~41)
7594 13:56:17.379046 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7595 13:56:17.382783 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7596 13:56:17.382884
7597 13:56:17.385976 ----->DramcWriteLeveling(PI) begin...
7598 13:56:17.386077 ==
7599 13:56:17.389276 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 13:56:17.395975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 13:56:17.396133 ==
7602 13:56:17.399398 Write leveling (Byte 0): 36 => 36
7603 13:56:17.399497 Write leveling (Byte 1): 28 => 28
7604 13:56:17.402722 DramcWriteLeveling(PI) end<-----
7605 13:56:17.402822
7606 13:56:17.402919 ==
7607 13:56:17.405921 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 13:56:17.412659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 13:56:17.412774 ==
7610 13:56:17.415824 [Gating] SW mode calibration
7611 13:56:17.422371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7612 13:56:17.426213 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7613 13:56:17.432804 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7614 13:56:17.436077 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7615 13:56:17.439159 1 4 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7616 13:56:17.445764 1 4 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7617 13:56:17.449018 1 4 16 | B1->B0 | 2626 3636 | 0 0 | (1 1) (0 0)
7618 13:56:17.452377 1 4 20 | B1->B0 | 3434 3635 | 0 1 | (0 0) (0 0)
7619 13:56:17.459237 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7620 13:56:17.462388 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7621 13:56:17.465811 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7622 13:56:17.472451 1 5 4 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)
7623 13:56:17.475771 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 1)
7624 13:56:17.479202 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (0 0)
7625 13:56:17.482420 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
7626 13:56:17.488711 1 5 20 | B1->B0 | 2323 2d2c | 0 1 | (1 0) (0 0)
7627 13:56:17.492142 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7628 13:56:17.495845 1 5 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7629 13:56:17.502298 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7630 13:56:17.505658 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7631 13:56:17.508972 1 6 8 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
7632 13:56:17.515717 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7633 13:56:17.518999 1 6 16 | B1->B0 | 2727 4645 | 0 1 | (0 0) (0 0)
7634 13:56:17.522364 1 6 20 | B1->B0 | 4444 4645 | 0 1 | (0 0) (0 0)
7635 13:56:17.529132 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 13:56:17.532363 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 13:56:17.535468 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 13:56:17.542392 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 13:56:17.545370 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 13:56:17.548840 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7641 13:56:17.555626 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7642 13:56:17.558589 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7643 13:56:17.561832 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 13:56:17.568458 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 13:56:17.571975 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 13:56:17.575272 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 13:56:17.581877 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 13:56:17.585122 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 13:56:17.588464 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 13:56:17.595187 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 13:56:17.598968 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 13:56:17.601969 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 13:56:17.608612 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 13:56:17.612063 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 13:56:17.615464 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 13:56:17.618850 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7657 13:56:17.625410 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7658 13:56:17.628620 Total UI for P1: 0, mck2ui 16
7659 13:56:17.631935 best dqsien dly found for B0: ( 1, 9, 12)
7660 13:56:17.635377 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 13:56:17.638594 Total UI for P1: 0, mck2ui 16
7662 13:56:17.641963 best dqsien dly found for B1: ( 1, 9, 16)
7663 13:56:17.645338 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7664 13:56:17.648732 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7665 13:56:17.648809
7666 13:56:17.652020 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7667 13:56:17.655352 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7668 13:56:17.658564 [Gating] SW calibration Done
7669 13:56:17.658654 ==
7670 13:56:17.661703 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 13:56:17.668730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 13:56:17.668814 ==
7673 13:56:17.668889 RX Vref Scan: 0
7674 13:56:17.668954
7675 13:56:17.671902 RX Vref 0 -> 0, step: 1
7676 13:56:17.671988
7677 13:56:17.675009 RX Delay 0 -> 252, step: 8
7678 13:56:17.678853 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7679 13:56:17.681829 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7680 13:56:17.684957 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7681 13:56:17.688107 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7682 13:56:17.694836 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7683 13:56:17.698310 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7684 13:56:17.701780 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7685 13:56:17.705026 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7686 13:56:17.708357 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7687 13:56:17.715091 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7688 13:56:17.718117 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7689 13:56:17.721926 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7690 13:56:17.724897 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7691 13:56:17.728243 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7692 13:56:17.734890 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7693 13:56:17.738414 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7694 13:56:17.738490 ==
7695 13:56:17.741620 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 13:56:17.744861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 13:56:17.744942 ==
7698 13:56:17.748200 DQS Delay:
7699 13:56:17.748305 DQS0 = 0, DQS1 = 0
7700 13:56:17.748387 DQM Delay:
7701 13:56:17.751470 DQM0 = 137, DQM1 = 129
7702 13:56:17.751550 DQ Delay:
7703 13:56:17.754843 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7704 13:56:17.758154 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7705 13:56:17.761430 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
7706 13:56:17.767789 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7707 13:56:17.767869
7708 13:56:17.767933
7709 13:56:17.767993 ==
7710 13:56:17.771254 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 13:56:17.774542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 13:56:17.774654 ==
7713 13:56:17.774753
7714 13:56:17.774816
7715 13:56:17.777986 TX Vref Scan disable
7716 13:56:17.778066 == TX Byte 0 ==
7717 13:56:17.784610 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7718 13:56:17.788322 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7719 13:56:17.788445 == TX Byte 1 ==
7720 13:56:17.795088 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7721 13:56:17.798346 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7722 13:56:17.798427 ==
7723 13:56:17.801411 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 13:56:17.804949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 13:56:17.805030 ==
7726 13:56:17.819461
7727 13:56:17.822918 TX Vref early break, caculate TX vref
7728 13:56:17.826093 TX Vref=16, minBit 3, minWin=22, winSum=378
7729 13:56:17.829490 TX Vref=18, minBit 1, minWin=23, winSum=386
7730 13:56:17.832307 TX Vref=20, minBit 0, minWin=24, winSum=397
7731 13:56:17.835577 TX Vref=22, minBit 0, minWin=24, winSum=407
7732 13:56:17.839098 TX Vref=24, minBit 7, minWin=24, winSum=411
7733 13:56:17.845881 TX Vref=26, minBit 1, minWin=25, winSum=423
7734 13:56:17.848967 TX Vref=28, minBit 1, minWin=24, winSum=421
7735 13:56:17.852359 TX Vref=30, minBit 2, minWin=24, winSum=411
7736 13:56:17.855688 TX Vref=32, minBit 6, minWin=23, winSum=401
7737 13:56:17.858992 TX Vref=34, minBit 6, minWin=23, winSum=395
7738 13:56:17.865641 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 26
7739 13:56:17.865722
7740 13:56:17.868968 Final TX Range 0 Vref 26
7741 13:56:17.869049
7742 13:56:17.869143 ==
7743 13:56:17.872390 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 13:56:17.875510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 13:56:17.875632 ==
7746 13:56:17.875793
7747 13:56:17.875901
7748 13:56:17.878918 TX Vref Scan disable
7749 13:56:17.885607 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7750 13:56:17.885688 == TX Byte 0 ==
7751 13:56:17.889016 u2DelayCellOfst[0]=13 cells (4 PI)
7752 13:56:17.892204 u2DelayCellOfst[1]=17 cells (5 PI)
7753 13:56:17.896069 u2DelayCellOfst[2]=13 cells (4 PI)
7754 13:56:17.898781 u2DelayCellOfst[3]=10 cells (3 PI)
7755 13:56:17.902103 u2DelayCellOfst[4]=13 cells (4 PI)
7756 13:56:17.905504 u2DelayCellOfst[5]=0 cells (0 PI)
7757 13:56:17.908888 u2DelayCellOfst[6]=20 cells (6 PI)
7758 13:56:17.912150 u2DelayCellOfst[7]=20 cells (6 PI)
7759 13:56:17.915885 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7760 13:56:17.918806 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7761 13:56:17.922031 == TX Byte 1 ==
7762 13:56:17.922189 u2DelayCellOfst[8]=0 cells (0 PI)
7763 13:56:17.925447 u2DelayCellOfst[9]=0 cells (0 PI)
7764 13:56:17.928801 u2DelayCellOfst[10]=6 cells (2 PI)
7765 13:56:17.932444 u2DelayCellOfst[11]=3 cells (1 PI)
7766 13:56:17.935538 u2DelayCellOfst[12]=13 cells (4 PI)
7767 13:56:17.938777 u2DelayCellOfst[13]=10 cells (3 PI)
7768 13:56:17.942366 u2DelayCellOfst[14]=13 cells (4 PI)
7769 13:56:17.945518 u2DelayCellOfst[15]=10 cells (3 PI)
7770 13:56:17.948824 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7771 13:56:17.955548 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7772 13:56:17.955658 DramC Write-DBI on
7773 13:56:17.955724 ==
7774 13:56:17.958778 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 13:56:17.962013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 13:56:17.965279 ==
7777 13:56:17.965357
7778 13:56:17.965420
7779 13:56:17.965478 TX Vref Scan disable
7780 13:56:17.968656 == TX Byte 0 ==
7781 13:56:17.972013 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7782 13:56:17.975411 == TX Byte 1 ==
7783 13:56:17.978763 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7784 13:56:17.981927 DramC Write-DBI off
7785 13:56:17.982009
7786 13:56:17.982073 [DATLAT]
7787 13:56:17.982150 Freq=1600, CH0 RK0
7788 13:56:17.982223
7789 13:56:17.985381 DATLAT Default: 0xf
7790 13:56:17.985462 0, 0xFFFF, sum = 0
7791 13:56:17.988687 1, 0xFFFF, sum = 0
7792 13:56:17.992126 2, 0xFFFF, sum = 0
7793 13:56:17.992237 3, 0xFFFF, sum = 0
7794 13:56:17.995556 4, 0xFFFF, sum = 0
7795 13:56:17.995638 5, 0xFFFF, sum = 0
7796 13:56:17.998827 6, 0xFFFF, sum = 0
7797 13:56:17.998909 7, 0xFFFF, sum = 0
7798 13:56:18.001881 8, 0xFFFF, sum = 0
7799 13:56:18.001988 9, 0xFFFF, sum = 0
7800 13:56:18.005247 10, 0xFFFF, sum = 0
7801 13:56:18.005332 11, 0xFFFF, sum = 0
7802 13:56:18.008737 12, 0xFFFF, sum = 0
7803 13:56:18.008818 13, 0xFFFF, sum = 0
7804 13:56:18.012043 14, 0x0, sum = 1
7805 13:56:18.012151 15, 0x0, sum = 2
7806 13:56:18.015449 16, 0x0, sum = 3
7807 13:56:18.015557 17, 0x0, sum = 4
7808 13:56:18.018811 best_step = 15
7809 13:56:18.018917
7810 13:56:18.019008 ==
7811 13:56:18.022002 Dram Type= 6, Freq= 0, CH_0, rank 0
7812 13:56:18.025150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7813 13:56:18.025248 ==
7814 13:56:18.028889 RX Vref Scan: 1
7815 13:56:18.028970
7816 13:56:18.029040 Set Vref Range= 24 -> 127
7817 13:56:18.029180
7818 13:56:18.031958 RX Vref 24 -> 127, step: 1
7819 13:56:18.032053
7820 13:56:18.035294 RX Delay 19 -> 252, step: 4
7821 13:56:18.035379
7822 13:56:18.038734 Set Vref, RX VrefLevel [Byte0]: 24
7823 13:56:18.041933 [Byte1]: 24
7824 13:56:18.042016
7825 13:56:18.045084 Set Vref, RX VrefLevel [Byte0]: 25
7826 13:56:18.048243 [Byte1]: 25
7827 13:56:18.048345
7828 13:56:18.051656 Set Vref, RX VrefLevel [Byte0]: 26
7829 13:56:18.055055 [Byte1]: 26
7830 13:56:18.059269
7831 13:56:18.059352 Set Vref, RX VrefLevel [Byte0]: 27
7832 13:56:18.062660 [Byte1]: 27
7833 13:56:18.066683
7834 13:56:18.066767 Set Vref, RX VrefLevel [Byte0]: 28
7835 13:56:18.069900 [Byte1]: 28
7836 13:56:18.074229
7837 13:56:18.074312 Set Vref, RX VrefLevel [Byte0]: 29
7838 13:56:18.077328 [Byte1]: 29
7839 13:56:18.081887
7840 13:56:18.081970 Set Vref, RX VrefLevel [Byte0]: 30
7841 13:56:18.084993 [Byte1]: 30
7842 13:56:18.089232
7843 13:56:18.089314 Set Vref, RX VrefLevel [Byte0]: 31
7844 13:56:18.092427 [Byte1]: 31
7845 13:56:18.097000
7846 13:56:18.097082 Set Vref, RX VrefLevel [Byte0]: 32
7847 13:56:18.100376 [Byte1]: 32
7848 13:56:18.104870
7849 13:56:18.104952 Set Vref, RX VrefLevel [Byte0]: 33
7850 13:56:18.107938 [Byte1]: 33
7851 13:56:18.111806
7852 13:56:18.111886 Set Vref, RX VrefLevel [Byte0]: 34
7853 13:56:18.115451 [Byte1]: 34
7854 13:56:18.119388
7855 13:56:18.119465 Set Vref, RX VrefLevel [Byte0]: 35
7856 13:56:18.122651 [Byte1]: 35
7857 13:56:18.127242
7858 13:56:18.127318 Set Vref, RX VrefLevel [Byte0]: 36
7859 13:56:18.130301 [Byte1]: 36
7860 13:56:18.134687
7861 13:56:18.134772 Set Vref, RX VrefLevel [Byte0]: 37
7862 13:56:18.138367 [Byte1]: 37
7863 13:56:18.142351
7864 13:56:18.142443 Set Vref, RX VrefLevel [Byte0]: 38
7865 13:56:18.145729 [Byte1]: 38
7866 13:56:18.149734
7867 13:56:18.149843 Set Vref, RX VrefLevel [Byte0]: 39
7868 13:56:18.152954 [Byte1]: 39
7869 13:56:18.157692
7870 13:56:18.157781 Set Vref, RX VrefLevel [Byte0]: 40
7871 13:56:18.160852 [Byte1]: 40
7872 13:56:18.165148
7873 13:56:18.165236 Set Vref, RX VrefLevel [Byte0]: 41
7874 13:56:18.168579 [Byte1]: 41
7875 13:56:18.172448
7876 13:56:18.172539 Set Vref, RX VrefLevel [Byte0]: 42
7877 13:56:18.176283 [Byte1]: 42
7878 13:56:18.180263
7879 13:56:18.180369 Set Vref, RX VrefLevel [Byte0]: 43
7880 13:56:18.183705 [Byte1]: 43
7881 13:56:18.187562
7882 13:56:18.187637 Set Vref, RX VrefLevel [Byte0]: 44
7883 13:56:18.191384 [Byte1]: 44
7884 13:56:18.195267
7885 13:56:18.195344 Set Vref, RX VrefLevel [Byte0]: 45
7886 13:56:18.198831 [Byte1]: 45
7887 13:56:18.202865
7888 13:56:18.202941 Set Vref, RX VrefLevel [Byte0]: 46
7889 13:56:18.206184 [Byte1]: 46
7890 13:56:18.210734
7891 13:56:18.210819 Set Vref, RX VrefLevel [Byte0]: 47
7892 13:56:18.213961 [Byte1]: 47
7893 13:56:18.218434
7894 13:56:18.218519 Set Vref, RX VrefLevel [Byte0]: 48
7895 13:56:18.221160 [Byte1]: 48
7896 13:56:18.225742
7897 13:56:18.225831 Set Vref, RX VrefLevel [Byte0]: 49
7898 13:56:18.229153 [Byte1]: 49
7899 13:56:18.233124
7900 13:56:18.233206 Set Vref, RX VrefLevel [Byte0]: 50
7901 13:56:18.236494 [Byte1]: 50
7902 13:56:18.241024
7903 13:56:18.241102 Set Vref, RX VrefLevel [Byte0]: 51
7904 13:56:18.244316 [Byte1]: 51
7905 13:56:18.248671
7906 13:56:18.248757 Set Vref, RX VrefLevel [Byte0]: 52
7907 13:56:18.251769 [Byte1]: 52
7908 13:56:18.256181
7909 13:56:18.256258 Set Vref, RX VrefLevel [Byte0]: 53
7910 13:56:18.259625 [Byte1]: 53
7911 13:56:18.263625
7912 13:56:18.263707 Set Vref, RX VrefLevel [Byte0]: 54
7913 13:56:18.266891 [Byte1]: 54
7914 13:56:18.270989
7915 13:56:18.271074 Set Vref, RX VrefLevel [Byte0]: 55
7916 13:56:18.274632 [Byte1]: 55
7917 13:56:18.279299
7918 13:56:18.279388 Set Vref, RX VrefLevel [Byte0]: 56
7919 13:56:18.281920 [Byte1]: 56
7920 13:56:18.286322
7921 13:56:18.286400 Set Vref, RX VrefLevel [Byte0]: 57
7922 13:56:18.289570 [Byte1]: 57
7923 13:56:18.293629
7924 13:56:18.293736 Set Vref, RX VrefLevel [Byte0]: 58
7925 13:56:18.296952 [Byte1]: 58
7926 13:56:18.301665
7927 13:56:18.301744 Set Vref, RX VrefLevel [Byte0]: 59
7928 13:56:18.305066 [Byte1]: 59
7929 13:56:18.308882
7930 13:56:18.308966 Set Vref, RX VrefLevel [Byte0]: 60
7931 13:56:18.312673 [Byte1]: 60
7932 13:56:18.316790
7933 13:56:18.316868 Set Vref, RX VrefLevel [Byte0]: 61
7934 13:56:18.319655 [Byte1]: 61
7935 13:56:18.323965
7936 13:56:18.324053 Set Vref, RX VrefLevel [Byte0]: 62
7937 13:56:18.327166 [Byte1]: 62
7938 13:56:18.331443
7939 13:56:18.331523 Set Vref, RX VrefLevel [Byte0]: 63
7940 13:56:18.334780 [Byte1]: 63
7941 13:56:18.339563
7942 13:56:18.339647 Set Vref, RX VrefLevel [Byte0]: 64
7943 13:56:18.342799 [Byte1]: 64
7944 13:56:18.347282
7945 13:56:18.347395 Set Vref, RX VrefLevel [Byte0]: 65
7946 13:56:18.350377 [Byte1]: 65
7947 13:56:18.354125
7948 13:56:18.354201 Set Vref, RX VrefLevel [Byte0]: 66
7949 13:56:18.357816 [Byte1]: 66
7950 13:56:18.362228
7951 13:56:18.362313 Set Vref, RX VrefLevel [Byte0]: 67
7952 13:56:18.365658 [Byte1]: 67
7953 13:56:18.369587
7954 13:56:18.369671 Set Vref, RX VrefLevel [Byte0]: 68
7955 13:56:18.372959 [Byte1]: 68
7956 13:56:18.377036
7957 13:56:18.377124 Set Vref, RX VrefLevel [Byte0]: 69
7958 13:56:18.380262 [Byte1]: 69
7959 13:56:18.385127
7960 13:56:18.385205 Set Vref, RX VrefLevel [Byte0]: 70
7961 13:56:18.387799 [Byte1]: 70
7962 13:56:18.392481
7963 13:56:18.392555 Set Vref, RX VrefLevel [Byte0]: 71
7964 13:56:18.395589 [Byte1]: 71
7965 13:56:18.400107
7966 13:56:18.400226 Set Vref, RX VrefLevel [Byte0]: 72
7967 13:56:18.403053 [Byte1]: 72
7968 13:56:18.407604
7969 13:56:18.407684 Set Vref, RX VrefLevel [Byte0]: 73
7970 13:56:18.410702 [Byte1]: 73
7971 13:56:18.415218
7972 13:56:18.415304 Set Vref, RX VrefLevel [Byte0]: 74
7973 13:56:18.417958 [Byte1]: 74
7974 13:56:18.422594
7975 13:56:18.422676 Set Vref, RX VrefLevel [Byte0]: 75
7976 13:56:18.425941 [Byte1]: 75
7977 13:56:18.430379
7978 13:56:18.430459 Final RX Vref Byte 0 = 59 to rank0
7979 13:56:18.433561 Final RX Vref Byte 1 = 60 to rank0
7980 13:56:18.436496 Final RX Vref Byte 0 = 59 to rank1
7981 13:56:18.440019 Final RX Vref Byte 1 = 60 to rank1==
7982 13:56:18.443192 Dram Type= 6, Freq= 0, CH_0, rank 0
7983 13:56:18.450225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 13:56:18.450314 ==
7985 13:56:18.450383 DQS Delay:
7986 13:56:18.450451 DQS0 = 0, DQS1 = 0
7987 13:56:18.453564 DQM Delay:
7988 13:56:18.453642 DQM0 = 134, DQM1 = 127
7989 13:56:18.457167 DQ Delay:
7990 13:56:18.460339 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7991 13:56:18.463653 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
7992 13:56:18.466811 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7993 13:56:18.469885 DQ12 =134, DQ13 =132, DQ14 =138, DQ15 =134
7994 13:56:18.469970
7995 13:56:18.470038
7996 13:56:18.470100
7997 13:56:18.473167 [DramC_TX_OE_Calibration] TA2
7998 13:56:18.476458 Original DQ_B0 (3 6) =30, OEN = 27
7999 13:56:18.479947 Original DQ_B1 (3 6) =30, OEN = 27
8000 13:56:18.483144 24, 0x0, End_B0=24 End_B1=24
8001 13:56:18.483223 25, 0x0, End_B0=25 End_B1=25
8002 13:56:18.486497 26, 0x0, End_B0=26 End_B1=26
8003 13:56:18.489904 27, 0x0, End_B0=27 End_B1=27
8004 13:56:18.493259 28, 0x0, End_B0=28 End_B1=28
8005 13:56:18.496584 29, 0x0, End_B0=29 End_B1=29
8006 13:56:18.496669 30, 0x0, End_B0=30 End_B1=30
8007 13:56:18.499841 31, 0x5151, End_B0=30 End_B1=30
8008 13:56:18.503226 Byte0 end_step=30 best_step=27
8009 13:56:18.506627 Byte1 end_step=30 best_step=27
8010 13:56:18.509873 Byte0 TX OE(2T, 0.5T) = (3, 3)
8011 13:56:18.513011 Byte1 TX OE(2T, 0.5T) = (3, 3)
8012 13:56:18.513095
8013 13:56:18.513161
8014 13:56:18.519715 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8015 13:56:18.522939 CH0 RK0: MR19=303, MR18=2723
8016 13:56:18.529904 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
8017 13:56:18.529992
8018 13:56:18.532975 ----->DramcWriteLeveling(PI) begin...
8019 13:56:18.533052 ==
8020 13:56:18.536387 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 13:56:18.539620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 13:56:18.539694 ==
8023 13:56:18.542924 Write leveling (Byte 0): 35 => 35
8024 13:56:18.546192 Write leveling (Byte 1): 29 => 29
8025 13:56:18.549502 DramcWriteLeveling(PI) end<-----
8026 13:56:18.549577
8027 13:56:18.549648 ==
8028 13:56:18.553064 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 13:56:18.556125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 13:56:18.556219 ==
8031 13:56:18.559654 [Gating] SW mode calibration
8032 13:56:18.566260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8033 13:56:18.572763 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8034 13:56:18.576097 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8035 13:56:18.579648 1 4 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8036 13:56:18.585816 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8037 13:56:18.589375 1 4 12 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8038 13:56:18.592676 1 4 16 | B1->B0 | 2d2d 3a3a | 1 0 | (1 1) (0 0)
8039 13:56:18.599363 1 4 20 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
8040 13:56:18.602655 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8041 13:56:18.605917 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
8042 13:56:18.612644 1 5 0 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
8043 13:56:18.615889 1 5 4 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
8044 13:56:18.619175 1 5 8 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
8045 13:56:18.626459 1 5 12 | B1->B0 | 3434 3636 | 1 1 | (1 0) (1 0)
8046 13:56:18.629143 1 5 16 | B1->B0 | 3030 2d2c | 0 1 | (0 0) (0 1)
8047 13:56:18.632400 1 5 20 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
8048 13:56:18.639487 1 5 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8049 13:56:18.642349 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8050 13:56:18.645956 1 6 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8051 13:56:18.652577 1 6 4 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
8052 13:56:18.655991 1 6 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8053 13:56:18.659313 1 6 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
8054 13:56:18.666100 1 6 16 | B1->B0 | 3c3c 4545 | 0 1 | (0 0) (0 0)
8055 13:56:18.669249 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 13:56:18.672245 1 6 24 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
8057 13:56:18.679075 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8058 13:56:18.682334 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 13:56:18.685625 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 13:56:18.692389 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 13:56:18.695241 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 13:56:18.698664 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8063 13:56:18.705757 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8064 13:56:18.708893 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 13:56:18.712042 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 13:56:18.718831 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 13:56:18.722249 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 13:56:18.725570 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 13:56:18.731920 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 13:56:18.735280 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 13:56:18.738660 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 13:56:18.742114 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 13:56:18.748786 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 13:56:18.751798 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 13:56:18.755326 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 13:56:18.762162 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8077 13:56:18.765553 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8078 13:56:18.768881 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8079 13:56:18.771615 Total UI for P1: 0, mck2ui 16
8080 13:56:18.774931 best dqsien dly found for B0: ( 1, 9, 10)
8081 13:56:18.781575 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 13:56:18.781658 Total UI for P1: 0, mck2ui 16
8083 13:56:18.788789 best dqsien dly found for B1: ( 1, 9, 14)
8084 13:56:18.791807 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8085 13:56:18.795175 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8086 13:56:18.795284
8087 13:56:18.798453 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8088 13:56:18.801903 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8089 13:56:18.805063 [Gating] SW calibration Done
8090 13:56:18.805145 ==
8091 13:56:18.808708 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 13:56:18.811947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 13:56:18.812029 ==
8094 13:56:18.815129 RX Vref Scan: 0
8095 13:56:18.815211
8096 13:56:18.815276 RX Vref 0 -> 0, step: 1
8097 13:56:18.815338
8098 13:56:18.818359 RX Delay 0 -> 252, step: 8
8099 13:56:18.822045 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8100 13:56:18.828800 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8101 13:56:18.831809 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8102 13:56:18.835303 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8103 13:56:18.838721 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8104 13:56:18.842065 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8105 13:56:18.848703 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8106 13:56:18.852028 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8107 13:56:18.855336 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8108 13:56:18.858643 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8109 13:56:18.862043 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8110 13:56:18.868744 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8111 13:56:18.871890 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8112 13:56:18.875267 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8113 13:56:18.878663 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8114 13:56:18.881980 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8115 13:56:18.882061 ==
8116 13:56:18.885291 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 13:56:18.891916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 13:56:18.892005 ==
8119 13:56:18.892074 DQS Delay:
8120 13:56:18.895143 DQS0 = 0, DQS1 = 0
8121 13:56:18.895230 DQM Delay:
8122 13:56:18.898849 DQM0 = 136, DQM1 = 128
8123 13:56:18.898925 DQ Delay:
8124 13:56:18.902312 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8125 13:56:18.905735 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8126 13:56:18.908419 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8127 13:56:18.912195 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8128 13:56:18.912278
8129 13:56:18.912362
8130 13:56:18.912423 ==
8131 13:56:18.915407 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 13:56:18.921919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 13:56:18.922003 ==
8134 13:56:18.922109
8135 13:56:18.922214
8136 13:56:18.922312 TX Vref Scan disable
8137 13:56:18.925165 == TX Byte 0 ==
8138 13:56:18.928505 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8139 13:56:18.934963 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8140 13:56:18.935050 == TX Byte 1 ==
8141 13:56:18.938776 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8142 13:56:18.945430 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8143 13:56:18.945513 ==
8144 13:56:18.948637 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 13:56:18.951723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 13:56:18.951798 ==
8147 13:56:18.966015
8148 13:56:18.969463 TX Vref early break, caculate TX vref
8149 13:56:18.972770 TX Vref=16, minBit 1, minWin=22, winSum=388
8150 13:56:18.975736 TX Vref=18, minBit 3, minWin=23, winSum=398
8151 13:56:18.979322 TX Vref=20, minBit 0, minWin=24, winSum=404
8152 13:56:18.982639 TX Vref=22, minBit 1, minWin=24, winSum=412
8153 13:56:18.985992 TX Vref=24, minBit 3, minWin=25, winSum=421
8154 13:56:18.992777 TX Vref=26, minBit 0, minWin=25, winSum=423
8155 13:56:18.996145 TX Vref=28, minBit 1, minWin=25, winSum=423
8156 13:56:18.998918 TX Vref=30, minBit 0, minWin=25, winSum=417
8157 13:56:19.002170 TX Vref=32, minBit 2, minWin=24, winSum=408
8158 13:56:19.006045 TX Vref=34, minBit 1, minWin=24, winSum=402
8159 13:56:19.009271 TX Vref=36, minBit 1, minWin=23, winSum=395
8160 13:56:19.015824 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8161 13:56:19.015926
8162 13:56:19.019162 Final TX Range 0 Vref 26
8163 13:56:19.019246
8164 13:56:19.019318 ==
8165 13:56:19.022348 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 13:56:19.026071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 13:56:19.026178 ==
8168 13:56:19.026259
8169 13:56:19.026325
8170 13:56:19.029283 TX Vref Scan disable
8171 13:56:19.035947 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8172 13:56:19.036029 == TX Byte 0 ==
8173 13:56:19.039144 u2DelayCellOfst[0]=13 cells (4 PI)
8174 13:56:19.042316 u2DelayCellOfst[1]=13 cells (4 PI)
8175 13:56:19.045416 u2DelayCellOfst[2]=10 cells (3 PI)
8176 13:56:19.048787 u2DelayCellOfst[3]=6 cells (2 PI)
8177 13:56:19.052118 u2DelayCellOfst[4]=6 cells (2 PI)
8178 13:56:19.055295 u2DelayCellOfst[5]=0 cells (0 PI)
8179 13:56:19.058830 u2DelayCellOfst[6]=17 cells (5 PI)
8180 13:56:19.062003 u2DelayCellOfst[7]=17 cells (5 PI)
8181 13:56:19.065709 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8182 13:56:19.068824 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8183 13:56:19.072410 == TX Byte 1 ==
8184 13:56:19.075581 u2DelayCellOfst[8]=0 cells (0 PI)
8185 13:56:19.075666 u2DelayCellOfst[9]=0 cells (0 PI)
8186 13:56:19.078557 u2DelayCellOfst[10]=6 cells (2 PI)
8187 13:56:19.082409 u2DelayCellOfst[11]=3 cells (1 PI)
8188 13:56:19.085472 u2DelayCellOfst[12]=10 cells (3 PI)
8189 13:56:19.088673 u2DelayCellOfst[13]=10 cells (3 PI)
8190 13:56:19.092367 u2DelayCellOfst[14]=13 cells (4 PI)
8191 13:56:19.095687 u2DelayCellOfst[15]=10 cells (3 PI)
8192 13:56:19.098975 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8193 13:56:19.105776 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8194 13:56:19.105862 DramC Write-DBI on
8195 13:56:19.105933 ==
8196 13:56:19.109276 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 13:56:19.115345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 13:56:19.115434 ==
8199 13:56:19.115503
8200 13:56:19.115564
8201 13:56:19.115626 TX Vref Scan disable
8202 13:56:19.119030 == TX Byte 0 ==
8203 13:56:19.122863 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8204 13:56:19.125710 == TX Byte 1 ==
8205 13:56:19.129103 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8206 13:56:19.132777 DramC Write-DBI off
8207 13:56:19.132875
8208 13:56:19.132960 [DATLAT]
8209 13:56:19.133025 Freq=1600, CH0 RK1
8210 13:56:19.133086
8211 13:56:19.135960 DATLAT Default: 0xf
8212 13:56:19.136062 0, 0xFFFF, sum = 0
8213 13:56:19.139095 1, 0xFFFF, sum = 0
8214 13:56:19.142873 2, 0xFFFF, sum = 0
8215 13:56:19.142952 3, 0xFFFF, sum = 0
8216 13:56:19.145683 4, 0xFFFF, sum = 0
8217 13:56:19.145831 5, 0xFFFF, sum = 0
8218 13:56:19.148952 6, 0xFFFF, sum = 0
8219 13:56:19.149056 7, 0xFFFF, sum = 0
8220 13:56:19.152733 8, 0xFFFF, sum = 0
8221 13:56:19.152811 9, 0xFFFF, sum = 0
8222 13:56:19.156282 10, 0xFFFF, sum = 0
8223 13:56:19.156401 11, 0xFFFF, sum = 0
8224 13:56:19.159121 12, 0xFFFF, sum = 0
8225 13:56:19.159221 13, 0xFFFF, sum = 0
8226 13:56:19.162355 14, 0x0, sum = 1
8227 13:56:19.162433 15, 0x0, sum = 2
8228 13:56:19.165909 16, 0x0, sum = 3
8229 13:56:19.166012 17, 0x0, sum = 4
8230 13:56:19.169333 best_step = 15
8231 13:56:19.169407
8232 13:56:19.169480 ==
8233 13:56:19.172827 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 13:56:19.176238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 13:56:19.176351 ==
8236 13:56:19.176417 RX Vref Scan: 0
8237 13:56:19.176488
8238 13:56:19.179137 RX Vref 0 -> 0, step: 1
8239 13:56:19.179292
8240 13:56:19.182424 RX Delay 19 -> 252, step: 4
8241 13:56:19.185457 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8242 13:56:19.192041 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8243 13:56:19.195321 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8244 13:56:19.198970 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8245 13:56:19.202402 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8246 13:56:19.205528 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8247 13:56:19.211844 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8248 13:56:19.215218 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8249 13:56:19.218616 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8250 13:56:19.222026 iDelay=191, Bit 9, Center 114 (63 ~ 166) 104
8251 13:56:19.225400 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8252 13:56:19.232230 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8253 13:56:19.235665 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8254 13:56:19.238833 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8255 13:56:19.242000 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8256 13:56:19.245070 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8257 13:56:19.248929 ==
8258 13:56:19.252025 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 13:56:19.255019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 13:56:19.255093 ==
8261 13:56:19.255163 DQS Delay:
8262 13:56:19.258806 DQS0 = 0, DQS1 = 0
8263 13:56:19.258888 DQM Delay:
8264 13:56:19.261879 DQM0 = 135, DQM1 = 127
8265 13:56:19.261957 DQ Delay:
8266 13:56:19.265164 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8267 13:56:19.268466 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =142
8268 13:56:19.271700 DQ8 =118, DQ9 =114, DQ10 =128, DQ11 =118
8269 13:56:19.275033 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8270 13:56:19.275116
8271 13:56:19.275180
8272 13:56:19.275240
8273 13:56:19.278310 [DramC_TX_OE_Calibration] TA2
8274 13:56:19.281735 Original DQ_B0 (3 6) =30, OEN = 27
8275 13:56:19.285108 Original DQ_B1 (3 6) =30, OEN = 27
8276 13:56:19.288471 24, 0x0, End_B0=24 End_B1=24
8277 13:56:19.291852 25, 0x0, End_B0=25 End_B1=25
8278 13:56:19.291929 26, 0x0, End_B0=26 End_B1=26
8279 13:56:19.295123 27, 0x0, End_B0=27 End_B1=27
8280 13:56:19.298265 28, 0x0, End_B0=28 End_B1=28
8281 13:56:19.301825 29, 0x0, End_B0=29 End_B1=29
8282 13:56:19.305905 30, 0x0, End_B0=30 End_B1=30
8283 13:56:19.306011 31, 0x4141, End_B0=30 End_B1=30
8284 13:56:19.308411 Byte0 end_step=30 best_step=27
8285 13:56:19.311616 Byte1 end_step=30 best_step=27
8286 13:56:19.315369 Byte0 TX OE(2T, 0.5T) = (3, 3)
8287 13:56:19.318153 Byte1 TX OE(2T, 0.5T) = (3, 3)
8288 13:56:19.318225
8289 13:56:19.318288
8290 13:56:19.325135 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8291 13:56:19.328565 CH0 RK1: MR19=303, MR18=1F07
8292 13:56:19.335383 CH0_RK1: MR19=0x303, MR18=0x1F07, DQSOSC=394, MR23=63, INC=23, DEC=15
8293 13:56:19.338518 [RxdqsGatingPostProcess] freq 1600
8294 13:56:19.344990 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8295 13:56:19.345068 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 13:56:19.348465 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 13:56:19.351566 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 13:56:19.354770 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 13:56:19.358239 best DQS0 dly(2T, 0.5T) = (1, 1)
8300 13:56:19.361830 best DQS1 dly(2T, 0.5T) = (1, 1)
8301 13:56:19.364750 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8302 13:56:19.368034 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8303 13:56:19.371348 Pre-setting of DQS Precalculation
8304 13:56:19.374972 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8305 13:56:19.375057 ==
8306 13:56:19.378046 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 13:56:19.384782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 13:56:19.384866 ==
8309 13:56:19.388227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8310 13:56:19.395208 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8311 13:56:19.398463 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8312 13:56:19.404905 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8313 13:56:19.412124 [CA 0] Center 42 (13~72) winsize 60
8314 13:56:19.415410 [CA 1] Center 42 (12~72) winsize 61
8315 13:56:19.418768 [CA 2] Center 38 (9~68) winsize 60
8316 13:56:19.421972 [CA 3] Center 38 (10~67) winsize 58
8317 13:56:19.425288 [CA 4] Center 38 (9~68) winsize 60
8318 13:56:19.428976 [CA 5] Center 37 (8~67) winsize 60
8319 13:56:19.429056
8320 13:56:19.431921 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8321 13:56:19.432027
8322 13:56:19.435540 [CATrainingPosCal] consider 1 rank data
8323 13:56:19.439012 u2DelayCellTimex100 = 285/100 ps
8324 13:56:19.445119 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8325 13:56:19.449011 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8326 13:56:19.452310 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8327 13:56:19.455774 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8328 13:56:19.459068 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8329 13:56:19.462348 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8330 13:56:19.462428
8331 13:56:19.465639 CA PerBit enable=1, Macro0, CA PI delay=37
8332 13:56:19.465720
8333 13:56:19.469036 [CBTSetCACLKResult] CA Dly = 37
8334 13:56:19.472213 CS Dly: 10 (0~41)
8335 13:56:19.475428 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8336 13:56:19.478968 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8337 13:56:19.479050 ==
8338 13:56:19.482046 Dram Type= 6, Freq= 0, CH_1, rank 1
8339 13:56:19.485507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 13:56:19.488814 ==
8341 13:56:19.492154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8342 13:56:19.495134 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8343 13:56:19.501671 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8344 13:56:19.505502 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8345 13:56:19.515358 [CA 0] Center 42 (12~72) winsize 61
8346 13:56:19.519270 [CA 1] Center 42 (13~72) winsize 60
8347 13:56:19.522427 [CA 2] Center 38 (9~68) winsize 60
8348 13:56:19.525901 [CA 3] Center 38 (9~68) winsize 60
8349 13:56:19.529190 [CA 4] Center 39 (9~69) winsize 61
8350 13:56:19.532414 [CA 5] Center 37 (8~67) winsize 60
8351 13:56:19.532494
8352 13:56:19.535865 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8353 13:56:19.535945
8354 13:56:19.538970 [CATrainingPosCal] consider 2 rank data
8355 13:56:19.542094 u2DelayCellTimex100 = 285/100 ps
8356 13:56:19.545190 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8357 13:56:19.551956 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8358 13:56:19.555348 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8359 13:56:19.558927 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8360 13:56:19.562154 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8361 13:56:19.565202 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8362 13:56:19.565282
8363 13:56:19.568619 CA PerBit enable=1, Macro0, CA PI delay=37
8364 13:56:19.568698
8365 13:56:19.571983 [CBTSetCACLKResult] CA Dly = 37
8366 13:56:19.575402 CS Dly: 11 (0~44)
8367 13:56:19.578741 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8368 13:56:19.582166 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8369 13:56:19.582246
8370 13:56:19.585384 ----->DramcWriteLeveling(PI) begin...
8371 13:56:19.585469 ==
8372 13:56:19.588641 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 13:56:19.592067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 13:56:19.595388 ==
8375 13:56:19.595479 Write leveling (Byte 0): 25 => 25
8376 13:56:19.599085 Write leveling (Byte 1): 28 => 28
8377 13:56:19.602007 DramcWriteLeveling(PI) end<-----
8378 13:56:19.602089
8379 13:56:19.602167 ==
8380 13:56:19.605556 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 13:56:19.612178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 13:56:19.612300 ==
8383 13:56:19.615702 [Gating] SW mode calibration
8384 13:56:19.621934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8385 13:56:19.625629 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8386 13:56:19.632028 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 13:56:19.635406 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 13:56:19.638685 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (1 1) (1 1)
8389 13:56:19.641966 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8390 13:56:19.648438 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 13:56:19.651636 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 13:56:19.655102 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 13:56:19.661691 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 13:56:19.665194 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 13:56:19.668642 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 13:56:19.675216 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8397 13:56:19.678353 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
8398 13:56:19.681611 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 13:56:19.688185 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 13:56:19.691415 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 13:56:19.694813 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 13:56:19.701584 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 13:56:19.705021 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 13:56:19.708238 1 6 8 | B1->B0 | 2626 3e3e | 0 0 | (0 0) (0 0)
8405 13:56:19.714667 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8406 13:56:19.718354 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 13:56:19.721346 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 13:56:19.728280 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 13:56:19.731258 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 13:56:19.734754 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 13:56:19.741739 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 13:56:19.744930 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 13:56:19.748419 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8414 13:56:19.754862 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8415 13:56:19.758155 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 13:56:19.761476 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 13:56:19.768167 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 13:56:19.771621 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 13:56:19.774990 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 13:56:19.781266 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 13:56:19.784711 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 13:56:19.788005 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 13:56:19.794439 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 13:56:19.798295 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 13:56:19.801146 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 13:56:19.804552 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 13:56:19.811248 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 13:56:19.814606 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8429 13:56:19.817858 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8430 13:56:19.824234 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 13:56:19.827938 Total UI for P1: 0, mck2ui 16
8432 13:56:19.831295 best dqsien dly found for B0: ( 1, 9, 10)
8433 13:56:19.834721 Total UI for P1: 0, mck2ui 16
8434 13:56:19.837933 best dqsien dly found for B1: ( 1, 9, 10)
8435 13:56:19.841204 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8436 13:56:19.844220 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8437 13:56:19.844327
8438 13:56:19.847766 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8439 13:56:19.851225 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8440 13:56:19.854342 [Gating] SW calibration Done
8441 13:56:19.854423 ==
8442 13:56:19.857892 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 13:56:19.860976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 13:56:19.861073 ==
8445 13:56:19.864210 RX Vref Scan: 0
8446 13:56:19.864314
8447 13:56:19.864411 RX Vref 0 -> 0, step: 1
8448 13:56:19.867462
8449 13:56:19.867558 RX Delay 0 -> 252, step: 8
8450 13:56:19.874213 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8451 13:56:19.877680 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8452 13:56:19.881092 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8453 13:56:19.884330 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8454 13:56:19.887896 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8455 13:56:19.894423 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8456 13:56:19.897684 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8457 13:56:19.901035 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8458 13:56:19.904169 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8459 13:56:19.907368 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8460 13:56:19.910606 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8461 13:56:19.917730 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8462 13:56:19.921006 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8463 13:56:19.924231 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8464 13:56:19.927162 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8465 13:56:19.934232 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8466 13:56:19.934312 ==
8467 13:56:19.937389 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 13:56:19.940668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 13:56:19.940740 ==
8470 13:56:19.940802 DQS Delay:
8471 13:56:19.943862 DQS0 = 0, DQS1 = 0
8472 13:56:19.943929 DQM Delay:
8473 13:56:19.947247 DQM0 = 136, DQM1 = 132
8474 13:56:19.947327 DQ Delay:
8475 13:56:19.950398 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8476 13:56:19.953698 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8477 13:56:19.957525 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8478 13:56:19.960792 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8479 13:56:19.960875
8480 13:56:19.960938
8481 13:56:19.963922 ==
8482 13:56:19.967187 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 13:56:19.970292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 13:56:19.970373 ==
8485 13:56:19.970437
8486 13:56:19.970495
8487 13:56:19.973992 TX Vref Scan disable
8488 13:56:19.974072 == TX Byte 0 ==
8489 13:56:19.977131 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8490 13:56:19.983757 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8491 13:56:19.983839 == TX Byte 1 ==
8492 13:56:19.990421 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8493 13:56:19.993713 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8494 13:56:19.993794 ==
8495 13:56:19.997082 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 13:56:20.000421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 13:56:20.000502 ==
8498 13:56:20.012994
8499 13:56:20.016347 TX Vref early break, caculate TX vref
8500 13:56:20.019696 TX Vref=16, minBit 9, minWin=22, winSum=376
8501 13:56:20.023442 TX Vref=18, minBit 1, minWin=23, winSum=386
8502 13:56:20.026748 TX Vref=20, minBit 1, minWin=23, winSum=396
8503 13:56:20.029821 TX Vref=22, minBit 0, minWin=24, winSum=404
8504 13:56:20.033840 TX Vref=24, minBit 0, minWin=25, winSum=416
8505 13:56:20.039683 TX Vref=26, minBit 5, minWin=25, winSum=426
8506 13:56:20.043199 TX Vref=28, minBit 0, minWin=25, winSum=429
8507 13:56:20.046367 TX Vref=30, minBit 0, minWin=25, winSum=417
8508 13:56:20.049813 TX Vref=32, minBit 0, minWin=25, winSum=413
8509 13:56:20.053040 TX Vref=34, minBit 6, minWin=24, winSum=404
8510 13:56:20.060090 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8511 13:56:20.060211
8512 13:56:20.063084 Final TX Range 0 Vref 28
8513 13:56:20.063165
8514 13:56:20.063228 ==
8515 13:56:20.066385 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 13:56:20.069739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 13:56:20.069823 ==
8518 13:56:20.069887
8519 13:56:20.069946
8520 13:56:20.072906 TX Vref Scan disable
8521 13:56:20.079863 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8522 13:56:20.079945 == TX Byte 0 ==
8523 13:56:20.083415 u2DelayCellOfst[0]=17 cells (5 PI)
8524 13:56:20.086387 u2DelayCellOfst[1]=10 cells (3 PI)
8525 13:56:20.089589 u2DelayCellOfst[2]=0 cells (0 PI)
8526 13:56:20.093222 u2DelayCellOfst[3]=6 cells (2 PI)
8527 13:56:20.096468 u2DelayCellOfst[4]=10 cells (3 PI)
8528 13:56:20.099794 u2DelayCellOfst[5]=17 cells (5 PI)
8529 13:56:20.103153 u2DelayCellOfst[6]=20 cells (6 PI)
8530 13:56:20.103250 u2DelayCellOfst[7]=6 cells (2 PI)
8531 13:56:20.109865 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8532 13:56:20.113270 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8533 13:56:20.113350 == TX Byte 1 ==
8534 13:56:20.116099 u2DelayCellOfst[8]=0 cells (0 PI)
8535 13:56:20.120025 u2DelayCellOfst[9]=6 cells (2 PI)
8536 13:56:20.122774 u2DelayCellOfst[10]=13 cells (4 PI)
8537 13:56:20.126030 u2DelayCellOfst[11]=3 cells (1 PI)
8538 13:56:20.129955 u2DelayCellOfst[12]=17 cells (5 PI)
8539 13:56:20.133268 u2DelayCellOfst[13]=17 cells (5 PI)
8540 13:56:20.136715 u2DelayCellOfst[14]=20 cells (6 PI)
8541 13:56:20.139431 u2DelayCellOfst[15]=17 cells (5 PI)
8542 13:56:20.143316 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8543 13:56:20.149973 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8544 13:56:20.150118 DramC Write-DBI on
8545 13:56:20.150214 ==
8546 13:56:20.153150 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 13:56:20.156218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 13:56:20.156322 ==
8549 13:56:20.156388
8550 13:56:20.159872
8551 13:56:20.159951 TX Vref Scan disable
8552 13:56:20.163130 == TX Byte 0 ==
8553 13:56:20.166382 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8554 13:56:20.169943 == TX Byte 1 ==
8555 13:56:20.173139 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8556 13:56:20.173220 DramC Write-DBI off
8557 13:56:20.173284
8558 13:56:20.176478 [DATLAT]
8559 13:56:20.176559 Freq=1600, CH1 RK0
8560 13:56:20.176661
8561 13:56:20.179819 DATLAT Default: 0xf
8562 13:56:20.179899 0, 0xFFFF, sum = 0
8563 13:56:20.183147 1, 0xFFFF, sum = 0
8564 13:56:20.183228 2, 0xFFFF, sum = 0
8565 13:56:20.186359 3, 0xFFFF, sum = 0
8566 13:56:20.186440 4, 0xFFFF, sum = 0
8567 13:56:20.189703 5, 0xFFFF, sum = 0
8568 13:56:20.189787 6, 0xFFFF, sum = 0
8569 13:56:20.193356 7, 0xFFFF, sum = 0
8570 13:56:20.193440 8, 0xFFFF, sum = 0
8571 13:56:20.196526 9, 0xFFFF, sum = 0
8572 13:56:20.199825 10, 0xFFFF, sum = 0
8573 13:56:20.199928 11, 0xFFFF, sum = 0
8574 13:56:20.203196 12, 0xFFFF, sum = 0
8575 13:56:20.203303 13, 0xFFFF, sum = 0
8576 13:56:20.206566 14, 0x0, sum = 1
8577 13:56:20.206650 15, 0x0, sum = 2
8578 13:56:20.210007 16, 0x0, sum = 3
8579 13:56:20.210089 17, 0x0, sum = 4
8580 13:56:20.210156 best_step = 15
8581 13:56:20.210216
8582 13:56:20.212972 ==
8583 13:56:20.216175 Dram Type= 6, Freq= 0, CH_1, rank 0
8584 13:56:20.219485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8585 13:56:20.219559 ==
8586 13:56:20.219631 RX Vref Scan: 1
8587 13:56:20.219720
8588 13:56:20.223000 Set Vref Range= 24 -> 127
8589 13:56:20.223076
8590 13:56:20.226197 RX Vref 24 -> 127, step: 1
8591 13:56:20.226299
8592 13:56:20.229595 RX Delay 27 -> 252, step: 4
8593 13:56:20.229667
8594 13:56:20.232777 Set Vref, RX VrefLevel [Byte0]: 24
8595 13:56:20.235986 [Byte1]: 24
8596 13:56:20.236085
8597 13:56:20.239388 Set Vref, RX VrefLevel [Byte0]: 25
8598 13:56:20.242702 [Byte1]: 25
8599 13:56:20.242810
8600 13:56:20.246007 Set Vref, RX VrefLevel [Byte0]: 26
8601 13:56:20.249383 [Byte1]: 26
8602 13:56:20.252810
8603 13:56:20.252889 Set Vref, RX VrefLevel [Byte0]: 27
8604 13:56:20.256198 [Byte1]: 27
8605 13:56:20.260202
8606 13:56:20.260339 Set Vref, RX VrefLevel [Byte0]: 28
8607 13:56:20.263420 [Byte1]: 28
8608 13:56:20.268112
8609 13:56:20.268210 Set Vref, RX VrefLevel [Byte0]: 29
8610 13:56:20.271414 [Byte1]: 29
8611 13:56:20.275466
8612 13:56:20.275564 Set Vref, RX VrefLevel [Byte0]: 30
8613 13:56:20.278859 [Byte1]: 30
8614 13:56:20.282785
8615 13:56:20.282890 Set Vref, RX VrefLevel [Byte0]: 31
8616 13:56:20.286480 [Byte1]: 31
8617 13:56:20.290311
8618 13:56:20.290393 Set Vref, RX VrefLevel [Byte0]: 32
8619 13:56:20.294043 [Byte1]: 32
8620 13:56:20.297799
8621 13:56:20.297900 Set Vref, RX VrefLevel [Byte0]: 33
8622 13:56:20.301129 [Byte1]: 33
8623 13:56:20.305443
8624 13:56:20.305520 Set Vref, RX VrefLevel [Byte0]: 34
8625 13:56:20.308607 [Byte1]: 34
8626 13:56:20.312776
8627 13:56:20.312907 Set Vref, RX VrefLevel [Byte0]: 35
8628 13:56:20.316539 [Byte1]: 35
8629 13:56:20.320539
8630 13:56:20.320615 Set Vref, RX VrefLevel [Byte0]: 36
8631 13:56:20.324205 [Byte1]: 36
8632 13:56:20.327972
8633 13:56:20.328084 Set Vref, RX VrefLevel [Byte0]: 37
8634 13:56:20.331096 [Byte1]: 37
8635 13:56:20.335477
8636 13:56:20.335548 Set Vref, RX VrefLevel [Byte0]: 38
8637 13:56:20.338792 [Byte1]: 38
8638 13:56:20.343028
8639 13:56:20.343136 Set Vref, RX VrefLevel [Byte0]: 39
8640 13:56:20.346711 [Byte1]: 39
8641 13:56:20.350692
8642 13:56:20.350789 Set Vref, RX VrefLevel [Byte0]: 40
8643 13:56:20.353936 [Byte1]: 40
8644 13:56:20.357926
8645 13:56:20.358037 Set Vref, RX VrefLevel [Byte0]: 41
8646 13:56:20.361336 [Byte1]: 41
8647 13:56:20.365826
8648 13:56:20.365923 Set Vref, RX VrefLevel [Byte0]: 42
8649 13:56:20.369247 [Byte1]: 42
8650 13:56:20.373180
8651 13:56:20.373277 Set Vref, RX VrefLevel [Byte0]: 43
8652 13:56:20.376399 [Byte1]: 43
8653 13:56:20.381175
8654 13:56:20.381273 Set Vref, RX VrefLevel [Byte0]: 44
8655 13:56:20.383819 [Byte1]: 44
8656 13:56:20.388223
8657 13:56:20.388363 Set Vref, RX VrefLevel [Byte0]: 45
8658 13:56:20.391531 [Byte1]: 45
8659 13:56:20.396131
8660 13:56:20.396250 Set Vref, RX VrefLevel [Byte0]: 46
8661 13:56:20.399531 [Byte1]: 46
8662 13:56:20.403519
8663 13:56:20.403615 Set Vref, RX VrefLevel [Byte0]: 47
8664 13:56:20.406878 [Byte1]: 47
8665 13:56:20.410899
8666 13:56:20.411023 Set Vref, RX VrefLevel [Byte0]: 48
8667 13:56:20.414142 [Byte1]: 48
8668 13:56:20.418522
8669 13:56:20.418641 Set Vref, RX VrefLevel [Byte0]: 49
8670 13:56:20.421714 [Byte1]: 49
8671 13:56:20.426012
8672 13:56:20.426110 Set Vref, RX VrefLevel [Byte0]: 50
8673 13:56:20.429271 [Byte1]: 50
8674 13:56:20.433585
8675 13:56:20.433682 Set Vref, RX VrefLevel [Byte0]: 51
8676 13:56:20.436689 [Byte1]: 51
8677 13:56:20.441366
8678 13:56:20.441448 Set Vref, RX VrefLevel [Byte0]: 52
8679 13:56:20.444586 [Byte1]: 52
8680 13:56:20.448368
8681 13:56:20.448450 Set Vref, RX VrefLevel [Byte0]: 53
8682 13:56:20.451885 [Byte1]: 53
8683 13:56:20.455927
8684 13:56:20.456002 Set Vref, RX VrefLevel [Byte0]: 54
8685 13:56:20.459151 [Byte1]: 54
8686 13:56:20.463837
8687 13:56:20.463919 Set Vref, RX VrefLevel [Byte0]: 55
8688 13:56:20.466709 [Byte1]: 55
8689 13:56:20.470944
8690 13:56:20.471055 Set Vref, RX VrefLevel [Byte0]: 56
8691 13:56:20.474210 [Byte1]: 56
8692 13:56:20.478760
8693 13:56:20.478871 Set Vref, RX VrefLevel [Byte0]: 57
8694 13:56:20.482117 [Byte1]: 57
8695 13:56:20.486190
8696 13:56:20.486272 Set Vref, RX VrefLevel [Byte0]: 58
8697 13:56:20.489618 [Byte1]: 58
8698 13:56:20.493468
8699 13:56:20.493549 Set Vref, RX VrefLevel [Byte0]: 59
8700 13:56:20.496861 [Byte1]: 59
8701 13:56:20.501540
8702 13:56:20.501622 Set Vref, RX VrefLevel [Byte0]: 60
8703 13:56:20.504868 [Byte1]: 60
8704 13:56:20.508819
8705 13:56:20.508901 Set Vref, RX VrefLevel [Byte0]: 61
8706 13:56:20.512123 [Byte1]: 61
8707 13:56:20.516178
8708 13:56:20.516296 Set Vref, RX VrefLevel [Byte0]: 62
8709 13:56:20.519572 [Byte1]: 62
8710 13:56:20.524001
8711 13:56:20.524083 Set Vref, RX VrefLevel [Byte0]: 63
8712 13:56:20.527008 [Byte1]: 63
8713 13:56:20.531266
8714 13:56:20.531348 Set Vref, RX VrefLevel [Byte0]: 64
8715 13:56:20.534797 [Byte1]: 64
8716 13:56:20.539145
8717 13:56:20.539227 Set Vref, RX VrefLevel [Byte0]: 65
8718 13:56:20.542408 [Byte1]: 65
8719 13:56:20.546320
8720 13:56:20.546402 Set Vref, RX VrefLevel [Byte0]: 66
8721 13:56:20.549919 [Byte1]: 66
8722 13:56:20.554158
8723 13:56:20.554240 Set Vref, RX VrefLevel [Byte0]: 67
8724 13:56:20.557429 [Byte1]: 67
8725 13:56:20.561514
8726 13:56:20.561597 Set Vref, RX VrefLevel [Byte0]: 68
8727 13:56:20.564880 [Byte1]: 68
8728 13:56:20.569310
8729 13:56:20.569392 Set Vref, RX VrefLevel [Byte0]: 69
8730 13:56:20.572257 [Byte1]: 69
8731 13:56:20.576918
8732 13:56:20.577007 Set Vref, RX VrefLevel [Byte0]: 70
8733 13:56:20.579777 [Byte1]: 70
8734 13:56:20.584157
8735 13:56:20.584238 Set Vref, RX VrefLevel [Byte0]: 71
8736 13:56:20.587371 [Byte1]: 71
8737 13:56:20.591907
8738 13:56:20.592017 Set Vref, RX VrefLevel [Byte0]: 72
8739 13:56:20.595184 [Byte1]: 72
8740 13:56:20.599088
8741 13:56:20.599172 Set Vref, RX VrefLevel [Byte0]: 73
8742 13:56:20.602374 [Byte1]: 73
8743 13:56:20.606988
8744 13:56:20.607083 Set Vref, RX VrefLevel [Byte0]: 74
8745 13:56:20.610377 [Byte1]: 74
8746 13:56:20.614346
8747 13:56:20.614428 Set Vref, RX VrefLevel [Byte0]: 75
8748 13:56:20.617735 [Byte1]: 75
8749 13:56:20.621820
8750 13:56:20.621901 Set Vref, RX VrefLevel [Byte0]: 76
8751 13:56:20.625220 [Byte1]: 76
8752 13:56:20.629175
8753 13:56:20.632504 Set Vref, RX VrefLevel [Byte0]: 77
8754 13:56:20.632586 [Byte1]: 77
8755 13:56:20.637004
8756 13:56:20.637092 Set Vref, RX VrefLevel [Byte0]: 78
8757 13:56:20.640084 [Byte1]: 78
8758 13:56:20.644317
8759 13:56:20.644397 Set Vref, RX VrefLevel [Byte0]: 79
8760 13:56:20.647729 [Byte1]: 79
8761 13:56:20.651631
8762 13:56:20.651711 Final RX Vref Byte 0 = 59 to rank0
8763 13:56:20.654906 Final RX Vref Byte 1 = 58 to rank0
8764 13:56:20.658734 Final RX Vref Byte 0 = 59 to rank1
8765 13:56:20.661861 Final RX Vref Byte 1 = 58 to rank1==
8766 13:56:20.665372 Dram Type= 6, Freq= 0, CH_1, rank 0
8767 13:56:20.671761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 13:56:20.671841 ==
8769 13:56:20.671906 DQS Delay:
8770 13:56:20.671964 DQS0 = 0, DQS1 = 0
8771 13:56:20.675201 DQM Delay:
8772 13:56:20.675282 DQM0 = 134, DQM1 = 131
8773 13:56:20.678425 DQ Delay:
8774 13:56:20.681756 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8775 13:56:20.685134 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8776 13:56:20.688452 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =124
8777 13:56:20.691534 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8778 13:56:20.691614
8779 13:56:20.691730
8780 13:56:20.691793
8781 13:56:20.695060 [DramC_TX_OE_Calibration] TA2
8782 13:56:20.698385 Original DQ_B0 (3 6) =30, OEN = 27
8783 13:56:20.701733 Original DQ_B1 (3 6) =30, OEN = 27
8784 13:56:20.705313 24, 0x0, End_B0=24 End_B1=24
8785 13:56:20.705394 25, 0x0, End_B0=25 End_B1=25
8786 13:56:20.708604 26, 0x0, End_B0=26 End_B1=26
8787 13:56:20.711698 27, 0x0, End_B0=27 End_B1=27
8788 13:56:20.715374 28, 0x0, End_B0=28 End_B1=28
8789 13:56:20.715501 29, 0x0, End_B0=29 End_B1=29
8790 13:56:20.718407 30, 0x0, End_B0=30 End_B1=30
8791 13:56:20.721570 31, 0x4545, End_B0=30 End_B1=30
8792 13:56:20.724877 Byte0 end_step=30 best_step=27
8793 13:56:20.728789 Byte1 end_step=30 best_step=27
8794 13:56:20.731851 Byte0 TX OE(2T, 0.5T) = (3, 3)
8795 13:56:20.731935 Byte1 TX OE(2T, 0.5T) = (3, 3)
8796 13:56:20.735094
8797 13:56:20.735176
8798 13:56:20.741845 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8799 13:56:20.745150 CH1 RK0: MR19=303, MR18=1624
8800 13:56:20.751913 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8801 13:56:20.751997
8802 13:56:20.754857 ----->DramcWriteLeveling(PI) begin...
8803 13:56:20.754942 ==
8804 13:56:20.758605 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 13:56:20.761579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 13:56:20.761678 ==
8807 13:56:20.765070 Write leveling (Byte 0): 24 => 24
8808 13:56:20.768161 Write leveling (Byte 1): 29 => 29
8809 13:56:20.771813 DramcWriteLeveling(PI) end<-----
8810 13:56:20.771898
8811 13:56:20.771983 ==
8812 13:56:20.774949 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 13:56:20.778597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 13:56:20.778681 ==
8815 13:56:20.781418 [Gating] SW mode calibration
8816 13:56:20.788200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8817 13:56:20.795042 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8818 13:56:20.798602 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 13:56:20.801681 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 13:56:20.808330 1 4 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
8821 13:56:20.811650 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8822 13:56:20.814991 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 13:56:20.821380 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 13:56:20.824476 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 13:56:20.828026 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 13:56:20.834644 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 13:56:20.838399 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8828 13:56:20.841037 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8829 13:56:20.847844 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 13:56:20.851293 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 13:56:20.854657 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 13:56:20.861212 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 13:56:20.864626 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 13:56:20.867802 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 13:56:20.874614 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 13:56:20.877623 1 6 8 | B1->B0 | 3939 2323 | 0 0 | (0 0) (0 0)
8837 13:56:20.881240 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8838 13:56:20.887817 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 13:56:20.890884 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 13:56:20.894396 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 13:56:20.901008 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 13:56:20.904305 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 13:56:20.907589 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8844 13:56:20.914226 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8845 13:56:20.917448 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8846 13:56:20.920862 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 13:56:20.924175 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 13:56:20.930993 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 13:56:20.934099 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 13:56:20.937447 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 13:56:20.944052 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 13:56:20.947734 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 13:56:20.950787 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 13:56:20.957692 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 13:56:20.960499 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 13:56:20.964188 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 13:56:20.970701 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 13:56:20.974077 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 13:56:20.977303 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 13:56:20.983686 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8861 13:56:20.987447 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8862 13:56:20.990695 Total UI for P1: 0, mck2ui 16
8863 13:56:20.994027 best dqsien dly found for B1: ( 1, 9, 8)
8864 13:56:20.997334 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 13:56:21.000670 Total UI for P1: 0, mck2ui 16
8866 13:56:21.003809 best dqsien dly found for B0: ( 1, 9, 10)
8867 13:56:21.007612 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8868 13:56:21.010570 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8869 13:56:21.010651
8870 13:56:21.017486 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8871 13:56:21.020232 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8872 13:56:21.020335 [Gating] SW calibration Done
8873 13:56:21.023744 ==
8874 13:56:21.027067 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 13:56:21.030351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 13:56:21.030432 ==
8877 13:56:21.030496 RX Vref Scan: 0
8878 13:56:21.030556
8879 13:56:21.033767 RX Vref 0 -> 0, step: 1
8880 13:56:21.033848
8881 13:56:21.037673 RX Delay 0 -> 252, step: 8
8882 13:56:21.040924 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8883 13:56:21.043570 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8884 13:56:21.047000 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8885 13:56:21.054092 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8886 13:56:21.057427 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8887 13:56:21.060771 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8888 13:56:21.064008 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8889 13:56:21.067407 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8890 13:56:21.073773 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8891 13:56:21.077359 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8892 13:56:21.080282 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8893 13:56:21.083817 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8894 13:56:21.087073 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8895 13:56:21.093780 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8896 13:56:21.097283 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8897 13:56:21.100190 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8898 13:56:21.100309 ==
8899 13:56:21.103816 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 13:56:21.107290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 13:56:21.107375 ==
8902 13:56:21.110339 DQS Delay:
8903 13:56:21.110423 DQS0 = 0, DQS1 = 0
8904 13:56:21.113446 DQM Delay:
8905 13:56:21.113531 DQM0 = 136, DQM1 = 133
8906 13:56:21.116823 DQ Delay:
8907 13:56:21.120139 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8908 13:56:21.123211 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8909 13:56:21.126801 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8910 13:56:21.130145 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8911 13:56:21.130225
8912 13:56:21.130289
8913 13:56:21.130347 ==
8914 13:56:21.133132 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 13:56:21.137172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 13:56:21.137253 ==
8917 13:56:21.137338
8918 13:56:21.137401
8919 13:56:21.139815 TX Vref Scan disable
8920 13:56:21.143725 == TX Byte 0 ==
8921 13:56:21.147059 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8922 13:56:21.150433 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8923 13:56:21.153548 == TX Byte 1 ==
8924 13:56:21.156827 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8925 13:56:21.160103 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8926 13:56:21.160224 ==
8927 13:56:21.163463 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 13:56:21.170107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 13:56:21.170213 ==
8930 13:56:21.182763
8931 13:56:21.186133 TX Vref early break, caculate TX vref
8932 13:56:21.189415 TX Vref=16, minBit 0, minWin=23, winSum=383
8933 13:56:21.192726 TX Vref=18, minBit 0, minWin=24, winSum=393
8934 13:56:21.196003 TX Vref=20, minBit 1, minWin=24, winSum=400
8935 13:56:21.199209 TX Vref=22, minBit 0, minWin=24, winSum=410
8936 13:56:21.202644 TX Vref=24, minBit 0, minWin=25, winSum=419
8937 13:56:21.209007 TX Vref=26, minBit 0, minWin=25, winSum=426
8938 13:56:21.212406 TX Vref=28, minBit 0, minWin=26, winSum=426
8939 13:56:21.215534 TX Vref=30, minBit 0, minWin=25, winSum=420
8940 13:56:21.219154 TX Vref=32, minBit 0, minWin=24, winSum=415
8941 13:56:21.221912 TX Vref=34, minBit 6, minWin=24, winSum=407
8942 13:56:21.229032 TX Vref=36, minBit 6, minWin=23, winSum=394
8943 13:56:21.231884 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8944 13:56:21.231965
8945 13:56:21.235327 Final TX Range 0 Vref 28
8946 13:56:21.235408
8947 13:56:21.235509 ==
8948 13:56:21.238911 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 13:56:21.242471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 13:56:21.242568 ==
8951 13:56:21.245231
8952 13:56:21.245311
8953 13:56:21.245375 TX Vref Scan disable
8954 13:56:21.252215 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8955 13:56:21.252332 == TX Byte 0 ==
8956 13:56:21.255508 u2DelayCellOfst[0]=20 cells (6 PI)
8957 13:56:21.258421 u2DelayCellOfst[1]=10 cells (3 PI)
8958 13:56:21.261813 u2DelayCellOfst[2]=0 cells (0 PI)
8959 13:56:21.265030 u2DelayCellOfst[3]=6 cells (2 PI)
8960 13:56:21.268431 u2DelayCellOfst[4]=10 cells (3 PI)
8961 13:56:21.271728 u2DelayCellOfst[5]=20 cells (6 PI)
8962 13:56:21.275136 u2DelayCellOfst[6]=20 cells (6 PI)
8963 13:56:21.278556 u2DelayCellOfst[7]=6 cells (2 PI)
8964 13:56:21.281840 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8965 13:56:21.285169 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8966 13:56:21.288474 == TX Byte 1 ==
8967 13:56:21.291771 u2DelayCellOfst[8]=0 cells (0 PI)
8968 13:56:21.295109 u2DelayCellOfst[9]=3 cells (1 PI)
8969 13:56:21.298433 u2DelayCellOfst[10]=10 cells (3 PI)
8970 13:56:21.301761 u2DelayCellOfst[11]=6 cells (2 PI)
8971 13:56:21.304907 u2DelayCellOfst[12]=13 cells (4 PI)
8972 13:56:21.305036 u2DelayCellOfst[13]=17 cells (5 PI)
8973 13:56:21.308201 u2DelayCellOfst[14]=17 cells (5 PI)
8974 13:56:21.311591 u2DelayCellOfst[15]=17 cells (5 PI)
8975 13:56:21.318239 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8976 13:56:21.321663 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8977 13:56:21.321745 DramC Write-DBI on
8978 13:56:21.324847 ==
8979 13:56:21.324927 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 13:56:21.331519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 13:56:21.331601 ==
8982 13:56:21.331666
8983 13:56:21.331725
8984 13:56:21.334997 TX Vref Scan disable
8985 13:56:21.335078 == TX Byte 0 ==
8986 13:56:21.341436 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8987 13:56:21.341521 == TX Byte 1 ==
8988 13:56:21.345081 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8989 13:56:21.348133 DramC Write-DBI off
8990 13:56:21.348217
8991 13:56:21.348379 [DATLAT]
8992 13:56:21.351351 Freq=1600, CH1 RK1
8993 13:56:21.351435
8994 13:56:21.351520 DATLAT Default: 0xf
8995 13:56:21.355008 0, 0xFFFF, sum = 0
8996 13:56:21.355093 1, 0xFFFF, sum = 0
8997 13:56:21.358423 2, 0xFFFF, sum = 0
8998 13:56:21.358508 3, 0xFFFF, sum = 0
8999 13:56:21.361298 4, 0xFFFF, sum = 0
9000 13:56:21.361383 5, 0xFFFF, sum = 0
9001 13:56:21.364726 6, 0xFFFF, sum = 0
9002 13:56:21.364811 7, 0xFFFF, sum = 0
9003 13:56:21.368432 8, 0xFFFF, sum = 0
9004 13:56:21.368518 9, 0xFFFF, sum = 0
9005 13:56:21.371503 10, 0xFFFF, sum = 0
9006 13:56:21.374782 11, 0xFFFF, sum = 0
9007 13:56:21.374892 12, 0xFFFF, sum = 0
9008 13:56:21.378360 13, 0xFFFF, sum = 0
9009 13:56:21.378444 14, 0x0, sum = 1
9010 13:56:21.381459 15, 0x0, sum = 2
9011 13:56:21.381543 16, 0x0, sum = 3
9012 13:56:21.381631 17, 0x0, sum = 4
9013 13:56:21.384888 best_step = 15
9014 13:56:21.384971
9015 13:56:21.385057 ==
9016 13:56:21.388248 Dram Type= 6, Freq= 0, CH_1, rank 1
9017 13:56:21.391626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9018 13:56:21.391710 ==
9019 13:56:21.395029 RX Vref Scan: 0
9020 13:56:21.395113
9021 13:56:21.395198 RX Vref 0 -> 0, step: 1
9022 13:56:21.397730
9023 13:56:21.397813 RX Delay 19 -> 252, step: 4
9024 13:56:21.404818 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9025 13:56:21.408138 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
9026 13:56:21.411372 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
9027 13:56:21.414736 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9028 13:56:21.417954 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9029 13:56:21.424730 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9030 13:56:21.427996 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9031 13:56:21.431393 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9032 13:56:21.434803 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9033 13:56:21.438173 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9034 13:56:21.441547 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9035 13:56:21.448142 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9036 13:56:21.451253 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9037 13:56:21.455025 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9038 13:56:21.458121 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9039 13:56:21.464411 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9040 13:56:21.464493 ==
9041 13:56:21.468020 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 13:56:21.471100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 13:56:21.471181 ==
9044 13:56:21.471264 DQS Delay:
9045 13:56:21.474985 DQS0 = 0, DQS1 = 0
9046 13:56:21.475066 DQM Delay:
9047 13:56:21.478308 DQM0 = 134, DQM1 = 130
9048 13:56:21.478408 DQ Delay:
9049 13:56:21.481524 DQ0 =138, DQ1 =132, DQ2 =124, DQ3 =130
9050 13:56:21.484525 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9051 13:56:21.488000 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9052 13:56:21.491418 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9053 13:56:21.491501
9054 13:56:21.491566
9055 13:56:21.494394
9056 13:56:21.494475 [DramC_TX_OE_Calibration] TA2
9057 13:56:21.498163 Original DQ_B0 (3 6) =30, OEN = 27
9058 13:56:21.501248 Original DQ_B1 (3 6) =30, OEN = 27
9059 13:56:21.504492 24, 0x0, End_B0=24 End_B1=24
9060 13:56:21.507714 25, 0x0, End_B0=25 End_B1=25
9061 13:56:21.511254 26, 0x0, End_B0=26 End_B1=26
9062 13:56:21.511363 27, 0x0, End_B0=27 End_B1=27
9063 13:56:21.514542 28, 0x0, End_B0=28 End_B1=28
9064 13:56:21.517774 29, 0x0, End_B0=29 End_B1=29
9065 13:56:21.521475 30, 0x0, End_B0=30 End_B1=30
9066 13:56:21.524872 31, 0x4141, End_B0=30 End_B1=30
9067 13:56:21.524955 Byte0 end_step=30 best_step=27
9068 13:56:21.527731 Byte1 end_step=30 best_step=27
9069 13:56:21.530876 Byte0 TX OE(2T, 0.5T) = (3, 3)
9070 13:56:21.534356 Byte1 TX OE(2T, 0.5T) = (3, 3)
9071 13:56:21.534437
9072 13:56:21.534500
9073 13:56:21.541002 [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9074 13:56:21.544265 CH1 RK1: MR19=303, MR18=2208
9075 13:56:21.550986 CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16
9076 13:56:21.554263 [RxdqsGatingPostProcess] freq 1600
9077 13:56:21.560901 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9078 13:56:21.564164 best DQS0 dly(2T, 0.5T) = (1, 1)
9079 13:56:21.564237 best DQS1 dly(2T, 0.5T) = (1, 1)
9080 13:56:21.567638 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9081 13:56:21.571290 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9082 13:56:21.574289 best DQS0 dly(2T, 0.5T) = (1, 1)
9083 13:56:21.577713 best DQS1 dly(2T, 0.5T) = (1, 1)
9084 13:56:21.580595 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9085 13:56:21.584329 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9086 13:56:21.587438 Pre-setting of DQS Precalculation
9087 13:56:21.590707 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9088 13:56:21.600672 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9089 13:56:21.607485 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9090 13:56:21.607567
9091 13:56:21.607631
9092 13:56:21.610862 [Calibration Summary] 3200 Mbps
9093 13:56:21.610943 CH 0, Rank 0
9094 13:56:21.614140 SW Impedance : PASS
9095 13:56:21.614236 DUTY Scan : NO K
9096 13:56:21.617233 ZQ Calibration : PASS
9097 13:56:21.620697 Jitter Meter : NO K
9098 13:56:21.620778 CBT Training : PASS
9099 13:56:21.624171 Write leveling : PASS
9100 13:56:21.627343 RX DQS gating : PASS
9101 13:56:21.627425 RX DQ/DQS(RDDQC) : PASS
9102 13:56:21.630637 TX DQ/DQS : PASS
9103 13:56:21.633944 RX DATLAT : PASS
9104 13:56:21.634042 RX DQ/DQS(Engine): PASS
9105 13:56:21.637480 TX OE : PASS
9106 13:56:21.637561 All Pass.
9107 13:56:21.637665
9108 13:56:21.640798 CH 0, Rank 1
9109 13:56:21.640879 SW Impedance : PASS
9110 13:56:21.643822 DUTY Scan : NO K
9111 13:56:21.647356 ZQ Calibration : PASS
9112 13:56:21.647437 Jitter Meter : NO K
9113 13:56:21.650384 CBT Training : PASS
9114 13:56:21.653756 Write leveling : PASS
9115 13:56:21.653830 RX DQS gating : PASS
9116 13:56:21.657107 RX DQ/DQS(RDDQC) : PASS
9117 13:56:21.657189 TX DQ/DQS : PASS
9118 13:56:21.660275 RX DATLAT : PASS
9119 13:56:21.663634 RX DQ/DQS(Engine): PASS
9120 13:56:21.663716 TX OE : PASS
9121 13:56:21.667017 All Pass.
9122 13:56:21.667098
9123 13:56:21.667161 CH 1, Rank 0
9124 13:56:21.670348 SW Impedance : PASS
9125 13:56:21.670429 DUTY Scan : NO K
9126 13:56:21.673647 ZQ Calibration : PASS
9127 13:56:21.677323 Jitter Meter : NO K
9128 13:56:21.677404 CBT Training : PASS
9129 13:56:21.680670 Write leveling : PASS
9130 13:56:21.683973 RX DQS gating : PASS
9131 13:56:21.684084 RX DQ/DQS(RDDQC) : PASS
9132 13:56:21.687308 TX DQ/DQS : PASS
9133 13:56:21.690493 RX DATLAT : PASS
9134 13:56:21.690594 RX DQ/DQS(Engine): PASS
9135 13:56:21.693590 TX OE : PASS
9136 13:56:21.693686 All Pass.
9137 13:56:21.693769
9138 13:56:21.697203 CH 1, Rank 1
9139 13:56:21.697286 SW Impedance : PASS
9140 13:56:21.700136 DUTY Scan : NO K
9141 13:56:21.703844 ZQ Calibration : PASS
9142 13:56:21.703926 Jitter Meter : NO K
9143 13:56:21.707146 CBT Training : PASS
9144 13:56:21.707229 Write leveling : PASS
9145 13:56:21.710440 RX DQS gating : PASS
9146 13:56:21.713966 RX DQ/DQS(RDDQC) : PASS
9147 13:56:21.714063 TX DQ/DQS : PASS
9148 13:56:21.716623 RX DATLAT : PASS
9149 13:56:21.720043 RX DQ/DQS(Engine): PASS
9150 13:56:21.720126 TX OE : PASS
9151 13:56:21.723633 All Pass.
9152 13:56:21.723713
9153 13:56:21.723778 DramC Write-DBI on
9154 13:56:21.726916 PER_BANK_REFRESH: Hybrid Mode
9155 13:56:21.730032 TX_TRACKING: ON
9156 13:56:21.736914 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9157 13:56:21.746650 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9158 13:56:21.753315 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9159 13:56:21.756714 [FAST_K] Save calibration result to emmc
9160 13:56:21.760381 sync common calibartion params.
9161 13:56:21.760490 sync cbt_mode0:1, 1:1
9162 13:56:21.763578 dram_init: ddr_geometry: 2
9163 13:56:21.766935 dram_init: ddr_geometry: 2
9164 13:56:21.770475 dram_init: ddr_geometry: 2
9165 13:56:21.770557 0:dram_rank_size:100000000
9166 13:56:21.773472 1:dram_rank_size:100000000
9167 13:56:21.779985 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9168 13:56:21.780069 DFS_SHUFFLE_HW_MODE: ON
9169 13:56:21.783400 dramc_set_vcore_voltage set vcore to 725000
9170 13:56:21.786833 Read voltage for 1600, 0
9171 13:56:21.786942 Vio18 = 0
9172 13:56:21.790198 Vcore = 725000
9173 13:56:21.790280 Vdram = 0
9174 13:56:21.790346 Vddq = 0
9175 13:56:21.793611 Vmddr = 0
9176 13:56:21.793693 switch to 3200 Mbps bootup
9177 13:56:21.796766 [DramcRunTimeConfig]
9178 13:56:21.796848 PHYPLL
9179 13:56:21.800025 DPM_CONTROL_AFTERK: ON
9180 13:56:21.800107 PER_BANK_REFRESH: ON
9181 13:56:21.803264 REFRESH_OVERHEAD_REDUCTION: ON
9182 13:56:21.807193 CMD_PICG_NEW_MODE: OFF
9183 13:56:21.807275 XRTWTW_NEW_MODE: ON
9184 13:56:21.810200 XRTRTR_NEW_MODE: ON
9185 13:56:21.810282 TX_TRACKING: ON
9186 13:56:21.813650 RDSEL_TRACKING: OFF
9187 13:56:21.816762 DQS Precalculation for DVFS: ON
9188 13:56:21.816871 RX_TRACKING: OFF
9189 13:56:21.819666 HW_GATING DBG: ON
9190 13:56:21.819774 ZQCS_ENABLE_LP4: ON
9191 13:56:21.823725 RX_PICG_NEW_MODE: ON
9192 13:56:21.823834 TX_PICG_NEW_MODE: ON
9193 13:56:21.826327 ENABLE_RX_DCM_DPHY: ON
9194 13:56:21.829732 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9195 13:56:21.833058 DUMMY_READ_FOR_TRACKING: OFF
9196 13:56:21.833141 !!! SPM_CONTROL_AFTERK: OFF
9197 13:56:21.836276 !!! SPM could not control APHY
9198 13:56:21.839691 IMPEDANCE_TRACKING: ON
9199 13:56:21.839768 TEMP_SENSOR: ON
9200 13:56:21.843104 HW_SAVE_FOR_SR: OFF
9201 13:56:21.846664 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9202 13:56:21.850045 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9203 13:56:21.852809 Read ODT Tracking: ON
9204 13:56:21.852917 Refresh Rate DeBounce: ON
9205 13:56:21.856181 DFS_NO_QUEUE_FLUSH: ON
9206 13:56:21.859514 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9207 13:56:21.862915 ENABLE_DFS_RUNTIME_MRW: OFF
9208 13:56:21.863001 DDR_RESERVE_NEW_MODE: ON
9209 13:56:21.866763 MR_CBT_SWITCH_FREQ: ON
9210 13:56:21.869550 =========================
9211 13:56:21.887207 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9212 13:56:21.890522 dram_init: ddr_geometry: 2
9213 13:56:21.908413 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9214 13:56:21.911773 dram_init: dram init end (result: 0)
9215 13:56:21.918568 DRAM-K: Full calibration passed in 24520 msecs
9216 13:56:21.921692 MRC: failed to locate region type 0.
9217 13:56:21.921808 DRAM rank0 size:0x100000000,
9218 13:56:21.925613 DRAM rank1 size=0x100000000
9219 13:56:21.935272 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9220 13:56:21.941800 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9221 13:56:21.948624 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9222 13:56:21.955439 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9223 13:56:21.958702 DRAM rank0 size:0x100000000,
9224 13:56:21.962070 DRAM rank1 size=0x100000000
9225 13:56:21.962153 CBMEM:
9226 13:56:21.965422 IMD: root @ 0xfffff000 254 entries.
9227 13:56:21.968641 IMD: root @ 0xffffec00 62 entries.
9228 13:56:21.971767 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9229 13:56:21.975271 WARNING: RO_VPD is uninitialized or empty.
9230 13:56:21.982002 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9231 13:56:21.988688 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9232 13:56:22.001527 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9233 13:56:22.012852 BS: romstage times (exec / console): total (unknown) / 24039 ms
9234 13:56:22.012961
9235 13:56:22.013060
9236 13:56:22.022902 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9237 13:56:22.026355 ARM64: Exception handlers installed.
9238 13:56:22.029648 ARM64: Testing exception
9239 13:56:22.032888 ARM64: Done test exception
9240 13:56:22.032974 Enumerating buses...
9241 13:56:22.036048 Show all devs... Before device enumeration.
9242 13:56:22.039715 Root Device: enabled 1
9243 13:56:22.042815 CPU_CLUSTER: 0: enabled 1
9244 13:56:22.042926 CPU: 00: enabled 1
9245 13:56:22.046658 Compare with tree...
9246 13:56:22.046737 Root Device: enabled 1
9247 13:56:22.049732 CPU_CLUSTER: 0: enabled 1
9248 13:56:22.052967 CPU: 00: enabled 1
9249 13:56:22.053081 Root Device scanning...
9250 13:56:22.055863 scan_static_bus for Root Device
9251 13:56:22.059282 CPU_CLUSTER: 0 enabled
9252 13:56:22.062593 scan_static_bus for Root Device done
9253 13:56:22.065878 scan_bus: bus Root Device finished in 8 msecs
9254 13:56:22.065987 done
9255 13:56:22.072709 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9256 13:56:22.075962 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9257 13:56:22.082778 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9258 13:56:22.086231 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9259 13:56:22.089713 Allocating resources...
9260 13:56:22.089796 Reading resources...
9261 13:56:22.096621 Root Device read_resources bus 0 link: 0
9262 13:56:22.096737 DRAM rank0 size:0x100000000,
9263 13:56:22.099222 DRAM rank1 size=0x100000000
9264 13:56:22.102704 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9265 13:56:22.106181 CPU: 00 missing read_resources
9266 13:56:22.109593 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9267 13:56:22.116131 Root Device read_resources bus 0 link: 0 done
9268 13:56:22.116239 Done reading resources.
9269 13:56:22.123075 Show resources in subtree (Root Device)...After reading.
9270 13:56:22.125716 Root Device child on link 0 CPU_CLUSTER: 0
9271 13:56:22.129640 CPU_CLUSTER: 0 child on link 0 CPU: 00
9272 13:56:22.139179 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9273 13:56:22.139263 CPU: 00
9274 13:56:22.142461 Root Device assign_resources, bus 0 link: 0
9275 13:56:22.145814 CPU_CLUSTER: 0 missing set_resources
9276 13:56:22.148807 Root Device assign_resources, bus 0 link: 0 done
9277 13:56:22.152615 Done setting resources.
9278 13:56:22.159187 Show resources in subtree (Root Device)...After assigning values.
9279 13:56:22.162084 Root Device child on link 0 CPU_CLUSTER: 0
9280 13:56:22.165436 CPU_CLUSTER: 0 child on link 0 CPU: 00
9281 13:56:22.175539 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9282 13:56:22.175625 CPU: 00
9283 13:56:22.178712 Done allocating resources.
9284 13:56:22.182422 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9285 13:56:22.185656 Enabling resources...
9286 13:56:22.185740 done.
9287 13:56:22.192312 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9288 13:56:22.192420 Initializing devices...
9289 13:56:22.195718 Root Device init
9290 13:56:22.195823 init hardware done!
9291 13:56:22.198988 0x00000018: ctrlr->caps
9292 13:56:22.202348 52.000 MHz: ctrlr->f_max
9293 13:56:22.202432 0.400 MHz: ctrlr->f_min
9294 13:56:22.205741 0x40ff8080: ctrlr->voltages
9295 13:56:22.205820 sclk: 390625
9296 13:56:22.209031 Bus Width = 1
9297 13:56:22.209112 sclk: 390625
9298 13:56:22.209177 Bus Width = 1
9299 13:56:22.212253 Early init status = 3
9300 13:56:22.219005 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9301 13:56:22.222151 in-header: 03 fc 00 00 01 00 00 00
9302 13:56:22.222246 in-data: 00
9303 13:56:22.228692 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9304 13:56:22.232043 in-header: 03 fd 00 00 00 00 00 00
9305 13:56:22.235436 in-data:
9306 13:56:22.238794 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9307 13:56:22.242104 in-header: 03 fc 00 00 01 00 00 00
9308 13:56:22.245321 in-data: 00
9309 13:56:22.248609 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9310 13:56:22.254063 in-header: 03 fd 00 00 00 00 00 00
9311 13:56:22.257258 in-data:
9312 13:56:22.260764 [SSUSB] Setting up USB HOST controller...
9313 13:56:22.263540 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9314 13:56:22.267412 [SSUSB] phy power-on done.
9315 13:56:22.270306 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9316 13:56:22.277506 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9317 13:56:22.280281 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9318 13:56:22.286850 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9319 13:56:22.293698 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9320 13:56:22.300046 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9321 13:56:22.307254 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9322 13:56:22.313697 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9323 13:56:22.317228 SPM: binary array size = 0x9dc
9324 13:56:22.320644 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9325 13:56:22.327346 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9326 13:56:22.333463 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9327 13:56:22.336810 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9328 13:56:22.343589 configure_display: Starting display init
9329 13:56:22.377630 anx7625_power_on_init: Init interface.
9330 13:56:22.380742 anx7625_disable_pd_protocol: Disabled PD feature.
9331 13:56:22.383630 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9332 13:56:22.411883 anx7625_start_dp_work: Secure OCM version=00
9333 13:56:22.414778 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9334 13:56:22.429314 sp_tx_get_edid_block: EDID Block = 1
9335 13:56:22.532463 Extracted contents:
9336 13:56:22.535517 header: 00 ff ff ff ff ff ff 00
9337 13:56:22.538710 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9338 13:56:22.542183 version: 01 04
9339 13:56:22.545336 basic params: 95 1f 11 78 0a
9340 13:56:22.548874 chroma info: 76 90 94 55 54 90 27 21 50 54
9341 13:56:22.552212 established: 00 00 00
9342 13:56:22.558677 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9343 13:56:22.562104 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9344 13:56:22.568967 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9345 13:56:22.575081 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9346 13:56:22.581793 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9347 13:56:22.585140 extensions: 00
9348 13:56:22.585230 checksum: fb
9349 13:56:22.585295
9350 13:56:22.588617 Manufacturer: IVO Model 57d Serial Number 0
9351 13:56:22.591848 Made week 0 of 2020
9352 13:56:22.591930 EDID version: 1.4
9353 13:56:22.595228 Digital display
9354 13:56:22.598870 6 bits per primary color channel
9355 13:56:22.598953 DisplayPort interface
9356 13:56:22.602304 Maximum image size: 31 cm x 17 cm
9357 13:56:22.605576 Gamma: 220%
9358 13:56:22.605657 Check DPMS levels
9359 13:56:22.608260 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9360 13:56:22.611689 First detailed timing is preferred timing
9361 13:56:22.615475 Established timings supported:
9362 13:56:22.618592 Standard timings supported:
9363 13:56:22.618673 Detailed timings
9364 13:56:22.625074 Hex of detail: 383680a07038204018303c0035ae10000019
9365 13:56:22.628380 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9366 13:56:22.635024 0780 0798 07c8 0820 hborder 0
9367 13:56:22.638611 0438 043b 0447 0458 vborder 0
9368 13:56:22.638693 -hsync -vsync
9369 13:56:22.642200 Did detailed timing
9370 13:56:22.645357 Hex of detail: 000000000000000000000000000000000000
9371 13:56:22.648605 Manufacturer-specified data, tag 0
9372 13:56:22.655337 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9373 13:56:22.655444 ASCII string: InfoVision
9374 13:56:22.662042 Hex of detail: 000000fe00523134304e574635205248200a
9375 13:56:22.665123 ASCII string: R140NWF5 RH
9376 13:56:22.665207 Checksum
9377 13:56:22.665272 Checksum: 0xfb (valid)
9378 13:56:22.671602 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9379 13:56:22.674926 DSI data_rate: 832800000 bps
9380 13:56:22.678286 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9381 13:56:22.682042 anx7625_parse_edid: pixelclock(138800).
9382 13:56:22.688926 hactive(1920), hsync(48), hfp(24), hbp(88)
9383 13:56:22.691661 vactive(1080), vsync(12), vfp(3), vbp(17)
9384 13:56:22.695104 anx7625_dsi_config: config dsi.
9385 13:56:22.701720 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9386 13:56:22.714177 anx7625_dsi_config: success to config DSI
9387 13:56:22.717530 anx7625_dp_start: MIPI phy setup OK.
9388 13:56:22.720867 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9389 13:56:22.724596 mtk_ddp_mode_set invalid vrefresh 60
9390 13:56:22.727765 main_disp_path_setup
9391 13:56:22.727842 ovl_layer_smi_id_en
9392 13:56:22.731328 ovl_layer_smi_id_en
9393 13:56:22.731403 ccorr_config
9394 13:56:22.731466 aal_config
9395 13:56:22.734419 gamma_config
9396 13:56:22.734494 postmask_config
9397 13:56:22.737786 dither_config
9398 13:56:22.740553 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9399 13:56:22.747721 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9400 13:56:22.750754 Root Device init finished in 552 msecs
9401 13:56:22.753796 CPU_CLUSTER: 0 init
9402 13:56:22.760908 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9403 13:56:22.764392 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9404 13:56:22.767074 APU_MBOX 0x190000b0 = 0x10001
9405 13:56:22.770474 APU_MBOX 0x190001b0 = 0x10001
9406 13:56:22.773961 APU_MBOX 0x190005b0 = 0x10001
9407 13:56:22.777197 APU_MBOX 0x190006b0 = 0x10001
9408 13:56:22.780526 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9409 13:56:22.793130 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9410 13:56:22.805930 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9411 13:56:22.812511 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9412 13:56:22.824111 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9413 13:56:22.833369 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9414 13:56:22.836628 CPU_CLUSTER: 0 init finished in 81 msecs
9415 13:56:22.839916 Devices initialized
9416 13:56:22.843411 Show all devs... After init.
9417 13:56:22.843493 Root Device: enabled 1
9418 13:56:22.846791 CPU_CLUSTER: 0: enabled 1
9419 13:56:22.850297 CPU: 00: enabled 1
9420 13:56:22.853461 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9421 13:56:22.856201 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9422 13:56:22.860133 ELOG: NV offset 0x57f000 size 0x1000
9423 13:56:22.866754 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9424 13:56:22.873492 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9425 13:56:22.876585 ELOG: Event(17) added with size 13 at 2024-02-01 13:53:41 UTC
9426 13:56:22.879931 out: cmd=0x121: 03 db 21 01 00 00 00 00
9427 13:56:22.883029 in-header: 03 9b 00 00 2c 00 00 00
9428 13:56:22.896463 in-data: c4 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9429 13:56:22.903028 ELOG: Event(A1) added with size 10 at 2024-02-01 13:53:41 UTC
9430 13:56:22.910145 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9431 13:56:22.916177 ELOG: Event(A0) added with size 9 at 2024-02-01 13:53:41 UTC
9432 13:56:22.920025 elog_add_boot_reason: Logged dev mode boot
9433 13:56:22.923164 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9434 13:56:22.926587 Finalize devices...
9435 13:56:22.926669 Devices finalized
9436 13:56:22.933258 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9437 13:56:22.936359 Writing coreboot table at 0xffe64000
9438 13:56:22.939647 0. 000000000010a000-0000000000113fff: RAMSTAGE
9439 13:56:22.942896 1. 0000000040000000-00000000400fffff: RAM
9440 13:56:22.949413 2. 0000000040100000-000000004032afff: RAMSTAGE
9441 13:56:22.952822 3. 000000004032b000-00000000545fffff: RAM
9442 13:56:22.956213 4. 0000000054600000-000000005465ffff: BL31
9443 13:56:22.959577 5. 0000000054660000-00000000ffe63fff: RAM
9444 13:56:22.966321 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9445 13:56:22.969771 7. 0000000100000000-000000023fffffff: RAM
9446 13:56:22.969864 Passing 5 GPIOs to payload:
9447 13:56:22.975799 NAME | PORT | POLARITY | VALUE
9448 13:56:22.979831 EC in RW | 0x000000aa | low | undefined
9449 13:56:22.985969 EC interrupt | 0x00000005 | low | undefined
9450 13:56:22.989582 TPM interrupt | 0x000000ab | high | undefined
9451 13:56:22.992665 SD card detect | 0x00000011 | high | undefined
9452 13:56:22.999486 speaker enable | 0x00000093 | high | undefined
9453 13:56:23.002856 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9454 13:56:23.006236 in-header: 03 f9 00 00 02 00 00 00
9455 13:56:23.006346 in-data: 02 00
9456 13:56:23.009637 ADC[4]: Raw value=904357 ID=7
9457 13:56:23.012359 ADC[3]: Raw value=213441 ID=1
9458 13:56:23.012460 RAM Code: 0x71
9459 13:56:23.015777 ADC[6]: Raw value=75701 ID=0
9460 13:56:23.019156 ADC[5]: Raw value=213072 ID=1
9461 13:56:23.019266 SKU Code: 0x1
9462 13:56:23.025687 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum fb11
9463 13:56:23.029404 coreboot table: 964 bytes.
9464 13:56:23.032454 IMD ROOT 0. 0xfffff000 0x00001000
9465 13:56:23.035782 IMD SMALL 1. 0xffffe000 0x00001000
9466 13:56:23.039028 RO MCACHE 2. 0xffffc000 0x00001104
9467 13:56:23.042181 CONSOLE 3. 0xfff7c000 0x00080000
9468 13:56:23.045793 FMAP 4. 0xfff7b000 0x00000452
9469 13:56:23.049043 TIME STAMP 5. 0xfff7a000 0x00000910
9470 13:56:23.052676 VBOOT WORK 6. 0xfff66000 0x00014000
9471 13:56:23.056016 RAMOOPS 7. 0xffe66000 0x00100000
9472 13:56:23.059030 COREBOOT 8. 0xffe64000 0x00002000
9473 13:56:23.059114 IMD small region:
9474 13:56:23.062244 IMD ROOT 0. 0xffffec00 0x00000400
9475 13:56:23.065764 VPD 1. 0xffffeb80 0x0000006c
9476 13:56:23.069012 MMC STATUS 2. 0xffffeb60 0x00000004
9477 13:56:23.075774 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9478 13:56:23.079245 Probing TPM: done!
9479 13:56:23.082584 Connected to device vid:did:rid of 1ae0:0028:00
9480 13:56:23.092427 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9481 13:56:23.095665 Initialized TPM device CR50 revision 0
9482 13:56:23.100046 Checking cr50 for pending updates
9483 13:56:23.103022 Reading cr50 TPM mode
9484 13:56:23.111685 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9485 13:56:23.117880 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9486 13:56:23.158173 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9487 13:56:23.161583 Checking segment from ROM address 0x40100000
9488 13:56:23.164981 Checking segment from ROM address 0x4010001c
9489 13:56:23.171368 Loading segment from ROM address 0x40100000
9490 13:56:23.171453 code (compression=0)
9491 13:56:23.178044 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9492 13:56:23.188924 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9493 13:56:23.189042 it's not compressed!
9494 13:56:23.194995 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9495 13:56:23.198138 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9496 13:56:23.218459 Loading segment from ROM address 0x4010001c
9497 13:56:23.218579 Entry Point 0x80000000
9498 13:56:23.221963 Loaded segments
9499 13:56:23.225413 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9500 13:56:23.232181 Jumping to boot code at 0x80000000(0xffe64000)
9501 13:56:23.238294 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9502 13:56:23.245075 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9503 13:56:23.253321 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9504 13:56:23.256751 Checking segment from ROM address 0x40100000
9505 13:56:23.259915 Checking segment from ROM address 0x4010001c
9506 13:56:23.266258 Loading segment from ROM address 0x40100000
9507 13:56:23.266344 code (compression=1)
9508 13:56:23.273178 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9509 13:56:23.283210 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9510 13:56:23.283297 using LZMA
9511 13:56:23.291432 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9512 13:56:23.298085 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9513 13:56:23.301125 Loading segment from ROM address 0x4010001c
9514 13:56:23.301209 Entry Point 0x54601000
9515 13:56:23.304706 Loaded segments
9516 13:56:23.307627 NOTICE: MT8192 bl31_setup
9517 13:56:23.314825 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9518 13:56:23.318461 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9519 13:56:23.321689 WARNING: region 0:
9520 13:56:23.325395 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 13:56:23.325504 WARNING: region 1:
9522 13:56:23.331845 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9523 13:56:23.335074 WARNING: region 2:
9524 13:56:23.338167 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9525 13:56:23.342066 WARNING: region 3:
9526 13:56:23.345609 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9527 13:56:23.348837 WARNING: region 4:
9528 13:56:23.351569 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9529 13:56:23.354997 WARNING: region 5:
9530 13:56:23.358498 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 13:56:23.361882 WARNING: region 6:
9532 13:56:23.365213 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 13:56:23.365317 WARNING: region 7:
9534 13:56:23.372024 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 13:56:23.378938 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9536 13:56:23.381607 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9537 13:56:23.385101 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9538 13:56:23.391768 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9539 13:56:23.395177 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9540 13:56:23.398627 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9541 13:56:23.405210 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9542 13:56:23.408570 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9543 13:56:23.411928 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9544 13:56:23.418318 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9545 13:56:23.421923 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9546 13:56:23.428684 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9547 13:56:23.431828 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9548 13:56:23.435305 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9549 13:56:23.441596 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9550 13:56:23.445012 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9551 13:56:23.448460 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9552 13:56:23.455252 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9553 13:56:23.458663 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9554 13:56:23.461729 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9555 13:56:23.468477 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9556 13:56:23.471605 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9557 13:56:23.478711 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9558 13:56:23.481554 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9559 13:56:23.488314 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9560 13:56:23.491641 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9561 13:56:23.495662 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9562 13:56:23.501844 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9563 13:56:23.505282 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9564 13:56:23.508749 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9565 13:56:23.515339 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9566 13:56:23.518694 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9567 13:56:23.522046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9568 13:56:23.528747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9569 13:56:23.532579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9570 13:56:23.535689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9571 13:56:23.539041 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9572 13:56:23.545677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9573 13:56:23.549228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9574 13:56:23.552419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9575 13:56:23.555833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9576 13:56:23.559119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9577 13:56:23.566031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9578 13:56:23.569052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9579 13:56:23.572765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9580 13:56:23.578938 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9581 13:56:23.582136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9582 13:56:23.585935 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9583 13:56:23.592617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9584 13:56:23.596052 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9585 13:56:23.599418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9586 13:56:23.605535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9587 13:56:23.608980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9588 13:56:23.615689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9589 13:56:23.618930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9590 13:56:23.622243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9591 13:56:23.629041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9592 13:56:23.632376 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9593 13:56:23.639067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9594 13:56:23.642437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9595 13:56:23.649009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9596 13:56:23.652901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9597 13:56:23.659089 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9598 13:56:23.662256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9599 13:56:23.665429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9600 13:56:23.672604 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9601 13:56:23.676088 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9602 13:56:23.682390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9603 13:56:23.685610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9604 13:56:23.689389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9605 13:56:23.695972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9606 13:56:23.699317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9607 13:56:23.705664 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9608 13:56:23.709296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9609 13:56:23.715845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9610 13:56:23.718970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9611 13:56:23.726178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9612 13:56:23.728993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9613 13:56:23.732404 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9614 13:56:23.739279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9615 13:56:23.742492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9616 13:56:23.749247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9617 13:56:23.752520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9618 13:56:23.759225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9619 13:56:23.762497 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9620 13:56:23.765727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9621 13:56:23.772358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9622 13:56:23.775928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9623 13:56:23.783042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9624 13:56:23.786420 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9625 13:56:23.789204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9626 13:56:23.796199 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9627 13:56:23.799460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9628 13:56:23.806038 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9629 13:56:23.809445 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9630 13:56:23.816135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9631 13:56:23.819357 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9632 13:56:23.822814 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9633 13:56:23.826108 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9634 13:56:23.833097 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9635 13:56:23.836141 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9636 13:56:23.839478 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9637 13:56:23.846402 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9638 13:56:23.849877 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9639 13:56:23.856087 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9640 13:56:23.859817 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9641 13:56:23.862871 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9642 13:56:23.869851 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9643 13:56:23.873080 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9644 13:56:23.876398 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9645 13:56:23.883328 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9646 13:56:23.886234 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9647 13:56:23.892903 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9648 13:56:23.896155 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9649 13:56:23.899452 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9650 13:56:23.906486 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9651 13:56:23.909841 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9652 13:56:23.913175 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9653 13:56:23.919922 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9654 13:56:23.923233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9655 13:56:23.926477 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9656 13:56:23.929823 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9657 13:56:23.933113 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9658 13:56:23.939818 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9659 13:56:23.943214 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9660 13:56:23.949796 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9661 13:56:23.953302 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9662 13:56:23.956851 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9663 13:56:23.963024 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9664 13:56:23.966499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9665 13:56:23.969738 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9666 13:56:23.976609 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9667 13:56:23.979770 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9668 13:56:23.986870 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9669 13:56:23.990205 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9670 13:56:23.993114 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9671 13:56:23.999935 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9672 13:56:24.003517 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9673 13:56:24.009775 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9674 13:56:24.013356 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9675 13:56:24.016850 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9676 13:56:24.023295 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9677 13:56:24.026701 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9678 13:56:24.033341 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9679 13:56:24.036767 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9680 13:56:24.040239 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9681 13:56:24.046934 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9682 13:56:24.050159 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9683 13:56:24.053444 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9684 13:56:24.060145 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9685 13:56:24.063616 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9686 13:56:24.066824 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9687 13:56:24.073431 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9688 13:56:24.076778 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9689 13:56:24.083699 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9690 13:56:24.087256 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9691 13:56:24.090336 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9692 13:56:24.096901 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9693 13:56:24.100218 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9694 13:56:24.106780 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9695 13:56:24.110267 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9696 13:56:24.113535 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9697 13:56:24.120011 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9698 13:56:24.123491 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9699 13:56:24.130057 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9700 13:56:24.133587 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9701 13:56:24.136614 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9702 13:56:24.143207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9703 13:56:24.147008 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9704 13:56:24.150229 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9705 13:56:24.156819 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9706 13:56:24.160200 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9707 13:56:24.166743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9708 13:56:24.169966 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9709 13:56:24.173170 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9710 13:56:24.179874 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9711 13:56:24.183409 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9712 13:56:24.189963 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9713 13:56:24.193167 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9714 13:56:24.196552 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9715 13:56:24.203066 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9716 13:56:24.206893 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9717 13:56:24.213274 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9718 13:56:24.216635 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9719 13:56:24.219928 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9720 13:56:24.226472 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9721 13:56:24.230018 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9722 13:56:24.236313 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9723 13:56:24.240041 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9724 13:56:24.243262 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9725 13:56:24.249789 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9726 13:56:24.253101 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9727 13:56:24.259911 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9728 13:56:24.263105 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9729 13:56:24.266162 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9730 13:56:24.272991 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9731 13:56:24.276265 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9732 13:56:24.283018 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9733 13:56:24.286358 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9734 13:56:24.293084 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9735 13:56:24.296469 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9736 13:56:24.299641 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9737 13:56:24.306366 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9738 13:56:24.309662 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9739 13:56:24.315777 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9740 13:56:24.319603 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9741 13:56:24.322983 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9742 13:56:24.329676 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9743 13:56:24.332367 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9744 13:56:24.339494 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9745 13:56:24.342608 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9746 13:56:24.349502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9747 13:56:24.352716 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9748 13:56:24.355951 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9749 13:56:24.362905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9750 13:56:24.366328 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9751 13:56:24.372842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9752 13:56:24.376228 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9753 13:56:24.379523 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9754 13:56:24.385934 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9755 13:56:24.389354 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9756 13:56:24.395970 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9757 13:56:24.399261 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9758 13:56:24.402540 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9759 13:56:24.409668 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9760 13:56:24.413109 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9761 13:56:24.419570 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9762 13:56:24.422664 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9763 13:56:24.425976 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9764 13:56:24.432546 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9765 13:56:24.435956 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9766 13:56:24.439311 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9767 13:56:24.442610 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9768 13:56:24.449274 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9769 13:56:24.452672 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9770 13:56:24.455768 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9771 13:56:24.462700 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9772 13:56:24.465640 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9773 13:56:24.469139 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9774 13:56:24.475876 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9775 13:56:24.479217 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9776 13:56:24.485925 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9777 13:56:24.489313 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9778 13:56:24.492412 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9779 13:56:24.498843 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9780 13:56:24.502128 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9781 13:56:24.505829 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9782 13:56:24.512257 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9783 13:56:24.515742 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9784 13:56:24.519391 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9785 13:56:24.525824 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9786 13:56:24.529016 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9787 13:56:24.535664 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9788 13:56:24.539000 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9789 13:56:24.542376 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9790 13:56:24.548965 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9791 13:56:24.552392 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9792 13:56:24.555606 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9793 13:56:24.562205 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9794 13:56:24.565476 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9795 13:56:24.568759 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9796 13:56:24.575137 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9797 13:56:24.578785 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9798 13:56:24.585502 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9799 13:56:24.588966 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9800 13:56:24.591979 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9801 13:56:24.598456 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9802 13:56:24.601907 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9803 13:56:24.605136 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9804 13:56:24.612352 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9805 13:56:24.615495 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9806 13:56:24.618669 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9807 13:56:24.621669 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9808 13:56:24.625332 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9809 13:56:24.631949 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9810 13:56:24.634916 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9811 13:56:24.638385 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9812 13:56:24.641752 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9813 13:56:24.648755 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9814 13:56:24.651928 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9815 13:56:24.654681 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9816 13:56:24.661331 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9817 13:56:24.664796 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9818 13:56:24.668172 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9819 13:56:24.674768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9820 13:56:24.678204 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9821 13:56:24.684674 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9822 13:56:24.687955 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9823 13:56:24.694889 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9824 13:56:24.697857 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9825 13:56:24.701105 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9826 13:56:24.707964 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9827 13:56:24.711351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9828 13:56:24.718129 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9829 13:56:24.721578 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9830 13:56:24.724269 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9831 13:56:24.731048 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9832 13:56:24.734404 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9833 13:56:24.740878 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9834 13:56:24.744413 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9835 13:56:24.747660 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9836 13:56:24.754414 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9837 13:56:24.757793 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9838 13:56:24.764325 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9839 13:56:24.768118 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9840 13:56:24.771115 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9841 13:56:24.778060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9842 13:56:24.781539 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9843 13:56:24.788125 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9844 13:56:24.791591 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9845 13:56:24.794794 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9846 13:56:24.800926 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9847 13:56:24.804299 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9848 13:56:24.811023 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9849 13:56:24.814960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9850 13:56:24.817743 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9851 13:56:24.824328 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9852 13:56:24.827653 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9853 13:56:24.834607 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9854 13:56:24.838197 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9855 13:56:24.844784 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9856 13:56:24.848004 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9857 13:56:24.851178 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9858 13:56:24.858019 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9859 13:56:24.861314 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9860 13:56:24.867622 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9861 13:56:24.870804 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9862 13:56:24.873938 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9863 13:56:24.880618 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9864 13:56:24.884032 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9865 13:56:24.890678 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9866 13:56:24.894003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9867 13:56:24.897606 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9868 13:56:24.904299 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9869 13:56:24.907164 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9870 13:56:24.913853 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9871 13:56:24.917163 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9872 13:56:24.920721 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9873 13:56:24.927433 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9874 13:56:24.930508 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9875 13:56:24.937340 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9876 13:56:24.940704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9877 13:56:24.947268 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9878 13:56:24.950809 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9879 13:56:24.954254 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9880 13:56:24.960737 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9881 13:56:24.963838 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9882 13:56:24.970323 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9883 13:56:24.973740 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9884 13:56:24.977132 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9885 13:56:24.983709 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9886 13:56:24.987136 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9887 13:56:24.993908 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9888 13:56:24.996825 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9889 13:56:25.000187 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9890 13:56:25.007636 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9891 13:56:25.010644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9892 13:56:25.017409 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9893 13:56:25.020703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9894 13:56:25.027449 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9895 13:56:25.030176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9896 13:56:25.033567 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9897 13:56:25.040358 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9898 13:56:25.043705 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9899 13:56:25.050582 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9900 13:56:25.053527 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9901 13:56:25.060331 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9902 13:56:25.063710 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9903 13:56:25.067211 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9904 13:56:25.073724 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9905 13:56:25.076848 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9906 13:56:25.084054 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9907 13:56:25.087303 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9908 13:56:25.093468 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9909 13:56:25.096983 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9910 13:56:25.100234 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9911 13:56:25.106958 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9912 13:56:25.110300 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9913 13:56:25.117287 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9914 13:56:25.120104 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9915 13:56:25.126903 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9916 13:56:25.130285 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9917 13:56:25.133332 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9918 13:56:25.139959 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9919 13:56:25.144001 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9920 13:56:25.150666 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9921 13:56:25.153828 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9922 13:56:25.160389 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9923 13:56:25.163545 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9924 13:56:25.166764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9925 13:56:25.173612 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9926 13:56:25.177056 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9927 13:56:25.183575 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9928 13:56:25.186773 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9929 13:56:25.193680 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9930 13:56:25.196744 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9931 13:56:25.200006 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9932 13:56:25.206813 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9933 13:56:25.210060 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9934 13:56:25.216833 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9935 13:56:25.220232 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9936 13:56:25.226343 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9937 13:56:25.229572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9938 13:56:25.233344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9939 13:56:25.239549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9940 13:56:25.243227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9941 13:56:25.249551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9942 13:56:25.252837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9943 13:56:25.259686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9944 13:56:25.262905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9945 13:56:25.269798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9946 13:56:25.272858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9947 13:56:25.280005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9948 13:56:25.283240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9949 13:56:25.289804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9950 13:56:25.293042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9951 13:56:25.299679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9952 13:56:25.302811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9953 13:56:25.309591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9954 13:56:25.312894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9955 13:56:25.319508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9956 13:56:25.322802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9957 13:56:25.326308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9958 13:56:25.333119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9959 13:56:25.336580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9960 13:56:25.342618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9961 13:56:25.346603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9962 13:56:25.352722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9963 13:56:25.359188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9964 13:56:25.363209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9965 13:56:25.369469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9966 13:56:25.372622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9967 13:56:25.379393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9968 13:56:25.382615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9969 13:56:25.385747 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9970 13:56:25.389190 INFO: [APUAPC] vio 0
9971 13:56:25.392270 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9972 13:56:25.399468 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9973 13:56:25.402892 INFO: [APUAPC] D0_APC_0: 0x400510
9974 13:56:25.406414 INFO: [APUAPC] D0_APC_1: 0x0
9975 13:56:25.409641 INFO: [APUAPC] D0_APC_2: 0x1540
9976 13:56:25.409721 INFO: [APUAPC] D0_APC_3: 0x0
9977 13:56:25.412770 INFO: [APUAPC] D1_APC_0: 0xffffffff
9978 13:56:25.419069 INFO: [APUAPC] D1_APC_1: 0xffffffff
9979 13:56:25.419179 INFO: [APUAPC] D1_APC_2: 0x3fffff
9980 13:56:25.422391 INFO: [APUAPC] D1_APC_3: 0x0
9981 13:56:25.425815 INFO: [APUAPC] D2_APC_0: 0xffffffff
9982 13:56:25.429403 INFO: [APUAPC] D2_APC_1: 0xffffffff
9983 13:56:25.432782 INFO: [APUAPC] D2_APC_2: 0x3fffff
9984 13:56:25.436057 INFO: [APUAPC] D2_APC_3: 0x0
9985 13:56:25.439347 INFO: [APUAPC] D3_APC_0: 0xffffffff
9986 13:56:25.442847 INFO: [APUAPC] D3_APC_1: 0xffffffff
9987 13:56:25.445858 INFO: [APUAPC] D3_APC_2: 0x3fffff
9988 13:56:25.449500 INFO: [APUAPC] D3_APC_3: 0x0
9989 13:56:25.452710 INFO: [APUAPC] D4_APC_0: 0xffffffff
9990 13:56:25.456093 INFO: [APUAPC] D4_APC_1: 0xffffffff
9991 13:56:25.458931 INFO: [APUAPC] D4_APC_2: 0x3fffff
9992 13:56:25.462323 INFO: [APUAPC] D4_APC_3: 0x0
9993 13:56:25.465787 INFO: [APUAPC] D5_APC_0: 0xffffffff
9994 13:56:25.469211 INFO: [APUAPC] D5_APC_1: 0xffffffff
9995 13:56:25.472596 INFO: [APUAPC] D5_APC_2: 0x3fffff
9996 13:56:25.475920 INFO: [APUAPC] D5_APC_3: 0x0
9997 13:56:25.479472 INFO: [APUAPC] D6_APC_0: 0xffffffff
9998 13:56:25.482259 INFO: [APUAPC] D6_APC_1: 0xffffffff
9999 13:56:25.485706 INFO: [APUAPC] D6_APC_2: 0x3fffff
10000 13:56:25.488714 INFO: [APUAPC] D6_APC_3: 0x0
10001 13:56:25.492055 INFO: [APUAPC] D7_APC_0: 0xffffffff
10002 13:56:25.495252 INFO: [APUAPC] D7_APC_1: 0xffffffff
10003 13:56:25.498699 INFO: [APUAPC] D7_APC_2: 0x3fffff
10004 13:56:25.501877 INFO: [APUAPC] D7_APC_3: 0x0
10005 13:56:25.505801 INFO: [APUAPC] D8_APC_0: 0xffffffff
10006 13:56:25.508553 INFO: [APUAPC] D8_APC_1: 0xffffffff
10007 13:56:25.512113 INFO: [APUAPC] D8_APC_2: 0x3fffff
10008 13:56:25.515412 INFO: [APUAPC] D8_APC_3: 0x0
10009 13:56:25.518763 INFO: [APUAPC] D9_APC_0: 0xffffffff
10010 13:56:25.521925 INFO: [APUAPC] D9_APC_1: 0xffffffff
10011 13:56:25.525291 INFO: [APUAPC] D9_APC_2: 0x3fffff
10012 13:56:25.528938 INFO: [APUAPC] D9_APC_3: 0x0
10013 13:56:25.531964 INFO: [APUAPC] D10_APC_0: 0xffffffff
10014 13:56:25.535735 INFO: [APUAPC] D10_APC_1: 0xffffffff
10015 13:56:25.539036 INFO: [APUAPC] D10_APC_2: 0x3fffff
10016 13:56:25.542135 INFO: [APUAPC] D10_APC_3: 0x0
10017 13:56:25.545604 INFO: [APUAPC] D11_APC_0: 0xffffffff
10018 13:56:25.548303 INFO: [APUAPC] D11_APC_1: 0xffffffff
10019 13:56:25.551734 INFO: [APUAPC] D11_APC_2: 0x3fffff
10020 13:56:25.555312 INFO: [APUAPC] D11_APC_3: 0x0
10021 13:56:25.558656 INFO: [APUAPC] D12_APC_0: 0xffffffff
10022 13:56:25.561985 INFO: [APUAPC] D12_APC_1: 0xffffffff
10023 13:56:25.565556 INFO: [APUAPC] D12_APC_2: 0x3fffff
10024 13:56:25.568211 INFO: [APUAPC] D12_APC_3: 0x0
10025 13:56:25.571636 INFO: [APUAPC] D13_APC_0: 0xffffffff
10026 13:56:25.575206 INFO: [APUAPC] D13_APC_1: 0xffffffff
10027 13:56:25.578679 INFO: [APUAPC] D13_APC_2: 0x3fffff
10028 13:56:25.582116 INFO: [APUAPC] D13_APC_3: 0x0
10029 13:56:25.584910 INFO: [APUAPC] D14_APC_0: 0xffffffff
10030 13:56:25.588349 INFO: [APUAPC] D14_APC_1: 0xffffffff
10031 13:56:25.591769 INFO: [APUAPC] D14_APC_2: 0x3fffff
10032 13:56:25.595060 INFO: [APUAPC] D14_APC_3: 0x0
10033 13:56:25.598147 INFO: [APUAPC] D15_APC_0: 0xffffffff
10034 13:56:25.601441 INFO: [APUAPC] D15_APC_1: 0xffffffff
10035 13:56:25.604932 INFO: [APUAPC] D15_APC_2: 0x3fffff
10036 13:56:25.608658 INFO: [APUAPC] D15_APC_3: 0x0
10037 13:56:25.611734 INFO: [APUAPC] APC_CON: 0x4
10038 13:56:25.615407 INFO: [NOCDAPC] D0_APC_0: 0x0
10039 13:56:25.615514 INFO: [NOCDAPC] D0_APC_1: 0x0
10040 13:56:25.618550 INFO: [NOCDAPC] D1_APC_0: 0x0
10041 13:56:25.622060 INFO: [NOCDAPC] D1_APC_1: 0xfff
10042 13:56:25.625284 INFO: [NOCDAPC] D2_APC_0: 0x0
10043 13:56:25.628485 INFO: [NOCDAPC] D2_APC_1: 0xfff
10044 13:56:25.632264 INFO: [NOCDAPC] D3_APC_0: 0x0
10045 13:56:25.634826 INFO: [NOCDAPC] D3_APC_1: 0xfff
10046 13:56:25.638417 INFO: [NOCDAPC] D4_APC_0: 0x0
10047 13:56:25.641706 INFO: [NOCDAPC] D4_APC_1: 0xfff
10048 13:56:25.645128 INFO: [NOCDAPC] D5_APC_0: 0x0
10049 13:56:25.648364 INFO: [NOCDAPC] D5_APC_1: 0xfff
10050 13:56:25.648475 INFO: [NOCDAPC] D6_APC_0: 0x0
10051 13:56:25.651209 INFO: [NOCDAPC] D6_APC_1: 0xfff
10052 13:56:25.654782 INFO: [NOCDAPC] D7_APC_0: 0x0
10053 13:56:25.658080 INFO: [NOCDAPC] D7_APC_1: 0xfff
10054 13:56:25.661506 INFO: [NOCDAPC] D8_APC_0: 0x0
10055 13:56:25.664813 INFO: [NOCDAPC] D8_APC_1: 0xfff
10056 13:56:25.668330 INFO: [NOCDAPC] D9_APC_0: 0x0
10057 13:56:25.671654 INFO: [NOCDAPC] D9_APC_1: 0xfff
10058 13:56:25.674423 INFO: [NOCDAPC] D10_APC_0: 0x0
10059 13:56:25.677869 INFO: [NOCDAPC] D10_APC_1: 0xfff
10060 13:56:25.681277 INFO: [NOCDAPC] D11_APC_0: 0x0
10061 13:56:25.684553 INFO: [NOCDAPC] D11_APC_1: 0xfff
10062 13:56:25.684655 INFO: [NOCDAPC] D12_APC_0: 0x0
10063 13:56:25.687938 INFO: [NOCDAPC] D12_APC_1: 0xfff
10064 13:56:25.691269 INFO: [NOCDAPC] D13_APC_0: 0x0
10065 13:56:25.694658 INFO: [NOCDAPC] D13_APC_1: 0xfff
10066 13:56:25.698033 INFO: [NOCDAPC] D14_APC_0: 0x0
10067 13:56:25.701714 INFO: [NOCDAPC] D14_APC_1: 0xfff
10068 13:56:25.704606 INFO: [NOCDAPC] D15_APC_0: 0x0
10069 13:56:25.708231 INFO: [NOCDAPC] D15_APC_1: 0xfff
10070 13:56:25.711522 INFO: [NOCDAPC] APC_CON: 0x4
10071 13:56:25.714816 INFO: [APUAPC] set_apusys_apc done
10072 13:56:25.718021 INFO: [DEVAPC] devapc_init done
10073 13:56:25.721059 INFO: GICv3 without legacy support detected.
10074 13:56:25.724426 INFO: ARM GICv3 driver initialized in EL3
10075 13:56:25.727761 INFO: Maximum SPI INTID supported: 639
10076 13:56:25.734705 INFO: BL31: Initializing runtime services
10077 13:56:25.737687 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10078 13:56:25.740975 INFO: SPM: enable CPC mode
10079 13:56:25.747778 INFO: mcdi ready for mcusys-off-idle and system suspend
10080 13:56:25.750960 INFO: BL31: Preparing for EL3 exit to normal world
10081 13:56:25.754585 INFO: Entry point address = 0x80000000
10082 13:56:25.757861 INFO: SPSR = 0x8
10083 13:56:25.763592
10084 13:56:25.763695
10085 13:56:25.763786
10086 13:56:25.766329 Starting depthcharge on Spherion...
10087 13:56:25.766454
10088 13:56:25.766518 Wipe memory regions:
10089 13:56:25.766578
10090 13:56:25.767251 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10091 13:56:25.767353 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10092 13:56:25.767685 Setting prompt string to ['asurada:']
10093 13:56:25.767772 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10094 13:56:25.769853 [0x00000040000000, 0x00000054600000)
10095 13:56:25.891740
10096 13:56:25.891889 [0x00000054660000, 0x00000080000000)
10097 13:56:26.152517
10098 13:56:26.152646 [0x000000821a7280, 0x000000ffe64000)
10099 13:56:26.896124
10100 13:56:26.896310 [0x00000100000000, 0x00000240000000)
10101 13:56:28.784004
10102 13:56:28.787310 Initializing XHCI USB controller at 0x11200000.
10103 13:56:29.825432
10104 13:56:29.828756 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10105 13:56:29.828865
10106 13:56:29.828933
10107 13:56:29.828995
10108 13:56:29.829280 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10110 13:56:29.929661 asurada: tftpboot 192.168.201.1 12682934/tftp-deploy-4nfmyslk/kernel/image.itb 12682934/tftp-deploy-4nfmyslk/kernel/cmdline
10111 13:56:29.929818 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10112 13:56:29.929926 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10113 13:56:29.934342 tftpboot 192.168.201.1 12682934/tftp-deploy-4nfmyslk/kernel/image.ittp-deploy-4nfmyslk/kernel/cmdline
10114 13:56:29.934424
10115 13:56:29.934503 Waiting for link
10116 13:56:30.094385
10117 13:56:30.094530 R8152: Initializing
10118 13:56:30.094599
10119 13:56:30.097702 Version 9 (ocp_data = 6010)
10120 13:56:30.097784
10121 13:56:30.100818 R8152: Done initializing
10122 13:56:30.100900
10123 13:56:30.100965 Adding net device
10124 13:56:32.047016
10125 13:56:32.047179 done.
10126 13:56:32.047279
10127 13:56:32.047375 MAC: 00:e0:4c:78:7a:aa
10128 13:56:32.047466
10129 13:56:32.049921 Sending DHCP discover... done.
10130 13:56:32.050023
10131 13:56:32.053248 Waiting for reply... done.
10132 13:56:32.053354
10133 13:56:32.056615 Sending DHCP request... done.
10134 13:56:32.056690
10135 13:56:32.056769 Waiting for reply... done.
10136 13:56:32.056857
10137 13:56:32.060216 My ip is 192.168.201.12
10138 13:56:32.060319
10139 13:56:32.063503 The DHCP server ip is 192.168.201.1
10140 13:56:32.063576
10141 13:56:32.066728 TFTP server IP predefined by user: 192.168.201.1
10142 13:56:32.066801
10143 13:56:32.073547 Bootfile predefined by user: 12682934/tftp-deploy-4nfmyslk/kernel/image.itb
10144 13:56:32.073648
10145 13:56:32.076222 Sending tftp read request... done.
10146 13:56:32.076324
10147 13:56:32.080086 Waiting for the transfer...
10148 13:56:32.080207
10149 13:56:32.340919 00000000 ################################################################
10150 13:56:32.341054
10151 13:56:32.593488 00080000 ################################################################
10152 13:56:32.593653
10153 13:56:32.856660 00100000 ################################################################
10154 13:56:32.856794
10155 13:56:33.117810 00180000 ################################################################
10156 13:56:33.117974
10157 13:56:33.382436 00200000 ################################################################
10158 13:56:33.382588
10159 13:56:33.640215 00280000 ################################################################
10160 13:56:33.640371
10161 13:56:33.902740 00300000 ################################################################
10162 13:56:33.902881
10163 13:56:34.161491 00380000 ################################################################
10164 13:56:34.161645
10165 13:56:34.419400 00400000 ################################################################
10166 13:56:34.419570
10167 13:56:34.677882 00480000 ################################################################
10168 13:56:34.678016
10169 13:56:34.952134 00500000 ################################################################
10170 13:56:34.952266
10171 13:56:35.206708 00580000 ################################################################
10172 13:56:35.206869
10173 13:56:35.490151 00600000 ################################################################
10174 13:56:35.490310
10175 13:56:35.754321 00680000 ################################################################
10176 13:56:35.754457
10177 13:56:36.013221 00700000 ################################################################
10178 13:56:36.013357
10179 13:56:36.261764 00780000 ################################################################
10180 13:56:36.261901
10181 13:56:36.508083 00800000 ################################################################
10182 13:56:36.508250
10183 13:56:36.772985 00880000 ################################################################
10184 13:56:36.773133
10185 13:56:37.059439 00900000 ################################################################
10186 13:56:37.059588
10187 13:56:37.333188 00980000 ################################################################
10188 13:56:37.333347
10189 13:56:37.617906 00a00000 ################################################################
10190 13:56:37.618055
10191 13:56:37.894228 00a80000 ################################################################
10192 13:56:37.894413
10193 13:56:38.164565 00b00000 ################################################################
10194 13:56:38.164700
10195 13:56:38.419978 00b80000 ################################################################
10196 13:56:38.420131
10197 13:56:38.696348 00c00000 ################################################################
10198 13:56:38.696494
10199 13:56:38.965598 00c80000 ################################################################
10200 13:56:38.965742
10201 13:56:39.241829 00d00000 ################################################################
10202 13:56:39.241997
10203 13:56:39.518439 00d80000 ################################################################
10204 13:56:39.518590
10205 13:56:39.808008 00e00000 ################################################################
10206 13:56:39.808157
10207 13:56:40.094876 00e80000 ################################################################
10208 13:56:40.095041
10209 13:56:40.363963 00f00000 ################################################################
10210 13:56:40.364111
10211 13:56:40.640554 00f80000 ################################################################
10212 13:56:40.640700
10213 13:56:40.928658 01000000 ################################################################
10214 13:56:40.928808
10215 13:56:41.205731 01080000 ################################################################
10216 13:56:41.205900
10217 13:56:41.479310 01100000 ################################################################
10218 13:56:41.479473
10219 13:56:41.741316 01180000 ################################################################
10220 13:56:41.741461
10221 13:56:42.024073 01200000 ################################################################
10222 13:56:42.024237
10223 13:56:42.275746 01280000 ################################################################
10224 13:56:42.275884
10225 13:56:42.532662 01300000 ################################################################
10226 13:56:42.532803
10227 13:56:42.803926 01380000 ################################################################
10228 13:56:42.804072
10229 13:56:43.085029 01400000 ################################################################
10230 13:56:43.085175
10231 13:56:43.371251 01480000 ################################################################
10232 13:56:43.371388
10233 13:56:43.650445 01500000 ################################################################
10234 13:56:43.650618
10235 13:56:43.936175 01580000 ################################################################
10236 13:56:43.936415
10237 13:56:44.229880 01600000 ################################################################
10238 13:56:44.230028
10239 13:56:44.507187 01680000 ################################################################
10240 13:56:44.507357
10241 13:56:44.778626 01700000 ################################################################
10242 13:56:44.778769
10243 13:56:45.031735 01780000 ################################################################
10244 13:56:45.031907
10245 13:56:45.305119 01800000 ################################################################
10246 13:56:45.305266
10247 13:56:45.577611 01880000 ################################################################
10248 13:56:45.577768
10249 13:56:45.834285 01900000 ################################################################
10250 13:56:45.834433
10251 13:56:46.105840 01980000 ################################################################
10252 13:56:46.105987
10253 13:56:46.387400 01a00000 ################################################################
10254 13:56:46.387587
10255 13:56:46.678002 01a80000 ################################################################
10256 13:56:46.678164
10257 13:56:46.957382 01b00000 ################################################################
10258 13:56:46.957542
10259 13:56:47.239172 01b80000 ################################################################
10260 13:56:47.239339
10261 13:56:47.499075 01c00000 ################################################################
10262 13:56:47.499249
10263 13:56:47.504202 01c80000 ## done.
10264 13:56:47.504344
10265 13:56:47.507322 The bootfile was 29895582 bytes long.
10266 13:56:47.507416
10267 13:56:47.510822 Sending tftp read request... done.
10268 13:56:47.510924
10269 13:56:47.514205 Waiting for the transfer...
10270 13:56:47.514281
10271 13:56:47.514346 00000000 # done.
10272 13:56:47.514408
10273 13:56:47.523812 Command line loaded dynamically from TFTP file: 12682934/tftp-deploy-4nfmyslk/kernel/cmdline
10274 13:56:47.523921
10275 13:56:47.543765 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682934/extract-nfsrootfs-rmbfr8up,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10276 13:56:47.543869
10277 13:56:47.547095 Loading FIT.
10278 13:56:47.547193
10279 13:56:47.550653 Image ramdisk-1 has 17799409 bytes.
10280 13:56:47.550725
10281 13:56:47.550791 Image fdt-1 has 47278 bytes.
10282 13:56:47.550851
10283 13:56:47.554067 Image kernel-1 has 12046857 bytes.
10284 13:56:47.554140
10285 13:56:47.563823 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10286 13:56:47.563925
10287 13:56:47.580237 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10288 13:56:47.580343
10289 13:56:47.586954 Choosing best match conf-1 for compat google,spherion-rev2.
10290 13:56:47.591292
10291 13:56:47.595717 Connected to device vid:did:rid of 1ae0:0028:00
10292 13:56:47.603686
10293 13:56:47.606932 tpm_get_response: command 0x17b, return code 0x0
10294 13:56:47.607008
10295 13:56:47.610252 ec_init: CrosEC protocol v3 supported (256, 248)
10296 13:56:47.614205
10297 13:56:47.617941 tpm_cleanup: add release locality here.
10298 13:56:47.618043
10299 13:56:47.618135 Shutting down all USB controllers.
10300 13:56:47.620975
10301 13:56:47.621048 Removing current net device
10302 13:56:47.621110
10303 13:56:47.628087 Exiting depthcharge with code 4 at timestamp: 51203423
10304 13:56:47.628186
10305 13:56:47.630977 LZMA decompressing kernel-1 to 0x821a6718
10306 13:56:47.631051
10307 13:56:47.634010 LZMA decompressing kernel-1 to 0x40000000
10308 13:56:49.135247
10309 13:56:49.135412 jumping to kernel
10310 13:56:49.136249 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10311 13:56:49.136424 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10312 13:56:49.136533 Setting prompt string to ['Linux version [0-9]']
10313 13:56:49.136637 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10314 13:56:49.136736 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10315 13:56:49.218244
10316 13:56:49.221357 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10317 13:56:49.224870 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10318 13:56:49.224964 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10319 13:56:49.225035 Setting prompt string to []
10320 13:56:49.225136 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10321 13:56:49.225244 Using line separator: #'\n'#
10322 13:56:49.225306 No login prompt set.
10323 13:56:49.225368 Parsing kernel messages
10324 13:56:49.225423 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10325 13:56:49.225523 [login-action] Waiting for messages, (timeout 00:04:02)
10326 13:56:49.244917 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10327 13:56:49.248082 [ 0.000000] random: crng init done
10328 13:56:49.254801 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10329 13:56:49.254909 [ 0.000000] efi: UEFI not found.
10330 13:56:49.264193 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10331 13:56:49.271050 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10332 13:56:49.281120 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10333 13:56:49.291195 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10334 13:56:49.297366 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10335 13:56:49.303981 [ 0.000000] printk: bootconsole [mtk8250] enabled
10336 13:56:49.307292 [ 0.000000] NUMA: No NUMA configuration found
10337 13:56:49.317571 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10338 13:56:49.320891 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10339 13:56:49.324052 [ 0.000000] Zone ranges:
10340 13:56:49.330575 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10341 13:56:49.333650 [ 0.000000] DMA32 empty
10342 13:56:49.340532 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10343 13:56:49.343788 [ 0.000000] Movable zone start for each node
10344 13:56:49.347184 [ 0.000000] Early memory node ranges
10345 13:56:49.353972 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10346 13:56:49.360257 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10347 13:56:49.366736 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10348 13:56:49.373409 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10349 13:56:49.376648 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10350 13:56:49.386782 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10351 13:56:49.442124 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10352 13:56:49.448630 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10353 13:56:49.455344 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10354 13:56:49.458723 [ 0.000000] psci: probing for conduit method from DT.
10355 13:56:49.465095 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10356 13:56:49.468055 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10357 13:56:49.475147 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10358 13:56:49.478338 [ 0.000000] psci: SMC Calling Convention v1.2
10359 13:56:49.484618 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10360 13:56:49.488032 [ 0.000000] Detected VIPT I-cache on CPU0
10361 13:56:49.495104 [ 0.000000] CPU features: detected: GIC system register CPU interface
10362 13:56:49.501899 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10363 13:56:49.508028 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10364 13:56:49.514879 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10365 13:56:49.521745 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10366 13:56:49.531610 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10367 13:56:49.534901 [ 0.000000] alternatives: applying boot alternatives
10368 13:56:49.541529 [ 0.000000] Fallback order for Node 0: 0
10369 13:56:49.547876 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10370 13:56:49.551040 [ 0.000000] Policy zone: Normal
10371 13:56:49.574165 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682934/extract-nfsrootfs-rmbfr8up,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10372 13:56:49.584201 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10373 13:56:49.594460 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10374 13:56:49.604573 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10375 13:56:49.611077 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10376 13:56:49.614443 <6>[ 0.000000] software IO TLB: area num 8.
10377 13:56:49.670866 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10378 13:56:49.820009 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402900K reserved, 32768K cma-reserved)
10379 13:56:49.827009 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10380 13:56:49.833264 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10381 13:56:49.836680 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10382 13:56:49.843595 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10383 13:56:49.849720 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10384 13:56:49.853129 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10385 13:56:49.863315 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10386 13:56:49.870172 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10387 13:56:49.876781 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10388 13:56:49.883598 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10389 13:56:49.886999 <6>[ 0.000000] GICv3: 608 SPIs implemented
10390 13:56:49.889663 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10391 13:56:49.896780 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10392 13:56:49.899725 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10393 13:56:49.906347 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10394 13:56:49.919299 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10395 13:56:49.932581 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10396 13:56:49.939231 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10397 13:56:49.947159 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10398 13:56:49.960134 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10399 13:56:49.966638 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10400 13:56:49.973294 <6>[ 0.009185] Console: colour dummy device 80x25
10401 13:56:49.983182 <6>[ 0.013940] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10402 13:56:49.989901 <6>[ 0.024446] pid_max: default: 32768 minimum: 301
10403 13:56:49.993267 <6>[ 0.029311] LSM: Security Framework initializing
10404 13:56:49.999807 <6>[ 0.034248] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10405 13:56:50.009661 <6>[ 0.042060] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10406 13:56:50.019482 <6>[ 0.051471] cblist_init_generic: Setting adjustable number of callback queues.
10407 13:56:50.022705 <6>[ 0.058960] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 13:56:50.032895 <6>[ 0.065299] cblist_init_generic: Setting adjustable number of callback queues.
10409 13:56:50.039245 <6>[ 0.072726] cblist_init_generic: Setting shift to 3 and lim to 1.
10410 13:56:50.043043 <6>[ 0.079129] rcu: Hierarchical SRCU implementation.
10411 13:56:50.049537 <6>[ 0.084144] rcu: Max phase no-delay instances is 1000.
10412 13:56:50.056487 <6>[ 0.091204] EFI services will not be available.
10413 13:56:50.059204 <6>[ 0.096190] smp: Bringing up secondary CPUs ...
10414 13:56:50.067773 <6>[ 0.101239] Detected VIPT I-cache on CPU1
10415 13:56:50.074878 <6>[ 0.101310] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10416 13:56:50.081235 <6>[ 0.101340] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10417 13:56:50.084041 <6>[ 0.101682] Detected VIPT I-cache on CPU2
10418 13:56:50.090749 <6>[ 0.101734] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10419 13:56:50.097395 <6>[ 0.101753] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10420 13:56:50.104176 <6>[ 0.102010] Detected VIPT I-cache on CPU3
10421 13:56:50.110963 <6>[ 0.102057] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10422 13:56:50.117658 <6>[ 0.102071] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10423 13:56:50.121082 <6>[ 0.102375] CPU features: detected: Spectre-v4
10424 13:56:50.127630 <6>[ 0.102382] CPU features: detected: Spectre-BHB
10425 13:56:50.130867 <6>[ 0.102387] Detected PIPT I-cache on CPU4
10426 13:56:50.137573 <6>[ 0.102442] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10427 13:56:50.144132 <6>[ 0.102459] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10428 13:56:50.150716 <6>[ 0.102754] Detected PIPT I-cache on CPU5
10429 13:56:50.157166 <6>[ 0.102816] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10430 13:56:50.163818 <6>[ 0.102832] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10431 13:56:50.166874 <6>[ 0.103114] Detected PIPT I-cache on CPU6
10432 13:56:50.173784 <6>[ 0.103178] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10433 13:56:50.180619 <6>[ 0.103194] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10434 13:56:50.187070 <6>[ 0.103490] Detected PIPT I-cache on CPU7
10435 13:56:50.193262 <6>[ 0.103553] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10436 13:56:50.199971 <6>[ 0.103570] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10437 13:56:50.203382 <6>[ 0.103617] smp: Brought up 1 node, 8 CPUs
10438 13:56:50.210304 <6>[ 0.244946] SMP: Total of 8 processors activated.
10439 13:56:50.213583 <6>[ 0.249897] CPU features: detected: 32-bit EL0 Support
10440 13:56:50.223401 <6>[ 0.255260] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10441 13:56:50.229786 <6>[ 0.264060] CPU features: detected: Common not Private translations
10442 13:56:50.236931 <6>[ 0.270576] CPU features: detected: CRC32 instructions
10443 13:56:50.240278 <6>[ 0.275927] CPU features: detected: RCpc load-acquire (LDAPR)
10444 13:56:50.246925 <6>[ 0.281887] CPU features: detected: LSE atomic instructions
10445 13:56:50.253054 <6>[ 0.287705] CPU features: detected: Privileged Access Never
10446 13:56:50.259550 <6>[ 0.293520] CPU features: detected: RAS Extension Support
10447 13:56:50.266400 <6>[ 0.299164] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10448 13:56:50.269618 <6>[ 0.306383] CPU: All CPU(s) started at EL2
10449 13:56:50.275819 <6>[ 0.310727] alternatives: applying system-wide alternatives
10450 13:56:50.285802 <6>[ 0.321451] devtmpfs: initialized
10451 13:56:50.297898 <6>[ 0.330457] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10452 13:56:50.307926 <6>[ 0.340424] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10453 13:56:50.311093 <6>[ 0.348008] pinctrl core: initialized pinctrl subsystem
10454 13:56:50.319024 <6>[ 0.354657] DMI not present or invalid.
10455 13:56:50.325316 <6>[ 0.359069] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10456 13:56:50.331775 <6>[ 0.365957] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10457 13:56:50.341963 <6>[ 0.373541] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10458 13:56:50.348728 <6>[ 0.381775] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10459 13:56:50.355439 <6>[ 0.390020] audit: initializing netlink subsys (disabled)
10460 13:56:50.361546 <5>[ 0.395714] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10461 13:56:50.368223 <6>[ 0.396413] thermal_sys: Registered thermal governor 'step_wise'
10462 13:56:50.375273 <6>[ 0.403685] thermal_sys: Registered thermal governor 'power_allocator'
10463 13:56:50.381759 <6>[ 0.409942] cpuidle: using governor menu
10464 13:56:50.384756 <6>[ 0.420908] NET: Registered PF_QIPCRTR protocol family
10465 13:56:50.391759 <6>[ 0.426394] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10466 13:56:50.397797 <6>[ 0.433497] ASID allocator initialised with 32768 entries
10467 13:56:50.404458 <6>[ 0.440062] Serial: AMBA PL011 UART driver
10468 13:56:50.412821 <4>[ 0.448781] Trying to register duplicate clock ID: 134
10469 13:56:50.469079 <6>[ 0.507838] KASLR enabled
10470 13:56:50.483175 <6>[ 0.515542] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10471 13:56:50.489761 <6>[ 0.522557] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10472 13:56:50.495962 <6>[ 0.529048] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10473 13:56:50.503009 <6>[ 0.536057] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10474 13:56:50.509709 <6>[ 0.542548] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10475 13:56:50.516486 <6>[ 0.549556] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10476 13:56:50.522958 <6>[ 0.556045] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10477 13:56:50.529539 <6>[ 0.563051] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10478 13:56:50.532563 <6>[ 0.570561] ACPI: Interpreter disabled.
10479 13:56:50.541145 <6>[ 0.576986] iommu: Default domain type: Translated
10480 13:56:50.547900 <6>[ 0.582102] iommu: DMA domain TLB invalidation policy: strict mode
10481 13:56:50.551087 <5>[ 0.588762] SCSI subsystem initialized
10482 13:56:50.557399 <6>[ 0.592926] usbcore: registered new interface driver usbfs
10483 13:56:50.564282 <6>[ 0.598661] usbcore: registered new interface driver hub
10484 13:56:50.567614 <6>[ 0.604213] usbcore: registered new device driver usb
10485 13:56:50.574510 <6>[ 0.610313] pps_core: LinuxPPS API ver. 1 registered
10486 13:56:50.584787 <6>[ 0.615508] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10487 13:56:50.587529 <6>[ 0.624860] PTP clock support registered
10488 13:56:50.590941 <6>[ 0.629102] EDAC MC: Ver: 3.0.0
10489 13:56:50.598611 <6>[ 0.634242] FPGA manager framework
10490 13:56:50.601782 <6>[ 0.637924] Advanced Linux Sound Architecture Driver Initialized.
10491 13:56:50.605444 <6>[ 0.644703] vgaarb: loaded
10492 13:56:50.612380 <6>[ 0.647864] clocksource: Switched to clocksource arch_sys_counter
10493 13:56:50.618777 <5>[ 0.654306] VFS: Disk quotas dquot_6.6.0
10494 13:56:50.625927 <6>[ 0.658492] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10495 13:56:50.628819 <6>[ 0.665685] pnp: PnP ACPI: disabled
10496 13:56:50.636788 <6>[ 0.672430] NET: Registered PF_INET protocol family
10497 13:56:50.646760 <6>[ 0.678027] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10498 13:56:50.657990 <6>[ 0.690359] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10499 13:56:50.668121 <6>[ 0.699181] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10500 13:56:50.674713 <6>[ 0.707152] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10501 13:56:50.681247 <6>[ 0.715858] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10502 13:56:50.692916 <6>[ 0.725610] TCP: Hash tables configured (established 65536 bind 65536)
10503 13:56:50.700085 <6>[ 0.732479] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10504 13:56:50.706659 <6>[ 0.739682] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10505 13:56:50.713240 <6>[ 0.747390] NET: Registered PF_UNIX/PF_LOCAL protocol family
10506 13:56:50.719686 <6>[ 0.753538] RPC: Registered named UNIX socket transport module.
10507 13:56:50.722830 <6>[ 0.759692] RPC: Registered udp transport module.
10508 13:56:50.729976 <6>[ 0.764627] RPC: Registered tcp transport module.
10509 13:56:50.736554 <6>[ 0.769560] RPC: Registered tcp NFSv4.1 backchannel transport module.
10510 13:56:50.739874 <6>[ 0.776226] PCI: CLS 0 bytes, default 64
10511 13:56:50.743503 <6>[ 0.780525] Unpacking initramfs...
10512 13:56:50.753035 <6>[ 0.784576] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10513 13:56:50.759593 <6>[ 0.793197] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10514 13:56:50.766217 <6>[ 0.802010] kvm [1]: IPA Size Limit: 40 bits
10515 13:56:50.769472 <6>[ 0.806538] kvm [1]: GICv3: no GICV resource entry
10516 13:56:50.776108 <6>[ 0.811560] kvm [1]: disabling GICv2 emulation
10517 13:56:50.782782 <6>[ 0.816252] kvm [1]: GIC system register CPU interface enabled
10518 13:56:50.785904 <6>[ 0.822418] kvm [1]: vgic interrupt IRQ18
10519 13:56:50.792565 <6>[ 0.826777] kvm [1]: VHE mode initialized successfully
10520 13:56:50.795808 <5>[ 0.833253] Initialise system trusted keyrings
10521 13:56:50.802898 <6>[ 0.838071] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10522 13:56:50.812591 <6>[ 0.848115] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10523 13:56:50.819253 <5>[ 0.854493] NFS: Registering the id_resolver key type
10524 13:56:50.822425 <5>[ 0.859796] Key type id_resolver registered
10525 13:56:50.829182 <5>[ 0.864214] Key type id_legacy registered
10526 13:56:50.835387 <6>[ 0.868497] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10527 13:56:50.842237 <6>[ 0.875419] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10528 13:56:50.848595 <6>[ 0.883127] 9p: Installing v9fs 9p2000 file system support
10529 13:56:50.885227 <5>[ 0.920729] Key type asymmetric registered
10530 13:56:50.888572 <5>[ 0.925064] Asymmetric key parser 'x509' registered
10531 13:56:50.898343 <6>[ 0.930210] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10532 13:56:50.901566 <6>[ 0.937827] io scheduler mq-deadline registered
10533 13:56:50.904844 <6>[ 0.942590] io scheduler kyber registered
10534 13:56:50.923757 <6>[ 0.959693] EINJ: ACPI disabled.
10535 13:56:50.955991 <4>[ 0.985266] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10536 13:56:50.965619 <4>[ 0.995901] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10537 13:56:50.981146 <6>[ 1.016880] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10538 13:56:50.989035 <6>[ 1.024882] printk: console [ttyS0] disabled
10539 13:56:51.017506 <6>[ 1.049529] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10540 13:56:51.023591 <6>[ 1.059006] printk: console [ttyS0] enabled
10541 13:56:51.026805 <6>[ 1.059006] printk: console [ttyS0] enabled
10542 13:56:51.033857 <6>[ 1.067904] printk: bootconsole [mtk8250] disabled
10543 13:56:51.037238 <6>[ 1.067904] printk: bootconsole [mtk8250] disabled
10544 13:56:51.043411 <6>[ 1.079131] SuperH (H)SCI(F) driver initialized
10545 13:56:51.046796 <6>[ 1.084423] msm_serial: driver initialized
10546 13:56:51.060899 <6>[ 1.093422] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10547 13:56:51.071552 <6>[ 1.101969] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10548 13:56:51.078131 <6>[ 1.110512] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10549 13:56:51.087668 <6>[ 1.119140] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10550 13:56:51.094302 <6>[ 1.127848] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10551 13:56:51.104555 <6>[ 1.136580] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10552 13:56:51.114143 <6>[ 1.145123] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10553 13:56:51.120591 <6>[ 1.153927] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10554 13:56:51.130547 <6>[ 1.162470] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10555 13:56:51.142604 <6>[ 1.178161] loop: module loaded
10556 13:56:51.148493 <6>[ 1.184205] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10557 13:56:51.171912 <4>[ 1.207675] mtk-pmic-keys: Failed to locate of_node [id: -1]
10558 13:56:51.179058 <6>[ 1.214744] megasas: 07.719.03.00-rc1
10559 13:56:51.188394 <6>[ 1.224470] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10560 13:56:51.195987 <6>[ 1.231271] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10561 13:56:51.212131 <6>[ 1.248055] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10562 13:56:51.269389 <6>[ 1.298331] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10563 13:56:51.524004 <6>[ 1.559952] Freeing initrd memory: 17380K
10564 13:56:51.534354 <6>[ 1.570176] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10565 13:56:51.545010 <6>[ 1.581095] tun: Universal TUN/TAP device driver, 1.6
10566 13:56:51.548269 <6>[ 1.587148] thunder_xcv, ver 1.0
10567 13:56:51.551808 <6>[ 1.590654] thunder_bgx, ver 1.0
10568 13:56:51.554964 <6>[ 1.594150] nicpf, ver 1.0
10569 13:56:51.565837 <6>[ 1.598148] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10570 13:56:51.568708 <6>[ 1.605624] hns3: Copyright (c) 2017 Huawei Corporation.
10571 13:56:51.575682 <6>[ 1.611212] hclge is initializing
10572 13:56:51.579120 <6>[ 1.614793] e1000: Intel(R) PRO/1000 Network Driver
10573 13:56:51.585771 <6>[ 1.619922] e1000: Copyright (c) 1999-2006 Intel Corporation.
10574 13:56:51.589118 <6>[ 1.625935] e1000e: Intel(R) PRO/1000 Network Driver
10575 13:56:51.595739 <6>[ 1.631150] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10576 13:56:51.602398 <6>[ 1.637338] igb: Intel(R) Gigabit Ethernet Network Driver
10577 13:56:51.608922 <6>[ 1.642987] igb: Copyright (c) 2007-2014 Intel Corporation.
10578 13:56:51.615517 <6>[ 1.648823] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10579 13:56:51.622134 <6>[ 1.655341] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10580 13:56:51.625322 <6>[ 1.661798] sky2: driver version 1.30
10581 13:56:51.632042 <6>[ 1.666780] VFIO - User Level meta-driver version: 0.3
10582 13:56:51.638935 <6>[ 1.674994] usbcore: registered new interface driver usb-storage
10583 13:56:51.645758 <6>[ 1.681440] usbcore: registered new device driver onboard-usb-hub
10584 13:56:51.654671 <6>[ 1.690583] mt6397-rtc mt6359-rtc: registered as rtc0
10585 13:56:51.665309 <6>[ 1.696050] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:54:09 UTC (1706795649)
10586 13:56:51.668557 <6>[ 1.705604] i2c_dev: i2c /dev entries driver
10587 13:56:51.684604 <6>[ 1.717299] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10588 13:56:51.704142 <6>[ 1.740280] cpu cpu0: EM: created perf domain
10589 13:56:51.707892 <6>[ 1.745199] cpu cpu4: EM: created perf domain
10590 13:56:51.714950 <6>[ 1.750764] sdhci: Secure Digital Host Controller Interface driver
10591 13:56:51.721565 <6>[ 1.757197] sdhci: Copyright(c) Pierre Ossman
10592 13:56:51.728184 <6>[ 1.762155] Synopsys Designware Multimedia Card Interface Driver
10593 13:56:51.735024 <6>[ 1.768788] sdhci-pltfm: SDHCI platform and OF driver helper
10594 13:56:51.738443 <6>[ 1.768912] mmc0: CQHCI version 5.10
10595 13:56:51.745087 <6>[ 1.779122] ledtrig-cpu: registered to indicate activity on CPUs
10596 13:56:51.751493 <6>[ 1.786144] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10597 13:56:51.758591 <6>[ 1.793196] usbcore: registered new interface driver usbhid
10598 13:56:51.761871 <6>[ 1.799018] usbhid: USB HID core driver
10599 13:56:51.768172 <6>[ 1.803232] spi_master spi0: will run message pump with realtime priority
10600 13:56:51.811645 <6>[ 1.841132] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10601 13:56:51.830537 <6>[ 1.856119] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10602 13:56:51.833707 <6>[ 1.869734] mmc0: Command Queue Engine enabled
10603 13:56:51.840360 <6>[ 1.874504] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10604 13:56:51.847292 <6>[ 1.881439] cros-ec-spi spi0.0: Chrome EC device registered
10605 13:56:51.850255 <6>[ 1.881780] mmcblk0: mmc0:0001 DA4128 116 GiB
10606 13:56:51.861266 <6>[ 1.897232] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10607 13:56:51.868753 <6>[ 1.904339] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10608 13:56:51.875080 <6>[ 1.910286] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10609 13:56:51.881585 <6>[ 1.916242] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10610 13:56:51.892076 <6>[ 1.921036] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10611 13:56:51.898738 <6>[ 1.933310] NET: Registered PF_PACKET protocol family
10612 13:56:51.901924 <6>[ 1.938715] 9pnet: Installing 9P2000 support
10613 13:56:51.908219 <5>[ 1.943286] Key type dns_resolver registered
10614 13:56:51.911728 <6>[ 1.948281] registered taskstats version 1
10615 13:56:51.918088 <5>[ 1.952670] Loading compiled-in X.509 certificates
10616 13:56:51.947280 <4>[ 1.976527] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 13:56:51.957678 <4>[ 1.987323] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 13:56:51.964042 <3>[ 1.997860] debugfs: File 'uA_load' in directory '/' already present!
10619 13:56:51.970586 <3>[ 2.004567] debugfs: File 'min_uV' in directory '/' already present!
10620 13:56:51.977821 <3>[ 2.011177] debugfs: File 'max_uV' in directory '/' already present!
10621 13:56:51.984174 <3>[ 2.017787] debugfs: File 'constraint_flags' in directory '/' already present!
10622 13:56:51.995123 <3>[ 2.027574] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10623 13:56:52.007278 <6>[ 2.043183] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10624 13:56:52.014098 <6>[ 2.050067] xhci-mtk 11200000.usb: xHCI Host Controller
10625 13:56:52.020868 <6>[ 2.055588] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10626 13:56:52.030871 <6>[ 2.063519] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10627 13:56:52.037876 <6>[ 2.072948] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10628 13:56:52.044115 <6>[ 2.079030] xhci-mtk 11200000.usb: xHCI Host Controller
10629 13:56:52.051346 <6>[ 2.084512] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10630 13:56:52.058082 <6>[ 2.092163] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10631 13:56:52.064844 <6>[ 2.100003] hub 1-0:1.0: USB hub found
10632 13:56:52.067760 <6>[ 2.104025] hub 1-0:1.0: 1 port detected
10633 13:56:52.074446 <6>[ 2.108317] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10634 13:56:52.081005 <6>[ 2.117030] hub 2-0:1.0: USB hub found
10635 13:56:52.084413 <6>[ 2.121052] hub 2-0:1.0: 1 port detected
10636 13:56:52.091652 <6>[ 2.127937] mtk-msdc 11f70000.mmc: Got CD GPIO
10637 13:56:52.105213 <6>[ 2.137497] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10638 13:56:52.111752 <6>[ 2.145528] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10639 13:56:52.121967 <4>[ 2.153457] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10640 13:56:52.132061 <6>[ 2.163020] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10641 13:56:52.138123 <6>[ 2.171100] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10642 13:56:52.145414 <6>[ 2.179120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10643 13:56:52.155281 <6>[ 2.187045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10644 13:56:52.162171 <6>[ 2.194862] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10645 13:56:52.171923 <6>[ 2.202679] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10646 13:56:52.181651 <6>[ 2.213093] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10647 13:56:52.188563 <6>[ 2.221484] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10648 13:56:52.198566 <6>[ 2.229832] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10649 13:56:52.204612 <6>[ 2.238172] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10650 13:56:52.214764 <6>[ 2.246511] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10651 13:56:52.221642 <6>[ 2.254850] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10652 13:56:52.231712 <6>[ 2.263196] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10653 13:56:52.237880 <6>[ 2.271535] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10654 13:56:52.247751 <6>[ 2.279874] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10655 13:56:52.254848 <6>[ 2.288214] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10656 13:56:52.264522 <6>[ 2.296552] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10657 13:56:52.270837 <6>[ 2.304890] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10658 13:56:52.280900 <6>[ 2.313228] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10659 13:56:52.287600 <6>[ 2.321566] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10660 13:56:52.297625 <6>[ 2.329904] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10661 13:56:52.304231 <6>[ 2.338644] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10662 13:56:52.311014 <6>[ 2.345783] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10663 13:56:52.317642 <6>[ 2.352546] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10664 13:56:52.324209 <6>[ 2.359299] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10665 13:56:52.330759 <6>[ 2.366232] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10666 13:56:52.340874 <6>[ 2.373098] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10667 13:56:52.350514 <6>[ 2.382234] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10668 13:56:52.360804 <6>[ 2.391353] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10669 13:56:52.370636 <6>[ 2.400646] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10670 13:56:52.377152 <6>[ 2.410112] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10671 13:56:52.386872 <6>[ 2.419578] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10672 13:56:52.396763 <6>[ 2.428697] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10673 13:56:52.406664 <6>[ 2.438163] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10674 13:56:52.417093 <6>[ 2.447281] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10675 13:56:52.426882 <6>[ 2.456575] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10676 13:56:52.436753 <6>[ 2.466734] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10677 13:56:52.446953 <6>[ 2.478206] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10678 13:56:52.453656 <6>[ 2.487806] Trying to probe devices needed for running init ...
10679 13:56:52.499401 <6>[ 2.532135] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10680 13:56:52.654002 <6>[ 2.689998] hub 1-1:1.0: USB hub found
10681 13:56:52.657113 <6>[ 2.694487] hub 1-1:1.0: 4 ports detected
10682 13:56:52.667704 <6>[ 2.703203] hub 1-1:1.0: USB hub found
10683 13:56:52.670219 <6>[ 2.707567] hub 1-1:1.0: 4 ports detected
10684 13:56:52.779471 <6>[ 2.812489] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10685 13:56:52.805603 <6>[ 2.841735] hub 2-1:1.0: USB hub found
10686 13:56:52.809345 <6>[ 2.846232] hub 2-1:1.0: 3 ports detected
10687 13:56:52.817951 <6>[ 2.854294] hub 2-1:1.0: USB hub found
10688 13:56:52.821730 <6>[ 2.858797] hub 2-1:1.0: 3 ports detected
10689 13:56:52.995040 <6>[ 3.028180] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10690 13:56:53.128154 <6>[ 3.163988] hub 1-1.4:1.0: USB hub found
10691 13:56:53.131307 <6>[ 3.168650] hub 1-1.4:1.0: 2 ports detected
10692 13:56:53.141316 <6>[ 3.177382] hub 1-1.4:1.0: USB hub found
10693 13:56:53.144509 <6>[ 3.181959] hub 1-1.4:1.0: 2 ports detected
10694 13:56:53.211709 <6>[ 3.244397] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10695 13:56:53.443396 <6>[ 3.476179] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10696 13:56:53.635495 <6>[ 3.668157] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10697 13:57:04.733014 <6>[ 14.773156] ALSA device list:
10698 13:57:04.739260 <6>[ 14.776451] No soundcards found.
10699 13:57:04.747705 <6>[ 14.784376] Freeing unused kernel memory: 8448K
10700 13:57:04.750942 <6>[ 14.789397] Run /init as init process
10701 13:57:04.762625 Loading, please wait...
10702 13:57:04.782797 Starting version 247.3-7+deb11u2
10703 13:57:05.033063 <6>[ 15.066052] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10704 13:57:05.039527 <6>[ 15.067962] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10705 13:57:05.049214 <6>[ 15.081144] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10706 13:57:05.056047 <6>[ 15.089866] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10707 13:57:05.062527 <4>[ 15.097561] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10708 13:57:05.072658 <3>[ 15.100860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 13:57:05.076049 <6>[ 15.113141] remoteproc remoteproc0: scp is available
10710 13:57:05.085436 <4>[ 15.113169] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10711 13:57:05.092733 <3>[ 15.114001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 13:57:05.098813 <6>[ 15.119249] remoteproc remoteproc0: powering up scp
10713 13:57:05.106142 <3>[ 15.126558] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 13:57:05.115976 <6>[ 15.134600] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10715 13:57:05.119194 <6>[ 15.134618] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10716 13:57:05.128926 <3>[ 15.146138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 13:57:05.132474 <6>[ 15.160441] mc: Linux media interface: v0.10
10718 13:57:05.142600 <3>[ 15.161947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 13:57:05.148940 <6>[ 15.169983] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10720 13:57:05.155748 <6>[ 15.176991] usbcore: registered new device driver r8152-cfgselector
10721 13:57:05.162375 <3>[ 15.182657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 13:57:05.172162 <3>[ 15.182666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 13:57:05.178717 <3>[ 15.182675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 13:57:05.188693 <3>[ 15.182761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 13:57:05.195429 <3>[ 15.182818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 13:57:05.205550 <3>[ 15.182824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 13:57:05.212846 <3>[ 15.182827] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 13:57:05.219034 <3>[ 15.182869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 13:57:05.228980 <6>[ 15.193508] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10730 13:57:05.239123 <3>[ 15.197012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 13:57:05.245971 <3>[ 15.197015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 13:57:05.255956 <3>[ 15.197017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 13:57:05.262648 <3>[ 15.197020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 13:57:05.270556 <3>[ 15.197037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 13:57:05.277166 <6>[ 15.221250] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10736 13:57:05.286906 <6>[ 15.221873] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10737 13:57:05.294023 <6>[ 15.229803] pci_bus 0000:00: root bus resource [bus 00-ff]
10738 13:57:05.300711 <4>[ 15.232439] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10739 13:57:05.307287 <4>[ 15.232439] Fallback method does not support PEC.
10740 13:57:05.316542 <6>[ 15.248573] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10741 13:57:05.323574 <6>[ 15.254062] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10742 13:57:05.329574 <3>[ 15.259371] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10743 13:57:05.339536 <6>[ 15.273236] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10744 13:57:05.346435 <6>[ 15.273245] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10745 13:57:05.356337 <6>[ 15.280512] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10746 13:57:05.366194 <6>[ 15.280583] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10747 13:57:05.369604 <6>[ 15.280870] videodev: Linux video capture interface: v2.00
10748 13:57:05.379588 <6>[ 15.284536] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10749 13:57:05.386391 <6>[ 15.289020] remoteproc remoteproc0: remote processor scp is now up
10750 13:57:05.392969 <6>[ 15.289814] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10751 13:57:05.399430 <6>[ 15.296851] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10752 13:57:05.402712 <6>[ 15.305179] Bluetooth: Core ver 2.22
10753 13:57:05.412639 <4>[ 15.306997] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10754 13:57:05.422348 <4>[ 15.307005] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10755 13:57:05.429663 <3>[ 15.311518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10756 13:57:05.435690 <6>[ 15.312770] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10757 13:57:05.442442 <6>[ 15.319681] NET: Registered PF_BLUETOOTH protocol family
10758 13:57:05.445739 <6>[ 15.328733] pci 0000:00:00.0: supports D1 D2
10759 13:57:05.452385 <6>[ 15.334391] Bluetooth: HCI device and connection manager initialized
10760 13:57:05.458771 <6>[ 15.334416] Bluetooth: HCI socket layer initialized
10761 13:57:05.465030 <6>[ 15.348025] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10762 13:57:05.471965 <6>[ 15.349371] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10763 13:57:05.485708 <6>[ 15.350682] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10764 13:57:05.491933 <6>[ 15.350780] usbcore: registered new interface driver uvcvideo
10765 13:57:05.495076 <6>[ 15.357320] Bluetooth: L2CAP socket layer initialized
10766 13:57:05.504803 <6>[ 15.365407] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10767 13:57:05.508614 <6>[ 15.372095] r8152 2-1.3:1.0 eth0: v1.12.13
10768 13:57:05.514609 <6>[ 15.372159] usbcore: registered new interface driver r8152
10769 13:57:05.517975 <6>[ 15.373222] Bluetooth: SCO socket layer initialized
10770 13:57:05.525106 <6>[ 15.373728] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10771 13:57:05.531670 <6>[ 15.381835] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10772 13:57:05.538211 <6>[ 15.389490] usbcore: registered new interface driver cdc_ether
10773 13:57:05.544723 <6>[ 15.398701] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10774 13:57:05.551566 <6>[ 15.413171] usbcore: registered new interface driver r8153_ecm
10775 13:57:05.557931 <6>[ 15.421190] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10776 13:57:05.564413 <6>[ 15.437940] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10777 13:57:05.574368 <6>[ 15.442072] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10778 13:57:05.578072 <6>[ 15.446504] usbcore: registered new interface driver btusb
10779 13:57:05.587522 <4>[ 15.447268] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10780 13:57:05.594223 <3>[ 15.447280] Bluetooth: hci0: Failed to load firmware file (-2)
10781 13:57:05.601230 <3>[ 15.447285] Bluetooth: hci0: Failed to set up firmware (-2)
10782 13:57:05.610973 <4>[ 15.447291] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10783 13:57:05.617750 <6>[ 15.455032] pci 0000:01:00.0: supports D1 D2
10784 13:57:05.624356 <6>[ 15.658553] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10785 13:57:05.642049 <6>[ 15.676086] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10786 13:57:05.648715 <6>[ 15.682978] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10787 13:57:05.655489 <6>[ 15.691062] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10788 13:57:05.665659 <6>[ 15.699063] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10789 13:57:05.672088 <6>[ 15.707063] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10790 13:57:05.682249 <6>[ 15.715064] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10791 13:57:05.685418 <6>[ 15.723063] pci 0000:00:00.0: PCI bridge to [bus 01]
10792 13:57:05.695663 <6>[ 15.728280] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10793 13:57:05.702127 <6>[ 15.736397] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10794 13:57:05.708618 <6>[ 15.743217] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10795 13:57:05.715180 <6>[ 15.749953] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10796 13:57:05.731252 <5>[ 15.764525] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10797 13:57:05.750082 <5>[ 15.783608] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10798 13:57:05.756726 <5>[ 15.791044] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10799 13:57:05.766225 <4>[ 15.799475] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10800 13:57:05.769768 <6>[ 15.808357] cfg80211: failed to load regulatory.db
10801 13:57:05.820135 <6>[ 15.854212] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10802 13:57:05.826757 <6>[ 15.861714] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10803 13:57:05.851028 <6>[ 15.888363] mt7921e 0000:01:00.0: ASIC revision: 79610010
10804 13:57:05.953388 <6>[ 15.987432] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10805 13:57:05.956671 <6>[ 15.987432]
10806 13:57:05.973146 Begin: Loading essential drivers ... done.
10807 13:57:05.976417 Begin: Running /scripts/init-premount ... done.
10808 13:57:05.983392 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10809 13:57:05.992768 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10810 13:57:05.996266 Device /sys/class/net/enx00e04c787aaa found
10811 13:57:05.996423 done.
10812 13:57:06.054265 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10813 13:57:06.223670 <6>[ 16.257724] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10814 13:57:06.915993 <6>[ 16.952940] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10815 13:57:07.074817 <6>[ 17.111679] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10816 13:57:07.159092 IP-Config: no response after 2 secs - giving up
10817 13:57:07.195103 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10818 13:57:07.917692 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10819 13:57:07.924220 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10820 13:57:07.931139 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10821 13:57:07.937629 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10822 13:57:07.944214 host : mt8192-asurada-spherion-r0-cbg-0
10823 13:57:07.950795 domain : lava-rack
10824 13:57:07.953959 rootserver: 192.168.201.1 rootpath:
10825 13:57:07.954132 filename :
10826 13:57:08.066036 done.
10827 13:57:08.072538 Begin: Running /scripts/nfs-bottom ... done.
10828 13:57:08.093067 Begin: Running /scripts/init-bottom ... done.
10829 13:57:09.258378 <6>[ 19.296027] NET: Registered PF_INET6 protocol family
10830 13:57:09.265581 <6>[ 19.303120] Segment Routing with IPv6
10831 13:57:09.268704 <6>[ 19.307084] In-situ OAM (IOAM) with IPv6
10832 13:57:09.384513 <30>[ 19.402706] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10833 13:57:09.388261 <30>[ 19.427154] systemd[1]: Detected architecture arm64.
10834 13:57:09.407343
10835 13:57:09.410869 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10836 13:57:09.410951
10837 13:57:09.428028 <30>[ 19.465945] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10838 13:57:10.264935 <30>[ 20.299453] systemd[1]: Queued start job for default target Graphical Interface.
10839 13:57:10.297138 <30>[ 20.334531] systemd[1]: Created slice system-getty.slice.
10840 13:57:10.303539 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10841 13:57:10.319749 <30>[ 20.357532] systemd[1]: Created slice system-modprobe.slice.
10842 13:57:10.326566 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10843 13:57:10.344114 <30>[ 20.381390] systemd[1]: Created slice system-serial\x2dgetty.slice.
10844 13:57:10.350557 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10845 13:57:10.367830 <30>[ 20.405218] systemd[1]: Created slice User and Session Slice.
10846 13:57:10.374436 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10847 13:57:10.395211 <30>[ 20.429000] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10848 13:57:10.404572 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10849 13:57:10.423079 <30>[ 20.456921] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10850 13:57:10.429574 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10851 13:57:10.453294 <30>[ 20.484300] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10852 13:57:10.460457 <30>[ 20.496462] systemd[1]: Reached target Local Encrypted Volumes.
10853 13:57:10.466574 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10854 13:57:10.483005 <30>[ 20.520573] systemd[1]: Reached target Paths.
10855 13:57:10.489289 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10856 13:57:10.502871 <30>[ 20.540139] systemd[1]: Reached target Remote File Systems.
10857 13:57:10.509084 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10858 13:57:10.526764 <30>[ 20.564525] systemd[1]: Reached target Slices.
10859 13:57:10.533828 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10860 13:57:10.546640 <30>[ 20.584160] systemd[1]: Reached target Swap.
10861 13:57:10.549775 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10862 13:57:10.570363 <30>[ 20.604634] systemd[1]: Listening on initctl Compatibility Named Pipe.
10863 13:57:10.576797 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10864 13:57:10.583359 <30>[ 20.620698] systemd[1]: Listening on Journal Audit Socket.
10865 13:57:10.589972 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10866 13:57:10.608316 <30>[ 20.645387] systemd[1]: Listening on Journal Socket (/dev/log).
10867 13:57:10.614639 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10868 13:57:10.631376 <30>[ 20.668719] systemd[1]: Listening on Journal Socket.
10869 13:57:10.637421 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10870 13:57:10.655297 <30>[ 20.689617] systemd[1]: Listening on Network Service Netlink Socket.
10871 13:57:10.661637 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10872 13:57:10.677555 <30>[ 20.715009] systemd[1]: Listening on udev Control Socket.
10873 13:57:10.683878 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10874 13:57:10.698899 <30>[ 20.736583] systemd[1]: Listening on udev Kernel Socket.
10875 13:57:10.705457 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10876 13:57:10.762852 <30>[ 20.800377] systemd[1]: Mounting Huge Pages File System...
10877 13:57:10.769623 Mounting [0;1;39mHuge Pages File System[0m...
10878 13:57:10.786740 <30>[ 20.824537] systemd[1]: Mounting POSIX Message Queue File System...
10879 13:57:10.793989 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10880 13:57:10.814768 <30>[ 20.852649] systemd[1]: Mounting Kernel Debug File System...
10881 13:57:10.821829 Mounting [0;1;39mKernel Debug File System[0m...
10882 13:57:10.838406 <30>[ 20.872700] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10883 13:57:10.855488 <30>[ 20.889565] systemd[1]: Starting Create list of static device nodes for the current kernel...
10884 13:57:10.865206 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10885 13:57:10.883417 <30>[ 20.920903] systemd[1]: Starting Load Kernel Module configfs...
10886 13:57:10.889730 Starting [0;1;39mLoad Kernel Module configfs[0m...
10887 13:57:10.905727 <30>[ 20.943293] systemd[1]: Starting Load Kernel Module drm...
10888 13:57:10.912322 Starting [0;1;39mLoad Kernel Module drm[0m...
10889 13:57:10.947140 <30>[ 20.984543] systemd[1]: Starting Load Kernel Module fuse...
10890 13:57:10.953441 Starting [0;1;39mLoad Kernel Module fuse[0m...
10891 13:57:10.975411 <30>[ 21.010109] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10892 13:57:10.990362 <30>[ 21.028299] systemd[1]: Starting Journal Service...
10893 13:57:10.996862 Startin<6>[ 21.034588] fuse: init (API version 7.37)
10894 13:57:11.000278 g [0;1;39mJournal Service[0m...
10895 13:57:11.019757 <30>[ 21.057873] systemd[1]: Starting Load Kernel Modules...
10896 13:57:11.026309 Starting [0;1;39mLoad Kernel Modules[0m...
10897 13:57:11.044965 <30>[ 21.079612] systemd[1]: Starting Remount Root and Kernel File Systems...
10898 13:57:11.051862 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10899 13:57:11.069740 <30>[ 21.107564] systemd[1]: Starting Coldplug All udev Devices...
10900 13:57:11.076589 Starting [0;1;39mColdplug All udev Devices[0m...
10901 13:57:11.097973 <30>[ 21.135748] systemd[1]: Mounted Huge Pages File System.
10902 13:57:11.104562 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10903 13:57:11.119046 <30>[ 21.156738] systemd[1]: Mounted POSIX Message Queue File System.
10904 13:57:11.126163 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10905 13:57:11.137025 <3>[ 21.171403] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 13:57:11.143975 <30>[ 21.180840] systemd[1]: Mounted Kernel Debug File System.
10907 13:57:11.150292 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10908 13:57:11.168479 <3>[ 21.202489] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 13:57:11.178138 <30>[ 21.212311] systemd[1]: Finished Create list of static device nodes for the current kernel.
10910 13:57:11.188364 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10911 13:57:11.204238 <30>[ 21.240954] systemd[1]: modprobe@configfs.service: Succeeded.
10912 13:57:11.214798 <3>[ 21.246595] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 13:57:11.221029 <30>[ 21.247695] systemd[1]: Finished Load Kernel Module configfs.
10914 13:57:11.227345 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10915 13:57:11.239156 <30>[ 21.277054] systemd[1]: modprobe@drm.service: Succeeded.
10916 13:57:11.249499 <3>[ 21.277324] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 13:57:11.255814 <30>[ 21.283567] systemd[1]: Finished Load Kernel Module drm.
10918 13:57:11.258970 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10919 13:57:11.278230 <3>[ 21.312274] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 13:57:11.284440 <30>[ 21.313005] systemd[1]: modprobe@fuse.service: Succeeded.
10921 13:57:11.291554 <30>[ 21.327729] systemd[1]: Finished Load Kernel Module fuse.
10922 13:57:11.298122 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10923 13:57:11.308715 <3>[ 21.342636] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 13:57:11.315226 <30>[ 21.353003] systemd[1]: Finished Load Kernel Modules.
10925 13:57:11.321689 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10926 13:57:11.338035 <3>[ 21.372312] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 13:57:11.348532 <30>[ 21.382791] systemd[1]: Finished Remount Root and Kernel File Systems.
10928 13:57:11.355431 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10929 13:57:11.369577 <3>[ 21.404028] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 13:57:11.400511 <3>[ 21.434976] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 13:57:11.407115 <30>[ 21.437370] systemd[1]: Mounting FUSE Control File System...
10932 13:57:11.413617 Mounting [0;1;39mFUSE Control File System[0m...
10933 13:57:11.433871 <3>[ 21.468195] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 13:57:11.440248 <30>[ 21.468263] systemd[1]: Mounting Kernel Configuration File System...
10935 13:57:11.446733 Mounting [0;1;39mKernel Configuration File System[0m...
10936 13:57:11.470354 <30>[ 21.504576] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10937 13:57:11.480400 <30>[ 21.513725] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10938 13:57:11.490486 <30>[ 21.527706] systemd[1]: Starting Load/Save Random Seed...
10939 13:57:11.496838 Starting [0;1;39mLoad/Save Random Seed[0m...
10940 13:57:11.514893 <30>[ 21.552601] systemd[1]: Starting Apply Kernel Variables...
10941 13:57:11.521904 Starting [0;1;39mApply Kernel Variables[0m...
10942 13:57:11.538816 <4>[ 21.565865] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10943 13:57:11.545186 <3>[ 21.581527] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10944 13:57:11.551368 <30>[ 21.586490] systemd[1]: Starting Create System Users...
10945 13:57:11.557816 Starting [0;1;39mCreate System Users[0m...
10946 13:57:11.573115 <30>[ 21.611154] systemd[1]: Started Journal Service.
10947 13:57:11.579777 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10948 13:57:11.602142 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10949 13:57:11.614399 See 'systemctl status systemd-udev-trigger.service' for details.
10950 13:57:11.631405 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10951 13:57:11.651273 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10952 13:57:11.672245 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10953 13:57:11.692243 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10954 13:57:11.708221 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10955 13:57:11.759740 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10956 13:57:11.776496 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10957 13:57:11.815096 <46>[ 21.849678] systemd-journald[301]: Received client request to flush runtime journal.
10958 13:57:11.859161 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10959 13:57:11.875120 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10960 13:57:11.894461 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10961 13:57:11.962767 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10962 13:57:13.227018 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10963 13:57:13.274455 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10964 13:57:13.300484 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10965 13:57:13.321329 Starting [0;1;39mNetwork Service[0m...
10966 13:57:13.688543 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10967 13:57:13.713741 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10968 13:57:13.759506 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10969 13:57:13.978189 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10970 13:57:14.001548 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10971 13:57:14.043122 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10972 13:57:14.068292 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10973 13:57:14.087122 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10974 13:57:14.122014 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10975 13:57:14.143292 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10976 13:57:14.211481 Starting [0;1;39mNetwork Name Resolution[0m...
10977 13:57:14.234010 Starting [0;1;39mNetwork Time Synchronization[0m...
10978 13:57:14.255193 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10979 13:57:14.348946 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10980 13:57:14.423176 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10981 13:57:14.438871 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10982 13:57:14.461671 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10983 13:57:14.474333 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10984 13:57:14.494693 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10985 13:57:14.644398 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10986 13:57:14.675730 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10987 13:57:14.699805 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10988 13:57:15.065677 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10989 13:57:15.077876 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10990 13:57:15.333621 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10991 13:57:15.345956 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10992 13:57:15.362431 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10993 13:57:15.406904 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10994 13:57:15.806187 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10995 13:57:15.962987 Starting [0;1;39mUser Login Management[0m...
10996 13:57:15.979321 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10997 13:57:15.997367 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10998 13:57:16.013781 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10999 13:57:16.067247 Starting [0;1;39mPermit User Sessions[0m...
11000 13:57:16.087854 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11001 13:57:16.165442 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11002 13:57:16.223136 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11003 13:57:16.247506 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11004 13:57:16.266650 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11005 13:57:16.288395 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11006 13:57:16.308349 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11007 13:57:16.327010 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11008 13:57:16.371152 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11009 13:57:16.440726 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11010 13:57:16.512898
11011 13:57:16.513018
11012 13:57:16.515911 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11013 13:57:16.515993
11014 13:57:16.519200 debian-bullseye-arm64 login: root (automatic login)
11015 13:57:16.519281
11016 13:57:16.519345
11017 13:57:16.800749 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
11018 13:57:16.800882
11019 13:57:16.807494 The programs included with the Debian GNU/Linux system are free software;
11020 13:57:16.813862 the exact distribution terms for each program are described in the
11021 13:57:16.817088 individual files in /usr/share/doc/*/copyright.
11022 13:57:16.817174
11023 13:57:16.823845 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11024 13:57:16.826924 permitted by applicable law.
11025 13:57:16.888756 Matched prompt #10: / #
11027 13:57:16.888990 Setting prompt string to ['/ #']
11028 13:57:16.889096 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11030 13:57:16.889291 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11031 13:57:16.889379 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
11032 13:57:16.889449 Setting prompt string to ['/ #']
11033 13:57:16.889509 Forcing a shell prompt, looking for ['/ #']
11035 13:57:16.939813 / #
11036 13:57:16.940338 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11037 13:57:16.940738 Waiting using forced prompt support (timeout 00:02:30)
11038 13:57:16.945483
11039 13:57:16.946256 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11040 13:57:16.946736 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11042 13:57:17.047769 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682934/extract-nfsrootfs-rmbfr8up'
11043 13:57:17.053173 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682934/extract-nfsrootfs-rmbfr8up'
11045 13:57:17.154032 / # export NFS_SERVER_IP='192.168.201.1'
11046 13:57:17.160359 export NFS_SERVER_IP='192.168.201.1'
11047 13:57:17.161173 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11048 13:57:17.161643 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
11049 13:57:17.162089 end: 2 depthcharge-action (duration 00:01:26) [common]
11050 13:57:17.162539 start: 3 lava-test-retry (timeout 00:01:00) [common]
11051 13:57:17.162972 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11052 13:57:17.163353 Using namespace: common
11054 13:57:17.264534 / # #
11055 13:57:17.265146 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11056 13:57:17.271649 #
11057 13:57:17.272550 Using /lava-12682934
11059 13:57:17.373703 / # export SHELL=/bin/sh
11060 13:57:17.380352 export SHELL=/bin/sh
11062 13:57:17.481950 / # . /lava-12682934/environment
11063 13:57:17.488567 . /lava-12682934/environment
11065 13:57:17.595317 / # /lava-12682934/bin/lava-test-runner /lava-12682934/0
11066 13:57:17.595576 Test shell timeout: 10s (minimum of the action and connection timeout)
11067 13:57:17.601046 /lava-12682934/bin/lava-test-runner /lava-12682934/0
11068 13:57:17.835328 + export TESTRUN_ID=0_dmesg
11069 13:57:17.838582 + cd /lava-12682934/0/tests/0_dmesg
11070 13:57:17.842219 + cat uuid
11071 13:57:17.856669 + UUID=12682934_<8>[ 27.891792] <LAVA_SIGNAL_STARTRUN 0_dmesg 12682934_1.6.2.3.1>
11072 13:57:17.857095 1.6.2.3.1
11073 13:57:17.857432 + set +x
11074 13:57:17.858018 Received signal: <STARTRUN> 0_dmesg 12682934_1.6.2.3.1
11075 13:57:17.858408 Starting test lava.0_dmesg (12682934_1.6.2.3.1)
11076 13:57:17.858830 Skipping test definition patterns.
11077 13:57:17.863190 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11078 13:57:17.962331 <8>[ 27.997846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11079 13:57:17.963068 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11081 13:57:18.031218 <8>[ 28.066468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11082 13:57:18.032006 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11084 13:57:18.106437 <8>[ 28.141497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11085 13:57:18.107212 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11087 13:57:18.113307 + <8>[ 28.151076] <LAVA_SIGNAL_ENDRUN 0_dmesg 12682934_1.6.2.3.1>
11088 13:57:18.113731 set +x
11089 13:57:18.114318 Received signal: <ENDRUN> 0_dmesg 12682934_1.6.2.3.1
11090 13:57:18.114709 Ending use of test pattern.
11091 13:57:18.115010 Ending test lava.0_dmesg (12682934_1.6.2.3.1), duration 0.26
11093 13:57:18.120167 <LAVA_TEST_RUNNER EXIT>
11094 13:57:18.120886 ok: lava_test_shell seems to have completed
11095 13:57:18.121411 alert: pass
crit: pass
emerg: pass
11096 13:57:18.121813 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11097 13:57:18.122228 end: 3 lava-test-retry (duration 00:00:01) [common]
11098 13:57:18.122643 start: 4 lava-test-retry (timeout 00:01:00) [common]
11099 13:57:18.123043 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11100 13:57:18.123356 Using namespace: common
11102 13:57:18.224369 / # #
11103 13:57:18.225373 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11104 13:57:18.226366 Using /lava-12682934
11106 13:57:18.327540 export SHELL=/bin/sh
11107 13:57:18.328371 #
11109 13:57:18.429882 / # export SHELL=/bin/sh. /lava-12682934/environment
11110 13:57:18.430617
11112 13:57:18.532003 / # . /lava-12682934/environment/lava-12682934/bin/lava-test-runner /lava-12682934/1
11113 13:57:18.532636 Test shell timeout: 10s (minimum of the action and connection timeout)
11114 13:57:18.533198
11115 13:57:18.538205 / # /lava-12682934/bin/lava-test-runner /lava-12682934/1
11116 13:57:18.653445 + export TESTRUN_ID=1_bootrr
11117 13:57:18.656678 + cd /lava-12682934/1/tests/1_bootrr
11118 13:57:18.660362 + cat uuid
11119 13:57:18.672192 + UUID=12682934_<8>[ 28.707497] <LAVA_SIGNAL_STARTRUN 1_bootrr 12682934_1.6.2.3.5>
11120 13:57:18.672666 1.6.2.3.5
11121 13:57:18.673011 + set +x
11122 13:57:18.673584 Received signal: <STARTRUN> 1_bootrr 12682934_1.6.2.3.5
11123 13:57:18.673954 Starting test lava.1_bootrr (12682934_1.6.2.3.5)
11124 13:57:18.674486 Skipping test definition patterns.
11125 13:57:18.686136 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12682934/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11126 13:57:18.688784 + cd /opt/bootrr/libexec/bootrr
11127 13:57:18.689249 + sh helpers/bootrr-auto
11128 13:57:18.748148 /lava-12682934/1/../bin/lava-test-case
11129 13:57:18.778856 <8>[ 28.813833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11130 13:57:18.779769 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11132 13:57:18.831852 /lava-12682934/1/../bin/lava-test-case
11133 13:57:18.861208 <8>[ 28.895945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11134 13:57:18.862025 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11136 13:57:18.885087 /lava-12682934/1/../bin/lava-test-case
11137 13:57:18.909747 <8>[ 28.945042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11138 13:57:18.910110 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11140 13:57:18.967680 /lava-12682934/1/../bin/lava-test-case
11141 13:57:18.991266 <8>[ 29.026732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11142 13:57:18.991664 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11144 13:57:19.027494 /lava-12682934/1/../bin/lava-test-case
11145 13:57:19.055423 <8>[ 29.090280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11146 13:57:19.056102 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11148 13:57:19.091788 /lava-12682934/1/../bin/lava-test-case
11149 13:57:19.115124 <8>[ 29.150469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11150 13:57:19.115421 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11152 13:57:19.153065 /lava-12682934/1/../bin/lava-test-case
11153 13:57:19.179174 <8>[ 29.213978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11154 13:57:19.179973 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11156 13:57:19.210335 /lava-12682934/1/../bin/lava-test-case
11157 13:57:19.236581 <8>[ 29.271799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11158 13:57:19.237413 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11160 13:57:19.259386 /lava-12682934/1/../bin/lava-test-case
11161 13:57:19.284418 <8>[ 29.319246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11162 13:57:19.285254 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11164 13:57:19.319527 /lava-12682934/1/../bin/lava-test-case
11165 13:57:19.343676 <8>[ 29.378992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11166 13:57:19.344394 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11168 13:57:19.372843 /lava-12682934/1/../bin/lava-test-case
11169 13:57:19.396476 <8>[ 29.431494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11170 13:57:19.397270 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11172 13:57:19.431664 /lava-12682934/1/../bin/lava-test-case
11173 13:57:19.456110 <8>[ 29.491344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11174 13:57:19.456820 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11176 13:57:19.488385 /lava-12682934/1/../bin/lava-test-case
11177 13:57:19.512321 <8>[ 29.547733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11178 13:57:19.513015 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11180 13:57:19.545102 /lava-12682934/1/../bin/lava-test-case
11181 13:57:19.568962 <8>[ 29.604209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11182 13:57:19.569776 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11184 13:57:19.604043 /lava-12682934/1/../bin/lava-test-case
11185 13:57:19.632136 <8>[ 29.667397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11186 13:57:19.633241 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11188 13:57:19.656343 /lava-12682934/1/../bin/lava-test-case
11189 13:57:19.688432 <8>[ 29.723347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11190 13:57:19.689206 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11192 13:57:19.724393 /lava-12682934/1/../bin/lava-test-case
11193 13:57:19.751959 <8>[ 29.787635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11194 13:57:19.752232 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11196 13:57:19.772058 /lava-12682934/1/../bin/lava-test-case
11197 13:57:19.799139 <8>[ 29.833900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11198 13:57:19.799951 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11200 13:57:19.837771 /lava-12682934/1/../bin/lava-test-case
11201 13:57:19.864981 <8>[ 29.900695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11202 13:57:19.865342 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11204 13:57:19.886922 /lava-12682934/1/../bin/lava-test-case
11205 13:57:19.908207 <8>[ 29.943991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11206 13:57:19.908492 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11208 13:57:19.939454 /lava-12682934/1/../bin/lava-test-case
11209 13:57:19.960924 <8>[ 29.996867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11210 13:57:19.961188 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11212 13:57:19.984266 /lava-12682934/1/../bin/lava-test-case
11213 13:57:20.005008 <8>[ 30.040229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11214 13:57:20.005468 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11216 13:57:20.038639 /lava-12682934/1/../bin/lava-test-case
11217 13:57:20.062527 <8>[ 30.097964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11218 13:57:20.063210 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11220 13:57:20.082635 /lava-12682934/1/../bin/lava-test-case
11221 13:57:20.106873 <8>[ 30.142289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11222 13:57:20.107550 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11224 13:57:20.138673 /lava-12682934/1/../bin/lava-test-case
11225 13:57:20.164013 <8>[ 30.199368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11226 13:57:20.164853 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11228 13:57:20.201507 /lava-12682934/1/../bin/lava-test-case
11229 13:57:20.234113 <8>[ 30.269255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11230 13:57:20.235007 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11232 13:57:20.259423 /lava-12682934/1/../bin/lava-test-case
11233 13:57:20.287600 <8>[ 30.322966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11234 13:57:20.288561 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11236 13:57:20.327915 /lava-12682934/1/../bin/lava-test-case
11237 13:57:20.352995 <8>[ 30.388173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11238 13:57:20.353770 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11240 13:57:20.378236 /lava-12682934/1/../bin/lava-test-case
11241 13:57:20.408615 <8>[ 30.443896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11242 13:57:20.409320 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11244 13:57:20.445680 /lava-12682934/1/../bin/lava-test-case
11245 13:57:20.476548 <8>[ 30.511635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11246 13:57:20.477329 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11248 13:57:20.513407 /lava-12682934/1/../bin/lava-test-case
11249 13:57:20.539682 <8>[ 30.574780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11250 13:57:20.540467 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11252 13:57:20.573771 /lava-12682934/1/../bin/lava-test-case
11253 13:57:20.599871 <8>[ 30.635047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11254 13:57:20.600607 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11256 13:57:20.634402 /lava-12682934/1/../bin/lava-test-case
11257 13:57:20.657606 <8>[ 30.693076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11258 13:57:20.658303 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11260 13:57:20.684454 /lava-12682934/1/../bin/lava-test-case
11261 13:57:20.707434 <8>[ 30.742670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11262 13:57:20.708360 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11264 13:57:20.745937 /lava-12682934/1/../bin/lava-test-case
11265 13:57:20.778931 <8>[ 30.814280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11266 13:57:20.779760 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11268 13:57:20.813462 /lava-12682934/1/../bin/lava-test-case
11269 13:57:20.842160 <8>[ 30.877437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11270 13:57:20.842539 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11272 13:57:20.861843 /lava-12682934/1/../bin/lava-test-case
11273 13:57:20.885593 <8>[ 30.920548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11274 13:57:20.886460 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11276 13:57:20.922706 /lava-12682934/1/../bin/lava-test-case
11277 13:57:20.952875 <8>[ 30.988293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11278 13:57:20.953612 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11280 13:57:20.983282 /lava-12682934/1/../bin/lava-test-case
11281 13:57:21.009405 <8>[ 31.045309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11282 13:57:21.009689 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11284 13:57:21.044354 /lava-12682934/1/../bin/lava-test-case
11285 13:57:21.072399 <8>[ 31.107539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11286 13:57:21.073167 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11288 13:57:21.097918 /lava-12682934/1/../bin/lava-test-case
11289 13:57:21.127578 <8>[ 31.163568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11290 13:57:21.128052 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11292 13:57:21.164470 /lava-12682934/1/../bin/lava-test-case
11293 13:57:21.195001 <8>[ 31.230606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11294 13:57:21.195851 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11296 13:57:21.219515 /lava-12682934/1/../bin/lava-test-case
11297 13:57:21.245832 <8>[ 31.281094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11298 13:57:21.246508 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11300 13:57:21.279611 /lava-12682934/1/../bin/lava-test-case
11301 13:57:21.307960 <8>[ 31.343381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11302 13:57:21.308819 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11304 13:57:21.339624 /lava-12682934/1/../bin/lava-test-case
11305 13:57:21.368149 <8>[ 31.403280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11306 13:57:21.368928 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11308 13:57:21.402685 /lava-12682934/1/../bin/lava-test-case
11309 13:57:21.432770 <8>[ 31.468095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11310 13:57:21.433675 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11312 13:57:21.456959 /lava-12682934/1/../bin/lava-test-case
11313 13:57:21.489545 <8>[ 31.524660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11314 13:57:21.490357 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11316 13:57:21.528392 /lava-12682934/1/../bin/lava-test-case
11317 13:57:21.560933 <8>[ 31.596696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11318 13:57:21.561694 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11320 13:57:21.585482 /lava-12682934/1/../bin/lava-test-case
11321 13:57:21.616831 <8>[ 31.652517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11322 13:57:21.617540 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11324 13:57:21.659749 /lava-12682934/1/../bin/lava-test-case
11325 13:57:21.688591 <8>[ 31.724009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11326 13:57:21.689389 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11328 13:57:21.725425 /lava-12682934/1/../bin/lava-test-case
11329 13:57:21.755785 <8>[ 31.791198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11330 13:57:21.756064 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11332 13:57:21.778416 /lava-12682934/1/../bin/lava-test-case
11333 13:57:21.807621 <8>[ 31.843416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11334 13:57:21.808324 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11336 13:57:21.844727 /lava-12682934/1/../bin/lava-test-case
11337 13:57:21.874167 <8>[ 31.909779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11338 13:57:21.874858 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11340 13:57:21.894304 /lava-12682934/1/../bin/lava-test-case
11341 13:57:21.916493 <8>[ 31.952425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11342 13:57:21.916872 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11344 13:57:21.949643 /lava-12682934/1/../bin/lava-test-case
11345 13:57:21.976326 <8>[ 32.011474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11346 13:57:21.977257 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11348 13:57:22.020815 /lava-12682934/1/../bin/lava-test-case
11349 13:57:22.052097 <8>[ 32.087732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11350 13:57:22.052832 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11352 13:57:22.088814 /lava-12682934/1/../bin/lava-test-case
11353 13:57:22.119131 <8>[ 32.155054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11354 13:57:22.119819 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11356 13:57:22.154804 /lava-12682934/1/../bin/lava-test-case
11357 13:57:22.180298 <8>[ 32.216208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11358 13:57:22.180659 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11360 13:57:22.207475 /lava-12682934/1/../bin/lava-test-case
11361 13:57:22.234326 <8>[ 32.269960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11362 13:57:22.235021 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11364 13:57:22.256439 /lava-12682934/1/../bin/lava-test-case
11365 13:57:22.285120 <8>[ 32.320497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11366 13:57:22.285826 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11368 13:57:22.317944 /lava-12682934/1/../bin/lava-test-case
11369 13:57:22.344250 <8>[ 32.379779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11370 13:57:22.344986 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11372 13:57:22.384653 /lava-12682934/1/../bin/lava-test-case
11373 13:57:22.414619 <8>[ 32.450196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11374 13:57:22.415557 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11376 13:57:22.436184 /lava-12682934/1/../bin/lava-test-case
11377 13:57:22.461371 <8>[ 32.497172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11378 13:57:22.461922 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11380 13:57:22.499890 /lava-12682934/1/../bin/lava-test-case
11381 13:57:22.531402 <8>[ 32.567113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11382 13:57:22.531977 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11384 13:57:22.552435 /lava-12682934/1/../bin/lava-test-case
11385 13:57:22.579790 <8>[ 32.615423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11386 13:57:22.580382 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11388 13:57:22.614284 /lava-12682934/1/../bin/lava-test-case
11389 13:57:22.638405 <8>[ 32.674281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11390 13:57:22.638944 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11392 13:57:22.659548 /lava-12682934/1/../bin/lava-test-case
11393 13:57:22.683271 <8>[ 32.718893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11394 13:57:22.683806 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11396 13:57:22.724047 /lava-12682934/1/../bin/lava-test-case
11397 13:57:22.749485 <8>[ 32.785321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11398 13:57:22.750113 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11400 13:57:22.784247 /lava-12682934/1/../bin/lava-test-case
11401 13:57:22.812070 <8>[ 32.847781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11402 13:57:22.812970 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11404 13:57:22.847527 /lava-12682934/1/../bin/lava-test-case
11405 13:57:22.871822 <8>[ 32.907321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11406 13:57:22.872195 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11408 13:57:22.904828 /lava-12682934/1/../bin/lava-test-case
11409 13:57:22.929535 <8>[ 32.965667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11410 13:57:22.929907 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11412 13:57:22.960413 /lava-12682934/1/../bin/lava-test-case
11413 13:57:22.982640 <8>[ 33.018367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11414 13:57:22.983022 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11416 13:57:23.011549 /lava-12682934/1/../bin/lava-test-case
11417 13:57:23.035699 <8>[ 33.071499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11418 13:57:23.036066 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11420 13:57:23.071286 /lava-12682934/1/../bin/lava-test-case
11421 13:57:23.094417 <8>[ 33.129848] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11422 13:57:23.095145 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11424 13:57:23.128970 /lava-12682934/1/../bin/lava-test-case
11425 13:57:23.156895 <8>[ 33.192593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11426 13:57:23.157173 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11428 13:57:23.190973 /lava-12682934/1/../bin/lava-test-case
11429 13:57:23.217953 <8>[ 33.253546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11430 13:57:23.218645 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11432 13:57:23.251718 /lava-12682934/1/../bin/lava-test-case
11433 13:57:23.276087 <8>[ 33.312044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11434 13:57:23.276838 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11436 13:57:23.310073 /lava-12682934/1/../bin/lava-test-case
11437 13:57:23.333376 <8>[ 33.369501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11438 13:57:23.333736 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11440 13:57:23.364196 /lava-12682934/1/../bin/lava-test-case
11441 13:57:23.388597 <8>[ 33.423911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11442 13:57:23.389362 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11444 13:57:23.429681 /lava-12682934/1/../bin/lava-test-case
11445 13:57:23.456144 <8>[ 33.492411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11446 13:57:23.456422 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11448 13:57:23.485842 /lava-12682934/1/../bin/lava-test-case
11449 13:57:23.511026 <8>[ 33.547105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11450 13:57:23.511307 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11452 13:57:23.544140 /lava-12682934/1/../bin/lava-test-case
11453 13:57:23.567246 <8>[ 33.602995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11454 13:57:23.567927 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11456 13:57:23.589290 /lava-12682934/1/../bin/lava-test-case
11457 13:57:23.615598 <8>[ 33.651465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11458 13:57:23.616416 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11460 13:57:23.651924 /lava-12682934/1/../bin/lava-test-case
11461 13:57:23.680000 <8>[ 33.715769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11462 13:57:23.680752 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11464 13:57:23.702721 /lava-12682934/1/../bin/lava-test-case
11465 13:57:23.735118 <8>[ 33.770611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11466 13:57:23.736135 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11468 13:57:23.775991 /lava-12682934/1/../bin/lava-test-case
11469 13:57:23.807903 <8>[ 33.843517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11470 13:57:23.808705 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11472 13:57:23.832761 /lava-12682934/1/../bin/lava-test-case
11473 13:57:23.864465 <8>[ 33.899745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11474 13:57:23.865284 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11476 13:57:23.906936 /lava-12682934/1/../bin/lava-test-case
11477 13:57:23.937703 <8>[ 33.973434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11478 13:57:23.938434 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11480 13:57:23.965448 /lava-12682934/1/../bin/lava-test-case
11481 13:57:23.994275 <8>[ 34.030601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11482 13:57:23.994572 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11484 13:57:24.026491 /lava-12682934/1/../bin/lava-test-case
11485 13:57:24.053907 <8>[ 34.090202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11486 13:57:24.054262 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11488 13:57:24.076577 /lava-12682934/1/../bin/lava-test-case
11489 13:57:24.101172 <8>[ 34.136835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11490 13:57:24.101946 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11492 13:57:24.142028 /lava-12682934/1/../bin/lava-test-case
11493 13:57:24.169890 <8>[ 34.206217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11494 13:57:24.170253 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11496 13:57:24.190865 /lava-12682934/1/../bin/lava-test-case
11497 13:57:24.215374 <8>[ 34.251347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11498 13:57:24.215990 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11500 13:57:24.251558 /lava-12682934/1/../bin/lava-test-case
11501 13:57:24.278250 <8>[ 34.314064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11502 13:57:24.278944 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11504 13:57:24.311706 /lava-12682934/1/../bin/lava-test-case
11505 13:57:24.339256 <8>[ 34.374819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11506 13:57:24.339980 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11508 13:57:24.360447 /lava-12682934/1/../bin/lava-test-case
11509 13:57:24.388917 <8>[ 34.424523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11510 13:57:24.389611 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11512 13:57:24.429964 /lava-12682934/1/../bin/lava-test-case
11513 13:57:24.459875 <8>[ 34.495847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11514 13:57:24.460625 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11516 13:57:24.492870 /lava-12682934/1/../bin/lava-test-case
11517 13:57:24.523284 <8>[ 34.559130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11518 13:57:24.524431 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11520 13:57:24.561032 /lava-12682934/1/../bin/lava-test-case
11521 13:57:24.587746 <8>[ 34.623383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11522 13:57:24.588480 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11524 13:57:24.609378 /lava-12682934/1/../bin/lava-test-case
11525 13:57:24.634087 <8>[ 34.670074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11526 13:57:24.634444 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11528 13:57:25.679711 /lava-12682934/1/../bin/lava-test-case
11529 13:57:25.707497 <8>[ 35.743580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11530 13:57:25.708201 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11532 13:57:25.728982 /lava-12682934/1/../bin/lava-test-case
11533 13:57:25.757033 <8>[ 35.793184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11534 13:57:25.757823 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11536 13:57:26.808334 /lava-12682934/1/../bin/lava-test-case
11537 13:57:26.843639 <8>[ 36.879544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11538 13:57:26.844380 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11540 13:57:26.867269 /lava-12682934/1/../bin/lava-test-case
11541 13:57:26.892828 <8>[ 36.929237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11542 13:57:26.893192 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11544 13:57:27.938740 /lava-12682934/1/../bin/lava-test-case
11545 13:57:27.974208 <8>[ 38.010404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11546 13:57:27.975079 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11548 13:57:27.998205 /lava-12682934/1/../bin/lava-test-case
11549 13:57:28.028461 <8>[ 38.064360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11550 13:57:28.029433 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11552 13:57:29.077245 /lava-12682934/1/../bin/lava-test-case
11553 13:57:29.105468 <8>[ 39.142231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11554 13:57:29.106178 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11556 13:57:29.125351 /lava-12682934/1/../bin/lava-test-case
11557 13:57:29.149994 <8>[ 39.186494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11558 13:57:29.150681 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11560 13:57:30.194493 /lava-12682934/1/../bin/lava-test-case
11561 13:57:30.226602 <8>[ 40.262848] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11562 13:57:30.227406 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11564 13:57:30.247032 /lava-12682934/1/../bin/lava-test-case
11565 13:57:30.271139 <8>[ 40.307917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11566 13:57:30.271876 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11568 13:57:31.316895 /lava-12682934/1/../bin/lava-test-case
11569 13:57:31.345300 <8>[ 41.382180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11570 13:57:31.345586 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11572 13:57:31.365700 /lava-12682934/1/../bin/lava-test-case
11573 13:57:31.387289 <8>[ 41.424421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11574 13:57:31.387551 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11576 13:57:32.426634 /lava-12682934/1/../bin/lava-test-case
11577 13:57:32.450996 <8>[ 42.487902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11578 13:57:32.451270 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11580 13:57:32.467739 /lava-12682934/1/../bin/lava-test-case
11581 13:57:32.485703 <8>[ 42.522689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11582 13:57:32.485997 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11584 13:57:32.507790 /lava-12682934/1/../bin/lava-test-case
11585 13:57:32.527631 <8>[ 42.564504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11586 13:57:32.528425 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11588 13:57:33.573724 /lava-12682934/1/../bin/lava-test-case
11589 13:57:33.600805 <8>[ 43.637956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11590 13:57:33.601499 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11592 13:57:33.622345 /lava-12682934/1/../bin/lava-test-case
11593 13:57:33.648369 <8>[ 43.685155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11594 13:57:33.649072 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11596 13:57:33.684430 /lava-12682934/1/../bin/lava-test-case
11597 13:57:33.711214 <8>[ 43.748131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11598 13:57:33.712027 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11600 13:57:33.732682 /lava-12682934/1/../bin/lava-test-case
11601 13:57:33.756589 <8>[ 43.793637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11602 13:57:33.757356 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11604 13:57:33.789107 /lava-12682934/1/../bin/lava-test-case
11605 13:57:33.812951 <8>[ 43.849809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11606 13:57:33.813213 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11608 13:57:33.841561 /lava-12682934/1/../bin/lava-test-case
11609 13:57:33.866829 <8>[ 43.904062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11610 13:57:33.867107 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11612 13:57:33.906862 /lava-12682934/1/../bin/lava-test-case
11613 13:57:33.931792 <8>[ 43.968386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11614 13:57:33.932481 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11616 13:57:33.953121 /lava-12682934/1/../bin/lava-test-case
11617 13:57:33.977846 <8>[ 44.014847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11618 13:57:33.978523 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11620 13:57:34.010317 /lava-12682934/1/../bin/lava-test-case
11621 13:57:34.036110 <8>[ 44.073185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11622 13:57:34.036837 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11624 13:57:34.070775 /lava-12682934/1/../bin/lava-test-case
11625 13:57:34.091583 <8>[ 44.128697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11626 13:57:34.091856 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11628 13:57:34.109204 /lava-12682934/1/../bin/lava-test-case
11629 13:57:34.125376 <8>[ 44.162745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11630 13:57:34.125647 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11632 13:57:34.156193 /lava-12682934/1/../bin/lava-test-case
11633 13:57:34.175692 <8>[ 44.212846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11634 13:57:34.176368 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11636 13:57:34.197553 /lava-12682934/1/../bin/lava-test-case
11637 13:57:34.224837 <8>[ 44.261902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11638 13:57:34.225098 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11640 13:57:34.264142 /lava-12682934/1/../bin/lava-test-case
11641 13:57:34.284980 <8>[ 44.322343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11642 13:57:34.285242 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11644 13:57:34.302928 /lava-12682934/1/../bin/lava-test-case
11645 13:57:34.320982 <8>[ 44.358400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11646 13:57:34.321238 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11648 13:57:34.348787 /lava-12682934/1/../bin/lava-test-case
11649 13:57:34.368092 <8>[ 44.405525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11650 13:57:34.368311 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11652 13:57:34.388352 /lava-12682934/1/../bin/lava-test-case
11653 13:57:34.408441 <8>[ 44.445461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11654 13:57:34.409285 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11656 13:57:34.442201 /lava-12682934/1/../bin/lava-test-case
11657 13:57:34.469553 <8>[ 44.506513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11658 13:57:34.470255 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11660 13:57:34.492851 /lava-12682934/1/../bin/lava-test-case
11661 13:57:34.519542 <8>[ 44.556371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11662 13:57:34.520248 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11664 13:57:34.547768 /lava-12682934/1/../bin/lava-test-case
11665 13:57:34.569766 <8>[ 44.607262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11666 13:57:34.570029 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11668 13:57:34.599045 /lava-12682934/1/../bin/lava-test-case
11669 13:57:34.620994 <8>[ 44.658085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11670 13:57:34.621263 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11672 13:57:35.660258 /lava-12682934/1/../bin/lava-test-case
11673 13:57:35.685747 <8>[ 45.722900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11674 13:57:35.686178 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11676 13:57:36.120709 <6>[ 46.164294] vpu: disabling
11677 13:57:36.123764 <6>[ 46.167415] vproc2: disabling
11678 13:57:36.128742 <6>[ 46.172119] vproc1: disabling
11679 13:57:36.132532 <6>[ 46.176001] vaud18: disabling
11680 13:57:36.139068 <6>[ 46.179513] vsram_others: disabling
11681 13:57:36.142328 <6>[ 46.183582] va09: disabling
11682 13:57:36.145677 <6>[ 46.187588] vsram_md: disabling
11683 13:57:36.148892 <6>[ 46.191373] Vgpu: disabling
11684 13:57:36.727312 /lava-12682934/1/../bin/lava-test-case
11685 13:57:36.755270 <8>[ 46.792584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11686 13:57:36.756148 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11688 13:57:36.776393 /lava-12682934/1/../bin/lava-test-case
11689 13:57:36.798567 <8>[ 46.835874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11690 13:57:36.798841 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11692 13:57:36.825003 /lava-12682934/1/../bin/lava-test-case
11693 13:57:36.846227 <8>[ 46.883576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11694 13:57:36.846525 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11696 13:57:36.864767 /lava-12682934/1/../bin/lava-test-case
11697 13:57:36.883209 <8>[ 46.920668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11698 13:57:36.883476 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11700 13:57:36.909307 /lava-12682934/1/../bin/lava-test-case
11701 13:57:36.926524 <8>[ 46.964229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11702 13:57:36.926884 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11704 13:57:36.946294 /lava-12682934/1/../bin/lava-test-case
11705 13:57:36.967786 <8>[ 47.004770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11706 13:57:36.968525 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11708 13:57:36.998222 /lava-12682934/1/../bin/lava-test-case
11709 13:57:37.023103 <8>[ 47.060304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11710 13:57:37.024081 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11712 13:57:37.050369 /lava-12682934/1/../bin/lava-test-case
11713 13:57:37.074629 <8>[ 47.112115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11714 13:57:37.075352 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11716 13:57:37.104065 /lava-12682934/1/../bin/lava-test-case
11717 13:57:37.126384 <8>[ 47.163815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11718 13:57:37.127126 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11720 13:57:37.149444 /lava-12682934/1/../bin/lava-test-case
11721 13:57:37.173902 <8>[ 47.211526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11722 13:57:37.174155 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11724 13:57:37.203389 /lava-12682934/1/../bin/lava-test-case
11725 13:57:37.231638 <8>[ 47.269248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11726 13:57:37.232226 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11728 13:57:37.254786 /lava-12682934/1/../bin/lava-test-case
11729 13:57:37.279177 <8>[ 47.316866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11730 13:57:37.280072 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11732 13:57:37.309270 /lava-12682934/1/../bin/lava-test-case
11733 13:57:37.329248 <8>[ 47.366701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11734 13:57:37.329511 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11736 13:57:37.353879 /lava-12682934/1/../bin/lava-test-case
11737 13:57:37.374303 <8>[ 47.411990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11738 13:57:37.374568 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11740 13:57:37.401413 /lava-12682934/1/../bin/lava-test-case
11741 13:57:37.422492 <8>[ 47.460222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11742 13:57:37.423033 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11744 13:57:37.443443 /lava-12682934/1/../bin/lava-test-case
11745 13:57:37.467610 <8>[ 47.505136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11746 13:57:37.468450 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11748 13:57:37.499414 /lava-12682934/1/../bin/lava-test-case
11749 13:57:37.529368 <8>[ 47.567040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11750 13:57:37.529655 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11752 13:57:37.548479 /lava-12682934/1/../bin/lava-test-case
11753 13:57:37.569280 <8>[ 47.606753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11754 13:57:37.569548 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11756 13:57:37.600912 /lava-12682934/1/../bin/lava-test-case
11757 13:57:37.623401 <8>[ 47.660805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11758 13:57:37.624252 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11760 13:57:37.643419 /lava-12682934/1/../bin/lava-test-case
11761 13:57:37.668856 <8>[ 47.706101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11762 13:57:37.669632 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11764 13:57:37.699715 /lava-12682934/1/../bin/lava-test-case
11765 13:57:37.718325 <8>[ 47.756103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11766 13:57:37.718620 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11768 13:57:38.748310 /lava-12682934/1/../bin/lava-test-case
11769 13:57:38.772950 <8>[ 48.810599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11770 13:57:38.773296 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11772 13:57:39.801264 /lava-12682934/1/../bin/lava-test-case
11773 13:57:39.830020 <8>[ 49.868135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11774 13:57:39.830292 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11775 13:57:39.830379 Bad test result: blocked
11776 13:57:39.849957 /lava-12682934/1/../bin/lava-test-case
11777 13:57:39.871763 <8>[ 49.909807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11778 13:57:39.872022 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11780 13:57:40.915249 /lava-12682934/1/../bin/lava-test-case
11781 13:57:40.947851 <8>[ 50.985537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11782 13:57:40.948745 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11784 13:57:40.969622 /lava-12682934/1/../bin/lava-test-case
11785 13:57:41.000520 <8>[ 51.037944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11786 13:57:41.001489 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11788 13:57:41.033604 /lava-12682934/1/../bin/lava-test-case
11789 13:57:41.063573 <8>[ 51.101016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11790 13:57:41.064439 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11792 13:57:41.098430 /lava-12682934/1/../bin/lava-test-case
11793 13:57:41.129635 <8>[ 51.167324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11794 13:57:41.130521 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11796 13:57:41.154081 /lava-12682934/1/../bin/lava-test-case
11797 13:57:41.178303 <8>[ 51.215981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11798 13:57:41.178752 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11800 13:57:41.208568 /lava-12682934/1/../bin/lava-test-case
11801 13:57:41.233821 <8>[ 51.271715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11802 13:57:41.234512 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11804 13:57:41.264776 /lava-12682934/1/../bin/lava-test-case
11805 13:57:41.292855 <8>[ 51.330343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11806 13:57:41.293664 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11808 13:57:42.335659 /lava-12682934/1/../bin/lava-test-case
11809 13:57:42.361194 <8>[ 52.399143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11810 13:57:42.361558 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11812 13:57:42.378285 /lava-12682934/1/../bin/lava-test-case
11813 13:57:42.396744 <8>[ 52.435034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11814 13:57:42.397063 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11816 13:57:43.433879 /lava-12682934/1/../bin/lava-test-case
11817 13:57:43.462136 <8>[ 53.500184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11818 13:57:43.462999 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11820 13:57:43.485959 /lava-12682934/1/../bin/lava-test-case
11821 13:57:43.513509 <8>[ 53.551433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11822 13:57:43.514202 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11824 13:57:44.559339 /lava-12682934/1/../bin/lava-test-case
11825 13:57:44.585181 <8>[ 54.623373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11826 13:57:44.585484 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11828 13:57:44.604247 /lava-12682934/1/../bin/lava-test-case
11829 13:57:44.628163 <8>[ 54.666403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11830 13:57:44.628523 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11832 13:57:45.664706 /lava-12682934/1/../bin/lava-test-case
11833 13:57:45.689478 <8>[ 55.727649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11834 13:57:45.689761 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11836 13:57:45.708719 /lava-12682934/1/../bin/lava-test-case
11837 13:57:45.728239 <8>[ 55.766748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11838 13:57:45.728541 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11840 13:57:45.755059 /lava-12682934/1/../bin/lava-test-case
11841 13:57:45.774511 <8>[ 55.813148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11842 13:57:45.774788 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11844 13:57:45.800794 /lava-12682934/1/../bin/lava-test-case
11845 13:57:45.817755 <8>[ 55.856426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11846 13:57:45.818039 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11848 13:57:45.835547 /lava-12682934/1/../bin/lava-test-case
11849 13:57:45.856158 <8>[ 55.894969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11850 13:57:45.856436 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11852 13:57:45.880841 /lava-12682934/1/../bin/lava-test-case
11853 13:57:45.900267 <8>[ 55.939083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11854 13:57:45.900620 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11856 13:57:45.916726 /lava-12682934/1/../bin/lava-test-case
11857 13:57:45.936250 <8>[ 55.975027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11858 13:57:45.936575 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11860 13:57:45.963809 /lava-12682934/1/../bin/lava-test-case
11861 13:57:45.987697 <8>[ 56.025904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11862 13:57:45.987989 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11864 13:57:46.014863 /lava-12682934/1/../bin/lava-test-case
11865 13:57:46.037811 <8>[ 56.076453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11866 13:57:46.038110 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11868 13:57:46.069026 /lava-12682934/1/../bin/lava-test-case
11869 13:57:46.089415 <8>[ 56.128095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11870 13:57:46.089698 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11872 13:57:46.095258 + set +x
11873 13:57:46.098553 Received signal: <ENDRUN> 1_bootrr 12682934_1.6.2.3.5
11874 13:57:46.098643 Ending use of test pattern.
11875 13:57:46.098710 Ending test lava.1_bootrr (12682934_1.6.2.3.5), duration 27.42
11877 13:57:46.101468 <8>[ 56.140108] <LAVA_SIGNAL_ENDRUN 1_bootrr 12682934_1.6.2.3.5>
11878 13:57:46.104777 <LAVA_TEST_RUNNER EXIT>
11879 13:57:46.105029 ok: lava_test_shell seems to have completed
11880 13:57:46.106019 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11881 13:57:46.106160 end: 4.1 lava-test-shell (duration 00:00:28) [common]
11882 13:57:46.106247 end: 4 lava-test-retry (duration 00:00:28) [common]
11883 13:57:46.106333 start: 5 finalize (timeout 00:07:37) [common]
11884 13:57:46.106422 start: 5.1 power-off (timeout 00:00:30) [common]
11885 13:57:46.106571 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11886 13:57:46.177217 >> Command sent successfully.
11887 13:57:46.180041 Returned 0 in 0 seconds
11888 13:57:46.280477 end: 5.1 power-off (duration 00:00:00) [common]
11890 13:57:46.280815 start: 5.2 read-feedback (timeout 00:07:37) [common]
11891 13:57:46.281077 Listened to connection for namespace 'common' for up to 1s
11892 13:57:47.282033 Finalising connection for namespace 'common'
11893 13:57:47.282233 Disconnecting from shell: Finalise
11894 13:57:47.282333 / #
11895 13:57:47.382674 end: 5.2 read-feedback (duration 00:00:01) [common]
11896 13:57:47.382856 end: 5 finalize (duration 00:00:01) [common]
11897 13:57:47.382978 Cleaning after the job
11898 13:57:47.383083 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/ramdisk
11899 13:57:47.385659 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/kernel
11900 13:57:47.399065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/dtb
11901 13:57:47.399256 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/nfsrootfs
11902 13:57:47.473533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682934/tftp-deploy-4nfmyslk/modules
11903 13:57:47.485995 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682934
11904 13:57:47.868083 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682934
11905 13:57:47.868265 Job finished correctly