Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 15
- Kernel Errors: 28
1 13:52:14.964702 lava-dispatcher, installed at version: 2023.10
2 13:52:14.964922 start: 0 validate
3 13:52:14.965051 Start time: 2024-02-01 13:52:14.965044+00:00 (UTC)
4 13:52:14.965165 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:52:14.965291 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:52:15.237997 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:52:15.238216 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:53:02.759329 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:53:02.760045 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:53:03.028836 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:53:03.029612 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:53:06.296071 validate duration: 51.33
14 13:53:06.296364 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:53:06.296459 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:53:06.296545 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:53:06.296678 Not decompressing ramdisk as can be used compressed.
18 13:53:06.296767 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 13:53:06.296832 saving as /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/ramdisk/rootfs.cpio.gz
20 13:53:06.296898 total size: 34390042 (32 MB)
21 13:53:06.562104 progress 0 % (0 MB)
22 13:53:06.573806 progress 5 % (1 MB)
23 13:53:06.583432 progress 10 % (3 MB)
24 13:53:06.593057 progress 15 % (4 MB)
25 13:53:06.602098 progress 20 % (6 MB)
26 13:53:06.611728 progress 25 % (8 MB)
27 13:53:06.621458 progress 30 % (9 MB)
28 13:53:06.631241 progress 35 % (11 MB)
29 13:53:06.640953 progress 40 % (13 MB)
30 13:53:06.650876 progress 45 % (14 MB)
31 13:53:06.660478 progress 50 % (16 MB)
32 13:53:06.670007 progress 55 % (18 MB)
33 13:53:06.679615 progress 60 % (19 MB)
34 13:53:06.689170 progress 65 % (21 MB)
35 13:53:06.698259 progress 70 % (22 MB)
36 13:53:06.707956 progress 75 % (24 MB)
37 13:53:06.717075 progress 80 % (26 MB)
38 13:53:06.726447 progress 85 % (27 MB)
39 13:53:06.735464 progress 90 % (29 MB)
40 13:53:06.744536 progress 95 % (31 MB)
41 13:53:06.753475 progress 100 % (32 MB)
42 13:53:06.753700 32 MB downloaded in 0.46 s (71.80 MB/s)
43 13:53:06.753901 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:53:06.754181 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:53:06.754270 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:53:06.754354 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:53:06.754528 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:53:06.754598 saving as /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/kernel/Image
50 13:53:06.754659 total size: 51532288 (49 MB)
51 13:53:06.754721 No compression specified
52 13:53:06.755860 progress 0 % (0 MB)
53 13:53:06.769262 progress 5 % (2 MB)
54 13:53:06.783369 progress 10 % (4 MB)
55 13:53:06.797020 progress 15 % (7 MB)
56 13:53:06.810897 progress 20 % (9 MB)
57 13:53:06.824803 progress 25 % (12 MB)
58 13:53:06.838078 progress 30 % (14 MB)
59 13:53:06.851616 progress 35 % (17 MB)
60 13:53:06.865294 progress 40 % (19 MB)
61 13:53:06.879338 progress 45 % (22 MB)
62 13:53:06.893799 progress 50 % (24 MB)
63 13:53:06.907955 progress 55 % (27 MB)
64 13:53:06.922290 progress 60 % (29 MB)
65 13:53:06.937064 progress 65 % (31 MB)
66 13:53:06.951403 progress 70 % (34 MB)
67 13:53:06.965429 progress 75 % (36 MB)
68 13:53:06.979413 progress 80 % (39 MB)
69 13:53:06.993267 progress 85 % (41 MB)
70 13:53:07.007587 progress 90 % (44 MB)
71 13:53:07.021419 progress 95 % (46 MB)
72 13:53:07.035461 progress 100 % (49 MB)
73 13:53:07.035728 49 MB downloaded in 0.28 s (174.85 MB/s)
74 13:53:07.035890 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:53:07.036213 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:53:07.036308 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:53:07.036394 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:53:07.036543 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:53:07.036612 saving as /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/dtb/mt8192-asurada-spherion-r0.dtb
81 13:53:07.036674 total size: 47278 (0 MB)
82 13:53:07.036736 No compression specified
83 13:53:07.037993 progress 69 % (0 MB)
84 13:53:07.038280 progress 100 % (0 MB)
85 13:53:07.038480 0 MB downloaded in 0.00 s (25.00 MB/s)
86 13:53:07.038604 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:53:07.038828 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:53:07.038912 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:53:07.038993 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:53:07.039110 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:53:07.039182 saving as /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/modules/modules.tar
93 13:53:07.039243 total size: 8623988 (8 MB)
94 13:53:07.039304 Using unxz to decompress xz
95 13:53:07.044018 progress 0 % (0 MB)
96 13:53:07.066292 progress 5 % (0 MB)
97 13:53:07.091897 progress 10 % (0 MB)
98 13:53:07.116411 progress 15 % (1 MB)
99 13:53:07.140343 progress 20 % (1 MB)
100 13:53:07.164827 progress 25 % (2 MB)
101 13:53:07.191252 progress 30 % (2 MB)
102 13:53:07.218202 progress 35 % (2 MB)
103 13:53:07.241972 progress 40 % (3 MB)
104 13:53:07.266644 progress 45 % (3 MB)
105 13:53:07.292414 progress 50 % (4 MB)
106 13:53:07.317918 progress 55 % (4 MB)
107 13:53:07.345030 progress 60 % (4 MB)
108 13:53:07.376374 progress 65 % (5 MB)
109 13:53:07.404688 progress 70 % (5 MB)
110 13:53:07.429407 progress 75 % (6 MB)
111 13:53:07.457798 progress 80 % (6 MB)
112 13:53:07.485012 progress 85 % (7 MB)
113 13:53:07.510462 progress 90 % (7 MB)
114 13:53:07.543383 progress 95 % (7 MB)
115 13:53:07.572938 progress 100 % (8 MB)
116 13:53:07.577973 8 MB downloaded in 0.54 s (15.27 MB/s)
117 13:53:07.578341 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:53:07.578762 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:53:07.578897 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:53:07.579047 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:53:07.579172 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:53:07.579307 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:53:07.579619 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72
125 13:53:07.579818 makedir: /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin
126 13:53:07.579973 makedir: /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/tests
127 13:53:07.580123 makedir: /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/results
128 13:53:07.580290 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-add-keys
129 13:53:07.580502 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-add-sources
130 13:53:07.580699 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-background-process-start
131 13:53:07.580887 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-background-process-stop
132 13:53:07.581073 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-common-functions
133 13:53:07.581257 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-echo-ipv4
134 13:53:07.581443 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-install-packages
135 13:53:07.581635 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-installed-packages
136 13:53:07.581821 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-os-build
137 13:53:07.582014 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-probe-channel
138 13:53:07.582197 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-probe-ip
139 13:53:07.582388 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-target-ip
140 13:53:07.582582 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-target-mac
141 13:53:07.582775 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-target-storage
142 13:53:07.582972 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-test-case
143 13:53:07.583164 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-test-event
144 13:53:07.583352 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-test-feedback
145 13:53:07.583545 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-test-raise
146 13:53:07.583734 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-test-reference
147 13:53:07.583924 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-test-runner
148 13:53:07.584110 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-test-set
149 13:53:07.584303 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-test-shell
150 13:53:07.584498 Updating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-install-packages (oe)
151 13:53:07.584725 Updating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/bin/lava-installed-packages (oe)
152 13:53:07.584915 Creating /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/environment
153 13:53:07.585069 LAVA metadata
154 13:53:07.585185 - LAVA_JOB_ID=12682904
155 13:53:07.585296 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:53:07.585455 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:53:07.585566 skipped lava-vland-overlay
158 13:53:07.585685 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:53:07.585810 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:53:07.585916 skipped lava-multinode-overlay
161 13:53:07.586046 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:53:07.586182 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:53:07.586308 Loading test definitions
164 13:53:07.586459 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:53:07.586579 Using /lava-12682904 at stage 0
166 13:53:07.587038 uuid=12682904_1.5.2.3.1 testdef=None
167 13:53:07.587167 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:53:07.587296 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:53:07.588054 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:53:07.588406 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:53:07.589320 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:53:07.589676 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:53:07.590577 runner path: /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/0/tests/0_cros-ec test_uuid 12682904_1.5.2.3.1
176 13:53:07.590791 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:53:07.591121 Creating lava-test-runner.conf files
179 13:53:07.591224 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682904/lava-overlay-sd3whu72/lava-12682904/0 for stage 0
180 13:53:07.591359 - 0_cros-ec
181 13:53:07.591502 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:53:07.591637 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:53:07.601363 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:53:07.601554 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:53:07.601691 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:53:07.601828 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:53:07.601972 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:53:08.636894 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:53:08.637384 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:53:08.637553 extracting modules file /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682904/extract-overlay-ramdisk-5648eg4z/ramdisk
191 13:53:08.896465 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:53:08.896643 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 13:53:08.896739 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682904/compress-overlay-6nlf2l7x/overlay-1.5.2.4.tar.gz to ramdisk
194 13:53:08.896818 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682904/compress-overlay-6nlf2l7x/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682904/extract-overlay-ramdisk-5648eg4z/ramdisk
195 13:53:08.903542 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:53:08.903665 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 13:53:08.903759 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:53:08.903851 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 13:53:08.903929 Building ramdisk /var/lib/lava/dispatcher/tmp/12682904/extract-overlay-ramdisk-5648eg4z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682904/extract-overlay-ramdisk-5648eg4z/ramdisk
200 13:53:09.722076 >> 271082 blocks
201 13:53:14.564007 rename /var/lib/lava/dispatcher/tmp/12682904/extract-overlay-ramdisk-5648eg4z/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/ramdisk/ramdisk.cpio.gz
202 13:53:14.564579 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 13:53:14.564788 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 13:53:14.564943 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 13:53:14.565101 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/kernel/Image'
206 13:53:28.170263 Returned 0 in 13 seconds
207 13:53:28.270931 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/kernel/image.itb
208 13:53:29.078493 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:53:29.078873 output: Created: Thu Feb 1 13:53:28 2024
210 13:53:29.078954 output: Image 0 (kernel-1)
211 13:53:29.079023 output: Description:
212 13:53:29.079089 output: Created: Thu Feb 1 13:53:28 2024
213 13:53:29.079152 output: Type: Kernel Image
214 13:53:29.079210 output: Compression: lzma compressed
215 13:53:29.079270 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
216 13:53:29.079326 output: Architecture: AArch64
217 13:53:29.079382 output: OS: Linux
218 13:53:29.079438 output: Load Address: 0x00000000
219 13:53:29.079494 output: Entry Point: 0x00000000
220 13:53:29.079550 output: Hash algo: crc32
221 13:53:29.079622 output: Hash value: 5aa40db2
222 13:53:29.079692 output: Image 1 (fdt-1)
223 13:53:29.079748 output: Description: mt8192-asurada-spherion-r0
224 13:53:29.079801 output: Created: Thu Feb 1 13:53:28 2024
225 13:53:29.079856 output: Type: Flat Device Tree
226 13:53:29.079909 output: Compression: uncompressed
227 13:53:29.079963 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:53:29.080016 output: Architecture: AArch64
229 13:53:29.080069 output: Hash algo: crc32
230 13:53:29.080122 output: Hash value: cc4352de
231 13:53:29.080176 output: Image 2 (ramdisk-1)
232 13:53:29.080228 output: Description: unavailable
233 13:53:29.080281 output: Created: Thu Feb 1 13:53:28 2024
234 13:53:29.080335 output: Type: RAMDisk Image
235 13:53:29.080388 output: Compression: Unknown Compression
236 13:53:29.080441 output: Data Size: 47536029 Bytes = 46421.90 KiB = 45.33 MiB
237 13:53:29.080495 output: Architecture: AArch64
238 13:53:29.080548 output: OS: Linux
239 13:53:29.080601 output: Load Address: unavailable
240 13:53:29.080654 output: Entry Point: unavailable
241 13:53:29.080707 output: Hash algo: crc32
242 13:53:29.080759 output: Hash value: 136099e2
243 13:53:29.080812 output: Default Configuration: 'conf-1'
244 13:53:29.080865 output: Configuration 0 (conf-1)
245 13:53:29.080918 output: Description: mt8192-asurada-spherion-r0
246 13:53:29.080971 output: Kernel: kernel-1
247 13:53:29.081024 output: Init Ramdisk: ramdisk-1
248 13:53:29.081076 output: FDT: fdt-1
249 13:53:29.081129 output: Loadables: kernel-1
250 13:53:29.081182 output:
251 13:53:29.081382 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 13:53:29.081483 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 13:53:29.081588 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 13:53:29.081767 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 13:53:29.081845 No LXC device requested
256 13:53:29.081926 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:53:29.082010 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 13:53:29.082086 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:53:29.082158 Checking files for TFTP limit of 4294967296 bytes.
260 13:53:29.082753 end: 1 tftp-deploy (duration 00:00:23) [common]
261 13:53:29.082876 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:53:29.082997 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:53:29.083163 substitutions:
264 13:53:29.083245 - {DTB}: 12682904/tftp-deploy-erzz8upf/dtb/mt8192-asurada-spherion-r0.dtb
265 13:53:29.083342 - {INITRD}: 12682904/tftp-deploy-erzz8upf/ramdisk/ramdisk.cpio.gz
266 13:53:29.083417 - {KERNEL}: 12682904/tftp-deploy-erzz8upf/kernel/Image
267 13:53:29.083492 - {LAVA_MAC}: None
268 13:53:29.083579 - {PRESEED_CONFIG}: None
269 13:53:29.083637 - {PRESEED_LOCAL}: None
270 13:53:29.083703 - {RAMDISK}: 12682904/tftp-deploy-erzz8upf/ramdisk/ramdisk.cpio.gz
271 13:53:29.083760 - {ROOT_PART}: None
272 13:53:29.083817 - {ROOT}: None
273 13:53:29.083873 - {SERVER_IP}: 192.168.201.1
274 13:53:29.083928 - {TEE}: None
275 13:53:29.083984 Parsed boot commands:
276 13:53:29.084039 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:53:29.084219 Parsed boot commands: tftpboot 192.168.201.1 12682904/tftp-deploy-erzz8upf/kernel/image.itb 12682904/tftp-deploy-erzz8upf/kernel/cmdline
278 13:53:29.084310 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:53:29.084401 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:53:29.084502 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:53:29.084587 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:53:29.084661 Not connected, no need to disconnect.
283 13:53:29.084737 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:53:29.084819 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:53:29.084884 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 13:53:29.089023 Setting prompt string to ['lava-test: # ']
287 13:53:29.089425 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:53:29.089541 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:53:29.089654 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:53:29.089750 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:53:29.090113 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 13:53:34.226038 >> Command sent successfully.
293 13:53:34.228649 Returned 0 in 5 seconds
294 13:53:34.329030 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:53:34.329351 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:53:34.329449 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:53:34.329540 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:53:34.329607 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:53:34.329715 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:53:34.330077 [Enter `^Ec?' for help]
302 13:53:34.507818
303 13:53:34.507975
304 13:53:34.508049 F0: 102B 0000
305 13:53:34.508114
306 13:53:34.508174 F3: 1001 0000 [0200]
307 13:53:34.511163
308 13:53:34.511249 F3: 1001 0000
309 13:53:34.511317
310 13:53:34.511379 F7: 102D 0000
311 13:53:34.511439
312 13:53:34.514310 F1: 0000 0000
313 13:53:34.514456
314 13:53:34.514526 V0: 0000 0000 [0001]
315 13:53:34.514592
316 13:53:34.517641 00: 0007 8000
317 13:53:34.517728
318 13:53:34.517794 01: 0000 0000
319 13:53:34.517858
320 13:53:34.521577 BP: 0C00 0209 [0000]
321 13:53:34.521660
322 13:53:34.521726 G0: 1182 0000
323 13:53:34.521788
324 13:53:34.524891 EC: 0000 0021 [4000]
325 13:53:34.524974
326 13:53:34.525041 S7: 0000 0000 [0000]
327 13:53:34.525102
328 13:53:34.528612 CC: 0000 0000 [0001]
329 13:53:34.528695
330 13:53:34.528762 T0: 0000 0040 [010F]
331 13:53:34.528825
332 13:53:34.528884 Jump to BL
333 13:53:34.528943
334 13:53:34.554703
335 13:53:34.554795
336 13:53:34.554861
337 13:53:34.561688 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:53:34.564714 ARM64: Exception handlers installed.
339 13:53:34.568976 ARM64: Testing exception
340 13:53:34.572489 ARM64: Done test exception
341 13:53:34.578800 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:53:34.589040 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:53:34.595956 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:53:34.606870 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:53:34.612960 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:53:34.619971 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:53:34.631904 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:53:34.638280 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:53:34.657559 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:53:34.660659 WDT: Last reset was cold boot
351 13:53:34.664276 SPI1(PAD0) initialized at 2873684 Hz
352 13:53:34.667496 SPI5(PAD0) initialized at 992727 Hz
353 13:53:34.672071 VBOOT: Loading verstage.
354 13:53:34.677815 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:53:34.680659 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:53:34.684175 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:53:34.687785 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:53:34.694856 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:53:34.701526 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:53:34.712516 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 13:53:34.712601
362 13:53:34.712688
363 13:53:34.723111 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:53:34.726006 ARM64: Exception handlers installed.
365 13:53:34.729901 ARM64: Testing exception
366 13:53:34.729985 ARM64: Done test exception
367 13:53:34.736074 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:53:34.740120 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:53:34.754230 Probing TPM: . done!
370 13:53:34.754316 TPM ready after 0 ms
371 13:53:34.761364 Connected to device vid:did:rid of 1ae0:0028:00
372 13:53:34.768012 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 13:53:34.824268 Initialized TPM device CR50 revision 0
374 13:53:34.836620 tlcl_send_startup: Startup return code is 0
375 13:53:34.836715 TPM: setup succeeded
376 13:53:34.847923 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:53:34.855968 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:53:34.867378 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:53:34.877040 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:53:34.880802 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:53:34.888970 in-header: 03 07 00 00 08 00 00 00
382 13:53:34.892940 in-data: aa e4 47 04 13 02 00 00
383 13:53:34.896423 Chrome EC: UHEPI supported
384 13:53:34.904172 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:53:34.907935 in-header: 03 ad 00 00 08 00 00 00
386 13:53:34.908021 in-data: 00 20 20 08 00 00 00 00
387 13:53:34.911522 Phase 1
388 13:53:34.915175 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:53:34.919520 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:53:34.926642 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:53:34.926752 Recovery requested (1009000e)
392 13:53:34.936987 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:53:34.942734 tlcl_extend: response is 0
394 13:53:34.952528 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:53:34.957663 tlcl_extend: response is 0
396 13:53:34.964646 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:53:34.984309 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 13:53:34.991194 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:53:34.991286
400 13:53:34.991353
401 13:53:35.001855 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:53:35.005635 ARM64: Exception handlers installed.
403 13:53:35.005720 ARM64: Testing exception
404 13:53:35.009601 ARM64: Done test exception
405 13:53:35.030092 pmic_efuse_setting: Set efuses in 11 msecs
406 13:53:35.033696 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:53:35.040783 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:53:35.043895 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:53:35.047286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:53:35.055182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:53:35.058318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:53:35.062280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:53:35.069961 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:53:35.074560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:53:35.077477 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:53:35.081040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:53:35.088859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:53:35.092796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:53:35.096608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:53:35.103578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:53:35.107729 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:53:35.114999 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:53:35.118711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:53:35.126353 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:53:35.129949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:53:35.137637 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:53:35.140955 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:53:35.148661 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:53:35.152787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:53:35.160669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:53:35.163708 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:53:35.172042 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:53:35.175385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:53:35.178537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:53:35.185469 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:53:35.189982 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:53:35.193670 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:53:35.197762 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:53:35.204710 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:53:35.208784 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:53:35.215151 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:53:35.219188 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:53:35.222698 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:53:35.230135 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:53:35.234715 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:53:35.237545 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:53:35.241412 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:53:35.244967 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:53:35.252672 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:53:35.255646 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:53:35.259589 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:53:35.263122 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:53:35.267418 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:53:35.270945 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:53:35.278210 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:53:35.282162 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:53:35.285830 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:53:35.292981 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:53:35.300564 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:53:35.308058 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:53:35.314535 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:53:35.322458 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:53:35.325743 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:53:35.333280 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:53:35.337156 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:53:35.344027 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 13:53:35.348028 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:53:35.355040 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 13:53:35.358105 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:53:35.368279 [RTC]rtc_get_frequency_meter,154: input=15, output=791
471 13:53:35.376632 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 13:53:35.386487 [RTC]rtc_get_frequency_meter,154: input=19, output=885
473 13:53:35.396562 [RTC]rtc_get_frequency_meter,154: input=17, output=838
474 13:53:35.406177 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 13:53:35.415351 [RTC]rtc_get_frequency_meter,154: input=15, output=791
476 13:53:35.424966 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 13:53:35.429084 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 13:53:35.432311 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 13:53:35.436543 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 13:53:35.443278 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 13:53:35.447398 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 13:53:35.450990 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 13:53:35.454572 ADC[4]: Raw value=902066 ID=7
484 13:53:35.454709 ADC[3]: Raw value=213336 ID=1
485 13:53:35.458316 RAM Code: 0x71
486 13:53:35.462229 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 13:53:35.466009 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 13:53:35.477055 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 13:53:35.481224 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 13:53:35.484319 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 13:53:35.488796 in-header: 03 07 00 00 08 00 00 00
492 13:53:35.493442 in-data: aa e4 47 04 13 02 00 00
493 13:53:35.496409 Chrome EC: UHEPI supported
494 13:53:35.503596 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 13:53:35.507284 in-header: 03 ed 00 00 08 00 00 00
496 13:53:35.507413 in-data: 80 20 60 08 00 00 00 00
497 13:53:35.510832 MRC: failed to locate region type 0.
498 13:53:35.518375 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 13:53:35.523128 DRAM-K: Running full calibration
500 13:53:35.529207 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 13:53:35.529345 header.status = 0x0
502 13:53:35.533442 header.version = 0x6 (expected: 0x6)
503 13:53:35.536705 header.size = 0xd00 (expected: 0xd00)
504 13:53:35.536812 header.flags = 0x0
505 13:53:35.544065 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 13:53:35.563109 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
507 13:53:35.569982 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 13:53:35.573563 dram_init: ddr_geometry: 2
509 13:53:35.573671 [EMI] MDL number = 2
510 13:53:35.577714 [EMI] Get MDL freq = 0
511 13:53:35.577812 dram_init: ddr_type: 0
512 13:53:35.581119 is_discrete_lpddr4: 1
513 13:53:35.581216 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 13:53:35.584831
515 13:53:35.584921
516 13:53:35.584989 [Bian_co] ETT version 0.0.0.1
517 13:53:35.589169 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 13:53:35.592999
519 13:53:35.596209 dramc_set_vcore_voltage set vcore to 650000
520 13:53:35.596307 Read voltage for 800, 4
521 13:53:35.596377 Vio18 = 0
522 13:53:35.600002 Vcore = 650000
523 13:53:35.600094 Vdram = 0
524 13:53:35.600173 Vddq = 0
525 13:53:35.603801 Vmddr = 0
526 13:53:35.603893 dram_init: config_dvfs: 1
527 13:53:35.609922 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 13:53:35.613394 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 13:53:35.616580 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 13:53:35.623333 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 13:53:35.627199 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 13:53:35.630681 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 13:53:35.633726 MEM_TYPE=3, freq_sel=18
534 13:53:35.633816 sv_algorithm_assistance_LP4_1600
535 13:53:35.640422 ============ PULL DRAM RESETB DOWN ============
536 13:53:35.643473 ========== PULL DRAM RESETB DOWN end =========
537 13:53:35.647096 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 13:53:35.650710 ===================================
539 13:53:35.653986 LPDDR4 DRAM CONFIGURATION
540 13:53:35.657967 ===================================
541 13:53:35.660551 EX_ROW_EN[0] = 0x0
542 13:53:35.660640 EX_ROW_EN[1] = 0x0
543 13:53:35.664017 LP4Y_EN = 0x0
544 13:53:35.664105 WORK_FSP = 0x0
545 13:53:35.667077 WL = 0x2
546 13:53:35.667162 RL = 0x2
547 13:53:35.670297 BL = 0x2
548 13:53:35.670382 RPST = 0x0
549 13:53:35.673895 RD_PRE = 0x0
550 13:53:35.673983 WR_PRE = 0x1
551 13:53:35.677333 WR_PST = 0x0
552 13:53:35.677420 DBI_WR = 0x0
553 13:53:35.680319 DBI_RD = 0x0
554 13:53:35.680411 OTF = 0x1
555 13:53:35.683965 ===================================
556 13:53:35.687288 ===================================
557 13:53:35.690382 ANA top config
558 13:53:35.694064 ===================================
559 13:53:35.694176 DLL_ASYNC_EN = 0
560 13:53:35.697376 ALL_SLAVE_EN = 1
561 13:53:35.701084 NEW_RANK_MODE = 1
562 13:53:35.704040 DLL_IDLE_MODE = 1
563 13:53:35.704137 LP45_APHY_COMB_EN = 1
564 13:53:35.707228 TX_ODT_DIS = 1
565 13:53:35.711130 NEW_8X_MODE = 1
566 13:53:35.714467 ===================================
567 13:53:35.717352 ===================================
568 13:53:35.720646 data_rate = 1600
569 13:53:35.724575 CKR = 1
570 13:53:35.724701 DQ_P2S_RATIO = 8
571 13:53:35.727613 ===================================
572 13:53:35.731026 CA_P2S_RATIO = 8
573 13:53:35.735202 DQ_CA_OPEN = 0
574 13:53:35.737523 DQ_SEMI_OPEN = 0
575 13:53:35.741162 CA_SEMI_OPEN = 0
576 13:53:35.744939 CA_FULL_RATE = 0
577 13:53:35.745046 DQ_CKDIV4_EN = 1
578 13:53:35.747553 CA_CKDIV4_EN = 1
579 13:53:35.750841 CA_PREDIV_EN = 0
580 13:53:35.754635 PH8_DLY = 0
581 13:53:35.757512 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 13:53:35.761535 DQ_AAMCK_DIV = 4
583 13:53:35.761647 CA_AAMCK_DIV = 4
584 13:53:35.764313 CA_ADMCK_DIV = 4
585 13:53:35.767773 DQ_TRACK_CA_EN = 0
586 13:53:35.771021 CA_PICK = 800
587 13:53:35.774418 CA_MCKIO = 800
588 13:53:35.778587 MCKIO_SEMI = 0
589 13:53:35.778709 PLL_FREQ = 3068
590 13:53:35.781662 DQ_UI_PI_RATIO = 32
591 13:53:35.785806 CA_UI_PI_RATIO = 0
592 13:53:35.789244 ===================================
593 13:53:35.793012 ===================================
594 13:53:35.793132 memory_type:LPDDR4
595 13:53:35.796642 GP_NUM : 10
596 13:53:35.796742 SRAM_EN : 1
597 13:53:35.800703 MD32_EN : 0
598 13:53:35.804402 ===================================
599 13:53:35.804517 [ANA_INIT] >>>>>>>>>>>>>>
600 13:53:35.808336 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 13:53:35.811941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 13:53:35.815895 ===================================
603 13:53:35.818675 data_rate = 1600,PCW = 0X7600
604 13:53:35.822191 ===================================
605 13:53:35.825271 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 13:53:35.829095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:53:35.836045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 13:53:35.839018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 13:53:35.842252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:53:35.845941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 13:53:35.849082 [ANA_INIT] flow start
612 13:53:35.853078 [ANA_INIT] PLL >>>>>>>>
613 13:53:35.853172 [ANA_INIT] PLL <<<<<<<<
614 13:53:35.855879 [ANA_INIT] MIDPI >>>>>>>>
615 13:53:35.859398 [ANA_INIT] MIDPI <<<<<<<<
616 13:53:35.863394 [ANA_INIT] DLL >>>>>>>>
617 13:53:35.863492 [ANA_INIT] flow end
618 13:53:35.866070 ============ LP4 DIFF to SE enter ============
619 13:53:35.873117 ============ LP4 DIFF to SE exit ============
620 13:53:35.873221 [ANA_INIT] <<<<<<<<<<<<<
621 13:53:35.876379 [Flow] Enable top DCM control >>>>>
622 13:53:35.879828 [Flow] Enable top DCM control <<<<<
623 13:53:35.883114 Enable DLL master slave shuffle
624 13:53:35.889140 ==============================================================
625 13:53:35.889245 Gating Mode config
626 13:53:35.896409 ==============================================================
627 13:53:35.899432 Config description:
628 13:53:35.906060 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 13:53:35.912964 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 13:53:35.919859 SELPH_MODE 0: By rank 1: By Phase
631 13:53:35.923207 ==============================================================
632 13:53:35.926068 GAT_TRACK_EN = 1
633 13:53:35.929039 RX_GATING_MODE = 2
634 13:53:35.932767 RX_GATING_TRACK_MODE = 2
635 13:53:35.936289 SELPH_MODE = 1
636 13:53:35.939213 PICG_EARLY_EN = 1
637 13:53:35.943879 VALID_LAT_VALUE = 1
638 13:53:35.950048 ==============================================================
639 13:53:35.953055 Enter into Gating configuration >>>>
640 13:53:35.953175 Exit from Gating configuration <<<<
641 13:53:35.956190 Enter into DVFS_PRE_config >>>>>
642 13:53:35.969750 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 13:53:35.973442 Exit from DVFS_PRE_config <<<<<
644 13:53:35.976288 Enter into PICG configuration >>>>
645 13:53:35.976395 Exit from PICG configuration <<<<
646 13:53:35.980876 [RX_INPUT] configuration >>>>>
647 13:53:35.983338 [RX_INPUT] configuration <<<<<
648 13:53:35.989734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 13:53:35.994163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 13:53:36.000297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 13:53:36.007050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 13:53:36.013941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 13:53:36.021028 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 13:53:36.024611 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 13:53:36.027577 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 13:53:36.030792 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 13:53:36.034989 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 13:53:36.041133 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 13:53:36.044178 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 13:53:36.047684 ===================================
661 13:53:36.050941 LPDDR4 DRAM CONFIGURATION
662 13:53:36.054453 ===================================
663 13:53:36.054559 EX_ROW_EN[0] = 0x0
664 13:53:36.058728 EX_ROW_EN[1] = 0x0
665 13:53:36.058828 LP4Y_EN = 0x0
666 13:53:36.060959 WORK_FSP = 0x0
667 13:53:36.061047 WL = 0x2
668 13:53:36.064252 RL = 0x2
669 13:53:36.064348 BL = 0x2
670 13:53:36.067451 RPST = 0x0
671 13:53:36.067544 RD_PRE = 0x0
672 13:53:36.071109 WR_PRE = 0x1
673 13:53:36.071202 WR_PST = 0x0
674 13:53:36.074126 DBI_WR = 0x0
675 13:53:36.074220 DBI_RD = 0x0
676 13:53:36.077734 OTF = 0x1
677 13:53:36.080956 ===================================
678 13:53:36.084419 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 13:53:36.087790 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 13:53:36.094535 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 13:53:36.098106 ===================================
682 13:53:36.098215 LPDDR4 DRAM CONFIGURATION
683 13:53:36.100929 ===================================
684 13:53:36.105328 EX_ROW_EN[0] = 0x10
685 13:53:36.107576 EX_ROW_EN[1] = 0x0
686 13:53:36.107676 LP4Y_EN = 0x0
687 13:53:36.111309 WORK_FSP = 0x0
688 13:53:36.111407 WL = 0x2
689 13:53:36.114591 RL = 0x2
690 13:53:36.114687 BL = 0x2
691 13:53:36.117677 RPST = 0x0
692 13:53:36.117796 RD_PRE = 0x0
693 13:53:36.121236 WR_PRE = 0x1
694 13:53:36.121328 WR_PST = 0x0
695 13:53:36.125084 DBI_WR = 0x0
696 13:53:36.125176 DBI_RD = 0x0
697 13:53:36.128535 OTF = 0x1
698 13:53:36.131792 ===================================
699 13:53:36.134874 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 13:53:36.140280 nWR fixed to 40
701 13:53:36.143748 [ModeRegInit_LP4] CH0 RK0
702 13:53:36.143850 [ModeRegInit_LP4] CH0 RK1
703 13:53:36.146686 [ModeRegInit_LP4] CH1 RK0
704 13:53:36.150325 [ModeRegInit_LP4] CH1 RK1
705 13:53:36.150451 match AC timing 13
706 13:53:36.157843 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 13:53:36.160276 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 13:53:36.163675 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 13:53:36.170617 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 13:53:36.173687 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 13:53:36.173794 [EMI DOE] emi_dcm 0
712 13:53:36.181137 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 13:53:36.181263 ==
714 13:53:36.184448 Dram Type= 6, Freq= 0, CH_0, rank 0
715 13:53:36.187070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 13:53:36.187165 ==
717 13:53:36.194233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 13:53:36.197187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 13:53:36.208143 [CA 0] Center 37 (7~68) winsize 62
720 13:53:36.211510 [CA 1] Center 37 (6~68) winsize 63
721 13:53:36.214100 [CA 2] Center 35 (4~66) winsize 63
722 13:53:36.217959 [CA 3] Center 34 (4~65) winsize 62
723 13:53:36.221407 [CA 4] Center 33 (3~64) winsize 62
724 13:53:36.224682 [CA 5] Center 33 (3~64) winsize 62
725 13:53:36.224782
726 13:53:36.227986 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 13:53:36.228097
728 13:53:36.231157 [CATrainingPosCal] consider 1 rank data
729 13:53:36.234603 u2DelayCellTimex100 = 270/100 ps
730 13:53:36.237947 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 13:53:36.241829 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 13:53:36.244904 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
733 13:53:36.251358 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 13:53:36.255474 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:53:36.258195 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 13:53:36.258294
737 13:53:36.261477 CA PerBit enable=1, Macro0, CA PI delay=33
738 13:53:36.261576
739 13:53:36.265611 [CBTSetCACLKResult] CA Dly = 33
740 13:53:36.265712 CS Dly: 5 (0~36)
741 13:53:36.265781 ==
742 13:53:36.268219 Dram Type= 6, Freq= 0, CH_0, rank 1
743 13:53:36.271725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 13:53:36.275166 ==
745 13:53:36.278662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 13:53:36.285743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 13:53:36.294116 [CA 0] Center 37 (7~68) winsize 62
748 13:53:36.297721 [CA 1] Center 37 (7~68) winsize 62
749 13:53:36.300449 [CA 2] Center 35 (4~66) winsize 63
750 13:53:36.304035 [CA 3] Center 35 (4~66) winsize 63
751 13:53:36.307725 [CA 4] Center 33 (3~64) winsize 62
752 13:53:36.310390 [CA 5] Center 33 (3~64) winsize 62
753 13:53:36.310555
754 13:53:36.313809 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 13:53:36.313908
756 13:53:36.317667 [CATrainingPosCal] consider 2 rank data
757 13:53:36.321741 u2DelayCellTimex100 = 270/100 ps
758 13:53:36.323979 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:53:36.327428 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 13:53:36.334571 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
761 13:53:36.337728 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 13:53:36.341229 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:53:36.344172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 13:53:36.344302
765 13:53:36.347948 CA PerBit enable=1, Macro0, CA PI delay=33
766 13:53:36.348077
767 13:53:36.350932 [CBTSetCACLKResult] CA Dly = 33
768 13:53:36.351051 CS Dly: 6 (0~38)
769 13:53:36.351151
770 13:53:36.354662 ----->DramcWriteLeveling(PI) begin...
771 13:53:36.354787 ==
772 13:53:36.357792 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:53:36.364658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:53:36.364809 ==
775 13:53:36.364914 Write leveling (Byte 0): 31 => 31
776 13:53:36.368448 Write leveling (Byte 1): 31 => 31
777 13:53:36.371946 DramcWriteLeveling(PI) end<-----
778 13:53:36.372080
779 13:53:36.372183 ==
780 13:53:36.375960 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:53:36.379427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:53:36.379562 ==
783 13:53:36.382779 [Gating] SW mode calibration
784 13:53:36.389026 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 13:53:36.396719 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 13:53:36.400251 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:53:36.403338 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 13:53:36.410256 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 13:53:36.413272 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:53:36.416447 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:53:36.420819 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:53:36.426917 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:53:36.430384 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:53:36.433724 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:53:36.440399 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:53:36.443697 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:53:36.446875 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:53:36.453801 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:53:36.457246 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:53:36.460976 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:53:36.467486 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:53:36.471280 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:53:36.473967 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:53:36.480396 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 13:53:36.484041 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:53:36.487016 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:53:36.490798 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:53:36.497414 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:53:36.500989 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:53:36.503760 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:53:36.510590 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:53:36.514495 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 13:53:36.517125 0 9 12 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
814 13:53:36.524792 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:53:36.527509 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:53:36.530736 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:53:36.537933 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:53:36.541017 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:53:36.544180 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 13:53:36.547388 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
821 13:53:36.554219 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
822 13:53:36.558233 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:53:36.561021 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:53:36.567726 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:53:36.571307 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:53:36.575059 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:53:36.581665 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:53:36.584774 0 11 8 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
829 13:53:36.587975 0 11 12 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
830 13:53:36.594694 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:53:36.597968 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:53:36.601311 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:53:36.607925 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:53:36.611296 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:53:36.614633 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:53:36.618161 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 13:53:36.625434 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:53:36.627871 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:53:36.631511 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:53:36.638252 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:53:36.641457 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:53:36.645081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:53:36.652087 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:53:36.655241 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:53:36.659292 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:53:36.664997 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:53:36.668150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:53:36.671506 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:53:36.674991 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:53:36.682225 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:53:36.685522 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:53:36.689039 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 13:53:36.695370 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 13:53:36.695497 Total UI for P1: 0, mck2ui 16
855 13:53:36.702141 best dqsien dly found for B0: ( 0, 14, 8)
856 13:53:36.702267 Total UI for P1: 0, mck2ui 16
857 13:53:36.708809 best dqsien dly found for B1: ( 0, 14, 8)
858 13:53:36.712212 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 13:53:36.715480 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 13:53:36.715587
861 13:53:36.718572 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 13:53:36.721671 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 13:53:36.725257 [Gating] SW calibration Done
864 13:53:36.725357 ==
865 13:53:36.728332 Dram Type= 6, Freq= 0, CH_0, rank 0
866 13:53:36.731708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 13:53:36.731813 ==
868 13:53:36.736053 RX Vref Scan: 0
869 13:53:36.736175
870 13:53:36.736245 RX Vref 0 -> 0, step: 1
871 13:53:36.736308
872 13:53:36.738864 RX Delay -130 -> 252, step: 16
873 13:53:36.741938 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 13:53:36.748789 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 13:53:36.751812 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 13:53:36.755272 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
877 13:53:36.759276 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 13:53:36.762383 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 13:53:36.765364 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 13:53:36.772379 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 13:53:36.775754 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
882 13:53:36.778999 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 13:53:36.782118 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 13:53:36.785819 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 13:53:36.792059 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
886 13:53:36.795794 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 13:53:36.798768 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 13:53:36.802534 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 13:53:36.802632 ==
890 13:53:36.805830 Dram Type= 6, Freq= 0, CH_0, rank 0
891 13:53:36.812567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 13:53:36.812726 ==
893 13:53:36.812824 DQS Delay:
894 13:53:36.812915 DQS0 = 0, DQS1 = 0
895 13:53:36.815816 DQM Delay:
896 13:53:36.815906 DQM0 = 83, DQM1 = 74
897 13:53:36.818917 DQ Delay:
898 13:53:36.822477 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
899 13:53:36.822582 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
900 13:53:36.826278 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
901 13:53:36.829643 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
902 13:53:36.829742
903 13:53:36.832514
904 13:53:36.832602 ==
905 13:53:36.836164 Dram Type= 6, Freq= 0, CH_0, rank 0
906 13:53:36.839638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 13:53:36.839737 ==
908 13:53:36.839808
909 13:53:36.839870
910 13:53:36.842707 TX Vref Scan disable
911 13:53:36.842795 == TX Byte 0 ==
912 13:53:36.849448 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 13:53:36.854684 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 13:53:36.854809 == TX Byte 1 ==
915 13:53:36.856198 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 13:53:36.862681 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 13:53:36.862798 ==
918 13:53:36.865823 Dram Type= 6, Freq= 0, CH_0, rank 0
919 13:53:36.869503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 13:53:36.869615 ==
921 13:53:36.882595 TX Vref=22, minBit 5, minWin=27, winSum=440
922 13:53:36.885796 TX Vref=24, minBit 5, minWin=27, winSum=448
923 13:53:36.889825 TX Vref=26, minBit 9, minWin=27, winSum=451
924 13:53:36.893468 TX Vref=28, minBit 12, minWin=27, winSum=457
925 13:53:36.896230 TX Vref=30, minBit 2, minWin=28, winSum=459
926 13:53:36.899787 TX Vref=32, minBit 3, minWin=28, winSum=456
927 13:53:36.906554 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
928 13:53:36.906687
929 13:53:36.910015 Final TX Range 1 Vref 30
930 13:53:36.910115
931 13:53:36.910216 ==
932 13:53:36.913087 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:53:36.916247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:53:36.916344 ==
935 13:53:36.916433
936 13:53:36.916514
937 13:53:36.919650 TX Vref Scan disable
938 13:53:36.923040 == TX Byte 0 ==
939 13:53:36.926389 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 13:53:36.929818 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 13:53:36.932974 == TX Byte 1 ==
942 13:53:36.936573 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 13:53:36.940832 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 13:53:36.940940
945 13:53:36.943271 [DATLAT]
946 13:53:36.943362 Freq=800, CH0 RK0
947 13:53:36.943450
948 13:53:36.946801 DATLAT Default: 0xa
949 13:53:36.946891 0, 0xFFFF, sum = 0
950 13:53:36.950317 1, 0xFFFF, sum = 0
951 13:53:36.950463 2, 0xFFFF, sum = 0
952 13:53:36.953263 3, 0xFFFF, sum = 0
953 13:53:36.953352 4, 0xFFFF, sum = 0
954 13:53:36.956643 5, 0xFFFF, sum = 0
955 13:53:36.956735 6, 0xFFFF, sum = 0
956 13:53:36.960330 7, 0xFFFF, sum = 0
957 13:53:36.960427 8, 0xFFFF, sum = 0
958 13:53:36.963642 9, 0x0, sum = 1
959 13:53:36.963735 10, 0x0, sum = 2
960 13:53:36.966331 11, 0x0, sum = 3
961 13:53:36.966473 12, 0x0, sum = 4
962 13:53:36.969754 best_step = 10
963 13:53:36.969842
964 13:53:36.969909 ==
965 13:53:36.973285 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:53:36.976610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:53:36.976710 ==
968 13:53:36.980287 RX Vref Scan: 1
969 13:53:36.980401
970 13:53:36.980529 Set Vref Range= 32 -> 127
971 13:53:36.980702
972 13:53:36.983629 RX Vref 32 -> 127, step: 1
973 13:53:36.983714
974 13:53:36.986392 RX Delay -95 -> 252, step: 8
975 13:53:36.986518
976 13:53:36.990663 Set Vref, RX VrefLevel [Byte0]: 32
977 13:53:36.993305 [Byte1]: 32
978 13:53:36.993398
979 13:53:36.996538 Set Vref, RX VrefLevel [Byte0]: 33
980 13:53:37.000101 [Byte1]: 33
981 13:53:37.000245
982 13:53:37.003826 Set Vref, RX VrefLevel [Byte0]: 34
983 13:53:37.007289 [Byte1]: 34
984 13:53:37.011198
985 13:53:37.011313 Set Vref, RX VrefLevel [Byte0]: 35
986 13:53:37.013689 [Byte1]: 35
987 13:53:37.018095
988 13:53:37.018195 Set Vref, RX VrefLevel [Byte0]: 36
989 13:53:37.021858 [Byte1]: 36
990 13:53:37.025961
991 13:53:37.026060 Set Vref, RX VrefLevel [Byte0]: 37
992 13:53:37.028924 [Byte1]: 37
993 13:53:37.034184
994 13:53:37.034328 Set Vref, RX VrefLevel [Byte0]: 38
995 13:53:37.036874 [Byte1]: 38
996 13:53:37.041748
997 13:53:37.041861 Set Vref, RX VrefLevel [Byte0]: 39
998 13:53:37.045548 [Byte1]: 39
999 13:53:37.048850
1000 13:53:37.048954 Set Vref, RX VrefLevel [Byte0]: 40
1001 13:53:37.052140 [Byte1]: 40
1002 13:53:37.056369
1003 13:53:37.056474 Set Vref, RX VrefLevel [Byte0]: 41
1004 13:53:37.059962 [Byte1]: 41
1005 13:53:37.064594
1006 13:53:37.064701 Set Vref, RX VrefLevel [Byte0]: 42
1007 13:53:37.067327 [Byte1]: 42
1008 13:53:37.071203
1009 13:53:37.071302 Set Vref, RX VrefLevel [Byte0]: 43
1010 13:53:37.074782 [Byte1]: 43
1011 13:53:37.078755
1012 13:53:37.078856 Set Vref, RX VrefLevel [Byte0]: 44
1013 13:53:37.081998 [Byte1]: 44
1014 13:53:37.086591
1015 13:53:37.086691 Set Vref, RX VrefLevel [Byte0]: 45
1016 13:53:37.089726 [Byte1]: 45
1017 13:53:37.094238
1018 13:53:37.094339 Set Vref, RX VrefLevel [Byte0]: 46
1019 13:53:37.097277 [Byte1]: 46
1020 13:53:37.101508
1021 13:53:37.101605 Set Vref, RX VrefLevel [Byte0]: 47
1022 13:53:37.104907 [Byte1]: 47
1023 13:53:37.109220
1024 13:53:37.109328 Set Vref, RX VrefLevel [Byte0]: 48
1025 13:53:37.112459 [Byte1]: 48
1026 13:53:37.117659
1027 13:53:37.117775 Set Vref, RX VrefLevel [Byte0]: 49
1028 13:53:37.120236 [Byte1]: 49
1029 13:53:37.124830
1030 13:53:37.124938 Set Vref, RX VrefLevel [Byte0]: 50
1031 13:53:37.128211 [Byte1]: 50
1032 13:53:37.131850
1033 13:53:37.131944 Set Vref, RX VrefLevel [Byte0]: 51
1034 13:53:37.136175 [Byte1]: 51
1035 13:53:37.139727
1036 13:53:37.139826 Set Vref, RX VrefLevel [Byte0]: 52
1037 13:53:37.143116 [Byte1]: 52
1038 13:53:37.147597
1039 13:53:37.147700 Set Vref, RX VrefLevel [Byte0]: 53
1040 13:53:37.150715 [Byte1]: 53
1041 13:53:37.155221
1042 13:53:37.155324 Set Vref, RX VrefLevel [Byte0]: 54
1043 13:53:37.157973 [Byte1]: 54
1044 13:53:37.162918
1045 13:53:37.163019 Set Vref, RX VrefLevel [Byte0]: 55
1046 13:53:37.166549 [Byte1]: 55
1047 13:53:37.170167
1048 13:53:37.170282 Set Vref, RX VrefLevel [Byte0]: 56
1049 13:53:37.173437 [Byte1]: 56
1050 13:53:37.177562
1051 13:53:37.177667 Set Vref, RX VrefLevel [Byte0]: 57
1052 13:53:37.181232 [Byte1]: 57
1053 13:53:37.185474
1054 13:53:37.185579 Set Vref, RX VrefLevel [Byte0]: 58
1055 13:53:37.188576 [Byte1]: 58
1056 13:53:37.192941
1057 13:53:37.193043 Set Vref, RX VrefLevel [Byte0]: 59
1058 13:53:37.196658 [Byte1]: 59
1059 13:53:37.201022
1060 13:53:37.201125 Set Vref, RX VrefLevel [Byte0]: 60
1061 13:53:37.204101 [Byte1]: 60
1062 13:53:37.207873
1063 13:53:37.207973 Set Vref, RX VrefLevel [Byte0]: 61
1064 13:53:37.212151 [Byte1]: 61
1065 13:53:37.215356
1066 13:53:37.215457 Set Vref, RX VrefLevel [Byte0]: 62
1067 13:53:37.218929 [Byte1]: 62
1068 13:53:37.223500
1069 13:53:37.223604 Set Vref, RX VrefLevel [Byte0]: 63
1070 13:53:37.226662 [Byte1]: 63
1071 13:53:37.231092
1072 13:53:37.231191 Set Vref, RX VrefLevel [Byte0]: 64
1073 13:53:37.234302 [Byte1]: 64
1074 13:53:37.238839
1075 13:53:37.238936 Set Vref, RX VrefLevel [Byte0]: 65
1076 13:53:37.241974 [Byte1]: 65
1077 13:53:37.246136
1078 13:53:37.246231 Set Vref, RX VrefLevel [Byte0]: 66
1079 13:53:37.249442 [Byte1]: 66
1080 13:53:37.253230
1081 13:53:37.253325 Set Vref, RX VrefLevel [Byte0]: 67
1082 13:53:37.257021 [Byte1]: 67
1083 13:53:37.261179
1084 13:53:37.261277 Set Vref, RX VrefLevel [Byte0]: 68
1085 13:53:37.265205 [Byte1]: 68
1086 13:53:37.269169
1087 13:53:37.269261 Set Vref, RX VrefLevel [Byte0]: 69
1088 13:53:37.272476 [Byte1]: 69
1089 13:53:37.276570
1090 13:53:37.276670 Set Vref, RX VrefLevel [Byte0]: 70
1091 13:53:37.279389 [Byte1]: 70
1092 13:53:37.283966
1093 13:53:37.284074 Set Vref, RX VrefLevel [Byte0]: 71
1094 13:53:37.287374 [Byte1]: 71
1095 13:53:37.291335
1096 13:53:37.291430 Set Vref, RX VrefLevel [Byte0]: 72
1097 13:53:37.295156 [Byte1]: 72
1098 13:53:37.299052
1099 13:53:37.299150 Set Vref, RX VrefLevel [Byte0]: 73
1100 13:53:37.302132 [Byte1]: 73
1101 13:53:37.306858
1102 13:53:37.306958 Set Vref, RX VrefLevel [Byte0]: 74
1103 13:53:37.310465 [Byte1]: 74
1104 13:53:37.314707
1105 13:53:37.314812 Set Vref, RX VrefLevel [Byte0]: 75
1106 13:53:37.317568 [Byte1]: 75
1107 13:53:37.321959
1108 13:53:37.322060 Set Vref, RX VrefLevel [Byte0]: 76
1109 13:53:37.326113 [Byte1]: 76
1110 13:53:37.329378
1111 13:53:37.329476 Final RX Vref Byte 0 = 60 to rank0
1112 13:53:37.333119 Final RX Vref Byte 1 = 55 to rank0
1113 13:53:37.336435 Final RX Vref Byte 0 = 60 to rank1
1114 13:53:37.339981 Final RX Vref Byte 1 = 55 to rank1==
1115 13:53:37.343078 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 13:53:37.346332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 13:53:37.350007 ==
1118 13:53:37.350110 DQS Delay:
1119 13:53:37.350212 DQS0 = 0, DQS1 = 0
1120 13:53:37.353003 DQM Delay:
1121 13:53:37.353123 DQM0 = 87, DQM1 = 79
1122 13:53:37.356422 DQ Delay:
1123 13:53:37.356527 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1124 13:53:37.360204 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1125 13:53:37.363462 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1126 13:53:37.366611 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1127 13:53:37.366701
1128 13:53:37.366765
1129 13:53:37.377350 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1130 13:53:37.379908 CH0 RK0: MR19=606, MR18=2B11
1131 13:53:37.387091 CH0_RK0: MR19=0x606, MR18=0x2B11, DQSOSC=398, MR23=63, INC=93, DEC=62
1132 13:53:37.387213
1133 13:53:37.390040 ----->DramcWriteLeveling(PI) begin...
1134 13:53:37.390126 ==
1135 13:53:37.394362 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 13:53:37.396982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 13:53:37.397078 ==
1138 13:53:37.399851 Write leveling (Byte 0): 30 => 30
1139 13:53:37.403335 Write leveling (Byte 1): 30 => 30
1140 13:53:37.406574 DramcWriteLeveling(PI) end<-----
1141 13:53:37.406665
1142 13:53:37.406752 ==
1143 13:53:37.410169 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 13:53:37.413439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 13:53:37.413533 ==
1146 13:53:37.416640 [Gating] SW mode calibration
1147 13:53:37.423740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 13:53:37.426951 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 13:53:37.433626 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 13:53:37.436895 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1151 13:53:37.440473 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 13:53:37.484245 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:53:37.484629 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:53:37.484898 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:53:37.485164 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:53:37.485238 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:53:37.485848 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:53:37.486657 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:53:37.486959 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:53:37.487289 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:53:37.487388 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:53:37.489848 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:53:37.493204 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:53:37.499639 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:53:37.502977 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:53:37.506522 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 13:53:37.514903 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1168 13:53:37.516388 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1169 13:53:37.519846 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:53:37.526903 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:53:37.530068 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:53:37.533879 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:53:37.539955 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:53:37.543339 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1175 13:53:37.546928 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1176 13:53:37.550603 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1177 13:53:37.557871 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 13:53:37.560111 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:53:37.563745 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:53:37.570026 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:53:37.573557 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1182 13:53:37.577173 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
1183 13:53:37.584153 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1184 13:53:37.587514 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:53:37.590289 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:53:37.596815 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:53:37.600659 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:53:37.604349 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:53:37.607050 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:53:37.614539 0 11 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1191 13:53:37.618107 0 11 8 | B1->B0 | 2929 3b3b | 0 1 | (0 0) (0 0)
1192 13:53:37.621998 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1193 13:53:37.626086 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:53:37.631993 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:53:37.635443 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:53:37.639385 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:53:37.643023 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:53:37.649611 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 13:53:37.653250 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:53:37.656266 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 13:53:37.659599 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:53:37.666505 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:53:37.669536 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:53:37.673480 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:53:37.680204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:53:37.683292 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:53:37.686837 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:53:37.693063 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:53:37.696978 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:53:37.700094 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:53:37.706588 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:53:37.709773 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:53:37.713466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:53:37.719785 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1215 13:53:37.719932 Total UI for P1: 0, mck2ui 16
1216 13:53:37.723922 best dqsien dly found for B0: ( 0, 14, 2)
1217 13:53:37.730213 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1218 13:53:37.733586 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 13:53:37.736895 Total UI for P1: 0, mck2ui 16
1220 13:53:37.740399 best dqsien dly found for B1: ( 0, 14, 8)
1221 13:53:37.743968 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1222 13:53:37.747383 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 13:53:37.747503
1224 13:53:37.750593 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1225 13:53:37.753919 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 13:53:37.757996 [Gating] SW calibration Done
1227 13:53:37.758119 ==
1228 13:53:37.760365 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 13:53:37.764197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 13:53:37.767362 ==
1231 13:53:37.767479 RX Vref Scan: 0
1232 13:53:37.767574
1233 13:53:37.770446 RX Vref 0 -> 0, step: 1
1234 13:53:37.770562
1235 13:53:37.774377 RX Delay -130 -> 252, step: 16
1236 13:53:37.777275 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 13:53:37.780201 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1238 13:53:37.784780 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 13:53:37.787344 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 13:53:37.790297 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1241 13:53:37.797413 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 13:53:37.801107 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1243 13:53:37.804677 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1244 13:53:37.807194 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 13:53:37.811038 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 13:53:37.817479 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1247 13:53:37.820573 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 13:53:37.824125 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1249 13:53:37.827244 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 13:53:37.831116 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1251 13:53:37.837683 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1252 13:53:37.837817 ==
1253 13:53:37.840944 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 13:53:37.844405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 13:53:37.844524 ==
1256 13:53:37.844620 DQS Delay:
1257 13:53:37.847693 DQS0 = 0, DQS1 = 0
1258 13:53:37.847801 DQM Delay:
1259 13:53:37.851388 DQM0 = 85, DQM1 = 75
1260 13:53:37.851498 DQ Delay:
1261 13:53:37.854089 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1262 13:53:37.858305 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1263 13:53:37.860764 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1264 13:53:37.864305 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1265 13:53:37.864419
1266 13:53:37.864515
1267 13:53:37.864605 ==
1268 13:53:37.867881 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 13:53:37.870897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 13:53:37.871010 ==
1271 13:53:37.871104
1272 13:53:37.871194
1273 13:53:37.874385 TX Vref Scan disable
1274 13:53:37.878020 == TX Byte 0 ==
1275 13:53:37.880907 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 13:53:37.884440 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 13:53:37.887847 == TX Byte 1 ==
1278 13:53:37.891195 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1279 13:53:37.894283 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1280 13:53:37.894423 ==
1281 13:53:37.898051 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 13:53:37.902094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 13:53:37.904983 ==
1284 13:53:37.915994 TX Vref=22, minBit 0, minWin=27, winSum=444
1285 13:53:37.919259 TX Vref=24, minBit 3, minWin=27, winSum=447
1286 13:53:37.922698 TX Vref=26, minBit 7, minWin=27, winSum=452
1287 13:53:37.925959 TX Vref=28, minBit 3, minWin=27, winSum=453
1288 13:53:37.928870 TX Vref=30, minBit 0, minWin=28, winSum=457
1289 13:53:37.932549 TX Vref=32, minBit 2, minWin=28, winSum=455
1290 13:53:37.939518 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1291 13:53:37.939666
1292 13:53:37.942386 Final TX Range 1 Vref 30
1293 13:53:37.942543
1294 13:53:37.942636 ==
1295 13:53:37.945691 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 13:53:37.949351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 13:53:37.949481 ==
1298 13:53:37.949577
1299 13:53:37.949666
1300 13:53:37.952907 TX Vref Scan disable
1301 13:53:37.956221 == TX Byte 0 ==
1302 13:53:37.959156 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1303 13:53:37.963189 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1304 13:53:37.966311 == TX Byte 1 ==
1305 13:53:37.969292 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1306 13:53:37.972422 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1307 13:53:37.972541
1308 13:53:37.975875 [DATLAT]
1309 13:53:37.975987 Freq=800, CH0 RK1
1310 13:53:37.976081
1311 13:53:37.979120 DATLAT Default: 0xa
1312 13:53:37.979233 0, 0xFFFF, sum = 0
1313 13:53:37.983018 1, 0xFFFF, sum = 0
1314 13:53:37.983136 2, 0xFFFF, sum = 0
1315 13:53:37.985765 3, 0xFFFF, sum = 0
1316 13:53:37.985875 4, 0xFFFF, sum = 0
1317 13:53:37.989022 5, 0xFFFF, sum = 0
1318 13:53:37.989157 6, 0xFFFF, sum = 0
1319 13:53:37.993607 7, 0xFFFF, sum = 0
1320 13:53:37.993701 8, 0xFFFF, sum = 0
1321 13:53:37.996576 9, 0x0, sum = 1
1322 13:53:37.996671 10, 0x0, sum = 2
1323 13:53:37.999387 11, 0x0, sum = 3
1324 13:53:37.999494 12, 0x0, sum = 4
1325 13:53:38.002599 best_step = 10
1326 13:53:38.002715
1327 13:53:38.002819 ==
1328 13:53:38.005841 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 13:53:38.009029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 13:53:38.009153 ==
1331 13:53:38.012713 RX Vref Scan: 0
1332 13:53:38.012874
1333 13:53:38.012967 RX Vref 0 -> 0, step: 1
1334 13:53:38.013058
1335 13:53:38.016239 RX Delay -95 -> 252, step: 8
1336 13:53:38.022841 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1337 13:53:38.026627 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 13:53:38.029523 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 13:53:38.033310 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 13:53:38.036921 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 13:53:38.039713 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 13:53:38.046310 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 13:53:38.049704 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 13:53:38.052544 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 13:53:38.056314 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 13:53:38.060185 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 13:53:38.066854 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 13:53:38.069698 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 13:53:38.073256 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1350 13:53:38.076452 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 13:53:38.079732 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 13:53:38.082992 ==
1353 13:53:38.083109 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 13:53:38.089936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 13:53:38.090065 ==
1356 13:53:38.090158 DQS Delay:
1357 13:53:38.093290 DQS0 = 0, DQS1 = 0
1358 13:53:38.093400 DQM Delay:
1359 13:53:38.093493 DQM0 = 87, DQM1 = 77
1360 13:53:38.096353 DQ Delay:
1361 13:53:38.099967 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1362 13:53:38.103602 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 13:53:38.106554 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 13:53:38.109639 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1365 13:53:38.109757
1366 13:53:38.109845
1367 13:53:38.116810 [DQSOSCAuto] RK1, (LSB)MR18= 0x3019, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1368 13:53:38.121211 CH0 RK1: MR19=606, MR18=3019
1369 13:53:38.126390 CH0_RK1: MR19=0x606, MR18=0x3019, DQSOSC=397, MR23=63, INC=93, DEC=62
1370 13:53:38.130027 [RxdqsGatingPostProcess] freq 800
1371 13:53:38.133380 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 13:53:38.136911 Pre-setting of DQS Precalculation
1373 13:53:38.143301 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 13:53:38.143445 ==
1375 13:53:38.146357 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 13:53:38.150158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 13:53:38.150275 ==
1378 13:53:38.156750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 13:53:38.160903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 13:53:38.170402 [CA 0] Center 36 (6~66) winsize 61
1381 13:53:38.173644 [CA 1] Center 36 (6~66) winsize 61
1382 13:53:38.176901 [CA 2] Center 34 (4~65) winsize 62
1383 13:53:38.180966 [CA 3] Center 33 (3~64) winsize 62
1384 13:53:38.184021 [CA 4] Center 34 (4~65) winsize 62
1385 13:53:38.186831 [CA 5] Center 33 (3~64) winsize 62
1386 13:53:38.186946
1387 13:53:38.190026 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 13:53:38.190133
1389 13:53:38.193657 [CATrainingPosCal] consider 1 rank data
1390 13:53:38.196992 u2DelayCellTimex100 = 270/100 ps
1391 13:53:38.200427 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 13:53:38.204147 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 13:53:38.206979 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1394 13:53:38.213747 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 13:53:38.217565 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 13:53:38.220159 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 13:53:38.220272
1398 13:53:38.223847 CA PerBit enable=1, Macro0, CA PI delay=33
1399 13:53:38.223962
1400 13:53:38.227322 [CBTSetCACLKResult] CA Dly = 33
1401 13:53:38.227435 CS Dly: 4 (0~35)
1402 13:53:38.227524 ==
1403 13:53:38.230506 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 13:53:38.237217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 13:53:38.237356 ==
1406 13:53:38.240198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 13:53:38.246809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 13:53:38.256450 [CA 0] Center 36 (6~66) winsize 61
1409 13:53:38.259619 [CA 1] Center 36 (6~66) winsize 61
1410 13:53:38.262936 [CA 2] Center 34 (3~65) winsize 63
1411 13:53:38.266821 [CA 3] Center 33 (3~64) winsize 62
1412 13:53:38.269646 [CA 4] Center 33 (3~64) winsize 62
1413 13:53:38.273450 [CA 5] Center 33 (3~64) winsize 62
1414 13:53:38.273571
1415 13:53:38.276353 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 13:53:38.276464
1417 13:53:38.280634 [CATrainingPosCal] consider 2 rank data
1418 13:53:38.284287 u2DelayCellTimex100 = 270/100 ps
1419 13:53:38.287893 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 13:53:38.292379 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 13:53:38.296200 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1422 13:53:38.299049 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 13:53:38.302557 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1424 13:53:38.306777 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 13:53:38.306906
1426 13:53:38.309961 CA PerBit enable=1, Macro0, CA PI delay=33
1427 13:53:38.310056
1428 13:53:38.313513 [CBTSetCACLKResult] CA Dly = 33
1429 13:53:38.313605 CS Dly: 5 (0~37)
1430 13:53:38.313693
1431 13:53:38.317764 ----->DramcWriteLeveling(PI) begin...
1432 13:53:38.317894 ==
1433 13:53:38.320220 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 13:53:38.324268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 13:53:38.327059 ==
1436 13:53:38.327174 Write leveling (Byte 0): 29 => 29
1437 13:53:38.330469 Write leveling (Byte 1): 30 => 30
1438 13:53:38.333925 DramcWriteLeveling(PI) end<-----
1439 13:53:38.334040
1440 13:53:38.334134 ==
1441 13:53:38.337346 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 13:53:38.344170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 13:53:38.344306 ==
1444 13:53:38.344398 [Gating] SW mode calibration
1445 13:53:38.353860 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 13:53:38.357241 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 13:53:38.360931 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 13:53:38.367569 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 13:53:38.371347 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1450 13:53:38.374499 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:53:38.381015 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:53:38.384288 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:53:38.387606 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:53:38.395215 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:53:38.398173 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:53:38.401191 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1457 13:53:38.404385 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:53:38.411072 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1459 13:53:38.414603 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1460 13:53:38.418430 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1461 13:53:38.424831 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1462 13:53:38.427681 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1463 13:53:38.431478 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 13:53:38.438574 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 13:53:38.442114 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1466 13:53:38.445013 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:53:38.451584 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:53:38.454757 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:53:38.458341 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:53:38.464737 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1471 13:53:38.468429 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:53:38.471690 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:53:38.474695 0 9 8 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 0)
1474 13:53:38.481548 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 13:53:38.485398 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:53:38.488288 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:53:38.495972 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:53:38.498678 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1479 13:53:38.501497 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 13:53:38.508669 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1481 13:53:38.511904 0 10 8 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (1 0)
1482 13:53:38.515310 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1483 13:53:38.518796 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:53:38.525606 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:53:38.528959 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1486 13:53:38.532244 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:53:38.539822 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:53:38.542682 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1489 13:53:38.545506 0 11 8 | B1->B0 | 3434 2e2e | 0 0 | (1 1) (0 0)
1490 13:53:38.552311 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1491 13:53:38.555663 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:53:38.559181 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:53:38.565839 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:53:38.569123 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:53:38.572662 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:53:38.576067 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1497 13:53:38.582635 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:53:38.586376 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:53:38.589311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:53:38.595913 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:53:38.599318 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:53:38.602435 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:53:38.609305 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:53:38.613174 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:53:38.615983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:53:38.622860 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:53:38.626145 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:53:38.630192 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:53:38.633254 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:53:38.639568 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:53:38.642793 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:53:38.646411 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 13:53:38.653788 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 13:53:38.656388 Total UI for P1: 0, mck2ui 16
1515 13:53:38.659677 best dqsien dly found for B0: ( 0, 14, 4)
1516 13:53:38.659770 Total UI for P1: 0, mck2ui 16
1517 13:53:38.666556 best dqsien dly found for B1: ( 0, 14, 4)
1518 13:53:38.670167 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1519 13:53:38.673608 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1520 13:53:38.673703
1521 13:53:38.676636 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1522 13:53:38.680212 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 13:53:38.683228 [Gating] SW calibration Done
1524 13:53:38.683322 ==
1525 13:53:38.686893 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 13:53:38.690379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 13:53:38.690496 ==
1528 13:53:38.693223 RX Vref Scan: 0
1529 13:53:38.693310
1530 13:53:38.693396 RX Vref 0 -> 0, step: 1
1531 13:53:38.693476
1532 13:53:38.696637 RX Delay -130 -> 252, step: 16
1533 13:53:38.700058 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1534 13:53:38.706708 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1535 13:53:38.710588 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1536 13:53:38.713884 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1537 13:53:38.717272 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1538 13:53:38.719980 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1539 13:53:38.723334 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1540 13:53:38.730223 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1541 13:53:38.733438 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1542 13:53:38.736817 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1543 13:53:38.739906 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1544 13:53:38.743341 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1545 13:53:38.750044 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1546 13:53:38.753410 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1547 13:53:38.757264 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1548 13:53:38.760196 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1549 13:53:38.760306 ==
1550 13:53:38.763283 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 13:53:38.770238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 13:53:38.770381 ==
1553 13:53:38.770523 DQS Delay:
1554 13:53:38.770606 DQS0 = 0, DQS1 = 0
1555 13:53:38.773496 DQM Delay:
1556 13:53:38.773584 DQM0 = 85, DQM1 = 76
1557 13:53:38.777705 DQ Delay:
1558 13:53:38.780151 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1559 13:53:38.780245 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1560 13:53:38.783493 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1561 13:53:38.790161 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1562 13:53:38.790285
1563 13:53:38.790390
1564 13:53:38.790511 ==
1565 13:53:38.793938 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 13:53:38.797317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 13:53:38.797418 ==
1568 13:53:38.797505
1569 13:53:38.797585
1570 13:53:38.800597 TX Vref Scan disable
1571 13:53:38.800687 == TX Byte 0 ==
1572 13:53:38.807369 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1573 13:53:38.810341 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1574 13:53:38.810483 == TX Byte 1 ==
1575 13:53:38.816953 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1576 13:53:38.820495 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1577 13:53:38.820656 ==
1578 13:53:38.823771 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 13:53:38.827080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 13:53:38.827209 ==
1581 13:53:38.840363 TX Vref=22, minBit 1, minWin=27, winSum=440
1582 13:53:38.844367 TX Vref=24, minBit 1, minWin=27, winSum=443
1583 13:53:38.847846 TX Vref=26, minBit 1, minWin=27, winSum=444
1584 13:53:38.850673 TX Vref=28, minBit 0, minWin=28, winSum=449
1585 13:53:38.854062 TX Vref=30, minBit 0, minWin=28, winSum=451
1586 13:53:38.857490 TX Vref=32, minBit 0, minWin=28, winSum=451
1587 13:53:38.865341 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
1588 13:53:38.865523
1589 13:53:38.868465 Final TX Range 1 Vref 30
1590 13:53:38.868592
1591 13:53:38.868683 ==
1592 13:53:38.871761 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 13:53:38.874908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 13:53:38.875031 ==
1595 13:53:38.875126
1596 13:53:38.875211
1597 13:53:38.878616 TX Vref Scan disable
1598 13:53:38.881676 == TX Byte 0 ==
1599 13:53:38.884867 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1600 13:53:38.889144 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1601 13:53:38.891657 == TX Byte 1 ==
1602 13:53:38.895522 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1603 13:53:38.898776 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1604 13:53:38.898911
1605 13:53:38.899009 [DATLAT]
1606 13:53:38.902383 Freq=800, CH1 RK0
1607 13:53:38.902558
1608 13:53:38.902686 DATLAT Default: 0xa
1609 13:53:38.905937 0, 0xFFFF, sum = 0
1610 13:53:38.906054 1, 0xFFFF, sum = 0
1611 13:53:38.908460 2, 0xFFFF, sum = 0
1612 13:53:38.908571 3, 0xFFFF, sum = 0
1613 13:53:38.911952 4, 0xFFFF, sum = 0
1614 13:53:38.915791 5, 0xFFFF, sum = 0
1615 13:53:38.915931 6, 0xFFFF, sum = 0
1616 13:53:38.919160 7, 0xFFFF, sum = 0
1617 13:53:38.919286 8, 0xFFFF, sum = 0
1618 13:53:38.919383 9, 0x0, sum = 1
1619 13:53:38.922023 10, 0x0, sum = 2
1620 13:53:38.922133 11, 0x0, sum = 3
1621 13:53:38.925647 12, 0x0, sum = 4
1622 13:53:38.925776 best_step = 10
1623 13:53:38.925870
1624 13:53:38.925960 ==
1625 13:53:38.928500 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 13:53:38.935187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 13:53:38.935349 ==
1628 13:53:38.935452 RX Vref Scan: 1
1629 13:53:38.935542
1630 13:53:38.938601 Set Vref Range= 32 -> 127
1631 13:53:38.938723
1632 13:53:38.942220 RX Vref 32 -> 127, step: 1
1633 13:53:38.942340
1634 13:53:38.945864 RX Delay -111 -> 252, step: 8
1635 13:53:38.945996
1636 13:53:38.949060 Set Vref, RX VrefLevel [Byte0]: 32
1637 13:53:38.949185 [Byte1]: 32
1638 13:53:38.953385
1639 13:53:38.953526 Set Vref, RX VrefLevel [Byte0]: 33
1640 13:53:38.956325 [Byte1]: 33
1641 13:53:38.961355
1642 13:53:38.961502 Set Vref, RX VrefLevel [Byte0]: 34
1643 13:53:38.964608 [Byte1]: 34
1644 13:53:38.968386
1645 13:53:38.968514 Set Vref, RX VrefLevel [Byte0]: 35
1646 13:53:38.971954 [Byte1]: 35
1647 13:53:38.976418
1648 13:53:38.976559 Set Vref, RX VrefLevel [Byte0]: 36
1649 13:53:38.979213 [Byte1]: 36
1650 13:53:38.984346
1651 13:53:38.984515 Set Vref, RX VrefLevel [Byte0]: 37
1652 13:53:38.987155 [Byte1]: 37
1653 13:53:38.991517
1654 13:53:38.991652 Set Vref, RX VrefLevel [Byte0]: 38
1655 13:53:38.995100 [Byte1]: 38
1656 13:53:38.999480
1657 13:53:38.999622 Set Vref, RX VrefLevel [Byte0]: 39
1658 13:53:39.003449 [Byte1]: 39
1659 13:53:39.006565
1660 13:53:39.006692 Set Vref, RX VrefLevel [Byte0]: 40
1661 13:53:39.010819 [Byte1]: 40
1662 13:53:39.014250
1663 13:53:39.014390 Set Vref, RX VrefLevel [Byte0]: 41
1664 13:53:39.017795 [Byte1]: 41
1665 13:53:39.022500
1666 13:53:39.022655 Set Vref, RX VrefLevel [Byte0]: 42
1667 13:53:39.025560 [Byte1]: 42
1668 13:53:39.029329
1669 13:53:39.029463 Set Vref, RX VrefLevel [Byte0]: 43
1670 13:53:39.032874 [Byte1]: 43
1671 13:53:39.036993
1672 13:53:39.037135 Set Vref, RX VrefLevel [Byte0]: 44
1673 13:53:39.040842 [Byte1]: 44
1674 13:53:39.045244
1675 13:53:39.045384 Set Vref, RX VrefLevel [Byte0]: 45
1676 13:53:39.048439 [Byte1]: 45
1677 13:53:39.052974
1678 13:53:39.053126 Set Vref, RX VrefLevel [Byte0]: 46
1679 13:53:39.056280 [Byte1]: 46
1680 13:53:39.060265
1681 13:53:39.060407 Set Vref, RX VrefLevel [Byte0]: 47
1682 13:53:39.063428 [Byte1]: 47
1683 13:53:39.067867
1684 13:53:39.068017 Set Vref, RX VrefLevel [Byte0]: 48
1685 13:53:39.071045 [Byte1]: 48
1686 13:53:39.075867
1687 13:53:39.076012 Set Vref, RX VrefLevel [Byte0]: 49
1688 13:53:39.078634 [Byte1]: 49
1689 13:53:39.083443
1690 13:53:39.083605 Set Vref, RX VrefLevel [Byte0]: 50
1691 13:53:39.086221 [Byte1]: 50
1692 13:53:39.090958
1693 13:53:39.091102 Set Vref, RX VrefLevel [Byte0]: 51
1694 13:53:39.094120 [Byte1]: 51
1695 13:53:39.098493
1696 13:53:39.098654 Set Vref, RX VrefLevel [Byte0]: 52
1697 13:53:39.101589 [Byte1]: 52
1698 13:53:39.106355
1699 13:53:39.106558 Set Vref, RX VrefLevel [Byte0]: 53
1700 13:53:39.110586 [Byte1]: 53
1701 13:53:39.113630
1702 13:53:39.113769 Set Vref, RX VrefLevel [Byte0]: 54
1703 13:53:39.116978 [Byte1]: 54
1704 13:53:39.121190
1705 13:53:39.121339 Set Vref, RX VrefLevel [Byte0]: 55
1706 13:53:39.124459 [Byte1]: 55
1707 13:53:39.128868
1708 13:53:39.129016 Set Vref, RX VrefLevel [Byte0]: 56
1709 13:53:39.132338 [Byte1]: 56
1710 13:53:39.137024
1711 13:53:39.137166 Set Vref, RX VrefLevel [Byte0]: 57
1712 13:53:39.141297 [Byte1]: 57
1713 13:53:39.144996
1714 13:53:39.145129 Set Vref, RX VrefLevel [Byte0]: 58
1715 13:53:39.148072 [Byte1]: 58
1716 13:53:39.152285
1717 13:53:39.152425 Set Vref, RX VrefLevel [Byte0]: 59
1718 13:53:39.155347 [Byte1]: 59
1719 13:53:39.159557
1720 13:53:39.159679 Set Vref, RX VrefLevel [Byte0]: 60
1721 13:53:39.162934 [Byte1]: 60
1722 13:53:39.167382
1723 13:53:39.167519 Set Vref, RX VrefLevel [Byte0]: 61
1724 13:53:39.170768 [Byte1]: 61
1725 13:53:39.175699
1726 13:53:39.175834 Set Vref, RX VrefLevel [Byte0]: 62
1727 13:53:39.178376 [Byte1]: 62
1728 13:53:39.182837
1729 13:53:39.182980 Set Vref, RX VrefLevel [Byte0]: 63
1730 13:53:39.186206 [Byte1]: 63
1731 13:53:39.190887
1732 13:53:39.191013 Set Vref, RX VrefLevel [Byte0]: 64
1733 13:53:39.193662 [Byte1]: 64
1734 13:53:39.198177
1735 13:53:39.198296 Set Vref, RX VrefLevel [Byte0]: 65
1736 13:53:39.201064 [Byte1]: 65
1737 13:53:39.205401
1738 13:53:39.205520 Set Vref, RX VrefLevel [Byte0]: 66
1739 13:53:39.209007 [Byte1]: 66
1740 13:53:39.213039
1741 13:53:39.213213 Set Vref, RX VrefLevel [Byte0]: 67
1742 13:53:39.216257 [Byte1]: 67
1743 13:53:39.220664
1744 13:53:39.220789 Set Vref, RX VrefLevel [Byte0]: 68
1745 13:53:39.223929 [Byte1]: 68
1746 13:53:39.229156
1747 13:53:39.229292 Set Vref, RX VrefLevel [Byte0]: 69
1748 13:53:39.231766 [Byte1]: 69
1749 13:53:39.236415
1750 13:53:39.236533 Set Vref, RX VrefLevel [Byte0]: 70
1751 13:53:39.239619 [Byte1]: 70
1752 13:53:39.244058
1753 13:53:39.244176 Set Vref, RX VrefLevel [Byte0]: 71
1754 13:53:39.246974 [Byte1]: 71
1755 13:53:39.251484
1756 13:53:39.251599 Set Vref, RX VrefLevel [Byte0]: 72
1757 13:53:39.254903 [Byte1]: 72
1758 13:53:39.259382
1759 13:53:39.259508 Set Vref, RX VrefLevel [Byte0]: 73
1760 13:53:39.262626 [Byte1]: 73
1761 13:53:39.266624
1762 13:53:39.266745 Set Vref, RX VrefLevel [Byte0]: 74
1763 13:53:39.270668 [Byte1]: 74
1764 13:53:39.274960
1765 13:53:39.275084 Set Vref, RX VrefLevel [Byte0]: 75
1766 13:53:39.277838 [Byte1]: 75
1767 13:53:39.282302
1768 13:53:39.282472 Set Vref, RX VrefLevel [Byte0]: 76
1769 13:53:39.285541 [Byte1]: 76
1770 13:53:39.289575
1771 13:53:39.289699 Set Vref, RX VrefLevel [Byte0]: 77
1772 13:53:39.293047 [Byte1]: 77
1773 13:53:39.297362
1774 13:53:39.297488 Set Vref, RX VrefLevel [Byte0]: 78
1775 13:53:39.300768 [Byte1]: 78
1776 13:53:39.304748
1777 13:53:39.304896 Set Vref, RX VrefLevel [Byte0]: 79
1778 13:53:39.308469 [Byte1]: 79
1779 13:53:39.312410
1780 13:53:39.312554 Final RX Vref Byte 0 = 57 to rank0
1781 13:53:39.316489 Final RX Vref Byte 1 = 59 to rank0
1782 13:53:39.319290 Final RX Vref Byte 0 = 57 to rank1
1783 13:53:39.322656 Final RX Vref Byte 1 = 59 to rank1==
1784 13:53:39.326570 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 13:53:39.329344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 13:53:39.333104 ==
1787 13:53:39.333227 DQS Delay:
1788 13:53:39.333320 DQS0 = 0, DQS1 = 0
1789 13:53:39.336153 DQM Delay:
1790 13:53:39.336250 DQM0 = 83, DQM1 = 74
1791 13:53:39.336351 DQ Delay:
1792 13:53:39.340071 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1793 13:53:39.343165 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =76
1794 13:53:39.347156 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1795 13:53:39.349624 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1796 13:53:39.349739
1797 13:53:39.349829
1798 13:53:39.359576 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1799 13:53:39.363737 CH1 RK0: MR19=606, MR18=2B00
1800 13:53:39.366378 CH1_RK0: MR19=0x606, MR18=0x2B00, DQSOSC=398, MR23=63, INC=93, DEC=62
1801 13:53:39.366546
1802 13:53:39.371065 ----->DramcWriteLeveling(PI) begin...
1803 13:53:39.373595 ==
1804 13:53:39.376909 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 13:53:39.379667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 13:53:39.379792 ==
1807 13:53:39.383900 Write leveling (Byte 0): 27 => 27
1808 13:53:39.386899 Write leveling (Byte 1): 27 => 27
1809 13:53:39.390169 DramcWriteLeveling(PI) end<-----
1810 13:53:39.390316
1811 13:53:39.390441 ==
1812 13:53:39.393963 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 13:53:39.396847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 13:53:39.396966 ==
1815 13:53:39.400452 [Gating] SW mode calibration
1816 13:53:39.407525 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 13:53:39.410131 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 13:53:39.417334 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1819 13:53:39.420776 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1820 13:53:39.423560 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1821 13:53:39.430427 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:53:39.433740 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:53:39.437334 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:53:39.444179 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:53:39.447224 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:53:39.450945 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:53:39.454193 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:53:39.460769 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:53:39.463806 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:53:39.467732 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1831 13:53:39.473805 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1832 13:53:39.477363 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:53:39.481149 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1834 13:53:39.488006 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1835 13:53:39.491161 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
1836 13:53:39.493976 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1837 13:53:39.500996 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:53:39.504312 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1839 13:53:39.508143 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:53:39.510913 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:53:39.517708 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:53:39.521235 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1843 13:53:39.525236 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
1844 13:53:39.531232 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1845 13:53:39.534365 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 13:53:39.537859 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 13:53:39.544372 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 13:53:39.548201 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1849 13:53:39.551378 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 13:53:39.557847 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 13:53:39.561643 0 10 4 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (1 1)
1852 13:53:39.564557 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:53:39.571427 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:53:39.574821 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:53:39.577731 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1856 13:53:39.581097 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:53:39.588030 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:53:39.591416 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:53:39.594789 0 11 4 | B1->B0 | 2b2b 3636 | 0 0 | (0 0) (1 1)
1860 13:53:39.601379 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1861 13:53:39.604629 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 13:53:39.608253 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 13:53:39.614731 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 13:53:39.618811 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 13:53:39.621493 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 13:53:39.628069 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 13:53:39.632478 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1868 13:53:39.636305 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1869 13:53:39.641772 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:53:39.645145 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:53:39.649113 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:53:39.651703 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:53:39.658597 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:53:39.661970 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:53:39.665689 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 13:53:39.672778 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:53:39.675528 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:53:39.679025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:53:39.685455 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:53:39.688818 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 13:53:39.692459 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 13:53:39.698752 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1883 13:53:39.701971 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1884 13:53:39.705705 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1885 13:53:39.709107 Total UI for P1: 0, mck2ui 16
1886 13:53:39.712356 best dqsien dly found for B0: ( 0, 14, 2)
1887 13:53:39.715504 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 13:53:39.719091 Total UI for P1: 0, mck2ui 16
1889 13:53:39.722331 best dqsien dly found for B1: ( 0, 14, 6)
1890 13:53:39.725625 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1891 13:53:39.729173 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1892 13:53:39.729307
1893 13:53:39.735786 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1894 13:53:39.742531 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1895 13:53:39.742688 [Gating] SW calibration Done
1896 13:53:39.742952 ==
1897 13:53:39.743020 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 13:53:39.748992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 13:53:39.749145 ==
1900 13:53:39.749214 RX Vref Scan: 0
1901 13:53:39.749275
1902 13:53:39.752580 RX Vref 0 -> 0, step: 1
1903 13:53:39.752697
1904 13:53:39.756250 RX Delay -130 -> 252, step: 16
1905 13:53:39.759858 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1906 13:53:39.762623 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1907 13:53:39.766065 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1908 13:53:39.772206 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1909 13:53:39.775998 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1910 13:53:39.779597 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1911 13:53:39.782943 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1912 13:53:39.786621 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1913 13:53:39.792415 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1914 13:53:39.796665 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1915 13:53:39.799476 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1916 13:53:39.803380 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1917 13:53:39.806097 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1918 13:53:39.813941 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1919 13:53:39.816031 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1920 13:53:39.819543 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1921 13:53:39.819719 ==
1922 13:53:39.822354 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 13:53:39.826798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 13:53:39.826951 ==
1925 13:53:39.829384 DQS Delay:
1926 13:53:39.829484 DQS0 = 0, DQS1 = 0
1927 13:53:39.832723 DQM Delay:
1928 13:53:39.832834 DQM0 = 81, DQM1 = 77
1929 13:53:39.832902 DQ Delay:
1930 13:53:39.836286 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1931 13:53:39.839784 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1932 13:53:39.843419 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1933 13:53:39.845926 DQ12 =85, DQ13 =93, DQ14 =85, DQ15 =85
1934 13:53:39.846038
1935 13:53:39.846106
1936 13:53:39.846167 ==
1937 13:53:39.849389 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 13:53:39.856324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 13:53:39.856484 ==
1940 13:53:39.856553
1941 13:53:39.856614
1942 13:53:39.856673 TX Vref Scan disable
1943 13:53:39.860147 == TX Byte 0 ==
1944 13:53:39.863464 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1945 13:53:39.866793 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1946 13:53:39.870044 == TX Byte 1 ==
1947 13:53:39.872952 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1948 13:53:39.876736 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1949 13:53:39.879978 ==
1950 13:53:39.880109 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 13:53:39.887041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 13:53:39.887192 ==
1953 13:53:39.898771 TX Vref=22, minBit 1, minWin=27, winSum=443
1954 13:53:39.902157 TX Vref=24, minBit 1, minWin=27, winSum=442
1955 13:53:39.905553 TX Vref=26, minBit 10, minWin=27, winSum=446
1956 13:53:39.908881 TX Vref=28, minBit 1, minWin=27, winSum=450
1957 13:53:39.911950 TX Vref=30, minBit 12, minWin=27, winSum=450
1958 13:53:39.915493 TX Vref=32, minBit 0, minWin=28, winSum=449
1959 13:53:39.922156 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 32
1960 13:53:39.922338
1961 13:53:39.925394 Final TX Range 1 Vref 32
1962 13:53:39.925514
1963 13:53:39.925580 ==
1964 13:53:39.929181 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 13:53:39.931976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 13:53:39.932110 ==
1967 13:53:39.932180
1968 13:53:39.932242
1969 13:53:39.936183 TX Vref Scan disable
1970 13:53:39.938637 == TX Byte 0 ==
1971 13:53:39.942152 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1972 13:53:39.945558 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1973 13:53:39.949217 == TX Byte 1 ==
1974 13:53:39.952406 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1975 13:53:39.955730 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1976 13:53:39.955876
1977 13:53:39.959909 [DATLAT]
1978 13:53:39.960049 Freq=800, CH1 RK1
1979 13:53:39.960118
1980 13:53:39.962599 DATLAT Default: 0xa
1981 13:53:39.962704 0, 0xFFFF, sum = 0
1982 13:53:39.965836 1, 0xFFFF, sum = 0
1983 13:53:39.965949 2, 0xFFFF, sum = 0
1984 13:53:39.969089 3, 0xFFFF, sum = 0
1985 13:53:39.969203 4, 0xFFFF, sum = 0
1986 13:53:39.972525 5, 0xFFFF, sum = 0
1987 13:53:39.972642 6, 0xFFFF, sum = 0
1988 13:53:39.976057 7, 0xFFFF, sum = 0
1989 13:53:39.976180 8, 0xFFFF, sum = 0
1990 13:53:39.979125 9, 0x0, sum = 1
1991 13:53:39.979238 10, 0x0, sum = 2
1992 13:53:39.982639 11, 0x0, sum = 3
1993 13:53:39.982764 12, 0x0, sum = 4
1994 13:53:39.985944 best_step = 10
1995 13:53:39.986064
1996 13:53:39.986129 ==
1997 13:53:39.989181 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 13:53:39.992574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 13:53:39.992702 ==
2000 13:53:39.996217 RX Vref Scan: 0
2001 13:53:39.996345
2002 13:53:39.996411 RX Vref 0 -> 0, step: 1
2003 13:53:39.996472
2004 13:53:39.999658 RX Delay -111 -> 252, step: 8
2005 13:53:40.006740 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2006 13:53:40.009790 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2007 13:53:40.013267 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2008 13:53:40.016786 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2009 13:53:40.019323 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2010 13:53:40.023181 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2011 13:53:40.029819 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2012 13:53:40.032810 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2013 13:53:40.036375 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2014 13:53:40.039695 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2015 13:53:40.042951 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2016 13:53:40.049583 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2017 13:53:40.053485 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2018 13:53:40.056548 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2019 13:53:40.059830 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2020 13:53:40.062967 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2021 13:53:40.063097 ==
2022 13:53:40.066858 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 13:53:40.073961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 13:53:40.074114 ==
2025 13:53:40.074182 DQS Delay:
2026 13:53:40.076291 DQS0 = 0, DQS1 = 0
2027 13:53:40.076384 DQM Delay:
2028 13:53:40.076451 DQM0 = 80, DQM1 = 75
2029 13:53:40.079862 DQ Delay:
2030 13:53:40.084202 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2031 13:53:40.087098 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2032 13:53:40.089942 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2033 13:53:40.093241 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2034 13:53:40.093369
2035 13:53:40.093436
2036 13:53:40.099999 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2037 13:53:40.103430 CH1 RK1: MR19=606, MR18=1D28
2038 13:53:40.110369 CH1_RK1: MR19=0x606, MR18=0x1D28, DQSOSC=399, MR23=63, INC=92, DEC=61
2039 13:53:40.113244 [RxdqsGatingPostProcess] freq 800
2040 13:53:40.116620 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2041 13:53:40.120382 Pre-setting of DQS Precalculation
2042 13:53:40.126974 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2043 13:53:40.134105 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2044 13:53:40.140308 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2045 13:53:40.140456
2046 13:53:40.140527
2047 13:53:40.143711 [Calibration Summary] 1600 Mbps
2048 13:53:40.143824 CH 0, Rank 0
2049 13:53:40.146966 SW Impedance : PASS
2050 13:53:40.147079 DUTY Scan : NO K
2051 13:53:40.150630 ZQ Calibration : PASS
2052 13:53:40.153982 Jitter Meter : NO K
2053 13:53:40.154144 CBT Training : PASS
2054 13:53:40.157243 Write leveling : PASS
2055 13:53:40.160269 RX DQS gating : PASS
2056 13:53:40.160393 RX DQ/DQS(RDDQC) : PASS
2057 13:53:40.163791 TX DQ/DQS : PASS
2058 13:53:40.167243 RX DATLAT : PASS
2059 13:53:40.167372 RX DQ/DQS(Engine): PASS
2060 13:53:40.170428 TX OE : NO K
2061 13:53:40.170560 All Pass.
2062 13:53:40.170626
2063 13:53:40.174001 CH 0, Rank 1
2064 13:53:40.174134 SW Impedance : PASS
2065 13:53:40.177468 DUTY Scan : NO K
2066 13:53:40.181166 ZQ Calibration : PASS
2067 13:53:40.181302 Jitter Meter : NO K
2068 13:53:40.184087 CBT Training : PASS
2069 13:53:40.184204 Write leveling : PASS
2070 13:53:40.187187 RX DQS gating : PASS
2071 13:53:40.190950 RX DQ/DQS(RDDQC) : PASS
2072 13:53:40.191087 TX DQ/DQS : PASS
2073 13:53:40.194700 RX DATLAT : PASS
2074 13:53:40.198350 RX DQ/DQS(Engine): PASS
2075 13:53:40.198533 TX OE : NO K
2076 13:53:40.200628 All Pass.
2077 13:53:40.200722
2078 13:53:40.200804 CH 1, Rank 0
2079 13:53:40.203945 SW Impedance : PASS
2080 13:53:40.204071 DUTY Scan : NO K
2081 13:53:40.207483 ZQ Calibration : PASS
2082 13:53:40.210623 Jitter Meter : NO K
2083 13:53:40.210748 CBT Training : PASS
2084 13:53:40.214066 Write leveling : PASS
2085 13:53:40.214186 RX DQS gating : PASS
2086 13:53:40.218132 RX DQ/DQS(RDDQC) : PASS
2087 13:53:40.221276 TX DQ/DQS : PASS
2088 13:53:40.221403 RX DATLAT : PASS
2089 13:53:40.224124 RX DQ/DQS(Engine): PASS
2090 13:53:40.228097 TX OE : NO K
2091 13:53:40.228243 All Pass.
2092 13:53:40.228315
2093 13:53:40.228376 CH 1, Rank 1
2094 13:53:40.231006 SW Impedance : PASS
2095 13:53:40.234512 DUTY Scan : NO K
2096 13:53:40.234641 ZQ Calibration : PASS
2097 13:53:40.238015 Jitter Meter : NO K
2098 13:53:40.240949 CBT Training : PASS
2099 13:53:40.241071 Write leveling : PASS
2100 13:53:40.244816 RX DQS gating : PASS
2101 13:53:40.247754 RX DQ/DQS(RDDQC) : PASS
2102 13:53:40.247874 TX DQ/DQS : PASS
2103 13:53:40.251372 RX DATLAT : PASS
2104 13:53:40.251489 RX DQ/DQS(Engine): PASS
2105 13:53:40.254588 TX OE : NO K
2106 13:53:40.254725 All Pass.
2107 13:53:40.254799
2108 13:53:40.257858 DramC Write-DBI off
2109 13:53:40.260964 PER_BANK_REFRESH: Hybrid Mode
2110 13:53:40.261087 TX_TRACKING: ON
2111 13:53:40.264519 [GetDramInforAfterCalByMRR] Vendor 6.
2112 13:53:40.267964 [GetDramInforAfterCalByMRR] Revision 606.
2113 13:53:40.271592 [GetDramInforAfterCalByMRR] Revision 2 0.
2114 13:53:40.274762 MR0 0x3b3b
2115 13:53:40.274890 MR8 0x5151
2116 13:53:40.278178 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 13:53:40.278296
2118 13:53:40.281359 MR0 0x3b3b
2119 13:53:40.281470 MR8 0x5151
2120 13:53:40.285178 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 13:53:40.285311
2122 13:53:40.295053 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2123 13:53:40.298276 [FAST_K] Save calibration result to emmc
2124 13:53:40.301588 [FAST_K] Save calibration result to emmc
2125 13:53:40.301760 dram_init: config_dvfs: 1
2126 13:53:40.308038 dramc_set_vcore_voltage set vcore to 662500
2127 13:53:40.308230 Read voltage for 1200, 2
2128 13:53:40.311757 Vio18 = 0
2129 13:53:40.311917 Vcore = 662500
2130 13:53:40.312017 Vdram = 0
2131 13:53:40.315079 Vddq = 0
2132 13:53:40.315221 Vmddr = 0
2133 13:53:40.318757 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2134 13:53:40.324978 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2135 13:53:40.328385 MEM_TYPE=3, freq_sel=15
2136 13:53:40.328559 sv_algorithm_assistance_LP4_1600
2137 13:53:40.334789 ============ PULL DRAM RESETB DOWN ============
2138 13:53:40.338761 ========== PULL DRAM RESETB DOWN end =========
2139 13:53:40.341532 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2140 13:53:40.344816 ===================================
2141 13:53:40.348972 LPDDR4 DRAM CONFIGURATION
2142 13:53:40.351914 ===================================
2143 13:53:40.355148 EX_ROW_EN[0] = 0x0
2144 13:53:40.355312 EX_ROW_EN[1] = 0x0
2145 13:53:40.358653 LP4Y_EN = 0x0
2146 13:53:40.358809 WORK_FSP = 0x0
2147 13:53:40.361953 WL = 0x4
2148 13:53:40.362100 RL = 0x4
2149 13:53:40.365198 BL = 0x2
2150 13:53:40.365345 RPST = 0x0
2151 13:53:40.368446 RD_PRE = 0x0
2152 13:53:40.368587 WR_PRE = 0x1
2153 13:53:40.371698 WR_PST = 0x0
2154 13:53:40.371814 DBI_WR = 0x0
2155 13:53:40.375349 DBI_RD = 0x0
2156 13:53:40.375499 OTF = 0x1
2157 13:53:40.378587 ===================================
2158 13:53:40.382167 ===================================
2159 13:53:40.385764 ANA top config
2160 13:53:40.388830 ===================================
2161 13:53:40.388964 DLL_ASYNC_EN = 0
2162 13:53:40.392654 ALL_SLAVE_EN = 0
2163 13:53:40.395128 NEW_RANK_MODE = 1
2164 13:53:40.398704 DLL_IDLE_MODE = 1
2165 13:53:40.402583 LP45_APHY_COMB_EN = 1
2166 13:53:40.402728 TX_ODT_DIS = 1
2167 13:53:40.405098 NEW_8X_MODE = 1
2168 13:53:40.409588 ===================================
2169 13:53:40.413978 ===================================
2170 13:53:40.415239 data_rate = 2400
2171 13:53:40.418517 CKR = 1
2172 13:53:40.422359 DQ_P2S_RATIO = 8
2173 13:53:40.425384 ===================================
2174 13:53:40.425522 CA_P2S_RATIO = 8
2175 13:53:40.428903 DQ_CA_OPEN = 0
2176 13:53:40.432448 DQ_SEMI_OPEN = 0
2177 13:53:40.435577 CA_SEMI_OPEN = 0
2178 13:53:40.439419 CA_FULL_RATE = 0
2179 13:53:40.439560 DQ_CKDIV4_EN = 0
2180 13:53:40.442286 CA_CKDIV4_EN = 0
2181 13:53:40.445350 CA_PREDIV_EN = 0
2182 13:53:40.448835 PH8_DLY = 17
2183 13:53:40.452254 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2184 13:53:40.456019 DQ_AAMCK_DIV = 4
2185 13:53:40.456162 CA_AAMCK_DIV = 4
2186 13:53:40.459291 CA_ADMCK_DIV = 4
2187 13:53:40.463322 DQ_TRACK_CA_EN = 0
2188 13:53:40.465505 CA_PICK = 1200
2189 13:53:40.468945 CA_MCKIO = 1200
2190 13:53:40.472573 MCKIO_SEMI = 0
2191 13:53:40.476548 PLL_FREQ = 2366
2192 13:53:40.476684 DQ_UI_PI_RATIO = 32
2193 13:53:40.479562 CA_UI_PI_RATIO = 0
2194 13:53:40.483199 ===================================
2195 13:53:40.486364 ===================================
2196 13:53:40.489524 memory_type:LPDDR4
2197 13:53:40.492954 GP_NUM : 10
2198 13:53:40.493091 SRAM_EN : 1
2199 13:53:40.495765 MD32_EN : 0
2200 13:53:40.498985 ===================================
2201 13:53:40.499110 [ANA_INIT] >>>>>>>>>>>>>>
2202 13:53:40.502864 <<<<<< [CONFIGURE PHASE]: ANA_TX
2203 13:53:40.505745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2204 13:53:40.509166 ===================================
2205 13:53:40.512758 data_rate = 2400,PCW = 0X5b00
2206 13:53:40.516293 ===================================
2207 13:53:40.519143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2208 13:53:40.525902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 13:53:40.529189 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 13:53:40.536083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2211 13:53:40.539512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2212 13:53:40.542755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2213 13:53:40.542899 [ANA_INIT] flow start
2214 13:53:40.546049 [ANA_INIT] PLL >>>>>>>>
2215 13:53:40.549786 [ANA_INIT] PLL <<<<<<<<
2216 13:53:40.552829 [ANA_INIT] MIDPI >>>>>>>>
2217 13:53:40.552960 [ANA_INIT] MIDPI <<<<<<<<
2218 13:53:40.556035 [ANA_INIT] DLL >>>>>>>>
2219 13:53:40.559453 [ANA_INIT] DLL <<<<<<<<
2220 13:53:40.559593 [ANA_INIT] flow end
2221 13:53:40.562619 ============ LP4 DIFF to SE enter ============
2222 13:53:40.569670 ============ LP4 DIFF to SE exit ============
2223 13:53:40.569831 [ANA_INIT] <<<<<<<<<<<<<
2224 13:53:40.573258 [Flow] Enable top DCM control >>>>>
2225 13:53:40.576804 [Flow] Enable top DCM control <<<<<
2226 13:53:40.579541 Enable DLL master slave shuffle
2227 13:53:40.586625 ==============================================================
2228 13:53:40.586828 Gating Mode config
2229 13:53:40.592826 ==============================================================
2230 13:53:40.596026 Config description:
2231 13:53:40.603567 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2232 13:53:40.610358 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2233 13:53:40.616351 SELPH_MODE 0: By rank 1: By Phase
2234 13:53:40.622969 ==============================================================
2235 13:53:40.623169 GAT_TRACK_EN = 1
2236 13:53:40.626358 RX_GATING_MODE = 2
2237 13:53:40.629959 RX_GATING_TRACK_MODE = 2
2238 13:53:40.633801 SELPH_MODE = 1
2239 13:53:40.636746 PICG_EARLY_EN = 1
2240 13:53:40.640227 VALID_LAT_VALUE = 1
2241 13:53:40.646799 ==============================================================
2242 13:53:40.649951 Enter into Gating configuration >>>>
2243 13:53:40.652964 Exit from Gating configuration <<<<
2244 13:53:40.656729 Enter into DVFS_PRE_config >>>>>
2245 13:53:40.666366 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2246 13:53:40.670213 Exit from DVFS_PRE_config <<<<<
2247 13:53:40.673201 Enter into PICG configuration >>>>
2248 13:53:40.677598 Exit from PICG configuration <<<<
2249 13:53:40.677785 [RX_INPUT] configuration >>>>>
2250 13:53:40.679955 [RX_INPUT] configuration <<<<<
2251 13:53:40.686629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2252 13:53:40.690326 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2253 13:53:40.697536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 13:53:40.703437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 13:53:40.710282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 13:53:40.716571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 13:53:40.720377 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2258 13:53:40.723674 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2259 13:53:40.726840 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2260 13:53:40.733759 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2261 13:53:40.737075 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2262 13:53:40.740818 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 13:53:40.744010 ===================================
2264 13:53:40.746929 LPDDR4 DRAM CONFIGURATION
2265 13:53:40.751227 ===================================
2266 13:53:40.751382 EX_ROW_EN[0] = 0x0
2267 13:53:40.753605 EX_ROW_EN[1] = 0x0
2268 13:53:40.757078 LP4Y_EN = 0x0
2269 13:53:40.757217 WORK_FSP = 0x0
2270 13:53:40.760468 WL = 0x4
2271 13:53:40.760591 RL = 0x4
2272 13:53:40.764095 BL = 0x2
2273 13:53:40.764255 RPST = 0x0
2274 13:53:40.767345 RD_PRE = 0x0
2275 13:53:40.767461 WR_PRE = 0x1
2276 13:53:40.771040 WR_PST = 0x0
2277 13:53:40.771167 DBI_WR = 0x0
2278 13:53:40.773981 DBI_RD = 0x0
2279 13:53:40.774086 OTF = 0x1
2280 13:53:40.777545 ===================================
2281 13:53:40.780907 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2282 13:53:40.787887 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2283 13:53:40.791268 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2284 13:53:40.794327 ===================================
2285 13:53:40.797744 LPDDR4 DRAM CONFIGURATION
2286 13:53:40.800926 ===================================
2287 13:53:40.801068 EX_ROW_EN[0] = 0x10
2288 13:53:40.804178 EX_ROW_EN[1] = 0x0
2289 13:53:40.804296 LP4Y_EN = 0x0
2290 13:53:40.807994 WORK_FSP = 0x0
2291 13:53:40.808123 WL = 0x4
2292 13:53:40.810951 RL = 0x4
2293 13:53:40.811063 BL = 0x2
2294 13:53:40.814464 RPST = 0x0
2295 13:53:40.814592 RD_PRE = 0x0
2296 13:53:40.818010 WR_PRE = 0x1
2297 13:53:40.818139 WR_PST = 0x0
2298 13:53:40.821335 DBI_WR = 0x0
2299 13:53:40.821451 DBI_RD = 0x0
2300 13:53:40.824214 OTF = 0x1
2301 13:53:40.827758 ===================================
2302 13:53:40.834570 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2303 13:53:40.834723 ==
2304 13:53:40.838732 Dram Type= 6, Freq= 0, CH_0, rank 0
2305 13:53:40.841867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2306 13:53:40.842006 ==
2307 13:53:40.844552 [Duty_Offset_Calibration]
2308 13:53:40.844697 B0:2 B1:-1 CA:1
2309 13:53:40.844793
2310 13:53:40.847999 [DutyScan_Calibration_Flow] k_type=0
2311 13:53:40.857791
2312 13:53:40.857951 ==CLK 0==
2313 13:53:40.860926 Final CLK duty delay cell = -4
2314 13:53:40.864575 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2315 13:53:40.867636 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2316 13:53:40.870908 [-4] AVG Duty = 4953%(X100)
2317 13:53:40.871042
2318 13:53:40.874388 CH0 CLK Duty spec in!! Max-Min= 156%
2319 13:53:40.877710 [DutyScan_Calibration_Flow] ====Done====
2320 13:53:40.877849
2321 13:53:40.880909 [DutyScan_Calibration_Flow] k_type=1
2322 13:53:40.896153
2323 13:53:40.896311 ==DQS 0 ==
2324 13:53:40.899588 Final DQS duty delay cell = 0
2325 13:53:40.903237 [0] MAX Duty = 5125%(X100), DQS PI = 48
2326 13:53:40.906978 [0] MIN Duty = 5000%(X100), DQS PI = 12
2327 13:53:40.907126 [0] AVG Duty = 5062%(X100)
2328 13:53:40.909791
2329 13:53:40.909896 ==DQS 1 ==
2330 13:53:40.913367 Final DQS duty delay cell = -4
2331 13:53:40.916164 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2332 13:53:40.919637 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2333 13:53:40.923457 [-4] AVG Duty = 5062%(X100)
2334 13:53:40.923596
2335 13:53:40.926743 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2336 13:53:40.926862
2337 13:53:40.929886 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2338 13:53:40.933076 [DutyScan_Calibration_Flow] ====Done====
2339 13:53:40.933203
2340 13:53:40.936137 [DutyScan_Calibration_Flow] k_type=3
2341 13:53:40.953750
2342 13:53:40.953905 ==DQM 0 ==
2343 13:53:40.956976 Final DQM duty delay cell = 0
2344 13:53:40.959828 [0] MAX Duty = 5000%(X100), DQS PI = 56
2345 13:53:40.963026 [0] MIN Duty = 4907%(X100), DQS PI = 2
2346 13:53:40.963158 [0] AVG Duty = 4953%(X100)
2347 13:53:40.966349
2348 13:53:40.966517 ==DQM 1 ==
2349 13:53:40.969480 Final DQM duty delay cell = 0
2350 13:53:40.973531 [0] MAX Duty = 5156%(X100), DQS PI = 62
2351 13:53:40.976401 [0] MIN Duty = 4969%(X100), DQS PI = 10
2352 13:53:40.976543 [0] AVG Duty = 5062%(X100)
2353 13:53:40.980162
2354 13:53:40.983788 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2355 13:53:40.983933
2356 13:53:40.986775 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2357 13:53:40.990004 [DutyScan_Calibration_Flow] ====Done====
2358 13:53:40.990133
2359 13:53:40.993534 [DutyScan_Calibration_Flow] k_type=2
2360 13:53:41.008955
2361 13:53:41.009114 ==DQ 0 ==
2362 13:53:41.012178 Final DQ duty delay cell = -4
2363 13:53:41.015372 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2364 13:53:41.018974 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2365 13:53:41.022032 [-4] AVG Duty = 4969%(X100)
2366 13:53:41.022164
2367 13:53:41.022233 ==DQ 1 ==
2368 13:53:41.025751 Final DQ duty delay cell = 0
2369 13:53:41.029293 [0] MAX Duty = 5031%(X100), DQS PI = 18
2370 13:53:41.032558 [0] MIN Duty = 4907%(X100), DQS PI = 46
2371 13:53:41.032688 [0] AVG Duty = 4969%(X100)
2372 13:53:41.035321
2373 13:53:41.039402 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2374 13:53:41.039540
2375 13:53:41.043017 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2376 13:53:41.045779 [DutyScan_Calibration_Flow] ====Done====
2377 13:53:41.045897 ==
2378 13:53:41.049251 Dram Type= 6, Freq= 0, CH_1, rank 0
2379 13:53:41.052532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2380 13:53:41.052658 ==
2381 13:53:41.056252 [Duty_Offset_Calibration]
2382 13:53:41.056379 B0:1 B1:1 CA:2
2383 13:53:41.056446
2384 13:53:41.059350 [DutyScan_Calibration_Flow] k_type=0
2385 13:53:41.069181
2386 13:53:41.069342 ==CLK 0==
2387 13:53:41.072616 Final CLK duty delay cell = 0
2388 13:53:41.075980 [0] MAX Duty = 5156%(X100), DQS PI = 24
2389 13:53:41.079416 [0] MIN Duty = 4938%(X100), DQS PI = 42
2390 13:53:41.079551 [0] AVG Duty = 5047%(X100)
2391 13:53:41.082412
2392 13:53:41.082556 CH1 CLK Duty spec in!! Max-Min= 218%
2393 13:53:41.089375 [DutyScan_Calibration_Flow] ====Done====
2394 13:53:41.089532
2395 13:53:41.092262 [DutyScan_Calibration_Flow] k_type=1
2396 13:53:41.108372
2397 13:53:41.108532 ==DQS 0 ==
2398 13:53:41.111956 Final DQS duty delay cell = 0
2399 13:53:41.115835 [0] MAX Duty = 5031%(X100), DQS PI = 18
2400 13:53:41.118392 [0] MIN Duty = 4844%(X100), DQS PI = 48
2401 13:53:41.121913 [0] AVG Duty = 4937%(X100)
2402 13:53:41.122054
2403 13:53:41.122121 ==DQS 1 ==
2404 13:53:41.125048 Final DQS duty delay cell = 0
2405 13:53:41.128533 [0] MAX Duty = 5062%(X100), DQS PI = 36
2406 13:53:41.131738 [0] MIN Duty = 4907%(X100), DQS PI = 16
2407 13:53:41.135063 [0] AVG Duty = 4984%(X100)
2408 13:53:41.135193
2409 13:53:41.138448 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2410 13:53:41.138571
2411 13:53:41.142154 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2412 13:53:41.145376 [DutyScan_Calibration_Flow] ====Done====
2413 13:53:41.145510
2414 13:53:41.148149 [DutyScan_Calibration_Flow] k_type=3
2415 13:53:41.165291
2416 13:53:41.165449 ==DQM 0 ==
2417 13:53:41.168765 Final DQM duty delay cell = 0
2418 13:53:41.172035 [0] MAX Duty = 5093%(X100), DQS PI = 18
2419 13:53:41.174948 [0] MIN Duty = 4907%(X100), DQS PI = 44
2420 13:53:41.175076 [0] AVG Duty = 5000%(X100)
2421 13:53:41.178418
2422 13:53:41.178546 ==DQM 1 ==
2423 13:53:41.181840 Final DQM duty delay cell = 0
2424 13:53:41.185120 [0] MAX Duty = 5156%(X100), DQS PI = 62
2425 13:53:41.189711 [0] MIN Duty = 4938%(X100), DQS PI = 22
2426 13:53:41.189861 [0] AVG Duty = 5047%(X100)
2427 13:53:41.189931
2428 13:53:41.195730 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2429 13:53:41.195872
2430 13:53:41.198666 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2431 13:53:41.201848 [DutyScan_Calibration_Flow] ====Done====
2432 13:53:41.201987
2433 13:53:41.205878 [DutyScan_Calibration_Flow] k_type=2
2434 13:53:41.221572
2435 13:53:41.221737 ==DQ 0 ==
2436 13:53:41.224869 Final DQ duty delay cell = 0
2437 13:53:41.228101 [0] MAX Duty = 5124%(X100), DQS PI = 18
2438 13:53:41.231524 [0] MIN Duty = 4969%(X100), DQS PI = 12
2439 13:53:41.231666 [0] AVG Duty = 5046%(X100)
2440 13:53:41.231734
2441 13:53:41.235331 ==DQ 1 ==
2442 13:53:41.238641 Final DQ duty delay cell = 0
2443 13:53:41.241705 [0] MAX Duty = 5124%(X100), DQS PI = 58
2444 13:53:41.245251 [0] MIN Duty = 5031%(X100), DQS PI = 2
2445 13:53:41.245397 [0] AVG Duty = 5077%(X100)
2446 13:53:41.245470
2447 13:53:41.248489 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2448 13:53:41.248601
2449 13:53:41.251668 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2450 13:53:41.258281 [DutyScan_Calibration_Flow] ====Done====
2451 13:53:41.262470 nWR fixed to 30
2452 13:53:41.262613 [ModeRegInit_LP4] CH0 RK0
2453 13:53:41.265142 [ModeRegInit_LP4] CH0 RK1
2454 13:53:41.268287 [ModeRegInit_LP4] CH1 RK0
2455 13:53:41.268414 [ModeRegInit_LP4] CH1 RK1
2456 13:53:41.272045 match AC timing 7
2457 13:53:41.275129 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2458 13:53:41.278612 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2459 13:53:41.285597 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2460 13:53:41.288438 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2461 13:53:41.295413 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2462 13:53:41.295564 ==
2463 13:53:41.298901 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 13:53:41.301878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2465 13:53:41.301997 ==
2466 13:53:41.305415 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2467 13:53:41.312110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2468 13:53:41.321482 [CA 0] Center 40 (10~71) winsize 62
2469 13:53:41.324858 [CA 1] Center 39 (9~70) winsize 62
2470 13:53:41.328282 [CA 2] Center 36 (6~67) winsize 62
2471 13:53:41.331492 [CA 3] Center 35 (5~66) winsize 62
2472 13:53:41.335614 [CA 4] Center 35 (5~65) winsize 61
2473 13:53:41.338145 [CA 5] Center 34 (4~65) winsize 62
2474 13:53:41.338279
2475 13:53:41.341481 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2476 13:53:41.341599
2477 13:53:41.345067 [CATrainingPosCal] consider 1 rank data
2478 13:53:41.348344 u2DelayCellTimex100 = 270/100 ps
2479 13:53:41.352264 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2480 13:53:41.354896 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2481 13:53:41.361542 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2482 13:53:41.365164 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2483 13:53:41.368126 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2484 13:53:41.372192 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2485 13:53:41.372343
2486 13:53:41.375554 CA PerBit enable=1, Macro0, CA PI delay=34
2487 13:53:41.375671
2488 13:53:41.379025 [CBTSetCACLKResult] CA Dly = 34
2489 13:53:41.379142 CS Dly: 7 (0~38)
2490 13:53:41.379210 ==
2491 13:53:41.381960 Dram Type= 6, Freq= 0, CH_0, rank 1
2492 13:53:41.389179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2493 13:53:41.389333 ==
2494 13:53:41.392134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2495 13:53:41.398632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2496 13:53:41.407503 [CA 0] Center 39 (9~70) winsize 62
2497 13:53:41.411178 [CA 1] Center 39 (9~70) winsize 62
2498 13:53:41.414461 [CA 2] Center 36 (6~67) winsize 62
2499 13:53:41.417304 [CA 3] Center 36 (5~67) winsize 63
2500 13:53:41.420969 [CA 4] Center 34 (4~65) winsize 62
2501 13:53:41.424248 [CA 5] Center 34 (4~64) winsize 61
2502 13:53:41.424398
2503 13:53:41.427434 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2504 13:53:41.427567
2505 13:53:41.430749 [CATrainingPosCal] consider 2 rank data
2506 13:53:41.434855 u2DelayCellTimex100 = 270/100 ps
2507 13:53:41.437858 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2508 13:53:41.441260 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2509 13:53:41.444642 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2510 13:53:41.451181 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2511 13:53:41.454882 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2512 13:53:41.458165 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2513 13:53:41.458300
2514 13:53:41.461362 CA PerBit enable=1, Macro0, CA PI delay=34
2515 13:53:41.461485
2516 13:53:41.464814 [CBTSetCACLKResult] CA Dly = 34
2517 13:53:41.464933 CS Dly: 8 (0~41)
2518 13:53:41.465001
2519 13:53:41.467855 ----->DramcWriteLeveling(PI) begin...
2520 13:53:41.467961 ==
2521 13:53:41.471385 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 13:53:41.478426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 13:53:41.478583 ==
2524 13:53:41.481195 Write leveling (Byte 0): 29 => 29
2525 13:53:41.484940 Write leveling (Byte 1): 28 => 28
2526 13:53:41.485088 DramcWriteLeveling(PI) end<-----
2527 13:53:41.485156
2528 13:53:41.488300 ==
2529 13:53:41.488418 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 13:53:41.495207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 13:53:41.495359 ==
2532 13:53:41.498223 [Gating] SW mode calibration
2533 13:53:41.504938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2534 13:53:41.508284 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2535 13:53:41.515193 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 13:53:41.518873 0 15 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2537 13:53:41.521406 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2538 13:53:41.525398 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 13:53:41.532469 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 13:53:41.535053 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 13:53:41.539581 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 13:53:41.545404 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 13:53:41.549441 1 0 0 | B1->B0 | 3434 3030 | 0 1 | (0 1) (1 0)
2544 13:53:41.552130 1 0 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
2545 13:53:41.558615 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 13:53:41.562618 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 13:53:41.565218 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 13:53:41.572190 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 13:53:41.575460 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 13:53:41.579477 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 13:53:41.582237 1 1 0 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
2552 13:53:41.588995 1 1 4 | B1->B0 | 3938 4646 | 1 0 | (0 0) (0 0)
2553 13:53:41.592461 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 13:53:41.595672 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 13:53:41.602908 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 13:53:41.605661 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 13:53:41.609612 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 13:53:41.616226 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 13:53:41.618919 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2560 13:53:41.622666 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2561 13:53:41.629455 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:53:41.632665 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:53:41.636069 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:53:41.639055 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:53:41.645865 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:53:41.649289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:53:41.652597 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 13:53:41.659936 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 13:53:41.663115 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:53:41.666080 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 13:53:41.673585 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 13:53:41.676467 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 13:53:41.679528 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 13:53:41.686632 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 13:53:41.690458 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2576 13:53:41.692622 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2577 13:53:41.696083 Total UI for P1: 0, mck2ui 16
2578 13:53:41.701069 best dqsien dly found for B0: ( 1, 4, 0)
2579 13:53:41.702967 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 13:53:41.706194 Total UI for P1: 0, mck2ui 16
2581 13:53:41.710023 best dqsien dly found for B1: ( 1, 4, 2)
2582 13:53:41.713940 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2583 13:53:41.716309 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2584 13:53:41.716428
2585 13:53:41.722770 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2586 13:53:41.726123 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2587 13:53:41.726257 [Gating] SW calibration Done
2588 13:53:41.729728 ==
2589 13:53:41.729852 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 13:53:41.737235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 13:53:41.737394 ==
2592 13:53:41.737464 RX Vref Scan: 0
2593 13:53:41.737526
2594 13:53:41.740023 RX Vref 0 -> 0, step: 1
2595 13:53:41.740126
2596 13:53:41.743543 RX Delay -40 -> 252, step: 8
2597 13:53:41.746691 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2598 13:53:41.750372 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2599 13:53:41.753323 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2600 13:53:41.760078 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2601 13:53:41.763437 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2602 13:53:41.766597 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2603 13:53:41.770170 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2604 13:53:41.773401 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2605 13:53:41.777408 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2606 13:53:41.783429 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2607 13:53:41.786725 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2608 13:53:41.791168 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2609 13:53:41.793390 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2610 13:53:41.796938 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2611 13:53:41.803266 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2612 13:53:41.807608 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2613 13:53:41.807760 ==
2614 13:53:41.810565 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 13:53:41.813348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 13:53:41.813471 ==
2617 13:53:41.816646 DQS Delay:
2618 13:53:41.816764 DQS0 = 0, DQS1 = 0
2619 13:53:41.816854 DQM Delay:
2620 13:53:41.820630 DQM0 = 116, DQM1 = 107
2621 13:53:41.820770 DQ Delay:
2622 13:53:41.823686 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2623 13:53:41.826778 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2624 13:53:41.829958 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =95
2625 13:53:41.834327 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2626 13:53:41.836635
2627 13:53:41.836747
2628 13:53:41.836838 ==
2629 13:53:41.840502 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 13:53:41.843578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 13:53:41.843709 ==
2632 13:53:41.843804
2633 13:53:41.843886
2634 13:53:41.847189 TX Vref Scan disable
2635 13:53:41.847303 == TX Byte 0 ==
2636 13:53:41.853427 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2637 13:53:41.857019 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2638 13:53:41.857163 == TX Byte 1 ==
2639 13:53:41.863425 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2640 13:53:41.867282 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2641 13:53:41.867430 ==
2642 13:53:41.870527 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 13:53:41.873694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 13:53:41.873826 ==
2645 13:53:41.885790 TX Vref=22, minBit 1, minWin=24, winSum=416
2646 13:53:41.889527 TX Vref=24, minBit 5, minWin=25, winSum=423
2647 13:53:41.893074 TX Vref=26, minBit 5, minWin=25, winSum=429
2648 13:53:41.895715 TX Vref=28, minBit 1, minWin=26, winSum=435
2649 13:53:41.899356 TX Vref=30, minBit 1, minWin=26, winSum=436
2650 13:53:41.902558 TX Vref=32, minBit 0, minWin=26, winSum=434
2651 13:53:41.909491 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 30
2652 13:53:41.909646
2653 13:53:41.912630 Final TX Range 1 Vref 30
2654 13:53:41.912790
2655 13:53:41.912943 ==
2656 13:53:41.916124 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 13:53:41.920290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 13:53:41.920518 ==
2659 13:53:41.920622
2660 13:53:41.920705
2661 13:53:41.923453 TX Vref Scan disable
2662 13:53:41.925978 == TX Byte 0 ==
2663 13:53:41.929598 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2664 13:53:41.932971 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2665 13:53:41.936611 == TX Byte 1 ==
2666 13:53:41.940003 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2667 13:53:41.943295 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2668 13:53:41.943435
2669 13:53:41.946350 [DATLAT]
2670 13:53:41.946521 Freq=1200, CH0 RK0
2671 13:53:41.946611
2672 13:53:41.949358 DATLAT Default: 0xd
2673 13:53:41.949456 0, 0xFFFF, sum = 0
2674 13:53:41.952840 1, 0xFFFF, sum = 0
2675 13:53:41.952947 2, 0xFFFF, sum = 0
2676 13:53:41.956945 3, 0xFFFF, sum = 0
2677 13:53:41.957070 4, 0xFFFF, sum = 0
2678 13:53:41.959676 5, 0xFFFF, sum = 0
2679 13:53:41.959791 6, 0xFFFF, sum = 0
2680 13:53:41.963053 7, 0xFFFF, sum = 0
2681 13:53:41.963203 8, 0xFFFF, sum = 0
2682 13:53:41.966526 9, 0xFFFF, sum = 0
2683 13:53:41.966669 10, 0xFFFF, sum = 0
2684 13:53:41.969508 11, 0xFFFF, sum = 0
2685 13:53:41.969642 12, 0x0, sum = 1
2686 13:53:41.973056 13, 0x0, sum = 2
2687 13:53:41.973205 14, 0x0, sum = 3
2688 13:53:41.976188 15, 0x0, sum = 4
2689 13:53:41.976325 best_step = 13
2690 13:53:41.976420
2691 13:53:41.976509 ==
2692 13:53:41.980191 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 13:53:41.983761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 13:53:41.986386 ==
2695 13:53:41.986584 RX Vref Scan: 1
2696 13:53:41.986684
2697 13:53:41.989857 Set Vref Range= 32 -> 127
2698 13:53:41.990003
2699 13:53:41.993605 RX Vref 32 -> 127, step: 1
2700 13:53:41.993756
2701 13:53:41.993855 RX Delay -21 -> 252, step: 4
2702 13:53:41.993945
2703 13:53:41.996627 Set Vref, RX VrefLevel [Byte0]: 32
2704 13:53:42.000010 [Byte1]: 32
2705 13:53:42.004288
2706 13:53:42.004464 Set Vref, RX VrefLevel [Byte0]: 33
2707 13:53:42.007759 [Byte1]: 33
2708 13:53:42.012243
2709 13:53:42.012428 Set Vref, RX VrefLevel [Byte0]: 34
2710 13:53:42.016402 [Byte1]: 34
2711 13:53:42.019717
2712 13:53:42.019885 Set Vref, RX VrefLevel [Byte0]: 35
2713 13:53:42.023174 [Byte1]: 35
2714 13:53:42.027799
2715 13:53:42.027987 Set Vref, RX VrefLevel [Byte0]: 36
2716 13:53:42.031085 [Byte1]: 36
2717 13:53:42.036056
2718 13:53:42.036243 Set Vref, RX VrefLevel [Byte0]: 37
2719 13:53:42.040129 [Byte1]: 37
2720 13:53:42.043624
2721 13:53:42.043801 Set Vref, RX VrefLevel [Byte0]: 38
2722 13:53:42.047246 [Byte1]: 38
2723 13:53:42.051611
2724 13:53:42.051790 Set Vref, RX VrefLevel [Byte0]: 39
2725 13:53:42.054976 [Byte1]: 39
2726 13:53:42.059617
2727 13:53:42.059804 Set Vref, RX VrefLevel [Byte0]: 40
2728 13:53:42.062897 [Byte1]: 40
2729 13:53:42.067979
2730 13:53:42.068168 Set Vref, RX VrefLevel [Byte0]: 41
2731 13:53:42.070899 [Byte1]: 41
2732 13:53:42.075350
2733 13:53:42.075531 Set Vref, RX VrefLevel [Byte0]: 42
2734 13:53:42.079488 [Byte1]: 42
2735 13:53:42.084366
2736 13:53:42.084555 Set Vref, RX VrefLevel [Byte0]: 43
2737 13:53:42.086997 [Byte1]: 43
2738 13:53:42.091449
2739 13:53:42.091634 Set Vref, RX VrefLevel [Byte0]: 44
2740 13:53:42.094829 [Byte1]: 44
2741 13:53:42.099176
2742 13:53:42.099353 Set Vref, RX VrefLevel [Byte0]: 45
2743 13:53:42.102576 [Byte1]: 45
2744 13:53:42.107462
2745 13:53:42.107647 Set Vref, RX VrefLevel [Byte0]: 46
2746 13:53:42.110714 [Byte1]: 46
2747 13:53:42.115670
2748 13:53:42.115857 Set Vref, RX VrefLevel [Byte0]: 47
2749 13:53:42.118174 [Byte1]: 47
2750 13:53:42.122777
2751 13:53:42.122966 Set Vref, RX VrefLevel [Byte0]: 48
2752 13:53:42.126575 [Byte1]: 48
2753 13:53:42.130643
2754 13:53:42.130816 Set Vref, RX VrefLevel [Byte0]: 49
2755 13:53:42.134079 [Byte1]: 49
2756 13:53:42.138637
2757 13:53:42.138819 Set Vref, RX VrefLevel [Byte0]: 50
2758 13:53:42.141850 [Byte1]: 50
2759 13:53:42.146901
2760 13:53:42.147089 Set Vref, RX VrefLevel [Byte0]: 51
2761 13:53:42.150066 [Byte1]: 51
2762 13:53:42.154988
2763 13:53:42.155174 Set Vref, RX VrefLevel [Byte0]: 52
2764 13:53:42.157929 [Byte1]: 52
2765 13:53:42.163215
2766 13:53:42.163410 Set Vref, RX VrefLevel [Byte0]: 53
2767 13:53:42.166006 [Byte1]: 53
2768 13:53:42.170594
2769 13:53:42.170774 Set Vref, RX VrefLevel [Byte0]: 54
2770 13:53:42.173766 [Byte1]: 54
2771 13:53:42.178523
2772 13:53:42.178708 Set Vref, RX VrefLevel [Byte0]: 55
2773 13:53:42.182022 [Byte1]: 55
2774 13:53:42.186292
2775 13:53:42.186506 Set Vref, RX VrefLevel [Byte0]: 56
2776 13:53:42.189615 [Byte1]: 56
2777 13:53:42.194436
2778 13:53:42.194641 Set Vref, RX VrefLevel [Byte0]: 57
2779 13:53:42.198351 [Byte1]: 57
2780 13:53:42.202599
2781 13:53:42.202775 Set Vref, RX VrefLevel [Byte0]: 58
2782 13:53:42.205728 [Byte1]: 58
2783 13:53:42.210776
2784 13:53:42.210963 Set Vref, RX VrefLevel [Byte0]: 59
2785 13:53:42.213345 [Byte1]: 59
2786 13:53:42.218298
2787 13:53:42.218525 Set Vref, RX VrefLevel [Byte0]: 60
2788 13:53:42.221508 [Byte1]: 60
2789 13:53:42.226858
2790 13:53:42.227054 Set Vref, RX VrefLevel [Byte0]: 61
2791 13:53:42.229568 [Byte1]: 61
2792 13:53:42.233992
2793 13:53:42.234178 Set Vref, RX VrefLevel [Byte0]: 62
2794 13:53:42.237486 [Byte1]: 62
2795 13:53:42.241989
2796 13:53:42.242174 Set Vref, RX VrefLevel [Byte0]: 63
2797 13:53:42.245294 [Byte1]: 63
2798 13:53:42.249710
2799 13:53:42.249896 Set Vref, RX VrefLevel [Byte0]: 64
2800 13:53:42.253223 [Byte1]: 64
2801 13:53:42.258318
2802 13:53:42.258549 Set Vref, RX VrefLevel [Byte0]: 65
2803 13:53:42.261338 [Byte1]: 65
2804 13:53:42.266264
2805 13:53:42.266488 Set Vref, RX VrefLevel [Byte0]: 66
2806 13:53:42.270144 [Byte1]: 66
2807 13:53:42.273559
2808 13:53:42.273723 Set Vref, RX VrefLevel [Byte0]: 67
2809 13:53:42.276851 [Byte1]: 67
2810 13:53:42.281199
2811 13:53:42.281375 Set Vref, RX VrefLevel [Byte0]: 68
2812 13:53:42.284952 [Byte1]: 68
2813 13:53:42.289910
2814 13:53:42.290104 Set Vref, RX VrefLevel [Byte0]: 69
2815 13:53:42.292677 [Byte1]: 69
2816 13:53:42.297288
2817 13:53:42.297471 Final RX Vref Byte 0 = 53 to rank0
2818 13:53:42.300683 Final RX Vref Byte 1 = 51 to rank0
2819 13:53:42.304225 Final RX Vref Byte 0 = 53 to rank1
2820 13:53:42.307425 Final RX Vref Byte 1 = 51 to rank1==
2821 13:53:42.310883 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 13:53:42.314328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 13:53:42.317267 ==
2824 13:53:42.317420 DQS Delay:
2825 13:53:42.317519 DQS0 = 0, DQS1 = 0
2826 13:53:42.321113 DQM Delay:
2827 13:53:42.321274 DQM0 = 115, DQM1 = 104
2828 13:53:42.324303 DQ Delay:
2829 13:53:42.327579 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2830 13:53:42.332002 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2831 13:53:42.334050 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2832 13:53:42.337493 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2833 13:53:42.337658
2834 13:53:42.337760
2835 13:53:42.344370 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbeb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
2836 13:53:42.347781 CH0 RK0: MR19=303, MR18=FBEB
2837 13:53:42.354268 CH0_RK0: MR19=0x303, MR18=0xFBEB, DQSOSC=412, MR23=63, INC=38, DEC=25
2838 13:53:42.354501
2839 13:53:42.357827 ----->DramcWriteLeveling(PI) begin...
2840 13:53:42.358005 ==
2841 13:53:42.361148 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 13:53:42.364734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 13:53:42.364875 ==
2844 13:53:42.368077 Write leveling (Byte 0): 32 => 32
2845 13:53:42.372043 Write leveling (Byte 1): 31 => 31
2846 13:53:42.374667 DramcWriteLeveling(PI) end<-----
2847 13:53:42.374788
2848 13:53:42.374855 ==
2849 13:53:42.378768 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 13:53:42.381762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 13:53:42.381892 ==
2852 13:53:42.385236 [Gating] SW mode calibration
2853 13:53:42.391940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 13:53:42.398037 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 13:53:42.401519 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2856 13:53:42.405076 0 15 4 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
2857 13:53:42.411870 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 13:53:42.415704 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 13:53:42.418875 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 13:53:42.425041 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 13:53:42.428740 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2862 13:53:42.433202 0 15 28 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
2863 13:53:42.438926 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2864 13:53:42.441782 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2865 13:53:42.445315 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 13:53:42.452028 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 13:53:42.454967 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 13:53:42.458393 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 13:53:42.464986 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2870 13:53:42.469277 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2871 13:53:42.472085 1 1 0 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
2872 13:53:42.475397 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 13:53:42.483213 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 13:53:42.485693 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 13:53:42.488965 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 13:53:42.495324 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 13:53:42.498611 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 13:53:42.501954 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2879 13:53:42.508870 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2880 13:53:42.512807 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2881 13:53:42.515807 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 13:53:42.519430 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 13:53:42.526792 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 13:53:42.529191 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 13:53:42.532377 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 13:53:42.539559 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 13:53:42.543451 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 13:53:42.546002 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:53:42.552695 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 13:53:42.555990 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 13:53:42.559379 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 13:53:42.566836 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 13:53:42.569769 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 13:53:42.572680 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2895 13:53:42.579395 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2896 13:53:42.579593 Total UI for P1: 0, mck2ui 16
2897 13:53:42.584289 best dqsien dly found for B0: ( 1, 3, 26)
2898 13:53:42.589502 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 13:53:42.593055 Total UI for P1: 0, mck2ui 16
2900 13:53:42.596255 best dqsien dly found for B1: ( 1, 4, 0)
2901 13:53:42.599738 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2902 13:53:42.603617 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2903 13:53:42.603794
2904 13:53:42.606201 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2905 13:53:42.609877 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2906 13:53:42.613004 [Gating] SW calibration Done
2907 13:53:42.613143 ==
2908 13:53:42.616523 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 13:53:42.619760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 13:53:42.619897 ==
2911 13:53:42.623497 RX Vref Scan: 0
2912 13:53:42.623668
2913 13:53:42.623769 RX Vref 0 -> 0, step: 1
2914 13:53:42.623859
2915 13:53:42.627296 RX Delay -40 -> 252, step: 8
2916 13:53:42.629943 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2917 13:53:42.636698 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2918 13:53:42.639825 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2919 13:53:42.644073 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2920 13:53:42.646902 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2921 13:53:42.649962 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2922 13:53:42.653155 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2923 13:53:42.660022 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2924 13:53:42.663600 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2925 13:53:42.666837 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2926 13:53:42.670413 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2927 13:53:42.673759 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2928 13:53:42.680303 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2929 13:53:42.683501 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2930 13:53:42.687133 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2931 13:53:42.690371 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2932 13:53:42.690571 ==
2933 13:53:42.694640 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 13:53:42.697205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 13:53:42.700352 ==
2936 13:53:42.700512 DQS Delay:
2937 13:53:42.700612 DQS0 = 0, DQS1 = 0
2938 13:53:42.704578 DQM Delay:
2939 13:53:42.704737 DQM0 = 115, DQM1 = 106
2940 13:53:42.707091 DQ Delay:
2941 13:53:42.710368 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2942 13:53:42.714154 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2943 13:53:42.718284 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2944 13:53:42.720833 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2945 13:53:42.720998
2946 13:53:42.721108
2947 13:53:42.721171 ==
2948 13:53:42.723872 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 13:53:42.727305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 13:53:42.727423 ==
2951 13:53:42.727493
2952 13:53:42.727553
2953 13:53:42.730618 TX Vref Scan disable
2954 13:53:42.734273 == TX Byte 0 ==
2955 13:53:42.737345 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2956 13:53:42.740833 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2957 13:53:42.740956 == TX Byte 1 ==
2958 13:53:42.748046 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2959 13:53:42.751287 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2960 13:53:42.751435 ==
2961 13:53:42.755552 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 13:53:42.757689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 13:53:42.757813 ==
2964 13:53:42.770545 TX Vref=22, minBit 1, minWin=25, winSum=416
2965 13:53:42.773785 TX Vref=24, minBit 0, minWin=26, winSum=421
2966 13:53:42.777818 TX Vref=26, minBit 0, minWin=26, winSum=425
2967 13:53:42.780226 TX Vref=28, minBit 4, minWin=26, winSum=431
2968 13:53:42.784446 TX Vref=30, minBit 10, minWin=26, winSum=434
2969 13:53:42.790274 TX Vref=32, minBit 3, minWin=26, winSum=431
2970 13:53:42.793461 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 30
2971 13:53:42.793613
2972 13:53:42.797749 Final TX Range 1 Vref 30
2973 13:53:42.797899
2974 13:53:42.797994 ==
2975 13:53:42.800713 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 13:53:42.803419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 13:53:42.803550 ==
2978 13:53:42.807829
2979 13:53:42.807972
2980 13:53:42.808069 TX Vref Scan disable
2981 13:53:42.810970 == TX Byte 0 ==
2982 13:53:42.814199 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2983 13:53:42.816973 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2984 13:53:42.820267 == TX Byte 1 ==
2985 13:53:42.823533 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2986 13:53:42.827126 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2987 13:53:42.827280
2988 13:53:42.830945 [DATLAT]
2989 13:53:42.831119 Freq=1200, CH0 RK1
2990 13:53:42.831238
2991 13:53:42.833472 DATLAT Default: 0xd
2992 13:53:42.833614 0, 0xFFFF, sum = 0
2993 13:53:42.837349 1, 0xFFFF, sum = 0
2994 13:53:42.837496 2, 0xFFFF, sum = 0
2995 13:53:42.840990 3, 0xFFFF, sum = 0
2996 13:53:42.841129 4, 0xFFFF, sum = 0
2997 13:53:42.843724 5, 0xFFFF, sum = 0
2998 13:53:42.843857 6, 0xFFFF, sum = 0
2999 13:53:42.846878 7, 0xFFFF, sum = 0
3000 13:53:42.847013 8, 0xFFFF, sum = 0
3001 13:53:42.850268 9, 0xFFFF, sum = 0
3002 13:53:42.854110 10, 0xFFFF, sum = 0
3003 13:53:42.854271 11, 0xFFFF, sum = 0
3004 13:53:42.857013 12, 0x0, sum = 1
3005 13:53:42.857148 13, 0x0, sum = 2
3006 13:53:42.857248 14, 0x0, sum = 3
3007 13:53:42.861223 15, 0x0, sum = 4
3008 13:53:42.861378 best_step = 13
3009 13:53:42.861477
3010 13:53:42.861567 ==
3011 13:53:42.864082 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 13:53:42.870523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 13:53:42.870694 ==
3014 13:53:42.870831 RX Vref Scan: 0
3015 13:53:42.870921
3016 13:53:42.874037 RX Vref 0 -> 0, step: 1
3017 13:53:42.874165
3018 13:53:42.877344 RX Delay -21 -> 252, step: 4
3019 13:53:42.880727 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3020 13:53:42.884496 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3021 13:53:42.890381 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3022 13:53:42.894134 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3023 13:53:42.897422 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3024 13:53:42.900359 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3025 13:53:42.904154 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3026 13:53:42.910578 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3027 13:53:42.914255 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3028 13:53:42.917715 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3029 13:53:42.920900 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3030 13:53:42.923750 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3031 13:53:42.928007 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3032 13:53:42.934320 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3033 13:53:42.937338 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3034 13:53:42.940903 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3035 13:53:42.941050 ==
3036 13:53:42.944968 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 13:53:42.947798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 13:53:42.947940 ==
3039 13:53:42.950933 DQS Delay:
3040 13:53:42.951062 DQS0 = 0, DQS1 = 0
3041 13:53:42.954623 DQM Delay:
3042 13:53:42.954763 DQM0 = 114, DQM1 = 104
3043 13:53:42.957543 DQ Delay:
3044 13:53:42.961082 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3045 13:53:42.964465 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3046 13:53:42.968191 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3047 13:53:42.972361 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3048 13:53:42.972524
3049 13:53:42.972623
3050 13:53:42.977977 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3051 13:53:42.981078 CH0 RK1: MR19=403, MR18=F2
3052 13:53:42.987801 CH0_RK1: MR19=0x403, MR18=0xF2, DQSOSC=410, MR23=63, INC=39, DEC=26
3053 13:53:42.991600 [RxdqsGatingPostProcess] freq 1200
3054 13:53:42.994624 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 13:53:42.999059 best DQS0 dly(2T, 0.5T) = (0, 12)
3056 13:53:43.001331 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 13:53:43.005036 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3058 13:53:43.008308 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 13:53:43.011628 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 13:53:43.014875 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 13:53:43.018296 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 13:53:43.021640 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 13:53:43.025420 Pre-setting of DQS Precalculation
3064 13:53:43.029436 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 13:53:43.029599 ==
3066 13:53:43.031491 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 13:53:43.036702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 13:53:43.036875 ==
3069 13:53:43.041485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 13:53:43.048083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3071 13:53:43.055755 [CA 0] Center 38 (9~68) winsize 60
3072 13:53:43.059678 [CA 1] Center 38 (8~68) winsize 61
3073 13:53:43.062485 [CA 2] Center 35 (5~65) winsize 61
3074 13:53:43.066475 [CA 3] Center 34 (4~65) winsize 62
3075 13:53:43.069245 [CA 4] Center 34 (4~65) winsize 62
3076 13:53:43.072999 [CA 5] Center 34 (4~64) winsize 61
3077 13:53:43.073153
3078 13:53:43.076002 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3079 13:53:43.076139
3080 13:53:43.079743 [CATrainingPosCal] consider 1 rank data
3081 13:53:43.083358 u2DelayCellTimex100 = 270/100 ps
3082 13:53:43.086122 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3083 13:53:43.089619 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3084 13:53:43.093007 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3085 13:53:43.099470 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3086 13:53:43.102720 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3087 13:53:43.106175 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3088 13:53:43.106323
3089 13:53:43.110235 CA PerBit enable=1, Macro0, CA PI delay=34
3090 13:53:43.110384
3091 13:53:43.112971 [CBTSetCACLKResult] CA Dly = 34
3092 13:53:43.113087 CS Dly: 5 (0~36)
3093 13:53:43.113182 ==
3094 13:53:43.116066 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 13:53:43.122657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 13:53:43.122799 ==
3097 13:53:43.125935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 13:53:43.132715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3099 13:53:43.141656 [CA 0] Center 38 (8~68) winsize 61
3100 13:53:43.144806 [CA 1] Center 38 (8~68) winsize 61
3101 13:53:43.148609 [CA 2] Center 34 (4~65) winsize 62
3102 13:53:43.151187 [CA 3] Center 34 (3~65) winsize 63
3103 13:53:43.155131 [CA 4] Center 34 (4~65) winsize 62
3104 13:53:43.158203 [CA 5] Center 33 (3~63) winsize 61
3105 13:53:43.158349
3106 13:53:43.161216 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 13:53:43.161351
3108 13:53:43.164619 [CATrainingPosCal] consider 2 rank data
3109 13:53:43.167967 u2DelayCellTimex100 = 270/100 ps
3110 13:53:43.171695 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3111 13:53:43.175177 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3112 13:53:43.182310 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3113 13:53:43.184943 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 13:53:43.187960 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3115 13:53:43.191782 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3116 13:53:43.191921
3117 13:53:43.195359 CA PerBit enable=1, Macro0, CA PI delay=33
3118 13:53:43.195472
3119 13:53:43.198747 [CBTSetCACLKResult] CA Dly = 33
3120 13:53:43.198850 CS Dly: 7 (0~40)
3121 13:53:43.198915
3122 13:53:43.201659 ----->DramcWriteLeveling(PI) begin...
3123 13:53:43.204889 ==
3124 13:53:43.205003 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 13:53:43.212035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 13:53:43.212184 ==
3127 13:53:43.215075 Write leveling (Byte 0): 25 => 25
3128 13:53:43.218121 Write leveling (Byte 1): 31 => 31
3129 13:53:43.218237 DramcWriteLeveling(PI) end<-----
3130 13:53:43.221599
3131 13:53:43.221712 ==
3132 13:53:43.225049 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 13:53:43.228355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 13:53:43.228477 ==
3135 13:53:43.231469 [Gating] SW mode calibration
3136 13:53:43.238432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 13:53:43.242010 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 13:53:43.248972 0 15 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
3139 13:53:43.251721 0 15 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3140 13:53:43.254957 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 13:53:43.262104 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 13:53:43.265696 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3143 13:53:43.268296 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 13:53:43.275228 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 13:53:43.278423 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3146 13:53:43.282049 1 0 0 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (1 0)
3147 13:53:43.285003 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 13:53:43.292107 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 13:53:43.295947 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 13:53:43.299121 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3151 13:53:43.305590 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 13:53:43.309429 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 13:53:43.311919 1 0 28 | B1->B0 | 2828 2626 | 1 0 | (0 0) (0 0)
3154 13:53:43.318807 1 1 0 | B1->B0 | 4040 2d2d | 0 0 | (0 0) (0 0)
3155 13:53:43.323033 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 13:53:43.325764 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 13:53:43.332083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 13:53:43.335701 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 13:53:43.339396 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 13:53:43.342289 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 13:53:43.349158 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 13:53:43.352467 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3163 13:53:43.355623 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 13:53:43.362154 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 13:53:43.365423 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 13:53:43.368687 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 13:53:43.376242 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 13:53:43.379240 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 13:53:43.382710 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 13:53:43.389996 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 13:53:43.392977 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 13:53:43.396122 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 13:53:43.399609 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 13:53:43.406372 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 13:53:43.409507 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 13:53:43.413112 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 13:53:43.419330 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 13:53:43.422824 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 13:53:43.426278 Total UI for P1: 0, mck2ui 16
3180 13:53:43.429444 best dqsien dly found for B0: ( 1, 3, 28)
3181 13:53:43.433032 Total UI for P1: 0, mck2ui 16
3182 13:53:43.436110 best dqsien dly found for B1: ( 1, 3, 30)
3183 13:53:43.440278 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3184 13:53:43.443160 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3185 13:53:43.443278
3186 13:53:43.445972 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3187 13:53:43.449801 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3188 13:53:43.453235 [Gating] SW calibration Done
3189 13:53:43.453361 ==
3190 13:53:43.456741 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 13:53:43.460058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 13:53:43.460184 ==
3193 13:53:43.463176 RX Vref Scan: 0
3194 13:53:43.463306
3195 13:53:43.466105 RX Vref 0 -> 0, step: 1
3196 13:53:43.466211
3197 13:53:43.466280 RX Delay -40 -> 252, step: 8
3198 13:53:43.473688 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3199 13:53:43.476814 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3200 13:53:43.479812 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3201 13:53:43.483236 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3202 13:53:43.486657 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3203 13:53:43.493383 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3204 13:53:43.496915 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3205 13:53:43.499917 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3206 13:53:43.503296 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3207 13:53:43.508028 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3208 13:53:43.510088 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3209 13:53:43.517254 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3210 13:53:43.520108 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3211 13:53:43.523529 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3212 13:53:43.527229 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3213 13:53:43.530238 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3214 13:53:43.533666 ==
3215 13:53:43.537028 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 13:53:43.540925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 13:53:43.541060 ==
3218 13:53:43.541133 DQS Delay:
3219 13:53:43.543916 DQS0 = 0, DQS1 = 0
3220 13:53:43.544017 DQM Delay:
3221 13:53:43.547103 DQM0 = 116, DQM1 = 109
3222 13:53:43.547211 DQ Delay:
3223 13:53:43.550344 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3224 13:53:43.553586 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3225 13:53:43.557582 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3226 13:53:43.560811 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3227 13:53:43.560941
3228 13:53:43.561010
3229 13:53:43.561071 ==
3230 13:53:43.564229 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 13:53:43.566883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 13:53:43.570304 ==
3233 13:53:43.570496
3234 13:53:43.570565
3235 13:53:43.570626 TX Vref Scan disable
3236 13:53:43.573914 == TX Byte 0 ==
3237 13:53:43.577255 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3238 13:53:43.581245 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3239 13:53:43.584257 == TX Byte 1 ==
3240 13:53:43.587243 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3241 13:53:43.590859 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3242 13:53:43.594026 ==
3243 13:53:43.594158 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 13:53:43.600635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 13:53:43.600897 ==
3246 13:53:43.611962 TX Vref=22, minBit 1, minWin=24, winSum=403
3247 13:53:43.614753 TX Vref=24, minBit 1, minWin=25, winSum=413
3248 13:53:43.618746 TX Vref=26, minBit 1, minWin=25, winSum=418
3249 13:53:43.621720 TX Vref=28, minBit 0, minWin=26, winSum=422
3250 13:53:43.625262 TX Vref=30, minBit 11, minWin=25, winSum=421
3251 13:53:43.631960 TX Vref=32, minBit 13, minWin=25, winSum=423
3252 13:53:43.635124 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
3253 13:53:43.635252
3254 13:53:43.638823 Final TX Range 1 Vref 28
3255 13:53:43.638951
3256 13:53:43.639017 ==
3257 13:53:43.642110 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 13:53:43.645553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 13:53:43.645696 ==
3260 13:53:43.645769
3261 13:53:43.648682
3262 13:53:43.648799 TX Vref Scan disable
3263 13:53:43.652427 == TX Byte 0 ==
3264 13:53:43.655640 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3265 13:53:43.658979 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3266 13:53:43.662006 == TX Byte 1 ==
3267 13:53:43.665049 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3268 13:53:43.669094 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3269 13:53:43.669243
3270 13:53:43.671787 [DATLAT]
3271 13:53:43.671914 Freq=1200, CH1 RK0
3272 13:53:43.671982
3273 13:53:43.675683 DATLAT Default: 0xd
3274 13:53:43.675819 0, 0xFFFF, sum = 0
3275 13:53:43.679316 1, 0xFFFF, sum = 0
3276 13:53:43.679454 2, 0xFFFF, sum = 0
3277 13:53:43.681803 3, 0xFFFF, sum = 0
3278 13:53:43.681915 4, 0xFFFF, sum = 0
3279 13:53:43.685905 5, 0xFFFF, sum = 0
3280 13:53:43.686045 6, 0xFFFF, sum = 0
3281 13:53:43.688726 7, 0xFFFF, sum = 0
3282 13:53:43.688848 8, 0xFFFF, sum = 0
3283 13:53:43.691954 9, 0xFFFF, sum = 0
3284 13:53:43.692097 10, 0xFFFF, sum = 0
3285 13:53:43.695768 11, 0xFFFF, sum = 0
3286 13:53:43.695914 12, 0x0, sum = 1
3287 13:53:43.699780 13, 0x0, sum = 2
3288 13:53:43.699924 14, 0x0, sum = 3
3289 13:53:43.702324 15, 0x0, sum = 4
3290 13:53:43.702498 best_step = 13
3291 13:53:43.702567
3292 13:53:43.702628 ==
3293 13:53:43.706174 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 13:53:43.712326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 13:53:43.712479 ==
3296 13:53:43.712549 RX Vref Scan: 1
3297 13:53:43.712610
3298 13:53:43.715605 Set Vref Range= 32 -> 127
3299 13:53:43.715731
3300 13:53:43.719155 RX Vref 32 -> 127, step: 1
3301 13:53:43.719356
3302 13:53:43.722260 RX Delay -21 -> 252, step: 4
3303 13:53:43.722384
3304 13:53:43.722500 Set Vref, RX VrefLevel [Byte0]: 32
3305 13:53:43.725707 [Byte1]: 32
3306 13:53:43.730255
3307 13:53:43.730458 Set Vref, RX VrefLevel [Byte0]: 33
3308 13:53:43.733903 [Byte1]: 33
3309 13:53:43.738184
3310 13:53:43.738342 Set Vref, RX VrefLevel [Byte0]: 34
3311 13:53:43.741521 [Byte1]: 34
3312 13:53:43.746288
3313 13:53:43.746486 Set Vref, RX VrefLevel [Byte0]: 35
3314 13:53:43.749800 [Byte1]: 35
3315 13:53:43.753785
3316 13:53:43.753930 Set Vref, RX VrefLevel [Byte0]: 36
3317 13:53:43.757463 [Byte1]: 36
3318 13:53:43.762262
3319 13:53:43.762443 Set Vref, RX VrefLevel [Byte0]: 37
3320 13:53:43.765253 [Byte1]: 37
3321 13:53:43.770315
3322 13:53:43.770510 Set Vref, RX VrefLevel [Byte0]: 38
3323 13:53:43.773221 [Byte1]: 38
3324 13:53:43.777662
3325 13:53:43.777790 Set Vref, RX VrefLevel [Byte0]: 39
3326 13:53:43.780945 [Byte1]: 39
3327 13:53:43.785527
3328 13:53:43.785660 Set Vref, RX VrefLevel [Byte0]: 40
3329 13:53:43.789167 [Byte1]: 40
3330 13:53:43.793353
3331 13:53:43.793491 Set Vref, RX VrefLevel [Byte0]: 41
3332 13:53:43.796649 [Byte1]: 41
3333 13:53:43.801420
3334 13:53:43.801556 Set Vref, RX VrefLevel [Byte0]: 42
3335 13:53:43.805117 [Byte1]: 42
3336 13:53:43.810113
3337 13:53:43.810249 Set Vref, RX VrefLevel [Byte0]: 43
3338 13:53:43.813088 [Byte1]: 43
3339 13:53:43.817485
3340 13:53:43.817618 Set Vref, RX VrefLevel [Byte0]: 44
3341 13:53:43.820690 [Byte1]: 44
3342 13:53:43.825065
3343 13:53:43.825200 Set Vref, RX VrefLevel [Byte0]: 45
3344 13:53:43.828315 [Byte1]: 45
3345 13:53:43.832951
3346 13:53:43.833086 Set Vref, RX VrefLevel [Byte0]: 46
3347 13:53:43.836433 [Byte1]: 46
3348 13:53:43.840978
3349 13:53:43.841139 Set Vref, RX VrefLevel [Byte0]: 47
3350 13:53:43.844275 [Byte1]: 47
3351 13:53:43.848826
3352 13:53:43.848969 Set Vref, RX VrefLevel [Byte0]: 48
3353 13:53:43.851977 [Byte1]: 48
3354 13:53:43.857109
3355 13:53:43.857244 Set Vref, RX VrefLevel [Byte0]: 49
3356 13:53:43.860372 [Byte1]: 49
3357 13:53:43.865108
3358 13:53:43.865274 Set Vref, RX VrefLevel [Byte0]: 50
3359 13:53:43.868710 [Byte1]: 50
3360 13:53:43.872504
3361 13:53:43.872657 Set Vref, RX VrefLevel [Byte0]: 51
3362 13:53:43.876415 [Byte1]: 51
3363 13:53:43.881043
3364 13:53:43.881220 Set Vref, RX VrefLevel [Byte0]: 52
3365 13:53:43.884481 [Byte1]: 52
3366 13:53:43.888599
3367 13:53:43.888760 Set Vref, RX VrefLevel [Byte0]: 53
3368 13:53:43.891572 [Byte1]: 53
3369 13:53:43.896866
3370 13:53:43.897055 Set Vref, RX VrefLevel [Byte0]: 54
3371 13:53:43.899417 [Byte1]: 54
3372 13:53:43.905252
3373 13:53:43.905438 Set Vref, RX VrefLevel [Byte0]: 55
3374 13:53:43.907869 [Byte1]: 55
3375 13:53:43.912728
3376 13:53:43.912908 Set Vref, RX VrefLevel [Byte0]: 56
3377 13:53:43.915718 [Byte1]: 56
3378 13:53:43.920366
3379 13:53:43.920535 Set Vref, RX VrefLevel [Byte0]: 57
3380 13:53:43.924362 [Byte1]: 57
3381 13:53:43.928172
3382 13:53:43.928349 Set Vref, RX VrefLevel [Byte0]: 58
3383 13:53:43.931507 [Byte1]: 58
3384 13:53:43.936674
3385 13:53:43.936854 Set Vref, RX VrefLevel [Byte0]: 59
3386 13:53:43.939496 [Byte1]: 59
3387 13:53:43.944026
3388 13:53:43.944165 Set Vref, RX VrefLevel [Byte0]: 60
3389 13:53:43.947179 [Byte1]: 60
3390 13:53:43.952134
3391 13:53:43.952279 Set Vref, RX VrefLevel [Byte0]: 61
3392 13:53:43.955099 [Byte1]: 61
3393 13:53:43.959842
3394 13:53:43.959980 Set Vref, RX VrefLevel [Byte0]: 62
3395 13:53:43.963207 [Byte1]: 62
3396 13:53:43.967771
3397 13:53:43.967913 Set Vref, RX VrefLevel [Byte0]: 63
3398 13:53:43.972019 [Byte1]: 63
3399 13:53:43.975990
3400 13:53:43.976121 Set Vref, RX VrefLevel [Byte0]: 64
3401 13:53:43.979194 [Byte1]: 64
3402 13:53:43.983937
3403 13:53:43.984081 Set Vref, RX VrefLevel [Byte0]: 65
3404 13:53:43.986837 [Byte1]: 65
3405 13:53:43.991818
3406 13:53:43.991965 Set Vref, RX VrefLevel [Byte0]: 66
3407 13:53:43.995081 [Byte1]: 66
3408 13:53:44.000448
3409 13:53:44.000597 Set Vref, RX VrefLevel [Byte0]: 67
3410 13:53:44.002842 [Byte1]: 67
3411 13:53:44.007259
3412 13:53:44.007396 Set Vref, RX VrefLevel [Byte0]: 68
3413 13:53:44.011093 [Byte1]: 68
3414 13:53:44.015340
3415 13:53:44.015478 Final RX Vref Byte 0 = 57 to rank0
3416 13:53:44.018966 Final RX Vref Byte 1 = 53 to rank0
3417 13:53:44.021882 Final RX Vref Byte 0 = 57 to rank1
3418 13:53:44.025834 Final RX Vref Byte 1 = 53 to rank1==
3419 13:53:44.028764 Dram Type= 6, Freq= 0, CH_1, rank 0
3420 13:53:44.032015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 13:53:44.035330 ==
3422 13:53:44.035447 DQS Delay:
3423 13:53:44.035515 DQS0 = 0, DQS1 = 0
3424 13:53:44.038750 DQM Delay:
3425 13:53:44.038858 DQM0 = 116, DQM1 = 109
3426 13:53:44.042747 DQ Delay:
3427 13:53:44.045643 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3428 13:53:44.049172 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3429 13:53:44.052396 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3430 13:53:44.056505 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =114
3431 13:53:44.056640
3432 13:53:44.056714
3433 13:53:44.062704 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3434 13:53:44.066255 CH1 RK0: MR19=303, MR18=FCE1
3435 13:53:44.072557 CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3436 13:53:44.072706
3437 13:53:44.075903 ----->DramcWriteLeveling(PI) begin...
3438 13:53:44.076015 ==
3439 13:53:44.079125 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 13:53:44.082638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 13:53:44.082761 ==
3442 13:53:44.085876 Write leveling (Byte 0): 25 => 25
3443 13:53:44.089630 Write leveling (Byte 1): 27 => 27
3444 13:53:44.092756 DramcWriteLeveling(PI) end<-----
3445 13:53:44.092893
3446 13:53:44.092965 ==
3447 13:53:44.096003 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 13:53:44.099266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 13:53:44.099389 ==
3450 13:53:44.102807 [Gating] SW mode calibration
3451 13:53:44.109176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3452 13:53:44.115850 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3453 13:53:44.119393 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3454 13:53:44.126592 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 13:53:44.129595 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 13:53:44.133056 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 13:53:44.136641 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 13:53:44.143242 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 13:53:44.146316 0 15 24 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
3460 13:53:44.150328 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 13:53:44.156318 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 13:53:44.159742 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 13:53:44.163129 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3464 13:53:44.169917 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 13:53:44.172888 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 13:53:44.176354 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 13:53:44.183022 1 0 24 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
3468 13:53:44.186127 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3469 13:53:44.189899 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 13:53:44.196717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 13:53:44.199789 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 13:53:44.203811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 13:53:44.206314 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 13:53:44.213417 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3475 13:53:44.216341 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3476 13:53:44.219861 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3477 13:53:44.226284 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 13:53:44.229942 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 13:53:44.233256 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 13:53:44.240292 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 13:53:44.243714 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 13:53:44.246340 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 13:53:44.253194 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 13:53:44.256374 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:53:44.260177 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:53:44.266306 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:53:44.269970 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:53:44.273668 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:53:44.279987 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 13:53:44.283011 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 13:53:44.286527 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3492 13:53:44.290089 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3493 13:53:44.293048 Total UI for P1: 0, mck2ui 16
3494 13:53:44.296311 best dqsien dly found for B0: ( 1, 3, 24)
3495 13:53:44.302857 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 13:53:44.306268 Total UI for P1: 0, mck2ui 16
3497 13:53:44.310081 best dqsien dly found for B1: ( 1, 3, 26)
3498 13:53:44.313046 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3499 13:53:44.316723 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3500 13:53:44.316864
3501 13:53:44.320085 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3502 13:53:44.324014 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3503 13:53:44.326866 [Gating] SW calibration Done
3504 13:53:44.327013 ==
3505 13:53:44.329768 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 13:53:44.333147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 13:53:44.333292 ==
3508 13:53:44.336756 RX Vref Scan: 0
3509 13:53:44.336887
3510 13:53:44.336983 RX Vref 0 -> 0, step: 1
3511 13:53:44.337074
3512 13:53:44.340057 RX Delay -40 -> 252, step: 8
3513 13:53:44.343818 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3514 13:53:44.350296 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3515 13:53:44.353113 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3516 13:53:44.356946 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3517 13:53:44.360527 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3518 13:53:44.363134 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3519 13:53:44.370350 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3520 13:53:44.372900 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3521 13:53:44.376472 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3522 13:53:44.379957 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3523 13:53:44.383445 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3524 13:53:44.390013 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3525 13:53:44.393496 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3526 13:53:44.396953 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3527 13:53:44.399820 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3528 13:53:44.403063 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3529 13:53:44.406807 ==
3530 13:53:44.409672 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 13:53:44.413142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 13:53:44.413289 ==
3533 13:53:44.413390 DQS Delay:
3534 13:53:44.416576 DQS0 = 0, DQS1 = 0
3535 13:53:44.416769 DQM Delay:
3536 13:53:44.419904 DQM0 = 113, DQM1 = 110
3537 13:53:44.420033 DQ Delay:
3538 13:53:44.423118 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3539 13:53:44.426335 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3540 13:53:44.430056 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3541 13:53:44.432874 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3542 13:53:44.433008
3543 13:53:44.433104
3544 13:53:44.433191 ==
3545 13:53:44.436394 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 13:53:44.443361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 13:53:44.443551 ==
3548 13:53:44.443652
3549 13:53:44.443742
3550 13:53:44.443831 TX Vref Scan disable
3551 13:53:44.446880 == TX Byte 0 ==
3552 13:53:44.449577 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3553 13:53:44.453436 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3554 13:53:44.456552 == TX Byte 1 ==
3555 13:53:44.460093 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3556 13:53:44.463281 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3557 13:53:44.466785 ==
3558 13:53:44.470327 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 13:53:44.473282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 13:53:44.473428 ==
3561 13:53:44.484126 TX Vref=22, minBit 6, minWin=25, winSum=418
3562 13:53:44.487759 TX Vref=24, minBit 3, minWin=25, winSum=423
3563 13:53:44.491343 TX Vref=26, minBit 1, minWin=25, winSum=426
3564 13:53:44.494102 TX Vref=28, minBit 3, minWin=26, winSum=432
3565 13:53:44.497827 TX Vref=30, minBit 0, minWin=27, winSum=435
3566 13:53:44.500862 TX Vref=32, minBit 4, minWin=26, winSum=434
3567 13:53:44.508026 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 30
3568 13:53:44.508217
3569 13:53:44.511053 Final TX Range 1 Vref 30
3570 13:53:44.511176
3571 13:53:44.511271 ==
3572 13:53:44.514477 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 13:53:44.518187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 13:53:44.518339 ==
3575 13:53:44.518465
3576 13:53:44.521009
3577 13:53:44.521124 TX Vref Scan disable
3578 13:53:44.524297 == TX Byte 0 ==
3579 13:53:44.527479 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3580 13:53:44.531008 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3581 13:53:44.534216 == TX Byte 1 ==
3582 13:53:44.538277 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3583 13:53:44.541219 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3584 13:53:44.541362
3585 13:53:44.543985 [DATLAT]
3586 13:53:44.544108 Freq=1200, CH1 RK1
3587 13:53:44.544205
3588 13:53:44.547703 DATLAT Default: 0xd
3589 13:53:44.547834 0, 0xFFFF, sum = 0
3590 13:53:44.550785 1, 0xFFFF, sum = 0
3591 13:53:44.550910 2, 0xFFFF, sum = 0
3592 13:53:44.554593 3, 0xFFFF, sum = 0
3593 13:53:44.554762 4, 0xFFFF, sum = 0
3594 13:53:44.557532 5, 0xFFFF, sum = 0
3595 13:53:44.557665 6, 0xFFFF, sum = 0
3596 13:53:44.561294 7, 0xFFFF, sum = 0
3597 13:53:44.564314 8, 0xFFFF, sum = 0
3598 13:53:44.564468 9, 0xFFFF, sum = 0
3599 13:53:44.568763 10, 0xFFFF, sum = 0
3600 13:53:44.568928 11, 0xFFFF, sum = 0
3601 13:53:44.571133 12, 0x0, sum = 1
3602 13:53:44.571253 13, 0x0, sum = 2
3603 13:53:44.574500 14, 0x0, sum = 3
3604 13:53:44.574635 15, 0x0, sum = 4
3605 13:53:44.574733 best_step = 13
3606 13:53:44.574823
3607 13:53:44.577742 ==
3608 13:53:44.577875 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 13:53:44.584321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 13:53:44.584499 ==
3611 13:53:44.584600 RX Vref Scan: 0
3612 13:53:44.584690
3613 13:53:44.587647 RX Vref 0 -> 0, step: 1
3614 13:53:44.587766
3615 13:53:44.591220 RX Delay -21 -> 252, step: 4
3616 13:53:44.594433 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3617 13:53:44.597664 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3618 13:53:44.604823 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3619 13:53:44.607949 iDelay=191, Bit 3, Center 110 (43 ~ 178) 136
3620 13:53:44.611270 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3621 13:53:44.614147 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3622 13:53:44.618009 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3623 13:53:44.624285 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3624 13:53:44.627495 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3625 13:53:44.630900 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3626 13:53:44.635503 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3627 13:53:44.637626 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3628 13:53:44.644018 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3629 13:53:44.647760 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3630 13:53:44.651198 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3631 13:53:44.654656 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3632 13:53:44.654807 ==
3633 13:53:44.657368 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 13:53:44.664417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 13:53:44.664606 ==
3636 13:53:44.664711 DQS Delay:
3637 13:53:44.664802 DQS0 = 0, DQS1 = 0
3638 13:53:44.667714 DQM Delay:
3639 13:53:44.667838 DQM0 = 113, DQM1 = 109
3640 13:53:44.671094 DQ Delay:
3641 13:53:44.674114 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =110
3642 13:53:44.678036 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3643 13:53:44.681078 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3644 13:53:44.684555 DQ12 =114, DQ13 =120, DQ14 =116, DQ15 =118
3645 13:53:44.684711
3646 13:53:44.684810
3647 13:53:44.690996 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3648 13:53:44.693969 CH1 RK1: MR19=303, MR18=F7FF
3649 13:53:44.701329 CH1_RK1: MR19=0x303, MR18=0xF7FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3650 13:53:44.704359 [RxdqsGatingPostProcess] freq 1200
3651 13:53:44.711207 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3652 13:53:44.714349 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 13:53:44.718218 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 13:53:44.721413 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 13:53:44.721565 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 13:53:44.724201 best DQS0 dly(2T, 0.5T) = (0, 11)
3657 13:53:44.727935 best DQS1 dly(2T, 0.5T) = (0, 11)
3658 13:53:44.732052 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3659 13:53:44.735383 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3660 13:53:44.737742 Pre-setting of DQS Precalculation
3661 13:53:44.744135 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3662 13:53:44.751522 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3663 13:53:44.757758 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3664 13:53:44.757946
3665 13:53:44.758048
3666 13:53:44.760524 [Calibration Summary] 2400 Mbps
3667 13:53:44.760644 CH 0, Rank 0
3668 13:53:44.764354 SW Impedance : PASS
3669 13:53:44.767645 DUTY Scan : NO K
3670 13:53:44.767808 ZQ Calibration : PASS
3671 13:53:44.771393 Jitter Meter : NO K
3672 13:53:44.773935 CBT Training : PASS
3673 13:53:44.774066 Write leveling : PASS
3674 13:53:44.777267 RX DQS gating : PASS
3675 13:53:44.781415 RX DQ/DQS(RDDQC) : PASS
3676 13:53:44.781605 TX DQ/DQS : PASS
3677 13:53:44.784620 RX DATLAT : PASS
3678 13:53:44.784756 RX DQ/DQS(Engine): PASS
3679 13:53:44.787755 TX OE : NO K
3680 13:53:44.787887 All Pass.
3681 13:53:44.787984
3682 13:53:44.791292 CH 0, Rank 1
3683 13:53:44.791431 SW Impedance : PASS
3684 13:53:44.794607 DUTY Scan : NO K
3685 13:53:44.797563 ZQ Calibration : PASS
3686 13:53:44.797731 Jitter Meter : NO K
3687 13:53:44.800924 CBT Training : PASS
3688 13:53:44.804315 Write leveling : PASS
3689 13:53:44.804466 RX DQS gating : PASS
3690 13:53:44.807489 RX DQ/DQS(RDDQC) : PASS
3691 13:53:44.811039 TX DQ/DQS : PASS
3692 13:53:44.811200 RX DATLAT : PASS
3693 13:53:44.814690 RX DQ/DQS(Engine): PASS
3694 13:53:44.817730 TX OE : NO K
3695 13:53:44.817878 All Pass.
3696 13:53:44.817978
3697 13:53:44.818068 CH 1, Rank 0
3698 13:53:44.821196 SW Impedance : PASS
3699 13:53:44.821332 DUTY Scan : NO K
3700 13:53:44.824218 ZQ Calibration : PASS
3701 13:53:44.827642 Jitter Meter : NO K
3702 13:53:44.827803 CBT Training : PASS
3703 13:53:44.830977 Write leveling : PASS
3704 13:53:44.834259 RX DQS gating : PASS
3705 13:53:44.834440 RX DQ/DQS(RDDQC) : PASS
3706 13:53:44.837716 TX DQ/DQS : PASS
3707 13:53:44.841217 RX DATLAT : PASS
3708 13:53:44.841374 RX DQ/DQS(Engine): PASS
3709 13:53:44.844343 TX OE : NO K
3710 13:53:44.844481 All Pass.
3711 13:53:44.844575
3712 13:53:44.847578 CH 1, Rank 1
3713 13:53:44.847708 SW Impedance : PASS
3714 13:53:44.850928 DUTY Scan : NO K
3715 13:53:44.855623 ZQ Calibration : PASS
3716 13:53:44.855794 Jitter Meter : NO K
3717 13:53:44.857391 CBT Training : PASS
3718 13:53:44.862650 Write leveling : PASS
3719 13:53:44.862820 RX DQS gating : PASS
3720 13:53:44.864152 RX DQ/DQS(RDDQC) : PASS
3721 13:53:44.864260 TX DQ/DQS : PASS
3722 13:53:44.867847 RX DATLAT : PASS
3723 13:53:44.871403 RX DQ/DQS(Engine): PASS
3724 13:53:44.871599 TX OE : NO K
3725 13:53:44.874326 All Pass.
3726 13:53:44.874497
3727 13:53:44.874597 DramC Write-DBI off
3728 13:53:44.877604 PER_BANK_REFRESH: Hybrid Mode
3729 13:53:44.881178 TX_TRACKING: ON
3730 13:53:44.887955 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3731 13:53:44.891042 [FAST_K] Save calibration result to emmc
3732 13:53:44.894145 dramc_set_vcore_voltage set vcore to 650000
3733 13:53:44.897484 Read voltage for 600, 5
3734 13:53:44.897643 Vio18 = 0
3735 13:53:44.900710 Vcore = 650000
3736 13:53:44.900853 Vdram = 0
3737 13:53:44.900954 Vddq = 0
3738 13:53:44.904586 Vmddr = 0
3739 13:53:44.907936 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3740 13:53:44.914310 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3741 13:53:44.914534 MEM_TYPE=3, freq_sel=19
3742 13:53:44.917880 sv_algorithm_assistance_LP4_1600
3743 13:53:44.924385 ============ PULL DRAM RESETB DOWN ============
3744 13:53:44.927773 ========== PULL DRAM RESETB DOWN end =========
3745 13:53:44.931059 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3746 13:53:44.935348 ===================================
3747 13:53:44.938326 LPDDR4 DRAM CONFIGURATION
3748 13:53:44.940889 ===================================
3749 13:53:44.941031 EX_ROW_EN[0] = 0x0
3750 13:53:44.944290 EX_ROW_EN[1] = 0x0
3751 13:53:44.948162 LP4Y_EN = 0x0
3752 13:53:44.948319 WORK_FSP = 0x0
3753 13:53:44.951407 WL = 0x2
3754 13:53:44.951541 RL = 0x2
3755 13:53:44.954589 BL = 0x2
3756 13:53:44.954724 RPST = 0x0
3757 13:53:44.957942 RD_PRE = 0x0
3758 13:53:44.958095 WR_PRE = 0x1
3759 13:53:44.961413 WR_PST = 0x0
3760 13:53:44.961557 DBI_WR = 0x0
3761 13:53:44.964501 DBI_RD = 0x0
3762 13:53:44.964639 OTF = 0x1
3763 13:53:44.967831 ===================================
3764 13:53:44.971330 ===================================
3765 13:53:44.975187 ANA top config
3766 13:53:44.977756 ===================================
3767 13:53:44.977903 DLL_ASYNC_EN = 0
3768 13:53:44.981115 ALL_SLAVE_EN = 1
3769 13:53:44.984576 NEW_RANK_MODE = 1
3770 13:53:44.988393 DLL_IDLE_MODE = 1
3771 13:53:44.988563 LP45_APHY_COMB_EN = 1
3772 13:53:44.991184 TX_ODT_DIS = 1
3773 13:53:44.994607 NEW_8X_MODE = 1
3774 13:53:44.997501 ===================================
3775 13:53:45.000925 ===================================
3776 13:53:45.004703 data_rate = 1200
3777 13:53:45.007839 CKR = 1
3778 13:53:45.008056 DQ_P2S_RATIO = 8
3779 13:53:45.011248 ===================================
3780 13:53:45.014602 CA_P2S_RATIO = 8
3781 13:53:45.018016 DQ_CA_OPEN = 0
3782 13:53:45.021410 DQ_SEMI_OPEN = 0
3783 13:53:45.024450 CA_SEMI_OPEN = 0
3784 13:53:45.027970 CA_FULL_RATE = 0
3785 13:53:45.028169 DQ_CKDIV4_EN = 1
3786 13:53:45.031040 CA_CKDIV4_EN = 1
3787 13:53:45.034462 CA_PREDIV_EN = 0
3788 13:53:45.037663 PH8_DLY = 0
3789 13:53:45.041204 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3790 13:53:45.044272 DQ_AAMCK_DIV = 4
3791 13:53:45.044430 CA_AAMCK_DIV = 4
3792 13:53:45.047620 CA_ADMCK_DIV = 4
3793 13:53:45.050982 DQ_TRACK_CA_EN = 0
3794 13:53:45.054855 CA_PICK = 600
3795 13:53:45.057648 CA_MCKIO = 600
3796 13:53:45.061011 MCKIO_SEMI = 0
3797 13:53:45.065212 PLL_FREQ = 2288
3798 13:53:45.065388 DQ_UI_PI_RATIO = 32
3799 13:53:45.068374 CA_UI_PI_RATIO = 0
3800 13:53:45.072273 ===================================
3801 13:53:45.074683 ===================================
3802 13:53:45.078192 memory_type:LPDDR4
3803 13:53:45.081144 GP_NUM : 10
3804 13:53:45.081271 SRAM_EN : 1
3805 13:53:45.084880 MD32_EN : 0
3806 13:53:45.088636 ===================================
3807 13:53:45.088773 [ANA_INIT] >>>>>>>>>>>>>>
3808 13:53:45.090937 <<<<<< [CONFIGURE PHASE]: ANA_TX
3809 13:53:45.094865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3810 13:53:45.097782 ===================================
3811 13:53:45.101501 data_rate = 1200,PCW = 0X5800
3812 13:53:45.105205 ===================================
3813 13:53:45.107900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3814 13:53:45.114986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3815 13:53:45.118428 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 13:53:45.124283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3817 13:53:45.127959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3818 13:53:45.131242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3819 13:53:45.134236 [ANA_INIT] flow start
3820 13:53:45.134364 [ANA_INIT] PLL >>>>>>>>
3821 13:53:45.138180 [ANA_INIT] PLL <<<<<<<<
3822 13:53:45.141369 [ANA_INIT] MIDPI >>>>>>>>
3823 13:53:45.141500 [ANA_INIT] MIDPI <<<<<<<<
3824 13:53:45.144166 [ANA_INIT] DLL >>>>>>>>
3825 13:53:45.147821 [ANA_INIT] flow end
3826 13:53:45.150940 ============ LP4 DIFF to SE enter ============
3827 13:53:45.154551 ============ LP4 DIFF to SE exit ============
3828 13:53:45.157879 [ANA_INIT] <<<<<<<<<<<<<
3829 13:53:45.161124 [Flow] Enable top DCM control >>>>>
3830 13:53:45.164624 [Flow] Enable top DCM control <<<<<
3831 13:53:45.167913 Enable DLL master slave shuffle
3832 13:53:45.172220 ==============================================================
3833 13:53:45.174957 Gating Mode config
3834 13:53:45.177588 ==============================================================
3835 13:53:45.181901 Config description:
3836 13:53:45.191327 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3837 13:53:45.198583 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3838 13:53:45.201483 SELPH_MODE 0: By rank 1: By Phase
3839 13:53:45.207758 ==============================================================
3840 13:53:45.211248 GAT_TRACK_EN = 1
3841 13:53:45.214912 RX_GATING_MODE = 2
3842 13:53:45.217736 RX_GATING_TRACK_MODE = 2
3843 13:53:45.220987 SELPH_MODE = 1
3844 13:53:45.224466 PICG_EARLY_EN = 1
3845 13:53:45.224626 VALID_LAT_VALUE = 1
3846 13:53:45.231231 ==============================================================
3847 13:53:45.234444 Enter into Gating configuration >>>>
3848 13:53:45.238573 Exit from Gating configuration <<<<
3849 13:53:45.241078 Enter into DVFS_PRE_config >>>>>
3850 13:53:45.251369 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3851 13:53:45.254842 Exit from DVFS_PRE_config <<<<<
3852 13:53:45.258503 Enter into PICG configuration >>>>
3853 13:53:45.261662 Exit from PICG configuration <<<<
3854 13:53:45.264443 [RX_INPUT] configuration >>>>>
3855 13:53:45.267731 [RX_INPUT] configuration <<<<<
3856 13:53:45.271215 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3857 13:53:45.278114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3858 13:53:45.284546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 13:53:45.291313 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 13:53:45.297966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 13:53:45.301571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 13:53:45.308368 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3863 13:53:45.311928 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3864 13:53:45.315439 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3865 13:53:45.318030 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3866 13:53:45.321070 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3867 13:53:45.328045 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3868 13:53:45.331536 ===================================
3869 13:53:45.334737 LPDDR4 DRAM CONFIGURATION
3870 13:53:45.334956 ===================================
3871 13:53:45.337841 EX_ROW_EN[0] = 0x0
3872 13:53:45.341023 EX_ROW_EN[1] = 0x0
3873 13:53:45.341177 LP4Y_EN = 0x0
3874 13:53:45.344757 WORK_FSP = 0x0
3875 13:53:45.344907 WL = 0x2
3876 13:53:45.348420 RL = 0x2
3877 13:53:45.348568 BL = 0x2
3878 13:53:45.351523 RPST = 0x0
3879 13:53:45.351655 RD_PRE = 0x0
3880 13:53:45.354404 WR_PRE = 0x1
3881 13:53:45.354562 WR_PST = 0x0
3882 13:53:45.358130 DBI_WR = 0x0
3883 13:53:45.358263 DBI_RD = 0x0
3884 13:53:45.361686 OTF = 0x1
3885 13:53:45.365015 ===================================
3886 13:53:45.368421 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3887 13:53:45.371125 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3888 13:53:45.378465 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 13:53:45.381517 ===================================
3890 13:53:45.381665 LPDDR4 DRAM CONFIGURATION
3891 13:53:45.384462 ===================================
3892 13:53:45.387855 EX_ROW_EN[0] = 0x10
3893 13:53:45.391599 EX_ROW_EN[1] = 0x0
3894 13:53:45.391754 LP4Y_EN = 0x0
3895 13:53:45.394294 WORK_FSP = 0x0
3896 13:53:45.394469 WL = 0x2
3897 13:53:45.397904 RL = 0x2
3898 13:53:45.398043 BL = 0x2
3899 13:53:45.401872 RPST = 0x0
3900 13:53:45.402018 RD_PRE = 0x0
3901 13:53:45.404478 WR_PRE = 0x1
3902 13:53:45.404600 WR_PST = 0x0
3903 13:53:45.408195 DBI_WR = 0x0
3904 13:53:45.408327 DBI_RD = 0x0
3905 13:53:45.411065 OTF = 0x1
3906 13:53:45.414574 ===================================
3907 13:53:45.421265 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3908 13:53:45.424567 nWR fixed to 30
3909 13:53:45.424739 [ModeRegInit_LP4] CH0 RK0
3910 13:53:45.428910 [ModeRegInit_LP4] CH0 RK1
3911 13:53:45.431026 [ModeRegInit_LP4] CH1 RK0
3912 13:53:45.431162 [ModeRegInit_LP4] CH1 RK1
3913 13:53:45.434295 match AC timing 17
3914 13:53:45.438153 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3915 13:53:45.441356 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3916 13:53:45.447828 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3917 13:53:45.451493 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3918 13:53:45.457832 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3919 13:53:45.458022 ==
3920 13:53:45.461986 Dram Type= 6, Freq= 0, CH_0, rank 0
3921 13:53:45.464312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3922 13:53:45.464446 ==
3923 13:53:45.470831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3924 13:53:45.477796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3925 13:53:45.481077 [CA 0] Center 36 (6~66) winsize 61
3926 13:53:45.484698 [CA 1] Center 35 (5~66) winsize 62
3927 13:53:45.487869 [CA 2] Center 34 (4~64) winsize 61
3928 13:53:45.491115 [CA 3] Center 34 (4~64) winsize 61
3929 13:53:45.494409 [CA 4] Center 33 (3~64) winsize 62
3930 13:53:45.494603 [CA 5] Center 33 (3~64) winsize 62
3931 13:53:45.498531
3932 13:53:45.500875 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3933 13:53:45.501011
3934 13:53:45.504279 [CATrainingPosCal] consider 1 rank data
3935 13:53:45.507393 u2DelayCellTimex100 = 270/100 ps
3936 13:53:45.510911 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3937 13:53:45.514522 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3938 13:53:45.517664 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3939 13:53:45.520933 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3940 13:53:45.524333 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3941 13:53:45.527940 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3942 13:53:45.528112
3943 13:53:45.530805 CA PerBit enable=1, Macro0, CA PI delay=33
3944 13:53:45.530937
3945 13:53:45.534971 [CBTSetCACLKResult] CA Dly = 33
3946 13:53:45.537383 CS Dly: 4 (0~35)
3947 13:53:45.537527 ==
3948 13:53:45.541670 Dram Type= 6, Freq= 0, CH_0, rank 1
3949 13:53:45.544817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 13:53:45.544991 ==
3951 13:53:45.550709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 13:53:45.557686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3953 13:53:45.560900 [CA 0] Center 36 (6~66) winsize 61
3954 13:53:45.564460 [CA 1] Center 36 (6~66) winsize 61
3955 13:53:45.568305 [CA 2] Center 34 (4~65) winsize 62
3956 13:53:45.571205 [CA 3] Center 34 (4~65) winsize 62
3957 13:53:45.574666 [CA 4] Center 33 (3~64) winsize 62
3958 13:53:45.577659 [CA 5] Center 33 (3~64) winsize 62
3959 13:53:45.577820
3960 13:53:45.581307 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3961 13:53:45.581458
3962 13:53:45.584344 [CATrainingPosCal] consider 2 rank data
3963 13:53:45.588133 u2DelayCellTimex100 = 270/100 ps
3964 13:53:45.590813 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3965 13:53:45.594617 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3966 13:53:45.597560 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3967 13:53:45.601158 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3968 13:53:45.604384 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3969 13:53:45.608069 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 13:53:45.608240
3971 13:53:45.611296 CA PerBit enable=1, Macro0, CA PI delay=33
3972 13:53:45.611442
3973 13:53:45.614612 [CBTSetCACLKResult] CA Dly = 33
3974 13:53:45.617694 CS Dly: 4 (0~36)
3975 13:53:45.617848
3976 13:53:45.621421 ----->DramcWriteLeveling(PI) begin...
3977 13:53:45.621588 ==
3978 13:53:45.624727 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 13:53:45.629566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 13:53:45.629752 ==
3981 13:53:45.631361 Write leveling (Byte 0): 31 => 31
3982 13:53:45.634906 Write leveling (Byte 1): 30 => 30
3983 13:53:45.637819 DramcWriteLeveling(PI) end<-----
3984 13:53:45.637969
3985 13:53:45.638067 ==
3986 13:53:45.641179 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 13:53:45.645071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 13:53:45.645241 ==
3989 13:53:45.647976 [Gating] SW mode calibration
3990 13:53:45.654587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3991 13:53:45.661649 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3992 13:53:45.664691 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 13:53:45.668084 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 13:53:45.674705 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 13:53:45.677949 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
3996 13:53:45.681260 0 9 16 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (1 1)
3997 13:53:45.687828 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3998 13:53:45.691401 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 13:53:45.695075 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 13:53:45.701892 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 13:53:45.704260 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 13:53:45.707897 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 13:53:45.714301 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 13:53:45.717889 0 10 16 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (1 1)
4005 13:53:45.721138 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 13:53:45.728204 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 13:53:45.731220 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 13:53:45.735271 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 13:53:45.740867 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 13:53:45.744344 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 13:53:45.747890 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 13:53:45.754469 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4013 13:53:45.757588 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4014 13:53:45.761235 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 13:53:45.765074 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 13:53:45.771389 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 13:53:45.774593 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 13:53:45.778083 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:53:45.784605 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:53:45.787900 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:53:45.791449 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:53:45.798173 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:53:45.801103 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:53:45.804528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:53:45.811355 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:53:45.814677 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:53:45.817659 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4028 13:53:45.825642 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 13:53:45.825885 Total UI for P1: 0, mck2ui 16
4030 13:53:45.827880 best dqsien dly found for B0: ( 0, 13, 14)
4031 13:53:45.831753 Total UI for P1: 0, mck2ui 16
4032 13:53:45.835642 best dqsien dly found for B1: ( 0, 13, 12)
4033 13:53:45.841604 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4034 13:53:45.845868 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4035 13:53:45.846049
4036 13:53:45.848177 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4037 13:53:45.851677 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4038 13:53:45.855047 [Gating] SW calibration Done
4039 13:53:45.855215 ==
4040 13:53:45.858532 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 13:53:45.862223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 13:53:45.862377 ==
4043 13:53:45.862529 RX Vref Scan: 0
4044 13:53:45.864903
4045 13:53:45.865020 RX Vref 0 -> 0, step: 1
4046 13:53:45.865115
4047 13:53:45.868872 RX Delay -230 -> 252, step: 16
4048 13:53:45.871545 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4049 13:53:45.878110 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4050 13:53:45.882375 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4051 13:53:45.885282 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4052 13:53:45.888191 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4053 13:53:45.892872 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4054 13:53:45.898112 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4055 13:53:45.901753 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4056 13:53:45.904947 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4057 13:53:45.908499 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4058 13:53:45.915633 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4059 13:53:45.918258 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4060 13:53:45.921534 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4061 13:53:45.925349 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4062 13:53:45.928281 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4063 13:53:45.934900 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4064 13:53:45.935092 ==
4065 13:53:45.938200 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 13:53:45.941401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 13:53:45.941549 ==
4068 13:53:45.941647 DQS Delay:
4069 13:53:45.944648 DQS0 = 0, DQS1 = 0
4070 13:53:45.944782 DQM Delay:
4071 13:53:45.948141 DQM0 = 42, DQM1 = 32
4072 13:53:45.948272 DQ Delay:
4073 13:53:45.951550 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4074 13:53:45.955799 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4075 13:53:45.958010 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4076 13:53:45.961491 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4077 13:53:45.961651
4078 13:53:45.961749
4079 13:53:45.961839 ==
4080 13:53:45.964871 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 13:53:45.968051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 13:53:45.971957 ==
4083 13:53:45.972121
4084 13:53:45.972221
4085 13:53:45.972310 TX Vref Scan disable
4086 13:53:45.975008 == TX Byte 0 ==
4087 13:53:45.978869 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4088 13:53:45.981787 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4089 13:53:45.985447 == TX Byte 1 ==
4090 13:53:45.987897 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4091 13:53:45.991518 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4092 13:53:45.994817 ==
4093 13:53:45.994970 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 13:53:46.001593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 13:53:46.001780 ==
4096 13:53:46.001883
4097 13:53:46.001974
4098 13:53:46.002063 TX Vref Scan disable
4099 13:53:46.006580 == TX Byte 0 ==
4100 13:53:46.009188 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4101 13:53:46.013000 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4102 13:53:46.016171 == TX Byte 1 ==
4103 13:53:46.019971 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4104 13:53:46.023002 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4105 13:53:46.026627
4106 13:53:46.026789 [DATLAT]
4107 13:53:46.026889 Freq=600, CH0 RK0
4108 13:53:46.026980
4109 13:53:46.030157 DATLAT Default: 0x9
4110 13:53:46.030298 0, 0xFFFF, sum = 0
4111 13:53:46.033423 1, 0xFFFF, sum = 0
4112 13:53:46.033558 2, 0xFFFF, sum = 0
4113 13:53:46.036493 3, 0xFFFF, sum = 0
4114 13:53:46.036627 4, 0xFFFF, sum = 0
4115 13:53:46.039702 5, 0xFFFF, sum = 0
4116 13:53:46.039830 6, 0xFFFF, sum = 0
4117 13:53:46.043095 7, 0xFFFF, sum = 0
4118 13:53:46.043251 8, 0x0, sum = 1
4119 13:53:46.046241 9, 0x0, sum = 2
4120 13:53:46.046374 10, 0x0, sum = 3
4121 13:53:46.049385 11, 0x0, sum = 4
4122 13:53:46.049513 best_step = 9
4123 13:53:46.049608
4124 13:53:46.049698 ==
4125 13:53:46.053427 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 13:53:46.059686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 13:53:46.059875 ==
4128 13:53:46.059979 RX Vref Scan: 1
4129 13:53:46.060070
4130 13:53:46.062737 RX Vref 0 -> 0, step: 1
4131 13:53:46.062857
4132 13:53:46.066525 RX Delay -195 -> 252, step: 8
4133 13:53:46.066676
4134 13:53:46.070002 Set Vref, RX VrefLevel [Byte0]: 53
4135 13:53:46.073070 [Byte1]: 51
4136 13:53:46.073213
4137 13:53:46.077168 Final RX Vref Byte 0 = 53 to rank0
4138 13:53:46.079615 Final RX Vref Byte 1 = 51 to rank0
4139 13:53:46.082907 Final RX Vref Byte 0 = 53 to rank1
4140 13:53:46.086290 Final RX Vref Byte 1 = 51 to rank1==
4141 13:53:46.089927 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 13:53:46.092599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 13:53:46.092741 ==
4144 13:53:46.096286 DQS Delay:
4145 13:53:46.096464 DQS0 = 0, DQS1 = 0
4146 13:53:46.096578 DQM Delay:
4147 13:53:46.099517 DQM0 = 42, DQM1 = 33
4148 13:53:46.099646 DQ Delay:
4149 13:53:46.103257 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4150 13:53:46.107445 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4151 13:53:46.110374 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4152 13:53:46.113027 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4153 13:53:46.113176
4154 13:53:46.113275
4155 13:53:46.122833 [DQSOSCAuto] RK0, (LSB)MR18= 0x4624, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4156 13:53:46.123038 CH0 RK0: MR19=808, MR18=4624
4157 13:53:46.129415 CH0_RK0: MR19=0x808, MR18=0x4624, DQSOSC=396, MR23=63, INC=167, DEC=111
4158 13:53:46.129654
4159 13:53:46.133083 ----->DramcWriteLeveling(PI) begin...
4160 13:53:46.133227 ==
4161 13:53:46.136218 Dram Type= 6, Freq= 0, CH_0, rank 1
4162 13:53:46.142771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 13:53:46.142960 ==
4164 13:53:46.146041 Write leveling (Byte 0): 30 => 30
4165 13:53:46.150293 Write leveling (Byte 1): 30 => 30
4166 13:53:46.150503 DramcWriteLeveling(PI) end<-----
4167 13:53:46.150607
4168 13:53:46.154153 ==
4169 13:53:46.156086 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 13:53:46.159963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 13:53:46.160120 ==
4172 13:53:46.163308 [Gating] SW mode calibration
4173 13:53:46.169524 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4174 13:53:46.172866 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4175 13:53:46.179393 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 13:53:46.183598 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 13:53:46.186434 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 13:53:46.193036 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
4179 13:53:46.196154 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (0 0)
4180 13:53:46.199513 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 13:53:46.205996 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 13:53:46.209747 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 13:53:46.213268 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 13:53:46.216304 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 13:53:46.223558 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 13:53:46.226207 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4187 13:53:46.230061 0 10 16 | B1->B0 | 3737 4545 | 0 0 | (1 1) (0 0)
4188 13:53:46.236208 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 13:53:46.239635 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 13:53:46.243274 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 13:53:46.249978 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 13:53:46.253042 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 13:53:46.256119 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 13:53:46.263099 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4195 13:53:46.266888 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4196 13:53:46.270144 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 13:53:46.276539 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 13:53:46.279892 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 13:53:46.283812 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 13:53:46.289590 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 13:53:46.293046 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 13:53:46.296634 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:53:46.302906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:53:46.306322 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:53:46.310045 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:53:46.313349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:53:46.319559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:53:46.322954 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:53:46.326749 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 13:53:46.333118 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4211 13:53:46.336688 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4212 13:53:46.339714 Total UI for P1: 0, mck2ui 16
4213 13:53:46.343001 best dqsien dly found for B0: ( 0, 13, 12)
4214 13:53:46.346513 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 13:53:46.349819 Total UI for P1: 0, mck2ui 16
4216 13:53:46.353392 best dqsien dly found for B1: ( 0, 13, 16)
4217 13:53:46.356952 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4218 13:53:46.359653 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4219 13:53:46.359767
4220 13:53:46.366538 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4221 13:53:46.370483 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4222 13:53:46.373241 [Gating] SW calibration Done
4223 13:53:46.373359 ==
4224 13:53:46.376329 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 13:53:46.379885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 13:53:46.380013 ==
4227 13:53:46.380109 RX Vref Scan: 0
4228 13:53:46.380202
4229 13:53:46.383250 RX Vref 0 -> 0, step: 1
4230 13:53:46.383365
4231 13:53:46.386291 RX Delay -230 -> 252, step: 16
4232 13:53:46.389541 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4233 13:53:46.392967 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4234 13:53:46.399850 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4235 13:53:46.403093 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4236 13:53:46.406754 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4237 13:53:46.409932 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4238 13:53:46.413317 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4239 13:53:46.420114 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4240 13:53:46.423187 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4241 13:53:46.426082 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4242 13:53:46.429879 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4243 13:53:46.436488 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4244 13:53:46.439754 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4245 13:53:46.443181 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4246 13:53:46.446364 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4247 13:53:46.453057 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4248 13:53:46.453227 ==
4249 13:53:46.456474 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 13:53:46.459668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 13:53:46.459799 ==
4252 13:53:46.459898 DQS Delay:
4253 13:53:46.462855 DQS0 = 0, DQS1 = 0
4254 13:53:46.462967 DQM Delay:
4255 13:53:46.467023 DQM0 = 41, DQM1 = 32
4256 13:53:46.467156 DQ Delay:
4257 13:53:46.470075 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4258 13:53:46.472815 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =57
4259 13:53:46.476220 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4260 13:53:46.480825 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4261 13:53:46.480944
4262 13:53:46.481011
4263 13:53:46.481071 ==
4264 13:53:46.483418 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 13:53:46.486419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 13:53:46.486522 ==
4267 13:53:46.486590
4268 13:53:46.486650
4269 13:53:46.489839 TX Vref Scan disable
4270 13:53:46.493035 == TX Byte 0 ==
4271 13:53:46.496563 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4272 13:53:46.500224 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4273 13:53:46.503103 == TX Byte 1 ==
4274 13:53:46.506184 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4275 13:53:46.509877 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4276 13:53:46.509980 ==
4277 13:53:46.513496 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 13:53:46.519462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 13:53:46.519581 ==
4280 13:53:46.519649
4281 13:53:46.519709
4282 13:53:46.519768 TX Vref Scan disable
4283 13:53:46.523989 == TX Byte 0 ==
4284 13:53:46.527340 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4285 13:53:46.533987 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4286 13:53:46.534123 == TX Byte 1 ==
4287 13:53:46.537105 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4288 13:53:46.543605 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4289 13:53:46.543739
4290 13:53:46.543808 [DATLAT]
4291 13:53:46.543869 Freq=600, CH0 RK1
4292 13:53:46.543929
4293 13:53:46.547457 DATLAT Default: 0x9
4294 13:53:46.547565 0, 0xFFFF, sum = 0
4295 13:53:46.550707 1, 0xFFFF, sum = 0
4296 13:53:46.553624 2, 0xFFFF, sum = 0
4297 13:53:46.553722 3, 0xFFFF, sum = 0
4298 13:53:46.557353 4, 0xFFFF, sum = 0
4299 13:53:46.557450 5, 0xFFFF, sum = 0
4300 13:53:46.560518 6, 0xFFFF, sum = 0
4301 13:53:46.560646 7, 0xFFFF, sum = 0
4302 13:53:46.563838 8, 0x0, sum = 1
4303 13:53:46.563931 9, 0x0, sum = 2
4304 13:53:46.563997 10, 0x0, sum = 3
4305 13:53:46.567145 11, 0x0, sum = 4
4306 13:53:46.567238 best_step = 9
4307 13:53:46.567303
4308 13:53:46.567362 ==
4309 13:53:46.571054 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 13:53:46.577433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 13:53:46.577571 ==
4312 13:53:46.577639 RX Vref Scan: 0
4313 13:53:46.577700
4314 13:53:46.580393 RX Vref 0 -> 0, step: 1
4315 13:53:46.580482
4316 13:53:46.584183 RX Delay -195 -> 252, step: 8
4317 13:53:46.586988 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4318 13:53:46.594227 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4319 13:53:46.597290 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4320 13:53:46.601303 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4321 13:53:46.604081 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4322 13:53:46.607180 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4323 13:53:46.614507 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4324 13:53:46.617229 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4325 13:53:46.620394 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4326 13:53:46.623504 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4327 13:53:46.630659 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4328 13:53:46.633979 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4329 13:53:46.636916 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4330 13:53:46.640631 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4331 13:53:46.647056 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4332 13:53:46.650614 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4333 13:53:46.650749 ==
4334 13:53:46.653942 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 13:53:46.657432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 13:53:46.657565 ==
4337 13:53:46.657665 DQS Delay:
4338 13:53:46.660812 DQS0 = 0, DQS1 = 0
4339 13:53:46.660928 DQM Delay:
4340 13:53:46.664000 DQM0 = 39, DQM1 = 33
4341 13:53:46.664114 DQ Delay:
4342 13:53:46.666952 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4343 13:53:46.670282 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4344 13:53:46.673729 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4345 13:53:46.676899 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4346 13:53:46.677025
4347 13:53:46.677122
4348 13:53:46.687087 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4349 13:53:46.687268 CH0 RK1: MR19=808, MR18=4A2C
4350 13:53:46.693744 CH0_RK1: MR19=0x808, MR18=0x4A2C, DQSOSC=395, MR23=63, INC=168, DEC=112
4351 13:53:46.697051 [RxdqsGatingPostProcess] freq 600
4352 13:53:46.703644 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4353 13:53:46.707326 Pre-setting of DQS Precalculation
4354 13:53:46.711482 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4355 13:53:46.711625 ==
4356 13:53:46.713849 Dram Type= 6, Freq= 0, CH_1, rank 0
4357 13:53:46.717058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 13:53:46.717180 ==
4359 13:53:46.723960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 13:53:46.730265 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4361 13:53:46.734106 [CA 0] Center 35 (5~65) winsize 61
4362 13:53:46.737311 [CA 1] Center 35 (5~66) winsize 62
4363 13:53:46.740563 [CA 2] Center 34 (4~65) winsize 62
4364 13:53:46.743488 [CA 3] Center 33 (3~64) winsize 62
4365 13:53:46.746988 [CA 4] Center 34 (3~65) winsize 63
4366 13:53:46.750621 [CA 5] Center 33 (2~64) winsize 63
4367 13:53:46.750763
4368 13:53:46.753590 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4369 13:53:46.753711
4370 13:53:46.757885 [CATrainingPosCal] consider 1 rank data
4371 13:53:46.760288 u2DelayCellTimex100 = 270/100 ps
4372 13:53:46.763676 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4373 13:53:46.767372 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 13:53:46.770700 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 13:53:46.773620 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 13:53:46.776947 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4377 13:53:46.783841 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4378 13:53:46.784008
4379 13:53:46.787182 CA PerBit enable=1, Macro0, CA PI delay=33
4380 13:53:46.787315
4381 13:53:46.790959 [CBTSetCACLKResult] CA Dly = 33
4382 13:53:46.791088 CS Dly: 3 (0~34)
4383 13:53:46.791187 ==
4384 13:53:46.793609 Dram Type= 6, Freq= 0, CH_1, rank 1
4385 13:53:46.796813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 13:53:46.800586 ==
4387 13:53:46.804395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 13:53:46.810290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4389 13:53:46.814237 [CA 0] Center 35 (5~66) winsize 62
4390 13:53:46.816872 [CA 1] Center 35 (5~66) winsize 62
4391 13:53:46.820597 [CA 2] Center 34 (4~65) winsize 62
4392 13:53:46.823903 [CA 3] Center 34 (3~65) winsize 63
4393 13:53:46.827908 [CA 4] Center 34 (4~65) winsize 62
4394 13:53:46.830983 [CA 5] Center 33 (3~64) winsize 62
4395 13:53:46.831121
4396 13:53:46.834211 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4397 13:53:46.834335
4398 13:53:46.837084 [CATrainingPosCal] consider 2 rank data
4399 13:53:46.840530 u2DelayCellTimex100 = 270/100 ps
4400 13:53:46.843724 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4401 13:53:46.847056 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 13:53:46.850695 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 13:53:46.853716 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 13:53:46.856836 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 13:53:46.863928 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 13:53:46.864092
4407 13:53:46.867684 CA PerBit enable=1, Macro0, CA PI delay=33
4408 13:53:46.867809
4409 13:53:46.870526 [CBTSetCACLKResult] CA Dly = 33
4410 13:53:46.870648 CS Dly: 5 (0~38)
4411 13:53:46.870746
4412 13:53:46.873969 ----->DramcWriteLeveling(PI) begin...
4413 13:53:46.874091 ==
4414 13:53:46.876921 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 13:53:46.884226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 13:53:46.884400 ==
4417 13:53:46.884506 Write leveling (Byte 0): 30 => 30
4418 13:53:46.887226 Write leveling (Byte 1): 29 => 29
4419 13:53:46.890321 DramcWriteLeveling(PI) end<-----
4420 13:53:46.890454
4421 13:53:46.890551 ==
4422 13:53:46.894192 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 13:53:46.900576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 13:53:46.900731 ==
4425 13:53:46.900828 [Gating] SW mode calibration
4426 13:53:46.910523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4427 13:53:46.914158 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4428 13:53:46.917342 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4429 13:53:46.923974 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4430 13:53:46.927495 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4431 13:53:46.931565 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 1)
4432 13:53:46.937240 0 9 16 | B1->B0 | 2828 2525 | 0 0 | (1 1) (1 1)
4433 13:53:46.940649 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 13:53:46.944079 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 13:53:46.950754 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 13:53:46.953815 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 13:53:46.956983 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 13:53:46.963939 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 13:53:46.967499 0 10 12 | B1->B0 | 2626 2d2d | 0 0 | (1 1) (1 1)
4440 13:53:46.971300 0 10 16 | B1->B0 | 4141 4040 | 0 0 | (0 0) (0 0)
4441 13:53:46.977152 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 13:53:46.980473 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 13:53:46.984160 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 13:53:46.990253 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 13:53:46.993452 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 13:53:46.997750 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 13:53:47.004422 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4448 13:53:47.007088 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4449 13:53:47.010443 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 13:53:47.017266 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 13:53:47.020013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 13:53:47.023579 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 13:53:47.030189 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 13:53:47.033274 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:53:47.037268 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:53:47.043178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:53:47.046695 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:53:47.050314 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:53:47.053154 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:53:47.060072 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:53:47.063646 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:53:47.067071 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 13:53:47.073261 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4464 13:53:47.076671 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4465 13:53:47.079976 Total UI for P1: 0, mck2ui 16
4466 13:53:47.083344 best dqsien dly found for B1: ( 0, 13, 12)
4467 13:53:47.086526 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 13:53:47.090565 Total UI for P1: 0, mck2ui 16
4469 13:53:47.093145 best dqsien dly found for B0: ( 0, 13, 14)
4470 13:53:47.097235 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4471 13:53:47.099948 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4472 13:53:47.103800
4473 13:53:47.107622 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4474 13:53:47.110607 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4475 13:53:47.113148 [Gating] SW calibration Done
4476 13:53:47.113235 ==
4477 13:53:47.116775 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 13:53:47.120344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 13:53:47.120439 ==
4480 13:53:47.120506 RX Vref Scan: 0
4481 13:53:47.120567
4482 13:53:47.123305 RX Vref 0 -> 0, step: 1
4483 13:53:47.123394
4484 13:53:47.126839 RX Delay -230 -> 252, step: 16
4485 13:53:47.130187 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4486 13:53:47.133744 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4487 13:53:47.139949 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4488 13:53:47.143388 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4489 13:53:47.146663 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4490 13:53:47.149871 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4491 13:53:47.156805 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4492 13:53:47.161188 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4493 13:53:47.163402 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4494 13:53:47.166856 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4495 13:53:47.170283 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4496 13:53:47.176832 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4497 13:53:47.180380 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4498 13:53:47.183062 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4499 13:53:47.186805 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4500 13:53:47.193301 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4501 13:53:47.193427 ==
4502 13:53:47.196632 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 13:53:47.200570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 13:53:47.200681 ==
4505 13:53:47.200748 DQS Delay:
4506 13:53:47.203716 DQS0 = 0, DQS1 = 0
4507 13:53:47.203802 DQM Delay:
4508 13:53:47.206705 DQM0 = 44, DQM1 = 34
4509 13:53:47.206791 DQ Delay:
4510 13:53:47.209882 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4511 13:53:47.213368 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4512 13:53:47.216575 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4513 13:53:47.219836 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4514 13:53:47.219956
4515 13:53:47.220078
4516 13:53:47.220139 ==
4517 13:53:47.223425 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 13:53:47.226541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 13:53:47.226654 ==
4520 13:53:47.226724
4521 13:53:47.230078
4522 13:53:47.230252 TX Vref Scan disable
4523 13:53:47.233264 == TX Byte 0 ==
4524 13:53:47.237462 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4525 13:53:47.240261 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4526 13:53:47.243421 == TX Byte 1 ==
4527 13:53:47.247017 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4528 13:53:47.249826 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4529 13:53:47.249930 ==
4530 13:53:47.253804 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 13:53:47.260211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 13:53:47.260365 ==
4533 13:53:47.260436
4534 13:53:47.260528
4535 13:53:47.260616 TX Vref Scan disable
4536 13:53:47.264428 == TX Byte 0 ==
4537 13:53:47.268002 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4538 13:53:47.271203 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4539 13:53:47.274317 == TX Byte 1 ==
4540 13:53:47.278277 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4541 13:53:47.282603 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4542 13:53:47.284265
4543 13:53:47.284360 [DATLAT]
4544 13:53:47.284427 Freq=600, CH1 RK0
4545 13:53:47.284488
4546 13:53:47.288244 DATLAT Default: 0x9
4547 13:53:47.288356 0, 0xFFFF, sum = 0
4548 13:53:47.290979 1, 0xFFFF, sum = 0
4549 13:53:47.291080 2, 0xFFFF, sum = 0
4550 13:53:47.294306 3, 0xFFFF, sum = 0
4551 13:53:47.294479 4, 0xFFFF, sum = 0
4552 13:53:47.298154 5, 0xFFFF, sum = 0
4553 13:53:47.298270 6, 0xFFFF, sum = 0
4554 13:53:47.301078 7, 0xFFFF, sum = 0
4555 13:53:47.301185 8, 0x0, sum = 1
4556 13:53:47.304580 9, 0x0, sum = 2
4557 13:53:47.304688 10, 0x0, sum = 3
4558 13:53:47.308168 11, 0x0, sum = 4
4559 13:53:47.308277 best_step = 9
4560 13:53:47.308346
4561 13:53:47.308407 ==
4562 13:53:47.311941 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 13:53:47.318225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 13:53:47.318368 ==
4565 13:53:47.318481 RX Vref Scan: 1
4566 13:53:47.318544
4567 13:53:47.321668 RX Vref 0 -> 0, step: 1
4568 13:53:47.321786
4569 13:53:47.324301 RX Delay -195 -> 252, step: 8
4570 13:53:47.324386
4571 13:53:47.328129 Set Vref, RX VrefLevel [Byte0]: 57
4572 13:53:47.330921 [Byte1]: 53
4573 13:53:47.331013
4574 13:53:47.335187 Final RX Vref Byte 0 = 57 to rank0
4575 13:53:47.337832 Final RX Vref Byte 1 = 53 to rank0
4576 13:53:47.341409 Final RX Vref Byte 0 = 57 to rank1
4577 13:53:47.344413 Final RX Vref Byte 1 = 53 to rank1==
4578 13:53:47.348000 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 13:53:47.351224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 13:53:47.351314 ==
4581 13:53:47.354570 DQS Delay:
4582 13:53:47.354656 DQS0 = 0, DQS1 = 0
4583 13:53:47.354722 DQM Delay:
4584 13:53:47.358277 DQM0 = 40, DQM1 = 33
4585 13:53:47.358409 DQ Delay:
4586 13:53:47.361528 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4587 13:53:47.364466 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4588 13:53:47.368228 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4589 13:53:47.371320 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4590 13:53:47.371416
4591 13:53:47.371481
4592 13:53:47.381324 [DQSOSCAuto] RK0, (LSB)MR18= 0x4208, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4593 13:53:47.381462 CH1 RK0: MR19=808, MR18=4208
4594 13:53:47.387696 CH1_RK0: MR19=0x808, MR18=0x4208, DQSOSC=397, MR23=63, INC=166, DEC=110
4595 13:53:47.387803
4596 13:53:47.391428 ----->DramcWriteLeveling(PI) begin...
4597 13:53:47.391517 ==
4598 13:53:47.394764 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 13:53:47.401486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 13:53:47.401602 ==
4601 13:53:47.404557 Write leveling (Byte 0): 30 => 30
4602 13:53:47.408203 Write leveling (Byte 1): 30 => 30
4603 13:53:47.408318 DramcWriteLeveling(PI) end<-----
4604 13:53:47.408385
4605 13:53:47.411330 ==
4606 13:53:47.411428 Dram Type= 6, Freq= 0, CH_1, rank 1
4607 13:53:47.418245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 13:53:47.418422 ==
4609 13:53:47.421870 [Gating] SW mode calibration
4610 13:53:47.428405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4611 13:53:47.431455 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4612 13:53:47.438154 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4613 13:53:47.441728 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 13:53:47.444818 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4615 13:53:47.451390 0 9 12 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 1)
4616 13:53:47.454939 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4617 13:53:47.458497 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4618 13:53:47.464763 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 13:53:47.467803 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 13:53:47.471510 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4621 13:53:47.474547 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4622 13:53:47.481297 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4623 13:53:47.484345 0 10 12 | B1->B0 | 3232 3d3d | 0 0 | (0 0) (0 0)
4624 13:53:47.487817 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4625 13:53:47.494610 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 13:53:47.498179 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 13:53:47.501649 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 13:53:47.508192 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 13:53:47.511237 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 13:53:47.514499 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 13:53:47.521551 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4632 13:53:47.525056 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 13:53:47.528189 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 13:53:47.535442 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 13:53:47.538336 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 13:53:47.541642 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 13:53:47.548286 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 13:53:47.551646 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 13:53:47.554781 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:53:47.557866 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:53:47.565337 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:53:47.568670 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:53:47.571675 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 13:53:47.578118 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 13:53:47.581653 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 13:53:47.585301 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 13:53:47.591742 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 13:53:47.594910 Total UI for P1: 0, mck2ui 16
4649 13:53:47.598349 best dqsien dly found for B0: ( 0, 13, 10)
4650 13:53:47.598481 Total UI for P1: 0, mck2ui 16
4651 13:53:47.605074 best dqsien dly found for B1: ( 0, 13, 10)
4652 13:53:47.608214 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4653 13:53:47.612037 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4654 13:53:47.612145
4655 13:53:47.615065 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4656 13:53:47.618067 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4657 13:53:47.621699 [Gating] SW calibration Done
4658 13:53:47.621801 ==
4659 13:53:47.624991 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 13:53:47.628232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 13:53:47.628393 ==
4662 13:53:47.632164 RX Vref Scan: 0
4663 13:53:47.632259
4664 13:53:47.632326 RX Vref 0 -> 0, step: 1
4665 13:53:47.632388
4666 13:53:47.635259 RX Delay -230 -> 252, step: 16
4667 13:53:47.641232 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4668 13:53:47.644667 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4669 13:53:47.647935 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4670 13:53:47.651272 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4671 13:53:47.655078 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4672 13:53:47.661148 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4673 13:53:47.665193 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4674 13:53:47.667813 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4675 13:53:47.671604 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4676 13:53:47.677940 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4677 13:53:47.682009 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4678 13:53:47.684496 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4679 13:53:47.688110 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4680 13:53:47.691098 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4681 13:53:47.697955 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4682 13:53:47.701791 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4683 13:53:47.701916 ==
4684 13:53:47.704693 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 13:53:47.708095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 13:53:47.708193 ==
4687 13:53:47.711276 DQS Delay:
4688 13:53:47.711381 DQS0 = 0, DQS1 = 0
4689 13:53:47.714717 DQM Delay:
4690 13:53:47.714807 DQM0 = 40, DQM1 = 36
4691 13:53:47.714873 DQ Delay:
4692 13:53:47.718351 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4693 13:53:47.721517 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4694 13:53:47.724900 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4695 13:53:47.728197 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4696 13:53:47.728297
4697 13:53:47.728380
4698 13:53:47.728483 ==
4699 13:53:47.731385 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 13:53:47.738001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 13:53:47.738126 ==
4702 13:53:47.738197
4703 13:53:47.738257
4704 13:53:47.738314 TX Vref Scan disable
4705 13:53:47.741963 == TX Byte 0 ==
4706 13:53:47.746017 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4707 13:53:47.748206 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4708 13:53:47.751924 == TX Byte 1 ==
4709 13:53:47.755133 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4710 13:53:47.758670 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4711 13:53:47.762057 ==
4712 13:53:47.762162 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 13:53:47.768447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 13:53:47.768576 ==
4715 13:53:47.768645
4716 13:53:47.768736
4717 13:53:47.771772 TX Vref Scan disable
4718 13:53:47.771864 == TX Byte 0 ==
4719 13:53:47.778899 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4720 13:53:47.782216 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4721 13:53:47.782324 == TX Byte 1 ==
4722 13:53:47.788654 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4723 13:53:47.792004 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4724 13:53:47.792109
4725 13:53:47.792177 [DATLAT]
4726 13:53:47.795762 Freq=600, CH1 RK1
4727 13:53:47.795854
4728 13:53:47.795919 DATLAT Default: 0x9
4729 13:53:47.798522 0, 0xFFFF, sum = 0
4730 13:53:47.798611 1, 0xFFFF, sum = 0
4731 13:53:47.802051 2, 0xFFFF, sum = 0
4732 13:53:47.802150 3, 0xFFFF, sum = 0
4733 13:53:47.805093 4, 0xFFFF, sum = 0
4734 13:53:47.805183 5, 0xFFFF, sum = 0
4735 13:53:47.808600 6, 0xFFFF, sum = 0
4736 13:53:47.811960 7, 0xFFFF, sum = 0
4737 13:53:47.812087 8, 0x0, sum = 1
4738 13:53:47.812155 9, 0x0, sum = 2
4739 13:53:47.815437 10, 0x0, sum = 3
4740 13:53:47.815551 11, 0x0, sum = 4
4741 13:53:47.818986 best_step = 9
4742 13:53:47.819094
4743 13:53:47.819161 ==
4744 13:53:47.821541 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 13:53:47.825405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 13:53:47.825525 ==
4747 13:53:47.828676 RX Vref Scan: 0
4748 13:53:47.828783
4749 13:53:47.828850 RX Vref 0 -> 0, step: 1
4750 13:53:47.828912
4751 13:53:47.831672 RX Delay -179 -> 252, step: 8
4752 13:53:47.838622 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4753 13:53:47.841920 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4754 13:53:47.846155 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4755 13:53:47.848759 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4756 13:53:47.855517 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4757 13:53:47.858695 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4758 13:53:47.861964 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4759 13:53:47.865458 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4760 13:53:47.869724 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4761 13:53:47.875694 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4762 13:53:47.879426 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4763 13:53:47.882265 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4764 13:53:47.885624 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4765 13:53:47.892379 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4766 13:53:47.895872 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4767 13:53:47.899438 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4768 13:53:47.899577 ==
4769 13:53:47.902501 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 13:53:47.905682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 13:53:47.905776 ==
4772 13:53:47.909443 DQS Delay:
4773 13:53:47.909540 DQS0 = 0, DQS1 = 0
4774 13:53:47.912333 DQM Delay:
4775 13:53:47.912419 DQM0 = 38, DQM1 = 32
4776 13:53:47.912485 DQ Delay:
4777 13:53:47.915756 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4778 13:53:47.919264 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4779 13:53:47.922691 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4780 13:53:47.925627 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4781 13:53:47.925717
4782 13:53:47.925782
4783 13:53:47.936319 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d4c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4784 13:53:47.939484 CH1 RK1: MR19=808, MR18=3D4C
4785 13:53:47.942711 CH1_RK1: MR19=0x808, MR18=0x3D4C, DQSOSC=395, MR23=63, INC=168, DEC=112
4786 13:53:47.946012 [RxdqsGatingPostProcess] freq 600
4787 13:53:47.952372 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4788 13:53:47.955811 Pre-setting of DQS Precalculation
4789 13:53:47.959074 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4790 13:53:47.966562 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4791 13:53:47.975613 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4792 13:53:47.975748
4793 13:53:47.975817
4794 13:53:47.979099 [Calibration Summary] 1200 Mbps
4795 13:53:47.979185 CH 0, Rank 0
4796 13:53:47.982824 SW Impedance : PASS
4797 13:53:47.982911 DUTY Scan : NO K
4798 13:53:47.986161 ZQ Calibration : PASS
4799 13:53:47.989264 Jitter Meter : NO K
4800 13:53:47.989351 CBT Training : PASS
4801 13:53:47.992385 Write leveling : PASS
4802 13:53:47.992473 RX DQS gating : PASS
4803 13:53:47.996024 RX DQ/DQS(RDDQC) : PASS
4804 13:53:47.999397 TX DQ/DQS : PASS
4805 13:53:47.999494 RX DATLAT : PASS
4806 13:53:48.002564 RX DQ/DQS(Engine): PASS
4807 13:53:48.006640 TX OE : NO K
4808 13:53:48.006730 All Pass.
4809 13:53:48.006796
4810 13:53:48.006857 CH 0, Rank 1
4811 13:53:48.009351 SW Impedance : PASS
4812 13:53:48.012658 DUTY Scan : NO K
4813 13:53:48.012746 ZQ Calibration : PASS
4814 13:53:48.016172 Jitter Meter : NO K
4815 13:53:48.020504 CBT Training : PASS
4816 13:53:48.020600 Write leveling : PASS
4817 13:53:48.022528 RX DQS gating : PASS
4818 13:53:48.022646 RX DQ/DQS(RDDQC) : PASS
4819 13:53:48.026052 TX DQ/DQS : PASS
4820 13:53:48.029461 RX DATLAT : PASS
4821 13:53:48.029548 RX DQ/DQS(Engine): PASS
4822 13:53:48.032686 TX OE : NO K
4823 13:53:48.032773 All Pass.
4824 13:53:48.032838
4825 13:53:48.036509 CH 1, Rank 0
4826 13:53:48.036607 SW Impedance : PASS
4827 13:53:48.039769 DUTY Scan : NO K
4828 13:53:48.043298 ZQ Calibration : PASS
4829 13:53:48.043387 Jitter Meter : NO K
4830 13:53:48.046749 CBT Training : PASS
4831 13:53:48.049198 Write leveling : PASS
4832 13:53:48.049286 RX DQS gating : PASS
4833 13:53:48.052850 RX DQ/DQS(RDDQC) : PASS
4834 13:53:48.056066 TX DQ/DQS : PASS
4835 13:53:48.056154 RX DATLAT : PASS
4836 13:53:48.059854 RX DQ/DQS(Engine): PASS
4837 13:53:48.062832 TX OE : NO K
4838 13:53:48.062919 All Pass.
4839 13:53:48.062985
4840 13:53:48.063046 CH 1, Rank 1
4841 13:53:48.066213 SW Impedance : PASS
4842 13:53:48.066297 DUTY Scan : NO K
4843 13:53:48.069514 ZQ Calibration : PASS
4844 13:53:48.072842 Jitter Meter : NO K
4845 13:53:48.072931 CBT Training : PASS
4846 13:53:48.076366 Write leveling : PASS
4847 13:53:48.079386 RX DQS gating : PASS
4848 13:53:48.079477 RX DQ/DQS(RDDQC) : PASS
4849 13:53:48.083084 TX DQ/DQS : PASS
4850 13:53:48.086925 RX DATLAT : PASS
4851 13:53:48.087018 RX DQ/DQS(Engine): PASS
4852 13:53:48.090248 TX OE : NO K
4853 13:53:48.090359 All Pass.
4854 13:53:48.090449
4855 13:53:48.093461 DramC Write-DBI off
4856 13:53:48.097092 PER_BANK_REFRESH: Hybrid Mode
4857 13:53:48.097187 TX_TRACKING: ON
4858 13:53:48.106496 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4859 13:53:48.109850 [FAST_K] Save calibration result to emmc
4860 13:53:48.113459 dramc_set_vcore_voltage set vcore to 662500
4861 13:53:48.113562 Read voltage for 933, 3
4862 13:53:48.116758 Vio18 = 0
4863 13:53:48.116846 Vcore = 662500
4864 13:53:48.116912 Vdram = 0
4865 13:53:48.120594 Vddq = 0
4866 13:53:48.120684 Vmddr = 0
4867 13:53:48.126346 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4868 13:53:48.130406 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4869 13:53:48.132923 MEM_TYPE=3, freq_sel=17
4870 13:53:48.137403 sv_algorithm_assistance_LP4_1600
4871 13:53:48.140262 ============ PULL DRAM RESETB DOWN ============
4872 13:53:48.143073 ========== PULL DRAM RESETB DOWN end =========
4873 13:53:48.150066 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4874 13:53:48.153676 ===================================
4875 13:53:48.153782 LPDDR4 DRAM CONFIGURATION
4876 13:53:48.156247 ===================================
4877 13:53:48.159704 EX_ROW_EN[0] = 0x0
4878 13:53:48.159796 EX_ROW_EN[1] = 0x0
4879 13:53:48.163392 LP4Y_EN = 0x0
4880 13:53:48.166673 WORK_FSP = 0x0
4881 13:53:48.166782 WL = 0x3
4882 13:53:48.169733 RL = 0x3
4883 13:53:48.169821 BL = 0x2
4884 13:53:48.173050 RPST = 0x0
4885 13:53:48.173141 RD_PRE = 0x0
4886 13:53:48.176459 WR_PRE = 0x1
4887 13:53:48.176545 WR_PST = 0x0
4888 13:53:48.180287 DBI_WR = 0x0
4889 13:53:48.180376 DBI_RD = 0x0
4890 13:53:48.183284 OTF = 0x1
4891 13:53:48.186751 ===================================
4892 13:53:48.190096 ===================================
4893 13:53:48.190196 ANA top config
4894 13:53:48.194575 ===================================
4895 13:53:48.196717 DLL_ASYNC_EN = 0
4896 13:53:48.200305 ALL_SLAVE_EN = 1
4897 13:53:48.200406 NEW_RANK_MODE = 1
4898 13:53:48.203262 DLL_IDLE_MODE = 1
4899 13:53:48.207412 LP45_APHY_COMB_EN = 1
4900 13:53:48.210246 TX_ODT_DIS = 1
4901 13:53:48.210336 NEW_8X_MODE = 1
4902 13:53:48.213533 ===================================
4903 13:53:48.216629 ===================================
4904 13:53:48.220157 data_rate = 1866
4905 13:53:48.223876 CKR = 1
4906 13:53:48.226410 DQ_P2S_RATIO = 8
4907 13:53:48.230010 ===================================
4908 13:53:48.233629 CA_P2S_RATIO = 8
4909 13:53:48.236935 DQ_CA_OPEN = 0
4910 13:53:48.237038 DQ_SEMI_OPEN = 0
4911 13:53:48.240223 CA_SEMI_OPEN = 0
4912 13:53:48.243260 CA_FULL_RATE = 0
4913 13:53:48.246848 DQ_CKDIV4_EN = 1
4914 13:53:48.249895 CA_CKDIV4_EN = 1
4915 13:53:48.249998 CA_PREDIV_EN = 0
4916 13:53:48.253424 PH8_DLY = 0
4917 13:53:48.257649 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4918 13:53:48.260422 DQ_AAMCK_DIV = 4
4919 13:53:48.263796 CA_AAMCK_DIV = 4
4920 13:53:48.267916 CA_ADMCK_DIV = 4
4921 13:53:48.268016 DQ_TRACK_CA_EN = 0
4922 13:53:48.270089 CA_PICK = 933
4923 13:53:48.273420 CA_MCKIO = 933
4924 13:53:48.277431 MCKIO_SEMI = 0
4925 13:53:48.281086 PLL_FREQ = 3732
4926 13:53:48.283356 DQ_UI_PI_RATIO = 32
4927 13:53:48.286721 CA_UI_PI_RATIO = 0
4928 13:53:48.290362 ===================================
4929 13:53:48.294029 ===================================
4930 13:53:48.294181 memory_type:LPDDR4
4931 13:53:48.297112 GP_NUM : 10
4932 13:53:48.300301 SRAM_EN : 1
4933 13:53:48.300479 MD32_EN : 0
4934 13:53:48.303346 ===================================
4935 13:53:48.306895 [ANA_INIT] >>>>>>>>>>>>>>
4936 13:53:48.311119 <<<<<< [CONFIGURE PHASE]: ANA_TX
4937 13:53:48.313305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4938 13:53:48.316901 ===================================
4939 13:53:48.320180 data_rate = 1866,PCW = 0X8f00
4940 13:53:48.320277 ===================================
4941 13:53:48.327336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4942 13:53:48.330682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 13:53:48.337016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4944 13:53:48.340789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4945 13:53:48.343641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4946 13:53:48.347302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4947 13:53:48.350733 [ANA_INIT] flow start
4948 13:53:48.353509 [ANA_INIT] PLL >>>>>>>>
4949 13:53:48.353604 [ANA_INIT] PLL <<<<<<<<
4950 13:53:48.357801 [ANA_INIT] MIDPI >>>>>>>>
4951 13:53:48.360407 [ANA_INIT] MIDPI <<<<<<<<
4952 13:53:48.360499 [ANA_INIT] DLL >>>>>>>>
4953 13:53:48.363543 [ANA_INIT] flow end
4954 13:53:48.367504 ============ LP4 DIFF to SE enter ============
4955 13:53:48.370270 ============ LP4 DIFF to SE exit ============
4956 13:53:48.373864 [ANA_INIT] <<<<<<<<<<<<<
4957 13:53:48.377308 [Flow] Enable top DCM control >>>>>
4958 13:53:48.380417 [Flow] Enable top DCM control <<<<<
4959 13:53:48.384525 Enable DLL master slave shuffle
4960 13:53:48.390664 ==============================================================
4961 13:53:48.390790 Gating Mode config
4962 13:53:48.397689 ==============================================================
4963 13:53:48.397816 Config description:
4964 13:53:48.407614 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4965 13:53:48.414422 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4966 13:53:48.420587 SELPH_MODE 0: By rank 1: By Phase
4967 13:53:48.423829 ==============================================================
4968 13:53:48.427869 GAT_TRACK_EN = 1
4969 13:53:48.430844 RX_GATING_MODE = 2
4970 13:53:48.434107 RX_GATING_TRACK_MODE = 2
4971 13:53:48.437402 SELPH_MODE = 1
4972 13:53:48.440769 PICG_EARLY_EN = 1
4973 13:53:48.443963 VALID_LAT_VALUE = 1
4974 13:53:48.447234 ==============================================================
4975 13:53:48.450675 Enter into Gating configuration >>>>
4976 13:53:48.454083 Exit from Gating configuration <<<<
4977 13:53:48.457484 Enter into DVFS_PRE_config >>>>>
4978 13:53:48.470892 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4979 13:53:48.471043 Exit from DVFS_PRE_config <<<<<
4980 13:53:48.474417 Enter into PICG configuration >>>>
4981 13:53:48.477174 Exit from PICG configuration <<<<
4982 13:53:48.480390 [RX_INPUT] configuration >>>>>
4983 13:53:48.484123 [RX_INPUT] configuration <<<<<
4984 13:53:48.490601 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4985 13:53:48.493852 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4986 13:53:48.500752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 13:53:48.507608 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 13:53:48.514109 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 13:53:48.521008 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 13:53:48.524408 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4991 13:53:48.527320 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4992 13:53:48.530706 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4993 13:53:48.538061 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4994 13:53:48.541001 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4995 13:53:48.544269 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 13:53:48.547679 ===================================
4997 13:53:48.551272 LPDDR4 DRAM CONFIGURATION
4998 13:53:48.554549 ===================================
4999 13:53:48.554658 EX_ROW_EN[0] = 0x0
5000 13:53:48.558084 EX_ROW_EN[1] = 0x0
5001 13:53:48.558177 LP4Y_EN = 0x0
5002 13:53:48.560917 WORK_FSP = 0x0
5003 13:53:48.561006 WL = 0x3
5004 13:53:48.564802 RL = 0x3
5005 13:53:48.567859 BL = 0x2
5006 13:53:48.567950 RPST = 0x0
5007 13:53:48.571085 RD_PRE = 0x0
5008 13:53:48.571176 WR_PRE = 0x1
5009 13:53:48.574365 WR_PST = 0x0
5010 13:53:48.574480 DBI_WR = 0x0
5011 13:53:48.577788 DBI_RD = 0x0
5012 13:53:48.577876 OTF = 0x1
5013 13:53:48.581087 ===================================
5014 13:53:48.584571 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5015 13:53:48.587722 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5016 13:53:48.595529 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5017 13:53:48.598612 ===================================
5018 13:53:48.601754 LPDDR4 DRAM CONFIGURATION
5019 13:53:48.604526 ===================================
5020 13:53:48.604630 EX_ROW_EN[0] = 0x10
5021 13:53:48.607881 EX_ROW_EN[1] = 0x0
5022 13:53:48.607966 LP4Y_EN = 0x0
5023 13:53:48.610987 WORK_FSP = 0x0
5024 13:53:48.611073 WL = 0x3
5025 13:53:48.615042 RL = 0x3
5026 13:53:48.615144 BL = 0x2
5027 13:53:48.618006 RPST = 0x0
5028 13:53:48.618088 RD_PRE = 0x0
5029 13:53:48.621461 WR_PRE = 0x1
5030 13:53:48.621545 WR_PST = 0x0
5031 13:53:48.624253 DBI_WR = 0x0
5032 13:53:48.624337 DBI_RD = 0x0
5033 13:53:48.627785 OTF = 0x1
5034 13:53:48.631438 ===================================
5035 13:53:48.637584 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5036 13:53:48.641415 nWR fixed to 30
5037 13:53:48.644558 [ModeRegInit_LP4] CH0 RK0
5038 13:53:48.644646 [ModeRegInit_LP4] CH0 RK1
5039 13:53:48.648246 [ModeRegInit_LP4] CH1 RK0
5040 13:53:48.651241 [ModeRegInit_LP4] CH1 RK1
5041 13:53:48.651329 match AC timing 9
5042 13:53:48.657367 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5043 13:53:48.661247 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5044 13:53:48.664388 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5045 13:53:48.671420 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5046 13:53:48.674250 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5047 13:53:48.674349 ==
5048 13:53:48.677456 Dram Type= 6, Freq= 0, CH_0, rank 0
5049 13:53:48.681744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5050 13:53:48.681840 ==
5051 13:53:48.687548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5052 13:53:48.694806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5053 13:53:48.697633 [CA 0] Center 38 (8~69) winsize 62
5054 13:53:48.701171 [CA 1] Center 38 (8~69) winsize 62
5055 13:53:48.705228 [CA 2] Center 35 (5~66) winsize 62
5056 13:53:48.708121 [CA 3] Center 35 (4~66) winsize 63
5057 13:53:48.711450 [CA 4] Center 34 (4~65) winsize 62
5058 13:53:48.714784 [CA 5] Center 33 (3~64) winsize 62
5059 13:53:48.714878
5060 13:53:48.718210 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5061 13:53:48.718320
5062 13:53:48.721017 [CATrainingPosCal] consider 1 rank data
5063 13:53:48.724516 u2DelayCellTimex100 = 270/100 ps
5064 13:53:48.727686 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5065 13:53:48.731128 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5066 13:53:48.734777 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5067 13:53:48.737763 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5068 13:53:48.741462 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5069 13:53:48.744995 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5070 13:53:48.745085
5071 13:53:48.748359 CA PerBit enable=1, Macro0, CA PI delay=33
5072 13:53:48.748444
5073 13:53:48.752256 [CBTSetCACLKResult] CA Dly = 33
5074 13:53:48.754602 CS Dly: 6 (0~37)
5075 13:53:48.754688 ==
5076 13:53:48.757674 Dram Type= 6, Freq= 0, CH_0, rank 1
5077 13:53:48.761313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 13:53:48.761401 ==
5079 13:53:48.768038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 13:53:48.774914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5081 13:53:48.778686 [CA 0] Center 38 (7~69) winsize 63
5082 13:53:48.781096 [CA 1] Center 38 (7~69) winsize 63
5083 13:53:48.784927 [CA 2] Center 35 (5~66) winsize 62
5084 13:53:48.787838 [CA 3] Center 35 (5~66) winsize 62
5085 13:53:48.790975 [CA 4] Center 34 (3~65) winsize 63
5086 13:53:48.794992 [CA 5] Center 33 (3~64) winsize 62
5087 13:53:48.795091
5088 13:53:48.797766 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5089 13:53:48.797875
5090 13:53:48.800926 [CATrainingPosCal] consider 2 rank data
5091 13:53:48.804798 u2DelayCellTimex100 = 270/100 ps
5092 13:53:48.807565 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5093 13:53:48.810852 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5094 13:53:48.814599 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5095 13:53:48.817604 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5096 13:53:48.820880 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5097 13:53:48.825046 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5098 13:53:48.825145
5099 13:53:48.831197 CA PerBit enable=1, Macro0, CA PI delay=33
5100 13:53:48.831309
5101 13:53:48.831374 [CBTSetCACLKResult] CA Dly = 33
5102 13:53:48.834490 CS Dly: 7 (0~39)
5103 13:53:48.834579
5104 13:53:48.837677 ----->DramcWriteLeveling(PI) begin...
5105 13:53:48.837769 ==
5106 13:53:48.841027 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 13:53:48.844718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 13:53:48.844808 ==
5109 13:53:48.847464 Write leveling (Byte 0): 30 => 30
5110 13:53:48.851061 Write leveling (Byte 1): 28 => 28
5111 13:53:48.854216 DramcWriteLeveling(PI) end<-----
5112 13:53:48.854308
5113 13:53:48.854373 ==
5114 13:53:48.857372 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 13:53:48.861233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 13:53:48.864779 ==
5117 13:53:48.864870 [Gating] SW mode calibration
5118 13:53:48.871074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5119 13:53:48.877959 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5120 13:53:48.881426 0 14 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5121 13:53:48.887548 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5122 13:53:48.891054 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 13:53:48.894517 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 13:53:48.901406 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 13:53:48.904158 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 13:53:48.907693 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 13:53:48.914538 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5128 13:53:48.917661 0 15 0 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (0 1)
5129 13:53:48.921262 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 13:53:48.927600 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 13:53:48.930831 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 13:53:48.934421 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 13:53:48.937748 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 13:53:48.944560 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 13:53:48.947553 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5136 13:53:48.950694 1 0 0 | B1->B0 | 2c2c 3d3d | 1 0 | (0 0) (0 0)
5137 13:53:48.958117 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 13:53:48.960994 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 13:53:48.964544 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 13:53:48.970878 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 13:53:48.974840 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 13:53:48.977630 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 13:53:48.984067 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5144 13:53:48.987643 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5145 13:53:48.990779 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 13:53:48.997363 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 13:53:49.000502 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 13:53:49.004579 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 13:53:49.010741 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 13:53:49.013813 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 13:53:49.017428 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 13:53:49.024706 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 13:53:49.027542 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:53:49.031176 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:53:49.037858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:53:49.041546 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:53:49.044399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:53:49.047435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:53:49.054234 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5160 13:53:49.057334 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5161 13:53:49.060624 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 13:53:49.063836 Total UI for P1: 0, mck2ui 16
5163 13:53:49.067546 best dqsien dly found for B0: ( 1, 2, 30)
5164 13:53:49.070867 Total UI for P1: 0, mck2ui 16
5165 13:53:49.074883 best dqsien dly found for B1: ( 1, 3, 0)
5166 13:53:49.077372 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5167 13:53:49.080624 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5168 13:53:49.080747
5169 13:53:49.087951 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5170 13:53:49.091940 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5171 13:53:49.092069 [Gating] SW calibration Done
5172 13:53:49.094930 ==
5173 13:53:49.097736 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 13:53:49.100519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 13:53:49.100645 ==
5176 13:53:49.100744 RX Vref Scan: 0
5177 13:53:49.100837
5178 13:53:49.104095 RX Vref 0 -> 0, step: 1
5179 13:53:49.104216
5180 13:53:49.107261 RX Delay -80 -> 252, step: 8
5181 13:53:49.111277 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5182 13:53:49.113962 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5183 13:53:49.117799 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5184 13:53:49.121403 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5185 13:53:49.128015 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5186 13:53:49.130615 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5187 13:53:49.134092 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5188 13:53:49.137613 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5189 13:53:49.141584 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5190 13:53:49.147866 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5191 13:53:49.150935 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5192 13:53:49.154105 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5193 13:53:49.158076 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5194 13:53:49.161312 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5195 13:53:49.165132 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5196 13:53:49.170890 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5197 13:53:49.171062 ==
5198 13:53:49.173882 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 13:53:49.177385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 13:53:49.177537 ==
5201 13:53:49.177639 DQS Delay:
5202 13:53:49.180973 DQS0 = 0, DQS1 = 0
5203 13:53:49.181126 DQM Delay:
5204 13:53:49.184285 DQM0 = 99, DQM1 = 88
5205 13:53:49.184443 DQ Delay:
5206 13:53:49.187680 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5207 13:53:49.190761 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5208 13:53:49.194321 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5209 13:53:49.197532 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5210 13:53:49.197673
5211 13:53:49.197771
5212 13:53:49.197860 ==
5213 13:53:49.200936 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 13:53:49.204543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 13:53:49.204675 ==
5216 13:53:49.207257
5217 13:53:49.207371
5218 13:53:49.207466 TX Vref Scan disable
5219 13:53:49.211027 == TX Byte 0 ==
5220 13:53:49.214054 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5221 13:53:49.217843 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5222 13:53:49.221291 == TX Byte 1 ==
5223 13:53:49.224674 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5224 13:53:49.228404 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5225 13:53:49.228537 ==
5226 13:53:49.231419 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 13:53:49.237551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 13:53:49.237722 ==
5229 13:53:49.237825
5230 13:53:49.237917
5231 13:53:49.238007 TX Vref Scan disable
5232 13:53:49.242232 == TX Byte 0 ==
5233 13:53:49.245390 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5234 13:53:49.252088 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5235 13:53:49.252265 == TX Byte 1 ==
5236 13:53:49.255079 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5237 13:53:49.258455 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5238 13:53:49.262095
5239 13:53:49.262232 [DATLAT]
5240 13:53:49.262330 Freq=933, CH0 RK0
5241 13:53:49.262464
5242 13:53:49.265068 DATLAT Default: 0xd
5243 13:53:49.265179 0, 0xFFFF, sum = 0
5244 13:53:49.268935 1, 0xFFFF, sum = 0
5245 13:53:49.269058 2, 0xFFFF, sum = 0
5246 13:53:49.271690 3, 0xFFFF, sum = 0
5247 13:53:49.271800 4, 0xFFFF, sum = 0
5248 13:53:49.274933 5, 0xFFFF, sum = 0
5249 13:53:49.275052 6, 0xFFFF, sum = 0
5250 13:53:49.278186 7, 0xFFFF, sum = 0
5251 13:53:49.281880 8, 0xFFFF, sum = 0
5252 13:53:49.282007 9, 0xFFFF, sum = 0
5253 13:53:49.282103 10, 0x0, sum = 1
5254 13:53:49.284816 11, 0x0, sum = 2
5255 13:53:49.284925 12, 0x0, sum = 3
5256 13:53:49.289231 13, 0x0, sum = 4
5257 13:53:49.289362 best_step = 11
5258 13:53:49.289493
5259 13:53:49.289581 ==
5260 13:53:49.291847 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 13:53:49.298362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 13:53:49.298554 ==
5263 13:53:49.298648 RX Vref Scan: 1
5264 13:53:49.298735
5265 13:53:49.302573 RX Vref 0 -> 0, step: 1
5266 13:53:49.302698
5267 13:53:49.305220 RX Delay -61 -> 252, step: 4
5268 13:53:49.305327
5269 13:53:49.308268 Set Vref, RX VrefLevel [Byte0]: 53
5270 13:53:49.311837 [Byte1]: 51
5271 13:53:49.311966
5272 13:53:49.315052 Final RX Vref Byte 0 = 53 to rank0
5273 13:53:49.318261 Final RX Vref Byte 1 = 51 to rank0
5274 13:53:49.321468 Final RX Vref Byte 0 = 53 to rank1
5275 13:53:49.325260 Final RX Vref Byte 1 = 51 to rank1==
5276 13:53:49.328218 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 13:53:49.331839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 13:53:49.331982 ==
5279 13:53:49.335353 DQS Delay:
5280 13:53:49.335486 DQS0 = 0, DQS1 = 0
5281 13:53:49.335580 DQM Delay:
5282 13:53:49.338585 DQM0 = 97, DQM1 = 87
5283 13:53:49.338700 DQ Delay:
5284 13:53:49.341926 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5285 13:53:49.345991 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5286 13:53:49.348535 DQ8 =78, DQ9 =78, DQ10 =86, DQ11 =80
5287 13:53:49.352107 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =98
5288 13:53:49.352238
5289 13:53:49.352329
5290 13:53:49.362149 [DQSOSCAuto] RK0, (LSB)MR18= 0x1602, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5291 13:53:49.365641 CH0 RK0: MR19=505, MR18=1602
5292 13:53:49.368731 CH0_RK0: MR19=0x505, MR18=0x1602, DQSOSC=414, MR23=63, INC=63, DEC=42
5293 13:53:49.368852
5294 13:53:49.372377 ----->DramcWriteLeveling(PI) begin...
5295 13:53:49.375971 ==
5296 13:53:49.376097 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 13:53:49.381892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 13:53:49.382014 ==
5299 13:53:49.385046 Write leveling (Byte 0): 33 => 33
5300 13:53:49.388616 Write leveling (Byte 1): 27 => 27
5301 13:53:49.392530 DramcWriteLeveling(PI) end<-----
5302 13:53:49.392647
5303 13:53:49.392740 ==
5304 13:53:49.395308 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 13:53:49.398621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 13:53:49.398739 ==
5307 13:53:49.402125 [Gating] SW mode calibration
5308 13:53:49.409114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5309 13:53:49.411800 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5310 13:53:49.419190 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
5311 13:53:49.421911 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5312 13:53:49.425334 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 13:53:49.431997 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 13:53:49.435557 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 13:53:49.439057 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 13:53:49.445310 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 13:53:49.448903 0 14 28 | B1->B0 | 3030 2a2a | 0 0 | (0 0) (0 0)
5318 13:53:49.452214 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5319 13:53:49.458918 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5320 13:53:49.462532 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 13:53:49.465510 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 13:53:49.468636 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 13:53:49.475991 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 13:53:49.479360 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 13:53:49.482009 0 15 28 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (0 0)
5326 13:53:49.489772 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5327 13:53:49.492397 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 13:53:49.495474 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 13:53:49.502144 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 13:53:49.506222 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 13:53:49.509061 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 13:53:49.516111 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 13:53:49.518744 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5334 13:53:49.522762 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5335 13:53:49.529528 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5336 13:53:49.532930 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 13:53:49.535607 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 13:53:49.539210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 13:53:49.546713 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 13:53:49.549082 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 13:53:49.552393 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 13:53:49.558890 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:53:49.562996 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:53:49.566115 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 13:53:49.572515 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 13:53:49.576277 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 13:53:49.579466 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 13:53:49.586643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 13:53:49.589852 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5350 13:53:49.592664 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5351 13:53:49.599299 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 13:53:49.599422 Total UI for P1: 0, mck2ui 16
5353 13:53:49.605767 best dqsien dly found for B0: ( 1, 2, 30)
5354 13:53:49.605872 Total UI for P1: 0, mck2ui 16
5355 13:53:49.609195 best dqsien dly found for B1: ( 1, 3, 2)
5356 13:53:49.615956 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5357 13:53:49.620026 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5358 13:53:49.620129
5359 13:53:49.622825 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5360 13:53:49.626114 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5361 13:53:49.629605 [Gating] SW calibration Done
5362 13:53:49.629701 ==
5363 13:53:49.632869 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 13:53:49.635956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 13:53:49.636052 ==
5366 13:53:49.639131 RX Vref Scan: 0
5367 13:53:49.639220
5368 13:53:49.639286 RX Vref 0 -> 0, step: 1
5369 13:53:49.639347
5370 13:53:49.642371 RX Delay -80 -> 252, step: 8
5371 13:53:49.645871 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5372 13:53:49.649192 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5373 13:53:49.656533 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5374 13:53:49.659323 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5375 13:53:49.662306 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5376 13:53:49.665795 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5377 13:53:49.669364 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5378 13:53:49.672738 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5379 13:53:49.679349 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5380 13:53:49.682558 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5381 13:53:49.685811 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5382 13:53:49.689366 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5383 13:53:49.693585 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5384 13:53:49.695897 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5385 13:53:49.702688 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5386 13:53:49.705785 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5387 13:53:49.705906 ==
5388 13:53:49.709916 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 13:53:49.712519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 13:53:49.712608 ==
5391 13:53:49.715848 DQS Delay:
5392 13:53:49.715933 DQS0 = 0, DQS1 = 0
5393 13:53:49.715999 DQM Delay:
5394 13:53:49.719374 DQM0 = 96, DQM1 = 87
5395 13:53:49.719461 DQ Delay:
5396 13:53:49.722377 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5397 13:53:49.725843 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5398 13:53:49.729504 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5399 13:53:49.732853 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5400 13:53:49.732947
5401 13:53:49.733013
5402 13:53:49.733073 ==
5403 13:53:49.735867 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 13:53:49.739347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 13:53:49.742742 ==
5406 13:53:49.742830
5407 13:53:49.742895
5408 13:53:49.742955 TX Vref Scan disable
5409 13:53:49.745675 == TX Byte 0 ==
5410 13:53:49.749228 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5411 13:53:49.752971 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5412 13:53:49.756029 == TX Byte 1 ==
5413 13:53:49.759649 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5414 13:53:49.762511 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5415 13:53:49.765998 ==
5416 13:53:49.769203 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 13:53:49.772358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 13:53:49.772447 ==
5419 13:53:49.772513
5420 13:53:49.772573
5421 13:53:49.776041 TX Vref Scan disable
5422 13:53:49.776125 == TX Byte 0 ==
5423 13:53:49.782757 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5424 13:53:49.786720 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5425 13:53:49.786841 == TX Byte 1 ==
5426 13:53:49.792497 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5427 13:53:49.795757 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5428 13:53:49.795848
5429 13:53:49.795914 [DATLAT]
5430 13:53:49.799365 Freq=933, CH0 RK1
5431 13:53:49.799449
5432 13:53:49.799514 DATLAT Default: 0xb
5433 13:53:49.802255 0, 0xFFFF, sum = 0
5434 13:53:49.802366 1, 0xFFFF, sum = 0
5435 13:53:49.805916 2, 0xFFFF, sum = 0
5436 13:53:49.806034 3, 0xFFFF, sum = 0
5437 13:53:49.809201 4, 0xFFFF, sum = 0
5438 13:53:49.809290 5, 0xFFFF, sum = 0
5439 13:53:49.812672 6, 0xFFFF, sum = 0
5440 13:53:49.812760 7, 0xFFFF, sum = 0
5441 13:53:49.816215 8, 0xFFFF, sum = 0
5442 13:53:49.816301 9, 0xFFFF, sum = 0
5443 13:53:49.819548 10, 0x0, sum = 1
5444 13:53:49.819635 11, 0x0, sum = 2
5445 13:53:49.822363 12, 0x0, sum = 3
5446 13:53:49.822499 13, 0x0, sum = 4
5447 13:53:49.826197 best_step = 11
5448 13:53:49.826282
5449 13:53:49.826348 ==
5450 13:53:49.829184 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 13:53:49.832646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 13:53:49.832736 ==
5453 13:53:49.835728 RX Vref Scan: 0
5454 13:53:49.835815
5455 13:53:49.835882 RX Vref 0 -> 0, step: 1
5456 13:53:49.835943
5457 13:53:49.839021 RX Delay -61 -> 252, step: 4
5458 13:53:49.846144 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5459 13:53:49.849959 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5460 13:53:49.853126 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5461 13:53:49.855916 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5462 13:53:49.859604 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5463 13:53:49.862586 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5464 13:53:49.869513 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5465 13:53:49.872979 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5466 13:53:49.876203 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5467 13:53:49.879386 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5468 13:53:49.882990 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5469 13:53:49.889701 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5470 13:53:49.892796 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5471 13:53:49.896153 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5472 13:53:49.899506 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5473 13:53:49.903272 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5474 13:53:49.903371 ==
5475 13:53:49.905962 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 13:53:49.909668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 13:53:49.912752 ==
5478 13:53:49.912839 DQS Delay:
5479 13:53:49.912904 DQS0 = 0, DQS1 = 0
5480 13:53:49.916193 DQM Delay:
5481 13:53:49.916277 DQM0 = 95, DQM1 = 87
5482 13:53:49.920108 DQ Delay:
5483 13:53:49.920197 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5484 13:53:49.923160 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5485 13:53:49.926349 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =78
5486 13:53:49.933089 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =96
5487 13:53:49.933206
5488 13:53:49.933274
5489 13:53:49.939894 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5490 13:53:49.942856 CH0 RK1: MR19=505, MR18=1F0C
5491 13:53:49.949789 CH0_RK1: MR19=0x505, MR18=0x1F0C, DQSOSC=412, MR23=63, INC=63, DEC=42
5492 13:53:49.953189 [RxdqsGatingPostProcess] freq 933
5493 13:53:49.956770 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5494 13:53:49.959467 best DQS0 dly(2T, 0.5T) = (0, 10)
5495 13:53:49.962729 best DQS1 dly(2T, 0.5T) = (0, 11)
5496 13:53:49.966272 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5497 13:53:49.969790 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5498 13:53:49.972885 best DQS0 dly(2T, 0.5T) = (0, 10)
5499 13:53:49.976008 best DQS1 dly(2T, 0.5T) = (0, 11)
5500 13:53:49.979865 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5501 13:53:49.982739 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5502 13:53:49.986692 Pre-setting of DQS Precalculation
5503 13:53:49.989766 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5504 13:53:49.989853 ==
5505 13:53:49.993088 Dram Type= 6, Freq= 0, CH_1, rank 0
5506 13:53:49.996548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 13:53:49.996634 ==
5508 13:53:50.002985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 13:53:50.010002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5510 13:53:50.013469 [CA 0] Center 36 (6~67) winsize 62
5511 13:53:50.016522 [CA 1] Center 36 (6~67) winsize 62
5512 13:53:50.019620 [CA 2] Center 34 (4~64) winsize 61
5513 13:53:50.023491 [CA 3] Center 33 (3~64) winsize 62
5514 13:53:50.026493 [CA 4] Center 34 (4~64) winsize 61
5515 13:53:50.030020 [CA 5] Center 33 (3~64) winsize 62
5516 13:53:50.030108
5517 13:53:50.033834 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5518 13:53:50.033924
5519 13:53:50.036746 [CATrainingPosCal] consider 1 rank data
5520 13:53:50.039438 u2DelayCellTimex100 = 270/100 ps
5521 13:53:50.043119 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5522 13:53:50.046527 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5523 13:53:50.049942 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 13:53:50.053372 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5525 13:53:50.056131 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5526 13:53:50.059686 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5527 13:53:50.063064
5528 13:53:50.066277 CA PerBit enable=1, Macro0, CA PI delay=33
5529 13:53:50.066389
5530 13:53:50.069651 [CBTSetCACLKResult] CA Dly = 33
5531 13:53:50.069735 CS Dly: 4 (0~35)
5532 13:53:50.069800 ==
5533 13:53:50.073015 Dram Type= 6, Freq= 0, CH_1, rank 1
5534 13:53:50.076395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 13:53:50.076482 ==
5536 13:53:50.083283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5537 13:53:50.089625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5538 13:53:50.093328 [CA 0] Center 36 (6~67) winsize 62
5539 13:53:50.096539 [CA 1] Center 36 (6~67) winsize 62
5540 13:53:50.099773 [CA 2] Center 34 (4~64) winsize 61
5541 13:53:50.103140 [CA 3] Center 33 (3~64) winsize 62
5542 13:53:50.106719 [CA 4] Center 34 (4~65) winsize 62
5543 13:53:50.110169 [CA 5] Center 32 (2~63) winsize 62
5544 13:53:50.110253
5545 13:53:50.113433 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5546 13:53:50.113517
5547 13:53:50.116463 [CATrainingPosCal] consider 2 rank data
5548 13:53:50.119726 u2DelayCellTimex100 = 270/100 ps
5549 13:53:50.123254 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5550 13:53:50.126729 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5551 13:53:50.129940 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 13:53:50.133378 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 13:53:50.136690 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5554 13:53:50.140081 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5555 13:53:50.140166
5556 13:53:50.146951 CA PerBit enable=1, Macro0, CA PI delay=33
5557 13:53:50.147046
5558 13:53:50.147114 [CBTSetCACLKResult] CA Dly = 33
5559 13:53:50.150704 CS Dly: 5 (0~38)
5560 13:53:50.150789
5561 13:53:50.153480 ----->DramcWriteLeveling(PI) begin...
5562 13:53:50.153566 ==
5563 13:53:50.156652 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 13:53:50.160612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 13:53:50.160720 ==
5566 13:53:50.163101 Write leveling (Byte 0): 27 => 27
5567 13:53:50.166481 Write leveling (Byte 1): 29 => 29
5568 13:53:50.169973 DramcWriteLeveling(PI) end<-----
5569 13:53:50.170083
5570 13:53:50.170178 ==
5571 13:53:50.173610 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 13:53:50.176721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 13:53:50.180107 ==
5574 13:53:50.180223 [Gating] SW mode calibration
5575 13:53:50.186543 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5576 13:53:50.193256 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5577 13:53:50.196583 0 14 0 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
5578 13:53:50.203839 0 14 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5579 13:53:50.206953 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5580 13:53:50.209947 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 13:53:50.216515 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 13:53:50.220503 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 13:53:50.223364 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5584 13:53:50.230053 0 14 28 | B1->B0 | 3030 2f2f | 1 1 | (1 0) (1 0)
5585 13:53:50.233650 0 15 0 | B1->B0 | 2424 2a2a | 0 0 | (1 0) (0 0)
5586 13:53:50.236750 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 13:53:50.240078 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 13:53:50.246744 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 13:53:50.249955 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 13:53:50.253952 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 13:53:50.260600 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 13:53:50.263333 0 15 28 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
5593 13:53:50.267276 1 0 0 | B1->B0 | 4444 4141 | 0 0 | (0 0) (0 0)
5594 13:53:50.273521 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 13:53:50.276511 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 13:53:50.280285 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 13:53:50.286941 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 13:53:50.290262 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 13:53:50.293770 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 13:53:50.300312 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5601 13:53:50.303350 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 13:53:50.306710 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 13:53:50.313277 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 13:53:50.316539 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 13:53:50.320080 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 13:53:50.326969 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 13:53:50.330233 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 13:53:50.333531 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 13:53:50.336719 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 13:53:50.344049 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 13:53:50.347045 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 13:53:50.351044 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 13:53:50.357156 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 13:53:50.361133 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 13:53:50.363513 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 13:53:50.370728 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 13:53:50.370814 Total UI for P1: 0, mck2ui 16
5618 13:53:50.377288 best dqsien dly found for B0: ( 1, 2, 26)
5619 13:53:50.377374 Total UI for P1: 0, mck2ui 16
5620 13:53:50.383964 best dqsien dly found for B1: ( 1, 2, 26)
5621 13:53:50.387701 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5622 13:53:50.390293 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5623 13:53:50.390390
5624 13:53:50.393442 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5625 13:53:50.396908 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5626 13:53:50.400437 [Gating] SW calibration Done
5627 13:53:50.400520 ==
5628 13:53:50.403745 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 13:53:50.407237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 13:53:50.407336 ==
5631 13:53:50.410557 RX Vref Scan: 0
5632 13:53:50.410654
5633 13:53:50.410750 RX Vref 0 -> 0, step: 1
5634 13:53:50.410826
5635 13:53:50.413715 RX Delay -80 -> 252, step: 8
5636 13:53:50.416897 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5637 13:53:50.420239 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5638 13:53:50.427012 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5639 13:53:50.430372 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5640 13:53:50.433974 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5641 13:53:50.437022 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5642 13:53:50.440619 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5643 13:53:50.443525 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5644 13:53:50.450590 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5645 13:53:50.453847 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5646 13:53:50.456966 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5647 13:53:50.460246 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5648 13:53:50.463910 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5649 13:53:50.470516 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5650 13:53:50.473664 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5651 13:53:50.477206 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5652 13:53:50.477291 ==
5653 13:53:50.480218 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 13:53:50.483502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 13:53:50.483584 ==
5656 13:53:50.487003 DQS Delay:
5657 13:53:50.487086 DQS0 = 0, DQS1 = 0
5658 13:53:50.487151 DQM Delay:
5659 13:53:50.490357 DQM0 = 97, DQM1 = 88
5660 13:53:50.490476 DQ Delay:
5661 13:53:50.493684 DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95
5662 13:53:50.497277 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5663 13:53:50.500849 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5664 13:53:50.503801 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5665 13:53:50.503885
5666 13:53:50.503950
5667 13:53:50.504010 ==
5668 13:53:50.506891 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 13:53:50.513841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 13:53:50.513953 ==
5671 13:53:50.514047
5672 13:53:50.514129
5673 13:53:50.514235 TX Vref Scan disable
5674 13:53:50.517439 == TX Byte 0 ==
5675 13:53:50.520747 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5676 13:53:50.523821 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5677 13:53:50.527078 == TX Byte 1 ==
5678 13:53:50.530376 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5679 13:53:50.533924 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5680 13:53:50.536904 ==
5681 13:53:50.540231 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 13:53:50.543968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 13:53:50.544077 ==
5684 13:53:50.544170
5685 13:53:50.544258
5686 13:53:50.546882 TX Vref Scan disable
5687 13:53:50.546986 == TX Byte 0 ==
5688 13:53:50.553711 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5689 13:53:50.557140 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5690 13:53:50.557254 == TX Byte 1 ==
5691 13:53:50.563559 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5692 13:53:50.567276 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5693 13:53:50.567387
5694 13:53:50.567483 [DATLAT]
5695 13:53:50.571215 Freq=933, CH1 RK0
5696 13:53:50.571322
5697 13:53:50.571414 DATLAT Default: 0xd
5698 13:53:50.573755 0, 0xFFFF, sum = 0
5699 13:53:50.573865 1, 0xFFFF, sum = 0
5700 13:53:50.577308 2, 0xFFFF, sum = 0
5701 13:53:50.577416 3, 0xFFFF, sum = 0
5702 13:53:50.580406 4, 0xFFFF, sum = 0
5703 13:53:50.580515 5, 0xFFFF, sum = 0
5704 13:53:50.583797 6, 0xFFFF, sum = 0
5705 13:53:50.583906 7, 0xFFFF, sum = 0
5706 13:53:50.586911 8, 0xFFFF, sum = 0
5707 13:53:50.587020 9, 0xFFFF, sum = 0
5708 13:53:50.590855 10, 0x0, sum = 1
5709 13:53:50.590966 11, 0x0, sum = 2
5710 13:53:50.593813 12, 0x0, sum = 3
5711 13:53:50.593921 13, 0x0, sum = 4
5712 13:53:50.596977 best_step = 11
5713 13:53:50.597084
5714 13:53:50.597176 ==
5715 13:53:50.600224 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 13:53:50.603894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 13:53:50.604007 ==
5718 13:53:50.607794 RX Vref Scan: 1
5719 13:53:50.607899
5720 13:53:50.607992 RX Vref 0 -> 0, step: 1
5721 13:53:50.608082
5722 13:53:50.610914 RX Delay -69 -> 252, step: 4
5723 13:53:50.611020
5724 13:53:50.613690 Set Vref, RX VrefLevel [Byte0]: 57
5725 13:53:50.618140 [Byte1]: 53
5726 13:53:50.620896
5727 13:53:50.621003 Final RX Vref Byte 0 = 57 to rank0
5728 13:53:50.624655 Final RX Vref Byte 1 = 53 to rank0
5729 13:53:50.627564 Final RX Vref Byte 0 = 57 to rank1
5730 13:53:50.631229 Final RX Vref Byte 1 = 53 to rank1==
5731 13:53:50.634802 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 13:53:50.641253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 13:53:50.641371 ==
5734 13:53:50.641467 DQS Delay:
5735 13:53:50.641558 DQS0 = 0, DQS1 = 0
5736 13:53:50.644245 DQM Delay:
5737 13:53:50.644352 DQM0 = 97, DQM1 = 90
5738 13:53:50.648257 DQ Delay:
5739 13:53:50.651454 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5740 13:53:50.654219 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5741 13:53:50.657910 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =86
5742 13:53:50.661255 DQ12 =98, DQ13 =98, DQ14 =94, DQ15 =96
5743 13:53:50.661367
5744 13:53:50.661462
5745 13:53:50.667475 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ef, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5746 13:53:50.671216 CH1 RK0: MR19=504, MR18=13EF
5747 13:53:50.677790 CH1_RK0: MR19=0x504, MR18=0x13EF, DQSOSC=415, MR23=63, INC=62, DEC=41
5748 13:53:50.677920
5749 13:53:50.681244 ----->DramcWriteLeveling(PI) begin...
5750 13:53:50.681356 ==
5751 13:53:50.684392 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 13:53:50.688071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 13:53:50.688182 ==
5754 13:53:50.691263 Write leveling (Byte 0): 27 => 27
5755 13:53:50.695299 Write leveling (Byte 1): 26 => 26
5756 13:53:50.698262 DramcWriteLeveling(PI) end<-----
5757 13:53:50.698369
5758 13:53:50.698504 ==
5759 13:53:50.701349 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 13:53:50.705022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 13:53:50.705133 ==
5762 13:53:50.707863 [Gating] SW mode calibration
5763 13:53:50.714334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5764 13:53:50.721220 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5765 13:53:50.724609 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 13:53:50.728083 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 13:53:50.734376 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 13:53:50.737889 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 13:53:50.741211 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 13:53:50.748064 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5771 13:53:50.751256 0 14 24 | B1->B0 | 3333 2e2e | 1 0 | (1 1) (0 1)
5772 13:53:50.754561 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5773 13:53:50.761568 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5774 13:53:50.764738 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 13:53:50.767706 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5776 13:53:50.774350 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 13:53:50.778098 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5778 13:53:50.781604 0 15 20 | B1->B0 | 2423 2727 | 1 0 | (0 0) (0 0)
5779 13:53:50.788282 0 15 24 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
5780 13:53:50.791183 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5781 13:53:50.794262 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 13:53:50.798001 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 13:53:50.804444 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 13:53:50.807716 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 13:53:50.811249 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 13:53:50.817907 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5787 13:53:50.821421 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5788 13:53:50.824286 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 13:53:50.831351 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 13:53:50.835162 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 13:53:50.838015 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 13:53:50.844698 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 13:53:50.847610 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 13:53:50.851071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 13:53:50.857787 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 13:53:50.861347 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 13:53:50.864183 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:53:50.871236 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:53:50.874115 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:53:50.877905 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 13:53:50.884317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 13:53:50.887901 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 13:53:50.891349 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5804 13:53:50.894354 Total UI for P1: 0, mck2ui 16
5805 13:53:50.897703 best dqsien dly found for B0: ( 1, 2, 22)
5806 13:53:50.901432 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 13:53:50.904173 Total UI for P1: 0, mck2ui 16
5808 13:53:50.907718 best dqsien dly found for B1: ( 1, 2, 24)
5809 13:53:50.911082 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5810 13:53:50.917872 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5811 13:53:50.917997
5812 13:53:50.921340 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5813 13:53:50.924730 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5814 13:53:50.927982 [Gating] SW calibration Done
5815 13:53:50.928094 ==
5816 13:53:50.931294 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 13:53:50.934578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 13:53:50.934689 ==
5819 13:53:50.934784 RX Vref Scan: 0
5820 13:53:50.937500
5821 13:53:50.937607 RX Vref 0 -> 0, step: 1
5822 13:53:50.937702
5823 13:53:50.941113 RX Delay -80 -> 252, step: 8
5824 13:53:50.944634 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5825 13:53:50.947836 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5826 13:53:50.954457 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5827 13:53:50.957759 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5828 13:53:50.961254 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5829 13:53:50.964308 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5830 13:53:50.967959 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5831 13:53:50.970935 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5832 13:53:50.974123 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5833 13:53:50.981029 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5834 13:53:50.984627 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5835 13:53:50.988397 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5836 13:53:50.991277 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5837 13:53:50.994580 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5838 13:53:50.998146 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5839 13:53:51.004828 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5840 13:53:51.004956 ==
5841 13:53:51.007692 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 13:53:51.011280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 13:53:51.011392 ==
5844 13:53:51.011486 DQS Delay:
5845 13:53:51.014665 DQS0 = 0, DQS1 = 0
5846 13:53:51.014775 DQM Delay:
5847 13:53:51.018009 DQM0 = 94, DQM1 = 89
5848 13:53:51.018147 DQ Delay:
5849 13:53:51.021115 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5850 13:53:51.024960 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5851 13:53:51.027857 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5852 13:53:51.031770 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5853 13:53:51.031881
5854 13:53:51.031974
5855 13:53:51.032066 ==
5856 13:53:51.034543 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 13:53:51.038602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 13:53:51.038716 ==
5859 13:53:51.038811
5860 13:53:51.041533
5861 13:53:51.041640 TX Vref Scan disable
5862 13:53:51.044915 == TX Byte 0 ==
5863 13:53:51.048023 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5864 13:53:51.051467 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5865 13:53:51.054588 == TX Byte 1 ==
5866 13:53:51.058631 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5867 13:53:51.061405 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5868 13:53:51.061516 ==
5869 13:53:51.064579 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 13:53:51.071523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 13:53:51.071641 ==
5872 13:53:51.071737
5873 13:53:51.071827
5874 13:53:51.071915 TX Vref Scan disable
5875 13:53:51.075578 == TX Byte 0 ==
5876 13:53:51.078875 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5877 13:53:51.085012 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5878 13:53:51.085124 == TX Byte 1 ==
5879 13:53:51.088293 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5880 13:53:51.095073 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5881 13:53:51.095188
5882 13:53:51.095282 [DATLAT]
5883 13:53:51.095373 Freq=933, CH1 RK1
5884 13:53:51.095464
5885 13:53:51.099115 DATLAT Default: 0xb
5886 13:53:51.099223 0, 0xFFFF, sum = 0
5887 13:53:51.101708 1, 0xFFFF, sum = 0
5888 13:53:51.101816 2, 0xFFFF, sum = 0
5889 13:53:51.105063 3, 0xFFFF, sum = 0
5890 13:53:51.108873 4, 0xFFFF, sum = 0
5891 13:53:51.108987 5, 0xFFFF, sum = 0
5892 13:53:51.112382 6, 0xFFFF, sum = 0
5893 13:53:51.112494 7, 0xFFFF, sum = 0
5894 13:53:51.114937 8, 0xFFFF, sum = 0
5895 13:53:51.115046 9, 0xFFFF, sum = 0
5896 13:53:51.118054 10, 0x0, sum = 1
5897 13:53:51.118165 11, 0x0, sum = 2
5898 13:53:51.121605 12, 0x0, sum = 3
5899 13:53:51.121715 13, 0x0, sum = 4
5900 13:53:51.121811 best_step = 11
5901 13:53:51.121903
5902 13:53:51.125114 ==
5903 13:53:51.128284 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 13:53:51.131878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 13:53:51.131988 ==
5906 13:53:51.132081 RX Vref Scan: 0
5907 13:53:51.132171
5908 13:53:51.134910 RX Vref 0 -> 0, step: 1
5909 13:53:51.135018
5910 13:53:51.138162 RX Delay -61 -> 252, step: 4
5911 13:53:51.141699 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5912 13:53:51.148036 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5913 13:53:51.151409 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5914 13:53:51.154931 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5915 13:53:51.157744 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5916 13:53:51.161370 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5917 13:53:51.167891 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5918 13:53:51.171614 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5919 13:53:51.174577 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5920 13:53:51.178923 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5921 13:53:51.182037 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5922 13:53:51.184796 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5923 13:53:51.191248 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5924 13:53:51.194615 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5925 13:53:51.197548 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5926 13:53:51.201300 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5927 13:53:51.201414 ==
5928 13:53:51.204393 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 13:53:51.211158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 13:53:51.211278 ==
5931 13:53:51.211376 DQS Delay:
5932 13:53:51.211467 DQS0 = 0, DQS1 = 0
5933 13:53:51.214383 DQM Delay:
5934 13:53:51.214507 DQM0 = 95, DQM1 = 90
5935 13:53:51.217570 DQ Delay:
5936 13:53:51.221569 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5937 13:53:51.224886 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =90
5938 13:53:51.227710 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5939 13:53:51.231113 DQ12 =96, DQ13 =98, DQ14 =100, DQ15 =98
5940 13:53:51.231197
5941 13:53:51.231263
5942 13:53:51.237720 [DQSOSCAuto] RK1, (LSB)MR18= 0x111a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5943 13:53:51.240916 CH1 RK1: MR19=505, MR18=111A
5944 13:53:51.247486 CH1_RK1: MR19=0x505, MR18=0x111A, DQSOSC=413, MR23=63, INC=63, DEC=42
5945 13:53:51.250948 [RxdqsGatingPostProcess] freq 933
5946 13:53:51.254322 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5947 13:53:51.257546 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 13:53:51.261141 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 13:53:51.264343 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 13:53:51.267901 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 13:53:51.271032 best DQS0 dly(2T, 0.5T) = (0, 10)
5952 13:53:51.274343 best DQS1 dly(2T, 0.5T) = (0, 10)
5953 13:53:51.277553 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5954 13:53:51.280630 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5955 13:53:51.285443 Pre-setting of DQS Precalculation
5956 13:53:51.287514 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5957 13:53:51.297431 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5958 13:53:51.304061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5959 13:53:51.304165
5960 13:53:51.304233
5961 13:53:51.307777 [Calibration Summary] 1866 Mbps
5962 13:53:51.307862 CH 0, Rank 0
5963 13:53:51.311087 SW Impedance : PASS
5964 13:53:51.311174 DUTY Scan : NO K
5965 13:53:51.313874 ZQ Calibration : PASS
5966 13:53:51.317163 Jitter Meter : NO K
5967 13:53:51.317250 CBT Training : PASS
5968 13:53:51.321031 Write leveling : PASS
5969 13:53:51.325097 RX DQS gating : PASS
5970 13:53:51.325183 RX DQ/DQS(RDDQC) : PASS
5971 13:53:51.327735 TX DQ/DQS : PASS
5972 13:53:51.327819 RX DATLAT : PASS
5973 13:53:51.330845 RX DQ/DQS(Engine): PASS
5974 13:53:51.334367 TX OE : NO K
5975 13:53:51.334490 All Pass.
5976 13:53:51.334557
5977 13:53:51.334619 CH 0, Rank 1
5978 13:53:51.337797 SW Impedance : PASS
5979 13:53:51.340748 DUTY Scan : NO K
5980 13:53:51.340834 ZQ Calibration : PASS
5981 13:53:51.344036 Jitter Meter : NO K
5982 13:53:51.347635 CBT Training : PASS
5983 13:53:51.347720 Write leveling : PASS
5984 13:53:51.350656 RX DQS gating : PASS
5985 13:53:51.354086 RX DQ/DQS(RDDQC) : PASS
5986 13:53:51.354170 TX DQ/DQS : PASS
5987 13:53:51.357588 RX DATLAT : PASS
5988 13:53:51.361007 RX DQ/DQS(Engine): PASS
5989 13:53:51.361092 TX OE : NO K
5990 13:53:51.361159 All Pass.
5991 13:53:51.364596
5992 13:53:51.364679 CH 1, Rank 0
5993 13:53:51.367724 SW Impedance : PASS
5994 13:53:51.367808 DUTY Scan : NO K
5995 13:53:51.371127 ZQ Calibration : PASS
5996 13:53:51.371211 Jitter Meter : NO K
5997 13:53:51.374318 CBT Training : PASS
5998 13:53:51.377644 Write leveling : PASS
5999 13:53:51.377728 RX DQS gating : PASS
6000 13:53:51.381034 RX DQ/DQS(RDDQC) : PASS
6001 13:53:51.384060 TX DQ/DQS : PASS
6002 13:53:51.384146 RX DATLAT : PASS
6003 13:53:51.387528 RX DQ/DQS(Engine): PASS
6004 13:53:51.391151 TX OE : NO K
6005 13:53:51.391239 All Pass.
6006 13:53:51.391306
6007 13:53:51.391369 CH 1, Rank 1
6008 13:53:51.394692 SW Impedance : PASS
6009 13:53:51.398530 DUTY Scan : NO K
6010 13:53:51.398617 ZQ Calibration : PASS
6011 13:53:51.400863 Jitter Meter : NO K
6012 13:53:51.404307 CBT Training : PASS
6013 13:53:51.404421 Write leveling : PASS
6014 13:53:51.407395 RX DQS gating : PASS
6015 13:53:51.407505 RX DQ/DQS(RDDQC) : PASS
6016 13:53:51.410980 TX DQ/DQS : PASS
6017 13:53:51.414347 RX DATLAT : PASS
6018 13:53:51.414494 RX DQ/DQS(Engine): PASS
6019 13:53:51.417662 TX OE : NO K
6020 13:53:51.417771 All Pass.
6021 13:53:51.417865
6022 13:53:51.421272 DramC Write-DBI off
6023 13:53:51.424263 PER_BANK_REFRESH: Hybrid Mode
6024 13:53:51.424372 TX_TRACKING: ON
6025 13:53:51.434383 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6026 13:53:51.437974 [FAST_K] Save calibration result to emmc
6027 13:53:51.440828 dramc_set_vcore_voltage set vcore to 650000
6028 13:53:51.444252 Read voltage for 400, 6
6029 13:53:51.444365 Vio18 = 0
6030 13:53:51.444458 Vcore = 650000
6031 13:53:51.447686 Vdram = 0
6032 13:53:51.447795 Vddq = 0
6033 13:53:51.447889 Vmddr = 0
6034 13:53:51.454054 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6035 13:53:51.457641 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6036 13:53:51.461037 MEM_TYPE=3, freq_sel=20
6037 13:53:51.464434 sv_algorithm_assistance_LP4_800
6038 13:53:51.467904 ============ PULL DRAM RESETB DOWN ============
6039 13:53:51.471396 ========== PULL DRAM RESETB DOWN end =========
6040 13:53:51.477842 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6041 13:53:51.480818 ===================================
6042 13:53:51.480937 LPDDR4 DRAM CONFIGURATION
6043 13:53:51.484589 ===================================
6044 13:53:51.487695 EX_ROW_EN[0] = 0x0
6045 13:53:51.491642 EX_ROW_EN[1] = 0x0
6046 13:53:51.491760 LP4Y_EN = 0x0
6047 13:53:51.494708 WORK_FSP = 0x0
6048 13:53:51.494816 WL = 0x2
6049 13:53:51.497930 RL = 0x2
6050 13:53:51.498037 BL = 0x2
6051 13:53:51.501394 RPST = 0x0
6052 13:53:51.501503 RD_PRE = 0x0
6053 13:53:51.504445 WR_PRE = 0x1
6054 13:53:51.504552 WR_PST = 0x0
6055 13:53:51.507766 DBI_WR = 0x0
6056 13:53:51.507851 DBI_RD = 0x0
6057 13:53:51.511738 OTF = 0x1
6058 13:53:51.514730 ===================================
6059 13:53:51.518110 ===================================
6060 13:53:51.518195 ANA top config
6061 13:53:51.521293 ===================================
6062 13:53:51.525078 DLL_ASYNC_EN = 0
6063 13:53:51.528497 ALL_SLAVE_EN = 1
6064 13:53:51.528601 NEW_RANK_MODE = 1
6065 13:53:51.531393 DLL_IDLE_MODE = 1
6066 13:53:51.535326 LP45_APHY_COMB_EN = 1
6067 13:53:51.537958 TX_ODT_DIS = 1
6068 13:53:51.541941 NEW_8X_MODE = 1
6069 13:53:51.544637 ===================================
6070 13:53:51.547862 ===================================
6071 13:53:51.547947 data_rate = 800
6072 13:53:51.551677 CKR = 1
6073 13:53:51.554796 DQ_P2S_RATIO = 4
6074 13:53:51.558151 ===================================
6075 13:53:51.562113 CA_P2S_RATIO = 4
6076 13:53:51.564770 DQ_CA_OPEN = 0
6077 13:53:51.568456 DQ_SEMI_OPEN = 1
6078 13:53:51.568540 CA_SEMI_OPEN = 1
6079 13:53:51.571315 CA_FULL_RATE = 0
6080 13:53:51.574429 DQ_CKDIV4_EN = 0
6081 13:53:51.577720 CA_CKDIV4_EN = 1
6082 13:53:51.581681 CA_PREDIV_EN = 0
6083 13:53:51.581766 PH8_DLY = 0
6084 13:53:51.584732 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6085 13:53:51.588269 DQ_AAMCK_DIV = 0
6086 13:53:51.591573 CA_AAMCK_DIV = 0
6087 13:53:51.594618 CA_ADMCK_DIV = 4
6088 13:53:51.598317 DQ_TRACK_CA_EN = 0
6089 13:53:51.598415 CA_PICK = 800
6090 13:53:51.601910 CA_MCKIO = 400
6091 13:53:51.604926 MCKIO_SEMI = 400
6092 13:53:51.607975 PLL_FREQ = 3016
6093 13:53:51.611600 DQ_UI_PI_RATIO = 32
6094 13:53:51.615242 CA_UI_PI_RATIO = 32
6095 13:53:51.618321 ===================================
6096 13:53:51.621377 ===================================
6097 13:53:51.624795 memory_type:LPDDR4
6098 13:53:51.624884 GP_NUM : 10
6099 13:53:51.628355 SRAM_EN : 1
6100 13:53:51.628439 MD32_EN : 0
6101 13:53:51.631737 ===================================
6102 13:53:51.634674 [ANA_INIT] >>>>>>>>>>>>>>
6103 13:53:51.638169 <<<<<< [CONFIGURE PHASE]: ANA_TX
6104 13:53:51.642134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6105 13:53:51.644728 ===================================
6106 13:53:51.648417 data_rate = 800,PCW = 0X7400
6107 13:53:51.651455 ===================================
6108 13:53:51.655662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6109 13:53:51.658422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 13:53:51.671790 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6111 13:53:51.675080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6112 13:53:51.678297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6113 13:53:51.681497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6114 13:53:51.684932 [ANA_INIT] flow start
6115 13:53:51.685017 [ANA_INIT] PLL >>>>>>>>
6116 13:53:51.688449 [ANA_INIT] PLL <<<<<<<<
6117 13:53:51.691853 [ANA_INIT] MIDPI >>>>>>>>
6118 13:53:51.695208 [ANA_INIT] MIDPI <<<<<<<<
6119 13:53:51.695291 [ANA_INIT] DLL >>>>>>>>
6120 13:53:51.698312 [ANA_INIT] flow end
6121 13:53:51.701508 ============ LP4 DIFF to SE enter ============
6122 13:53:51.705466 ============ LP4 DIFF to SE exit ============
6123 13:53:51.708216 [ANA_INIT] <<<<<<<<<<<<<
6124 13:53:51.711477 [Flow] Enable top DCM control >>>>>
6125 13:53:51.715288 [Flow] Enable top DCM control <<<<<
6126 13:53:51.718169 Enable DLL master slave shuffle
6127 13:53:51.725208 ==============================================================
6128 13:53:51.725298 Gating Mode config
6129 13:53:51.731903 ==============================================================
6130 13:53:51.731991 Config description:
6131 13:53:51.741734 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6132 13:53:51.748387 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6133 13:53:51.755921 SELPH_MODE 0: By rank 1: By Phase
6134 13:53:51.758518 ==============================================================
6135 13:53:51.761651 GAT_TRACK_EN = 0
6136 13:53:51.765210 RX_GATING_MODE = 2
6137 13:53:51.768020 RX_GATING_TRACK_MODE = 2
6138 13:53:51.771839 SELPH_MODE = 1
6139 13:53:51.774798 PICG_EARLY_EN = 1
6140 13:53:51.778366 VALID_LAT_VALUE = 1
6141 13:53:51.781365 ==============================================================
6142 13:53:51.784806 Enter into Gating configuration >>>>
6143 13:53:51.788230 Exit from Gating configuration <<<<
6144 13:53:51.792039 Enter into DVFS_PRE_config >>>>>
6145 13:53:51.804856 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6146 13:53:51.808133 Exit from DVFS_PRE_config <<<<<
6147 13:53:51.808240 Enter into PICG configuration >>>>
6148 13:53:51.811580 Exit from PICG configuration <<<<
6149 13:53:51.815355 [RX_INPUT] configuration >>>>>
6150 13:53:51.818650 [RX_INPUT] configuration <<<<<
6151 13:53:51.825189 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6152 13:53:51.828003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6153 13:53:51.835110 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 13:53:51.841605 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 13:53:51.848715 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6156 13:53:51.855082 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6157 13:53:51.858712 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6158 13:53:51.861633 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6159 13:53:51.865263 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6160 13:53:51.871886 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6161 13:53:51.875299 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6162 13:53:51.878656 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6163 13:53:51.882063 ===================================
6164 13:53:51.885358 LPDDR4 DRAM CONFIGURATION
6165 13:53:51.888535 ===================================
6166 13:53:51.888624 EX_ROW_EN[0] = 0x0
6167 13:53:51.891672 EX_ROW_EN[1] = 0x0
6168 13:53:51.894930 LP4Y_EN = 0x0
6169 13:53:51.895017 WORK_FSP = 0x0
6170 13:53:51.898254 WL = 0x2
6171 13:53:51.898340 RL = 0x2
6172 13:53:51.902132 BL = 0x2
6173 13:53:51.902218 RPST = 0x0
6174 13:53:51.905020 RD_PRE = 0x0
6175 13:53:51.905105 WR_PRE = 0x1
6176 13:53:51.908389 WR_PST = 0x0
6177 13:53:51.908476 DBI_WR = 0x0
6178 13:53:51.912616 DBI_RD = 0x0
6179 13:53:51.912703 OTF = 0x1
6180 13:53:51.915640 ===================================
6181 13:53:51.918334 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6182 13:53:51.925419 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6183 13:53:51.928113 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 13:53:51.931906 ===================================
6185 13:53:51.935171 LPDDR4 DRAM CONFIGURATION
6186 13:53:51.938589 ===================================
6187 13:53:51.938678 EX_ROW_EN[0] = 0x10
6188 13:53:51.941664 EX_ROW_EN[1] = 0x0
6189 13:53:51.941752 LP4Y_EN = 0x0
6190 13:53:51.945207 WORK_FSP = 0x0
6191 13:53:51.945294 WL = 0x2
6192 13:53:51.948420 RL = 0x2
6193 13:53:51.952081 BL = 0x2
6194 13:53:51.952169 RPST = 0x0
6195 13:53:51.954924 RD_PRE = 0x0
6196 13:53:51.955010 WR_PRE = 0x1
6197 13:53:51.958670 WR_PST = 0x0
6198 13:53:51.958761 DBI_WR = 0x0
6199 13:53:51.961389 DBI_RD = 0x0
6200 13:53:51.961475 OTF = 0x1
6201 13:53:51.964958 ===================================
6202 13:53:51.971724 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6203 13:53:51.975287 nWR fixed to 30
6204 13:53:51.978743 [ModeRegInit_LP4] CH0 RK0
6205 13:53:51.978837 [ModeRegInit_LP4] CH0 RK1
6206 13:53:51.982322 [ModeRegInit_LP4] CH1 RK0
6207 13:53:51.985210 [ModeRegInit_LP4] CH1 RK1
6208 13:53:51.985298 match AC timing 19
6209 13:53:51.992576 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6210 13:53:51.995141 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6211 13:53:51.998384 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6212 13:53:52.005454 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6213 13:53:52.008963 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6214 13:53:52.009051 ==
6215 13:53:52.012463 Dram Type= 6, Freq= 0, CH_0, rank 0
6216 13:53:52.015545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6217 13:53:52.015629 ==
6218 13:53:52.022271 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6219 13:53:52.028549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6220 13:53:52.032040 [CA 0] Center 36 (8~64) winsize 57
6221 13:53:52.035652 [CA 1] Center 36 (8~64) winsize 57
6222 13:53:52.038683 [CA 2] Center 36 (8~64) winsize 57
6223 13:53:52.038766 [CA 3] Center 36 (8~64) winsize 57
6224 13:53:52.042298 [CA 4] Center 36 (8~64) winsize 57
6225 13:53:52.045458 [CA 5] Center 36 (8~64) winsize 57
6226 13:53:52.045541
6227 13:53:52.049085 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6228 13:53:52.052449
6229 13:53:52.055070 [CATrainingPosCal] consider 1 rank data
6230 13:53:52.055154 u2DelayCellTimex100 = 270/100 ps
6231 13:53:52.062287 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 13:53:52.064873 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 13:53:52.069323 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 13:53:52.072492 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 13:53:52.076235 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 13:53:52.078603 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 13:53:52.078686
6238 13:53:52.081943 CA PerBit enable=1, Macro0, CA PI delay=36
6239 13:53:52.082026
6240 13:53:52.085103 [CBTSetCACLKResult] CA Dly = 36
6241 13:53:52.088765 CS Dly: 1 (0~32)
6242 13:53:52.088847 ==
6243 13:53:52.091927 Dram Type= 6, Freq= 0, CH_0, rank 1
6244 13:53:52.095197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 13:53:52.095279 ==
6246 13:53:52.102887 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 13:53:52.105288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6248 13:53:52.108410 [CA 0] Center 36 (8~64) winsize 57
6249 13:53:52.111643 [CA 1] Center 36 (8~64) winsize 57
6250 13:53:52.115198 [CA 2] Center 36 (8~64) winsize 57
6251 13:53:52.118368 [CA 3] Center 36 (8~64) winsize 57
6252 13:53:52.121708 [CA 4] Center 36 (8~64) winsize 57
6253 13:53:52.125480 [CA 5] Center 36 (8~64) winsize 57
6254 13:53:52.125563
6255 13:53:52.128329 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6256 13:53:52.128412
6257 13:53:52.131863 [CATrainingPosCal] consider 2 rank data
6258 13:53:52.135398 u2DelayCellTimex100 = 270/100 ps
6259 13:53:52.138671 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 13:53:52.141799 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 13:53:52.145099 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 13:53:52.148501 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 13:53:52.156227 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 13:53:52.158236 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 13:53:52.158320
6266 13:53:52.162029 CA PerBit enable=1, Macro0, CA PI delay=36
6267 13:53:52.162116
6268 13:53:52.165191 [CBTSetCACLKResult] CA Dly = 36
6269 13:53:52.165273 CS Dly: 1 (0~32)
6270 13:53:52.165340
6271 13:53:52.168350 ----->DramcWriteLeveling(PI) begin...
6272 13:53:52.168434 ==
6273 13:53:52.172910 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 13:53:52.178345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 13:53:52.178439 ==
6276 13:53:52.181845 Write leveling (Byte 0): 40 => 8
6277 13:53:52.181938 Write leveling (Byte 1): 32 => 0
6278 13:53:52.185492 DramcWriteLeveling(PI) end<-----
6279 13:53:52.185574
6280 13:53:52.185640 ==
6281 13:53:52.188638 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 13:53:52.195329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 13:53:52.195413 ==
6284 13:53:52.195479 [Gating] SW mode calibration
6285 13:53:52.205117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6286 13:53:52.208758 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6287 13:53:52.211942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 13:53:52.219007 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6289 13:53:52.221564 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 13:53:52.225907 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 13:53:52.231700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 13:53:52.235051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 13:53:52.238653 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 13:53:52.245854 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 13:53:52.248901 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 13:53:52.252395 Total UI for P1: 0, mck2ui 16
6297 13:53:52.255351 best dqsien dly found for B0: ( 0, 14, 24)
6298 13:53:52.258778 Total UI for P1: 0, mck2ui 16
6299 13:53:52.261829 best dqsien dly found for B1: ( 0, 14, 24)
6300 13:53:52.265523 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6301 13:53:52.268751 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6302 13:53:52.268835
6303 13:53:52.272139 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 13:53:52.275424 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6305 13:53:52.278753 [Gating] SW calibration Done
6306 13:53:52.278835 ==
6307 13:53:52.282100 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 13:53:52.285548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 13:53:52.288700 ==
6310 13:53:52.288783 RX Vref Scan: 0
6311 13:53:52.288848
6312 13:53:52.292410 RX Vref 0 -> 0, step: 1
6313 13:53:52.292492
6314 13:53:52.295309 RX Delay -410 -> 252, step: 16
6315 13:53:52.298557 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6316 13:53:52.302056 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6317 13:53:52.305533 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6318 13:53:52.312977 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6319 13:53:52.315602 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6320 13:53:52.318851 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6321 13:53:52.322000 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6322 13:53:52.328730 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6323 13:53:52.332092 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6324 13:53:52.335520 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6325 13:53:52.338633 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6326 13:53:52.345214 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6327 13:53:52.349055 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6328 13:53:52.352655 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6329 13:53:52.355462 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6330 13:53:52.362388 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6331 13:53:52.362511 ==
6332 13:53:52.365356 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 13:53:52.368875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 13:53:52.368957 ==
6335 13:53:52.369021 DQS Delay:
6336 13:53:52.372070 DQS0 = 35, DQS1 = 51
6337 13:53:52.372160 DQM Delay:
6338 13:53:52.375590 DQM0 = 6, DQM1 = 10
6339 13:53:52.375670 DQ Delay:
6340 13:53:52.378676 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6341 13:53:52.382571 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6342 13:53:52.385936 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6343 13:53:52.388811 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6344 13:53:52.388891
6345 13:53:52.388954
6346 13:53:52.389013 ==
6347 13:53:52.392468 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 13:53:52.395476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 13:53:52.395559 ==
6350 13:53:52.395623
6351 13:53:52.395682
6352 13:53:52.398970 TX Vref Scan disable
6353 13:53:52.399056 == TX Byte 0 ==
6354 13:53:52.405847 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 13:53:52.409275 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 13:53:52.409369 == TX Byte 1 ==
6357 13:53:52.415954 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6358 13:53:52.418841 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6359 13:53:52.418931 ==
6360 13:53:52.422357 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 13:53:52.425805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 13:53:52.425891 ==
6363 13:53:52.425957
6364 13:53:52.426017
6365 13:53:52.428633 TX Vref Scan disable
6366 13:53:52.428714 == TX Byte 0 ==
6367 13:53:52.435538 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 13:53:52.438675 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 13:53:52.438764 == TX Byte 1 ==
6370 13:53:52.445552 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6371 13:53:52.449425 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6372 13:53:52.449510
6373 13:53:52.449574 [DATLAT]
6374 13:53:52.451872 Freq=400, CH0 RK0
6375 13:53:52.451953
6376 13:53:52.452018 DATLAT Default: 0xf
6377 13:53:52.456258 0, 0xFFFF, sum = 0
6378 13:53:52.456342 1, 0xFFFF, sum = 0
6379 13:53:52.458767 2, 0xFFFF, sum = 0
6380 13:53:52.458849 3, 0xFFFF, sum = 0
6381 13:53:52.461882 4, 0xFFFF, sum = 0
6382 13:53:52.461964 5, 0xFFFF, sum = 0
6383 13:53:52.465601 6, 0xFFFF, sum = 0
6384 13:53:52.465684 7, 0xFFFF, sum = 0
6385 13:53:52.468718 8, 0xFFFF, sum = 0
6386 13:53:52.471972 9, 0xFFFF, sum = 0
6387 13:53:52.472054 10, 0xFFFF, sum = 0
6388 13:53:52.475099 11, 0xFFFF, sum = 0
6389 13:53:52.475180 12, 0xFFFF, sum = 0
6390 13:53:52.478548 13, 0x0, sum = 1
6391 13:53:52.478631 14, 0x0, sum = 2
6392 13:53:52.482226 15, 0x0, sum = 3
6393 13:53:52.482337 16, 0x0, sum = 4
6394 13:53:52.482435 best_step = 14
6395 13:53:52.482497
6396 13:53:52.485452 ==
6397 13:53:52.488769 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 13:53:52.492166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 13:53:52.492282 ==
6400 13:53:52.492351 RX Vref Scan: 1
6401 13:53:52.492411
6402 13:53:52.495330 RX Vref 0 -> 0, step: 1
6403 13:53:52.495410
6404 13:53:52.498924 RX Delay -343 -> 252, step: 8
6405 13:53:52.499004
6406 13:53:52.502336 Set Vref, RX VrefLevel [Byte0]: 53
6407 13:53:52.505306 [Byte1]: 51
6408 13:53:52.509123
6409 13:53:52.509205 Final RX Vref Byte 0 = 53 to rank0
6410 13:53:52.512382 Final RX Vref Byte 1 = 51 to rank0
6411 13:53:52.516202 Final RX Vref Byte 0 = 53 to rank1
6412 13:53:52.519434 Final RX Vref Byte 1 = 51 to rank1==
6413 13:53:52.522935 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 13:53:52.529424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 13:53:52.529597 ==
6416 13:53:52.529668 DQS Delay:
6417 13:53:52.532513 DQS0 = 44, DQS1 = 60
6418 13:53:52.532653 DQM Delay:
6419 13:53:52.532720 DQM0 = 11, DQM1 = 15
6420 13:53:52.535827 DQ Delay:
6421 13:53:52.539143 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6422 13:53:52.539284 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6423 13:53:52.542581 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6424 13:53:52.545944 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6425 13:53:52.546076
6426 13:53:52.549234
6427 13:53:52.555661 [DQSOSCAuto] RK0, (LSB)MR18= 0x8755, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
6428 13:53:52.558704 CH0 RK0: MR19=C0C, MR18=8755
6429 13:53:52.565611 CH0_RK0: MR19=0xC0C, MR18=0x8755, DQSOSC=392, MR23=63, INC=384, DEC=256
6430 13:53:52.565751 ==
6431 13:53:52.569031 Dram Type= 6, Freq= 0, CH_0, rank 1
6432 13:53:52.572136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 13:53:52.572244 ==
6434 13:53:52.575325 [Gating] SW mode calibration
6435 13:53:52.582540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6436 13:53:52.589014 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6437 13:53:52.592323 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 13:53:52.595669 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 13:53:52.599267 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 13:53:52.605467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 13:53:52.608624 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 13:53:52.612527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 13:53:52.619044 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 13:53:52.622263 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 13:53:52.625864 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 13:53:52.628800 Total UI for P1: 0, mck2ui 16
6447 13:53:52.632283 best dqsien dly found for B0: ( 0, 14, 24)
6448 13:53:52.635880 Total UI for P1: 0, mck2ui 16
6449 13:53:52.638574 best dqsien dly found for B1: ( 0, 14, 24)
6450 13:53:52.642614 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6451 13:53:52.645643 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6452 13:53:52.645728
6453 13:53:52.652435 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 13:53:52.655540 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6455 13:53:52.658976 [Gating] SW calibration Done
6456 13:53:52.659062 ==
6457 13:53:52.662279 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 13:53:52.665544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 13:53:52.665630 ==
6460 13:53:52.665717 RX Vref Scan: 0
6461 13:53:52.665799
6462 13:53:52.668573 RX Vref 0 -> 0, step: 1
6463 13:53:52.668657
6464 13:53:52.672138 RX Delay -410 -> 252, step: 16
6465 13:53:52.675206 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6466 13:53:52.682107 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6467 13:53:52.685653 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6468 13:53:52.688935 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6469 13:53:52.692439 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6470 13:53:52.695219 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6471 13:53:52.702543 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6472 13:53:52.705416 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6473 13:53:52.708612 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6474 13:53:52.711970 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6475 13:53:52.718709 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6476 13:53:52.722740 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6477 13:53:52.725754 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6478 13:53:52.732150 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6479 13:53:52.735286 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6480 13:53:52.738913 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6481 13:53:52.739020 ==
6482 13:53:52.742228 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 13:53:52.745237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 13:53:52.745319 ==
6485 13:53:52.748904 DQS Delay:
6486 13:53:52.748984 DQS0 = 43, DQS1 = 51
6487 13:53:52.752720 DQM Delay:
6488 13:53:52.752800 DQM0 = 11, DQM1 = 10
6489 13:53:52.752865 DQ Delay:
6490 13:53:52.756530 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6491 13:53:52.758735 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6492 13:53:52.762240 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6493 13:53:52.765392 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6494 13:53:52.765473
6495 13:53:52.765537
6496 13:53:52.765596 ==
6497 13:53:52.768946 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 13:53:52.775879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 13:53:52.775962 ==
6500 13:53:52.776026
6501 13:53:52.776085
6502 13:53:52.776142 TX Vref Scan disable
6503 13:53:52.778734 == TX Byte 0 ==
6504 13:53:52.782070 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6505 13:53:52.786271 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6506 13:53:52.788923 == TX Byte 1 ==
6507 13:53:52.792224 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6508 13:53:52.795710 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6509 13:53:52.795791 ==
6510 13:53:52.799272 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 13:53:52.805555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 13:53:52.805637 ==
6513 13:53:52.805701
6514 13:53:52.805760
6515 13:53:52.805816 TX Vref Scan disable
6516 13:53:52.809195 == TX Byte 0 ==
6517 13:53:52.812176 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6518 13:53:52.815833 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6519 13:53:52.818772 == TX Byte 1 ==
6520 13:53:52.822401 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6521 13:53:52.825479 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6522 13:53:52.825559
6523 13:53:52.828540 [DATLAT]
6524 13:53:52.828622 Freq=400, CH0 RK1
6525 13:53:52.828688
6526 13:53:52.832363 DATLAT Default: 0xe
6527 13:53:52.832447 0, 0xFFFF, sum = 0
6528 13:53:52.835612 1, 0xFFFF, sum = 0
6529 13:53:52.835697 2, 0xFFFF, sum = 0
6530 13:53:52.839760 3, 0xFFFF, sum = 0
6531 13:53:52.839844 4, 0xFFFF, sum = 0
6532 13:53:52.842917 5, 0xFFFF, sum = 0
6533 13:53:52.843000 6, 0xFFFF, sum = 0
6534 13:53:52.845462 7, 0xFFFF, sum = 0
6535 13:53:52.845545 8, 0xFFFF, sum = 0
6536 13:53:52.849381 9, 0xFFFF, sum = 0
6537 13:53:52.849464 10, 0xFFFF, sum = 0
6538 13:53:52.852559 11, 0xFFFF, sum = 0
6539 13:53:52.852643 12, 0xFFFF, sum = 0
6540 13:53:52.855876 13, 0x0, sum = 1
6541 13:53:52.855960 14, 0x0, sum = 2
6542 13:53:52.858876 15, 0x0, sum = 3
6543 13:53:52.858962 16, 0x0, sum = 4
6544 13:53:52.862441 best_step = 14
6545 13:53:52.862527
6546 13:53:52.862594 ==
6547 13:53:52.865413 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 13:53:52.869772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 13:53:52.869855 ==
6550 13:53:52.872470 RX Vref Scan: 0
6551 13:53:52.872552
6552 13:53:52.872617 RX Vref 0 -> 0, step: 1
6553 13:53:52.872679
6554 13:53:52.875587 RX Delay -343 -> 252, step: 8
6555 13:53:52.883150 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6556 13:53:52.887490 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6557 13:53:52.890137 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6558 13:53:52.893505 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6559 13:53:52.900043 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6560 13:53:52.903452 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6561 13:53:52.906983 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6562 13:53:52.909763 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6563 13:53:52.916769 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6564 13:53:52.920480 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6565 13:53:52.923773 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6566 13:53:52.926894 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6567 13:53:52.933232 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6568 13:53:52.936793 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6569 13:53:52.940011 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6570 13:53:52.946629 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6571 13:53:52.946716 ==
6572 13:53:52.950085 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 13:53:52.953409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 13:53:52.953491 ==
6575 13:53:52.953556 DQS Delay:
6576 13:53:52.956717 DQS0 = 44, DQS1 = 56
6577 13:53:52.956877 DQM Delay:
6578 13:53:52.959830 DQM0 = 9, DQM1 = 10
6579 13:53:52.959917 DQ Delay:
6580 13:53:52.963900 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6581 13:53:52.967120 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6582 13:53:52.970106 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6583 13:53:52.973602 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6584 13:53:52.973683
6585 13:53:52.973748
6586 13:53:52.980146 [DQSOSCAuto] RK1, (LSB)MR18= 0x996a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6587 13:53:52.983500 CH0 RK1: MR19=C0C, MR18=996A
6588 13:53:52.990203 CH0_RK1: MR19=0xC0C, MR18=0x996A, DQSOSC=390, MR23=63, INC=388, DEC=258
6589 13:53:52.993372 [RxdqsGatingPostProcess] freq 400
6590 13:53:52.997081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6591 13:53:53.000573 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 13:53:53.003902 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 13:53:53.006845 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 13:53:53.010242 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 13:53:53.013953 best DQS0 dly(2T, 0.5T) = (0, 10)
6596 13:53:53.017308 best DQS1 dly(2T, 0.5T) = (0, 10)
6597 13:53:53.020602 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6598 13:53:53.023841 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6599 13:53:53.026889 Pre-setting of DQS Precalculation
6600 13:53:53.030116 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6601 13:53:53.030199 ==
6602 13:53:53.033470 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 13:53:53.040651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6604 13:53:53.040809 ==
6605 13:53:53.043684 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6606 13:53:53.050361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6607 13:53:53.053885 [CA 0] Center 36 (8~64) winsize 57
6608 13:53:53.056968 [CA 1] Center 36 (8~64) winsize 57
6609 13:53:53.060781 [CA 2] Center 36 (8~64) winsize 57
6610 13:53:53.063724 [CA 3] Center 36 (8~64) winsize 57
6611 13:53:53.067727 [CA 4] Center 36 (8~64) winsize 57
6612 13:53:53.070561 [CA 5] Center 36 (8~64) winsize 57
6613 13:53:53.070689
6614 13:53:53.073729 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6615 13:53:53.073849
6616 13:53:53.077335 [CATrainingPosCal] consider 1 rank data
6617 13:53:53.080230 u2DelayCellTimex100 = 270/100 ps
6618 13:53:53.084077 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 13:53:53.087232 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 13:53:53.090593 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 13:53:53.093932 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 13:53:53.097313 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 13:53:53.100424 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 13:53:53.100659
6625 13:53:53.107277 CA PerBit enable=1, Macro0, CA PI delay=36
6626 13:53:53.107550
6627 13:53:53.107727 [CBTSetCACLKResult] CA Dly = 36
6628 13:53:53.110782 CS Dly: 1 (0~32)
6629 13:53:53.111070 ==
6630 13:53:53.113842 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 13:53:53.117609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 13:53:53.117916 ==
6633 13:53:53.124143 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 13:53:53.130694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6635 13:53:53.134178 [CA 0] Center 36 (8~64) winsize 57
6636 13:53:53.137622 [CA 1] Center 36 (8~64) winsize 57
6637 13:53:53.138004 [CA 2] Center 36 (8~64) winsize 57
6638 13:53:53.140910 [CA 3] Center 36 (8~64) winsize 57
6639 13:53:53.144221 [CA 4] Center 36 (8~64) winsize 57
6640 13:53:53.147300 [CA 5] Center 36 (8~64) winsize 57
6641 13:53:53.147479
6642 13:53:53.150604 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6643 13:53:53.150709
6644 13:53:53.157080 [CATrainingPosCal] consider 2 rank data
6645 13:53:53.157207 u2DelayCellTimex100 = 270/100 ps
6646 13:53:53.163762 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 13:53:53.167427 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 13:53:53.170384 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 13:53:53.173605 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 13:53:53.176718 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 13:53:53.180620 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 13:53:53.180701
6653 13:53:53.183933 CA PerBit enable=1, Macro0, CA PI delay=36
6654 13:53:53.184024
6655 13:53:53.186984 [CBTSetCACLKResult] CA Dly = 36
6656 13:53:53.189867 CS Dly: 1 (0~32)
6657 13:53:53.189957
6658 13:53:53.194003 ----->DramcWriteLeveling(PI) begin...
6659 13:53:53.194100 ==
6660 13:53:53.197316 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 13:53:53.200930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 13:53:53.201013 ==
6663 13:53:53.203581 Write leveling (Byte 0): 40 => 8
6664 13:53:53.207256 Write leveling (Byte 1): 40 => 8
6665 13:53:53.210620 DramcWriteLeveling(PI) end<-----
6666 13:53:53.210858
6667 13:53:53.211046 ==
6668 13:53:53.213262 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 13:53:53.217048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 13:53:53.217238 ==
6671 13:53:53.220226 [Gating] SW mode calibration
6672 13:53:53.226784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6673 13:53:53.233470 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6674 13:53:53.236617 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 13:53:53.239995 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6676 13:53:53.246597 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 13:53:53.250106 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 13:53:53.253252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 13:53:53.256589 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 13:53:53.263636 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 13:53:53.267414 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 13:53:53.270289 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 13:53:53.273453 Total UI for P1: 0, mck2ui 16
6684 13:53:53.277454 best dqsien dly found for B0: ( 0, 14, 24)
6685 13:53:53.280838 Total UI for P1: 0, mck2ui 16
6686 13:53:53.284843 best dqsien dly found for B1: ( 0, 14, 24)
6687 13:53:53.286950 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6688 13:53:53.290196 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6689 13:53:53.293264
6690 13:53:53.296651 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 13:53:53.300112 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6692 13:53:53.303693 [Gating] SW calibration Done
6693 13:53:53.303774 ==
6694 13:53:53.306598 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 13:53:53.310387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 13:53:53.310509 ==
6697 13:53:53.310575 RX Vref Scan: 0
6698 13:53:53.310636
6699 13:53:53.313914 RX Vref 0 -> 0, step: 1
6700 13:53:53.313994
6701 13:53:53.316427 RX Delay -410 -> 252, step: 16
6702 13:53:53.320061 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6703 13:53:53.326725 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6704 13:53:53.330369 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6705 13:53:53.333419 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6706 13:53:53.336863 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6707 13:53:53.343339 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6708 13:53:53.346634 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6709 13:53:53.350512 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6710 13:53:53.353494 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6711 13:53:53.357228 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6712 13:53:53.363389 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6713 13:53:53.366719 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6714 13:53:53.370417 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6715 13:53:53.377179 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6716 13:53:53.380212 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6717 13:53:53.383776 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6718 13:53:53.383857 ==
6719 13:53:53.387047 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 13:53:53.390118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 13:53:53.390200 ==
6722 13:53:53.393393 DQS Delay:
6723 13:53:53.393474 DQS0 = 51, DQS1 = 59
6724 13:53:53.396705 DQM Delay:
6725 13:53:53.396786 DQM0 = 19, DQM1 = 18
6726 13:53:53.396852 DQ Delay:
6727 13:53:53.400163 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6728 13:53:53.403568 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6729 13:53:53.407481 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6730 13:53:53.410246 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6731 13:53:53.410327
6732 13:53:53.410392
6733 13:53:53.413535 ==
6734 13:53:53.413615 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 13:53:53.420622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 13:53:53.420704 ==
6737 13:53:53.420769
6738 13:53:53.420829
6739 13:53:53.423895 TX Vref Scan disable
6740 13:53:53.423977 == TX Byte 0 ==
6741 13:53:53.426937 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 13:53:53.430470 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 13:53:53.434338 == TX Byte 1 ==
6744 13:53:53.437285 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 13:53:53.440493 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 13:53:53.443809 ==
6747 13:53:53.443891 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 13:53:53.450123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 13:53:53.450205 ==
6750 13:53:53.450269
6751 13:53:53.450329
6752 13:53:53.453423 TX Vref Scan disable
6753 13:53:53.453506 == TX Byte 0 ==
6754 13:53:53.456975 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 13:53:53.460377 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 13:53:53.463816 == TX Byte 1 ==
6757 13:53:53.466535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 13:53:53.470391 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 13:53:53.470481
6760 13:53:53.473519 [DATLAT]
6761 13:53:53.473599 Freq=400, CH1 RK0
6762 13:53:53.473665
6763 13:53:53.476883 DATLAT Default: 0xf
6764 13:53:53.476963 0, 0xFFFF, sum = 0
6765 13:53:53.480290 1, 0xFFFF, sum = 0
6766 13:53:53.480372 2, 0xFFFF, sum = 0
6767 13:53:53.483709 3, 0xFFFF, sum = 0
6768 13:53:53.483793 4, 0xFFFF, sum = 0
6769 13:53:53.487016 5, 0xFFFF, sum = 0
6770 13:53:53.487099 6, 0xFFFF, sum = 0
6771 13:53:53.489915 7, 0xFFFF, sum = 0
6772 13:53:53.493281 8, 0xFFFF, sum = 0
6773 13:53:53.493364 9, 0xFFFF, sum = 0
6774 13:53:53.496645 10, 0xFFFF, sum = 0
6775 13:53:53.496727 11, 0xFFFF, sum = 0
6776 13:53:53.500515 12, 0xFFFF, sum = 0
6777 13:53:53.500597 13, 0x0, sum = 1
6778 13:53:53.503485 14, 0x0, sum = 2
6779 13:53:53.503567 15, 0x0, sum = 3
6780 13:53:53.506929 16, 0x0, sum = 4
6781 13:53:53.507011 best_step = 14
6782 13:53:53.507076
6783 13:53:53.507136 ==
6784 13:53:53.510922 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 13:53:53.513385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 13:53:53.513466 ==
6787 13:53:53.516980 RX Vref Scan: 1
6788 13:53:53.517060
6789 13:53:53.517124 RX Vref 0 -> 0, step: 1
6790 13:53:53.520374
6791 13:53:53.520454 RX Delay -359 -> 252, step: 8
6792 13:53:53.520519
6793 13:53:53.523418 Set Vref, RX VrefLevel [Byte0]: 57
6794 13:53:53.526927 [Byte1]: 53
6795 13:53:53.532016
6796 13:53:53.532108 Final RX Vref Byte 0 = 57 to rank0
6797 13:53:53.535496 Final RX Vref Byte 1 = 53 to rank0
6798 13:53:53.539061 Final RX Vref Byte 0 = 57 to rank1
6799 13:53:53.541836 Final RX Vref Byte 1 = 53 to rank1==
6800 13:53:53.545614 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 13:53:53.552103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 13:53:53.552196 ==
6803 13:53:53.552262 DQS Delay:
6804 13:53:53.555278 DQS0 = 48, DQS1 = 60
6805 13:53:53.555370 DQM Delay:
6806 13:53:53.555436 DQM0 = 11, DQM1 = 13
6807 13:53:53.558372 DQ Delay:
6808 13:53:53.562036 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6809 13:53:53.562121 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =4
6810 13:53:53.565357 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6811 13:53:53.568696 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6812 13:53:53.568857
6813 13:53:53.572581
6814 13:53:53.578670 [DQSOSCAuto] RK0, (LSB)MR18= 0x872f, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6815 13:53:53.582449 CH1 RK0: MR19=C0C, MR18=872F
6816 13:53:53.588931 CH1_RK0: MR19=0xC0C, MR18=0x872F, DQSOSC=392, MR23=63, INC=384, DEC=256
6817 13:53:53.589107 ==
6818 13:53:53.592348 Dram Type= 6, Freq= 0, CH_1, rank 1
6819 13:53:53.595954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 13:53:53.596391 ==
6821 13:53:53.599267 [Gating] SW mode calibration
6822 13:53:53.605584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6823 13:53:53.609348 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6824 13:53:53.615901 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 13:53:53.619908 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6826 13:53:53.622558 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 13:53:53.629114 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 13:53:53.632588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 13:53:53.635411 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 13:53:53.642553 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 13:53:53.645867 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 13:53:53.649108 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 13:53:53.652779 Total UI for P1: 0, mck2ui 16
6834 13:53:53.656137 best dqsien dly found for B0: ( 0, 14, 24)
6835 13:53:53.659146 Total UI for P1: 0, mck2ui 16
6836 13:53:53.662309 best dqsien dly found for B1: ( 0, 14, 24)
6837 13:53:53.665705 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6838 13:53:53.669349 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6839 13:53:53.669839
6840 13:53:53.676061 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 13:53:53.679783 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6842 13:53:53.680304 [Gating] SW calibration Done
6843 13:53:53.682803 ==
6844 13:53:53.686368 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 13:53:53.689251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 13:53:53.689792 ==
6847 13:53:53.690137 RX Vref Scan: 0
6848 13:53:53.690508
6849 13:53:53.692681 RX Vref 0 -> 0, step: 1
6850 13:53:53.693204
6851 13:53:53.696063 RX Delay -410 -> 252, step: 16
6852 13:53:53.699044 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6853 13:53:53.702581 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6854 13:53:53.709263 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6855 13:53:53.713095 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6856 13:53:53.715892 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6857 13:53:53.719011 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6858 13:53:53.726509 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6859 13:53:53.729376 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6860 13:53:53.732712 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6861 13:53:53.736235 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6862 13:53:53.742850 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6863 13:53:53.746128 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6864 13:53:53.749709 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6865 13:53:53.752884 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6866 13:53:53.759556 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6867 13:53:53.762498 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6868 13:53:53.763017 ==
6869 13:53:53.765851 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 13:53:53.769324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 13:53:53.769851 ==
6872 13:53:53.773019 DQS Delay:
6873 13:53:53.773538 DQS0 = 43, DQS1 = 59
6874 13:53:53.776361 DQM Delay:
6875 13:53:53.776888 DQM0 = 10, DQM1 = 20
6876 13:53:53.777228 DQ Delay:
6877 13:53:53.779058 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6878 13:53:53.782532 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6879 13:53:53.786145 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6880 13:53:53.789136 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6881 13:53:53.789661
6882 13:53:53.789995
6883 13:53:53.790500 ==
6884 13:53:53.792487 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 13:53:53.799008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 13:53:53.799532 ==
6887 13:53:53.799871
6888 13:53:53.800176
6889 13:53:53.800470 TX Vref Scan disable
6890 13:53:53.802537 == TX Byte 0 ==
6891 13:53:53.805699 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6892 13:53:53.808996 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6893 13:53:53.813546 == TX Byte 1 ==
6894 13:53:53.815946 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6895 13:53:53.819690 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6896 13:53:53.820216 ==
6897 13:53:53.822788 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 13:53:53.826162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 13:53:53.829326 ==
6900 13:53:53.829749
6901 13:53:53.830152
6902 13:53:53.830517 TX Vref Scan disable
6903 13:53:53.833213 == TX Byte 0 ==
6904 13:53:53.835881 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6905 13:53:53.839480 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6906 13:53:53.842374 == TX Byte 1 ==
6907 13:53:53.845859 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6908 13:53:53.849281 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6909 13:53:53.849807
6910 13:53:53.852924 [DATLAT]
6911 13:53:53.853443 Freq=400, CH1 RK1
6912 13:53:53.853840
6913 13:53:53.855529 DATLAT Default: 0xe
6914 13:53:53.856041 0, 0xFFFF, sum = 0
6915 13:53:53.859549 1, 0xFFFF, sum = 0
6916 13:53:53.860077 2, 0xFFFF, sum = 0
6917 13:53:53.862449 3, 0xFFFF, sum = 0
6918 13:53:53.862873 4, 0xFFFF, sum = 0
6919 13:53:53.865730 5, 0xFFFF, sum = 0
6920 13:53:53.866257 6, 0xFFFF, sum = 0
6921 13:53:53.869322 7, 0xFFFF, sum = 0
6922 13:53:53.869844 8, 0xFFFF, sum = 0
6923 13:53:53.872744 9, 0xFFFF, sum = 0
6924 13:53:53.873273 10, 0xFFFF, sum = 0
6925 13:53:53.876016 11, 0xFFFF, sum = 0
6926 13:53:53.876545 12, 0xFFFF, sum = 0
6927 13:53:53.879379 13, 0x0, sum = 1
6928 13:53:53.879904 14, 0x0, sum = 2
6929 13:53:53.882391 15, 0x0, sum = 3
6930 13:53:53.882966 16, 0x0, sum = 4
6931 13:53:53.885763 best_step = 14
6932 13:53:53.886282
6933 13:53:53.886661 ==
6934 13:53:53.888947 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 13:53:53.892973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 13:53:53.893502 ==
6937 13:53:53.895686 RX Vref Scan: 0
6938 13:53:53.896208
6939 13:53:53.896548 RX Vref 0 -> 0, step: 1
6940 13:53:53.896865
6941 13:53:53.898820 RX Delay -359 -> 252, step: 8
6942 13:53:53.907223 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6943 13:53:53.910622 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6944 13:53:53.914125 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6945 13:53:53.916876 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6946 13:53:53.923777 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6947 13:53:53.927396 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6948 13:53:53.930182 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6949 13:53:53.933593 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6950 13:53:53.940448 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6951 13:53:53.943757 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6952 13:53:53.946898 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6953 13:53:53.950442 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6954 13:53:53.956999 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6955 13:53:53.960481 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6956 13:53:53.963940 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6957 13:53:53.970491 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6958 13:53:53.971016 ==
6959 13:53:53.974597 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 13:53:53.976957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 13:53:53.977384 ==
6962 13:53:53.977718 DQS Delay:
6963 13:53:53.980988 DQS0 = 52, DQS1 = 60
6964 13:53:53.981513 DQM Delay:
6965 13:53:53.983921 DQM0 = 13, DQM1 = 12
6966 13:53:53.984353 DQ Delay:
6967 13:53:53.987286 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6968 13:53:53.990484 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6969 13:53:53.993877 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6970 13:53:53.997348 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6971 13:53:53.997872
6972 13:53:53.998213
6973 13:53:54.003916 [DQSOSCAuto] RK1, (LSB)MR18= 0x7890, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6974 13:53:54.006934 CH1 RK1: MR19=C0C, MR18=7890
6975 13:53:54.014102 CH1_RK1: MR19=0xC0C, MR18=0x7890, DQSOSC=391, MR23=63, INC=386, DEC=257
6976 13:53:54.017216 [RxdqsGatingPostProcess] freq 400
6977 13:53:54.020907 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6978 13:53:54.023668 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 13:53:54.027368 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 13:53:54.030099 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 13:53:54.033757 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 13:53:54.037280 best DQS0 dly(2T, 0.5T) = (0, 10)
6983 13:53:54.040817 best DQS1 dly(2T, 0.5T) = (0, 10)
6984 13:53:54.043981 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6985 13:53:54.047009 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6986 13:53:54.050533 Pre-setting of DQS Precalculation
6987 13:53:54.053873 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6988 13:53:54.063817 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6989 13:53:54.070204 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6990 13:53:54.070674
6991 13:53:54.071010
6992 13:53:54.074034 [Calibration Summary] 800 Mbps
6993 13:53:54.074488 CH 0, Rank 0
6994 13:53:54.077449 SW Impedance : PASS
6995 13:53:54.078030 DUTY Scan : NO K
6996 13:53:54.081136 ZQ Calibration : PASS
6997 13:53:54.084314 Jitter Meter : NO K
6998 13:53:54.084852 CBT Training : PASS
6999 13:53:54.087300 Write leveling : PASS
7000 13:53:54.087722 RX DQS gating : PASS
7001 13:53:54.090570 RX DQ/DQS(RDDQC) : PASS
7002 13:53:54.093825 TX DQ/DQS : PASS
7003 13:53:54.094354 RX DATLAT : PASS
7004 13:53:54.097167 RX DQ/DQS(Engine): PASS
7005 13:53:54.100821 TX OE : NO K
7006 13:53:54.101355 All Pass.
7007 13:53:54.101698
7008 13:53:54.102009 CH 0, Rank 1
7009 13:53:54.103473 SW Impedance : PASS
7010 13:53:54.107149 DUTY Scan : NO K
7011 13:53:54.107568 ZQ Calibration : PASS
7012 13:53:54.110503 Jitter Meter : NO K
7013 13:53:54.114481 CBT Training : PASS
7014 13:53:54.115001 Write leveling : NO K
7015 13:53:54.117480 RX DQS gating : PASS
7016 13:53:54.120985 RX DQ/DQS(RDDQC) : PASS
7017 13:53:54.121513 TX DQ/DQS : PASS
7018 13:53:54.123960 RX DATLAT : PASS
7019 13:53:54.124489 RX DQ/DQS(Engine): PASS
7020 13:53:54.127165 TX OE : NO K
7021 13:53:54.127587 All Pass.
7022 13:53:54.127920
7023 13:53:54.130430 CH 1, Rank 0
7024 13:53:54.130946 SW Impedance : PASS
7025 13:53:54.134162 DUTY Scan : NO K
7026 13:53:54.137653 ZQ Calibration : PASS
7027 13:53:54.138309 Jitter Meter : NO K
7028 13:53:54.140814 CBT Training : PASS
7029 13:53:54.143881 Write leveling : PASS
7030 13:53:54.144309 RX DQS gating : PASS
7031 13:53:54.147058 RX DQ/DQS(RDDQC) : PASS
7032 13:53:54.150661 TX DQ/DQS : PASS
7033 13:53:54.151207 RX DATLAT : PASS
7034 13:53:54.154318 RX DQ/DQS(Engine): PASS
7035 13:53:54.157164 TX OE : NO K
7036 13:53:54.157704 All Pass.
7037 13:53:54.158052
7038 13:53:54.158369 CH 1, Rank 1
7039 13:53:54.160536 SW Impedance : PASS
7040 13:53:54.163944 DUTY Scan : NO K
7041 13:53:54.164373 ZQ Calibration : PASS
7042 13:53:54.166899 Jitter Meter : NO K
7043 13:53:54.170443 CBT Training : PASS
7044 13:53:54.170974 Write leveling : NO K
7045 13:53:54.174083 RX DQS gating : PASS
7046 13:53:54.174647 RX DQ/DQS(RDDQC) : PASS
7047 13:53:54.177178 TX DQ/DQS : PASS
7048 13:53:54.180592 RX DATLAT : PASS
7049 13:53:54.181015 RX DQ/DQS(Engine): PASS
7050 13:53:54.184243 TX OE : NO K
7051 13:53:54.184773 All Pass.
7052 13:53:54.185113
7053 13:53:54.186978 DramC Write-DBI off
7054 13:53:54.190342 PER_BANK_REFRESH: Hybrid Mode
7055 13:53:54.190860 TX_TRACKING: ON
7056 13:53:54.200244 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7057 13:53:54.203718 [FAST_K] Save calibration result to emmc
7058 13:53:54.207597 dramc_set_vcore_voltage set vcore to 725000
7059 13:53:54.211384 Read voltage for 1600, 0
7060 13:53:54.211953 Vio18 = 0
7061 13:53:54.212512 Vcore = 725000
7062 13:53:54.213964 Vdram = 0
7063 13:53:54.214379 Vddq = 0
7064 13:53:54.214766 Vmddr = 0
7065 13:53:54.220718 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7066 13:53:54.224345 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7067 13:53:54.227232 MEM_TYPE=3, freq_sel=13
7068 13:53:54.230567 sv_algorithm_assistance_LP4_3733
7069 13:53:54.233999 ============ PULL DRAM RESETB DOWN ============
7070 13:53:54.237561 ========== PULL DRAM RESETB DOWN end =========
7071 13:53:54.244458 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7072 13:53:54.247246 ===================================
7073 13:53:54.250891 LPDDR4 DRAM CONFIGURATION
7074 13:53:54.254150 ===================================
7075 13:53:54.254712 EX_ROW_EN[0] = 0x0
7076 13:53:54.257186 EX_ROW_EN[1] = 0x0
7077 13:53:54.257734 LP4Y_EN = 0x0
7078 13:53:54.260937 WORK_FSP = 0x1
7079 13:53:54.261461 WL = 0x5
7080 13:53:54.264223 RL = 0x5
7081 13:53:54.264748 BL = 0x2
7082 13:53:54.266948 RPST = 0x0
7083 13:53:54.267367 RD_PRE = 0x0
7084 13:53:54.271054 WR_PRE = 0x1
7085 13:53:54.271592 WR_PST = 0x1
7086 13:53:54.274148 DBI_WR = 0x0
7087 13:53:54.274703 DBI_RD = 0x0
7088 13:53:54.277656 OTF = 0x1
7089 13:53:54.280817 ===================================
7090 13:53:54.284567 ===================================
7091 13:53:54.285091 ANA top config
7092 13:53:54.287381 ===================================
7093 13:53:54.290996 DLL_ASYNC_EN = 0
7094 13:53:54.294353 ALL_SLAVE_EN = 0
7095 13:53:54.297420 NEW_RANK_MODE = 1
7096 13:53:54.297949 DLL_IDLE_MODE = 1
7097 13:53:54.301062 LP45_APHY_COMB_EN = 1
7098 13:53:54.303952 TX_ODT_DIS = 0
7099 13:53:54.307637 NEW_8X_MODE = 1
7100 13:53:54.310498 ===================================
7101 13:53:54.314164 ===================================
7102 13:53:54.317685 data_rate = 3200
7103 13:53:54.318221 CKR = 1
7104 13:53:54.320398 DQ_P2S_RATIO = 8
7105 13:53:54.323728 ===================================
7106 13:53:54.327293 CA_P2S_RATIO = 8
7107 13:53:54.330705 DQ_CA_OPEN = 0
7108 13:53:54.334259 DQ_SEMI_OPEN = 0
7109 13:53:54.334832 CA_SEMI_OPEN = 0
7110 13:53:54.337071 CA_FULL_RATE = 0
7111 13:53:54.341078 DQ_CKDIV4_EN = 0
7112 13:53:54.343929 CA_CKDIV4_EN = 0
7113 13:53:54.347826 CA_PREDIV_EN = 0
7114 13:53:54.350391 PH8_DLY = 12
7115 13:53:54.350841 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7116 13:53:54.354235 DQ_AAMCK_DIV = 4
7117 13:53:54.357564 CA_AAMCK_DIV = 4
7118 13:53:54.361188 CA_ADMCK_DIV = 4
7119 13:53:54.364339 DQ_TRACK_CA_EN = 0
7120 13:53:54.367232 CA_PICK = 1600
7121 13:53:54.370889 CA_MCKIO = 1600
7122 13:53:54.371311 MCKIO_SEMI = 0
7123 13:53:54.374072 PLL_FREQ = 3068
7124 13:53:54.377660 DQ_UI_PI_RATIO = 32
7125 13:53:54.381110 CA_UI_PI_RATIO = 0
7126 13:53:54.384558 ===================================
7127 13:53:54.387641 ===================================
7128 13:53:54.391081 memory_type:LPDDR4
7129 13:53:54.391607 GP_NUM : 10
7130 13:53:54.394826 SRAM_EN : 1
7131 13:53:54.395350 MD32_EN : 0
7132 13:53:54.397906 ===================================
7133 13:53:54.401369 [ANA_INIT] >>>>>>>>>>>>>>
7134 13:53:54.404242 <<<<<< [CONFIGURE PHASE]: ANA_TX
7135 13:53:54.407353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7136 13:53:54.410951 ===================================
7137 13:53:54.414021 data_rate = 3200,PCW = 0X7600
7138 13:53:54.417679 ===================================
7139 13:53:54.420969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7140 13:53:54.424322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 13:53:54.430684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7142 13:53:54.437410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7143 13:53:54.441047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7144 13:53:54.444670 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7145 13:53:54.445196 [ANA_INIT] flow start
7146 13:53:54.447507 [ANA_INIT] PLL >>>>>>>>
7147 13:53:54.451191 [ANA_INIT] PLL <<<<<<<<
7148 13:53:54.451719 [ANA_INIT] MIDPI >>>>>>>>
7149 13:53:54.454287 [ANA_INIT] MIDPI <<<<<<<<
7150 13:53:54.457697 [ANA_INIT] DLL >>>>>>>>
7151 13:53:54.458231 [ANA_INIT] DLL <<<<<<<<
7152 13:53:54.461177 [ANA_INIT] flow end
7153 13:53:54.464299 ============ LP4 DIFF to SE enter ============
7154 13:53:54.468106 ============ LP4 DIFF to SE exit ============
7155 13:53:54.471321 [ANA_INIT] <<<<<<<<<<<<<
7156 13:53:54.474312 [Flow] Enable top DCM control >>>>>
7157 13:53:54.477665 [Flow] Enable top DCM control <<<<<
7158 13:53:54.481376 Enable DLL master slave shuffle
7159 13:53:54.487610 ==============================================================
7160 13:53:54.488031 Gating Mode config
7161 13:53:54.494594 ==============================================================
7162 13:53:54.495120 Config description:
7163 13:53:54.504512 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7164 13:53:54.510959 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7165 13:53:54.518082 SELPH_MODE 0: By rank 1: By Phase
7166 13:53:54.521005 ==============================================================
7167 13:53:54.524277 GAT_TRACK_EN = 1
7168 13:53:54.527752 RX_GATING_MODE = 2
7169 13:53:54.530590 RX_GATING_TRACK_MODE = 2
7170 13:53:54.535062 SELPH_MODE = 1
7171 13:53:54.537551 PICG_EARLY_EN = 1
7172 13:53:54.541299 VALID_LAT_VALUE = 1
7173 13:53:54.544621 ==============================================================
7174 13:53:54.547586 Enter into Gating configuration >>>>
7175 13:53:54.550898 Exit from Gating configuration <<<<
7176 13:53:54.554265 Enter into DVFS_PRE_config >>>>>
7177 13:53:54.567490 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7178 13:53:54.570705 Exit from DVFS_PRE_config <<<<<
7179 13:53:54.574886 Enter into PICG configuration >>>>
7180 13:53:54.575406 Exit from PICG configuration <<<<
7181 13:53:54.578656 [RX_INPUT] configuration >>>>>
7182 13:53:54.581880 [RX_INPUT] configuration <<<<<
7183 13:53:54.587689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7184 13:53:54.590938 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7185 13:53:54.597721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 13:53:54.604340 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 13:53:54.611174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7188 13:53:54.617528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7189 13:53:54.620625 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7190 13:53:54.624560 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7191 13:53:54.628094 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7192 13:53:54.634214 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7193 13:53:54.638071 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7194 13:53:54.641350 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7195 13:53:54.644585 ===================================
7196 13:53:54.648123 LPDDR4 DRAM CONFIGURATION
7197 13:53:54.651735 ===================================
7198 13:53:54.652256 EX_ROW_EN[0] = 0x0
7199 13:53:54.654985 EX_ROW_EN[1] = 0x0
7200 13:53:54.655524 LP4Y_EN = 0x0
7201 13:53:54.657648 WORK_FSP = 0x1
7202 13:53:54.661486 WL = 0x5
7203 13:53:54.661903 RL = 0x5
7204 13:53:54.664295 BL = 0x2
7205 13:53:54.664710 RPST = 0x0
7206 13:53:54.667834 RD_PRE = 0x0
7207 13:53:54.668257 WR_PRE = 0x1
7208 13:53:54.670952 WR_PST = 0x1
7209 13:53:54.671411 DBI_WR = 0x0
7210 13:53:54.674456 DBI_RD = 0x0
7211 13:53:54.674876 OTF = 0x1
7212 13:53:54.677902 ===================================
7213 13:53:54.681088 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7214 13:53:54.687933 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7215 13:53:54.691270 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 13:53:54.695079 ===================================
7217 13:53:54.697922 LPDDR4 DRAM CONFIGURATION
7218 13:53:54.701349 ===================================
7219 13:53:54.701769 EX_ROW_EN[0] = 0x10
7220 13:53:54.704689 EX_ROW_EN[1] = 0x0
7221 13:53:54.705104 LP4Y_EN = 0x0
7222 13:53:54.707972 WORK_FSP = 0x1
7223 13:53:54.708429 WL = 0x5
7224 13:53:54.711266 RL = 0x5
7225 13:53:54.711689 BL = 0x2
7226 13:53:54.714350 RPST = 0x0
7227 13:53:54.714818 RD_PRE = 0x0
7228 13:53:54.717860 WR_PRE = 0x1
7229 13:53:54.718275 WR_PST = 0x1
7230 13:53:54.721221 DBI_WR = 0x0
7231 13:53:54.724644 DBI_RD = 0x0
7232 13:53:54.725057 OTF = 0x1
7233 13:53:54.728051 ===================================
7234 13:53:54.734717 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7235 13:53:54.735135 ==
7236 13:53:54.738119 Dram Type= 6, Freq= 0, CH_0, rank 0
7237 13:53:54.741858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7238 13:53:54.742390 ==
7239 13:53:54.744791 [Duty_Offset_Calibration]
7240 13:53:54.745313 B0:2 B1:-1 CA:1
7241 13:53:54.745651
7242 13:53:54.748193 [DutyScan_Calibration_Flow] k_type=0
7243 13:53:54.759099
7244 13:53:54.759617 ==CLK 0==
7245 13:53:54.761935 Final CLK duty delay cell = -4
7246 13:53:54.765316 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7247 13:53:54.768938 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7248 13:53:54.771999 [-4] AVG Duty = 4937%(X100)
7249 13:53:54.772421
7250 13:53:54.775288 CH0 CLK Duty spec in!! Max-Min= 187%
7251 13:53:54.778308 [DutyScan_Calibration_Flow] ====Done====
7252 13:53:54.778757
7253 13:53:54.782004 [DutyScan_Calibration_Flow] k_type=1
7254 13:53:54.798091
7255 13:53:54.798670 ==DQS 0 ==
7256 13:53:54.801226 Final DQS duty delay cell = 0
7257 13:53:54.804319 [0] MAX Duty = 5125%(X100), DQS PI = 20
7258 13:53:54.807926 [0] MIN Duty = 5000%(X100), DQS PI = 32
7259 13:53:54.808347 [0] AVG Duty = 5062%(X100)
7260 13:53:54.810933
7261 13:53:54.811347 ==DQS 1 ==
7262 13:53:54.814665 Final DQS duty delay cell = -4
7263 13:53:54.817793 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7264 13:53:54.821075 [-4] MIN Duty = 5031%(X100), DQS PI = 8
7265 13:53:54.824755 [-4] AVG Duty = 5062%(X100)
7266 13:53:54.825177
7267 13:53:54.827968 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7268 13:53:54.828388
7269 13:53:54.831384 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7270 13:53:54.834515 [DutyScan_Calibration_Flow] ====Done====
7271 13:53:54.834937
7272 13:53:54.837495 [DutyScan_Calibration_Flow] k_type=3
7273 13:53:54.855269
7274 13:53:54.855500 ==DQM 0 ==
7275 13:53:54.857982 Final DQM duty delay cell = 0
7276 13:53:54.861697 [0] MAX Duty = 5000%(X100), DQS PI = 38
7277 13:53:54.864672 [0] MIN Duty = 4875%(X100), DQS PI = 6
7278 13:53:54.867965 [0] AVG Duty = 4937%(X100)
7279 13:53:54.868189
7280 13:53:54.868370 ==DQM 1 ==
7281 13:53:54.871598 Final DQM duty delay cell = 0
7282 13:53:54.874730 [0] MAX Duty = 5187%(X100), DQS PI = 58
7283 13:53:54.878521 [0] MIN Duty = 4969%(X100), DQS PI = 20
7284 13:53:54.881766 [0] AVG Duty = 5078%(X100)
7285 13:53:54.882082
7286 13:53:54.884657 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7287 13:53:54.884893
7288 13:53:54.888140 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7289 13:53:54.891181 [DutyScan_Calibration_Flow] ====Done====
7290 13:53:54.891409
7291 13:53:54.894554 [DutyScan_Calibration_Flow] k_type=2
7292 13:53:54.918361
7293 13:53:54.918577 ==DQ 0 ==
7294 13:53:54.918701 Final DQ duty delay cell = 0
7295 13:53:54.918817 [0] MAX Duty = 5156%(X100), DQS PI = 0
7296 13:53:54.922389 [0] MIN Duty = 5031%(X100), DQS PI = 12
7297 13:53:54.922567 [0] AVG Duty = 5093%(X100)
7298 13:53:54.922743
7299 13:53:54.924999 ==DQ 1 ==
7300 13:53:54.928510 Final DQ duty delay cell = 0
7301 13:53:54.932024 [0] MAX Duty = 5031%(X100), DQS PI = 32
7302 13:53:54.935403 [0] MIN Duty = 4907%(X100), DQS PI = 42
7303 13:53:54.935552 [0] AVG Duty = 4969%(X100)
7304 13:53:54.935671
7305 13:53:54.938985 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7306 13:53:54.939135
7307 13:53:54.942309 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7308 13:53:54.948964 [DutyScan_Calibration_Flow] ====Done====
7309 13:53:54.949239 ==
7310 13:53:54.951721 Dram Type= 6, Freq= 0, CH_1, rank 0
7311 13:53:54.955250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7312 13:53:54.955590 ==
7313 13:53:54.958716 [Duty_Offset_Calibration]
7314 13:53:54.959044 B0:1 B1:1 CA:2
7315 13:53:54.959251
7316 13:53:54.962152 [DutyScan_Calibration_Flow] k_type=0
7317 13:53:54.972637
7318 13:53:54.973155 ==CLK 0==
7319 13:53:54.976585 Final CLK duty delay cell = 0
7320 13:53:54.979319 [0] MAX Duty = 5187%(X100), DQS PI = 24
7321 13:53:54.982264 [0] MIN Duty = 4969%(X100), DQS PI = 40
7322 13:53:54.982832 [0] AVG Duty = 5078%(X100)
7323 13:53:54.985807
7324 13:53:54.986319 CH1 CLK Duty spec in!! Max-Min= 218%
7325 13:53:54.992009 [DutyScan_Calibration_Flow] ====Done====
7326 13:53:54.992512
7327 13:53:54.995687 [DutyScan_Calibration_Flow] k_type=1
7328 13:53:55.012299
7329 13:53:55.012814 ==DQS 0 ==
7330 13:53:55.015397 Final DQS duty delay cell = 0
7331 13:53:55.019070 [0] MAX Duty = 5062%(X100), DQS PI = 20
7332 13:53:55.022182 [0] MIN Duty = 4813%(X100), DQS PI = 52
7333 13:53:55.022722 [0] AVG Duty = 4937%(X100)
7334 13:53:55.025557
7335 13:53:55.026100 ==DQS 1 ==
7336 13:53:55.028749 Final DQS duty delay cell = 0
7337 13:53:55.032012 [0] MAX Duty = 5062%(X100), DQS PI = 56
7338 13:53:55.035740 [0] MIN Duty = 4938%(X100), DQS PI = 12
7339 13:53:55.036260 [0] AVG Duty = 5000%(X100)
7340 13:53:55.038537
7341 13:53:55.041961 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7342 13:53:55.042374
7343 13:53:55.045689 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7344 13:53:55.048962 [DutyScan_Calibration_Flow] ====Done====
7345 13:53:55.049495
7346 13:53:55.052162 [DutyScan_Calibration_Flow] k_type=3
7347 13:53:55.069174
7348 13:53:55.069713 ==DQM 0 ==
7349 13:53:55.072274 Final DQM duty delay cell = 0
7350 13:53:55.075633 [0] MAX Duty = 5124%(X100), DQS PI = 18
7351 13:53:55.079310 [0] MIN Duty = 4844%(X100), DQS PI = 52
7352 13:53:55.082391 [0] AVG Duty = 4984%(X100)
7353 13:53:55.082848
7354 13:53:55.083177 ==DQM 1 ==
7355 13:53:55.085611 Final DQM duty delay cell = 0
7356 13:53:55.089318 [0] MAX Duty = 5125%(X100), DQS PI = 8
7357 13:53:55.092111 [0] MIN Duty = 4875%(X100), DQS PI = 22
7358 13:53:55.092535 [0] AVG Duty = 5000%(X100)
7359 13:53:55.095975
7360 13:53:55.099135 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7361 13:53:55.099655
7362 13:53:55.102622 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7363 13:53:55.105630 [DutyScan_Calibration_Flow] ====Done====
7364 13:53:55.106154
7365 13:53:55.109195 [DutyScan_Calibration_Flow] k_type=2
7366 13:53:55.125888
7367 13:53:55.126496 ==DQ 0 ==
7368 13:53:55.129428 Final DQ duty delay cell = 0
7369 13:53:55.132612 [0] MAX Duty = 5156%(X100), DQS PI = 22
7370 13:53:55.136015 [0] MIN Duty = 4907%(X100), DQS PI = 52
7371 13:53:55.136588 [0] AVG Duty = 5031%(X100)
7372 13:53:55.136958
7373 13:53:55.139266 ==DQ 1 ==
7374 13:53:55.142859 Final DQ duty delay cell = 0
7375 13:53:55.145755 [0] MAX Duty = 5093%(X100), DQS PI = 6
7376 13:53:55.149189 [0] MIN Duty = 5031%(X100), DQS PI = 0
7377 13:53:55.149762 [0] AVG Duty = 5062%(X100)
7378 13:53:55.150140
7379 13:53:55.152563 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7380 13:53:55.153128
7381 13:53:55.155944 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7382 13:53:55.159349 [DutyScan_Calibration_Flow] ====Done====
7383 13:53:55.165098 nWR fixed to 30
7384 13:53:55.168015 [ModeRegInit_LP4] CH0 RK0
7385 13:53:55.168531 [ModeRegInit_LP4] CH0 RK1
7386 13:53:55.171426 [ModeRegInit_LP4] CH1 RK0
7387 13:53:55.174737 [ModeRegInit_LP4] CH1 RK1
7388 13:53:55.175151 match AC timing 5
7389 13:53:55.180965 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7390 13:53:55.184920 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7391 13:53:55.188330 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7392 13:53:55.194772 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7393 13:53:55.197967 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7394 13:53:55.198515 [MiockJmeterHQA]
7395 13:53:55.198851
7396 13:53:55.201339 [DramcMiockJmeter] u1RxGatingPI = 0
7397 13:53:55.204765 0 : 4368, 4140
7398 13:53:55.205291 4 : 4255, 4029
7399 13:53:55.207606 8 : 4253, 4027
7400 13:53:55.208031 12 : 4363, 4137
7401 13:53:55.211169 16 : 4253, 4026
7402 13:53:55.211695 20 : 4253, 4026
7403 13:53:55.212035 24 : 4260, 4031
7404 13:53:55.214860 28 : 4367, 4140
7405 13:53:55.215393 32 : 4253, 4026
7406 13:53:55.217984 36 : 4258, 4030
7407 13:53:55.218439 40 : 4363, 4137
7408 13:53:55.221399 44 : 4252, 4027
7409 13:53:55.221818 48 : 4366, 4140
7410 13:53:55.222157 52 : 4363, 4137
7411 13:53:55.224503 56 : 4250, 4027
7412 13:53:55.225021 60 : 4363, 4140
7413 13:53:55.228209 64 : 4252, 4029
7414 13:53:55.228722 68 : 4250, 4027
7415 13:53:55.231273 72 : 4363, 4140
7416 13:53:55.231799 76 : 4255, 4029
7417 13:53:55.234595 80 : 4361, 4138
7418 13:53:55.235017 84 : 4366, 4140
7419 13:53:55.235359 88 : 4248, 4024
7420 13:53:55.237945 92 : 4252, 4029
7421 13:53:55.238365 96 : 4361, 3448
7422 13:53:55.241295 100 : 4366, 0
7423 13:53:55.241727 104 : 4252, 0
7424 13:53:55.242064 108 : 4361, 0
7425 13:53:55.245058 112 : 4250, 0
7426 13:53:55.245579 116 : 4252, 0
7427 13:53:55.247799 120 : 4250, 0
7428 13:53:55.248225 124 : 4252, 0
7429 13:53:55.248566 128 : 4250, 0
7430 13:53:55.250980 132 : 4365, 0
7431 13:53:55.251404 136 : 4253, 0
7432 13:53:55.254743 140 : 4363, 0
7433 13:53:55.255276 144 : 4249, 0
7434 13:53:55.255622 148 : 4255, 0
7435 13:53:55.257994 152 : 4363, 0
7436 13:53:55.258460 156 : 4253, 0
7437 13:53:55.261371 160 : 4250, 0
7438 13:53:55.261794 164 : 4252, 0
7439 13:53:55.262130 168 : 4250, 0
7440 13:53:55.264824 172 : 4252, 0
7441 13:53:55.265342 176 : 4250, 0
7442 13:53:55.265682 180 : 4360, 0
7443 13:53:55.268391 184 : 4250, 0
7444 13:53:55.268910 188 : 4250, 0
7445 13:53:55.271211 192 : 4366, 0
7446 13:53:55.271637 196 : 4252, 0
7447 13:53:55.271978 200 : 4255, 0
7448 13:53:55.274459 204 : 4363, 0
7449 13:53:55.274881 208 : 4365, 0
7450 13:53:55.278547 212 : 4252, 131
7451 13:53:55.278971 216 : 4255, 3791
7452 13:53:55.279307 220 : 4252, 4027
7453 13:53:55.281391 224 : 4255, 4029
7454 13:53:55.281924 228 : 4252, 4029
7455 13:53:55.285089 232 : 4363, 4137
7456 13:53:55.285623 236 : 4253, 4029
7457 13:53:55.287830 240 : 4250, 4026
7458 13:53:55.288255 244 : 4363, 4137
7459 13:53:55.291069 248 : 4250, 4027
7460 13:53:55.291493 252 : 4250, 4027
7461 13:53:55.295033 256 : 4250, 4027
7462 13:53:55.295461 260 : 4250, 4026
7463 13:53:55.298236 264 : 4363, 4140
7464 13:53:55.298819 268 : 4252, 4029
7465 13:53:55.301253 272 : 4360, 4138
7466 13:53:55.301782 276 : 4255, 4029
7467 13:53:55.302127 280 : 4255, 4029
7468 13:53:55.304937 284 : 4252, 4030
7469 13:53:55.305466 288 : 4366, 4140
7470 13:53:55.307972 292 : 4252, 4030
7471 13:53:55.308396 296 : 4363, 4137
7472 13:53:55.311562 300 : 4252, 4029
7473 13:53:55.311987 304 : 4255, 4029
7474 13:53:55.314920 308 : 4252, 4030
7475 13:53:55.315348 312 : 4250, 4027
7476 13:53:55.318203 316 : 4250, 4027
7477 13:53:55.318651 320 : 4255, 4029
7478 13:53:55.321851 324 : 4250, 4027
7479 13:53:55.322277 328 : 4361, 4138
7480 13:53:55.324826 332 : 4360, 2843
7481 13:53:55.325356 336 : 4250, 45
7482 13:53:55.325698
7483 13:53:55.328601 MIOCK jitter meter ch=0
7484 13:53:55.329125
7485 13:53:55.331263 1T = (336-100) = 236 dly cells
7486 13:53:55.334876 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7487 13:53:55.335299 ==
7488 13:53:55.338114 Dram Type= 6, Freq= 0, CH_0, rank 0
7489 13:53:55.344474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7490 13:53:55.344905 ==
7491 13:53:55.347826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7492 13:53:55.354346 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7493 13:53:55.358308 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7494 13:53:55.364827 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7495 13:53:55.372028 [CA 0] Center 44 (14~74) winsize 61
7496 13:53:55.375828 [CA 1] Center 43 (13~74) winsize 62
7497 13:53:55.379148 [CA 2] Center 39 (10~68) winsize 59
7498 13:53:55.381993 [CA 3] Center 39 (10~68) winsize 59
7499 13:53:55.386001 [CA 4] Center 37 (7~67) winsize 61
7500 13:53:55.389791 [CA 5] Center 37 (7~67) winsize 61
7501 13:53:55.390320
7502 13:53:55.392003 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7503 13:53:55.392423
7504 13:53:55.395466 [CATrainingPosCal] consider 1 rank data
7505 13:53:55.398874 u2DelayCellTimex100 = 275/100 ps
7506 13:53:55.401976 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7507 13:53:55.409062 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7508 13:53:55.411775 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7509 13:53:55.415577 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7510 13:53:55.418769 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7511 13:53:55.421893 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7512 13:53:55.422314
7513 13:53:55.425841 CA PerBit enable=1, Macro0, CA PI delay=37
7514 13:53:55.426355
7515 13:53:55.428951 [CBTSetCACLKResult] CA Dly = 37
7516 13:53:55.432665 CS Dly: 11 (0~42)
7517 13:53:55.435794 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7518 13:53:55.438794 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7519 13:53:55.439260 ==
7520 13:53:55.442226 Dram Type= 6, Freq= 0, CH_0, rank 1
7521 13:53:55.445916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 13:53:55.449004 ==
7523 13:53:55.452495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7524 13:53:55.455930 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7525 13:53:55.462080 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7526 13:53:55.465341 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7527 13:53:55.476067 [CA 0] Center 43 (13~74) winsize 62
7528 13:53:55.479541 [CA 1] Center 43 (13~74) winsize 62
7529 13:53:55.482262 [CA 2] Center 39 (10~69) winsize 60
7530 13:53:55.486115 [CA 3] Center 38 (9~68) winsize 60
7531 13:53:55.489714 [CA 4] Center 37 (7~67) winsize 61
7532 13:53:55.492360 [CA 5] Center 37 (7~67) winsize 61
7533 13:53:55.492784
7534 13:53:55.496188 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7535 13:53:55.496715
7536 13:53:55.499772 [CATrainingPosCal] consider 2 rank data
7537 13:53:55.502619 u2DelayCellTimex100 = 275/100 ps
7538 13:53:55.506180 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7539 13:53:55.512642 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7540 13:53:55.516216 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7541 13:53:55.519192 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7542 13:53:55.522993 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7543 13:53:55.526083 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7544 13:53:55.526702
7545 13:53:55.529296 CA PerBit enable=1, Macro0, CA PI delay=37
7546 13:53:55.529863
7547 13:53:55.532625 [CBTSetCACLKResult] CA Dly = 37
7548 13:53:55.535740 CS Dly: 12 (0~44)
7549 13:53:55.539394 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7550 13:53:55.542643 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7551 13:53:55.543064
7552 13:53:55.546127 ----->DramcWriteLeveling(PI) begin...
7553 13:53:55.546618 ==
7554 13:53:55.549086 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 13:53:55.552775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 13:53:55.555652 ==
7557 13:53:55.556074 Write leveling (Byte 0): 32 => 32
7558 13:53:55.559333 Write leveling (Byte 1): 27 => 27
7559 13:53:55.562505 DramcWriteLeveling(PI) end<-----
7560 13:53:55.562928
7561 13:53:55.563263 ==
7562 13:53:55.565756 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 13:53:55.572677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 13:53:55.573197 ==
7565 13:53:55.573535 [Gating] SW mode calibration
7566 13:53:55.582268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7567 13:53:55.586027 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7568 13:53:55.589280 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 13:53:55.595621 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 13:53:55.598909 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 13:53:55.602479 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 13:53:55.609239 1 4 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7573 13:53:55.612746 1 4 20 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7574 13:53:55.615839 1 4 24 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
7575 13:53:55.622340 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 13:53:55.625849 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7577 13:53:55.629114 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 13:53:55.636257 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 13:53:55.639456 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 13:53:55.642539 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7581 13:53:55.648999 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7582 13:53:55.652557 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7583 13:53:55.655744 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 13:53:55.662684 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 13:53:55.665924 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 13:53:55.669452 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 13:53:55.676146 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 13:53:55.679255 1 6 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7589 13:53:55.682599 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7590 13:53:55.689285 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7591 13:53:55.693285 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 13:53:55.695652 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 13:53:55.699220 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 13:53:55.705642 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 13:53:55.709275 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 13:53:55.712187 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7597 13:53:55.719037 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7598 13:53:55.721921 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7599 13:53:55.725472 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 13:53:55.732116 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 13:53:55.735712 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 13:53:55.739196 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 13:53:55.745646 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 13:53:55.749073 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 13:53:55.752362 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 13:53:55.759132 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 13:53:55.762285 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 13:53:55.765523 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 13:53:55.772053 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 13:53:55.775407 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 13:53:55.778899 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 13:53:55.785738 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7613 13:53:55.788584 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7614 13:53:55.792637 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7615 13:53:55.795868 Total UI for P1: 0, mck2ui 16
7616 13:53:55.799211 best dqsien dly found for B0: ( 1, 9, 18)
7617 13:53:55.802383 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 13:53:55.805223 Total UI for P1: 0, mck2ui 16
7619 13:53:55.809074 best dqsien dly found for B1: ( 1, 9, 22)
7620 13:53:55.813221 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7621 13:53:55.818955 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7622 13:53:55.819404
7623 13:53:55.822880 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7624 13:53:55.825517 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7625 13:53:55.828885 [Gating] SW calibration Done
7626 13:53:55.829427 ==
7627 13:53:55.831923 Dram Type= 6, Freq= 0, CH_0, rank 0
7628 13:53:55.835966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7629 13:53:55.836410 ==
7630 13:53:55.836913 RX Vref Scan: 0
7631 13:53:55.838962
7632 13:53:55.839552 RX Vref 0 -> 0, step: 1
7633 13:53:55.840005
7634 13:53:55.842374 RX Delay 0 -> 252, step: 8
7635 13:53:55.845606 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7636 13:53:55.849213 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7637 13:53:55.855586 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7638 13:53:55.858972 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7639 13:53:55.862794 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7640 13:53:55.865794 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7641 13:53:55.869312 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7642 13:53:55.876110 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7643 13:53:55.878977 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7644 13:53:55.882510 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7645 13:53:55.885551 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7646 13:53:55.889428 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7647 13:53:55.893226 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7648 13:53:55.899479 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7649 13:53:55.902910 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7650 13:53:55.906186 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7651 13:53:55.906784 ==
7652 13:53:55.909808 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 13:53:55.913247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 13:53:55.915791 ==
7655 13:53:55.916210 DQS Delay:
7656 13:53:55.916543 DQS0 = 0, DQS1 = 0
7657 13:53:55.919066 DQM Delay:
7658 13:53:55.919480 DQM0 = 132, DQM1 = 125
7659 13:53:55.922364 DQ Delay:
7660 13:53:55.926262 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7661 13:53:55.929357 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7662 13:53:55.932872 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7663 13:53:55.936511 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7664 13:53:55.937026
7665 13:53:55.937358
7666 13:53:55.937665 ==
7667 13:53:55.939350 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 13:53:55.942313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 13:53:55.942788 ==
7670 13:53:55.943126
7671 13:53:55.943438
7672 13:53:55.946040 TX Vref Scan disable
7673 13:53:55.949361 == TX Byte 0 ==
7674 13:53:55.952713 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7675 13:53:55.955896 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7676 13:53:55.959516 == TX Byte 1 ==
7677 13:53:55.962372 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7678 13:53:55.966138 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7679 13:53:55.966711 ==
7680 13:53:55.969348 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 13:53:55.972223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 13:53:55.976068 ==
7683 13:53:55.987738
7684 13:53:55.990888 TX Vref early break, caculate TX vref
7685 13:53:55.994825 TX Vref=16, minBit 1, minWin=22, winSum=365
7686 13:53:55.997795 TX Vref=18, minBit 7, minWin=22, winSum=369
7687 13:53:56.001120 TX Vref=20, minBit 7, minWin=22, winSum=383
7688 13:53:56.004067 TX Vref=22, minBit 0, minWin=24, winSum=393
7689 13:53:56.007750 TX Vref=24, minBit 2, minWin=24, winSum=405
7690 13:53:56.014343 TX Vref=26, minBit 1, minWin=25, winSum=412
7691 13:53:56.017551 TX Vref=28, minBit 4, minWin=25, winSum=418
7692 13:53:56.020669 TX Vref=30, minBit 3, minWin=25, winSum=418
7693 13:53:56.023891 TX Vref=32, minBit 2, minWin=24, winSum=408
7694 13:53:56.027292 TX Vref=34, minBit 2, minWin=23, winSum=393
7695 13:53:56.034206 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
7696 13:53:56.034748
7697 13:53:56.037917 Final TX Range 0 Vref 28
7698 13:53:56.038474
7699 13:53:56.038815 ==
7700 13:53:56.040961 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 13:53:56.044971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 13:53:56.045561 ==
7703 13:53:56.045914
7704 13:53:56.046224
7705 13:53:56.047715 TX Vref Scan disable
7706 13:53:56.054209 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7707 13:53:56.054673 == TX Byte 0 ==
7708 13:53:56.057658 u2DelayCellOfst[0]=14 cells (4 PI)
7709 13:53:56.060645 u2DelayCellOfst[1]=21 cells (6 PI)
7710 13:53:56.064551 u2DelayCellOfst[2]=14 cells (4 PI)
7711 13:53:56.067420 u2DelayCellOfst[3]=17 cells (5 PI)
7712 13:53:56.070984 u2DelayCellOfst[4]=10 cells (3 PI)
7713 13:53:56.074221 u2DelayCellOfst[5]=0 cells (0 PI)
7714 13:53:56.077554 u2DelayCellOfst[6]=21 cells (6 PI)
7715 13:53:56.077973 u2DelayCellOfst[7]=21 cells (6 PI)
7716 13:53:56.084500 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7717 13:53:56.088027 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7718 13:53:56.088445 == TX Byte 1 ==
7719 13:53:56.091384 u2DelayCellOfst[8]=0 cells (0 PI)
7720 13:53:56.094574 u2DelayCellOfst[9]=0 cells (0 PI)
7721 13:53:56.097951 u2DelayCellOfst[10]=7 cells (2 PI)
7722 13:53:56.101018 u2DelayCellOfst[11]=0 cells (0 PI)
7723 13:53:56.104461 u2DelayCellOfst[12]=14 cells (4 PI)
7724 13:53:56.107997 u2DelayCellOfst[13]=10 cells (3 PI)
7725 13:53:56.110768 u2DelayCellOfst[14]=17 cells (5 PI)
7726 13:53:56.114605 u2DelayCellOfst[15]=10 cells (3 PI)
7727 13:53:56.118022 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7728 13:53:56.120876 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7729 13:53:56.124234 DramC Write-DBI on
7730 13:53:56.124655 ==
7731 13:53:56.127914 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 13:53:56.131112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 13:53:56.131539 ==
7734 13:53:56.131926
7735 13:53:56.132247
7736 13:53:56.134686 TX Vref Scan disable
7737 13:53:56.137857 == TX Byte 0 ==
7738 13:53:56.141034 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7739 13:53:56.144850 == TX Byte 1 ==
7740 13:53:56.147873 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7741 13:53:56.148470 DramC Write-DBI off
7742 13:53:56.148867
7743 13:53:56.151472 [DATLAT]
7744 13:53:56.151985 Freq=1600, CH0 RK0
7745 13:53:56.152396
7746 13:53:56.154454 DATLAT Default: 0xf
7747 13:53:56.154921 0, 0xFFFF, sum = 0
7748 13:53:56.157989 1, 0xFFFF, sum = 0
7749 13:53:56.158577 2, 0xFFFF, sum = 0
7750 13:53:56.161001 3, 0xFFFF, sum = 0
7751 13:53:56.161656 4, 0xFFFF, sum = 0
7752 13:53:56.164732 5, 0xFFFF, sum = 0
7753 13:53:56.165258 6, 0xFFFF, sum = 0
7754 13:53:56.167920 7, 0xFFFF, sum = 0
7755 13:53:56.168386 8, 0xFFFF, sum = 0
7756 13:53:56.171148 9, 0xFFFF, sum = 0
7757 13:53:56.174253 10, 0xFFFF, sum = 0
7758 13:53:56.174734 11, 0xFFFF, sum = 0
7759 13:53:56.178154 12, 0xFFFF, sum = 0
7760 13:53:56.178625 13, 0xFFFF, sum = 0
7761 13:53:56.181508 14, 0x0, sum = 1
7762 13:53:56.181933 15, 0x0, sum = 2
7763 13:53:56.184467 16, 0x0, sum = 3
7764 13:53:56.184890 17, 0x0, sum = 4
7765 13:53:56.185231 best_step = 15
7766 13:53:56.185543
7767 13:53:56.188192 ==
7768 13:53:56.190952 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 13:53:56.194665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 13:53:56.195088 ==
7771 13:53:56.195424 RX Vref Scan: 1
7772 13:53:56.195735
7773 13:53:56.198010 Set Vref Range= 24 -> 127
7774 13:53:56.198467
7775 13:53:56.201304 RX Vref 24 -> 127, step: 1
7776 13:53:56.201724
7777 13:53:56.204399 RX Delay 11 -> 252, step: 4
7778 13:53:56.204816
7779 13:53:56.207898 Set Vref, RX VrefLevel [Byte0]: 24
7780 13:53:56.210937 [Byte1]: 24
7781 13:53:56.211355
7782 13:53:56.214909 Set Vref, RX VrefLevel [Byte0]: 25
7783 13:53:56.217479 [Byte1]: 25
7784 13:53:56.217931
7785 13:53:56.221018 Set Vref, RX VrefLevel [Byte0]: 26
7786 13:53:56.224205 [Byte1]: 26
7787 13:53:56.227980
7788 13:53:56.228398 Set Vref, RX VrefLevel [Byte0]: 27
7789 13:53:56.231173 [Byte1]: 27
7790 13:53:56.235681
7791 13:53:56.236112 Set Vref, RX VrefLevel [Byte0]: 28
7792 13:53:56.238212 [Byte1]: 28
7793 13:53:56.243221
7794 13:53:56.243747 Set Vref, RX VrefLevel [Byte0]: 29
7795 13:53:56.245886 [Byte1]: 29
7796 13:53:56.250348
7797 13:53:56.250809 Set Vref, RX VrefLevel [Byte0]: 30
7798 13:53:56.253790 [Byte1]: 30
7799 13:53:56.258006
7800 13:53:56.262003 Set Vref, RX VrefLevel [Byte0]: 31
7801 13:53:56.262636 [Byte1]: 31
7802 13:53:56.265749
7803 13:53:56.266455 Set Vref, RX VrefLevel [Byte0]: 32
7804 13:53:56.268900 [Byte1]: 32
7805 13:53:56.273681
7806 13:53:56.274095 Set Vref, RX VrefLevel [Byte0]: 33
7807 13:53:56.277130 [Byte1]: 33
7808 13:53:56.281259
7809 13:53:56.281741 Set Vref, RX VrefLevel [Byte0]: 34
7810 13:53:56.284404 [Byte1]: 34
7811 13:53:56.289006
7812 13:53:56.289519 Set Vref, RX VrefLevel [Byte0]: 35
7813 13:53:56.291733 [Byte1]: 35
7814 13:53:56.296453
7815 13:53:56.297085 Set Vref, RX VrefLevel [Byte0]: 36
7816 13:53:56.299468 [Byte1]: 36
7817 13:53:56.303702
7818 13:53:56.304205 Set Vref, RX VrefLevel [Byte0]: 37
7819 13:53:56.306860 [Byte1]: 37
7820 13:53:56.311583
7821 13:53:56.311998 Set Vref, RX VrefLevel [Byte0]: 38
7822 13:53:56.314731 [Byte1]: 38
7823 13:53:56.318987
7824 13:53:56.319402 Set Vref, RX VrefLevel [Byte0]: 39
7825 13:53:56.322121 [Byte1]: 39
7826 13:53:56.326927
7827 13:53:56.327439 Set Vref, RX VrefLevel [Byte0]: 40
7828 13:53:56.330559 [Byte1]: 40
7829 13:53:56.334742
7830 13:53:56.335286 Set Vref, RX VrefLevel [Byte0]: 41
7831 13:53:56.337588 [Byte1]: 41
7832 13:53:56.341927
7833 13:53:56.342508 Set Vref, RX VrefLevel [Byte0]: 42
7834 13:53:56.345009 [Byte1]: 42
7835 13:53:56.349482
7836 13:53:56.349992 Set Vref, RX VrefLevel [Byte0]: 43
7837 13:53:56.352733 [Byte1]: 43
7838 13:53:56.357705
7839 13:53:56.358218 Set Vref, RX VrefLevel [Byte0]: 44
7840 13:53:56.361224 [Byte1]: 44
7841 13:53:56.365049
7842 13:53:56.365504 Set Vref, RX VrefLevel [Byte0]: 45
7843 13:53:56.368089 [Byte1]: 45
7844 13:53:56.372208
7845 13:53:56.372626 Set Vref, RX VrefLevel [Byte0]: 46
7846 13:53:56.376147 [Byte1]: 46
7847 13:53:56.380330
7848 13:53:56.380830 Set Vref, RX VrefLevel [Byte0]: 47
7849 13:53:56.383294 [Byte1]: 47
7850 13:53:56.387227
7851 13:53:56.387854 Set Vref, RX VrefLevel [Byte0]: 48
7852 13:53:56.391012 [Byte1]: 48
7853 13:53:56.395413
7854 13:53:56.396015 Set Vref, RX VrefLevel [Byte0]: 49
7855 13:53:56.398208 [Byte1]: 49
7856 13:53:56.403213
7857 13:53:56.403664 Set Vref, RX VrefLevel [Byte0]: 50
7858 13:53:56.406325 [Byte1]: 50
7859 13:53:56.410469
7860 13:53:56.410910 Set Vref, RX VrefLevel [Byte0]: 51
7861 13:53:56.413828 [Byte1]: 51
7862 13:53:56.417795
7863 13:53:56.418214 Set Vref, RX VrefLevel [Byte0]: 52
7864 13:53:56.420943 [Byte1]: 52
7865 13:53:56.425485
7866 13:53:56.425950 Set Vref, RX VrefLevel [Byte0]: 53
7867 13:53:56.428891 [Byte1]: 53
7868 13:53:56.433479
7869 13:53:56.433933 Set Vref, RX VrefLevel [Byte0]: 54
7870 13:53:56.436301 [Byte1]: 54
7871 13:53:56.440979
7872 13:53:56.441393 Set Vref, RX VrefLevel [Byte0]: 55
7873 13:53:56.444149 [Byte1]: 55
7874 13:53:56.448493
7875 13:53:56.449007 Set Vref, RX VrefLevel [Byte0]: 56
7876 13:53:56.451718 [Byte1]: 56
7877 13:53:56.456088
7878 13:53:56.456590 Set Vref, RX VrefLevel [Byte0]: 57
7879 13:53:56.459162 [Byte1]: 57
7880 13:53:56.463701
7881 13:53:56.464117 Set Vref, RX VrefLevel [Byte0]: 58
7882 13:53:56.467328 [Byte1]: 58
7883 13:53:56.471842
7884 13:53:56.472453 Set Vref, RX VrefLevel [Byte0]: 59
7885 13:53:56.474846 [Byte1]: 59
7886 13:53:56.478654
7887 13:53:56.479260 Set Vref, RX VrefLevel [Byte0]: 60
7888 13:53:56.482054 [Byte1]: 60
7889 13:53:56.486490
7890 13:53:56.486909 Set Vref, RX VrefLevel [Byte0]: 61
7891 13:53:56.489898 [Byte1]: 61
7892 13:53:56.494113
7893 13:53:56.494552 Set Vref, RX VrefLevel [Byte0]: 62
7894 13:53:56.497458 [Byte1]: 62
7895 13:53:56.501712
7896 13:53:56.502130 Set Vref, RX VrefLevel [Byte0]: 63
7897 13:53:56.505534 [Byte1]: 63
7898 13:53:56.509551
7899 13:53:56.510083 Set Vref, RX VrefLevel [Byte0]: 64
7900 13:53:56.512814 [Byte1]: 64
7901 13:53:56.517246
7902 13:53:56.517713 Set Vref, RX VrefLevel [Byte0]: 65
7903 13:53:56.520539 [Byte1]: 65
7904 13:53:56.524443
7905 13:53:56.524851 Set Vref, RX VrefLevel [Byte0]: 66
7906 13:53:56.527933 [Byte1]: 66
7907 13:53:56.532134
7908 13:53:56.532649 Set Vref, RX VrefLevel [Byte0]: 67
7909 13:53:56.535635 [Byte1]: 67
7910 13:53:56.539548
7911 13:53:56.539956 Set Vref, RX VrefLevel [Byte0]: 68
7912 13:53:56.543045 [Byte1]: 68
7913 13:53:56.547181
7914 13:53:56.547599 Set Vref, RX VrefLevel [Byte0]: 69
7915 13:53:56.550527 [Byte1]: 69
7916 13:53:56.555200
7917 13:53:56.555617 Set Vref, RX VrefLevel [Byte0]: 70
7918 13:53:56.558594 [Byte1]: 70
7919 13:53:56.563030
7920 13:53:56.563566 Set Vref, RX VrefLevel [Byte0]: 71
7921 13:53:56.565740 [Byte1]: 71
7922 13:53:56.570389
7923 13:53:56.571040 Set Vref, RX VrefLevel [Byte0]: 72
7924 13:53:56.574165 [Byte1]: 72
7925 13:53:56.578193
7926 13:53:56.578761 Set Vref, RX VrefLevel [Byte0]: 73
7927 13:53:56.581115 [Byte1]: 73
7928 13:53:56.585367
7929 13:53:56.585829 Set Vref, RX VrefLevel [Byte0]: 74
7930 13:53:56.589490 [Byte1]: 74
7931 13:53:56.593585
7932 13:53:56.594094 Set Vref, RX VrefLevel [Byte0]: 75
7933 13:53:56.596433 [Byte1]: 75
7934 13:53:56.601431
7935 13:53:56.601943 Set Vref, RX VrefLevel [Byte0]: 76
7936 13:53:56.604739 [Byte1]: 76
7937 13:53:56.608522
7938 13:53:56.609087 Final RX Vref Byte 0 = 53 to rank0
7939 13:53:56.611931 Final RX Vref Byte 1 = 61 to rank0
7940 13:53:56.615204 Final RX Vref Byte 0 = 53 to rank1
7941 13:53:56.618437 Final RX Vref Byte 1 = 61 to rank1==
7942 13:53:56.621985 Dram Type= 6, Freq= 0, CH_0, rank 0
7943 13:53:56.624936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 13:53:56.628326 ==
7945 13:53:56.628840 DQS Delay:
7946 13:53:56.629209 DQS0 = 0, DQS1 = 0
7947 13:53:56.631848 DQM Delay:
7948 13:53:56.632259 DQM0 = 129, DQM1 = 122
7949 13:53:56.635199 DQ Delay:
7950 13:53:56.638448 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7951 13:53:56.641504 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =138
7952 13:53:56.644842 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7953 13:53:56.648298 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =134
7954 13:53:56.648738
7955 13:53:56.649156
7956 13:53:56.649481
7957 13:53:56.652139 [DramC_TX_OE_Calibration] TA2
7958 13:53:56.655118 Original DQ_B0 (3 6) =30, OEN = 27
7959 13:53:56.658225 Original DQ_B1 (3 6) =30, OEN = 27
7960 13:53:56.658744 24, 0x0, End_B0=24 End_B1=24
7961 13:53:56.661931 25, 0x0, End_B0=25 End_B1=25
7962 13:53:56.665028 26, 0x0, End_B0=26 End_B1=26
7963 13:53:56.668800 27, 0x0, End_B0=27 End_B1=27
7964 13:53:56.672209 28, 0x0, End_B0=28 End_B1=28
7965 13:53:56.672729 29, 0x0, End_B0=29 End_B1=29
7966 13:53:56.675556 30, 0x0, End_B0=30 End_B1=30
7967 13:53:56.678654 31, 0x4141, End_B0=30 End_B1=30
7968 13:53:56.681836 Byte0 end_step=30 best_step=27
7969 13:53:56.685427 Byte1 end_step=30 best_step=27
7970 13:53:56.688530 Byte0 TX OE(2T, 0.5T) = (3, 3)
7971 13:53:56.688950 Byte1 TX OE(2T, 0.5T) = (3, 3)
7972 13:53:56.689284
7973 13:53:56.689592
7974 13:53:56.698315 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7975 13:53:56.702188 CH0 RK0: MR19=303, MR18=1307
7976 13:53:56.708455 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
7977 13:53:56.708890
7978 13:53:56.712130 ----->DramcWriteLeveling(PI) begin...
7979 13:53:56.712553 ==
7980 13:53:56.714828 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 13:53:56.718585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 13:53:56.719006 ==
7983 13:53:56.722069 Write leveling (Byte 0): 35 => 35
7984 13:53:56.725081 Write leveling (Byte 1): 27 => 27
7985 13:53:56.728545 DramcWriteLeveling(PI) end<-----
7986 13:53:56.728979
7987 13:53:56.729305 ==
7988 13:53:56.731607 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 13:53:56.735059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 13:53:56.735552 ==
7991 13:53:56.738536 [Gating] SW mode calibration
7992 13:53:56.744679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7993 13:53:56.751379 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7994 13:53:56.754824 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 13:53:56.758367 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 13:53:56.764882 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 13:53:56.768116 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7998 13:53:56.771690 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7999 13:53:56.778336 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8000 13:53:56.781382 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 13:53:56.784643 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 13:53:56.788388 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 13:53:56.795062 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 13:53:56.798140 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8005 13:53:56.802347 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8006 13:53:56.808512 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8007 13:53:56.811539 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8008 13:53:56.814880 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 13:53:56.821454 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 13:53:56.825339 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 13:53:56.828111 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 13:53:56.835383 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8013 13:53:56.838314 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8014 13:53:56.841814 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8015 13:53:56.848267 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8016 13:53:56.851732 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 13:53:56.854904 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 13:53:56.861321 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 13:53:56.864717 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 13:53:56.868124 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 13:53:56.875051 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8022 13:53:56.878118 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8023 13:53:56.881667 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8024 13:53:56.885372 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8025 13:53:56.891461 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 13:53:56.895371 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 13:53:56.898855 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 13:53:56.905590 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 13:53:56.908468 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 13:53:56.911562 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 13:53:56.918868 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 13:53:56.921935 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 13:53:56.925198 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 13:53:56.931692 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 13:53:56.934896 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 13:53:56.938233 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8037 13:53:56.945120 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8038 13:53:56.948534 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8039 13:53:56.951894 Total UI for P1: 0, mck2ui 16
8040 13:53:56.954934 best dqsien dly found for B0: ( 1, 9, 10)
8041 13:53:56.958387 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8042 13:53:56.962104 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 13:53:56.965021 Total UI for P1: 0, mck2ui 16
8044 13:53:56.968949 best dqsien dly found for B1: ( 1, 9, 18)
8045 13:53:56.971502 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8046 13:53:56.978208 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8047 13:53:56.978291
8048 13:53:56.981424 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8049 13:53:56.984970 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8050 13:53:56.988412 [Gating] SW calibration Done
8051 13:53:56.988495 ==
8052 13:53:56.991494 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 13:53:56.995039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 13:53:56.995123 ==
8055 13:53:56.995206 RX Vref Scan: 0
8056 13:53:56.995304
8057 13:53:56.998270 RX Vref 0 -> 0, step: 1
8058 13:53:56.998377
8059 13:53:57.001491 RX Delay 0 -> 252, step: 8
8060 13:53:57.005084 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8061 13:53:57.008773 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8062 13:53:57.012327 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8063 13:53:57.018648 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8064 13:53:57.021801 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8065 13:53:57.025680 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8066 13:53:57.029081 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8067 13:53:57.032195 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8068 13:53:57.039568 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8069 13:53:57.043073 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8070 13:53:57.045929 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8071 13:53:57.048953 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8072 13:53:57.052769 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8073 13:53:57.059375 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8074 13:53:57.062786 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8075 13:53:57.065849 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8076 13:53:57.066276 ==
8077 13:53:57.069056 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 13:53:57.072846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 13:53:57.073272 ==
8080 13:53:57.076005 DQS Delay:
8081 13:53:57.076531 DQS0 = 0, DQS1 = 0
8082 13:53:57.079406 DQM Delay:
8083 13:53:57.079930 DQM0 = 131, DQM1 = 125
8084 13:53:57.080401 DQ Delay:
8085 13:53:57.085644 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8086 13:53:57.089239 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8087 13:53:57.092011 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8088 13:53:57.095517 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
8089 13:53:57.095941
8090 13:53:57.096397
8091 13:53:57.096804 ==
8092 13:53:57.099019 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 13:53:57.102259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 13:53:57.102765 ==
8095 13:53:57.103197
8096 13:53:57.103604
8097 13:53:57.105882 TX Vref Scan disable
8098 13:53:57.109105 == TX Byte 0 ==
8099 13:53:57.112098 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8100 13:53:57.115598 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8101 13:53:57.118863 == TX Byte 1 ==
8102 13:53:57.122081 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8103 13:53:57.125653 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8104 13:53:57.126165 ==
8105 13:53:57.129006 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 13:53:57.135418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 13:53:57.135943 ==
8108 13:53:57.149298
8109 13:53:57.152821 TX Vref early break, caculate TX vref
8110 13:53:57.155564 TX Vref=16, minBit 9, minWin=22, winSum=377
8111 13:53:57.159327 TX Vref=18, minBit 8, minWin=23, winSum=388
8112 13:53:57.162376 TX Vref=20, minBit 9, minWin=23, winSum=391
8113 13:53:57.166158 TX Vref=22, minBit 3, minWin=24, winSum=404
8114 13:53:57.169259 TX Vref=24, minBit 9, minWin=24, winSum=408
8115 13:53:57.175677 TX Vref=26, minBit 4, minWin=25, winSum=420
8116 13:53:57.178862 TX Vref=28, minBit 3, minWin=26, winSum=426
8117 13:53:57.182097 TX Vref=30, minBit 2, minWin=25, winSum=421
8118 13:53:57.185601 TX Vref=32, minBit 8, minWin=25, winSum=418
8119 13:53:57.189479 TX Vref=34, minBit 8, minWin=24, winSum=410
8120 13:53:57.192130 TX Vref=36, minBit 4, minWin=24, winSum=402
8121 13:53:57.199007 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 28
8122 13:53:57.199514
8123 13:53:57.202541 Final TX Range 0 Vref 28
8124 13:53:57.203006
8125 13:53:57.203371 ==
8126 13:53:57.205714 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 13:53:57.208963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 13:53:57.209543 ==
8129 13:53:57.209918
8130 13:53:57.210261
8131 13:53:57.212338 TX Vref Scan disable
8132 13:53:57.219014 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8133 13:53:57.219483 == TX Byte 0 ==
8134 13:53:57.222491 u2DelayCellOfst[0]=14 cells (4 PI)
8135 13:53:57.225624 u2DelayCellOfst[1]=21 cells (6 PI)
8136 13:53:57.228450 u2DelayCellOfst[2]=10 cells (3 PI)
8137 13:53:57.231920 u2DelayCellOfst[3]=14 cells (4 PI)
8138 13:53:57.235669 u2DelayCellOfst[4]=10 cells (3 PI)
8139 13:53:57.238751 u2DelayCellOfst[5]=0 cells (0 PI)
8140 13:53:57.242033 u2DelayCellOfst[6]=17 cells (5 PI)
8141 13:53:57.245268 u2DelayCellOfst[7]=21 cells (6 PI)
8142 13:53:57.248960 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8143 13:53:57.252959 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8144 13:53:57.255544 == TX Byte 1 ==
8145 13:53:57.258534 u2DelayCellOfst[8]=0 cells (0 PI)
8146 13:53:57.258972 u2DelayCellOfst[9]=0 cells (0 PI)
8147 13:53:57.262928 u2DelayCellOfst[10]=7 cells (2 PI)
8148 13:53:57.265368 u2DelayCellOfst[11]=0 cells (0 PI)
8149 13:53:57.269195 u2DelayCellOfst[12]=10 cells (3 PI)
8150 13:53:57.272613 u2DelayCellOfst[13]=10 cells (3 PI)
8151 13:53:57.275512 u2DelayCellOfst[14]=14 cells (4 PI)
8152 13:53:57.279117 u2DelayCellOfst[15]=10 cells (3 PI)
8153 13:53:57.282883 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8154 13:53:57.288927 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8155 13:53:57.289467 DramC Write-DBI on
8156 13:53:57.289924 ==
8157 13:53:57.292351 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 13:53:57.295927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 13:53:57.299596 ==
8160 13:53:57.300136
8161 13:53:57.300588
8162 13:53:57.301008 TX Vref Scan disable
8163 13:53:57.302376 == TX Byte 0 ==
8164 13:53:57.306247 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8165 13:53:57.309676 == TX Byte 1 ==
8166 13:53:57.312543 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8167 13:53:57.315724 DramC Write-DBI off
8168 13:53:57.316270
8169 13:53:57.316724 [DATLAT]
8170 13:53:57.317146 Freq=1600, CH0 RK1
8171 13:53:57.317560
8172 13:53:57.319132 DATLAT Default: 0xf
8173 13:53:57.319564 0, 0xFFFF, sum = 0
8174 13:53:57.322475 1, 0xFFFF, sum = 0
8175 13:53:57.323014 2, 0xFFFF, sum = 0
8176 13:53:57.325952 3, 0xFFFF, sum = 0
8177 13:53:57.329113 4, 0xFFFF, sum = 0
8178 13:53:57.329557 5, 0xFFFF, sum = 0
8179 13:53:57.332671 6, 0xFFFF, sum = 0
8180 13:53:57.333220 7, 0xFFFF, sum = 0
8181 13:53:57.335609 8, 0xFFFF, sum = 0
8182 13:53:57.336049 9, 0xFFFF, sum = 0
8183 13:53:57.338916 10, 0xFFFF, sum = 0
8184 13:53:57.339354 11, 0xFFFF, sum = 0
8185 13:53:57.342478 12, 0xFFFF, sum = 0
8186 13:53:57.343030 13, 0xFFFF, sum = 0
8187 13:53:57.345928 14, 0x0, sum = 1
8188 13:53:57.346369 15, 0x0, sum = 2
8189 13:53:57.348908 16, 0x0, sum = 3
8190 13:53:57.349348 17, 0x0, sum = 4
8191 13:53:57.352402 best_step = 15
8192 13:53:57.352937
8193 13:53:57.353393 ==
8194 13:53:57.355792 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 13:53:57.359109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 13:53:57.359553 ==
8197 13:53:57.360004 RX Vref Scan: 0
8198 13:53:57.362349
8199 13:53:57.362931 RX Vref 0 -> 0, step: 1
8200 13:53:57.363392
8201 13:53:57.365956 RX Delay 11 -> 252, step: 4
8202 13:53:57.369372 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8203 13:53:57.375999 iDelay=191, Bit 1, Center 128 (75 ~ 182) 108
8204 13:53:57.379138 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8205 13:53:57.382784 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8206 13:53:57.386033 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8207 13:53:57.389056 iDelay=191, Bit 5, Center 116 (59 ~ 174) 116
8208 13:53:57.392575 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8209 13:53:57.398931 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8210 13:53:57.402724 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8211 13:53:57.406308 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8212 13:53:57.409137 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8213 13:53:57.412150 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8214 13:53:57.419352 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8215 13:53:57.422734 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8216 13:53:57.425679 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8217 13:53:57.429094 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8218 13:53:57.429579 ==
8219 13:53:57.432267 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 13:53:57.439360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 13:53:57.439781 ==
8222 13:53:57.440353 DQS Delay:
8223 13:53:57.442657 DQS0 = 0, DQS1 = 0
8224 13:53:57.443185 DQM Delay:
8225 13:53:57.443792 DQM0 = 126, DQM1 = 122
8226 13:53:57.445844 DQ Delay:
8227 13:53:57.449179 DQ0 =126, DQ1 =128, DQ2 =122, DQ3 =126
8228 13:53:57.452823 DQ4 =126, DQ5 =116, DQ6 =134, DQ7 =136
8229 13:53:57.455698 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8230 13:53:57.459256 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8231 13:53:57.459817
8232 13:53:57.460168
8233 13:53:57.460544
8234 13:53:57.462817 [DramC_TX_OE_Calibration] TA2
8235 13:53:57.465481 Original DQ_B0 (3 6) =30, OEN = 27
8236 13:53:57.468993 Original DQ_B1 (3 6) =30, OEN = 27
8237 13:53:57.472623 24, 0x0, End_B0=24 End_B1=24
8238 13:53:57.473212 25, 0x0, End_B0=25 End_B1=25
8239 13:53:57.476499 26, 0x0, End_B0=26 End_B1=26
8240 13:53:57.478847 27, 0x0, End_B0=27 End_B1=27
8241 13:53:57.482874 28, 0x0, End_B0=28 End_B1=28
8242 13:53:57.485805 29, 0x0, End_B0=29 End_B1=29
8243 13:53:57.486494 30, 0x0, End_B0=30 End_B1=30
8244 13:53:57.488959 31, 0x4141, End_B0=30 End_B1=30
8245 13:53:57.492493 Byte0 end_step=30 best_step=27
8246 13:53:57.495396 Byte1 end_step=30 best_step=27
8247 13:53:57.499213 Byte0 TX OE(2T, 0.5T) = (3, 3)
8248 13:53:57.502759 Byte1 TX OE(2T, 0.5T) = (3, 3)
8249 13:53:57.503058
8250 13:53:57.503296
8251 13:53:57.509108 [DQSOSCAuto] RK1, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8252 13:53:57.512178 CH0 RK1: MR19=303, MR18=1509
8253 13:53:57.519013 CH0_RK1: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8254 13:53:57.522758 [RxdqsGatingPostProcess] freq 1600
8255 13:53:57.525561 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8256 13:53:57.529011 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 13:53:57.532331 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 13:53:57.535257 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 13:53:57.539180 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 13:53:57.542368 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 13:53:57.545839 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 13:53:57.548859 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 13:53:57.552236 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 13:53:57.555969 Pre-setting of DQS Precalculation
8265 13:53:57.558784 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8266 13:53:57.559083 ==
8267 13:53:57.562712 Dram Type= 6, Freq= 0, CH_1, rank 0
8268 13:53:57.565607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 13:53:57.565919 ==
8270 13:53:57.572100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 13:53:57.575225 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 13:53:57.581848 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 13:53:57.584984 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 13:53:57.595490 [CA 0] Center 41 (13~70) winsize 58
8275 13:53:57.598390 [CA 1] Center 42 (13~72) winsize 60
8276 13:53:57.602137 [CA 2] Center 37 (8~66) winsize 59
8277 13:53:57.605176 [CA 3] Center 36 (8~65) winsize 58
8278 13:53:57.608699 [CA 4] Center 37 (8~67) winsize 60
8279 13:53:57.611637 [CA 5] Center 36 (7~66) winsize 60
8280 13:53:57.611737
8281 13:53:57.615556 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8282 13:53:57.615664
8283 13:53:57.618405 [CATrainingPosCal] consider 1 rank data
8284 13:53:57.621883 u2DelayCellTimex100 = 275/100 ps
8285 13:53:57.625508 CA0 delay=41 (13~70),Diff = 5 PI (17 cell)
8286 13:53:57.631994 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8287 13:53:57.635458 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8288 13:53:57.638298 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8289 13:53:57.641922 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8290 13:53:57.645844 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8291 13:53:57.646036
8292 13:53:57.648716 CA PerBit enable=1, Macro0, CA PI delay=36
8293 13:53:57.648898
8294 13:53:57.651898 [CBTSetCACLKResult] CA Dly = 36
8295 13:53:57.652070 CS Dly: 9 (0~40)
8296 13:53:57.658875 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 13:53:57.661832 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 13:53:57.662144 ==
8299 13:53:57.665611 Dram Type= 6, Freq= 0, CH_1, rank 1
8300 13:53:57.668382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 13:53:57.668754 ==
8302 13:53:57.675487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 13:53:57.678904 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 13:53:57.685204 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 13:53:57.688799 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 13:53:57.698460 [CA 0] Center 42 (13~72) winsize 60
8307 13:53:57.702168 [CA 1] Center 43 (14~72) winsize 59
8308 13:53:57.705433 [CA 2] Center 37 (8~66) winsize 59
8309 13:53:57.708724 [CA 3] Center 37 (8~66) winsize 59
8310 13:53:57.711807 [CA 4] Center 37 (8~67) winsize 60
8311 13:53:57.715436 [CA 5] Center 36 (7~66) winsize 60
8312 13:53:57.715939
8313 13:53:57.718748 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8314 13:53:57.719298
8315 13:53:57.722109 [CATrainingPosCal] consider 2 rank data
8316 13:53:57.725192 u2DelayCellTimex100 = 275/100 ps
8317 13:53:57.729133 CA0 delay=41 (13~70),Diff = 5 PI (17 cell)
8318 13:53:57.735621 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8319 13:53:57.738531 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 13:53:57.742636 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8321 13:53:57.745474 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8322 13:53:57.749063 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8323 13:53:57.749553
8324 13:53:57.752169 CA PerBit enable=1, Macro0, CA PI delay=36
8325 13:53:57.752542
8326 13:53:57.755384 [CBTSetCACLKResult] CA Dly = 36
8327 13:53:57.758813 CS Dly: 10 (0~43)
8328 13:53:57.762266 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 13:53:57.766065 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 13:53:57.766627
8331 13:53:57.768863 ----->DramcWriteLeveling(PI) begin...
8332 13:53:57.769430 ==
8333 13:53:57.772005 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 13:53:57.775311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 13:53:57.775746 ==
8336 13:53:57.779184 Write leveling (Byte 0): 23 => 23
8337 13:53:57.782061 Write leveling (Byte 1): 28 => 28
8338 13:53:57.785260 DramcWriteLeveling(PI) end<-----
8339 13:53:57.785685
8340 13:53:57.786013 ==
8341 13:53:57.788828 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 13:53:57.795085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 13:53:57.795516 ==
8344 13:53:57.795846 [Gating] SW mode calibration
8345 13:53:57.805327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8346 13:53:57.809351 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8347 13:53:57.812456 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 13:53:57.819168 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 13:53:57.822673 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 13:53:57.825411 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 13:53:57.832191 1 4 16 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
8352 13:53:57.835436 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 13:53:57.838793 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 13:53:57.845266 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 13:53:57.849144 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 13:53:57.852109 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 13:53:57.859344 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 13:53:57.862332 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8359 13:53:57.865331 1 5 16 | B1->B0 | 2e2e 3333 | 0 1 | (0 1) (1 0)
8360 13:53:57.869041 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8361 13:53:57.876251 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 13:53:57.878762 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 13:53:57.881995 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 13:53:57.888826 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 13:53:57.892312 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 13:53:57.895269 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 13:53:57.901971 1 6 16 | B1->B0 | 4444 3434 | 0 0 | (0 0) (0 0)
8368 13:53:57.905202 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 13:53:57.908676 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 13:53:57.915428 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 13:53:57.919148 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 13:53:57.922106 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 13:53:57.928959 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 13:53:57.932365 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 13:53:57.935415 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8376 13:53:57.942010 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 13:53:57.946472 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 13:53:57.948592 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 13:53:57.955575 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 13:53:57.959176 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 13:53:57.961874 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 13:53:57.968906 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 13:53:57.972297 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 13:53:57.975424 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 13:53:57.978870 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 13:53:57.985686 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 13:53:57.988959 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 13:53:57.992259 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 13:53:57.998823 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 13:53:58.002802 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8391 13:53:58.005609 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8392 13:53:58.012337 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 13:53:58.012773 Total UI for P1: 0, mck2ui 16
8394 13:53:58.019276 best dqsien dly found for B0: ( 1, 9, 14)
8395 13:53:58.019914 Total UI for P1: 0, mck2ui 16
8396 13:53:58.025465 best dqsien dly found for B1: ( 1, 9, 14)
8397 13:53:58.028774 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8398 13:53:58.032214 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8399 13:53:58.032629
8400 13:53:58.035915 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8401 13:53:58.039329 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8402 13:53:58.042673 [Gating] SW calibration Done
8403 13:53:58.043088 ==
8404 13:53:58.045586 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 13:53:58.049164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 13:53:58.049584 ==
8407 13:53:58.052790 RX Vref Scan: 0
8408 13:53:58.053216
8409 13:53:58.053548 RX Vref 0 -> 0, step: 1
8410 13:53:58.053859
8411 13:53:58.055431 RX Delay 0 -> 252, step: 8
8412 13:53:58.059215 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8413 13:53:58.065737 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8414 13:53:58.069130 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8415 13:53:58.072819 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8416 13:53:58.075621 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8417 13:53:58.078741 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8418 13:53:58.082502 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8419 13:53:58.089156 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8420 13:53:58.092315 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8421 13:53:58.095594 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8422 13:53:58.098683 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8423 13:53:58.102181 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8424 13:53:58.109062 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8425 13:53:58.112292 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8426 13:53:58.115110 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8427 13:53:58.118594 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8428 13:53:58.122030 ==
8429 13:53:58.122586 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 13:53:58.128910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 13:53:58.129426 ==
8432 13:53:58.129763 DQS Delay:
8433 13:53:58.132490 DQS0 = 0, DQS1 = 0
8434 13:53:58.132902 DQM Delay:
8435 13:53:58.136112 DQM0 = 134, DQM1 = 127
8436 13:53:58.136622 DQ Delay:
8437 13:53:58.138771 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8438 13:53:58.142810 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8439 13:53:58.145900 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8440 13:53:58.149048 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8441 13:53:58.149561
8442 13:53:58.149894
8443 13:53:58.150205 ==
8444 13:53:58.152259 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 13:53:58.158851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 13:53:58.159370 ==
8447 13:53:58.159713
8448 13:53:58.160021
8449 13:53:58.160315 TX Vref Scan disable
8450 13:53:58.162128 == TX Byte 0 ==
8451 13:53:58.165415 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8452 13:53:58.171996 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8453 13:53:58.172510 == TX Byte 1 ==
8454 13:53:58.175346 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8455 13:53:58.182165 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8456 13:53:58.182717 ==
8457 13:53:58.185415 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 13:53:58.188878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 13:53:58.189433 ==
8460 13:53:58.201197
8461 13:53:58.204804 TX Vref early break, caculate TX vref
8462 13:53:58.208196 TX Vref=16, minBit 8, minWin=21, winSum=363
8463 13:53:58.211251 TX Vref=18, minBit 5, minWin=22, winSum=375
8464 13:53:58.214705 TX Vref=20, minBit 8, minWin=22, winSum=387
8465 13:53:58.218014 TX Vref=22, minBit 8, minWin=22, winSum=392
8466 13:53:58.221211 TX Vref=24, minBit 5, minWin=24, winSum=408
8467 13:53:58.228142 TX Vref=26, minBit 8, minWin=24, winSum=413
8468 13:53:58.231406 TX Vref=28, minBit 8, minWin=24, winSum=419
8469 13:53:58.234547 TX Vref=30, minBit 8, minWin=25, winSum=423
8470 13:53:58.238219 TX Vref=32, minBit 0, minWin=25, winSum=412
8471 13:53:58.241042 TX Vref=34, minBit 11, minWin=23, winSum=398
8472 13:53:58.247835 [TxChooseVref] Worse bit 8, Min win 25, Win sum 423, Final Vref 30
8473 13:53:58.248293
8474 13:53:58.251082 Final TX Range 0 Vref 30
8475 13:53:58.251505
8476 13:53:58.251836 ==
8477 13:53:58.254484 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 13:53:58.257978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 13:53:58.258527 ==
8480 13:53:58.258867
8481 13:53:58.259246
8482 13:53:58.261545 TX Vref Scan disable
8483 13:53:58.267656 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8484 13:53:58.268085 == TX Byte 0 ==
8485 13:53:58.271375 u2DelayCellOfst[0]=17 cells (5 PI)
8486 13:53:58.274628 u2DelayCellOfst[1]=14 cells (4 PI)
8487 13:53:58.277594 u2DelayCellOfst[2]=0 cells (0 PI)
8488 13:53:58.281496 u2DelayCellOfst[3]=7 cells (2 PI)
8489 13:53:58.284185 u2DelayCellOfst[4]=10 cells (3 PI)
8490 13:53:58.287591 u2DelayCellOfst[5]=17 cells (5 PI)
8491 13:53:58.291043 u2DelayCellOfst[6]=17 cells (5 PI)
8492 13:53:58.291455 u2DelayCellOfst[7]=7 cells (2 PI)
8493 13:53:58.297903 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8494 13:53:58.301278 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8495 13:53:58.301721 == TX Byte 1 ==
8496 13:53:58.304410 u2DelayCellOfst[8]=0 cells (0 PI)
8497 13:53:58.307366 u2DelayCellOfst[9]=7 cells (2 PI)
8498 13:53:58.310969 u2DelayCellOfst[10]=10 cells (3 PI)
8499 13:53:58.314499 u2DelayCellOfst[11]=7 cells (2 PI)
8500 13:53:58.317792 u2DelayCellOfst[12]=14 cells (4 PI)
8501 13:53:58.320862 u2DelayCellOfst[13]=17 cells (5 PI)
8502 13:53:58.324586 u2DelayCellOfst[14]=17 cells (5 PI)
8503 13:53:58.327907 u2DelayCellOfst[15]=17 cells (5 PI)
8504 13:53:58.330878 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8505 13:53:58.334590 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8506 13:53:58.337960 DramC Write-DBI on
8507 13:53:58.338626 ==
8508 13:53:58.341166 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 13:53:58.344523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 13:53:58.344944 ==
8511 13:53:58.347494
8512 13:53:58.348002
8513 13:53:58.348342 TX Vref Scan disable
8514 13:53:58.351081 == TX Byte 0 ==
8515 13:53:58.354784 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8516 13:53:58.357864 == TX Byte 1 ==
8517 13:53:58.361496 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8518 13:53:58.362011 DramC Write-DBI off
8519 13:53:58.362348
8520 13:53:58.364667 [DATLAT]
8521 13:53:58.365103 Freq=1600, CH1 RK0
8522 13:53:58.365441
8523 13:53:58.367307 DATLAT Default: 0xf
8524 13:53:58.367790 0, 0xFFFF, sum = 0
8525 13:53:58.371034 1, 0xFFFF, sum = 0
8526 13:53:58.371454 2, 0xFFFF, sum = 0
8527 13:53:58.374751 3, 0xFFFF, sum = 0
8528 13:53:58.375169 4, 0xFFFF, sum = 0
8529 13:53:58.377528 5, 0xFFFF, sum = 0
8530 13:53:58.378056 6, 0xFFFF, sum = 0
8531 13:53:58.381423 7, 0xFFFF, sum = 0
8532 13:53:58.381950 8, 0xFFFF, sum = 0
8533 13:53:58.384510 9, 0xFFFF, sum = 0
8534 13:53:58.387734 10, 0xFFFF, sum = 0
8535 13:53:58.388200 11, 0xFFFF, sum = 0
8536 13:53:58.391128 12, 0xFFFF, sum = 0
8537 13:53:58.391550 13, 0xFFFF, sum = 0
8538 13:53:58.394576 14, 0x0, sum = 1
8539 13:53:58.395097 15, 0x0, sum = 2
8540 13:53:58.397975 16, 0x0, sum = 3
8541 13:53:58.398551 17, 0x0, sum = 4
8542 13:53:58.398901 best_step = 15
8543 13:53:58.399214
8544 13:53:58.401325 ==
8545 13:53:58.404174 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 13:53:58.407756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 13:53:58.408318 ==
8548 13:53:58.408666 RX Vref Scan: 1
8549 13:53:58.408980
8550 13:53:58.410920 Set Vref Range= 24 -> 127
8551 13:53:58.411331
8552 13:53:58.414724 RX Vref 24 -> 127, step: 1
8553 13:53:58.415138
8554 13:53:58.418017 RX Delay 11 -> 252, step: 4
8555 13:53:58.418471
8556 13:53:58.421209 Set Vref, RX VrefLevel [Byte0]: 24
8557 13:53:58.424440 [Byte1]: 24
8558 13:53:58.424958
8559 13:53:58.427915 Set Vref, RX VrefLevel [Byte0]: 25
8560 13:53:58.431513 [Byte1]: 25
8561 13:53:58.432030
8562 13:53:58.434492 Set Vref, RX VrefLevel [Byte0]: 26
8563 13:53:58.437485 [Byte1]: 26
8564 13:53:58.440810
8565 13:53:58.441222 Set Vref, RX VrefLevel [Byte0]: 27
8566 13:53:58.443991 [Byte1]: 27
8567 13:53:58.448344
8568 13:53:58.448768 Set Vref, RX VrefLevel [Byte0]: 28
8569 13:53:58.452109 [Byte1]: 28
8570 13:53:58.456491
8571 13:53:58.456900 Set Vref, RX VrefLevel [Byte0]: 29
8572 13:53:58.459960 [Byte1]: 29
8573 13:53:58.463874
8574 13:53:58.464386 Set Vref, RX VrefLevel [Byte0]: 30
8575 13:53:58.467303 [Byte1]: 30
8576 13:53:58.471625
8577 13:53:58.472142 Set Vref, RX VrefLevel [Byte0]: 31
8578 13:53:58.474794 [Byte1]: 31
8579 13:53:58.479181
8580 13:53:58.479739 Set Vref, RX VrefLevel [Byte0]: 32
8581 13:53:58.482577 [Byte1]: 32
8582 13:53:58.486810
8583 13:53:58.487263 Set Vref, RX VrefLevel [Byte0]: 33
8584 13:53:58.489758 [Byte1]: 33
8585 13:53:58.494505
8586 13:53:58.495058 Set Vref, RX VrefLevel [Byte0]: 34
8587 13:53:58.498255 [Byte1]: 34
8588 13:53:58.502087
8589 13:53:58.502576 Set Vref, RX VrefLevel [Byte0]: 35
8590 13:53:58.505157 [Byte1]: 35
8591 13:53:58.509478
8592 13:53:58.509935 Set Vref, RX VrefLevel [Byte0]: 36
8593 13:53:58.512956 [Byte1]: 36
8594 13:53:58.516868
8595 13:53:58.517414 Set Vref, RX VrefLevel [Byte0]: 37
8596 13:53:58.520884 [Byte1]: 37
8597 13:53:58.524884
8598 13:53:58.525297 Set Vref, RX VrefLevel [Byte0]: 38
8599 13:53:58.528507 [Byte1]: 38
8600 13:53:58.532360
8601 13:53:58.532869 Set Vref, RX VrefLevel [Byte0]: 39
8602 13:53:58.535506 [Byte1]: 39
8603 13:53:58.540059
8604 13:53:58.540474 Set Vref, RX VrefLevel [Byte0]: 40
8605 13:53:58.543016 [Byte1]: 40
8606 13:53:58.547673
8607 13:53:58.548154 Set Vref, RX VrefLevel [Byte0]: 41
8608 13:53:58.550710 [Byte1]: 41
8609 13:53:58.555691
8610 13:53:58.556104 Set Vref, RX VrefLevel [Byte0]: 42
8611 13:53:58.558745 [Byte1]: 42
8612 13:53:58.562636
8613 13:53:58.563145 Set Vref, RX VrefLevel [Byte0]: 43
8614 13:53:58.566549 [Byte1]: 43
8615 13:53:58.570779
8616 13:53:58.571192 Set Vref, RX VrefLevel [Byte0]: 44
8617 13:53:58.573694 [Byte1]: 44
8618 13:53:58.578202
8619 13:53:58.578772 Set Vref, RX VrefLevel [Byte0]: 45
8620 13:53:58.581445 [Byte1]: 45
8621 13:53:58.586444
8622 13:53:58.587006 Set Vref, RX VrefLevel [Byte0]: 46
8623 13:53:58.589215 [Byte1]: 46
8624 13:53:58.593432
8625 13:53:58.593884 Set Vref, RX VrefLevel [Byte0]: 47
8626 13:53:58.596418 [Byte1]: 47
8627 13:53:58.600799
8628 13:53:58.601278 Set Vref, RX VrefLevel [Byte0]: 48
8629 13:53:58.604411 [Byte1]: 48
8630 13:53:58.608520
8631 13:53:58.609008 Set Vref, RX VrefLevel [Byte0]: 49
8632 13:53:58.611629 [Byte1]: 49
8633 13:53:58.616372
8634 13:53:58.616782 Set Vref, RX VrefLevel [Byte0]: 50
8635 13:53:58.619509 [Byte1]: 50
8636 13:53:58.623468
8637 13:53:58.623881 Set Vref, RX VrefLevel [Byte0]: 51
8638 13:53:58.626876 [Byte1]: 51
8639 13:53:58.631337
8640 13:53:58.631906 Set Vref, RX VrefLevel [Byte0]: 52
8641 13:53:58.634475 [Byte1]: 52
8642 13:53:58.639047
8643 13:53:58.639588 Set Vref, RX VrefLevel [Byte0]: 53
8644 13:53:58.641889 [Byte1]: 53
8645 13:53:58.646673
8646 13:53:58.647084 Set Vref, RX VrefLevel [Byte0]: 54
8647 13:53:58.649655 [Byte1]: 54
8648 13:53:58.654448
8649 13:53:58.655065 Set Vref, RX VrefLevel [Byte0]: 55
8650 13:53:58.657562 [Byte1]: 55
8651 13:53:58.661637
8652 13:53:58.662264 Set Vref, RX VrefLevel [Byte0]: 56
8653 13:53:58.665211 [Byte1]: 56
8654 13:53:58.669484
8655 13:53:58.669960 Set Vref, RX VrefLevel [Byte0]: 57
8656 13:53:58.672519 [Byte1]: 57
8657 13:53:58.677193
8658 13:53:58.677771 Set Vref, RX VrefLevel [Byte0]: 58
8659 13:53:58.680152 [Byte1]: 58
8660 13:53:58.684911
8661 13:53:58.685325 Set Vref, RX VrefLevel [Byte0]: 59
8662 13:53:58.687976 [Byte1]: 59
8663 13:53:58.692575
8664 13:53:58.692987 Set Vref, RX VrefLevel [Byte0]: 60
8665 13:53:58.695247 [Byte1]: 60
8666 13:53:58.700000
8667 13:53:58.700421 Set Vref, RX VrefLevel [Byte0]: 61
8668 13:53:58.703268 [Byte1]: 61
8669 13:53:58.707136
8670 13:53:58.707736 Set Vref, RX VrefLevel [Byte0]: 62
8671 13:53:58.710788 [Byte1]: 62
8672 13:53:58.714884
8673 13:53:58.715292 Set Vref, RX VrefLevel [Byte0]: 63
8674 13:53:58.718521 [Byte1]: 63
8675 13:53:58.722812
8676 13:53:58.723328 Set Vref, RX VrefLevel [Byte0]: 64
8677 13:53:58.726247 [Byte1]: 64
8678 13:53:58.730578
8679 13:53:58.731080 Set Vref, RX VrefLevel [Byte0]: 65
8680 13:53:58.733789 [Byte1]: 65
8681 13:53:58.737768
8682 13:53:58.738276 Set Vref, RX VrefLevel [Byte0]: 66
8683 13:53:58.744629 [Byte1]: 66
8684 13:53:58.745069
8685 13:53:58.747530 Set Vref, RX VrefLevel [Byte0]: 67
8686 13:53:58.750942 [Byte1]: 67
8687 13:53:58.751448
8688 13:53:58.754383 Set Vref, RX VrefLevel [Byte0]: 68
8689 13:53:58.757498 [Byte1]: 68
8690 13:53:58.758071
8691 13:53:58.761206 Set Vref, RX VrefLevel [Byte0]: 69
8692 13:53:58.764453 [Byte1]: 69
8693 13:53:58.768448
8694 13:53:58.768917 Set Vref, RX VrefLevel [Byte0]: 70
8695 13:53:58.771429 [Byte1]: 70
8696 13:53:58.776042
8697 13:53:58.776456 Set Vref, RX VrefLevel [Byte0]: 71
8698 13:53:58.779683 [Byte1]: 71
8699 13:53:58.783706
8700 13:53:58.784218 Set Vref, RX VrefLevel [Byte0]: 72
8701 13:53:58.786887 [Byte1]: 72
8702 13:53:58.791175
8703 13:53:58.791635 Set Vref, RX VrefLevel [Byte0]: 73
8704 13:53:58.795454 [Byte1]: 73
8705 13:53:58.799065
8706 13:53:58.799586 Set Vref, RX VrefLevel [Byte0]: 74
8707 13:53:58.802578 [Byte1]: 74
8708 13:53:58.806456
8709 13:53:58.806868 Set Vref, RX VrefLevel [Byte0]: 75
8710 13:53:58.809639 [Byte1]: 75
8711 13:53:58.814217
8712 13:53:58.814683 Final RX Vref Byte 0 = 57 to rank0
8713 13:53:58.817759 Final RX Vref Byte 1 = 56 to rank0
8714 13:53:58.820649 Final RX Vref Byte 0 = 57 to rank1
8715 13:53:58.823903 Final RX Vref Byte 1 = 56 to rank1==
8716 13:53:58.827744 Dram Type= 6, Freq= 0, CH_1, rank 0
8717 13:53:58.830605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 13:53:58.834749 ==
8719 13:53:58.835299 DQS Delay:
8720 13:53:58.835648 DQS0 = 0, DQS1 = 0
8721 13:53:58.837548 DQM Delay:
8722 13:53:58.837961 DQM0 = 131, DQM1 = 124
8723 13:53:58.840494 DQ Delay:
8724 13:53:58.844000 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8725 13:53:58.848059 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
8726 13:53:58.850899 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8727 13:53:58.854421 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8728 13:53:58.854940
8729 13:53:58.855268
8730 13:53:58.855573
8731 13:53:58.858131 [DramC_TX_OE_Calibration] TA2
8732 13:53:58.861138 Original DQ_B0 (3 6) =30, OEN = 27
8733 13:53:58.864496 Original DQ_B1 (3 6) =30, OEN = 27
8734 13:53:58.867344 24, 0x0, End_B0=24 End_B1=24
8735 13:53:58.867781 25, 0x0, End_B0=25 End_B1=25
8736 13:53:58.870611 26, 0x0, End_B0=26 End_B1=26
8737 13:53:58.874534 27, 0x0, End_B0=27 End_B1=27
8738 13:53:58.877564 28, 0x0, End_B0=28 End_B1=28
8739 13:53:58.878126 29, 0x0, End_B0=29 End_B1=29
8740 13:53:58.880821 30, 0x0, End_B0=30 End_B1=30
8741 13:53:58.884606 31, 0x4141, End_B0=30 End_B1=30
8742 13:53:58.887608 Byte0 end_step=30 best_step=27
8743 13:53:58.891058 Byte1 end_step=30 best_step=27
8744 13:53:58.894006 Byte0 TX OE(2T, 0.5T) = (3, 3)
8745 13:53:58.894499 Byte1 TX OE(2T, 0.5T) = (3, 3)
8746 13:53:58.894871
8747 13:53:58.897508
8748 13:53:58.904045 [DQSOSCAuto] RK0, (LSB)MR18= 0x1804, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
8749 13:53:58.907119 CH1 RK0: MR19=303, MR18=1804
8750 13:53:58.913929 CH1_RK0: MR19=0x303, MR18=0x1804, DQSOSC=397, MR23=63, INC=23, DEC=15
8751 13:53:58.914473
8752 13:53:58.917960 ----->DramcWriteLeveling(PI) begin...
8753 13:53:58.918528 ==
8754 13:53:58.920534 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 13:53:58.924494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 13:53:58.925031 ==
8757 13:53:58.927882 Write leveling (Byte 0): 25 => 25
8758 13:53:58.930703 Write leveling (Byte 1): 28 => 28
8759 13:53:58.934333 DramcWriteLeveling(PI) end<-----
8760 13:53:58.934916
8761 13:53:58.935257 ==
8762 13:53:58.937484 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 13:53:58.940854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 13:53:58.941320 ==
8765 13:53:58.944151 [Gating] SW mode calibration
8766 13:53:58.950696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8767 13:53:58.957202 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8768 13:53:58.960933 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 13:53:58.964476 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 13:53:58.970593 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8771 13:53:58.973873 1 4 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
8772 13:53:58.977484 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 13:53:58.983838 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 13:53:58.987377 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 13:53:58.990906 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 13:53:58.994254 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 13:53:59.001556 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 13:53:59.003873 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8779 13:53:59.007182 1 5 12 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
8780 13:53:59.013926 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8781 13:53:59.017440 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 13:53:59.020558 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 13:53:59.027245 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 13:53:59.030603 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 13:53:59.034140 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 13:53:59.040570 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8787 13:53:59.044078 1 6 12 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
8788 13:53:59.047862 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 13:53:59.054355 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 13:53:59.057449 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 13:53:59.060902 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 13:53:59.067589 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 13:53:59.070886 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 13:53:59.074329 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8795 13:53:59.080533 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8796 13:53:59.084048 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8797 13:53:59.087405 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 13:53:59.090873 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 13:53:59.097595 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 13:53:59.100588 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 13:53:59.104124 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 13:53:59.110902 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 13:53:59.114322 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 13:53:59.117623 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 13:53:59.124314 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 13:53:59.127511 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 13:53:59.130629 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 13:53:59.137951 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 13:53:59.140661 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8810 13:53:59.144166 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8811 13:53:59.150940 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8812 13:53:59.151449 Total UI for P1: 0, mck2ui 16
8813 13:53:59.157654 best dqsien dly found for B0: ( 1, 9, 6)
8814 13:53:59.160779 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8815 13:53:59.164245 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 13:53:59.167644 Total UI for P1: 0, mck2ui 16
8817 13:53:59.170729 best dqsien dly found for B1: ( 1, 9, 14)
8818 13:53:59.174255 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8819 13:53:59.177915 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8820 13:53:59.178530
8821 13:53:59.181042 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8822 13:53:59.187758 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8823 13:53:59.188326 [Gating] SW calibration Done
8824 13:53:59.188696 ==
8825 13:53:59.190790 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 13:53:59.198099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 13:53:59.198700 ==
8828 13:53:59.199067 RX Vref Scan: 0
8829 13:53:59.199403
8830 13:53:59.200832 RX Vref 0 -> 0, step: 1
8831 13:53:59.201299
8832 13:53:59.204467 RX Delay 0 -> 252, step: 8
8833 13:53:59.207350 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8834 13:53:59.210961 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8835 13:53:59.214686 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8836 13:53:59.217568 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8837 13:53:59.224380 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8838 13:53:59.227110 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8839 13:53:59.231042 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8840 13:53:59.234473 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8841 13:53:59.237720 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8842 13:53:59.244700 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8843 13:53:59.247645 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8844 13:53:59.251241 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8845 13:53:59.254950 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8846 13:53:59.257699 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8847 13:53:59.264383 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8848 13:53:59.268174 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8849 13:53:59.268761 ==
8850 13:53:59.271358 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 13:53:59.274692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 13:53:59.275338 ==
8853 13:53:59.277404 DQS Delay:
8854 13:53:59.277855 DQS0 = 0, DQS1 = 0
8855 13:53:59.278212 DQM Delay:
8856 13:53:59.281022 DQM0 = 132, DQM1 = 127
8857 13:53:59.281600 DQ Delay:
8858 13:53:59.284500 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8859 13:53:59.287706 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8860 13:53:59.290912 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8861 13:53:59.297617 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8862 13:53:59.298137
8863 13:53:59.298534
8864 13:53:59.298874 ==
8865 13:53:59.301397 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 13:53:59.303989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 13:53:59.304523 ==
8868 13:53:59.304888
8869 13:53:59.305225
8870 13:53:59.307292 TX Vref Scan disable
8871 13:53:59.307747 == TX Byte 0 ==
8872 13:53:59.314058 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8873 13:53:59.317853 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8874 13:53:59.318299 == TX Byte 1 ==
8875 13:53:59.324434 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8876 13:53:59.327631 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8877 13:53:59.328046 ==
8878 13:53:59.331061 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 13:53:59.334513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 13:53:59.334964 ==
8881 13:53:59.349530
8882 13:53:59.352457 TX Vref early break, caculate TX vref
8883 13:53:59.355409 TX Vref=16, minBit 8, minWin=22, winSum=378
8884 13:53:59.359468 TX Vref=18, minBit 8, minWin=23, winSum=386
8885 13:53:59.362053 TX Vref=20, minBit 8, minWin=23, winSum=395
8886 13:53:59.365673 TX Vref=22, minBit 8, minWin=24, winSum=404
8887 13:53:59.369157 TX Vref=24, minBit 8, minWin=24, winSum=410
8888 13:53:59.375914 TX Vref=26, minBit 8, minWin=25, winSum=417
8889 13:53:59.379327 TX Vref=28, minBit 5, minWin=25, winSum=422
8890 13:53:59.382355 TX Vref=30, minBit 0, minWin=25, winSum=418
8891 13:53:59.386172 TX Vref=32, minBit 0, minWin=25, winSum=410
8892 13:53:59.389197 TX Vref=34, minBit 8, minWin=24, winSum=400
8893 13:53:59.392521 TX Vref=36, minBit 0, minWin=23, winSum=395
8894 13:53:59.399405 [TxChooseVref] Worse bit 5, Min win 25, Win sum 422, Final Vref 28
8895 13:53:59.399910
8896 13:53:59.402358 Final TX Range 0 Vref 28
8897 13:53:59.402831
8898 13:53:59.403160 ==
8899 13:53:59.406465 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 13:53:59.409485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 13:53:59.410015 ==
8902 13:53:59.410534
8903 13:53:59.410859
8904 13:53:59.412655 TX Vref Scan disable
8905 13:53:59.419361 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8906 13:53:59.419799 == TX Byte 0 ==
8907 13:53:59.422343 u2DelayCellOfst[0]=17 cells (5 PI)
8908 13:53:59.426007 u2DelayCellOfst[1]=10 cells (3 PI)
8909 13:53:59.429633 u2DelayCellOfst[2]=0 cells (0 PI)
8910 13:53:59.432222 u2DelayCellOfst[3]=7 cells (2 PI)
8911 13:53:59.436324 u2DelayCellOfst[4]=7 cells (2 PI)
8912 13:53:59.439596 u2DelayCellOfst[5]=17 cells (5 PI)
8913 13:53:59.442357 u2DelayCellOfst[6]=17 cells (5 PI)
8914 13:53:59.442813 u2DelayCellOfst[7]=7 cells (2 PI)
8915 13:53:59.449015 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8916 13:53:59.452780 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8917 13:53:59.453266 == TX Byte 1 ==
8918 13:53:59.456414 u2DelayCellOfst[8]=0 cells (0 PI)
8919 13:53:59.459618 u2DelayCellOfst[9]=3 cells (1 PI)
8920 13:53:59.462454 u2DelayCellOfst[10]=10 cells (3 PI)
8921 13:53:59.465981 u2DelayCellOfst[11]=7 cells (2 PI)
8922 13:53:59.469206 u2DelayCellOfst[12]=14 cells (4 PI)
8923 13:53:59.472625 u2DelayCellOfst[13]=14 cells (4 PI)
8924 13:53:59.476302 u2DelayCellOfst[14]=17 cells (5 PI)
8925 13:53:59.479160 u2DelayCellOfst[15]=14 cells (4 PI)
8926 13:53:59.482451 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8927 13:53:59.486022 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8928 13:53:59.489408 DramC Write-DBI on
8929 13:53:59.489843 ==
8930 13:53:59.492740 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 13:53:59.496017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 13:53:59.496430 ==
8933 13:53:59.496758
8934 13:53:59.497060
8935 13:53:59.499102 TX Vref Scan disable
8936 13:53:59.502480 == TX Byte 0 ==
8937 13:53:59.505725 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8938 13:53:59.509583 == TX Byte 1 ==
8939 13:53:59.512878 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8940 13:53:59.513295 DramC Write-DBI off
8941 13:53:59.513626
8942 13:53:59.516257 [DATLAT]
8943 13:53:59.516664 Freq=1600, CH1 RK1
8944 13:53:59.516993
8945 13:53:59.518988 DATLAT Default: 0xf
8946 13:53:59.519400 0, 0xFFFF, sum = 0
8947 13:53:59.522730 1, 0xFFFF, sum = 0
8948 13:53:59.523172 2, 0xFFFF, sum = 0
8949 13:53:59.525944 3, 0xFFFF, sum = 0
8950 13:53:59.526392 4, 0xFFFF, sum = 0
8951 13:53:59.529590 5, 0xFFFF, sum = 0
8952 13:53:59.530034 6, 0xFFFF, sum = 0
8953 13:53:59.532483 7, 0xFFFF, sum = 0
8954 13:53:59.532904 8, 0xFFFF, sum = 0
8955 13:53:59.535936 9, 0xFFFF, sum = 0
8956 13:53:59.539236 10, 0xFFFF, sum = 0
8957 13:53:59.539856 11, 0xFFFF, sum = 0
8958 13:53:59.542881 12, 0xFFFF, sum = 0
8959 13:53:59.543310 13, 0xFFFF, sum = 0
8960 13:53:59.545941 14, 0x0, sum = 1
8961 13:53:59.546481 15, 0x0, sum = 2
8962 13:53:59.549176 16, 0x0, sum = 3
8963 13:53:59.549596 17, 0x0, sum = 4
8964 13:53:59.549931 best_step = 15
8965 13:53:59.550470
8966 13:53:59.552490 ==
8967 13:53:59.555867 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 13:53:59.559349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 13:53:59.559767 ==
8970 13:53:59.560163 RX Vref Scan: 0
8971 13:53:59.560480
8972 13:53:59.562699 RX Vref 0 -> 0, step: 1
8973 13:53:59.563113
8974 13:53:59.566056 RX Delay 11 -> 252, step: 4
8975 13:53:59.569144 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8976 13:53:59.572563 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8977 13:53:59.579632 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8978 13:53:59.582668 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8979 13:53:59.586292 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8980 13:53:59.589707 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8981 13:53:59.592596 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8982 13:53:59.596062 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8983 13:53:59.602676 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8984 13:53:59.605942 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8985 13:53:59.609194 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8986 13:53:59.612504 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8987 13:53:59.616611 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8988 13:53:59.622905 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8989 13:53:59.626334 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8990 13:53:59.629553 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
8991 13:53:59.630068 ==
8992 13:53:59.633163 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 13:53:59.636429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 13:53:59.636977 ==
8995 13:53:59.639488 DQS Delay:
8996 13:53:59.639947 DQS0 = 0, DQS1 = 0
8997 13:53:59.642850 DQM Delay:
8998 13:53:59.643403 DQM0 = 129, DQM1 = 125
8999 13:53:59.646386 DQ Delay:
9000 13:53:59.649516 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9001 13:53:59.652938 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9002 13:53:59.656422 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =116
9003 13:53:59.660026 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9004 13:53:59.660566
9005 13:53:59.661015
9006 13:53:59.661433
9007 13:53:59.662904 [DramC_TX_OE_Calibration] TA2
9008 13:53:59.666476 Original DQ_B0 (3 6) =30, OEN = 27
9009 13:53:59.669609 Original DQ_B1 (3 6) =30, OEN = 27
9010 13:53:59.670056 24, 0x0, End_B0=24 End_B1=24
9011 13:53:59.672980 25, 0x0, End_B0=25 End_B1=25
9012 13:53:59.676466 26, 0x0, End_B0=26 End_B1=26
9013 13:53:59.679594 27, 0x0, End_B0=27 End_B1=27
9014 13:53:59.682826 28, 0x0, End_B0=28 End_B1=28
9015 13:53:59.683267 29, 0x0, End_B0=29 End_B1=29
9016 13:53:59.686245 30, 0x0, End_B0=30 End_B1=30
9017 13:53:59.689687 31, 0x5151, End_B0=30 End_B1=30
9018 13:53:59.692739 Byte0 end_step=30 best_step=27
9019 13:53:59.696392 Byte1 end_step=30 best_step=27
9020 13:53:59.696827 Byte0 TX OE(2T, 0.5T) = (3, 3)
9021 13:53:59.700125 Byte1 TX OE(2T, 0.5T) = (3, 3)
9022 13:53:59.700685
9023 13:53:59.701143
9024 13:53:59.709694 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9025 13:53:59.713389 CH1 RK1: MR19=303, MR18=1117
9026 13:53:59.716236 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9027 13:53:59.719791 [RxdqsGatingPostProcess] freq 1600
9028 13:53:59.726736 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9029 13:53:59.730180 best DQS0 dly(2T, 0.5T) = (1, 1)
9030 13:53:59.733259 best DQS1 dly(2T, 0.5T) = (1, 1)
9031 13:53:59.736472 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9032 13:53:59.739711 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9033 13:53:59.743300 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 13:53:59.743726 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 13:53:59.746284 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 13:53:59.749728 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 13:53:59.753318 Pre-setting of DQS Precalculation
9038 13:53:59.759576 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9039 13:53:59.766666 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9040 13:53:59.773506 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9041 13:53:59.774029
9042 13:53:59.774451
9043 13:53:59.777056 [Calibration Summary] 3200 Mbps
9044 13:53:59.777665 CH 0, Rank 0
9045 13:53:59.779692 SW Impedance : PASS
9046 13:53:59.783648 DUTY Scan : NO K
9047 13:53:59.784210 ZQ Calibration : PASS
9048 13:53:59.786556 Jitter Meter : NO K
9049 13:53:59.790124 CBT Training : PASS
9050 13:53:59.790632 Write leveling : PASS
9051 13:53:59.793499 RX DQS gating : PASS
9052 13:53:59.796489 RX DQ/DQS(RDDQC) : PASS
9053 13:53:59.796947 TX DQ/DQS : PASS
9054 13:53:59.800659 RX DATLAT : PASS
9055 13:53:59.801218 RX DQ/DQS(Engine): PASS
9056 13:53:59.803568 TX OE : PASS
9057 13:53:59.804082 All Pass.
9058 13:53:59.804460
9059 13:53:59.806867 CH 0, Rank 1
9060 13:53:59.807324 SW Impedance : PASS
9061 13:53:59.810025 DUTY Scan : NO K
9062 13:53:59.813126 ZQ Calibration : PASS
9063 13:53:59.813583 Jitter Meter : NO K
9064 13:53:59.816669 CBT Training : PASS
9065 13:53:59.819853 Write leveling : PASS
9066 13:53:59.820312 RX DQS gating : PASS
9067 13:53:59.823243 RX DQ/DQS(RDDQC) : PASS
9068 13:53:59.827122 TX DQ/DQS : PASS
9069 13:53:59.827539 RX DATLAT : PASS
9070 13:53:59.830105 RX DQ/DQS(Engine): PASS
9071 13:53:59.833367 TX OE : PASS
9072 13:53:59.833886 All Pass.
9073 13:53:59.834218
9074 13:53:59.834570 CH 1, Rank 0
9075 13:53:59.836909 SW Impedance : PASS
9076 13:53:59.837432 DUTY Scan : NO K
9077 13:53:59.839877 ZQ Calibration : PASS
9078 13:53:59.843132 Jitter Meter : NO K
9079 13:53:59.843546 CBT Training : PASS
9080 13:53:59.846570 Write leveling : PASS
9081 13:53:59.850254 RX DQS gating : PASS
9082 13:53:59.850774 RX DQ/DQS(RDDQC) : PASS
9083 13:53:59.853510 TX DQ/DQS : PASS
9084 13:53:59.856666 RX DATLAT : PASS
9085 13:53:59.857082 RX DQ/DQS(Engine): PASS
9086 13:53:59.859834 TX OE : PASS
9087 13:53:59.860251 All Pass.
9088 13:53:59.860583
9089 13:53:59.863386 CH 1, Rank 1
9090 13:53:59.863875 SW Impedance : PASS
9091 13:53:59.866568 DUTY Scan : NO K
9092 13:53:59.870454 ZQ Calibration : PASS
9093 13:53:59.870879 Jitter Meter : NO K
9094 13:53:59.873060 CBT Training : PASS
9095 13:53:59.876882 Write leveling : PASS
9096 13:53:59.877433 RX DQS gating : PASS
9097 13:53:59.880123 RX DQ/DQS(RDDQC) : PASS
9098 13:53:59.880708 TX DQ/DQS : PASS
9099 13:53:59.883929 RX DATLAT : PASS
9100 13:53:59.887026 RX DQ/DQS(Engine): PASS
9101 13:53:59.887443 TX OE : PASS
9102 13:53:59.890709 All Pass.
9103 13:53:59.891126
9104 13:53:59.891460 DramC Write-DBI on
9105 13:53:59.893370 PER_BANK_REFRESH: Hybrid Mode
9106 13:53:59.893816 TX_TRACKING: ON
9107 13:53:59.903468 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9108 13:53:59.913399 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9109 13:53:59.920505 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9110 13:53:59.923521 [FAST_K] Save calibration result to emmc
9111 13:53:59.926612 sync common calibartion params.
9112 13:53:59.927039 sync cbt_mode0:1, 1:1
9113 13:53:59.929883 dram_init: ddr_geometry: 2
9114 13:53:59.933523 dram_init: ddr_geometry: 2
9115 13:53:59.933939 dram_init: ddr_geometry: 2
9116 13:53:59.936971 0:dram_rank_size:100000000
9117 13:53:59.940001 1:dram_rank_size:100000000
9118 13:53:59.943525 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9119 13:53:59.946919 DFS_SHUFFLE_HW_MODE: ON
9120 13:53:59.949934 dramc_set_vcore_voltage set vcore to 725000
9121 13:53:59.953266 Read voltage for 1600, 0
9122 13:53:59.953349 Vio18 = 0
9123 13:53:59.956638 Vcore = 725000
9124 13:53:59.956720 Vdram = 0
9125 13:53:59.956784 Vddq = 0
9126 13:53:59.959934 Vmddr = 0
9127 13:53:59.960015 switch to 3200 Mbps bootup
9128 13:53:59.963209 [DramcRunTimeConfig]
9129 13:53:59.963290 PHYPLL
9130 13:53:59.966178 DPM_CONTROL_AFTERK: ON
9131 13:53:59.966285 PER_BANK_REFRESH: ON
9132 13:53:59.969772 REFRESH_OVERHEAD_REDUCTION: ON
9133 13:53:59.973006 CMD_PICG_NEW_MODE: OFF
9134 13:53:59.973087 XRTWTW_NEW_MODE: ON
9135 13:53:59.976692 XRTRTR_NEW_MODE: ON
9136 13:53:59.976778 TX_TRACKING: ON
9137 13:53:59.979877 RDSEL_TRACKING: OFF
9138 13:53:59.983047 DQS Precalculation for DVFS: ON
9139 13:53:59.983129 RX_TRACKING: OFF
9140 13:53:59.986638 HW_GATING DBG: ON
9141 13:53:59.986720 ZQCS_ENABLE_LP4: ON
9142 13:53:59.989813 RX_PICG_NEW_MODE: ON
9143 13:53:59.989894 TX_PICG_NEW_MODE: ON
9144 13:53:59.993244 ENABLE_RX_DCM_DPHY: ON
9145 13:53:59.996443 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9146 13:53:59.999545 DUMMY_READ_FOR_TRACKING: OFF
9147 13:53:59.999625 !!! SPM_CONTROL_AFTERK: OFF
9148 13:54:00.003117 !!! SPM could not control APHY
9149 13:54:00.006467 IMPEDANCE_TRACKING: ON
9150 13:54:00.006569 TEMP_SENSOR: ON
9151 13:54:00.010197 HW_SAVE_FOR_SR: OFF
9152 13:54:00.013464 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9153 13:54:00.016890 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9154 13:54:00.016970 Read ODT Tracking: ON
9155 13:54:00.019841 Refresh Rate DeBounce: ON
9156 13:54:00.023430 DFS_NO_QUEUE_FLUSH: ON
9157 13:54:00.026802 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9158 13:54:00.026879 ENABLE_DFS_RUNTIME_MRW: OFF
9159 13:54:00.030248 DDR_RESERVE_NEW_MODE: ON
9160 13:54:00.032877 MR_CBT_SWITCH_FREQ: ON
9161 13:54:00.032955 =========================
9162 13:54:00.053420 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9163 13:54:00.056242 dram_init: ddr_geometry: 2
9164 13:54:00.074696 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9165 13:54:00.077916 dram_init: dram init end (result: 0)
9166 13:54:00.084858 DRAM-K: Full calibration passed in 24551 msecs
9167 13:54:00.088197 MRC: failed to locate region type 0.
9168 13:54:00.088317 DRAM rank0 size:0x100000000,
9169 13:54:00.091851 DRAM rank1 size=0x100000000
9170 13:54:00.101049 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9171 13:54:00.108407 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9172 13:54:00.114430 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9173 13:54:00.121104 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9174 13:54:00.124255 DRAM rank0 size:0x100000000,
9175 13:54:00.128085 DRAM rank1 size=0x100000000
9176 13:54:00.128214 CBMEM:
9177 13:54:00.131672 IMD: root @ 0xfffff000 254 entries.
9178 13:54:00.134765 IMD: root @ 0xffffec00 62 entries.
9179 13:54:00.137767 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9180 13:54:00.141676 WARNING: RO_VPD is uninitialized or empty.
9181 13:54:00.147473 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9182 13:54:00.154532 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9183 13:54:00.167509 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9184 13:54:00.179190 BS: romstage times (exec / console): total (unknown) / 24056 ms
9185 13:54:00.179283
9186 13:54:00.179355
9187 13:54:00.188975 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9188 13:54:00.192192 ARM64: Exception handlers installed.
9189 13:54:00.195427 ARM64: Testing exception
9190 13:54:00.199093 ARM64: Done test exception
9191 13:54:00.199175 Enumerating buses...
9192 13:54:00.202634 Show all devs... Before device enumeration.
9193 13:54:00.205740 Root Device: enabled 1
9194 13:54:00.209168 CPU_CLUSTER: 0: enabled 1
9195 13:54:00.209241 CPU: 00: enabled 1
9196 13:54:00.212244 Compare with tree...
9197 13:54:00.212323 Root Device: enabled 1
9198 13:54:00.215368 CPU_CLUSTER: 0: enabled 1
9199 13:54:00.219233 CPU: 00: enabled 1
9200 13:54:00.219312 Root Device scanning...
9201 13:54:00.222278 scan_static_bus for Root Device
9202 13:54:00.225974 CPU_CLUSTER: 0 enabled
9203 13:54:00.228970 scan_static_bus for Root Device done
9204 13:54:00.232759 scan_bus: bus Root Device finished in 8 msecs
9205 13:54:00.232838 done
9206 13:54:00.238988 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9207 13:54:00.242240 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9208 13:54:00.248708 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9209 13:54:00.252167 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9210 13:54:00.255795 Allocating resources...
9211 13:54:00.255874 Reading resources...
9212 13:54:00.262286 Root Device read_resources bus 0 link: 0
9213 13:54:00.262379 DRAM rank0 size:0x100000000,
9214 13:54:00.265753 DRAM rank1 size=0x100000000
9215 13:54:00.269225 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9216 13:54:00.272181 CPU: 00 missing read_resources
9217 13:54:00.276087 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9218 13:54:00.282324 Root Device read_resources bus 0 link: 0 done
9219 13:54:00.282462 Done reading resources.
9220 13:54:00.289084 Show resources in subtree (Root Device)...After reading.
9221 13:54:00.291948 Root Device child on link 0 CPU_CLUSTER: 0
9222 13:54:00.295500 CPU_CLUSTER: 0 child on link 0 CPU: 00
9223 13:54:00.305559 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9224 13:54:00.305648 CPU: 00
9225 13:54:00.309272 Root Device assign_resources, bus 0 link: 0
9226 13:54:00.312576 CPU_CLUSTER: 0 missing set_resources
9227 13:54:00.315603 Root Device assign_resources, bus 0 link: 0 done
9228 13:54:00.318913 Done setting resources.
9229 13:54:00.325809 Show resources in subtree (Root Device)...After assigning values.
9230 13:54:00.329014 Root Device child on link 0 CPU_CLUSTER: 0
9231 13:54:00.332402 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 13:54:00.341945 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 13:54:00.342023 CPU: 00
9234 13:54:00.345282 Done allocating resources.
9235 13:54:00.348758 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9236 13:54:00.352672 Enabling resources...
9237 13:54:00.352751 done.
9238 13:54:00.355531 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9239 13:54:00.358650 Initializing devices...
9240 13:54:00.361887 Root Device init
9241 13:54:00.361962 init hardware done!
9242 13:54:00.365517 0x00000018: ctrlr->caps
9243 13:54:00.365597 52.000 MHz: ctrlr->f_max
9244 13:54:00.368887 0.400 MHz: ctrlr->f_min
9245 13:54:00.372025 0x40ff8080: ctrlr->voltages
9246 13:54:00.372113 sclk: 390625
9247 13:54:00.375393 Bus Width = 1
9248 13:54:00.375464 sclk: 390625
9249 13:54:00.375525 Bus Width = 1
9250 13:54:00.378797 Early init status = 3
9251 13:54:00.381923 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9252 13:54:00.387153 in-header: 03 fc 00 00 01 00 00 00
9253 13:54:00.390430 in-data: 00
9254 13:54:00.394111 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9255 13:54:00.398830 in-header: 03 fd 00 00 00 00 00 00
9256 13:54:00.402488 in-data:
9257 13:54:00.406105 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9258 13:54:00.410536 in-header: 03 fc 00 00 01 00 00 00
9259 13:54:00.413582 in-data: 00
9260 13:54:00.416671 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9261 13:54:00.422317 in-header: 03 fd 00 00 00 00 00 00
9262 13:54:00.425843 in-data:
9263 13:54:00.429344 [SSUSB] Setting up USB HOST controller...
9264 13:54:00.432837 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9265 13:54:00.435781 [SSUSB] phy power-on done.
9266 13:54:00.439457 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9267 13:54:00.445759 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9268 13:54:00.449160 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9269 13:54:00.455438 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9270 13:54:00.462189 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9271 13:54:00.468749 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9272 13:54:00.475803 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9273 13:54:00.482046 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9274 13:54:00.482121 SPM: binary array size = 0x9dc
9275 13:54:00.488831 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9276 13:54:00.495536 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9277 13:54:00.502151 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9278 13:54:00.505681 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9279 13:54:00.508822 configure_display: Starting display init
9280 13:54:00.545567 anx7625_power_on_init: Init interface.
9281 13:54:00.548712 anx7625_disable_pd_protocol: Disabled PD feature.
9282 13:54:00.551953 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9283 13:54:00.580302 anx7625_start_dp_work: Secure OCM version=00
9284 13:54:00.583660 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9285 13:54:00.598145 sp_tx_get_edid_block: EDID Block = 1
9286 13:54:00.700533 Extracted contents:
9287 13:54:00.704390 header: 00 ff ff ff ff ff ff 00
9288 13:54:00.707083 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9289 13:54:00.710762 version: 01 04
9290 13:54:00.714139 basic params: 95 1f 11 78 0a
9291 13:54:00.717552 chroma info: 76 90 94 55 54 90 27 21 50 54
9292 13:54:00.720920 established: 00 00 00
9293 13:54:00.727309 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9294 13:54:00.730731 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9295 13:54:00.737316 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9296 13:54:00.743990 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9297 13:54:00.750247 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9298 13:54:00.754502 extensions: 00
9299 13:54:00.754577 checksum: fb
9300 13:54:00.754641
9301 13:54:00.756973 Manufacturer: IVO Model 57d Serial Number 0
9302 13:54:00.760824 Made week 0 of 2020
9303 13:54:00.760900 EDID version: 1.4
9304 13:54:00.764671 Digital display
9305 13:54:00.767156 6 bits per primary color channel
9306 13:54:00.767229 DisplayPort interface
9307 13:54:00.770663 Maximum image size: 31 cm x 17 cm
9308 13:54:00.773613 Gamma: 220%
9309 13:54:00.773684 Check DPMS levels
9310 13:54:00.777186 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9311 13:54:00.780654 First detailed timing is preferred timing
9312 13:54:00.784187 Established timings supported:
9313 13:54:00.787018 Standard timings supported:
9314 13:54:00.787089 Detailed timings
9315 13:54:00.793764 Hex of detail: 383680a07038204018303c0035ae10000019
9316 13:54:00.797333 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9317 13:54:00.800950 0780 0798 07c8 0820 hborder 0
9318 13:54:00.807251 0438 043b 0447 0458 vborder 0
9319 13:54:00.807327 -hsync -vsync
9320 13:54:00.810333 Did detailed timing
9321 13:54:00.814256 Hex of detail: 000000000000000000000000000000000000
9322 13:54:00.817735 Manufacturer-specified data, tag 0
9323 13:54:00.823789 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9324 13:54:00.823896 ASCII string: InfoVision
9325 13:54:00.830486 Hex of detail: 000000fe00523134304e574635205248200a
9326 13:54:00.830566 ASCII string: R140NWF5 RH
9327 13:54:00.833902 Checksum
9328 13:54:00.833982 Checksum: 0xfb (valid)
9329 13:54:00.840682 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9330 13:54:00.840763 DSI data_rate: 832800000 bps
9331 13:54:00.848686 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9332 13:54:00.851855 anx7625_parse_edid: pixelclock(138800).
9333 13:54:00.855097 hactive(1920), hsync(48), hfp(24), hbp(88)
9334 13:54:00.858010 vactive(1080), vsync(12), vfp(3), vbp(17)
9335 13:54:00.861734 anx7625_dsi_config: config dsi.
9336 13:54:00.868536 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9337 13:54:00.882508 anx7625_dsi_config: success to config DSI
9338 13:54:00.885893 anx7625_dp_start: MIPI phy setup OK.
9339 13:54:00.889908 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9340 13:54:00.892661 mtk_ddp_mode_set invalid vrefresh 60
9341 13:54:00.896288 main_disp_path_setup
9342 13:54:00.896368 ovl_layer_smi_id_en
9343 13:54:00.899493 ovl_layer_smi_id_en
9344 13:54:00.899574 ccorr_config
9345 13:54:00.899638 aal_config
9346 13:54:00.902700 gamma_config
9347 13:54:00.902781 postmask_config
9348 13:54:00.905806 dither_config
9349 13:54:00.909876 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9350 13:54:00.916100 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9351 13:54:00.919773 Root Device init finished in 554 msecs
9352 13:54:00.919853 CPU_CLUSTER: 0 init
9353 13:54:00.929431 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9354 13:54:00.932598 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9355 13:54:00.936073 APU_MBOX 0x190000b0 = 0x10001
9356 13:54:00.939484 APU_MBOX 0x190001b0 = 0x10001
9357 13:54:00.942852 APU_MBOX 0x190005b0 = 0x10001
9358 13:54:00.946097 APU_MBOX 0x190006b0 = 0x10001
9359 13:54:00.949306 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9360 13:54:00.961843 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9361 13:54:00.974198 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9362 13:54:00.980923 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9363 13:54:00.992169 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9364 13:54:01.001584 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9365 13:54:01.004960 CPU_CLUSTER: 0 init finished in 81 msecs
9366 13:54:01.008454 Devices initialized
9367 13:54:01.011266 Show all devs... After init.
9368 13:54:01.011339 Root Device: enabled 1
9369 13:54:01.014796 CPU_CLUSTER: 0: enabled 1
9370 13:54:01.018461 CPU: 00: enabled 1
9371 13:54:01.021468 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9372 13:54:01.024700 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9373 13:54:01.028213 ELOG: NV offset 0x57f000 size 0x1000
9374 13:54:01.034735 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9375 13:54:01.041540 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9376 13:54:01.044743 ELOG: Event(17) added with size 13 at 2024-02-01 13:54:02 UTC
9377 13:54:01.048230 out: cmd=0x121: 03 db 21 01 00 00 00 00
9378 13:54:01.052850 in-header: 03 f1 00 00 2c 00 00 00
9379 13:54:01.066314 in-data: 6e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9380 13:54:01.073048 ELOG: Event(A1) added with size 10 at 2024-02-01 13:54:02 UTC
9381 13:54:01.080171 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9382 13:54:01.082735 ELOG: Event(A0) added with size 9 at 2024-02-01 13:54:02 UTC
9383 13:54:01.089570 elog_add_boot_reason: Logged dev mode boot
9384 13:54:01.092952 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9385 13:54:01.096790 Finalize devices...
9386 13:54:01.096868 Devices finalized
9387 13:54:01.103318 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9388 13:54:01.106491 Writing coreboot table at 0xffe64000
9389 13:54:01.109520 0. 000000000010a000-0000000000113fff: RAMSTAGE
9390 13:54:01.113021 1. 0000000040000000-00000000400fffff: RAM
9391 13:54:01.116145 2. 0000000040100000-000000004032afff: RAMSTAGE
9392 13:54:01.119539 3. 000000004032b000-00000000545fffff: RAM
9393 13:54:01.126547 4. 0000000054600000-000000005465ffff: BL31
9394 13:54:01.130042 5. 0000000054660000-00000000ffe63fff: RAM
9395 13:54:01.132762 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9396 13:54:01.139609 7. 0000000100000000-000000023fffffff: RAM
9397 13:54:01.139681 Passing 5 GPIOs to payload:
9398 13:54:01.146769 NAME | PORT | POLARITY | VALUE
9399 13:54:01.149879 EC in RW | 0x000000aa | low | undefined
9400 13:54:01.153574 EC interrupt | 0x00000005 | low | undefined
9401 13:54:01.159412 TPM interrupt | 0x000000ab | high | undefined
9402 13:54:01.162933 SD card detect | 0x00000011 | high | undefined
9403 13:54:01.169645 speaker enable | 0x00000093 | high | undefined
9404 13:54:01.173124 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9405 13:54:01.176216 in-header: 03 f9 00 00 02 00 00 00
9406 13:54:01.176297 in-data: 02 00
9407 13:54:01.179442 ADC[4]: Raw value=900221 ID=7
9408 13:54:01.182849 ADC[3]: Raw value=213336 ID=1
9409 13:54:01.182929 RAM Code: 0x71
9410 13:54:01.186425 ADC[6]: Raw value=74557 ID=0
9411 13:54:01.189187 ADC[5]: Raw value=211860 ID=1
9412 13:54:01.189267 SKU Code: 0x1
9413 13:54:01.196389 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum af6e
9414 13:54:01.199326 coreboot table: 964 bytes.
9415 13:54:01.202335 IMD ROOT 0. 0xfffff000 0x00001000
9416 13:54:01.206217 IMD SMALL 1. 0xffffe000 0x00001000
9417 13:54:01.209422 RO MCACHE 2. 0xffffc000 0x00001104
9418 13:54:01.212514 CONSOLE 3. 0xfff7c000 0x00080000
9419 13:54:01.216293 FMAP 4. 0xfff7b000 0x00000452
9420 13:54:01.219623 TIME STAMP 5. 0xfff7a000 0x00000910
9421 13:54:01.223076 VBOOT WORK 6. 0xfff66000 0x00014000
9422 13:54:01.226150 RAMOOPS 7. 0xffe66000 0x00100000
9423 13:54:01.229406 COREBOOT 8. 0xffe64000 0x00002000
9424 13:54:01.229510 IMD small region:
9425 13:54:01.232773 IMD ROOT 0. 0xffffec00 0x00000400
9426 13:54:01.235904 VPD 1. 0xffffeb80 0x0000006c
9427 13:54:01.239156 MMC STATUS 2. 0xffffeb60 0x00000004
9428 13:54:01.245749 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9429 13:54:01.245831 Probing TPM: done!
9430 13:54:01.252465 Connected to device vid:did:rid of 1ae0:0028:00
9431 13:54:01.259439 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9432 13:54:01.262754 Initialized TPM device CR50 revision 0
9433 13:54:01.266567 Checking cr50 for pending updates
9434 13:54:01.272114 Reading cr50 TPM mode
9435 13:54:01.280843 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9436 13:54:01.287694 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9437 13:54:01.327690 read SPI 0x3990ec 0x4f1b0: 34856 us, 9295 KB/s, 74.360 Mbps
9438 13:54:01.330996 Checking segment from ROM address 0x40100000
9439 13:54:01.334649 Checking segment from ROM address 0x4010001c
9440 13:54:01.341277 Loading segment from ROM address 0x40100000
9441 13:54:01.341348 code (compression=0)
9442 13:54:01.347846 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9443 13:54:01.357707 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9444 13:54:01.357789 it's not compressed!
9445 13:54:01.364690 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9446 13:54:01.367660 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9447 13:54:01.387890 Loading segment from ROM address 0x4010001c
9448 13:54:01.387970 Entry Point 0x80000000
9449 13:54:01.391185 Loaded segments
9450 13:54:01.394468 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9451 13:54:01.401259 Jumping to boot code at 0x80000000(0xffe64000)
9452 13:54:01.407924 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9453 13:54:01.414720 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9454 13:54:01.422522 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9455 13:54:01.425705 Checking segment from ROM address 0x40100000
9456 13:54:01.429055 Checking segment from ROM address 0x4010001c
9457 13:54:01.436112 Loading segment from ROM address 0x40100000
9458 13:54:01.436190 code (compression=1)
9459 13:54:01.442573 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9460 13:54:01.452747 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9461 13:54:01.452826 using LZMA
9462 13:54:01.460902 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9463 13:54:01.467697 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9464 13:54:01.470965 Loading segment from ROM address 0x4010001c
9465 13:54:01.471038 Entry Point 0x54601000
9466 13:54:01.473976 Loaded segments
9467 13:54:01.477313 NOTICE: MT8192 bl31_setup
9468 13:54:01.484329 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9469 13:54:01.487644 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9470 13:54:01.491144 WARNING: region 0:
9471 13:54:01.494547 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 13:54:01.494617 WARNING: region 1:
9473 13:54:01.502081 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9474 13:54:01.504770 WARNING: region 2:
9475 13:54:01.508275 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9476 13:54:01.511004 WARNING: region 3:
9477 13:54:01.514724 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 13:54:01.518159 WARNING: region 4:
9479 13:54:01.524512 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 13:54:01.524585 WARNING: region 5:
9481 13:54:01.527585 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 13:54:01.530885 WARNING: region 6:
9483 13:54:01.534242 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 13:54:01.534317 WARNING: region 7:
9485 13:54:01.541661 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 13:54:01.547787 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9487 13:54:01.551184 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9488 13:54:01.554507 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9489 13:54:01.561689 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9490 13:54:01.564726 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9491 13:54:01.568165 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9492 13:54:01.574556 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9493 13:54:01.578089 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9494 13:54:01.581798 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9495 13:54:01.588132 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9496 13:54:01.591178 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9497 13:54:01.594850 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9498 13:54:01.601353 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9499 13:54:01.605254 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9500 13:54:01.611648 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9501 13:54:01.614921 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9502 13:54:01.618359 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9503 13:54:01.625162 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9504 13:54:01.628178 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9505 13:54:01.632181 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9506 13:54:01.638233 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9507 13:54:01.641847 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9508 13:54:01.648641 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9509 13:54:01.652488 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9510 13:54:01.655257 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9511 13:54:01.662131 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9512 13:54:01.665321 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9513 13:54:01.668993 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9514 13:54:01.675195 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9515 13:54:01.678404 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9516 13:54:01.685656 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9517 13:54:01.688618 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9518 13:54:01.692402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9519 13:54:01.695445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9520 13:54:01.702405 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9521 13:54:01.705618 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9522 13:54:01.709335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9523 13:54:01.712177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9524 13:54:01.718803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9525 13:54:01.722780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9526 13:54:01.725629 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9527 13:54:01.729444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9528 13:54:01.735886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9529 13:54:01.739233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9530 13:54:01.742749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9531 13:54:01.746137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9532 13:54:01.752738 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9533 13:54:01.756436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9534 13:54:01.759895 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9535 13:54:01.766603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9536 13:54:01.769519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9537 13:54:01.772775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9538 13:54:01.779560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9539 13:54:01.783376 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9540 13:54:01.789983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9541 13:54:01.793337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9542 13:54:01.796479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9543 13:54:01.803037 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9544 13:54:01.806614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9545 13:54:01.813018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9546 13:54:01.816289 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9547 13:54:01.823608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9548 13:54:01.826468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9549 13:54:01.833320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9550 13:54:01.836938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9551 13:54:01.839765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9552 13:54:01.846950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9553 13:54:01.850223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9554 13:54:01.857326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9555 13:54:01.860069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9556 13:54:01.864096 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9557 13:54:01.870326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9558 13:54:01.873471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9559 13:54:01.880698 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9560 13:54:01.884676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9561 13:54:01.886972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9562 13:54:01.894010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9563 13:54:01.897945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9564 13:54:01.904252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9565 13:54:01.907258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9566 13:54:01.914447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9567 13:54:01.917286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9568 13:54:01.920863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9569 13:54:01.927460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9570 13:54:01.931107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9571 13:54:01.937792 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9572 13:54:01.941042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9573 13:54:01.947822 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9574 13:54:01.951374 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9575 13:54:01.954258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9576 13:54:01.961278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9577 13:54:01.964220 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9578 13:54:01.971337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9579 13:54:01.974777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9580 13:54:01.981448 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9581 13:54:01.984536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9582 13:54:01.988144 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9583 13:54:01.991332 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9584 13:54:01.997655 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9585 13:54:02.001307 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9586 13:54:02.004590 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9587 13:54:02.011146 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9588 13:54:02.014930 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9589 13:54:02.018417 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9590 13:54:02.024964 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9591 13:54:02.028276 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9592 13:54:02.035200 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9593 13:54:02.038022 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9594 13:54:02.041553 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9595 13:54:02.048136 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9596 13:54:02.051426 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9597 13:54:02.055043 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9598 13:54:02.061617 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9599 13:54:02.064949 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9600 13:54:02.071484 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9601 13:54:02.074952 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9602 13:54:02.078690 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9603 13:54:02.085493 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9604 13:54:02.088487 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9605 13:54:02.091399 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9606 13:54:02.095215 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9607 13:54:02.101668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9608 13:54:02.105168 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9609 13:54:02.108766 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9610 13:54:02.111716 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9611 13:54:02.118557 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9612 13:54:02.121760 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9613 13:54:02.128785 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9614 13:54:02.131770 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9615 13:54:02.135412 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9616 13:54:02.141863 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9617 13:54:02.144913 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9618 13:54:02.151963 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9619 13:54:02.155128 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9620 13:54:02.158764 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9621 13:54:02.165597 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9622 13:54:02.168848 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9623 13:54:02.172113 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9624 13:54:02.178926 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9625 13:54:02.182344 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9626 13:54:02.188482 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9627 13:54:02.192109 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9628 13:54:02.195863 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9629 13:54:02.202359 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9630 13:54:02.205372 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9631 13:54:02.208968 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9632 13:54:02.215923 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9633 13:54:02.218717 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9634 13:54:02.225533 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9635 13:54:02.228724 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9636 13:54:02.232494 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9637 13:54:02.239257 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9638 13:54:02.242306 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9639 13:54:02.245909 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9640 13:54:02.252350 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9641 13:54:02.255968 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9642 13:54:02.262280 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9643 13:54:02.266235 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9644 13:54:02.269135 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9645 13:54:02.275833 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9646 13:54:02.278891 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9647 13:54:02.282717 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9648 13:54:02.289189 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9649 13:54:02.292642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9650 13:54:02.299037 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9651 13:54:02.302435 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9652 13:54:02.306296 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9653 13:54:02.312694 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9654 13:54:02.316144 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9655 13:54:02.322602 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9656 13:54:02.325577 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9657 13:54:02.329015 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9658 13:54:02.336089 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9659 13:54:02.339184 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9660 13:54:02.342653 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9661 13:54:02.349526 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9662 13:54:02.352736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9663 13:54:02.359227 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9664 13:54:02.362593 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9665 13:54:02.365984 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9666 13:54:02.372367 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9667 13:54:02.376447 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9668 13:54:02.382250 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9669 13:54:02.385864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9670 13:54:02.389088 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9671 13:54:02.395645 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9672 13:54:02.399434 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9673 13:54:02.402433 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9674 13:54:02.409156 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9675 13:54:02.412542 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9676 13:54:02.419089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9677 13:54:02.423142 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9678 13:54:02.429148 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9679 13:54:02.432293 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9680 13:54:02.435998 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9681 13:54:02.442588 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9682 13:54:02.445994 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9683 13:54:02.452173 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9684 13:54:02.455633 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9685 13:54:02.462256 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9686 13:54:02.465522 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9687 13:54:02.468809 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9688 13:54:02.475869 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9689 13:54:02.478972 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9690 13:54:02.485488 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9691 13:54:02.488943 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9692 13:54:02.492775 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9693 13:54:02.499081 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9694 13:54:02.502431 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9695 13:54:02.509474 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9696 13:54:02.512326 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9697 13:54:02.515536 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9698 13:54:02.522651 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9699 13:54:02.525892 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9700 13:54:02.532404 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9701 13:54:02.535548 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9702 13:54:02.539387 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9703 13:54:02.545671 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9704 13:54:02.549230 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9705 13:54:02.556240 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9706 13:54:02.559010 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9707 13:54:02.562686 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9708 13:54:02.568885 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9709 13:54:02.572647 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9710 13:54:02.579099 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9711 13:54:02.582183 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9712 13:54:02.589202 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9713 13:54:02.592640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9714 13:54:02.595882 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9715 13:54:02.602737 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9716 13:54:02.606060 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9717 13:54:02.608833 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9718 13:54:02.612243 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9719 13:54:02.615320 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9720 13:54:02.622271 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9721 13:54:02.625595 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9722 13:54:02.632339 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9723 13:54:02.635840 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9724 13:54:02.639384 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9725 13:54:02.645147 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9726 13:54:02.648620 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9727 13:54:02.655732 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9728 13:54:02.659166 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9729 13:54:02.662153 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9730 13:54:02.669050 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9731 13:54:02.672236 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9732 13:54:02.675554 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9733 13:54:02.681861 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9734 13:54:02.685742 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9735 13:54:02.688649 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9736 13:54:02.695033 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9737 13:54:02.698350 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9738 13:54:02.701803 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9739 13:54:02.708682 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9740 13:54:02.712017 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9741 13:54:02.719058 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9742 13:54:02.721936 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9743 13:54:02.725506 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9744 13:54:02.732207 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9745 13:54:02.735221 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9746 13:54:02.738547 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9747 13:54:02.745514 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9748 13:54:02.748364 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9749 13:54:02.752087 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9750 13:54:02.758546 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9751 13:54:02.762215 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9752 13:54:02.768460 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9753 13:54:02.771989 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9754 13:54:02.775515 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9755 13:54:02.778401 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9756 13:54:02.785163 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9757 13:54:02.788677 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9758 13:54:02.792200 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9759 13:54:02.795511 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9760 13:54:02.798711 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9761 13:54:02.805865 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9762 13:54:02.808897 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9763 13:54:02.811797 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9764 13:54:02.815437 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9765 13:54:02.821993 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9766 13:54:02.825210 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9767 13:54:02.828600 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9768 13:54:02.835538 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9769 13:54:02.839018 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9770 13:54:02.845429 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9771 13:54:02.848711 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9772 13:54:02.852339 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9773 13:54:02.858722 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9774 13:54:02.862065 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9775 13:54:02.865682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9776 13:54:02.872363 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9777 13:54:02.875287 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9778 13:54:02.881964 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9779 13:54:02.885234 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9780 13:54:02.891912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9781 13:54:02.895244 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9782 13:54:02.898918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9783 13:54:02.905245 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9784 13:54:02.909032 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9785 13:54:02.915404 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9786 13:54:02.919099 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9787 13:54:02.922213 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9788 13:54:02.928685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9789 13:54:02.931751 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9790 13:54:02.938932 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9791 13:54:02.942239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9792 13:54:02.945839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9793 13:54:02.951822 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9794 13:54:02.955133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9795 13:54:02.962022 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9796 13:54:02.965416 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9797 13:54:02.968799 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9798 13:54:02.975235 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9799 13:54:02.978685 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9800 13:54:02.985506 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9801 13:54:02.988603 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9802 13:54:02.991995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9803 13:54:02.998890 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9804 13:54:03.001991 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9805 13:54:03.008677 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9806 13:54:03.012117 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9807 13:54:03.015406 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9808 13:54:03.022448 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9809 13:54:03.025498 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9810 13:54:03.032122 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9811 13:54:03.035545 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9812 13:54:03.038801 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9813 13:54:03.045492 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9814 13:54:03.049146 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9815 13:54:03.055399 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9816 13:54:03.059029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9817 13:54:03.062313 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9818 13:54:03.068774 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9819 13:54:03.072496 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9820 13:54:03.079153 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9821 13:54:03.082280 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9822 13:54:03.085686 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9823 13:54:03.092119 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9824 13:54:03.095926 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9825 13:54:03.102716 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9826 13:54:03.105629 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9827 13:54:03.108858 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9828 13:54:03.115995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9829 13:54:03.119059 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9830 13:54:03.125665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9831 13:54:03.128851 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9832 13:54:03.132179 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9833 13:54:03.138917 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9834 13:54:03.142488 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9835 13:54:03.148938 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9836 13:54:03.152339 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9837 13:54:03.155540 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9838 13:54:03.162387 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9839 13:54:03.165511 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9840 13:54:03.172307 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9841 13:54:03.175926 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9842 13:54:03.178875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9843 13:54:03.185783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9844 13:54:03.188724 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9845 13:54:03.195474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9846 13:54:03.198825 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9847 13:54:03.205845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9848 13:54:03.208690 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9849 13:54:03.212135 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9850 13:54:03.218827 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9851 13:54:03.221987 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9852 13:54:03.229110 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9853 13:54:03.232521 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9854 13:54:03.239337 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9855 13:54:03.242707 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9856 13:54:03.245920 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9857 13:54:03.252216 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9858 13:54:03.255441 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9859 13:54:03.262146 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9860 13:54:03.265794 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9861 13:54:03.272334 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9862 13:54:03.275935 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9863 13:54:03.278727 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9864 13:54:03.285386 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9865 13:54:03.288971 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9866 13:54:03.295484 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9867 13:54:03.299289 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9868 13:54:03.305598 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9869 13:54:03.308841 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9870 13:54:03.316089 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9871 13:54:03.319405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9872 13:54:03.322273 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9873 13:54:03.328938 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9874 13:54:03.332384 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9875 13:54:03.339215 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9876 13:54:03.342703 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9877 13:54:03.345927 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9878 13:54:03.352537 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9879 13:54:03.355732 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9880 13:54:03.362344 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9881 13:54:03.365958 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9882 13:54:03.372756 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9883 13:54:03.375954 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9884 13:54:03.379097 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9885 13:54:03.385954 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9886 13:54:03.389710 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9887 13:54:03.396402 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9888 13:54:03.399454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9889 13:54:03.402656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9890 13:54:03.409017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9891 13:54:03.412668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9892 13:54:03.419086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9893 13:54:03.422709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9894 13:54:03.429374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9895 13:54:03.432607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9896 13:54:03.439167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9897 13:54:03.442501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9898 13:54:03.449194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9899 13:54:03.452950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9900 13:54:03.459123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9901 13:54:03.462989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9902 13:54:03.466298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9903 13:54:03.472575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9904 13:54:03.476263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9905 13:54:03.482625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9906 13:54:03.486586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9907 13:54:03.492801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9908 13:54:03.496025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9909 13:54:03.502759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9910 13:54:03.506353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9911 13:54:03.513535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9912 13:54:03.516272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9913 13:54:03.522901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9914 13:54:03.526587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9915 13:54:03.533216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9916 13:54:03.536896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9917 13:54:03.543108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9918 13:54:03.546349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9919 13:54:03.553090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9920 13:54:03.556448 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9921 13:54:03.560090 INFO: [APUAPC] vio 0
9922 13:54:03.562862 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9923 13:54:03.569671 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9924 13:54:03.573188 INFO: [APUAPC] D0_APC_0: 0x400510
9925 13:54:03.573270 INFO: [APUAPC] D0_APC_1: 0x0
9926 13:54:03.576432 INFO: [APUAPC] D0_APC_2: 0x1540
9927 13:54:03.579897 INFO: [APUAPC] D0_APC_3: 0x0
9928 13:54:03.583154 INFO: [APUAPC] D1_APC_0: 0xffffffff
9929 13:54:03.586329 INFO: [APUAPC] D1_APC_1: 0xffffffff
9930 13:54:03.589614 INFO: [APUAPC] D1_APC_2: 0x3fffff
9931 13:54:03.592864 INFO: [APUAPC] D1_APC_3: 0x0
9932 13:54:03.596418 INFO: [APUAPC] D2_APC_0: 0xffffffff
9933 13:54:03.599895 INFO: [APUAPC] D2_APC_1: 0xffffffff
9934 13:54:03.602913 INFO: [APUAPC] D2_APC_2: 0x3fffff
9935 13:54:03.606283 INFO: [APUAPC] D2_APC_3: 0x0
9936 13:54:03.609785 INFO: [APUAPC] D3_APC_0: 0xffffffff
9937 13:54:03.613242 INFO: [APUAPC] D3_APC_1: 0xffffffff
9938 13:54:03.616974 INFO: [APUAPC] D3_APC_2: 0x3fffff
9939 13:54:03.619828 INFO: [APUAPC] D3_APC_3: 0x0
9940 13:54:03.623149 INFO: [APUAPC] D4_APC_0: 0xffffffff
9941 13:54:03.626672 INFO: [APUAPC] D4_APC_1: 0xffffffff
9942 13:54:03.630294 INFO: [APUAPC] D4_APC_2: 0x3fffff
9943 13:54:03.633016 INFO: [APUAPC] D4_APC_3: 0x0
9944 13:54:03.636579 INFO: [APUAPC] D5_APC_0: 0xffffffff
9945 13:54:03.640026 INFO: [APUAPC] D5_APC_1: 0xffffffff
9946 13:54:03.643522 INFO: [APUAPC] D5_APC_2: 0x3fffff
9947 13:54:03.646619 INFO: [APUAPC] D5_APC_3: 0x0
9948 13:54:03.649570 INFO: [APUAPC] D6_APC_0: 0xffffffff
9949 13:54:03.653077 INFO: [APUAPC] D6_APC_1: 0xffffffff
9950 13:54:03.656487 INFO: [APUAPC] D6_APC_2: 0x3fffff
9951 13:54:03.659826 INFO: [APUAPC] D6_APC_3: 0x0
9952 13:54:03.663065 INFO: [APUAPC] D7_APC_0: 0xffffffff
9953 13:54:03.666379 INFO: [APUAPC] D7_APC_1: 0xffffffff
9954 13:54:03.669781 INFO: [APUAPC] D7_APC_2: 0x3fffff
9955 13:54:03.669868 INFO: [APUAPC] D7_APC_3: 0x0
9956 13:54:03.673464 INFO: [APUAPC] D8_APC_0: 0xffffffff
9957 13:54:03.679555 INFO: [APUAPC] D8_APC_1: 0xffffffff
9958 13:54:03.679641 INFO: [APUAPC] D8_APC_2: 0x3fffff
9959 13:54:03.683171 INFO: [APUAPC] D8_APC_3: 0x0
9960 13:54:03.686207 INFO: [APUAPC] D9_APC_0: 0xffffffff
9961 13:54:03.689489 INFO: [APUAPC] D9_APC_1: 0xffffffff
9962 13:54:03.692988 INFO: [APUAPC] D9_APC_2: 0x3fffff
9963 13:54:03.696341 INFO: [APUAPC] D9_APC_3: 0x0
9964 13:54:03.699582 INFO: [APUAPC] D10_APC_0: 0xffffffff
9965 13:54:03.702978 INFO: [APUAPC] D10_APC_1: 0xffffffff
9966 13:54:03.706612 INFO: [APUAPC] D10_APC_2: 0x3fffff
9967 13:54:03.709686 INFO: [APUAPC] D10_APC_3: 0x0
9968 13:54:03.713145 INFO: [APUAPC] D11_APC_0: 0xffffffff
9969 13:54:03.716578 INFO: [APUAPC] D11_APC_1: 0xffffffff
9970 13:54:03.719611 INFO: [APUAPC] D11_APC_2: 0x3fffff
9971 13:54:03.722998 INFO: [APUAPC] D11_APC_3: 0x0
9972 13:54:03.726522 INFO: [APUAPC] D12_APC_0: 0xffffffff
9973 13:54:03.730039 INFO: [APUAPC] D12_APC_1: 0xffffffff
9974 13:54:03.732900 INFO: [APUAPC] D12_APC_2: 0x3fffff
9975 13:54:03.736511 INFO: [APUAPC] D12_APC_3: 0x0
9976 13:54:03.739470 INFO: [APUAPC] D13_APC_0: 0xffffffff
9977 13:54:03.743195 INFO: [APUAPC] D13_APC_1: 0xffffffff
9978 13:54:03.746273 INFO: [APUAPC] D13_APC_2: 0x3fffff
9979 13:54:03.749590 INFO: [APUAPC] D13_APC_3: 0x0
9980 13:54:03.753023 INFO: [APUAPC] D14_APC_0: 0xffffffff
9981 13:54:03.756031 INFO: [APUAPC] D14_APC_1: 0xffffffff
9982 13:54:03.759687 INFO: [APUAPC] D14_APC_2: 0x3fffff
9983 13:54:03.762961 INFO: [APUAPC] D14_APC_3: 0x0
9984 13:54:03.766498 INFO: [APUAPC] D15_APC_0: 0xffffffff
9985 13:54:03.769990 INFO: [APUAPC] D15_APC_1: 0xffffffff
9986 13:54:03.773238 INFO: [APUAPC] D15_APC_2: 0x3fffff
9987 13:54:03.776199 INFO: [APUAPC] D15_APC_3: 0x0
9988 13:54:03.779503 INFO: [APUAPC] APC_CON: 0x4
9989 13:54:03.783144 INFO: [NOCDAPC] D0_APC_0: 0x0
9990 13:54:03.786757 INFO: [NOCDAPC] D0_APC_1: 0x0
9991 13:54:03.789557 INFO: [NOCDAPC] D1_APC_0: 0x0
9992 13:54:03.794229 INFO: [NOCDAPC] D1_APC_1: 0xfff
9993 13:54:03.796597 INFO: [NOCDAPC] D2_APC_0: 0x0
9994 13:54:03.799908 INFO: [NOCDAPC] D2_APC_1: 0xfff
9995 13:54:03.799989 INFO: [NOCDAPC] D3_APC_0: 0x0
9996 13:54:03.802840 INFO: [NOCDAPC] D3_APC_1: 0xfff
9997 13:54:03.806383 INFO: [NOCDAPC] D4_APC_0: 0x0
9998 13:54:03.809545 INFO: [NOCDAPC] D4_APC_1: 0xfff
9999 13:54:03.813086 INFO: [NOCDAPC] D5_APC_0: 0x0
10000 13:54:03.816293 INFO: [NOCDAPC] D5_APC_1: 0xfff
10001 13:54:03.819410 INFO: [NOCDAPC] D6_APC_0: 0x0
10002 13:54:03.823105 INFO: [NOCDAPC] D6_APC_1: 0xfff
10003 13:54:03.826552 INFO: [NOCDAPC] D7_APC_0: 0x0
10004 13:54:03.829620 INFO: [NOCDAPC] D7_APC_1: 0xfff
10005 13:54:03.829696 INFO: [NOCDAPC] D8_APC_0: 0x0
10006 13:54:03.832818 INFO: [NOCDAPC] D8_APC_1: 0xfff
10007 13:54:03.836659 INFO: [NOCDAPC] D9_APC_0: 0x0
10008 13:54:03.839740 INFO: [NOCDAPC] D9_APC_1: 0xfff
10009 13:54:03.842897 INFO: [NOCDAPC] D10_APC_0: 0x0
10010 13:54:03.846645 INFO: [NOCDAPC] D10_APC_1: 0xfff
10011 13:54:03.849598 INFO: [NOCDAPC] D11_APC_0: 0x0
10012 13:54:03.853099 INFO: [NOCDAPC] D11_APC_1: 0xfff
10013 13:54:03.856154 INFO: [NOCDAPC] D12_APC_0: 0x0
10014 13:54:03.859458 INFO: [NOCDAPC] D12_APC_1: 0xfff
10015 13:54:03.862955 INFO: [NOCDAPC] D13_APC_0: 0x0
10016 13:54:03.866122 INFO: [NOCDAPC] D13_APC_1: 0xfff
10017 13:54:03.869501 INFO: [NOCDAPC] D14_APC_0: 0x0
10018 13:54:03.869600 INFO: [NOCDAPC] D14_APC_1: 0xfff
10019 13:54:03.873180 INFO: [NOCDAPC] D15_APC_0: 0x0
10020 13:54:03.876525 INFO: [NOCDAPC] D15_APC_1: 0xfff
10021 13:54:03.879647 INFO: [NOCDAPC] APC_CON: 0x4
10022 13:54:03.883157 INFO: [APUAPC] set_apusys_apc done
10023 13:54:03.886184 INFO: [DEVAPC] devapc_init done
10024 13:54:03.889696 INFO: GICv3 without legacy support detected.
10025 13:54:03.896396 INFO: ARM GICv3 driver initialized in EL3
10026 13:54:03.899539 INFO: Maximum SPI INTID supported: 639
10027 13:54:03.902797 INFO: BL31: Initializing runtime services
10028 13:54:03.909391 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10029 13:54:03.912717 INFO: SPM: enable CPC mode
10030 13:54:03.916291 INFO: mcdi ready for mcusys-off-idle and system suspend
10031 13:54:03.919840 INFO: BL31: Preparing for EL3 exit to normal world
10032 13:54:03.926203 INFO: Entry point address = 0x80000000
10033 13:54:03.926306 INFO: SPSR = 0x8
10034 13:54:03.932452
10035 13:54:03.932528
10036 13:54:03.932602
10037 13:54:03.935773 Starting depthcharge on Spherion...
10038 13:54:03.935842
10039 13:54:03.935900 Wipe memory regions:
10040 13:54:03.935961
10041 13:54:03.936634 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10042 13:54:03.936734 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10043 13:54:03.936814 Setting prompt string to ['asurada:']
10044 13:54:03.936899 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10045 13:54:03.939161 [0x00000040000000, 0x00000054600000)
10046 13:54:04.061767
10047 13:54:04.061896 [0x00000054660000, 0x00000080000000)
10048 13:54:04.322046
10049 13:54:04.322189 [0x000000821a7280, 0x000000ffe64000)
10050 13:54:05.067129
10051 13:54:05.067274 [0x00000100000000, 0x00000240000000)
10052 13:54:06.957684
10053 13:54:06.960574 Initializing XHCI USB controller at 0x11200000.
10054 13:54:07.998863
10055 13:54:08.002128 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10056 13:54:08.002214
10057 13:54:08.002329
10058 13:54:08.002437
10059 13:54:08.002726 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 13:54:08.103020 asurada: tftpboot 192.168.201.1 12682904/tftp-deploy-erzz8upf/kernel/image.itb 12682904/tftp-deploy-erzz8upf/kernel/cmdline
10062 13:54:08.103151 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 13:54:08.103286 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10064 13:54:08.107210 tftpboot 192.168.201.1 12682904/tftp-deploy-erzz8upf/kernel/image.ittp-deploy-erzz8upf/kernel/cmdline
10065 13:54:08.107312
10066 13:54:08.107378 Waiting for link
10067 13:54:08.267740
10068 13:54:08.267865 R8152: Initializing
10069 13:54:08.267934
10070 13:54:08.271403 Version 6 (ocp_data = 5c30)
10071 13:54:08.271488
10072 13:54:08.274725 R8152: Done initializing
10073 13:54:08.274801
10074 13:54:08.274863 Adding net device
10075 13:54:10.146174
10076 13:54:10.146316 done.
10077 13:54:10.146385
10078 13:54:10.146491 MAC: 00:24:32:30:78:52
10079 13:54:10.146552
10080 13:54:10.148966 Sending DHCP discover... done.
10081 13:54:10.149045
10082 13:54:22.330701 Waiting for reply... R8152: Bulk read error 0xffffffbf
10083 13:54:22.330832
10084 13:54:22.334035 Receive failed.
10085 13:54:22.334118
10086 13:54:22.334182 done.
10087 13:54:22.334242
10088 13:54:22.337542 Sending DHCP request... done.
10089 13:54:22.337624
10090 13:54:22.348788 Waiting for reply... done.
10091 13:54:22.348871
10092 13:54:22.348935 My ip is 192.168.201.14
10093 13:54:22.348995
10094 13:54:22.352414 The DHCP server ip is 192.168.201.1
10095 13:54:22.352500
10096 13:54:22.359163 TFTP server IP predefined by user: 192.168.201.1
10097 13:54:22.359245
10098 13:54:22.365489 Bootfile predefined by user: 12682904/tftp-deploy-erzz8upf/kernel/image.itb
10099 13:54:22.365570
10100 13:54:22.365635 Sending tftp read request... done.
10101 13:54:22.369272
10102 13:54:22.372472 Waiting for the transfer...
10103 13:54:22.372552
10104 13:54:22.921207 00000000 ################################################################
10105 13:54:22.921345
10106 13:54:23.467703 00080000 ################################################################
10107 13:54:23.467851
10108 13:54:24.019284 00100000 ################################################################
10109 13:54:24.019430
10110 13:54:24.565668 00180000 ################################################################
10111 13:54:24.565798
10112 13:54:25.105641 00200000 ################################################################
10113 13:54:25.105782
10114 13:54:25.652123 00280000 ################################################################
10115 13:54:25.652270
10116 13:54:26.196080 00300000 ################################################################
10117 13:54:26.196226
10118 13:54:26.751012 00380000 ################################################################
10119 13:54:26.751160
10120 13:54:27.345434 00400000 ################################################################
10121 13:54:27.346012
10122 13:54:28.050550 00480000 ################################################################
10123 13:54:28.051123
10124 13:54:28.759055 00500000 ################################################################
10125 13:54:28.759296
10126 13:54:29.473522 00580000 ################################################################
10127 13:54:29.474086
10128 13:54:30.183289 00600000 ################################################################
10129 13:54:30.183799
10130 13:54:30.885500 00680000 ################################################################
10131 13:54:30.886003
10132 13:54:31.587294 00700000 ################################################################
10133 13:54:31.587801
10134 13:54:32.296134 00780000 ################################################################
10135 13:54:32.296650
10136 13:54:33.009291 00800000 ################################################################
10137 13:54:33.009893
10138 13:54:33.722483 00880000 ################################################################
10139 13:54:33.723026
10140 13:54:34.438276 00900000 ################################################################
10141 13:54:34.438822
10142 13:54:35.110828 00980000 ################################################################
10143 13:54:35.110966
10144 13:54:35.808529 00a00000 ################################################################
10145 13:54:35.809079
10146 13:54:36.512473 00a80000 ################################################################
10147 13:54:36.513020
10148 13:54:37.207985 00b00000 ################################################################
10149 13:54:37.208126
10150 13:54:37.883438 00b80000 ################################################################
10151 13:54:37.883956
10152 13:54:38.562742 00c00000 ################################################################
10153 13:54:38.563252
10154 13:54:39.190734 00c80000 ################################################################
10155 13:54:39.190884
10156 13:54:39.760253 00d00000 ################################################################
10157 13:54:39.760385
10158 13:54:40.367226 00d80000 ################################################################
10159 13:54:40.367908
10160 13:54:40.982019 00e00000 ################################################################
10161 13:54:40.982703
10162 13:54:41.557194 00e80000 ################################################################
10163 13:54:41.557350
10164 13:54:42.103517 00f00000 ################################################################
10165 13:54:42.103649
10166 13:54:42.648521 00f80000 ################################################################
10167 13:54:42.648679
10168 13:54:43.197485 01000000 ################################################################
10169 13:54:43.197646
10170 13:54:43.735772 01080000 ################################################################
10171 13:54:43.735940
10172 13:54:44.284641 01100000 ################################################################
10173 13:54:44.284768
10174 13:54:44.829365 01180000 ################################################################
10175 13:54:44.829533
10176 13:54:45.382725 01200000 ################################################################
10177 13:54:45.382883
10178 13:54:45.955830 01280000 ################################################################
10179 13:54:45.955991
10180 13:54:46.582545 01300000 ################################################################
10181 13:54:46.583199
10182 13:54:47.159456 01380000 ################################################################
10183 13:54:47.159614
10184 13:54:47.709432 01400000 ################################################################
10185 13:54:47.709599
10186 13:54:48.260758 01480000 ################################################################
10187 13:54:48.260890
10188 13:54:48.790083 01500000 ################################################################
10189 13:54:48.790247
10190 13:54:49.315941 01580000 ################################################################
10191 13:54:49.316093
10192 13:54:49.862900 01600000 ################################################################
10193 13:54:49.863046
10194 13:54:50.391163 01680000 ################################################################
10195 13:54:50.391300
10196 13:54:50.916841 01700000 ################################################################
10197 13:54:50.917025
10198 13:54:51.439398 01780000 ################################################################
10199 13:54:51.439568
10200 13:54:51.956862 01800000 ################################################################
10201 13:54:51.957019
10202 13:54:52.478702 01880000 ################################################################
10203 13:54:52.478850
10204 13:54:53.052327 01900000 ################################################################
10205 13:54:53.052812
10206 13:54:53.643567 01980000 ################################################################
10207 13:54:53.643718
10208 13:54:54.314593 01a00000 ################################################################
10209 13:54:54.314738
10210 13:54:54.960960 01a80000 ################################################################
10211 13:54:54.961102
10212 13:54:55.503599 01b00000 ################################################################
10213 13:54:55.503769
10214 13:54:56.055704 01b80000 ################################################################
10215 13:54:56.055834
10216 13:54:56.591337 01c00000 ################################################################
10217 13:54:56.591502
10218 13:54:57.126103 01c80000 ################################################################
10219 13:54:57.126245
10220 13:54:57.658103 01d00000 ################################################################
10221 13:54:57.658266
10222 13:54:58.193790 01d80000 ################################################################
10223 13:54:58.193935
10224 13:54:58.737398 01e00000 ################################################################
10225 13:54:58.737900
10226 13:54:59.371904 01e80000 ################################################################
10227 13:54:59.372071
10228 13:54:59.909354 01f00000 ################################################################
10229 13:54:59.909524
10230 13:55:00.433937 01f80000 ################################################################
10231 13:55:00.434097
10232 13:55:00.986258 02000000 ################################################################
10233 13:55:00.986411
10234 13:55:01.542848 02080000 ################################################################
10235 13:55:01.542993
10236 13:55:02.097866 02100000 ################################################################
10237 13:55:02.098018
10238 13:55:02.682453 02180000 ################################################################
10239 13:55:02.682596
10240 13:55:03.260954 02200000 ################################################################
10241 13:55:03.261140
10242 13:55:03.810379 02280000 ################################################################
10243 13:55:03.810565
10244 13:55:04.384209 02300000 ################################################################
10245 13:55:04.384398
10246 13:55:04.942634 02380000 ################################################################
10247 13:55:04.942817
10248 13:55:05.494387 02400000 ################################################################
10249 13:55:05.494561
10250 13:55:06.113493 02480000 ################################################################
10251 13:55:06.113652
10252 13:55:06.722815 02500000 ################################################################
10253 13:55:06.722968
10254 13:55:07.342301 02580000 ################################################################
10255 13:55:07.342483
10256 13:55:07.927143 02600000 ################################################################
10257 13:55:07.927276
10258 13:55:08.517112 02680000 ################################################################
10259 13:55:08.517261
10260 13:55:09.051672 02700000 ################################################################
10261 13:55:09.051833
10262 13:55:09.585626 02780000 ################################################################
10263 13:55:09.585851
10264 13:55:10.115277 02800000 ################################################################
10265 13:55:10.115406
10266 13:55:10.640945 02880000 ################################################################
10267 13:55:10.641080
10268 13:55:11.177413 02900000 ################################################################
10269 13:55:11.177558
10270 13:55:11.699013 02980000 ################################################################
10271 13:55:11.699174
10272 13:55:12.227596 02a00000 ################################################################
10273 13:55:12.227739
10274 13:55:12.754658 02a80000 ################################################################
10275 13:55:12.754797
10276 13:55:13.273314 02b00000 ################################################################
10277 13:55:13.273464
10278 13:55:13.792485 02b80000 ################################################################
10279 13:55:13.792631
10280 13:55:14.309860 02c00000 ################################################################
10281 13:55:14.310013
10282 13:55:14.828547 02c80000 ################################################################
10283 13:55:14.828679
10284 13:55:15.348127 02d00000 ################################################################
10285 13:55:15.348294
10286 13:55:15.868201 02d80000 ################################################################
10287 13:55:15.868334
10288 13:55:16.398303 02e00000 ################################################################
10289 13:55:16.398495
10290 13:55:16.921501 02e80000 ################################################################
10291 13:55:16.921636
10292 13:55:17.443179 02f00000 ################################################################
10293 13:55:17.443320
10294 13:55:17.963236 02f80000 ################################################################
10295 13:55:17.963369
10296 13:55:18.482609 03000000 ################################################################
10297 13:55:18.482763
10298 13:55:19.015492 03080000 ################################################################
10299 13:55:19.015640
10300 13:55:19.573785 03100000 ################################################################
10301 13:55:19.573941
10302 13:55:20.112152 03180000 ################################################################
10303 13:55:20.112325
10304 13:55:20.656781 03200000 ################################################################
10305 13:55:20.656956
10306 13:55:21.201965 03280000 ################################################################
10307 13:55:21.202126
10308 13:55:21.752061 03300000 ################################################################
10309 13:55:21.752202
10310 13:55:22.311137 03380000 ################################################################
10311 13:55:22.311286
10312 13:55:22.864862 03400000 ################################################################
10313 13:55:22.865013
10314 13:55:23.404517 03480000 ################################################################
10315 13:55:23.404683
10316 13:55:23.959089 03500000 ################################################################
10317 13:55:23.959222
10318 13:55:24.512447 03580000 ################################################################
10319 13:55:24.512601
10320 13:55:25.067172 03600000 ################################################################
10321 13:55:25.067320
10322 13:55:25.613184 03680000 ################################################################
10323 13:55:25.613357
10324 13:55:26.142794 03700000 ################################################################
10325 13:55:26.142968
10326 13:55:26.689357 03780000 ################################################################
10327 13:55:26.689887
10328 13:55:27.252184 03800000 ################################################################
10329 13:55:27.252364
10330 13:55:27.655908 03880000 ################################################ done.
10331 13:55:27.659252
10332 13:55:27.659341 The bootfile was 59632202 bytes long.
10333 13:55:27.663366
10334 13:55:27.663447 Sending tftp read request... done.
10335 13:55:27.663513
10336 13:55:27.666145 Waiting for the transfer...
10337 13:55:27.666220
10338 13:55:27.669357 00000000 # done.
10339 13:55:27.669438
10340 13:55:27.676088 Command line loaded dynamically from TFTP file: 12682904/tftp-deploy-erzz8upf/kernel/cmdline
10341 13:55:27.676173
10342 13:55:27.689189 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10343 13:55:27.689273
10344 13:55:27.689338 Loading FIT.
10345 13:55:27.689399
10346 13:55:27.693130 Image ramdisk-1 has 47536029 bytes.
10347 13:55:27.693212
10348 13:55:27.695959 Image fdt-1 has 47278 bytes.
10349 13:55:27.696066
10350 13:55:27.699783 Image kernel-1 has 12046857 bytes.
10351 13:55:27.699858
10352 13:55:27.709627 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10353 13:55:27.709709
10354 13:55:27.725967 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10355 13:55:27.726059
10356 13:55:27.732720 Choosing best match conf-1 for compat google,spherion-rev2.
10357 13:55:27.732798
10358 13:55:27.740484 Connected to device vid:did:rid of 1ae0:0028:00
10359 13:55:27.748752
10360 13:55:27.751970 tpm_get_response: command 0x17b, return code 0x0
10361 13:55:27.752044
10362 13:55:27.755614 ec_init: CrosEC protocol v3 supported (256, 248)
10363 13:55:27.759262
10364 13:55:27.762850 tpm_cleanup: add release locality here.
10365 13:55:27.762928
10366 13:55:27.762994 Shutting down all USB controllers.
10367 13:55:27.765832
10368 13:55:27.765905 Removing current net device
10369 13:55:27.765971
10370 13:55:27.772308 Exiting depthcharge with code 4 at timestamp: 113214474
10371 13:55:27.772386
10372 13:55:27.776616 LZMA decompressing kernel-1 to 0x821a6718
10373 13:55:27.776689
10374 13:55:27.779299 LZMA decompressing kernel-1 to 0x40000000
10375 13:55:29.279332
10376 13:55:29.279485 jumping to kernel
10377 13:55:29.280008 end: 2.2.4 bootloader-commands (duration 00:01:25) [common]
10378 13:55:29.280109 start: 2.2.5 auto-login-action (timeout 00:03:00) [common]
10379 13:55:29.280188 Setting prompt string to ['Linux version [0-9]']
10380 13:55:29.280257 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10381 13:55:29.280326 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10382 13:55:29.361658
10383 13:55:29.364575 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10384 13:55:29.368923 start: 2.2.5.1 login-action (timeout 00:03:00) [common]
10385 13:55:29.369011 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10386 13:55:29.369085 Setting prompt string to []
10387 13:55:29.369164 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10388 13:55:29.369235 Using line separator: #'\n'#
10389 13:55:29.369294 No login prompt set.
10390 13:55:29.369356 Parsing kernel messages
10391 13:55:29.369414 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10392 13:55:29.369546 [login-action] Waiting for messages, (timeout 00:03:00)
10393 13:55:29.387888 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10394 13:55:29.391486 [ 0.000000] random: crng init done
10395 13:55:29.394380 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10396 13:55:29.397952 [ 0.000000] efi: UEFI not found.
10397 13:55:29.407890 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10398 13:55:29.414726 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10399 13:55:29.424593 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10400 13:55:29.434430 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10401 13:55:29.441004 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10402 13:55:29.444500 [ 0.000000] printk: bootconsole [mtk8250] enabled
10403 13:55:29.453218 [ 0.000000] NUMA: No NUMA configuration found
10404 13:55:29.459433 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10405 13:55:29.466361 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10406 13:55:29.466498 [ 0.000000] Zone ranges:
10407 13:55:29.472899 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10408 13:55:29.476213 [ 0.000000] DMA32 empty
10409 13:55:29.482644 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10410 13:55:29.486434 [ 0.000000] Movable zone start for each node
10411 13:55:29.489991 [ 0.000000] Early memory node ranges
10412 13:55:29.496169 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10413 13:55:29.502987 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10414 13:55:29.509237 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10415 13:55:29.516264 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10416 13:55:29.522935 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10417 13:55:29.529537 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10418 13:55:29.585785 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10419 13:55:29.593125 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10420 13:55:29.600220 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10421 13:55:29.602825 [ 0.000000] psci: probing for conduit method from DT.
10422 13:55:29.609234 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10423 13:55:29.612903 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10424 13:55:29.619336 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10425 13:55:29.622787 [ 0.000000] psci: SMC Calling Convention v1.2
10426 13:55:29.629150 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10427 13:55:29.632568 [ 0.000000] Detected VIPT I-cache on CPU0
10428 13:55:29.638996 [ 0.000000] CPU features: detected: GIC system register CPU interface
10429 13:55:29.645540 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10430 13:55:29.652550 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10431 13:55:29.659043 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10432 13:55:29.665661 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10433 13:55:29.672289 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10434 13:55:29.679083 [ 0.000000] alternatives: applying boot alternatives
10435 13:55:29.682209 [ 0.000000] Fallback order for Node 0: 0
10436 13:55:29.689102 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10437 13:55:29.692460 [ 0.000000] Policy zone: Normal
10438 13:55:29.708758 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10439 13:55:29.719195 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10440 13:55:29.729570 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10441 13:55:29.739557 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10442 13:55:29.745885 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10443 13:55:29.749179 <6>[ 0.000000] software IO TLB: area num 8.
10444 13:55:29.806312 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10445 13:55:29.955473 <6>[ 0.000000] Memory: 7920828K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 431940K reserved, 32768K cma-reserved)
10446 13:55:29.962114 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10447 13:55:29.968574 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10448 13:55:29.971501 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10449 13:55:29.978366 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10450 13:55:29.984877 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10451 13:55:29.988391 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10452 13:55:29.998126 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10453 13:55:30.004810 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10454 13:55:30.008299 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10455 13:55:30.015998 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10456 13:55:30.019936 <6>[ 0.000000] GICv3: 608 SPIs implemented
10457 13:55:30.026546 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10458 13:55:30.030154 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10459 13:55:30.033148 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10460 13:55:30.043192 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10461 13:55:30.053071 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10462 13:55:30.066144 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10463 13:55:30.072873 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10464 13:55:30.081768 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10465 13:55:30.095143 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10466 13:55:30.101731 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10467 13:55:30.108865 <6>[ 0.009186] Console: colour dummy device 80x25
10468 13:55:30.118268 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10469 13:55:30.121646 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10470 13:55:30.128776 <6>[ 0.029247] LSM: Security Framework initializing
10471 13:55:30.135285 <6>[ 0.034186] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10472 13:55:30.145198 <6>[ 0.042049] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10473 13:55:30.151675 <6>[ 0.051459] cblist_init_generic: Setting adjustable number of callback queues.
10474 13:55:30.158870 <6>[ 0.058904] cblist_init_generic: Setting shift to 3 and lim to 1.
10475 13:55:30.165110 <6>[ 0.065241] cblist_init_generic: Setting adjustable number of callback queues.
10476 13:55:30.172084 <6>[ 0.072714] cblist_init_generic: Setting shift to 3 and lim to 1.
10477 13:55:30.178385 <6>[ 0.079155] rcu: Hierarchical SRCU implementation.
10478 13:55:30.185153 <6>[ 0.084171] rcu: Max phase no-delay instances is 1000.
10479 13:55:30.188170 <6>[ 0.091226] EFI services will not be available.
10480 13:55:30.195390 <6>[ 0.096156] smp: Bringing up secondary CPUs ...
10481 13:55:30.202755 <6>[ 0.101235] Detected VIPT I-cache on CPU1
10482 13:55:30.209479 <6>[ 0.101304] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10483 13:55:30.215998 <6>[ 0.101337] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10484 13:55:30.219581 <6>[ 0.101670] Detected VIPT I-cache on CPU2
10485 13:55:30.225894 <6>[ 0.101718] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10486 13:55:30.232533 <6>[ 0.101733] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10487 13:55:30.239402 <6>[ 0.101989] Detected VIPT I-cache on CPU3
10488 13:55:30.245581 <6>[ 0.102036] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10489 13:55:30.252425 <6>[ 0.102049] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10490 13:55:30.256019 <6>[ 0.102354] CPU features: detected: Spectre-v4
10491 13:55:30.262752 <6>[ 0.102361] CPU features: detected: Spectre-BHB
10492 13:55:30.265741 <6>[ 0.102366] Detected PIPT I-cache on CPU4
10493 13:55:30.272573 <6>[ 0.102420] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10494 13:55:30.279185 <6>[ 0.102436] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10495 13:55:30.285476 <6>[ 0.102726] Detected PIPT I-cache on CPU5
10496 13:55:30.292231 <6>[ 0.102786] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10497 13:55:30.298965 <6>[ 0.102805] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10498 13:55:30.302818 <6>[ 0.103081] Detected PIPT I-cache on CPU6
10499 13:55:30.308928 <6>[ 0.103145] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10500 13:55:30.315563 <6>[ 0.103162] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10501 13:55:30.322001 <6>[ 0.103457] Detected PIPT I-cache on CPU7
10502 13:55:30.329191 <6>[ 0.103521] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10503 13:55:30.335420 <6>[ 0.103538] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10504 13:55:30.338935 <6>[ 0.103585] smp: Brought up 1 node, 8 CPUs
10505 13:55:30.345478 <6>[ 0.244999] SMP: Total of 8 processors activated.
10506 13:55:30.349069 <6>[ 0.249920] CPU features: detected: 32-bit EL0 Support
10507 13:55:30.358893 <6>[ 0.255283] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10508 13:55:30.365717 <6>[ 0.264138] CPU features: detected: Common not Private translations
10509 13:55:30.369134 <6>[ 0.270654] CPU features: detected: CRC32 instructions
10510 13:55:30.375406 <6>[ 0.276005] CPU features: detected: RCpc load-acquire (LDAPR)
10511 13:55:30.382182 <6>[ 0.282002] CPU features: detected: LSE atomic instructions
10512 13:55:30.388994 <6>[ 0.287819] CPU features: detected: Privileged Access Never
10513 13:55:30.391929 <6>[ 0.293599] CPU features: detected: RAS Extension Support
10514 13:55:30.399060 <6>[ 0.299208] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10515 13:55:30.405193 <6>[ 0.306427] CPU: All CPU(s) started at EL2
10516 13:55:30.412210 <6>[ 0.310744] alternatives: applying system-wide alternatives
10517 13:55:30.420499 <6>[ 0.321489] devtmpfs: initialized
10518 13:55:30.432633 <6>[ 0.330362] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10519 13:55:30.442624 <6>[ 0.340319] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10520 13:55:30.446315 <6>[ 0.347962] pinctrl core: initialized pinctrl subsystem
10521 13:55:30.453409 <6>[ 0.354603] DMI not present or invalid.
10522 13:55:30.459969 <6>[ 0.359007] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10523 13:55:30.466613 <6>[ 0.365874] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10524 13:55:30.476769 <6>[ 0.373457] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10525 13:55:30.483813 <6>[ 0.381690] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10526 13:55:30.489991 <6>[ 0.389935] audit: initializing netlink subsys (disabled)
10527 13:55:30.497170 <5>[ 0.395627] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10528 13:55:30.503824 <6>[ 0.396315] thermal_sys: Registered thermal governor 'step_wise'
10529 13:55:30.510207 <6>[ 0.403593] thermal_sys: Registered thermal governor 'power_allocator'
10530 13:55:30.513339 <6>[ 0.409848] cpuidle: using governor menu
10531 13:55:30.520289 <6>[ 0.420809] NET: Registered PF_QIPCRTR protocol family
10532 13:55:30.526729 <6>[ 0.426282] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10533 13:55:30.533515 <6>[ 0.433384] ASID allocator initialised with 32768 entries
10534 13:55:30.536771 <6>[ 0.439943] Serial: AMBA PL011 UART driver
10535 13:55:30.547500 <4>[ 0.448668] Trying to register duplicate clock ID: 134
10536 13:55:30.601543 <6>[ 0.505977] KASLR enabled
10537 13:55:30.615872 <6>[ 0.513679] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10538 13:55:30.622533 <6>[ 0.520694] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10539 13:55:30.629027 <6>[ 0.527184] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10540 13:55:30.635983 <6>[ 0.534189] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10541 13:55:30.642505 <6>[ 0.540677] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10542 13:55:30.649125 <6>[ 0.547681] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10543 13:55:30.656245 <6>[ 0.554167] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10544 13:55:30.662731 <6>[ 0.561171] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10545 13:55:30.666078 <6>[ 0.568625] ACPI: Interpreter disabled.
10546 13:55:30.674181 <6>[ 0.575056] iommu: Default domain type: Translated
10547 13:55:30.680851 <6>[ 0.580170] iommu: DMA domain TLB invalidation policy: strict mode
10548 13:55:30.684199 <5>[ 0.586829] SCSI subsystem initialized
10549 13:55:30.690953 <6>[ 0.591074] usbcore: registered new interface driver usbfs
10550 13:55:30.697120 <6>[ 0.596804] usbcore: registered new interface driver hub
10551 13:55:30.700538 <6>[ 0.602356] usbcore: registered new device driver usb
10552 13:55:30.707093 <6>[ 0.608471] pps_core: LinuxPPS API ver. 1 registered
10553 13:55:30.717278 <6>[ 0.613665] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10554 13:55:30.720685 <6>[ 0.623005] PTP clock support registered
10555 13:55:30.723823 <6>[ 0.627245] EDAC MC: Ver: 3.0.0
10556 13:55:30.731300 <6>[ 0.632426] FPGA manager framework
10557 13:55:30.737989 <6>[ 0.636102] Advanced Linux Sound Architecture Driver Initialized.
10558 13:55:30.741455 <6>[ 0.642864] vgaarb: loaded
10559 13:55:30.747802 <6>[ 0.646006] clocksource: Switched to clocksource arch_sys_counter
10560 13:55:30.750994 <5>[ 0.652450] VFS: Disk quotas dquot_6.6.0
10561 13:55:30.757978 <6>[ 0.656638] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10562 13:55:30.761106 <6>[ 0.663831] pnp: PnP ACPI: disabled
10563 13:55:30.769736 <6>[ 0.670520] NET: Registered PF_INET protocol family
10564 13:55:30.779530 <6>[ 0.676110] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10565 13:55:30.790521 <6>[ 0.688431] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10566 13:55:30.800679 <6>[ 0.697248] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10567 13:55:30.807524 <6>[ 0.705220] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10568 13:55:30.814052 <6>[ 0.713921] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10569 13:55:30.822763 <6>[ 0.723668] TCP: Hash tables configured (established 65536 bind 65536)
10570 13:55:30.832532 <6>[ 0.730539] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10571 13:55:30.839548 <6>[ 0.737737] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10572 13:55:30.845754 <6>[ 0.745446] NET: Registered PF_UNIX/PF_LOCAL protocol family
10573 13:55:30.852590 <6>[ 0.751589] RPC: Registered named UNIX socket transport module.
10574 13:55:30.855752 <6>[ 0.757742] RPC: Registered udp transport module.
10575 13:55:30.862731 <6>[ 0.762673] RPC: Registered tcp transport module.
10576 13:55:30.869527 <6>[ 0.767606] RPC: Registered tcp NFSv4.1 backchannel transport module.
10577 13:55:30.872194 <6>[ 0.774269] PCI: CLS 0 bytes, default 64
10578 13:55:30.875693 <6>[ 0.778604] Unpacking initramfs...
10579 13:55:30.900714 <6>[ 0.798231] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10580 13:55:30.910498 <6>[ 0.806894] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10581 13:55:30.913819 <6>[ 0.815749] kvm [1]: IPA Size Limit: 40 bits
10582 13:55:30.920624 <6>[ 0.820279] kvm [1]: GICv3: no GICV resource entry
10583 13:55:30.923931 <6>[ 0.825302] kvm [1]: disabling GICv2 emulation
10584 13:55:30.930688 <6>[ 0.829988] kvm [1]: GIC system register CPU interface enabled
10585 13:55:30.934496 <6>[ 0.836158] kvm [1]: vgic interrupt IRQ18
10586 13:55:30.940825 <6>[ 0.840515] kvm [1]: VHE mode initialized successfully
10587 13:55:30.947094 <5>[ 0.846995] Initialise system trusted keyrings
10588 13:55:30.953723 <6>[ 0.851805] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10589 13:55:30.960937 <6>[ 0.861783] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10590 13:55:30.967510 <5>[ 0.868157] NFS: Registering the id_resolver key type
10591 13:55:30.970810 <5>[ 0.873476] Key type id_resolver registered
10592 13:55:30.977324 <5>[ 0.877894] Key type id_legacy registered
10593 13:55:30.983837 <6>[ 0.882181] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10594 13:55:30.990712 <6>[ 0.889105] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10595 13:55:30.996963 <6>[ 0.896818] 9p: Installing v9fs 9p2000 file system support
10596 13:55:31.032942 <5>[ 0.934093] Key type asymmetric registered
10597 13:55:31.036522 <5>[ 0.938425] Asymmetric key parser 'x509' registered
10598 13:55:31.046545 <6>[ 0.943563] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10599 13:55:31.049503 <6>[ 0.951179] io scheduler mq-deadline registered
10600 13:55:31.052993 <6>[ 0.955958] io scheduler kyber registered
10601 13:55:31.071807 <6>[ 0.972945] EINJ: ACPI disabled.
10602 13:55:31.103886 <4>[ 0.998202] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 13:55:31.114214 <4>[ 1.008847] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 13:55:31.128611 <6>[ 1.029548] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10605 13:55:31.136304 <6>[ 1.037501] printk: console [ttyS0] disabled
10606 13:55:31.164821 <6>[ 1.062155] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10607 13:55:31.170753 <6>[ 1.071626] printk: console [ttyS0] enabled
10608 13:55:31.174735 <6>[ 1.071626] printk: console [ttyS0] enabled
10609 13:55:31.180677 <6>[ 1.080521] printk: bootconsole [mtk8250] disabled
10610 13:55:31.184275 <6>[ 1.080521] printk: bootconsole [mtk8250] disabled
10611 13:55:31.190545 <6>[ 1.091888] SuperH (H)SCI(F) driver initialized
10612 13:55:31.193960 <6>[ 1.097165] msm_serial: driver initialized
10613 13:55:31.208575 <6>[ 1.106081] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10614 13:55:31.218418 <6>[ 1.114627] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10615 13:55:31.224779 <6>[ 1.123169] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10616 13:55:31.234711 <6>[ 1.131798] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10617 13:55:31.241586 <6>[ 1.140506] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10618 13:55:31.251466 <6>[ 1.149231] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10619 13:55:31.261570 <6>[ 1.157772] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10620 13:55:31.268409 <6>[ 1.166581] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10621 13:55:31.278169 <6>[ 1.175126] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10622 13:55:31.289865 <6>[ 1.190916] loop: module loaded
10623 13:55:31.296148 <6>[ 1.196840] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10624 13:55:31.318285 <4>[ 1.219538] mtk-pmic-keys: Failed to locate of_node [id: -1]
10625 13:55:31.325370 <6>[ 1.226474] megasas: 07.719.03.00-rc1
10626 13:55:31.335162 <6>[ 1.236154] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10627 13:55:31.344333 <6>[ 1.245392] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10628 13:55:31.361315 <6>[ 1.262185] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10629 13:55:31.417722 <6>[ 1.312358] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10630 13:55:32.909784 <6>[ 2.811245] Freeing initrd memory: 46420K
10631 13:55:32.920517 <6>[ 2.821529] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10632 13:55:32.930864 <6>[ 2.832319] tun: Universal TUN/TAP device driver, 1.6
10633 13:55:32.934860 <6>[ 2.838387] thunder_xcv, ver 1.0
10634 13:55:32.937956 <6>[ 2.841900] thunder_bgx, ver 1.0
10635 13:55:32.940796 <6>[ 2.845397] nicpf, ver 1.0
10636 13:55:32.951492 <6>[ 2.849396] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10637 13:55:32.955042 <6>[ 2.856872] hns3: Copyright (c) 2017 Huawei Corporation.
10638 13:55:32.961632 <6>[ 2.862461] hclge is initializing
10639 13:55:32.964799 <6>[ 2.866040] e1000: Intel(R) PRO/1000 Network Driver
10640 13:55:32.971268 <6>[ 2.871169] e1000: Copyright (c) 1999-2006 Intel Corporation.
10641 13:55:32.974721 <6>[ 2.877180] e1000e: Intel(R) PRO/1000 Network Driver
10642 13:55:32.980924 <6>[ 2.882396] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10643 13:55:32.987650 <6>[ 2.888583] igb: Intel(R) Gigabit Ethernet Network Driver
10644 13:55:32.994757 <6>[ 2.894233] igb: Copyright (c) 2007-2014 Intel Corporation.
10645 13:55:33.001463 <6>[ 2.900068] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10646 13:55:33.008006 <6>[ 2.906586] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10647 13:55:33.011554 <6>[ 2.913048] sky2: driver version 1.30
10648 13:55:33.018151 <6>[ 2.918042] VFIO - User Level meta-driver version: 0.3
10649 13:55:33.025556 <6>[ 2.926276] usbcore: registered new interface driver usb-storage
10650 13:55:33.031338 <6>[ 2.932721] usbcore: registered new device driver onboard-usb-hub
10651 13:55:33.040465 <6>[ 2.941853] mt6397-rtc mt6359-rtc: registered as rtc0
10652 13:55:33.050545 <6>[ 2.947321] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:55:34 UTC (1706795734)
10653 13:55:33.053684 <6>[ 2.956885] i2c_dev: i2c /dev entries driver
10654 13:55:33.070516 <6>[ 2.968577] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10655 13:55:33.090119 <6>[ 2.991556] cpu cpu0: EM: created perf domain
10656 13:55:33.093523 <6>[ 2.996516] cpu cpu4: EM: created perf domain
10657 13:55:33.100542 <6>[ 3.002092] sdhci: Secure Digital Host Controller Interface driver
10658 13:55:33.107415 <6>[ 3.008522] sdhci: Copyright(c) Pierre Ossman
10659 13:55:33.113971 <6>[ 3.013472] Synopsys Designware Multimedia Card Interface Driver
10660 13:55:33.120351 <6>[ 3.020108] sdhci-pltfm: SDHCI platform and OF driver helper
10661 13:55:33.123978 <6>[ 3.020132] mmc0: CQHCI version 5.10
10662 13:55:33.130742 <6>[ 3.030261] ledtrig-cpu: registered to indicate activity on CPUs
10663 13:55:33.136888 <6>[ 3.037375] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10664 13:55:33.143538 <6>[ 3.044426] usbcore: registered new interface driver usbhid
10665 13:55:33.146941 <6>[ 3.050250] usbhid: USB HID core driver
10666 13:55:33.153967 <6>[ 3.054452] spi_master spi0: will run message pump with realtime priority
10667 13:55:33.198731 <6>[ 3.093238] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10668 13:55:33.218100 <6>[ 3.109451] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10669 13:55:33.225288 <6>[ 3.124285] cros-ec-spi spi0.0: Chrome EC device registered
10670 13:55:33.228683 <6>[ 3.130371] mmc0: Command Queue Engine enabled
10671 13:55:33.235073 <6>[ 3.135134] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10672 13:55:33.241944 <6>[ 3.142621] mmcblk0: mmc0:0001 DA4128 116 GiB
10673 13:55:33.251943 <6>[ 3.148812] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10674 13:55:33.258281 <6>[ 3.152773] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10675 13:55:33.261579 <6>[ 3.159268] NET: Registered PF_PACKET protocol family
10676 13:55:33.268139 <6>[ 3.165125] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10677 13:55:33.271781 <6>[ 3.169464] 9pnet: Installing 9P2000 support
10678 13:55:33.278259 <6>[ 3.175269] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10679 13:55:33.281457 <5>[ 3.179153] Key type dns_resolver registered
10680 13:55:33.288192 <6>[ 3.184929] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10681 13:55:33.294883 <6>[ 3.189330] registered taskstats version 1
10682 13:55:33.298151 <5>[ 3.199768] Loading compiled-in X.509 certificates
10683 13:55:33.327404 <4>[ 3.221674] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10684 13:55:33.337227 <4>[ 3.232430] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 13:55:33.343647 <3>[ 3.242974] debugfs: File 'uA_load' in directory '/' already present!
10686 13:55:33.350558 <3>[ 3.249674] debugfs: File 'min_uV' in directory '/' already present!
10687 13:55:33.356724 <3>[ 3.256351] debugfs: File 'max_uV' in directory '/' already present!
10688 13:55:33.363695 <3>[ 3.262964] debugfs: File 'constraint_flags' in directory '/' already present!
10689 13:55:33.374974 <3>[ 3.272986] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10690 13:55:33.387266 <6>[ 3.288858] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10691 13:55:33.394075 <6>[ 3.295618] xhci-mtk 11200000.usb: xHCI Host Controller
10692 13:55:33.401187 <6>[ 3.301120] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10693 13:55:33.410864 <6>[ 3.308975] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10694 13:55:33.417660 <6>[ 3.318405] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10695 13:55:33.424422 <6>[ 3.324600] xhci-mtk 11200000.usb: xHCI Host Controller
10696 13:55:33.430938 <6>[ 3.330101] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10697 13:55:33.437586 <6>[ 3.337757] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10698 13:55:33.444177 <6>[ 3.345630] hub 1-0:1.0: USB hub found
10699 13:55:33.447670 <6>[ 3.349657] hub 1-0:1.0: 1 port detected
10700 13:55:33.457601 <6>[ 3.353962] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10701 13:55:33.461114 <6>[ 3.362743] hub 2-0:1.0: USB hub found
10702 13:55:33.463847 <6>[ 3.366773] hub 2-0:1.0: 1 port detected
10703 13:55:33.473903 <6>[ 3.375020] mtk-msdc 11f70000.mmc: Got CD GPIO
10704 13:55:33.488399 <6>[ 3.386311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10705 13:55:33.494675 <6>[ 3.394419] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10706 13:55:33.504957 <4>[ 3.402316] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10707 13:55:33.514618 <6>[ 3.411856] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10708 13:55:33.521196 <6>[ 3.419935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10709 13:55:33.527749 <6>[ 3.427957] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10710 13:55:33.538122 <6>[ 3.435872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10711 13:55:33.544729 <6>[ 3.443704] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10712 13:55:33.554701 <6>[ 3.451522] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10713 13:55:33.564442 <6>[ 3.461910] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10714 13:55:33.571783 <6>[ 3.470268] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10715 13:55:33.581002 <6>[ 3.478635] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10716 13:55:33.587647 <6>[ 3.486976] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10717 13:55:33.598040 <6>[ 3.495327] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10718 13:55:33.604192 <6>[ 3.503666] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10719 13:55:33.614301 <6>[ 3.512015] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10720 13:55:33.620809 <6>[ 3.520354] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10721 13:55:33.631065 <6>[ 3.528702] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10722 13:55:33.637440 <6>[ 3.537042] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10723 13:55:33.647721 <6>[ 3.545380] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10724 13:55:33.654454 <6>[ 3.553719] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10725 13:55:33.663981 <6>[ 3.562060] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10726 13:55:33.674059 <6>[ 3.570399] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10727 13:55:33.680580 <6>[ 3.578737] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10728 13:55:33.687312 <6>[ 3.587475] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10729 13:55:33.694404 <6>[ 3.594643] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10730 13:55:33.700723 <6>[ 3.601403] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10731 13:55:33.708004 <6>[ 3.608159] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10732 13:55:33.713902 <6>[ 3.615115] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10733 13:55:33.723845 <6>[ 3.621968] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10734 13:55:33.733881 <6>[ 3.631102] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10735 13:55:33.743948 <6>[ 3.640259] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10736 13:55:33.754509 <6>[ 3.649660] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10737 13:55:33.763923 <6>[ 3.659128] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10738 13:55:33.770792 <6>[ 3.668593] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10739 13:55:33.780461 <6>[ 3.677713] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10740 13:55:33.790444 <6>[ 3.687178] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10741 13:55:33.800498 <6>[ 3.696297] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10742 13:55:33.810442 <6>[ 3.705591] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10743 13:55:33.820224 <6>[ 3.715763] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10744 13:55:33.830068 <6>[ 3.727629] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10745 13:55:33.876352 <6>[ 3.774285] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10746 13:55:34.031072 <6>[ 3.932342] hub 1-1:1.0: USB hub found
10747 13:55:34.033990 <6>[ 3.936864] hub 1-1:1.0: 4 ports detected
10748 13:55:34.043883 <6>[ 3.945503] hub 1-1:1.0: USB hub found
10749 13:55:34.047637 <6>[ 3.949829] hub 1-1:1.0: 4 ports detected
10750 13:55:34.156304 <6>[ 4.054598] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10751 13:55:34.182365 <6>[ 4.084010] hub 2-1:1.0: USB hub found
10752 13:55:34.185639 <6>[ 4.088501] hub 2-1:1.0: 3 ports detected
10753 13:55:34.195451 <6>[ 4.096606] hub 2-1:1.0: USB hub found
10754 13:55:34.198886 <6>[ 4.101051] hub 2-1:1.0: 3 ports detected
10755 13:55:34.372278 <6>[ 4.270325] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10756 13:55:34.504107 <6>[ 4.405761] hub 1-1.4:1.0: USB hub found
10757 13:55:34.507575 <6>[ 4.410372] hub 1-1.4:1.0: 2 ports detected
10758 13:55:34.517167 <6>[ 4.418620] hub 1-1.4:1.0: USB hub found
10759 13:55:34.520431 <6>[ 4.423167] hub 1-1.4:1.0: 2 ports detected
10760 13:55:34.588181 <6>[ 4.486442] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10761 13:55:34.816023 <6>[ 4.714296] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10762 13:55:35.008269 <6>[ 4.906281] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10763 13:55:46.109505 <6>[ 16.015329] ALSA device list:
10764 13:55:46.116072 <6>[ 16.018617] No soundcards found.
10765 13:55:46.123655 <6>[ 16.026656] Freeing unused kernel memory: 8448K
10766 13:55:46.127272 <6>[ 16.031648] Run /init as init process
10767 13:55:46.172976 <6>[ 16.075332] NET: Registered PF_INET6 protocol family
10768 13:55:46.179106 <6>[ 16.081682] Segment Routing with IPv6
10769 13:55:46.182418 <6>[ 16.085653] In-situ OAM (IOAM) with IPv6
10770 13:55:46.214624 <30>[ 16.100602] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10771 13:55:46.221666 <30>[ 16.124358] systemd[1]: Detected architecture arm64.
10772 13:55:46.221779
10773 13:55:46.228027 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10774 13:55:46.228103
10775 13:55:46.243633 <30>[ 16.146213] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10776 13:55:46.393271 <30>[ 16.292903] systemd[1]: Queued start job for default target Graphical Interface.
10777 13:55:46.408072 <30>[ 16.310976] systemd[1]: Created slice system-getty.slice.
10778 13:55:46.415251 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10779 13:55:46.431910 <30>[ 16.334674] systemd[1]: Created slice system-modprobe.slice.
10780 13:55:46.438255 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10781 13:55:46.456081 <30>[ 16.358747] systemd[1]: Created slice system-serial\x2dgetty.slice.
10782 13:55:46.465838 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10783 13:55:46.480568 <30>[ 16.383325] systemd[1]: Created slice User and Session Slice.
10784 13:55:46.487640 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10785 13:55:46.507408 <30>[ 16.406881] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10786 13:55:46.517118 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10787 13:55:46.535276 <30>[ 16.434834] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10788 13:55:46.541662 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10789 13:55:46.562180 <30>[ 16.458266] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10790 13:55:46.568822 <30>[ 16.470361] systemd[1]: Reached target Local Encrypted Volumes.
10791 13:55:46.575624 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10792 13:55:46.591711 <30>[ 16.494794] systemd[1]: Reached target Paths.
10793 13:55:46.595158 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10794 13:55:46.611242 <30>[ 16.514279] systemd[1]: Reached target Remote File Systems.
10795 13:55:46.617929 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10796 13:55:46.631600 <30>[ 16.534261] systemd[1]: Reached target Slices.
10797 13:55:46.634758 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10798 13:55:46.651533 <30>[ 16.554291] systemd[1]: Reached target Swap.
10799 13:55:46.655112 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10800 13:55:46.675599 <30>[ 16.574792] systemd[1]: Listening on initctl Compatibility Named Pipe.
10801 13:55:46.682101 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10802 13:55:46.696864 <30>[ 16.599731] systemd[1]: Listening on Journal Audit Socket.
10803 13:55:46.703460 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10804 13:55:46.720602 <30>[ 16.623474] systemd[1]: Listening on Journal Socket (/dev/log).
10805 13:55:46.727004 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10806 13:55:46.744738 <30>[ 16.647501] systemd[1]: Listening on Journal Socket.
10807 13:55:46.751643 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10808 13:55:46.764170 <30>[ 16.666994] systemd[1]: Listening on Network Service Netlink Socket.
10809 13:55:46.774517 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10810 13:55:46.788718 <30>[ 16.691552] systemd[1]: Listening on udev Control Socket.
10811 13:55:46.795346 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10812 13:55:46.813138 <30>[ 16.715350] systemd[1]: Listening on udev Kernel Socket.
10813 13:55:46.818908 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10814 13:55:46.871626 <30>[ 16.774536] systemd[1]: Mounting Huge Pages File System...
10815 13:55:46.878258 Mounting [0;1;39mHuge Pages File System[0m...
10816 13:55:46.895312 <30>[ 16.798364] systemd[1]: Mounting POSIX Message Queue File System...
10817 13:55:46.902057 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10818 13:55:46.943458 <30>[ 16.846386] systemd[1]: Mounting Kernel Debug File System...
10819 13:55:46.949954 Mounting [0;1;39mKernel Debug File System[0m...
10820 13:55:46.967281 <30>[ 16.866662] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10821 13:55:46.980556 <30>[ 16.879778] systemd[1]: Starting Create list of static device nodes for the current kernel...
10822 13:55:46.986834 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10823 13:55:47.036254 <30>[ 16.938653] systemd[1]: Starting Load Kernel Module configfs...
10824 13:55:47.042202 Starting [0;1;39mLoad Kernel Module configfs[0m...
10825 13:55:47.059866 <30>[ 16.962680] systemd[1]: Starting Load Kernel Module drm...
10826 13:55:47.066541 Starting [0;1;39mLoad Kernel Module drm[0m...
10827 13:55:47.086793 <30>[ 16.986655] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10828 13:55:47.123656 <30>[ 17.026835] systemd[1]: Starting Journal Service...
10829 13:55:47.127315 Starting [0;1;39mJournal Service[0m...
10830 13:55:47.146208 <30>[ 17.049291] systemd[1]: Starting Load Kernel Modules...
10831 13:55:47.152636 Starting [0;1;39mLoad Kernel Modules[0m...
10832 13:55:47.173516 <30>[ 17.072648] systemd[1]: Starting Remount Root and Kernel File Systems...
10833 13:55:47.179902 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10834 13:55:47.194769 <30>[ 17.097677] systemd[1]: Starting Coldplug All udev Devices...
10835 13:55:47.201718 Starting [0;1;39mColdplug All udev Devices[0m...
10836 13:55:47.222321 <30>[ 17.125359] systemd[1]: Started Journal Service.
10837 13:55:47.228917 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10838 13:55:47.245427 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10839 13:55:47.264220 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10840 13:55:47.285225 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10841 13:55:47.308585 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10842 13:55:47.329107 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10843 13:55:47.350356 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10844 13:55:47.369439 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10845 13:55:47.393212 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10846 13:55:47.411599 See 'systemctl status systemd-remount-fs.service' for details.
10847 13:55:47.459805 Mounting [0;1;39mKernel Configuration File System[0m...
10848 13:55:47.480184 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10849 13:55:47.494274 <46>[ 17.393327] systemd-journald[177]: Received client request to flush runtime journal.
10850 13:55:47.504217 Starting [0;1;39mLoad/Save Random Seed[0m...
10851 13:55:47.523708 Starting [0;1;39mApply Kernel Variables[0m...
10852 13:55:47.545419 Starting [0;1;39mCreate System Users[0m...
10853 13:55:47.566832 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10854 13:55:47.588376 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10855 13:55:47.612931 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10856 13:55:47.629056 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10857 13:55:47.649687 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10858 13:55:47.663881 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10859 13:55:47.704023 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10860 13:55:47.725939 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10861 13:55:47.739930 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10862 13:55:47.755589 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10863 13:55:47.807951 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10864 13:55:47.832109 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10865 13:55:47.854029 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10866 13:55:47.872410 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10867 13:55:47.933105 Starting [0;1;39mNetwork Service[0m...
10868 13:55:47.961880 Starting [0;1;39mNetwork Time Synchronization[0m...
10869 13:55:47.985224 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10870 13:55:48.006376 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10871 13:55:48.041447 [[0;32m OK [0m] Found device [0;1;39m/dev/t<6>[ 17.940025] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10872 13:55:48.041548 tyS0[0m.
10873 13:55:48.054315 <6>[ 17.953885] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10874 13:55:48.058088 <6>[ 17.956329] remoteproc remoteproc0: scp is available
10875 13:55:48.067392 <6>[ 17.961917] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10876 13:55:48.074288 <6>[ 17.966951] remoteproc remoteproc0: powering up scp
10877 13:55:48.080681 <6>[ 17.975833] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10878 13:55:48.090551 <6>[ 17.981007] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10879 13:55:48.097219 <6>[ 17.981401] usbcore: registered new device driver r8152-cfgselector
10880 13:55:48.103954 <6>[ 18.002910] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10881 13:55:48.110687 <6>[ 18.004485] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10882 13:55:48.117448 <4>[ 18.009785] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10883 13:55:48.124102 <4>[ 18.009877] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10884 13:55:48.133634 <3>[ 18.012661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 13:55:48.140795 <4>[ 18.028452] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10886 13:55:48.147346 <4>[ 18.028452] Fallback method does not support PEC.
10887 13:55:48.153725 <3>[ 18.032471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 13:55:48.157612 <6>[ 18.036546] mc: Linux media interface: v0.10
10889 13:55:48.164378 <6>[ 18.063162] videodev: Linux video capture interface: v2.00
10890 13:55:48.171435 <3>[ 18.067128] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 13:55:48.181554 <3>[ 18.070458] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 13:55:48.191170 <6>[ 18.086752] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10893 13:55:48.198162 <3>[ 18.089934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 13:55:48.207913 <3>[ 18.106242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 13:55:48.214584 <6>[ 18.111762] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10896 13:55:48.220907 <3>[ 18.114410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10897 13:55:48.230978 [[0;32m OK [<3>[ 18.114434] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 13:55:48.237847 <3>[ 18.114448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10899 13:55:48.247660 0m] Started [0;<3>[ 18.116060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 13:55:48.254248 <6>[ 18.121830] pci_bus 0000:00: root bus resource [bus 00-ff]
10901 13:55:48.264540 1;39mNetwork Tim<3>[ 18.130864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 13:55:48.270651 <6>[ 18.139225] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10903 13:55:48.281033 <6>[ 18.139286] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10904 13:55:48.287475 <6>[ 18.139289] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10905 13:55:48.294482 <6>[ 18.139299] remoteproc remoteproc0: remote processor scp is now up
10906 13:55:48.303620 <6>[ 18.139299] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10907 13:55:48.310828 <6>[ 18.139351] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10908 13:55:48.317093 <6>[ 18.139365] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10909 13:55:48.320437 <6>[ 18.139428] pci 0000:00:00.0: supports D1 D2
10910 13:55:48.330729 e Synchronizatio<6>[ 18.139430] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10911 13:55:48.337631 <6>[ 18.140391] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10912 13:55:48.344292 <6>[ 18.140464] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10913 13:55:48.350427 <6>[ 18.140489] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10914 13:55:48.360489 <6>[ 18.140503] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10915 13:55:48.367000 <6>[ 18.140518] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10916 13:55:48.370772 <6>[ 18.140621] pci 0000:01:00.0: supports D1 D2
10917 13:55:48.370848 n[0m.
10918 13:55:48.376944 <6>[ 18.140622] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10919 13:55:48.386647 <3>[ 18.147272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 13:55:48.393549 <3>[ 18.147279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 13:55:48.403318 <3>[ 18.147379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 13:55:48.410300 <3>[ 18.147383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 13:55:48.420222 <3>[ 18.147387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 13:55:48.426548 <3>[ 18.147394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 13:55:48.437035 <3>[ 18.147398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 13:55:48.443839 <3>[ 18.147426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 13:55:48.451252 <6>[ 18.150262] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10928 13:55:48.461099 <6>[ 18.159237] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10929 13:55:48.471080 <6>[ 18.160066] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10930 13:55:48.477675 <4>[ 18.160149] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10931 13:55:48.487805 <4>[ 18.160163] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10932 13:55:48.494812 <6>[ 18.162576] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10933 13:55:48.503969 <6>[ 18.163671] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10934 13:55:48.510876 <6>[ 18.164963] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10935 13:55:48.520736 <6>[ 18.172148] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10936 13:55:48.527546 <6>[ 18.178928] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10937 13:55:48.537132 <6>[ 18.178941] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10938 13:55:48.540474 <6>[ 18.226252] r8152 2-1.3:1.0 eth0: v1.12.13
10939 13:55:48.547154 <6>[ 18.229262] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10940 13:55:48.553895 <6>[ 18.237570] usbcore: registered new interface driver r8152
10941 13:55:48.557423 <6>[ 18.238286] Bluetooth: Core ver 2.22
10942 13:55:48.563877 <6>[ 18.238357] NET: Registered PF_BLUETOOTH protocol family
10943 13:55:48.570545 <6>[ 18.238359] Bluetooth: HCI device and connection manager initialized
10944 13:55:48.576910 <6>[ 18.238384] Bluetooth: HCI socket layer initialized
10945 13:55:48.580409 <6>[ 18.238391] Bluetooth: L2CAP socket layer initialized
10946 13:55:48.587272 <6>[ 18.238405] Bluetooth: SCO socket layer initialized
10947 13:55:48.593500 <6>[ 18.245735] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10948 13:55:48.600313 <6>[ 18.245748] pci 0000:00:00.0: PCI bridge to [bus 01]
10949 13:55:48.606921 <6>[ 18.261272] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10950 13:55:48.613410 <6>[ 18.266958] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10951 13:55:48.626928 <6>[ 18.276445] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10952 13:55:48.633440 <6>[ 18.279345] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10953 13:55:48.639998 <6>[ 18.279569] usbcore: registered new interface driver cdc_ether
10954 13:55:48.646612 <6>[ 18.286759] usbcore: registered new interface driver r8153_ecm
10955 13:55:48.650115 <6>[ 18.286842] usbcore: registered new interface driver uvcvideo
10956 13:55:48.656346 <6>[ 18.287284] usbcore: registered new interface driver btusb
10957 13:55:48.666361 <4>[ 18.288163] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10958 13:55:48.673270 <3>[ 18.288174] Bluetooth: hci0: Failed to load firmware file (-2)
10959 13:55:48.680090 <3>[ 18.288177] Bluetooth: hci0: Failed to set up firmware (-2)
10960 13:55:48.689667 <4>[ 18.288182] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10961 13:55:48.696312 <6>[ 18.297747] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10962 13:55:48.702893 <6>[ 18.298274] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10963 13:55:48.709389 <6>[ 18.298763] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10964 13:55:48.713352 <6>[ 18.322174] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10965 13:55:48.722599 <5>[ 18.328584] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10966 13:55:48.729109 <3>[ 18.360104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 13:55:48.739523 <3>[ 18.360724] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10968 13:55:48.746133 <5>[ 18.379812] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10969 13:55:48.757294 [[0;32m OK [<5>[ 18.653762] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10970 13:55:48.764122 0m] Finished [0<4>[ 18.663595] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10971 13:55:48.774169 ;1;39mUpdate UTM<3>[ 18.670028] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 13:55:48.780601 P about System B<6>[ 18.673711] cfg80211: failed to load regulatory.db
10973 13:55:48.790981 oot/Shutdown[0m<3>[ 18.684253] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10974 13:55:48.791063 .
10975 13:55:48.805244 <3>[ 18.705107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 13:55:48.828217 <6>[ 18.730666] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10977 13:55:48.838914 <3>[ 18.737584] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 13:55:48.845337 <6>[ 18.738259] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10979 13:55:48.874592 [[0;32m OK [<3>[ 18.771367] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 13:55:48.877662 <6>[ 18.773525] mt7921e 0000:01:00.0: ASIC revision: 79610010
10981 13:55:48.884531 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10982 13:55:48.903130 [[0;32m OK [<3>[ 18.802425] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 13:55:48.909214 0m] Reached target [0;1;39mBluetooth[0m.
10984 13:55:48.923788 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10985 13:55:48.936689 <3>[ 18.836149] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 13:55:48.943016 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10987 13:55:48.962476 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10988 13:55:48.984076 <6>[ 18.883572] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10989 13:55:48.984167 <6>[ 18.883572]
10990 13:55:49.003545 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10991 13:55:49.026889 Starting [0;1;39mNetwork Name Resolution[0m...
10992 13:55:49.044711 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10993 13:55:49.060212 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10994 13:55:49.078299 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10995 13:55:49.095872 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10996 13:55:49.111777 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10997 13:55:49.131292 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10998 13:55:49.143243 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10999 13:55:49.159583 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11000 13:55:49.211898 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11001 13:55:49.241567 Starting [0;1;39mUser Login Management[0m...
11002 13:55:49.252437 <6>[ 19.152368] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11003 13:55:49.262123 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11004 13:55:49.279442 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11005 13:55:49.296676 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11006 13:55:49.315615 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11007 13:55:49.334970 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11008 13:55:49.371690 Starting [0;1;39mPermit User Sessions[0m...
11009 13:55:49.388079 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11010 13:55:49.396346 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11011 13:55:49.407422 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11012 13:55:49.427620 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11013 13:55:49.444002 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11014 13:55:49.459812 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11015 13:55:49.475747 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11016 13:55:49.544194 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11017 13:55:49.578738 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11018 13:55:49.623181
11019 13:55:49.623287
11020 13:55:49.626303 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11021 13:55:49.626377
11022 13:55:49.630026 debian-bullseye-arm64 login: root (automatic login)
11023 13:55:49.630104
11024 13:55:49.630166
11025 13:55:49.645675 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
11026 13:55:49.645756
11027 13:55:49.652121 The programs included with the Debian GNU/Linux system are free software;
11028 13:55:49.658977 the exact distribution terms for each program are described in the
11029 13:55:49.662247 individual files in /usr/share/doc/*/copyright.
11030 13:55:49.662324
11031 13:55:49.668778 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11032 13:55:49.672333 permitted by applicable law.
11033 13:55:49.672795 Matched prompt #10: / #
11035 13:55:49.673006 Setting prompt string to ['/ #']
11036 13:55:49.673100 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11038 13:55:49.673289 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11039 13:55:49.673378 start: 2.2.6 expect-shell-connection (timeout 00:02:39) [common]
11040 13:55:49.673449 Setting prompt string to ['/ #']
11041 13:55:49.673508 Forcing a shell prompt, looking for ['/ #']
11043 13:55:49.723698 / #
11044 13:55:49.723826 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11045 13:55:49.723916 Waiting using forced prompt support (timeout 00:02:30)
11046 13:55:49.728777
11047 13:55:49.729044 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11048 13:55:49.729131 start: 2.2.7 export-device-env (timeout 00:02:39) [common]
11049 13:55:49.729221 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11050 13:55:49.729306 end: 2.2 depthcharge-retry (duration 00:02:21) [common]
11051 13:55:49.729391 end: 2 depthcharge-action (duration 00:02:21) [common]
11052 13:55:49.729479 start: 3 lava-test-retry (timeout 00:05:00) [common]
11053 13:55:49.729569 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11054 13:55:49.729639 Using namespace: common
11056 13:55:49.829922 / # #
11057 13:55:49.830078 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11058 13:55:49.835144 #
11059 13:55:49.835404 Using /lava-12682904
11061 13:55:49.935682 / # export SHELL=/bin/sh
11062 13:55:49.935871 <6>[ 19.797194] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11063 13:55:49.935947 export SHELL=/bin/sh<6>[ 19.805336] r8152 2-1.3:1.0 enx002432307852: carrier on
11064 13:55:49.941344
11066 13:55:50.041787 / # . /lava-12682904/environment
11067 13:55:50.047576 . /lava-12682904/environment
11069 13:55:50.148099 / # /lava-12682904/bin/lava-test-runner /lava-12682904/0
11070 13:55:50.148267 Test shell timeout: 10s (minimum of the action and connection timeout)
11071 13:55:50.148694 <6>[ 20.006505] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11072 13:55:50.153155 /lava-12682904/bin/lava-test-runner /lava-12682904/0
11073 13:55:50.172919 + export TESTRUN_ID=0_cros-ec
11074 13:55:50.179351 +<8>[ 20.081371] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12682904_1.5.2.3.1>
11075 13:55:50.179599 Received signal: <STARTRUN> 0_cros-ec 12682904_1.5.2.3.1
11076 13:55:50.179672 Starting test lava.0_cros-ec (12682904_1.5.2.3.1)
11077 13:55:50.179754 Skipping test definition patterns.
11078 13:55:50.182736 cd /lava-12682904/0/tests/0_cros-ec
11079 13:55:50.182806 + cat uuid
11080 13:55:50.186037 + UUID=12682904_1.5.2.3.1
11081 13:55:50.186110 + set +x
11082 13:55:50.192597 + python3 -m cros.runners.lava_runner -v
11083 13:55:50.553104 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11084 13:55:50.559585 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11085 13:55:50.559665
11086 13:55:50.566421 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11088 13:55:50.569920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11089 13:55:50.575904 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11090 13:55:50.582553 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11091 13:55:50.582632
11092 13:55:50.592431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11093 13:55:50.592689 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11095 13:55:50.599272 test_cros_ec<8>[ 20.500500] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12682904_1.5.2.3.1>
11096 13:55:50.599522 Received signal: <ENDRUN> 0_cros-ec 12682904_1.5.2.3.1
11097 13:55:50.599603 Ending use of test pattern.
11098 13:55:50.599665 Ending test lava.0_cros-ec (12682904_1.5.2.3.1), duration 0.42
11100 13:55:50.602402 _gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11101 13:55:50.609276 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11102 13:55:50.609377
11103 13:55:50.616260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11104 13:55:50.616507 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11106 13:55:50.622346 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11107 13:55:50.629380 Checks the standard ABI for the main Embedded Controller. ... ok
11108 13:55:50.629454
11109 13:55:50.632707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11110 13:55:50.632946 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11112 13:55:50.639120 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11113 13:55:50.645677 Checks the main Embedded controller character device. ... ok
11114 13:55:50.645753
11115 13:55:50.649161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11116 13:55:50.649400 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11118 13:55:50.655963 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11119 13:55:50.662181 Checks basic comunication with the main Embedded controller. ... ok
11120 13:55:50.662258
11121 13:55:50.669064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11122 13:55:50.669305 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11124 13:55:50.672329 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11125 13:55:50.679479 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11126 13:55:50.679555
11127 13:55:50.685496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11128 13:55:50.685737 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11130 13:55:50.692339 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11131 13:55:50.698756 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11132 13:55:50.698837
11133 13:55:50.705690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11134 13:55:50.705956 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11136 13:55:50.712159 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11137 13:55:50.718767 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11138 13:55:50.718850
11139 13:55:50.722014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11140 13:55:50.722267 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11142 13:55:50.728795 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11143 13:55:50.735420 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11144 13:55:50.735502
11145 13:55:50.741953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11146 13:55:50.742207 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11148 13:55:50.748539 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11149 13:55:50.755582 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11150 13:55:50.755664
11151 13:55:50.762568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11152 13:55:50.762821 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11154 13:55:50.768554 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11155 13:55:50.775213 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11156 13:55:50.775296
11157 13:55:50.782134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11158 13:55:50.782388 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11160 13:55:50.785630 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11161 13:55:50.795230 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11162 13:55:50.795313
11163 13:55:50.798765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11164 13:55:50.799018 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11166 13:55:50.805235 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11167 13:55:50.815238 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11168 13:55:50.815332
11169 13:55:50.821857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11170 13:55:50.822127 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11172 13:55:50.828291 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11173 13:55:50.831863 Check the cros battery ABI. ... skipped 'No BAT found'
11174 13:55:50.831945
11175 13:55:50.838554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11176 13:55:50.838807 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11178 13:55:50.845360 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11179 13:55:50.851954 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11180 13:55:50.852036
11181 13:55:50.858176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11182 13:55:50.858419 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11184 13:55:50.864983 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11185 13:55:50.871526 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11186 13:55:50.871609
11187 13:55:50.878680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11188 13:55:50.878935 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11190 13:55:50.885298 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11191 13:55:50.891585 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11192 13:55:50.891667
11193 13:55:50.898226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11194 13:55:50.898309
11195 13:55:50.898545 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11197 13:55:50.905026 ----------------------------------------------------------------------
11198 13:55:50.905109 Ran 18 tests in 0.008s
11199 13:55:50.905173
11200 13:55:50.908625 OK (skipped=15)
11201 13:55:50.908707 + set +x
11202 13:55:50.911510 <LAVA_TEST_RUNNER EXIT>
11203 13:55:50.911763 ok: lava_test_shell seems to have completed
11204 13:55:50.911939 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11205 13:55:50.912037 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11206 13:55:50.912127 end: 3 lava-test-retry (duration 00:00:01) [common]
11207 13:55:50.912214 start: 4 finalize (timeout 00:07:15) [common]
11208 13:55:50.912304 start: 4.1 power-off (timeout 00:00:30) [common]
11209 13:55:50.912451 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11210 13:55:50.988209 >> Command sent successfully.
11211 13:55:50.990713 Returned 0 in 0 seconds
11212 13:55:51.091113 end: 4.1 power-off (duration 00:00:00) [common]
11214 13:55:51.091441 start: 4.2 read-feedback (timeout 00:07:15) [common]
11215 13:55:51.091708 Listened to connection for namespace 'common' for up to 1s
11216 13:55:52.092668 Finalising connection for namespace 'common'
11217 13:55:52.092845 Disconnecting from shell: Finalise
11218 13:55:52.092923 / #
11219 13:55:52.193270 end: 4.2 read-feedback (duration 00:00:01) [common]
11220 13:55:52.193452 end: 4 finalize (duration 00:00:01) [common]
11221 13:55:52.193561 Cleaning after the job
11222 13:55:52.193658 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/ramdisk
11223 13:55:52.200587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/kernel
11224 13:55:52.209429 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/dtb
11225 13:55:52.209609 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682904/tftp-deploy-erzz8upf/modules
11226 13:55:52.217062 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682904
11227 13:55:52.335240 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682904
11228 13:55:52.335437 Job finished correctly