Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 16
- Kernel Errors: 32
1 13:59:34.819016 lava-dispatcher, installed at version: 2023.10
2 13:59:34.819245 start: 0 validate
3 13:59:34.819375 Start time: 2024-02-01 13:59:34.819367+00:00 (UTC)
4 13:59:34.819488 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:59:34.819627 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:59:35.104021 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:59:35.104700 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:59:35.375675 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:59:35.376362 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:59:35.637910 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:59:35.638676 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:59:35.916948 validate duration: 1.10
14 13:59:35.918190 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:59:35.918755 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:59:35.919456 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:59:35.920309 Not decompressing ramdisk as can be used compressed.
18 13:59:35.920968 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 13:59:35.921529 saving as /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/ramdisk/rootfs.cpio.gz
20 13:59:35.922078 total size: 43284872 (41 MB)
21 13:59:35.927262 progress 0 % (0 MB)
22 13:59:35.951681 progress 5 % (2 MB)
23 13:59:35.966477 progress 10 % (4 MB)
24 13:59:35.978084 progress 15 % (6 MB)
25 13:59:35.989776 progress 20 % (8 MB)
26 13:59:36.001847 progress 25 % (10 MB)
27 13:59:36.013772 progress 30 % (12 MB)
28 13:59:36.025041 progress 35 % (14 MB)
29 13:59:36.037027 progress 40 % (16 MB)
30 13:59:36.048918 progress 45 % (18 MB)
31 13:59:36.061008 progress 50 % (20 MB)
32 13:59:36.072401 progress 55 % (22 MB)
33 13:59:36.084272 progress 60 % (24 MB)
34 13:59:36.095614 progress 65 % (26 MB)
35 13:59:36.107513 progress 70 % (28 MB)
36 13:59:36.119251 progress 75 % (30 MB)
37 13:59:36.130663 progress 80 % (33 MB)
38 13:59:36.142122 progress 85 % (35 MB)
39 13:59:36.154117 progress 90 % (37 MB)
40 13:59:36.165617 progress 95 % (39 MB)
41 13:59:36.177896 progress 100 % (41 MB)
42 13:59:36.178152 41 MB downloaded in 0.26 s (161.18 MB/s)
43 13:59:36.178317 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:59:36.178608 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:59:36.178695 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:59:36.178778 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:59:36.178919 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:59:36.178994 saving as /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/kernel/Image
50 13:59:36.179055 total size: 51532288 (49 MB)
51 13:59:36.179116 No compression specified
52 13:59:36.180232 progress 0 % (0 MB)
53 13:59:36.194132 progress 5 % (2 MB)
54 13:59:36.208651 progress 10 % (4 MB)
55 13:59:36.222233 progress 15 % (7 MB)
56 13:59:36.236550 progress 20 % (9 MB)
57 13:59:36.251191 progress 25 % (12 MB)
58 13:59:36.265331 progress 30 % (14 MB)
59 13:59:36.279613 progress 35 % (17 MB)
60 13:59:36.294052 progress 40 % (19 MB)
61 13:59:36.307372 progress 45 % (22 MB)
62 13:59:36.321518 progress 50 % (24 MB)
63 13:59:36.335589 progress 55 % (27 MB)
64 13:59:36.349426 progress 60 % (29 MB)
65 13:59:36.364106 progress 65 % (31 MB)
66 13:59:36.377783 progress 70 % (34 MB)
67 13:59:36.391396 progress 75 % (36 MB)
68 13:59:36.404958 progress 80 % (39 MB)
69 13:59:36.418326 progress 85 % (41 MB)
70 13:59:36.431789 progress 90 % (44 MB)
71 13:59:36.444996 progress 95 % (46 MB)
72 13:59:36.458034 progress 100 % (49 MB)
73 13:59:36.458245 49 MB downloaded in 0.28 s (176.03 MB/s)
74 13:59:36.458404 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:59:36.458637 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:59:36.458725 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:59:36.458816 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:59:36.458955 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:59:36.459031 saving as /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/dtb/mt8192-asurada-spherion-r0.dtb
81 13:59:36.459097 total size: 47278 (0 MB)
82 13:59:36.459160 No compression specified
83 13:59:36.460248 progress 69 % (0 MB)
84 13:59:36.460524 progress 100 % (0 MB)
85 13:59:36.460681 0 MB downloaded in 0.00 s (28.51 MB/s)
86 13:59:36.460804 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:59:36.461025 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:59:36.461113 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:59:36.461195 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:59:36.461311 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:59:36.461381 saving as /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/modules/modules.tar
93 13:59:36.461443 total size: 8623988 (8 MB)
94 13:59:36.461504 Using unxz to decompress xz
95 13:59:36.465875 progress 0 % (0 MB)
96 13:59:36.486861 progress 5 % (0 MB)
97 13:59:36.510410 progress 10 % (0 MB)
98 13:59:36.533797 progress 15 % (1 MB)
99 13:59:36.556971 progress 20 % (1 MB)
100 13:59:36.581127 progress 25 % (2 MB)
101 13:59:36.606869 progress 30 % (2 MB)
102 13:59:36.633157 progress 35 % (2 MB)
103 13:59:36.656282 progress 40 % (3 MB)
104 13:59:36.680459 progress 45 % (3 MB)
105 13:59:36.705515 progress 50 % (4 MB)
106 13:59:36.729873 progress 55 % (4 MB)
107 13:59:36.754946 progress 60 % (4 MB)
108 13:59:36.783066 progress 65 % (5 MB)
109 13:59:36.808837 progress 70 % (5 MB)
110 13:59:36.832526 progress 75 % (6 MB)
111 13:59:36.860517 progress 80 % (6 MB)
112 13:59:36.886290 progress 85 % (7 MB)
113 13:59:36.911648 progress 90 % (7 MB)
114 13:59:36.943697 progress 95 % (7 MB)
115 13:59:36.972592 progress 100 % (8 MB)
116 13:59:36.977681 8 MB downloaded in 0.52 s (15.93 MB/s)
117 13:59:36.977940 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:59:36.978207 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:59:36.978301 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:59:36.978468 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:59:36.978600 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:59:36.978695 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:59:36.978923 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr
125 13:59:36.979064 makedir: /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin
126 13:59:36.979173 makedir: /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/tests
127 13:59:36.979276 makedir: /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/results
128 13:59:36.979390 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-add-keys
129 13:59:36.979545 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-add-sources
130 13:59:36.979680 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-background-process-start
131 13:59:36.979810 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-background-process-stop
132 13:59:36.979937 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-common-functions
133 13:59:36.980063 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-echo-ipv4
134 13:59:36.980190 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-install-packages
135 13:59:36.980317 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-installed-packages
136 13:59:36.980444 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-os-build
137 13:59:36.980570 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-probe-channel
138 13:59:36.980695 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-probe-ip
139 13:59:36.980821 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-target-ip
140 13:59:36.980946 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-target-mac
141 13:59:36.981071 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-target-storage
142 13:59:36.981201 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-test-case
143 13:59:36.981328 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-test-event
144 13:59:36.981453 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-test-feedback
145 13:59:36.981583 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-test-raise
146 13:59:36.981711 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-test-reference
147 13:59:36.981838 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-test-runner
148 13:59:36.981964 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-test-set
149 13:59:36.982093 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-test-shell
150 13:59:36.982225 Updating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-install-packages (oe)
151 13:59:36.982408 Updating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/bin/lava-installed-packages (oe)
152 13:59:36.982551 Creating /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/environment
153 13:59:36.982653 LAVA metadata
154 13:59:36.982727 - LAVA_JOB_ID=12682978
155 13:59:36.982795 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:59:36.982899 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:59:36.982968 skipped lava-vland-overlay
158 13:59:36.983044 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:59:36.983125 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:59:36.983194 skipped lava-multinode-overlay
161 13:59:36.983266 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:59:36.983351 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:59:36.983428 Loading test definitions
164 13:59:36.983520 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:59:36.983593 Using /lava-12682978 at stage 0
166 13:59:36.983924 uuid=12682978_1.5.2.3.1 testdef=None
167 13:59:36.984012 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:59:36.984095 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:59:36.984648 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:59:36.984866 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:59:36.985480 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:59:36.985707 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:59:36.986297 runner path: /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/0/tests/0_igt-gpu-panfrost test_uuid 12682978_1.5.2.3.1
176 13:59:36.986491 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:59:36.986698 Creating lava-test-runner.conf files
179 13:59:36.986761 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682978/lava-overlay-g3197iyr/lava-12682978/0 for stage 0
180 13:59:36.986854 - 0_igt-gpu-panfrost
181 13:59:36.986951 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:59:36.987036 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:59:36.993830 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:59:36.993941 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:59:36.994026 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:59:36.994111 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:59:36.994202 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:59:38.406449 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:59:38.406834 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:59:38.406951 extracting modules file /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682978/extract-overlay-ramdisk-38rxd9_y/ramdisk
191 13:59:38.636470 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:59:38.636638 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 13:59:38.636735 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682978/compress-overlay-q4mhar1b/overlay-1.5.2.4.tar.gz to ramdisk
194 13:59:38.636808 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682978/compress-overlay-q4mhar1b/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682978/extract-overlay-ramdisk-38rxd9_y/ramdisk
195 13:59:38.643561 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:59:38.643675 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 13:59:38.643771 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:59:38.643858 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 13:59:38.643936 Building ramdisk /var/lib/lava/dispatcher/tmp/12682978/extract-overlay-ramdisk-38rxd9_y/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682978/extract-overlay-ramdisk-38rxd9_y/ramdisk
200 13:59:39.694270 >> 369992 blocks
201 13:59:45.640842 rename /var/lib/lava/dispatcher/tmp/12682978/extract-overlay-ramdisk-38rxd9_y/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/ramdisk/ramdisk.cpio.gz
202 13:59:45.641279 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 13:59:45.641401 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 13:59:45.641499 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 13:59:45.641608 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/kernel/Image'
206 13:59:58.044081 Returned 0 in 12 seconds
207 13:59:58.145148 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/kernel/image.itb
208 13:59:58.995412 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:59:58.995791 output: Created: Thu Feb 1 13:59:58 2024
210 13:59:58.995867 output: Image 0 (kernel-1)
211 13:59:58.995934 output: Description:
212 13:59:58.995999 output: Created: Thu Feb 1 13:59:58 2024
213 13:59:58.996059 output: Type: Kernel Image
214 13:59:58.996119 output: Compression: lzma compressed
215 13:59:58.996176 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
216 13:59:58.996234 output: Architecture: AArch64
217 13:59:58.996289 output: OS: Linux
218 13:59:58.996342 output: Load Address: 0x00000000
219 13:59:58.996397 output: Entry Point: 0x00000000
220 13:59:58.996453 output: Hash algo: crc32
221 13:59:58.996507 output: Hash value: 5aa40db2
222 13:59:58.996562 output: Image 1 (fdt-1)
223 13:59:58.996616 output: Description: mt8192-asurada-spherion-r0
224 13:59:58.996668 output: Created: Thu Feb 1 13:59:58 2024
225 13:59:58.996720 output: Type: Flat Device Tree
226 13:59:58.996773 output: Compression: uncompressed
227 13:59:58.996824 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:59:58.996877 output: Architecture: AArch64
229 13:59:58.996928 output: Hash algo: crc32
230 13:59:58.996980 output: Hash value: cc4352de
231 13:59:58.997032 output: Image 2 (ramdisk-1)
232 13:59:58.997083 output: Description: unavailable
233 13:59:58.997134 output: Created: Thu Feb 1 13:59:58 2024
234 13:59:58.997186 output: Type: RAMDisk Image
235 13:59:58.997238 output: Compression: Unknown Compression
236 13:59:58.997290 output: Data Size: 56434467 Bytes = 55111.78 KiB = 53.82 MiB
237 13:59:58.997342 output: Architecture: AArch64
238 13:59:58.997394 output: OS: Linux
239 13:59:58.997445 output: Load Address: unavailable
240 13:59:58.997496 output: Entry Point: unavailable
241 13:59:58.997548 output: Hash algo: crc32
242 13:59:58.997599 output: Hash value: f47ed99c
243 13:59:58.997651 output: Default Configuration: 'conf-1'
244 13:59:58.997702 output: Configuration 0 (conf-1)
245 13:59:58.997754 output: Description: mt8192-asurada-spherion-r0
246 13:59:58.997806 output: Kernel: kernel-1
247 13:59:58.997858 output: Init Ramdisk: ramdisk-1
248 13:59:58.997909 output: FDT: fdt-1
249 13:59:58.997960 output: Loadables: kernel-1
250 13:59:58.998011 output:
251 13:59:58.998211 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 13:59:58.998310 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 13:59:58.998425 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 13:59:58.998526 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 13:59:58.998607 No LXC device requested
256 13:59:58.998688 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:59:58.998772 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 13:59:58.998848 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:59:58.998921 Checking files for TFTP limit of 4294967296 bytes.
260 13:59:58.999428 end: 1 tftp-deploy (duration 00:00:23) [common]
261 13:59:58.999531 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:59:58.999621 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:59:58.999744 substitutions:
264 13:59:58.999811 - {DTB}: 12682978/tftp-deploy-ut4sv5oc/dtb/mt8192-asurada-spherion-r0.dtb
265 13:59:58.999874 - {INITRD}: 12682978/tftp-deploy-ut4sv5oc/ramdisk/ramdisk.cpio.gz
266 13:59:58.999933 - {KERNEL}: 12682978/tftp-deploy-ut4sv5oc/kernel/Image
267 13:59:58.999991 - {LAVA_MAC}: None
268 13:59:59.000047 - {PRESEED_CONFIG}: None
269 13:59:59.000101 - {PRESEED_LOCAL}: None
270 13:59:59.000156 - {RAMDISK}: 12682978/tftp-deploy-ut4sv5oc/ramdisk/ramdisk.cpio.gz
271 13:59:59.000211 - {ROOT_PART}: None
272 13:59:59.000264 - {ROOT}: None
273 13:59:59.000317 - {SERVER_IP}: 192.168.201.1
274 13:59:59.000370 - {TEE}: None
275 13:59:59.000423 Parsed boot commands:
276 13:59:59.000476 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:59:59.000654 Parsed boot commands: tftpboot 192.168.201.1 12682978/tftp-deploy-ut4sv5oc/kernel/image.itb 12682978/tftp-deploy-ut4sv5oc/kernel/cmdline
278 13:59:59.000742 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:59:59.000826 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:59:59.000927 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:59:59.001010 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:59:59.001085 Not connected, no need to disconnect.
283 13:59:59.001160 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:59:59.001240 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:59:59.001305 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 13:59:59.005467 Setting prompt string to ['lava-test: # ']
287 13:59:59.005837 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:59:59.005946 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:59:59.006068 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:59:59.006189 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:59:59.006466 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 14:00:04.148980 >> Command sent successfully.
293 14:00:04.156122 Returned 0 in 5 seconds
294 14:00:04.256953 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 14:00:04.257964 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 14:00:04.258301 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 14:00:04.258631 Setting prompt string to 'Starting depthcharge on Spherion...'
299 14:00:04.258858 Changing prompt to 'Starting depthcharge on Spherion...'
300 14:00:04.259100 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 14:00:04.259901 [Enter `^Ec?' for help]
302 14:00:04.427605
303 14:00:04.428136
304 14:00:04.428496 F0: 102B 0000
305 14:00:04.428828
306 14:00:04.429140 F3: 1001 0000 [0200]
307 14:00:04.429442
308 14:00:04.430477 F3: 1001 0000
309 14:00:04.430901
310 14:00:04.431333 F7: 102D 0000
311 14:00:04.431659
312 14:00:04.431963 F1: 0000 0000
313 14:00:04.432260
314 14:00:04.434426 V0: 0000 0000 [0001]
315 14:00:04.434908
316 14:00:04.435246 00: 0007 8000
317 14:00:04.435584
318 14:00:04.438482 01: 0000 0000
319 14:00:04.438914
320 14:00:04.439263 BP: 0C00 0209 [0000]
321 14:00:04.439579
322 14:00:04.439879 G0: 1182 0000
323 14:00:04.442040
324 14:00:04.442508 EC: 0000 0021 [4000]
325 14:00:04.442851
326 14:00:04.443162 S7: 0000 0000 [0000]
327 14:00:04.446120
328 14:00:04.446577 CC: 0000 0000 [0001]
329 14:00:04.446915
330 14:00:04.447225 T0: 0000 0040 [010F]
331 14:00:04.449565
332 14:00:04.449985 Jump to BL
333 14:00:04.450325
334 14:00:04.474181
335 14:00:04.474713
336 14:00:04.475049
337 14:00:04.480924 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 14:00:04.483997 ARM64: Exception handlers installed.
339 14:00:04.487999 ARM64: Testing exception
340 14:00:04.492263 ARM64: Done test exception
341 14:00:04.499172 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 14:00:04.506310 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 14:00:04.513608 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 14:00:04.524477 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 14:00:04.530580 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 14:00:04.541361 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 14:00:04.551967 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 14:00:04.558240 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 14:00:04.576341 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 14:00:04.579638 WDT: Last reset was cold boot
351 14:00:04.582789 SPI1(PAD0) initialized at 2873684 Hz
352 14:00:04.586705 SPI5(PAD0) initialized at 992727 Hz
353 14:00:04.589723 VBOOT: Loading verstage.
354 14:00:04.596273 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 14:00:04.600274 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 14:00:04.603148 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 14:00:04.606462 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 14:00:04.614168 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 14:00:04.620495 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 14:00:04.631455 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 14:00:04.631916
362 14:00:04.632258
363 14:00:04.641146 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 14:00:04.644854 ARM64: Exception handlers installed.
365 14:00:04.647912 ARM64: Testing exception
366 14:00:04.648367 ARM64: Done test exception
367 14:00:04.654844 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 14:00:04.657846 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 14:00:04.672629 Probing TPM: . done!
370 14:00:04.673077 TPM ready after 0 ms
371 14:00:04.679535 Connected to device vid:did:rid of 1ae0:0028:00
372 14:00:04.686760 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 14:00:04.743197 Initialized TPM device CR50 revision 0
374 14:00:04.754634 tlcl_send_startup: Startup return code is 0
375 14:00:04.755103 TPM: setup succeeded
376 14:00:04.766305 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 14:00:04.775095 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 14:00:04.785781 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 14:00:04.796836 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 14:00:04.800119 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 14:00:04.808664 in-header: 03 07 00 00 08 00 00 00
382 14:00:04.812659 in-data: aa e4 47 04 13 02 00 00
383 14:00:04.816009 Chrome EC: UHEPI supported
384 14:00:04.823732 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 14:00:04.827099 in-header: 03 ad 00 00 08 00 00 00
386 14:00:04.827677 in-data: 00 20 20 08 00 00 00 00
387 14:00:04.831440 Phase 1
388 14:00:04.835108 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 14:00:04.838511 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 14:00:04.846515 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 14:00:04.846968 Recovery requested (1009000e)
392 14:00:04.859451 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 14:00:04.863320 tlcl_extend: response is 0
394 14:00:04.871450 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 14:00:04.877075 tlcl_extend: response is 0
396 14:00:04.884100 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 14:00:04.904234 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 14:00:04.910950 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 14:00:04.911470
400 14:00:04.911808
401 14:00:04.921592 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 14:00:04.925365 ARM64: Exception handlers installed.
403 14:00:04.925935 ARM64: Testing exception
404 14:00:04.928474 ARM64: Done test exception
405 14:00:04.949774 pmic_efuse_setting: Set efuses in 11 msecs
406 14:00:04.953381 pmwrap_interface_init: Select PMIF_VLD_RDY
407 14:00:04.960091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 14:00:04.963513 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 14:00:04.966310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 14:00:04.974186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 14:00:04.978110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 14:00:04.981660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 14:00:04.988963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 14:00:04.992645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 14:00:04.996317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 14:00:05.000176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 14:00:05.007746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 14:00:05.011332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 14:00:05.015196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 14:00:05.022828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 14:00:05.027043 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 14:00:05.034122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 14:00:05.037095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 14:00:05.045334 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 14:00:05.049022 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 14:00:05.056790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 14:00:05.059939 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 14:00:05.067788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 14:00:05.071168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 14:00:05.079156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 14:00:05.082239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 14:00:05.089565 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 14:00:05.092890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 14:00:05.100320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 14:00:05.103791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 14:00:05.107922 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 14:00:05.115353 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 14:00:05.118901 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 14:00:05.122100 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 14:00:05.130368 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 14:00:05.133683 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 14:00:05.137046 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 14:00:05.144643 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 14:00:05.148449 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 14:00:05.151968 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 14:00:05.155404 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 14:00:05.163110 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 14:00:05.167233 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 14:00:05.170155 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 14:00:05.174470 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 14:00:05.181418 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 14:00:05.185131 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 14:00:05.188586 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 14:00:05.191873 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 14:00:05.196043 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 14:00:05.200048 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 14:00:05.203537 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 14:00:05.211267 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 14:00:05.222455 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 14:00:05.226032 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 14:00:05.233019 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 14:00:05.244273 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 14:00:05.248317 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 14:00:05.251750 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 14:00:05.255436 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 14:00:05.263119 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 14:00:05.266816 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 14:00:05.273711 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 14:00:05.277372 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 14:00:05.287321 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 14:00:05.296554 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 14:00:05.305501 [RTC]rtc_get_frequency_meter,154: input=19, output=883
473 14:00:05.316796 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 14:00:05.325617 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 14:00:05.334469 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 14:00:05.344088 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 14:00:05.347822 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 14:00:05.355111 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 14:00:05.358547 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 14:00:05.361852 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 14:00:05.365574 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 14:00:05.369178 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 14:00:05.372880 ADC[4]: Raw value=901697 ID=7
484 14:00:05.376853 ADC[3]: Raw value=213336 ID=1
485 14:00:05.377273 RAM Code: 0x71
486 14:00:05.380381 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 14:00:05.387586 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 14:00:05.395173 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 14:00:05.402519 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 14:00:05.405839 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 14:00:05.409361 in-header: 03 07 00 00 08 00 00 00
492 14:00:05.413550 in-data: aa e4 47 04 13 02 00 00
493 14:00:05.413851 Chrome EC: UHEPI supported
494 14:00:05.420528 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 14:00:05.424694 in-header: 03 ed 00 00 08 00 00 00
496 14:00:05.428252 in-data: 80 20 60 08 00 00 00 00
497 14:00:05.432548 MRC: failed to locate region type 0.
498 14:00:05.435961 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 14:00:05.439833 DRAM-K: Running full calibration
500 14:00:05.446861 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 14:00:05.450580 header.status = 0x0
502 14:00:05.451018 header.version = 0x6 (expected: 0x6)
503 14:00:05.454454 header.size = 0xd00 (expected: 0xd00)
504 14:00:05.458737 header.flags = 0x0
505 14:00:05.461606 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 14:00:05.481474 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 14:00:05.488452 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 14:00:05.492646 dram_init: ddr_geometry: 2
509 14:00:05.492964 [EMI] MDL number = 2
510 14:00:05.495721 [EMI] Get MDL freq = 0
511 14:00:05.496113 dram_init: ddr_type: 0
512 14:00:05.499921 is_discrete_lpddr4: 1
513 14:00:05.503481 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 14:00:05.503869
515 14:00:05.504162
516 14:00:05.504505 [Bian_co] ETT version 0.0.0.1
517 14:00:05.510872 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 14:00:05.511310
519 14:00:05.514518 dramc_set_vcore_voltage set vcore to 650000
520 14:00:05.514858 Read voltage for 800, 4
521 14:00:05.517967 Vio18 = 0
522 14:00:05.518299 Vcore = 650000
523 14:00:05.518603 Vdram = 0
524 14:00:05.521662 Vddq = 0
525 14:00:05.522019 Vmddr = 0
526 14:00:05.522319 dram_init: config_dvfs: 1
527 14:00:05.528732 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 14:00:05.532169 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 14:00:05.538620 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 14:00:05.541901 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 14:00:05.545106 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 14:00:05.548468 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 14:00:05.551703 MEM_TYPE=3, freq_sel=18
534 14:00:05.555440 sv_algorithm_assistance_LP4_1600
535 14:00:05.559241 ============ PULL DRAM RESETB DOWN ============
536 14:00:05.562063 ========== PULL DRAM RESETB DOWN end =========
537 14:00:05.565640 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 14:00:05.569077 ===================================
539 14:00:05.572254 LPDDR4 DRAM CONFIGURATION
540 14:00:05.575521 ===================================
541 14:00:05.578955 EX_ROW_EN[0] = 0x0
542 14:00:05.579403 EX_ROW_EN[1] = 0x0
543 14:00:05.582189 LP4Y_EN = 0x0
544 14:00:05.582694 WORK_FSP = 0x0
545 14:00:05.585488 WL = 0x2
546 14:00:05.585936 RL = 0x2
547 14:00:05.589142 BL = 0x2
548 14:00:05.589576 RPST = 0x0
549 14:00:05.592426 RD_PRE = 0x0
550 14:00:05.592869 WR_PRE = 0x1
551 14:00:05.595750 WR_PST = 0x0
552 14:00:05.596172 DBI_WR = 0x0
553 14:00:05.599353 DBI_RD = 0x0
554 14:00:05.599775 OTF = 0x1
555 14:00:05.602270 ===================================
556 14:00:05.605608 ===================================
557 14:00:05.609141 ANA top config
558 14:00:05.612381 ===================================
559 14:00:05.615792 DLL_ASYNC_EN = 0
560 14:00:05.616214 ALL_SLAVE_EN = 1
561 14:00:05.619287 NEW_RANK_MODE = 1
562 14:00:05.623183 DLL_IDLE_MODE = 1
563 14:00:05.626081 LP45_APHY_COMB_EN = 1
564 14:00:05.626650 TX_ODT_DIS = 1
565 14:00:05.629245 NEW_8X_MODE = 1
566 14:00:05.632952 ===================================
567 14:00:05.636156 ===================================
568 14:00:05.639230 data_rate = 1600
569 14:00:05.642954 CKR = 1
570 14:00:05.645904 DQ_P2S_RATIO = 8
571 14:00:05.649388 ===================================
572 14:00:05.649959 CA_P2S_RATIO = 8
573 14:00:05.652600 DQ_CA_OPEN = 0
574 14:00:05.656246 DQ_SEMI_OPEN = 0
575 14:00:05.659383 CA_SEMI_OPEN = 0
576 14:00:05.662688 CA_FULL_RATE = 0
577 14:00:05.666326 DQ_CKDIV4_EN = 1
578 14:00:05.666911 CA_CKDIV4_EN = 1
579 14:00:05.669665 CA_PREDIV_EN = 0
580 14:00:05.673186 PH8_DLY = 0
581 14:00:05.676186 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 14:00:05.679526 DQ_AAMCK_DIV = 4
583 14:00:05.679953 CA_AAMCK_DIV = 4
584 14:00:05.683254 CA_ADMCK_DIV = 4
585 14:00:05.686475 DQ_TRACK_CA_EN = 0
586 14:00:05.689715 CA_PICK = 800
587 14:00:05.693397 CA_MCKIO = 800
588 14:00:05.697055 MCKIO_SEMI = 0
589 14:00:05.700805 PLL_FREQ = 3068
590 14:00:05.701365 DQ_UI_PI_RATIO = 32
591 14:00:05.703946 CA_UI_PI_RATIO = 0
592 14:00:05.707775 ===================================
593 14:00:05.711222 ===================================
594 14:00:05.714857 memory_type:LPDDR4
595 14:00:05.715281 GP_NUM : 10
596 14:00:05.718754 SRAM_EN : 1
597 14:00:05.719219 MD32_EN : 0
598 14:00:05.722518 ===================================
599 14:00:05.726059 [ANA_INIT] >>>>>>>>>>>>>>
600 14:00:05.730492 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 14:00:05.731083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 14:00:05.733718 ===================================
603 14:00:05.737254 data_rate = 1600,PCW = 0X7600
604 14:00:05.740251 ===================================
605 14:00:05.743820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 14:00:05.751014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 14:00:05.753503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 14:00:05.760547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 14:00:05.763871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 14:00:05.767057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 14:00:05.767435 [ANA_INIT] flow start
612 14:00:05.770601 [ANA_INIT] PLL >>>>>>>>
613 14:00:05.774002 [ANA_INIT] PLL <<<<<<<<
614 14:00:05.774497 [ANA_INIT] MIDPI >>>>>>>>
615 14:00:05.777310 [ANA_INIT] MIDPI <<<<<<<<
616 14:00:05.780207 [ANA_INIT] DLL >>>>>>>>
617 14:00:05.780669 [ANA_INIT] flow end
618 14:00:05.787620 ============ LP4 DIFF to SE enter ============
619 14:00:05.790825 ============ LP4 DIFF to SE exit ============
620 14:00:05.793803 [ANA_INIT] <<<<<<<<<<<<<
621 14:00:05.797977 [Flow] Enable top DCM control >>>>>
622 14:00:05.800759 [Flow] Enable top DCM control <<<<<
623 14:00:05.801291 Enable DLL master slave shuffle
624 14:00:05.807380 ==============================================================
625 14:00:05.810951 Gating Mode config
626 14:00:05.814378 ==============================================================
627 14:00:05.817745 Config description:
628 14:00:05.827523 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 14:00:05.834587 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 14:00:05.838212 SELPH_MODE 0: By rank 1: By Phase
631 14:00:05.844770 ==============================================================
632 14:00:05.847389 GAT_TRACK_EN = 1
633 14:00:05.850696 RX_GATING_MODE = 2
634 14:00:05.851121 RX_GATING_TRACK_MODE = 2
635 14:00:05.854454 SELPH_MODE = 1
636 14:00:05.857535 PICG_EARLY_EN = 1
637 14:00:05.861194 VALID_LAT_VALUE = 1
638 14:00:05.867492 ==============================================================
639 14:00:05.871091 Enter into Gating configuration >>>>
640 14:00:05.874903 Exit from Gating configuration <<<<
641 14:00:05.877936 Enter into DVFS_PRE_config >>>>>
642 14:00:05.887679 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 14:00:05.891127 Exit from DVFS_PRE_config <<<<<
644 14:00:05.894489 Enter into PICG configuration >>>>
645 14:00:05.897919 Exit from PICG configuration <<<<
646 14:00:05.900857 [RX_INPUT] configuration >>>>>
647 14:00:05.901290 [RX_INPUT] configuration <<<<<
648 14:00:05.908121 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 14:00:05.914443 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 14:00:05.918639 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 14:00:05.925926 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 14:00:05.932633 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 14:00:05.938973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 14:00:05.942516 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 14:00:05.945788 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 14:00:05.948723 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 14:00:05.956127 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 14:00:05.958962 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 14:00:05.962336 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 14:00:05.965933 ===================================
661 14:00:05.969199 LPDDR4 DRAM CONFIGURATION
662 14:00:05.972761 ===================================
663 14:00:05.973191 EX_ROW_EN[0] = 0x0
664 14:00:05.975965 EX_ROW_EN[1] = 0x0
665 14:00:05.979277 LP4Y_EN = 0x0
666 14:00:05.979748 WORK_FSP = 0x0
667 14:00:05.982591 WL = 0x2
668 14:00:05.983064 RL = 0x2
669 14:00:05.985915 BL = 0x2
670 14:00:05.986443 RPST = 0x0
671 14:00:05.989388 RD_PRE = 0x0
672 14:00:05.989994 WR_PRE = 0x1
673 14:00:05.992607 WR_PST = 0x0
674 14:00:05.993133 DBI_WR = 0x0
675 14:00:05.996008 DBI_RD = 0x0
676 14:00:05.996537 OTF = 0x1
677 14:00:05.999380 ===================================
678 14:00:06.002939 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 14:00:06.009265 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 14:00:06.012782 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 14:00:06.016122 ===================================
682 14:00:06.019703 LPDDR4 DRAM CONFIGURATION
683 14:00:06.022864 ===================================
684 14:00:06.023314 EX_ROW_EN[0] = 0x10
685 14:00:06.025720 EX_ROW_EN[1] = 0x0
686 14:00:06.026214 LP4Y_EN = 0x0
687 14:00:06.029330 WORK_FSP = 0x0
688 14:00:06.029878 WL = 0x2
689 14:00:06.032744 RL = 0x2
690 14:00:06.033169 BL = 0x2
691 14:00:06.036437 RPST = 0x0
692 14:00:06.036911 RD_PRE = 0x0
693 14:00:06.039332 WR_PRE = 0x1
694 14:00:06.039785 WR_PST = 0x0
695 14:00:06.043018 DBI_WR = 0x0
696 14:00:06.043441 DBI_RD = 0x0
697 14:00:06.045835 OTF = 0x1
698 14:00:06.049684 ===================================
699 14:00:06.056207 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 14:00:06.059379 nWR fixed to 40
701 14:00:06.062879 [ModeRegInit_LP4] CH0 RK0
702 14:00:06.063304 [ModeRegInit_LP4] CH0 RK1
703 14:00:06.066540 [ModeRegInit_LP4] CH1 RK0
704 14:00:06.069567 [ModeRegInit_LP4] CH1 RK1
705 14:00:06.069993 match AC timing 13
706 14:00:06.076425 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 14:00:06.079952 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 14:00:06.083262 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 14:00:06.089899 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 14:00:06.093185 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 14:00:06.093790 [EMI DOE] emi_dcm 0
712 14:00:06.100020 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 14:00:06.100633 ==
714 14:00:06.103531 Dram Type= 6, Freq= 0, CH_0, rank 0
715 14:00:06.106362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 14:00:06.106880 ==
717 14:00:06.113313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 14:00:06.116461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 14:00:06.127106 [CA 0] Center 37 (7~68) winsize 62
720 14:00:06.130253 [CA 1] Center 37 (6~68) winsize 63
721 14:00:06.133539 [CA 2] Center 35 (4~66) winsize 63
722 14:00:06.136856 [CA 3] Center 34 (4~65) winsize 62
723 14:00:06.140438 [CA 4] Center 34 (4~65) winsize 62
724 14:00:06.143694 [CA 5] Center 34 (4~64) winsize 61
725 14:00:06.144122
726 14:00:06.147407 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 14:00:06.147959
728 14:00:06.150473 [CATrainingPosCal] consider 1 rank data
729 14:00:06.154141 u2DelayCellTimex100 = 270/100 ps
730 14:00:06.157408 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 14:00:06.160527 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
732 14:00:06.164381 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
733 14:00:06.167196 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
734 14:00:06.174110 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 14:00:06.177822 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
736 14:00:06.178521
737 14:00:06.180602 CA PerBit enable=1, Macro0, CA PI delay=34
738 14:00:06.181235
739 14:00:06.184041 [CBTSetCACLKResult] CA Dly = 34
740 14:00:06.184465 CS Dly: 4 (0~35)
741 14:00:06.184803 ==
742 14:00:06.187572 Dram Type= 6, Freq= 0, CH_0, rank 1
743 14:00:06.190971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 14:00:06.194214 ==
745 14:00:06.197667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 14:00:06.204083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 14:00:06.212702 [CA 0] Center 37 (7~68) winsize 62
748 14:00:06.216433 [CA 1] Center 37 (6~68) winsize 63
749 14:00:06.219577 [CA 2] Center 35 (4~66) winsize 63
750 14:00:06.223062 [CA 3] Center 35 (4~66) winsize 63
751 14:00:06.226474 [CA 4] Center 34 (4~65) winsize 62
752 14:00:06.229748 [CA 5] Center 33 (3~64) winsize 62
753 14:00:06.230172
754 14:00:06.233015 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 14:00:06.233436
756 14:00:06.236424 [CATrainingPosCal] consider 2 rank data
757 14:00:06.240312 u2DelayCellTimex100 = 270/100 ps
758 14:00:06.243092 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 14:00:06.246752 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
760 14:00:06.252868 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
761 14:00:06.256497 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
762 14:00:06.259482 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
763 14:00:06.263291 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 14:00:06.263707
765 14:00:06.266687 CA PerBit enable=1, Macro0, CA PI delay=34
766 14:00:06.267274
767 14:00:06.269489 [CBTSetCACLKResult] CA Dly = 34
768 14:00:06.269967 CS Dly: 5 (0~38)
769 14:00:06.270315
770 14:00:06.273701 ----->DramcWriteLeveling(PI) begin...
771 14:00:06.274145 ==
772 14:00:06.276907 Dram Type= 6, Freq= 0, CH_0, rank 0
773 14:00:06.284274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 14:00:06.284916 ==
775 14:00:06.287130 Write leveling (Byte 0): 29 => 29
776 14:00:06.287755 Write leveling (Byte 1): 29 => 29
777 14:00:06.291283 DramcWriteLeveling(PI) end<-----
778 14:00:06.291919
779 14:00:06.292271 ==
780 14:00:06.294766 Dram Type= 6, Freq= 0, CH_0, rank 0
781 14:00:06.299104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 14:00:06.299554 ==
783 14:00:06.302303 [Gating] SW mode calibration
784 14:00:06.308690 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 14:00:06.316715 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 14:00:06.319590 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 14:00:06.322808 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 14:00:06.326069 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 14:00:06.332749 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 14:00:06.336048 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 14:00:06.339593 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 14:00:06.346203 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 14:00:06.349354 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 14:00:06.352681 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 14:00:06.359686 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 14:00:06.363244 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 14:00:06.366729 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 14:00:06.373048 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 14:00:06.376245 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 14:00:06.379596 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 14:00:06.382936 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 14:00:06.389780 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 14:00:06.393085 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 14:00:06.396532 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
805 14:00:06.403089 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 14:00:06.406970 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 14:00:06.410229 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 14:00:06.417059 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 14:00:06.420166 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 14:00:06.423722 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 14:00:06.429951 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 14:00:06.433566 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 14:00:06.437145 0 9 12 | B1->B0 | 2525 3333 | 1 1 | (1 1) (1 1)
814 14:00:06.439887 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 14:00:06.447124 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 14:00:06.450106 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 14:00:06.453456 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 14:00:06.460432 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 14:00:06.463574 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 14:00:06.466900 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
821 14:00:06.473873 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
822 14:00:06.477248 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 14:00:06.480536 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 14:00:06.486987 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 14:00:06.490153 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 14:00:06.493890 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 14:00:06.497241 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 14:00:06.504328 0 11 8 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
829 14:00:06.507455 0 11 12 | B1->B0 | 3535 4040 | 0 0 | (0 0) (0 0)
830 14:00:06.510625 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 14:00:06.517444 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 14:00:06.521311 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 14:00:06.524674 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 14:00:06.530971 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 14:00:06.534142 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 14:00:06.538075 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 14:00:06.544062 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 14:00:06.547279 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 14:00:06.550835 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 14:00:06.554429 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 14:00:06.560700 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 14:00:06.564512 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 14:00:06.567730 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 14:00:06.574655 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 14:00:06.577571 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 14:00:06.581170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 14:00:06.587541 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 14:00:06.590846 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 14:00:06.595002 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 14:00:06.601452 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 14:00:06.604696 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 14:00:06.607793 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 14:00:06.614835 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 14:00:06.615205 Total UI for P1: 0, mck2ui 16
855 14:00:06.617903 best dqsien dly found for B0: ( 0, 14, 8)
856 14:00:06.621841 Total UI for P1: 0, mck2ui 16
857 14:00:06.625167 best dqsien dly found for B1: ( 0, 14, 8)
858 14:00:06.627986 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 14:00:06.631933 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 14:00:06.632342
861 14:00:06.638447 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 14:00:06.642120 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 14:00:06.642549 [Gating] SW calibration Done
864 14:00:06.645627 ==
865 14:00:06.648111 Dram Type= 6, Freq= 0, CH_0, rank 0
866 14:00:06.651888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 14:00:06.652309 ==
868 14:00:06.652656 RX Vref Scan: 0
869 14:00:06.652893
870 14:00:06.654851 RX Vref 0 -> 0, step: 1
871 14:00:06.655234
872 14:00:06.658207 RX Delay -130 -> 252, step: 16
873 14:00:06.661503 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 14:00:06.665016 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 14:00:06.668422 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
876 14:00:06.675400 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
877 14:00:06.678770 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 14:00:06.682237 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 14:00:06.685891 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 14:00:06.689007 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 14:00:06.692426 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 14:00:06.699023 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 14:00:06.702199 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 14:00:06.705729 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 14:00:06.709082 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
886 14:00:06.712601 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 14:00:06.718977 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 14:00:06.722574 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 14:00:06.722885 ==
890 14:00:06.725868 Dram Type= 6, Freq= 0, CH_0, rank 0
891 14:00:06.729180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 14:00:06.729481 ==
893 14:00:06.732173 DQS Delay:
894 14:00:06.732544 DQS0 = 0, DQS1 = 0
895 14:00:06.732786 DQM Delay:
896 14:00:06.735496 DQM0 = 82, DQM1 = 76
897 14:00:06.735797 DQ Delay:
898 14:00:06.738932 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
899 14:00:06.742939 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
900 14:00:06.745912 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
901 14:00:06.749363 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
902 14:00:06.749751
903 14:00:06.750087
904 14:00:06.750431 ==
905 14:00:06.752649 Dram Type= 6, Freq= 0, CH_0, rank 0
906 14:00:06.755994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 14:00:06.759535 ==
908 14:00:06.759832
909 14:00:06.760066
910 14:00:06.760282 TX Vref Scan disable
911 14:00:06.762805 == TX Byte 0 ==
912 14:00:06.766081 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 14:00:06.769137 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 14:00:06.772545 == TX Byte 1 ==
915 14:00:06.776126 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 14:00:06.779126 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 14:00:06.782666 ==
918 14:00:06.782973 Dram Type= 6, Freq= 0, CH_0, rank 0
919 14:00:06.789238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 14:00:06.789744 ==
921 14:00:06.801510 TX Vref=22, minBit 0, minWin=27, winSum=439
922 14:00:06.805187 TX Vref=24, minBit 0, minWin=27, winSum=444
923 14:00:06.808384 TX Vref=26, minBit 8, minWin=27, winSum=445
924 14:00:06.811879 TX Vref=28, minBit 15, minWin=27, winSum=452
925 14:00:06.815117 TX Vref=30, minBit 13, minWin=27, winSum=453
926 14:00:06.818360 TX Vref=32, minBit 3, minWin=27, winSum=450
927 14:00:06.825322 [TxChooseVref] Worse bit 13, Min win 27, Win sum 453, Final Vref 30
928 14:00:06.825711
929 14:00:06.828536 Final TX Range 1 Vref 30
930 14:00:06.828956
931 14:00:06.829273 ==
932 14:00:06.831654 Dram Type= 6, Freq= 0, CH_0, rank 0
933 14:00:06.835435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 14:00:06.835829 ==
935 14:00:06.836140
936 14:00:06.836427
937 14:00:06.838756 TX Vref Scan disable
938 14:00:06.841953 == TX Byte 0 ==
939 14:00:06.845901 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 14:00:06.848987 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 14:00:06.852261 == TX Byte 1 ==
942 14:00:06.855563 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 14:00:06.858833 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 14:00:06.859240
945 14:00:06.861973 [DATLAT]
946 14:00:06.862534 Freq=800, CH0 RK0
947 14:00:06.862916
948 14:00:06.865861 DATLAT Default: 0xa
949 14:00:06.866247 0, 0xFFFF, sum = 0
950 14:00:06.869292 1, 0xFFFF, sum = 0
951 14:00:06.869721 2, 0xFFFF, sum = 0
952 14:00:06.872317 3, 0xFFFF, sum = 0
953 14:00:06.872712 4, 0xFFFF, sum = 0
954 14:00:06.875728 5, 0xFFFF, sum = 0
955 14:00:06.876136 6, 0xFFFF, sum = 0
956 14:00:06.878919 7, 0xFFFF, sum = 0
957 14:00:06.879315 8, 0xFFFF, sum = 0
958 14:00:06.882458 9, 0x0, sum = 1
959 14:00:06.882855 10, 0x0, sum = 2
960 14:00:06.885379 11, 0x0, sum = 3
961 14:00:06.885793 12, 0x0, sum = 4
962 14:00:06.888995 best_step = 10
963 14:00:06.889380
964 14:00:06.889683 ==
965 14:00:06.892526 Dram Type= 6, Freq= 0, CH_0, rank 0
966 14:00:06.895443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 14:00:06.895874 ==
968 14:00:06.896238 RX Vref Scan: 1
969 14:00:06.899091
970 14:00:06.899572 Set Vref Range= 32 -> 127
971 14:00:06.899889
972 14:00:06.902567 RX Vref 32 -> 127, step: 1
973 14:00:06.902957
974 14:00:06.905808 RX Delay -95 -> 252, step: 8
975 14:00:06.906198
976 14:00:06.909421 Set Vref, RX VrefLevel [Byte0]: 32
977 14:00:06.912141 [Byte1]: 32
978 14:00:06.912599
979 14:00:06.916126 Set Vref, RX VrefLevel [Byte0]: 33
980 14:00:06.919413 [Byte1]: 33
981 14:00:06.919828
982 14:00:06.923064 Set Vref, RX VrefLevel [Byte0]: 34
983 14:00:06.926456 [Byte1]: 34
984 14:00:06.929624
985 14:00:06.930024 Set Vref, RX VrefLevel [Byte0]: 35
986 14:00:06.932933 [Byte1]: 35
987 14:00:06.937005
988 14:00:06.937405 Set Vref, RX VrefLevel [Byte0]: 36
989 14:00:06.940585 [Byte1]: 36
990 14:00:06.944637
991 14:00:06.945075 Set Vref, RX VrefLevel [Byte0]: 37
992 14:00:06.948289 [Byte1]: 37
993 14:00:06.952417
994 14:00:06.952810 Set Vref, RX VrefLevel [Byte0]: 38
995 14:00:06.956398 [Byte1]: 38
996 14:00:06.960548
997 14:00:06.960938 Set Vref, RX VrefLevel [Byte0]: 39
998 14:00:06.963755 [Byte1]: 39
999 14:00:06.968320
1000 14:00:06.968879 Set Vref, RX VrefLevel [Byte0]: 40
1001 14:00:06.971864 [Byte1]: 40
1002 14:00:06.975422
1003 14:00:06.975848 Set Vref, RX VrefLevel [Byte0]: 41
1004 14:00:06.979018 [Byte1]: 41
1005 14:00:06.983501
1006 14:00:06.983914 Set Vref, RX VrefLevel [Byte0]: 42
1007 14:00:06.987087 [Byte1]: 42
1008 14:00:06.990629
1009 14:00:06.991096 Set Vref, RX VrefLevel [Byte0]: 43
1010 14:00:06.993717 [Byte1]: 43
1011 14:00:06.997782
1012 14:00:06.998167 Set Vref, RX VrefLevel [Byte0]: 44
1013 14:00:07.001619 [Byte1]: 44
1014 14:00:07.005726
1015 14:00:07.006107 Set Vref, RX VrefLevel [Byte0]: 45
1016 14:00:07.009007 [Byte1]: 45
1017 14:00:07.013147
1018 14:00:07.013627 Set Vref, RX VrefLevel [Byte0]: 46
1019 14:00:07.016824 [Byte1]: 46
1020 14:00:07.020674
1021 14:00:07.021180 Set Vref, RX VrefLevel [Byte0]: 47
1022 14:00:07.023964 [Byte1]: 47
1023 14:00:07.028479
1024 14:00:07.028878 Set Vref, RX VrefLevel [Byte0]: 48
1025 14:00:07.031451 [Byte1]: 48
1026 14:00:07.035632
1027 14:00:07.036008 Set Vref, RX VrefLevel [Byte0]: 49
1028 14:00:07.039006 [Byte1]: 49
1029 14:00:07.043758
1030 14:00:07.044132 Set Vref, RX VrefLevel [Byte0]: 50
1031 14:00:07.046779 [Byte1]: 50
1032 14:00:07.051079
1033 14:00:07.051509 Set Vref, RX VrefLevel [Byte0]: 51
1034 14:00:07.054646 [Byte1]: 51
1035 14:00:07.059398
1036 14:00:07.059780 Set Vref, RX VrefLevel [Byte0]: 52
1037 14:00:07.061658 [Byte1]: 52
1038 14:00:07.066087
1039 14:00:07.066513 Set Vref, RX VrefLevel [Byte0]: 53
1040 14:00:07.069582 [Byte1]: 53
1041 14:00:07.074022
1042 14:00:07.074460 Set Vref, RX VrefLevel [Byte0]: 54
1043 14:00:07.077585 [Byte1]: 54
1044 14:00:07.081577
1045 14:00:07.081966 Set Vref, RX VrefLevel [Byte0]: 55
1046 14:00:07.084771 [Byte1]: 55
1047 14:00:07.089048
1048 14:00:07.089437 Set Vref, RX VrefLevel [Byte0]: 56
1049 14:00:07.092421 [Byte1]: 56
1050 14:00:07.096757
1051 14:00:07.097269 Set Vref, RX VrefLevel [Byte0]: 57
1052 14:00:07.099992 [Byte1]: 57
1053 14:00:07.104399
1054 14:00:07.104773 Set Vref, RX VrefLevel [Byte0]: 58
1055 14:00:07.107537 [Byte1]: 58
1056 14:00:07.111776
1057 14:00:07.112301 Set Vref, RX VrefLevel [Byte0]: 59
1058 14:00:07.115385 [Byte1]: 59
1059 14:00:07.119362
1060 14:00:07.119740 Set Vref, RX VrefLevel [Byte0]: 60
1061 14:00:07.122542 [Byte1]: 60
1062 14:00:07.127241
1063 14:00:07.127616 Set Vref, RX VrefLevel [Byte0]: 61
1064 14:00:07.130712 [Byte1]: 61
1065 14:00:07.134700
1066 14:00:07.135083 Set Vref, RX VrefLevel [Byte0]: 62
1067 14:00:07.137915 [Byte1]: 62
1068 14:00:07.142284
1069 14:00:07.142723 Set Vref, RX VrefLevel [Byte0]: 63
1070 14:00:07.145546 [Byte1]: 63
1071 14:00:07.149975
1072 14:00:07.150357 Set Vref, RX VrefLevel [Byte0]: 64
1073 14:00:07.153002 [Byte1]: 64
1074 14:00:07.157599
1075 14:00:07.158044 Set Vref, RX VrefLevel [Byte0]: 65
1076 14:00:07.160913 [Byte1]: 65
1077 14:00:07.165480
1078 14:00:07.165857 Set Vref, RX VrefLevel [Byte0]: 66
1079 14:00:07.167897 [Byte1]: 66
1080 14:00:07.172672
1081 14:00:07.173068 Set Vref, RX VrefLevel [Byte0]: 67
1082 14:00:07.175788 [Byte1]: 67
1083 14:00:07.180219
1084 14:00:07.180621 Set Vref, RX VrefLevel [Byte0]: 68
1085 14:00:07.183453 [Byte1]: 68
1086 14:00:07.187726
1087 14:00:07.188107 Set Vref, RX VrefLevel [Byte0]: 69
1088 14:00:07.191441 [Byte1]: 69
1089 14:00:07.195804
1090 14:00:07.196219 Set Vref, RX VrefLevel [Byte0]: 70
1091 14:00:07.198569 [Byte1]: 70
1092 14:00:07.203059
1093 14:00:07.203444 Set Vref, RX VrefLevel [Byte0]: 71
1094 14:00:07.206338 [Byte1]: 71
1095 14:00:07.210529
1096 14:00:07.210904 Set Vref, RX VrefLevel [Byte0]: 72
1097 14:00:07.213699 [Byte1]: 72
1098 14:00:07.218094
1099 14:00:07.218531 Set Vref, RX VrefLevel [Byte0]: 73
1100 14:00:07.221230 [Byte1]: 73
1101 14:00:07.226308
1102 14:00:07.226738 Set Vref, RX VrefLevel [Byte0]: 74
1103 14:00:07.229542 [Byte1]: 74
1104 14:00:07.233319
1105 14:00:07.236719 Set Vref, RX VrefLevel [Byte0]: 75
1106 14:00:07.237128 [Byte1]: 75
1107 14:00:07.241148
1108 14:00:07.241558 Set Vref, RX VrefLevel [Byte0]: 76
1109 14:00:07.244097 [Byte1]: 76
1110 14:00:07.248387
1111 14:00:07.248892 Set Vref, RX VrefLevel [Byte0]: 77
1112 14:00:07.252174 [Byte1]: 77
1113 14:00:07.256603
1114 14:00:07.257141 Set Vref, RX VrefLevel [Byte0]: 78
1115 14:00:07.260045 [Byte1]: 78
1116 14:00:07.263561
1117 14:00:07.263936 Final RX Vref Byte 0 = 61 to rank0
1118 14:00:07.267321 Final RX Vref Byte 1 = 58 to rank0
1119 14:00:07.270753 Final RX Vref Byte 0 = 61 to rank1
1120 14:00:07.274312 Final RX Vref Byte 1 = 58 to rank1==
1121 14:00:07.277249 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 14:00:07.280910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 14:00:07.283898 ==
1124 14:00:07.284333 DQS Delay:
1125 14:00:07.284740 DQS0 = 0, DQS1 = 0
1126 14:00:07.287188 DQM Delay:
1127 14:00:07.287661 DQM0 = 86, DQM1 = 79
1128 14:00:07.290708 DQ Delay:
1129 14:00:07.293604 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1130 14:00:07.294006 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1131 14:00:07.297587 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1132 14:00:07.300559 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1133 14:00:07.301101
1134 14:00:07.303705
1135 14:00:07.310879 [DQSOSCAuto] RK0, (LSB)MR18= 0x270e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1136 14:00:07.314162 CH0 RK0: MR19=606, MR18=270E
1137 14:00:07.321134 CH0_RK0: MR19=0x606, MR18=0x270E, DQSOSC=400, MR23=63, INC=92, DEC=61
1138 14:00:07.321538
1139 14:00:07.324010 ----->DramcWriteLeveling(PI) begin...
1140 14:00:07.324397 ==
1141 14:00:07.327132 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 14:00:07.331059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 14:00:07.331468 ==
1144 14:00:07.334116 Write leveling (Byte 0): 30 => 30
1145 14:00:07.337271 Write leveling (Byte 1): 29 => 29
1146 14:00:07.341048 DramcWriteLeveling(PI) end<-----
1147 14:00:07.341456
1148 14:00:07.341793 ==
1149 14:00:07.344197 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 14:00:07.347253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 14:00:07.347643 ==
1152 14:00:07.351155 [Gating] SW mode calibration
1153 14:00:07.358085 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 14:00:07.401520 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 14:00:07.402272 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 14:00:07.402709 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 14:00:07.403090 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1158 14:00:07.403406 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 14:00:07.403754 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 14:00:07.404194 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 14:00:07.404612 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 14:00:07.405054 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 14:00:07.405457 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 14:00:07.408382 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 14:00:07.411976 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 14:00:07.415159 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 14:00:07.418555 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 14:00:07.425703 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 14:00:07.428321 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 14:00:07.432171 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 14:00:07.438471 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1172 14:00:07.442021 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1173 14:00:07.445469 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1174 14:00:07.452287 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 14:00:07.455350 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 14:00:07.459066 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 14:00:07.465358 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 14:00:07.469199 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 14:00:07.472391 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 14:00:07.475848 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 14:00:07.483012 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1182 14:00:07.485297 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1183 14:00:07.489300 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 14:00:07.495921 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 14:00:07.499116 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 14:00:07.502750 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 14:00:07.508631 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 14:00:07.512104 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1189 14:00:07.515499 0 10 8 | B1->B0 | 3030 2525 | 0 1 | (0 0) (1 0)
1190 14:00:07.522457 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1191 14:00:07.526276 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 14:00:07.528995 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 14:00:07.533512 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 14:00:07.540772 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 14:00:07.543883 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 14:00:07.548113 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
1197 14:00:07.550938 0 11 8 | B1->B0 | 3131 4040 | 1 0 | (0 0) (0 0)
1198 14:00:07.554508 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1199 14:00:07.561265 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 14:00:07.565113 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 14:00:07.568087 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 14:00:07.574780 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 14:00:07.578202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 14:00:07.581724 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 14:00:07.588287 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1206 14:00:07.591616 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1207 14:00:07.595737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 14:00:07.598682 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 14:00:07.605108 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 14:00:07.608581 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 14:00:07.612131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 14:00:07.618969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 14:00:07.622199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 14:00:07.625388 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 14:00:07.632084 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 14:00:07.635649 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 14:00:07.638531 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 14:00:07.645523 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 14:00:07.648753 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 14:00:07.652089 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 14:00:07.658630 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 14:00:07.659028 Total UI for P1: 0, mck2ui 16
1223 14:00:07.662122 best dqsien dly found for B0: ( 0, 14, 4)
1224 14:00:07.665549 Total UI for P1: 0, mck2ui 16
1225 14:00:07.668662 best dqsien dly found for B1: ( 0, 14, 6)
1226 14:00:07.671958 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1227 14:00:07.675797 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1228 14:00:07.679108
1229 14:00:07.682254 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1230 14:00:07.685322 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 14:00:07.689218 [Gating] SW calibration Done
1232 14:00:07.689605 ==
1233 14:00:07.692376 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 14:00:07.695716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 14:00:07.696112 ==
1236 14:00:07.696432 RX Vref Scan: 0
1237 14:00:07.696722
1238 14:00:07.698878 RX Vref 0 -> 0, step: 1
1239 14:00:07.699330
1240 14:00:07.702444 RX Delay -130 -> 252, step: 16
1241 14:00:07.705694 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1242 14:00:07.709151 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1243 14:00:07.715641 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1244 14:00:07.719032 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1245 14:00:07.722229 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1246 14:00:07.725903 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1247 14:00:07.729018 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1248 14:00:07.732602 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1249 14:00:07.739354 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1250 14:00:07.742038 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1251 14:00:07.746066 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1252 14:00:07.748924 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1253 14:00:07.752327 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1254 14:00:07.758839 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1255 14:00:07.762951 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1256 14:00:07.765629 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1257 14:00:07.766016 ==
1258 14:00:07.769340 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 14:00:07.772460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 14:00:07.772850 ==
1261 14:00:07.776199 DQS Delay:
1262 14:00:07.776585 DQS0 = 0, DQS1 = 0
1263 14:00:07.779240 DQM Delay:
1264 14:00:07.779625 DQM0 = 87, DQM1 = 78
1265 14:00:07.779931 DQ Delay:
1266 14:00:07.783062 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1267 14:00:07.785856 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
1268 14:00:07.789164 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1269 14:00:07.792948 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1270 14:00:07.793347
1271 14:00:07.793652
1272 14:00:07.796164 ==
1273 14:00:07.796592 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 14:00:07.802937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 14:00:07.803405 ==
1276 14:00:07.803807
1277 14:00:07.804321
1278 14:00:07.805914 TX Vref Scan disable
1279 14:00:07.806490 == TX Byte 0 ==
1280 14:00:07.809390 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1281 14:00:07.816253 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1282 14:00:07.816761 == TX Byte 1 ==
1283 14:00:07.819345 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1284 14:00:07.826192 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1285 14:00:07.826601 ==
1286 14:00:07.829595 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 14:00:07.832682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 14:00:07.833151 ==
1289 14:00:07.845761 TX Vref=22, minBit 3, minWin=27, winSum=444
1290 14:00:07.849126 TX Vref=24, minBit 9, minWin=27, winSum=452
1291 14:00:07.852936 TX Vref=26, minBit 3, minWin=27, winSum=447
1292 14:00:07.856005 TX Vref=28, minBit 0, minWin=28, winSum=455
1293 14:00:07.859076 TX Vref=30, minBit 0, minWin=28, winSum=455
1294 14:00:07.862700 TX Vref=32, minBit 0, minWin=28, winSum=452
1295 14:00:07.869199 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1296 14:00:07.869583
1297 14:00:07.872758 Final TX Range 1 Vref 28
1298 14:00:07.873266
1299 14:00:07.873741 ==
1300 14:00:07.876149 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 14:00:07.879295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 14:00:07.879820 ==
1303 14:00:07.880301
1304 14:00:07.880783
1305 14:00:07.882861 TX Vref Scan disable
1306 14:00:07.885801 == TX Byte 0 ==
1307 14:00:07.889550 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1308 14:00:07.892746 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1309 14:00:07.895823 == TX Byte 1 ==
1310 14:00:07.899331 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1311 14:00:07.902663 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1312 14:00:07.903147
1313 14:00:07.906550 [DATLAT]
1314 14:00:07.906930 Freq=800, CH0 RK1
1315 14:00:07.907237
1316 14:00:07.909860 DATLAT Default: 0xa
1317 14:00:07.910241 0, 0xFFFF, sum = 0
1318 14:00:07.912883 1, 0xFFFF, sum = 0
1319 14:00:07.913361 2, 0xFFFF, sum = 0
1320 14:00:07.916669 3, 0xFFFF, sum = 0
1321 14:00:07.917069 4, 0xFFFF, sum = 0
1322 14:00:07.919777 5, 0xFFFF, sum = 0
1323 14:00:07.920167 6, 0xFFFF, sum = 0
1324 14:00:07.923367 7, 0xFFFF, sum = 0
1325 14:00:07.923878 8, 0xFFFF, sum = 0
1326 14:00:07.926605 9, 0x0, sum = 1
1327 14:00:07.927082 10, 0x0, sum = 2
1328 14:00:07.930344 11, 0x0, sum = 3
1329 14:00:07.930779 12, 0x0, sum = 4
1330 14:00:07.932992 best_step = 10
1331 14:00:07.933371
1332 14:00:07.933667 ==
1333 14:00:07.936430 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 14:00:07.939394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 14:00:07.939870 ==
1336 14:00:07.940316 RX Vref Scan: 0
1337 14:00:07.943086
1338 14:00:07.943486 RX Vref 0 -> 0, step: 1
1339 14:00:07.943803
1340 14:00:07.946613 RX Delay -95 -> 252, step: 8
1341 14:00:07.949678 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1342 14:00:07.956638 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1343 14:00:07.959985 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1344 14:00:07.963323 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1345 14:00:07.967274 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1346 14:00:07.969755 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1347 14:00:07.976488 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1348 14:00:07.979997 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1349 14:00:07.983160 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1350 14:00:07.987781 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1351 14:00:07.990579 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1352 14:00:07.993451 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1353 14:00:08.000189 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1354 14:00:08.003418 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1355 14:00:08.007515 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1356 14:00:08.010240 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1357 14:00:08.010661 ==
1358 14:00:08.013635 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 14:00:08.020352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 14:00:08.020866 ==
1361 14:00:08.021306 DQS Delay:
1362 14:00:08.023735 DQS0 = 0, DQS1 = 0
1363 14:00:08.024109 DQM Delay:
1364 14:00:08.024437 DQM0 = 87, DQM1 = 77
1365 14:00:08.026892 DQ Delay:
1366 14:00:08.030650 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1367 14:00:08.033524 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1368 14:00:08.036848 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1369 14:00:08.040405 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1370 14:00:08.040787
1371 14:00:08.041086
1372 14:00:08.047120 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1373 14:00:08.050470 CH0 RK1: MR19=606, MR18=2E16
1374 14:00:08.057355 CH0_RK1: MR19=0x606, MR18=0x2E16, DQSOSC=398, MR23=63, INC=93, DEC=62
1375 14:00:08.061039 [RxdqsGatingPostProcess] freq 800
1376 14:00:08.064249 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 14:00:08.067345 Pre-setting of DQS Precalculation
1378 14:00:08.073989 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 14:00:08.074519 ==
1380 14:00:08.077725 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 14:00:08.080537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 14:00:08.081075 ==
1383 14:00:08.087379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 14:00:08.090977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 14:00:08.100522 [CA 0] Center 36 (6~67) winsize 62
1386 14:00:08.103908 [CA 1] Center 36 (6~66) winsize 61
1387 14:00:08.107077 [CA 2] Center 34 (4~65) winsize 62
1388 14:00:08.110890 [CA 3] Center 33 (3~64) winsize 62
1389 14:00:08.114325 [CA 4] Center 34 (4~65) winsize 62
1390 14:00:08.117361 [CA 5] Center 33 (3~64) winsize 62
1391 14:00:08.117742
1392 14:00:08.120797 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1393 14:00:08.121179
1394 14:00:08.124617 [CATrainingPosCal] consider 1 rank data
1395 14:00:08.127742 u2DelayCellTimex100 = 270/100 ps
1396 14:00:08.130850 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1397 14:00:08.134699 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1398 14:00:08.140859 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1399 14:00:08.144197 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1400 14:00:08.147413 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1401 14:00:08.150608 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1402 14:00:08.151054
1403 14:00:08.154250 CA PerBit enable=1, Macro0, CA PI delay=33
1404 14:00:08.154765
1405 14:00:08.157985 [CBTSetCACLKResult] CA Dly = 33
1406 14:00:08.158444 CS Dly: 5 (0~36)
1407 14:00:08.158873 ==
1408 14:00:08.160735 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 14:00:08.167530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 14:00:08.168056 ==
1411 14:00:08.171468 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 14:00:08.177611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 14:00:08.186640 [CA 0] Center 36 (6~67) winsize 62
1414 14:00:08.189914 [CA 1] Center 36 (6~66) winsize 61
1415 14:00:08.193666 [CA 2] Center 34 (4~65) winsize 62
1416 14:00:08.196974 [CA 3] Center 33 (3~64) winsize 62
1417 14:00:08.200887 [CA 4] Center 34 (3~65) winsize 63
1418 14:00:08.204358 [CA 5] Center 33 (3~64) winsize 62
1419 14:00:08.204770
1420 14:00:08.208092 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1421 14:00:08.208496
1422 14:00:08.211733 [CATrainingPosCal] consider 2 rank data
1423 14:00:08.215458 u2DelayCellTimex100 = 270/100 ps
1424 14:00:08.219267 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1425 14:00:08.223097 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1426 14:00:08.226919 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1427 14:00:08.230305 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1428 14:00:08.234762 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1429 14:00:08.237987 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1430 14:00:08.238423
1431 14:00:08.240559 CA PerBit enable=1, Macro0, CA PI delay=33
1432 14:00:08.241068
1433 14:00:08.243945 [CBTSetCACLKResult] CA Dly = 33
1434 14:00:08.244329 CS Dly: 5 (0~37)
1435 14:00:08.244714
1436 14:00:08.247494 ----->DramcWriteLeveling(PI) begin...
1437 14:00:08.247876 ==
1438 14:00:08.251069 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 14:00:08.254040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 14:00:08.257597 ==
1441 14:00:08.257973 Write leveling (Byte 0): 25 => 25
1442 14:00:08.261030 Write leveling (Byte 1): 30 => 30
1443 14:00:08.264072 DramcWriteLeveling(PI) end<-----
1444 14:00:08.264469
1445 14:00:08.264764 ==
1446 14:00:08.267688 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 14:00:08.273948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 14:00:08.274368 ==
1449 14:00:08.274721 [Gating] SW mode calibration
1450 14:00:08.284627 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 14:00:08.287821 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 14:00:08.290905 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 14:00:08.297309 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 14:00:08.300700 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 14:00:08.304545 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 14:00:08.310775 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 14:00:08.314469 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 14:00:08.317420 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 14:00:08.324263 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 14:00:08.327438 0 7 0 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1461 14:00:08.330886 0 7 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1462 14:00:08.337485 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 14:00:08.341035 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1464 14:00:08.344639 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1465 14:00:08.351958 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 14:00:08.354730 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 14:00:08.357652 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1468 14:00:08.361159 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1469 14:00:08.367583 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 14:00:08.371252 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 14:00:08.374749 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 14:00:08.380934 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 14:00:08.384792 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 14:00:08.387987 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1475 14:00:08.394375 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 14:00:08.398161 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 14:00:08.401011 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 14:00:08.407995 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1479 14:00:08.411354 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 14:00:08.414509 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1481 14:00:08.421234 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 14:00:08.424759 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 14:00:08.428294 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1484 14:00:08.431861 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1485 14:00:08.438378 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 14:00:08.441826 0 10 8 | B1->B0 | 2c2c 2e2e | 0 0 | (1 1) (0 0)
1487 14:00:08.444644 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1488 14:00:08.451799 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 14:00:08.455001 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 14:00:08.458048 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 14:00:08.465418 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1492 14:00:08.468798 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 14:00:08.471489 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1494 14:00:08.478808 0 11 8 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
1495 14:00:08.481778 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 14:00:08.485415 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 14:00:08.492294 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 14:00:08.495078 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 14:00:08.498639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 14:00:08.501786 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 14:00:08.508604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 14:00:08.512105 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1503 14:00:08.515294 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 14:00:08.521859 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 14:00:08.525059 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 14:00:08.528570 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 14:00:08.535135 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 14:00:08.538809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 14:00:08.542100 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 14:00:08.548639 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 14:00:08.552257 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 14:00:08.555903 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 14:00:08.562577 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 14:00:08.565698 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 14:00:08.569544 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 14:00:08.572921 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 14:00:08.579129 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 14:00:08.582530 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 14:00:08.586034 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 14:00:08.589285 Total UI for P1: 0, mck2ui 16
1521 14:00:08.592516 best dqsien dly found for B0: ( 0, 14, 8)
1522 14:00:08.596343 Total UI for P1: 0, mck2ui 16
1523 14:00:08.599204 best dqsien dly found for B1: ( 0, 14, 8)
1524 14:00:08.602609 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1525 14:00:08.605825 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1526 14:00:08.606379
1527 14:00:08.613334 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1528 14:00:08.616387 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1529 14:00:08.616844 [Gating] SW calibration Done
1530 14:00:08.617206 ==
1531 14:00:08.618997 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 14:00:08.626081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 14:00:08.626674 ==
1534 14:00:08.627042 RX Vref Scan: 0
1535 14:00:08.627382
1536 14:00:08.629244 RX Vref 0 -> 0, step: 1
1537 14:00:08.629701
1538 14:00:08.632687 RX Delay -130 -> 252, step: 16
1539 14:00:08.636151 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1540 14:00:08.639653 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1541 14:00:08.642888 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1542 14:00:08.649492 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1543 14:00:08.652567 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1544 14:00:08.656076 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1545 14:00:08.659408 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1546 14:00:08.662860 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1547 14:00:08.669357 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1548 14:00:08.673142 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1549 14:00:08.676373 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1550 14:00:08.679170 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1551 14:00:08.683096 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1552 14:00:08.689611 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1553 14:00:08.692898 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1554 14:00:08.696158 iDelay=206, Bit 15, Center 77 (-34 ~ 189) 224
1555 14:00:08.696623 ==
1556 14:00:08.699856 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 14:00:08.702422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 14:00:08.702892 ==
1559 14:00:08.706495 DQS Delay:
1560 14:00:08.707043 DQS0 = 0, DQS1 = 0
1561 14:00:08.709526 DQM Delay:
1562 14:00:08.709989 DQM0 = 81, DQM1 = 74
1563 14:00:08.710354 DQ Delay:
1564 14:00:08.713116 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1565 14:00:08.716235 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =77
1566 14:00:08.719769 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1567 14:00:08.723160 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1568 14:00:08.723713
1569 14:00:08.724080
1570 14:00:08.724419 ==
1571 14:00:08.726018 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 14:00:08.733329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 14:00:08.733888 ==
1574 14:00:08.734249
1575 14:00:08.734657
1576 14:00:08.734984 TX Vref Scan disable
1577 14:00:08.736545 == TX Byte 0 ==
1578 14:00:08.739900 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 14:00:08.742824 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 14:00:08.746335 == TX Byte 1 ==
1581 14:00:08.749642 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1582 14:00:08.752857 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1583 14:00:08.756620 ==
1584 14:00:08.759571 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 14:00:08.763054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 14:00:08.763570 ==
1587 14:00:08.776159 TX Vref=22, minBit 3, minWin=26, winSum=437
1588 14:00:08.779621 TX Vref=24, minBit 1, minWin=27, winSum=443
1589 14:00:08.782880 TX Vref=26, minBit 0, minWin=27, winSum=443
1590 14:00:08.786966 TX Vref=28, minBit 1, minWin=27, winSum=447
1591 14:00:08.790611 TX Vref=30, minBit 5, minWin=27, winSum=451
1592 14:00:08.794095 TX Vref=32, minBit 0, minWin=27, winSum=449
1593 14:00:08.800289 [TxChooseVref] Worse bit 5, Min win 27, Win sum 451, Final Vref 30
1594 14:00:08.800829
1595 14:00:08.803445 Final TX Range 1 Vref 30
1596 14:00:08.803903
1597 14:00:08.804262 ==
1598 14:00:08.806715 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 14:00:08.809891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 14:00:08.810348 ==
1601 14:00:08.810770
1602 14:00:08.811113
1603 14:00:08.813257 TX Vref Scan disable
1604 14:00:08.816868 == TX Byte 0 ==
1605 14:00:08.820716 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1606 14:00:08.824227 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1607 14:00:08.826707 == TX Byte 1 ==
1608 14:00:08.830314 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1609 14:00:08.833726 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1610 14:00:08.834145
1611 14:00:08.834517 [DATLAT]
1612 14:00:08.836952 Freq=800, CH1 RK0
1613 14:00:08.837466
1614 14:00:08.840516 DATLAT Default: 0xa
1615 14:00:08.841032 0, 0xFFFF, sum = 0
1616 14:00:08.843736 1, 0xFFFF, sum = 0
1617 14:00:08.844157 2, 0xFFFF, sum = 0
1618 14:00:08.847084 3, 0xFFFF, sum = 0
1619 14:00:08.847599 4, 0xFFFF, sum = 0
1620 14:00:08.850449 5, 0xFFFF, sum = 0
1621 14:00:08.850872 6, 0xFFFF, sum = 0
1622 14:00:08.854514 7, 0xFFFF, sum = 0
1623 14:00:08.854996 8, 0xFFFF, sum = 0
1624 14:00:08.857161 9, 0x0, sum = 1
1625 14:00:08.857578 10, 0x0, sum = 2
1626 14:00:08.860552 11, 0x0, sum = 3
1627 14:00:08.861067 12, 0x0, sum = 4
1628 14:00:08.861401 best_step = 10
1629 14:00:08.861704
1630 14:00:08.863944 ==
1631 14:00:08.864461 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 14:00:08.870741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 14:00:08.871244 ==
1634 14:00:08.871573 RX Vref Scan: 1
1635 14:00:08.871877
1636 14:00:08.874158 Set Vref Range= 32 -> 127
1637 14:00:08.874615
1638 14:00:08.877449 RX Vref 32 -> 127, step: 1
1639 14:00:08.877857
1640 14:00:08.880847 RX Delay -111 -> 252, step: 8
1641 14:00:08.881368
1642 14:00:08.884092 Set Vref, RX VrefLevel [Byte0]: 32
1643 14:00:08.887261 [Byte1]: 32
1644 14:00:08.887672
1645 14:00:08.890365 Set Vref, RX VrefLevel [Byte0]: 33
1646 14:00:08.893993 [Byte1]: 33
1647 14:00:08.894438
1648 14:00:08.898010 Set Vref, RX VrefLevel [Byte0]: 34
1649 14:00:08.900867 [Byte1]: 34
1650 14:00:08.903975
1651 14:00:08.904387 Set Vref, RX VrefLevel [Byte0]: 35
1652 14:00:08.907334 [Byte1]: 35
1653 14:00:08.911713
1654 14:00:08.912150 Set Vref, RX VrefLevel [Byte0]: 36
1655 14:00:08.915265 [Byte1]: 36
1656 14:00:08.919385
1657 14:00:08.919895 Set Vref, RX VrefLevel [Byte0]: 37
1658 14:00:08.922703 [Byte1]: 37
1659 14:00:08.927098
1660 14:00:08.927510 Set Vref, RX VrefLevel [Byte0]: 38
1661 14:00:08.930549 [Byte1]: 38
1662 14:00:08.934837
1663 14:00:08.935348 Set Vref, RX VrefLevel [Byte0]: 39
1664 14:00:08.937768 [Byte1]: 39
1665 14:00:08.942498
1666 14:00:08.942875 Set Vref, RX VrefLevel [Byte0]: 40
1667 14:00:08.945783 [Byte1]: 40
1668 14:00:08.949564
1669 14:00:08.949982 Set Vref, RX VrefLevel [Byte0]: 41
1670 14:00:08.953523 [Byte1]: 41
1671 14:00:08.958099
1672 14:00:08.958651 Set Vref, RX VrefLevel [Byte0]: 42
1673 14:00:08.961402 [Byte1]: 42
1674 14:00:08.965195
1675 14:00:08.965744 Set Vref, RX VrefLevel [Byte0]: 43
1676 14:00:08.968578 [Byte1]: 43
1677 14:00:08.973519
1678 14:00:08.974069 Set Vref, RX VrefLevel [Byte0]: 44
1679 14:00:08.976019 [Byte1]: 44
1680 14:00:08.980536
1681 14:00:08.981086 Set Vref, RX VrefLevel [Byte0]: 45
1682 14:00:08.983747 [Byte1]: 45
1683 14:00:08.988606
1684 14:00:08.989157 Set Vref, RX VrefLevel [Byte0]: 46
1685 14:00:08.991382 [Byte1]: 46
1686 14:00:08.995939
1687 14:00:08.996512 Set Vref, RX VrefLevel [Byte0]: 47
1688 14:00:08.999094 [Byte1]: 47
1689 14:00:09.003385
1690 14:00:09.003954 Set Vref, RX VrefLevel [Byte0]: 48
1691 14:00:09.006861 [Byte1]: 48
1692 14:00:09.010979
1693 14:00:09.011429 Set Vref, RX VrefLevel [Byte0]: 49
1694 14:00:09.014880 [Byte1]: 49
1695 14:00:09.018603
1696 14:00:09.019063 Set Vref, RX VrefLevel [Byte0]: 50
1697 14:00:09.022368 [Byte1]: 50
1698 14:00:09.026163
1699 14:00:09.026769 Set Vref, RX VrefLevel [Byte0]: 51
1700 14:00:09.030198 [Byte1]: 51
1701 14:00:09.034034
1702 14:00:09.034621 Set Vref, RX VrefLevel [Byte0]: 52
1703 14:00:09.037551 [Byte1]: 52
1704 14:00:09.041671
1705 14:00:09.042220 Set Vref, RX VrefLevel [Byte0]: 53
1706 14:00:09.045260 [Byte1]: 53
1707 14:00:09.049649
1708 14:00:09.050113 Set Vref, RX VrefLevel [Byte0]: 54
1709 14:00:09.052902 [Byte1]: 54
1710 14:00:09.056849
1711 14:00:09.057404 Set Vref, RX VrefLevel [Byte0]: 55
1712 14:00:09.060283 [Byte1]: 55
1713 14:00:09.064701
1714 14:00:09.065253 Set Vref, RX VrefLevel [Byte0]: 56
1715 14:00:09.068432 [Byte1]: 56
1716 14:00:09.072337
1717 14:00:09.072890 Set Vref, RX VrefLevel [Byte0]: 57
1718 14:00:09.075657 [Byte1]: 57
1719 14:00:09.080012
1720 14:00:09.080563 Set Vref, RX VrefLevel [Byte0]: 58
1721 14:00:09.083123 [Byte1]: 58
1722 14:00:09.087461
1723 14:00:09.088012 Set Vref, RX VrefLevel [Byte0]: 59
1724 14:00:09.091306 [Byte1]: 59
1725 14:00:09.095199
1726 14:00:09.095754 Set Vref, RX VrefLevel [Byte0]: 60
1727 14:00:09.098692 [Byte1]: 60
1728 14:00:09.102742
1729 14:00:09.103200 Set Vref, RX VrefLevel [Byte0]: 61
1730 14:00:09.106019 [Byte1]: 61
1731 14:00:09.110447
1732 14:00:09.111065 Set Vref, RX VrefLevel [Byte0]: 62
1733 14:00:09.113833 [Byte1]: 62
1734 14:00:09.118278
1735 14:00:09.118868 Set Vref, RX VrefLevel [Byte0]: 63
1736 14:00:09.121831 [Byte1]: 63
1737 14:00:09.126443
1738 14:00:09.127004 Set Vref, RX VrefLevel [Byte0]: 64
1739 14:00:09.129141 [Byte1]: 64
1740 14:00:09.133825
1741 14:00:09.134376 Set Vref, RX VrefLevel [Byte0]: 65
1742 14:00:09.137007 [Byte1]: 65
1743 14:00:09.141722
1744 14:00:09.142274 Set Vref, RX VrefLevel [Byte0]: 66
1745 14:00:09.144710 [Byte1]: 66
1746 14:00:09.148729
1747 14:00:09.149297 Set Vref, RX VrefLevel [Byte0]: 67
1748 14:00:09.152471 [Byte1]: 67
1749 14:00:09.156594
1750 14:00:09.157150 Set Vref, RX VrefLevel [Byte0]: 68
1751 14:00:09.159987 [Byte1]: 68
1752 14:00:09.164272
1753 14:00:09.164821 Set Vref, RX VrefLevel [Byte0]: 69
1754 14:00:09.167769 [Byte1]: 69
1755 14:00:09.171881
1756 14:00:09.172430 Set Vref, RX VrefLevel [Byte0]: 70
1757 14:00:09.175318 [Byte1]: 70
1758 14:00:09.179684
1759 14:00:09.180243 Set Vref, RX VrefLevel [Byte0]: 71
1760 14:00:09.182358 [Byte1]: 71
1761 14:00:09.187349
1762 14:00:09.187811 Set Vref, RX VrefLevel [Byte0]: 72
1763 14:00:09.190164 [Byte1]: 72
1764 14:00:09.194742
1765 14:00:09.195208 Set Vref, RX VrefLevel [Byte0]: 73
1766 14:00:09.198097 [Byte1]: 73
1767 14:00:09.202510
1768 14:00:09.203062 Set Vref, RX VrefLevel [Byte0]: 74
1769 14:00:09.205440 [Byte1]: 74
1770 14:00:09.210227
1771 14:00:09.210865 Set Vref, RX VrefLevel [Byte0]: 75
1772 14:00:09.213137 [Byte1]: 75
1773 14:00:09.217674
1774 14:00:09.218136 Set Vref, RX VrefLevel [Byte0]: 76
1775 14:00:09.220720 [Byte1]: 76
1776 14:00:09.225359
1777 14:00:09.225913 Set Vref, RX VrefLevel [Byte0]: 77
1778 14:00:09.228374 [Byte1]: 77
1779 14:00:09.232729
1780 14:00:09.233278 Final RX Vref Byte 0 = 61 to rank0
1781 14:00:09.236208 Final RX Vref Byte 1 = 58 to rank0
1782 14:00:09.239717 Final RX Vref Byte 0 = 61 to rank1
1783 14:00:09.243334 Final RX Vref Byte 1 = 58 to rank1==
1784 14:00:09.246106 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 14:00:09.249156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 14:00:09.252967 ==
1787 14:00:09.253433 DQS Delay:
1788 14:00:09.253796 DQS0 = 0, DQS1 = 0
1789 14:00:09.256950 DQM Delay:
1790 14:00:09.257503 DQM0 = 84, DQM1 = 73
1791 14:00:09.259680 DQ Delay:
1792 14:00:09.262930 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1793 14:00:09.263394 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1794 14:00:09.266280 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1795 14:00:09.269839 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1796 14:00:09.270390
1797 14:00:09.272918
1798 14:00:09.279530 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1799 14:00:09.283034 CH1 RK0: MR19=605, MR18=26FB
1800 14:00:09.289483 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1801 14:00:09.290045
1802 14:00:09.293502 ----->DramcWriteLeveling(PI) begin...
1803 14:00:09.294071 ==
1804 14:00:09.296840 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 14:00:09.299871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 14:00:09.300336 ==
1807 14:00:09.303693 Write leveling (Byte 0): 27 => 27
1808 14:00:09.306978 Write leveling (Byte 1): 28 => 28
1809 14:00:09.309802 DramcWriteLeveling(PI) end<-----
1810 14:00:09.310257
1811 14:00:09.310669 ==
1812 14:00:09.313593 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 14:00:09.316616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 14:00:09.317086 ==
1815 14:00:09.320207 [Gating] SW mode calibration
1816 14:00:09.326746 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 14:00:09.333807 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 14:00:09.336607 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1819 14:00:09.340466 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1820 14:00:09.343242 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1821 14:00:09.349876 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 14:00:09.353672 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 14:00:09.356934 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 14:00:09.363568 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 14:00:09.367003 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 14:00:09.370394 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 14:00:09.377247 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 14:00:09.380637 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 14:00:09.384042 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1830 14:00:09.390277 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 14:00:09.393897 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1832 14:00:09.397297 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 14:00:09.400146 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 14:00:09.407031 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1835 14:00:09.410546 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1836 14:00:09.413863 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 14:00:09.420840 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 14:00:09.423602 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 14:00:09.427280 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 14:00:09.434050 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 14:00:09.437205 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 14:00:09.440563 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 14:00:09.447406 0 9 4 | B1->B0 | 2424 2828 | 0 0 | (0 0) (1 1)
1844 14:00:09.450637 0 9 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
1845 14:00:09.454174 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1846 14:00:09.460443 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 14:00:09.463668 0 9 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1848 14:00:09.467038 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1849 14:00:09.473837 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1850 14:00:09.477046 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 14:00:09.480332 0 10 4 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
1852 14:00:09.487271 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1853 14:00:09.490736 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 14:00:09.493532 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 14:00:09.496809 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 14:00:09.503649 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 14:00:09.506736 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 14:00:09.510477 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 14:00:09.517209 0 11 4 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
1860 14:00:09.520868 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1861 14:00:09.524032 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 14:00:09.530565 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 14:00:09.533763 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 14:00:09.537822 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 14:00:09.544112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 14:00:09.547779 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 14:00:09.550998 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1868 14:00:09.554196 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 14:00:09.561392 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 14:00:09.564330 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 14:00:09.568147 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 14:00:09.574359 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 14:00:09.577959 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 14:00:09.581450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 14:00:09.587617 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 14:00:09.591374 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 14:00:09.594821 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 14:00:09.601232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 14:00:09.604915 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 14:00:09.607938 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 14:00:09.611331 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 14:00:09.618170 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 14:00:09.621656 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1884 14:00:09.625189 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 14:00:09.627994 Total UI for P1: 0, mck2ui 16
1886 14:00:09.631707 best dqsien dly found for B0: ( 0, 14, 4)
1887 14:00:09.635411 Total UI for P1: 0, mck2ui 16
1888 14:00:09.638774 best dqsien dly found for B1: ( 0, 14, 4)
1889 14:00:09.641650 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1890 14:00:09.644742 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1891 14:00:09.645216
1892 14:00:09.651549 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1893 14:00:09.654887 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1894 14:00:09.655437 [Gating] SW calibration Done
1895 14:00:09.655912 ==
1896 14:00:09.658258 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 14:00:09.665339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 14:00:09.665941 ==
1899 14:00:09.666466 RX Vref Scan: 0
1900 14:00:09.666920
1901 14:00:09.668153 RX Vref 0 -> 0, step: 1
1902 14:00:09.668623
1903 14:00:09.671850 RX Delay -130 -> 252, step: 16
1904 14:00:09.675275 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1905 14:00:09.678642 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1906 14:00:09.682182 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1907 14:00:09.688579 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1908 14:00:09.692079 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1909 14:00:09.695095 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1910 14:00:09.698598 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1911 14:00:09.702283 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1912 14:00:09.705180 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1913 14:00:09.711944 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1914 14:00:09.715094 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1915 14:00:09.718561 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1916 14:00:09.722016 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1917 14:00:09.725427 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1918 14:00:09.731879 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1919 14:00:09.735137 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1920 14:00:09.735615 ==
1921 14:00:09.738907 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 14:00:09.742031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 14:00:09.742501 ==
1924 14:00:09.745398 DQS Delay:
1925 14:00:09.745835 DQS0 = 0, DQS1 = 0
1926 14:00:09.746202 DQM Delay:
1927 14:00:09.749275 DQM0 = 79, DQM1 = 77
1928 14:00:09.749869 DQ Delay:
1929 14:00:09.752021 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1930 14:00:09.755660 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1931 14:00:09.758543 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1932 14:00:09.762394 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1933 14:00:09.762854
1934 14:00:09.763190
1935 14:00:09.763522 ==
1936 14:00:09.765433 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 14:00:09.771989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 14:00:09.772071 ==
1939 14:00:09.772135
1940 14:00:09.772194
1941 14:00:09.772254 TX Vref Scan disable
1942 14:00:09.775056 == TX Byte 0 ==
1943 14:00:09.778519 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1944 14:00:09.781952 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1945 14:00:09.784848 == TX Byte 1 ==
1946 14:00:09.788742 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1947 14:00:09.792064 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1948 14:00:09.795364 ==
1949 14:00:09.798333 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 14:00:09.801748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 14:00:09.801830 ==
1952 14:00:09.813859 TX Vref=22, minBit 1, minWin=27, winSum=443
1953 14:00:09.817742 TX Vref=24, minBit 5, minWin=27, winSum=444
1954 14:00:09.820568 TX Vref=26, minBit 15, minWin=27, winSum=449
1955 14:00:09.823978 TX Vref=28, minBit 15, minWin=27, winSum=448
1956 14:00:09.827245 TX Vref=30, minBit 0, minWin=28, winSum=452
1957 14:00:09.834108 TX Vref=32, minBit 0, minWin=28, winSum=453
1958 14:00:09.837557 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1959 14:00:09.837638
1960 14:00:09.840538 Final TX Range 1 Vref 32
1961 14:00:09.840619
1962 14:00:09.840682 ==
1963 14:00:09.844018 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 14:00:09.847304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 14:00:09.847385 ==
1966 14:00:09.850724
1967 14:00:09.850804
1968 14:00:09.850866 TX Vref Scan disable
1969 14:00:09.853757 == TX Byte 0 ==
1970 14:00:09.857445 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1971 14:00:09.860472 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1972 14:00:09.864555 == TX Byte 1 ==
1973 14:00:09.867409 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1974 14:00:09.871316 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1975 14:00:09.871397
1976 14:00:09.874372 [DATLAT]
1977 14:00:09.874494 Freq=800, CH1 RK1
1978 14:00:09.874558
1979 14:00:09.877849 DATLAT Default: 0xa
1980 14:00:09.877928 0, 0xFFFF, sum = 0
1981 14:00:09.880951 1, 0xFFFF, sum = 0
1982 14:00:09.881031 2, 0xFFFF, sum = 0
1983 14:00:09.884424 3, 0xFFFF, sum = 0
1984 14:00:09.884505 4, 0xFFFF, sum = 0
1985 14:00:09.887558 5, 0xFFFF, sum = 0
1986 14:00:09.887639 6, 0xFFFF, sum = 0
1987 14:00:09.891240 7, 0xFFFF, sum = 0
1988 14:00:09.891321 8, 0xFFFF, sum = 0
1989 14:00:09.894736 9, 0x0, sum = 1
1990 14:00:09.894816 10, 0x0, sum = 2
1991 14:00:09.897862 11, 0x0, sum = 3
1992 14:00:09.897943 12, 0x0, sum = 4
1993 14:00:09.901384 best_step = 10
1994 14:00:09.901463
1995 14:00:09.901526 ==
1996 14:00:09.904114 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 14:00:09.907763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 14:00:09.907844 ==
1999 14:00:09.910969 RX Vref Scan: 0
2000 14:00:09.911049
2001 14:00:09.911112 RX Vref 0 -> 0, step: 1
2002 14:00:09.911171
2003 14:00:09.914339 RX Delay -95 -> 252, step: 8
2004 14:00:09.921468 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2005 14:00:09.924193 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2006 14:00:09.927588 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2007 14:00:09.931234 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2008 14:00:09.934658 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2009 14:00:09.937932 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2010 14:00:09.944769 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2011 14:00:09.947708 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2012 14:00:09.951064 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2013 14:00:09.954710 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2014 14:00:09.958247 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2015 14:00:09.965057 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2016 14:00:09.967958 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2017 14:00:09.971924 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2018 14:00:09.974882 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2019 14:00:09.978012 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2020 14:00:09.981546 ==
2021 14:00:09.981629 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 14:00:09.988592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 14:00:09.988675 ==
2024 14:00:09.988758 DQS Delay:
2025 14:00:09.991830 DQS0 = 0, DQS1 = 0
2026 14:00:09.991912 DQM Delay:
2027 14:00:09.991996 DQM0 = 80, DQM1 = 75
2028 14:00:09.995002 DQ Delay:
2029 14:00:09.998373 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2030 14:00:10.001808 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
2031 14:00:10.005071 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2032 14:00:10.008732 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2033 14:00:10.008832
2034 14:00:10.008896
2035 14:00:10.015103 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2036 14:00:10.018515 CH1 RK1: MR19=606, MR18=222D
2037 14:00:10.025002 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2038 14:00:10.028790 [RxdqsGatingPostProcess] freq 800
2039 14:00:10.031777 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2040 14:00:10.035588 Pre-setting of DQS Precalculation
2041 14:00:10.042302 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2042 14:00:10.048519 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2043 14:00:10.055314 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2044 14:00:10.055395
2045 14:00:10.055457
2046 14:00:10.059107 [Calibration Summary] 1600 Mbps
2047 14:00:10.059187 CH 0, Rank 0
2048 14:00:10.062582 SW Impedance : PASS
2049 14:00:10.065591 DUTY Scan : NO K
2050 14:00:10.065671 ZQ Calibration : PASS
2051 14:00:10.069011 Jitter Meter : NO K
2052 14:00:10.069092 CBT Training : PASS
2053 14:00:10.072261 Write leveling : PASS
2054 14:00:10.075709 RX DQS gating : PASS
2055 14:00:10.075789 RX DQ/DQS(RDDQC) : PASS
2056 14:00:10.079044 TX DQ/DQS : PASS
2057 14:00:10.082200 RX DATLAT : PASS
2058 14:00:10.082280 RX DQ/DQS(Engine): PASS
2059 14:00:10.085780 TX OE : NO K
2060 14:00:10.085860 All Pass.
2061 14:00:10.085922
2062 14:00:10.089133 CH 0, Rank 1
2063 14:00:10.089213 SW Impedance : PASS
2064 14:00:10.092068 DUTY Scan : NO K
2065 14:00:10.095655 ZQ Calibration : PASS
2066 14:00:10.095734 Jitter Meter : NO K
2067 14:00:10.098692 CBT Training : PASS
2068 14:00:10.102179 Write leveling : PASS
2069 14:00:10.102258 RX DQS gating : PASS
2070 14:00:10.105751 RX DQ/DQS(RDDQC) : PASS
2071 14:00:10.105830 TX DQ/DQS : PASS
2072 14:00:10.109085 RX DATLAT : PASS
2073 14:00:10.112332 RX DQ/DQS(Engine): PASS
2074 14:00:10.112412 TX OE : NO K
2075 14:00:10.115568 All Pass.
2076 14:00:10.115648
2077 14:00:10.115709 CH 1, Rank 0
2078 14:00:10.119059 SW Impedance : PASS
2079 14:00:10.119138 DUTY Scan : NO K
2080 14:00:10.122309 ZQ Calibration : PASS
2081 14:00:10.125682 Jitter Meter : NO K
2082 14:00:10.125761 CBT Training : PASS
2083 14:00:10.129830 Write leveling : PASS
2084 14:00:10.132664 RX DQS gating : PASS
2085 14:00:10.132744 RX DQ/DQS(RDDQC) : PASS
2086 14:00:10.136426 TX DQ/DQS : PASS
2087 14:00:10.136507 RX DATLAT : PASS
2088 14:00:10.139324 RX DQ/DQS(Engine): PASS
2089 14:00:10.142501 TX OE : NO K
2090 14:00:10.142581 All Pass.
2091 14:00:10.142644
2092 14:00:10.142703 CH 1, Rank 1
2093 14:00:10.146031 SW Impedance : PASS
2094 14:00:10.149785 DUTY Scan : NO K
2095 14:00:10.149867 ZQ Calibration : PASS
2096 14:00:10.152929 Jitter Meter : NO K
2097 14:00:10.156385 CBT Training : PASS
2098 14:00:10.156467 Write leveling : PASS
2099 14:00:10.159380 RX DQS gating : PASS
2100 14:00:10.163407 RX DQ/DQS(RDDQC) : PASS
2101 14:00:10.163490 TX DQ/DQS : PASS
2102 14:00:10.166182 RX DATLAT : PASS
2103 14:00:10.169482 RX DQ/DQS(Engine): PASS
2104 14:00:10.169564 TX OE : NO K
2105 14:00:10.169649 All Pass.
2106 14:00:10.169727
2107 14:00:10.172624 DramC Write-DBI off
2108 14:00:10.176312 PER_BANK_REFRESH: Hybrid Mode
2109 14:00:10.176394 TX_TRACKING: ON
2110 14:00:10.179896 [GetDramInforAfterCalByMRR] Vendor 6.
2111 14:00:10.183270 [GetDramInforAfterCalByMRR] Revision 606.
2112 14:00:10.186788 [GetDramInforAfterCalByMRR] Revision 2 0.
2113 14:00:10.190166 MR0 0x3b3b
2114 14:00:10.190249 MR8 0x5151
2115 14:00:10.193489 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 14:00:10.193571
2117 14:00:10.196170 MR0 0x3b3b
2118 14:00:10.196253 MR8 0x5151
2119 14:00:10.199865 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 14:00:10.199947
2121 14:00:10.210358 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2122 14:00:10.213078 [FAST_K] Save calibration result to emmc
2123 14:00:10.216418 [FAST_K] Save calibration result to emmc
2124 14:00:10.216500 dram_init: config_dvfs: 1
2125 14:00:10.223740 dramc_set_vcore_voltage set vcore to 662500
2126 14:00:10.223822 Read voltage for 1200, 2
2127 14:00:10.226915 Vio18 = 0
2128 14:00:10.226997 Vcore = 662500
2129 14:00:10.227080 Vdram = 0
2130 14:00:10.230350 Vddq = 0
2131 14:00:10.230482 Vmddr = 0
2132 14:00:10.233812 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2133 14:00:10.240113 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2134 14:00:10.243943 MEM_TYPE=3, freq_sel=15
2135 14:00:10.244025 sv_algorithm_assistance_LP4_1600
2136 14:00:10.250402 ============ PULL DRAM RESETB DOWN ============
2137 14:00:10.254240 ========== PULL DRAM RESETB DOWN end =========
2138 14:00:10.256740 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 14:00:10.260419 ===================================
2140 14:00:10.264136 LPDDR4 DRAM CONFIGURATION
2141 14:00:10.267525 ===================================
2142 14:00:10.270571 EX_ROW_EN[0] = 0x0
2143 14:00:10.270653 EX_ROW_EN[1] = 0x0
2144 14:00:10.273711 LP4Y_EN = 0x0
2145 14:00:10.273793 WORK_FSP = 0x0
2146 14:00:10.277463 WL = 0x4
2147 14:00:10.277545 RL = 0x4
2148 14:00:10.280952 BL = 0x2
2149 14:00:10.281034 RPST = 0x0
2150 14:00:10.283799 RD_PRE = 0x0
2151 14:00:10.283881 WR_PRE = 0x1
2152 14:00:10.286994 WR_PST = 0x0
2153 14:00:10.287076 DBI_WR = 0x0
2154 14:00:10.290502 DBI_RD = 0x0
2155 14:00:10.290584 OTF = 0x1
2156 14:00:10.293650 ===================================
2157 14:00:10.297805 ===================================
2158 14:00:10.300550 ANA top config
2159 14:00:10.303977 ===================================
2160 14:00:10.304059 DLL_ASYNC_EN = 0
2161 14:00:10.307412 ALL_SLAVE_EN = 0
2162 14:00:10.310853 NEW_RANK_MODE = 1
2163 14:00:10.313743 DLL_IDLE_MODE = 1
2164 14:00:10.313850 LP45_APHY_COMB_EN = 1
2165 14:00:10.317797 TX_ODT_DIS = 1
2166 14:00:10.320707 NEW_8X_MODE = 1
2167 14:00:10.324346 ===================================
2168 14:00:10.327058 ===================================
2169 14:00:10.330568 data_rate = 2400
2170 14:00:10.334184 CKR = 1
2171 14:00:10.337463 DQ_P2S_RATIO = 8
2172 14:00:10.341114 ===================================
2173 14:00:10.341196 CA_P2S_RATIO = 8
2174 14:00:10.344009 DQ_CA_OPEN = 0
2175 14:00:10.347673 DQ_SEMI_OPEN = 0
2176 14:00:10.350639 CA_SEMI_OPEN = 0
2177 14:00:10.354125 CA_FULL_RATE = 0
2178 14:00:10.354207 DQ_CKDIV4_EN = 0
2179 14:00:10.357595 CA_CKDIV4_EN = 0
2180 14:00:10.360877 CA_PREDIV_EN = 0
2181 14:00:10.364171 PH8_DLY = 17
2182 14:00:10.367470 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2183 14:00:10.371340 DQ_AAMCK_DIV = 4
2184 14:00:10.371423 CA_AAMCK_DIV = 4
2185 14:00:10.374362 CA_ADMCK_DIV = 4
2186 14:00:10.377413 DQ_TRACK_CA_EN = 0
2187 14:00:10.380980 CA_PICK = 1200
2188 14:00:10.384393 CA_MCKIO = 1200
2189 14:00:10.387290 MCKIO_SEMI = 0
2190 14:00:10.390935 PLL_FREQ = 2366
2191 14:00:10.391018 DQ_UI_PI_RATIO = 32
2192 14:00:10.394353 CA_UI_PI_RATIO = 0
2193 14:00:10.397645 ===================================
2194 14:00:10.401378 ===================================
2195 14:00:10.404148 memory_type:LPDDR4
2196 14:00:10.407608 GP_NUM : 10
2197 14:00:10.407690 SRAM_EN : 1
2198 14:00:10.411367 MD32_EN : 0
2199 14:00:10.415212 ===================================
2200 14:00:10.415295 [ANA_INIT] >>>>>>>>>>>>>>
2201 14:00:10.417534 <<<<<< [CONFIGURE PHASE]: ANA_TX
2202 14:00:10.421375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2203 14:00:10.424490 ===================================
2204 14:00:10.427531 data_rate = 2400,PCW = 0X5b00
2205 14:00:10.430945 ===================================
2206 14:00:10.434798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2207 14:00:10.441242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 14:00:10.444716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 14:00:10.451374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2210 14:00:10.454736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2211 14:00:10.457761 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2212 14:00:10.461095 [ANA_INIT] flow start
2213 14:00:10.461177 [ANA_INIT] PLL >>>>>>>>
2214 14:00:10.464789 [ANA_INIT] PLL <<<<<<<<
2215 14:00:10.468117 [ANA_INIT] MIDPI >>>>>>>>
2216 14:00:10.468200 [ANA_INIT] MIDPI <<<<<<<<
2217 14:00:10.471143 [ANA_INIT] DLL >>>>>>>>
2218 14:00:10.474382 [ANA_INIT] DLL <<<<<<<<
2219 14:00:10.474506 [ANA_INIT] flow end
2220 14:00:10.478133 ============ LP4 DIFF to SE enter ============
2221 14:00:10.484566 ============ LP4 DIFF to SE exit ============
2222 14:00:10.484649 [ANA_INIT] <<<<<<<<<<<<<
2223 14:00:10.487820 [Flow] Enable top DCM control >>>>>
2224 14:00:10.491531 [Flow] Enable top DCM control <<<<<
2225 14:00:10.494955 Enable DLL master slave shuffle
2226 14:00:10.501494 ==============================================================
2227 14:00:10.501578 Gating Mode config
2228 14:00:10.507798 ==============================================================
2229 14:00:10.511304 Config description:
2230 14:00:10.518237 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2231 14:00:10.524897 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2232 14:00:10.531440 SELPH_MODE 0: By rank 1: By Phase
2233 14:00:10.538251 ==============================================================
2234 14:00:10.538359 GAT_TRACK_EN = 1
2235 14:00:10.541500 RX_GATING_MODE = 2
2236 14:00:10.545150 RX_GATING_TRACK_MODE = 2
2237 14:00:10.548250 SELPH_MODE = 1
2238 14:00:10.551575 PICG_EARLY_EN = 1
2239 14:00:10.555168 VALID_LAT_VALUE = 1
2240 14:00:10.561992 ==============================================================
2241 14:00:10.565369 Enter into Gating configuration >>>>
2242 14:00:10.568259 Exit from Gating configuration <<<<
2243 14:00:10.568339 Enter into DVFS_PRE_config >>>>>
2244 14:00:10.582000 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2245 14:00:10.585235 Exit from DVFS_PRE_config <<<<<
2246 14:00:10.588385 Enter into PICG configuration >>>>
2247 14:00:10.592274 Exit from PICG configuration <<<<
2248 14:00:10.592354 [RX_INPUT] configuration >>>>>
2249 14:00:10.595274 [RX_INPUT] configuration <<<<<
2250 14:00:10.602176 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2251 14:00:10.605500 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2252 14:00:10.612180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 14:00:10.618524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 14:00:10.625331 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 14:00:10.632072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 14:00:10.635579 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2257 14:00:10.638995 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2258 14:00:10.642595 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2259 14:00:10.648763 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2260 14:00:10.652407 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2261 14:00:10.655286 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 14:00:10.658734 ===================================
2263 14:00:10.662135 LPDDR4 DRAM CONFIGURATION
2264 14:00:10.665374 ===================================
2265 14:00:10.668814 EX_ROW_EN[0] = 0x0
2266 14:00:10.668894 EX_ROW_EN[1] = 0x0
2267 14:00:10.672426 LP4Y_EN = 0x0
2268 14:00:10.672506 WORK_FSP = 0x0
2269 14:00:10.675948 WL = 0x4
2270 14:00:10.676027 RL = 0x4
2271 14:00:10.678891 BL = 0x2
2272 14:00:10.678970 RPST = 0x0
2273 14:00:10.682193 RD_PRE = 0x0
2274 14:00:10.682272 WR_PRE = 0x1
2275 14:00:10.685283 WR_PST = 0x0
2276 14:00:10.685363 DBI_WR = 0x0
2277 14:00:10.688887 DBI_RD = 0x0
2278 14:00:10.688966 OTF = 0x1
2279 14:00:10.692069 ===================================
2280 14:00:10.695680 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2281 14:00:10.702206 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2282 14:00:10.705560 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 14:00:10.709219 ===================================
2284 14:00:10.712873 LPDDR4 DRAM CONFIGURATION
2285 14:00:10.715358 ===================================
2286 14:00:10.715439 EX_ROW_EN[0] = 0x10
2287 14:00:10.718982 EX_ROW_EN[1] = 0x0
2288 14:00:10.719064 LP4Y_EN = 0x0
2289 14:00:10.722407 WORK_FSP = 0x0
2290 14:00:10.722518 WL = 0x4
2291 14:00:10.725846 RL = 0x4
2292 14:00:10.725953 BL = 0x2
2293 14:00:10.729066 RPST = 0x0
2294 14:00:10.732605 RD_PRE = 0x0
2295 14:00:10.732734 WR_PRE = 0x1
2296 14:00:10.736272 WR_PST = 0x0
2297 14:00:10.736379 DBI_WR = 0x0
2298 14:00:10.738884 DBI_RD = 0x0
2299 14:00:10.738962 OTF = 0x1
2300 14:00:10.742700 ===================================
2301 14:00:10.748925 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2302 14:00:10.749005 ==
2303 14:00:10.752596 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 14:00:10.756146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2305 14:00:10.756226 ==
2306 14:00:10.759792 [Duty_Offset_Calibration]
2307 14:00:10.759871 B0:2 B1:-1 CA:1
2308 14:00:10.759934
2309 14:00:10.762518 [DutyScan_Calibration_Flow] k_type=0
2310 14:00:10.772701
2311 14:00:10.772780 ==CLK 0==
2312 14:00:10.775852 Final CLK duty delay cell = -4
2313 14:00:10.779423 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2314 14:00:10.782852 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2315 14:00:10.786081 [-4] AVG Duty = 4953%(X100)
2316 14:00:10.786160
2317 14:00:10.789678 CH0 CLK Duty spec in!! Max-Min= 156%
2318 14:00:10.792918 [DutyScan_Calibration_Flow] ====Done====
2319 14:00:10.792997
2320 14:00:10.796096 [DutyScan_Calibration_Flow] k_type=1
2321 14:00:10.811343
2322 14:00:10.811422 ==DQS 0 ==
2323 14:00:10.814847 Final DQS duty delay cell = 0
2324 14:00:10.818257 [0] MAX Duty = 5125%(X100), DQS PI = 48
2325 14:00:10.822041 [0] MIN Duty = 5000%(X100), DQS PI = 12
2326 14:00:10.822122 [0] AVG Duty = 5062%(X100)
2327 14:00:10.824744
2328 14:00:10.824825 ==DQS 1 ==
2329 14:00:10.828462 Final DQS duty delay cell = -4
2330 14:00:10.831847 [-4] MAX Duty = 5124%(X100), DQS PI = 14
2331 14:00:10.835077 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2332 14:00:10.838177 [-4] AVG Duty = 5062%(X100)
2333 14:00:10.838257
2334 14:00:10.841708 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2335 14:00:10.841789
2336 14:00:10.845226 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2337 14:00:10.848622 [DutyScan_Calibration_Flow] ====Done====
2338 14:00:10.848703
2339 14:00:10.851836 [DutyScan_Calibration_Flow] k_type=3
2340 14:00:10.868565
2341 14:00:10.868654 ==DQM 0 ==
2342 14:00:10.872364 Final DQM duty delay cell = 0
2343 14:00:10.875390 [0] MAX Duty = 5000%(X100), DQS PI = 46
2344 14:00:10.878738 [0] MIN Duty = 4907%(X100), DQS PI = 2
2345 14:00:10.878820 [0] AVG Duty = 4953%(X100)
2346 14:00:10.882142
2347 14:00:10.882222 ==DQM 1 ==
2348 14:00:10.885191 Final DQM duty delay cell = 0
2349 14:00:10.889052 [0] MAX Duty = 5124%(X100), DQS PI = 32
2350 14:00:10.891701 [0] MIN Duty = 4969%(X100), DQS PI = 10
2351 14:00:10.891783 [0] AVG Duty = 5046%(X100)
2352 14:00:10.891847
2353 14:00:10.895043 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2354 14:00:10.898461
2355 14:00:10.902160 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2356 14:00:10.905488 [DutyScan_Calibration_Flow] ====Done====
2357 14:00:10.905567
2358 14:00:10.908751 [DutyScan_Calibration_Flow] k_type=2
2359 14:00:10.923807
2360 14:00:10.923892 ==DQ 0 ==
2361 14:00:10.927213 Final DQ duty delay cell = -4
2362 14:00:10.931591 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2363 14:00:10.934224 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2364 14:00:10.937601 [-4] AVG Duty = 4969%(X100)
2365 14:00:10.937729
2366 14:00:10.937820 ==DQ 1 ==
2367 14:00:10.940682 Final DQ duty delay cell = 0
2368 14:00:10.944518 [0] MAX Duty = 5031%(X100), DQS PI = 26
2369 14:00:10.947759 [0] MIN Duty = 4907%(X100), DQS PI = 46
2370 14:00:10.947839 [0] AVG Duty = 4969%(X100)
2371 14:00:10.950936
2372 14:00:10.954291 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2373 14:00:10.954371
2374 14:00:10.957528 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2375 14:00:10.960709 [DutyScan_Calibration_Flow] ====Done====
2376 14:00:10.960789 ==
2377 14:00:10.964287 Dram Type= 6, Freq= 0, CH_1, rank 0
2378 14:00:10.967637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 14:00:10.967720 ==
2380 14:00:10.971066 [Duty_Offset_Calibration]
2381 14:00:10.971146 B0:1 B1:1 CA:2
2382 14:00:10.971208
2383 14:00:10.974549 [DutyScan_Calibration_Flow] k_type=0
2384 14:00:10.984497
2385 14:00:10.984578 ==CLK 0==
2386 14:00:10.987896 Final CLK duty delay cell = 0
2387 14:00:10.990788 [0] MAX Duty = 5156%(X100), DQS PI = 24
2388 14:00:10.995257 [0] MIN Duty = 4938%(X100), DQS PI = 46
2389 14:00:10.995337 [0] AVG Duty = 5047%(X100)
2390 14:00:10.997907
2391 14:00:10.997985 CH1 CLK Duty spec in!! Max-Min= 218%
2392 14:00:11.004266 [DutyScan_Calibration_Flow] ====Done====
2393 14:00:11.004348
2394 14:00:11.007575 [DutyScan_Calibration_Flow] k_type=1
2395 14:00:11.023814
2396 14:00:11.023907 ==DQS 0 ==
2397 14:00:11.027313 Final DQS duty delay cell = 0
2398 14:00:11.030513 [0] MAX Duty = 5031%(X100), DQS PI = 18
2399 14:00:11.034053 [0] MIN Duty = 4813%(X100), DQS PI = 50
2400 14:00:11.037441 [0] AVG Duty = 4922%(X100)
2401 14:00:11.037529
2402 14:00:11.037630 ==DQS 1 ==
2403 14:00:11.040383 Final DQS duty delay cell = 0
2404 14:00:11.043527 [0] MAX Duty = 5062%(X100), DQS PI = 36
2405 14:00:11.047739 [0] MIN Duty = 4907%(X100), DQS PI = 8
2406 14:00:11.047825 [0] AVG Duty = 4984%(X100)
2407 14:00:11.050253
2408 14:00:11.054415 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2409 14:00:11.054510
2410 14:00:11.056870 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2411 14:00:11.060498 [DutyScan_Calibration_Flow] ====Done====
2412 14:00:11.060580
2413 14:00:11.063843 [DutyScan_Calibration_Flow] k_type=3
2414 14:00:11.080156
2415 14:00:11.080253 ==DQM 0 ==
2416 14:00:11.083561 Final DQM duty delay cell = 0
2417 14:00:11.086736 [0] MAX Duty = 5093%(X100), DQS PI = 18
2418 14:00:11.090660 [0] MIN Duty = 4907%(X100), DQS PI = 48
2419 14:00:11.090742 [0] AVG Duty = 5000%(X100)
2420 14:00:11.093801
2421 14:00:11.093901 ==DQM 1 ==
2422 14:00:11.096864 Final DQM duty delay cell = 0
2423 14:00:11.100155 [0] MAX Duty = 5124%(X100), DQS PI = 62
2424 14:00:11.103869 [0] MIN Duty = 4938%(X100), DQS PI = 22
2425 14:00:11.103950 [0] AVG Duty = 5031%(X100)
2426 14:00:11.106769
2427 14:00:11.111073 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2428 14:00:11.111153
2429 14:00:11.113588 CH1 DQM 1 Duty spec in!! Max-Min= 186%
2430 14:00:11.117185 [DutyScan_Calibration_Flow] ====Done====
2431 14:00:11.117267
2432 14:00:11.120429 [DutyScan_Calibration_Flow] k_type=2
2433 14:00:11.136685
2434 14:00:11.136766 ==DQ 0 ==
2435 14:00:11.140613 Final DQ duty delay cell = 0
2436 14:00:11.143776 [0] MAX Duty = 5124%(X100), DQS PI = 18
2437 14:00:11.146884 [0] MIN Duty = 4969%(X100), DQS PI = 6
2438 14:00:11.146965 [0] AVG Duty = 5046%(X100)
2439 14:00:11.147028
2440 14:00:11.150248 ==DQ 1 ==
2441 14:00:11.153691 Final DQ duty delay cell = 0
2442 14:00:11.156880 [0] MAX Duty = 5124%(X100), DQS PI = 58
2443 14:00:11.160370 [0] MIN Duty = 5031%(X100), DQS PI = 4
2444 14:00:11.160452 [0] AVG Duty = 5077%(X100)
2445 14:00:11.160515
2446 14:00:11.163437 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2447 14:00:11.163518
2448 14:00:11.166909 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2449 14:00:11.170125 [DutyScan_Calibration_Flow] ====Done====
2450 14:00:11.175776 nWR fixed to 30
2451 14:00:11.178746 [ModeRegInit_LP4] CH0 RK0
2452 14:00:11.178831 [ModeRegInit_LP4] CH0 RK1
2453 14:00:11.182893 [ModeRegInit_LP4] CH1 RK0
2454 14:00:11.185590 [ModeRegInit_LP4] CH1 RK1
2455 14:00:11.185691 match AC timing 7
2456 14:00:11.192095 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2457 14:00:11.195602 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2458 14:00:11.199095 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2459 14:00:11.206020 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2460 14:00:11.208921 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2461 14:00:11.209004 ==
2462 14:00:11.212564 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 14:00:11.215958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2464 14:00:11.216044 ==
2465 14:00:11.222659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2466 14:00:11.229132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2467 14:00:11.236335 [CA 0] Center 40 (10~71) winsize 62
2468 14:00:11.239643 [CA 1] Center 39 (9~70) winsize 62
2469 14:00:11.242984 [CA 2] Center 36 (6~67) winsize 62
2470 14:00:11.246354 [CA 3] Center 36 (5~67) winsize 63
2471 14:00:11.250071 [CA 4] Center 35 (5~65) winsize 61
2472 14:00:11.253296 [CA 5] Center 34 (4~64) winsize 61
2473 14:00:11.253385
2474 14:00:11.256632 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2475 14:00:11.256714
2476 14:00:11.260017 [CATrainingPosCal] consider 1 rank data
2477 14:00:11.263577 u2DelayCellTimex100 = 270/100 ps
2478 14:00:11.266884 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2479 14:00:11.270022 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2480 14:00:11.276823 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2481 14:00:11.280077 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2482 14:00:11.283491 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2483 14:00:11.287028 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2484 14:00:11.287112
2485 14:00:11.290316 CA PerBit enable=1, Macro0, CA PI delay=34
2486 14:00:11.290407
2487 14:00:11.293903 [CBTSetCACLKResult] CA Dly = 34
2488 14:00:11.293988 CS Dly: 7 (0~38)
2489 14:00:11.294089 ==
2490 14:00:11.297075 Dram Type= 6, Freq= 0, CH_0, rank 1
2491 14:00:11.303887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 14:00:11.303973 ==
2493 14:00:11.306806 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 14:00:11.313932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2495 14:00:11.322679 [CA 0] Center 39 (9~70) winsize 62
2496 14:00:11.325722 [CA 1] Center 39 (9~70) winsize 62
2497 14:00:11.329611 [CA 2] Center 36 (6~67) winsize 62
2498 14:00:11.332471 [CA 3] Center 36 (5~67) winsize 63
2499 14:00:11.335815 [CA 4] Center 34 (4~65) winsize 62
2500 14:00:11.339088 [CA 5] Center 34 (4~64) winsize 61
2501 14:00:11.339173
2502 14:00:11.342768 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2503 14:00:11.342852
2504 14:00:11.345987 [CATrainingPosCal] consider 2 rank data
2505 14:00:11.349234 u2DelayCellTimex100 = 270/100 ps
2506 14:00:11.352831 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2507 14:00:11.356157 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2508 14:00:11.359655 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2509 14:00:11.366355 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2510 14:00:11.369831 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2511 14:00:11.373142 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2512 14:00:11.373227
2513 14:00:11.376280 CA PerBit enable=1, Macro0, CA PI delay=34
2514 14:00:11.376364
2515 14:00:11.379762 [CBTSetCACLKResult] CA Dly = 34
2516 14:00:11.379847 CS Dly: 8 (0~41)
2517 14:00:11.379947
2518 14:00:11.382865 ----->DramcWriteLeveling(PI) begin...
2519 14:00:11.382951 ==
2520 14:00:11.386333 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 14:00:11.393220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 14:00:11.393305 ==
2523 14:00:11.396611 Write leveling (Byte 0): 30 => 30
2524 14:00:11.396696 Write leveling (Byte 1): 29 => 29
2525 14:00:11.399779 DramcWriteLeveling(PI) end<-----
2526 14:00:11.399864
2527 14:00:11.399964 ==
2528 14:00:11.403663 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 14:00:11.410016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 14:00:11.410102 ==
2531 14:00:11.413441 [Gating] SW mode calibration
2532 14:00:11.419941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2533 14:00:11.424045 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2534 14:00:11.430378 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 14:00:11.433485 0 15 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2536 14:00:11.437092 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 14:00:11.440150 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 14:00:11.446617 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 14:00:11.450021 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 14:00:11.454132 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 14:00:11.460119 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2542 14:00:11.463714 1 0 0 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
2543 14:00:11.466786 1 0 4 | B1->B0 | 2929 2424 | 0 0 | (1 0) (0 0)
2544 14:00:11.473530 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 14:00:11.476943 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 14:00:11.480413 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 14:00:11.487074 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 14:00:11.490636 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 14:00:11.493763 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 14:00:11.500433 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2551 14:00:11.504008 1 1 4 | B1->B0 | 3c3c 4444 | 0 1 | (0 0) (0 0)
2552 14:00:11.507222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 14:00:11.511042 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 14:00:11.517226 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 14:00:11.520935 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 14:00:11.524361 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 14:00:11.531003 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 14:00:11.534059 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 14:00:11.537510 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 14:00:11.544643 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 14:00:11.547814 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 14:00:11.550891 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 14:00:11.554363 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 14:00:11.561509 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 14:00:11.564836 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 14:00:11.567976 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 14:00:11.574729 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 14:00:11.578231 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 14:00:11.581577 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 14:00:11.587615 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 14:00:11.591383 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 14:00:11.594349 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 14:00:11.601091 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 14:00:11.604672 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2575 14:00:11.608414 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2576 14:00:11.611162 Total UI for P1: 0, mck2ui 16
2577 14:00:11.614748 best dqsien dly found for B0: ( 1, 4, 0)
2578 14:00:11.617910 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 14:00:11.621243 Total UI for P1: 0, mck2ui 16
2580 14:00:11.624861 best dqsien dly found for B1: ( 1, 4, 2)
2581 14:00:11.628288 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2582 14:00:11.631319 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2583 14:00:11.631394
2584 14:00:11.638264 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2585 14:00:11.641394 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2586 14:00:11.641474 [Gating] SW calibration Done
2587 14:00:11.644696 ==
2588 14:00:11.647973 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 14:00:11.651248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 14:00:11.651329 ==
2591 14:00:11.651392 RX Vref Scan: 0
2592 14:00:11.651451
2593 14:00:11.654429 RX Vref 0 -> 0, step: 1
2594 14:00:11.654541
2595 14:00:11.657945 RX Delay -40 -> 252, step: 8
2596 14:00:11.661349 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2597 14:00:11.664672 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2598 14:00:11.667880 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2599 14:00:11.675666 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2600 14:00:11.677946 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2601 14:00:11.681412 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2602 14:00:11.685277 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2603 14:00:11.688092 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2604 14:00:11.694901 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2605 14:00:11.698372 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2606 14:00:11.701722 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2607 14:00:11.705474 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2608 14:00:11.708346 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2609 14:00:11.714869 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2610 14:00:11.718726 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2611 14:00:11.721528 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2612 14:00:11.721608 ==
2613 14:00:11.725262 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 14:00:11.728668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 14:00:11.728749 ==
2616 14:00:11.731947 DQS Delay:
2617 14:00:11.732028 DQS0 = 0, DQS1 = 0
2618 14:00:11.732122 DQM Delay:
2619 14:00:11.734978 DQM0 = 116, DQM1 = 107
2620 14:00:11.735058 DQ Delay:
2621 14:00:11.738636 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2622 14:00:11.742229 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2623 14:00:11.745497 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2624 14:00:11.749052 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2625 14:00:11.752055
2626 14:00:11.752136
2627 14:00:11.752199 ==
2628 14:00:11.755235 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 14:00:11.758652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 14:00:11.758758 ==
2631 14:00:11.758849
2632 14:00:11.758935
2633 14:00:11.761799 TX Vref Scan disable
2634 14:00:11.761878 == TX Byte 0 ==
2635 14:00:11.768351 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2636 14:00:11.772400 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2637 14:00:11.772480 == TX Byte 1 ==
2638 14:00:11.779315 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2639 14:00:11.782175 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2640 14:00:11.782263 ==
2641 14:00:11.786036 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 14:00:11.788754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 14:00:11.788839 ==
2644 14:00:11.801606 TX Vref=22, minBit 7, minWin=24, winSum=420
2645 14:00:11.804743 TX Vref=24, minBit 1, minWin=25, winSum=424
2646 14:00:11.808177 TX Vref=26, minBit 1, minWin=25, winSum=426
2647 14:00:11.811046 TX Vref=28, minBit 12, minWin=25, winSum=433
2648 14:00:11.814456 TX Vref=30, minBit 0, minWin=26, winSum=436
2649 14:00:11.818363 TX Vref=32, minBit 0, minWin=26, winSum=433
2650 14:00:11.825048 [TxChooseVref] Worse bit 0, Min win 26, Win sum 436, Final Vref 30
2651 14:00:11.825132
2652 14:00:11.828021 Final TX Range 1 Vref 30
2653 14:00:11.828105
2654 14:00:11.828191 ==
2655 14:00:11.831281 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 14:00:11.835011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 14:00:11.835096 ==
2658 14:00:11.835182
2659 14:00:11.835262
2660 14:00:11.837845 TX Vref Scan disable
2661 14:00:11.841862 == TX Byte 0 ==
2662 14:00:11.844494 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2663 14:00:11.848585 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2664 14:00:11.851804 == TX Byte 1 ==
2665 14:00:11.854870 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2666 14:00:11.858481 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2667 14:00:11.858566
2668 14:00:11.861840 [DATLAT]
2669 14:00:11.861924 Freq=1200, CH0 RK0
2670 14:00:11.862010
2671 14:00:11.864966 DATLAT Default: 0xd
2672 14:00:11.865050 0, 0xFFFF, sum = 0
2673 14:00:11.868198 1, 0xFFFF, sum = 0
2674 14:00:11.868284 2, 0xFFFF, sum = 0
2675 14:00:11.871418 3, 0xFFFF, sum = 0
2676 14:00:11.871505 4, 0xFFFF, sum = 0
2677 14:00:11.874824 5, 0xFFFF, sum = 0
2678 14:00:11.874910 6, 0xFFFF, sum = 0
2679 14:00:11.878204 7, 0xFFFF, sum = 0
2680 14:00:11.878290 8, 0xFFFF, sum = 0
2681 14:00:11.881679 9, 0xFFFF, sum = 0
2682 14:00:11.881765 10, 0xFFFF, sum = 0
2683 14:00:11.884822 11, 0xFFFF, sum = 0
2684 14:00:11.884907 12, 0x0, sum = 1
2685 14:00:11.888753 13, 0x0, sum = 2
2686 14:00:11.888839 14, 0x0, sum = 3
2687 14:00:11.891767 15, 0x0, sum = 4
2688 14:00:11.891853 best_step = 13
2689 14:00:11.891953
2690 14:00:11.892052 ==
2691 14:00:11.895155 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 14:00:11.901642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 14:00:11.901723 ==
2694 14:00:11.901786 RX Vref Scan: 1
2695 14:00:11.901845
2696 14:00:11.905020 Set Vref Range= 32 -> 127
2697 14:00:11.905100
2698 14:00:11.908201 RX Vref 32 -> 127, step: 1
2699 14:00:11.908281
2700 14:00:11.908343 RX Delay -21 -> 252, step: 4
2701 14:00:11.908402
2702 14:00:11.911444 Set Vref, RX VrefLevel [Byte0]: 32
2703 14:00:11.914751 [Byte1]: 32
2704 14:00:11.919315
2705 14:00:11.919420 Set Vref, RX VrefLevel [Byte0]: 33
2706 14:00:11.922822 [Byte1]: 33
2707 14:00:11.927145
2708 14:00:11.927249 Set Vref, RX VrefLevel [Byte0]: 34
2709 14:00:11.930305 [Byte1]: 34
2710 14:00:11.934964
2711 14:00:11.935042 Set Vref, RX VrefLevel [Byte0]: 35
2712 14:00:11.938606 [Byte1]: 35
2713 14:00:11.942992
2714 14:00:11.943092 Set Vref, RX VrefLevel [Byte0]: 36
2715 14:00:11.946474 [Byte1]: 36
2716 14:00:11.951034
2717 14:00:11.951107 Set Vref, RX VrefLevel [Byte0]: 37
2718 14:00:11.954151 [Byte1]: 37
2719 14:00:11.958835
2720 14:00:11.958937 Set Vref, RX VrefLevel [Byte0]: 38
2721 14:00:11.962531 [Byte1]: 38
2722 14:00:11.966876
2723 14:00:11.966975 Set Vref, RX VrefLevel [Byte0]: 39
2724 14:00:11.970515 [Byte1]: 39
2725 14:00:11.974706
2726 14:00:11.974809 Set Vref, RX VrefLevel [Byte0]: 40
2727 14:00:11.978126 [Byte1]: 40
2728 14:00:11.982744
2729 14:00:11.982849 Set Vref, RX VrefLevel [Byte0]: 41
2730 14:00:11.986132 [Byte1]: 41
2731 14:00:11.990989
2732 14:00:11.991089 Set Vref, RX VrefLevel [Byte0]: 42
2733 14:00:11.994311 [Byte1]: 42
2734 14:00:11.998524
2735 14:00:11.998615 Set Vref, RX VrefLevel [Byte0]: 43
2736 14:00:12.001770 [Byte1]: 43
2737 14:00:12.006345
2738 14:00:12.006469 Set Vref, RX VrefLevel [Byte0]: 44
2739 14:00:12.009693 [Byte1]: 44
2740 14:00:12.014633
2741 14:00:12.014710 Set Vref, RX VrefLevel [Byte0]: 45
2742 14:00:12.018687 [Byte1]: 45
2743 14:00:12.022313
2744 14:00:12.022431 Set Vref, RX VrefLevel [Byte0]: 46
2745 14:00:12.025545 [Byte1]: 46
2746 14:00:12.030460
2747 14:00:12.030541 Set Vref, RX VrefLevel [Byte0]: 47
2748 14:00:12.033770 [Byte1]: 47
2749 14:00:12.038362
2750 14:00:12.038501 Set Vref, RX VrefLevel [Byte0]: 48
2751 14:00:12.041669 [Byte1]: 48
2752 14:00:12.046298
2753 14:00:12.046413 Set Vref, RX VrefLevel [Byte0]: 49
2754 14:00:12.049347 [Byte1]: 49
2755 14:00:12.054338
2756 14:00:12.054449 Set Vref, RX VrefLevel [Byte0]: 50
2757 14:00:12.057918 [Byte1]: 50
2758 14:00:12.062143
2759 14:00:12.062243 Set Vref, RX VrefLevel [Byte0]: 51
2760 14:00:12.065133 [Byte1]: 51
2761 14:00:12.069945
2762 14:00:12.070042 Set Vref, RX VrefLevel [Byte0]: 52
2763 14:00:12.073366 [Byte1]: 52
2764 14:00:12.077838
2765 14:00:12.077945 Set Vref, RX VrefLevel [Byte0]: 53
2766 14:00:12.081165 [Byte1]: 53
2767 14:00:12.085567
2768 14:00:12.085645 Set Vref, RX VrefLevel [Byte0]: 54
2769 14:00:12.088924 [Byte1]: 54
2770 14:00:12.093615
2771 14:00:12.093699 Set Vref, RX VrefLevel [Byte0]: 55
2772 14:00:12.097041 [Byte1]: 55
2773 14:00:12.101786
2774 14:00:12.101865 Set Vref, RX VrefLevel [Byte0]: 56
2775 14:00:12.104997 [Byte1]: 56
2776 14:00:12.109900
2777 14:00:12.109980 Set Vref, RX VrefLevel [Byte0]: 57
2778 14:00:12.113116 [Byte1]: 57
2779 14:00:12.117616
2780 14:00:12.117695 Set Vref, RX VrefLevel [Byte0]: 58
2781 14:00:12.120992 [Byte1]: 58
2782 14:00:12.125290
2783 14:00:12.125369 Set Vref, RX VrefLevel [Byte0]: 59
2784 14:00:12.128745 [Byte1]: 59
2785 14:00:12.133166
2786 14:00:12.133247 Set Vref, RX VrefLevel [Byte0]: 60
2787 14:00:12.136651 [Byte1]: 60
2788 14:00:12.141369
2789 14:00:12.141449 Set Vref, RX VrefLevel [Byte0]: 61
2790 14:00:12.144678 [Byte1]: 61
2791 14:00:12.149298
2792 14:00:12.149379 Set Vref, RX VrefLevel [Byte0]: 62
2793 14:00:12.152666 [Byte1]: 62
2794 14:00:12.157329
2795 14:00:12.157409 Set Vref, RX VrefLevel [Byte0]: 63
2796 14:00:12.160530 [Byte1]: 63
2797 14:00:12.165419
2798 14:00:12.165498 Set Vref, RX VrefLevel [Byte0]: 64
2799 14:00:12.168383 [Byte1]: 64
2800 14:00:12.172984
2801 14:00:12.173064 Set Vref, RX VrefLevel [Byte0]: 65
2802 14:00:12.176224 [Byte1]: 65
2803 14:00:12.180976
2804 14:00:12.181055 Set Vref, RX VrefLevel [Byte0]: 66
2805 14:00:12.184177 [Byte1]: 66
2806 14:00:12.188915
2807 14:00:12.188995 Set Vref, RX VrefLevel [Byte0]: 67
2808 14:00:12.192142 [Byte1]: 67
2809 14:00:12.196866
2810 14:00:12.196945 Set Vref, RX VrefLevel [Byte0]: 68
2811 14:00:12.199884 [Byte1]: 68
2812 14:00:12.204408
2813 14:00:12.204492 Set Vref, RX VrefLevel [Byte0]: 69
2814 14:00:12.207891 [Byte1]: 69
2815 14:00:12.212446
2816 14:00:12.212529 Final RX Vref Byte 0 = 54 to rank0
2817 14:00:12.215887 Final RX Vref Byte 1 = 51 to rank0
2818 14:00:12.219288 Final RX Vref Byte 0 = 54 to rank1
2819 14:00:12.222520 Final RX Vref Byte 1 = 51 to rank1==
2820 14:00:12.226044 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 14:00:12.229647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 14:00:12.232622 ==
2823 14:00:12.232702 DQS Delay:
2824 14:00:12.232765 DQS0 = 0, DQS1 = 0
2825 14:00:12.235972 DQM Delay:
2826 14:00:12.236052 DQM0 = 115, DQM1 = 104
2827 14:00:12.239698 DQ Delay:
2828 14:00:12.242691 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2829 14:00:12.246239 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2830 14:00:12.249233 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2831 14:00:12.252999 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2832 14:00:12.253079
2833 14:00:12.253142
2834 14:00:12.259825 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2835 14:00:12.263003 CH0 RK0: MR19=303, MR18=FEED
2836 14:00:12.269139 CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26
2837 14:00:12.269220
2838 14:00:12.273223 ----->DramcWriteLeveling(PI) begin...
2839 14:00:12.273305 ==
2840 14:00:12.275795 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 14:00:12.279501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 14:00:12.279582 ==
2843 14:00:12.282767 Write leveling (Byte 0): 33 => 33
2844 14:00:12.286512 Write leveling (Byte 1): 27 => 27
2845 14:00:12.289943 DramcWriteLeveling(PI) end<-----
2846 14:00:12.290022
2847 14:00:12.290085 ==
2848 14:00:12.292765 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 14:00:12.296298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 14:00:12.300004 ==
2851 14:00:12.300085 [Gating] SW mode calibration
2852 14:00:12.306702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 14:00:12.313319 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 14:00:12.316746 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2855 14:00:12.323291 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
2856 14:00:12.326567 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 14:00:12.330319 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 14:00:12.333252 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 14:00:12.339909 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 14:00:12.343696 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2861 14:00:12.346998 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2862 14:00:12.353550 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2863 14:00:12.356670 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 14:00:12.360005 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 14:00:12.366633 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 14:00:12.370304 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 14:00:12.373397 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 14:00:12.380209 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2869 14:00:12.383601 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2870 14:00:12.386837 1 1 0 | B1->B0 | 2c2b 3b3b | 1 1 | (0 0) (0 0)
2871 14:00:12.390562 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2872 14:00:12.397079 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 14:00:12.400617 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 14:00:12.404217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 14:00:12.410817 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 14:00:12.413915 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 14:00:12.417433 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 14:00:12.424151 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2879 14:00:12.427663 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2880 14:00:12.430664 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 14:00:12.437477 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 14:00:12.441348 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 14:00:12.444182 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 14:00:12.451741 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 14:00:12.454384 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 14:00:12.457797 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 14:00:12.461395 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 14:00:12.467536 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 14:00:12.471057 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 14:00:12.474184 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 14:00:12.481426 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 14:00:12.484270 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2893 14:00:12.487475 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 14:00:12.494577 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 14:00:12.494662 Total UI for P1: 0, mck2ui 16
2896 14:00:12.501044 best dqsien dly found for B0: ( 1, 3, 26)
2897 14:00:12.504827 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2898 14:00:12.507674 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 14:00:12.511110 Total UI for P1: 0, mck2ui 16
2900 14:00:12.514285 best dqsien dly found for B1: ( 1, 4, 2)
2901 14:00:12.517789 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2902 14:00:12.521357 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2903 14:00:12.521459
2904 14:00:12.524244 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2905 14:00:12.528319 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2906 14:00:12.531355 [Gating] SW calibration Done
2907 14:00:12.531453 ==
2908 14:00:12.534340 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 14:00:12.537807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 14:00:12.541758 ==
2911 14:00:12.541860 RX Vref Scan: 0
2912 14:00:12.541949
2913 14:00:12.544564 RX Vref 0 -> 0, step: 1
2914 14:00:12.544670
2915 14:00:12.548351 RX Delay -40 -> 252, step: 8
2916 14:00:12.551511 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2917 14:00:12.555119 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2918 14:00:12.557952 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2919 14:00:12.561965 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2920 14:00:12.565127 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2921 14:00:12.572021 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2922 14:00:12.574949 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2923 14:00:12.578283 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2924 14:00:12.581456 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2925 14:00:12.585236 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2926 14:00:12.591903 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2927 14:00:12.595558 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2928 14:00:12.598518 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2929 14:00:12.601981 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2930 14:00:12.604917 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2931 14:00:12.611759 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2932 14:00:12.611864 ==
2933 14:00:12.614998 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 14:00:12.618517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 14:00:12.618623 ==
2936 14:00:12.618716 DQS Delay:
2937 14:00:12.621718 DQS0 = 0, DQS1 = 0
2938 14:00:12.621818 DQM Delay:
2939 14:00:12.625183 DQM0 = 116, DQM1 = 106
2940 14:00:12.625279 DQ Delay:
2941 14:00:12.628471 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2942 14:00:12.631653 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2943 14:00:12.635555 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2944 14:00:12.638844 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2945 14:00:12.638920
2946 14:00:12.638996
2947 14:00:12.639082 ==
2948 14:00:12.642280 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 14:00:12.648428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 14:00:12.648531 ==
2951 14:00:12.648627
2952 14:00:12.648716
2953 14:00:12.648801 TX Vref Scan disable
2954 14:00:12.652058 == TX Byte 0 ==
2955 14:00:12.655464 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2956 14:00:12.658906 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2957 14:00:12.662183 == TX Byte 1 ==
2958 14:00:12.665753 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2959 14:00:12.669021 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2960 14:00:12.672037 ==
2961 14:00:12.676132 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 14:00:12.679025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 14:00:12.679127 ==
2964 14:00:12.690306 TX Vref=22, minBit 1, minWin=25, winSum=416
2965 14:00:12.694102 TX Vref=24, minBit 0, minWin=26, winSum=424
2966 14:00:12.697463 TX Vref=26, minBit 1, minWin=26, winSum=431
2967 14:00:12.700551 TX Vref=28, minBit 0, minWin=26, winSum=432
2968 14:00:12.704072 TX Vref=30, minBit 3, minWin=26, winSum=436
2969 14:00:12.707609 TX Vref=32, minBit 1, minWin=26, winSum=435
2970 14:00:12.713989 [TxChooseVref] Worse bit 3, Min win 26, Win sum 436, Final Vref 30
2971 14:00:12.714097
2972 14:00:12.717697 Final TX Range 1 Vref 30
2973 14:00:12.717796
2974 14:00:12.717893 ==
2975 14:00:12.720817 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 14:00:12.723891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 14:00:12.723990 ==
2978 14:00:12.724084
2979 14:00:12.724170
2980 14:00:12.727241 TX Vref Scan disable
2981 14:00:12.730572 == TX Byte 0 ==
2982 14:00:12.734455 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2983 14:00:12.737251 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2984 14:00:12.740637 == TX Byte 1 ==
2985 14:00:12.744085 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2986 14:00:12.747547 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2987 14:00:12.747628
2988 14:00:12.751234 [DATLAT]
2989 14:00:12.751313 Freq=1200, CH0 RK1
2990 14:00:12.751376
2991 14:00:12.754890 DATLAT Default: 0xd
2992 14:00:12.754971 0, 0xFFFF, sum = 0
2993 14:00:12.757873 1, 0xFFFF, sum = 0
2994 14:00:12.757954 2, 0xFFFF, sum = 0
2995 14:00:12.760894 3, 0xFFFF, sum = 0
2996 14:00:12.760976 4, 0xFFFF, sum = 0
2997 14:00:12.764000 5, 0xFFFF, sum = 0
2998 14:00:12.764082 6, 0xFFFF, sum = 0
2999 14:00:12.768007 7, 0xFFFF, sum = 0
3000 14:00:12.768088 8, 0xFFFF, sum = 0
3001 14:00:12.770711 9, 0xFFFF, sum = 0
3002 14:00:12.770798 10, 0xFFFF, sum = 0
3003 14:00:12.774381 11, 0xFFFF, sum = 0
3004 14:00:12.774465 12, 0x0, sum = 1
3005 14:00:12.777627 13, 0x0, sum = 2
3006 14:00:12.777727 14, 0x0, sum = 3
3007 14:00:12.780816 15, 0x0, sum = 4
3008 14:00:12.780935 best_step = 13
3009 14:00:12.781035
3010 14:00:12.781128 ==
3011 14:00:12.784149 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 14:00:12.791369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 14:00:12.791473 ==
3014 14:00:12.791567 RX Vref Scan: 0
3015 14:00:12.791655
3016 14:00:12.794873 RX Vref 0 -> 0, step: 1
3017 14:00:12.794947
3018 14:00:12.798096 RX Delay -21 -> 252, step: 4
3019 14:00:12.800926 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3020 14:00:12.804238 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3021 14:00:12.807957 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3022 14:00:12.814771 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3023 14:00:12.817726 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3024 14:00:12.821467 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3025 14:00:12.824470 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3026 14:00:12.827934 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3027 14:00:12.834554 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3028 14:00:12.838196 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3029 14:00:12.841264 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3030 14:00:12.844587 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3031 14:00:12.847831 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3032 14:00:12.854391 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3033 14:00:12.857983 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3034 14:00:12.861369 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3035 14:00:12.861450 ==
3036 14:00:12.864815 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 14:00:12.868707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 14:00:12.868788 ==
3039 14:00:12.871558 DQS Delay:
3040 14:00:12.871637 DQS0 = 0, DQS1 = 0
3041 14:00:12.871701 DQM Delay:
3042 14:00:12.875140 DQM0 = 114, DQM1 = 104
3043 14:00:12.875220 DQ Delay:
3044 14:00:12.878729 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3045 14:00:12.881621 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3046 14:00:12.885052 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3047 14:00:12.888190 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3048 14:00:12.891697
3049 14:00:12.891776
3050 14:00:12.898851 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3051 14:00:12.901741 CH0 RK1: MR19=403, MR18=4F4
3052 14:00:12.908703 CH0_RK1: MR19=0x403, MR18=0x4F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3053 14:00:12.908783 [RxdqsGatingPostProcess] freq 1200
3054 14:00:12.915390 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 14:00:12.918568 best DQS0 dly(2T, 0.5T) = (0, 12)
3056 14:00:12.921934 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 14:00:12.925467 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3058 14:00:12.928854 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 14:00:12.932392 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 14:00:12.935067 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 14:00:12.938619 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 14:00:12.941648 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 14:00:12.945462 Pre-setting of DQS Precalculation
3064 14:00:12.948852 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 14:00:12.948933 ==
3066 14:00:12.951865 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 14:00:12.955744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 14:00:12.955825 ==
3069 14:00:12.962302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 14:00:12.968695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3071 14:00:12.975962 [CA 0] Center 38 (8~68) winsize 61
3072 14:00:12.979643 [CA 1] Center 38 (8~68) winsize 61
3073 14:00:12.983428 [CA 2] Center 35 (5~65) winsize 61
3074 14:00:12.986089 [CA 3] Center 34 (4~65) winsize 62
3075 14:00:12.989899 [CA 4] Center 34 (4~65) winsize 62
3076 14:00:12.993078 [CA 5] Center 33 (3~64) winsize 62
3077 14:00:12.993180
3078 14:00:12.996226 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3079 14:00:12.996324
3080 14:00:12.999429 [CATrainingPosCal] consider 1 rank data
3081 14:00:13.003374 u2DelayCellTimex100 = 270/100 ps
3082 14:00:13.006095 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3083 14:00:13.009589 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3084 14:00:13.012940 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3085 14:00:13.019949 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3086 14:00:13.023347 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3087 14:00:13.026538 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3088 14:00:13.026619
3089 14:00:13.029758 CA PerBit enable=1, Macro0, CA PI delay=33
3090 14:00:13.029837
3091 14:00:13.033454 [CBTSetCACLKResult] CA Dly = 33
3092 14:00:13.033535 CS Dly: 6 (0~37)
3093 14:00:13.033598 ==
3094 14:00:13.036589 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 14:00:13.042782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 14:00:13.042862 ==
3097 14:00:13.046641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 14:00:13.053057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3099 14:00:13.061380 [CA 0] Center 38 (8~68) winsize 61
3100 14:00:13.065015 [CA 1] Center 38 (8~68) winsize 61
3101 14:00:13.068816 [CA 2] Center 35 (5~65) winsize 61
3102 14:00:13.071618 [CA 3] Center 34 (4~65) winsize 62
3103 14:00:13.075102 [CA 4] Center 34 (4~65) winsize 62
3104 14:00:13.078643 [CA 5] Center 33 (3~63) winsize 61
3105 14:00:13.078723
3106 14:00:13.082029 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 14:00:13.082109
3108 14:00:13.085326 [CATrainingPosCal] consider 2 rank data
3109 14:00:13.088409 u2DelayCellTimex100 = 270/100 ps
3110 14:00:13.091912 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3111 14:00:13.095695 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3112 14:00:13.098902 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3113 14:00:13.105155 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 14:00:13.108895 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3115 14:00:13.112120 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3116 14:00:13.112200
3117 14:00:13.115086 CA PerBit enable=1, Macro0, CA PI delay=33
3118 14:00:13.115166
3119 14:00:13.118622 [CBTSetCACLKResult] CA Dly = 33
3120 14:00:13.118738 CS Dly: 7 (0~40)
3121 14:00:13.118803
3122 14:00:13.122091 ----->DramcWriteLeveling(PI) begin...
3123 14:00:13.122172 ==
3124 14:00:13.126084 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 14:00:13.131882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 14:00:13.131962 ==
3127 14:00:13.135283 Write leveling (Byte 0): 26 => 26
3128 14:00:13.135362 Write leveling (Byte 1): 29 => 29
3129 14:00:13.138700 DramcWriteLeveling(PI) end<-----
3130 14:00:13.138780
3131 14:00:13.138843 ==
3132 14:00:13.142278 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 14:00:13.148791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 14:00:13.148872 ==
3135 14:00:13.152019 [Gating] SW mode calibration
3136 14:00:13.158983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 14:00:13.162384 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 14:00:13.168830 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3139 14:00:13.172529 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 14:00:13.175747 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 14:00:13.179221 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3142 14:00:13.185737 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 14:00:13.189193 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 14:00:13.192571 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3145 14:00:13.199434 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3146 14:00:13.202673 1 0 0 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 1)
3147 14:00:13.206209 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 14:00:13.212695 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3149 14:00:13.216119 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 14:00:13.219209 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 14:00:13.226260 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 14:00:13.229273 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3153 14:00:13.232698 1 0 28 | B1->B0 | 3131 2a2a | 1 0 | (0 0) (0 0)
3154 14:00:13.236098 1 1 0 | B1->B0 | 4040 2f2e | 0 1 | (0 0) (0 0)
3155 14:00:13.242880 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 14:00:13.246340 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 14:00:13.249935 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 14:00:13.256537 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 14:00:13.259968 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 14:00:13.263442 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 14:00:13.269744 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3162 14:00:13.273632 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 14:00:13.276826 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 14:00:13.283345 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 14:00:13.286801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 14:00:13.290350 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 14:00:13.293698 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 14:00:13.300078 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 14:00:13.303220 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 14:00:13.306793 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 14:00:13.313598 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 14:00:13.316606 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 14:00:13.320452 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 14:00:13.326734 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 14:00:13.330224 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 14:00:13.333816 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 14:00:13.340261 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 14:00:13.343943 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3179 14:00:13.347415 Total UI for P1: 0, mck2ui 16
3180 14:00:13.350208 best dqsien dly found for B0: ( 1, 3, 28)
3181 14:00:13.353897 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 14:00:13.357156 Total UI for P1: 0, mck2ui 16
3183 14:00:13.360304 best dqsien dly found for B1: ( 1, 4, 0)
3184 14:00:13.364085 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3185 14:00:13.367348 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3186 14:00:13.367428
3187 14:00:13.370647 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3188 14:00:13.373732 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3189 14:00:13.377044 [Gating] SW calibration Done
3190 14:00:13.377125 ==
3191 14:00:13.380721 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 14:00:13.383681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 14:00:13.387347 ==
3194 14:00:13.387426 RX Vref Scan: 0
3195 14:00:13.387490
3196 14:00:13.390461 RX Vref 0 -> 0, step: 1
3197 14:00:13.390540
3198 14:00:13.394073 RX Delay -40 -> 252, step: 8
3199 14:00:13.397726 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3200 14:00:13.400502 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3201 14:00:13.403925 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3202 14:00:13.407394 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3203 14:00:13.410946 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3204 14:00:13.417758 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3205 14:00:13.420761 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3206 14:00:13.424005 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3207 14:00:13.427670 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 14:00:13.430862 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3209 14:00:13.437783 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3210 14:00:13.440947 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 14:00:13.444446 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3212 14:00:13.448032 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3213 14:00:13.451700 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3214 14:00:13.457819 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3215 14:00:13.457899 ==
3216 14:00:13.460885 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 14:00:13.464273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 14:00:13.464354 ==
3219 14:00:13.464418 DQS Delay:
3220 14:00:13.467685 DQS0 = 0, DQS1 = 0
3221 14:00:13.467765 DQM Delay:
3222 14:00:13.471152 DQM0 = 115, DQM1 = 108
3223 14:00:13.471231 DQ Delay:
3224 14:00:13.474686 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3225 14:00:13.477893 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3226 14:00:13.481523 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3227 14:00:13.484541 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3228 14:00:13.484620
3229 14:00:13.484683
3230 14:00:13.484741 ==
3231 14:00:13.487980 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 14:00:13.494661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 14:00:13.494742 ==
3234 14:00:13.494807
3235 14:00:13.494866
3236 14:00:13.494922 TX Vref Scan disable
3237 14:00:13.498515 == TX Byte 0 ==
3238 14:00:13.501569 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3239 14:00:13.505286 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3240 14:00:13.508281 == TX Byte 1 ==
3241 14:00:13.511523 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3242 14:00:13.515667 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3243 14:00:13.518095 ==
3244 14:00:13.521663 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 14:00:13.524651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 14:00:13.524731 ==
3247 14:00:13.536240 TX Vref=22, minBit 0, minWin=25, winSum=411
3248 14:00:13.539994 TX Vref=24, minBit 0, minWin=25, winSum=417
3249 14:00:13.543096 TX Vref=26, minBit 1, minWin=26, winSum=424
3250 14:00:13.545941 TX Vref=28, minBit 0, minWin=26, winSum=427
3251 14:00:13.549070 TX Vref=30, minBit 3, minWin=26, winSum=433
3252 14:00:13.552410 TX Vref=32, minBit 1, minWin=26, winSum=428
3253 14:00:13.559792 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 30
3254 14:00:13.559907
3255 14:00:13.562830 Final TX Range 1 Vref 30
3256 14:00:13.562929
3257 14:00:13.563030 ==
3258 14:00:13.566265 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 14:00:13.569556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 14:00:13.569645 ==
3261 14:00:13.569734
3262 14:00:13.569833
3263 14:00:13.572786 TX Vref Scan disable
3264 14:00:13.576230 == TX Byte 0 ==
3265 14:00:13.579856 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3266 14:00:13.583463 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3267 14:00:13.586349 == TX Byte 1 ==
3268 14:00:13.589561 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3269 14:00:13.593471 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3270 14:00:13.593574
3271 14:00:13.596320 [DATLAT]
3272 14:00:13.596415 Freq=1200, CH1 RK0
3273 14:00:13.596507
3274 14:00:13.599762 DATLAT Default: 0xd
3275 14:00:13.599862 0, 0xFFFF, sum = 0
3276 14:00:13.603096 1, 0xFFFF, sum = 0
3277 14:00:13.603192 2, 0xFFFF, sum = 0
3278 14:00:13.606599 3, 0xFFFF, sum = 0
3279 14:00:13.606672 4, 0xFFFF, sum = 0
3280 14:00:13.609770 5, 0xFFFF, sum = 0
3281 14:00:13.609846 6, 0xFFFF, sum = 0
3282 14:00:13.613068 7, 0xFFFF, sum = 0
3283 14:00:13.613176 8, 0xFFFF, sum = 0
3284 14:00:13.616573 9, 0xFFFF, sum = 0
3285 14:00:13.616685 10, 0xFFFF, sum = 0
3286 14:00:13.620420 11, 0xFFFF, sum = 0
3287 14:00:13.620525 12, 0x0, sum = 1
3288 14:00:13.623022 13, 0x0, sum = 2
3289 14:00:13.623121 14, 0x0, sum = 3
3290 14:00:13.626677 15, 0x0, sum = 4
3291 14:00:13.626788 best_step = 13
3292 14:00:13.626881
3293 14:00:13.626967 ==
3294 14:00:13.629753 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 14:00:13.636619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 14:00:13.636730 ==
3297 14:00:13.636820 RX Vref Scan: 1
3298 14:00:13.636919
3299 14:00:13.639931 Set Vref Range= 32 -> 127
3300 14:00:13.640030
3301 14:00:13.643533 RX Vref 32 -> 127, step: 1
3302 14:00:13.643609
3303 14:00:13.643670 RX Delay -21 -> 252, step: 4
3304 14:00:13.643742
3305 14:00:13.646688 Set Vref, RX VrefLevel [Byte0]: 32
3306 14:00:13.649970 [Byte1]: 32
3307 14:00:13.654494
3308 14:00:13.654593 Set Vref, RX VrefLevel [Byte0]: 33
3309 14:00:13.657901 [Byte1]: 33
3310 14:00:13.662101
3311 14:00:13.662201 Set Vref, RX VrefLevel [Byte0]: 34
3312 14:00:13.665432 [Byte1]: 34
3313 14:00:13.669894
3314 14:00:13.670000 Set Vref, RX VrefLevel [Byte0]: 35
3315 14:00:13.673701 [Byte1]: 35
3316 14:00:13.677783
3317 14:00:13.677896 Set Vref, RX VrefLevel [Byte0]: 36
3318 14:00:13.681549 [Byte1]: 36
3319 14:00:13.685611
3320 14:00:13.685719 Set Vref, RX VrefLevel [Byte0]: 37
3321 14:00:13.689016 [Byte1]: 37
3322 14:00:13.693533
3323 14:00:13.693642 Set Vref, RX VrefLevel [Byte0]: 38
3324 14:00:13.697107 [Byte1]: 38
3325 14:00:13.701592
3326 14:00:13.701691 Set Vref, RX VrefLevel [Byte0]: 39
3327 14:00:13.704964 [Byte1]: 39
3328 14:00:13.709915
3329 14:00:13.710024 Set Vref, RX VrefLevel [Byte0]: 40
3330 14:00:13.712960 [Byte1]: 40
3331 14:00:13.717432
3332 14:00:13.717528 Set Vref, RX VrefLevel [Byte0]: 41
3333 14:00:13.720993 [Byte1]: 41
3334 14:00:13.725494
3335 14:00:13.725577 Set Vref, RX VrefLevel [Byte0]: 42
3336 14:00:13.729622 [Byte1]: 42
3337 14:00:13.733373
3338 14:00:13.733471 Set Vref, RX VrefLevel [Byte0]: 43
3339 14:00:13.736818 [Byte1]: 43
3340 14:00:13.741361
3341 14:00:13.741440 Set Vref, RX VrefLevel [Byte0]: 44
3342 14:00:13.744955 [Byte1]: 44
3343 14:00:13.749367
3344 14:00:13.749446 Set Vref, RX VrefLevel [Byte0]: 45
3345 14:00:13.752401 [Byte1]: 45
3346 14:00:13.756832
3347 14:00:13.756911 Set Vref, RX VrefLevel [Byte0]: 46
3348 14:00:13.760776 [Byte1]: 46
3349 14:00:13.764916
3350 14:00:13.764995 Set Vref, RX VrefLevel [Byte0]: 47
3351 14:00:13.768245 [Byte1]: 47
3352 14:00:13.773149
3353 14:00:13.773245 Set Vref, RX VrefLevel [Byte0]: 48
3354 14:00:13.776591 [Byte1]: 48
3355 14:00:13.781104
3356 14:00:13.781184 Set Vref, RX VrefLevel [Byte0]: 49
3357 14:00:13.784128 [Byte1]: 49
3358 14:00:13.788747
3359 14:00:13.788826 Set Vref, RX VrefLevel [Byte0]: 50
3360 14:00:13.792535 [Byte1]: 50
3361 14:00:13.796990
3362 14:00:13.797069 Set Vref, RX VrefLevel [Byte0]: 51
3363 14:00:13.800294 [Byte1]: 51
3364 14:00:13.804931
3365 14:00:13.805010 Set Vref, RX VrefLevel [Byte0]: 52
3366 14:00:13.807868 [Byte1]: 52
3367 14:00:13.812453
3368 14:00:13.812533 Set Vref, RX VrefLevel [Byte0]: 53
3369 14:00:13.815928 [Byte1]: 53
3370 14:00:13.820628
3371 14:00:13.820707 Set Vref, RX VrefLevel [Byte0]: 54
3372 14:00:13.823954 [Byte1]: 54
3373 14:00:13.828811
3374 14:00:13.828890 Set Vref, RX VrefLevel [Byte0]: 55
3375 14:00:13.832328 [Byte1]: 55
3376 14:00:13.836595
3377 14:00:13.836678 Set Vref, RX VrefLevel [Byte0]: 56
3378 14:00:13.839432 [Byte1]: 56
3379 14:00:13.844063
3380 14:00:13.844141 Set Vref, RX VrefLevel [Byte0]: 57
3381 14:00:13.847437 [Byte1]: 57
3382 14:00:13.851997
3383 14:00:13.852075 Set Vref, RX VrefLevel [Byte0]: 58
3384 14:00:13.855447 [Byte1]: 58
3385 14:00:13.859882
3386 14:00:13.859961 Set Vref, RX VrefLevel [Byte0]: 59
3387 14:00:13.863147 [Byte1]: 59
3388 14:00:13.867916
3389 14:00:13.868008 Set Vref, RX VrefLevel [Byte0]: 60
3390 14:00:13.871229 [Byte1]: 60
3391 14:00:13.876183
3392 14:00:13.876261 Set Vref, RX VrefLevel [Byte0]: 61
3393 14:00:13.879840 [Byte1]: 61
3394 14:00:13.883864
3395 14:00:13.883943 Set Vref, RX VrefLevel [Byte0]: 62
3396 14:00:13.887065 [Byte1]: 62
3397 14:00:13.891713
3398 14:00:13.891818 Set Vref, RX VrefLevel [Byte0]: 63
3399 14:00:13.895198 [Byte1]: 63
3400 14:00:13.899702
3401 14:00:13.899781 Set Vref, RX VrefLevel [Byte0]: 64
3402 14:00:13.903197 [Byte1]: 64
3403 14:00:13.907986
3404 14:00:13.908064 Set Vref, RX VrefLevel [Byte0]: 65
3405 14:00:13.911156 [Byte1]: 65
3406 14:00:13.915605
3407 14:00:13.915684 Set Vref, RX VrefLevel [Byte0]: 66
3408 14:00:13.918789 [Byte1]: 66
3409 14:00:13.923420
3410 14:00:13.923525 Set Vref, RX VrefLevel [Byte0]: 67
3411 14:00:13.926775 [Byte1]: 67
3412 14:00:13.931213
3413 14:00:13.931292 Set Vref, RX VrefLevel [Byte0]: 68
3414 14:00:13.934740 [Byte1]: 68
3415 14:00:13.939197
3416 14:00:13.939275 Set Vref, RX VrefLevel [Byte0]: 69
3417 14:00:13.942628 [Byte1]: 69
3418 14:00:13.946916
3419 14:00:13.946994 Set Vref, RX VrefLevel [Byte0]: 70
3420 14:00:13.951186 [Byte1]: 70
3421 14:00:13.955000
3422 14:00:13.955080 Set Vref, RX VrefLevel [Byte0]: 71
3423 14:00:13.958537 [Byte1]: 71
3424 14:00:13.962933
3425 14:00:13.963012 Set Vref, RX VrefLevel [Byte0]: 72
3426 14:00:13.966741 [Byte1]: 72
3427 14:00:13.970823
3428 14:00:13.970902 Final RX Vref Byte 0 = 56 to rank0
3429 14:00:13.974370 Final RX Vref Byte 1 = 52 to rank0
3430 14:00:13.977825 Final RX Vref Byte 0 = 56 to rank1
3431 14:00:13.980928 Final RX Vref Byte 1 = 52 to rank1==
3432 14:00:13.984157 Dram Type= 6, Freq= 0, CH_1, rank 0
3433 14:00:13.987913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 14:00:13.991295 ==
3435 14:00:13.991376 DQS Delay:
3436 14:00:13.991438 DQS0 = 0, DQS1 = 0
3437 14:00:13.994122 DQM Delay:
3438 14:00:13.994201 DQM0 = 115, DQM1 = 109
3439 14:00:13.998392 DQ Delay:
3440 14:00:14.001121 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3441 14:00:14.005262 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3442 14:00:14.008014 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =106
3443 14:00:14.010970 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3444 14:00:14.011050
3445 14:00:14.011112
3446 14:00:14.017809 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe4, (MSB)MR19= 0x303, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3447 14:00:14.021051 CH1 RK0: MR19=303, MR18=FFE4
3448 14:00:14.027705 CH1_RK0: MR19=0x303, MR18=0xFFE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3449 14:00:14.027785
3450 14:00:14.031145 ----->DramcWriteLeveling(PI) begin...
3451 14:00:14.031227 ==
3452 14:00:14.035067 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 14:00:14.037905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 14:00:14.037985 ==
3455 14:00:14.041192 Write leveling (Byte 0): 26 => 26
3456 14:00:14.045075 Write leveling (Byte 1): 30 => 30
3457 14:00:14.047792 DramcWriteLeveling(PI) end<-----
3458 14:00:14.047872
3459 14:00:14.047934 ==
3460 14:00:14.051634 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 14:00:14.054598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 14:00:14.058853 ==
3463 14:00:14.058932 [Gating] SW mode calibration
3464 14:00:14.064872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3465 14:00:14.071335 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3466 14:00:14.074947 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3467 14:00:14.081488 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3468 14:00:14.084808 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 14:00:14.087766 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 14:00:14.094750 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 14:00:14.097773 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 14:00:14.101679 0 15 24 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
3473 14:00:14.108266 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3474 14:00:14.111108 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 14:00:14.114533 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 14:00:14.121456 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 14:00:14.124877 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 14:00:14.127674 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 14:00:14.130986 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3480 14:00:14.137819 1 0 24 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
3481 14:00:14.141545 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3482 14:00:14.144447 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 14:00:14.151474 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 14:00:14.154334 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 14:00:14.157864 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 14:00:14.164591 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 14:00:14.167901 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3488 14:00:14.171119 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3489 14:00:14.178110 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3490 14:00:14.181468 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 14:00:14.184630 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 14:00:14.190854 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 14:00:14.194633 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 14:00:14.197740 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 14:00:14.204232 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 14:00:14.208029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 14:00:14.211771 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 14:00:14.217988 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 14:00:14.221266 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 14:00:14.224519 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 14:00:14.230946 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 14:00:14.234637 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 14:00:14.237701 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3504 14:00:14.241100 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3505 14:00:14.247611 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3506 14:00:14.251317 Total UI for P1: 0, mck2ui 16
3507 14:00:14.254292 best dqsien dly found for B0: ( 1, 3, 22)
3508 14:00:14.257657 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 14:00:14.260990 Total UI for P1: 0, mck2ui 16
3510 14:00:14.264367 best dqsien dly found for B1: ( 1, 3, 28)
3511 14:00:14.267798 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3512 14:00:14.271345 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3513 14:00:14.271425
3514 14:00:14.274369 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3515 14:00:14.277645 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3516 14:00:14.281189 [Gating] SW calibration Done
3517 14:00:14.281269 ==
3518 14:00:14.284115 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 14:00:14.291269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 14:00:14.291349 ==
3521 14:00:14.291413 RX Vref Scan: 0
3522 14:00:14.291472
3523 14:00:14.294346 RX Vref 0 -> 0, step: 1
3524 14:00:14.294478
3525 14:00:14.297719 RX Delay -40 -> 252, step: 8
3526 14:00:14.300738 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3527 14:00:14.304352 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3528 14:00:14.307851 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3529 14:00:14.311346 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3530 14:00:14.317528 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3531 14:00:14.321072 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3532 14:00:14.324372 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3533 14:00:14.327562 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3534 14:00:14.331110 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3535 14:00:14.337722 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3536 14:00:14.341240 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3537 14:00:14.344336 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3538 14:00:14.347596 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3539 14:00:14.350636 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3540 14:00:14.357408 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3541 14:00:14.361039 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3542 14:00:14.361154 ==
3543 14:00:14.364272 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 14:00:14.368018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 14:00:14.368091 ==
3546 14:00:14.370804 DQS Delay:
3547 14:00:14.370878 DQS0 = 0, DQS1 = 0
3548 14:00:14.370944 DQM Delay:
3549 14:00:14.374081 DQM0 = 113, DQM1 = 110
3550 14:00:14.374174 DQ Delay:
3551 14:00:14.377569 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3552 14:00:14.381018 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3553 14:00:14.384345 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3554 14:00:14.391225 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3555 14:00:14.391324
3556 14:00:14.391413
3557 14:00:14.391502 ==
3558 14:00:14.394280 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 14:00:14.397798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 14:00:14.397899 ==
3561 14:00:14.397990
3562 14:00:14.398076
3563 14:00:14.400763 TX Vref Scan disable
3564 14:00:14.400861 == TX Byte 0 ==
3565 14:00:14.407762 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3566 14:00:14.410950 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3567 14:00:14.411031 == TX Byte 1 ==
3568 14:00:14.417972 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3569 14:00:14.421156 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3570 14:00:14.421261 ==
3571 14:00:14.424360 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 14:00:14.427366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 14:00:14.427442 ==
3574 14:00:14.440348 TX Vref=22, minBit 2, minWin=25, winSum=420
3575 14:00:14.443157 TX Vref=24, minBit 15, minWin=24, winSum=423
3576 14:00:14.446542 TX Vref=26, minBit 3, minWin=25, winSum=427
3577 14:00:14.450034 TX Vref=28, minBit 1, minWin=25, winSum=431
3578 14:00:14.453680 TX Vref=30, minBit 1, minWin=26, winSum=432
3579 14:00:14.456878 TX Vref=32, minBit 1, minWin=26, winSum=433
3580 14:00:14.463453 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 32
3581 14:00:14.463532
3582 14:00:14.466929 Final TX Range 1 Vref 32
3583 14:00:14.467007
3584 14:00:14.467069 ==
3585 14:00:14.470248 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 14:00:14.473353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 14:00:14.473456 ==
3588 14:00:14.473559
3589 14:00:14.476874
3590 14:00:14.476973 TX Vref Scan disable
3591 14:00:14.480170 == TX Byte 0 ==
3592 14:00:14.483674 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3593 14:00:14.486904 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3594 14:00:14.490621 == TX Byte 1 ==
3595 14:00:14.493752 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3596 14:00:14.496964 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3597 14:00:14.497064
3598 14:00:14.500417 [DATLAT]
3599 14:00:14.500526 Freq=1200, CH1 RK1
3600 14:00:14.500616
3601 14:00:14.503432 DATLAT Default: 0xd
3602 14:00:14.503540 0, 0xFFFF, sum = 0
3603 14:00:14.506995 1, 0xFFFF, sum = 0
3604 14:00:14.507084 2, 0xFFFF, sum = 0
3605 14:00:14.510171 3, 0xFFFF, sum = 0
3606 14:00:14.510271 4, 0xFFFF, sum = 0
3607 14:00:14.513740 5, 0xFFFF, sum = 0
3608 14:00:14.513841 6, 0xFFFF, sum = 0
3609 14:00:14.517227 7, 0xFFFF, sum = 0
3610 14:00:14.517328 8, 0xFFFF, sum = 0
3611 14:00:14.519963 9, 0xFFFF, sum = 0
3612 14:00:14.524117 10, 0xFFFF, sum = 0
3613 14:00:14.524223 11, 0xFFFF, sum = 0
3614 14:00:14.526713 12, 0x0, sum = 1
3615 14:00:14.526790 13, 0x0, sum = 2
3616 14:00:14.530043 14, 0x0, sum = 3
3617 14:00:14.530154 15, 0x0, sum = 4
3618 14:00:14.530247 best_step = 13
3619 14:00:14.530333
3620 14:00:14.533241 ==
3621 14:00:14.533328 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 14:00:14.540411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 14:00:14.540492 ==
3624 14:00:14.540556 RX Vref Scan: 0
3625 14:00:14.540615
3626 14:00:14.543527 RX Vref 0 -> 0, step: 1
3627 14:00:14.543606
3628 14:00:14.546630 RX Delay -21 -> 252, step: 4
3629 14:00:14.550328 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3630 14:00:14.553247 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3631 14:00:14.560239 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3632 14:00:14.563500 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3633 14:00:14.567067 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3634 14:00:14.570636 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3635 14:00:14.573382 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3636 14:00:14.580085 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3637 14:00:14.583282 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3638 14:00:14.586939 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3639 14:00:14.590629 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3640 14:00:14.593350 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3641 14:00:14.599970 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3642 14:00:14.603154 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3643 14:00:14.606902 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3644 14:00:14.609682 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3645 14:00:14.609761 ==
3646 14:00:14.613330 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 14:00:14.620152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 14:00:14.620233 ==
3649 14:00:14.620297 DQS Delay:
3650 14:00:14.623098 DQS0 = 0, DQS1 = 0
3651 14:00:14.623178 DQM Delay:
3652 14:00:14.626446 DQM0 = 113, DQM1 = 110
3653 14:00:14.626525 DQ Delay:
3654 14:00:14.629753 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3655 14:00:14.632910 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3656 14:00:14.636992 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3657 14:00:14.639648 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =120
3658 14:00:14.639728
3659 14:00:14.639789
3660 14:00:14.649969 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3661 14:00:14.650050 CH1 RK1: MR19=303, MR18=F7FF
3662 14:00:14.656632 CH1_RK1: MR19=0x303, MR18=0xF7FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3663 14:00:14.659487 [RxdqsGatingPostProcess] freq 1200
3664 14:00:14.666337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3665 14:00:14.669739 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 14:00:14.672873 best DQS1 dly(2T, 0.5T) = (0, 12)
3667 14:00:14.676171 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 14:00:14.679605 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3669 14:00:14.679685 best DQS0 dly(2T, 0.5T) = (0, 11)
3670 14:00:14.682770 best DQS1 dly(2T, 0.5T) = (0, 11)
3671 14:00:14.685970 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3672 14:00:14.689395 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3673 14:00:14.692593 Pre-setting of DQS Precalculation
3674 14:00:14.699482 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3675 14:00:14.706125 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3676 14:00:14.713231 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3677 14:00:14.713344
3678 14:00:14.713436
3679 14:00:14.716352 [Calibration Summary] 2400 Mbps
3680 14:00:14.716446 CH 0, Rank 0
3681 14:00:14.719546 SW Impedance : PASS
3682 14:00:14.722771 DUTY Scan : NO K
3683 14:00:14.722851 ZQ Calibration : PASS
3684 14:00:14.726377 Jitter Meter : NO K
3685 14:00:14.729683 CBT Training : PASS
3686 14:00:14.729762 Write leveling : PASS
3687 14:00:14.732605 RX DQS gating : PASS
3688 14:00:14.736455 RX DQ/DQS(RDDQC) : PASS
3689 14:00:14.736535 TX DQ/DQS : PASS
3690 14:00:14.739234 RX DATLAT : PASS
3691 14:00:14.742673 RX DQ/DQS(Engine): PASS
3692 14:00:14.742753 TX OE : NO K
3693 14:00:14.742832 All Pass.
3694 14:00:14.746855
3695 14:00:14.746957 CH 0, Rank 1
3696 14:00:14.749603 SW Impedance : PASS
3697 14:00:14.749685 DUTY Scan : NO K
3698 14:00:14.752978 ZQ Calibration : PASS
3699 14:00:14.753057 Jitter Meter : NO K
3700 14:00:14.756466 CBT Training : PASS
3701 14:00:14.760305 Write leveling : PASS
3702 14:00:14.760385 RX DQS gating : PASS
3703 14:00:14.763211 RX DQ/DQS(RDDQC) : PASS
3704 14:00:14.766519 TX DQ/DQS : PASS
3705 14:00:14.766600 RX DATLAT : PASS
3706 14:00:14.769434 RX DQ/DQS(Engine): PASS
3707 14:00:14.772991 TX OE : NO K
3708 14:00:14.773071 All Pass.
3709 14:00:14.773134
3710 14:00:14.773191 CH 1, Rank 0
3711 14:00:14.776252 SW Impedance : PASS
3712 14:00:14.779956 DUTY Scan : NO K
3713 14:00:14.780036 ZQ Calibration : PASS
3714 14:00:14.782761 Jitter Meter : NO K
3715 14:00:14.786929 CBT Training : PASS
3716 14:00:14.787009 Write leveling : PASS
3717 14:00:14.789579 RX DQS gating : PASS
3718 14:00:14.789659 RX DQ/DQS(RDDQC) : PASS
3719 14:00:14.792968 TX DQ/DQS : PASS
3720 14:00:14.796372 RX DATLAT : PASS
3721 14:00:14.796452 RX DQ/DQS(Engine): PASS
3722 14:00:14.799923 TX OE : NO K
3723 14:00:14.800002 All Pass.
3724 14:00:14.800065
3725 14:00:14.802762 CH 1, Rank 1
3726 14:00:14.802868 SW Impedance : PASS
3727 14:00:14.806335 DUTY Scan : NO K
3728 14:00:14.809713 ZQ Calibration : PASS
3729 14:00:14.809823 Jitter Meter : NO K
3730 14:00:14.813372 CBT Training : PASS
3731 14:00:14.816045 Write leveling : PASS
3732 14:00:14.816154 RX DQS gating : PASS
3733 14:00:14.819694 RX DQ/DQS(RDDQC) : PASS
3734 14:00:14.822736 TX DQ/DQS : PASS
3735 14:00:14.822839 RX DATLAT : PASS
3736 14:00:14.826706 RX DQ/DQS(Engine): PASS
3737 14:00:14.826849 TX OE : NO K
3738 14:00:14.829957 All Pass.
3739 14:00:14.830063
3740 14:00:14.830226 DramC Write-DBI off
3741 14:00:14.833201 PER_BANK_REFRESH: Hybrid Mode
3742 14:00:14.836449 TX_TRACKING: ON
3743 14:00:14.843458 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3744 14:00:14.846646 [FAST_K] Save calibration result to emmc
3745 14:00:14.852999 dramc_set_vcore_voltage set vcore to 650000
3746 14:00:14.853103 Read voltage for 600, 5
3747 14:00:14.853197 Vio18 = 0
3748 14:00:14.856456 Vcore = 650000
3749 14:00:14.856556 Vdram = 0
3750 14:00:14.856646 Vddq = 0
3751 14:00:14.860272 Vmddr = 0
3752 14:00:14.863087 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3753 14:00:14.869824 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3754 14:00:14.869930 MEM_TYPE=3, freq_sel=19
3755 14:00:14.873000 sv_algorithm_assistance_LP4_1600
3756 14:00:14.879725 ============ PULL DRAM RESETB DOWN ============
3757 14:00:14.883297 ========== PULL DRAM RESETB DOWN end =========
3758 14:00:14.886658 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3759 14:00:14.890028 ===================================
3760 14:00:14.893169 LPDDR4 DRAM CONFIGURATION
3761 14:00:14.896561 ===================================
3762 14:00:14.899705 EX_ROW_EN[0] = 0x0
3763 14:00:14.899812 EX_ROW_EN[1] = 0x0
3764 14:00:14.903139 LP4Y_EN = 0x0
3765 14:00:14.903242 WORK_FSP = 0x0
3766 14:00:14.906359 WL = 0x2
3767 14:00:14.906456 RL = 0x2
3768 14:00:14.909672 BL = 0x2
3769 14:00:14.909753 RPST = 0x0
3770 14:00:14.912938 RD_PRE = 0x0
3771 14:00:14.913037 WR_PRE = 0x1
3772 14:00:14.916372 WR_PST = 0x0
3773 14:00:14.916466 DBI_WR = 0x0
3774 14:00:14.919873 DBI_RD = 0x0
3775 14:00:14.919973 OTF = 0x1
3776 14:00:14.923094 ===================================
3777 14:00:14.926560 ===================================
3778 14:00:14.929953 ANA top config
3779 14:00:14.933480 ===================================
3780 14:00:14.933560 DLL_ASYNC_EN = 0
3781 14:00:14.936482 ALL_SLAVE_EN = 1
3782 14:00:14.940430 NEW_RANK_MODE = 1
3783 14:00:14.943254 DLL_IDLE_MODE = 1
3784 14:00:14.946747 LP45_APHY_COMB_EN = 1
3785 14:00:14.946832 TX_ODT_DIS = 1
3786 14:00:14.949675 NEW_8X_MODE = 1
3787 14:00:14.953648 ===================================
3788 14:00:14.956665 ===================================
3789 14:00:14.960015 data_rate = 1200
3790 14:00:14.963214 CKR = 1
3791 14:00:14.966862 DQ_P2S_RATIO = 8
3792 14:00:14.970028 ===================================
3793 14:00:14.970107 CA_P2S_RATIO = 8
3794 14:00:14.973431 DQ_CA_OPEN = 0
3795 14:00:14.976478 DQ_SEMI_OPEN = 0
3796 14:00:14.980230 CA_SEMI_OPEN = 0
3797 14:00:14.983505 CA_FULL_RATE = 0
3798 14:00:14.987060 DQ_CKDIV4_EN = 1
3799 14:00:14.987182 CA_CKDIV4_EN = 1
3800 14:00:14.990125 CA_PREDIV_EN = 0
3801 14:00:14.993190 PH8_DLY = 0
3802 14:00:14.996815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3803 14:00:15.000448 DQ_AAMCK_DIV = 4
3804 14:00:15.000528 CA_AAMCK_DIV = 4
3805 14:00:15.003309 CA_ADMCK_DIV = 4
3806 14:00:15.006792 DQ_TRACK_CA_EN = 0
3807 14:00:15.010195 CA_PICK = 600
3808 14:00:15.013586 CA_MCKIO = 600
3809 14:00:15.016897 MCKIO_SEMI = 0
3810 14:00:15.020477 PLL_FREQ = 2288
3811 14:00:15.020558 DQ_UI_PI_RATIO = 32
3812 14:00:15.023191 CA_UI_PI_RATIO = 0
3813 14:00:15.026666 ===================================
3814 14:00:15.029765 ===================================
3815 14:00:15.033568 memory_type:LPDDR4
3816 14:00:15.036657 GP_NUM : 10
3817 14:00:15.036737 SRAM_EN : 1
3818 14:00:15.039909 MD32_EN : 0
3819 14:00:15.043582 ===================================
3820 14:00:15.043661 [ANA_INIT] >>>>>>>>>>>>>>
3821 14:00:15.046801 <<<<<< [CONFIGURE PHASE]: ANA_TX
3822 14:00:15.050224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3823 14:00:15.053349 ===================================
3824 14:00:15.057127 data_rate = 1200,PCW = 0X5800
3825 14:00:15.060617 ===================================
3826 14:00:15.063710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3827 14:00:15.070157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 14:00:15.073415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 14:00:15.080500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3830 14:00:15.083608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3831 14:00:15.086970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3832 14:00:15.090316 [ANA_INIT] flow start
3833 14:00:15.090440 [ANA_INIT] PLL >>>>>>>>
3834 14:00:15.093486 [ANA_INIT] PLL <<<<<<<<
3835 14:00:15.096895 [ANA_INIT] MIDPI >>>>>>>>
3836 14:00:15.096974 [ANA_INIT] MIDPI <<<<<<<<
3837 14:00:15.100165 [ANA_INIT] DLL >>>>>>>>
3838 14:00:15.103587 [ANA_INIT] flow end
3839 14:00:15.107060 ============ LP4 DIFF to SE enter ============
3840 14:00:15.110129 ============ LP4 DIFF to SE exit ============
3841 14:00:15.113299 [ANA_INIT] <<<<<<<<<<<<<
3842 14:00:15.116861 [Flow] Enable top DCM control >>>>>
3843 14:00:15.120467 [Flow] Enable top DCM control <<<<<
3844 14:00:15.123676 Enable DLL master slave shuffle
3845 14:00:15.127043 ==============================================================
3846 14:00:15.130300 Gating Mode config
3847 14:00:15.133733 ==============================================================
3848 14:00:15.137283 Config description:
3849 14:00:15.146956 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3850 14:00:15.153844 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3851 14:00:15.157464 SELPH_MODE 0: By rank 1: By Phase
3852 14:00:15.163865 ==============================================================
3853 14:00:15.166907 GAT_TRACK_EN = 1
3854 14:00:15.170662 RX_GATING_MODE = 2
3855 14:00:15.173515 RX_GATING_TRACK_MODE = 2
3856 14:00:15.176797 SELPH_MODE = 1
3857 14:00:15.176876 PICG_EARLY_EN = 1
3858 14:00:15.180472 VALID_LAT_VALUE = 1
3859 14:00:15.187303 ==============================================================
3860 14:00:15.190314 Enter into Gating configuration >>>>
3861 14:00:15.194169 Exit from Gating configuration <<<<
3862 14:00:15.196957 Enter into DVFS_PRE_config >>>>>
3863 14:00:15.206928 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3864 14:00:15.210077 Exit from DVFS_PRE_config <<<<<
3865 14:00:15.213572 Enter into PICG configuration >>>>
3866 14:00:15.217217 Exit from PICG configuration <<<<
3867 14:00:15.220467 [RX_INPUT] configuration >>>>>
3868 14:00:15.223538 [RX_INPUT] configuration <<<<<
3869 14:00:15.227369 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3870 14:00:15.234023 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3871 14:00:15.240252 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3872 14:00:15.246812 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3873 14:00:15.253790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3874 14:00:15.257212 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3875 14:00:15.264187 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3876 14:00:15.267152 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3877 14:00:15.269941 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3878 14:00:15.274435 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3879 14:00:15.276764 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3880 14:00:15.283282 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 14:00:15.287280 ===================================
3882 14:00:15.289891 LPDDR4 DRAM CONFIGURATION
3883 14:00:15.293668 ===================================
3884 14:00:15.293747 EX_ROW_EN[0] = 0x0
3885 14:00:15.296995 EX_ROW_EN[1] = 0x0
3886 14:00:15.297075 LP4Y_EN = 0x0
3887 14:00:15.300207 WORK_FSP = 0x0
3888 14:00:15.300287 WL = 0x2
3889 14:00:15.303631 RL = 0x2
3890 14:00:15.303712 BL = 0x2
3891 14:00:15.306652 RPST = 0x0
3892 14:00:15.306732 RD_PRE = 0x0
3893 14:00:15.310076 WR_PRE = 0x1
3894 14:00:15.310155 WR_PST = 0x0
3895 14:00:15.313489 DBI_WR = 0x0
3896 14:00:15.313569 DBI_RD = 0x0
3897 14:00:15.317291 OTF = 0x1
3898 14:00:15.320551 ===================================
3899 14:00:15.323316 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3900 14:00:15.326972 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3901 14:00:15.333763 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3902 14:00:15.336866 ===================================
3903 14:00:15.336946 LPDDR4 DRAM CONFIGURATION
3904 14:00:15.340486 ===================================
3905 14:00:15.343666 EX_ROW_EN[0] = 0x10
3906 14:00:15.347158 EX_ROW_EN[1] = 0x0
3907 14:00:15.347237 LP4Y_EN = 0x0
3908 14:00:15.350311 WORK_FSP = 0x0
3909 14:00:15.350436 WL = 0x2
3910 14:00:15.353364 RL = 0x2
3911 14:00:15.353443 BL = 0x2
3912 14:00:15.357286 RPST = 0x0
3913 14:00:15.357369 RD_PRE = 0x0
3914 14:00:15.360307 WR_PRE = 0x1
3915 14:00:15.360387 WR_PST = 0x0
3916 14:00:15.363660 DBI_WR = 0x0
3917 14:00:15.363740 DBI_RD = 0x0
3918 14:00:15.366860 OTF = 0x1
3919 14:00:15.370153 ===================================
3920 14:00:15.377010 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3921 14:00:15.380308 nWR fixed to 30
3922 14:00:15.380392 [ModeRegInit_LP4] CH0 RK0
3923 14:00:15.383827 [ModeRegInit_LP4] CH0 RK1
3924 14:00:15.386966 [ModeRegInit_LP4] CH1 RK0
3925 14:00:15.387045 [ModeRegInit_LP4] CH1 RK1
3926 14:00:15.390673 match AC timing 17
3927 14:00:15.393970 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3928 14:00:15.397072 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3929 14:00:15.403984 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3930 14:00:15.406983 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3931 14:00:15.413865 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3932 14:00:15.413948 ==
3933 14:00:15.417160 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 14:00:15.420411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 14:00:15.420492 ==
3936 14:00:15.427075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 14:00:15.430223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3938 14:00:15.434864 [CA 0] Center 36 (6~66) winsize 61
3939 14:00:15.437916 [CA 1] Center 36 (6~66) winsize 61
3940 14:00:15.441784 [CA 2] Center 34 (4~65) winsize 62
3941 14:00:15.445053 [CA 3] Center 34 (4~65) winsize 62
3942 14:00:15.448118 [CA 4] Center 34 (4~64) winsize 61
3943 14:00:15.451316 [CA 5] Center 33 (3~64) winsize 62
3944 14:00:15.451419
3945 14:00:15.454737 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3946 14:00:15.454814
3947 14:00:15.458380 [CATrainingPosCal] consider 1 rank data
3948 14:00:15.461411 u2DelayCellTimex100 = 270/100 ps
3949 14:00:15.464776 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3950 14:00:15.468060 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3951 14:00:15.475182 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 14:00:15.477909 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3953 14:00:15.481311 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3954 14:00:15.485053 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3955 14:00:15.485152
3956 14:00:15.488259 CA PerBit enable=1, Macro0, CA PI delay=33
3957 14:00:15.488359
3958 14:00:15.491351 [CBTSetCACLKResult] CA Dly = 33
3959 14:00:15.491446 CS Dly: 5 (0~36)
3960 14:00:15.491548 ==
3961 14:00:15.494886 Dram Type= 6, Freq= 0, CH_0, rank 1
3962 14:00:15.501709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 14:00:15.501809 ==
3964 14:00:15.504704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3965 14:00:15.511599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3966 14:00:15.514840 [CA 0] Center 36 (6~66) winsize 61
3967 14:00:15.518372 [CA 1] Center 36 (6~66) winsize 61
3968 14:00:15.522065 [CA 2] Center 34 (4~65) winsize 62
3969 14:00:15.524609 [CA 3] Center 34 (4~64) winsize 61
3970 14:00:15.527961 [CA 4] Center 33 (3~64) winsize 62
3971 14:00:15.531442 [CA 5] Center 33 (3~64) winsize 62
3972 14:00:15.531548
3973 14:00:15.534823 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3974 14:00:15.534897
3975 14:00:15.538147 [CATrainingPosCal] consider 2 rank data
3976 14:00:15.541448 u2DelayCellTimex100 = 270/100 ps
3977 14:00:15.544738 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3978 14:00:15.548275 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3979 14:00:15.554866 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3980 14:00:15.557984 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3981 14:00:15.561175 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3982 14:00:15.564911 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3983 14:00:15.565019
3984 14:00:15.567790 CA PerBit enable=1, Macro0, CA PI delay=33
3985 14:00:15.567863
3986 14:00:15.571736 [CBTSetCACLKResult] CA Dly = 33
3987 14:00:15.571827 CS Dly: 5 (0~36)
3988 14:00:15.571916
3989 14:00:15.574657 ----->DramcWriteLeveling(PI) begin...
3990 14:00:15.578052 ==
3991 14:00:15.581188 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 14:00:15.584566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 14:00:15.584663 ==
3994 14:00:15.588521 Write leveling (Byte 0): 33 => 33
3995 14:00:15.591390 Write leveling (Byte 1): 29 => 29
3996 14:00:15.594534 DramcWriteLeveling(PI) end<-----
3997 14:00:15.594609
3998 14:00:15.594673 ==
3999 14:00:15.598164 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 14:00:15.601198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 14:00:15.601294 ==
4002 14:00:15.604678 [Gating] SW mode calibration
4003 14:00:15.611453 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4004 14:00:15.614404 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4005 14:00:15.621727 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 14:00:15.624621 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 14:00:15.628050 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 14:00:15.634392 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4009 14:00:15.638065 0 9 16 | B1->B0 | 3131 2828 | 0 1 | (0 0) (1 1)
4010 14:00:15.641147 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 14:00:15.647954 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 14:00:15.651615 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 14:00:15.654880 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 14:00:15.661430 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 14:00:15.664687 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 14:00:15.667952 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 14:00:15.674703 0 10 16 | B1->B0 | 2d2d 3d3d | 1 1 | (0 0) (0 0)
4018 14:00:15.678470 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 14:00:15.681648 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 14:00:15.687740 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 14:00:15.691463 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 14:00:15.694850 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 14:00:15.701323 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 14:00:15.705200 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 14:00:15.708303 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4026 14:00:15.711426 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4027 14:00:15.718358 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 14:00:15.721461 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 14:00:15.725095 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 14:00:15.731828 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 14:00:15.734638 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 14:00:15.737942 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 14:00:15.745119 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 14:00:15.748002 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 14:00:15.751569 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 14:00:15.757859 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 14:00:15.761196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 14:00:15.764384 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 14:00:15.771479 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 14:00:15.774604 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4041 14:00:15.778194 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4042 14:00:15.784549 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 14:00:15.784651 Total UI for P1: 0, mck2ui 16
4044 14:00:15.791593 best dqsien dly found for B0: ( 0, 13, 14)
4045 14:00:15.791697 Total UI for P1: 0, mck2ui 16
4046 14:00:15.794323 best dqsien dly found for B1: ( 0, 13, 16)
4047 14:00:15.801004 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4048 14:00:15.804703 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4049 14:00:15.804783
4050 14:00:15.807983 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4051 14:00:15.812041 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4052 14:00:15.814860 [Gating] SW calibration Done
4053 14:00:15.814941 ==
4054 14:00:15.817704 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 14:00:15.821208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 14:00:15.821288 ==
4057 14:00:15.824504 RX Vref Scan: 0
4058 14:00:15.824584
4059 14:00:15.824646 RX Vref 0 -> 0, step: 1
4060 14:00:15.824708
4061 14:00:15.828410 RX Delay -230 -> 252, step: 16
4062 14:00:15.831097 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4063 14:00:15.837837 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4064 14:00:15.841348 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4065 14:00:15.845161 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4066 14:00:15.848230 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4067 14:00:15.851632 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4068 14:00:15.857977 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4069 14:00:15.861306 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4070 14:00:15.864908 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4071 14:00:15.868232 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4072 14:00:15.874586 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4073 14:00:15.878377 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4074 14:00:15.881357 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4075 14:00:15.884820 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4076 14:00:15.891333 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4077 14:00:15.894824 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4078 14:00:15.894904 ==
4079 14:00:15.898068 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 14:00:15.901438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 14:00:15.901519 ==
4082 14:00:15.901582 DQS Delay:
4083 14:00:15.905098 DQS0 = 0, DQS1 = 0
4084 14:00:15.905179 DQM Delay:
4085 14:00:15.908488 DQM0 = 40, DQM1 = 34
4086 14:00:15.908588 DQ Delay:
4087 14:00:15.911315 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4088 14:00:15.914790 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4089 14:00:15.918302 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4090 14:00:15.921477 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4091 14:00:15.921557
4092 14:00:15.921620
4093 14:00:15.921679 ==
4094 14:00:15.925103 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 14:00:15.928204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 14:00:15.928285 ==
4097 14:00:15.931882
4098 14:00:15.931977
4099 14:00:15.932068 TX Vref Scan disable
4100 14:00:15.935267 == TX Byte 0 ==
4101 14:00:15.938162 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4102 14:00:15.941918 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4103 14:00:15.944799 == TX Byte 1 ==
4104 14:00:15.948242 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4105 14:00:15.951768 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4106 14:00:15.951848 ==
4107 14:00:15.954920 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 14:00:15.961817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 14:00:15.961898 ==
4110 14:00:15.961961
4111 14:00:15.962019
4112 14:00:15.962075 TX Vref Scan disable
4113 14:00:15.966323 == TX Byte 0 ==
4114 14:00:15.969389 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4115 14:00:15.973001 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4116 14:00:15.976373 == TX Byte 1 ==
4117 14:00:15.979650 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4118 14:00:15.986635 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4119 14:00:15.986720
4120 14:00:15.986782 [DATLAT]
4121 14:00:15.986842 Freq=600, CH0 RK0
4122 14:00:15.986899
4123 14:00:15.989809 DATLAT Default: 0x9
4124 14:00:15.989888 0, 0xFFFF, sum = 0
4125 14:00:15.993364 1, 0xFFFF, sum = 0
4126 14:00:15.993445 2, 0xFFFF, sum = 0
4127 14:00:15.996066 3, 0xFFFF, sum = 0
4128 14:00:15.996146 4, 0xFFFF, sum = 0
4129 14:00:15.999512 5, 0xFFFF, sum = 0
4130 14:00:15.999610 6, 0xFFFF, sum = 0
4131 14:00:16.003209 7, 0xFFFF, sum = 0
4132 14:00:16.003295 8, 0x0, sum = 1
4133 14:00:16.006523 9, 0x0, sum = 2
4134 14:00:16.006604 10, 0x0, sum = 3
4135 14:00:16.009554 11, 0x0, sum = 4
4136 14:00:16.009636 best_step = 9
4137 14:00:16.009699
4138 14:00:16.009757 ==
4139 14:00:16.012848 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 14:00:16.019729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 14:00:16.019810 ==
4142 14:00:16.019873 RX Vref Scan: 1
4143 14:00:16.019932
4144 14:00:16.023097 RX Vref 0 -> 0, step: 1
4145 14:00:16.023176
4146 14:00:16.026028 RX Delay -179 -> 252, step: 8
4147 14:00:16.026135
4148 14:00:16.029457 Set Vref, RX VrefLevel [Byte0]: 54
4149 14:00:16.033017 [Byte1]: 51
4150 14:00:16.033098
4151 14:00:16.036387 Final RX Vref Byte 0 = 54 to rank0
4152 14:00:16.039409 Final RX Vref Byte 1 = 51 to rank0
4153 14:00:16.042891 Final RX Vref Byte 0 = 54 to rank1
4154 14:00:16.046979 Final RX Vref Byte 1 = 51 to rank1==
4155 14:00:16.049988 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 14:00:16.053296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 14:00:16.053376 ==
4158 14:00:16.056375 DQS Delay:
4159 14:00:16.056454 DQS0 = 0, DQS1 = 0
4160 14:00:16.056517 DQM Delay:
4161 14:00:16.059390 DQM0 = 42, DQM1 = 33
4162 14:00:16.059470 DQ Delay:
4163 14:00:16.062970 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4164 14:00:16.066346 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4165 14:00:16.070039 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4166 14:00:16.073359 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4167 14:00:16.073456
4168 14:00:16.073545
4169 14:00:16.082911 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4170 14:00:16.083013 CH0 RK0: MR19=808, MR18=3E1D
4171 14:00:16.089498 CH0_RK0: MR19=0x808, MR18=0x3E1D, DQSOSC=398, MR23=63, INC=165, DEC=110
4172 14:00:16.089580
4173 14:00:16.093260 ----->DramcWriteLeveling(PI) begin...
4174 14:00:16.093361 ==
4175 14:00:16.096420 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 14:00:16.102938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 14:00:16.103018 ==
4178 14:00:16.106150 Write leveling (Byte 0): 33 => 33
4179 14:00:16.109927 Write leveling (Byte 1): 33 => 33
4180 14:00:16.110028 DramcWriteLeveling(PI) end<-----
4181 14:00:16.113431
4182 14:00:16.113511 ==
4183 14:00:16.116312 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 14:00:16.119749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 14:00:16.119849 ==
4186 14:00:16.123279 [Gating] SW mode calibration
4187 14:00:16.129530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4188 14:00:16.132969 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4189 14:00:16.139979 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 14:00:16.142763 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 14:00:16.146937 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 14:00:16.152993 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4193 14:00:16.156359 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
4194 14:00:16.159580 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 14:00:16.166377 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 14:00:16.169731 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 14:00:16.172758 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 14:00:16.180064 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 14:00:16.183074 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 14:00:16.186645 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4201 14:00:16.192581 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4202 14:00:16.196021 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 14:00:16.199280 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 14:00:16.206095 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 14:00:16.209430 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 14:00:16.212717 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 14:00:16.216082 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 14:00:16.222839 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4209 14:00:16.226349 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4210 14:00:16.229716 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 14:00:16.236323 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 14:00:16.239223 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 14:00:16.242792 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 14:00:16.249578 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 14:00:16.252648 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 14:00:16.256483 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 14:00:16.262420 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 14:00:16.266316 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 14:00:16.269702 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 14:00:16.276379 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 14:00:16.279309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 14:00:16.282924 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 14:00:16.289380 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 14:00:16.292773 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4225 14:00:16.296169 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4226 14:00:16.299668 Total UI for P1: 0, mck2ui 16
4227 14:00:16.302789 best dqsien dly found for B0: ( 0, 13, 12)
4228 14:00:16.306319 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 14:00:16.309642 Total UI for P1: 0, mck2ui 16
4230 14:00:16.312982 best dqsien dly found for B1: ( 0, 13, 16)
4231 14:00:16.316318 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4232 14:00:16.323519 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4233 14:00:16.323614
4234 14:00:16.326314 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4235 14:00:16.329429 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4236 14:00:16.333214 [Gating] SW calibration Done
4237 14:00:16.333322 ==
4238 14:00:16.336566 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 14:00:16.339440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 14:00:16.339515 ==
4241 14:00:16.339585 RX Vref Scan: 0
4242 14:00:16.342928
4243 14:00:16.343005 RX Vref 0 -> 0, step: 1
4244 14:00:16.343067
4245 14:00:16.346540 RX Delay -230 -> 252, step: 16
4246 14:00:16.349716 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4247 14:00:16.356270 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4248 14:00:16.359276 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4249 14:00:16.362919 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4250 14:00:16.366554 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4251 14:00:16.369951 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4252 14:00:16.376293 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4253 14:00:16.379957 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4254 14:00:16.383446 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4255 14:00:16.386165 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4256 14:00:16.389510 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4257 14:00:16.396240 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4258 14:00:16.399862 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4259 14:00:16.403476 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4260 14:00:16.406596 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4261 14:00:16.412943 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4262 14:00:16.413046 ==
4263 14:00:16.416768 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 14:00:16.419446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 14:00:16.419547 ==
4266 14:00:16.419622 DQS Delay:
4267 14:00:16.422885 DQS0 = 0, DQS1 = 0
4268 14:00:16.422960 DQM Delay:
4269 14:00:16.426644 DQM0 = 39, DQM1 = 32
4270 14:00:16.426718 DQ Delay:
4271 14:00:16.429797 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4272 14:00:16.433375 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4273 14:00:16.436725 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4274 14:00:16.439855 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4275 14:00:16.439927
4276 14:00:16.439988
4277 14:00:16.440045 ==
4278 14:00:16.443093 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 14:00:16.446731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 14:00:16.446812 ==
4281 14:00:16.446924
4282 14:00:16.449550
4283 14:00:16.449629 TX Vref Scan disable
4284 14:00:16.452888 == TX Byte 0 ==
4285 14:00:16.456149 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4286 14:00:16.459481 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4287 14:00:16.463166 == TX Byte 1 ==
4288 14:00:16.466329 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4289 14:00:16.469754 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4290 14:00:16.469835 ==
4291 14:00:16.472879 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 14:00:16.479930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 14:00:16.480012 ==
4294 14:00:16.480075
4295 14:00:16.480133
4296 14:00:16.480189 TX Vref Scan disable
4297 14:00:16.483851 == TX Byte 0 ==
4298 14:00:16.487649 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4299 14:00:16.494304 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4300 14:00:16.494453 == TX Byte 1 ==
4301 14:00:16.497229 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4302 14:00:16.504338 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4303 14:00:16.504449
4304 14:00:16.504544 [DATLAT]
4305 14:00:16.504634 Freq=600, CH0 RK1
4306 14:00:16.504732
4307 14:00:16.507818 DATLAT Default: 0x9
4308 14:00:16.507926 0, 0xFFFF, sum = 0
4309 14:00:16.511368 1, 0xFFFF, sum = 0
4310 14:00:16.511470 2, 0xFFFF, sum = 0
4311 14:00:16.514482 3, 0xFFFF, sum = 0
4312 14:00:16.517410 4, 0xFFFF, sum = 0
4313 14:00:16.517515 5, 0xFFFF, sum = 0
4314 14:00:16.520649 6, 0xFFFF, sum = 0
4315 14:00:16.520751 7, 0xFFFF, sum = 0
4316 14:00:16.523775 8, 0x0, sum = 1
4317 14:00:16.523873 9, 0x0, sum = 2
4318 14:00:16.523975 10, 0x0, sum = 3
4319 14:00:16.527429 11, 0x0, sum = 4
4320 14:00:16.527537 best_step = 9
4321 14:00:16.527625
4322 14:00:16.527719 ==
4323 14:00:16.530968 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 14:00:16.537112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 14:00:16.537213 ==
4326 14:00:16.537311 RX Vref Scan: 0
4327 14:00:16.537400
4328 14:00:16.540515 RX Vref 0 -> 0, step: 1
4329 14:00:16.540623
4330 14:00:16.543849 RX Delay -195 -> 252, step: 8
4331 14:00:16.547059 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4332 14:00:16.553926 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4333 14:00:16.557169 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4334 14:00:16.560384 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4335 14:00:16.564578 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4336 14:00:16.567468 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4337 14:00:16.574240 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4338 14:00:16.577778 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4339 14:00:16.581043 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4340 14:00:16.584509 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4341 14:00:16.590666 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4342 14:00:16.594161 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4343 14:00:16.597491 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4344 14:00:16.600645 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4345 14:00:16.604384 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4346 14:00:16.611319 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4347 14:00:16.611398 ==
4348 14:00:16.614140 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 14:00:16.617423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 14:00:16.617527 ==
4351 14:00:16.617625 DQS Delay:
4352 14:00:16.621232 DQS0 = 0, DQS1 = 0
4353 14:00:16.621333 DQM Delay:
4354 14:00:16.624528 DQM0 = 39, DQM1 = 33
4355 14:00:16.624600 DQ Delay:
4356 14:00:16.627245 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4357 14:00:16.630642 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4358 14:00:16.634012 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =20
4359 14:00:16.637586 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4360 14:00:16.637663
4361 14:00:16.637753
4362 14:00:16.647725 [DQSOSCAuto] RK1, (LSB)MR18= 0x4627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4363 14:00:16.647807 CH0 RK1: MR19=808, MR18=4627
4364 14:00:16.653946 CH0_RK1: MR19=0x808, MR18=0x4627, DQSOSC=396, MR23=63, INC=167, DEC=111
4365 14:00:16.657217 [RxdqsGatingPostProcess] freq 600
4366 14:00:16.663774 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4367 14:00:16.667412 Pre-setting of DQS Precalculation
4368 14:00:16.670553 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4369 14:00:16.670632 ==
4370 14:00:16.674166 Dram Type= 6, Freq= 0, CH_1, rank 0
4371 14:00:16.677298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 14:00:16.677402 ==
4373 14:00:16.683869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4374 14:00:16.690405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4375 14:00:16.693877 [CA 0] Center 35 (5~66) winsize 62
4376 14:00:16.697334 [CA 1] Center 35 (5~65) winsize 61
4377 14:00:16.700598 [CA 2] Center 34 (4~65) winsize 62
4378 14:00:16.704453 [CA 3] Center 33 (3~64) winsize 62
4379 14:00:16.707781 [CA 4] Center 34 (3~65) winsize 63
4380 14:00:16.710788 [CA 5] Center 33 (2~64) winsize 63
4381 14:00:16.710868
4382 14:00:16.713939 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4383 14:00:16.714038
4384 14:00:16.717104 [CATrainingPosCal] consider 1 rank data
4385 14:00:16.720308 u2DelayCellTimex100 = 270/100 ps
4386 14:00:16.724220 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4387 14:00:16.727173 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4388 14:00:16.730764 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 14:00:16.733899 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 14:00:16.736997 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4391 14:00:16.744134 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4392 14:00:16.744236
4393 14:00:16.747483 CA PerBit enable=1, Macro0, CA PI delay=33
4394 14:00:16.747583
4395 14:00:16.750806 [CBTSetCACLKResult] CA Dly = 33
4396 14:00:16.750906 CS Dly: 4 (0~35)
4397 14:00:16.750999 ==
4398 14:00:16.754132 Dram Type= 6, Freq= 0, CH_1, rank 1
4399 14:00:16.757355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 14:00:16.757456 ==
4401 14:00:16.764113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4402 14:00:16.770760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4403 14:00:16.774114 [CA 0] Center 35 (5~66) winsize 62
4404 14:00:16.777710 [CA 1] Center 36 (6~66) winsize 61
4405 14:00:16.781111 [CA 2] Center 34 (4~65) winsize 62
4406 14:00:16.783816 [CA 3] Center 34 (3~65) winsize 63
4407 14:00:16.787393 [CA 4] Center 34 (3~65) winsize 63
4408 14:00:16.790939 [CA 5] Center 33 (3~64) winsize 62
4409 14:00:16.791019
4410 14:00:16.794313 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4411 14:00:16.794394
4412 14:00:16.797657 [CATrainingPosCal] consider 2 rank data
4413 14:00:16.801166 u2DelayCellTimex100 = 270/100 ps
4414 14:00:16.803857 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4415 14:00:16.807259 CA1 delay=35 (6~65),Diff = 2 PI (19 cell)
4416 14:00:16.810788 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4417 14:00:16.813978 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 14:00:16.817449 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4419 14:00:16.824302 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 14:00:16.824384
4421 14:00:16.827209 CA PerBit enable=1, Macro0, CA PI delay=33
4422 14:00:16.827290
4423 14:00:16.830844 [CBTSetCACLKResult] CA Dly = 33
4424 14:00:16.830924 CS Dly: 4 (0~35)
4425 14:00:16.830988
4426 14:00:16.834018 ----->DramcWriteLeveling(PI) begin...
4427 14:00:16.834099 ==
4428 14:00:16.837334 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 14:00:16.843608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 14:00:16.843690 ==
4431 14:00:16.847293 Write leveling (Byte 0): 30 => 30
4432 14:00:16.847374 Write leveling (Byte 1): 30 => 30
4433 14:00:16.850530 DramcWriteLeveling(PI) end<-----
4434 14:00:16.850610
4435 14:00:16.850673 ==
4436 14:00:16.853785 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 14:00:16.860379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 14:00:16.860492 ==
4439 14:00:16.863493 [Gating] SW mode calibration
4440 14:00:16.870622 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4441 14:00:16.873489 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4442 14:00:16.880189 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4443 14:00:16.883374 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 14:00:16.887106 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 14:00:16.893991 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (0 1)
4446 14:00:16.896959 0 9 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4447 14:00:16.900489 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 14:00:16.906768 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4449 14:00:16.910353 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 14:00:16.913845 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 14:00:16.920055 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4452 14:00:16.923767 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 14:00:16.926998 0 10 12 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
4454 14:00:16.930325 0 10 16 | B1->B0 | 3d3d 4040 | 0 0 | (0 0) (0 0)
4455 14:00:16.936720 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 14:00:16.940376 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 14:00:16.943510 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 14:00:16.950114 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 14:00:16.953408 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 14:00:16.956939 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 14:00:16.963656 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 14:00:16.966641 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 14:00:16.970271 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 14:00:16.976437 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 14:00:16.980036 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 14:00:16.983181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 14:00:16.989796 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 14:00:16.993092 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 14:00:16.996978 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 14:00:17.003282 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 14:00:17.006824 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 14:00:17.009629 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 14:00:17.016491 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 14:00:17.019967 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 14:00:17.023623 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 14:00:17.030147 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 14:00:17.033520 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4478 14:00:17.036718 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4479 14:00:17.039864 Total UI for P1: 0, mck2ui 16
4480 14:00:17.043316 best dqsien dly found for B1: ( 0, 13, 12)
4481 14:00:17.046766 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 14:00:17.049945 Total UI for P1: 0, mck2ui 16
4483 14:00:17.053296 best dqsien dly found for B0: ( 0, 13, 14)
4484 14:00:17.056436 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4485 14:00:17.064159 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4486 14:00:17.064241
4487 14:00:17.066545 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4488 14:00:17.069971 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4489 14:00:17.073007 [Gating] SW calibration Done
4490 14:00:17.073099 ==
4491 14:00:17.076333 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 14:00:17.079724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 14:00:17.079808 ==
4494 14:00:17.083013 RX Vref Scan: 0
4495 14:00:17.083092
4496 14:00:17.083153 RX Vref 0 -> 0, step: 1
4497 14:00:17.083211
4498 14:00:17.086212 RX Delay -230 -> 252, step: 16
4499 14:00:17.089517 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4500 14:00:17.096372 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4501 14:00:17.100254 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4502 14:00:17.102881 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4503 14:00:17.106575 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4504 14:00:17.109493 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4505 14:00:17.116278 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4506 14:00:17.119739 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4507 14:00:17.122923 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4508 14:00:17.126355 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4509 14:00:17.133287 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4510 14:00:17.136237 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4511 14:00:17.140345 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4512 14:00:17.142941 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4513 14:00:17.149667 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4514 14:00:17.153059 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4515 14:00:17.153159 ==
4516 14:00:17.156375 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 14:00:17.159694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 14:00:17.159794 ==
4519 14:00:17.162998 DQS Delay:
4520 14:00:17.163073 DQS0 = 0, DQS1 = 0
4521 14:00:17.163135 DQM Delay:
4522 14:00:17.166709 DQM0 = 44, DQM1 = 35
4523 14:00:17.166777 DQ Delay:
4524 14:00:17.170015 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4525 14:00:17.172982 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4526 14:00:17.176210 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4527 14:00:17.179604 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4528 14:00:17.179678
4529 14:00:17.179743
4530 14:00:17.179801 ==
4531 14:00:17.182946 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 14:00:17.186164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 14:00:17.189847 ==
4534 14:00:17.189943
4535 14:00:17.190032
4536 14:00:17.190117 TX Vref Scan disable
4537 14:00:17.192839 == TX Byte 0 ==
4538 14:00:17.195933 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 14:00:17.203189 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 14:00:17.203292 == TX Byte 1 ==
4541 14:00:17.206194 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 14:00:17.209678 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 14:00:17.213174 ==
4544 14:00:17.216421 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 14:00:17.219522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 14:00:17.219597 ==
4547 14:00:17.219685
4548 14:00:17.219774
4549 14:00:17.222829 TX Vref Scan disable
4550 14:00:17.222899 == TX Byte 0 ==
4551 14:00:17.229686 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4552 14:00:17.232638 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4553 14:00:17.232712 == TX Byte 1 ==
4554 14:00:17.239299 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4555 14:00:17.242792 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4556 14:00:17.242863
4557 14:00:17.242923 [DATLAT]
4558 14:00:17.246084 Freq=600, CH1 RK0
4559 14:00:17.246178
4560 14:00:17.246264 DATLAT Default: 0x9
4561 14:00:17.249746 0, 0xFFFF, sum = 0
4562 14:00:17.249824 1, 0xFFFF, sum = 0
4563 14:00:17.252473 2, 0xFFFF, sum = 0
4564 14:00:17.252571 3, 0xFFFF, sum = 0
4565 14:00:17.256155 4, 0xFFFF, sum = 0
4566 14:00:17.259542 5, 0xFFFF, sum = 0
4567 14:00:17.259645 6, 0xFFFF, sum = 0
4568 14:00:17.262810 7, 0xFFFF, sum = 0
4569 14:00:17.262886 8, 0x0, sum = 1
4570 14:00:17.262949 9, 0x0, sum = 2
4571 14:00:17.266324 10, 0x0, sum = 3
4572 14:00:17.266402 11, 0x0, sum = 4
4573 14:00:17.269359 best_step = 9
4574 14:00:17.269432
4575 14:00:17.269493 ==
4576 14:00:17.272629 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 14:00:17.275827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 14:00:17.275901 ==
4579 14:00:17.279657 RX Vref Scan: 1
4580 14:00:17.279729
4581 14:00:17.279793 RX Vref 0 -> 0, step: 1
4582 14:00:17.279853
4583 14:00:17.282729 RX Delay -195 -> 252, step: 8
4584 14:00:17.282804
4585 14:00:17.286082 Set Vref, RX VrefLevel [Byte0]: 56
4586 14:00:17.289147 [Byte1]: 52
4587 14:00:17.293051
4588 14:00:17.293161 Final RX Vref Byte 0 = 56 to rank0
4589 14:00:17.296581 Final RX Vref Byte 1 = 52 to rank0
4590 14:00:17.299658 Final RX Vref Byte 0 = 56 to rank1
4591 14:00:17.303240 Final RX Vref Byte 1 = 52 to rank1==
4592 14:00:17.306784 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 14:00:17.309891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 14:00:17.313436 ==
4595 14:00:17.313512 DQS Delay:
4596 14:00:17.313575 DQS0 = 0, DQS1 = 0
4597 14:00:17.316462 DQM Delay:
4598 14:00:17.316564 DQM0 = 40, DQM1 = 33
4599 14:00:17.320102 DQ Delay:
4600 14:00:17.324045 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4601 14:00:17.324149 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4602 14:00:17.326480 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4603 14:00:17.330025 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4604 14:00:17.333280
4605 14:00:17.333390
4606 14:00:17.340179 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e03, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4607 14:00:17.343325 CH1 RK0: MR19=808, MR18=3E03
4608 14:00:17.349689 CH1_RK0: MR19=0x808, MR18=0x3E03, DQSOSC=398, MR23=63, INC=165, DEC=110
4609 14:00:17.349792
4610 14:00:17.353221 ----->DramcWriteLeveling(PI) begin...
4611 14:00:17.353321 ==
4612 14:00:17.356575 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 14:00:17.359926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 14:00:17.360003 ==
4615 14:00:17.363353 Write leveling (Byte 0): 31 => 31
4616 14:00:17.366736 Write leveling (Byte 1): 31 => 31
4617 14:00:17.370042 DramcWriteLeveling(PI) end<-----
4618 14:00:17.370115
4619 14:00:17.370176 ==
4620 14:00:17.372809 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 14:00:17.376523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 14:00:17.376599 ==
4623 14:00:17.380336 [Gating] SW mode calibration
4624 14:00:17.387080 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4625 14:00:17.393523 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4626 14:00:17.397057 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4627 14:00:17.399913 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 14:00:17.406388 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 14:00:17.409803 0 9 12 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (1 1)
4630 14:00:17.413123 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 14:00:17.419572 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 14:00:17.422947 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4633 14:00:17.426493 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4634 14:00:17.432817 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 14:00:17.436659 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 14:00:17.440030 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4637 14:00:17.446309 0 10 12 | B1->B0 | 302f 4444 | 1 0 | (1 1) (0 0)
4638 14:00:17.449588 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4639 14:00:17.453396 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 14:00:17.459715 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 14:00:17.463138 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 14:00:17.466411 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 14:00:17.472820 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 14:00:17.476364 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4645 14:00:17.479957 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4646 14:00:17.483003 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 14:00:17.489732 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 14:00:17.493167 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 14:00:17.496478 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 14:00:17.503320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 14:00:17.506393 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 14:00:17.510328 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 14:00:17.517091 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 14:00:17.519654 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 14:00:17.522997 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 14:00:17.530030 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 14:00:17.533168 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 14:00:17.536300 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 14:00:17.542753 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 14:00:17.546359 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4661 14:00:17.549729 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4662 14:00:17.556521 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 14:00:17.556625 Total UI for P1: 0, mck2ui 16
4664 14:00:17.563274 best dqsien dly found for B0: ( 0, 13, 10)
4665 14:00:17.563379 Total UI for P1: 0, mck2ui 16
4666 14:00:17.566196 best dqsien dly found for B1: ( 0, 13, 12)
4667 14:00:17.573114 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4668 14:00:17.576169 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4669 14:00:17.576280
4670 14:00:17.579648 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4671 14:00:17.582994 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4672 14:00:17.586714 [Gating] SW calibration Done
4673 14:00:17.586789 ==
4674 14:00:17.589506 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 14:00:17.593237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 14:00:17.593336 ==
4677 14:00:17.596007 RX Vref Scan: 0
4678 14:00:17.596106
4679 14:00:17.596194 RX Vref 0 -> 0, step: 1
4680 14:00:17.596294
4681 14:00:17.599308 RX Delay -230 -> 252, step: 16
4682 14:00:17.602934 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4683 14:00:17.609646 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4684 14:00:17.612753 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4685 14:00:17.616154 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4686 14:00:17.619481 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4687 14:00:17.626251 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4688 14:00:17.629301 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4689 14:00:17.632459 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4690 14:00:17.636003 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4691 14:00:17.639676 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4692 14:00:17.645970 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4693 14:00:17.649908 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4694 14:00:17.652971 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4695 14:00:17.656218 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4696 14:00:17.662825 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4697 14:00:17.665808 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4698 14:00:17.665892 ==
4699 14:00:17.669813 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 14:00:17.673499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 14:00:17.673593 ==
4702 14:00:17.676133 DQS Delay:
4703 14:00:17.676231 DQS0 = 0, DQS1 = 0
4704 14:00:17.676319 DQM Delay:
4705 14:00:17.679468 DQM0 = 40, DQM1 = 34
4706 14:00:17.679550 DQ Delay:
4707 14:00:17.682839 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4708 14:00:17.685944 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4709 14:00:17.689952 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4710 14:00:17.693028 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4711 14:00:17.693109
4712 14:00:17.693171
4713 14:00:17.693229 ==
4714 14:00:17.695893 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 14:00:17.702976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 14:00:17.703057 ==
4717 14:00:17.703121
4718 14:00:17.703179
4719 14:00:17.703235 TX Vref Scan disable
4720 14:00:17.706433 == TX Byte 0 ==
4721 14:00:17.709978 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 14:00:17.713367 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 14:00:17.716051 == TX Byte 1 ==
4724 14:00:17.719360 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4725 14:00:17.723216 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4726 14:00:17.726720 ==
4727 14:00:17.729489 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 14:00:17.733293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 14:00:17.733374 ==
4730 14:00:17.733436
4731 14:00:17.733494
4732 14:00:17.735993 TX Vref Scan disable
4733 14:00:17.736072 == TX Byte 0 ==
4734 14:00:17.742721 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4735 14:00:17.746062 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4736 14:00:17.746167 == TX Byte 1 ==
4737 14:00:17.752935 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4738 14:00:17.756471 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4739 14:00:17.756551
4740 14:00:17.756615 [DATLAT]
4741 14:00:17.759725 Freq=600, CH1 RK1
4742 14:00:17.759805
4743 14:00:17.759867 DATLAT Default: 0x9
4744 14:00:17.763240 0, 0xFFFF, sum = 0
4745 14:00:17.763321 1, 0xFFFF, sum = 0
4746 14:00:17.765951 2, 0xFFFF, sum = 0
4747 14:00:17.766032 3, 0xFFFF, sum = 0
4748 14:00:17.769476 4, 0xFFFF, sum = 0
4749 14:00:17.773370 5, 0xFFFF, sum = 0
4750 14:00:17.773452 6, 0xFFFF, sum = 0
4751 14:00:17.776337 7, 0xFFFF, sum = 0
4752 14:00:17.776425 8, 0x0, sum = 1
4753 14:00:17.776490 9, 0x0, sum = 2
4754 14:00:17.779371 10, 0x0, sum = 3
4755 14:00:17.779452 11, 0x0, sum = 4
4756 14:00:17.782821 best_step = 9
4757 14:00:17.782900
4758 14:00:17.782962 ==
4759 14:00:17.786361 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 14:00:17.790065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 14:00:17.790145 ==
4762 14:00:17.793670 RX Vref Scan: 0
4763 14:00:17.793750
4764 14:00:17.793812 RX Vref 0 -> 0, step: 1
4765 14:00:17.793871
4766 14:00:17.796200 RX Delay -195 -> 252, step: 8
4767 14:00:17.803509 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4768 14:00:17.807041 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4769 14:00:17.810366 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4770 14:00:17.813614 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4771 14:00:17.820389 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4772 14:00:17.823644 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4773 14:00:17.826900 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4774 14:00:17.829961 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4775 14:00:17.833223 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4776 14:00:17.840345 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4777 14:00:17.843453 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4778 14:00:17.846990 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4779 14:00:17.850321 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4780 14:00:17.856469 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4781 14:00:17.859858 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4782 14:00:17.863380 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4783 14:00:17.863461 ==
4784 14:00:17.866507 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 14:00:17.869781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 14:00:17.869861 ==
4787 14:00:17.873311 DQS Delay:
4788 14:00:17.873390 DQS0 = 0, DQS1 = 0
4789 14:00:17.876634 DQM Delay:
4790 14:00:17.876714 DQM0 = 38, DQM1 = 33
4791 14:00:17.876777 DQ Delay:
4792 14:00:17.880049 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4793 14:00:17.883856 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4794 14:00:17.886533 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4795 14:00:17.889965 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4796 14:00:17.890045
4797 14:00:17.890107
4798 14:00:17.900222 [DQSOSCAuto] RK1, (LSB)MR18= 0x3543, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
4799 14:00:17.903538 CH1 RK1: MR19=808, MR18=3543
4800 14:00:17.909952 CH1_RK1: MR19=0x808, MR18=0x3543, DQSOSC=397, MR23=63, INC=166, DEC=110
4801 14:00:17.910049 [RxdqsGatingPostProcess] freq 600
4802 14:00:17.916998 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4803 14:00:17.919770 Pre-setting of DQS Precalculation
4804 14:00:17.924346 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4805 14:00:17.933022 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4806 14:00:17.940164 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4807 14:00:17.940237
4808 14:00:17.940302
4809 14:00:17.943076 [Calibration Summary] 1200 Mbps
4810 14:00:17.943142 CH 0, Rank 0
4811 14:00:17.946282 SW Impedance : PASS
4812 14:00:17.946377 DUTY Scan : NO K
4813 14:00:17.950308 ZQ Calibration : PASS
4814 14:00:17.952954 Jitter Meter : NO K
4815 14:00:17.953021 CBT Training : PASS
4816 14:00:17.956506 Write leveling : PASS
4817 14:00:17.959829 RX DQS gating : PASS
4818 14:00:17.959896 RX DQ/DQS(RDDQC) : PASS
4819 14:00:17.963556 TX DQ/DQS : PASS
4820 14:00:17.966415 RX DATLAT : PASS
4821 14:00:17.966511 RX DQ/DQS(Engine): PASS
4822 14:00:17.969876 TX OE : NO K
4823 14:00:17.969942 All Pass.
4824 14:00:17.970004
4825 14:00:17.973126 CH 0, Rank 1
4826 14:00:17.973202 SW Impedance : PASS
4827 14:00:17.976753 DUTY Scan : NO K
4828 14:00:17.976827 ZQ Calibration : PASS
4829 14:00:17.980217 Jitter Meter : NO K
4830 14:00:17.983751 CBT Training : PASS
4831 14:00:17.983819 Write leveling : PASS
4832 14:00:17.986747 RX DQS gating : PASS
4833 14:00:17.989826 RX DQ/DQS(RDDQC) : PASS
4834 14:00:17.989926 TX DQ/DQS : PASS
4835 14:00:17.993604 RX DATLAT : PASS
4836 14:00:17.996488 RX DQ/DQS(Engine): PASS
4837 14:00:17.996557 TX OE : NO K
4838 14:00:18.000109 All Pass.
4839 14:00:18.000177
4840 14:00:18.000235 CH 1, Rank 0
4841 14:00:18.003042 SW Impedance : PASS
4842 14:00:18.003139 DUTY Scan : NO K
4843 14:00:18.006815 ZQ Calibration : PASS
4844 14:00:18.010338 Jitter Meter : NO K
4845 14:00:18.010482 CBT Training : PASS
4846 14:00:18.012963 Write leveling : PASS
4847 14:00:18.016450 RX DQS gating : PASS
4848 14:00:18.016543 RX DQ/DQS(RDDQC) : PASS
4849 14:00:18.019922 TX DQ/DQS : PASS
4850 14:00:18.019996 RX DATLAT : PASS
4851 14:00:18.023306 RX DQ/DQS(Engine): PASS
4852 14:00:18.026692 TX OE : NO K
4853 14:00:18.026766 All Pass.
4854 14:00:18.026830
4855 14:00:18.026890 CH 1, Rank 1
4856 14:00:18.030104 SW Impedance : PASS
4857 14:00:18.034230 DUTY Scan : NO K
4858 14:00:18.034330 ZQ Calibration : PASS
4859 14:00:18.036535 Jitter Meter : NO K
4860 14:00:18.040405 CBT Training : PASS
4861 14:00:18.040504 Write leveling : PASS
4862 14:00:18.043477 RX DQS gating : PASS
4863 14:00:18.046551 RX DQ/DQS(RDDQC) : PASS
4864 14:00:18.046631 TX DQ/DQS : PASS
4865 14:00:18.049995 RX DATLAT : PASS
4866 14:00:18.053307 RX DQ/DQS(Engine): PASS
4867 14:00:18.053375 TX OE : NO K
4868 14:00:18.053439 All Pass.
4869 14:00:18.056758
4870 14:00:18.056825 DramC Write-DBI off
4871 14:00:18.059678 PER_BANK_REFRESH: Hybrid Mode
4872 14:00:18.059754 TX_TRACKING: ON
4873 14:00:18.070175 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4874 14:00:18.073068 [FAST_K] Save calibration result to emmc
4875 14:00:18.077156 dramc_set_vcore_voltage set vcore to 662500
4876 14:00:18.079646 Read voltage for 933, 3
4877 14:00:18.079718 Vio18 = 0
4878 14:00:18.083190 Vcore = 662500
4879 14:00:18.083260 Vdram = 0
4880 14:00:18.083319 Vddq = 0
4881 14:00:18.083375 Vmddr = 0
4882 14:00:18.090066 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4883 14:00:18.093520 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4884 14:00:18.096269 MEM_TYPE=3, freq_sel=17
4885 14:00:18.100200 sv_algorithm_assistance_LP4_1600
4886 14:00:18.103362 ============ PULL DRAM RESETB DOWN ============
4887 14:00:18.109797 ========== PULL DRAM RESETB DOWN end =========
4888 14:00:18.113396 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4889 14:00:18.116407 ===================================
4890 14:00:18.119630 LPDDR4 DRAM CONFIGURATION
4891 14:00:18.123671 ===================================
4892 14:00:18.123742 EX_ROW_EN[0] = 0x0
4893 14:00:18.126432 EX_ROW_EN[1] = 0x0
4894 14:00:18.126522 LP4Y_EN = 0x0
4895 14:00:18.129720 WORK_FSP = 0x0
4896 14:00:18.129787 WL = 0x3
4897 14:00:18.133077 RL = 0x3
4898 14:00:18.133143 BL = 0x2
4899 14:00:18.136628 RPST = 0x0
4900 14:00:18.136700 RD_PRE = 0x0
4901 14:00:18.139917 WR_PRE = 0x1
4902 14:00:18.139989 WR_PST = 0x0
4903 14:00:18.143386 DBI_WR = 0x0
4904 14:00:18.143453 DBI_RD = 0x0
4905 14:00:18.147196 OTF = 0x1
4906 14:00:18.149824 ===================================
4907 14:00:18.154260 ===================================
4908 14:00:18.154326 ANA top config
4909 14:00:18.156695 ===================================
4910 14:00:18.160122 DLL_ASYNC_EN = 0
4911 14:00:18.163079 ALL_SLAVE_EN = 1
4912 14:00:18.166385 NEW_RANK_MODE = 1
4913 14:00:18.166496 DLL_IDLE_MODE = 1
4914 14:00:18.169782 LP45_APHY_COMB_EN = 1
4915 14:00:18.173237 TX_ODT_DIS = 1
4916 14:00:18.177004 NEW_8X_MODE = 1
4917 14:00:18.180123 ===================================
4918 14:00:18.183602 ===================================
4919 14:00:18.187020 data_rate = 1866
4920 14:00:18.187088 CKR = 1
4921 14:00:18.189897 DQ_P2S_RATIO = 8
4922 14:00:18.193406 ===================================
4923 14:00:18.197076 CA_P2S_RATIO = 8
4924 14:00:18.199884 DQ_CA_OPEN = 0
4925 14:00:18.203193 DQ_SEMI_OPEN = 0
4926 14:00:18.207039 CA_SEMI_OPEN = 0
4927 14:00:18.207113 CA_FULL_RATE = 0
4928 14:00:18.209985 DQ_CKDIV4_EN = 1
4929 14:00:18.213133 CA_CKDIV4_EN = 1
4930 14:00:18.216543 CA_PREDIV_EN = 0
4931 14:00:18.219803 PH8_DLY = 0
4932 14:00:18.223038 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4933 14:00:18.223109 DQ_AAMCK_DIV = 4
4934 14:00:18.226349 CA_AAMCK_DIV = 4
4935 14:00:18.229860 CA_ADMCK_DIV = 4
4936 14:00:18.233140 DQ_TRACK_CA_EN = 0
4937 14:00:18.236587 CA_PICK = 933
4938 14:00:18.240284 CA_MCKIO = 933
4939 14:00:18.240383 MCKIO_SEMI = 0
4940 14:00:18.243040 PLL_FREQ = 3732
4941 14:00:18.246253 DQ_UI_PI_RATIO = 32
4942 14:00:18.249828 CA_UI_PI_RATIO = 0
4943 14:00:18.252996 ===================================
4944 14:00:18.256720 ===================================
4945 14:00:18.260643 memory_type:LPDDR4
4946 14:00:18.260754 GP_NUM : 10
4947 14:00:18.263515 SRAM_EN : 1
4948 14:00:18.266403 MD32_EN : 0
4949 14:00:18.269887 ===================================
4950 14:00:18.269985 [ANA_INIT] >>>>>>>>>>>>>>
4951 14:00:18.273312 <<<<<< [CONFIGURE PHASE]: ANA_TX
4952 14:00:18.276221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4953 14:00:18.279797 ===================================
4954 14:00:18.283286 data_rate = 1866,PCW = 0X8f00
4955 14:00:18.286309 ===================================
4956 14:00:18.289823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4957 14:00:18.296370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 14:00:18.299349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 14:00:18.306333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4960 14:00:18.309640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4961 14:00:18.313364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4962 14:00:18.313472 [ANA_INIT] flow start
4963 14:00:18.316284 [ANA_INIT] PLL >>>>>>>>
4964 14:00:18.319734 [ANA_INIT] PLL <<<<<<<<
4965 14:00:18.323160 [ANA_INIT] MIDPI >>>>>>>>
4966 14:00:18.323232 [ANA_INIT] MIDPI <<<<<<<<
4967 14:00:18.326517 [ANA_INIT] DLL >>>>>>>>
4968 14:00:18.326596 [ANA_INIT] flow end
4969 14:00:18.333038 ============ LP4 DIFF to SE enter ============
4970 14:00:18.336506 ============ LP4 DIFF to SE exit ============
4971 14:00:18.339497 [ANA_INIT] <<<<<<<<<<<<<
4972 14:00:18.342773 [Flow] Enable top DCM control >>>>>
4973 14:00:18.346102 [Flow] Enable top DCM control <<<<<
4974 14:00:18.349330 Enable DLL master slave shuffle
4975 14:00:18.353189 ==============================================================
4976 14:00:18.356559 Gating Mode config
4977 14:00:18.359677 ==============================================================
4978 14:00:18.362938 Config description:
4979 14:00:18.372828 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4980 14:00:18.379541 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4981 14:00:18.383361 SELPH_MODE 0: By rank 1: By Phase
4982 14:00:18.389494 ==============================================================
4983 14:00:18.392931 GAT_TRACK_EN = 1
4984 14:00:18.396422 RX_GATING_MODE = 2
4985 14:00:18.399458 RX_GATING_TRACK_MODE = 2
4986 14:00:18.402881 SELPH_MODE = 1
4987 14:00:18.405971 PICG_EARLY_EN = 1
4988 14:00:18.406044 VALID_LAT_VALUE = 1
4989 14:00:18.412371 ==============================================================
4990 14:00:18.415990 Enter into Gating configuration >>>>
4991 14:00:18.419290 Exit from Gating configuration <<<<
4992 14:00:18.422712 Enter into DVFS_PRE_config >>>>>
4993 14:00:18.432809 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4994 14:00:18.436552 Exit from DVFS_PRE_config <<<<<
4995 14:00:18.439901 Enter into PICG configuration >>>>
4996 14:00:18.443041 Exit from PICG configuration <<<<
4997 14:00:18.446197 [RX_INPUT] configuration >>>>>
4998 14:00:18.449395 [RX_INPUT] configuration <<<<<
4999 14:00:18.452747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5000 14:00:18.459601 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5001 14:00:18.465859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 14:00:18.472780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 14:00:18.479085 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5004 14:00:18.482557 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5005 14:00:18.489530 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5006 14:00:18.492661 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5007 14:00:18.495636 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5008 14:00:18.498946 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5009 14:00:18.506298 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5010 14:00:18.509247 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 14:00:18.513016 ===================================
5012 14:00:18.515814 LPDDR4 DRAM CONFIGURATION
5013 14:00:18.519431 ===================================
5014 14:00:18.519503 EX_ROW_EN[0] = 0x0
5015 14:00:18.522405 EX_ROW_EN[1] = 0x0
5016 14:00:18.522508 LP4Y_EN = 0x0
5017 14:00:18.526270 WORK_FSP = 0x0
5018 14:00:18.526343 WL = 0x3
5019 14:00:18.529159 RL = 0x3
5020 14:00:18.529234 BL = 0x2
5021 14:00:18.532468 RPST = 0x0
5022 14:00:18.532538 RD_PRE = 0x0
5023 14:00:18.536010 WR_PRE = 0x1
5024 14:00:18.536078 WR_PST = 0x0
5025 14:00:18.539509 DBI_WR = 0x0
5026 14:00:18.539579 DBI_RD = 0x0
5027 14:00:18.543029 OTF = 0x1
5028 14:00:18.545889 ===================================
5029 14:00:18.549354 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5030 14:00:18.553211 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5031 14:00:18.559174 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 14:00:18.562894 ===================================
5033 14:00:18.562962 LPDDR4 DRAM CONFIGURATION
5034 14:00:18.565916 ===================================
5035 14:00:18.569833 EX_ROW_EN[0] = 0x10
5036 14:00:18.572674 EX_ROW_EN[1] = 0x0
5037 14:00:18.572765 LP4Y_EN = 0x0
5038 14:00:18.576271 WORK_FSP = 0x0
5039 14:00:18.576368 WL = 0x3
5040 14:00:18.579609 RL = 0x3
5041 14:00:18.579710 BL = 0x2
5042 14:00:18.583031 RPST = 0x0
5043 14:00:18.583127 RD_PRE = 0x0
5044 14:00:18.585962 WR_PRE = 0x1
5045 14:00:18.586031 WR_PST = 0x0
5046 14:00:18.589552 DBI_WR = 0x0
5047 14:00:18.589620 DBI_RD = 0x0
5048 14:00:18.592773 OTF = 0x1
5049 14:00:18.596628 ===================================
5050 14:00:18.602916 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5051 14:00:18.606197 nWR fixed to 30
5052 14:00:18.606302 [ModeRegInit_LP4] CH0 RK0
5053 14:00:18.609406 [ModeRegInit_LP4] CH0 RK1
5054 14:00:18.612947 [ModeRegInit_LP4] CH1 RK0
5055 14:00:18.615989 [ModeRegInit_LP4] CH1 RK1
5056 14:00:18.616091 match AC timing 9
5057 14:00:18.619360 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5058 14:00:18.623018 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5059 14:00:18.629632 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5060 14:00:18.632506 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5061 14:00:18.639447 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5062 14:00:18.639521 ==
5063 14:00:18.642839 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 14:00:18.646331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 14:00:18.646431 ==
5066 14:00:18.652928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 14:00:18.655845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5068 14:00:18.660924 [CA 0] Center 38 (8~69) winsize 62
5069 14:00:18.663613 [CA 1] Center 38 (7~69) winsize 63
5070 14:00:18.667331 [CA 2] Center 35 (5~66) winsize 62
5071 14:00:18.670221 [CA 3] Center 34 (4~65) winsize 62
5072 14:00:18.673633 [CA 4] Center 34 (4~65) winsize 62
5073 14:00:18.676839 [CA 5] Center 34 (4~64) winsize 61
5074 14:00:18.676936
5075 14:00:18.680244 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5076 14:00:18.680316
5077 14:00:18.683539 [CATrainingPosCal] consider 1 rank data
5078 14:00:18.686952 u2DelayCellTimex100 = 270/100 ps
5079 14:00:18.690593 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 14:00:18.693769 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5081 14:00:18.700172 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5082 14:00:18.703442 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 14:00:18.706827 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5084 14:00:18.710482 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 14:00:18.710583
5086 14:00:18.714367 CA PerBit enable=1, Macro0, CA PI delay=34
5087 14:00:18.714487
5088 14:00:18.716908 [CBTSetCACLKResult] CA Dly = 34
5089 14:00:18.717014 CS Dly: 6 (0~37)
5090 14:00:18.720296 ==
5091 14:00:18.720398 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 14:00:18.726595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 14:00:18.726697 ==
5094 14:00:18.730300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 14:00:18.736524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5096 14:00:18.740174 [CA 0] Center 38 (8~69) winsize 62
5097 14:00:18.743765 [CA 1] Center 38 (8~69) winsize 62
5098 14:00:18.747198 [CA 2] Center 35 (5~66) winsize 62
5099 14:00:18.750311 [CA 3] Center 35 (5~66) winsize 62
5100 14:00:18.753962 [CA 4] Center 34 (4~65) winsize 62
5101 14:00:18.756971 [CA 5] Center 33 (3~64) winsize 62
5102 14:00:18.757045
5103 14:00:18.760305 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5104 14:00:18.760377
5105 14:00:18.763729 [CATrainingPosCal] consider 2 rank data
5106 14:00:18.766754 u2DelayCellTimex100 = 270/100 ps
5107 14:00:18.770642 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5108 14:00:18.774158 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5109 14:00:18.780326 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5110 14:00:18.783873 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5111 14:00:18.787276 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5112 14:00:18.790704 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5113 14:00:18.790777
5114 14:00:18.793680 CA PerBit enable=1, Macro0, CA PI delay=34
5115 14:00:18.793751
5116 14:00:18.797063 [CBTSetCACLKResult] CA Dly = 34
5117 14:00:18.797135 CS Dly: 7 (0~39)
5118 14:00:18.797231
5119 14:00:18.800445 ----->DramcWriteLeveling(PI) begin...
5120 14:00:18.803779 ==
5121 14:00:18.803880 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 14:00:18.810205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 14:00:18.810283 ==
5124 14:00:18.813454 Write leveling (Byte 0): 29 => 29
5125 14:00:18.817086 Write leveling (Byte 1): 29 => 29
5126 14:00:18.820196 DramcWriteLeveling(PI) end<-----
5127 14:00:18.820271
5128 14:00:18.820349 ==
5129 14:00:18.823826 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 14:00:18.827160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 14:00:18.827243 ==
5132 14:00:18.830315 [Gating] SW mode calibration
5133 14:00:18.837418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5134 14:00:18.840524 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5135 14:00:18.847000 0 14 0 | B1->B0 | 2424 2f2f | 1 1 | (1 1) (0 0)
5136 14:00:18.850710 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5137 14:00:18.853528 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 14:00:18.860094 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 14:00:18.863498 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 14:00:18.866849 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 14:00:18.873640 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 14:00:18.876694 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5143 14:00:18.880056 0 15 0 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (0 1)
5144 14:00:18.887127 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 14:00:18.890208 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 14:00:18.893395 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 14:00:18.900407 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 14:00:18.903603 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 14:00:18.906895 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 14:00:18.913649 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 14:00:18.916898 1 0 0 | B1->B0 | 2e2e 3a3a | 0 0 | (0 0) (0 0)
5152 14:00:18.920751 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 14:00:18.926879 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 14:00:18.930325 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 14:00:18.934255 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 14:00:18.936998 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 14:00:18.943605 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 14:00:18.946870 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 14:00:18.950293 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 14:00:18.957297 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 14:00:18.960618 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 14:00:18.963824 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 14:00:18.970695 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 14:00:18.973703 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 14:00:18.977350 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 14:00:18.983377 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 14:00:18.986848 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 14:00:18.990457 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 14:00:18.997532 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 14:00:19.000689 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 14:00:19.004108 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 14:00:19.010383 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 14:00:19.014010 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 14:00:19.017387 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5175 14:00:19.020890 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 14:00:19.027096 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 14:00:19.031031 Total UI for P1: 0, mck2ui 16
5178 14:00:19.033707 best dqsien dly found for B0: ( 1, 3, 2)
5179 14:00:19.037095 Total UI for P1: 0, mck2ui 16
5180 14:00:19.040420 best dqsien dly found for B1: ( 1, 3, 2)
5181 14:00:19.043569 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5182 14:00:19.047814 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5183 14:00:19.047888
5184 14:00:19.050185 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5185 14:00:19.053882 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5186 14:00:19.057640 [Gating] SW calibration Done
5187 14:00:19.057719 ==
5188 14:00:19.060221 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 14:00:19.063619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 14:00:19.063703 ==
5191 14:00:19.067326 RX Vref Scan: 0
5192 14:00:19.067428
5193 14:00:19.067521 RX Vref 0 -> 0, step: 1
5194 14:00:19.067609
5195 14:00:19.070500 RX Delay -80 -> 252, step: 8
5196 14:00:19.073929 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5197 14:00:19.081401 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5198 14:00:19.083636 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5199 14:00:19.087159 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5200 14:00:19.090237 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5201 14:00:19.093993 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5202 14:00:19.096871 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5203 14:00:19.100547 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5204 14:00:19.107198 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5205 14:00:19.110198 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5206 14:00:19.113829 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5207 14:00:19.117441 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5208 14:00:19.120523 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5209 14:00:19.126922 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5210 14:00:19.130386 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5211 14:00:19.133795 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5212 14:00:19.133895 ==
5213 14:00:19.136970 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 14:00:19.140141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 14:00:19.140216 ==
5216 14:00:19.143707 DQS Delay:
5217 14:00:19.143786 DQS0 = 0, DQS1 = 0
5218 14:00:19.146758 DQM Delay:
5219 14:00:19.146836 DQM0 = 98, DQM1 = 86
5220 14:00:19.146913 DQ Delay:
5221 14:00:19.149988 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =91
5222 14:00:19.153413 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5223 14:00:19.157212 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5224 14:00:19.160196 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5225 14:00:19.160271
5226 14:00:19.160356
5227 14:00:19.163351 ==
5228 14:00:19.166919 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 14:00:19.170086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 14:00:19.170192 ==
5231 14:00:19.170290
5232 14:00:19.170389
5233 14:00:19.173353 TX Vref Scan disable
5234 14:00:19.173429 == TX Byte 0 ==
5235 14:00:19.176807 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5236 14:00:19.183781 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5237 14:00:19.183883 == TX Byte 1 ==
5238 14:00:19.186641 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5239 14:00:19.193339 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5240 14:00:19.193417 ==
5241 14:00:19.196525 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 14:00:19.200062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 14:00:19.200136 ==
5244 14:00:19.200218
5245 14:00:19.200292
5246 14:00:19.203206 TX Vref Scan disable
5247 14:00:19.206563 == TX Byte 0 ==
5248 14:00:19.210026 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5249 14:00:19.213293 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5250 14:00:19.216562 == TX Byte 1 ==
5251 14:00:19.220117 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5252 14:00:19.223669 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5253 14:00:19.223752
5254 14:00:19.226767 [DATLAT]
5255 14:00:19.226850 Freq=933, CH0 RK0
5256 14:00:19.226930
5257 14:00:19.229945 DATLAT Default: 0xd
5258 14:00:19.230023 0, 0xFFFF, sum = 0
5259 14:00:19.233187 1, 0xFFFF, sum = 0
5260 14:00:19.233295 2, 0xFFFF, sum = 0
5261 14:00:19.237024 3, 0xFFFF, sum = 0
5262 14:00:19.237123 4, 0xFFFF, sum = 0
5263 14:00:19.240059 5, 0xFFFF, sum = 0
5264 14:00:19.240136 6, 0xFFFF, sum = 0
5265 14:00:19.243520 7, 0xFFFF, sum = 0
5266 14:00:19.243601 8, 0xFFFF, sum = 0
5267 14:00:19.247102 9, 0xFFFF, sum = 0
5268 14:00:19.247176 10, 0x0, sum = 1
5269 14:00:19.250230 11, 0x0, sum = 2
5270 14:00:19.250330 12, 0x0, sum = 3
5271 14:00:19.253489 13, 0x0, sum = 4
5272 14:00:19.253565 best_step = 11
5273 14:00:19.253646
5274 14:00:19.253720 ==
5275 14:00:19.257011 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 14:00:19.260096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 14:00:19.260169 ==
5278 14:00:19.263471 RX Vref Scan: 1
5279 14:00:19.263544
5280 14:00:19.267085 RX Vref 0 -> 0, step: 1
5281 14:00:19.267159
5282 14:00:19.267241 RX Delay -61 -> 252, step: 4
5283 14:00:19.267316
5284 14:00:19.270042 Set Vref, RX VrefLevel [Byte0]: 54
5285 14:00:19.273609 [Byte1]: 51
5286 14:00:19.278513
5287 14:00:19.278622 Final RX Vref Byte 0 = 54 to rank0
5288 14:00:19.281809 Final RX Vref Byte 1 = 51 to rank0
5289 14:00:19.285161 Final RX Vref Byte 0 = 54 to rank1
5290 14:00:19.288251 Final RX Vref Byte 1 = 51 to rank1==
5291 14:00:19.291220 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 14:00:19.298643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 14:00:19.298730 ==
5294 14:00:19.298802 DQS Delay:
5295 14:00:19.298866 DQS0 = 0, DQS1 = 0
5296 14:00:19.301830 DQM Delay:
5297 14:00:19.301909 DQM0 = 96, DQM1 = 88
5298 14:00:19.304699 DQ Delay:
5299 14:00:19.308063 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5300 14:00:19.311733 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5301 14:00:19.311805 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80
5302 14:00:19.318552 DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =96
5303 14:00:19.318623
5304 14:00:19.318682
5305 14:00:19.324720 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5306 14:00:19.328052 CH0 RK0: MR19=504, MR18=12FD
5307 14:00:19.335048 CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5308 14:00:19.335121
5309 14:00:19.338272 ----->DramcWriteLeveling(PI) begin...
5310 14:00:19.338372 ==
5311 14:00:19.341391 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 14:00:19.344987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 14:00:19.345055 ==
5314 14:00:19.348543 Write leveling (Byte 0): 30 => 30
5315 14:00:19.351429 Write leveling (Byte 1): 30 => 30
5316 14:00:19.354873 DramcWriteLeveling(PI) end<-----
5317 14:00:19.354949
5318 14:00:19.355043 ==
5319 14:00:19.358645 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 14:00:19.361899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 14:00:19.361968 ==
5322 14:00:19.365181 [Gating] SW mode calibration
5323 14:00:19.371585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5324 14:00:19.378473 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5325 14:00:19.382354 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5326 14:00:19.385251 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5327 14:00:19.391608 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 14:00:19.395148 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 14:00:19.398490 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 14:00:19.404690 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 14:00:19.408078 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5332 14:00:19.411739 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
5333 14:00:19.418701 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5334 14:00:19.422295 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 14:00:19.425113 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 14:00:19.431514 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 14:00:19.435093 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 14:00:19.438757 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 14:00:19.442062 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 14:00:19.448471 0 15 28 | B1->B0 | 2b2b 3636 | 0 0 | (0 0) (0 0)
5341 14:00:19.451802 1 0 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5342 14:00:19.455093 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5343 14:00:19.461707 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 14:00:19.465032 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 14:00:19.468564 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 14:00:19.475156 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 14:00:19.478682 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 14:00:19.481574 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5349 14:00:19.488418 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5350 14:00:19.491758 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5351 14:00:19.495233 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 14:00:19.502004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 14:00:19.505618 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 14:00:19.509500 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 14:00:19.514967 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 14:00:19.518546 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 14:00:19.521692 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 14:00:19.525153 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 14:00:19.531857 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 14:00:19.535219 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 14:00:19.538482 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 14:00:19.545093 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 14:00:19.548239 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 14:00:19.552325 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5365 14:00:19.555775 Total UI for P1: 0, mck2ui 16
5366 14:00:19.558538 best dqsien dly found for B0: ( 1, 2, 26)
5367 14:00:19.564955 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5368 14:00:19.568327 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 14:00:19.571805 Total UI for P1: 0, mck2ui 16
5370 14:00:19.575287 best dqsien dly found for B1: ( 1, 2, 30)
5371 14:00:19.578312 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5372 14:00:19.581813 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5373 14:00:19.581886
5374 14:00:19.584908 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5375 14:00:19.588655 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5376 14:00:19.591523 [Gating] SW calibration Done
5377 14:00:19.591594 ==
5378 14:00:19.595367 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 14:00:19.598825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 14:00:19.602372 ==
5381 14:00:19.602488 RX Vref Scan: 0
5382 14:00:19.602567
5383 14:00:19.605314 RX Vref 0 -> 0, step: 1
5384 14:00:19.605386
5385 14:00:19.608221 RX Delay -80 -> 252, step: 8
5386 14:00:19.612345 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5387 14:00:19.615166 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5388 14:00:19.618300 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5389 14:00:19.622195 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5390 14:00:19.625272 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5391 14:00:19.628364 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5392 14:00:19.635085 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5393 14:00:19.638593 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5394 14:00:19.642016 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5395 14:00:19.645411 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5396 14:00:19.648422 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5397 14:00:19.655604 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5398 14:00:19.658335 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5399 14:00:19.662022 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5400 14:00:19.665319 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5401 14:00:19.668768 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5402 14:00:19.668843 ==
5403 14:00:19.672460 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 14:00:19.678790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 14:00:19.678864 ==
5406 14:00:19.678943 DQS Delay:
5407 14:00:19.679020 DQS0 = 0, DQS1 = 0
5408 14:00:19.682117 DQM Delay:
5409 14:00:19.682186 DQM0 = 97, DQM1 = 87
5410 14:00:19.685566 DQ Delay:
5411 14:00:19.688539 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5412 14:00:19.692009 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5413 14:00:19.692081 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5414 14:00:19.699041 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5415 14:00:19.699115
5416 14:00:19.699193
5417 14:00:19.699267 ==
5418 14:00:19.701727 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 14:00:19.705720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 14:00:19.705798 ==
5421 14:00:19.705877
5422 14:00:19.705952
5423 14:00:19.708500 TX Vref Scan disable
5424 14:00:19.708571 == TX Byte 0 ==
5425 14:00:19.715563 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5426 14:00:19.718763 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5427 14:00:19.718841 == TX Byte 1 ==
5428 14:00:19.725526 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5429 14:00:19.728991 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5430 14:00:19.729069 ==
5431 14:00:19.732350 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 14:00:19.735451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 14:00:19.735528 ==
5434 14:00:19.735607
5435 14:00:19.735681
5436 14:00:19.739042 TX Vref Scan disable
5437 14:00:19.742376 == TX Byte 0 ==
5438 14:00:19.745382 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5439 14:00:19.748602 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5440 14:00:19.752717 == TX Byte 1 ==
5441 14:00:19.755514 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5442 14:00:19.758910 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5443 14:00:19.758982
5444 14:00:19.759063 [DATLAT]
5445 14:00:19.762033 Freq=933, CH0 RK1
5446 14:00:19.762107
5447 14:00:19.765624 DATLAT Default: 0xb
5448 14:00:19.765699 0, 0xFFFF, sum = 0
5449 14:00:19.769009 1, 0xFFFF, sum = 0
5450 14:00:19.769084 2, 0xFFFF, sum = 0
5451 14:00:19.772097 3, 0xFFFF, sum = 0
5452 14:00:19.772173 4, 0xFFFF, sum = 0
5453 14:00:19.775745 5, 0xFFFF, sum = 0
5454 14:00:19.775823 6, 0xFFFF, sum = 0
5455 14:00:19.778883 7, 0xFFFF, sum = 0
5456 14:00:19.778963 8, 0xFFFF, sum = 0
5457 14:00:19.782190 9, 0xFFFF, sum = 0
5458 14:00:19.782265 10, 0x0, sum = 1
5459 14:00:19.785725 11, 0x0, sum = 2
5460 14:00:19.785801 12, 0x0, sum = 3
5461 14:00:19.789114 13, 0x0, sum = 4
5462 14:00:19.789186 best_step = 11
5463 14:00:19.789261
5464 14:00:19.789338 ==
5465 14:00:19.792083 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 14:00:19.795364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 14:00:19.795438 ==
5468 14:00:19.799110 RX Vref Scan: 0
5469 14:00:19.799182
5470 14:00:19.802454 RX Vref 0 -> 0, step: 1
5471 14:00:19.802553
5472 14:00:19.802649 RX Delay -61 -> 252, step: 4
5473 14:00:19.810488 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5474 14:00:19.813496 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5475 14:00:19.816910 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5476 14:00:19.820252 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5477 14:00:19.824317 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5478 14:00:19.826987 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5479 14:00:19.833350 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5480 14:00:19.836925 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5481 14:00:19.840086 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5482 14:00:19.843954 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5483 14:00:19.846792 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5484 14:00:19.853753 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5485 14:00:19.857265 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5486 14:00:19.860242 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5487 14:00:19.863175 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5488 14:00:19.866668 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5489 14:00:19.866743 ==
5490 14:00:19.870499 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 14:00:19.873607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 14:00:19.876641 ==
5493 14:00:19.876745 DQS Delay:
5494 14:00:19.876825 DQS0 = 0, DQS1 = 0
5495 14:00:19.880061 DQM Delay:
5496 14:00:19.880133 DQM0 = 95, DQM1 = 88
5497 14:00:19.883687 DQ Delay:
5498 14:00:19.887348 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =94
5499 14:00:19.889953 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5500 14:00:19.890031 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =78
5501 14:00:19.896819 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5502 14:00:19.896892
5503 14:00:19.896970
5504 14:00:19.903549 [DQSOSCAuto] RK1, (LSB)MR18= 0x1906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5505 14:00:19.906736 CH0 RK1: MR19=505, MR18=1906
5506 14:00:19.913452 CH0_RK1: MR19=0x505, MR18=0x1906, DQSOSC=413, MR23=63, INC=63, DEC=42
5507 14:00:19.916696 [RxdqsGatingPostProcess] freq 933
5508 14:00:19.920134 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5509 14:00:19.923281 best DQS0 dly(2T, 0.5T) = (0, 11)
5510 14:00:19.927121 best DQS1 dly(2T, 0.5T) = (0, 11)
5511 14:00:19.930306 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5512 14:00:19.933698 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5513 14:00:19.937109 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 14:00:19.940078 best DQS1 dly(2T, 0.5T) = (0, 10)
5515 14:00:19.943251 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 14:00:19.946916 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5517 14:00:19.950235 Pre-setting of DQS Precalculation
5518 14:00:19.953685 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5519 14:00:19.953758 ==
5520 14:00:19.957243 Dram Type= 6, Freq= 0, CH_1, rank 0
5521 14:00:19.960095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 14:00:19.963371 ==
5523 14:00:19.967258 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 14:00:19.973683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5525 14:00:19.976929 [CA 0] Center 36 (6~67) winsize 62
5526 14:00:19.980405 [CA 1] Center 36 (6~67) winsize 62
5527 14:00:19.984179 [CA 2] Center 34 (4~64) winsize 61
5528 14:00:19.987430 [CA 3] Center 34 (4~64) winsize 61
5529 14:00:19.990939 [CA 4] Center 34 (4~64) winsize 61
5530 14:00:19.994587 [CA 5] Center 33 (3~64) winsize 62
5531 14:00:19.994664
5532 14:00:19.996950 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5533 14:00:19.997021
5534 14:00:20.000630 [CATrainingPosCal] consider 1 rank data
5535 14:00:20.003842 u2DelayCellTimex100 = 270/100 ps
5536 14:00:20.007624 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 14:00:20.010887 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 14:00:20.013777 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5539 14:00:20.016995 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 14:00:20.020173 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5541 14:00:20.027063 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 14:00:20.027140
5543 14:00:20.030578 CA PerBit enable=1, Macro0, CA PI delay=33
5544 14:00:20.030658
5545 14:00:20.033914 [CBTSetCACLKResult] CA Dly = 33
5546 14:00:20.033990 CS Dly: 4 (0~35)
5547 14:00:20.034090 ==
5548 14:00:20.037112 Dram Type= 6, Freq= 0, CH_1, rank 1
5549 14:00:20.040388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 14:00:20.043774 ==
5551 14:00:20.047656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 14:00:20.053404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5553 14:00:20.056808 [CA 0] Center 36 (6~67) winsize 62
5554 14:00:20.060218 [CA 1] Center 37 (7~67) winsize 61
5555 14:00:20.063339 [CA 2] Center 33 (3~64) winsize 62
5556 14:00:20.066972 [CA 3] Center 33 (3~64) winsize 62
5557 14:00:20.070116 [CA 4] Center 34 (4~65) winsize 62
5558 14:00:20.073411 [CA 5] Center 33 (2~64) winsize 63
5559 14:00:20.073485
5560 14:00:20.076510 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5561 14:00:20.076583
5562 14:00:20.080215 [CATrainingPosCal] consider 2 rank data
5563 14:00:20.083256 u2DelayCellTimex100 = 270/100 ps
5564 14:00:20.086732 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 14:00:20.090213 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5566 14:00:20.093439 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5567 14:00:20.096733 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 14:00:20.100267 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 14:00:20.107343 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 14:00:20.107420
5571 14:00:20.109925 CA PerBit enable=1, Macro0, CA PI delay=33
5572 14:00:20.110050
5573 14:00:20.113908 [CBTSetCACLKResult] CA Dly = 33
5574 14:00:20.113993 CS Dly: 5 (0~38)
5575 14:00:20.114096
5576 14:00:20.116447 ----->DramcWriteLeveling(PI) begin...
5577 14:00:20.116520 ==
5578 14:00:20.120484 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 14:00:20.126549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 14:00:20.126631 ==
5581 14:00:20.129929 Write leveling (Byte 0): 28 => 28
5582 14:00:20.130035 Write leveling (Byte 1): 29 => 29
5583 14:00:20.133572 DramcWriteLeveling(PI) end<-----
5584 14:00:20.133649
5585 14:00:20.133745 ==
5586 14:00:20.136588 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 14:00:20.143400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 14:00:20.143480 ==
5589 14:00:20.146557 [Gating] SW mode calibration
5590 14:00:20.153299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5591 14:00:20.157005 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5592 14:00:20.163287 0 14 0 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
5593 14:00:20.166163 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 14:00:20.170025 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 14:00:20.176369 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 14:00:20.179825 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5597 14:00:20.182971 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 14:00:20.189702 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 14:00:20.192882 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
5600 14:00:20.195844 0 15 0 | B1->B0 | 2525 2424 | 0 0 | (1 0) (0 0)
5601 14:00:20.202680 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 14:00:20.206070 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 14:00:20.209443 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 14:00:20.216779 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 14:00:20.219555 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 14:00:20.222632 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 14:00:20.230020 0 15 28 | B1->B0 | 2b2b 2c2c | 0 0 | (0 0) (0 0)
5608 14:00:20.232380 1 0 0 | B1->B0 | 3f3f 4646 | 1 0 | (1 1) (0 0)
5609 14:00:20.235801 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 14:00:20.239287 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 14:00:20.246203 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 14:00:20.249770 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 14:00:20.252647 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 14:00:20.259223 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 14:00:20.262975 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5616 14:00:20.266316 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5617 14:00:20.273466 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 14:00:20.276042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 14:00:20.279529 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 14:00:20.286083 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 14:00:20.289294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 14:00:20.292908 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 14:00:20.299148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 14:00:20.303162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 14:00:20.306022 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 14:00:20.312983 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 14:00:20.316525 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 14:00:20.319364 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 14:00:20.322786 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 14:00:20.329290 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5631 14:00:20.332772 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5632 14:00:20.335989 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 14:00:20.339605 Total UI for P1: 0, mck2ui 16
5634 14:00:20.342550 best dqsien dly found for B0: ( 1, 2, 28)
5635 14:00:20.346581 Total UI for P1: 0, mck2ui 16
5636 14:00:20.349504 best dqsien dly found for B1: ( 1, 2, 26)
5637 14:00:20.352854 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5638 14:00:20.356571 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5639 14:00:20.356647
5640 14:00:20.362438 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5641 14:00:20.365885 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5642 14:00:20.369360 [Gating] SW calibration Done
5643 14:00:20.369435 ==
5644 14:00:20.373201 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 14:00:20.375946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 14:00:20.376017 ==
5647 14:00:20.376076 RX Vref Scan: 0
5648 14:00:20.376132
5649 14:00:20.379367 RX Vref 0 -> 0, step: 1
5650 14:00:20.379434
5651 14:00:20.383228 RX Delay -80 -> 252, step: 8
5652 14:00:20.386347 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5653 14:00:20.389462 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5654 14:00:20.392758 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5655 14:00:20.399326 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5656 14:00:20.402862 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5657 14:00:20.405980 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5658 14:00:20.409463 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5659 14:00:20.413041 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5660 14:00:20.416518 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5661 14:00:20.422749 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5662 14:00:20.426179 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5663 14:00:20.429655 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5664 14:00:20.433001 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5665 14:00:20.436165 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5666 14:00:20.443429 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5667 14:00:20.446321 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5668 14:00:20.446419 ==
5669 14:00:20.449193 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 14:00:20.452555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 14:00:20.452641 ==
5672 14:00:20.452714 DQS Delay:
5673 14:00:20.456077 DQS0 = 0, DQS1 = 0
5674 14:00:20.456152 DQM Delay:
5675 14:00:20.459526 DQM0 = 96, DQM1 = 88
5676 14:00:20.459598 DQ Delay:
5677 14:00:20.462460 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5678 14:00:20.465737 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5679 14:00:20.469260 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5680 14:00:20.472630 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5681 14:00:20.472718
5682 14:00:20.472807
5683 14:00:20.472893 ==
5684 14:00:20.476008 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 14:00:20.479362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 14:00:20.482940 ==
5687 14:00:20.483033
5688 14:00:20.483119
5689 14:00:20.483204 TX Vref Scan disable
5690 14:00:20.486200 == TX Byte 0 ==
5691 14:00:20.489801 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5692 14:00:20.492590 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5693 14:00:20.496324 == TX Byte 1 ==
5694 14:00:20.499509 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5695 14:00:20.502393 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5696 14:00:20.505708 ==
5697 14:00:20.505775 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 14:00:20.512853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 14:00:20.512953 ==
5700 14:00:20.513042
5701 14:00:20.513131
5702 14:00:20.516349 TX Vref Scan disable
5703 14:00:20.516420 == TX Byte 0 ==
5704 14:00:20.522871 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5705 14:00:20.526198 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5706 14:00:20.526295 == TX Byte 1 ==
5707 14:00:20.532644 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5708 14:00:20.536241 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5709 14:00:20.536346
5710 14:00:20.536442 [DATLAT]
5711 14:00:20.539377 Freq=933, CH1 RK0
5712 14:00:20.539462
5713 14:00:20.539525 DATLAT Default: 0xd
5714 14:00:20.542775 0, 0xFFFF, sum = 0
5715 14:00:20.542852 1, 0xFFFF, sum = 0
5716 14:00:20.547098 2, 0xFFFF, sum = 0
5717 14:00:20.547170 3, 0xFFFF, sum = 0
5718 14:00:20.550669 4, 0xFFFF, sum = 0
5719 14:00:20.550797 5, 0xFFFF, sum = 0
5720 14:00:20.552890 6, 0xFFFF, sum = 0
5721 14:00:20.552976 7, 0xFFFF, sum = 0
5722 14:00:20.556041 8, 0xFFFF, sum = 0
5723 14:00:20.556138 9, 0xFFFF, sum = 0
5724 14:00:20.559542 10, 0x0, sum = 1
5725 14:00:20.559643 11, 0x0, sum = 2
5726 14:00:20.563111 12, 0x0, sum = 3
5727 14:00:20.563216 13, 0x0, sum = 4
5728 14:00:20.566030 best_step = 11
5729 14:00:20.566102
5730 14:00:20.566162 ==
5731 14:00:20.569764 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 14:00:20.573062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 14:00:20.573134 ==
5734 14:00:20.573196 RX Vref Scan: 1
5735 14:00:20.576673
5736 14:00:20.576740 RX Vref 0 -> 0, step: 1
5737 14:00:20.576798
5738 14:00:20.579523 RX Delay -69 -> 252, step: 4
5739 14:00:20.579596
5740 14:00:20.582612 Set Vref, RX VrefLevel [Byte0]: 56
5741 14:00:20.586210 [Byte1]: 52
5742 14:00:20.589612
5743 14:00:20.589688 Final RX Vref Byte 0 = 56 to rank0
5744 14:00:20.592813 Final RX Vref Byte 1 = 52 to rank0
5745 14:00:20.596412 Final RX Vref Byte 0 = 56 to rank1
5746 14:00:20.599960 Final RX Vref Byte 1 = 52 to rank1==
5747 14:00:20.603067 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 14:00:20.609826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 14:00:20.609933 ==
5750 14:00:20.610028 DQS Delay:
5751 14:00:20.610115 DQS0 = 0, DQS1 = 0
5752 14:00:20.612810 DQM Delay:
5753 14:00:20.612916 DQM0 = 97, DQM1 = 90
5754 14:00:20.616125 DQ Delay:
5755 14:00:20.619613 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5756 14:00:20.623012 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5757 14:00:20.626451 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
5758 14:00:20.629783 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =94
5759 14:00:20.629861
5760 14:00:20.629962
5761 14:00:20.637190 [DQSOSCAuto] RK0, (LSB)MR18= 0x12ef, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 416 ps
5762 14:00:20.639467 CH1 RK0: MR19=504, MR18=12EF
5763 14:00:20.646572 CH1_RK0: MR19=0x504, MR18=0x12EF, DQSOSC=416, MR23=63, INC=62, DEC=41
5764 14:00:20.646648
5765 14:00:20.649857 ----->DramcWriteLeveling(PI) begin...
5766 14:00:20.649930 ==
5767 14:00:20.653588 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 14:00:20.656294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 14:00:20.656367 ==
5770 14:00:20.660139 Write leveling (Byte 0): 27 => 27
5771 14:00:20.663014 Write leveling (Byte 1): 27 => 27
5772 14:00:20.666410 DramcWriteLeveling(PI) end<-----
5773 14:00:20.666514
5774 14:00:20.666595 ==
5775 14:00:20.669852 Dram Type= 6, Freq= 0, CH_1, rank 1
5776 14:00:20.673196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 14:00:20.673273 ==
5778 14:00:20.676724 [Gating] SW mode calibration
5779 14:00:20.682915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5780 14:00:20.689953 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5781 14:00:20.693590 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 14:00:20.696668 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 14:00:20.703103 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 14:00:20.706664 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 14:00:20.709533 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 14:00:20.716259 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 14:00:20.719699 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5788 14:00:20.723271 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5789 14:00:20.729906 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 14:00:20.733745 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 14:00:20.736654 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 14:00:20.743480 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 14:00:20.746224 0 15 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5794 14:00:20.749948 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 14:00:20.753574 0 15 24 | B1->B0 | 2626 3333 | 0 0 | (0 0) (1 1)
5796 14:00:20.759785 0 15 28 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5797 14:00:20.763717 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 14:00:20.766400 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 14:00:20.773298 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 14:00:20.776673 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 14:00:20.779867 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 14:00:20.786919 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 14:00:20.789924 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5804 14:00:20.793868 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5805 14:00:20.799937 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 14:00:20.802989 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 14:00:20.806980 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 14:00:20.813413 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 14:00:20.816555 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 14:00:20.820057 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 14:00:20.826700 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 14:00:20.829945 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 14:00:20.833489 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 14:00:20.840011 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 14:00:20.843453 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 14:00:20.846718 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 14:00:20.849962 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 14:00:20.856725 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 14:00:20.860008 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5820 14:00:20.863032 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 14:00:20.866652 Total UI for P1: 0, mck2ui 16
5822 14:00:20.869730 best dqsien dly found for B0: ( 1, 2, 24)
5823 14:00:20.873036 Total UI for P1: 0, mck2ui 16
5824 14:00:20.876381 best dqsien dly found for B1: ( 1, 2, 26)
5825 14:00:20.880001 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5826 14:00:20.883034 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5827 14:00:20.886435
5828 14:00:20.889806 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5829 14:00:20.893414 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5830 14:00:20.896751 [Gating] SW calibration Done
5831 14:00:20.896821 ==
5832 14:00:20.899904 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 14:00:20.903023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 14:00:20.903116 ==
5835 14:00:20.903186 RX Vref Scan: 0
5836 14:00:20.903254
5837 14:00:20.906301 RX Vref 0 -> 0, step: 1
5838 14:00:20.906407
5839 14:00:20.909882 RX Delay -80 -> 252, step: 8
5840 14:00:20.913246 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5841 14:00:20.916656 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5842 14:00:20.919615 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5843 14:00:20.927024 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5844 14:00:20.929792 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5845 14:00:20.933294 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5846 14:00:20.936594 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5847 14:00:20.939789 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5848 14:00:20.943681 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5849 14:00:20.950009 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5850 14:00:20.953347 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5851 14:00:20.956595 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5852 14:00:20.959974 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5853 14:00:20.963900 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5854 14:00:20.966802 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5855 14:00:20.973688 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5856 14:00:20.973764 ==
5857 14:00:20.976618 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 14:00:20.980100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 14:00:20.980168 ==
5860 14:00:20.980231 DQS Delay:
5861 14:00:20.982993 DQS0 = 0, DQS1 = 0
5862 14:00:20.983067 DQM Delay:
5863 14:00:20.986729 DQM0 = 94, DQM1 = 89
5864 14:00:20.986827 DQ Delay:
5865 14:00:20.989854 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5866 14:00:20.993185 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5867 14:00:20.996740 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5868 14:00:21.000069 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5869 14:00:21.000144
5870 14:00:21.000205
5871 14:00:21.000266 ==
5872 14:00:21.003412 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 14:00:21.006829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 14:00:21.006903 ==
5875 14:00:21.006965
5876 14:00:21.009797
5877 14:00:21.009863 TX Vref Scan disable
5878 14:00:21.012996 == TX Byte 0 ==
5879 14:00:21.016522 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5880 14:00:21.019828 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5881 14:00:21.023354 == TX Byte 1 ==
5882 14:00:21.026551 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5883 14:00:21.029778 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5884 14:00:21.029877 ==
5885 14:00:21.033207 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 14:00:21.040024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 14:00:21.040097 ==
5888 14:00:21.040159
5889 14:00:21.040216
5890 14:00:21.040271 TX Vref Scan disable
5891 14:00:21.043772 == TX Byte 0 ==
5892 14:00:21.047249 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5893 14:00:21.050721 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5894 14:00:21.054028 == TX Byte 1 ==
5895 14:00:21.057011 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5896 14:00:21.064288 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5897 14:00:21.064357
5898 14:00:21.064417 [DATLAT]
5899 14:00:21.064477 Freq=933, CH1 RK1
5900 14:00:21.064533
5901 14:00:21.067104 DATLAT Default: 0xb
5902 14:00:21.067171 0, 0xFFFF, sum = 0
5903 14:00:21.070308 1, 0xFFFF, sum = 0
5904 14:00:21.070415 2, 0xFFFF, sum = 0
5905 14:00:21.073621 3, 0xFFFF, sum = 0
5906 14:00:21.073691 4, 0xFFFF, sum = 0
5907 14:00:21.077234 5, 0xFFFF, sum = 0
5908 14:00:21.080371 6, 0xFFFF, sum = 0
5909 14:00:21.080447 7, 0xFFFF, sum = 0
5910 14:00:21.084046 8, 0xFFFF, sum = 0
5911 14:00:21.084158 9, 0xFFFF, sum = 0
5912 14:00:21.087187 10, 0x0, sum = 1
5913 14:00:21.087261 11, 0x0, sum = 2
5914 14:00:21.087334 12, 0x0, sum = 3
5915 14:00:21.090217 13, 0x0, sum = 4
5916 14:00:21.090320 best_step = 11
5917 14:00:21.090417
5918 14:00:21.093929 ==
5919 14:00:21.094025 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 14:00:21.100575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 14:00:21.100674 ==
5922 14:00:21.100764 RX Vref Scan: 0
5923 14:00:21.100849
5924 14:00:21.104003 RX Vref 0 -> 0, step: 1
5925 14:00:21.104096
5926 14:00:21.106965 RX Delay -61 -> 252, step: 4
5927 14:00:21.110774 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5928 14:00:21.117570 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5929 14:00:21.120299 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5930 14:00:21.123760 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5931 14:00:21.127453 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5932 14:00:21.130387 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5933 14:00:21.133942 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5934 14:00:21.140445 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5935 14:00:21.143968 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5936 14:00:21.147087 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5937 14:00:21.150545 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5938 14:00:21.153989 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5939 14:00:21.157578 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5940 14:00:21.164244 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5941 14:00:21.167016 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5942 14:00:21.170819 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5943 14:00:21.171106 ==
5944 14:00:21.174371 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 14:00:21.177091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 14:00:21.180998 ==
5947 14:00:21.181475 DQS Delay:
5948 14:00:21.181723 DQS0 = 0, DQS1 = 0
5949 14:00:21.184783 DQM Delay:
5950 14:00:21.185284 DQM0 = 95, DQM1 = 91
5951 14:00:21.187919 DQ Delay:
5952 14:00:21.188396 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5953 14:00:21.190955 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =92
5954 14:00:21.194008 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =82
5955 14:00:21.200669 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5956 14:00:21.201221
5957 14:00:21.201581
5958 14:00:21.207396 [DQSOSCAuto] RK1, (LSB)MR18= 0xb14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5959 14:00:21.211101 CH1 RK1: MR19=505, MR18=B14
5960 14:00:21.218467 CH1_RK1: MR19=0x505, MR18=0xB14, DQSOSC=415, MR23=63, INC=62, DEC=41
5961 14:00:21.220915 [RxdqsGatingPostProcess] freq 933
5962 14:00:21.224244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5963 14:00:21.227682 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 14:00:21.230909 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 14:00:21.234283 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 14:00:21.237437 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 14:00:21.240958 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 14:00:21.244693 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 14:00:21.247770 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 14:00:21.250699 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 14:00:21.254214 Pre-setting of DQS Precalculation
5972 14:00:21.257494 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5973 14:00:21.264180 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5974 14:00:21.270739 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5975 14:00:21.271277
5976 14:00:21.274429
5977 14:00:21.274841 [Calibration Summary] 1866 Mbps
5978 14:00:21.277442 CH 0, Rank 0
5979 14:00:21.277851 SW Impedance : PASS
5980 14:00:21.280894 DUTY Scan : NO K
5981 14:00:21.284780 ZQ Calibration : PASS
5982 14:00:21.285291 Jitter Meter : NO K
5983 14:00:21.287862 CBT Training : PASS
5984 14:00:21.290976 Write leveling : PASS
5985 14:00:21.291393 RX DQS gating : PASS
5986 14:00:21.294513 RX DQ/DQS(RDDQC) : PASS
5987 14:00:21.297825 TX DQ/DQS : PASS
5988 14:00:21.298262 RX DATLAT : PASS
5989 14:00:21.300500 RX DQ/DQS(Engine): PASS
5990 14:00:21.304387 TX OE : NO K
5991 14:00:21.304896 All Pass.
5992 14:00:21.305227
5993 14:00:21.305532 CH 0, Rank 1
5994 14:00:21.307692 SW Impedance : PASS
5995 14:00:21.310606 DUTY Scan : NO K
5996 14:00:21.311185 ZQ Calibration : PASS
5997 14:00:21.314084 Jitter Meter : NO K
5998 14:00:21.314543 CBT Training : PASS
5999 14:00:21.317697 Write leveling : PASS
6000 14:00:21.320885 RX DQS gating : PASS
6001 14:00:21.321301 RX DQ/DQS(RDDQC) : PASS
6002 14:00:21.324270 TX DQ/DQS : PASS
6003 14:00:21.327698 RX DATLAT : PASS
6004 14:00:21.328110 RX DQ/DQS(Engine): PASS
6005 14:00:21.331094 TX OE : NO K
6006 14:00:21.331558 All Pass.
6007 14:00:21.331886
6008 14:00:21.334374 CH 1, Rank 0
6009 14:00:21.334848 SW Impedance : PASS
6010 14:00:21.337901 DUTY Scan : NO K
6011 14:00:21.341245 ZQ Calibration : PASS
6012 14:00:21.341822 Jitter Meter : NO K
6013 14:00:21.344282 CBT Training : PASS
6014 14:00:21.347759 Write leveling : PASS
6015 14:00:21.348172 RX DQS gating : PASS
6016 14:00:21.350880 RX DQ/DQS(RDDQC) : PASS
6017 14:00:21.351292 TX DQ/DQS : PASS
6018 14:00:21.354225 RX DATLAT : PASS
6019 14:00:21.357511 RX DQ/DQS(Engine): PASS
6020 14:00:21.358025 TX OE : NO K
6021 14:00:21.361315 All Pass.
6022 14:00:21.361726
6023 14:00:21.362051 CH 1, Rank 1
6024 14:00:21.363911 SW Impedance : PASS
6025 14:00:21.364359 DUTY Scan : NO K
6026 14:00:21.367685 ZQ Calibration : PASS
6027 14:00:21.370573 Jitter Meter : NO K
6028 14:00:21.370988 CBT Training : PASS
6029 14:00:21.374455 Write leveling : PASS
6030 14:00:21.377723 RX DQS gating : PASS
6031 14:00:21.378248 RX DQ/DQS(RDDQC) : PASS
6032 14:00:21.381142 TX DQ/DQS : PASS
6033 14:00:21.384204 RX DATLAT : PASS
6034 14:00:21.384713 RX DQ/DQS(Engine): PASS
6035 14:00:21.387641 TX OE : NO K
6036 14:00:21.388155 All Pass.
6037 14:00:21.388486
6038 14:00:21.391009 DramC Write-DBI off
6039 14:00:21.394486 PER_BANK_REFRESH: Hybrid Mode
6040 14:00:21.395005 TX_TRACKING: ON
6041 14:00:21.404553 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6042 14:00:21.407432 [FAST_K] Save calibration result to emmc
6043 14:00:21.410800 dramc_set_vcore_voltage set vcore to 650000
6044 14:00:21.413730 Read voltage for 400, 6
6045 14:00:21.414150 Vio18 = 0
6046 14:00:21.414523 Vcore = 650000
6047 14:00:21.417179 Vdram = 0
6048 14:00:21.417639 Vddq = 0
6049 14:00:21.418002 Vmddr = 0
6050 14:00:21.424414 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6051 14:00:21.427223 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6052 14:00:21.430511 MEM_TYPE=3, freq_sel=20
6053 14:00:21.434249 sv_algorithm_assistance_LP4_800
6054 14:00:21.437675 ============ PULL DRAM RESETB DOWN ============
6055 14:00:21.440609 ========== PULL DRAM RESETB DOWN end =========
6056 14:00:21.447287 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6057 14:00:21.450703 ===================================
6058 14:00:21.451257 LPDDR4 DRAM CONFIGURATION
6059 14:00:21.454381 ===================================
6060 14:00:21.457277 EX_ROW_EN[0] = 0x0
6061 14:00:21.460873 EX_ROW_EN[1] = 0x0
6062 14:00:21.461429 LP4Y_EN = 0x0
6063 14:00:21.463646 WORK_FSP = 0x0
6064 14:00:21.464104 WL = 0x2
6065 14:00:21.467390 RL = 0x2
6066 14:00:21.467845 BL = 0x2
6067 14:00:21.471051 RPST = 0x0
6068 14:00:21.471596 RD_PRE = 0x0
6069 14:00:21.474550 WR_PRE = 0x1
6070 14:00:21.475146 WR_PST = 0x0
6071 14:00:21.477159 DBI_WR = 0x0
6072 14:00:21.477727 DBI_RD = 0x0
6073 14:00:21.480077 OTF = 0x1
6074 14:00:21.483681 ===================================
6075 14:00:21.487219 ===================================
6076 14:00:21.487741 ANA top config
6077 14:00:21.490124 ===================================
6078 14:00:21.493944 DLL_ASYNC_EN = 0
6079 14:00:21.496529 ALL_SLAVE_EN = 1
6080 14:00:21.500362 NEW_RANK_MODE = 1
6081 14:00:21.500925 DLL_IDLE_MODE = 1
6082 14:00:21.503425 LP45_APHY_COMB_EN = 1
6083 14:00:21.507130 TX_ODT_DIS = 1
6084 14:00:21.510324 NEW_8X_MODE = 1
6085 14:00:21.513562 ===================================
6086 14:00:21.516885 ===================================
6087 14:00:21.520299 data_rate = 800
6088 14:00:21.520757 CKR = 1
6089 14:00:21.523916 DQ_P2S_RATIO = 4
6090 14:00:21.527067 ===================================
6091 14:00:21.529910 CA_P2S_RATIO = 4
6092 14:00:21.533755 DQ_CA_OPEN = 0
6093 14:00:21.536620 DQ_SEMI_OPEN = 1
6094 14:00:21.540064 CA_SEMI_OPEN = 1
6095 14:00:21.540552 CA_FULL_RATE = 0
6096 14:00:21.543140 DQ_CKDIV4_EN = 0
6097 14:00:21.546543 CA_CKDIV4_EN = 1
6098 14:00:21.550547 CA_PREDIV_EN = 0
6099 14:00:21.553615 PH8_DLY = 0
6100 14:00:21.554130 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6101 14:00:21.557046 DQ_AAMCK_DIV = 0
6102 14:00:21.561124 CA_AAMCK_DIV = 0
6103 14:00:21.563214 CA_ADMCK_DIV = 4
6104 14:00:21.566779 DQ_TRACK_CA_EN = 0
6105 14:00:21.570389 CA_PICK = 800
6106 14:00:21.573511 CA_MCKIO = 400
6107 14:00:21.574063 MCKIO_SEMI = 400
6108 14:00:21.577093 PLL_FREQ = 3016
6109 14:00:21.579830 DQ_UI_PI_RATIO = 32
6110 14:00:21.583420 CA_UI_PI_RATIO = 32
6111 14:00:21.586504 ===================================
6112 14:00:21.590565 ===================================
6113 14:00:21.593825 memory_type:LPDDR4
6114 14:00:21.594374 GP_NUM : 10
6115 14:00:21.596635 SRAM_EN : 1
6116 14:00:21.600113 MD32_EN : 0
6117 14:00:21.603467 ===================================
6118 14:00:21.604026 [ANA_INIT] >>>>>>>>>>>>>>
6119 14:00:21.606853 <<<<<< [CONFIGURE PHASE]: ANA_TX
6120 14:00:21.610159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6121 14:00:21.613131 ===================================
6122 14:00:21.616593 data_rate = 800,PCW = 0X7400
6123 14:00:21.619737 ===================================
6124 14:00:21.623247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6125 14:00:21.630152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 14:00:21.639705 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 14:00:21.642921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6128 14:00:21.646377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6129 14:00:21.653082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6130 14:00:21.653551 [ANA_INIT] flow start
6131 14:00:21.656476 [ANA_INIT] PLL >>>>>>>>
6132 14:00:21.656898 [ANA_INIT] PLL <<<<<<<<
6133 14:00:21.660108 [ANA_INIT] MIDPI >>>>>>>>
6134 14:00:21.663147 [ANA_INIT] MIDPI <<<<<<<<
6135 14:00:21.666729 [ANA_INIT] DLL >>>>>>>>
6136 14:00:21.667149 [ANA_INIT] flow end
6137 14:00:21.670204 ============ LP4 DIFF to SE enter ============
6138 14:00:21.676599 ============ LP4 DIFF to SE exit ============
6139 14:00:21.677021 [ANA_INIT] <<<<<<<<<<<<<
6140 14:00:21.679880 [Flow] Enable top DCM control >>>>>
6141 14:00:21.683258 [Flow] Enable top DCM control <<<<<
6142 14:00:21.686569 Enable DLL master slave shuffle
6143 14:00:21.693295 ==============================================================
6144 14:00:21.693811 Gating Mode config
6145 14:00:21.699739 ==============================================================
6146 14:00:21.703210 Config description:
6147 14:00:21.712983 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6148 14:00:21.719773 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6149 14:00:21.723165 SELPH_MODE 0: By rank 1: By Phase
6150 14:00:21.729447 ==============================================================
6151 14:00:21.729677 GAT_TRACK_EN = 0
6152 14:00:21.732788 RX_GATING_MODE = 2
6153 14:00:21.736707 RX_GATING_TRACK_MODE = 2
6154 14:00:21.739828 SELPH_MODE = 1
6155 14:00:21.743289 PICG_EARLY_EN = 1
6156 14:00:21.746861 VALID_LAT_VALUE = 1
6157 14:00:21.753336 ==============================================================
6158 14:00:21.756918 Enter into Gating configuration >>>>
6159 14:00:21.759656 Exit from Gating configuration <<<<
6160 14:00:21.763258 Enter into DVFS_PRE_config >>>>>
6161 14:00:21.773495 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6162 14:00:21.776722 Exit from DVFS_PRE_config <<<<<
6163 14:00:21.779824 Enter into PICG configuration >>>>
6164 14:00:21.782948 Exit from PICG configuration <<<<
6165 14:00:21.786753 [RX_INPUT] configuration >>>>>
6166 14:00:21.787187 [RX_INPUT] configuration <<<<<
6167 14:00:21.792872 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6168 14:00:21.799960 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6169 14:00:21.803473 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 14:00:21.809961 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 14:00:21.816403 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 14:00:21.823439 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 14:00:21.826674 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6174 14:00:21.829515 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6175 14:00:21.836101 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6176 14:00:21.839817 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6177 14:00:21.843210 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6178 14:00:21.846211 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 14:00:21.849811 ===================================
6180 14:00:21.852702 LPDDR4 DRAM CONFIGURATION
6181 14:00:21.856623 ===================================
6182 14:00:21.860090 EX_ROW_EN[0] = 0x0
6183 14:00:21.860309 EX_ROW_EN[1] = 0x0
6184 14:00:21.862853 LP4Y_EN = 0x0
6185 14:00:21.863073 WORK_FSP = 0x0
6186 14:00:21.866416 WL = 0x2
6187 14:00:21.866720 RL = 0x2
6188 14:00:21.869854 BL = 0x2
6189 14:00:21.870075 RPST = 0x0
6190 14:00:21.873389 RD_PRE = 0x0
6191 14:00:21.873703 WR_PRE = 0x1
6192 14:00:21.876451 WR_PST = 0x0
6193 14:00:21.879781 DBI_WR = 0x0
6194 14:00:21.880146 DBI_RD = 0x0
6195 14:00:21.883395 OTF = 0x1
6196 14:00:21.886511 ===================================
6197 14:00:21.889983 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6198 14:00:21.893415 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6199 14:00:21.896613 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 14:00:21.900267 ===================================
6201 14:00:21.903029 LPDDR4 DRAM CONFIGURATION
6202 14:00:21.906790 ===================================
6203 14:00:21.909894 EX_ROW_EN[0] = 0x10
6204 14:00:21.910349 EX_ROW_EN[1] = 0x0
6205 14:00:21.913078 LP4Y_EN = 0x0
6206 14:00:21.913488 WORK_FSP = 0x0
6207 14:00:21.916739 WL = 0x2
6208 14:00:21.917152 RL = 0x2
6209 14:00:21.920522 BL = 0x2
6210 14:00:21.921046 RPST = 0x0
6211 14:00:21.923101 RD_PRE = 0x0
6212 14:00:21.923517 WR_PRE = 0x1
6213 14:00:21.927125 WR_PST = 0x0
6214 14:00:21.927552 DBI_WR = 0x0
6215 14:00:21.930465 DBI_RD = 0x0
6216 14:00:21.930976 OTF = 0x1
6217 14:00:21.933194 ===================================
6218 14:00:21.940016 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6219 14:00:21.944636 nWR fixed to 30
6220 14:00:21.948182 [ModeRegInit_LP4] CH0 RK0
6221 14:00:21.948697 [ModeRegInit_LP4] CH0 RK1
6222 14:00:21.951150 [ModeRegInit_LP4] CH1 RK0
6223 14:00:21.954732 [ModeRegInit_LP4] CH1 RK1
6224 14:00:21.955143 match AC timing 19
6225 14:00:21.961611 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6226 14:00:21.965182 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6227 14:00:21.967765 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6228 14:00:21.974967 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6229 14:00:21.978141 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6230 14:00:21.978711 ==
6231 14:00:21.981505 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 14:00:21.985136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 14:00:21.985683 ==
6234 14:00:21.991129 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 14:00:21.998555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6236 14:00:22.000980 [CA 0] Center 36 (8~64) winsize 57
6237 14:00:22.004803 [CA 1] Center 36 (8~64) winsize 57
6238 14:00:22.005264 [CA 2] Center 36 (8~64) winsize 57
6239 14:00:22.008113 [CA 3] Center 36 (8~64) winsize 57
6240 14:00:22.011589 [CA 4] Center 36 (8~64) winsize 57
6241 14:00:22.014493 [CA 5] Center 36 (8~64) winsize 57
6242 14:00:22.014958
6243 14:00:22.018112 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6244 14:00:22.018723
6245 14:00:22.024533 [CATrainingPosCal] consider 1 rank data
6246 14:00:22.025097 u2DelayCellTimex100 = 270/100 ps
6247 14:00:22.027725 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 14:00:22.034758 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 14:00:22.038560 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 14:00:22.041643 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 14:00:22.045099 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 14:00:22.048007 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 14:00:22.048565
6254 14:00:22.052181 CA PerBit enable=1, Macro0, CA PI delay=36
6255 14:00:22.052742
6256 14:00:22.054594 [CBTSetCACLKResult] CA Dly = 36
6257 14:00:22.055055 CS Dly: 1 (0~32)
6258 14:00:22.058241 ==
6259 14:00:22.061661 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 14:00:22.064804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 14:00:22.065406 ==
6262 14:00:22.067708 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 14:00:22.074819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6264 14:00:22.078455 [CA 0] Center 36 (8~64) winsize 57
6265 14:00:22.081941 [CA 1] Center 36 (8~64) winsize 57
6266 14:00:22.084478 [CA 2] Center 36 (8~64) winsize 57
6267 14:00:22.088594 [CA 3] Center 36 (8~64) winsize 57
6268 14:00:22.091732 [CA 4] Center 36 (8~64) winsize 57
6269 14:00:22.095273 [CA 5] Center 36 (8~64) winsize 57
6270 14:00:22.095824
6271 14:00:22.098063 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6272 14:00:22.098656
6273 14:00:22.101662 [CATrainingPosCal] consider 2 rank data
6274 14:00:22.104699 u2DelayCellTimex100 = 270/100 ps
6275 14:00:22.107985 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 14:00:22.111301 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 14:00:22.114975 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 14:00:22.118373 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 14:00:22.121078 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 14:00:22.128539 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 14:00:22.129097
6282 14:00:22.131118 CA PerBit enable=1, Macro0, CA PI delay=36
6283 14:00:22.131593
6284 14:00:22.135031 [CBTSetCACLKResult] CA Dly = 36
6285 14:00:22.135585 CS Dly: 1 (0~32)
6286 14:00:22.135956
6287 14:00:22.138192 ----->DramcWriteLeveling(PI) begin...
6288 14:00:22.138776 ==
6289 14:00:22.141089 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 14:00:22.144577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 14:00:22.148185 ==
6292 14:00:22.148742 Write leveling (Byte 0): 40 => 8
6293 14:00:22.151532 Write leveling (Byte 1): 32 => 0
6294 14:00:22.154534 DramcWriteLeveling(PI) end<-----
6295 14:00:22.154989
6296 14:00:22.155344 ==
6297 14:00:22.157651 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 14:00:22.164697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 14:00:22.165112 ==
6300 14:00:22.165437 [Gating] SW mode calibration
6301 14:00:22.174566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6302 14:00:22.178047 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6303 14:00:22.181281 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 14:00:22.188350 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 14:00:22.191646 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 14:00:22.194327 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 14:00:22.201314 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 14:00:22.204526 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 14:00:22.208066 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 14:00:22.214666 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 14:00:22.218047 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 14:00:22.221377 Total UI for P1: 0, mck2ui 16
6313 14:00:22.225058 best dqsien dly found for B0: ( 0, 14, 24)
6314 14:00:22.228634 Total UI for P1: 0, mck2ui 16
6315 14:00:22.231887 best dqsien dly found for B1: ( 0, 14, 24)
6316 14:00:22.235123 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6317 14:00:22.238140 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6318 14:00:22.238601
6319 14:00:22.241704 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 14:00:22.244525 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 14:00:22.247795 [Gating] SW calibration Done
6322 14:00:22.248214 ==
6323 14:00:22.251806 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 14:00:22.254766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 14:00:22.258153 ==
6326 14:00:22.258617 RX Vref Scan: 0
6327 14:00:22.258953
6328 14:00:22.261326 RX Vref 0 -> 0, step: 1
6329 14:00:22.261742
6330 14:00:22.264842 RX Delay -410 -> 252, step: 16
6331 14:00:22.268219 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6332 14:00:22.271706 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6333 14:00:22.274629 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6334 14:00:22.281230 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6335 14:00:22.284619 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6336 14:00:22.287993 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6337 14:00:22.291306 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6338 14:00:22.297777 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6339 14:00:22.301310 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6340 14:00:22.304587 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6341 14:00:22.307798 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6342 14:00:22.314573 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6343 14:00:22.317971 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6344 14:00:22.321488 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6345 14:00:22.324612 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6346 14:00:22.331138 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6347 14:00:22.331632 ==
6348 14:00:22.334318 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 14:00:22.337651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 14:00:22.338165 ==
6351 14:00:22.338639 DQS Delay:
6352 14:00:22.341412 DQS0 = 35, DQS1 = 51
6353 14:00:22.341840 DQM Delay:
6354 14:00:22.345004 DQM0 = 8, DQM1 = 10
6355 14:00:22.345448 DQ Delay:
6356 14:00:22.347700 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6357 14:00:22.351313 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6358 14:00:22.354528 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6359 14:00:22.357603 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6360 14:00:22.358239
6361 14:00:22.358692
6362 14:00:22.359120 ==
6363 14:00:22.361157 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 14:00:22.364434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 14:00:22.365003 ==
6366 14:00:22.365544
6367 14:00:22.365986
6368 14:00:22.367828 TX Vref Scan disable
6369 14:00:22.368239 == TX Byte 0 ==
6370 14:00:22.374900 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 14:00:22.377556 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 14:00:22.378111 == TX Byte 1 ==
6373 14:00:22.384633 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6374 14:00:22.387793 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6375 14:00:22.388205 ==
6376 14:00:22.390828 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 14:00:22.394297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 14:00:22.394762 ==
6379 14:00:22.395162
6380 14:00:22.395757
6381 14:00:22.397527 TX Vref Scan disable
6382 14:00:22.401399 == TX Byte 0 ==
6383 14:00:22.404371 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 14:00:22.407796 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 14:00:22.410779 == TX Byte 1 ==
6386 14:00:22.414897 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6387 14:00:22.417829 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6388 14:00:22.418252
6389 14:00:22.418727 [DATLAT]
6390 14:00:22.421337 Freq=400, CH0 RK0
6391 14:00:22.421773
6392 14:00:22.422100 DATLAT Default: 0xf
6393 14:00:22.424377 0, 0xFFFF, sum = 0
6394 14:00:22.424797 1, 0xFFFF, sum = 0
6395 14:00:22.428004 2, 0xFFFF, sum = 0
6396 14:00:22.428422 3, 0xFFFF, sum = 0
6397 14:00:22.431339 4, 0xFFFF, sum = 0
6398 14:00:22.434822 5, 0xFFFF, sum = 0
6399 14:00:22.435242 6, 0xFFFF, sum = 0
6400 14:00:22.437799 7, 0xFFFF, sum = 0
6401 14:00:22.438220 8, 0xFFFF, sum = 0
6402 14:00:22.441319 9, 0xFFFF, sum = 0
6403 14:00:22.441745 10, 0xFFFF, sum = 0
6404 14:00:22.444810 11, 0xFFFF, sum = 0
6405 14:00:22.445339 12, 0xFFFF, sum = 0
6406 14:00:22.447803 13, 0x0, sum = 1
6407 14:00:22.448222 14, 0x0, sum = 2
6408 14:00:22.451233 15, 0x0, sum = 3
6409 14:00:22.451836 16, 0x0, sum = 4
6410 14:00:22.452322 best_step = 14
6411 14:00:22.454545
6412 14:00:22.454959 ==
6413 14:00:22.458038 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 14:00:22.461254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 14:00:22.461831 ==
6416 14:00:22.462347 RX Vref Scan: 1
6417 14:00:22.462742
6418 14:00:22.464724 RX Vref 0 -> 0, step: 1
6419 14:00:22.465139
6420 14:00:22.468027 RX Delay -343 -> 252, step: 8
6421 14:00:22.468505
6422 14:00:22.471564 Set Vref, RX VrefLevel [Byte0]: 54
6423 14:00:22.474550 [Byte1]: 51
6424 14:00:22.478456
6425 14:00:22.479066 Final RX Vref Byte 0 = 54 to rank0
6426 14:00:22.481541 Final RX Vref Byte 1 = 51 to rank0
6427 14:00:22.484985 Final RX Vref Byte 0 = 54 to rank1
6428 14:00:22.488371 Final RX Vref Byte 1 = 51 to rank1==
6429 14:00:22.491546 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 14:00:22.495096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 14:00:22.498292 ==
6432 14:00:22.498776 DQS Delay:
6433 14:00:22.499269 DQS0 = 44, DQS1 = 56
6434 14:00:22.501538 DQM Delay:
6435 14:00:22.501959 DQM0 = 11, DQM1 = 12
6436 14:00:22.505025 DQ Delay:
6437 14:00:22.508412 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6438 14:00:22.509018 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6439 14:00:22.511740 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6440 14:00:22.514757 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6441 14:00:22.515248
6442 14:00:22.515676
6443 14:00:22.524849 [DQSOSCAuto] RK0, (LSB)MR18= 0x8755, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
6444 14:00:22.528447 CH0 RK0: MR19=C0C, MR18=8755
6445 14:00:22.535081 CH0_RK0: MR19=0xC0C, MR18=0x8755, DQSOSC=392, MR23=63, INC=384, DEC=256
6446 14:00:22.535501 ==
6447 14:00:22.538670 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 14:00:22.541987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 14:00:22.542524 ==
6450 14:00:22.544929 [Gating] SW mode calibration
6451 14:00:22.552531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6452 14:00:22.555470 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6453 14:00:22.562216 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 14:00:22.565204 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 14:00:22.568656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 14:00:22.574887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 14:00:22.578780 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 14:00:22.582229 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 14:00:22.588756 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 14:00:22.591919 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 14:00:22.595286 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 14:00:22.598568 Total UI for P1: 0, mck2ui 16
6463 14:00:22.601844 best dqsien dly found for B0: ( 0, 14, 24)
6464 14:00:22.605033 Total UI for P1: 0, mck2ui 16
6465 14:00:22.608644 best dqsien dly found for B1: ( 0, 14, 24)
6466 14:00:22.611529 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6467 14:00:22.615621 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6468 14:00:22.616069
6469 14:00:22.618921 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 14:00:22.625731 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 14:00:22.626175 [Gating] SW calibration Done
6472 14:00:22.626661 ==
6473 14:00:22.628821 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 14:00:22.635551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 14:00:22.635986 ==
6476 14:00:22.636425 RX Vref Scan: 0
6477 14:00:22.636839
6478 14:00:22.638741 RX Vref 0 -> 0, step: 1
6479 14:00:22.639173
6480 14:00:22.642311 RX Delay -410 -> 252, step: 16
6481 14:00:22.645190 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6482 14:00:22.648597 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6483 14:00:22.655700 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6484 14:00:22.658763 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6485 14:00:22.662177 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6486 14:00:22.665522 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6487 14:00:22.671618 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6488 14:00:22.675460 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6489 14:00:22.678603 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6490 14:00:22.682252 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6491 14:00:22.688653 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6492 14:00:22.692327 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6493 14:00:22.694964 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6494 14:00:22.698641 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6495 14:00:22.704915 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6496 14:00:22.708736 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6497 14:00:22.709196 ==
6498 14:00:22.711790 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 14:00:22.715426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 14:00:22.715890 ==
6501 14:00:22.718730 DQS Delay:
6502 14:00:22.719174 DQS0 = 43, DQS1 = 51
6503 14:00:22.721791 DQM Delay:
6504 14:00:22.722221 DQM0 = 11, DQM1 = 10
6505 14:00:22.722706 DQ Delay:
6506 14:00:22.725223 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6507 14:00:22.728737 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6508 14:00:22.731643 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6509 14:00:22.734824 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6510 14:00:22.735253
6511 14:00:22.735686
6512 14:00:22.736094 ==
6513 14:00:22.738150 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 14:00:22.742045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 14:00:22.745332 ==
6516 14:00:22.745808
6517 14:00:22.746317
6518 14:00:22.746770 TX Vref Scan disable
6519 14:00:22.748435 == TX Byte 0 ==
6520 14:00:22.751857 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6521 14:00:22.755172 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6522 14:00:22.758706 == TX Byte 1 ==
6523 14:00:22.763525 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6524 14:00:22.765460 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6525 14:00:22.765889 ==
6526 14:00:22.769044 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 14:00:22.771692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 14:00:22.772124 ==
6529 14:00:22.775255
6530 14:00:22.775683
6531 14:00:22.776124 TX Vref Scan disable
6532 14:00:22.778467 == TX Byte 0 ==
6533 14:00:22.782019 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6534 14:00:22.785164 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6535 14:00:22.788497 == TX Byte 1 ==
6536 14:00:22.792084 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6537 14:00:22.795314 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6538 14:00:22.795742
6539 14:00:22.796174 [DATLAT]
6540 14:00:22.798506 Freq=400, CH0 RK1
6541 14:00:22.798936
6542 14:00:22.799370 DATLAT Default: 0xe
6543 14:00:22.802451 0, 0xFFFF, sum = 0
6544 14:00:22.802889 1, 0xFFFF, sum = 0
6545 14:00:22.805562 2, 0xFFFF, sum = 0
6546 14:00:22.808315 3, 0xFFFF, sum = 0
6547 14:00:22.808748 4, 0xFFFF, sum = 0
6548 14:00:22.812207 5, 0xFFFF, sum = 0
6549 14:00:22.812642 6, 0xFFFF, sum = 0
6550 14:00:22.815601 7, 0xFFFF, sum = 0
6551 14:00:22.816038 8, 0xFFFF, sum = 0
6552 14:00:22.818675 9, 0xFFFF, sum = 0
6553 14:00:22.819197 10, 0xFFFF, sum = 0
6554 14:00:22.822154 11, 0xFFFF, sum = 0
6555 14:00:22.822644 12, 0xFFFF, sum = 0
6556 14:00:22.825565 13, 0x0, sum = 1
6557 14:00:22.826002 14, 0x0, sum = 2
6558 14:00:22.828569 15, 0x0, sum = 3
6559 14:00:22.829003 16, 0x0, sum = 4
6560 14:00:22.829444 best_step = 14
6561 14:00:22.831862
6562 14:00:22.832278 ==
6563 14:00:22.835351 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 14:00:22.838503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 14:00:22.838922 ==
6566 14:00:22.839249 RX Vref Scan: 0
6567 14:00:22.839556
6568 14:00:22.842431 RX Vref 0 -> 0, step: 1
6569 14:00:22.842872
6570 14:00:22.845416 RX Delay -343 -> 252, step: 8
6571 14:00:22.852424 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6572 14:00:22.855801 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6573 14:00:22.859639 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6574 14:00:22.863013 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6575 14:00:22.869199 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6576 14:00:22.872747 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6577 14:00:22.876993 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6578 14:00:22.880024 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6579 14:00:22.886201 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6580 14:00:22.889806 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6581 14:00:22.892583 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6582 14:00:22.895923 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6583 14:00:22.903013 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6584 14:00:22.905612 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6585 14:00:22.909900 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6586 14:00:22.912563 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6587 14:00:22.915508 ==
6588 14:00:22.915710 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 14:00:22.922382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 14:00:22.922582 ==
6591 14:00:22.922725 DQS Delay:
6592 14:00:22.925886 DQS0 = 48, DQS1 = 60
6593 14:00:22.926065 DQM Delay:
6594 14:00:22.929791 DQM0 = 13, DQM1 = 13
6595 14:00:22.929971 DQ Delay:
6596 14:00:22.932966 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6597 14:00:22.936035 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6598 14:00:22.939123 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6599 14:00:22.942461 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6600 14:00:22.942717
6601 14:00:22.942915
6602 14:00:22.949387 [DQSOSCAuto] RK1, (LSB)MR18= 0x976a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6603 14:00:22.952830 CH0 RK1: MR19=C0C, MR18=976A
6604 14:00:22.959430 CH0_RK1: MR19=0xC0C, MR18=0x976A, DQSOSC=390, MR23=63, INC=388, DEC=258
6605 14:00:22.962654 [RxdqsGatingPostProcess] freq 400
6606 14:00:22.965732 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6607 14:00:22.969130 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 14:00:22.972791 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 14:00:22.975688 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 14:00:22.979413 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 14:00:22.982641 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 14:00:22.986197 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 14:00:22.989721 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 14:00:22.992828 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 14:00:22.996113 Pre-setting of DQS Precalculation
6616 14:00:22.999050 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6617 14:00:22.999466 ==
6618 14:00:23.002597 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 14:00:23.009535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 14:00:23.010100 ==
6621 14:00:23.013077 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 14:00:23.019559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6623 14:00:23.022751 [CA 0] Center 36 (8~64) winsize 57
6624 14:00:23.026456 [CA 1] Center 36 (8~64) winsize 57
6625 14:00:23.029502 [CA 2] Center 36 (8~64) winsize 57
6626 14:00:23.032755 [CA 3] Center 36 (8~64) winsize 57
6627 14:00:23.036022 [CA 4] Center 36 (8~64) winsize 57
6628 14:00:23.039736 [CA 5] Center 36 (8~64) winsize 57
6629 14:00:23.040150
6630 14:00:23.042578 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6631 14:00:23.042993
6632 14:00:23.045952 [CATrainingPosCal] consider 1 rank data
6633 14:00:23.049246 u2DelayCellTimex100 = 270/100 ps
6634 14:00:23.052525 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 14:00:23.056047 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 14:00:23.059273 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 14:00:23.062883 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 14:00:23.066132 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 14:00:23.070237 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 14:00:23.070869
6641 14:00:23.075751 CA PerBit enable=1, Macro0, CA PI delay=36
6642 14:00:23.076312
6643 14:00:23.079284 [CBTSetCACLKResult] CA Dly = 36
6644 14:00:23.079820 CS Dly: 1 (0~32)
6645 14:00:23.080306 ==
6646 14:00:23.082726 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 14:00:23.085927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 14:00:23.086525 ==
6649 14:00:23.092673 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 14:00:23.099127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6651 14:00:23.102312 [CA 0] Center 36 (8~64) winsize 57
6652 14:00:23.105950 [CA 1] Center 36 (8~64) winsize 57
6653 14:00:23.109416 [CA 2] Center 36 (8~64) winsize 57
6654 14:00:23.112830 [CA 3] Center 36 (8~64) winsize 57
6655 14:00:23.113010 [CA 4] Center 36 (8~64) winsize 57
6656 14:00:23.115517 [CA 5] Center 36 (8~64) winsize 57
6657 14:00:23.115757
6658 14:00:23.122546 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6659 14:00:23.122727
6660 14:00:23.125903 [CATrainingPosCal] consider 2 rank data
6661 14:00:23.128878 u2DelayCellTimex100 = 270/100 ps
6662 14:00:23.132223 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 14:00:23.136155 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 14:00:23.139360 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 14:00:23.142595 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 14:00:23.145644 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 14:00:23.149205 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 14:00:23.149384
6669 14:00:23.152269 CA PerBit enable=1, Macro0, CA PI delay=36
6670 14:00:23.152448
6671 14:00:23.155691 [CBTSetCACLKResult] CA Dly = 36
6672 14:00:23.159436 CS Dly: 1 (0~32)
6673 14:00:23.159615
6674 14:00:23.162816 ----->DramcWriteLeveling(PI) begin...
6675 14:00:23.163000 ==
6676 14:00:23.165853 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 14:00:23.169107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 14:00:23.169289 ==
6679 14:00:23.172852 Write leveling (Byte 0): 40 => 8
6680 14:00:23.175997 Write leveling (Byte 1): 40 => 8
6681 14:00:23.178886 DramcWriteLeveling(PI) end<-----
6682 14:00:23.179066
6683 14:00:23.179206 ==
6684 14:00:23.182191 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 14:00:23.185721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 14:00:23.185902 ==
6687 14:00:23.189162 [Gating] SW mode calibration
6688 14:00:23.195676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6689 14:00:23.202442 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6690 14:00:23.206143 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 14:00:23.208997 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6692 14:00:23.215773 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 14:00:23.218956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 14:00:23.222073 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 14:00:23.229004 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 14:00:23.232367 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 14:00:23.235986 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 14:00:23.242444 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 14:00:23.242624 Total UI for P1: 0, mck2ui 16
6700 14:00:23.245418 best dqsien dly found for B0: ( 0, 14, 24)
6701 14:00:23.249101 Total UI for P1: 0, mck2ui 16
6702 14:00:23.252121 best dqsien dly found for B1: ( 0, 14, 24)
6703 14:00:23.255825 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6704 14:00:23.262243 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6705 14:00:23.262448
6706 14:00:23.265815 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 14:00:23.268772 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 14:00:23.272826 [Gating] SW calibration Done
6709 14:00:23.272954 ==
6710 14:00:23.276058 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 14:00:23.278894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 14:00:23.279024 ==
6713 14:00:23.279124 RX Vref Scan: 0
6714 14:00:23.282268
6715 14:00:23.282394 RX Vref 0 -> 0, step: 1
6716 14:00:23.282506
6717 14:00:23.285787 RX Delay -410 -> 252, step: 16
6718 14:00:23.289127 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6719 14:00:23.295542 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6720 14:00:23.298841 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6721 14:00:23.302409 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6722 14:00:23.305554 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6723 14:00:23.312387 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6724 14:00:23.315623 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6725 14:00:23.318841 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6726 14:00:23.323111 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6727 14:00:23.329456 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6728 14:00:23.332725 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6729 14:00:23.336157 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6730 14:00:23.339863 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6731 14:00:23.346060 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6732 14:00:23.349406 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6733 14:00:23.352632 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6734 14:00:23.353047 ==
6735 14:00:23.356123 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 14:00:23.359279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 14:00:23.363702 ==
6738 14:00:23.364117 DQS Delay:
6739 14:00:23.364511 DQS0 = 51, DQS1 = 59
6740 14:00:23.366326 DQM Delay:
6741 14:00:23.366772 DQM0 = 19, DQM1 = 16
6742 14:00:23.369037 DQ Delay:
6743 14:00:23.369451 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6744 14:00:23.372442 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6745 14:00:23.376249 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6746 14:00:23.379161 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6747 14:00:23.379454
6748 14:00:23.379683
6749 14:00:23.382607 ==
6750 14:00:23.385909 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 14:00:23.389096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 14:00:23.389395 ==
6753 14:00:23.389627
6754 14:00:23.389847
6755 14:00:23.393096 TX Vref Scan disable
6756 14:00:23.393387 == TX Byte 0 ==
6757 14:00:23.395865 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 14:00:23.402618 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 14:00:23.403031 == TX Byte 1 ==
6760 14:00:23.406372 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 14:00:23.409617 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 14:00:23.412432 ==
6763 14:00:23.415891 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 14:00:23.419389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 14:00:23.419800 ==
6766 14:00:23.420152
6767 14:00:23.420490
6768 14:00:23.423418 TX Vref Scan disable
6769 14:00:23.423814 == TX Byte 0 ==
6770 14:00:23.425861 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 14:00:23.432493 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 14:00:23.432929 == TX Byte 1 ==
6773 14:00:23.435942 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 14:00:23.439375 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 14:00:23.442315
6776 14:00:23.442508 [DATLAT]
6777 14:00:23.442650 Freq=400, CH1 RK0
6778 14:00:23.442784
6779 14:00:23.445425 DATLAT Default: 0xf
6780 14:00:23.445666 0, 0xFFFF, sum = 0
6781 14:00:23.448932 1, 0xFFFF, sum = 0
6782 14:00:23.449183 2, 0xFFFF, sum = 0
6783 14:00:23.452318 3, 0xFFFF, sum = 0
6784 14:00:23.452566 4, 0xFFFF, sum = 0
6785 14:00:23.455806 5, 0xFFFF, sum = 0
6786 14:00:23.455989 6, 0xFFFF, sum = 0
6787 14:00:23.459138 7, 0xFFFF, sum = 0
6788 14:00:23.462508 8, 0xFFFF, sum = 0
6789 14:00:23.463127 9, 0xFFFF, sum = 0
6790 14:00:23.466239 10, 0xFFFF, sum = 0
6791 14:00:23.466727 11, 0xFFFF, sum = 0
6792 14:00:23.469257 12, 0xFFFF, sum = 0
6793 14:00:23.469772 13, 0x0, sum = 1
6794 14:00:23.472822 14, 0x0, sum = 2
6795 14:00:23.473384 15, 0x0, sum = 3
6796 14:00:23.476175 16, 0x0, sum = 4
6797 14:00:23.476739 best_step = 14
6798 14:00:23.477222
6799 14:00:23.477695 ==
6800 14:00:23.479188 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 14:00:23.483052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 14:00:23.483423 ==
6803 14:00:23.485991 RX Vref Scan: 1
6804 14:00:23.486290
6805 14:00:23.489413 RX Vref 0 -> 0, step: 1
6806 14:00:23.489636
6807 14:00:23.489813 RX Delay -359 -> 252, step: 8
6808 14:00:23.489980
6809 14:00:23.492392 Set Vref, RX VrefLevel [Byte0]: 56
6810 14:00:23.496200 [Byte1]: 52
6811 14:00:23.501177
6812 14:00:23.501360 Final RX Vref Byte 0 = 56 to rank0
6813 14:00:23.504888 Final RX Vref Byte 1 = 52 to rank0
6814 14:00:23.507853 Final RX Vref Byte 0 = 56 to rank1
6815 14:00:23.511803 Final RX Vref Byte 1 = 52 to rank1==
6816 14:00:23.514373 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 14:00:23.521528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 14:00:23.521709 ==
6819 14:00:23.521849 DQS Delay:
6820 14:00:23.521981 DQS0 = 48, DQS1 = 60
6821 14:00:23.524501 DQM Delay:
6822 14:00:23.524679 DQM0 = 12, DQM1 = 12
6823 14:00:23.527930 DQ Delay:
6824 14:00:23.531290 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6825 14:00:23.531470 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6826 14:00:23.534821 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6827 14:00:23.537827 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6828 14:00:23.538004
6829 14:00:23.538142
6830 14:00:23.547992 [DQSOSCAuto] RK0, (LSB)MR18= 0x872d, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
6831 14:00:23.551645 CH1 RK0: MR19=C0C, MR18=872D
6832 14:00:23.557858 CH1_RK0: MR19=0xC0C, MR18=0x872D, DQSOSC=392, MR23=63, INC=384, DEC=256
6833 14:00:23.558036 ==
6834 14:00:23.561464 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 14:00:23.564783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 14:00:23.564962 ==
6837 14:00:23.567699 [Gating] SW mode calibration
6838 14:00:23.574323 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6839 14:00:23.577863 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6840 14:00:23.584837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 14:00:23.587988 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 14:00:23.591331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 14:00:23.598070 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 14:00:23.601091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 14:00:23.604336 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 14:00:23.611039 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 14:00:23.614262 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 14:00:23.617771 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 14:00:23.620903 Total UI for P1: 0, mck2ui 16
6850 14:00:23.624053 best dqsien dly found for B0: ( 0, 14, 24)
6851 14:00:23.627732 Total UI for P1: 0, mck2ui 16
6852 14:00:23.630570 best dqsien dly found for B1: ( 0, 14, 24)
6853 14:00:23.634659 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6854 14:00:23.638165 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6855 14:00:23.640623
6856 14:00:23.643964 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 14:00:23.647584 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 14:00:23.650536 [Gating] SW calibration Done
6859 14:00:23.650685 ==
6860 14:00:23.654719 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 14:00:23.657482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 14:00:23.657632 ==
6863 14:00:23.657750 RX Vref Scan: 0
6864 14:00:23.657860
6865 14:00:23.661018 RX Vref 0 -> 0, step: 1
6866 14:00:23.661167
6867 14:00:23.664179 RX Delay -410 -> 252, step: 16
6868 14:00:23.667441 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6869 14:00:23.674049 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6870 14:00:23.677561 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6871 14:00:23.680820 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6872 14:00:23.684083 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6873 14:00:23.690903 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6874 14:00:23.694343 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6875 14:00:23.697255 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6876 14:00:23.700613 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6877 14:00:23.707473 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6878 14:00:23.710855 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6879 14:00:23.713841 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6880 14:00:23.717324 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6881 14:00:23.724227 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6882 14:00:23.727533 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6883 14:00:23.730928 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6884 14:00:23.731445 ==
6885 14:00:23.734508 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 14:00:23.738122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 14:00:23.738551 ==
6888 14:00:23.741277 DQS Delay:
6889 14:00:23.741656 DQS0 = 43, DQS1 = 59
6890 14:00:23.744241 DQM Delay:
6891 14:00:23.744652 DQM0 = 9, DQM1 = 18
6892 14:00:23.747922 DQ Delay:
6893 14:00:23.748303 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6894 14:00:23.751290 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6895 14:00:23.754474 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6896 14:00:23.757787 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6897 14:00:23.758168
6898 14:00:23.758500
6899 14:00:23.758786 ==
6900 14:00:23.761049 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 14:00:23.768012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 14:00:23.768402 ==
6903 14:00:23.768717
6904 14:00:23.769008
6905 14:00:23.769275 TX Vref Scan disable
6906 14:00:23.771368 == TX Byte 0 ==
6907 14:00:23.774704 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6908 14:00:23.777733 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6909 14:00:23.781230 == TX Byte 1 ==
6910 14:00:23.784243 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6911 14:00:23.787747 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6912 14:00:23.788237 ==
6913 14:00:23.791105 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 14:00:23.797668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 14:00:23.798063 ==
6916 14:00:23.798371
6917 14:00:23.798792
6918 14:00:23.799084 TX Vref Scan disable
6919 14:00:23.800934 == TX Byte 0 ==
6920 14:00:23.804857 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6921 14:00:23.808448 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6922 14:00:23.811248 == TX Byte 1 ==
6923 14:00:23.814647 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6924 14:00:23.817727 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6925 14:00:23.818095
6926 14:00:23.821193 [DATLAT]
6927 14:00:23.821468 Freq=400, CH1 RK1
6928 14:00:23.821686
6929 14:00:23.824062 DATLAT Default: 0xe
6930 14:00:23.824352 0, 0xFFFF, sum = 0
6931 14:00:23.827785 1, 0xFFFF, sum = 0
6932 14:00:23.828121 2, 0xFFFF, sum = 0
6933 14:00:23.831202 3, 0xFFFF, sum = 0
6934 14:00:23.831537 4, 0xFFFF, sum = 0
6935 14:00:23.834383 5, 0xFFFF, sum = 0
6936 14:00:23.834752 6, 0xFFFF, sum = 0
6937 14:00:23.837786 7, 0xFFFF, sum = 0
6938 14:00:23.838117 8, 0xFFFF, sum = 0
6939 14:00:23.841377 9, 0xFFFF, sum = 0
6940 14:00:23.841674 10, 0xFFFF, sum = 0
6941 14:00:23.844135 11, 0xFFFF, sum = 0
6942 14:00:23.844415 12, 0xFFFF, sum = 0
6943 14:00:23.847680 13, 0x0, sum = 1
6944 14:00:23.847910 14, 0x0, sum = 2
6945 14:00:23.850755 15, 0x0, sum = 3
6946 14:00:23.850968 16, 0x0, sum = 4
6947 14:00:23.854564 best_step = 14
6948 14:00:23.854787
6949 14:00:23.854992 ==
6950 14:00:23.857393 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 14:00:23.860876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 14:00:23.861095 ==
6953 14:00:23.864474 RX Vref Scan: 0
6954 14:00:23.864685
6955 14:00:23.864849 RX Vref 0 -> 0, step: 1
6956 14:00:23.865079
6957 14:00:23.867626 RX Delay -359 -> 252, step: 8
6958 14:00:23.875977 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6959 14:00:23.878919 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6960 14:00:23.882560 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6961 14:00:23.886175 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6962 14:00:23.892386 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6963 14:00:23.895853 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6964 14:00:23.899441 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6965 14:00:23.902430 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6966 14:00:23.908850 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6967 14:00:23.912064 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6968 14:00:23.915459 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6969 14:00:23.919039 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6970 14:00:23.925595 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6971 14:00:23.929194 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6972 14:00:23.932641 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6973 14:00:23.935806 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6974 14:00:23.939183 ==
6975 14:00:23.942583 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 14:00:23.945510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 14:00:23.945753 ==
6978 14:00:23.945927 DQS Delay:
6979 14:00:23.949218 DQS0 = 48, DQS1 = 56
6980 14:00:23.949430 DQM Delay:
6981 14:00:23.952491 DQM0 = 9, DQM1 = 9
6982 14:00:23.952750 DQ Delay:
6983 14:00:23.955835 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6984 14:00:23.958780 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
6985 14:00:23.962729 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6986 14:00:23.965741 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6987 14:00:23.965940
6988 14:00:23.966104
6989 14:00:23.972143 [DQSOSCAuto] RK1, (LSB)MR18= 0x7990, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6990 14:00:23.975548 CH1 RK1: MR19=C0C, MR18=7990
6991 14:00:23.982298 CH1_RK1: MR19=0xC0C, MR18=0x7990, DQSOSC=391, MR23=63, INC=386, DEC=257
6992 14:00:23.985428 [RxdqsGatingPostProcess] freq 400
6993 14:00:23.989684 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6994 14:00:23.992361 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 14:00:23.995723 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 14:00:23.999189 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 14:00:24.002183 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 14:00:24.005638 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 14:00:24.008887 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 14:00:24.012186 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 14:00:24.015542 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 14:00:24.018791 Pre-setting of DQS Precalculation
7003 14:00:24.022832 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7004 14:00:24.029536 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7005 14:00:24.039488 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7006 14:00:24.039776
7007 14:00:24.040022
7008 14:00:24.042328 [Calibration Summary] 800 Mbps
7009 14:00:24.042570 CH 0, Rank 0
7010 14:00:24.045800 SW Impedance : PASS
7011 14:00:24.046008 DUTY Scan : NO K
7012 14:00:24.049072 ZQ Calibration : PASS
7013 14:00:24.049295 Jitter Meter : NO K
7014 14:00:24.052504 CBT Training : PASS
7015 14:00:24.055713 Write leveling : PASS
7016 14:00:24.055972 RX DQS gating : PASS
7017 14:00:24.059078 RX DQ/DQS(RDDQC) : PASS
7018 14:00:24.062465 TX DQ/DQS : PASS
7019 14:00:24.062720 RX DATLAT : PASS
7020 14:00:24.065854 RX DQ/DQS(Engine): PASS
7021 14:00:24.069272 TX OE : NO K
7022 14:00:24.069490 All Pass.
7023 14:00:24.069655
7024 14:00:24.069806 CH 0, Rank 1
7025 14:00:24.072744 SW Impedance : PASS
7026 14:00:24.075853 DUTY Scan : NO K
7027 14:00:24.076173 ZQ Calibration : PASS
7028 14:00:24.079420 Jitter Meter : NO K
7029 14:00:24.082563 CBT Training : PASS
7030 14:00:24.082795 Write leveling : NO K
7031 14:00:24.086075 RX DQS gating : PASS
7032 14:00:24.086284 RX DQ/DQS(RDDQC) : PASS
7033 14:00:24.089536 TX DQ/DQS : PASS
7034 14:00:24.092451 RX DATLAT : PASS
7035 14:00:24.092667 RX DQ/DQS(Engine): PASS
7036 14:00:24.095947 TX OE : NO K
7037 14:00:24.096245 All Pass.
7038 14:00:24.096453
7039 14:00:24.099985 CH 1, Rank 0
7040 14:00:24.100296 SW Impedance : PASS
7041 14:00:24.102643 DUTY Scan : NO K
7042 14:00:24.105604 ZQ Calibration : PASS
7043 14:00:24.105818 Jitter Meter : NO K
7044 14:00:24.109306 CBT Training : PASS
7045 14:00:24.112226 Write leveling : PASS
7046 14:00:24.112438 RX DQS gating : PASS
7047 14:00:24.116137 RX DQ/DQS(RDDQC) : PASS
7048 14:00:24.119652 TX DQ/DQS : PASS
7049 14:00:24.119876 RX DATLAT : PASS
7050 14:00:24.122564 RX DQ/DQS(Engine): PASS
7051 14:00:24.125495 TX OE : NO K
7052 14:00:24.125768 All Pass.
7053 14:00:24.125940
7054 14:00:24.126097 CH 1, Rank 1
7055 14:00:24.129226 SW Impedance : PASS
7056 14:00:24.132923 DUTY Scan : NO K
7057 14:00:24.133167 ZQ Calibration : PASS
7058 14:00:24.135990 Jitter Meter : NO K
7059 14:00:24.136198 CBT Training : PASS
7060 14:00:24.138841 Write leveling : NO K
7061 14:00:24.142198 RX DQS gating : PASS
7062 14:00:24.142424 RX DQ/DQS(RDDQC) : PASS
7063 14:00:24.145506 TX DQ/DQS : PASS
7064 14:00:24.148730 RX DATLAT : PASS
7065 14:00:24.148960 RX DQ/DQS(Engine): PASS
7066 14:00:24.152497 TX OE : NO K
7067 14:00:24.152705 All Pass.
7068 14:00:24.152867
7069 14:00:24.155583 DramC Write-DBI off
7070 14:00:24.158983 PER_BANK_REFRESH: Hybrid Mode
7071 14:00:24.159194 TX_TRACKING: ON
7072 14:00:24.169514 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7073 14:00:24.172384 [FAST_K] Save calibration result to emmc
7074 14:00:24.175893 dramc_set_vcore_voltage set vcore to 725000
7075 14:00:24.179396 Read voltage for 1600, 0
7076 14:00:24.179604 Vio18 = 0
7077 14:00:24.179785 Vcore = 725000
7078 14:00:24.182442 Vdram = 0
7079 14:00:24.182713 Vddq = 0
7080 14:00:24.182946 Vmddr = 0
7081 14:00:24.189192 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7082 14:00:24.192721 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7083 14:00:24.196235 MEM_TYPE=3, freq_sel=13
7084 14:00:24.199160 sv_algorithm_assistance_LP4_3733
7085 14:00:24.202533 ============ PULL DRAM RESETB DOWN ============
7086 14:00:24.205914 ========== PULL DRAM RESETB DOWN end =========
7087 14:00:24.212310 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7088 14:00:24.216154 ===================================
7089 14:00:24.216511 LPDDR4 DRAM CONFIGURATION
7090 14:00:24.219738 ===================================
7091 14:00:24.222549 EX_ROW_EN[0] = 0x0
7092 14:00:24.225787 EX_ROW_EN[1] = 0x0
7093 14:00:24.226052 LP4Y_EN = 0x0
7094 14:00:24.229397 WORK_FSP = 0x1
7095 14:00:24.229710 WL = 0x5
7096 14:00:24.232664 RL = 0x5
7097 14:00:24.232914 BL = 0x2
7098 14:00:24.235702 RPST = 0x0
7099 14:00:24.235994 RD_PRE = 0x0
7100 14:00:24.239486 WR_PRE = 0x1
7101 14:00:24.239754 WR_PST = 0x1
7102 14:00:24.242511 DBI_WR = 0x0
7103 14:00:24.242771 DBI_RD = 0x0
7104 14:00:24.245937 OTF = 0x1
7105 14:00:24.249150 ===================================
7106 14:00:24.252771 ===================================
7107 14:00:24.253024 ANA top config
7108 14:00:24.256113 ===================================
7109 14:00:24.259792 DLL_ASYNC_EN = 0
7110 14:00:24.263085 ALL_SLAVE_EN = 0
7111 14:00:24.263340 NEW_RANK_MODE = 1
7112 14:00:24.265897 DLL_IDLE_MODE = 1
7113 14:00:24.269361 LP45_APHY_COMB_EN = 1
7114 14:00:24.272497 TX_ODT_DIS = 0
7115 14:00:24.276379 NEW_8X_MODE = 1
7116 14:00:24.276642 ===================================
7117 14:00:24.279755 ===================================
7118 14:00:24.282749 data_rate = 3200
7119 14:00:24.286109 CKR = 1
7120 14:00:24.289468 DQ_P2S_RATIO = 8
7121 14:00:24.292421 ===================================
7122 14:00:24.295809 CA_P2S_RATIO = 8
7123 14:00:24.299690 DQ_CA_OPEN = 0
7124 14:00:24.302461 DQ_SEMI_OPEN = 0
7125 14:00:24.302810 CA_SEMI_OPEN = 0
7126 14:00:24.305734 CA_FULL_RATE = 0
7127 14:00:24.309470 DQ_CKDIV4_EN = 0
7128 14:00:24.312411 CA_CKDIV4_EN = 0
7129 14:00:24.316345 CA_PREDIV_EN = 0
7130 14:00:24.318981 PH8_DLY = 12
7131 14:00:24.319333 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7132 14:00:24.322710 DQ_AAMCK_DIV = 4
7133 14:00:24.325991 CA_AAMCK_DIV = 4
7134 14:00:24.329319 CA_ADMCK_DIV = 4
7135 14:00:24.332740 DQ_TRACK_CA_EN = 0
7136 14:00:24.335881 CA_PICK = 1600
7137 14:00:24.336145 CA_MCKIO = 1600
7138 14:00:24.339209 MCKIO_SEMI = 0
7139 14:00:24.342481 PLL_FREQ = 3068
7140 14:00:24.346034 DQ_UI_PI_RATIO = 32
7141 14:00:24.348967 CA_UI_PI_RATIO = 0
7142 14:00:24.352824 ===================================
7143 14:00:24.356121 ===================================
7144 14:00:24.359103 memory_type:LPDDR4
7145 14:00:24.359374 GP_NUM : 10
7146 14:00:24.362433 SRAM_EN : 1
7147 14:00:24.362696 MD32_EN : 0
7148 14:00:24.366292 ===================================
7149 14:00:24.369052 [ANA_INIT] >>>>>>>>>>>>>>
7150 14:00:24.372356 <<<<<< [CONFIGURE PHASE]: ANA_TX
7151 14:00:24.375715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7152 14:00:24.379439 ===================================
7153 14:00:24.382568 data_rate = 3200,PCW = 0X7600
7154 14:00:24.385951 ===================================
7155 14:00:24.389303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7156 14:00:24.395713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 14:00:24.399172 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 14:00:24.405854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7159 14:00:24.408959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7160 14:00:24.412183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7161 14:00:24.412444 [ANA_INIT] flow start
7162 14:00:24.415741 [ANA_INIT] PLL >>>>>>>>
7163 14:00:24.419166 [ANA_INIT] PLL <<<<<<<<
7164 14:00:24.419427 [ANA_INIT] MIDPI >>>>>>>>
7165 14:00:24.422657 [ANA_INIT] MIDPI <<<<<<<<
7166 14:00:24.426250 [ANA_INIT] DLL >>>>>>>>
7167 14:00:24.426593 [ANA_INIT] DLL <<<<<<<<
7168 14:00:24.429031 [ANA_INIT] flow end
7169 14:00:24.432648 ============ LP4 DIFF to SE enter ============
7170 14:00:24.436346 ============ LP4 DIFF to SE exit ============
7171 14:00:24.439211 [ANA_INIT] <<<<<<<<<<<<<
7172 14:00:24.442907 [Flow] Enable top DCM control >>>>>
7173 14:00:24.446230 [Flow] Enable top DCM control <<<<<
7174 14:00:24.449366 Enable DLL master slave shuffle
7175 14:00:24.456364 ==============================================================
7176 14:00:24.456622 Gating Mode config
7177 14:00:24.462725 ==============================================================
7178 14:00:24.462987 Config description:
7179 14:00:24.472432 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7180 14:00:24.479124 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7181 14:00:24.486196 SELPH_MODE 0: By rank 1: By Phase
7182 14:00:24.489246 ==============================================================
7183 14:00:24.492480 GAT_TRACK_EN = 1
7184 14:00:24.496202 RX_GATING_MODE = 2
7185 14:00:24.499473 RX_GATING_TRACK_MODE = 2
7186 14:00:24.502563 SELPH_MODE = 1
7187 14:00:24.505752 PICG_EARLY_EN = 1
7188 14:00:24.509113 VALID_LAT_VALUE = 1
7189 14:00:24.512385 ==============================================================
7190 14:00:24.515963 Enter into Gating configuration >>>>
7191 14:00:24.518880 Exit from Gating configuration <<<<
7192 14:00:24.522248 Enter into DVFS_PRE_config >>>>>
7193 14:00:24.536293 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7194 14:00:24.539012 Exit from DVFS_PRE_config <<<<<
7195 14:00:24.542276 Enter into PICG configuration >>>>
7196 14:00:24.545476 Exit from PICG configuration <<<<
7197 14:00:24.545728 [RX_INPUT] configuration >>>>>
7198 14:00:24.549003 [RX_INPUT] configuration <<<<<
7199 14:00:24.555603 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7200 14:00:24.560012 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7201 14:00:24.565825 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 14:00:24.572997 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 14:00:24.579144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 14:00:24.585823 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 14:00:24.588984 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7206 14:00:24.592577 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7207 14:00:24.595830 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7208 14:00:24.602471 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7209 14:00:24.605922 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7210 14:00:24.609386 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 14:00:24.612480 ===================================
7212 14:00:24.615720 LPDDR4 DRAM CONFIGURATION
7213 14:00:24.618878 ===================================
7214 14:00:24.622474 EX_ROW_EN[0] = 0x0
7215 14:00:24.622729 EX_ROW_EN[1] = 0x0
7216 14:00:24.626443 LP4Y_EN = 0x0
7217 14:00:24.626697 WORK_FSP = 0x1
7218 14:00:24.629326 WL = 0x5
7219 14:00:24.629580 RL = 0x5
7220 14:00:24.632506 BL = 0x2
7221 14:00:24.632763 RPST = 0x0
7222 14:00:24.635791 RD_PRE = 0x0
7223 14:00:24.636048 WR_PRE = 0x1
7224 14:00:24.639418 WR_PST = 0x1
7225 14:00:24.639674 DBI_WR = 0x0
7226 14:00:24.642697 DBI_RD = 0x0
7227 14:00:24.642953 OTF = 0x1
7228 14:00:24.646034 ===================================
7229 14:00:24.649632 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7230 14:00:24.655978 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7231 14:00:24.659305 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 14:00:24.663151 ===================================
7233 14:00:24.666441 LPDDR4 DRAM CONFIGURATION
7234 14:00:24.669208 ===================================
7235 14:00:24.669466 EX_ROW_EN[0] = 0x10
7236 14:00:24.672989 EX_ROW_EN[1] = 0x0
7237 14:00:24.673246 LP4Y_EN = 0x0
7238 14:00:24.675842 WORK_FSP = 0x1
7239 14:00:24.676097 WL = 0x5
7240 14:00:24.679596 RL = 0x5
7241 14:00:24.679852 BL = 0x2
7242 14:00:24.683020 RPST = 0x0
7243 14:00:24.683276 RD_PRE = 0x0
7244 14:00:24.686467 WR_PRE = 0x1
7245 14:00:24.690002 WR_PST = 0x1
7246 14:00:24.690258 DBI_WR = 0x0
7247 14:00:24.692809 DBI_RD = 0x0
7248 14:00:24.693066 OTF = 0x1
7249 14:00:24.696088 ===================================
7250 14:00:24.702623 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7251 14:00:24.702916 ==
7252 14:00:24.706358 Dram Type= 6, Freq= 0, CH_0, rank 0
7253 14:00:24.709590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7254 14:00:24.709675 ==
7255 14:00:24.712679 [Duty_Offset_Calibration]
7256 14:00:24.712762 B0:2 B1:-1 CA:1
7257 14:00:24.716240
7258 14:00:24.719154 [DutyScan_Calibration_Flow] k_type=0
7259 14:00:24.726734
7260 14:00:24.726822 ==CLK 0==
7261 14:00:24.729897 Final CLK duty delay cell = -4
7262 14:00:24.733070 [-4] MAX Duty = 5031%(X100), DQS PI = 6
7263 14:00:24.736788 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7264 14:00:24.739721 [-4] AVG Duty = 4937%(X100)
7265 14:00:24.739805
7266 14:00:24.743676 CH0 CLK Duty spec in!! Max-Min= 187%
7267 14:00:24.746534 [DutyScan_Calibration_Flow] ====Done====
7268 14:00:24.746625
7269 14:00:24.749702 [DutyScan_Calibration_Flow] k_type=1
7270 14:00:24.766007
7271 14:00:24.766132 ==DQS 0 ==
7272 14:00:24.769690 Final DQS duty delay cell = 0
7273 14:00:24.772633 [0] MAX Duty = 5125%(X100), DQS PI = 20
7274 14:00:24.775998 [0] MIN Duty = 5000%(X100), DQS PI = 14
7275 14:00:24.779536 [0] AVG Duty = 5062%(X100)
7276 14:00:24.779692
7277 14:00:24.779849 ==DQS 1 ==
7278 14:00:24.782774 Final DQS duty delay cell = -4
7279 14:00:24.786708 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7280 14:00:24.789668 [-4] MIN Duty = 5031%(X100), DQS PI = 8
7281 14:00:24.792691 [-4] AVG Duty = 5062%(X100)
7282 14:00:24.792932
7283 14:00:24.796240 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7284 14:00:24.796481
7285 14:00:24.799567 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7286 14:00:24.803001 [DutyScan_Calibration_Flow] ====Done====
7287 14:00:24.803250
7288 14:00:24.806359 [DutyScan_Calibration_Flow] k_type=3
7289 14:00:24.823337
7290 14:00:24.823588 ==DQM 0 ==
7291 14:00:24.827055 Final DQM duty delay cell = 0
7292 14:00:24.830149 [0] MAX Duty = 5000%(X100), DQS PI = 18
7293 14:00:24.833466 [0] MIN Duty = 4875%(X100), DQS PI = 4
7294 14:00:24.833705 [0] AVG Duty = 4937%(X100)
7295 14:00:24.837265
7296 14:00:24.837500 ==DQM 1 ==
7297 14:00:24.840057 Final DQM duty delay cell = 0
7298 14:00:24.843743 [0] MAX Duty = 5187%(X100), DQS PI = 58
7299 14:00:24.846871 [0] MIN Duty = 4969%(X100), DQS PI = 18
7300 14:00:24.847111 [0] AVG Duty = 5078%(X100)
7301 14:00:24.850149
7302 14:00:24.853927 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7303 14:00:24.854165
7304 14:00:24.856976 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7305 14:00:24.860202 [DutyScan_Calibration_Flow] ====Done====
7306 14:00:24.860441
7307 14:00:24.863192 [DutyScan_Calibration_Flow] k_type=2
7308 14:00:24.880341
7309 14:00:24.880579 ==DQ 0 ==
7310 14:00:24.883170 Final DQ duty delay cell = -4
7311 14:00:24.886571 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7312 14:00:24.890044 [-4] MIN Duty = 4844%(X100), DQS PI = 28
7313 14:00:24.893469 [-4] AVG Duty = 4922%(X100)
7314 14:00:24.893657
7315 14:00:24.893866 ==DQ 1 ==
7316 14:00:24.896321 Final DQ duty delay cell = 0
7317 14:00:24.899937 [0] MAX Duty = 5031%(X100), DQS PI = 30
7318 14:00:24.903686 [0] MIN Duty = 4907%(X100), DQS PI = 18
7319 14:00:24.903968 [0] AVG Duty = 4969%(X100)
7320 14:00:24.906438
7321 14:00:24.909784 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7322 14:00:24.909975
7323 14:00:24.913202 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7324 14:00:24.916661 [DutyScan_Calibration_Flow] ====Done====
7325 14:00:24.916852 ==
7326 14:00:24.919983 Dram Type= 6, Freq= 0, CH_1, rank 0
7327 14:00:24.923275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7328 14:00:24.923466 ==
7329 14:00:24.926429 [Duty_Offset_Calibration]
7330 14:00:24.926618 B0:1 B1:1 CA:2
7331 14:00:24.926768
7332 14:00:24.929750 [DutyScan_Calibration_Flow] k_type=0
7333 14:00:24.940330
7334 14:00:24.940517 ==CLK 0==
7335 14:00:24.943601 Final CLK duty delay cell = 0
7336 14:00:24.946892 [0] MAX Duty = 5187%(X100), DQS PI = 26
7337 14:00:24.950320 [0] MIN Duty = 4969%(X100), DQS PI = 40
7338 14:00:24.950532 [0] AVG Duty = 5078%(X100)
7339 14:00:24.954025
7340 14:00:24.954228 CH1 CLK Duty spec in!! Max-Min= 218%
7341 14:00:24.960736 [DutyScan_Calibration_Flow] ====Done====
7342 14:00:24.960967
7343 14:00:24.963437 [DutyScan_Calibration_Flow] k_type=1
7344 14:00:24.979910
7345 14:00:24.980098 ==DQS 0 ==
7346 14:00:24.983336 Final DQS duty delay cell = 0
7347 14:00:24.986657 [0] MAX Duty = 5062%(X100), DQS PI = 22
7348 14:00:24.990130 [0] MIN Duty = 4813%(X100), DQS PI = 52
7349 14:00:24.990317 [0] AVG Duty = 4937%(X100)
7350 14:00:24.993327
7351 14:00:24.993516 ==DQS 1 ==
7352 14:00:24.996764 Final DQS duty delay cell = 0
7353 14:00:25.000077 [0] MAX Duty = 5031%(X100), DQS PI = 36
7354 14:00:25.003612 [0] MIN Duty = 4938%(X100), DQS PI = 12
7355 14:00:25.003802 [0] AVG Duty = 4984%(X100)
7356 14:00:25.006860
7357 14:00:25.009951 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7358 14:00:25.010175
7359 14:00:25.013672 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7360 14:00:25.017253 [DutyScan_Calibration_Flow] ====Done====
7361 14:00:25.017490
7362 14:00:25.020054 [DutyScan_Calibration_Flow] k_type=3
7363 14:00:25.036670
7364 14:00:25.036860 ==DQM 0 ==
7365 14:00:25.039957 Final DQM duty delay cell = 0
7366 14:00:25.043819 [0] MAX Duty = 5156%(X100), DQS PI = 20
7367 14:00:25.046856 [0] MIN Duty = 4844%(X100), DQS PI = 50
7368 14:00:25.050287 [0] AVG Duty = 5000%(X100)
7369 14:00:25.050525
7370 14:00:25.050676 ==DQM 1 ==
7371 14:00:25.053795 Final DQM duty delay cell = 0
7372 14:00:25.056848 [0] MAX Duty = 5156%(X100), DQS PI = 62
7373 14:00:25.060059 [0] MIN Duty = 4875%(X100), DQS PI = 20
7374 14:00:25.063898 [0] AVG Duty = 5015%(X100)
7375 14:00:25.064096
7376 14:00:25.067053 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7377 14:00:25.067242
7378 14:00:25.070012 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7379 14:00:25.073456 [DutyScan_Calibration_Flow] ====Done====
7380 14:00:25.073652
7381 14:00:25.076806 [DutyScan_Calibration_Flow] k_type=2
7382 14:00:25.093942
7383 14:00:25.094130 ==DQ 0 ==
7384 14:00:25.096810 Final DQ duty delay cell = 0
7385 14:00:25.100574 [0] MAX Duty = 5125%(X100), DQS PI = 20
7386 14:00:25.104203 [0] MIN Duty = 4875%(X100), DQS PI = 52
7387 14:00:25.104409 [0] AVG Duty = 5000%(X100)
7388 14:00:25.107208
7389 14:00:25.107395 ==DQ 1 ==
7390 14:00:25.110571 Final DQ duty delay cell = 0
7391 14:00:25.113938 [0] MAX Duty = 5093%(X100), DQS PI = 6
7392 14:00:25.117272 [0] MIN Duty = 5031%(X100), DQS PI = 0
7393 14:00:25.117575 [0] AVG Duty = 5062%(X100)
7394 14:00:25.117746
7395 14:00:25.120311 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7396 14:00:25.120501
7397 14:00:25.124398 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7398 14:00:25.130690 [DutyScan_Calibration_Flow] ====Done====
7399 14:00:25.133899 nWR fixed to 30
7400 14:00:25.134090 [ModeRegInit_LP4] CH0 RK0
7401 14:00:25.137622 [ModeRegInit_LP4] CH0 RK1
7402 14:00:25.140319 [ModeRegInit_LP4] CH1 RK0
7403 14:00:25.140509 [ModeRegInit_LP4] CH1 RK1
7404 14:00:25.143927 match AC timing 5
7405 14:00:25.147364 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7406 14:00:25.150454 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7407 14:00:25.157314 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7408 14:00:25.160342 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7409 14:00:25.167089 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7410 14:00:25.167277 [MiockJmeterHQA]
7411 14:00:25.167427
7412 14:00:25.170339 [DramcMiockJmeter] u1RxGatingPI = 0
7413 14:00:25.170544 0 : 4366, 4137
7414 14:00:25.174097 4 : 4252, 4027
7415 14:00:25.174290 8 : 4252, 4027
7416 14:00:25.177081 12 : 4252, 4027
7417 14:00:25.177273 16 : 4253, 4026
7418 14:00:25.180390 20 : 4363, 4138
7419 14:00:25.180582 24 : 4363, 4138
7420 14:00:25.180734 28 : 4252, 4027
7421 14:00:25.183958 32 : 4253, 4026
7422 14:00:25.184151 36 : 4252, 4027
7423 14:00:25.187261 40 : 4252, 4027
7424 14:00:25.187488 44 : 4253, 4027
7425 14:00:25.190870 48 : 4363, 4138
7426 14:00:25.191098 52 : 4250, 4027
7427 14:00:25.194203 56 : 4250, 4027
7428 14:00:25.194504 60 : 4249, 4027
7429 14:00:25.194729 64 : 4249, 4027
7430 14:00:25.197489 68 : 4250, 4027
7431 14:00:25.197849 72 : 4360, 4137
7432 14:00:25.200616 76 : 4360, 4137
7433 14:00:25.200977 80 : 4249, 4027
7434 14:00:25.204439 84 : 4250, 4026
7435 14:00:25.204812 88 : 4250, 4027
7436 14:00:25.207762 92 : 4250, 4027
7437 14:00:25.208145 96 : 4250, 3006
7438 14:00:25.208448 100 : 4361, 0
7439 14:00:25.210700 104 : 4250, 0
7440 14:00:25.211062 108 : 4252, 0
7441 14:00:25.211349 112 : 4252, 0
7442 14:00:25.214134 116 : 4250, 0
7443 14:00:25.214536 120 : 4250, 0
7444 14:00:25.217600 124 : 4249, 0
7445 14:00:25.218159 128 : 4250, 0
7446 14:00:25.218615 132 : 4252, 0
7447 14:00:25.221233 136 : 4250, 0
7448 14:00:25.221599 140 : 4250, 0
7449 14:00:25.224548 144 : 4252, 0
7450 14:00:25.224910 148 : 4361, 0
7451 14:00:25.225201 152 : 4250, 0
7452 14:00:25.227409 156 : 4361, 0
7453 14:00:25.227783 160 : 4250, 0
7454 14:00:25.230936 164 : 4249, 0
7455 14:00:25.231296 168 : 4250, 0
7456 14:00:25.231580 172 : 4250, 0
7457 14:00:25.234346 176 : 4250, 0
7458 14:00:25.234800 180 : 4250, 0
7459 14:00:25.235143 184 : 4250, 0
7460 14:00:25.237514 188 : 4250, 0
7461 14:00:25.237882 192 : 4250, 0
7462 14:00:25.240927 196 : 4252, 0
7463 14:00:25.241419 200 : 4361, 0
7464 14:00:25.241766 204 : 4361, 0
7465 14:00:25.244585 208 : 4361, 0
7466 14:00:25.244949 212 : 4250, 127
7467 14:00:25.247726 216 : 4250, 3826
7468 14:00:25.248089 220 : 4361, 4138
7469 14:00:25.250900 224 : 4249, 4027
7470 14:00:25.251262 228 : 4253, 4026
7471 14:00:25.254327 232 : 4361, 4137
7472 14:00:25.254719 236 : 4250, 4027
7473 14:00:25.255007 240 : 4250, 4027
7474 14:00:25.257469 244 : 4250, 4026
7475 14:00:25.257831 248 : 4250, 4027
7476 14:00:25.260740 252 : 4250, 4026
7477 14:00:25.261103 256 : 4252, 4027
7478 14:00:25.264451 260 : 4360, 4137
7479 14:00:25.264812 264 : 4250, 4027
7480 14:00:25.267610 268 : 4250, 4027
7481 14:00:25.267970 272 : 4361, 4137
7482 14:00:25.271197 276 : 4249, 4027
7483 14:00:25.271631 280 : 4250, 4026
7484 14:00:25.274565 284 : 4361, 4137
7485 14:00:25.274937 288 : 4250, 4026
7486 14:00:25.277445 292 : 4250, 4027
7487 14:00:25.277809 296 : 4250, 4026
7488 14:00:25.278094 300 : 4250, 4027
7489 14:00:25.280884 304 : 4250, 4026
7490 14:00:25.281252 308 : 4249, 4027
7491 14:00:25.284174 312 : 4360, 4137
7492 14:00:25.284537 316 : 4250, 4027
7493 14:00:25.287864 320 : 4250, 4026
7494 14:00:25.288224 324 : 4361, 4137
7495 14:00:25.290573 328 : 4250, 4027
7496 14:00:25.290939 332 : 4250, 3079
7497 14:00:25.294280 336 : 4361, 41
7498 14:00:25.294703
7499 14:00:25.294986 MIOCK jitter meter ch=0
7500 14:00:25.295253
7501 14:00:25.297989 1T = (336-100) = 236 dly cells
7502 14:00:25.304406 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7503 14:00:25.304768 ==
7504 14:00:25.307490 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 14:00:25.311278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 14:00:25.311640 ==
7507 14:00:25.317759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 14:00:25.321406 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 14:00:25.324372 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 14:00:25.330689 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 14:00:25.340425 [CA 0] Center 44 (14~75) winsize 62
7512 14:00:25.344063 [CA 1] Center 44 (14~74) winsize 61
7513 14:00:25.347165 [CA 2] Center 39 (10~68) winsize 59
7514 14:00:25.350223 [CA 3] Center 39 (10~68) winsize 59
7515 14:00:25.353624 [CA 4] Center 37 (7~67) winsize 61
7516 14:00:25.357190 [CA 5] Center 37 (7~67) winsize 61
7517 14:00:25.357549
7518 14:00:25.360322 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 14:00:25.360682
7520 14:00:25.363727 [CATrainingPosCal] consider 1 rank data
7521 14:00:25.367335 u2DelayCellTimex100 = 275/100 ps
7522 14:00:25.370654 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7523 14:00:25.377336 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7524 14:00:25.380652 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7525 14:00:25.384225 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 14:00:25.387060 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7527 14:00:25.390589 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 14:00:25.391023
7529 14:00:25.393857 CA PerBit enable=1, Macro0, CA PI delay=37
7530 14:00:25.394300
7531 14:00:25.397369 [CBTSetCACLKResult] CA Dly = 37
7532 14:00:25.400561 CS Dly: 11 (0~42)
7533 14:00:25.404284 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 14:00:25.407233 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 14:00:25.407665 ==
7536 14:00:25.410570 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 14:00:25.414031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 14:00:25.417189 ==
7539 14:00:25.420730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 14:00:25.423696 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 14:00:25.430378 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 14:00:25.433701 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 14:00:25.444290 [CA 0] Center 43 (13~74) winsize 62
7544 14:00:25.447631 [CA 1] Center 43 (13~74) winsize 62
7545 14:00:25.451210 [CA 2] Center 39 (10~69) winsize 60
7546 14:00:25.453952 [CA 3] Center 38 (9~68) winsize 60
7547 14:00:25.457588 [CA 4] Center 37 (7~67) winsize 61
7548 14:00:25.461064 [CA 5] Center 37 (7~67) winsize 61
7549 14:00:25.461484
7550 14:00:25.464540 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 14:00:25.464963
7552 14:00:25.467966 [CATrainingPosCal] consider 2 rank data
7553 14:00:25.470881 u2DelayCellTimex100 = 275/100 ps
7554 14:00:25.474508 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7555 14:00:25.481534 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7556 14:00:25.484438 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7557 14:00:25.487578 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7558 14:00:25.490925 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7559 14:00:25.494495 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 14:00:25.494916
7561 14:00:25.497448 CA PerBit enable=1, Macro0, CA PI delay=37
7562 14:00:25.497747
7563 14:00:25.501042 [CBTSetCACLKResult] CA Dly = 37
7564 14:00:25.504065 CS Dly: 12 (0~44)
7565 14:00:25.507559 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 14:00:25.511093 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 14:00:25.511319
7568 14:00:25.514111 ----->DramcWriteLeveling(PI) begin...
7569 14:00:25.514348 ==
7570 14:00:25.517686 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 14:00:25.521118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 14:00:25.524240 ==
7573 14:00:25.524464 Write leveling (Byte 0): 32 => 32
7574 14:00:25.527297 Write leveling (Byte 1): 27 => 27
7575 14:00:25.530846 DramcWriteLeveling(PI) end<-----
7576 14:00:25.531079
7577 14:00:25.531314 ==
7578 14:00:25.534551 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 14:00:25.541186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 14:00:25.541422 ==
7581 14:00:25.541660 [Gating] SW mode calibration
7582 14:00:25.550693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 14:00:25.553904 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 14:00:25.560913 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 14:00:25.564216 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 14:00:25.567342 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 14:00:25.570805 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 14:00:25.577701 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7589 14:00:25.581127 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
7590 14:00:25.584405 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7591 14:00:25.591125 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 14:00:25.594000 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 14:00:25.597481 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 14:00:25.604369 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 14:00:25.607499 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 14:00:25.610946 1 5 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7597 14:00:25.617266 1 5 20 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
7598 14:00:25.620427 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
7599 14:00:25.623950 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 14:00:25.630666 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 14:00:25.634016 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 14:00:25.636952 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 14:00:25.643774 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 14:00:25.647011 1 6 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7605 14:00:25.650937 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7606 14:00:25.657412 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7607 14:00:25.660481 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 14:00:25.663927 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 14:00:25.667284 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 14:00:25.673861 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 14:00:25.677128 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 14:00:25.680563 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 14:00:25.687358 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 14:00:25.690718 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 14:00:25.694101 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 14:00:25.700473 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 14:00:25.703939 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 14:00:25.707418 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 14:00:25.713982 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 14:00:25.717457 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 14:00:25.720613 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 14:00:25.727295 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 14:00:25.730559 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 14:00:25.733729 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 14:00:25.741316 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 14:00:25.744086 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 14:00:25.748180 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 14:00:25.753995 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7629 14:00:25.757624 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7630 14:00:25.760964 Total UI for P1: 0, mck2ui 16
7631 14:00:25.764446 best dqsien dly found for B0: ( 1, 9, 14)
7632 14:00:25.767492 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 14:00:25.770868 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 14:00:25.774165 Total UI for P1: 0, mck2ui 16
7635 14:00:25.777748 best dqsien dly found for B1: ( 1, 9, 20)
7636 14:00:25.781225 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7637 14:00:25.783937 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7638 14:00:25.787761
7639 14:00:25.791014 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7640 14:00:25.794718 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7641 14:00:25.797581 [Gating] SW calibration Done
7642 14:00:25.797960 ==
7643 14:00:25.801007 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 14:00:25.804201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 14:00:25.804711 ==
7646 14:00:25.805033 RX Vref Scan: 0
7647 14:00:25.805318
7648 14:00:25.808085 RX Vref 0 -> 0, step: 1
7649 14:00:25.808465
7650 14:00:25.811140 RX Delay 0 -> 252, step: 8
7651 14:00:25.814313 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7652 14:00:25.817684 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7653 14:00:25.820989 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7654 14:00:25.827776 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7655 14:00:25.830787 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7656 14:00:25.834951 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7657 14:00:25.837976 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7658 14:00:25.841474 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7659 14:00:25.848036 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7660 14:00:25.851238 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7661 14:00:25.855062 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7662 14:00:25.857595 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7663 14:00:25.861316 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7664 14:00:25.867782 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7665 14:00:25.870948 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7666 14:00:25.874640 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7667 14:00:25.875029 ==
7668 14:00:25.877609 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 14:00:25.881926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 14:00:25.884902 ==
7671 14:00:25.885385 DQS Delay:
7672 14:00:25.885687 DQS0 = 0, DQS1 = 0
7673 14:00:25.887600 DQM Delay:
7674 14:00:25.887991 DQM0 = 132, DQM1 = 124
7675 14:00:25.891402 DQ Delay:
7676 14:00:25.894102 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7677 14:00:25.897977 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7678 14:00:25.900825 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =115
7679 14:00:25.904142 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7680 14:00:25.904525
7681 14:00:25.904829
7682 14:00:25.905114 ==
7683 14:00:25.907512 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 14:00:25.910885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 14:00:25.911288 ==
7686 14:00:25.911693
7687 14:00:25.912075
7688 14:00:25.914483 TX Vref Scan disable
7689 14:00:25.918425 == TX Byte 0 ==
7690 14:00:25.921346 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7691 14:00:25.924121 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7692 14:00:25.927690 == TX Byte 1 ==
7693 14:00:25.930923 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7694 14:00:25.934278 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7695 14:00:25.934982 ==
7696 14:00:25.937684 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 14:00:25.944469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 14:00:25.944970 ==
7699 14:00:25.958070
7700 14:00:25.960759 TX Vref early break, caculate TX vref
7701 14:00:25.963942 TX Vref=16, minBit 1, minWin=20, winSum=353
7702 14:00:25.967073 TX Vref=18, minBit 1, minWin=21, winSum=363
7703 14:00:25.970818 TX Vref=20, minBit 4, minWin=22, winSum=377
7704 14:00:25.973911 TX Vref=22, minBit 0, minWin=23, winSum=387
7705 14:00:25.977288 TX Vref=24, minBit 0, minWin=24, winSum=395
7706 14:00:25.984335 TX Vref=26, minBit 0, minWin=24, winSum=406
7707 14:00:25.987813 TX Vref=28, minBit 4, minWin=24, winSum=411
7708 14:00:25.990871 TX Vref=30, minBit 0, minWin=25, winSum=412
7709 14:00:25.994247 TX Vref=32, minBit 3, minWin=24, winSum=406
7710 14:00:25.997098 TX Vref=34, minBit 4, minWin=23, winSum=396
7711 14:00:26.000740 TX Vref=36, minBit 0, minWin=23, winSum=385
7712 14:00:26.007121 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 30
7713 14:00:26.007577
7714 14:00:26.011066 Final TX Range 0 Vref 30
7715 14:00:26.011522
7716 14:00:26.011884 ==
7717 14:00:26.014162 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 14:00:26.017475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 14:00:26.017919 ==
7720 14:00:26.018268
7721 14:00:26.018637
7722 14:00:26.020750 TX Vref Scan disable
7723 14:00:26.027476 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7724 14:00:26.028017 == TX Byte 0 ==
7725 14:00:26.031127 u2DelayCellOfst[0]=14 cells (4 PI)
7726 14:00:26.034384 u2DelayCellOfst[1]=21 cells (6 PI)
7727 14:00:26.037195 u2DelayCellOfst[2]=10 cells (3 PI)
7728 14:00:26.040721 u2DelayCellOfst[3]=14 cells (4 PI)
7729 14:00:26.044696 u2DelayCellOfst[4]=10 cells (3 PI)
7730 14:00:26.047460 u2DelayCellOfst[5]=0 cells (0 PI)
7731 14:00:26.050728 u2DelayCellOfst[6]=21 cells (6 PI)
7732 14:00:26.054311 u2DelayCellOfst[7]=17 cells (5 PI)
7733 14:00:26.057179 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7734 14:00:26.061340 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7735 14:00:26.064262 == TX Byte 1 ==
7736 14:00:26.064811 u2DelayCellOfst[8]=0 cells (0 PI)
7737 14:00:26.067247 u2DelayCellOfst[9]=0 cells (0 PI)
7738 14:00:26.071445 u2DelayCellOfst[10]=7 cells (2 PI)
7739 14:00:26.074128 u2DelayCellOfst[11]=0 cells (0 PI)
7740 14:00:26.077465 u2DelayCellOfst[12]=14 cells (4 PI)
7741 14:00:26.081133 u2DelayCellOfst[13]=14 cells (4 PI)
7742 14:00:26.085145 u2DelayCellOfst[14]=17 cells (5 PI)
7743 14:00:26.087324 u2DelayCellOfst[15]=14 cells (4 PI)
7744 14:00:26.090785 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7745 14:00:26.097916 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7746 14:00:26.098538 DramC Write-DBI on
7747 14:00:26.098913 ==
7748 14:00:26.101156 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 14:00:26.104931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 14:00:26.105489 ==
7751 14:00:26.107985
7752 14:00:26.108536
7753 14:00:26.108900 TX Vref Scan disable
7754 14:00:26.110787 == TX Byte 0 ==
7755 14:00:26.114014 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7756 14:00:26.117836 == TX Byte 1 ==
7757 14:00:26.122133 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7758 14:00:26.122730 DramC Write-DBI off
7759 14:00:26.124335
7760 14:00:26.124792 [DATLAT]
7761 14:00:26.125152 Freq=1600, CH0 RK0
7762 14:00:26.125493
7763 14:00:26.127447 DATLAT Default: 0xf
7764 14:00:26.127911 0, 0xFFFF, sum = 0
7765 14:00:26.131196 1, 0xFFFF, sum = 0
7766 14:00:26.131670 2, 0xFFFF, sum = 0
7767 14:00:26.133958 3, 0xFFFF, sum = 0
7768 14:00:26.137442 4, 0xFFFF, sum = 0
7769 14:00:26.137912 5, 0xFFFF, sum = 0
7770 14:00:26.140949 6, 0xFFFF, sum = 0
7771 14:00:26.141580 7, 0xFFFF, sum = 0
7772 14:00:26.144082 8, 0xFFFF, sum = 0
7773 14:00:26.144675 9, 0xFFFF, sum = 0
7774 14:00:26.147474 10, 0xFFFF, sum = 0
7775 14:00:26.148056 11, 0xFFFF, sum = 0
7776 14:00:26.150661 12, 0xFFFF, sum = 0
7777 14:00:26.151106 13, 0xFFFF, sum = 0
7778 14:00:26.154433 14, 0x0, sum = 1
7779 14:00:26.154935 15, 0x0, sum = 2
7780 14:00:26.157309 16, 0x0, sum = 3
7781 14:00:26.157745 17, 0x0, sum = 4
7782 14:00:26.160988 best_step = 15
7783 14:00:26.161455
7784 14:00:26.161881 ==
7785 14:00:26.164395 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 14:00:26.167676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 14:00:26.168103 ==
7788 14:00:26.168531 RX Vref Scan: 1
7789 14:00:26.168936
7790 14:00:26.170913 Set Vref Range= 24 -> 127
7791 14:00:26.171336
7792 14:00:26.174442 RX Vref 24 -> 127, step: 1
7793 14:00:26.174869
7794 14:00:26.177322 RX Delay 11 -> 252, step: 4
7795 14:00:26.177791
7796 14:00:26.181078 Set Vref, RX VrefLevel [Byte0]: 24
7797 14:00:26.184287 [Byte1]: 24
7798 14:00:26.184710
7799 14:00:26.187522 Set Vref, RX VrefLevel [Byte0]: 25
7800 14:00:26.192018 [Byte1]: 25
7801 14:00:26.192544
7802 14:00:26.193898 Set Vref, RX VrefLevel [Byte0]: 26
7803 14:00:26.197619 [Byte1]: 26
7804 14:00:26.201590
7805 14:00:26.202015 Set Vref, RX VrefLevel [Byte0]: 27
7806 14:00:26.204456 [Byte1]: 27
7807 14:00:26.209124
7808 14:00:26.209645 Set Vref, RX VrefLevel [Byte0]: 28
7809 14:00:26.212778 [Byte1]: 28
7810 14:00:26.216346
7811 14:00:26.216754 Set Vref, RX VrefLevel [Byte0]: 29
7812 14:00:26.220123 [Byte1]: 29
7813 14:00:26.224203
7814 14:00:26.224614 Set Vref, RX VrefLevel [Byte0]: 30
7815 14:00:26.227598 [Byte1]: 30
7816 14:00:26.232015
7817 14:00:26.232521 Set Vref, RX VrefLevel [Byte0]: 31
7818 14:00:26.235123 [Byte1]: 31
7819 14:00:26.239698
7820 14:00:26.240216 Set Vref, RX VrefLevel [Byte0]: 32
7821 14:00:26.242379 [Byte1]: 32
7822 14:00:26.246746
7823 14:00:26.247255 Set Vref, RX VrefLevel [Byte0]: 33
7824 14:00:26.249761 [Byte1]: 33
7825 14:00:26.254394
7826 14:00:26.254871 Set Vref, RX VrefLevel [Byte0]: 34
7827 14:00:26.257705 [Byte1]: 34
7828 14:00:26.262149
7829 14:00:26.262770 Set Vref, RX VrefLevel [Byte0]: 35
7830 14:00:26.265659 [Byte1]: 35
7831 14:00:26.269640
7832 14:00:26.270108 Set Vref, RX VrefLevel [Byte0]: 36
7833 14:00:26.273234 [Byte1]: 36
7834 14:00:26.277259
7835 14:00:26.277722 Set Vref, RX VrefLevel [Byte0]: 37
7836 14:00:26.281208 [Byte1]: 37
7837 14:00:26.285301
7838 14:00:26.285849 Set Vref, RX VrefLevel [Byte0]: 38
7839 14:00:26.288598 [Byte1]: 38
7840 14:00:26.293012
7841 14:00:26.293566 Set Vref, RX VrefLevel [Byte0]: 39
7842 14:00:26.295930 [Byte1]: 39
7843 14:00:26.299910
7844 14:00:26.300477 Set Vref, RX VrefLevel [Byte0]: 40
7845 14:00:26.303132 [Byte1]: 40
7846 14:00:26.308015
7847 14:00:26.308477 Set Vref, RX VrefLevel [Byte0]: 41
7848 14:00:26.310929 [Byte1]: 41
7849 14:00:26.316053
7850 14:00:26.316748 Set Vref, RX VrefLevel [Byte0]: 42
7851 14:00:26.319119 [Byte1]: 42
7852 14:00:26.323139
7853 14:00:26.323598 Set Vref, RX VrefLevel [Byte0]: 43
7854 14:00:26.327062 [Byte1]: 43
7855 14:00:26.330439
7856 14:00:26.330906 Set Vref, RX VrefLevel [Byte0]: 44
7857 14:00:26.334045 [Byte1]: 44
7858 14:00:26.338827
7859 14:00:26.339397 Set Vref, RX VrefLevel [Byte0]: 45
7860 14:00:26.341129 [Byte1]: 45
7861 14:00:26.345995
7862 14:00:26.346492 Set Vref, RX VrefLevel [Byte0]: 46
7863 14:00:26.348953 [Byte1]: 46
7864 14:00:26.353117
7865 14:00:26.353583 Set Vref, RX VrefLevel [Byte0]: 47
7866 14:00:26.357178 [Byte1]: 47
7867 14:00:26.361311
7868 14:00:26.361864 Set Vref, RX VrefLevel [Byte0]: 48
7869 14:00:26.364647 [Byte1]: 48
7870 14:00:26.368780
7871 14:00:26.369299 Set Vref, RX VrefLevel [Byte0]: 49
7872 14:00:26.372071 [Byte1]: 49
7873 14:00:26.376357
7874 14:00:26.376773 Set Vref, RX VrefLevel [Byte0]: 50
7875 14:00:26.379827 [Byte1]: 50
7876 14:00:26.383951
7877 14:00:26.384466 Set Vref, RX VrefLevel [Byte0]: 51
7878 14:00:26.387343 [Byte1]: 51
7879 14:00:26.391832
7880 14:00:26.392340 Set Vref, RX VrefLevel [Byte0]: 52
7881 14:00:26.394749 [Byte1]: 52
7882 14:00:26.399258
7883 14:00:26.399789 Set Vref, RX VrefLevel [Byte0]: 53
7884 14:00:26.402601 [Byte1]: 53
7885 14:00:26.407039
7886 14:00:26.407457 Set Vref, RX VrefLevel [Byte0]: 54
7887 14:00:26.410226 [Byte1]: 54
7888 14:00:26.414339
7889 14:00:26.414899 Set Vref, RX VrefLevel [Byte0]: 55
7890 14:00:26.417426 [Byte1]: 55
7891 14:00:26.421859
7892 14:00:26.422367 Set Vref, RX VrefLevel [Byte0]: 56
7893 14:00:26.425584 [Byte1]: 56
7894 14:00:26.429332
7895 14:00:26.429754 Set Vref, RX VrefLevel [Byte0]: 57
7896 14:00:26.432994 [Byte1]: 57
7897 14:00:26.437295
7898 14:00:26.437817 Set Vref, RX VrefLevel [Byte0]: 58
7899 14:00:26.440900 [Byte1]: 58
7900 14:00:26.445613
7901 14:00:26.446038 Set Vref, RX VrefLevel [Byte0]: 59
7902 14:00:26.448100 [Byte1]: 59
7903 14:00:26.452336
7904 14:00:26.452858 Set Vref, RX VrefLevel [Byte0]: 60
7905 14:00:26.455805 [Byte1]: 60
7906 14:00:26.460535
7907 14:00:26.461056 Set Vref, RX VrefLevel [Byte0]: 61
7908 14:00:26.463330 [Byte1]: 61
7909 14:00:26.467646
7910 14:00:26.468173 Set Vref, RX VrefLevel [Byte0]: 62
7911 14:00:26.471099 [Byte1]: 62
7912 14:00:26.475308
7913 14:00:26.475829 Set Vref, RX VrefLevel [Byte0]: 63
7914 14:00:26.478551 [Byte1]: 63
7915 14:00:26.483067
7916 14:00:26.483579 Set Vref, RX VrefLevel [Byte0]: 64
7917 14:00:26.486085 [Byte1]: 64
7918 14:00:26.490521
7919 14:00:26.491029 Set Vref, RX VrefLevel [Byte0]: 65
7920 14:00:26.493998 [Byte1]: 65
7921 14:00:26.498070
7922 14:00:26.498682 Set Vref, RX VrefLevel [Byte0]: 66
7923 14:00:26.501943 [Byte1]: 66
7924 14:00:26.505815
7925 14:00:26.506444 Set Vref, RX VrefLevel [Byte0]: 67
7926 14:00:26.509263 [Byte1]: 67
7927 14:00:26.513389
7928 14:00:26.513938 Set Vref, RX VrefLevel [Byte0]: 68
7929 14:00:26.516377 [Byte1]: 68
7930 14:00:26.521428
7931 14:00:26.521977 Set Vref, RX VrefLevel [Byte0]: 69
7932 14:00:26.524536 [Byte1]: 69
7933 14:00:26.528532
7934 14:00:26.528989 Set Vref, RX VrefLevel [Byte0]: 70
7935 14:00:26.531968 [Byte1]: 70
7936 14:00:26.536540
7937 14:00:26.537090 Set Vref, RX VrefLevel [Byte0]: 71
7938 14:00:26.539633 [Byte1]: 71
7939 14:00:26.543524
7940 14:00:26.543980 Set Vref, RX VrefLevel [Byte0]: 72
7941 14:00:26.547262 [Byte1]: 72
7942 14:00:26.551245
7943 14:00:26.551922 Set Vref, RX VrefLevel [Byte0]: 73
7944 14:00:26.554573 [Byte1]: 73
7945 14:00:26.559503
7946 14:00:26.560081 Set Vref, RX VrefLevel [Byte0]: 74
7947 14:00:26.562619 [Byte1]: 74
7948 14:00:26.566457
7949 14:00:26.567034 Final RX Vref Byte 0 = 56 to rank0
7950 14:00:26.570201 Final RX Vref Byte 1 = 62 to rank0
7951 14:00:26.573402 Final RX Vref Byte 0 = 56 to rank1
7952 14:00:26.576768 Final RX Vref Byte 1 = 62 to rank1==
7953 14:00:26.580246 Dram Type= 6, Freq= 0, CH_0, rank 0
7954 14:00:26.587113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 14:00:26.587666 ==
7956 14:00:26.588027 DQS Delay:
7957 14:00:26.588364 DQS0 = 0, DQS1 = 0
7958 14:00:26.590258 DQM Delay:
7959 14:00:26.590871 DQM0 = 129, DQM1 = 122
7960 14:00:26.593940 DQ Delay:
7961 14:00:26.596866 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7962 14:00:26.600100 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7963 14:00:26.603020 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7964 14:00:26.606795 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7965 14:00:26.607349
7966 14:00:26.607711
7967 14:00:26.608043
7968 14:00:26.610288 [DramC_TX_OE_Calibration] TA2
7969 14:00:26.613062 Original DQ_B0 (3 6) =30, OEN = 27
7970 14:00:26.616700 Original DQ_B1 (3 6) =30, OEN = 27
7971 14:00:26.619905 24, 0x0, End_B0=24 End_B1=24
7972 14:00:26.620499 25, 0x0, End_B0=25 End_B1=25
7973 14:00:26.623420 26, 0x0, End_B0=26 End_B1=26
7974 14:00:26.626481 27, 0x0, End_B0=27 End_B1=27
7975 14:00:26.629596 28, 0x0, End_B0=28 End_B1=28
7976 14:00:26.630062 29, 0x0, End_B0=29 End_B1=29
7977 14:00:26.633472 30, 0x0, End_B0=30 End_B1=30
7978 14:00:26.636451 31, 0x4141, End_B0=30 End_B1=30
7979 14:00:26.639978 Byte0 end_step=30 best_step=27
7980 14:00:26.643097 Byte1 end_step=30 best_step=27
7981 14:00:26.646458 Byte0 TX OE(2T, 0.5T) = (3, 3)
7982 14:00:26.646882 Byte1 TX OE(2T, 0.5T) = (3, 3)
7983 14:00:26.647212
7984 14:00:26.650301
7985 14:00:26.656520 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7986 14:00:26.659978 CH0 RK0: MR19=303, MR18=1307
7987 14:00:26.666916 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
7988 14:00:26.667488
7989 14:00:26.670376 ----->DramcWriteLeveling(PI) begin...
7990 14:00:26.670898 ==
7991 14:00:26.673483 Dram Type= 6, Freq= 0, CH_0, rank 1
7992 14:00:26.676338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7993 14:00:26.676823 ==
7994 14:00:26.679798 Write leveling (Byte 0): 35 => 35
7995 14:00:26.683322 Write leveling (Byte 1): 27 => 27
7996 14:00:26.687452 DramcWriteLeveling(PI) end<-----
7997 14:00:26.687918
7998 14:00:26.688454 ==
7999 14:00:26.690091 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 14:00:26.693451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 14:00:26.693868 ==
8002 14:00:26.697053 [Gating] SW mode calibration
8003 14:00:26.703060 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8004 14:00:26.710217 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8005 14:00:26.713476 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 14:00:26.716763 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 14:00:26.723090 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8008 14:00:26.726580 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8009 14:00:26.729782 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8010 14:00:26.736707 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8011 14:00:26.739919 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8012 14:00:26.743571 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 14:00:26.746361 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 14:00:26.752942 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 14:00:26.756719 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8016 14:00:26.759829 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8017 14:00:26.766769 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8018 14:00:26.770009 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8019 14:00:26.773318 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 14:00:26.780567 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 14:00:26.783680 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 14:00:26.787412 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 14:00:26.793414 1 6 8 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
8024 14:00:26.797374 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8025 14:00:26.800321 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8026 14:00:26.807359 1 6 20 | B1->B0 | 3534 4646 | 1 0 | (0 0) (0 0)
8027 14:00:26.810484 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 14:00:26.813847 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 14:00:26.820608 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 14:00:26.823491 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 14:00:26.826928 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 14:00:26.830378 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8033 14:00:26.837421 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 14:00:26.840197 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8035 14:00:26.844035 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8036 14:00:26.850361 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 14:00:26.853206 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 14:00:26.857252 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 14:00:26.863808 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 14:00:26.867166 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 14:00:26.869884 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 14:00:26.877257 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 14:00:26.880268 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 14:00:26.883758 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 14:00:26.890212 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 14:00:26.893578 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 14:00:26.897659 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8048 14:00:26.903461 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8049 14:00:26.906872 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 14:00:26.909891 Total UI for P1: 0, mck2ui 16
8051 14:00:26.913573 best dqsien dly found for B0: ( 1, 9, 10)
8052 14:00:26.917090 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 14:00:26.919853 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8054 14:00:26.926981 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 14:00:26.929973 Total UI for P1: 0, mck2ui 16
8056 14:00:26.933335 best dqsien dly found for B1: ( 1, 9, 20)
8057 14:00:26.937361 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8058 14:00:26.939958 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8059 14:00:26.940425
8060 14:00:26.943207 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8061 14:00:26.946964 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8062 14:00:26.950256 [Gating] SW calibration Done
8063 14:00:26.950777 ==
8064 14:00:26.953963 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 14:00:26.957019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 14:00:26.957487 ==
8067 14:00:26.960435 RX Vref Scan: 0
8068 14:00:26.960987
8069 14:00:26.963628 RX Vref 0 -> 0, step: 1
8070 14:00:26.964093
8071 14:00:26.964454 RX Delay 0 -> 252, step: 8
8072 14:00:26.970149 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8073 14:00:26.973752 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8074 14:00:26.977075 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8075 14:00:26.979988 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8076 14:00:26.983234 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8077 14:00:26.987353 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8078 14:00:26.993380 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8079 14:00:26.996997 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8080 14:00:27.000131 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8081 14:00:27.003589 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8082 14:00:27.007063 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8083 14:00:27.013771 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8084 14:00:27.016610 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8085 14:00:27.020132 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8086 14:00:27.023681 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8087 14:00:27.029841 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8088 14:00:27.030591 ==
8089 14:00:27.033702 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 14:00:27.036924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 14:00:27.037484 ==
8092 14:00:27.037848 DQS Delay:
8093 14:00:27.040198 DQS0 = 0, DQS1 = 0
8094 14:00:27.040747 DQM Delay:
8095 14:00:27.043473 DQM0 = 131, DQM1 = 125
8096 14:00:27.043934 DQ Delay:
8097 14:00:27.046840 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8098 14:00:27.050092 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8099 14:00:27.053579 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8100 14:00:27.056932 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8101 14:00:27.057643
8102 14:00:27.058019
8103 14:00:27.058356 ==
8104 14:00:27.060062 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 14:00:27.066875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 14:00:27.067436 ==
8107 14:00:27.067819
8108 14:00:27.068159
8109 14:00:27.068479 TX Vref Scan disable
8110 14:00:27.070918 == TX Byte 0 ==
8111 14:00:27.074055 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8112 14:00:27.080893 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8113 14:00:27.081442 == TX Byte 1 ==
8114 14:00:27.084085 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8115 14:00:27.090389 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8116 14:00:27.090980 ==
8117 14:00:27.093799 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 14:00:27.097412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 14:00:27.097967 ==
8120 14:00:27.111610
8121 14:00:27.115488 TX Vref early break, caculate TX vref
8122 14:00:27.118096 TX Vref=16, minBit 9, minWin=21, winSum=375
8123 14:00:27.122050 TX Vref=18, minBit 1, minWin=23, winSum=382
8124 14:00:27.125024 TX Vref=20, minBit 9, minWin=23, winSum=391
8125 14:00:27.128387 TX Vref=22, minBit 1, minWin=24, winSum=396
8126 14:00:27.131179 TX Vref=24, minBit 4, minWin=24, winSum=406
8127 14:00:27.138340 TX Vref=26, minBit 0, minWin=25, winSum=409
8128 14:00:27.141700 TX Vref=28, minBit 4, minWin=25, winSum=422
8129 14:00:27.145372 TX Vref=30, minBit 4, minWin=25, winSum=418
8130 14:00:27.148150 TX Vref=32, minBit 4, minWin=25, winSum=413
8131 14:00:27.151461 TX Vref=34, minBit 1, minWin=24, winSum=401
8132 14:00:27.155097 TX Vref=36, minBit 1, minWin=24, winSum=396
8133 14:00:27.161857 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
8134 14:00:27.162447
8135 14:00:27.164963 Final TX Range 0 Vref 28
8136 14:00:27.165570
8137 14:00:27.165942 ==
8138 14:00:27.168565 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 14:00:27.171582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 14:00:27.172138 ==
8141 14:00:27.172506
8142 14:00:27.172845
8143 14:00:27.174709 TX Vref Scan disable
8144 14:00:27.181511 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8145 14:00:27.182066 == TX Byte 0 ==
8146 14:00:27.184997 u2DelayCellOfst[0]=10 cells (3 PI)
8147 14:00:27.188256 u2DelayCellOfst[1]=17 cells (5 PI)
8148 14:00:27.191560 u2DelayCellOfst[2]=10 cells (3 PI)
8149 14:00:27.194811 u2DelayCellOfst[3]=10 cells (3 PI)
8150 14:00:27.198749 u2DelayCellOfst[4]=10 cells (3 PI)
8151 14:00:27.201437 u2DelayCellOfst[5]=0 cells (0 PI)
8152 14:00:27.205024 u2DelayCellOfst[6]=17 cells (5 PI)
8153 14:00:27.208185 u2DelayCellOfst[7]=17 cells (5 PI)
8154 14:00:27.211674 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8155 14:00:27.214803 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8156 14:00:27.218583 == TX Byte 1 ==
8157 14:00:27.219132 u2DelayCellOfst[8]=0 cells (0 PI)
8158 14:00:27.221974 u2DelayCellOfst[9]=0 cells (0 PI)
8159 14:00:27.225410 u2DelayCellOfst[10]=7 cells (2 PI)
8160 14:00:27.228379 u2DelayCellOfst[11]=0 cells (0 PI)
8161 14:00:27.231713 u2DelayCellOfst[12]=10 cells (3 PI)
8162 14:00:27.234690 u2DelayCellOfst[13]=10 cells (3 PI)
8163 14:00:27.238444 u2DelayCellOfst[14]=14 cells (4 PI)
8164 14:00:27.241801 u2DelayCellOfst[15]=10 cells (3 PI)
8165 14:00:27.244752 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8166 14:00:27.251634 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8167 14:00:27.252054 DramC Write-DBI on
8168 14:00:27.252386 ==
8169 14:00:27.254755 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 14:00:27.258433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 14:00:27.261447 ==
8172 14:00:27.261954
8173 14:00:27.262283
8174 14:00:27.262639 TX Vref Scan disable
8175 14:00:27.265036 == TX Byte 0 ==
8176 14:00:27.268646 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8177 14:00:27.271969 == TX Byte 1 ==
8178 14:00:27.274997 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8179 14:00:27.278791 DramC Write-DBI off
8180 14:00:27.279303
8181 14:00:27.279635 [DATLAT]
8182 14:00:27.279943 Freq=1600, CH0 RK1
8183 14:00:27.280240
8184 14:00:27.282261 DATLAT Default: 0xf
8185 14:00:27.282808 0, 0xFFFF, sum = 0
8186 14:00:27.285111 1, 0xFFFF, sum = 0
8187 14:00:27.285534 2, 0xFFFF, sum = 0
8188 14:00:27.288773 3, 0xFFFF, sum = 0
8189 14:00:27.291779 4, 0xFFFF, sum = 0
8190 14:00:27.292321 5, 0xFFFF, sum = 0
8191 14:00:27.295219 6, 0xFFFF, sum = 0
8192 14:00:27.295646 7, 0xFFFF, sum = 0
8193 14:00:27.298520 8, 0xFFFF, sum = 0
8194 14:00:27.298950 9, 0xFFFF, sum = 0
8195 14:00:27.301691 10, 0xFFFF, sum = 0
8196 14:00:27.302208 11, 0xFFFF, sum = 0
8197 14:00:27.305581 12, 0xFFFF, sum = 0
8198 14:00:27.306096 13, 0xFFFF, sum = 0
8199 14:00:27.308507 14, 0x0, sum = 1
8200 14:00:27.309029 15, 0x0, sum = 2
8201 14:00:27.311827 16, 0x0, sum = 3
8202 14:00:27.312345 17, 0x0, sum = 4
8203 14:00:27.315007 best_step = 15
8204 14:00:27.315428
8205 14:00:27.315759 ==
8206 14:00:27.318717 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 14:00:27.321818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 14:00:27.322241 ==
8209 14:00:27.322628 RX Vref Scan: 0
8210 14:00:27.322941
8211 14:00:27.325122 RX Vref 0 -> 0, step: 1
8212 14:00:27.325538
8213 14:00:27.328492 RX Delay 11 -> 252, step: 4
8214 14:00:27.331553 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8215 14:00:27.338958 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8216 14:00:27.341807 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8217 14:00:27.345329 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8218 14:00:27.348514 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8219 14:00:27.351919 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8220 14:00:27.355342 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8221 14:00:27.361884 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8222 14:00:27.365187 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8223 14:00:27.368829 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8224 14:00:27.372089 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8225 14:00:27.379007 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8226 14:00:27.381579 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8227 14:00:27.385612 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8228 14:00:27.388546 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8229 14:00:27.391946 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8230 14:00:27.392463 ==
8231 14:00:27.395222 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 14:00:27.401593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 14:00:27.402110 ==
8234 14:00:27.402488 DQS Delay:
8235 14:00:27.404920 DQS0 = 0, DQS1 = 0
8236 14:00:27.405338 DQM Delay:
8237 14:00:27.408835 DQM0 = 126, DQM1 = 123
8238 14:00:27.409348 DQ Delay:
8239 14:00:27.411720 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8240 14:00:27.414542 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8241 14:00:27.417938 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =118
8242 14:00:27.422114 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8243 14:00:27.422613
8244 14:00:27.422949
8245 14:00:27.423255
8246 14:00:27.424908 [DramC_TX_OE_Calibration] TA2
8247 14:00:27.428628 Original DQ_B0 (3 6) =30, OEN = 27
8248 14:00:27.431807 Original DQ_B1 (3 6) =30, OEN = 27
8249 14:00:27.434746 24, 0x0, End_B0=24 End_B1=24
8250 14:00:27.439081 25, 0x0, End_B0=25 End_B1=25
8251 14:00:27.439798 26, 0x0, End_B0=26 End_B1=26
8252 14:00:27.441190 27, 0x0, End_B0=27 End_B1=27
8253 14:00:27.444926 28, 0x0, End_B0=28 End_B1=28
8254 14:00:27.448101 29, 0x0, End_B0=29 End_B1=29
8255 14:00:27.448572 30, 0x0, End_B0=30 End_B1=30
8256 14:00:27.451713 31, 0x4141, End_B0=30 End_B1=30
8257 14:00:27.454509 Byte0 end_step=30 best_step=27
8258 14:00:27.458251 Byte1 end_step=30 best_step=27
8259 14:00:27.461844 Byte0 TX OE(2T, 0.5T) = (3, 3)
8260 14:00:27.464668 Byte1 TX OE(2T, 0.5T) = (3, 3)
8261 14:00:27.465130
8262 14:00:27.465489
8263 14:00:27.471928 [DQSOSCAuto] RK1, (LSB)MR18= 0x170b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8264 14:00:27.474722 CH0 RK1: MR19=303, MR18=170B
8265 14:00:27.481458 CH0_RK1: MR19=0x303, MR18=0x170B, DQSOSC=398, MR23=63, INC=23, DEC=15
8266 14:00:27.484925 [RxdqsGatingPostProcess] freq 1600
8267 14:00:27.487985 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8268 14:00:27.491217 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 14:00:27.495336 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 14:00:27.498022 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 14:00:27.501495 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 14:00:27.504981 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 14:00:27.508071 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 14:00:27.511630 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 14:00:27.515066 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 14:00:27.518567 Pre-setting of DQS Precalculation
8277 14:00:27.521761 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8278 14:00:27.522310 ==
8279 14:00:27.525430 Dram Type= 6, Freq= 0, CH_1, rank 0
8280 14:00:27.527745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 14:00:27.531608 ==
8282 14:00:27.535341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8283 14:00:27.538010 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8284 14:00:27.545015 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8285 14:00:27.547792 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8286 14:00:27.558272 [CA 0] Center 42 (13~71) winsize 59
8287 14:00:27.561334 [CA 1] Center 42 (13~71) winsize 59
8288 14:00:27.564689 [CA 2] Center 37 (8~66) winsize 59
8289 14:00:27.567956 [CA 3] Center 36 (7~65) winsize 59
8290 14:00:27.571295 [CA 4] Center 37 (7~67) winsize 61
8291 14:00:27.575031 [CA 5] Center 36 (6~66) winsize 61
8292 14:00:27.575585
8293 14:00:27.577552 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8294 14:00:27.578002
8295 14:00:27.581128 [CATrainingPosCal] consider 1 rank data
8296 14:00:27.584365 u2DelayCellTimex100 = 275/100 ps
8297 14:00:27.591347 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8298 14:00:27.594701 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8299 14:00:27.597820 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8300 14:00:27.601378 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8301 14:00:27.604569 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8302 14:00:27.608010 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8303 14:00:27.608521
8304 14:00:27.611203 CA PerBit enable=1, Macro0, CA PI delay=36
8305 14:00:27.611620
8306 14:00:27.614471 [CBTSetCACLKResult] CA Dly = 36
8307 14:00:27.617836 CS Dly: 8 (0~39)
8308 14:00:27.621638 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8309 14:00:27.624682 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8310 14:00:27.625195 ==
8311 14:00:27.627972 Dram Type= 6, Freq= 0, CH_1, rank 1
8312 14:00:27.631527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 14:00:27.634328 ==
8314 14:00:27.637672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8315 14:00:27.641643 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8316 14:00:27.647650 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8317 14:00:27.651010 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8318 14:00:27.661953 [CA 0] Center 44 (15~73) winsize 59
8319 14:00:27.664976 [CA 1] Center 43 (15~72) winsize 58
8320 14:00:27.668679 [CA 2] Center 38 (9~67) winsize 59
8321 14:00:27.671414 [CA 3] Center 37 (8~67) winsize 60
8322 14:00:27.674825 [CA 4] Center 38 (9~68) winsize 60
8323 14:00:27.678332 [CA 5] Center 37 (8~67) winsize 60
8324 14:00:27.678920
8325 14:00:27.681707 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8326 14:00:27.682256
8327 14:00:27.685038 [CATrainingPosCal] consider 2 rank data
8328 14:00:27.687795 u2DelayCellTimex100 = 275/100 ps
8329 14:00:27.691144 CA0 delay=43 (15~71),Diff = 7 PI (24 cell)
8330 14:00:27.698798 CA1 delay=43 (15~71),Diff = 7 PI (24 cell)
8331 14:00:27.701186 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8332 14:00:27.704403 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8333 14:00:27.708155 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8334 14:00:27.711569 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8335 14:00:27.712118
8336 14:00:27.714793 CA PerBit enable=1, Macro0, CA PI delay=36
8337 14:00:27.715342
8338 14:00:27.717868 [CBTSetCACLKResult] CA Dly = 36
8339 14:00:27.718531 CS Dly: 10 (0~44)
8340 14:00:27.725045 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8341 14:00:27.728252 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8342 14:00:27.728714
8343 14:00:27.731362 ----->DramcWriteLeveling(PI) begin...
8344 14:00:27.731915 ==
8345 14:00:27.734387 Dram Type= 6, Freq= 0, CH_1, rank 0
8346 14:00:27.738780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 14:00:27.739329 ==
8348 14:00:27.741574 Write leveling (Byte 0): 27 => 27
8349 14:00:27.745211 Write leveling (Byte 1): 28 => 28
8350 14:00:27.748963 DramcWriteLeveling(PI) end<-----
8351 14:00:27.749576
8352 14:00:27.749933 ==
8353 14:00:27.751261 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 14:00:27.754627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 14:00:27.758082 ==
8356 14:00:27.758744 [Gating] SW mode calibration
8357 14:00:27.768635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8358 14:00:27.771175 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8359 14:00:27.775179 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 14:00:27.781730 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 14:00:27.785038 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 14:00:27.788077 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 14:00:27.794901 1 4 16 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
8364 14:00:27.797905 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8365 14:00:27.801392 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 14:00:27.808380 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 14:00:27.811694 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 14:00:27.814950 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 14:00:27.821917 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 14:00:27.824685 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8371 14:00:27.828234 1 5 16 | B1->B0 | 3131 3434 | 1 0 | (1 0) (0 1)
8372 14:00:27.831519 1 5 20 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 1)
8373 14:00:27.838226 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 14:00:27.841171 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 14:00:27.845180 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 14:00:27.851558 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 14:00:27.854862 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 14:00:27.858577 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8379 14:00:27.864844 1 6 16 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
8380 14:00:27.868525 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 14:00:27.871678 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 14:00:27.878255 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 14:00:27.881861 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 14:00:27.885076 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 14:00:27.892496 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 14:00:27.895095 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 14:00:27.898195 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8388 14:00:27.902321 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8389 14:00:27.909005 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 14:00:27.912258 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 14:00:27.915145 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 14:00:27.921949 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 14:00:27.925871 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 14:00:27.928682 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 14:00:27.935468 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 14:00:27.938507 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 14:00:27.942045 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 14:00:27.948994 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 14:00:27.952593 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 14:00:27.955551 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 14:00:27.962392 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 14:00:27.965687 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8403 14:00:27.968695 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8404 14:00:27.975403 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 14:00:27.975957 Total UI for P1: 0, mck2ui 16
8406 14:00:27.978562 best dqsien dly found for B0: ( 1, 9, 14)
8407 14:00:27.981932 Total UI for P1: 0, mck2ui 16
8408 14:00:27.985334 best dqsien dly found for B1: ( 1, 9, 16)
8409 14:00:27.988558 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8410 14:00:27.995105 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8411 14:00:27.995657
8412 14:00:27.998748 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8413 14:00:28.001540 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8414 14:00:28.004989 [Gating] SW calibration Done
8415 14:00:28.005648 ==
8416 14:00:28.008313 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 14:00:28.012092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 14:00:28.012557 ==
8419 14:00:28.015590 RX Vref Scan: 0
8420 14:00:28.016009
8421 14:00:28.016345 RX Vref 0 -> 0, step: 1
8422 14:00:28.016707
8423 14:00:28.018484 RX Delay 0 -> 252, step: 8
8424 14:00:28.021714 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8425 14:00:28.025430 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8426 14:00:28.031884 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8427 14:00:28.035163 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8428 14:00:28.038636 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8429 14:00:28.042178 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8430 14:00:28.045074 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8431 14:00:28.052516 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8432 14:00:28.055512 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8433 14:00:28.058885 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8434 14:00:28.062071 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8435 14:00:28.065759 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8436 14:00:28.072101 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8437 14:00:28.076197 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8438 14:00:28.078674 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8439 14:00:28.082457 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8440 14:00:28.082912 ==
8441 14:00:28.085611 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 14:00:28.088749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 14:00:28.092372 ==
8444 14:00:28.092924 DQS Delay:
8445 14:00:28.093282 DQS0 = 0, DQS1 = 0
8446 14:00:28.095313 DQM Delay:
8447 14:00:28.095766 DQM0 = 134, DQM1 = 126
8448 14:00:28.098539 DQ Delay:
8449 14:00:28.102621 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8450 14:00:28.106168 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8451 14:00:28.109475 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8452 14:00:28.112186 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8453 14:00:28.112739
8454 14:00:28.113095
8455 14:00:28.113427 ==
8456 14:00:28.115730 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 14:00:28.118878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 14:00:28.119341 ==
8459 14:00:28.119700
8460 14:00:28.121640
8461 14:00:28.122138 TX Vref Scan disable
8462 14:00:28.125210 == TX Byte 0 ==
8463 14:00:28.128835 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8464 14:00:28.131929 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8465 14:00:28.135570 == TX Byte 1 ==
8466 14:00:28.138577 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8467 14:00:28.141851 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8468 14:00:28.142306 ==
8469 14:00:28.145146 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 14:00:28.151767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 14:00:28.152323 ==
8472 14:00:28.164350
8473 14:00:28.167697 TX Vref early break, caculate TX vref
8474 14:00:28.170894 TX Vref=16, minBit 8, minWin=20, winSum=358
8475 14:00:28.174390 TX Vref=18, minBit 8, minWin=21, winSum=373
8476 14:00:28.177853 TX Vref=20, minBit 5, minWin=22, winSum=382
8477 14:00:28.181431 TX Vref=22, minBit 0, minWin=23, winSum=393
8478 14:00:28.184606 TX Vref=24, minBit 5, minWin=24, winSum=401
8479 14:00:28.191942 TX Vref=26, minBit 11, minWin=24, winSum=411
8480 14:00:28.194584 TX Vref=28, minBit 5, minWin=24, winSum=414
8481 14:00:28.198483 TX Vref=30, minBit 8, minWin=24, winSum=413
8482 14:00:28.201819 TX Vref=32, minBit 0, minWin=24, winSum=406
8483 14:00:28.205258 TX Vref=34, minBit 9, minWin=23, winSum=395
8484 14:00:28.208298 TX Vref=36, minBit 0, minWin=23, winSum=382
8485 14:00:28.214711 [TxChooseVref] Worse bit 5, Min win 24, Win sum 414, Final Vref 28
8486 14:00:28.215272
8487 14:00:28.218691 Final TX Range 0 Vref 28
8488 14:00:28.219193
8489 14:00:28.219552 ==
8490 14:00:28.221530 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 14:00:28.224990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 14:00:28.225573 ==
8493 14:00:28.225939
8494 14:00:28.226271
8495 14:00:28.228384 TX Vref Scan disable
8496 14:00:28.234461 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8497 14:00:28.234947 == TX Byte 0 ==
8498 14:00:28.237702 u2DelayCellOfst[0]=17 cells (5 PI)
8499 14:00:28.241398 u2DelayCellOfst[1]=10 cells (3 PI)
8500 14:00:28.244583 u2DelayCellOfst[2]=0 cells (0 PI)
8501 14:00:28.247857 u2DelayCellOfst[3]=7 cells (2 PI)
8502 14:00:28.251129 u2DelayCellOfst[4]=10 cells (3 PI)
8503 14:00:28.254450 u2DelayCellOfst[5]=17 cells (5 PI)
8504 14:00:28.258309 u2DelayCellOfst[6]=17 cells (5 PI)
8505 14:00:28.258924 u2DelayCellOfst[7]=7 cells (2 PI)
8506 14:00:28.264768 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8507 14:00:28.268265 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8508 14:00:28.268818 == TX Byte 1 ==
8509 14:00:28.271053 u2DelayCellOfst[8]=0 cells (0 PI)
8510 14:00:28.274484 u2DelayCellOfst[9]=3 cells (1 PI)
8511 14:00:28.277886 u2DelayCellOfst[10]=7 cells (2 PI)
8512 14:00:28.281384 u2DelayCellOfst[11]=7 cells (2 PI)
8513 14:00:28.284856 u2DelayCellOfst[12]=10 cells (3 PI)
8514 14:00:28.287506 u2DelayCellOfst[13]=14 cells (4 PI)
8515 14:00:28.291331 u2DelayCellOfst[14]=14 cells (4 PI)
8516 14:00:28.294184 u2DelayCellOfst[15]=14 cells (4 PI)
8517 14:00:28.297652 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8518 14:00:28.304495 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8519 14:00:28.305024 DramC Write-DBI on
8520 14:00:28.305379 ==
8521 14:00:28.307934 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 14:00:28.311139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 14:00:28.311598 ==
8524 14:00:28.314445
8525 14:00:28.314993
8526 14:00:28.315352 TX Vref Scan disable
8527 14:00:28.318700 == TX Byte 0 ==
8528 14:00:28.321812 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8529 14:00:28.324291 == TX Byte 1 ==
8530 14:00:28.328552 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8531 14:00:28.329104 DramC Write-DBI off
8532 14:00:28.329469
8533 14:00:28.331495 [DATLAT]
8534 14:00:28.331969 Freq=1600, CH1 RK0
8535 14:00:28.332331
8536 14:00:28.334479 DATLAT Default: 0xf
8537 14:00:28.335030 0, 0xFFFF, sum = 0
8538 14:00:28.337591 1, 0xFFFF, sum = 0
8539 14:00:28.338277 2, 0xFFFF, sum = 0
8540 14:00:28.341173 3, 0xFFFF, sum = 0
8541 14:00:28.341633 4, 0xFFFF, sum = 0
8542 14:00:28.344350 5, 0xFFFF, sum = 0
8543 14:00:28.344836 6, 0xFFFF, sum = 0
8544 14:00:28.347793 7, 0xFFFF, sum = 0
8545 14:00:28.348258 8, 0xFFFF, sum = 0
8546 14:00:28.351490 9, 0xFFFF, sum = 0
8547 14:00:28.354583 10, 0xFFFF, sum = 0
8548 14:00:28.355138 11, 0xFFFF, sum = 0
8549 14:00:28.357948 12, 0xFFFF, sum = 0
8550 14:00:28.358569 13, 0xFFFF, sum = 0
8551 14:00:28.361227 14, 0x0, sum = 1
8552 14:00:28.361799 15, 0x0, sum = 2
8553 14:00:28.364780 16, 0x0, sum = 3
8554 14:00:28.365334 17, 0x0, sum = 4
8555 14:00:28.365702 best_step = 15
8556 14:00:28.367916
8557 14:00:28.368389 ==
8558 14:00:28.370916 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 14:00:28.374333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 14:00:28.374935 ==
8561 14:00:28.375296 RX Vref Scan: 1
8562 14:00:28.375630
8563 14:00:28.377622 Set Vref Range= 24 -> 127
8564 14:00:28.378074
8565 14:00:28.381485 RX Vref 24 -> 127, step: 1
8566 14:00:28.382027
8567 14:00:28.384787 RX Delay 11 -> 252, step: 4
8568 14:00:28.385335
8569 14:00:28.388054 Set Vref, RX VrefLevel [Byte0]: 24
8570 14:00:28.390846 [Byte1]: 24
8571 14:00:28.391449
8572 14:00:28.394288 Set Vref, RX VrefLevel [Byte0]: 25
8573 14:00:28.397962 [Byte1]: 25
8574 14:00:28.398561
8575 14:00:28.400936 Set Vref, RX VrefLevel [Byte0]: 26
8576 14:00:28.404120 [Byte1]: 26
8577 14:00:28.407742
8578 14:00:28.408357 Set Vref, RX VrefLevel [Byte0]: 27
8579 14:00:28.411497 [Byte1]: 27
8580 14:00:28.415731
8581 14:00:28.416275 Set Vref, RX VrefLevel [Byte0]: 28
8582 14:00:28.419083 [Byte1]: 28
8583 14:00:28.423362
8584 14:00:28.423902 Set Vref, RX VrefLevel [Byte0]: 29
8585 14:00:28.427182 [Byte1]: 29
8586 14:00:28.431175
8587 14:00:28.431934 Set Vref, RX VrefLevel [Byte0]: 30
8588 14:00:28.434145 [Byte1]: 30
8589 14:00:28.438469
8590 14:00:28.439241 Set Vref, RX VrefLevel [Byte0]: 31
8591 14:00:28.441726 [Byte1]: 31
8592 14:00:28.446287
8593 14:00:28.446813 Set Vref, RX VrefLevel [Byte0]: 32
8594 14:00:28.449785 [Byte1]: 32
8595 14:00:28.453424
8596 14:00:28.453901 Set Vref, RX VrefLevel [Byte0]: 33
8597 14:00:28.456769 [Byte1]: 33
8598 14:00:28.461796
8599 14:00:28.462356 Set Vref, RX VrefLevel [Byte0]: 34
8600 14:00:28.465086 [Byte1]: 34
8601 14:00:28.469194
8602 14:00:28.469744 Set Vref, RX VrefLevel [Byte0]: 35
8603 14:00:28.471855 [Byte1]: 35
8604 14:00:28.477126
8605 14:00:28.477679 Set Vref, RX VrefLevel [Byte0]: 36
8606 14:00:28.480039 [Byte1]: 36
8607 14:00:28.484372
8608 14:00:28.484920 Set Vref, RX VrefLevel [Byte0]: 37
8609 14:00:28.487354 [Byte1]: 37
8610 14:00:28.491957
8611 14:00:28.492506 Set Vref, RX VrefLevel [Byte0]: 38
8612 14:00:28.495257 [Byte1]: 38
8613 14:00:28.499417
8614 14:00:28.499963 Set Vref, RX VrefLevel [Byte0]: 39
8615 14:00:28.502538 [Byte1]: 39
8616 14:00:28.507298
8617 14:00:28.507848 Set Vref, RX VrefLevel [Byte0]: 40
8618 14:00:28.510736 [Byte1]: 40
8619 14:00:28.514568
8620 14:00:28.515145 Set Vref, RX VrefLevel [Byte0]: 41
8621 14:00:28.518061 [Byte1]: 41
8622 14:00:28.522231
8623 14:00:28.522983 Set Vref, RX VrefLevel [Byte0]: 42
8624 14:00:28.525223 [Byte1]: 42
8625 14:00:28.530148
8626 14:00:28.530658 Set Vref, RX VrefLevel [Byte0]: 43
8627 14:00:28.532922 [Byte1]: 43
8628 14:00:28.537568
8629 14:00:28.538055 Set Vref, RX VrefLevel [Byte0]: 44
8630 14:00:28.540455 [Byte1]: 44
8631 14:00:28.544925
8632 14:00:28.545522 Set Vref, RX VrefLevel [Byte0]: 45
8633 14:00:28.548104 [Byte1]: 45
8634 14:00:28.552880
8635 14:00:28.553483 Set Vref, RX VrefLevel [Byte0]: 46
8636 14:00:28.555835 [Byte1]: 46
8637 14:00:28.560180
8638 14:00:28.560871 Set Vref, RX VrefLevel [Byte0]: 47
8639 14:00:28.563588 [Byte1]: 47
8640 14:00:28.567523
8641 14:00:28.568005 Set Vref, RX VrefLevel [Byte0]: 48
8642 14:00:28.571052 [Byte1]: 48
8643 14:00:28.575809
8644 14:00:28.576351 Set Vref, RX VrefLevel [Byte0]: 49
8645 14:00:28.578746 [Byte1]: 49
8646 14:00:28.583373
8647 14:00:28.583923 Set Vref, RX VrefLevel [Byte0]: 50
8648 14:00:28.586543 [Byte1]: 50
8649 14:00:28.591324
8650 14:00:28.591871 Set Vref, RX VrefLevel [Byte0]: 51
8651 14:00:28.594292 [Byte1]: 51
8652 14:00:28.598878
8653 14:00:28.599426 Set Vref, RX VrefLevel [Byte0]: 52
8654 14:00:28.601864 [Byte1]: 52
8655 14:00:28.606289
8656 14:00:28.606889 Set Vref, RX VrefLevel [Byte0]: 53
8657 14:00:28.609450 [Byte1]: 53
8658 14:00:28.613907
8659 14:00:28.614486 Set Vref, RX VrefLevel [Byte0]: 54
8660 14:00:28.616656 [Byte1]: 54
8661 14:00:28.621087
8662 14:00:28.621555 Set Vref, RX VrefLevel [Byte0]: 55
8663 14:00:28.624417 [Byte1]: 55
8664 14:00:28.628857
8665 14:00:28.629407 Set Vref, RX VrefLevel [Byte0]: 56
8666 14:00:28.632140 [Byte1]: 56
8667 14:00:28.636168
8668 14:00:28.636617 Set Vref, RX VrefLevel [Byte0]: 57
8669 14:00:28.639746 [Byte1]: 57
8670 14:00:28.643623
8671 14:00:28.644245 Set Vref, RX VrefLevel [Byte0]: 58
8672 14:00:28.647734 [Byte1]: 58
8673 14:00:28.652111
8674 14:00:28.652660 Set Vref, RX VrefLevel [Byte0]: 59
8675 14:00:28.655056 [Byte1]: 59
8676 14:00:28.659921
8677 14:00:28.660652 Set Vref, RX VrefLevel [Byte0]: 60
8678 14:00:28.662297 [Byte1]: 60
8679 14:00:28.666883
8680 14:00:28.667428 Set Vref, RX VrefLevel [Byte0]: 61
8681 14:00:28.670482 [Byte1]: 61
8682 14:00:28.674224
8683 14:00:28.674733 Set Vref, RX VrefLevel [Byte0]: 62
8684 14:00:28.677933 [Byte1]: 62
8685 14:00:28.681911
8686 14:00:28.682518 Set Vref, RX VrefLevel [Byte0]: 63
8687 14:00:28.685285 [Byte1]: 63
8688 14:00:28.689634
8689 14:00:28.690246 Set Vref, RX VrefLevel [Byte0]: 64
8690 14:00:28.692703 [Byte1]: 64
8691 14:00:28.696934
8692 14:00:28.697394 Set Vref, RX VrefLevel [Byte0]: 65
8693 14:00:28.700501 [Byte1]: 65
8694 14:00:28.704422
8695 14:00:28.704879 Set Vref, RX VrefLevel [Byte0]: 66
8696 14:00:28.707806 [Byte1]: 66
8697 14:00:28.712341
8698 14:00:28.712810 Set Vref, RX VrefLevel [Byte0]: 67
8699 14:00:28.715809 [Byte1]: 67
8700 14:00:28.720369
8701 14:00:28.720904 Set Vref, RX VrefLevel [Byte0]: 68
8702 14:00:28.723019 [Byte1]: 68
8703 14:00:28.727671
8704 14:00:28.728220 Set Vref, RX VrefLevel [Byte0]: 69
8705 14:00:28.730929 [Byte1]: 69
8706 14:00:28.735130
8707 14:00:28.735637 Set Vref, RX VrefLevel [Byte0]: 70
8708 14:00:28.738649 [Byte1]: 70
8709 14:00:28.742798
8710 14:00:28.743260 Set Vref, RX VrefLevel [Byte0]: 71
8711 14:00:28.746198 [Byte1]: 71
8712 14:00:28.750359
8713 14:00:28.750867 Set Vref, RX VrefLevel [Byte0]: 72
8714 14:00:28.754292 [Byte1]: 72
8715 14:00:28.758537
8716 14:00:28.759114 Set Vref, RX VrefLevel [Byte0]: 73
8717 14:00:28.761117 [Byte1]: 73
8718 14:00:28.766114
8719 14:00:28.766790 Set Vref, RX VrefLevel [Byte0]: 74
8720 14:00:28.769466 [Byte1]: 74
8721 14:00:28.773297
8722 14:00:28.773843 Final RX Vref Byte 0 = 56 to rank0
8723 14:00:28.776895 Final RX Vref Byte 1 = 52 to rank0
8724 14:00:28.779940 Final RX Vref Byte 0 = 56 to rank1
8725 14:00:28.783205 Final RX Vref Byte 1 = 52 to rank1==
8726 14:00:28.787012 Dram Type= 6, Freq= 0, CH_1, rank 0
8727 14:00:28.790434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 14:00:28.793033 ==
8729 14:00:28.793486 DQS Delay:
8730 14:00:28.793844 DQS0 = 0, DQS1 = 0
8731 14:00:28.796470 DQM Delay:
8732 14:00:28.796950 DQM0 = 130, DQM1 = 124
8733 14:00:28.800147 DQ Delay:
8734 14:00:28.803881 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8735 14:00:28.806547 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8736 14:00:28.810086 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8737 14:00:28.813536 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =132
8738 14:00:28.814089
8739 14:00:28.814500
8740 14:00:28.814850
8741 14:00:28.816876 [DramC_TX_OE_Calibration] TA2
8742 14:00:28.820291 Original DQ_B0 (3 6) =30, OEN = 27
8743 14:00:28.823409 Original DQ_B1 (3 6) =30, OEN = 27
8744 14:00:28.826933 24, 0x0, End_B0=24 End_B1=24
8745 14:00:28.827498 25, 0x0, End_B0=25 End_B1=25
8746 14:00:28.829632 26, 0x0, End_B0=26 End_B1=26
8747 14:00:28.833539 27, 0x0, End_B0=27 End_B1=27
8748 14:00:28.836445 28, 0x0, End_B0=28 End_B1=28
8749 14:00:28.836908 29, 0x0, End_B0=29 End_B1=29
8750 14:00:28.839951 30, 0x0, End_B0=30 End_B1=30
8751 14:00:28.843151 31, 0x4141, End_B0=30 End_B1=30
8752 14:00:28.846468 Byte0 end_step=30 best_step=27
8753 14:00:28.849924 Byte1 end_step=30 best_step=27
8754 14:00:28.853543 Byte0 TX OE(2T, 0.5T) = (3, 3)
8755 14:00:28.854099 Byte1 TX OE(2T, 0.5T) = (3, 3)
8756 14:00:28.854509
8757 14:00:28.854854
8758 14:00:28.863473 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8759 14:00:28.866946 CH1 RK0: MR19=302, MR18=12FE
8760 14:00:28.873452 CH1_RK0: MR19=0x302, MR18=0x12FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8761 14:00:28.874004
8762 14:00:28.876883 ----->DramcWriteLeveling(PI) begin...
8763 14:00:28.877691 ==
8764 14:00:28.880222 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 14:00:28.883412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 14:00:28.883871 ==
8767 14:00:28.886501 Write leveling (Byte 0): 24 => 24
8768 14:00:28.890667 Write leveling (Byte 1): 27 => 27
8769 14:00:28.893273 DramcWriteLeveling(PI) end<-----
8770 14:00:28.893727
8771 14:00:28.894080 ==
8772 14:00:28.896733 Dram Type= 6, Freq= 0, CH_1, rank 1
8773 14:00:28.899988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 14:00:28.900915 ==
8775 14:00:28.903837 [Gating] SW mode calibration
8776 14:00:28.910372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8777 14:00:28.916499 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8778 14:00:28.919831 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 14:00:28.923184 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 14:00:28.929921 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8781 14:00:28.933157 1 4 12 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
8782 14:00:28.936487 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 14:00:28.943220 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 14:00:28.946950 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 14:00:28.949941 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 14:00:28.953199 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 14:00:28.960194 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8788 14:00:28.963585 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
8789 14:00:28.966457 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8790 14:00:28.973276 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 14:00:28.977455 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 14:00:28.980860 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 14:00:28.987306 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 14:00:28.990654 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 14:00:28.993611 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 14:00:29.000426 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8797 14:00:29.003594 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8798 14:00:29.006942 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 14:00:29.013745 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 14:00:29.017112 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 14:00:29.020469 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 14:00:29.023264 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 14:00:29.030335 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 14:00:29.033583 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8805 14:00:29.036795 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8806 14:00:29.043605 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8807 14:00:29.046675 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 14:00:29.050155 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 14:00:29.057006 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 14:00:29.060656 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 14:00:29.063957 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 14:00:29.070740 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 14:00:29.073858 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 14:00:29.077582 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 14:00:29.083641 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 14:00:29.087610 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 14:00:29.091022 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 14:00:29.094475 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 14:00:29.100515 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 14:00:29.104004 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8821 14:00:29.107836 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8822 14:00:29.110522 Total UI for P1: 0, mck2ui 16
8823 14:00:29.114387 best dqsien dly found for B0: ( 1, 9, 8)
8824 14:00:29.120628 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8825 14:00:29.123922 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 14:00:29.127079 Total UI for P1: 0, mck2ui 16
8827 14:00:29.130821 best dqsien dly found for B1: ( 1, 9, 12)
8828 14:00:29.133887 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8829 14:00:29.137178 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8830 14:00:29.137589
8831 14:00:29.141301 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8832 14:00:29.143926 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8833 14:00:29.147572 [Gating] SW calibration Done
8834 14:00:29.148046 ==
8835 14:00:29.150873 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 14:00:29.154554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 14:00:29.157045 ==
8838 14:00:29.157454 RX Vref Scan: 0
8839 14:00:29.157776
8840 14:00:29.160848 RX Vref 0 -> 0, step: 1
8841 14:00:29.161358
8842 14:00:29.161681 RX Delay 0 -> 252, step: 8
8843 14:00:29.167428 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8844 14:00:29.170764 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8845 14:00:29.173728 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8846 14:00:29.177913 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8847 14:00:29.180727 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8848 14:00:29.187363 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8849 14:00:29.190740 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8850 14:00:29.194231 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8851 14:00:29.197274 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8852 14:00:29.201241 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8853 14:00:29.207288 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8854 14:00:29.210738 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8855 14:00:29.214173 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8856 14:00:29.218207 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8857 14:00:29.220860 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8858 14:00:29.227211 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8859 14:00:29.227717 ==
8860 14:00:29.230752 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 14:00:29.234316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 14:00:29.234879 ==
8863 14:00:29.235207 DQS Delay:
8864 14:00:29.237831 DQS0 = 0, DQS1 = 0
8865 14:00:29.238242 DQM Delay:
8866 14:00:29.240835 DQM0 = 133, DQM1 = 128
8867 14:00:29.241339 DQ Delay:
8868 14:00:29.244135 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8869 14:00:29.247488 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =127
8870 14:00:29.251257 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8871 14:00:29.254098 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8872 14:00:29.254663
8873 14:00:29.255039
8874 14:00:29.257283 ==
8875 14:00:29.261149 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 14:00:29.264544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 14:00:29.265060 ==
8878 14:00:29.265392
8879 14:00:29.265693
8880 14:00:29.268092 TX Vref Scan disable
8881 14:00:29.268604 == TX Byte 0 ==
8882 14:00:29.270994 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8883 14:00:29.277618 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8884 14:00:29.278133 == TX Byte 1 ==
8885 14:00:29.281607 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8886 14:00:29.287838 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8887 14:00:29.288349 ==
8888 14:00:29.291070 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 14:00:29.294533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 14:00:29.295042 ==
8891 14:00:29.308225
8892 14:00:29.311542 TX Vref early break, caculate TX vref
8893 14:00:29.315206 TX Vref=16, minBit 8, minWin=22, winSum=377
8894 14:00:29.318100 TX Vref=18, minBit 9, minWin=22, winSum=387
8895 14:00:29.321263 TX Vref=20, minBit 8, minWin=22, winSum=397
8896 14:00:29.324817 TX Vref=22, minBit 9, minWin=24, winSum=405
8897 14:00:29.329171 TX Vref=24, minBit 15, minWin=24, winSum=411
8898 14:00:29.334888 TX Vref=26, minBit 8, minWin=25, winSum=423
8899 14:00:29.338163 TX Vref=28, minBit 13, minWin=25, winSum=426
8900 14:00:29.341426 TX Vref=30, minBit 5, minWin=25, winSum=421
8901 14:00:29.344934 TX Vref=32, minBit 0, minWin=25, winSum=417
8902 14:00:29.347748 TX Vref=34, minBit 5, minWin=24, winSum=405
8903 14:00:29.351546 TX Vref=36, minBit 0, minWin=24, winSum=399
8904 14:00:29.357795 [TxChooseVref] Worse bit 13, Min win 25, Win sum 426, Final Vref 28
8905 14:00:29.358311
8906 14:00:29.361521 Final TX Range 0 Vref 28
8907 14:00:29.362031
8908 14:00:29.362452 ==
8909 14:00:29.364443 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 14:00:29.367922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 14:00:29.368336 ==
8912 14:00:29.368661
8913 14:00:29.371263
8914 14:00:29.371670 TX Vref Scan disable
8915 14:00:29.378240 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8916 14:00:29.378806 == TX Byte 0 ==
8917 14:00:29.381556 u2DelayCellOfst[0]=14 cells (4 PI)
8918 14:00:29.384919 u2DelayCellOfst[1]=7 cells (2 PI)
8919 14:00:29.387858 u2DelayCellOfst[2]=0 cells (0 PI)
8920 14:00:29.391237 u2DelayCellOfst[3]=3 cells (1 PI)
8921 14:00:29.394773 u2DelayCellOfst[4]=7 cells (2 PI)
8922 14:00:29.398369 u2DelayCellOfst[5]=17 cells (5 PI)
8923 14:00:29.401200 u2DelayCellOfst[6]=14 cells (4 PI)
8924 14:00:29.404597 u2DelayCellOfst[7]=3 cells (1 PI)
8925 14:00:29.408024 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8926 14:00:29.411106 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8927 14:00:29.414637 == TX Byte 1 ==
8928 14:00:29.417664 u2DelayCellOfst[8]=0 cells (0 PI)
8929 14:00:29.418098 u2DelayCellOfst[9]=7 cells (2 PI)
8930 14:00:29.420972 u2DelayCellOfst[10]=14 cells (4 PI)
8931 14:00:29.424774 u2DelayCellOfst[11]=10 cells (3 PI)
8932 14:00:29.428025 u2DelayCellOfst[12]=17 cells (5 PI)
8933 14:00:29.431196 u2DelayCellOfst[13]=21 cells (6 PI)
8934 14:00:29.436028 u2DelayCellOfst[14]=21 cells (6 PI)
8935 14:00:29.437596 u2DelayCellOfst[15]=21 cells (6 PI)
8936 14:00:29.441212 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8937 14:00:29.448056 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8938 14:00:29.448513 DramC Write-DBI on
8939 14:00:29.448868 ==
8940 14:00:29.451183 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 14:00:29.458322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 14:00:29.458930 ==
8943 14:00:29.459293
8944 14:00:29.459625
8945 14:00:29.459940 TX Vref Scan disable
8946 14:00:29.461946 == TX Byte 0 ==
8947 14:00:29.464940 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8948 14:00:29.468308 == TX Byte 1 ==
8949 14:00:29.471367 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8950 14:00:29.474750 DramC Write-DBI off
8951 14:00:29.475321
8952 14:00:29.475687 [DATLAT]
8953 14:00:29.476020 Freq=1600, CH1 RK1
8954 14:00:29.476341
8955 14:00:29.478341 DATLAT Default: 0xf
8956 14:00:29.479012 0, 0xFFFF, sum = 0
8957 14:00:29.481740 1, 0xFFFF, sum = 0
8958 14:00:29.482201 2, 0xFFFF, sum = 0
8959 14:00:29.485156 3, 0xFFFF, sum = 0
8960 14:00:29.488646 4, 0xFFFF, sum = 0
8961 14:00:29.489208 5, 0xFFFF, sum = 0
8962 14:00:29.491605 6, 0xFFFF, sum = 0
8963 14:00:29.492166 7, 0xFFFF, sum = 0
8964 14:00:29.495324 8, 0xFFFF, sum = 0
8965 14:00:29.495888 9, 0xFFFF, sum = 0
8966 14:00:29.498524 10, 0xFFFF, sum = 0
8967 14:00:29.498986 11, 0xFFFF, sum = 0
8968 14:00:29.501685 12, 0xFFFF, sum = 0
8969 14:00:29.502240 13, 0xFFFF, sum = 0
8970 14:00:29.505147 14, 0x0, sum = 1
8971 14:00:29.505709 15, 0x0, sum = 2
8972 14:00:29.508524 16, 0x0, sum = 3
8973 14:00:29.508997 17, 0x0, sum = 4
8974 14:00:29.512137 best_step = 15
8975 14:00:29.512689
8976 14:00:29.513042 ==
8977 14:00:29.515139 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 14:00:29.518339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 14:00:29.519034 ==
8980 14:00:29.519412 RX Vref Scan: 0
8981 14:00:29.519841
8982 14:00:29.521673 RX Vref 0 -> 0, step: 1
8983 14:00:29.522309
8984 14:00:29.525107 RX Delay 11 -> 252, step: 4
8985 14:00:29.528723 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8986 14:00:29.535020 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8987 14:00:29.538727 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8988 14:00:29.542092 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8989 14:00:29.544968 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8990 14:00:29.548287 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8991 14:00:29.551485 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8992 14:00:29.559127 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8993 14:00:29.561774 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8994 14:00:29.564960 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8995 14:00:29.568003 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8996 14:00:29.571792 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8997 14:00:29.578588 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8998 14:00:29.581665 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8999 14:00:29.584737 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9000 14:00:29.588871 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9001 14:00:29.589383 ==
9002 14:00:29.591606 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 14:00:29.598756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 14:00:29.599292 ==
9005 14:00:29.599631 DQS Delay:
9006 14:00:29.602239 DQS0 = 0, DQS1 = 0
9007 14:00:29.602832 DQM Delay:
9008 14:00:29.605057 DQM0 = 129, DQM1 = 126
9009 14:00:29.605560 DQ Delay:
9010 14:00:29.608303 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9011 14:00:29.611973 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9012 14:00:29.615013 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
9013 14:00:29.618030 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9014 14:00:29.618497
9015 14:00:29.618831
9016 14:00:29.619130
9017 14:00:29.621138 [DramC_TX_OE_Calibration] TA2
9018 14:00:29.624662 Original DQ_B0 (3 6) =30, OEN = 27
9019 14:00:29.628576 Original DQ_B1 (3 6) =30, OEN = 27
9020 14:00:29.631383 24, 0x0, End_B0=24 End_B1=24
9021 14:00:29.631805 25, 0x0, End_B0=25 End_B1=25
9022 14:00:29.635002 26, 0x0, End_B0=26 End_B1=26
9023 14:00:29.638116 27, 0x0, End_B0=27 End_B1=27
9024 14:00:29.641883 28, 0x0, End_B0=28 End_B1=28
9025 14:00:29.645185 29, 0x0, End_B0=29 End_B1=29
9026 14:00:29.645610 30, 0x0, End_B0=30 End_B1=30
9027 14:00:29.648760 31, 0x4141, End_B0=30 End_B1=30
9028 14:00:29.651991 Byte0 end_step=30 best_step=27
9029 14:00:29.655088 Byte1 end_step=30 best_step=27
9030 14:00:29.658886 Byte0 TX OE(2T, 0.5T) = (3, 3)
9031 14:00:29.659402 Byte1 TX OE(2T, 0.5T) = (3, 3)
9032 14:00:29.661817
9033 14:00:29.662329
9034 14:00:29.668341 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9035 14:00:29.672072 CH1 RK1: MR19=303, MR18=1117
9036 14:00:29.678951 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9037 14:00:29.681854 [RxdqsGatingPostProcess] freq 1600
9038 14:00:29.685714 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9039 14:00:29.688361 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 14:00:29.692327 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 14:00:29.695023 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 14:00:29.699060 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 14:00:29.702105 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 14:00:29.706007 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 14:00:29.708778 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 14:00:29.712369 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 14:00:29.714827 Pre-setting of DQS Precalculation
9048 14:00:29.718923 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9049 14:00:29.725171 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9050 14:00:29.731575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9051 14:00:29.732133
9052 14:00:29.732492
9053 14:00:29.735112 [Calibration Summary] 3200 Mbps
9054 14:00:29.738498 CH 0, Rank 0
9055 14:00:29.738953 SW Impedance : PASS
9056 14:00:29.742014 DUTY Scan : NO K
9057 14:00:29.745255 ZQ Calibration : PASS
9058 14:00:29.745711 Jitter Meter : NO K
9059 14:00:29.748294 CBT Training : PASS
9060 14:00:29.752340 Write leveling : PASS
9061 14:00:29.752916 RX DQS gating : PASS
9062 14:00:29.755619 RX DQ/DQS(RDDQC) : PASS
9063 14:00:29.756174 TX DQ/DQS : PASS
9064 14:00:29.758520 RX DATLAT : PASS
9065 14:00:29.762077 RX DQ/DQS(Engine): PASS
9066 14:00:29.762858 TX OE : PASS
9067 14:00:29.765166 All Pass.
9068 14:00:29.765718
9069 14:00:29.766093 CH 0, Rank 1
9070 14:00:29.768902 SW Impedance : PASS
9071 14:00:29.769357 DUTY Scan : NO K
9072 14:00:29.772033 ZQ Calibration : PASS
9073 14:00:29.775358 Jitter Meter : NO K
9074 14:00:29.775814 CBT Training : PASS
9075 14:00:29.778299 Write leveling : PASS
9076 14:00:29.781915 RX DQS gating : PASS
9077 14:00:29.782520 RX DQ/DQS(RDDQC) : PASS
9078 14:00:29.785412 TX DQ/DQS : PASS
9079 14:00:29.789231 RX DATLAT : PASS
9080 14:00:29.789781 RX DQ/DQS(Engine): PASS
9081 14:00:29.792860 TX OE : PASS
9082 14:00:29.793423 All Pass.
9083 14:00:29.793784
9084 14:00:29.795217 CH 1, Rank 0
9085 14:00:29.795671 SW Impedance : PASS
9086 14:00:29.798863 DUTY Scan : NO K
9087 14:00:29.799414 ZQ Calibration : PASS
9088 14:00:29.802323 Jitter Meter : NO K
9089 14:00:29.805128 CBT Training : PASS
9090 14:00:29.805583 Write leveling : PASS
9091 14:00:29.808302 RX DQS gating : PASS
9092 14:00:29.811944 RX DQ/DQS(RDDQC) : PASS
9093 14:00:29.812517 TX DQ/DQS : PASS
9094 14:00:29.815444 RX DATLAT : PASS
9095 14:00:29.818436 RX DQ/DQS(Engine): PASS
9096 14:00:29.818903 TX OE : PASS
9097 14:00:29.821807 All Pass.
9098 14:00:29.822383
9099 14:00:29.822812 CH 1, Rank 1
9100 14:00:29.824858 SW Impedance : PASS
9101 14:00:29.825316 DUTY Scan : NO K
9102 14:00:29.828440 ZQ Calibration : PASS
9103 14:00:29.831790 Jitter Meter : NO K
9104 14:00:29.832355 CBT Training : PASS
9105 14:00:29.835629 Write leveling : PASS
9106 14:00:29.836082 RX DQS gating : PASS
9107 14:00:29.838294 RX DQ/DQS(RDDQC) : PASS
9108 14:00:29.842128 TX DQ/DQS : PASS
9109 14:00:29.842744 RX DATLAT : PASS
9110 14:00:29.845399 RX DQ/DQS(Engine): PASS
9111 14:00:29.848780 TX OE : PASS
9112 14:00:29.849240 All Pass.
9113 14:00:29.849598
9114 14:00:29.851661 DramC Write-DBI on
9115 14:00:29.852117 PER_BANK_REFRESH: Hybrid Mode
9116 14:00:29.855071 TX_TRACKING: ON
9117 14:00:29.865368 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9118 14:00:29.872699 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9119 14:00:29.879120 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9120 14:00:29.882254 [FAST_K] Save calibration result to emmc
9121 14:00:29.885748 sync common calibartion params.
9122 14:00:29.888809 sync cbt_mode0:1, 1:1
9123 14:00:29.889361 dram_init: ddr_geometry: 2
9124 14:00:29.892671 dram_init: ddr_geometry: 2
9125 14:00:29.895429 dram_init: ddr_geometry: 2
9126 14:00:29.895961 0:dram_rank_size:100000000
9127 14:00:29.899192 1:dram_rank_size:100000000
9128 14:00:29.906145 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9129 14:00:29.908795 DFS_SHUFFLE_HW_MODE: ON
9130 14:00:29.912029 dramc_set_vcore_voltage set vcore to 725000
9131 14:00:29.912592 Read voltage for 1600, 0
9132 14:00:29.915709 Vio18 = 0
9133 14:00:29.916256 Vcore = 725000
9134 14:00:29.916615 Vdram = 0
9135 14:00:29.918529 Vddq = 0
9136 14:00:29.919012 Vmddr = 0
9137 14:00:29.922309 switch to 3200 Mbps bootup
9138 14:00:29.922912 [DramcRunTimeConfig]
9139 14:00:29.923354 PHYPLL
9140 14:00:29.925759 DPM_CONTROL_AFTERK: ON
9141 14:00:29.928866 PER_BANK_REFRESH: ON
9142 14:00:29.929415 REFRESH_OVERHEAD_REDUCTION: ON
9143 14:00:29.931882 CMD_PICG_NEW_MODE: OFF
9144 14:00:29.935877 XRTWTW_NEW_MODE: ON
9145 14:00:29.936330 XRTRTR_NEW_MODE: ON
9146 14:00:29.938777 TX_TRACKING: ON
9147 14:00:29.939233 RDSEL_TRACKING: OFF
9148 14:00:29.942549 DQS Precalculation for DVFS: ON
9149 14:00:29.943134 RX_TRACKING: OFF
9150 14:00:29.945327 HW_GATING DBG: ON
9151 14:00:29.945786 ZQCS_ENABLE_LP4: ON
9152 14:00:29.948532 RX_PICG_NEW_MODE: ON
9153 14:00:29.951817 TX_PICG_NEW_MODE: ON
9154 14:00:29.952273 ENABLE_RX_DCM_DPHY: ON
9155 14:00:29.955267 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9156 14:00:29.958736 DUMMY_READ_FOR_TRACKING: OFF
9157 14:00:29.961795 !!! SPM_CONTROL_AFTERK: OFF
9158 14:00:29.962286 !!! SPM could not control APHY
9159 14:00:29.965161 IMPEDANCE_TRACKING: ON
9160 14:00:29.968422 TEMP_SENSOR: ON
9161 14:00:29.968832 HW_SAVE_FOR_SR: OFF
9162 14:00:29.971868 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9163 14:00:29.975337 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9164 14:00:29.979093 Read ODT Tracking: ON
9165 14:00:29.979610 Refresh Rate DeBounce: ON
9166 14:00:29.981982 DFS_NO_QUEUE_FLUSH: ON
9167 14:00:29.985361 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9168 14:00:29.989072 ENABLE_DFS_RUNTIME_MRW: OFF
9169 14:00:29.989931 DDR_RESERVE_NEW_MODE: ON
9170 14:00:29.992202 MR_CBT_SWITCH_FREQ: ON
9171 14:00:29.995246 =========================
9172 14:00:30.013365 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9173 14:00:30.016434 dram_init: ddr_geometry: 2
9174 14:00:30.034694 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9175 14:00:30.038267 dram_init: dram init end (result: 0)
9176 14:00:30.045432 DRAM-K: Full calibration passed in 24592 msecs
9177 14:00:30.047900 MRC: failed to locate region type 0.
9178 14:00:30.048312 DRAM rank0 size:0x100000000,
9179 14:00:30.051172 DRAM rank1 size=0x100000000
9180 14:00:30.061698 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9181 14:00:30.068150 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9182 14:00:30.074620 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9183 14:00:30.081396 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9184 14:00:30.084845 DRAM rank0 size:0x100000000,
9185 14:00:30.087919 DRAM rank1 size=0x100000000
9186 14:00:30.088329 CBMEM:
9187 14:00:30.091236 IMD: root @ 0xfffff000 254 entries.
9188 14:00:30.094848 IMD: root @ 0xffffec00 62 entries.
9189 14:00:30.097747 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9190 14:00:30.101492 WARNING: RO_VPD is uninitialized or empty.
9191 14:00:30.107862 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9192 14:00:30.114898 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9193 14:00:30.127573 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9194 14:00:30.138845 BS: romstage times (exec / console): total (unknown) / 24092 ms
9195 14:00:30.139368
9196 14:00:30.139693
9197 14:00:30.149172 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9198 14:00:30.152911 ARM64: Exception handlers installed.
9199 14:00:30.155890 ARM64: Testing exception
9200 14:00:30.159069 ARM64: Done test exception
9201 14:00:30.159480 Enumerating buses...
9202 14:00:30.162861 Show all devs... Before device enumeration.
9203 14:00:30.166124 Root Device: enabled 1
9204 14:00:30.169038 CPU_CLUSTER: 0: enabled 1
9205 14:00:30.169548 CPU: 00: enabled 1
9206 14:00:30.172148 Compare with tree...
9207 14:00:30.172560 Root Device: enabled 1
9208 14:00:30.175676 CPU_CLUSTER: 0: enabled 1
9209 14:00:30.179542 CPU: 00: enabled 1
9210 14:00:30.180050 Root Device scanning...
9211 14:00:30.182525 scan_static_bus for Root Device
9212 14:00:30.185714 CPU_CLUSTER: 0 enabled
9213 14:00:30.189036 scan_static_bus for Root Device done
9214 14:00:30.192842 scan_bus: bus Root Device finished in 8 msecs
9215 14:00:30.193358 done
9216 14:00:30.199466 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9217 14:00:30.202758 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9218 14:00:30.209152 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9219 14:00:30.212261 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9220 14:00:30.216262 Allocating resources...
9221 14:00:30.216774 Reading resources...
9222 14:00:30.219089 Root Device read_resources bus 0 link: 0
9223 14:00:30.222597 DRAM rank0 size:0x100000000,
9224 14:00:30.226762 DRAM rank1 size=0x100000000
9225 14:00:30.229300 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9226 14:00:30.232182 CPU: 00 missing read_resources
9227 14:00:30.235987 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9228 14:00:30.238861 Root Device read_resources bus 0 link: 0 done
9229 14:00:30.243003 Done reading resources.
9230 14:00:30.249285 Show resources in subtree (Root Device)...After reading.
9231 14:00:30.252974 Root Device child on link 0 CPU_CLUSTER: 0
9232 14:00:30.256122 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 14:00:30.266139 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 14:00:30.266696 CPU: 00
9235 14:00:30.269446 Root Device assign_resources, bus 0 link: 0
9236 14:00:30.272920 CPU_CLUSTER: 0 missing set_resources
9237 14:00:30.275547 Root Device assign_resources, bus 0 link: 0 done
9238 14:00:30.279076 Done setting resources.
9239 14:00:30.286033 Show resources in subtree (Root Device)...After assigning values.
9240 14:00:30.289312 Root Device child on link 0 CPU_CLUSTER: 0
9241 14:00:30.292853 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 14:00:30.302721 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 14:00:30.303233 CPU: 00
9244 14:00:30.306240 Done allocating resources.
9245 14:00:30.309545 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9246 14:00:30.312659 Enabling resources...
9247 14:00:30.313175 done.
9248 14:00:30.315877 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9249 14:00:30.319374 Initializing devices...
9250 14:00:30.319784 Root Device init
9251 14:00:30.323165 init hardware done!
9252 14:00:30.325837 0x00000018: ctrlr->caps
9253 14:00:30.326258 52.000 MHz: ctrlr->f_max
9254 14:00:30.329313 0.400 MHz: ctrlr->f_min
9255 14:00:30.332264 0x40ff8080: ctrlr->voltages
9256 14:00:30.332720 sclk: 390625
9257 14:00:30.335854 Bus Width = 1
9258 14:00:30.336377 sclk: 390625
9259 14:00:30.336713 Bus Width = 1
9260 14:00:30.339010 Early init status = 3
9261 14:00:30.342228 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9262 14:00:30.346499 in-header: 03 fc 00 00 01 00 00 00
9263 14:00:30.349799 in-data: 00
9264 14:00:30.353242 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9265 14:00:30.357680 in-header: 03 fd 00 00 00 00 00 00
9266 14:00:30.360976 in-data:
9267 14:00:30.364051 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9268 14:00:30.367451 in-header: 03 fc 00 00 01 00 00 00
9269 14:00:30.370861 in-data: 00
9270 14:00:30.374270 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9271 14:00:30.379392 in-header: 03 fd 00 00 00 00 00 00
9272 14:00:30.382329 in-data:
9273 14:00:30.385959 [SSUSB] Setting up USB HOST controller...
9274 14:00:30.389267 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9275 14:00:30.392979 [SSUSB] phy power-on done.
9276 14:00:30.395692 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9277 14:00:30.402241 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9278 14:00:30.405736 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9279 14:00:30.412201 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9280 14:00:30.419283 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9281 14:00:30.426288 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9282 14:00:30.432428 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9283 14:00:30.438976 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9284 14:00:30.439493 SPM: binary array size = 0x9dc
9285 14:00:30.445765 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9286 14:00:30.452537 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9287 14:00:30.459576 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9288 14:00:30.462780 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9289 14:00:30.465442 configure_display: Starting display init
9290 14:00:30.502012 anx7625_power_on_init: Init interface.
9291 14:00:30.505898 anx7625_disable_pd_protocol: Disabled PD feature.
9292 14:00:30.508660 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9293 14:00:30.536893 anx7625_start_dp_work: Secure OCM version=00
9294 14:00:30.539795 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9295 14:00:30.555021 sp_tx_get_edid_block: EDID Block = 1
9296 14:00:30.657256 Extracted contents:
9297 14:00:30.660678 header: 00 ff ff ff ff ff ff 00
9298 14:00:30.664187 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9299 14:00:30.667227 version: 01 04
9300 14:00:30.670663 basic params: 95 1f 11 78 0a
9301 14:00:30.673908 chroma info: 76 90 94 55 54 90 27 21 50 54
9302 14:00:30.676854 established: 00 00 00
9303 14:00:30.683415 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9304 14:00:30.686854 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9305 14:00:30.693849 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9306 14:00:30.700456 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9307 14:00:30.707155 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9308 14:00:30.710715 extensions: 00
9309 14:00:30.711249 checksum: fb
9310 14:00:30.711615
9311 14:00:30.713795 Manufacturer: IVO Model 57d Serial Number 0
9312 14:00:30.716692 Made week 0 of 2020
9313 14:00:30.717137 EDID version: 1.4
9314 14:00:30.720514 Digital display
9315 14:00:30.724138 6 bits per primary color channel
9316 14:00:30.724558 DisplayPort interface
9317 14:00:30.726798 Maximum image size: 31 cm x 17 cm
9318 14:00:30.730707 Gamma: 220%
9319 14:00:30.731142 Check DPMS levels
9320 14:00:30.733448 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9321 14:00:30.736870 First detailed timing is preferred timing
9322 14:00:30.740218 Established timings supported:
9323 14:00:30.743644 Standard timings supported:
9324 14:00:30.744097 Detailed timings
9325 14:00:30.750906 Hex of detail: 383680a07038204018303c0035ae10000019
9326 14:00:30.753908 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9327 14:00:30.757093 0780 0798 07c8 0820 hborder 0
9328 14:00:30.763640 0438 043b 0447 0458 vborder 0
9329 14:00:30.763936 -hsync -vsync
9330 14:00:30.766919 Did detailed timing
9331 14:00:30.770431 Hex of detail: 000000000000000000000000000000000000
9332 14:00:30.773709 Manufacturer-specified data, tag 0
9333 14:00:30.780208 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9334 14:00:30.780502 ASCII string: InfoVision
9335 14:00:30.787438 Hex of detail: 000000fe00523134304e574635205248200a
9336 14:00:30.787807 ASCII string: R140NWF5 RH
9337 14:00:30.790793 Checksum
9338 14:00:30.791070 Checksum: 0xfb (valid)
9339 14:00:30.796799 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9340 14:00:30.797090 DSI data_rate: 832800000 bps
9341 14:00:30.804983 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9342 14:00:30.808014 anx7625_parse_edid: pixelclock(138800).
9343 14:00:30.811743 hactive(1920), hsync(48), hfp(24), hbp(88)
9344 14:00:30.814628 vactive(1080), vsync(12), vfp(3), vbp(17)
9345 14:00:30.817967 anx7625_dsi_config: config dsi.
9346 14:00:30.825196 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9347 14:00:30.839415 anx7625_dsi_config: success to config DSI
9348 14:00:30.842590 anx7625_dp_start: MIPI phy setup OK.
9349 14:00:30.846228 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9350 14:00:30.848947 mtk_ddp_mode_set invalid vrefresh 60
9351 14:00:30.853081 main_disp_path_setup
9352 14:00:30.853636 ovl_layer_smi_id_en
9353 14:00:30.855779 ovl_layer_smi_id_en
9354 14:00:30.856327 ccorr_config
9355 14:00:30.856686 aal_config
9356 14:00:30.859110 gamma_config
9357 14:00:30.859599 postmask_config
9358 14:00:30.863262 dither_config
9359 14:00:30.866501 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9360 14:00:30.872594 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9361 14:00:30.875653 Root Device init finished in 551 msecs
9362 14:00:30.876109 CPU_CLUSTER: 0 init
9363 14:00:30.886168 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9364 14:00:30.889056 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9365 14:00:30.892807 APU_MBOX 0x190000b0 = 0x10001
9366 14:00:30.895985 APU_MBOX 0x190001b0 = 0x10001
9367 14:00:30.899251 APU_MBOX 0x190005b0 = 0x10001
9368 14:00:30.902583 APU_MBOX 0x190006b0 = 0x10001
9369 14:00:30.906527 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9370 14:00:30.918578 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9371 14:00:30.931038 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9372 14:00:30.937785 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9373 14:00:30.948835 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9374 14:00:30.958310 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9375 14:00:30.961683 CPU_CLUSTER: 0 init finished in 81 msecs
9376 14:00:30.965113 Devices initialized
9377 14:00:30.968176 Show all devs... After init.
9378 14:00:30.968634 Root Device: enabled 1
9379 14:00:30.971761 CPU_CLUSTER: 0: enabled 1
9380 14:00:30.975319 CPU: 00: enabled 1
9381 14:00:30.978345 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9382 14:00:30.981502 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9383 14:00:30.984876 ELOG: NV offset 0x57f000 size 0x1000
9384 14:00:30.992026 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9385 14:00:30.998221 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9386 14:00:31.001678 ELOG: Event(17) added with size 13 at 2024-02-01 14:00:32 UTC
9387 14:00:31.005947 out: cmd=0x121: 03 db 21 01 00 00 00 00
9388 14:00:31.009018 in-header: 03 cb 00 00 2c 00 00 00
9389 14:00:31.022520 in-data: 94 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 14:00:31.029483 ELOG: Event(A1) added with size 10 at 2024-02-01 14:00:32 UTC
9391 14:00:31.036283 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9392 14:00:31.042584 ELOG: Event(A0) added with size 9 at 2024-02-01 14:00:32 UTC
9393 14:00:31.046314 elog_add_boot_reason: Logged dev mode boot
9394 14:00:31.049301 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9395 14:00:31.052274 Finalize devices...
9396 14:00:31.052799 Devices finalized
9397 14:00:31.059765 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9398 14:00:31.062996 Writing coreboot table at 0xffe64000
9399 14:00:31.066558 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 14:00:31.069122 1. 0000000040000000-00000000400fffff: RAM
9401 14:00:31.072439 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 14:00:31.079345 3. 000000004032b000-00000000545fffff: RAM
9403 14:00:31.082862 4. 0000000054600000-000000005465ffff: BL31
9404 14:00:31.085695 5. 0000000054660000-00000000ffe63fff: RAM
9405 14:00:31.089332 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 14:00:31.095907 7. 0000000100000000-000000023fffffff: RAM
9407 14:00:31.096464 Passing 5 GPIOs to payload:
9408 14:00:31.103206 NAME | PORT | POLARITY | VALUE
9409 14:00:31.106186 EC in RW | 0x000000aa | low | undefined
9410 14:00:31.109568 EC interrupt | 0x00000005 | low | undefined
9411 14:00:31.116065 TPM interrupt | 0x000000ab | high | undefined
9412 14:00:31.119218 SD card detect | 0x00000011 | high | undefined
9413 14:00:31.125657 speaker enable | 0x00000093 | high | undefined
9414 14:00:31.129716 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 14:00:31.132868 in-header: 03 f9 00 00 02 00 00 00
9416 14:00:31.133418 in-data: 02 00
9417 14:00:31.135944 ADC[4]: Raw value=899483 ID=7
9418 14:00:31.139184 ADC[3]: Raw value=213336 ID=1
9419 14:00:31.139648 RAM Code: 0x71
9420 14:00:31.142685 ADC[6]: Raw value=74557 ID=0
9421 14:00:31.145957 ADC[5]: Raw value=212229 ID=1
9422 14:00:31.146559 SKU Code: 0x1
9423 14:00:31.153059 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum af6e
9424 14:00:31.156349 coreboot table: 964 bytes.
9425 14:00:31.159041 IMD ROOT 0. 0xfffff000 0x00001000
9426 14:00:31.162987 IMD SMALL 1. 0xffffe000 0x00001000
9427 14:00:31.166080 RO MCACHE 2. 0xffffc000 0x00001104
9428 14:00:31.169300 CONSOLE 3. 0xfff7c000 0x00080000
9429 14:00:31.172490 FMAP 4. 0xfff7b000 0x00000452
9430 14:00:31.176004 TIME STAMP 5. 0xfff7a000 0x00000910
9431 14:00:31.178953 VBOOT WORK 6. 0xfff66000 0x00014000
9432 14:00:31.182635 RAMOOPS 7. 0xffe66000 0x00100000
9433 14:00:31.183143 COREBOOT 8. 0xffe64000 0x00002000
9434 14:00:31.185621 IMD small region:
9435 14:00:31.189126 IMD ROOT 0. 0xffffec00 0x00000400
9436 14:00:31.192080 VPD 1. 0xffffeb80 0x0000006c
9437 14:00:31.196333 MMC STATUS 2. 0xffffeb60 0x00000004
9438 14:00:31.202780 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 14:00:31.203194 Probing TPM: done!
9440 14:00:31.209569 Connected to device vid:did:rid of 1ae0:0028:00
9441 14:00:31.216510 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9442 14:00:31.219252 Initialized TPM device CR50 revision 0
9443 14:00:31.223351 Checking cr50 for pending updates
9444 14:00:31.228693 Reading cr50 TPM mode
9445 14:00:31.237230 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9446 14:00:31.243624 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 14:00:31.283658 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9448 14:00:31.287306 Checking segment from ROM address 0x40100000
9449 14:00:31.291439 Checking segment from ROM address 0x4010001c
9450 14:00:31.297964 Loading segment from ROM address 0x40100000
9451 14:00:31.298594 code (compression=0)
9452 14:00:31.304504 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 14:00:31.314615 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 14:00:31.315165 it's not compressed!
9455 14:00:31.321118 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 14:00:31.324499 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 14:00:31.344901 Loading segment from ROM address 0x4010001c
9458 14:00:31.345462 Entry Point 0x80000000
9459 14:00:31.347492 Loaded segments
9460 14:00:31.351761 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 14:00:31.358230 Jumping to boot code at 0x80000000(0xffe64000)
9462 14:00:31.365131 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 14:00:31.371159 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 14:00:31.379014 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9465 14:00:31.382137 Checking segment from ROM address 0x40100000
9466 14:00:31.385693 Checking segment from ROM address 0x4010001c
9467 14:00:31.392494 Loading segment from ROM address 0x40100000
9468 14:00:31.393045 code (compression=1)
9469 14:00:31.399337 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 14:00:31.409149 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 14:00:31.409704 using LZMA
9472 14:00:31.416840 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 14:00:31.424098 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 14:00:31.427473 Loading segment from ROM address 0x4010001c
9475 14:00:31.428001 Entry Point 0x54601000
9476 14:00:31.430694 Loaded segments
9477 14:00:31.433978 NOTICE: MT8192 bl31_setup
9478 14:00:31.440828 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 14:00:31.443972 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 14:00:31.447797 WARNING: region 0:
9481 14:00:31.450950 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 14:00:31.451414 WARNING: region 1:
9483 14:00:31.457631 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 14:00:31.461552 WARNING: region 2:
9485 14:00:31.464233 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 14:00:31.467685 WARNING: region 3:
9487 14:00:31.470892 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 14:00:31.474629 WARNING: region 4:
9489 14:00:31.477491 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 14:00:31.480769 WARNING: region 5:
9491 14:00:31.484512 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 14:00:31.487379 WARNING: region 6:
9493 14:00:31.490712 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 14:00:31.491134 WARNING: region 7:
9495 14:00:31.497625 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 14:00:31.504213 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 14:00:31.508016 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 14:00:31.511376 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 14:00:31.514287 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 14:00:31.521619 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 14:00:31.524248 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 14:00:31.530840 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 14:00:31.534281 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 14:00:31.537623 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 14:00:31.544631 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 14:00:31.547740 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 14:00:31.551318 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 14:00:31.557796 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 14:00:31.561384 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 14:00:31.567920 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 14:00:31.571413 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 14:00:31.574523 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 14:00:31.581430 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 14:00:31.584809 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 14:00:31.587950 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 14:00:31.595256 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 14:00:31.598305 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 14:00:31.604744 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 14:00:31.607874 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 14:00:31.612142 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 14:00:31.618103 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 14:00:31.621601 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 14:00:31.625000 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 14:00:31.631594 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 14:00:31.634438 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 14:00:31.641298 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 14:00:31.644676 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 14:00:31.648125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 14:00:31.654596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 14:00:31.658351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 14:00:31.661312 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 14:00:31.664880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 14:00:31.671920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 14:00:31.675333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 14:00:31.678368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 14:00:31.682494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 14:00:31.684537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 14:00:31.691535 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 14:00:31.694741 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 14:00:31.698357 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 14:00:31.701599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 14:00:31.708185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 14:00:31.712045 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 14:00:31.715087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 14:00:31.721612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 14:00:31.725100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 14:00:31.732141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 14:00:31.735119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 14:00:31.738391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 14:00:31.745255 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 14:00:31.749042 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 14:00:31.755654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 14:00:31.758620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 14:00:31.765237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 14:00:31.769153 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 14:00:31.772055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 14:00:31.778506 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 14:00:31.782520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 14:00:31.788941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 14:00:31.792160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 14:00:31.799301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 14:00:31.802496 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 14:00:31.805976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 14:00:31.812847 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 14:00:31.816133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 14:00:31.823728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 14:00:31.825759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 14:00:31.829384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 14:00:31.835984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 14:00:31.839193 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 14:00:31.846191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 14:00:31.849387 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 14:00:31.855973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 14:00:31.859606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 14:00:31.862689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 14:00:31.869442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 14:00:31.872828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 14:00:31.879693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 14:00:31.882765 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 14:00:31.885941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 14:00:31.892595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 14:00:31.896540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 14:00:31.902772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 14:00:31.905845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 14:00:31.912686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 14:00:31.915957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 14:00:31.919494 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 14:00:31.926503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 14:00:31.929528 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 14:00:31.936239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 14:00:31.939972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 14:00:31.943764 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 14:00:31.949759 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 14:00:31.953431 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 14:00:31.956234 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 14:00:31.959612 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 14:00:31.966507 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 14:00:31.969692 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 14:00:31.976481 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 14:00:31.979779 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 14:00:31.983197 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 14:00:31.990062 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 14:00:31.993554 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 14:00:32.000211 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 14:00:32.003200 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 14:00:32.006534 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 14:00:32.013292 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 14:00:32.017095 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 14:00:32.020105 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 14:00:32.026952 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 14:00:32.030206 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 14:00:32.033540 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 14:00:32.040193 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 14:00:32.043878 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 14:00:32.047049 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 14:00:32.053876 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 14:00:32.057427 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 14:00:32.060555 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 14:00:32.063996 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 14:00:32.070979 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 14:00:32.074290 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 14:00:32.077572 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 14:00:32.083926 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 14:00:32.087231 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 14:00:32.094488 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 14:00:32.097247 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 14:00:32.100502 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 14:00:32.107344 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 14:00:32.110726 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 14:00:32.114297 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 14:00:32.120828 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 14:00:32.124105 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 14:00:32.127774 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 14:00:32.134446 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 14:00:32.137815 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 14:00:32.144262 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 14:00:32.147662 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 14:00:32.151037 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 14:00:32.157443 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 14:00:32.161046 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 14:00:32.167517 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 14:00:32.171675 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 14:00:32.174344 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 14:00:32.181082 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 14:00:32.184406 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 14:00:32.190949 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 14:00:32.194392 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 14:00:32.197954 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 14:00:32.204737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 14:00:32.207849 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 14:00:32.211064 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 14:00:32.218314 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 14:00:32.221266 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 14:00:32.224998 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 14:00:32.231573 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 14:00:32.235262 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 14:00:32.241251 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 14:00:32.244636 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 14:00:32.248100 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 14:00:32.255124 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 14:00:32.258060 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 14:00:32.264614 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 14:00:32.268184 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 14:00:32.271937 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 14:00:32.277926 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 14:00:32.281378 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 14:00:32.284922 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 14:00:32.291394 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 14:00:32.295087 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 14:00:32.301197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 14:00:32.304940 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 14:00:32.308437 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 14:00:32.315102 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 14:00:32.317974 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 14:00:32.324906 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 14:00:32.328253 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 14:00:32.331337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 14:00:32.338499 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 14:00:32.341688 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 14:00:32.344969 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 14:00:32.351590 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 14:00:32.354814 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 14:00:32.361494 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 14:00:32.365141 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 14:00:32.368448 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 14:00:32.374834 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 14:00:32.377995 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 14:00:32.384924 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 14:00:32.388218 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 14:00:32.391669 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 14:00:32.397906 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 14:00:32.401407 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 14:00:32.408410 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 14:00:32.411737 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 14:00:32.417844 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 14:00:32.421189 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 14:00:32.424743 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 14:00:32.431500 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 14:00:32.434703 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 14:00:32.441468 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 14:00:32.445259 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 14:00:32.448145 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 14:00:32.454984 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 14:00:32.458490 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 14:00:32.465098 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 14:00:32.468311 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 14:00:32.471731 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 14:00:32.478130 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 14:00:32.481542 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 14:00:32.488602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 14:00:32.491810 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 14:00:32.498592 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 14:00:32.501478 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 14:00:32.505055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 14:00:32.512017 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 14:00:32.514855 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 14:00:32.521537 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 14:00:32.524915 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 14:00:32.528112 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 14:00:32.534890 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 14:00:32.538446 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 14:00:32.544708 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 14:00:32.548408 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 14:00:32.551897 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 14:00:32.558350 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 14:00:32.561815 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 14:00:32.564716 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 14:00:32.568511 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 14:00:32.572027 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 14:00:32.578247 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 14:00:32.581512 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 14:00:32.588201 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 14:00:32.591738 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 14:00:32.595254 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 14:00:32.601717 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 14:00:32.604934 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 14:00:32.608631 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 14:00:32.615349 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 14:00:32.618262 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 14:00:32.621679 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 14:00:32.628452 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 14:00:32.631777 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 14:00:32.638197 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 14:00:32.641776 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 14:00:32.645133 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 14:00:32.651823 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 14:00:32.655471 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 14:00:32.658566 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 14:00:32.665053 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 14:00:32.668657 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 14:00:32.672119 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 14:00:32.678374 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 14:00:32.681735 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 14:00:32.685082 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 14:00:32.691750 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 14:00:32.695184 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 14:00:32.702098 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 14:00:32.705324 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 14:00:32.708635 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 14:00:32.714962 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 14:00:32.718317 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 14:00:32.721708 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 14:00:32.728484 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 14:00:32.731594 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 14:00:32.735260 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 14:00:32.738707 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 14:00:32.744809 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 14:00:32.748924 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 14:00:32.751531 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 14:00:32.755103 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 14:00:32.762004 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 14:00:32.765531 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 14:00:32.768662 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 14:00:32.771816 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 14:00:32.778387 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 14:00:32.781738 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 14:00:32.785313 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 14:00:32.791627 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 14:00:32.795014 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 14:00:32.798427 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 14:00:32.805269 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 14:00:32.808210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 14:00:32.815063 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 14:00:32.818276 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 14:00:32.821655 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 14:00:32.828763 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 14:00:32.831686 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 14:00:32.838974 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 14:00:32.842095 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 14:00:32.845190 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 14:00:32.851981 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 14:00:32.855148 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 14:00:32.861736 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 14:00:32.865363 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 14:00:32.868858 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 14:00:32.875044 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 14:00:32.878872 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 14:00:32.885347 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 14:00:32.889809 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 14:00:32.891864 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 14:00:32.898500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 14:00:32.902804 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 14:00:32.908625 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 14:00:32.912020 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 14:00:32.915287 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 14:00:32.922272 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 14:00:32.925440 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 14:00:32.932351 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 14:00:32.935270 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 14:00:32.938919 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 14:00:32.945147 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 14:00:32.949109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 14:00:32.955457 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 14:00:32.958869 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 14:00:32.965702 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 14:00:32.969076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 14:00:32.972070 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 14:00:32.978748 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 14:00:32.982154 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 14:00:32.985513 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 14:00:32.991736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 14:00:32.995348 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 14:00:33.002118 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 14:00:33.005086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 14:00:33.009067 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 14:00:33.014962 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 14:00:33.018489 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 14:00:33.025301 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 14:00:33.028261 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 14:00:33.035406 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 14:00:33.038381 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 14:00:33.041746 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 14:00:33.048840 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 14:00:33.052079 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 14:00:33.058444 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 14:00:33.061902 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 14:00:33.065627 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 14:00:33.071568 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 14:00:33.075256 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 14:00:33.081755 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 14:00:33.085333 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 14:00:33.089063 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 14:00:33.095645 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 14:00:33.098783 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 14:00:33.105169 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 14:00:33.109367 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 14:00:33.112360 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 14:00:33.118902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 14:00:33.121902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 14:00:33.128757 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 14:00:33.132184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 14:00:33.135196 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 14:00:33.142355 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 14:00:33.145097 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 14:00:33.152376 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 14:00:33.155371 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 14:00:33.158740 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 14:00:33.165080 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 14:00:33.168841 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 14:00:33.175143 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 14:00:33.179317 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 14:00:33.185642 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 14:00:33.188552 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 14:00:33.195731 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 14:00:33.198855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 14:00:33.201957 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 14:00:33.208801 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 14:00:33.212235 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 14:00:33.219154 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 14:00:33.222061 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 14:00:33.228784 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 14:00:33.232471 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 14:00:33.235678 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 14:00:33.242033 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 14:00:33.245508 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 14:00:33.252243 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 14:00:33.255767 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 14:00:33.262480 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 14:00:33.265381 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 14:00:33.269397 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 14:00:33.275916 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 14:00:33.279381 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 14:00:33.285992 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 14:00:33.290046 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 14:00:33.292040 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 14:00:33.298704 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 14:00:33.302241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 14:00:33.308739 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 14:00:33.311783 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 14:00:33.318530 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 14:00:33.322338 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 14:00:33.325472 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 14:00:33.332228 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 14:00:33.335530 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 14:00:33.342167 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 14:00:33.345595 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 14:00:33.349452 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 14:00:33.355557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 14:00:33.359102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 14:00:33.365388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 14:00:33.368904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 14:00:33.375887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 14:00:33.379260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 14:00:33.385292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 14:00:33.389019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 14:00:33.396000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 14:00:33.398957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 14:00:33.405970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 14:00:33.409071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 14:00:33.413169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 14:00:33.419424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 14:00:33.422305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 14:00:33.428972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 14:00:33.432337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 14:00:33.438930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 14:00:33.442484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 14:00:33.449225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 14:00:33.452630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 14:00:33.459438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 14:00:33.462815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 14:00:33.469271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 14:00:33.473159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 14:00:33.479160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 14:00:33.482721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 14:00:33.489069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 14:00:33.492519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 14:00:33.499796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 14:00:33.502323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 14:00:33.509310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 14:00:33.512926 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 14:00:33.515749 INFO: [APUAPC] vio 0
9932 14:00:33.519074 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 14:00:33.522423 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 14:00:33.525837 INFO: [APUAPC] D0_APC_0: 0x400510
9935 14:00:33.529476 INFO: [APUAPC] D0_APC_1: 0x0
9936 14:00:33.533075 INFO: [APUAPC] D0_APC_2: 0x1540
9937 14:00:33.536117 INFO: [APUAPC] D0_APC_3: 0x0
9938 14:00:33.538913 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 14:00:33.542429 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 14:00:33.546052 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 14:00:33.549524 INFO: [APUAPC] D1_APC_3: 0x0
9942 14:00:33.552487 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 14:00:33.555834 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 14:00:33.559423 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 14:00:33.562998 INFO: [APUAPC] D2_APC_3: 0x0
9946 14:00:33.566461 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 14:00:33.569451 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 14:00:33.572659 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 14:00:33.575955 INFO: [APUAPC] D3_APC_3: 0x0
9950 14:00:33.579481 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 14:00:33.582525 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 14:00:33.586219 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 14:00:33.589755 INFO: [APUAPC] D4_APC_3: 0x0
9954 14:00:33.592464 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 14:00:33.596372 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 14:00:33.599270 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 14:00:33.602505 INFO: [APUAPC] D5_APC_3: 0x0
9958 14:00:33.606104 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 14:00:33.609581 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 14:00:33.612335 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 14:00:33.616084 INFO: [APUAPC] D6_APC_3: 0x0
9962 14:00:33.619406 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 14:00:33.622524 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 14:00:33.625762 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 14:00:33.626178 INFO: [APUAPC] D7_APC_3: 0x0
9966 14:00:33.629318 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 14:00:33.632574 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 14:00:33.636159 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 14:00:33.639273 INFO: [APUAPC] D8_APC_3: 0x0
9970 14:00:33.642892 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 14:00:33.645903 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 14:00:33.649522 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 14:00:33.652327 INFO: [APUAPC] D9_APC_3: 0x0
9974 14:00:33.655733 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 14:00:33.659170 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 14:00:33.663096 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 14:00:33.665650 INFO: [APUAPC] D10_APC_3: 0x0
9978 14:00:33.669000 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 14:00:33.673010 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 14:00:33.675927 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 14:00:33.679273 INFO: [APUAPC] D11_APC_3: 0x0
9982 14:00:33.682191 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 14:00:33.685893 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 14:00:33.689600 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 14:00:33.692661 INFO: [APUAPC] D12_APC_3: 0x0
9986 14:00:33.695755 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 14:00:33.699034 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 14:00:33.702728 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 14:00:33.705545 INFO: [APUAPC] D13_APC_3: 0x0
9990 14:00:33.709600 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 14:00:33.713002 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 14:00:33.715636 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 14:00:33.719102 INFO: [APUAPC] D14_APC_3: 0x0
9994 14:00:33.722250 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 14:00:33.726247 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 14:00:33.729218 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 14:00:33.732348 INFO: [APUAPC] D15_APC_3: 0x0
9998 14:00:33.735937 INFO: [APUAPC] APC_CON: 0x4
9999 14:00:33.739170 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 14:00:33.742685 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 14:00:33.745340 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 14:00:33.748872 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 14:00:33.752157 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 14:00:33.755995 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 14:00:33.756404 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 14:00:33.759116 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 14:00:33.762173 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 14:00:33.765604 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 14:00:33.768594 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 14:00:33.772176 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 14:00:33.775411 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 14:00:33.779192 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 14:00:33.781990 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 14:00:33.785364 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 14:00:33.788505 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 14:00:33.788919 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 14:00:33.792095 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 14:00:33.795634 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 14:00:33.798807 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 14:00:33.802140 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 14:00:33.805490 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 14:00:33.808975 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 14:00:33.812311 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 14:00:33.815374 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 14:00:33.818935 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 14:00:33.822632 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 14:00:33.825608 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 14:00:33.828885 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 14:00:33.829361 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 14:00:33.832199 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 14:00:33.835605 INFO: [NOCDAPC] APC_CON: 0x4
10032 14:00:33.838825 INFO: [APUAPC] set_apusys_apc done
10033 14:00:33.842141 INFO: [DEVAPC] devapc_init done
10034 14:00:33.848608 INFO: GICv3 without legacy support detected.
10035 14:00:33.852263 INFO: ARM GICv3 driver initialized in EL3
10036 14:00:33.856141 INFO: Maximum SPI INTID supported: 639
10037 14:00:33.858777 INFO: BL31: Initializing runtime services
10038 14:00:33.865582 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 14:00:33.869281 INFO: SPM: enable CPC mode
10040 14:00:33.872323 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 14:00:33.878924 INFO: BL31: Preparing for EL3 exit to normal world
10042 14:00:33.882113 INFO: Entry point address = 0x80000000
10043 14:00:33.882561 INFO: SPSR = 0x8
10044 14:00:33.888455
10045 14:00:33.888884
10046 14:00:33.889373
10047 14:00:33.891625 Starting depthcharge on Spherion...
10048 14:00:33.892043
10049 14:00:33.892372 Wipe memory regions:
10050 14:00:33.892678
10051 14:00:33.895289 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10052 14:00:33.895783 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10053 14:00:33.896193 Setting prompt string to ['asurada:']
10054 14:00:33.896743 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10055 14:00:33.897425 [0x00000040000000, 0x00000054600000)
10056 14:00:34.017688
10057 14:00:34.018251 [0x00000054660000, 0x00000080000000)
10058 14:00:34.277871
10059 14:00:34.278485 [0x000000821a7280, 0x000000ffe64000)
10060 14:00:35.022664
10061 14:00:35.023150 [0x00000100000000, 0x00000240000000)
10062 14:00:36.912896
10063 14:00:36.916547 Initializing XHCI USB controller at 0x11200000.
10064 14:00:37.954769
10065 14:00:37.957605 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 14:00:37.958168
10067 14:00:37.958662
10068 14:00:37.958984
10069 14:00:37.959750 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 14:00:38.061078 asurada: tftpboot 192.168.201.1 12682978/tftp-deploy-ut4sv5oc/kernel/image.itb 12682978/tftp-deploy-ut4sv5oc/kernel/cmdline
10072 14:00:38.061799 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 14:00:38.062434 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10074 14:00:38.067478 tftpboot 192.168.201.1 12682978/tftp-deploy-ut4sv5oc/kernel/image.ittp-deploy-ut4sv5oc/kernel/cmdline
10075 14:00:38.067889
10076 14:00:38.068255 Waiting for link
10077 14:00:38.227193
10078 14:00:38.227832 R8152: Initializing
10079 14:00:38.228336
10080 14:00:38.230422 Version 6 (ocp_data = 5c30)
10081 14:00:38.230913
10082 14:00:38.233867 R8152: Done initializing
10083 14:00:38.234536
10084 14:00:38.235052 Adding net device
10085 14:00:40.102046
10086 14:00:40.102641 done.
10087 14:00:40.103013
10088 14:00:40.103352 MAC: 00:24:32:30:78:52
10089 14:00:40.103682
10090 14:00:40.105360 Sending DHCP discover... done.
10091 14:00:40.105835
10092 14:00:40.108182 Waiting for reply... done.
10093 14:00:40.108664
10094 14:00:40.111575 Sending DHCP request... done.
10095 14:00:40.112059
10096 14:00:40.116816 Waiting for reply... done.
10097 14:00:40.117367
10098 14:00:40.117736 My ip is 192.168.201.14
10099 14:00:40.118076
10100 14:00:40.120035 The DHCP server ip is 192.168.201.1
10101 14:00:40.120596
10102 14:00:40.125990 TFTP server IP predefined by user: 192.168.201.1
10103 14:00:40.126580
10104 14:00:40.132818 Bootfile predefined by user: 12682978/tftp-deploy-ut4sv5oc/kernel/image.itb
10105 14:00:40.133373
10106 14:00:40.133742 Sending tftp read request... done.
10107 14:00:40.134112
10108 14:00:40.143125 Waiting for the transfer...
10109 14:00:40.143736
10110 14:00:40.795289 00000000 ################################################################
10111 14:00:40.795437
10112 14:00:41.426786 00080000 ################################################################
10113 14:00:41.427409
10114 14:00:42.097772 00100000 ################################################################
10115 14:00:42.098269
10116 14:00:42.724456 00180000 ################################################################
10117 14:00:42.724596
10118 14:00:43.409045 00200000 ################################################################
10119 14:00:43.409561
10120 14:00:44.086686 00280000 ################################################################
10121 14:00:44.087211
10122 14:00:44.758129 00300000 ################################################################
10123 14:00:44.758660
10124 14:00:45.415425 00380000 ################################################################
10125 14:00:45.415564
10126 14:00:46.092322 00400000 ################################################################
10127 14:00:46.092862
10128 14:00:46.757784 00480000 ################################################################
10129 14:00:46.757935
10130 14:00:47.317109 00500000 ################################################################
10131 14:00:47.317259
10132 14:00:47.871631 00580000 ################################################################
10133 14:00:47.871780
10134 14:00:48.439950 00600000 ################################################################
10135 14:00:48.440100
10136 14:00:49.000590 00680000 ################################################################
10137 14:00:49.000747
10138 14:00:49.547670 00700000 ################################################################
10139 14:00:49.547826
10140 14:00:50.089881 00780000 ################################################################
10141 14:00:50.090028
10142 14:00:50.648737 00800000 ################################################################
10143 14:00:50.648892
10144 14:00:51.196825 00880000 ################################################################
10145 14:00:51.196978
10146 14:00:51.741611 00900000 ################################################################
10147 14:00:51.741758
10148 14:00:52.302255 00980000 ################################################################
10149 14:00:52.302607
10150 14:00:52.864866 00a00000 ################################################################
10151 14:00:52.865018
10152 14:00:53.411727 00a80000 ################################################################
10153 14:00:53.412289
10154 14:00:53.962677 00b00000 ################################################################
10155 14:00:53.962924
10156 14:00:54.522669 00b80000 ################################################################
10157 14:00:54.522816
10158 14:00:55.069824 00c00000 ################################################################
10159 14:00:55.069977
10160 14:00:55.625948 00c80000 ################################################################
10161 14:00:55.626121
10162 14:00:56.170388 00d00000 ################################################################
10163 14:00:56.170600
10164 14:00:56.717886 00d80000 ################################################################
10165 14:00:56.718034
10166 14:00:57.298875 00e00000 ################################################################
10167 14:00:57.299395
10168 14:00:57.892424 00e80000 ################################################################
10169 14:00:57.892577
10170 14:00:58.421840 00f00000 ################################################################
10171 14:00:58.421994
10172 14:00:58.949444 00f80000 ################################################################
10173 14:00:58.949595
10174 14:00:59.468059 01000000 ################################################################
10175 14:00:59.468210
10176 14:00:59.987805 01080000 ################################################################
10177 14:00:59.987959
10178 14:01:00.514624 01100000 ################################################################
10179 14:01:00.514790
10180 14:01:01.060063 01180000 ################################################################
10181 14:01:01.060212
10182 14:01:01.629132 01200000 ################################################################
10183 14:01:01.629280
10184 14:01:02.208340 01280000 ################################################################
10185 14:01:02.208484
10186 14:01:02.774180 01300000 ################################################################
10187 14:01:02.774315
10188 14:01:03.421840 01380000 ################################################################
10189 14:01:03.422388
10190 14:01:04.077016 01400000 ################################################################
10191 14:01:04.077240
10192 14:01:04.762740 01480000 ################################################################
10193 14:01:04.763259
10194 14:01:05.467209 01500000 ################################################################
10195 14:01:05.467719
10196 14:01:06.172069 01580000 ################################################################
10197 14:01:06.172225
10198 14:01:06.866207 01600000 ################################################################
10199 14:01:06.866792
10200 14:01:07.571763 01680000 ################################################################
10201 14:01:07.572326
10202 14:01:08.285939 01700000 ################################################################
10203 14:01:08.286544
10204 14:01:08.999383 01780000 ################################################################
10205 14:01:08.999932
10206 14:01:09.716275 01800000 ################################################################
10207 14:01:09.716985
10208 14:01:10.418171 01880000 ################################################################
10209 14:01:10.418716
10210 14:01:11.108509 01900000 ################################################################
10211 14:01:11.109057
10212 14:01:11.805105 01980000 ################################################################
10213 14:01:11.805693
10214 14:01:12.427637 01a00000 ################################################################
10215 14:01:12.427782
10216 14:01:12.988708 01a80000 ################################################################
10217 14:01:12.988845
10218 14:01:13.626266 01b00000 ################################################################
10219 14:01:13.626431
10220 14:01:14.250353 01b80000 ################################################################
10221 14:01:14.250535
10222 14:01:14.890650 01c00000 ################################################################
10223 14:01:14.891137
10224 14:01:15.502940 01c80000 ################################################################
10225 14:01:15.503076
10226 14:01:16.073719 01d00000 ################################################################
10227 14:01:16.073865
10228 14:01:16.658895 01d80000 ################################################################
10229 14:01:16.659033
10230 14:01:17.255143 01e00000 ################################################################
10231 14:01:17.255282
10232 14:01:17.821674 01e80000 ################################################################
10233 14:01:17.821826
10234 14:01:18.458723 01f00000 ################################################################
10235 14:01:18.459236
10236 14:01:19.178723 01f80000 ################################################################
10237 14:01:19.179239
10238 14:01:19.883185 02000000 ################################################################
10239 14:01:19.883790
10240 14:01:20.560099 02080000 ################################################################
10241 14:01:20.560244
10242 14:01:21.162031 02100000 ################################################################
10243 14:01:21.162179
10244 14:01:21.751398 02180000 ################################################################
10245 14:01:21.751544
10246 14:01:22.368428 02200000 ################################################################
10247 14:01:22.368969
10248 14:01:23.053152 02280000 ################################################################
10249 14:01:23.053726
10250 14:01:23.738949 02300000 ################################################################
10251 14:01:23.739546
10252 14:01:24.447913 02380000 ################################################################
10253 14:01:24.448446
10254 14:01:25.180700 02400000 ################################################################
10255 14:01:25.181206
10256 14:01:25.881918 02480000 ################################################################
10257 14:01:25.882448
10258 14:01:26.564270 02500000 ################################################################
10259 14:01:26.564794
10260 14:01:27.276570 02580000 ################################################################
10261 14:01:27.277093
10262 14:01:27.991348 02600000 ################################################################
10263 14:01:27.991872
10264 14:01:28.692916 02680000 ################################################################
10265 14:01:28.693434
10266 14:01:29.414172 02700000 ################################################################
10267 14:01:29.414766
10268 14:01:30.139360 02780000 ################################################################
10269 14:01:30.139879
10270 14:01:30.846865 02800000 ################################################################
10271 14:01:30.847458
10272 14:01:31.523223 02880000 ################################################################
10273 14:01:31.523759
10274 14:01:32.214384 02900000 ################################################################
10275 14:01:32.214935
10276 14:01:32.917113 02980000 ################################################################
10277 14:01:32.917617
10278 14:01:33.604585 02a00000 ################################################################
10279 14:01:33.605093
10280 14:01:34.274522 02a80000 ################################################################
10281 14:01:34.275029
10282 14:01:34.999670 02b00000 ################################################################
10283 14:01:35.000177
10284 14:01:35.709627 02b80000 ################################################################
10285 14:01:35.710242
10286 14:01:36.419455 02c00000 ################################################################
10287 14:01:36.419975
10288 14:01:37.157018 02c80000 ################################################################
10289 14:01:37.157536
10290 14:01:37.875621 02d00000 ################################################################
10291 14:01:37.876274
10292 14:01:38.576541 02d80000 ################################################################
10293 14:01:38.576691
10294 14:01:39.262868 02e00000 ################################################################
10295 14:01:39.263372
10296 14:01:39.974742 02e80000 ################################################################
10297 14:01:39.975258
10298 14:01:40.689043 02f00000 ################################################################
10299 14:01:40.689554
10300 14:01:41.400736 02f80000 ################################################################
10301 14:01:41.401246
10302 14:01:42.096902 03000000 ################################################################
10303 14:01:42.097410
10304 14:01:42.816540 03080000 ################################################################
10305 14:01:42.817248
10306 14:01:43.539221 03100000 ################################################################
10307 14:01:43.539731
10308 14:01:44.256308 03180000 ################################################################
10309 14:01:44.256879
10310 14:01:44.968401 03200000 ################################################################
10311 14:01:44.968912
10312 14:01:45.680393 03280000 ################################################################
10313 14:01:45.680927
10314 14:01:46.390904 03300000 ################################################################
10315 14:01:46.391418
10316 14:01:47.100193 03380000 ################################################################
10317 14:01:47.100730
10318 14:01:47.823690 03400000 ################################################################
10319 14:01:47.824250
10320 14:01:48.543102 03480000 ################################################################
10321 14:01:48.543637
10322 14:01:49.277907 03500000 ################################################################
10323 14:01:49.278467
10324 14:01:49.992958 03580000 ################################################################
10325 14:01:49.993490
10326 14:01:50.692735 03600000 ################################################################
10327 14:01:50.693281
10328 14:01:51.416052 03680000 ################################################################
10329 14:01:51.416570
10330 14:01:52.128440 03700000 ################################################################
10331 14:01:52.129045
10332 14:01:52.839872 03780000 ################################################################
10333 14:01:52.840383
10334 14:01:53.547987 03800000 ################################################################
10335 14:01:53.548499
10336 14:01:54.248642 03880000 ################################################################
10337 14:01:54.249159
10338 14:01:54.911682 03900000 ################################################################
10339 14:01:54.911822
10340 14:01:55.595960 03980000 ################################################################
10341 14:01:55.596460
10342 14:01:56.235856 03a00000 ################################################################
10343 14:01:56.236001
10344 14:01:56.852997 03a80000 ################################################################
10345 14:01:56.853513
10346 14:01:57.498750 03b00000 ################################################################
10347 14:01:57.498900
10348 14:01:58.078602 03b80000 ################################################################
10349 14:01:58.078791
10350 14:01:58.650017 03c00000 ################################################################
10351 14:01:58.650205
10352 14:01:59.224450 03c80000 ################################################################
10353 14:01:59.224603
10354 14:01:59.790132 03d00000 ################################################################
10355 14:01:59.790286
10356 14:02:00.381238 03d80000 ################################################################
10357 14:02:00.381388
10358 14:02:00.952980 03e00000 ################################################################
10359 14:02:00.953128
10360 14:02:01.514377 03e80000 ################################################################
10361 14:02:01.514577
10362 14:02:02.083412 03f00000 ################################################################
10363 14:02:02.083567
10364 14:02:02.655883 03f80000 ################################################################
10365 14:02:02.656057
10366 14:02:03.229443 04000000 ################################################################
10367 14:02:03.229661
10368 14:02:03.805773 04080000 ################################################################
10369 14:02:03.805923
10370 14:02:04.205356 04100000 ############################################## done.
10371 14:02:04.205504
10372 14:02:04.208780 The bootfile was 68530638 bytes long.
10373 14:02:04.208870
10374 14:02:04.212604 Sending tftp read request... done.
10375 14:02:04.212686
10376 14:02:04.212751 Waiting for the transfer...
10377 14:02:04.212812
10378 14:02:04.215345 00000000 # done.
10379 14:02:04.215429
10380 14:02:04.221845 Command line loaded dynamically from TFTP file: 12682978/tftp-deploy-ut4sv5oc/kernel/cmdline
10381 14:02:04.221928
10382 14:02:04.235809 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10383 14:02:04.235896
10384 14:02:04.238260 Loading FIT.
10385 14:02:04.238342
10386 14:02:04.241890 Image ramdisk-1 has 56434467 bytes.
10387 14:02:04.241972
10388 14:02:04.242035 Image fdt-1 has 47278 bytes.
10389 14:02:04.244978
10390 14:02:04.245059 Image kernel-1 has 12046857 bytes.
10391 14:02:04.245126
10392 14:02:04.255550 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10393 14:02:04.255635
10394 14:02:04.272014 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10395 14:02:04.272101
10396 14:02:04.278819 Choosing best match conf-1 for compat google,spherion-rev2.
10397 14:02:04.282534
10398 14:02:04.287176 Connected to device vid:did:rid of 1ae0:0028:00
10399 14:02:04.294231
10400 14:02:04.297393 tpm_get_response: command 0x17b, return code 0x0
10401 14:02:04.297475
10402 14:02:04.304124 ec_init: CrosEC protocol v3 supported (256, 248)
10403 14:02:04.304206
10404 14:02:04.307330 tpm_cleanup: add release locality here.
10405 14:02:04.307412
10406 14:02:04.311004 Shutting down all USB controllers.
10407 14:02:04.311086
10408 14:02:04.314213 Removing current net device
10409 14:02:04.314294
10410 14:02:04.317603 Exiting depthcharge with code 4 at timestamp: 119843405
10411 14:02:04.317685
10412 14:02:04.321706 LZMA decompressing kernel-1 to 0x821a6718
10413 14:02:04.324372
10414 14:02:04.327938 LZMA decompressing kernel-1 to 0x40000000
10415 14:02:05.827344
10416 14:02:05.827497 jumping to kernel
10417 14:02:05.828017 end: 2.2.4 bootloader-commands (duration 00:01:32) [common]
10418 14:02:05.828115 start: 2.2.5 auto-login-action (timeout 00:02:53) [common]
10419 14:02:05.828211 Setting prompt string to ['Linux version [0-9]']
10420 14:02:05.828292 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10421 14:02:05.828359 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10422 14:02:05.910037
10423 14:02:05.913480 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10424 14:02:05.917496 start: 2.2.5.1 login-action (timeout 00:02:53) [common]
10425 14:02:05.917602 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10426 14:02:05.917700 Setting prompt string to []
10427 14:02:05.917808 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10428 14:02:05.917909 Using line separator: #'\n'#
10429 14:02:05.917994 No login prompt set.
10430 14:02:05.918056 Parsing kernel messages
10431 14:02:05.918111 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10432 14:02:05.918211 [login-action] Waiting for messages, (timeout 00:02:53)
10433 14:02:05.936828 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10434 14:02:05.939912 [ 0.000000] random: crng init done
10435 14:02:05.947079 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10436 14:02:05.950193 [ 0.000000] efi: UEFI not found.
10437 14:02:05.956161 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10438 14:02:05.963021 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10439 14:02:05.972977 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10440 14:02:05.983124 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10441 14:02:05.989840 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10442 14:02:05.993263 [ 0.000000] printk: bootconsole [mtk8250] enabled
10443 14:02:06.001821 [ 0.000000] NUMA: No NUMA configuration found
10444 14:02:06.008925 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10445 14:02:06.015804 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10446 14:02:06.015887 [ 0.000000] Zone ranges:
10447 14:02:06.022430 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10448 14:02:06.025858 [ 0.000000] DMA32 empty
10449 14:02:06.031919 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10450 14:02:06.035152 [ 0.000000] Movable zone start for each node
10451 14:02:06.038732 [ 0.000000] Early memory node ranges
10452 14:02:06.045189 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10453 14:02:06.051744 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10454 14:02:06.058563 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10455 14:02:06.065058 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10456 14:02:06.072279 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10457 14:02:06.078341 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10458 14:02:06.134546 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10459 14:02:06.140929 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10460 14:02:06.147083 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10461 14:02:06.150385 [ 0.000000] psci: probing for conduit method from DT.
10462 14:02:06.157284 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10463 14:02:06.160473 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10464 14:02:06.167280 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10465 14:02:06.170333 [ 0.000000] psci: SMC Calling Convention v1.2
10466 14:02:06.177309 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10467 14:02:06.180174 [ 0.000000] Detected VIPT I-cache on CPU0
10468 14:02:06.186781 [ 0.000000] CPU features: detected: GIC system register CPU interface
10469 14:02:06.193878 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10470 14:02:06.200394 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10471 14:02:06.207167 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10472 14:02:06.213710 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10473 14:02:06.221298 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10474 14:02:06.227318 [ 0.000000] alternatives: applying boot alternatives
10475 14:02:06.230713 [ 0.000000] Fallback order for Node 0: 0
10476 14:02:06.237658 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10477 14:02:06.240488 [ 0.000000] Policy zone: Normal
10478 14:02:06.256861 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10479 14:02:06.266745 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10480 14:02:06.278524 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10481 14:02:06.288355 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10482 14:02:06.294969 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10483 14:02:06.298186 <6>[ 0.000000] software IO TLB: area num 8.
10484 14:02:06.354944 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10485 14:02:06.505075 <6>[ 0.000000] Memory: 7912140K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 440628K reserved, 32768K cma-reserved)
10486 14:02:06.510794 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10487 14:02:06.517354 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10488 14:02:06.520758 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10489 14:02:06.528230 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10490 14:02:06.533939 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10491 14:02:06.537753 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10492 14:02:06.547013 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10493 14:02:06.554166 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10494 14:02:06.560348 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10495 14:02:06.567031 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10496 14:02:06.570772 <6>[ 0.000000] GICv3: 608 SPIs implemented
10497 14:02:06.574745 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10498 14:02:06.580222 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10499 14:02:06.583391 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10500 14:02:06.590631 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10501 14:02:06.603782 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10502 14:02:06.613783 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10503 14:02:06.620394 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10504 14:02:06.630318 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10505 14:02:06.644035 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10506 14:02:06.650809 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10507 14:02:06.657204 <6>[ 0.009232] Console: colour dummy device 80x25
10508 14:02:06.667553 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10509 14:02:06.674080 <6>[ 0.024467] pid_max: default: 32768 minimum: 301
10510 14:02:06.676740 <6>[ 0.029339] LSM: Security Framework initializing
10511 14:02:06.683848 <6>[ 0.034277] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10512 14:02:06.694011 <6>[ 0.042091] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10513 14:02:06.700275 <6>[ 0.051504] cblist_init_generic: Setting adjustable number of callback queues.
10514 14:02:06.707027 <6>[ 0.058993] cblist_init_generic: Setting shift to 3 and lim to 1.
10515 14:02:06.716888 <6>[ 0.065370] cblist_init_generic: Setting adjustable number of callback queues.
10516 14:02:06.723756 <6>[ 0.072843] cblist_init_generic: Setting shift to 3 and lim to 1.
10517 14:02:06.726782 <6>[ 0.079246] rcu: Hierarchical SRCU implementation.
10518 14:02:06.733422 <6>[ 0.084262] rcu: Max phase no-delay instances is 1000.
10519 14:02:06.741014 <6>[ 0.091285] EFI services will not be available.
10520 14:02:06.743407 <6>[ 0.096238] smp: Bringing up secondary CPUs ...
10521 14:02:06.751364 <6>[ 0.101315] Detected VIPT I-cache on CPU1
10522 14:02:06.758385 <6>[ 0.101383] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10523 14:02:06.764803 <6>[ 0.101415] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10524 14:02:06.767798 <6>[ 0.101756] Detected VIPT I-cache on CPU2
10525 14:02:06.774977 <6>[ 0.101808] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10526 14:02:06.782227 <6>[ 0.101825] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10527 14:02:06.788401 <6>[ 0.102086] Detected VIPT I-cache on CPU3
10528 14:02:06.794966 <6>[ 0.102132] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10529 14:02:06.801292 <6>[ 0.102146] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10530 14:02:06.804737 <6>[ 0.102451] CPU features: detected: Spectre-v4
10531 14:02:06.811875 <6>[ 0.102458] CPU features: detected: Spectre-BHB
10532 14:02:06.815493 <6>[ 0.102463] Detected PIPT I-cache on CPU4
10533 14:02:06.821936 <6>[ 0.102520] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10534 14:02:06.828399 <6>[ 0.102536] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10535 14:02:06.831970 <6>[ 0.102830] Detected PIPT I-cache on CPU5
10536 14:02:06.842096 <6>[ 0.102893] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10537 14:02:06.848258 <6>[ 0.102911] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10538 14:02:06.852058 <6>[ 0.103191] Detected PIPT I-cache on CPU6
10539 14:02:06.858176 <6>[ 0.103256] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10540 14:02:06.864587 <6>[ 0.103273] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10541 14:02:06.868460 <6>[ 0.103569] Detected PIPT I-cache on CPU7
10542 14:02:06.878359 <6>[ 0.103633] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10543 14:02:06.885126 <6>[ 0.103649] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10544 14:02:06.888256 <6>[ 0.103697] smp: Brought up 1 node, 8 CPUs
10545 14:02:06.892451 <6>[ 0.244990] SMP: Total of 8 processors activated.
10546 14:02:06.898664 <6>[ 0.249911] CPU features: detected: 32-bit EL0 Support
10547 14:02:06.908570 <6>[ 0.255307] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10548 14:02:06.915374 <6>[ 0.264107] CPU features: detected: Common not Private translations
10549 14:02:06.918096 <6>[ 0.270583] CPU features: detected: CRC32 instructions
10550 14:02:06.924856 <6>[ 0.275935] CPU features: detected: RCpc load-acquire (LDAPR)
10551 14:02:06.931069 <6>[ 0.281931] CPU features: detected: LSE atomic instructions
10552 14:02:06.934851 <6>[ 0.287712] CPU features: detected: Privileged Access Never
10553 14:02:06.941894 <6>[ 0.293492] CPU features: detected: RAS Extension Support
10554 14:02:06.947687 <6>[ 0.299101] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10555 14:02:06.955417 <6>[ 0.306321] CPU: All CPU(s) started at EL2
10556 14:02:06.957658 <6>[ 0.310638] alternatives: applying system-wide alternatives
10557 14:02:06.969515 <6>[ 0.321390] devtmpfs: initialized
10558 14:02:06.985034 <6>[ 0.330343] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10559 14:02:06.991078 <6>[ 0.340300] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10560 14:02:06.997840 <6>[ 0.348557] pinctrl core: initialized pinctrl subsystem
10561 14:02:07.001432 <6>[ 0.355205] DMI not present or invalid.
10562 14:02:07.007888 <6>[ 0.359615] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10563 14:02:07.018238 <6>[ 0.366492] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10564 14:02:07.024302 <6>[ 0.374059] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10565 14:02:07.034567 <6>[ 0.382287] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10566 14:02:07.037982 <6>[ 0.390529] audit: initializing netlink subsys (disabled)
10567 14:02:07.047864 <5>[ 0.396221] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10568 14:02:07.055001 <6>[ 0.396913] thermal_sys: Registered thermal governor 'step_wise'
10569 14:02:07.061336 <6>[ 0.404187] thermal_sys: Registered thermal governor 'power_allocator'
10570 14:02:07.064742 <6>[ 0.410440] cpuidle: using governor menu
10571 14:02:07.068030 <6>[ 0.421401] NET: Registered PF_QIPCRTR protocol family
10572 14:02:07.077954 <6>[ 0.426882] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10573 14:02:07.081736 <6>[ 0.433983] ASID allocator initialised with 32768 entries
10574 14:02:07.088534 <6>[ 0.440550] Serial: AMBA PL011 UART driver
10575 14:02:07.096919 <4>[ 0.449341] Trying to register duplicate clock ID: 134
10576 14:02:07.153326 <6>[ 0.508725] KASLR enabled
10577 14:02:07.168698 <6>[ 0.516514] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10578 14:02:07.174389 <6>[ 0.523526] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10579 14:02:07.180797 <6>[ 0.530013] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10580 14:02:07.187784 <6>[ 0.537016] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10581 14:02:07.194692 <6>[ 0.543503] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10582 14:02:07.201921 <6>[ 0.550507] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10583 14:02:07.207734 <6>[ 0.556993] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10584 14:02:07.214330 <6>[ 0.563996] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10585 14:02:07.218269 <6>[ 0.571515] ACPI: Interpreter disabled.
10586 14:02:07.225743 <6>[ 0.577943] iommu: Default domain type: Translated
10587 14:02:07.232152 <6>[ 0.583058] iommu: DMA domain TLB invalidation policy: strict mode
10588 14:02:07.235811 <5>[ 0.589718] SCSI subsystem initialized
10589 14:02:07.242606 <6>[ 0.593888] usbcore: registered new interface driver usbfs
10590 14:02:07.248868 <6>[ 0.599622] usbcore: registered new interface driver hub
10591 14:02:07.252922 <6>[ 0.605175] usbcore: registered new device driver usb
10592 14:02:07.259407 <6>[ 0.611280] pps_core: LinuxPPS API ver. 1 registered
10593 14:02:07.269118 <6>[ 0.616473] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10594 14:02:07.272438 <6>[ 0.625822] PTP clock support registered
10595 14:02:07.276248 <6>[ 0.630065] EDAC MC: Ver: 3.0.0
10596 14:02:07.283078 <6>[ 0.635225] FPGA manager framework
10597 14:02:07.286213 <6>[ 0.638904] Advanced Linux Sound Architecture Driver Initialized.
10598 14:02:07.290300 <6>[ 0.645688] vgaarb: loaded
10599 14:02:07.296612 <6>[ 0.648836] clocksource: Switched to clocksource arch_sys_counter
10600 14:02:07.303818 <5>[ 0.655276] VFS: Disk quotas dquot_6.6.0
10601 14:02:07.309698 <6>[ 0.659463] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10602 14:02:07.313360 <6>[ 0.666654] pnp: PnP ACPI: disabled
10603 14:02:07.321451 <6>[ 0.673398] NET: Registered PF_INET protocol family
10604 14:02:07.331231 <6>[ 0.678997] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10605 14:02:07.342855 <6>[ 0.691320] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10606 14:02:07.353093 <6>[ 0.700135] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10607 14:02:07.358987 <6>[ 0.708108] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10608 14:02:07.365437 <6>[ 0.716809] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10609 14:02:07.377769 <6>[ 0.726533] TCP: Hash tables configured (established 65536 bind 65536)
10610 14:02:07.383993 <6>[ 0.733397] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10611 14:02:07.390815 <6>[ 0.740598] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10612 14:02:07.397416 <6>[ 0.748301] NET: Registered PF_UNIX/PF_LOCAL protocol family
10613 14:02:07.404435 <6>[ 0.754454] RPC: Registered named UNIX socket transport module.
10614 14:02:07.407281 <6>[ 0.760605] RPC: Registered udp transport module.
10615 14:02:07.413932 <6>[ 0.765540] RPC: Registered tcp transport module.
10616 14:02:07.420606 <6>[ 0.770471] RPC: Registered tcp NFSv4.1 backchannel transport module.
10617 14:02:07.424183 <6>[ 0.777138] PCI: CLS 0 bytes, default 64
10618 14:02:07.427186 <6>[ 0.781456] Unpacking initramfs...
10619 14:02:07.445367 <6>[ 0.793271] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10620 14:02:07.454026 <6>[ 0.801934] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10621 14:02:07.457624 <6>[ 0.810797] kvm [1]: IPA Size Limit: 40 bits
10622 14:02:07.464079 <6>[ 0.815326] kvm [1]: GICv3: no GICV resource entry
10623 14:02:07.467530 <6>[ 0.820346] kvm [1]: disabling GICv2 emulation
10624 14:02:07.474198 <6>[ 0.825034] kvm [1]: GIC system register CPU interface enabled
10625 14:02:07.481504 <6>[ 0.832892] kvm [1]: vgic interrupt IRQ18
10626 14:02:07.484339 <6>[ 0.837285] kvm [1]: VHE mode initialized successfully
10627 14:02:07.491455 <5>[ 0.843556] Initialise system trusted keyrings
10628 14:02:07.498038 <6>[ 0.848357] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10629 14:02:07.506243 <6>[ 0.858373] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10630 14:02:07.512738 <5>[ 0.864766] NFS: Registering the id_resolver key type
10631 14:02:07.516305 <5>[ 0.870067] Key type id_resolver registered
10632 14:02:07.523402 <5>[ 0.874483] Key type id_legacy registered
10633 14:02:07.530403 <6>[ 0.878762] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10634 14:02:07.536669 <6>[ 0.885683] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10635 14:02:07.543112 <6>[ 0.893381] 9p: Installing v9fs 9p2000 file system support
10636 14:02:07.579260 <5>[ 0.931657] Key type asymmetric registered
10637 14:02:07.582709 <5>[ 0.935991] Asymmetric key parser 'x509' registered
10638 14:02:07.593230 <6>[ 0.941146] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10639 14:02:07.596199 <6>[ 0.948760] io scheduler mq-deadline registered
10640 14:02:07.599266 <6>[ 0.953520] io scheduler kyber registered
10641 14:02:07.618016 <6>[ 0.970710] EINJ: ACPI disabled.
10642 14:02:07.650675 <4>[ 0.996466] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 14:02:07.660708 <4>[ 1.007225] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 14:02:07.675861 <6>[ 1.028126] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10645 14:02:07.683731 <6>[ 1.036145] printk: console [ttyS0] disabled
10646 14:02:07.711733 <6>[ 1.060789] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10647 14:02:07.718371 <6>[ 1.070265] printk: console [ttyS0] enabled
10648 14:02:07.721911 <6>[ 1.070265] printk: console [ttyS0] enabled
10649 14:02:07.728967 <6>[ 1.079160] printk: bootconsole [mtk8250] disabled
10650 14:02:07.731995 <6>[ 1.079160] printk: bootconsole [mtk8250] disabled
10651 14:02:07.738308 <6>[ 1.090366] SuperH (H)SCI(F) driver initialized
10652 14:02:07.742085 <6>[ 1.095647] msm_serial: driver initialized
10653 14:02:07.755863 <6>[ 1.104612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10654 14:02:07.766100 <6>[ 1.113161] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10655 14:02:07.772264 <6>[ 1.121704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10656 14:02:07.782229 <6>[ 1.130334] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10657 14:02:07.788764 <6>[ 1.139044] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10658 14:02:07.798786 <6>[ 1.147769] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10659 14:02:07.808646 <6>[ 1.156311] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10660 14:02:07.815194 <6>[ 1.165117] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10661 14:02:07.825561 <6>[ 1.173662] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10662 14:02:07.836914 <6>[ 1.189371] loop: module loaded
10663 14:02:07.843346 <6>[ 1.195385] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10664 14:02:07.866792 <4>[ 1.218791] mtk-pmic-keys: Failed to locate of_node [id: -1]
10665 14:02:07.873475 <6>[ 1.225860] megasas: 07.719.03.00-rc1
10666 14:02:07.883632 <6>[ 1.235626] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10667 14:02:07.896030 <6>[ 1.248223] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10668 14:02:07.912588 <6>[ 1.265010] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10669 14:02:07.969039 <6>[ 1.315027] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10670 14:02:09.827204 <6>[ 3.179977] Freeing initrd memory: 55108K
10671 14:02:09.838091 <6>[ 3.190532] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10672 14:02:09.849555 <6>[ 3.201712] tun: Universal TUN/TAP device driver, 1.6
10673 14:02:09.852314 <6>[ 3.207789] thunder_xcv, ver 1.0
10674 14:02:09.855764 <6>[ 3.211296] thunder_bgx, ver 1.0
10675 14:02:09.859342 <6>[ 3.214790] nicpf, ver 1.0
10676 14:02:09.870325 <6>[ 3.218820] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10677 14:02:09.873477 <6>[ 3.226296] hns3: Copyright (c) 2017 Huawei Corporation.
10678 14:02:09.876432 <6>[ 3.231885] hclge is initializing
10679 14:02:09.882707 <6>[ 3.235464] e1000: Intel(R) PRO/1000 Network Driver
10680 14:02:09.889451 <6>[ 3.240593] e1000: Copyright (c) 1999-2006 Intel Corporation.
10681 14:02:09.893060 <6>[ 3.246606] e1000e: Intel(R) PRO/1000 Network Driver
10682 14:02:09.899592 <6>[ 3.251822] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10683 14:02:09.906006 <6>[ 3.258011] igb: Intel(R) Gigabit Ethernet Network Driver
10684 14:02:09.913399 <6>[ 3.263661] igb: Copyright (c) 2007-2014 Intel Corporation.
10685 14:02:09.919878 <6>[ 3.269498] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10686 14:02:09.926356 <6>[ 3.276016] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10687 14:02:09.929510 <6>[ 3.282475] sky2: driver version 1.30
10688 14:02:09.935811 <6>[ 3.287474] VFIO - User Level meta-driver version: 0.3
10689 14:02:09.943571 <6>[ 3.295736] usbcore: registered new interface driver usb-storage
10690 14:02:09.949428 <6>[ 3.302186] usbcore: registered new device driver onboard-usb-hub
10691 14:02:09.958497 <6>[ 3.311371] mt6397-rtc mt6359-rtc: registered as rtc0
10692 14:02:09.969170 <6>[ 3.316840] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T14:02:11 UTC (1706796131)
10693 14:02:09.972119 <6>[ 3.326410] i2c_dev: i2c /dev entries driver
10694 14:02:09.989645 <6>[ 3.338257] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10695 14:02:10.009800 <6>[ 3.361245] cpu cpu0: EM: created perf domain
10696 14:02:10.012359 <6>[ 3.366174] cpu cpu4: EM: created perf domain
10697 14:02:10.019340 <6>[ 3.371820] sdhci: Secure Digital Host Controller Interface driver
10698 14:02:10.025798 <6>[ 3.378255] sdhci: Copyright(c) Pierre Ossman
10699 14:02:10.032729 <6>[ 3.383214] Synopsys Designware Multimedia Card Interface Driver
10700 14:02:10.039024 <6>[ 3.389846] sdhci-pltfm: SDHCI platform and OF driver helper
10701 14:02:10.042336 <6>[ 3.389958] mmc0: CQHCI version 5.10
10702 14:02:10.049244 <6>[ 3.399820] ledtrig-cpu: registered to indicate activity on CPUs
10703 14:02:10.055892 <6>[ 3.406785] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10704 14:02:10.062750 <6>[ 3.413839] usbcore: registered new interface driver usbhid
10705 14:02:10.065895 <6>[ 3.419661] usbhid: USB HID core driver
10706 14:02:10.073153 <6>[ 3.423853] spi_master spi0: will run message pump with realtime priority
10707 14:02:10.113868 <6>[ 3.460220] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10708 14:02:10.132972 <6>[ 3.475455] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10709 14:02:10.140315 <6>[ 3.490596] cros-ec-spi spi0.0: Chrome EC device registered
10710 14:02:10.143153 <6>[ 3.496624] mmc0: Command Queue Engine enabled
10711 14:02:10.150676 <6>[ 3.501380] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10712 14:02:10.156448 <6>[ 3.509275] mmcblk0: mmc0:0001 DA4128 116 GiB
10713 14:02:10.168838 <6>[ 3.521348] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10714 14:02:10.179259 <6>[ 3.524564] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10715 14:02:10.185559 <6>[ 3.528649] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10716 14:02:10.188781 <6>[ 3.537858] NET: Registered PF_PACKET protocol family
10717 14:02:10.195181 <6>[ 3.542548] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10718 14:02:10.198798 <6>[ 3.547172] 9pnet: Installing 9P2000 support
10719 14:02:10.205081 <6>[ 3.553002] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10720 14:02:10.211606 <5>[ 3.556872] Key type dns_resolver registered
10721 14:02:10.215384 <6>[ 3.568295] registered taskstats version 1
10722 14:02:10.218549 <5>[ 3.572674] Loading compiled-in X.509 certificates
10723 14:02:10.248847 <4>[ 3.594616] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10724 14:02:10.258373 <4>[ 3.605478] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10725 14:02:10.265969 <3>[ 3.616029] debugfs: File 'uA_load' in directory '/' already present!
10726 14:02:10.272750 <3>[ 3.622748] debugfs: File 'min_uV' in directory '/' already present!
10727 14:02:10.278401 <3>[ 3.629415] debugfs: File 'max_uV' in directory '/' already present!
10728 14:02:10.284868 <3>[ 3.636121] debugfs: File 'constraint_flags' in directory '/' already present!
10729 14:02:10.296171 <3>[ 3.645654] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10730 14:02:10.306602 <6>[ 3.659447] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10731 14:02:10.313608 <6>[ 3.666194] xhci-mtk 11200000.usb: xHCI Host Controller
10732 14:02:10.320196 <6>[ 3.671684] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10733 14:02:10.330303 <6>[ 3.679519] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10734 14:02:10.336622 <6>[ 3.688947] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10735 14:02:10.343610 <6>[ 3.695018] xhci-mtk 11200000.usb: xHCI Host Controller
10736 14:02:10.350423 <6>[ 3.700494] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10737 14:02:10.356732 <6>[ 3.708142] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10738 14:02:10.363409 <6>[ 3.715799] hub 1-0:1.0: USB hub found
10739 14:02:10.366745 <6>[ 3.719814] hub 1-0:1.0: 1 port detected
10740 14:02:10.373670 <6>[ 3.724085] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10741 14:02:10.380493 <6>[ 3.732637] hub 2-0:1.0: USB hub found
10742 14:02:10.383921 <6>[ 3.736642] hub 2-0:1.0: 1 port detected
10743 14:02:10.391326 <6>[ 3.744200] mtk-msdc 11f70000.mmc: Got CD GPIO
10744 14:02:10.402769 <6>[ 3.751914] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10745 14:02:10.408944 <6>[ 3.759950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10746 14:02:10.418839 <4>[ 3.767858] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10747 14:02:10.429259 <6>[ 3.777397] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10748 14:02:10.435694 <6>[ 3.785474] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10749 14:02:10.443818 <6>[ 3.793597] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10750 14:02:10.452807 <6>[ 3.801526] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10751 14:02:10.459208 <6>[ 3.809379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10752 14:02:10.469485 <6>[ 3.817203] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10753 14:02:10.479016 <6>[ 3.827618] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10754 14:02:10.485550 <6>[ 3.835988] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10755 14:02:10.496587 <6>[ 3.844367] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10756 14:02:10.502975 <6>[ 3.852710] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10757 14:02:10.512417 <6>[ 3.861062] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10758 14:02:10.518610 <6>[ 3.869401] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10759 14:02:10.528627 <6>[ 3.877752] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10760 14:02:10.535206 <6>[ 3.886102] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10761 14:02:10.545744 <6>[ 3.894451] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10762 14:02:10.551594 <6>[ 3.902790] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10763 14:02:10.561996 <6>[ 3.911138] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10764 14:02:10.572098 <6>[ 3.919478] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10765 14:02:10.578663 <6>[ 3.927816] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10766 14:02:10.589093 <6>[ 3.936156] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10767 14:02:10.595649 <6>[ 3.944496] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10768 14:02:10.601271 <6>[ 3.953263] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10769 14:02:10.608040 <6>[ 3.960329] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10770 14:02:10.614766 <6>[ 3.967094] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10771 14:02:10.621849 <6>[ 3.973853] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10772 14:02:10.631645 <6>[ 3.980783] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10773 14:02:10.638324 <6>[ 3.987643] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10774 14:02:10.648267 <6>[ 3.996771] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10775 14:02:10.658502 <6>[ 4.005889] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10776 14:02:10.668530 <6>[ 4.015182] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10777 14:02:10.678234 <6>[ 4.024693] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10778 14:02:10.684918 <6>[ 4.034247] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10779 14:02:10.695137 <6>[ 4.043367] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10780 14:02:10.704898 <6>[ 4.052835] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10781 14:02:10.714470 <6>[ 4.061956] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10782 14:02:10.724682 <6>[ 4.071250] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10783 14:02:10.734540 <6>[ 4.081410] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10784 14:02:10.744355 <6>[ 4.093261] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10785 14:02:10.812591 <6>[ 4.161115] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10786 14:02:10.967245 <6>[ 4.319275] hub 1-1:1.0: USB hub found
10787 14:02:10.971078 <6>[ 4.323784] hub 1-1:1.0: 4 ports detected
10788 14:02:10.980049 <6>[ 4.332369] hub 1-1:1.0: USB hub found
10789 14:02:10.983785 <6>[ 4.336702] hub 1-1:1.0: 4 ports detected
10790 14:02:11.092487 <6>[ 4.441476] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10791 14:02:11.118949 <6>[ 4.471011] hub 2-1:1.0: USB hub found
10792 14:02:11.122028 <6>[ 4.475508] hub 2-1:1.0: 3 ports detected
10793 14:02:11.131099 <6>[ 4.483425] hub 2-1:1.0: USB hub found
10794 14:02:11.134805 <6>[ 4.487878] hub 2-1:1.0: 3 ports detected
10795 14:02:11.308077 <6>[ 4.657153] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10796 14:02:11.440501 <6>[ 4.792626] hub 1-1.4:1.0: USB hub found
10797 14:02:11.443333 <6>[ 4.797209] hub 1-1.4:1.0: 2 ports detected
10798 14:02:11.453175 <6>[ 4.805354] hub 1-1.4:1.0: USB hub found
10799 14:02:11.456996 <6>[ 4.809934] hub 1-1.4:1.0: 2 ports detected
10800 14:02:11.523954 <6>[ 4.873235] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10801 14:02:11.752028 <6>[ 5.101125] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10802 14:02:11.944301 <6>[ 5.293136] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10803 14:02:23.041350 <6>[ 16.398104] ALSA device list:
10804 14:02:23.047275 <6>[ 16.401382] No soundcards found.
10805 14:02:23.055365 <6>[ 16.409281] Freeing unused kernel memory: 8448K
10806 14:02:23.058578 <6>[ 16.414254] Run /init as init process
10807 14:02:23.106864 <6>[ 16.460804] NET: Registered PF_INET6 protocol family
10808 14:02:23.113727 <6>[ 16.467567] Segment Routing with IPv6
10809 14:02:23.116911 <6>[ 16.471525] In-situ OAM (IOAM) with IPv6
10810 14:02:23.152219 <30>[ 16.489231] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10811 14:02:23.159557 <30>[ 16.513268] systemd[1]: Detected architecture arm64.
10812 14:02:23.159980
10813 14:02:23.166148 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10814 14:02:23.166611
10815 14:02:23.183330 <30>[ 16.537168] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10816 14:02:23.309785 <30>[ 16.660272] systemd[1]: Queued start job for default target Graphical Interface.
10817 14:02:23.349056 <30>[ 16.702053] systemd[1]: Created slice system-getty.slice.
10818 14:02:23.355224 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10819 14:02:23.371841 <30>[ 16.725594] systemd[1]: Created slice system-modprobe.slice.
10820 14:02:23.378527 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10821 14:02:23.396868 <30>[ 16.750042] systemd[1]: Created slice system-serial\x2dgetty.slice.
10822 14:02:23.406527 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10823 14:02:23.420717 <30>[ 16.774439] systemd[1]: Created slice User and Session Slice.
10824 14:02:23.427440 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10825 14:02:23.447709 <30>[ 16.797866] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10826 14:02:23.457319 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10827 14:02:23.475310 <30>[ 16.825322] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10828 14:02:23.481820 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10829 14:02:23.502256 <30>[ 16.849173] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10830 14:02:23.508664 <30>[ 16.861341] systemd[1]: Reached target Local Encrypted Volumes.
10831 14:02:23.514900 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10832 14:02:23.532011 <30>[ 16.885626] systemd[1]: Reached target Paths.
10833 14:02:23.535098 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10834 14:02:23.551181 <30>[ 16.905115] systemd[1]: Reached target Remote File Systems.
10835 14:02:23.558046 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10836 14:02:23.575578 <30>[ 16.929489] systemd[1]: Reached target Slices.
10837 14:02:23.582233 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10838 14:02:23.596390 <30>[ 16.949133] systemd[1]: Reached target Swap.
10839 14:02:23.598779 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10840 14:02:23.619035 <30>[ 16.969661] systemd[1]: Listening on initctl Compatibility Named Pipe.
10841 14:02:23.625812 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10842 14:02:23.632590 <30>[ 16.984811] systemd[1]: Listening on Journal Audit Socket.
10843 14:02:23.639349 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10844 14:02:23.651811 <30>[ 17.005624] systemd[1]: Listening on Journal Socket (/dev/log).
10845 14:02:23.658569 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10846 14:02:23.676811 <30>[ 17.030385] systemd[1]: Listening on Journal Socket.
10847 14:02:23.683039 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10848 14:02:23.695921 <30>[ 17.049715] systemd[1]: Listening on udev Control Socket.
10849 14:02:23.702237 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10850 14:02:23.720241 <30>[ 17.074182] systemd[1]: Listening on udev Kernel Socket.
10851 14:02:23.727005 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10852 14:02:23.783702 <30>[ 17.137326] systemd[1]: Mounting Huge Pages File System...
10853 14:02:23.790216 Mounting [0;1;39mHuge Pages File System[0m...
10854 14:02:23.805956 <30>[ 17.159859] systemd[1]: Mounting POSIX Message Queue File System...
10855 14:02:23.813109 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10856 14:02:23.829009 <30>[ 17.182932] systemd[1]: Mounting Kernel Debug File System...
10857 14:02:23.835226 Mounting [0;1;39mKernel Debug File System[0m...
10858 14:02:23.854669 <30>[ 17.205354] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10859 14:02:23.865873 <30>[ 17.216545] systemd[1]: Starting Create list of static device nodes for the current kernel...
10860 14:02:23.872774 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10861 14:02:23.891109 <30>[ 17.245221] systemd[1]: Starting Load Kernel Module configfs...
10862 14:02:23.898073 Starting [0;1;39mLoad Kernel Module configfs[0m...
10863 14:02:23.916071 <30>[ 17.269758] systemd[1]: Starting Load Kernel Module drm...
10864 14:02:23.922809 Starting [0;1;39mLoad Kernel Module drm[0m...
10865 14:02:23.938945 <30>[ 17.289559] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10866 14:02:23.988339 <30>[ 17.342076] systemd[1]: Starting Journal Service...
10867 14:02:23.991894 Starting [0;1;39mJournal Service[0m...
10868 14:02:24.012421 <30>[ 17.365970] systemd[1]: Starting Load Kernel Modules...
10869 14:02:24.018684 Starting [0;1;39mLoad Kernel Modules[0m...
10870 14:02:24.038367 <30>[ 17.389443] systemd[1]: Starting Remount Root and Kernel File Systems...
10871 14:02:24.045877 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10872 14:02:24.061645 <30>[ 17.415925] systemd[1]: Starting Coldplug All udev Devices...
10873 14:02:24.068947 Starting [0;1;39mColdplug All udev Devices[0m...
10874 14:02:24.086300 <30>[ 17.439865] systemd[1]: Started Journal Service.
10875 14:02:24.092364 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10876 14:02:24.109386 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10877 14:02:24.124292 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10878 14:02:24.139678 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10879 14:02:24.160321 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10880 14:02:24.177619 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10881 14:02:24.198016 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10882 14:02:24.218644 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10883 14:02:24.236952 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10884 14:02:24.251897 See 'systemctl status systemd-remount-fs.service' for details.
10885 14:02:24.296243 Mounting [0;1;39mKernel Configuration File System[0m...
10886 14:02:24.317772 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10887 14:02:24.334964 <46>[ 17.685922] systemd-journald[179]: Received client request to flush runtime journal.
10888 14:02:24.345063 Starting [0;1;39mLoad/Save Random Seed[0m...
10889 14:02:24.366770 Starting [0;1;39mApply Kernel Variables[0m...
10890 14:02:24.391567 Starting [0;1;39mCreate System Users[0m...
10891 14:02:24.410692 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10892 14:02:24.435832 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10893 14:02:24.452092 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10894 14:02:24.465355 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10895 14:02:24.480580 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10896 14:02:24.496390 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10897 14:02:24.535617 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10898 14:02:24.555686 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10899 14:02:24.567578 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10900 14:02:24.583201 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10901 14:02:24.631997 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10902 14:02:24.658564 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10903 14:02:24.676294 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10904 14:02:24.696926 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10905 14:02:24.748563 Starting [0;1;39mNetwork Time Synchronization[0m...
10906 14:02:24.770059 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10907 14:02:24.813943 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10908 14:02:24.840690 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10909 14:02:24.856979 <6>[ 18.207791] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10910 14:02:24.870658 <6>[ 18.221174] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10911 14:02:24.880519 <6>[ 18.230017] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10912 14:02:24.887309 <6>[ 18.238906] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10913 14:02:24.897187 <3>[ 18.246202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 14:02:24.903515 <3>[ 18.255819] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 14:02:24.914144 <3>[ 18.264251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 14:02:24.920780 Starting [0;1;39mLoad/<6>[ 18.274341] remoteproc remoteproc0: scp is available
10917 14:02:24.926869 Save Screen …o<6>[ 18.280853] remoteproc remoteproc0: powering up scp
10918 14:02:24.937036 f leds:white:kbd<6>[ 18.287267] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10919 14:02:24.943758 <6>[ 18.297114] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10920 14:02:24.944174 _backlight[0m...
10921 14:02:24.953727 <3>[ 18.304539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 14:02:24.960619 <3>[ 18.312755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 14:02:24.970595 <3>[ 18.320992] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10924 14:02:24.977052 <3>[ 18.329141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10925 14:02:24.986822 <3>[ 18.337229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10926 14:02:24.993784 <3>[ 18.337293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 14:02:25.000745 <4>[ 18.348901] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10928 14:02:25.010223 <3>[ 18.356561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 14:02:25.017250 <6>[ 18.362210] usbcore: registered new device driver r8152-cfgselector
10930 14:02:25.023685 <3>[ 18.368807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10931 14:02:25.030478 <4>[ 18.369900] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10932 14:02:25.040155 [[0;32m OK [<3>[ 18.390705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10933 14:02:25.047054 <6>[ 18.397199] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10934 14:02:25.054272 0m] Started [0;<6>[ 18.397231] mc: Linux media interface: v0.10
10935 14:02:25.063320 1;39mNetwork Tim<3>[ 18.411046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10936 14:02:25.069810 <6>[ 18.413163] pci_bus 0000:00: root bus resource [bus 00-ff]
10937 14:02:25.080299 e Synchronizatio<3>[ 18.423740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10938 14:02:25.080724 n[0m.
10939 14:02:25.086482 <6>[ 18.423787] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10940 14:02:25.092868 <6>[ 18.423797] remoteproc remoteproc0: remote processor scp is now up
10941 14:02:25.099665 <6>[ 18.423830] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10942 14:02:25.109309 <6>[ 18.428252] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10943 14:02:25.119550 <6>[ 18.428262] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10944 14:02:25.126020 <6>[ 18.428358] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10945 14:02:25.129443 <6>[ 18.437578] videodev: Linux video capture interface: v2.00
10946 14:02:25.139023 <3>[ 18.437735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10947 14:02:25.145633 <6>[ 18.446969] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10948 14:02:25.156935 <3>[ 18.453378] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10949 14:02:25.159589 <6>[ 18.460513] pci 0000:00:00.0: supports D1 D2
10950 14:02:25.167337 <6>[ 18.464745] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10951 14:02:25.173674 <3>[ 18.467667] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10952 14:02:25.180822 <6>[ 18.477560] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10953 14:02:25.190072 <6>[ 18.477844] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10954 14:02:25.200365 <3>[ 18.483910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10955 14:02:25.206669 <6>[ 18.490965] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10956 14:02:25.216575 <4>[ 18.491319] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10957 14:02:25.219687 <4>[ 18.491319] Fallback method does not support PEC.
10958 14:02:25.230048 <6>[ 18.501744] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10959 14:02:25.236755 <6>[ 18.508427] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10960 14:02:25.246086 <3>[ 18.522057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 14:02:25.253253 <6>[ 18.525711] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10962 14:02:25.263396 <6>[ 18.526976] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10963 14:02:25.269651 <6>[ 18.553418] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10964 14:02:25.279858 <6>[ 18.558010] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10965 14:02:25.286443 <6>[ 18.558026] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10966 14:02:25.292702 <6>[ 18.568306] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10967 14:02:25.299700 <6>[ 18.580038] pci 0000:01:00.0: supports D1 D2
10968 14:02:25.306606 <6>[ 18.593596] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10969 14:02:25.313548 <6>[ 18.596292] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10970 14:02:25.319357 <6>[ 18.597234] Bluetooth: Core ver 2.22
10971 14:02:25.326049 <6>[ 18.607028] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10972 14:02:25.336730 <4>[ 18.609090] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10973 14:02:25.343049 <4>[ 18.609101] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10974 14:02:25.349515 <6>[ 18.610581] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10975 14:02:25.355686 <6>[ 18.610628] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10976 14:02:25.366033 <6>[ 18.610631] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10977 14:02:25.371947 <6>[ 18.610643] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10978 14:02:25.382013 <6>[ 18.610656] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10979 14:02:25.390002 <6>[ 18.610668] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10980 14:02:25.395896 <6>[ 18.610680] pci 0000:00:00.0: PCI bridge to [bus 01]
10981 14:02:25.403091 <6>[ 18.610686] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10982 14:02:25.410447 <6>[ 18.610896] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10983 14:02:25.413928 <6>[ 18.612137] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10984 14:02:25.420956 <6>[ 18.612318] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10985 14:02:25.427115 <6>[ 18.613620] NET: Registered PF_BLUETOOTH protocol family
10986 14:02:25.437995 <6>[ 18.624060] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10987 14:02:25.444985 <6>[ 18.630399] Bluetooth: HCI device and connection manager initialized
10988 14:02:25.454549 <5>[ 18.632402] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10989 14:02:25.457949 <6>[ 18.638406] usbcore: registered new interface driver uvcvideo
10990 14:02:25.465203 <5>[ 18.642604] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10991 14:02:25.474540 <5>[ 18.642846] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10992 14:02:25.485228 <4>[ 18.642904] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10993 14:02:25.488200 <6>[ 18.642910] cfg80211: failed to load regulatory.db
10994 14:02:25.494361 <6>[ 18.645293] Bluetooth: HCI socket layer initialized
10995 14:02:25.498229 <6>[ 18.645305] Bluetooth: L2CAP socket layer initialized
10996 14:02:25.505355 <6>[ 18.647717] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10997 14:02:25.508936 <6>[ 18.668935] r8152 2-1.3:1.0 eth0: v1.12.13
10998 14:02:25.515637 <6>[ 18.673206] Bluetooth: SCO socket layer initialized
10999 14:02:25.520207 <6>[ 18.717584] usbcore: registered new interface driver btusb
11000 14:02:25.526564 <6>[ 18.721781] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11001 14:02:25.533518 <6>[ 18.721879] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11002 14:02:25.539887 <6>[ 18.724557] usbcore: registered new interface driver r8152
11003 14:02:25.550179 <4>[ 18.724762] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11004 14:02:25.557071 <3>[ 18.724772] Bluetooth: hci0: Failed to load firmware file (-2)
11005 14:02:25.563403 <3>[ 18.724775] Bluetooth: hci0: Failed to set up firmware (-2)
11006 14:02:25.573243 <4>[ 18.724779] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11007 14:02:25.580121 <6>[ 18.741025] mt7921e 0000:01:00.0: ASIC revision: 79610010
11008 14:02:25.583209 <6>[ 18.761944] usbcore: registered new interface driver cdc_ether
11009 14:02:25.593029 <3>[ 18.765356] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 14:02:25.602973 <3>[ 18.767469] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11011 14:02:25.609763 <3>[ 18.770571] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 14:02:25.620560 <3>[ 18.771336] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11013 14:02:25.626387 <6>[ 18.780179] usbcore: registered new interface driver r8153_ecm
11014 14:02:25.633170 <3>[ 18.793992] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 14:02:25.639615 <6>[ 18.839226] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11016 14:02:25.649829 <6>[ 18.859936] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11017 14:02:25.650299 <6>[ 18.859936]
11018 14:02:25.659586 <3>[ 18.863494] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 14:02:25.669316 <3>[ 18.885124] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 14:02:25.675754 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11021 14:02:25.696777 <3>[ 19.047385] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 14:02:25.703531 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11023 14:02:25.728836 <3>[ 19.079541] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 14:02:25.795254 <6>[ 19.145816] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11025 14:02:25.843018 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11026 14:02:25.855563 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11027 14:02:25.874354 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11028 14:02:25.887765 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11029 14:02:25.903205 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11030 14:02:25.920021 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11031 14:02:25.934864 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11032 14:02:25.958581 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11033 14:02:25.971262 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11034 14:02:25.987210 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11035 14:02:26.010637 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11036 14:02:26.047415 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11037 14:02:26.079125 Starting [0;1;39mUser Login Management[0m...
11038 14:02:26.100530 Starting [0;1;39mPermit User Sessions[0m...
11039 14:02:26.119132 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11040 14:02:26.136659 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11041 14:02:26.156169 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11042 14:02:26.171661 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11043 14:02:26.190391 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11044 14:02:26.209458 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11045 14:02:26.227897 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11046 14:02:26.244632 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11047 14:02:26.259902 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11048 14:02:26.311822 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11049 14:02:26.344411 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11050 14:02:26.383097
11051 14:02:26.383538
11052 14:02:26.386837 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11053 14:02:26.387256
11054 14:02:26.389589 debian-bullseye-arm64 login: root (automatic login)
11055 14:02:26.390009
11056 14:02:26.390335
11057 14:02:26.407720 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
11058 14:02:26.408140
11059 14:02:26.414767 The programs included with the Debian GNU/Linux system are free software;
11060 14:02:26.420702 the exact distribution terms for each program are described in the
11061 14:02:26.424206 individual files in /usr/share/doc/*/copyright.
11062 14:02:26.424624
11063 14:02:26.430742 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11064 14:02:26.434330 permitted by applicable law.
11065 14:02:26.435681 Matched prompt #10: / #
11067 14:02:26.436710 Setting prompt string to ['/ #']
11068 14:02:26.437179 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11070 14:02:26.438287 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11071 14:02:26.438758 start: 2.2.6 expect-shell-connection (timeout 00:02:33) [common]
11072 14:02:26.439108 Setting prompt string to ['/ #']
11073 14:02:26.439412 Forcing a shell prompt, looking for ['/ #']
11075 14:02:26.490150 / #
11076 14:02:26.490695 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11077 14:02:26.491080 Waiting using forced prompt support (timeout 00:02:30)
11078 14:02:26.496154
11079 14:02:26.496895 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11080 14:02:26.497347 start: 2.2.7 export-device-env (timeout 00:02:33) [common]
11081 14:02:26.497785 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11082 14:02:26.498210 end: 2.2 depthcharge-retry (duration 00:02:27) [common]
11083 14:02:26.498696 end: 2 depthcharge-action (duration 00:02:27) [common]
11084 14:02:26.499134 start: 3 lava-test-retry (timeout 00:07:09) [common]
11085 14:02:26.499552 start: 3.1 lava-test-shell (timeout 00:07:09) [common]
11086 14:02:26.499922 Using namespace: common
11088 14:02:26.600890 / # #
11089 14:02:26.601393 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11090 14:02:26.606986 #
11091 14:02:26.607695 Using /lava-12682978
11093 14:02:26.708673 / # export SHELL=/bin/sh
11094 14:02:26.709324 <6>[ 19.997077] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11095 14:02:26.714813 export SHELL=/bin/sh
11097 14:02:26.816159 / # . /lava-12682978/environment
11098 14:02:26.823050 . /lava-12682978/environment
11100 14:02:26.924489 / # /lava-12682978/bin/lava-test-runner /lava-12682978/0
11101 14:02:26.925017 Test shell timeout: 10s (minimum of the action and connection timeout)
11102 14:02:26.930523 /lava-12682978/bin/lava-test-runner /lava-12682978/0
11103 14:02:26.956716 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.310498] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12682978_1.5.2.3.1>
11104 14:02:26.957479 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12682978_1.5.2.3.1
11105 14:02:26.957848 Starting test lava.0_igt-gpu-panfrost (12682978_1.5.2.3.1)
11106 14:02:26.958265 Skipping test definition patterns.
11107 14:02:26.960519 nfrost
11108 14:02:26.963789 + cd /lava-12682978/0/tests/0_igt-gpu-panfrost
11109 14:02:26.964210 + cat uuid
11110 14:02:26.967235 + UUID=12682978_1.5.2.3.1
11111 14:02:26.967661 + set +x
11112 14:02:26.980294 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param <8>[ 20.334297] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11113 14:02:26.981220 Received signal: <TESTSET> START panfrost_gem_new
11114 14:02:26.981796 Starting test_set panfrost_gem_new
11115 14:02:26.983712 panfrost_prime panfrost_submit
11116 14:02:27.000127 <14>[ 20.354455] [IGT] panfrost_gem_new: executing
11117 14:02:27.006713 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.361417] [IGT] panfrost_gem_new: exiting, ret=77
11118 14:02:27.010342 rch64) (Linux: 6.1.72-cip13 aarch64)
11119 14:02:27.020031 Test requirement not met i<8>[ 20.371982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11120 14:02:27.020722 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11122 14:02:27.026858 n function drm_open_driver, file ../lib/drmtest.c:621:
11123 14:02:27.027420 Test requirement: !(fd<0)
11124 14:02:27.033844 No known gpu found for chipset flags 0x32 (panfrost)
11125 14:02:27.036784 Last er<14>[ 20.392058] [IGT] panfrost_gem_new: executing
11126 14:02:27.046745 rno: 2, No such file or director<14>[ 20.399061] [IGT] panfrost_gem_new: exiting, ret=77
11127 14:02:27.047404 y
11128 14:02:27.050092 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11129 14:02:27.057330 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11131 14:02:27.060054 IGT-Version: 1.2<8>[ 20.409822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11132 14:02:27.063040 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11133 14:02:27.069868 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11134 14:02:27.072910 Test requirement: !(fd<0)
11135 14:02:27.076925 No known gpu found for chipset flags 0x32 (panfrost)
11136 14:02:27.080064 Last errno: 2, No such file or directory
11137 14:02:27.083080 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11138 14:02:27.089999 <14>[ 20.444253] [IGT] panfrost_gem_new: executing
11139 14:02:27.096724 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.451950] [IGT] panfrost_gem_new: exiting, ret=77
11140 14:02:27.100628 rch64) (Linux: 6.1.72-cip13 aarch64)
11141 14:02:27.113045 Test requirement not met in function drm_open_driver, file<8>[ 20.465141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11142 14:02:27.113767 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11144 14:02:27.116772 ../lib/drmtest.c:621:
11145 14:02:27.119483 Test req<8>[ 20.474419] <LAVA_SIGNAL_TESTSET STOP>
11146 14:02:27.120246 Received signal: <TESTSET> STOP
11147 14:02:27.120605 Closing test_set panfrost_gem_new
11148 14:02:27.123261 uirement: !(fd<0)
11149 14:02:27.126502 No known gpu found for chipset flags 0x32 (panfrost)
11150 14:02:27.129704 Last errno: 2, No such file or directory
11151 14:02:27.132813 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11152 14:02:27.150656 <8>[ 20.504857] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11153 14:02:27.151344 Received signal: <TESTSET> START panfrost_get_param
11154 14:02:27.151697 Starting test_set panfrost_get_param
11155 14:02:27.168798 <14>[ 20.523098] [IGT] panfrost_get_param: executing
11156 14:02:27.176381 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.530169] [IGT] panfrost_get_param: exiting, ret=77
11157 14:02:27.178493 rch64) (Linux: 6.1.72-cip13 aarch64)
11158 14:02:27.188994 Test requirement not met i<8>[ 20.541502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11159 14:02:27.189669 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11161 14:02:27.195401 n function drm_open_driver, file ../lib/drmtest.c:621:
11162 14:02:27.195917 Test requirement: !(fd<0)
11163 14:02:27.202621 No known gpu found for chipset flags 0x32 (panfrost)
11164 14:02:27.208706 Last errno: 2, No such file or director<14>[ 20.562676] [IGT] panfrost_get_param: executing
11165 14:02:27.209313 y
11166 14:02:27.218462 [1mSubtest base-params: SKIP<14>[ 20.570961] [IGT] panfrost_get_param: exiting, ret=77
11167 14:02:27.218911 (0.000s)[0m
11168 14:02:27.232435 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch<8>[ 20.582853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11169 14:02:27.232861 64)
11170 14:02:27.233456 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11172 14:02:27.238773 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11173 14:02:27.241464 Test requirement: !(fd<0)
11174 14:02:27.245146 No known gpu found for chipset flags 0x32 (panfrost)
11175 14:02:27.251791 Last err<14>[ 20.606537] [IGT] panfrost_get_param: executing
11176 14:02:27.261747 no: 2, No such file or directory<14>[ 20.613637] [IGT] panfrost_get_param: exiting, ret=77
11177 14:02:27.262171
11178 14:02:27.265345 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11179 14:02:27.275130 IGT-Version: 1.27.1-g621c2d3 (aa<8>[ 20.626394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11180 14:02:27.275910 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11182 14:02:27.281932 rch64) (Linux: 6.1.72-cip13 aarc<8>[ 20.635544] <LAVA_SIGNAL_TESTSET STOP>
11183 14:02:27.282371 h64)
11184 14:02:27.283000 Received signal: <TESTSET> STOP
11185 14:02:27.283332 Closing test_set panfrost_get_param
11186 14:02:27.289089 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11187 14:02:27.291482 Test requirement: !(fd<0)
11188 14:02:27.294969 No known gpu found for chipset flags 0x32 (panfrost)
11189 14:02:27.298669 Last errno: 2, No such file or directory
11190 14:02:27.304882 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11191 14:02:27.312111 <8>[ 20.666817] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11192 14:02:27.312881 Received signal: <TESTSET> START panfrost_prime
11193 14:02:27.313249 Starting test_set panfrost_prime
11194 14:02:27.340550 <14>[ 20.694813] [IGT] panfrost_prime: executing
11195 14:02:27.350196 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.702448] [IGT] panfrost_prime: exiting, ret=77
11196 14:02:27.350683 .1.72-cip13 aarch64)
11197 14:02:27.364181 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11199 14:02:27.367002 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 20.716267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11200 14:02:27.367426 c:621:
11201 14:02:27.370712 Received signal: <TESTSET> STOP
11202 14:02:27.371128 Closing test_set panfrost_prime
11203 14:02:27.373502 Test requirement: !(fd<0<8>[ 20.726500] <LAVA_SIGNAL_TESTSET STOP>
11204 14:02:27.373922 )
11205 14:02:27.376965 No known gpu found for chipset flags 0x32 (panfrost)
11206 14:02:27.380380 Last errno: 2, No such file or directory
11207 14:02:27.383464 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11208 14:02:27.406033 <8>[ 20.760858] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11209 14:02:27.406443 Received signal: <TESTSET> START panfrost_submit
11210 14:02:27.406659 Starting test_set panfrost_submit
11211 14:02:27.437672 <14>[ 20.792090] [IGT] panfrost_submit: executing
11212 14:02:27.443974 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.800082] [IGT] panfrost_submit: exiting, ret=77
11213 14:02:27.447124 rch64) (Linux: 6.1.72-cip13 aarch64)
11214 14:02:27.460659 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 20.814652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11215 14:02:27.461096 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11217 14:02:27.463950 c:621:
11218 14:02:27.464172 Test requirement: !(fd<0)
11219 14:02:27.471052 No known gpu found for chipset flags 0x32 (panfrost)
11220 14:02:27.474464 Last errno: 2, No such file or directory
11221 14:02:27.477812 [1mSubtest pan-submit: SKIP (0.000s)[0m
11222 14:02:27.489889 <14>[ 20.844300] [IGT] panfrost_submit: executing
11223 14:02:27.496873 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.851927] [IGT] panfrost_submit: exiting, ret=77
11224 14:02:27.499810 rch64) (Linux: 6.1.72-cip13 aarch64)
11225 14:02:27.512981 Test requirement not met in function drm_open_driver, file<8>[ 20.864592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11226 14:02:27.513668 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11228 14:02:27.516384 ../lib/drmtest.c:621:
11229 14:02:27.520202 Test requirement: !(fd<0)
11230 14:02:27.523092 No known gpu found for chipset flags 0x32 (panfrost)
11231 14:02:27.526909 Last errno: 2, No such file or directory
11232 14:02:27.533025 [1mSubtest p<14>[ 20.886329] [IGT] panfrost_submit: executing
11233 14:02:27.539708 an-submit-error-no-jc: SKIP (0.0<14>[ 20.893990] [IGT] panfrost_submit: exiting, ret=77
11234 14:02:27.540128 00s)[0m
11235 14:02:27.546225 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11236 14:02:27.556537 Test requirement<8>[ 20.907148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11237 14:02:27.557225 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11239 14:02:27.562865 not met in function drm_open_driver, file ../lib/drmtest.c:621:
11240 14:02:27.566553 Test requirement: !(fd<0)
11241 14:02:27.570124 No known gpu found for chipset flags 0x32 (panfrost)
11242 14:02:27.573509 Last errno: 2, No such file or directory
11243 14:02:27.579865 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11244 14:02:27.583189 <14>[ 20.938379] [IGT] panfrost_submit: executing
11245 14:02:27.593275 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.946224] [IGT] panfrost_submit: exiting, ret=77
11246 14:02:27.596201 .1.72-cip13 aarch64)
11247 14:02:27.602798 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11248 14:02:27.612922 Test req<8>[ 20.962177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11249 14:02:27.613524 uirement: !(fd<0)
11250 14:02:27.614365 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11252 14:02:27.619684 No known gpu found for chipset flags 0x32 (panfrost)
11253 14:02:27.622884 Last errno: 2, No such file or directory
11254 14:02:27.625987 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11255 14:02:27.639256 <14>[ 20.993250] [IGT] panfrost_submit: executing
11256 14:02:27.650081 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.001028] [IGT] panfrost_submit: exiting, ret=77
11257 14:02:27.650533 .1.72-cip13 aarch64)
11258 14:02:27.665477 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 21.015109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11259 14:02:27.665940 c:621:
11260 14:02:27.666527 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11262 14:02:27.669175 Test requirement: !(fd<0)
11263 14:02:27.672568 No known gpu found for chipset flags 0x32 (panfrost)
11264 14:02:27.675676 Last errno: 2, No such file or directory
11265 14:02:27.682502 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11266 14:02:27.691922 <14>[ 21.046108] [IGT] panfrost_submit: executing
11267 14:02:27.701539 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.053796] [IGT] panfrost_submit: exiting, ret=77
11268 14:02:27.701965 .1.72-cip13 aarch64)
11269 14:02:27.708589 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11270 14:02:27.718667 Test req<8>[ 21.069788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11271 14:02:27.719394 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11273 14:02:27.721421 uirement: !(fd<0)
11274 14:02:27.725064 No known gpu found for chipset flags 0x32 (panfrost)
11275 14:02:27.728301 Last errno: 2, No such file or directory
11276 14:02:27.735117 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11277 14:02:27.746292 <14>[ 21.100789] [IGT] panfrost_submit: executing
11278 14:02:27.756233 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.108449] [IGT] panfrost_submit: exiting, ret=77
11279 14:02:27.756769 .1.72-cip13 aarch64)
11280 14:02:27.769742 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 21.122991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11281 14:02:27.770616 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11283 14:02:27.773151 c:621:
11284 14:02:27.773692 Test requirement: !(fd<0)
11285 14:02:27.779292 No known gpu found for chipset flags 0x32 (panfrost)
11286 14:02:27.782968 Last errno: 2, No such file or directory
11287 14:02:27.786588 [1mSubtest pan-reset: SKIP (0.000s)[0m
11288 14:02:27.797372 <14>[ 21.151675] [IGT] panfrost_submit: executing
11289 14:02:27.808008 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.159396] [IGT] panfrost_submit: exiting, ret=77
11290 14:02:27.808432 .1.72-cip13 aarch64)
11291 14:02:27.814504 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11292 14:02:27.823965 Test req<8>[ 21.175200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11293 14:02:27.824809 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11295 14:02:27.826945 uirement: !(fd<0)
11296 14:02:27.830434 No known gpu found for chipset flags 0x32 (panfrost)
11297 14:02:27.833752 Last errno: 2, No such file or directory
11298 14:02:27.836861 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11299 14:02:27.851659 <14>[ 21.206084] [IGT] panfrost_submit: executing
11300 14:02:27.861575 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.213854] [IGT] panfrost_submit: exiting, ret=77
11301 14:02:27.862166 .1.72-cip13 aarch64)
11302 14:02:27.878599 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 21.227720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11303 14:02:27.879164 c:621:
11304 14:02:27.879808 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11306 14:02:27.885605 Test requirement: !(fd<0<8>[ 21.238942] <LAVA_SIGNAL_TESTSET STOP>
11307 14:02:27.886093 )
11308 14:02:27.886762 Received signal: <TESTSET> STOP
11309 14:02:27.887126 Closing test_set panfrost_submit
11310 14:02:27.892026 No known gpu <8>[ 21.244206] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12682978_1.5.2.3.1>
11311 14:02:27.892749 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12682978_1.5.2.3.1
11312 14:02:27.893297 Ending use of test pattern.
11313 14:02:27.893718 Ending test lava.0_igt-gpu-panfrost (12682978_1.5.2.3.1), duration 0.94
11315 14:02:27.895832 found for chipset flags 0x32 (panfrost)
11316 14:02:27.898451 Last errno: 2, No such file or directory
11317 14:02:27.905326 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11318 14:02:27.905926 + set +x
11319 14:02:27.908275 <LAVA_TEST_RUNNER EXIT>
11320 14:02:27.909027 ok: lava_test_shell seems to have completed
11321 14:02:27.911717 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11322 14:02:27.912281 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11323 14:02:27.912960 end: 3 lava-test-retry (duration 00:00:01) [common]
11324 14:02:27.913498 start: 4 finalize (timeout 00:07:08) [common]
11325 14:02:27.914186 start: 4.1 power-off (timeout 00:00:30) [common]
11326 14:02:27.915439 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11327 14:02:28.021913 >> Command sent successfully.
11328 14:02:28.025079 Returned 0 in 0 seconds
11329 14:02:28.125866 end: 4.1 power-off (duration 00:00:00) [common]
11331 14:02:28.127575 start: 4.2 read-feedback (timeout 00:07:08) [common]
11332 14:02:28.128804 Listened to connection for namespace 'common' for up to 1s
11333 14:02:29.129389 Finalising connection for namespace 'common'
11334 14:02:29.130025 Disconnecting from shell: Finalise
11335 14:02:29.130452 / #
11336 14:02:29.231446 end: 4.2 read-feedback (duration 00:00:01) [common]
11337 14:02:29.232251 end: 4 finalize (duration 00:00:01) [common]
11338 14:02:29.233054 Cleaning after the job
11339 14:02:29.233763 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/ramdisk
11340 14:02:29.261510 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/kernel
11341 14:02:29.275866 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/dtb
11342 14:02:29.276112 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682978/tftp-deploy-ut4sv5oc/modules
11343 14:02:29.285033 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682978
11344 14:02:29.405930 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682978
11345 14:02:29.406096 Job finished correctly