Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 36
1 13:58:49.441554 lava-dispatcher, installed at version: 2023.10
2 13:58:49.441748 start: 0 validate
3 13:58:49.441892 Start time: 2024-02-01 13:58:49.441881+00:00 (UTC)
4 13:58:49.442089 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:58:49.442229 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 13:58:49.710411 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:58:49.710632 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:58:49.976527 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:58:49.977281 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:58:50.246273 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:58:50.246447 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:58:50.511812 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:58:50.511986 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:58:50.770824 validate duration: 1.33
16 13:58:50.771081 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:58:50.771181 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:58:50.771271 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:58:50.771397 Not decompressing ramdisk as can be used compressed.
20 13:58:50.771486 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 13:58:50.771554 saving as /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/ramdisk/initrd.cpio.gz
22 13:58:50.771654 total size: 4665395 (4 MB)
23 13:58:50.772867 progress 0 % (0 MB)
24 13:58:50.774382 progress 5 % (0 MB)
25 13:58:50.775738 progress 10 % (0 MB)
26 13:58:50.776956 progress 15 % (0 MB)
27 13:58:50.778209 progress 20 % (0 MB)
28 13:58:50.779418 progress 25 % (1 MB)
29 13:58:50.780743 progress 30 % (1 MB)
30 13:58:50.781999 progress 35 % (1 MB)
31 13:58:50.783230 progress 40 % (1 MB)
32 13:58:50.784616 progress 45 % (2 MB)
33 13:58:50.785823 progress 50 % (2 MB)
34 13:58:50.787067 progress 55 % (2 MB)
35 13:58:50.788269 progress 60 % (2 MB)
36 13:58:50.789464 progress 65 % (2 MB)
37 13:58:50.790713 progress 70 % (3 MB)
38 13:58:50.791911 progress 75 % (3 MB)
39 13:58:50.793107 progress 80 % (3 MB)
40 13:58:50.794493 progress 85 % (3 MB)
41 13:58:50.795692 progress 90 % (4 MB)
42 13:58:50.796887 progress 95 % (4 MB)
43 13:58:50.798111 progress 100 % (4 MB)
44 13:58:50.798264 4 MB downloaded in 0.03 s (167.21 MB/s)
45 13:58:50.798418 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:58:50.798665 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:58:50.798754 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:58:50.798840 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:58:50.798962 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:58:50.799037 saving as /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/kernel/Image
52 13:58:50.799101 total size: 51532288 (49 MB)
53 13:58:50.799165 No compression specified
54 13:58:50.800493 progress 0 % (0 MB)
55 13:58:50.813905 progress 5 % (2 MB)
56 13:58:50.827216 progress 10 % (4 MB)
57 13:58:50.840171 progress 15 % (7 MB)
58 13:58:50.853592 progress 20 % (9 MB)
59 13:58:50.866900 progress 25 % (12 MB)
60 13:58:50.879954 progress 30 % (14 MB)
61 13:58:50.893299 progress 35 % (17 MB)
62 13:58:50.906456 progress 40 % (19 MB)
63 13:58:50.919497 progress 45 % (22 MB)
64 13:58:50.932656 progress 50 % (24 MB)
65 13:58:50.945663 progress 55 % (27 MB)
66 13:58:50.958875 progress 60 % (29 MB)
67 13:58:50.971874 progress 65 % (31 MB)
68 13:58:50.984859 progress 70 % (34 MB)
69 13:58:50.998032 progress 75 % (36 MB)
70 13:58:51.011171 progress 80 % (39 MB)
71 13:58:51.024145 progress 85 % (41 MB)
72 13:58:51.037125 progress 90 % (44 MB)
73 13:58:51.050063 progress 95 % (46 MB)
74 13:58:51.062734 progress 100 % (49 MB)
75 13:58:51.062942 49 MB downloaded in 0.26 s (186.27 MB/s)
76 13:58:51.063091 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:58:51.063331 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:58:51.063424 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:58:51.063512 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:58:51.063645 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:58:51.063716 saving as /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/dtb/mt8192-asurada-spherion-r0.dtb
83 13:58:51.063779 total size: 47278 (0 MB)
84 13:58:51.063842 No compression specified
85 13:58:51.064910 progress 69 % (0 MB)
86 13:58:51.065184 progress 100 % (0 MB)
87 13:58:51.065339 0 MB downloaded in 0.00 s (28.93 MB/s)
88 13:58:51.065463 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:58:51.065695 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:58:51.065784 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:58:51.065870 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:58:51.066020 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 13:58:51.066091 saving as /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/nfsrootfs/full.rootfs.tar
95 13:58:51.066154 total size: 200813988 (191 MB)
96 13:58:51.066217 Using unxz to decompress xz
97 13:58:51.069882 progress 0 % (0 MB)
98 13:58:51.597077 progress 5 % (9 MB)
99 13:58:52.110858 progress 10 % (19 MB)
100 13:58:52.690362 progress 15 % (28 MB)
101 13:58:53.063121 progress 20 % (38 MB)
102 13:58:53.384366 progress 25 % (47 MB)
103 13:58:53.973773 progress 30 % (57 MB)
104 13:58:54.519626 progress 35 % (67 MB)
105 13:58:55.106050 progress 40 % (76 MB)
106 13:58:55.660002 progress 45 % (86 MB)
107 13:58:56.236032 progress 50 % (95 MB)
108 13:58:56.860532 progress 55 % (105 MB)
109 13:58:57.521853 progress 60 % (114 MB)
110 13:58:57.642162 progress 65 % (124 MB)
111 13:58:57.784332 progress 70 % (134 MB)
112 13:58:57.881090 progress 75 % (143 MB)
113 13:58:57.952737 progress 80 % (153 MB)
114 13:58:58.021673 progress 85 % (162 MB)
115 13:58:58.123133 progress 90 % (172 MB)
116 13:58:58.413278 progress 95 % (181 MB)
117 13:58:59.005016 progress 100 % (191 MB)
118 13:58:59.010430 191 MB downloaded in 7.94 s (24.11 MB/s)
119 13:58:59.010679 end: 1.4.1 http-download (duration 00:00:08) [common]
121 13:58:59.010943 end: 1.4 download-retry (duration 00:00:08) [common]
122 13:58:59.011035 start: 1.5 download-retry (timeout 00:09:52) [common]
123 13:58:59.011124 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 13:58:59.011273 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:58:59.011345 saving as /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/modules/modules.tar
126 13:58:59.011407 total size: 8623988 (8 MB)
127 13:58:59.011471 Using unxz to decompress xz
128 13:58:59.015130 progress 0 % (0 MB)
129 13:58:59.036230 progress 5 % (0 MB)
130 13:58:59.059593 progress 10 % (0 MB)
131 13:58:59.083157 progress 15 % (1 MB)
132 13:58:59.106989 progress 20 % (1 MB)
133 13:58:59.131075 progress 25 % (2 MB)
134 13:58:59.156766 progress 30 % (2 MB)
135 13:58:59.182702 progress 35 % (2 MB)
136 13:58:59.205970 progress 40 % (3 MB)
137 13:58:59.230412 progress 45 % (3 MB)
138 13:58:59.255690 progress 50 % (4 MB)
139 13:58:59.279625 progress 55 % (4 MB)
140 13:58:59.304251 progress 60 % (4 MB)
141 13:58:59.331577 progress 65 % (5 MB)
142 13:58:59.356566 progress 70 % (5 MB)
143 13:58:59.379887 progress 75 % (6 MB)
144 13:58:59.406259 progress 80 % (6 MB)
145 13:58:59.431784 progress 85 % (7 MB)
146 13:58:59.456589 progress 90 % (7 MB)
147 13:58:59.488074 progress 95 % (7 MB)
148 13:58:59.515746 progress 100 % (8 MB)
149 13:58:59.520685 8 MB downloaded in 0.51 s (16.15 MB/s)
150 13:58:59.520937 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:58:59.521240 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:58:59.521334 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 13:58:59.521449 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 13:59:05.877053 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12682968/extract-nfsrootfs-oglozrbb
156 13:59:05.877262 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
157 13:59:05.877366 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
158 13:59:05.877528 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6
159 13:59:05.877654 makedir: /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin
160 13:59:05.877753 makedir: /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/tests
161 13:59:05.877849 makedir: /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/results
162 13:59:05.878079 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-add-keys
163 13:59:05.878226 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-add-sources
164 13:59:05.878350 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-background-process-start
165 13:59:05.878471 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-background-process-stop
166 13:59:05.878593 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-common-functions
167 13:59:05.878711 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-echo-ipv4
168 13:59:05.878829 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-install-packages
169 13:59:05.878946 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-installed-packages
170 13:59:05.879098 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-os-build
171 13:59:05.879221 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-probe-channel
172 13:59:05.879339 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-probe-ip
173 13:59:05.879455 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-target-ip
174 13:59:05.879571 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-target-mac
175 13:59:05.879687 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-target-storage
176 13:59:05.879805 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-test-case
177 13:59:05.879925 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-test-event
178 13:59:05.880043 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-test-feedback
179 13:59:05.880161 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-test-raise
180 13:59:05.880277 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-test-reference
181 13:59:05.880393 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-test-runner
182 13:59:05.880509 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-test-set
183 13:59:05.880625 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-test-shell
184 13:59:05.880745 Updating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-add-keys (debian)
185 13:59:07.147282 Updating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-add-sources (debian)
186 13:59:07.148335 Updating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-install-packages (debian)
187 13:59:07.149146 Updating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-installed-packages (debian)
188 13:59:07.149923 Updating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/bin/lava-os-build (debian)
189 13:59:07.150683 Creating /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/environment
190 13:59:07.151258 LAVA metadata
191 13:59:07.151669 - LAVA_JOB_ID=12682968
192 13:59:07.152043 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:59:07.152633 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:44) [common]
194 13:59:07.152996 skipped lava-vland-overlay
195 13:59:07.153394 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:59:07.153819 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:44) [common]
197 13:59:07.154218 skipped lava-multinode-overlay
198 13:59:07.154640 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:59:07.155090 start: 1.6.2.3 test-definition (timeout 00:09:44) [common]
200 13:59:07.155513 Loading test definitions
201 13:59:07.156017 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:44) [common]
202 13:59:07.156430 Using /lava-12682968 at stage 0
203 13:59:07.158013 uuid=12682968_1.6.2.3.1 testdef=None
204 13:59:07.158519 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:59:07.159001 start: 1.6.2.3.2 test-overlay (timeout 00:09:44) [common]
206 13:59:07.161488 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:59:07.162811 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:44) [common]
209 13:59:07.165816 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:59:07.167041 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:44) [common]
212 13:59:07.180023 runner path: /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/0/tests/0_timesync-off test_uuid 12682968_1.6.2.3.1
213 13:59:07.180473 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:59:07.181130 start: 1.6.2.3.5 git-repo-action (timeout 00:09:44) [common]
216 13:59:07.181337 Using /lava-12682968 at stage 0
217 13:59:07.181651 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:59:07.181997 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/0/tests/1_kselftest-arm64'
219 13:59:09.855990 Running '/usr/bin/git checkout kernelci.org
220 13:59:10.000636 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 13:59:10.001342 uuid=12682968_1.6.2.3.5 testdef=None
222 13:59:10.001498 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 13:59:10.001742 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 13:59:10.002546 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:59:10.002783 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 13:59:10.003754 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:59:10.003992 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 13:59:10.004921 runner path: /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/0/tests/1_kselftest-arm64 test_uuid 12682968_1.6.2.3.5
232 13:59:10.005015 BOARD='mt8192-asurada-spherion-r0'
233 13:59:10.005081 BRANCH='cip'
234 13:59:10.005148 SKIPFILE='/dev/null'
235 13:59:10.005208 SKIP_INSTALL='True'
236 13:59:10.005266 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 13:59:10.005326 TST_CASENAME=''
238 13:59:10.005383 TST_CMDFILES='arm64'
239 13:59:10.005523 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:59:10.005728 Creating lava-test-runner.conf files
242 13:59:10.005793 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682968/lava-overlay-_kqsqyy6/lava-12682968/0 for stage 0
243 13:59:10.005885 - 0_timesync-off
244 13:59:10.005995 - 1_kselftest-arm64
245 13:59:10.006093 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 13:59:10.006182 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 13:59:17.545738 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 13:59:17.545914 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 13:59:17.546029 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:59:17.546134 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 13:59:17.546230 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 13:59:17.659089 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:59:17.659491 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 13:59:17.659651 extracting modules file /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682968/extract-nfsrootfs-oglozrbb
255 13:59:17.929669 extracting modules file /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682968/extract-overlay-ramdisk-vjyhxnkp/ramdisk
256 13:59:18.191589 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 13:59:18.191798 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 13:59:18.191920 [common] Applying overlay to NFS
259 13:59:18.192025 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682968/compress-overlay-cmtgagpo/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682968/extract-nfsrootfs-oglozrbb
260 13:59:19.150152 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:59:19.150326 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 13:59:19.150422 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:59:19.150517 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 13:59:19.150602 Building ramdisk /var/lib/lava/dispatcher/tmp/12682968/extract-overlay-ramdisk-vjyhxnkp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682968/extract-overlay-ramdisk-vjyhxnkp/ramdisk
265 13:59:19.417195 >> 119414 blocks
266 13:59:21.313678 rename /var/lib/lava/dispatcher/tmp/12682968/extract-overlay-ramdisk-vjyhxnkp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/ramdisk/ramdisk.cpio.gz
267 13:59:21.314143 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:59:21.314265 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 13:59:21.314367 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 13:59:21.314474 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/kernel/Image'
271 13:59:33.864393 Returned 0 in 12 seconds
272 13:59:33.964998 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/kernel/image.itb
273 13:59:34.367241 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:59:34.367598 output: Created: Thu Feb 1 13:59:34 2024
275 13:59:34.367670 output: Image 0 (kernel-1)
276 13:59:34.367739 output: Description:
277 13:59:34.367802 output: Created: Thu Feb 1 13:59:34 2024
278 13:59:34.367866 output: Type: Kernel Image
279 13:59:34.367929 output: Compression: lzma compressed
280 13:59:34.367992 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
281 13:59:34.368052 output: Architecture: AArch64
282 13:59:34.368113 output: OS: Linux
283 13:59:34.368171 output: Load Address: 0x00000000
284 13:59:34.368230 output: Entry Point: 0x00000000
285 13:59:34.368286 output: Hash algo: crc32
286 13:59:34.368345 output: Hash value: 5aa40db2
287 13:59:34.368400 output: Image 1 (fdt-1)
288 13:59:34.368456 output: Description: mt8192-asurada-spherion-r0
289 13:59:34.368510 output: Created: Thu Feb 1 13:59:34 2024
290 13:59:34.368565 output: Type: Flat Device Tree
291 13:59:34.368619 output: Compression: uncompressed
292 13:59:34.368673 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 13:59:34.368727 output: Architecture: AArch64
294 13:59:34.368781 output: Hash algo: crc32
295 13:59:34.368834 output: Hash value: cc4352de
296 13:59:34.368888 output: Image 2 (ramdisk-1)
297 13:59:34.368942 output: Description: unavailable
298 13:59:34.368996 output: Created: Thu Feb 1 13:59:34 2024
299 13:59:34.369050 output: Type: RAMDisk Image
300 13:59:34.369103 output: Compression: Unknown Compression
301 13:59:34.369157 output: Data Size: 17806087 Bytes = 17388.76 KiB = 16.98 MiB
302 13:59:34.369210 output: Architecture: AArch64
303 13:59:34.369264 output: OS: Linux
304 13:59:34.369317 output: Load Address: unavailable
305 13:59:34.369371 output: Entry Point: unavailable
306 13:59:34.369425 output: Hash algo: crc32
307 13:59:34.369478 output: Hash value: 592fdc1c
308 13:59:34.369532 output: Default Configuration: 'conf-1'
309 13:59:34.369586 output: Configuration 0 (conf-1)
310 13:59:34.369639 output: Description: mt8192-asurada-spherion-r0
311 13:59:34.369693 output: Kernel: kernel-1
312 13:59:34.369746 output: Init Ramdisk: ramdisk-1
313 13:59:34.369799 output: FDT: fdt-1
314 13:59:34.369853 output: Loadables: kernel-1
315 13:59:34.369906 output:
316 13:59:34.370140 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 13:59:34.370238 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 13:59:34.370344 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 13:59:34.370437 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 13:59:34.370515 No LXC device requested
321 13:59:34.370602 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:59:34.370703 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 13:59:34.370783 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:59:34.370856 Checking files for TFTP limit of 4294967296 bytes.
325 13:59:34.371328 end: 1 tftp-deploy (duration 00:00:44) [common]
326 13:59:34.371438 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:59:34.371531 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:59:34.371659 substitutions:
329 13:59:34.371727 - {DTB}: 12682968/tftp-deploy-k9n83o5t/dtb/mt8192-asurada-spherion-r0.dtb
330 13:59:34.371792 - {INITRD}: 12682968/tftp-deploy-k9n83o5t/ramdisk/ramdisk.cpio.gz
331 13:59:34.371854 - {KERNEL}: 12682968/tftp-deploy-k9n83o5t/kernel/Image
332 13:59:34.371912 - {LAVA_MAC}: None
333 13:59:34.371970 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12682968/extract-nfsrootfs-oglozrbb
334 13:59:34.372029 - {NFS_SERVER_IP}: 192.168.201.1
335 13:59:34.372086 - {PRESEED_CONFIG}: None
336 13:59:34.372142 - {PRESEED_LOCAL}: None
337 13:59:34.372199 - {RAMDISK}: 12682968/tftp-deploy-k9n83o5t/ramdisk/ramdisk.cpio.gz
338 13:59:34.372254 - {ROOT_PART}: None
339 13:59:34.372309 - {ROOT}: None
340 13:59:34.372363 - {SERVER_IP}: 192.168.201.1
341 13:59:34.372419 - {TEE}: None
342 13:59:34.372474 Parsed boot commands:
343 13:59:34.372528 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:59:34.372708 Parsed boot commands: tftpboot 192.168.201.1 12682968/tftp-deploy-k9n83o5t/kernel/image.itb 12682968/tftp-deploy-k9n83o5t/kernel/cmdline
345 13:59:34.372800 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:59:34.372885 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:59:34.372978 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:59:34.373065 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:59:34.373137 Not connected, no need to disconnect.
350 13:59:34.373211 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:59:34.373292 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:59:34.373360 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 13:59:34.376716 Setting prompt string to ['lava-test: # ']
354 13:59:34.377047 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:59:34.377153 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:59:34.377254 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:59:34.377351 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:59:34.377544 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 13:59:39.527630 >> Command sent successfully.
360 13:59:39.537990 Returned 0 in 5 seconds
361 13:59:39.639226 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 13:59:39.640645 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 13:59:39.641147 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 13:59:39.641596 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:59:39.641995 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:59:39.642445 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:59:39.643683 [Enter `^Ec?' for help]
369 13:59:39.806010
370 13:59:39.806553
371 13:59:39.806961 F0: 102B 0000
372 13:59:39.807341
373 13:59:39.807672 F3: 1001 0000 [0200]
374 13:59:39.807998
375 13:59:39.809209 F3: 1001 0000
376 13:59:39.809572
377 13:59:39.810007 F7: 102D 0000
378 13:59:39.810351
379 13:59:39.810663 F1: 0000 0000
380 13:59:39.810975
381 13:59:39.813071 V0: 0000 0000 [0001]
382 13:59:39.813568
383 13:59:39.813937 00: 0007 8000
384 13:59:39.814346
385 13:59:39.817439 01: 0000 0000
386 13:59:39.817921
387 13:59:39.818336 BP: 0C00 0209 [0000]
388 13:59:39.818674
389 13:59:39.818984 G0: 1182 0000
390 13:59:39.819305
391 13:59:39.821133 EC: 0000 0021 [4000]
392 13:59:39.821735
393 13:59:39.822290 S7: 0000 0000 [0000]
394 13:59:39.822651
395 13:59:39.824813 CC: 0000 0000 [0001]
396 13:59:39.825210
397 13:59:39.825529 T0: 0000 0040 [010F]
398 13:59:39.825867
399 13:59:39.828172 Jump to BL
400 13:59:39.828637
401 13:59:39.852550
402 13:59:39.852998
403 13:59:39.853358
404 13:59:39.860102 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 13:59:39.863662 ARM64: Exception handlers installed.
406 13:59:39.866758 ARM64: Testing exception
407 13:59:39.870829 ARM64: Done test exception
408 13:59:39.877778 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 13:59:39.884887 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 13:59:39.892522 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 13:59:39.903149 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 13:59:39.909692 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 13:59:39.919770 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 13:59:39.930836 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 13:59:39.937540 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 13:59:39.954839 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 13:59:39.958565 WDT: Last reset was cold boot
418 13:59:39.961850 SPI1(PAD0) initialized at 2873684 Hz
419 13:59:39.965415 SPI5(PAD0) initialized at 992727 Hz
420 13:59:39.968481 VBOOT: Loading verstage.
421 13:59:39.975385 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 13:59:39.978515 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 13:59:39.981852 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 13:59:39.984985 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 13:59:39.992675 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 13:59:39.999069 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 13:59:40.010132 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 13:59:40.010608
429 13:59:40.010959
430 13:59:40.019780 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 13:59:40.023647 ARM64: Exception handlers installed.
432 13:59:40.026899 ARM64: Testing exception
433 13:59:40.027386 ARM64: Done test exception
434 13:59:40.033112 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 13:59:40.036887 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 13:59:40.051397 Probing TPM: . done!
437 13:59:40.051837 TPM ready after 0 ms
438 13:59:40.058117 Connected to device vid:did:rid of 1ae0:0028:00
439 13:59:40.065099 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 13:59:40.121861 Initialized TPM device CR50 revision 0
441 13:59:40.134054 tlcl_send_startup: Startup return code is 0
442 13:59:40.134502 TPM: setup succeeded
443 13:59:40.145645 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 13:59:40.154239 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 13:59:40.164568 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 13:59:40.173989 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 13:59:40.177578 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 13:59:40.183660 in-header: 03 07 00 00 08 00 00 00
449 13:59:40.187010 in-data: aa e4 47 04 13 02 00 00
450 13:59:40.190799 Chrome EC: UHEPI supported
451 13:59:40.197821 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 13:59:40.201380 in-header: 03 ad 00 00 08 00 00 00
453 13:59:40.205217 in-data: 00 20 20 08 00 00 00 00
454 13:59:40.205690 Phase 1
455 13:59:40.208658 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 13:59:40.216807 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 13:59:40.220310 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 13:59:40.224155 Recovery requested (1009000e)
459 13:59:40.232540 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 13:59:40.237796 tlcl_extend: response is 0
461 13:59:40.247280 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 13:59:40.253057 tlcl_extend: response is 0
463 13:59:40.259608 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 13:59:40.280789 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 13:59:40.287730 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 13:59:40.288361
467 13:59:40.288728
468 13:59:40.297630 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 13:59:40.300993 ARM64: Exception handlers installed.
470 13:59:40.301432 ARM64: Testing exception
471 13:59:40.304290 ARM64: Done test exception
472 13:59:40.325570 pmic_efuse_setting: Set efuses in 11 msecs
473 13:59:40.328880 pmwrap_interface_init: Select PMIF_VLD_RDY
474 13:59:40.335727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 13:59:40.339647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 13:59:40.342981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 13:59:40.349677 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 13:59:40.353143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 13:59:40.360417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 13:59:40.364223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 13:59:40.367920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 13:59:40.371641 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 13:59:40.379045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 13:59:40.382932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 13:59:40.386658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 13:59:40.389920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 13:59:40.396798 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 13:59:40.403524 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 13:59:40.410983 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 13:59:40.414216 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 13:59:40.421673 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 13:59:40.425640 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 13:59:40.432481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 13:59:40.435527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 13:59:40.443171 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 13:59:40.449594 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 13:59:40.453046 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 13:59:40.459684 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 13:59:40.466253 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 13:59:40.469702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 13:59:40.473000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 13:59:40.479803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 13:59:40.483007 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 13:59:40.489669 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 13:59:40.492835 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 13:59:40.499587 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 13:59:40.502919 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 13:59:40.509874 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 13:59:40.513292 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 13:59:40.519952 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 13:59:40.523316 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 13:59:40.530053 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 13:59:40.533118 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 13:59:40.536489 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 13:59:40.542979 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 13:59:40.546831 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 13:59:40.550212 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 13:59:40.553991 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 13:59:40.560657 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 13:59:40.563963 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 13:59:40.567329 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 13:59:40.571085 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 13:59:40.577378 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 13:59:40.580678 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 13:59:40.587570 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 13:59:40.597407 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 13:59:40.601105 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 13:59:40.611276 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 13:59:40.617408 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 13:59:40.620831 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 13:59:40.627576 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:59:40.630608 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 13:59:40.638130 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2f
534 13:59:40.644516 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 13:59:40.647969 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 13:59:40.651309 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 13:59:40.662553 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 13:59:40.672058 [RTC]rtc_get_frequency_meter,154: input=23, output=956
539 13:59:40.681132 [RTC]rtc_get_frequency_meter,154: input=19, output=866
540 13:59:40.690929 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 13:59:40.701313 [RTC]rtc_get_frequency_meter,154: input=16, output=794
542 13:59:40.704566 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 13:59:40.708436 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 13:59:40.712258 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 13:59:40.719534 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 13:59:40.723177 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 13:59:40.723323 ADC[4]: Raw value=902876 ID=7
548 13:59:40.727090 ADC[3]: Raw value=213179 ID=1
549 13:59:40.730796 RAM Code: 0x71
550 13:59:40.734087 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 13:59:40.738063 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 13:59:40.745382 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 13:59:40.752886 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 13:59:40.756619 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 13:59:40.759989 in-header: 03 07 00 00 08 00 00 00
556 13:59:40.763313 in-data: aa e4 47 04 13 02 00 00
557 13:59:40.766716 Chrome EC: UHEPI supported
558 13:59:40.773230 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 13:59:40.776571 in-header: 03 ed 00 00 08 00 00 00
560 13:59:40.779909 in-data: 80 20 60 08 00 00 00 00
561 13:59:40.783284 MRC: failed to locate region type 0.
562 13:59:40.790108 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 13:59:40.793642 DRAM-K: Running full calibration
564 13:59:40.800379 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 13:59:40.800479 header.status = 0x0
566 13:59:40.803471 header.version = 0x6 (expected: 0x6)
567 13:59:40.806871 header.size = 0xd00 (expected: 0xd00)
568 13:59:40.810275 header.flags = 0x0
569 13:59:40.813648 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 13:59:40.833512 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 13:59:40.840909 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 13:59:40.841004 dram_init: ddr_geometry: 2
573 13:59:40.844154 [EMI] MDL number = 2
574 13:59:40.847727 [EMI] Get MDL freq = 0
575 13:59:40.847814 dram_init: ddr_type: 0
576 13:59:40.850567 is_discrete_lpddr4: 1
577 13:59:40.853763 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 13:59:40.853867
579 13:59:40.853965
580 13:59:40.857307 [Bian_co] ETT version 0.0.0.1
581 13:59:40.860476 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 13:59:40.860577
583 13:59:40.863782 dramc_set_vcore_voltage set vcore to 650000
584 13:59:40.867249 Read voltage for 800, 4
585 13:59:40.867326 Vio18 = 0
586 13:59:40.870505 Vcore = 650000
587 13:59:40.870608 Vdram = 0
588 13:59:40.870701 Vddq = 0
589 13:59:40.873733 Vmddr = 0
590 13:59:40.873834 dram_init: config_dvfs: 1
591 13:59:40.880494 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 13:59:40.883742 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 13:59:40.887088 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
594 13:59:40.893775 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
595 13:59:40.897499 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 13:59:40.900395 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 13:59:40.903724 MEM_TYPE=3, freq_sel=18
598 13:59:40.903798 sv_algorithm_assistance_LP4_1600
599 13:59:40.910697 ============ PULL DRAM RESETB DOWN ============
600 13:59:40.914104 ========== PULL DRAM RESETB DOWN end =========
601 13:59:40.917477 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 13:59:40.920836 ===================================
603 13:59:40.924162 LPDDR4 DRAM CONFIGURATION
604 13:59:40.927344 ===================================
605 13:59:40.930758 EX_ROW_EN[0] = 0x0
606 13:59:40.930868 EX_ROW_EN[1] = 0x0
607 13:59:40.933991 LP4Y_EN = 0x0
608 13:59:40.934065 WORK_FSP = 0x0
609 13:59:40.937266 WL = 0x2
610 13:59:40.937365 RL = 0x2
611 13:59:40.940594 BL = 0x2
612 13:59:40.940666 RPST = 0x0
613 13:59:40.944298 RD_PRE = 0x0
614 13:59:40.944373 WR_PRE = 0x1
615 13:59:40.947655 WR_PST = 0x0
616 13:59:40.947730 DBI_WR = 0x0
617 13:59:40.951026 DBI_RD = 0x0
618 13:59:40.951104 OTF = 0x1
619 13:59:40.954183 ===================================
620 13:59:40.957537 ===================================
621 13:59:40.960982 ANA top config
622 13:59:40.964347 ===================================
623 13:59:40.964464 DLL_ASYNC_EN = 0
624 13:59:40.967693 ALL_SLAVE_EN = 1
625 13:59:40.970890 NEW_RANK_MODE = 1
626 13:59:40.974182 DLL_IDLE_MODE = 1
627 13:59:40.977646 LP45_APHY_COMB_EN = 1
628 13:59:40.977731 TX_ODT_DIS = 1
629 13:59:40.980899 NEW_8X_MODE = 1
630 13:59:40.984330 ===================================
631 13:59:40.987720 ===================================
632 13:59:40.991057 data_rate = 1600
633 13:59:40.994382 CKR = 1
634 13:59:40.997722 DQ_P2S_RATIO = 8
635 13:59:41.000916 ===================================
636 13:59:41.001001 CA_P2S_RATIO = 8
637 13:59:41.004256 DQ_CA_OPEN = 0
638 13:59:41.007635 DQ_SEMI_OPEN = 0
639 13:59:41.010742 CA_SEMI_OPEN = 0
640 13:59:41.014283 CA_FULL_RATE = 0
641 13:59:41.017592 DQ_CKDIV4_EN = 1
642 13:59:41.017676 CA_CKDIV4_EN = 1
643 13:59:41.021038 CA_PREDIV_EN = 0
644 13:59:41.024362 PH8_DLY = 0
645 13:59:41.027760 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 13:59:41.031080 DQ_AAMCK_DIV = 4
647 13:59:41.034438 CA_AAMCK_DIV = 4
648 13:59:41.034523 CA_ADMCK_DIV = 4
649 13:59:41.037723 DQ_TRACK_CA_EN = 0
650 13:59:41.040841 CA_PICK = 800
651 13:59:41.044328 CA_MCKIO = 800
652 13:59:41.047646 MCKIO_SEMI = 0
653 13:59:41.051169 PLL_FREQ = 3068
654 13:59:41.054198 DQ_UI_PI_RATIO = 32
655 13:59:41.054282 CA_UI_PI_RATIO = 0
656 13:59:41.057592 ===================================
657 13:59:41.061146 ===================================
658 13:59:41.065036 memory_type:LPDDR4
659 13:59:41.067834 GP_NUM : 10
660 13:59:41.067919 SRAM_EN : 1
661 13:59:41.071206 MD32_EN : 0
662 13:59:41.074825 ===================================
663 13:59:41.074910 [ANA_INIT] >>>>>>>>>>>>>>
664 13:59:41.078626 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 13:59:41.083036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 13:59:41.086414 ===================================
667 13:59:41.090358 data_rate = 1600,PCW = 0X7600
668 13:59:41.093728 ===================================
669 13:59:41.093840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 13:59:41.101266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 13:59:41.105062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 13:59:41.112432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 13:59:41.116064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 13:59:41.119017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 13:59:41.119102 [ANA_INIT] flow start
676 13:59:41.122353 [ANA_INIT] PLL >>>>>>>>
677 13:59:41.125694 [ANA_INIT] PLL <<<<<<<<
678 13:59:41.125786 [ANA_INIT] MIDPI >>>>>>>>
679 13:59:41.128923 [ANA_INIT] MIDPI <<<<<<<<
680 13:59:41.132363 [ANA_INIT] DLL >>>>>>>>
681 13:59:41.132466 [ANA_INIT] flow end
682 13:59:41.136123 ============ LP4 DIFF to SE enter ============
683 13:59:41.142251 ============ LP4 DIFF to SE exit ============
684 13:59:41.142334 [ANA_INIT] <<<<<<<<<<<<<
685 13:59:41.145887 [Flow] Enable top DCM control >>>>>
686 13:59:41.149033 [Flow] Enable top DCM control <<<<<
687 13:59:41.152508 Enable DLL master slave shuffle
688 13:59:41.158830 ==============================================================
689 13:59:41.158913 Gating Mode config
690 13:59:41.165659 ==============================================================
691 13:59:41.169122 Config description:
692 13:59:41.178909 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 13:59:41.185788 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 13:59:41.189261 SELPH_MODE 0: By rank 1: By Phase
695 13:59:41.195958 ==============================================================
696 13:59:41.199358 GAT_TRACK_EN = 1
697 13:59:41.199433 RX_GATING_MODE = 2
698 13:59:41.202624 RX_GATING_TRACK_MODE = 2
699 13:59:41.206023 SELPH_MODE = 1
700 13:59:41.209110 PICG_EARLY_EN = 1
701 13:59:41.212339 VALID_LAT_VALUE = 1
702 13:59:41.219207 ==============================================================
703 13:59:41.222397 Enter into Gating configuration >>>>
704 13:59:41.225778 Exit from Gating configuration <<<<
705 13:59:41.229163 Enter into DVFS_PRE_config >>>>>
706 13:59:41.239327 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 13:59:41.242712 Exit from DVFS_PRE_config <<<<<
708 13:59:41.246063 Enter into PICG configuration >>>>
709 13:59:41.249421 Exit from PICG configuration <<<<
710 13:59:41.252714 [RX_INPUT] configuration >>>>>
711 13:59:41.252788 [RX_INPUT] configuration <<<<<
712 13:59:41.259217 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 13:59:41.265754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 13:59:41.269409 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 13:59:41.276989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 13:59:41.284257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 13:59:41.291453 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 13:59:41.295259 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 13:59:41.298556 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 13:59:41.302403 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 13:59:41.305724 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 13:59:41.309458 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 13:59:41.313075 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 13:59:41.316958 ===================================
725 13:59:41.320581 LPDDR4 DRAM CONFIGURATION
726 13:59:41.323839 ===================================
727 13:59:41.323927 EX_ROW_EN[0] = 0x0
728 13:59:41.327734 EX_ROW_EN[1] = 0x0
729 13:59:41.327813 LP4Y_EN = 0x0
730 13:59:41.331556 WORK_FSP = 0x0
731 13:59:41.331634 WL = 0x2
732 13:59:41.335322 RL = 0x2
733 13:59:41.335401 BL = 0x2
734 13:59:41.338749 RPST = 0x0
735 13:59:41.338825 RD_PRE = 0x0
736 13:59:41.342680 WR_PRE = 0x1
737 13:59:41.342757 WR_PST = 0x0
738 13:59:41.345971 DBI_WR = 0x0
739 13:59:41.346116 DBI_RD = 0x0
740 13:59:41.349869 OTF = 0x1
741 13:59:41.350037 ===================================
742 13:59:41.353769 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 13:59:41.357550 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 13:59:41.365587 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 13:59:41.369410 ===================================
746 13:59:41.369503 LPDDR4 DRAM CONFIGURATION
747 13:59:41.372919 ===================================
748 13:59:41.376452 EX_ROW_EN[0] = 0x10
749 13:59:41.376555 EX_ROW_EN[1] = 0x0
750 13:59:41.380205 LP4Y_EN = 0x0
751 13:59:41.380308 WORK_FSP = 0x0
752 13:59:41.384037 WL = 0x2
753 13:59:41.384116 RL = 0x2
754 13:59:41.384180 BL = 0x2
755 13:59:41.387901 RPST = 0x0
756 13:59:41.387984 RD_PRE = 0x0
757 13:59:41.391207 WR_PRE = 0x1
758 13:59:41.391311 WR_PST = 0x0
759 13:59:41.394802 DBI_WR = 0x0
760 13:59:41.394908 DBI_RD = 0x0
761 13:59:41.398751 OTF = 0x1
762 13:59:41.402509 ===================================
763 13:59:41.405811 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 13:59:41.411134 nWR fixed to 40
765 13:59:41.411237 [ModeRegInit_LP4] CH0 RK0
766 13:59:41.414820 [ModeRegInit_LP4] CH0 RK1
767 13:59:41.418511 [ModeRegInit_LP4] CH1 RK0
768 13:59:41.418596 [ModeRegInit_LP4] CH1 RK1
769 13:59:41.422361 match AC timing 13
770 13:59:41.426135 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 13:59:41.429805 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 13:59:41.433809 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 13:59:41.440662 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 13:59:41.444529 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 13:59:41.444607 [EMI DOE] emi_dcm 0
776 13:59:41.448838 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 13:59:41.448912 ==
778 13:59:41.452646 Dram Type= 6, Freq= 0, CH_0, rank 0
779 13:59:41.456074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 13:59:41.459962 ==
781 13:59:41.463340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 13:59:41.470748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 13:59:41.478624 [CA 0] Center 38 (7~69) winsize 63
784 13:59:41.482861 [CA 1] Center 38 (7~69) winsize 63
785 13:59:41.486211 [CA 2] Center 35 (5~66) winsize 62
786 13:59:41.490036 [CA 3] Center 35 (5~66) winsize 62
787 13:59:41.493540 [CA 4] Center 34 (4~65) winsize 62
788 13:59:41.493617 [CA 5] Center 33 (3~64) winsize 62
789 13:59:41.497472
790 13:59:41.501161 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 13:59:41.501237
792 13:59:41.504789 [CATrainingPosCal] consider 1 rank data
793 13:59:41.504866 u2DelayCellTimex100 = 270/100 ps
794 13:59:41.508680 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 13:59:41.512566 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 13:59:41.515851 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 13:59:41.519516 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 13:59:41.523290 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 13:59:41.527221 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 13:59:41.527319
801 13:59:41.531068 CA PerBit enable=1, Macro0, CA PI delay=33
802 13:59:41.531144
803 13:59:41.534599 [CBTSetCACLKResult] CA Dly = 33
804 13:59:41.534670 CS Dly: 5 (0~36)
805 13:59:41.538472 ==
806 13:59:41.538548 Dram Type= 6, Freq= 0, CH_0, rank 1
807 13:59:41.546099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 13:59:41.546174 ==
809 13:59:41.550113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 13:59:41.556713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 13:59:41.564911 [CA 0] Center 38 (7~69) winsize 63
812 13:59:41.568719 [CA 1] Center 38 (7~69) winsize 63
813 13:59:41.572237 [CA 2] Center 35 (5~66) winsize 62
814 13:59:41.575788 [CA 3] Center 35 (5~66) winsize 62
815 13:59:41.578893 [CA 4] Center 35 (4~66) winsize 63
816 13:59:41.582675 [CA 5] Center 34 (4~65) winsize 62
817 13:59:41.582755
818 13:59:41.585967 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 13:59:41.586054
820 13:59:41.589192 [CATrainingPosCal] consider 2 rank data
821 13:59:41.592460 u2DelayCellTimex100 = 270/100 ps
822 13:59:41.595578 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 13:59:41.598958 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 13:59:41.602297 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
825 13:59:41.605712 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 13:59:41.609091 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 13:59:41.612521 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 13:59:41.615873
829 13:59:41.619260 CA PerBit enable=1, Macro0, CA PI delay=34
830 13:59:41.619333
831 13:59:41.622557 [CBTSetCACLKResult] CA Dly = 34
832 13:59:41.622629 CS Dly: 6 (0~38)
833 13:59:41.622692
834 13:59:41.625653 ----->DramcWriteLeveling(PI) begin...
835 13:59:41.625728 ==
836 13:59:41.629047 Dram Type= 6, Freq= 0, CH_0, rank 0
837 13:59:41.632359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 13:59:41.632432 ==
839 13:59:41.635664 Write leveling (Byte 0): 33 => 33
840 13:59:41.639358 Write leveling (Byte 1): 33 => 33
841 13:59:41.642775 DramcWriteLeveling(PI) end<-----
842 13:59:41.642846
843 13:59:41.642909 ==
844 13:59:41.646153 Dram Type= 6, Freq= 0, CH_0, rank 0
845 13:59:41.652484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 13:59:41.652562 ==
847 13:59:41.652626 [Gating] SW mode calibration
848 13:59:41.659456 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 13:59:41.667123 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 13:59:41.670935 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 13:59:41.674698 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 13:59:41.678031 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 13:59:41.684818 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:59:41.688807 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:59:41.691778 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:59:41.695260 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:59:41.702064 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:59:41.705450 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:59:41.708575 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:59:41.715221 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:59:41.718773 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:59:41.722105 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:59:41.728649 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:59:41.732300 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:59:41.735218 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 13:59:41.742202 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 13:59:41.745543 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 13:59:41.748853 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
869 13:59:41.755578 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 13:59:41.758915 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 13:59:41.762236 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 13:59:41.765635 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:59:41.772306 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 13:59:41.775666 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 13:59:41.778998 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:59:41.785655 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 13:59:41.789008 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
878 13:59:41.792435 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 13:59:41.799049 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 13:59:41.802688 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 13:59:41.805756 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 13:59:41.812331 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 13:59:41.815450 0 10 4 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
884 13:59:41.818929 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
885 13:59:41.826043 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
886 13:59:41.829137 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 13:59:41.832610 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 13:59:41.839207 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 13:59:41.842468 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 13:59:41.845673 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 13:59:41.849120 0 11 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
892 13:59:41.855783 0 11 8 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
893 13:59:41.859219 0 11 12 | B1->B0 | 4342 4646 | 1 0 | (0 0) (0 0)
894 13:59:41.862221 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 13:59:41.868958 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 13:59:41.872247 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 13:59:41.876018 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 13:59:41.882642 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 13:59:41.886084 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 13:59:41.889463 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 13:59:41.895669 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 13:59:41.899416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:59:41.902525 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:59:41.909321 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:59:41.912792 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:59:41.915925 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:59:41.919397 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:59:41.925867 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:59:41.929366 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:59:41.932810 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:59:41.939324 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:59:41.942557 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 13:59:41.945946 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 13:59:41.952826 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 13:59:41.956120 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
916 13:59:41.959382 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 13:59:41.962767 Total UI for P1: 0, mck2ui 16
918 13:59:41.966121 best dqsien dly found for B0: ( 0, 14, 4)
919 13:59:41.972885 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 13:59:41.972968 Total UI for P1: 0, mck2ui 16
921 13:59:41.979246 best dqsien dly found for B1: ( 0, 14, 6)
922 13:59:41.982625 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 13:59:41.986122 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
924 13:59:41.986203
925 13:59:41.989503 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 13:59:41.992871 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
927 13:59:41.996123 [Gating] SW calibration Done
928 13:59:41.996208 ==
929 13:59:41.999381 Dram Type= 6, Freq= 0, CH_0, rank 0
930 13:59:42.002648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 13:59:42.002722 ==
932 13:59:42.006045 RX Vref Scan: 0
933 13:59:42.006118
934 13:59:42.006188 RX Vref 0 -> 0, step: 1
935 13:59:42.006249
936 13:59:42.009501 RX Delay -130 -> 252, step: 16
937 13:59:42.012609 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 13:59:42.019097 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 13:59:42.022703 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
940 13:59:42.026325 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
941 13:59:42.029218 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 13:59:42.032639 iDelay=222, Bit 5, Center 85 (-18 ~ 189) 208
943 13:59:42.039185 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 13:59:42.042632 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 13:59:42.046064 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 13:59:42.049396 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 13:59:42.052574 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
948 13:59:42.059587 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
949 13:59:42.062945 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 13:59:42.066195 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 13:59:42.069447 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 13:59:42.072820 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 13:59:42.072892 ==
954 13:59:42.076287 Dram Type= 6, Freq= 0, CH_0, rank 0
955 13:59:42.082715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 13:59:42.082791 ==
957 13:59:42.082855 DQS Delay:
958 13:59:42.086076 DQS0 = 0, DQS1 = 0
959 13:59:42.086153 DQM Delay:
960 13:59:42.086216 DQM0 = 94, DQM1 = 82
961 13:59:42.089490 DQ Delay:
962 13:59:42.092898 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
963 13:59:42.096149 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =101
964 13:59:42.099854 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =85
965 13:59:42.102995 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 13:59:42.103095
967 13:59:42.103185
968 13:59:42.103281 ==
969 13:59:42.106319 Dram Type= 6, Freq= 0, CH_0, rank 0
970 13:59:42.109767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 13:59:42.109870 ==
972 13:59:42.110027
973 13:59:42.110186
974 13:59:42.113036 TX Vref Scan disable
975 13:59:42.113171 == TX Byte 0 ==
976 13:59:42.119920 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
977 13:59:42.123313 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
978 13:59:42.123426 == TX Byte 1 ==
979 13:59:42.129872 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 13:59:42.133444 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 13:59:42.133529 ==
982 13:59:42.136661 Dram Type= 6, Freq= 0, CH_0, rank 0
983 13:59:42.139713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 13:59:42.139786 ==
985 13:59:42.153879 TX Vref=22, minBit 6, minWin=27, winSum=439
986 13:59:42.156667 TX Vref=24, minBit 6, minWin=27, winSum=441
987 13:59:42.160289 TX Vref=26, minBit 8, minWin=27, winSum=446
988 13:59:42.163619 TX Vref=28, minBit 8, minWin=27, winSum=448
989 13:59:42.166836 TX Vref=30, minBit 8, minWin=27, winSum=454
990 13:59:42.170237 TX Vref=32, minBit 10, minWin=27, winSum=455
991 13:59:42.176982 [TxChooseVref] Worse bit 10, Min win 27, Win sum 455, Final Vref 32
992 13:59:42.177093
993 13:59:42.180397 Final TX Range 1 Vref 32
994 13:59:42.180471
995 13:59:42.180541 ==
996 13:59:42.183710 Dram Type= 6, Freq= 0, CH_0, rank 0
997 13:59:42.187104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 13:59:42.187182 ==
999 13:59:42.187245
1000 13:59:42.190443
1001 13:59:42.190512 TX Vref Scan disable
1002 13:59:42.193795 == TX Byte 0 ==
1003 13:59:42.197237 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1004 13:59:42.200547 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1005 13:59:42.203690 == TX Byte 1 ==
1006 13:59:42.207318 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 13:59:42.210841 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 13:59:42.210919
1009 13:59:42.213849 [DATLAT]
1010 13:59:42.213965 Freq=800, CH0 RK0
1011 13:59:42.214050
1012 13:59:42.217191 DATLAT Default: 0xa
1013 13:59:42.217266 0, 0xFFFF, sum = 0
1014 13:59:42.220712 1, 0xFFFF, sum = 0
1015 13:59:42.220785 2, 0xFFFF, sum = 0
1016 13:59:42.223764 3, 0xFFFF, sum = 0
1017 13:59:42.223846 4, 0xFFFF, sum = 0
1018 13:59:42.227416 5, 0xFFFF, sum = 0
1019 13:59:42.227499 6, 0xFFFF, sum = 0
1020 13:59:42.230767 7, 0xFFFF, sum = 0
1021 13:59:42.230867 8, 0xFFFF, sum = 0
1022 13:59:42.233961 9, 0x0, sum = 1
1023 13:59:42.234058 10, 0x0, sum = 2
1024 13:59:42.237398 11, 0x0, sum = 3
1025 13:59:42.237480 12, 0x0, sum = 4
1026 13:59:42.240376 best_step = 10
1027 13:59:42.240455
1028 13:59:42.240518 ==
1029 13:59:42.243914 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 13:59:42.247331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 13:59:42.247406 ==
1032 13:59:42.250376 RX Vref Scan: 1
1033 13:59:42.250448
1034 13:59:42.250516 Set Vref Range= 32 -> 127
1035 13:59:42.250575
1036 13:59:42.253759 RX Vref 32 -> 127, step: 1
1037 13:59:42.253834
1038 13:59:42.257142 RX Delay -95 -> 252, step: 8
1039 13:59:42.257216
1040 13:59:42.260761 Set Vref, RX VrefLevel [Byte0]: 32
1041 13:59:42.263711 [Byte1]: 32
1042 13:59:42.263786
1043 13:59:42.267086 Set Vref, RX VrefLevel [Byte0]: 33
1044 13:59:42.270463 [Byte1]: 33
1045 13:59:42.273873
1046 13:59:42.273992 Set Vref, RX VrefLevel [Byte0]: 34
1047 13:59:42.277357 [Byte1]: 34
1048 13:59:42.281697
1049 13:59:42.281776 Set Vref, RX VrefLevel [Byte0]: 35
1050 13:59:42.284592 [Byte1]: 35
1051 13:59:42.289364
1052 13:59:42.289439 Set Vref, RX VrefLevel [Byte0]: 36
1053 13:59:42.292453 [Byte1]: 36
1054 13:59:42.296935
1055 13:59:42.297007 Set Vref, RX VrefLevel [Byte0]: 37
1056 13:59:42.299841 [Byte1]: 37
1057 13:59:42.304384
1058 13:59:42.304457 Set Vref, RX VrefLevel [Byte0]: 38
1059 13:59:42.307595 [Byte1]: 38
1060 13:59:42.311828
1061 13:59:42.311898 Set Vref, RX VrefLevel [Byte0]: 39
1062 13:59:42.315205 [Byte1]: 39
1063 13:59:42.320045
1064 13:59:42.320146 Set Vref, RX VrefLevel [Byte0]: 40
1065 13:59:42.323251 [Byte1]: 40
1066 13:59:42.327574
1067 13:59:42.327662 Set Vref, RX VrefLevel [Byte0]: 41
1068 13:59:42.330954 [Byte1]: 41
1069 13:59:42.334956
1070 13:59:42.335065 Set Vref, RX VrefLevel [Byte0]: 42
1071 13:59:42.338496 [Byte1]: 42
1072 13:59:42.342817
1073 13:59:42.342895 Set Vref, RX VrefLevel [Byte0]: 43
1074 13:59:42.346429 [Byte1]: 43
1075 13:59:42.350396
1076 13:59:42.350479 Set Vref, RX VrefLevel [Byte0]: 44
1077 13:59:42.353489 [Byte1]: 44
1078 13:59:42.357640
1079 13:59:42.357719 Set Vref, RX VrefLevel [Byte0]: 45
1080 13:59:42.360848 [Byte1]: 45
1081 13:59:42.365057
1082 13:59:42.365141 Set Vref, RX VrefLevel [Byte0]: 46
1083 13:59:42.368085 [Byte1]: 46
1084 13:59:42.372379
1085 13:59:42.372452 Set Vref, RX VrefLevel [Byte0]: 47
1086 13:59:42.376120 [Byte1]: 47
1087 13:59:42.380027
1088 13:59:42.380109 Set Vref, RX VrefLevel [Byte0]: 48
1089 13:59:42.383392 [Byte1]: 48
1090 13:59:42.387696
1091 13:59:42.387766 Set Vref, RX VrefLevel [Byte0]: 49
1092 13:59:42.391128 [Byte1]: 49
1093 13:59:42.395444
1094 13:59:42.395515 Set Vref, RX VrefLevel [Byte0]: 50
1095 13:59:42.398710 [Byte1]: 50
1096 13:59:42.403067
1097 13:59:42.403142 Set Vref, RX VrefLevel [Byte0]: 51
1098 13:59:42.406391 [Byte1]: 51
1099 13:59:42.410791
1100 13:59:42.410860 Set Vref, RX VrefLevel [Byte0]: 52
1101 13:59:42.414218 [Byte1]: 52
1102 13:59:42.418294
1103 13:59:42.418362 Set Vref, RX VrefLevel [Byte0]: 53
1104 13:59:42.421642 [Byte1]: 53
1105 13:59:42.426042
1106 13:59:42.426121 Set Vref, RX VrefLevel [Byte0]: 54
1107 13:59:42.428865 [Byte1]: 54
1108 13:59:42.433297
1109 13:59:42.433397 Set Vref, RX VrefLevel [Byte0]: 55
1110 13:59:42.436821 [Byte1]: 55
1111 13:59:42.440773
1112 13:59:42.440845 Set Vref, RX VrefLevel [Byte0]: 56
1113 13:59:42.444370 [Byte1]: 56
1114 13:59:42.448871
1115 13:59:42.448948 Set Vref, RX VrefLevel [Byte0]: 57
1116 13:59:42.451937 [Byte1]: 57
1117 13:59:42.456443
1118 13:59:42.456537 Set Vref, RX VrefLevel [Byte0]: 58
1119 13:59:42.459734 [Byte1]: 58
1120 13:59:42.463726
1121 13:59:42.463805 Set Vref, RX VrefLevel [Byte0]: 59
1122 13:59:42.467355 [Byte1]: 59
1123 13:59:42.471562
1124 13:59:42.471643 Set Vref, RX VrefLevel [Byte0]: 60
1125 13:59:42.474705 [Byte1]: 60
1126 13:59:42.479142
1127 13:59:42.479220 Set Vref, RX VrefLevel [Byte0]: 61
1128 13:59:42.482397 [Byte1]: 61
1129 13:59:42.486781
1130 13:59:42.486859 Set Vref, RX VrefLevel [Byte0]: 62
1131 13:59:42.490110 [Byte1]: 62
1132 13:59:42.494029
1133 13:59:42.494096 Set Vref, RX VrefLevel [Byte0]: 63
1134 13:59:42.497317 [Byte1]: 63
1135 13:59:42.501801
1136 13:59:42.501869 Set Vref, RX VrefLevel [Byte0]: 64
1137 13:59:42.505274 [Byte1]: 64
1138 13:59:42.509202
1139 13:59:42.509275 Set Vref, RX VrefLevel [Byte0]: 65
1140 13:59:42.512543 [Byte1]: 65
1141 13:59:42.517230
1142 13:59:42.517300 Set Vref, RX VrefLevel [Byte0]: 66
1143 13:59:42.520187 [Byte1]: 66
1144 13:59:42.524510
1145 13:59:42.524581 Set Vref, RX VrefLevel [Byte0]: 67
1146 13:59:42.527777 [Byte1]: 67
1147 13:59:42.532023
1148 13:59:42.532093 Set Vref, RX VrefLevel [Byte0]: 68
1149 13:59:42.535377 [Byte1]: 68
1150 13:59:42.540062
1151 13:59:42.540139 Set Vref, RX VrefLevel [Byte0]: 69
1152 13:59:42.543265 [Byte1]: 69
1153 13:59:42.547376
1154 13:59:42.547452 Set Vref, RX VrefLevel [Byte0]: 70
1155 13:59:42.550785 [Byte1]: 70
1156 13:59:42.555029
1157 13:59:42.555098 Set Vref, RX VrefLevel [Byte0]: 71
1158 13:59:42.558538 [Byte1]: 71
1159 13:59:42.562658
1160 13:59:42.562733 Set Vref, RX VrefLevel [Byte0]: 72
1161 13:59:42.565860 [Byte1]: 72
1162 13:59:42.570061
1163 13:59:42.570134 Set Vref, RX VrefLevel [Byte0]: 73
1164 13:59:42.573383 [Byte1]: 73
1165 13:59:42.577849
1166 13:59:42.577956 Set Vref, RX VrefLevel [Byte0]: 74
1167 13:59:42.581315 [Byte1]: 74
1168 13:59:42.585483
1169 13:59:42.585552 Set Vref, RX VrefLevel [Byte0]: 75
1170 13:59:42.588770 [Byte1]: 75
1171 13:59:42.593076
1172 13:59:42.593144 Set Vref, RX VrefLevel [Byte0]: 76
1173 13:59:42.596321 [Byte1]: 76
1174 13:59:42.600580
1175 13:59:42.600653 Set Vref, RX VrefLevel [Byte0]: 77
1176 13:59:42.603851 [Byte1]: 77
1177 13:59:42.608484
1178 13:59:42.608552 Final RX Vref Byte 0 = 62 to rank0
1179 13:59:42.611519 Final RX Vref Byte 1 = 57 to rank0
1180 13:59:42.614880 Final RX Vref Byte 0 = 62 to rank1
1181 13:59:42.618057 Final RX Vref Byte 1 = 57 to rank1==
1182 13:59:42.621448 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 13:59:42.624669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 13:59:42.628109 ==
1185 13:59:42.628189 DQS Delay:
1186 13:59:42.628251 DQS0 = 0, DQS1 = 0
1187 13:59:42.631382 DQM Delay:
1188 13:59:42.631450 DQM0 = 93, DQM1 = 83
1189 13:59:42.634800 DQ Delay:
1190 13:59:42.638205 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1191 13:59:42.641620 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1192 13:59:42.641688 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1193 13:59:42.648259 DQ12 =84, DQ13 =84, DQ14 =96, DQ15 =88
1194 13:59:42.648346
1195 13:59:42.648412
1196 13:59:42.654882 [DQSOSCAuto] RK0, (LSB)MR18= 0x3833, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1197 13:59:42.658049 CH0 RK0: MR19=606, MR18=3833
1198 13:59:42.664713 CH0_RK0: MR19=0x606, MR18=0x3833, DQSOSC=395, MR23=63, INC=94, DEC=63
1199 13:59:42.664798
1200 13:59:42.668268 ----->DramcWriteLeveling(PI) begin...
1201 13:59:42.668353 ==
1202 13:59:42.671685 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 13:59:42.674813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 13:59:42.674898 ==
1205 13:59:42.678093 Write leveling (Byte 0): 31 => 31
1206 13:59:42.681655 Write leveling (Byte 1): 27 => 27
1207 13:59:42.684827 DramcWriteLeveling(PI) end<-----
1208 13:59:42.684910
1209 13:59:42.684976 ==
1210 13:59:42.688114 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 13:59:42.691439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 13:59:42.691523 ==
1213 13:59:42.694841 [Gating] SW mode calibration
1214 13:59:42.701667 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 13:59:42.708338 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 13:59:42.711688 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 13:59:42.715142 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1218 13:59:42.721440 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 13:59:42.724785 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 13:59:42.728095 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:59:42.772179 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:59:42.772711 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 13:59:42.772976 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:59:42.773070 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:59:42.773146 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:59:42.773704 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:59:42.773994 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:59:42.774413 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:59:42.774670 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:59:42.774741 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:59:42.816147 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 13:59:42.816420 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 13:59:42.816499 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1234 13:59:42.816767 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1235 13:59:42.816842 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 13:59:42.817159 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 13:59:42.817414 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 13:59:42.817670 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 13:59:42.817928 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:59:42.818039 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:59:42.841689 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1242 13:59:42.841989 0 9 8 | B1->B0 | 2a2a 3333 | 1 0 | (0 0) (0 0)
1243 13:59:42.842083 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 13:59:42.842628 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 13:59:42.842706 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 13:59:42.845530 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 13:59:42.848863 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 13:59:42.852240 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 13:59:42.855668 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1250 13:59:42.862008 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1251 13:59:42.865504 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 13:59:42.868882 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 13:59:42.875459 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 13:59:42.878806 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 13:59:42.882438 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 13:59:42.888952 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 13:59:42.892222 0 11 4 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
1258 13:59:42.895383 0 11 8 | B1->B0 | 3939 4545 | 1 0 | (0 0) (0 0)
1259 13:59:42.902060 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 13:59:42.905824 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 13:59:42.909207 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 13:59:42.912989 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 13:59:42.916342 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 13:59:42.923743 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 13:59:42.926970 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1266 13:59:42.930301 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1267 13:59:42.934229 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 13:59:42.941494 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 13:59:42.944459 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 13:59:42.947769 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 13:59:42.954596 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 13:59:42.957972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 13:59:42.961286 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 13:59:42.968169 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 13:59:42.971282 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 13:59:42.974626 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 13:59:42.981270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 13:59:42.984643 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 13:59:42.987918 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 13:59:42.991175 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 13:59:42.998306 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1282 13:59:43.001455 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 13:59:43.004561 Total UI for P1: 0, mck2ui 16
1284 13:59:43.008070 best dqsien dly found for B0: ( 0, 14, 4)
1285 13:59:43.011345 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 13:59:43.014661 Total UI for P1: 0, mck2ui 16
1287 13:59:43.018031 best dqsien dly found for B1: ( 0, 14, 6)
1288 13:59:43.021430 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1289 13:59:43.024811 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1290 13:59:43.024889
1291 13:59:43.031516 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 13:59:43.034875 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1293 13:59:43.034951 [Gating] SW calibration Done
1294 13:59:43.038208 ==
1295 13:59:43.041495 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 13:59:43.044944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 13:59:43.045018 ==
1298 13:59:43.045081 RX Vref Scan: 0
1299 13:59:43.045142
1300 13:59:43.048150 RX Vref 0 -> 0, step: 1
1301 13:59:43.048246
1302 13:59:43.051371 RX Delay -130 -> 252, step: 16
1303 13:59:43.054756 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1304 13:59:43.058100 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1305 13:59:43.064449 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1306 13:59:43.067806 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1307 13:59:43.071269 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1308 13:59:43.074394 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1309 13:59:43.077854 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1310 13:59:43.084433 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1311 13:59:43.087892 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1312 13:59:43.091381 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1313 13:59:43.094418 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1314 13:59:43.097672 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1315 13:59:43.104655 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1316 13:59:43.107833 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1317 13:59:43.111340 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1318 13:59:43.114520 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1319 13:59:43.114603 ==
1320 13:59:43.117828 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 13:59:43.124685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 13:59:43.124769 ==
1323 13:59:43.124835 DQS Delay:
1324 13:59:43.124897 DQS0 = 0, DQS1 = 0
1325 13:59:43.128123 DQM Delay:
1326 13:59:43.128206 DQM0 = 89, DQM1 = 80
1327 13:59:43.131466 DQ Delay:
1328 13:59:43.134702 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1329 13:59:43.137687 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1330 13:59:43.137770 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1331 13:59:43.144463 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1332 13:59:43.144548
1333 13:59:43.144615
1334 13:59:43.144677 ==
1335 13:59:43.148174 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 13:59:43.151049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 13:59:43.151134 ==
1338 13:59:43.151201
1339 13:59:43.151264
1340 13:59:43.154375 TX Vref Scan disable
1341 13:59:43.154459 == TX Byte 0 ==
1342 13:59:43.161266 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1343 13:59:43.164634 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1344 13:59:43.164718 == TX Byte 1 ==
1345 13:59:43.171633 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1346 13:59:43.174542 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1347 13:59:43.174626 ==
1348 13:59:43.178072 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 13:59:43.181147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 13:59:43.181231 ==
1351 13:59:43.195422 TX Vref=22, minBit 1, minWin=27, winSum=443
1352 13:59:43.198868 TX Vref=24, minBit 8, minWin=27, winSum=451
1353 13:59:43.202104 TX Vref=26, minBit 14, minWin=27, winSum=454
1354 13:59:43.205435 TX Vref=28, minBit 10, minWin=27, winSum=454
1355 13:59:43.208838 TX Vref=30, minBit 8, minWin=28, winSum=458
1356 13:59:43.215630 TX Vref=32, minBit 8, minWin=28, winSum=459
1357 13:59:43.218625 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32
1358 13:59:43.218709
1359 13:59:43.221967 Final TX Range 1 Vref 32
1360 13:59:43.222091
1361 13:59:43.222171 ==
1362 13:59:43.225227 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 13:59:43.228701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 13:59:43.228790 ==
1365 13:59:43.232045
1366 13:59:43.232126
1367 13:59:43.232190 TX Vref Scan disable
1368 13:59:43.235434 == TX Byte 0 ==
1369 13:59:43.238789 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1370 13:59:43.242150 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1371 13:59:43.245576 == TX Byte 1 ==
1372 13:59:43.249000 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1373 13:59:43.252309 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1374 13:59:43.255673
1375 13:59:43.255754 [DATLAT]
1376 13:59:43.255819 Freq=800, CH0 RK1
1377 13:59:43.255879
1378 13:59:43.258940 DATLAT Default: 0xa
1379 13:59:43.259021 0, 0xFFFF, sum = 0
1380 13:59:43.262314 1, 0xFFFF, sum = 0
1381 13:59:43.262397 2, 0xFFFF, sum = 0
1382 13:59:43.265692 3, 0xFFFF, sum = 0
1383 13:59:43.265775 4, 0xFFFF, sum = 0
1384 13:59:43.268959 5, 0xFFFF, sum = 0
1385 13:59:43.269042 6, 0xFFFF, sum = 0
1386 13:59:43.272287 7, 0xFFFF, sum = 0
1387 13:59:43.275831 8, 0xFFFF, sum = 0
1388 13:59:43.275913 9, 0x0, sum = 1
1389 13:59:43.276005 10, 0x0, sum = 2
1390 13:59:43.278762 11, 0x0, sum = 3
1391 13:59:43.278847 12, 0x0, sum = 4
1392 13:59:43.282312 best_step = 10
1393 13:59:43.282393
1394 13:59:43.282457 ==
1395 13:59:43.285867 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 13:59:43.288845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 13:59:43.288927 ==
1398 13:59:43.292364 RX Vref Scan: 0
1399 13:59:43.292446
1400 13:59:43.292509 RX Vref 0 -> 0, step: 1
1401 13:59:43.292570
1402 13:59:43.295453 RX Delay -79 -> 252, step: 8
1403 13:59:43.302123 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1404 13:59:43.305532 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1405 13:59:43.308834 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1406 13:59:43.312632 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1407 13:59:43.315854 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1408 13:59:43.322562 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1409 13:59:43.325537 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1410 13:59:43.329176 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1411 13:59:43.332562 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1412 13:59:43.335924 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1413 13:59:43.342641 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1414 13:59:43.345597 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1415 13:59:43.348892 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1416 13:59:43.352124 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1417 13:59:43.355688 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1418 13:59:43.362434 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1419 13:59:43.362516 ==
1420 13:59:43.365730 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 13:59:43.369281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 13:59:43.369363 ==
1423 13:59:43.369428 DQS Delay:
1424 13:59:43.372644 DQS0 = 0, DQS1 = 0
1425 13:59:43.372726 DQM Delay:
1426 13:59:43.375949 DQM0 = 91, DQM1 = 82
1427 13:59:43.376031 DQ Delay:
1428 13:59:43.379285 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1429 13:59:43.382663 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1430 13:59:43.385884 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1431 13:59:43.389206 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1432 13:59:43.389287
1433 13:59:43.389351
1434 13:59:43.395741 [DQSOSCAuto] RK1, (LSB)MR18= 0x421b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1435 13:59:43.399287 CH0 RK1: MR19=606, MR18=421B
1436 13:59:43.406007 CH0_RK1: MR19=0x606, MR18=0x421B, DQSOSC=393, MR23=63, INC=95, DEC=63
1437 13:59:43.409292 [RxdqsGatingPostProcess] freq 800
1438 13:59:43.415886 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 13:59:43.419014 Pre-setting of DQS Precalculation
1440 13:59:43.422505 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 13:59:43.422587 ==
1442 13:59:43.426032 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 13:59:43.429169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 13:59:43.429252 ==
1445 13:59:43.435691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 13:59:43.442340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 13:59:43.450919 [CA 0] Center 36 (6~67) winsize 62
1448 13:59:43.453984 [CA 1] Center 36 (6~67) winsize 62
1449 13:59:43.457551 [CA 2] Center 34 (4~65) winsize 62
1450 13:59:43.460866 [CA 3] Center 34 (3~65) winsize 63
1451 13:59:43.464161 [CA 4] Center 34 (4~65) winsize 62
1452 13:59:43.467521 [CA 5] Center 33 (3~64) winsize 62
1453 13:59:43.467603
1454 13:59:43.470813 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1455 13:59:43.470894
1456 13:59:43.474159 [CATrainingPosCal] consider 1 rank data
1457 13:59:43.477509 u2DelayCellTimex100 = 270/100 ps
1458 13:59:43.480779 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1459 13:59:43.484347 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1460 13:59:43.491090 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 13:59:43.494106 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1462 13:59:43.497568 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 13:59:43.500690 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 13:59:43.500771
1465 13:59:43.504139 CA PerBit enable=1, Macro0, CA PI delay=33
1466 13:59:43.504221
1467 13:59:43.507397 [CBTSetCACLKResult] CA Dly = 33
1468 13:59:43.507478 CS Dly: 5 (0~36)
1469 13:59:43.507543 ==
1470 13:59:43.510356 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 13:59:43.517304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 13:59:43.517386 ==
1473 13:59:43.520555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 13:59:43.527130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 13:59:43.536767 [CA 0] Center 36 (6~67) winsize 62
1476 13:59:43.539913 [CA 1] Center 36 (6~67) winsize 62
1477 13:59:43.543292 [CA 2] Center 35 (5~66) winsize 62
1478 13:59:43.547054 [CA 3] Center 34 (4~65) winsize 62
1479 13:59:43.550391 [CA 4] Center 34 (4~65) winsize 62
1480 13:59:43.553593 [CA 5] Center 34 (3~65) winsize 63
1481 13:59:43.553675
1482 13:59:43.556888 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1483 13:59:43.556970
1484 13:59:43.560387 [CATrainingPosCal] consider 2 rank data
1485 13:59:43.563320 u2DelayCellTimex100 = 270/100 ps
1486 13:59:43.566645 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1487 13:59:43.570495 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1488 13:59:43.573713 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1489 13:59:43.580605 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1490 13:59:43.584421 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1491 13:59:43.588276 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 13:59:43.588358
1493 13:59:43.591768 CA PerBit enable=1, Macro0, CA PI delay=33
1494 13:59:43.591851
1495 13:59:43.591915 [CBTSetCACLKResult] CA Dly = 33
1496 13:59:43.595500 CS Dly: 5 (0~37)
1497 13:59:43.595581
1498 13:59:43.599194 ----->DramcWriteLeveling(PI) begin...
1499 13:59:43.599278 ==
1500 13:59:43.602715 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 13:59:43.606756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 13:59:43.606842 ==
1503 13:59:43.610096 Write leveling (Byte 0): 25 => 25
1504 13:59:43.613658 Write leveling (Byte 1): 31 => 31
1505 13:59:43.613745 DramcWriteLeveling(PI) end<-----
1506 13:59:43.617088
1507 13:59:43.617171 ==
1508 13:59:43.620280 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 13:59:43.623796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 13:59:43.623906 ==
1511 13:59:43.626811 [Gating] SW mode calibration
1512 13:59:43.633886 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 13:59:43.637088 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 13:59:43.643683 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1515 13:59:43.646979 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1516 13:59:43.650643 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 13:59:43.657482 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:59:43.660648 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:59:43.664016 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:59:43.670243 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:59:43.673580 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:59:43.676905 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:59:43.683674 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:59:43.687008 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:59:43.690359 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:59:43.697086 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:59:43.700508 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:59:43.703782 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:59:43.707010 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:59:43.713590 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 13:59:43.716991 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1532 13:59:43.720220 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:59:43.726844 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 13:59:43.730294 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 13:59:43.733998 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:59:43.740366 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 13:59:43.743984 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:59:43.747035 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:59:43.753810 0 9 4 | B1->B0 | 2525 2d2d | 1 1 | (1 1) (1 1)
1540 13:59:43.757248 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1541 13:59:43.760519 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 13:59:43.766979 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 13:59:43.770321 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 13:59:43.773579 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 13:59:43.780326 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 13:59:43.783613 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 13:59:43.787078 0 10 4 | B1->B0 | 2727 2929 | 0 0 | (1 0) (0 0)
1548 13:59:43.790352 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 13:59:43.797095 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 13:59:43.800433 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 13:59:43.803738 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 13:59:43.810340 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 13:59:43.814285 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 13:59:43.816954 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 13:59:43.823863 0 11 4 | B1->B0 | 2828 3232 | 0 0 | (0 0) (1 1)
1556 13:59:43.826935 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1557 13:59:43.830453 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 13:59:43.837042 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 13:59:43.840615 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 13:59:43.844033 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 13:59:43.850479 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 13:59:43.854038 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 13:59:43.857068 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1564 13:59:43.863543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1565 13:59:43.867294 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 13:59:43.870282 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 13:59:43.876967 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 13:59:43.880277 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 13:59:43.883715 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 13:59:43.887028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 13:59:43.893645 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 13:59:43.897050 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 13:59:43.900355 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 13:59:43.907504 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 13:59:43.910319 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 13:59:43.913652 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 13:59:43.920574 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 13:59:43.923967 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 13:59:43.927017 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1580 13:59:43.933709 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 13:59:43.933793 Total UI for P1: 0, mck2ui 16
1582 13:59:43.940729 best dqsien dly found for B0: ( 0, 14, 4)
1583 13:59:43.940813 Total UI for P1: 0, mck2ui 16
1584 13:59:43.947156 best dqsien dly found for B1: ( 0, 14, 4)
1585 13:59:43.950546 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1586 13:59:43.954022 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1587 13:59:43.954118
1588 13:59:43.957300 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 13:59:43.960723 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1590 13:59:43.963877 [Gating] SW calibration Done
1591 13:59:43.964054 ==
1592 13:59:43.967413 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 13:59:43.970907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 13:59:43.971116 ==
1595 13:59:43.974244 RX Vref Scan: 0
1596 13:59:43.974432
1597 13:59:43.974553 RX Vref 0 -> 0, step: 1
1598 13:59:43.974663
1599 13:59:43.977631 RX Delay -130 -> 252, step: 16
1600 13:59:43.981231 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1601 13:59:43.984234 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1602 13:59:43.990783 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1603 13:59:43.994153 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1604 13:59:43.997507 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1605 13:59:44.001017 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1606 13:59:44.004584 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1607 13:59:44.011398 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1608 13:59:44.014762 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1609 13:59:44.018179 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1610 13:59:44.021263 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1611 13:59:44.024951 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1612 13:59:44.031012 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1613 13:59:44.034382 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1614 13:59:44.037882 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1615 13:59:44.041211 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1616 13:59:44.041789 ==
1617 13:59:44.044401 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 13:59:44.051357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 13:59:44.051930 ==
1620 13:59:44.052311 DQS Delay:
1621 13:59:44.054508 DQS0 = 0, DQS1 = 0
1622 13:59:44.054980 DQM Delay:
1623 13:59:44.055358 DQM0 = 91, DQM1 = 85
1624 13:59:44.058129 DQ Delay:
1625 13:59:44.061162 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1626 13:59:44.064420 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1627 13:59:44.067898 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1628 13:59:44.071317 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1629 13:59:44.071790
1630 13:59:44.072167
1631 13:59:44.072515 ==
1632 13:59:44.074488 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 13:59:44.078107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 13:59:44.078687 ==
1635 13:59:44.079070
1636 13:59:44.079422
1637 13:59:44.081452 TX Vref Scan disable
1638 13:59:44.082081 == TX Byte 0 ==
1639 13:59:44.087929 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1640 13:59:44.091508 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1641 13:59:44.092091 == TX Byte 1 ==
1642 13:59:44.098328 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1643 13:59:44.101638 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1644 13:59:44.102275 ==
1645 13:59:44.104798 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 13:59:44.107930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 13:59:44.108412 ==
1648 13:59:44.122385 TX Vref=22, minBit 15, minWin=26, winSum=447
1649 13:59:44.125593 TX Vref=24, minBit 15, minWin=27, winSum=452
1650 13:59:44.129084 TX Vref=26, minBit 15, minWin=27, winSum=457
1651 13:59:44.132719 TX Vref=28, minBit 8, minWin=27, winSum=455
1652 13:59:44.136038 TX Vref=30, minBit 9, minWin=27, winSum=457
1653 13:59:44.142464 TX Vref=32, minBit 12, minWin=27, winSum=456
1654 13:59:44.146050 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 26
1655 13:59:44.146637
1656 13:59:44.149125 Final TX Range 1 Vref 26
1657 13:59:44.149714
1658 13:59:44.150138 ==
1659 13:59:44.152383 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 13:59:44.156542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 13:59:44.157127 ==
1662 13:59:44.157513
1663 13:59:44.157864
1664 13:59:44.160222 TX Vref Scan disable
1665 13:59:44.163326 == TX Byte 0 ==
1666 13:59:44.166359 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1667 13:59:44.169842 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1668 13:59:44.173436 == TX Byte 1 ==
1669 13:59:44.176392 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1670 13:59:44.179829 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1671 13:59:44.180314
1672 13:59:44.183237 [DATLAT]
1673 13:59:44.183717 Freq=800, CH1 RK0
1674 13:59:44.184193
1675 13:59:44.186561 DATLAT Default: 0xa
1676 13:59:44.187044 0, 0xFFFF, sum = 0
1677 13:59:44.189997 1, 0xFFFF, sum = 0
1678 13:59:44.190491 2, 0xFFFF, sum = 0
1679 13:59:44.193377 3, 0xFFFF, sum = 0
1680 13:59:44.193867 4, 0xFFFF, sum = 0
1681 13:59:44.196862 5, 0xFFFF, sum = 0
1682 13:59:44.197453 6, 0xFFFF, sum = 0
1683 13:59:44.200027 7, 0xFFFF, sum = 0
1684 13:59:44.200513 8, 0xFFFF, sum = 0
1685 13:59:44.203562 9, 0x0, sum = 1
1686 13:59:44.204149 10, 0x0, sum = 2
1687 13:59:44.206765 11, 0x0, sum = 3
1688 13:59:44.207258 12, 0x0, sum = 4
1689 13:59:44.210055 best_step = 10
1690 13:59:44.210534
1691 13:59:44.211008 ==
1692 13:59:44.213634 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 13:59:44.217063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 13:59:44.217649 ==
1695 13:59:44.220366 RX Vref Scan: 1
1696 13:59:44.220966
1697 13:59:44.221450 Set Vref Range= 32 -> 127
1698 13:59:44.221901
1699 13:59:44.223649 RX Vref 32 -> 127, step: 1
1700 13:59:44.224228
1701 13:59:44.226935 RX Delay -95 -> 252, step: 8
1702 13:59:44.227518
1703 13:59:44.230395 Set Vref, RX VrefLevel [Byte0]: 32
1704 13:59:44.233647 [Byte1]: 32
1705 13:59:44.234260
1706 13:59:44.236924 Set Vref, RX VrefLevel [Byte0]: 33
1707 13:59:44.240160 [Byte1]: 33
1708 13:59:44.240667
1709 13:59:44.243442 Set Vref, RX VrefLevel [Byte0]: 34
1710 13:59:44.246785 [Byte1]: 34
1711 13:59:44.250829
1712 13:59:44.251399 Set Vref, RX VrefLevel [Byte0]: 35
1713 13:59:44.253901 [Byte1]: 35
1714 13:59:44.258303
1715 13:59:44.258909 Set Vref, RX VrefLevel [Byte0]: 36
1716 13:59:44.261804 [Byte1]: 36
1717 13:59:44.266132
1718 13:59:44.266868 Set Vref, RX VrefLevel [Byte0]: 37
1719 13:59:44.269363 [Byte1]: 37
1720 13:59:44.273667
1721 13:59:44.274249 Set Vref, RX VrefLevel [Byte0]: 38
1722 13:59:44.276907 [Byte1]: 38
1723 13:59:44.281195
1724 13:59:44.281918 Set Vref, RX VrefLevel [Byte0]: 39
1725 13:59:44.284228 [Byte1]: 39
1726 13:59:44.288639
1727 13:59:44.289201 Set Vref, RX VrefLevel [Byte0]: 40
1728 13:59:44.292299 [Byte1]: 40
1729 13:59:44.296527
1730 13:59:44.297100 Set Vref, RX VrefLevel [Byte0]: 41
1731 13:59:44.299974 [Byte1]: 41
1732 13:59:44.304307
1733 13:59:44.304878 Set Vref, RX VrefLevel [Byte0]: 42
1734 13:59:44.307272 [Byte1]: 42
1735 13:59:44.311811
1736 13:59:44.312379 Set Vref, RX VrefLevel [Byte0]: 43
1737 13:59:44.315192 [Byte1]: 43
1738 13:59:44.319216
1739 13:59:44.319782 Set Vref, RX VrefLevel [Byte0]: 44
1740 13:59:44.322525 [Byte1]: 44
1741 13:59:44.326925
1742 13:59:44.327499 Set Vref, RX VrefLevel [Byte0]: 45
1743 13:59:44.330458 [Byte1]: 45
1744 13:59:44.334165
1745 13:59:44.334737 Set Vref, RX VrefLevel [Byte0]: 46
1746 13:59:44.338073 [Byte1]: 46
1747 13:59:44.342094
1748 13:59:44.342665 Set Vref, RX VrefLevel [Byte0]: 47
1749 13:59:44.345180 [Byte1]: 47
1750 13:59:44.349785
1751 13:59:44.350437 Set Vref, RX VrefLevel [Byte0]: 48
1752 13:59:44.352970 [Byte1]: 48
1753 13:59:44.357303
1754 13:59:44.357778 Set Vref, RX VrefLevel [Byte0]: 49
1755 13:59:44.360773 [Byte1]: 49
1756 13:59:44.365058
1757 13:59:44.365656 Set Vref, RX VrefLevel [Byte0]: 50
1758 13:59:44.367841 [Byte1]: 50
1759 13:59:44.372572
1760 13:59:44.373146 Set Vref, RX VrefLevel [Byte0]: 51
1761 13:59:44.375488 [Byte1]: 51
1762 13:59:44.379785
1763 13:59:44.380358 Set Vref, RX VrefLevel [Byte0]: 52
1764 13:59:44.383432 [Byte1]: 52
1765 13:59:44.387469
1766 13:59:44.387933 Set Vref, RX VrefLevel [Byte0]: 53
1767 13:59:44.390572 [Byte1]: 53
1768 13:59:44.395245
1769 13:59:44.395839 Set Vref, RX VrefLevel [Byte0]: 54
1770 13:59:44.398508 [Byte1]: 54
1771 13:59:44.402876
1772 13:59:44.403459 Set Vref, RX VrefLevel [Byte0]: 55
1773 13:59:44.405715 [Byte1]: 55
1774 13:59:44.410664
1775 13:59:44.411247 Set Vref, RX VrefLevel [Byte0]: 56
1776 13:59:44.414061 [Byte1]: 56
1777 13:59:44.418292
1778 13:59:44.418876 Set Vref, RX VrefLevel [Byte0]: 57
1779 13:59:44.420950 [Byte1]: 57
1780 13:59:44.425448
1781 13:59:44.426069 Set Vref, RX VrefLevel [Byte0]: 58
1782 13:59:44.428822 [Byte1]: 58
1783 13:59:44.433195
1784 13:59:44.433773 Set Vref, RX VrefLevel [Byte0]: 59
1785 13:59:44.436714 [Byte1]: 59
1786 13:59:44.440928
1787 13:59:44.441508 Set Vref, RX VrefLevel [Byte0]: 60
1788 13:59:44.444354 [Byte1]: 60
1789 13:59:44.448221
1790 13:59:44.448800 Set Vref, RX VrefLevel [Byte0]: 61
1791 13:59:44.451354 [Byte1]: 61
1792 13:59:44.456345
1793 13:59:44.456940 Set Vref, RX VrefLevel [Byte0]: 62
1794 13:59:44.458885 [Byte1]: 62
1795 13:59:44.463654
1796 13:59:44.464231 Set Vref, RX VrefLevel [Byte0]: 63
1797 13:59:44.466582 [Byte1]: 63
1798 13:59:44.471023
1799 13:59:44.471493 Set Vref, RX VrefLevel [Byte0]: 64
1800 13:59:44.474491 [Byte1]: 64
1801 13:59:44.478887
1802 13:59:44.479473 Set Vref, RX VrefLevel [Byte0]: 65
1803 13:59:44.481790 [Byte1]: 65
1804 13:59:44.486156
1805 13:59:44.486736 Set Vref, RX VrefLevel [Byte0]: 66
1806 13:59:44.489380 [Byte1]: 66
1807 13:59:44.494062
1808 13:59:44.494639 Set Vref, RX VrefLevel [Byte0]: 67
1809 13:59:44.497172 [Byte1]: 67
1810 13:59:44.501456
1811 13:59:44.501928 Set Vref, RX VrefLevel [Byte0]: 68
1812 13:59:44.504919 [Byte1]: 68
1813 13:59:44.509329
1814 13:59:44.509908 Set Vref, RX VrefLevel [Byte0]: 69
1815 13:59:44.512780 [Byte1]: 69
1816 13:59:44.516975
1817 13:59:44.517552 Set Vref, RX VrefLevel [Byte0]: 70
1818 13:59:44.520239 [Byte1]: 70
1819 13:59:44.524290
1820 13:59:44.524768 Set Vref, RX VrefLevel [Byte0]: 71
1821 13:59:44.527883 [Byte1]: 71
1822 13:59:44.531747
1823 13:59:44.532331 Set Vref, RX VrefLevel [Byte0]: 72
1824 13:59:44.534914 [Byte1]: 72
1825 13:59:44.539345
1826 13:59:44.539975 Set Vref, RX VrefLevel [Byte0]: 73
1827 13:59:44.542569 [Byte1]: 73
1828 13:59:44.547049
1829 13:59:44.547628 Set Vref, RX VrefLevel [Byte0]: 74
1830 13:59:44.550241 [Byte1]: 74
1831 13:59:44.554826
1832 13:59:44.555409 Set Vref, RX VrefLevel [Byte0]: 75
1833 13:59:44.557896 [Byte1]: 75
1834 13:59:44.562332
1835 13:59:44.562912 Set Vref, RX VrefLevel [Byte0]: 76
1836 13:59:44.565281 [Byte1]: 76
1837 13:59:44.569735
1838 13:59:44.570419 Set Vref, RX VrefLevel [Byte0]: 77
1839 13:59:44.573174 [Byte1]: 77
1840 13:59:44.577195
1841 13:59:44.577675 Final RX Vref Byte 0 = 49 to rank0
1842 13:59:44.580959 Final RX Vref Byte 1 = 63 to rank0
1843 13:59:44.584059 Final RX Vref Byte 0 = 49 to rank1
1844 13:59:44.587411 Final RX Vref Byte 1 = 63 to rank1==
1845 13:59:44.590851 Dram Type= 6, Freq= 0, CH_1, rank 0
1846 13:59:44.593992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 13:59:44.597684 ==
1848 13:59:44.598245 DQS Delay:
1849 13:59:44.598625 DQS0 = 0, DQS1 = 0
1850 13:59:44.600823 DQM Delay:
1851 13:59:44.601294 DQM0 = 91, DQM1 = 83
1852 13:59:44.604031 DQ Delay:
1853 13:59:44.607366 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1854 13:59:44.607840 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1855 13:59:44.610840 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1856 13:59:44.614353 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1857 13:59:44.617360
1858 13:59:44.617829
1859 13:59:44.624369 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1860 13:59:44.627920 CH1 RK0: MR19=606, MR18=2F4D
1861 13:59:44.634238 CH1_RK0: MR19=0x606, MR18=0x2F4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1862 13:59:44.634799
1863 13:59:44.637773 ----->DramcWriteLeveling(PI) begin...
1864 13:59:44.638397 ==
1865 13:59:44.641188 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 13:59:44.644623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 13:59:44.645193 ==
1868 13:59:44.648004 Write leveling (Byte 0): 28 => 28
1869 13:59:44.651369 Write leveling (Byte 1): 29 => 29
1870 13:59:44.654620 DramcWriteLeveling(PI) end<-----
1871 13:59:44.655188
1872 13:59:44.655566 ==
1873 13:59:44.657767 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 13:59:44.660935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 13:59:44.661414 ==
1876 13:59:44.663985 [Gating] SW mode calibration
1877 13:59:44.670791 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1878 13:59:44.677544 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1879 13:59:44.681021 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1880 13:59:44.684227 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1881 13:59:44.691210 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:59:44.694578 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:59:44.697556 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 13:59:44.700757 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 13:59:44.707794 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 13:59:44.711132 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:59:44.714404 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 13:59:44.721320 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 13:59:44.724771 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 13:59:44.727785 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:59:44.734708 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 13:59:44.738048 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 13:59:44.741592 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 13:59:44.748267 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 13:59:44.751540 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1896 13:59:44.754861 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1897 13:59:44.761599 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1898 13:59:44.764991 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 13:59:44.768041 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 13:59:44.774851 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 13:59:44.777921 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 13:59:44.781185 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 13:59:44.787721 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 13:59:44.791206 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1905 13:59:44.794579 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1906 13:59:44.798053 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 13:59:44.804527 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 13:59:44.807700 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 13:59:44.811384 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 13:59:44.818232 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 13:59:44.821487 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 13:59:44.825124 0 10 4 | B1->B0 | 2e2e 3030 | 0 0 | (0 0) (0 0)
1913 13:59:44.831739 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 13:59:44.834982 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 13:59:44.838444 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 13:59:44.845249 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 13:59:44.848368 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 13:59:44.851273 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 13:59:44.858121 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 13:59:44.861464 0 11 4 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
1921 13:59:44.864883 0 11 8 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
1922 13:59:44.871626 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 13:59:44.874736 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 13:59:44.878301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 13:59:44.881649 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 13:59:44.888094 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 13:59:44.891692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 13:59:44.894424 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1929 13:59:44.901358 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1930 13:59:44.904858 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 13:59:44.907981 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 13:59:44.914880 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 13:59:44.917891 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 13:59:44.921258 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 13:59:44.928094 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 13:59:44.931455 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 13:59:44.934708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 13:59:44.941300 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 13:59:44.944589 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 13:59:44.947616 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 13:59:44.954409 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 13:59:44.957809 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 13:59:44.961135 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 13:59:44.967902 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1945 13:59:44.971478 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1946 13:59:44.974710 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 13:59:44.978267 Total UI for P1: 0, mck2ui 16
1948 13:59:44.981580 best dqsien dly found for B0: ( 0, 14, 6)
1949 13:59:44.984858 Total UI for P1: 0, mck2ui 16
1950 13:59:44.988186 best dqsien dly found for B1: ( 0, 14, 6)
1951 13:59:44.991291 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1952 13:59:44.994374 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1953 13:59:44.994843
1954 13:59:44.998226 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1955 13:59:45.001320 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1956 13:59:45.004550 [Gating] SW calibration Done
1957 13:59:45.005022 ==
1958 13:59:45.007805 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 13:59:45.014848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 13:59:45.015422 ==
1961 13:59:45.015800 RX Vref Scan: 0
1962 13:59:45.016150
1963 13:59:45.017745 RX Vref 0 -> 0, step: 1
1964 13:59:45.018236
1965 13:59:45.021200 RX Delay -130 -> 252, step: 16
1966 13:59:45.024577 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1967 13:59:45.027756 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1968 13:59:45.031432 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1969 13:59:45.034517 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1970 13:59:45.041366 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1971 13:59:45.044724 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1972 13:59:45.048019 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1973 13:59:45.051363 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1974 13:59:45.054610 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1975 13:59:45.061314 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1976 13:59:45.064596 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1977 13:59:45.068030 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1978 13:59:45.071570 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1979 13:59:45.074750 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1980 13:59:45.081748 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1981 13:59:45.085062 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1982 13:59:45.085628 ==
1983 13:59:45.088404 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 13:59:45.091687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 13:59:45.092256 ==
1986 13:59:45.094715 DQS Delay:
1987 13:59:45.095179 DQS0 = 0, DQS1 = 0
1988 13:59:45.095552 DQM Delay:
1989 13:59:45.098041 DQM0 = 88, DQM1 = 81
1990 13:59:45.098511 DQ Delay:
1991 13:59:45.101394 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1992 13:59:45.105218 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1993 13:59:45.108228 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1994 13:59:45.111229 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1995 13:59:45.111698
1996 13:59:45.112067
1997 13:59:45.112408 ==
1998 13:59:45.114526 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 13:59:45.121372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 13:59:45.121869 ==
2001 13:59:45.122296
2002 13:59:45.122650
2003 13:59:45.122986 TX Vref Scan disable
2004 13:59:45.124817 == TX Byte 0 ==
2005 13:59:45.128465 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2006 13:59:45.131563 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2007 13:59:45.134871 == TX Byte 1 ==
2008 13:59:45.138015 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2009 13:59:45.141650 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2010 13:59:45.145210 ==
2011 13:59:45.148491 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 13:59:45.151411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 13:59:45.151987 ==
2014 13:59:45.164341 TX Vref=22, minBit 13, minWin=27, winSum=452
2015 13:59:45.167201 TX Vref=24, minBit 13, minWin=27, winSum=454
2016 13:59:45.170301 TX Vref=26, minBit 7, minWin=28, winSum=456
2017 13:59:45.173991 TX Vref=28, minBit 13, minWin=27, winSum=456
2018 13:59:45.177216 TX Vref=30, minBit 9, minWin=27, winSum=459
2019 13:59:45.184119 TX Vref=32, minBit 9, minWin=27, winSum=457
2020 13:59:45.186977 [TxChooseVref] Worse bit 7, Min win 28, Win sum 456, Final Vref 26
2021 13:59:45.187451
2022 13:59:45.190386 Final TX Range 1 Vref 26
2023 13:59:45.190884
2024 13:59:45.191256 ==
2025 13:59:45.193797 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 13:59:45.196991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 13:59:45.197462 ==
2028 13:59:45.200247
2029 13:59:45.200713
2030 13:59:45.201089 TX Vref Scan disable
2031 13:59:45.203837 == TX Byte 0 ==
2032 13:59:45.207154 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2033 13:59:45.210486 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2034 13:59:45.213602 == TX Byte 1 ==
2035 13:59:45.217091 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2036 13:59:45.220493 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2037 13:59:45.223677
2038 13:59:45.224142 [DATLAT]
2039 13:59:45.224509 Freq=800, CH1 RK1
2040 13:59:45.224854
2041 13:59:45.227430 DATLAT Default: 0xa
2042 13:59:45.227997 0, 0xFFFF, sum = 0
2043 13:59:45.230659 1, 0xFFFF, sum = 0
2044 13:59:45.231135 2, 0xFFFF, sum = 0
2045 13:59:45.233914 3, 0xFFFF, sum = 0
2046 13:59:45.234551 4, 0xFFFF, sum = 0
2047 13:59:45.237150 5, 0xFFFF, sum = 0
2048 13:59:45.237627 6, 0xFFFF, sum = 0
2049 13:59:45.240539 7, 0xFFFF, sum = 0
2050 13:59:45.243756 8, 0xFFFF, sum = 0
2051 13:59:45.244235 9, 0x0, sum = 1
2052 13:59:45.244706 10, 0x0, sum = 2
2053 13:59:45.247295 11, 0x0, sum = 3
2054 13:59:45.247769 12, 0x0, sum = 4
2055 13:59:45.250461 best_step = 10
2056 13:59:45.250930
2057 13:59:45.251302 ==
2058 13:59:45.253879 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 13:59:45.257401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 13:59:45.258024 ==
2061 13:59:45.260619 RX Vref Scan: 0
2062 13:59:45.261189
2063 13:59:45.261565 RX Vref 0 -> 0, step: 1
2064 13:59:45.261915
2065 13:59:45.263751 RX Delay -79 -> 252, step: 8
2066 13:59:45.270841 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2067 13:59:45.273675 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2068 13:59:45.277276 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2069 13:59:45.280541 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2070 13:59:45.283652 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2071 13:59:45.290449 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2072 13:59:45.293871 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2073 13:59:45.297234 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2074 13:59:45.300602 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2075 13:59:45.304107 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2076 13:59:45.310863 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2077 13:59:45.314243 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2078 13:59:45.317293 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2079 13:59:45.320974 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2080 13:59:45.324252 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2081 13:59:45.330762 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2082 13:59:45.331237 ==
2083 13:59:45.334194 Dram Type= 6, Freq= 0, CH_1, rank 1
2084 13:59:45.337100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2085 13:59:45.337643 ==
2086 13:59:45.338080 DQS Delay:
2087 13:59:45.341026 DQS0 = 0, DQS1 = 0
2088 13:59:45.341627 DQM Delay:
2089 13:59:45.344094 DQM0 = 90, DQM1 = 84
2090 13:59:45.344793 DQ Delay:
2091 13:59:45.347445 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2092 13:59:45.350637 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2093 13:59:45.353782 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2094 13:59:45.357427 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
2095 13:59:45.357901
2096 13:59:45.358310
2097 13:59:45.364192 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2098 13:59:45.367501 CH1 RK1: MR19=606, MR18=3C11
2099 13:59:45.374163 CH1_RK1: MR19=0x606, MR18=0x3C11, DQSOSC=394, MR23=63, INC=95, DEC=63
2100 13:59:45.377525 [RxdqsGatingPostProcess] freq 800
2101 13:59:45.384080 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2102 13:59:45.384651 Pre-setting of DQS Precalculation
2103 13:59:45.390963 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2104 13:59:45.397141 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2105 13:59:45.404408 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2106 13:59:45.405013
2107 13:59:45.405389
2108 13:59:45.407522 [Calibration Summary] 1600 Mbps
2109 13:59:45.410580 CH 0, Rank 0
2110 13:59:45.411162 SW Impedance : PASS
2111 13:59:45.413932 DUTY Scan : NO K
2112 13:59:45.417577 ZQ Calibration : PASS
2113 13:59:45.418315 Jitter Meter : NO K
2114 13:59:45.420751 CBT Training : PASS
2115 13:59:45.421266 Write leveling : PASS
2116 13:59:45.424253 RX DQS gating : PASS
2117 13:59:45.427434 RX DQ/DQS(RDDQC) : PASS
2118 13:59:45.427908 TX DQ/DQS : PASS
2119 13:59:45.431220 RX DATLAT : PASS
2120 13:59:45.434325 RX DQ/DQS(Engine): PASS
2121 13:59:45.434902 TX OE : NO K
2122 13:59:45.437608 All Pass.
2123 13:59:45.438112
2124 13:59:45.438490 CH 0, Rank 1
2125 13:59:45.440663 SW Impedance : PASS
2126 13:59:45.441153 DUTY Scan : NO K
2127 13:59:45.444182 ZQ Calibration : PASS
2128 13:59:45.447537 Jitter Meter : NO K
2129 13:59:45.448050 CBT Training : PASS
2130 13:59:45.450733 Write leveling : PASS
2131 13:59:45.454269 RX DQS gating : PASS
2132 13:59:45.454741 RX DQ/DQS(RDDQC) : PASS
2133 13:59:45.457666 TX DQ/DQS : PASS
2134 13:59:45.458185 RX DATLAT : PASS
2135 13:59:45.462896 RX DQ/DQS(Engine): PASS
2136 13:59:45.464203 TX OE : NO K
2137 13:59:45.464674 All Pass.
2138 13:59:45.465044
2139 13:59:45.465386 CH 1, Rank 0
2140 13:59:45.467592 SW Impedance : PASS
2141 13:59:45.470913 DUTY Scan : NO K
2142 13:59:45.471383 ZQ Calibration : PASS
2143 13:59:45.474483 Jitter Meter : NO K
2144 13:59:45.477852 CBT Training : PASS
2145 13:59:45.478376 Write leveling : PASS
2146 13:59:45.481056 RX DQS gating : PASS
2147 13:59:45.484476 RX DQ/DQS(RDDQC) : PASS
2148 13:59:45.484970 TX DQ/DQS : PASS
2149 13:59:45.487823 RX DATLAT : PASS
2150 13:59:45.488295 RX DQ/DQS(Engine): PASS
2151 13:59:45.491260 TX OE : NO K
2152 13:59:45.491733 All Pass.
2153 13:59:45.492109
2154 13:59:45.494185 CH 1, Rank 1
2155 13:59:45.494649 SW Impedance : PASS
2156 13:59:45.497659 DUTY Scan : NO K
2157 13:59:45.501093 ZQ Calibration : PASS
2158 13:59:45.501631 Jitter Meter : NO K
2159 13:59:45.504381 CBT Training : PASS
2160 13:59:45.507582 Write leveling : PASS
2161 13:59:45.508068 RX DQS gating : PASS
2162 13:59:45.511118 RX DQ/DQS(RDDQC) : PASS
2163 13:59:45.514429 TX DQ/DQS : PASS
2164 13:59:45.514991 RX DATLAT : PASS
2165 13:59:45.517746 RX DQ/DQS(Engine): PASS
2166 13:59:45.521158 TX OE : NO K
2167 13:59:45.521703 All Pass.
2168 13:59:45.522124
2169 13:59:45.522479 DramC Write-DBI off
2170 13:59:45.524720 PER_BANK_REFRESH: Hybrid Mode
2171 13:59:45.527703 TX_TRACKING: ON
2172 13:59:45.531489 [GetDramInforAfterCalByMRR] Vendor 6.
2173 13:59:45.534411 [GetDramInforAfterCalByMRR] Revision 606.
2174 13:59:45.537532 [GetDramInforAfterCalByMRR] Revision 2 0.
2175 13:59:45.538034 MR0 0x3b3b
2176 13:59:45.541010 MR8 0x5151
2177 13:59:45.544489 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 13:59:45.544965
2179 13:59:45.545338 MR0 0x3b3b
2180 13:59:45.545689 MR8 0x5151
2181 13:59:45.547957 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 13:59:45.550898
2183 13:59:45.557832 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2184 13:59:45.561197 [FAST_K] Save calibration result to emmc
2185 13:59:45.564376 [FAST_K] Save calibration result to emmc
2186 13:59:45.567407 dram_init: config_dvfs: 1
2187 13:59:45.570965 dramc_set_vcore_voltage set vcore to 662500
2188 13:59:45.574270 Read voltage for 1200, 2
2189 13:59:45.574810 Vio18 = 0
2190 13:59:45.577746 Vcore = 662500
2191 13:59:45.578342 Vdram = 0
2192 13:59:45.578724 Vddq = 0
2193 13:59:45.579075 Vmddr = 0
2194 13:59:45.584336 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2195 13:59:45.591057 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2196 13:59:45.591598 MEM_TYPE=3, freq_sel=15
2197 13:59:45.594434 sv_algorithm_assistance_LP4_1600
2198 13:59:45.597919 ============ PULL DRAM RESETB DOWN ============
2199 13:59:45.604482 ========== PULL DRAM RESETB DOWN end =========
2200 13:59:45.607836 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 13:59:45.611367 ===================================
2202 13:59:45.614401 LPDDR4 DRAM CONFIGURATION
2203 13:59:45.618149 ===================================
2204 13:59:45.618716 EX_ROW_EN[0] = 0x0
2205 13:59:45.621312 EX_ROW_EN[1] = 0x0
2206 13:59:45.621874 LP4Y_EN = 0x0
2207 13:59:45.624572 WORK_FSP = 0x0
2208 13:59:45.625041 WL = 0x4
2209 13:59:45.627731 RL = 0x4
2210 13:59:45.628203 BL = 0x2
2211 13:59:45.631366 RPST = 0x0
2212 13:59:45.631940 RD_PRE = 0x0
2213 13:59:45.634490 WR_PRE = 0x1
2214 13:59:45.634985 WR_PST = 0x0
2215 13:59:45.637814 DBI_WR = 0x0
2216 13:59:45.641053 DBI_RD = 0x0
2217 13:59:45.641525 OTF = 0x1
2218 13:59:45.644409 ===================================
2219 13:59:45.647711 ===================================
2220 13:59:45.648182 ANA top config
2221 13:59:45.651117 ===================================
2222 13:59:45.654507 DLL_ASYNC_EN = 0
2223 13:59:45.657603 ALL_SLAVE_EN = 0
2224 13:59:45.661026 NEW_RANK_MODE = 1
2225 13:59:45.661502 DLL_IDLE_MODE = 1
2226 13:59:45.664526 LP45_APHY_COMB_EN = 1
2227 13:59:45.667830 TX_ODT_DIS = 1
2228 13:59:45.671155 NEW_8X_MODE = 1
2229 13:59:45.674299 ===================================
2230 13:59:45.677983 ===================================
2231 13:59:45.681536 data_rate = 2400
2232 13:59:45.682150 CKR = 1
2233 13:59:45.684736 DQ_P2S_RATIO = 8
2234 13:59:45.687915 ===================================
2235 13:59:45.691613 CA_P2S_RATIO = 8
2236 13:59:45.694315 DQ_CA_OPEN = 0
2237 13:59:45.698006 DQ_SEMI_OPEN = 0
2238 13:59:45.701059 CA_SEMI_OPEN = 0
2239 13:59:45.701532 CA_FULL_RATE = 0
2240 13:59:45.704656 DQ_CKDIV4_EN = 0
2241 13:59:45.707758 CA_CKDIV4_EN = 0
2242 13:59:45.711154 CA_PREDIV_EN = 0
2243 13:59:45.714865 PH8_DLY = 17
2244 13:59:45.718099 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2245 13:59:45.718663 DQ_AAMCK_DIV = 4
2246 13:59:45.721433 CA_AAMCK_DIV = 4
2247 13:59:45.724379 CA_ADMCK_DIV = 4
2248 13:59:45.727985 DQ_TRACK_CA_EN = 0
2249 13:59:45.731273 CA_PICK = 1200
2250 13:59:45.734679 CA_MCKIO = 1200
2251 13:59:45.737971 MCKIO_SEMI = 0
2252 13:59:45.738551 PLL_FREQ = 2366
2253 13:59:45.741034 DQ_UI_PI_RATIO = 32
2254 13:59:45.744201 CA_UI_PI_RATIO = 0
2255 13:59:45.747876 ===================================
2256 13:59:45.750992 ===================================
2257 13:59:45.754324 memory_type:LPDDR4
2258 13:59:45.754801 GP_NUM : 10
2259 13:59:45.757908 SRAM_EN : 1
2260 13:59:45.761360 MD32_EN : 0
2261 13:59:45.764521 ===================================
2262 13:59:45.765080 [ANA_INIT] >>>>>>>>>>>>>>
2263 13:59:45.767885 <<<<<< [CONFIGURE PHASE]: ANA_TX
2264 13:59:45.771177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2265 13:59:45.774621 ===================================
2266 13:59:45.777869 data_rate = 2400,PCW = 0X5b00
2267 13:59:45.781082 ===================================
2268 13:59:45.784540 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2269 13:59:45.791099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 13:59:45.794512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 13:59:45.801154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2272 13:59:45.804502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2273 13:59:45.807917 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2274 13:59:45.808403 [ANA_INIT] flow start
2275 13:59:45.811130 [ANA_INIT] PLL >>>>>>>>
2276 13:59:45.814592 [ANA_INIT] PLL <<<<<<<<
2277 13:59:45.815165 [ANA_INIT] MIDPI >>>>>>>>
2278 13:59:45.817866 [ANA_INIT] MIDPI <<<<<<<<
2279 13:59:45.821554 [ANA_INIT] DLL >>>>>>>>
2280 13:59:45.824814 [ANA_INIT] DLL <<<<<<<<
2281 13:59:45.825301 [ANA_INIT] flow end
2282 13:59:45.828138 ============ LP4 DIFF to SE enter ============
2283 13:59:45.834808 ============ LP4 DIFF to SE exit ============
2284 13:59:45.835386 [ANA_INIT] <<<<<<<<<<<<<
2285 13:59:45.838112 [Flow] Enable top DCM control >>>>>
2286 13:59:45.841471 [Flow] Enable top DCM control <<<<<
2287 13:59:45.845169 Enable DLL master slave shuffle
2288 13:59:45.851417 ==============================================================
2289 13:59:45.852001 Gating Mode config
2290 13:59:45.858139 ==============================================================
2291 13:59:45.861242 Config description:
2292 13:59:45.867943 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2293 13:59:45.874902 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2294 13:59:45.881258 SELPH_MODE 0: By rank 1: By Phase
2295 13:59:45.884618 ==============================================================
2296 13:59:45.887900 GAT_TRACK_EN = 1
2297 13:59:45.891309 RX_GATING_MODE = 2
2298 13:59:45.894913 RX_GATING_TRACK_MODE = 2
2299 13:59:45.898135 SELPH_MODE = 1
2300 13:59:45.901376 PICG_EARLY_EN = 1
2301 13:59:45.904801 VALID_LAT_VALUE = 1
2302 13:59:45.911446 ==============================================================
2303 13:59:45.914970 Enter into Gating configuration >>>>
2304 13:59:45.918387 Exit from Gating configuration <<<<
2305 13:59:45.921623 Enter into DVFS_PRE_config >>>>>
2306 13:59:45.931269 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2307 13:59:45.934489 Exit from DVFS_PRE_config <<<<<
2308 13:59:45.938163 Enter into PICG configuration >>>>
2309 13:59:45.941172 Exit from PICG configuration <<<<
2310 13:59:45.941645 [RX_INPUT] configuration >>>>>
2311 13:59:45.944600 [RX_INPUT] configuration <<<<<
2312 13:59:45.951420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2313 13:59:45.954559 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2314 13:59:45.961389 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 13:59:45.967820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 13:59:45.974700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 13:59:45.981212 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 13:59:45.984684 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2319 13:59:45.988101 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2320 13:59:45.994196 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2321 13:59:45.997831 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2322 13:59:46.001002 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2323 13:59:46.004605 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 13:59:46.008059 ===================================
2325 13:59:46.011416 LPDDR4 DRAM CONFIGURATION
2326 13:59:46.014879 ===================================
2327 13:59:46.018209 EX_ROW_EN[0] = 0x0
2328 13:59:46.018785 EX_ROW_EN[1] = 0x0
2329 13:59:46.021698 LP4Y_EN = 0x0
2330 13:59:46.022306 WORK_FSP = 0x0
2331 13:59:46.025031 WL = 0x4
2332 13:59:46.025609 RL = 0x4
2333 13:59:46.028031 BL = 0x2
2334 13:59:46.028655 RPST = 0x0
2335 13:59:46.030977 RD_PRE = 0x0
2336 13:59:46.031448 WR_PRE = 0x1
2337 13:59:46.034622 WR_PST = 0x0
2338 13:59:46.035206 DBI_WR = 0x0
2339 13:59:46.038031 DBI_RD = 0x0
2340 13:59:46.041296 OTF = 0x1
2341 13:59:46.044705 ===================================
2342 13:59:46.048089 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2343 13:59:46.051759 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2344 13:59:46.054401 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2345 13:59:46.058042 ===================================
2346 13:59:46.061277 LPDDR4 DRAM CONFIGURATION
2347 13:59:46.064616 ===================================
2348 13:59:46.068102 EX_ROW_EN[0] = 0x10
2349 13:59:46.068649 EX_ROW_EN[1] = 0x0
2350 13:59:46.071415 LP4Y_EN = 0x0
2351 13:59:46.071884 WORK_FSP = 0x0
2352 13:59:46.074474 WL = 0x4
2353 13:59:46.074943 RL = 0x4
2354 13:59:46.077781 BL = 0x2
2355 13:59:46.078309 RPST = 0x0
2356 13:59:46.081118 RD_PRE = 0x0
2357 13:59:46.081675 WR_PRE = 0x1
2358 13:59:46.084365 WR_PST = 0x0
2359 13:59:46.084835 DBI_WR = 0x0
2360 13:59:46.087753 DBI_RD = 0x0
2361 13:59:46.088213 OTF = 0x1
2362 13:59:46.091149 ===================================
2363 13:59:46.097819 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2364 13:59:46.098330 ==
2365 13:59:46.101059 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 13:59:46.104547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 13:59:46.107894 ==
2368 13:59:46.108329 [Duty_Offset_Calibration]
2369 13:59:46.111113 B0:2 B1:0 CA:1
2370 13:59:46.111434
2371 13:59:46.114335 [DutyScan_Calibration_Flow] k_type=0
2372 13:59:46.122273
2373 13:59:46.122657 ==CLK 0==
2374 13:59:46.125630 Final CLK duty delay cell = -4
2375 13:59:46.129200 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2376 13:59:46.132651 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2377 13:59:46.135806 [-4] AVG Duty = 4953%(X100)
2378 13:59:46.136224
2379 13:59:46.138931 CH0 CLK Duty spec in!! Max-Min= 156%
2380 13:59:46.142084 [DutyScan_Calibration_Flow] ====Done====
2381 13:59:46.142422
2382 13:59:46.145459 [DutyScan_Calibration_Flow] k_type=1
2383 13:59:46.161022
2384 13:59:46.161569 ==DQS 0 ==
2385 13:59:46.164330 Final DQS duty delay cell = 0
2386 13:59:46.167560 [0] MAX Duty = 5187%(X100), DQS PI = 30
2387 13:59:46.170863 [0] MIN Duty = 4938%(X100), DQS PI = 0
2388 13:59:46.171320 [0] AVG Duty = 5062%(X100)
2389 13:59:46.174245
2390 13:59:46.174695 ==DQS 1 ==
2391 13:59:46.177718 Final DQS duty delay cell = -4
2392 13:59:46.181234 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2393 13:59:46.184254 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2394 13:59:46.187857 [-4] AVG Duty = 5015%(X100)
2395 13:59:46.188311
2396 13:59:46.191022 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2397 13:59:46.191479
2398 13:59:46.194298 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2399 13:59:46.197715 [DutyScan_Calibration_Flow] ====Done====
2400 13:59:46.198234
2401 13:59:46.200941 [DutyScan_Calibration_Flow] k_type=3
2402 13:59:46.218110
2403 13:59:46.219065 ==DQM 0 ==
2404 13:59:46.220910 Final DQM duty delay cell = 0
2405 13:59:46.224154 [0] MAX Duty = 5062%(X100), DQS PI = 24
2406 13:59:46.227586 [0] MIN Duty = 4844%(X100), DQS PI = 0
2407 13:59:46.228251 [0] AVG Duty = 4953%(X100)
2408 13:59:46.230821
2409 13:59:46.231207 ==DQM 1 ==
2410 13:59:46.234218 Final DQM duty delay cell = 0
2411 13:59:46.237705 [0] MAX Duty = 5187%(X100), DQS PI = 48
2412 13:59:46.241087 [0] MIN Duty = 5000%(X100), DQS PI = 12
2413 13:59:46.241500 [0] AVG Duty = 5093%(X100)
2414 13:59:46.244522
2415 13:59:46.248150 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2416 13:59:46.248709
2417 13:59:46.251440 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2418 13:59:46.254624 [DutyScan_Calibration_Flow] ====Done====
2419 13:59:46.255099
2420 13:59:46.258006 [DutyScan_Calibration_Flow] k_type=2
2421 13:59:46.274648
2422 13:59:46.275123 ==DQ 0 ==
2423 13:59:46.278130 Final DQ duty delay cell = -4
2424 13:59:46.281160 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2425 13:59:46.284559 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2426 13:59:46.285009 [-4] AVG Duty = 4968%(X100)
2427 13:59:46.287803
2428 13:59:46.288295 ==DQ 1 ==
2429 13:59:46.291254 Final DQ duty delay cell = 4
2430 13:59:46.295071 [4] MAX Duty = 5093%(X100), DQS PI = 4
2431 13:59:46.297771 [4] MIN Duty = 5031%(X100), DQS PI = 14
2432 13:59:46.298260 [4] AVG Duty = 5062%(X100)
2433 13:59:46.298699
2434 13:59:46.301111 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2435 13:59:46.304378
2436 13:59:46.308158 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2437 13:59:46.311082 [DutyScan_Calibration_Flow] ====Done====
2438 13:59:46.311610 ==
2439 13:59:46.314453 Dram Type= 6, Freq= 0, CH_1, rank 0
2440 13:59:46.317801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 13:59:46.318364 ==
2442 13:59:46.321150 [Duty_Offset_Calibration]
2443 13:59:46.321702 B0:0 B1:-1 CA:2
2444 13:59:46.322085
2445 13:59:46.324474 [DutyScan_Calibration_Flow] k_type=0
2446 13:59:46.335081
2447 13:59:46.335609 ==CLK 0==
2448 13:59:46.338278 Final CLK duty delay cell = 0
2449 13:59:46.341271 [0] MAX Duty = 5156%(X100), DQS PI = 16
2450 13:59:46.344427 [0] MIN Duty = 4938%(X100), DQS PI = 44
2451 13:59:46.344859 [0] AVG Duty = 5047%(X100)
2452 13:59:46.348020
2453 13:59:46.348563 CH1 CLK Duty spec in!! Max-Min= 218%
2454 13:59:46.354895 [DutyScan_Calibration_Flow] ====Done====
2455 13:59:46.355413
2456 13:59:46.358177 [DutyScan_Calibration_Flow] k_type=1
2457 13:59:46.374055
2458 13:59:46.374599 ==DQS 0 ==
2459 13:59:46.377227 Final DQS duty delay cell = 0
2460 13:59:46.380874 [0] MAX Duty = 5093%(X100), DQS PI = 24
2461 13:59:46.384306 [0] MIN Duty = 4969%(X100), DQS PI = 0
2462 13:59:46.384894 [0] AVG Duty = 5031%(X100)
2463 13:59:46.387593
2464 13:59:46.388187 ==DQS 1 ==
2465 13:59:46.390783 Final DQS duty delay cell = 0
2466 13:59:46.394275 [0] MAX Duty = 5156%(X100), DQS PI = 0
2467 13:59:46.397473 [0] MIN Duty = 4813%(X100), DQS PI = 36
2468 13:59:46.398018 [0] AVG Duty = 4984%(X100)
2469 13:59:46.398399
2470 13:59:46.404345 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2471 13:59:46.404929
2472 13:59:46.407271 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2473 13:59:46.410617 [DutyScan_Calibration_Flow] ====Done====
2474 13:59:46.411085
2475 13:59:46.413863 [DutyScan_Calibration_Flow] k_type=3
2476 13:59:46.431536
2477 13:59:46.432072 ==DQM 0 ==
2478 13:59:46.434753 Final DQM duty delay cell = 4
2479 13:59:46.438165 [4] MAX Duty = 5093%(X100), DQS PI = 6
2480 13:59:46.441724 [4] MIN Duty = 4969%(X100), DQS PI = 28
2481 13:59:46.442374 [4] AVG Duty = 5031%(X100)
2482 13:59:46.444570
2483 13:59:46.445093 ==DQM 1 ==
2484 13:59:46.447983 Final DQM duty delay cell = 0
2485 13:59:46.451035 [0] MAX Duty = 5249%(X100), DQS PI = 0
2486 13:59:46.454419 [0] MIN Duty = 4875%(X100), DQS PI = 36
2487 13:59:46.454995 [0] AVG Duty = 5062%(X100)
2488 13:59:46.457911
2489 13:59:46.461494 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2490 13:59:46.462109
2491 13:59:46.465008 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2492 13:59:46.467931 [DutyScan_Calibration_Flow] ====Done====
2493 13:59:46.468501
2494 13:59:46.471201 [DutyScan_Calibration_Flow] k_type=2
2495 13:59:46.487928
2496 13:59:46.488466 ==DQ 0 ==
2497 13:59:46.491213 Final DQ duty delay cell = 0
2498 13:59:46.494734 [0] MAX Duty = 5062%(X100), DQS PI = 20
2499 13:59:46.497518 [0] MIN Duty = 4938%(X100), DQS PI = 0
2500 13:59:46.498041 [0] AVG Duty = 5000%(X100)
2501 13:59:46.498434
2502 13:59:46.500890 ==DQ 1 ==
2503 13:59:46.504252 Final DQ duty delay cell = 0
2504 13:59:46.507590 [0] MAX Duty = 5031%(X100), DQS PI = 0
2505 13:59:46.510987 [0] MIN Duty = 4813%(X100), DQS PI = 36
2506 13:59:46.511464 [0] AVG Duty = 4922%(X100)
2507 13:59:46.511843
2508 13:59:46.514413 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2509 13:59:46.514881
2510 13:59:46.517568 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2511 13:59:46.524241 [DutyScan_Calibration_Flow] ====Done====
2512 13:59:46.527700 nWR fixed to 30
2513 13:59:46.528171 [ModeRegInit_LP4] CH0 RK0
2514 13:59:46.531081 [ModeRegInit_LP4] CH0 RK1
2515 13:59:46.534582 [ModeRegInit_LP4] CH1 RK0
2516 13:59:46.535005 [ModeRegInit_LP4] CH1 RK1
2517 13:59:46.537675 match AC timing 7
2518 13:59:46.541005 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2519 13:59:46.544228 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2520 13:59:46.550845 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2521 13:59:46.554523 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2522 13:59:46.561300 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2523 13:59:46.561827 ==
2524 13:59:46.564712 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 13:59:46.567868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 13:59:46.568299 ==
2527 13:59:46.574243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 13:59:46.577544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2529 13:59:46.587342 [CA 0] Center 38 (7~69) winsize 63
2530 13:59:46.590630 [CA 1] Center 38 (7~69) winsize 63
2531 13:59:46.594038 [CA 2] Center 34 (4~65) winsize 62
2532 13:59:46.597444 [CA 3] Center 34 (4~65) winsize 62
2533 13:59:46.600730 [CA 4] Center 33 (3~64) winsize 62
2534 13:59:46.604617 [CA 5] Center 32 (2~63) winsize 62
2535 13:59:46.605185
2536 13:59:46.607548 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2537 13:59:46.608018
2538 13:59:46.610725 [CATrainingPosCal] consider 1 rank data
2539 13:59:46.614420 u2DelayCellTimex100 = 270/100 ps
2540 13:59:46.617664 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2541 13:59:46.620835 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2542 13:59:46.627209 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2543 13:59:46.630674 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2544 13:59:46.634102 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2545 13:59:46.637457 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2546 13:59:46.637883
2547 13:59:46.640663 CA PerBit enable=1, Macro0, CA PI delay=32
2548 13:59:46.641102
2549 13:59:46.644133 [CBTSetCACLKResult] CA Dly = 32
2550 13:59:46.644561 CS Dly: 6 (0~37)
2551 13:59:46.644901 ==
2552 13:59:46.647716 Dram Type= 6, Freq= 0, CH_0, rank 1
2553 13:59:46.654400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 13:59:46.654826 ==
2555 13:59:46.657495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2556 13:59:46.664518 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2557 13:59:46.673224 [CA 0] Center 38 (7~69) winsize 63
2558 13:59:46.676530 [CA 1] Center 38 (8~69) winsize 62
2559 13:59:46.679835 [CA 2] Center 35 (5~66) winsize 62
2560 13:59:46.683296 [CA 3] Center 35 (4~66) winsize 63
2561 13:59:46.686553 [CA 4] Center 34 (3~65) winsize 63
2562 13:59:46.689853 [CA 5] Center 33 (3~64) winsize 62
2563 13:59:46.690470
2564 13:59:46.693216 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2565 13:59:46.693685
2566 13:59:46.696581 [CATrainingPosCal] consider 2 rank data
2567 13:59:46.699901 u2DelayCellTimex100 = 270/100 ps
2568 13:59:46.703223 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2569 13:59:46.706656 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2570 13:59:46.710001 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2571 13:59:46.716391 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2572 13:59:46.719866 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2573 13:59:46.723041 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2574 13:59:46.723543
2575 13:59:46.726535 CA PerBit enable=1, Macro0, CA PI delay=33
2576 13:59:46.727007
2577 13:59:46.729972 [CBTSetCACLKResult] CA Dly = 33
2578 13:59:46.730443 CS Dly: 7 (0~39)
2579 13:59:46.730779
2580 13:59:46.733550 ----->DramcWriteLeveling(PI) begin...
2581 13:59:46.734007 ==
2582 13:59:46.736361 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 13:59:46.743196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 13:59:46.743737 ==
2585 13:59:46.746488 Write leveling (Byte 0): 32 => 32
2586 13:59:46.750018 Write leveling (Byte 1): 31 => 31
2587 13:59:46.750444 DramcWriteLeveling(PI) end<-----
2588 13:59:46.753052
2589 13:59:46.753475 ==
2590 13:59:46.756379 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 13:59:46.759688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 13:59:46.760203 ==
2593 13:59:46.763660 [Gating] SW mode calibration
2594 13:59:46.769924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2595 13:59:46.773141 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2596 13:59:46.779977 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2597 13:59:46.783382 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2598 13:59:46.786820 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 13:59:46.793224 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 13:59:46.797021 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 13:59:46.800085 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 13:59:46.806463 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
2603 13:59:46.809763 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
2604 13:59:46.813490 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2605 13:59:46.819976 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 13:59:46.823077 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 13:59:46.826467 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 13:59:46.833417 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 13:59:46.837025 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 13:59:46.840274 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2611 13:59:46.843191 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (1 1) (0 0)
2612 13:59:46.849789 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
2613 13:59:46.853191 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
2614 13:59:46.856562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 13:59:46.863178 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 13:59:46.866517 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 13:59:46.869812 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 13:59:46.876738 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 13:59:46.880040 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2620 13:59:46.883156 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2621 13:59:46.890133 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 13:59:46.893644 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 13:59:46.896813 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 13:59:46.903524 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 13:59:46.906826 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 13:59:46.910049 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 13:59:46.916787 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 13:59:46.920209 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 13:59:46.923413 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 13:59:46.926804 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 13:59:46.933534 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 13:59:46.936581 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 13:59:46.940269 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 13:59:46.946705 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2635 13:59:46.950294 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2636 13:59:46.953190 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 13:59:46.956479 Total UI for P1: 0, mck2ui 16
2638 13:59:46.960041 best dqsien dly found for B0: ( 1, 3, 26)
2639 13:59:46.963301 Total UI for P1: 0, mck2ui 16
2640 13:59:46.966470 best dqsien dly found for B1: ( 1, 3, 28)
2641 13:59:46.970034 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2642 13:59:46.973312 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2643 13:59:46.973801
2644 13:59:46.980149 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2645 13:59:46.983393 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2646 13:59:46.983864 [Gating] SW calibration Done
2647 13:59:46.986871 ==
2648 13:59:46.990109 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 13:59:46.993431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 13:59:46.993906 ==
2651 13:59:46.994331 RX Vref Scan: 0
2652 13:59:46.994645
2653 13:59:46.996875 RX Vref 0 -> 0, step: 1
2654 13:59:46.997297
2655 13:59:47.000028 RX Delay -40 -> 252, step: 8
2656 13:59:47.003902 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2657 13:59:47.006820 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2658 13:59:47.010363 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2659 13:59:47.017176 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2660 13:59:47.020545 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2661 13:59:47.023619 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2662 13:59:47.026842 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2663 13:59:47.030322 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2664 13:59:47.036873 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2665 13:59:47.040567 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2666 13:59:47.043604 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2667 13:59:47.046715 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2668 13:59:47.050212 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2669 13:59:47.056887 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2670 13:59:47.060679 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2671 13:59:47.063809 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2672 13:59:47.064281 ==
2673 13:59:47.067609 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 13:59:47.070457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 13:59:47.070936 ==
2676 13:59:47.073561 DQS Delay:
2677 13:59:47.074095 DQS0 = 0, DQS1 = 0
2678 13:59:47.074505 DQM Delay:
2679 13:59:47.077190 DQM0 = 122, DQM1 = 110
2680 13:59:47.077658 DQ Delay:
2681 13:59:47.080161 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2682 13:59:47.083732 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2683 13:59:47.087338 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2684 13:59:47.093716 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2685 13:59:47.094231
2686 13:59:47.094631
2687 13:59:47.094981 ==
2688 13:59:47.097206 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 13:59:47.100612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 13:59:47.101041 ==
2691 13:59:47.101409
2692 13:59:47.101906
2693 13:59:47.103680 TX Vref Scan disable
2694 13:59:47.104102 == TX Byte 0 ==
2695 13:59:47.110438 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2696 13:59:47.113489 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2697 13:59:47.113917 == TX Byte 1 ==
2698 13:59:47.120511 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2699 13:59:47.123589 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2700 13:59:47.124071 ==
2701 13:59:47.126920 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 13:59:47.130387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 13:59:47.130927 ==
2704 13:59:47.142755 TX Vref=22, minBit 7, minWin=23, winSum=398
2705 13:59:47.146305 TX Vref=24, minBit 4, minWin=24, winSum=402
2706 13:59:47.149477 TX Vref=26, minBit 2, minWin=24, winSum=410
2707 13:59:47.152882 TX Vref=28, minBit 2, minWin=25, winSum=420
2708 13:59:47.156093 TX Vref=30, minBit 1, minWin=25, winSum=415
2709 13:59:47.159736 TX Vref=32, minBit 1, minWin=25, winSum=418
2710 13:59:47.166205 [TxChooseVref] Worse bit 2, Min win 25, Win sum 420, Final Vref 28
2711 13:59:47.166679
2712 13:59:47.169398 Final TX Range 1 Vref 28
2713 13:59:47.169868
2714 13:59:47.170290 ==
2715 13:59:47.172752 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 13:59:47.176328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 13:59:47.176898 ==
2718 13:59:47.177271
2719 13:59:47.179352
2720 13:59:47.179822 TX Vref Scan disable
2721 13:59:47.182730 == TX Byte 0 ==
2722 13:59:47.186455 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2723 13:59:47.189637 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2724 13:59:47.192790 == TX Byte 1 ==
2725 13:59:47.196191 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2726 13:59:47.199517 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2727 13:59:47.199990
2728 13:59:47.202921 [DATLAT]
2729 13:59:47.203391 Freq=1200, CH0 RK0
2730 13:59:47.203767
2731 13:59:47.206260 DATLAT Default: 0xd
2732 13:59:47.206780 0, 0xFFFF, sum = 0
2733 13:59:47.209549 1, 0xFFFF, sum = 0
2734 13:59:47.210019 2, 0xFFFF, sum = 0
2735 13:59:47.212835 3, 0xFFFF, sum = 0
2736 13:59:47.213269 4, 0xFFFF, sum = 0
2737 13:59:47.216407 5, 0xFFFF, sum = 0
2738 13:59:47.216954 6, 0xFFFF, sum = 0
2739 13:59:47.219828 7, 0xFFFF, sum = 0
2740 13:59:47.220374 8, 0xFFFF, sum = 0
2741 13:59:47.223076 9, 0xFFFF, sum = 0
2742 13:59:47.226643 10, 0xFFFF, sum = 0
2743 13:59:47.227244 11, 0xFFFF, sum = 0
2744 13:59:47.229498 12, 0x0, sum = 1
2745 13:59:47.230001 13, 0x0, sum = 2
2746 13:59:47.230367 14, 0x0, sum = 3
2747 13:59:47.232939 15, 0x0, sum = 4
2748 13:59:47.233426 best_step = 13
2749 13:59:47.233773
2750 13:59:47.236525 ==
2751 13:59:47.237075 Dram Type= 6, Freq= 0, CH_0, rank 0
2752 13:59:47.242893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2753 13:59:47.243342 ==
2754 13:59:47.243687 RX Vref Scan: 1
2755 13:59:47.244005
2756 13:59:47.246287 Set Vref Range= 32 -> 127
2757 13:59:47.246714
2758 13:59:47.249590 RX Vref 32 -> 127, step: 1
2759 13:59:47.250060
2760 13:59:47.252929 RX Delay -13 -> 252, step: 4
2761 13:59:47.253357
2762 13:59:47.256080 Set Vref, RX VrefLevel [Byte0]: 32
2763 13:59:47.259659 [Byte1]: 32
2764 13:59:47.260149
2765 13:59:47.263027 Set Vref, RX VrefLevel [Byte0]: 33
2766 13:59:47.266233 [Byte1]: 33
2767 13:59:47.266716
2768 13:59:47.269479 Set Vref, RX VrefLevel [Byte0]: 34
2769 13:59:47.272769 [Byte1]: 34
2770 13:59:47.277046
2771 13:59:47.277474 Set Vref, RX VrefLevel [Byte0]: 35
2772 13:59:47.280088 [Byte1]: 35
2773 13:59:47.284663
2774 13:59:47.285134 Set Vref, RX VrefLevel [Byte0]: 36
2775 13:59:47.287813 [Byte1]: 36
2776 13:59:47.292964
2777 13:59:47.293459 Set Vref, RX VrefLevel [Byte0]: 37
2778 13:59:47.296157 [Byte1]: 37
2779 13:59:47.300411
2780 13:59:47.300837 Set Vref, RX VrefLevel [Byte0]: 38
2781 13:59:47.303718 [Byte1]: 38
2782 13:59:47.308497
2783 13:59:47.308923 Set Vref, RX VrefLevel [Byte0]: 39
2784 13:59:47.311586 [Byte1]: 39
2785 13:59:47.316313
2786 13:59:47.316901 Set Vref, RX VrefLevel [Byte0]: 40
2787 13:59:47.320080 [Byte1]: 40
2788 13:59:47.324287
2789 13:59:47.324815 Set Vref, RX VrefLevel [Byte0]: 41
2790 13:59:47.327552 [Byte1]: 41
2791 13:59:47.332185
2792 13:59:47.332767 Set Vref, RX VrefLevel [Byte0]: 42
2793 13:59:47.335458 [Byte1]: 42
2794 13:59:47.340091
2795 13:59:47.340621 Set Vref, RX VrefLevel [Byte0]: 43
2796 13:59:47.343409 [Byte1]: 43
2797 13:59:47.347708
2798 13:59:47.348136 Set Vref, RX VrefLevel [Byte0]: 44
2799 13:59:47.351158 [Byte1]: 44
2800 13:59:47.356157
2801 13:59:47.356677 Set Vref, RX VrefLevel [Byte0]: 45
2802 13:59:47.359296 [Byte1]: 45
2803 13:59:47.363873
2804 13:59:47.364410 Set Vref, RX VrefLevel [Byte0]: 46
2805 13:59:47.367176 [Byte1]: 46
2806 13:59:47.371771
2807 13:59:47.372423 Set Vref, RX VrefLevel [Byte0]: 47
2808 13:59:47.374713 [Byte1]: 47
2809 13:59:47.379498
2810 13:59:47.380065 Set Vref, RX VrefLevel [Byte0]: 48
2811 13:59:47.382827 [Byte1]: 48
2812 13:59:47.387395
2813 13:59:47.387953 Set Vref, RX VrefLevel [Byte0]: 49
2814 13:59:47.390545 [Byte1]: 49
2815 13:59:47.395363
2816 13:59:47.396012 Set Vref, RX VrefLevel [Byte0]: 50
2817 13:59:47.398626 [Byte1]: 50
2818 13:59:47.403121
2819 13:59:47.403587 Set Vref, RX VrefLevel [Byte0]: 51
2820 13:59:47.406300 [Byte1]: 51
2821 13:59:47.410763
2822 13:59:47.411230 Set Vref, RX VrefLevel [Byte0]: 52
2823 13:59:47.414429 [Byte1]: 52
2824 13:59:47.419225
2825 13:59:47.419779 Set Vref, RX VrefLevel [Byte0]: 53
2826 13:59:47.422455 [Byte1]: 53
2827 13:59:47.426801
2828 13:59:47.427335 Set Vref, RX VrefLevel [Byte0]: 54
2829 13:59:47.430206 [Byte1]: 54
2830 13:59:47.434587
2831 13:59:47.435131 Set Vref, RX VrefLevel [Byte0]: 55
2832 13:59:47.438365 [Byte1]: 55
2833 13:59:47.442522
2834 13:59:47.443099 Set Vref, RX VrefLevel [Byte0]: 56
2835 13:59:47.445728 [Byte1]: 56
2836 13:59:47.450464
2837 13:59:47.450960 Set Vref, RX VrefLevel [Byte0]: 57
2838 13:59:47.453775 [Byte1]: 57
2839 13:59:47.458790
2840 13:59:47.459350 Set Vref, RX VrefLevel [Byte0]: 58
2841 13:59:47.461469 [Byte1]: 58
2842 13:59:47.466576
2843 13:59:47.467162 Set Vref, RX VrefLevel [Byte0]: 59
2844 13:59:47.469754 [Byte1]: 59
2845 13:59:47.474106
2846 13:59:47.474573 Set Vref, RX VrefLevel [Byte0]: 60
2847 13:59:47.477237 [Byte1]: 60
2848 13:59:47.481931
2849 13:59:47.482427 Set Vref, RX VrefLevel [Byte0]: 61
2850 13:59:47.485483 [Byte1]: 61
2851 13:59:47.489814
2852 13:59:47.490404 Set Vref, RX VrefLevel [Byte0]: 62
2853 13:59:47.493129 [Byte1]: 62
2854 13:59:47.497732
2855 13:59:47.498267 Set Vref, RX VrefLevel [Byte0]: 63
2856 13:59:47.501367 [Byte1]: 63
2857 13:59:47.505666
2858 13:59:47.506392 Set Vref, RX VrefLevel [Byte0]: 64
2859 13:59:47.508918 [Byte1]: 64
2860 13:59:47.513512
2861 13:59:47.514048 Set Vref, RX VrefLevel [Byte0]: 65
2862 13:59:47.517148 [Byte1]: 65
2863 13:59:47.521772
2864 13:59:47.522403 Set Vref, RX VrefLevel [Byte0]: 66
2865 13:59:47.524826 [Byte1]: 66
2866 13:59:47.529159
2867 13:59:47.529653 Set Vref, RX VrefLevel [Byte0]: 67
2868 13:59:47.532547 [Byte1]: 67
2869 13:59:47.537345
2870 13:59:47.537931 Set Vref, RX VrefLevel [Byte0]: 68
2871 13:59:47.540883 [Byte1]: 68
2872 13:59:47.545113
2873 13:59:47.545715 Set Vref, RX VrefLevel [Byte0]: 69
2874 13:59:47.548343 [Byte1]: 69
2875 13:59:47.552802
2876 13:59:47.553301 Final RX Vref Byte 0 = 59 to rank0
2877 13:59:47.556934 Final RX Vref Byte 1 = 49 to rank0
2878 13:59:47.559739 Final RX Vref Byte 0 = 59 to rank1
2879 13:59:47.562901 Final RX Vref Byte 1 = 49 to rank1==
2880 13:59:47.566599 Dram Type= 6, Freq= 0, CH_0, rank 0
2881 13:59:47.573040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 13:59:47.573598 ==
2883 13:59:47.574014 DQS Delay:
2884 13:59:47.574507 DQS0 = 0, DQS1 = 0
2885 13:59:47.576255 DQM Delay:
2886 13:59:47.576716 DQM0 = 122, DQM1 = 109
2887 13:59:47.579848 DQ Delay:
2888 13:59:47.583303 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2889 13:59:47.586302 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2890 13:59:47.589595 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2891 13:59:47.593781 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2892 13:59:47.594561
2893 13:59:47.595142
2894 13:59:47.599993 [DQSOSCAuto] RK0, (LSB)MR18= 0x704, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2895 13:59:47.603207 CH0 RK0: MR19=404, MR18=704
2896 13:59:47.609788 CH0_RK0: MR19=0x404, MR18=0x704, DQSOSC=407, MR23=63, INC=39, DEC=26
2897 13:59:47.610443
2898 13:59:47.612895 ----->DramcWriteLeveling(PI) begin...
2899 13:59:47.613372 ==
2900 13:59:47.616212 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 13:59:47.619926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 13:59:47.620534 ==
2903 13:59:47.623104 Write leveling (Byte 0): 34 => 34
2904 13:59:47.626093 Write leveling (Byte 1): 30 => 30
2905 13:59:47.629754 DramcWriteLeveling(PI) end<-----
2906 13:59:47.630258
2907 13:59:47.630633 ==
2908 13:59:47.632948 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 13:59:47.639379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 13:59:47.639809 ==
2911 13:59:47.640155 [Gating] SW mode calibration
2912 13:59:47.649688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2913 13:59:47.653256 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2914 13:59:47.656752 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2915 13:59:47.663395 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 13:59:47.666636 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 13:59:47.669991 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 13:59:47.676173 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 13:59:47.679745 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 13:59:47.683112 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2921 13:59:47.690065 0 15 28 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (0 0)
2922 13:59:47.692978 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2923 13:59:47.696423 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 13:59:47.703174 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 13:59:47.706631 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 13:59:47.710069 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 13:59:47.713376 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 13:59:47.719973 1 0 24 | B1->B0 | 2423 2525 | 1 0 | (0 0) (0 0)
2929 13:59:47.723099 1 0 28 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
2930 13:59:47.726447 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 13:59:47.733427 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 13:59:47.736408 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 13:59:47.739726 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 13:59:47.746891 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 13:59:47.749906 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 13:59:47.752970 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 13:59:47.759866 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2938 13:59:47.763363 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 13:59:47.766613 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 13:59:47.773480 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 13:59:47.776687 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 13:59:47.780084 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 13:59:47.786957 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 13:59:47.790164 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 13:59:47.793213 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 13:59:47.796576 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 13:59:47.803178 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 13:59:47.806529 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 13:59:47.810114 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 13:59:47.816819 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 13:59:47.819962 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 13:59:47.823230 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 13:59:47.830079 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2954 13:59:47.833335 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 13:59:47.836555 Total UI for P1: 0, mck2ui 16
2956 13:59:47.840137 best dqsien dly found for B0: ( 1, 3, 28)
2957 13:59:47.843770 Total UI for P1: 0, mck2ui 16
2958 13:59:47.846801 best dqsien dly found for B1: ( 1, 3, 28)
2959 13:59:47.850025 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2960 13:59:47.853294 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2961 13:59:47.853760
2962 13:59:47.856706 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2963 13:59:47.860049 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2964 13:59:47.863517 [Gating] SW calibration Done
2965 13:59:47.863985 ==
2966 13:59:47.866846 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 13:59:47.869712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 13:59:47.873498 ==
2969 13:59:47.874089 RX Vref Scan: 0
2970 13:59:47.874470
2971 13:59:47.876788 RX Vref 0 -> 0, step: 1
2972 13:59:47.877257
2973 13:59:47.879900 RX Delay -40 -> 252, step: 8
2974 13:59:47.883248 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2975 13:59:47.886820 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2976 13:59:47.889702 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2977 13:59:47.893144 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2978 13:59:47.899920 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2979 13:59:47.903236 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2980 13:59:47.906527 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2981 13:59:47.910113 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2982 13:59:47.913329 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2983 13:59:47.916685 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2984 13:59:47.923202 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2985 13:59:47.926314 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2986 13:59:47.929674 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2987 13:59:47.933344 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2988 13:59:47.936636 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2989 13:59:47.943556 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2990 13:59:47.944094 ==
2991 13:59:47.946694 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 13:59:47.949733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 13:59:47.950209 ==
2994 13:59:47.950610 DQS Delay:
2995 13:59:47.953084 DQS0 = 0, DQS1 = 0
2996 13:59:47.953505 DQM Delay:
2997 13:59:47.956603 DQM0 = 120, DQM1 = 108
2998 13:59:47.957026 DQ Delay:
2999 13:59:47.959842 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3000 13:59:47.963106 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3001 13:59:47.966566 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3002 13:59:47.970031 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3003 13:59:47.970455
3004 13:59:47.970792
3005 13:59:47.973177 ==
3006 13:59:47.976634 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 13:59:47.980021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 13:59:47.980451 ==
3009 13:59:47.980791
3010 13:59:47.981106
3011 13:59:47.983365 TX Vref Scan disable
3012 13:59:47.983789 == TX Byte 0 ==
3013 13:59:47.986598 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3014 13:59:47.993048 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3015 13:59:47.993568 == TX Byte 1 ==
3016 13:59:47.996740 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3017 13:59:48.003202 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3018 13:59:48.003626 ==
3019 13:59:48.006894 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 13:59:48.010053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 13:59:48.010482 ==
3022 13:59:48.022097 TX Vref=22, minBit 1, minWin=24, winSum=402
3023 13:59:48.025484 TX Vref=24, minBit 0, minWin=24, winSum=406
3024 13:59:48.028650 TX Vref=26, minBit 0, minWin=24, winSum=413
3025 13:59:48.032328 TX Vref=28, minBit 1, minWin=24, winSum=415
3026 13:59:48.035863 TX Vref=30, minBit 7, minWin=24, winSum=419
3027 13:59:48.038620 TX Vref=32, minBit 7, minWin=24, winSum=417
3028 13:59:48.045303 [TxChooseVref] Worse bit 7, Min win 24, Win sum 419, Final Vref 30
3029 13:59:48.045871
3030 13:59:48.048745 Final TX Range 1 Vref 30
3031 13:59:48.049186
3032 13:59:48.049729 ==
3033 13:59:48.051951 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 13:59:48.055938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 13:59:48.056482 ==
3036 13:59:48.056834
3037 13:59:48.059177
3038 13:59:48.059727 TX Vref Scan disable
3039 13:59:48.061998 == TX Byte 0 ==
3040 13:59:48.065263 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3041 13:59:48.068803 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3042 13:59:48.072384 == TX Byte 1 ==
3043 13:59:48.075465 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3044 13:59:48.079065 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3045 13:59:48.079494
3046 13:59:48.082561 [DATLAT]
3047 13:59:48.083100 Freq=1200, CH0 RK1
3048 13:59:48.083568
3049 13:59:48.085905 DATLAT Default: 0xd
3050 13:59:48.086469 0, 0xFFFF, sum = 0
3051 13:59:48.089256 1, 0xFFFF, sum = 0
3052 13:59:48.089698 2, 0xFFFF, sum = 0
3053 13:59:48.092276 3, 0xFFFF, sum = 0
3054 13:59:48.092706 4, 0xFFFF, sum = 0
3055 13:59:48.095285 5, 0xFFFF, sum = 0
3056 13:59:48.095715 6, 0xFFFF, sum = 0
3057 13:59:48.098829 7, 0xFFFF, sum = 0
3058 13:59:48.099277 8, 0xFFFF, sum = 0
3059 13:59:48.102268 9, 0xFFFF, sum = 0
3060 13:59:48.102708 10, 0xFFFF, sum = 0
3061 13:59:48.105498 11, 0xFFFF, sum = 0
3062 13:59:48.108838 12, 0x0, sum = 1
3063 13:59:48.109357 13, 0x0, sum = 2
3064 13:59:48.109884 14, 0x0, sum = 3
3065 13:59:48.112428 15, 0x0, sum = 4
3066 13:59:48.113024 best_step = 13
3067 13:59:48.113489
3068 13:59:48.113821 ==
3069 13:59:48.115734 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 13:59:48.122210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 13:59:48.122702 ==
3072 13:59:48.123044 RX Vref Scan: 0
3073 13:59:48.123370
3074 13:59:48.126011 RX Vref 0 -> 0, step: 1
3075 13:59:48.126537
3076 13:59:48.129159 RX Delay -21 -> 252, step: 4
3077 13:59:48.132586 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3078 13:59:48.135607 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3079 13:59:48.142294 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3080 13:59:48.145863 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3081 13:59:48.149103 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3082 13:59:48.152592 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3083 13:59:48.155870 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3084 13:59:48.162476 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3085 13:59:48.165593 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3086 13:59:48.169048 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3087 13:59:48.172279 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3088 13:59:48.175662 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3089 13:59:48.182065 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3090 13:59:48.185612 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3091 13:59:48.188980 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3092 13:59:48.192222 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3093 13:59:48.192693 ==
3094 13:59:48.195992 Dram Type= 6, Freq= 0, CH_0, rank 1
3095 13:59:48.198862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 13:59:48.202434 ==
3097 13:59:48.202900 DQS Delay:
3098 13:59:48.203271 DQS0 = 0, DQS1 = 0
3099 13:59:48.205770 DQM Delay:
3100 13:59:48.206270 DQM0 = 120, DQM1 = 108
3101 13:59:48.209079 DQ Delay:
3102 13:59:48.212529 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =116
3103 13:59:48.215815 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =126
3104 13:59:48.219292 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3105 13:59:48.222710 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3106 13:59:48.223275
3107 13:59:48.223650
3108 13:59:48.228899 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3109 13:59:48.232148 CH0 RK1: MR19=403, MR18=BF1
3110 13:59:48.238928 CH0_RK1: MR19=0x403, MR18=0xBF1, DQSOSC=405, MR23=63, INC=39, DEC=26
3111 13:59:48.242349 [RxdqsGatingPostProcess] freq 1200
3112 13:59:48.246018 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3113 13:59:48.249204 best DQS0 dly(2T, 0.5T) = (0, 11)
3114 13:59:48.252433 best DQS1 dly(2T, 0.5T) = (0, 11)
3115 13:59:48.255851 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3116 13:59:48.259298 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3117 13:59:48.262624 best DQS0 dly(2T, 0.5T) = (0, 11)
3118 13:59:48.265563 best DQS1 dly(2T, 0.5T) = (0, 11)
3119 13:59:48.268900 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3120 13:59:48.272509 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3121 13:59:48.275778 Pre-setting of DQS Precalculation
3122 13:59:48.278994 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3123 13:59:48.282221 ==
3124 13:59:48.285561 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 13:59:48.289181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 13:59:48.289667 ==
3127 13:59:48.292390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3128 13:59:48.298738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3129 13:59:48.307979 [CA 0] Center 37 (7~67) winsize 61
3130 13:59:48.311359 [CA 1] Center 37 (7~68) winsize 62
3131 13:59:48.314557 [CA 2] Center 34 (4~65) winsize 62
3132 13:59:48.317882 [CA 3] Center 33 (3~64) winsize 62
3133 13:59:48.321497 [CA 4] Center 33 (3~64) winsize 62
3134 13:59:48.325042 [CA 5] Center 32 (2~63) winsize 62
3135 13:59:48.325555
3136 13:59:48.328186 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3137 13:59:48.328611
3138 13:59:48.331640 [CATrainingPosCal] consider 1 rank data
3139 13:59:48.334461 u2DelayCellTimex100 = 270/100 ps
3140 13:59:48.338458 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
3141 13:59:48.341657 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3142 13:59:48.348001 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
3143 13:59:48.351431 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3144 13:59:48.354814 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
3145 13:59:48.358175 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3146 13:59:48.358600
3147 13:59:48.361605 CA PerBit enable=1, Macro0, CA PI delay=32
3148 13:59:48.362130
3149 13:59:48.364961 [CBTSetCACLKResult] CA Dly = 32
3150 13:59:48.365464 CS Dly: 4 (0~35)
3151 13:59:48.365805 ==
3152 13:59:48.367803 Dram Type= 6, Freq= 0, CH_1, rank 1
3153 13:59:48.374533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 13:59:48.375032 ==
3155 13:59:48.378093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3156 13:59:48.384573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3157 13:59:48.393637 [CA 0] Center 38 (8~68) winsize 61
3158 13:59:48.397253 [CA 1] Center 37 (7~68) winsize 62
3159 13:59:48.400282 [CA 2] Center 35 (5~66) winsize 62
3160 13:59:48.403770 [CA 3] Center 34 (4~65) winsize 62
3161 13:59:48.407036 [CA 4] Center 34 (4~64) winsize 61
3162 13:59:48.410585 [CA 5] Center 33 (3~63) winsize 61
3163 13:59:48.411128
3164 13:59:48.413752 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3165 13:59:48.414272
3166 13:59:48.417103 [CATrainingPosCal] consider 2 rank data
3167 13:59:48.420714 u2DelayCellTimex100 = 270/100 ps
3168 13:59:48.423775 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3169 13:59:48.426945 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3170 13:59:48.430314 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3171 13:59:48.437331 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3172 13:59:48.440749 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 13:59:48.444097 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3174 13:59:48.444665
3175 13:59:48.446955 CA PerBit enable=1, Macro0, CA PI delay=33
3176 13:59:48.447449
3177 13:59:48.450585 [CBTSetCACLKResult] CA Dly = 33
3178 13:59:48.451055 CS Dly: 5 (0~38)
3179 13:59:48.451423
3180 13:59:48.453727 ----->DramcWriteLeveling(PI) begin...
3181 13:59:48.456765 ==
3182 13:59:48.457404 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 13:59:48.463697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 13:59:48.464299 ==
3185 13:59:48.466814 Write leveling (Byte 0): 24 => 24
3186 13:59:48.470167 Write leveling (Byte 1): 27 => 27
3187 13:59:48.473536 DramcWriteLeveling(PI) end<-----
3188 13:59:48.474042
3189 13:59:48.474458 ==
3190 13:59:48.476841 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 13:59:48.480145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 13:59:48.480611 ==
3193 13:59:48.483911 [Gating] SW mode calibration
3194 13:59:48.490371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3195 13:59:48.493670 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3196 13:59:48.500130 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 13:59:48.503627 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 13:59:48.507196 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 13:59:48.513933 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 13:59:48.517017 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 13:59:48.520222 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3202 13:59:48.527029 0 15 24 | B1->B0 | 3030 2929 | 1 0 | (1 0) (0 0)
3203 13:59:48.530306 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3204 13:59:48.534013 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 13:59:48.540558 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 13:59:48.543996 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 13:59:48.547010 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 13:59:48.553461 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 13:59:48.556924 1 0 20 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
3210 13:59:48.560201 1 0 24 | B1->B0 | 3f3f 4343 | 0 1 | (0 0) (0 0)
3211 13:59:48.567304 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 13:59:48.570429 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 13:59:48.574060 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 13:59:48.576995 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 13:59:48.583724 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 13:59:48.586959 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 13:59:48.590371 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 13:59:48.597180 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3219 13:59:48.600570 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3220 13:59:48.603481 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 13:59:48.610376 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 13:59:48.613520 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 13:59:48.616840 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 13:59:48.623810 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 13:59:48.627106 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 13:59:48.630419 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 13:59:48.636802 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 13:59:48.640160 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 13:59:48.643515 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 13:59:48.650049 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 13:59:48.653483 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 13:59:48.657142 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 13:59:48.663693 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 13:59:48.666825 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3235 13:59:48.670072 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3236 13:59:48.673811 Total UI for P1: 0, mck2ui 16
3237 13:59:48.676996 best dqsien dly found for B0: ( 1, 3, 24)
3238 13:59:48.680634 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 13:59:48.683594 Total UI for P1: 0, mck2ui 16
3240 13:59:48.687120 best dqsien dly found for B1: ( 1, 3, 26)
3241 13:59:48.690386 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3242 13:59:48.693562 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3243 13:59:48.697451
3244 13:59:48.700496 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3245 13:59:48.703907 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3246 13:59:48.707020 [Gating] SW calibration Done
3247 13:59:48.707489 ==
3248 13:59:48.710559 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 13:59:48.713840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 13:59:48.714448 ==
3251 13:59:48.714835 RX Vref Scan: 0
3252 13:59:48.715192
3253 13:59:48.717095 RX Vref 0 -> 0, step: 1
3254 13:59:48.717564
3255 13:59:48.720467 RX Delay -40 -> 252, step: 8
3256 13:59:48.723804 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3257 13:59:48.726894 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3258 13:59:48.733715 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3259 13:59:48.736836 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3260 13:59:48.740922 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3261 13:59:48.743846 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3262 13:59:48.746890 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3263 13:59:48.750695 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3264 13:59:48.757099 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3265 13:59:48.760543 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3266 13:59:48.763782 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3267 13:59:48.766987 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3268 13:59:48.770630 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3269 13:59:48.777366 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3270 13:59:48.780304 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3271 13:59:48.783643 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3272 13:59:48.784120 ==
3273 13:59:48.786926 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 13:59:48.790619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 13:59:48.793829 ==
3276 13:59:48.794426 DQS Delay:
3277 13:59:48.794805 DQS0 = 0, DQS1 = 0
3278 13:59:48.797221 DQM Delay:
3279 13:59:48.797762 DQM0 = 120, DQM1 = 112
3280 13:59:48.800726 DQ Delay:
3281 13:59:48.804135 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3282 13:59:48.807552 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3283 13:59:48.810623 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3284 13:59:48.813843 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3285 13:59:48.814369
3286 13:59:48.814842
3287 13:59:48.815290 ==
3288 13:59:48.817120 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 13:59:48.820559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 13:59:48.821145 ==
3291 13:59:48.821633
3292 13:59:48.822197
3293 13:59:48.823958 TX Vref Scan disable
3294 13:59:48.827129 == TX Byte 0 ==
3295 13:59:48.830496 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3296 13:59:48.833897 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3297 13:59:48.837299 == TX Byte 1 ==
3298 13:59:48.840477 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3299 13:59:48.844042 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3300 13:59:48.844516 ==
3301 13:59:48.847044 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 13:59:48.850414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 13:59:48.853469 ==
3304 13:59:48.863575 TX Vref=22, minBit 10, minWin=23, winSum=395
3305 13:59:48.866624 TX Vref=24, minBit 1, minWin=24, winSum=402
3306 13:59:48.870050 TX Vref=26, minBit 3, minWin=25, winSum=407
3307 13:59:48.873439 TX Vref=28, minBit 14, minWin=24, winSum=412
3308 13:59:48.877015 TX Vref=30, minBit 9, minWin=25, winSum=417
3309 13:59:48.883812 TX Vref=32, minBit 9, minWin=25, winSum=418
3310 13:59:48.887190 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 32
3311 13:59:48.887710
3312 13:59:48.890617 Final TX Range 1 Vref 32
3313 13:59:48.891061
3314 13:59:48.891403 ==
3315 13:59:48.893423 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 13:59:48.896774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3317 13:59:48.897201 ==
3318 13:59:48.897568
3319 13:59:48.900700
3320 13:59:48.901255 TX Vref Scan disable
3321 13:59:48.903743 == TX Byte 0 ==
3322 13:59:48.907232 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3323 13:59:48.910134 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3324 13:59:48.913465 == TX Byte 1 ==
3325 13:59:48.916741 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3326 13:59:48.920538 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3327 13:59:48.921078
3328 13:59:48.923429 [DATLAT]
3329 13:59:48.923903 Freq=1200, CH1 RK0
3330 13:59:48.924251
3331 13:59:48.927187 DATLAT Default: 0xd
3332 13:59:48.927611 0, 0xFFFF, sum = 0
3333 13:59:48.930191 1, 0xFFFF, sum = 0
3334 13:59:48.930623 2, 0xFFFF, sum = 0
3335 13:59:48.933351 3, 0xFFFF, sum = 0
3336 13:59:48.933779 4, 0xFFFF, sum = 0
3337 13:59:48.936820 5, 0xFFFF, sum = 0
3338 13:59:48.937252 6, 0xFFFF, sum = 0
3339 13:59:48.940377 7, 0xFFFF, sum = 0
3340 13:59:48.940867 8, 0xFFFF, sum = 0
3341 13:59:48.943688 9, 0xFFFF, sum = 0
3342 13:59:48.946955 10, 0xFFFF, sum = 0
3343 13:59:48.947386 11, 0xFFFF, sum = 0
3344 13:59:48.950126 12, 0x0, sum = 1
3345 13:59:48.950556 13, 0x0, sum = 2
3346 13:59:48.950902 14, 0x0, sum = 3
3347 13:59:48.953443 15, 0x0, sum = 4
3348 13:59:48.954084 best_step = 13
3349 13:59:48.954440
3350 13:59:48.957338 ==
3351 13:59:48.957756 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 13:59:48.963606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 13:59:48.964040 ==
3354 13:59:48.964384 RX Vref Scan: 1
3355 13:59:48.964706
3356 13:59:48.966923 Set Vref Range= 32 -> 127
3357 13:59:48.967350
3358 13:59:48.970134 RX Vref 32 -> 127, step: 1
3359 13:59:48.970563
3360 13:59:48.973519 RX Delay -13 -> 252, step: 4
3361 13:59:48.973935
3362 13:59:48.976826 Set Vref, RX VrefLevel [Byte0]: 32
3363 13:59:48.980047 [Byte1]: 32
3364 13:59:48.980467
3365 13:59:48.983748 Set Vref, RX VrefLevel [Byte0]: 33
3366 13:59:48.987062 [Byte1]: 33
3367 13:59:48.987478
3368 13:59:48.990461 Set Vref, RX VrefLevel [Byte0]: 34
3369 13:59:48.993438 [Byte1]: 34
3370 13:59:48.998022
3371 13:59:48.998544 Set Vref, RX VrefLevel [Byte0]: 35
3372 13:59:49.001265 [Byte1]: 35
3373 13:59:49.005809
3374 13:59:49.006416 Set Vref, RX VrefLevel [Byte0]: 36
3375 13:59:49.009073 [Byte1]: 36
3376 13:59:49.013454
3377 13:59:49.013874 Set Vref, RX VrefLevel [Byte0]: 37
3378 13:59:49.017050 [Byte1]: 37
3379 13:59:49.021448
3380 13:59:49.021866 Set Vref, RX VrefLevel [Byte0]: 38
3381 13:59:49.024486 [Byte1]: 38
3382 13:59:49.029232
3383 13:59:49.029724 Set Vref, RX VrefLevel [Byte0]: 39
3384 13:59:49.032416 [Byte1]: 39
3385 13:59:49.037018
3386 13:59:49.037432 Set Vref, RX VrefLevel [Byte0]: 40
3387 13:59:49.040658 [Byte1]: 40
3388 13:59:49.045161
3389 13:59:49.045667 Set Vref, RX VrefLevel [Byte0]: 41
3390 13:59:49.048386 [Byte1]: 41
3391 13:59:49.053097
3392 13:59:49.053706 Set Vref, RX VrefLevel [Byte0]: 42
3393 13:59:49.056203 [Byte1]: 42
3394 13:59:49.060699
3395 13:59:49.061158 Set Vref, RX VrefLevel [Byte0]: 43
3396 13:59:49.063908 [Byte1]: 43
3397 13:59:49.068548
3398 13:59:49.069007 Set Vref, RX VrefLevel [Byte0]: 44
3399 13:59:49.072007 [Byte1]: 44
3400 13:59:49.076431
3401 13:59:49.076888 Set Vref, RX VrefLevel [Byte0]: 45
3402 13:59:49.079875 [Byte1]: 45
3403 13:59:49.084742
3404 13:59:49.085302 Set Vref, RX VrefLevel [Byte0]: 46
3405 13:59:49.087724 [Byte1]: 46
3406 13:59:49.092540
3407 13:59:49.093094 Set Vref, RX VrefLevel [Byte0]: 47
3408 13:59:49.095986 [Byte1]: 47
3409 13:59:49.100453
3410 13:59:49.101008 Set Vref, RX VrefLevel [Byte0]: 48
3411 13:59:49.103549 [Byte1]: 48
3412 13:59:49.108517
3413 13:59:49.109079 Set Vref, RX VrefLevel [Byte0]: 49
3414 13:59:49.111541 [Byte1]: 49
3415 13:59:49.115998
3416 13:59:49.116458 Set Vref, RX VrefLevel [Byte0]: 50
3417 13:59:49.119590 [Byte1]: 50
3418 13:59:49.123814
3419 13:59:49.124271 Set Vref, RX VrefLevel [Byte0]: 51
3420 13:59:49.127187 [Byte1]: 51
3421 13:59:49.132072
3422 13:59:49.132533 Set Vref, RX VrefLevel [Byte0]: 52
3423 13:59:49.135275 [Byte1]: 52
3424 13:59:49.139861
3425 13:59:49.140421 Set Vref, RX VrefLevel [Byte0]: 53
3426 13:59:49.142909 [Byte1]: 53
3427 13:59:49.147789
3428 13:59:49.148362 Set Vref, RX VrefLevel [Byte0]: 54
3429 13:59:49.150819 [Byte1]: 54
3430 13:59:49.155616
3431 13:59:49.156174 Set Vref, RX VrefLevel [Byte0]: 55
3432 13:59:49.159135 [Byte1]: 55
3433 13:59:49.163768
3434 13:59:49.164339 Set Vref, RX VrefLevel [Byte0]: 56
3435 13:59:49.166910 [Byte1]: 56
3436 13:59:49.171103
3437 13:59:49.171561 Set Vref, RX VrefLevel [Byte0]: 57
3438 13:59:49.174702 [Byte1]: 57
3439 13:59:49.178874
3440 13:59:49.179337 Set Vref, RX VrefLevel [Byte0]: 58
3441 13:59:49.182250 [Byte1]: 58
3442 13:59:49.187140
3443 13:59:49.187694 Set Vref, RX VrefLevel [Byte0]: 59
3444 13:59:49.190253 [Byte1]: 59
3445 13:59:49.195130
3446 13:59:49.195678 Set Vref, RX VrefLevel [Byte0]: 60
3447 13:59:49.198628 [Byte1]: 60
3448 13:59:49.202881
3449 13:59:49.203456 Set Vref, RX VrefLevel [Byte0]: 61
3450 13:59:49.206159 [Byte1]: 61
3451 13:59:49.210696
3452 13:59:49.211256 Set Vref, RX VrefLevel [Byte0]: 62
3453 13:59:49.213839 [Byte1]: 62
3454 13:59:49.218519
3455 13:59:49.219076 Set Vref, RX VrefLevel [Byte0]: 63
3456 13:59:49.221642 [Byte1]: 63
3457 13:59:49.226330
3458 13:59:49.226782 Set Vref, RX VrefLevel [Byte0]: 64
3459 13:59:49.230131 [Byte1]: 64
3460 13:59:49.234518
3461 13:59:49.235144 Set Vref, RX VrefLevel [Byte0]: 65
3462 13:59:49.237767 [Byte1]: 65
3463 13:59:49.242414
3464 13:59:49.242885 Set Vref, RX VrefLevel [Byte0]: 66
3465 13:59:49.245762 [Byte1]: 66
3466 13:59:49.250052
3467 13:59:49.250522 Set Vref, RX VrefLevel [Byte0]: 67
3468 13:59:49.253340 [Byte1]: 67
3469 13:59:49.257820
3470 13:59:49.258353 Set Vref, RX VrefLevel [Byte0]: 68
3471 13:59:49.261216 [Byte1]: 68
3472 13:59:49.266051
3473 13:59:49.266613 Final RX Vref Byte 0 = 53 to rank0
3474 13:59:49.269056 Final RX Vref Byte 1 = 50 to rank0
3475 13:59:49.272507 Final RX Vref Byte 0 = 53 to rank1
3476 13:59:49.275980 Final RX Vref Byte 1 = 50 to rank1==
3477 13:59:49.279238 Dram Type= 6, Freq= 0, CH_1, rank 0
3478 13:59:49.285415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 13:59:49.286034 ==
3480 13:59:49.286567 DQS Delay:
3481 13:59:49.287073 DQS0 = 0, DQS1 = 0
3482 13:59:49.288949 DQM Delay:
3483 13:59:49.289419 DQM0 = 119, DQM1 = 112
3484 13:59:49.292610 DQ Delay:
3485 13:59:49.295873 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3486 13:59:49.299475 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3487 13:59:49.302591 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3488 13:59:49.305974 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3489 13:59:49.306453
3490 13:59:49.306839
3491 13:59:49.312588 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3492 13:59:49.315898 CH1 RK0: MR19=404, MR18=13
3493 13:59:49.322677 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3494 13:59:49.323369
3495 13:59:49.325869 ----->DramcWriteLeveling(PI) begin...
3496 13:59:49.326505 ==
3497 13:59:49.328983 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 13:59:49.332291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 13:59:49.332763 ==
3500 13:59:49.335660 Write leveling (Byte 0): 25 => 25
3501 13:59:49.339013 Write leveling (Byte 1): 29 => 29
3502 13:59:49.342611 DramcWriteLeveling(PI) end<-----
3503 13:59:49.343201
3504 13:59:49.343698 ==
3505 13:59:49.346001 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 13:59:49.349386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 13:59:49.352883 ==
3508 13:59:49.353637 [Gating] SW mode calibration
3509 13:59:49.359438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3510 13:59:49.366124 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3511 13:59:49.369264 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 13:59:49.376483 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 13:59:49.379498 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 13:59:49.382728 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 13:59:49.389668 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 13:59:49.392900 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3517 13:59:49.396306 0 15 24 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
3518 13:59:49.399377 0 15 28 | B1->B0 | 2323 2b2b | 0 1 | (1 0) (1 0)
3519 13:59:49.406264 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 13:59:49.409761 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 13:59:49.412921 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 13:59:49.419900 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 13:59:49.423180 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 13:59:49.426590 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 13:59:49.433271 1 0 24 | B1->B0 | 3939 2828 | 0 0 | (0 0) (0 0)
3526 13:59:49.436406 1 0 28 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
3527 13:59:49.439460 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 13:59:49.446357 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 13:59:49.449527 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 13:59:49.452945 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 13:59:49.459263 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 13:59:49.462765 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 13:59:49.466530 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3534 13:59:49.473013 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3535 13:59:49.476394 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 13:59:49.479170 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 13:59:49.486212 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 13:59:49.489755 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 13:59:49.492596 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 13:59:49.499290 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 13:59:49.502624 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 13:59:49.505933 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 13:59:49.512618 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 13:59:49.515865 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 13:59:49.519186 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 13:59:49.522890 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 13:59:49.529427 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 13:59:49.532703 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 13:59:49.535678 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3550 13:59:49.542641 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 13:59:49.545973 Total UI for P1: 0, mck2ui 16
3552 13:59:49.549221 best dqsien dly found for B0: ( 1, 3, 24)
3553 13:59:49.552547 Total UI for P1: 0, mck2ui 16
3554 13:59:49.555759 best dqsien dly found for B1: ( 1, 3, 24)
3555 13:59:49.558962 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3556 13:59:49.562447 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3557 13:59:49.563021
3558 13:59:49.565773 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3559 13:59:49.568932 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3560 13:59:49.572461 [Gating] SW calibration Done
3561 13:59:49.573029 ==
3562 13:59:49.575555 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 13:59:49.578690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 13:59:49.579164 ==
3565 13:59:49.582461 RX Vref Scan: 0
3566 13:59:49.583068
3567 13:59:49.583455 RX Vref 0 -> 0, step: 1
3568 13:59:49.585877
3569 13:59:49.586479 RX Delay -40 -> 252, step: 8
3570 13:59:49.592573 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3571 13:59:49.595720 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3572 13:59:49.599028 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3573 13:59:49.602299 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3574 13:59:49.605593 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3575 13:59:49.609376 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3576 13:59:49.615571 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3577 13:59:49.619159 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3578 13:59:49.622426 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3579 13:59:49.626111 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3580 13:59:49.629320 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3581 13:59:49.636094 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3582 13:59:49.638737 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3583 13:59:49.642561 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3584 13:59:49.645779 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3585 13:59:49.651934 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3586 13:59:49.652539 ==
3587 13:59:49.655605 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 13:59:49.658641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 13:59:49.659113 ==
3590 13:59:49.659488 DQS Delay:
3591 13:59:49.662092 DQS0 = 0, DQS1 = 0
3592 13:59:49.662562 DQM Delay:
3593 13:59:49.665719 DQM0 = 118, DQM1 = 112
3594 13:59:49.666344 DQ Delay:
3595 13:59:49.669026 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3596 13:59:49.672256 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3597 13:59:49.675331 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3598 13:59:49.678476 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3599 13:59:49.678946
3600 13:59:49.679314
3601 13:59:49.681719 ==
3602 13:59:49.682296 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 13:59:49.688443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 13:59:49.689009 ==
3605 13:59:49.689385
3606 13:59:49.689730
3607 13:59:49.691724 TX Vref Scan disable
3608 13:59:49.692193 == TX Byte 0 ==
3609 13:59:49.695230 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3610 13:59:49.702064 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3611 13:59:49.702653 == TX Byte 1 ==
3612 13:59:49.705297 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3613 13:59:49.711625 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3614 13:59:49.712089 ==
3615 13:59:49.715093 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 13:59:49.718134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 13:59:49.718661 ==
3618 13:59:49.730858 TX Vref=22, minBit 3, minWin=24, winSum=406
3619 13:59:49.733687 TX Vref=24, minBit 1, minWin=25, winSum=416
3620 13:59:49.737211 TX Vref=26, minBit 10, minWin=25, winSum=417
3621 13:59:49.740565 TX Vref=28, minBit 0, minWin=26, winSum=421
3622 13:59:49.743974 TX Vref=30, minBit 3, minWin=26, winSum=425
3623 13:59:49.750379 TX Vref=32, minBit 2, minWin=25, winSum=422
3624 13:59:49.754056 [TxChooseVref] Worse bit 3, Min win 26, Win sum 425, Final Vref 30
3625 13:59:49.754640
3626 13:59:49.756964 Final TX Range 1 Vref 30
3627 13:59:49.757434
3628 13:59:49.757807 ==
3629 13:59:49.760538 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 13:59:49.763314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 13:59:49.766899 ==
3632 13:59:49.767471
3633 13:59:49.767843
3634 13:59:49.768187 TX Vref Scan disable
3635 13:59:49.770357 == TX Byte 0 ==
3636 13:59:49.773706 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3637 13:59:49.777013 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3638 13:59:49.780293 == TX Byte 1 ==
3639 13:59:49.783528 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3640 13:59:49.786865 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3641 13:59:49.790124
3642 13:59:49.790690 [DATLAT]
3643 13:59:49.791113 Freq=1200, CH1 RK1
3644 13:59:49.791480
3645 13:59:49.793542 DATLAT Default: 0xd
3646 13:59:49.794051 0, 0xFFFF, sum = 0
3647 13:59:49.797165 1, 0xFFFF, sum = 0
3648 13:59:49.797758 2, 0xFFFF, sum = 0
3649 13:59:49.800566 3, 0xFFFF, sum = 0
3650 13:59:49.803793 4, 0xFFFF, sum = 0
3651 13:59:49.804278 5, 0xFFFF, sum = 0
3652 13:59:49.807209 6, 0xFFFF, sum = 0
3653 13:59:49.807811 7, 0xFFFF, sum = 0
3654 13:59:49.810112 8, 0xFFFF, sum = 0
3655 13:59:49.810589 9, 0xFFFF, sum = 0
3656 13:59:49.813631 10, 0xFFFF, sum = 0
3657 13:59:49.814168 11, 0xFFFF, sum = 0
3658 13:59:49.816820 12, 0x0, sum = 1
3659 13:59:49.817297 13, 0x0, sum = 2
3660 13:59:49.820266 14, 0x0, sum = 3
3661 13:59:49.820748 15, 0x0, sum = 4
3662 13:59:49.821134 best_step = 13
3663 13:59:49.821484
3664 13:59:49.823760 ==
3665 13:59:49.827317 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 13:59:49.830124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 13:59:49.830607 ==
3668 13:59:49.830983 RX Vref Scan: 0
3669 13:59:49.831334
3670 13:59:49.833505 RX Vref 0 -> 0, step: 1
3671 13:59:49.833993
3672 13:59:49.837165 RX Delay -13 -> 252, step: 4
3673 13:59:49.840247 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3674 13:59:49.846628 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3675 13:59:49.850236 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3676 13:59:49.853730 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3677 13:59:49.857098 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3678 13:59:49.859963 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3679 13:59:49.866961 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3680 13:59:49.870347 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3681 13:59:49.873401 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3682 13:59:49.877105 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3683 13:59:49.880058 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3684 13:59:49.886831 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3685 13:59:49.890213 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3686 13:59:49.893265 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3687 13:59:49.896479 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3688 13:59:49.900268 iDelay=191, Bit 15, Center 124 (59 ~ 190) 132
3689 13:59:49.900838 ==
3690 13:59:49.903547 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 13:59:49.910000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 13:59:49.910574 ==
3693 13:59:49.910954 DQS Delay:
3694 13:59:49.913286 DQS0 = 0, DQS1 = 0
3695 13:59:49.913760 DQM Delay:
3696 13:59:49.917074 DQM0 = 119, DQM1 = 113
3697 13:59:49.917642 DQ Delay:
3698 13:59:49.920018 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3699 13:59:49.923455 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =116
3700 13:59:49.926572 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3701 13:59:49.930169 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3702 13:59:49.930732
3703 13:59:49.931110
3704 13:59:49.939848 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
3705 13:59:49.940423 CH1 RK1: MR19=403, MR18=6EA
3706 13:59:49.946633 CH1_RK1: MR19=0x403, MR18=0x6EA, DQSOSC=407, MR23=63, INC=39, DEC=26
3707 13:59:49.950100 [RxdqsGatingPostProcess] freq 1200
3708 13:59:49.956286 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3709 13:59:49.959432 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 13:59:49.962894 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 13:59:49.966337 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 13:59:49.970107 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 13:59:49.972830 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 13:59:49.973398 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 13:59:49.976816 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 13:59:49.979821 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 13:59:49.983388 Pre-setting of DQS Precalculation
3718 13:59:49.989658 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3719 13:59:49.996220 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3720 13:59:50.002805 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3721 13:59:50.003384
3722 13:59:50.003780
3723 13:59:50.006285 [Calibration Summary] 2400 Mbps
3724 13:59:50.006856 CH 0, Rank 0
3725 13:59:50.009376 SW Impedance : PASS
3726 13:59:50.013030 DUTY Scan : NO K
3727 13:59:50.013679 ZQ Calibration : PASS
3728 13:59:50.016383 Jitter Meter : NO K
3729 13:59:50.019610 CBT Training : PASS
3730 13:59:50.020085 Write leveling : PASS
3731 13:59:50.023459 RX DQS gating : PASS
3732 13:59:50.026526 RX DQ/DQS(RDDQC) : PASS
3733 13:59:50.027091 TX DQ/DQS : PASS
3734 13:59:50.029738 RX DATLAT : PASS
3735 13:59:50.032605 RX DQ/DQS(Engine): PASS
3736 13:59:50.033084 TX OE : NO K
3737 13:59:50.036050 All Pass.
3738 13:59:50.036519
3739 13:59:50.036890 CH 0, Rank 1
3740 13:59:50.039604 SW Impedance : PASS
3741 13:59:50.040080 DUTY Scan : NO K
3742 13:59:50.043207 ZQ Calibration : PASS
3743 13:59:50.046575 Jitter Meter : NO K
3744 13:59:50.047146 CBT Training : PASS
3745 13:59:50.049525 Write leveling : PASS
3746 13:59:50.050132 RX DQS gating : PASS
3747 13:59:50.052799 RX DQ/DQS(RDDQC) : PASS
3748 13:59:50.056503 TX DQ/DQS : PASS
3749 13:59:50.057071 RX DATLAT : PASS
3750 13:59:50.059519 RX DQ/DQS(Engine): PASS
3751 13:59:50.062982 TX OE : NO K
3752 13:59:50.063452 All Pass.
3753 13:59:50.063818
3754 13:59:50.064171 CH 1, Rank 0
3755 13:59:50.066062 SW Impedance : PASS
3756 13:59:50.069553 DUTY Scan : NO K
3757 13:59:50.070189 ZQ Calibration : PASS
3758 13:59:50.072791 Jitter Meter : NO K
3759 13:59:50.076245 CBT Training : PASS
3760 13:59:50.076843 Write leveling : PASS
3761 13:59:50.079300 RX DQS gating : PASS
3762 13:59:50.082886 RX DQ/DQS(RDDQC) : PASS
3763 13:59:50.083455 TX DQ/DQS : PASS
3764 13:59:50.086315 RX DATLAT : PASS
3765 13:59:50.089562 RX DQ/DQS(Engine): PASS
3766 13:59:50.090070 TX OE : NO K
3767 13:59:50.090449 All Pass.
3768 13:59:50.093072
3769 13:59:50.093665 CH 1, Rank 1
3770 13:59:50.096137 SW Impedance : PASS
3771 13:59:50.096612 DUTY Scan : NO K
3772 13:59:50.099718 ZQ Calibration : PASS
3773 13:59:50.100300 Jitter Meter : NO K
3774 13:59:50.102813 CBT Training : PASS
3775 13:59:50.106300 Write leveling : PASS
3776 13:59:50.106900 RX DQS gating : PASS
3777 13:59:50.109212 RX DQ/DQS(RDDQC) : PASS
3778 13:59:50.112891 TX DQ/DQS : PASS
3779 13:59:50.113479 RX DATLAT : PASS
3780 13:59:50.116359 RX DQ/DQS(Engine): PASS
3781 13:59:50.119341 TX OE : NO K
3782 13:59:50.119826 All Pass.
3783 13:59:50.120301
3784 13:59:50.122492 DramC Write-DBI off
3785 13:59:50.122971 PER_BANK_REFRESH: Hybrid Mode
3786 13:59:50.126168 TX_TRACKING: ON
3787 13:59:50.135805 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3788 13:59:50.138969 [FAST_K] Save calibration result to emmc
3789 13:59:50.142507 dramc_set_vcore_voltage set vcore to 650000
3790 13:59:50.142976 Read voltage for 600, 5
3791 13:59:50.145796 Vio18 = 0
3792 13:59:50.146453 Vcore = 650000
3793 13:59:50.146838 Vdram = 0
3794 13:59:50.149330 Vddq = 0
3795 13:59:50.149896 Vmddr = 0
3796 13:59:50.152471 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3797 13:59:50.159036 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3798 13:59:50.162546 MEM_TYPE=3, freq_sel=19
3799 13:59:50.166012 sv_algorithm_assistance_LP4_1600
3800 13:59:50.169400 ============ PULL DRAM RESETB DOWN ============
3801 13:59:50.172527 ========== PULL DRAM RESETB DOWN end =========
3802 13:59:50.179174 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3803 13:59:50.182217 ===================================
3804 13:59:50.182781 LPDDR4 DRAM CONFIGURATION
3805 13:59:50.186151 ===================================
3806 13:59:50.189568 EX_ROW_EN[0] = 0x0
3807 13:59:50.190180 EX_ROW_EN[1] = 0x0
3808 13:59:50.192412 LP4Y_EN = 0x0
3809 13:59:50.192877 WORK_FSP = 0x0
3810 13:59:50.195889 WL = 0x2
3811 13:59:50.196462 RL = 0x2
3812 13:59:50.198862 BL = 0x2
3813 13:59:50.202462 RPST = 0x0
3814 13:59:50.203039 RD_PRE = 0x0
3815 13:59:50.205705 WR_PRE = 0x1
3816 13:59:50.206303 WR_PST = 0x0
3817 13:59:50.208813 DBI_WR = 0x0
3818 13:59:50.209344 DBI_RD = 0x0
3819 13:59:50.212401 OTF = 0x1
3820 13:59:50.215989 ===================================
3821 13:59:50.219149 ===================================
3822 13:59:50.219621 ANA top config
3823 13:59:50.222113 ===================================
3824 13:59:50.226207 DLL_ASYNC_EN = 0
3825 13:59:50.229019 ALL_SLAVE_EN = 1
3826 13:59:50.229597 NEW_RANK_MODE = 1
3827 13:59:50.232361 DLL_IDLE_MODE = 1
3828 13:59:50.235940 LP45_APHY_COMB_EN = 1
3829 13:59:50.239020 TX_ODT_DIS = 1
3830 13:59:50.239499 NEW_8X_MODE = 1
3831 13:59:50.242728 ===================================
3832 13:59:50.245682 ===================================
3833 13:59:50.249123 data_rate = 1200
3834 13:59:50.252215 CKR = 1
3835 13:59:50.255831 DQ_P2S_RATIO = 8
3836 13:59:50.259196 ===================================
3837 13:59:50.262431 CA_P2S_RATIO = 8
3838 13:59:50.265721 DQ_CA_OPEN = 0
3839 13:59:50.266223 DQ_SEMI_OPEN = 0
3840 13:59:50.268875 CA_SEMI_OPEN = 0
3841 13:59:50.272148 CA_FULL_RATE = 0
3842 13:59:50.275785 DQ_CKDIV4_EN = 1
3843 13:59:50.278734 CA_CKDIV4_EN = 1
3844 13:59:50.281836 CA_PREDIV_EN = 0
3845 13:59:50.282327 PH8_DLY = 0
3846 13:59:50.285105 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3847 13:59:50.288714 DQ_AAMCK_DIV = 4
3848 13:59:50.292132 CA_AAMCK_DIV = 4
3849 13:59:50.295718 CA_ADMCK_DIV = 4
3850 13:59:50.298826 DQ_TRACK_CA_EN = 0
3851 13:59:50.299354 CA_PICK = 600
3852 13:59:50.301863 CA_MCKIO = 600
3853 13:59:50.305576 MCKIO_SEMI = 0
3854 13:59:50.309154 PLL_FREQ = 2288
3855 13:59:50.312401 DQ_UI_PI_RATIO = 32
3856 13:59:50.315589 CA_UI_PI_RATIO = 0
3857 13:59:50.318846 ===================================
3858 13:59:50.322128 ===================================
3859 13:59:50.322707 memory_type:LPDDR4
3860 13:59:50.325495 GP_NUM : 10
3861 13:59:50.328997 SRAM_EN : 1
3862 13:59:50.329568 MD32_EN : 0
3863 13:59:50.332006 ===================================
3864 13:59:50.335244 [ANA_INIT] >>>>>>>>>>>>>>
3865 13:59:50.338347 <<<<<< [CONFIGURE PHASE]: ANA_TX
3866 13:59:50.341637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3867 13:59:50.345156 ===================================
3868 13:59:50.348142 data_rate = 1200,PCW = 0X5800
3869 13:59:50.351759 ===================================
3870 13:59:50.355011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3871 13:59:50.358193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 13:59:50.365099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 13:59:50.371297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3874 13:59:50.374565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3875 13:59:50.378241 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3876 13:59:50.378776 [ANA_INIT] flow start
3877 13:59:50.381443 [ANA_INIT] PLL >>>>>>>>
3878 13:59:50.384813 [ANA_INIT] PLL <<<<<<<<
3879 13:59:50.385234 [ANA_INIT] MIDPI >>>>>>>>
3880 13:59:50.388707 [ANA_INIT] MIDPI <<<<<<<<
3881 13:59:50.391457 [ANA_INIT] DLL >>>>>>>>
3882 13:59:50.391923 [ANA_INIT] flow end
3883 13:59:50.394587 ============ LP4 DIFF to SE enter ============
3884 13:59:50.401574 ============ LP4 DIFF to SE exit ============
3885 13:59:50.402146 [ANA_INIT] <<<<<<<<<<<<<
3886 13:59:50.404892 [Flow] Enable top DCM control >>>>>
3887 13:59:50.407984 [Flow] Enable top DCM control <<<<<
3888 13:59:50.411220 Enable DLL master slave shuffle
3889 13:59:50.418398 ==============================================================
3890 13:59:50.418985 Gating Mode config
3891 13:59:50.424891 ==============================================================
3892 13:59:50.428273 Config description:
3893 13:59:50.438391 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3894 13:59:50.445047 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3895 13:59:50.448197 SELPH_MODE 0: By rank 1: By Phase
3896 13:59:50.454394 ==============================================================
3897 13:59:50.458063 GAT_TRACK_EN = 1
3898 13:59:50.461233 RX_GATING_MODE = 2
3899 13:59:50.464562 RX_GATING_TRACK_MODE = 2
3900 13:59:50.465034 SELPH_MODE = 1
3901 13:59:50.467730 PICG_EARLY_EN = 1
3902 13:59:50.470996 VALID_LAT_VALUE = 1
3903 13:59:50.477569 ==============================================================
3904 13:59:50.481025 Enter into Gating configuration >>>>
3905 13:59:50.484333 Exit from Gating configuration <<<<
3906 13:59:50.487693 Enter into DVFS_PRE_config >>>>>
3907 13:59:50.497554 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3908 13:59:50.500732 Exit from DVFS_PRE_config <<<<<
3909 13:59:50.504373 Enter into PICG configuration >>>>
3910 13:59:50.507385 Exit from PICG configuration <<<<
3911 13:59:50.511207 [RX_INPUT] configuration >>>>>
3912 13:59:50.514131 [RX_INPUT] configuration <<<<<
3913 13:59:50.517596 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3914 13:59:50.524211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3915 13:59:50.530888 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3916 13:59:50.537361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3917 13:59:50.544034 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 13:59:50.547289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 13:59:50.554008 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3920 13:59:50.557467 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3921 13:59:50.560566 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3922 13:59:50.563712 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3923 13:59:50.567085 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3924 13:59:50.573589 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 13:59:50.577022 ===================================
3926 13:59:50.580367 LPDDR4 DRAM CONFIGURATION
3927 13:59:50.583545 ===================================
3928 13:59:50.584012 EX_ROW_EN[0] = 0x0
3929 13:59:50.587526 EX_ROW_EN[1] = 0x0
3930 13:59:50.588096 LP4Y_EN = 0x0
3931 13:59:50.590541 WORK_FSP = 0x0
3932 13:59:50.591105 WL = 0x2
3933 13:59:50.593599 RL = 0x2
3934 13:59:50.594100 BL = 0x2
3935 13:59:50.596970 RPST = 0x0
3936 13:59:50.597431 RD_PRE = 0x0
3937 13:59:50.600173 WR_PRE = 0x1
3938 13:59:50.600639 WR_PST = 0x0
3939 13:59:50.603909 DBI_WR = 0x0
3940 13:59:50.604464 DBI_RD = 0x0
3941 13:59:50.607257 OTF = 0x1
3942 13:59:50.610602 ===================================
3943 13:59:50.613551 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3944 13:59:50.617080 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3945 13:59:50.623514 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 13:59:50.626967 ===================================
3947 13:59:50.627533 LPDDR4 DRAM CONFIGURATION
3948 13:59:50.630322 ===================================
3949 13:59:50.633594 EX_ROW_EN[0] = 0x10
3950 13:59:50.636943 EX_ROW_EN[1] = 0x0
3951 13:59:50.637502 LP4Y_EN = 0x0
3952 13:59:50.640130 WORK_FSP = 0x0
3953 13:59:50.640592 WL = 0x2
3954 13:59:50.643529 RL = 0x2
3955 13:59:50.644009 BL = 0x2
3956 13:59:50.646981 RPST = 0x0
3957 13:59:50.647540 RD_PRE = 0x0
3958 13:59:50.650383 WR_PRE = 0x1
3959 13:59:50.650939 WR_PST = 0x0
3960 13:59:50.653578 DBI_WR = 0x0
3961 13:59:50.654078 DBI_RD = 0x0
3962 13:59:50.656630 OTF = 0x1
3963 13:59:50.660380 ===================================
3964 13:59:50.666745 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3965 13:59:50.670192 nWR fixed to 30
3966 13:59:50.673106 [ModeRegInit_LP4] CH0 RK0
3967 13:59:50.673663 [ModeRegInit_LP4] CH0 RK1
3968 13:59:50.676557 [ModeRegInit_LP4] CH1 RK0
3969 13:59:50.680000 [ModeRegInit_LP4] CH1 RK1
3970 13:59:50.680505 match AC timing 17
3971 13:59:50.686375 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3972 13:59:50.690191 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3973 13:59:50.693140 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3974 13:59:50.699965 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3975 13:59:50.702959 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3976 13:59:50.703423 ==
3977 13:59:50.706787 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 13:59:50.710070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 13:59:50.710646 ==
3980 13:59:50.716758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3981 13:59:50.723113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3982 13:59:50.726570 [CA 0] Center 36 (5~67) winsize 63
3983 13:59:50.729829 [CA 1] Center 36 (6~67) winsize 62
3984 13:59:50.733187 [CA 2] Center 34 (4~65) winsize 62
3985 13:59:50.736672 [CA 3] Center 34 (4~65) winsize 62
3986 13:59:50.740123 [CA 4] Center 33 (3~64) winsize 62
3987 13:59:50.743451 [CA 5] Center 33 (3~64) winsize 62
3988 13:59:50.744026
3989 13:59:50.746851 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3990 13:59:50.747429
3991 13:59:50.749746 [CATrainingPosCal] consider 1 rank data
3992 13:59:50.752974 u2DelayCellTimex100 = 270/100 ps
3993 13:59:50.756541 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3994 13:59:50.759722 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3995 13:59:50.763053 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 13:59:50.766336 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3997 13:59:50.769664 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 13:59:50.773155 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 13:59:50.773744
4000 13:59:50.779697 CA PerBit enable=1, Macro0, CA PI delay=33
4001 13:59:50.780257
4002 13:59:50.783013 [CBTSetCACLKResult] CA Dly = 33
4003 13:59:50.783485 CS Dly: 5 (0~36)
4004 13:59:50.783859 ==
4005 13:59:50.786326 Dram Type= 6, Freq= 0, CH_0, rank 1
4006 13:59:50.789648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 13:59:50.790162 ==
4008 13:59:50.796518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 13:59:50.802894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4010 13:59:50.806352 [CA 0] Center 36 (6~67) winsize 62
4011 13:59:50.809867 [CA 1] Center 36 (6~67) winsize 62
4012 13:59:50.812738 [CA 2] Center 35 (5~66) winsize 62
4013 13:59:50.816327 [CA 3] Center 35 (4~66) winsize 63
4014 13:59:50.819574 [CA 4] Center 34 (3~65) winsize 63
4015 13:59:50.822941 [CA 5] Center 34 (3~65) winsize 63
4016 13:59:50.823407
4017 13:59:50.826657 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4018 13:59:50.827131
4019 13:59:50.829259 [CATrainingPosCal] consider 2 rank data
4020 13:59:50.832872 u2DelayCellTimex100 = 270/100 ps
4021 13:59:50.836184 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4022 13:59:50.840753 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4023 13:59:50.842738 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4024 13:59:50.845996 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4025 13:59:50.849583 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 13:59:50.858461 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 13:59:50.858935
4028 13:59:50.859648 CA PerBit enable=1, Macro0, CA PI delay=33
4029 13:59:50.860027
4030 13:59:50.862651 [CBTSetCACLKResult] CA Dly = 33
4031 13:59:50.863077 CS Dly: 5 (0~37)
4032 13:59:50.863417
4033 13:59:50.865936 ----->DramcWriteLeveling(PI) begin...
4034 13:59:50.866394 ==
4035 13:59:50.869576 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 13:59:50.876186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 13:59:50.876725 ==
4038 13:59:50.877073 Write leveling (Byte 0): 35 => 35
4039 13:59:50.879327 Write leveling (Byte 1): 29 => 29
4040 13:59:50.882898 DramcWriteLeveling(PI) end<-----
4041 13:59:50.883371
4042 13:59:50.883971 ==
4043 13:59:50.885883 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 13:59:50.892832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 13:59:50.893371 ==
4046 13:59:50.893753 [Gating] SW mode calibration
4047 13:59:50.902801 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4048 13:59:50.905995 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4049 13:59:50.909084 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 13:59:50.916148 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 13:59:50.919293 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 13:59:50.922586 0 9 12 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 0)
4053 13:59:50.928945 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
4054 13:59:50.932652 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 13:59:50.935461 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 13:59:50.942207 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 13:59:50.945450 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 13:59:50.949070 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 13:59:50.955732 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 13:59:50.959151 0 10 12 | B1->B0 | 2626 3c3c | 0 0 | (0 0) (0 0)
4061 13:59:50.962062 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4062 13:59:50.969163 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 13:59:50.972578 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 13:59:50.975812 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 13:59:50.982548 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 13:59:50.985913 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 13:59:50.989043 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 13:59:50.995363 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4069 13:59:50.998622 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4070 13:59:51.002397 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:59:51.008874 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:59:51.012001 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:59:51.015461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 13:59:51.022329 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 13:59:51.025514 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 13:59:51.029155 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 13:59:51.035451 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 13:59:51.038932 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 13:59:51.042339 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 13:59:51.048812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 13:59:51.052485 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 13:59:51.055459 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 13:59:51.061913 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4084 13:59:51.065079 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4085 13:59:51.068705 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 13:59:51.071994 Total UI for P1: 0, mck2ui 16
4087 13:59:51.075257 best dqsien dly found for B0: ( 0, 13, 10)
4088 13:59:51.078783 Total UI for P1: 0, mck2ui 16
4089 13:59:51.082127 best dqsien dly found for B1: ( 0, 13, 14)
4090 13:59:51.085084 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4091 13:59:51.088936 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4092 13:59:51.089511
4093 13:59:51.092258 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4094 13:59:51.098566 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4095 13:59:51.099137 [Gating] SW calibration Done
4096 13:59:51.101351 ==
4097 13:59:51.101820 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 13:59:51.108145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 13:59:51.108708 ==
4100 13:59:51.109083 RX Vref Scan: 0
4101 13:59:51.109432
4102 13:59:51.111722 RX Vref 0 -> 0, step: 1
4103 13:59:51.112253
4104 13:59:51.114634 RX Delay -230 -> 252, step: 16
4105 13:59:51.118206 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4106 13:59:51.121879 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4107 13:59:51.128514 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4108 13:59:51.131170 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4109 13:59:51.134863 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4110 13:59:51.138036 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4111 13:59:51.141402 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4112 13:59:51.148656 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4113 13:59:51.151647 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4114 13:59:51.154815 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4115 13:59:51.158086 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4116 13:59:51.164864 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4117 13:59:51.168233 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4118 13:59:51.171398 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4119 13:59:51.174791 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4120 13:59:51.181060 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4121 13:59:51.181532 ==
4122 13:59:51.184484 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 13:59:51.187739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 13:59:51.188211 ==
4125 13:59:51.188583 DQS Delay:
4126 13:59:51.191147 DQS0 = 0, DQS1 = 0
4127 13:59:51.191619 DQM Delay:
4128 13:59:51.194569 DQM0 = 50, DQM1 = 42
4129 13:59:51.195039 DQ Delay:
4130 13:59:51.197880 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4131 13:59:51.201179 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4132 13:59:51.204644 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4133 13:59:51.207655 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4134 13:59:51.207899
4135 13:59:51.208092
4136 13:59:51.208271 ==
4137 13:59:51.211041 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 13:59:51.213991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 13:59:51.214355 ==
4140 13:59:51.214566
4141 13:59:51.217503
4142 13:59:51.217695 TX Vref Scan disable
4143 13:59:51.220631 == TX Byte 0 ==
4144 13:59:51.223954 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4145 13:59:51.227296 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4146 13:59:51.230660 == TX Byte 1 ==
4147 13:59:51.234093 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4148 13:59:51.237378 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4149 13:59:51.237575 ==
4150 13:59:51.240793 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 13:59:51.247231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 13:59:51.247396 ==
4153 13:59:51.247527
4154 13:59:51.247647
4155 13:59:51.247762 TX Vref Scan disable
4156 13:59:51.252145 == TX Byte 0 ==
4157 13:59:51.255540 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4158 13:59:51.258728 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4159 13:59:51.262409 == TX Byte 1 ==
4160 13:59:51.265744 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4161 13:59:51.268775 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4162 13:59:51.272129
4163 13:59:51.272292 [DATLAT]
4164 13:59:51.272420 Freq=600, CH0 RK0
4165 13:59:51.272542
4166 13:59:51.275626 DATLAT Default: 0x9
4167 13:59:51.275880 0, 0xFFFF, sum = 0
4168 13:59:51.278902 1, 0xFFFF, sum = 0
4169 13:59:51.279111 2, 0xFFFF, sum = 0
4170 13:59:51.282157 3, 0xFFFF, sum = 0
4171 13:59:51.282357 4, 0xFFFF, sum = 0
4172 13:59:51.285611 5, 0xFFFF, sum = 0
4173 13:59:51.285778 6, 0xFFFF, sum = 0
4174 13:59:51.288864 7, 0xFFFF, sum = 0
4175 13:59:51.289035 8, 0x0, sum = 1
4176 13:59:51.292096 9, 0x0, sum = 2
4177 13:59:51.292285 10, 0x0, sum = 3
4178 13:59:51.295546 11, 0x0, sum = 4
4179 13:59:51.295736 best_step = 9
4180 13:59:51.295881
4181 13:59:51.296019 ==
4182 13:59:51.298863 Dram Type= 6, Freq= 0, CH_0, rank 0
4183 13:59:51.305506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 13:59:51.305723 ==
4185 13:59:51.305895 RX Vref Scan: 1
4186 13:59:51.306082
4187 13:59:51.308692 RX Vref 0 -> 0, step: 1
4188 13:59:51.308912
4189 13:59:51.312154 RX Delay -163 -> 252, step: 8
4190 13:59:51.312379
4191 13:59:51.315681 Set Vref, RX VrefLevel [Byte0]: 59
4192 13:59:51.319205 [Byte1]: 49
4193 13:59:51.319513
4194 13:59:51.322353 Final RX Vref Byte 0 = 59 to rank0
4195 13:59:51.325799 Final RX Vref Byte 1 = 49 to rank0
4196 13:59:51.329208 Final RX Vref Byte 0 = 59 to rank1
4197 13:59:51.332060 Final RX Vref Byte 1 = 49 to rank1==
4198 13:59:51.335645 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 13:59:51.338830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 13:59:51.339304 ==
4201 13:59:51.342246 DQS Delay:
4202 13:59:51.342714 DQS0 = 0, DQS1 = 0
4203 13:59:51.343088 DQM Delay:
4204 13:59:51.345328 DQM0 = 48, DQM1 = 39
4205 13:59:51.345753 DQ Delay:
4206 13:59:51.348732 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4207 13:59:51.352094 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4208 13:59:51.355428 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4209 13:59:51.358469 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4210 13:59:51.358895
4211 13:59:51.359232
4212 13:59:51.368024 [DQSOSCAuto] RK0, (LSB)MR18= 0x5752, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4213 13:59:51.371485 CH0 RK0: MR19=808, MR18=5752
4214 13:59:51.374678 CH0_RK0: MR19=0x808, MR18=0x5752, DQSOSC=393, MR23=63, INC=169, DEC=113
4215 13:59:51.374977
4216 13:59:51.381301 ----->DramcWriteLeveling(PI) begin...
4217 13:59:51.381550 ==
4218 13:59:51.384774 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 13:59:51.388105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 13:59:51.388321 ==
4221 13:59:51.391321 Write leveling (Byte 0): 33 => 33
4222 13:59:51.395218 Write leveling (Byte 1): 28 => 28
4223 13:59:51.398105 DramcWriteLeveling(PI) end<-----
4224 13:59:51.398531
4225 13:59:51.398865 ==
4226 13:59:51.401547 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 13:59:51.404949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 13:59:51.405376 ==
4229 13:59:51.408225 [Gating] SW mode calibration
4230 13:59:51.414733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4231 13:59:51.422010 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4232 13:59:51.424874 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 13:59:51.428357 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 13:59:51.431490 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4235 13:59:51.438451 0 9 12 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 1)
4236 13:59:51.441415 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4237 13:59:51.444998 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 13:59:51.451595 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 13:59:51.454631 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 13:59:51.458367 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 13:59:51.464997 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 13:59:51.468065 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 13:59:51.471519 0 10 12 | B1->B0 | 2f2f 2f2f | 1 0 | (0 0) (0 0)
4244 13:59:51.477978 0 10 16 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
4245 13:59:51.481664 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 13:59:51.484801 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 13:59:51.491776 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 13:59:51.494979 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 13:59:51.497916 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 13:59:51.504945 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 13:59:51.507975 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4252 13:59:51.511346 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 13:59:51.517719 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 13:59:51.521272 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 13:59:51.524592 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 13:59:51.531065 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 13:59:51.534662 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 13:59:51.538049 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 13:59:51.544484 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 13:59:51.547981 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 13:59:51.551282 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 13:59:51.557514 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 13:59:51.560922 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 13:59:51.564376 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 13:59:51.571125 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 13:59:51.574346 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 13:59:51.577553 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4268 13:59:51.584527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 13:59:51.585101 Total UI for P1: 0, mck2ui 16
4270 13:59:51.591355 best dqsien dly found for B0: ( 0, 13, 14)
4271 13:59:51.591928 Total UI for P1: 0, mck2ui 16
4272 13:59:51.594447 best dqsien dly found for B1: ( 0, 13, 12)
4273 13:59:51.600810 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4274 13:59:51.604420 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4275 13:59:51.604984
4276 13:59:51.607635 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4277 13:59:51.610569 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4278 13:59:51.614204 [Gating] SW calibration Done
4279 13:59:51.614771 ==
4280 13:59:51.617438 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 13:59:51.621065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 13:59:51.621640 ==
4283 13:59:51.624071 RX Vref Scan: 0
4284 13:59:51.624534
4285 13:59:51.624895 RX Vref 0 -> 0, step: 1
4286 13:59:51.625240
4287 13:59:51.627748 RX Delay -230 -> 252, step: 16
4288 13:59:51.631126 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4289 13:59:51.637348 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4290 13:59:51.640576 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4291 13:59:51.644084 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4292 13:59:51.647717 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4293 13:59:51.653876 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4294 13:59:51.657348 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4295 13:59:51.660486 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4296 13:59:51.663972 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4297 13:59:51.667242 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4298 13:59:51.673732 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4299 13:59:51.677350 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4300 13:59:51.680502 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4301 13:59:51.683575 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4302 13:59:51.690263 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4303 13:59:51.693818 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4304 13:59:51.694445 ==
4305 13:59:51.696946 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 13:59:51.700513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 13:59:51.701107 ==
4308 13:59:51.703807 DQS Delay:
4309 13:59:51.704378 DQS0 = 0, DQS1 = 0
4310 13:59:51.704756 DQM Delay:
4311 13:59:51.707097 DQM0 = 50, DQM1 = 42
4312 13:59:51.707627 DQ Delay:
4313 13:59:51.710584 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4314 13:59:51.713738 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4315 13:59:51.717063 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4316 13:59:51.720792 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4317 13:59:51.721385
4318 13:59:51.721764
4319 13:59:51.722169 ==
4320 13:59:51.724286 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 13:59:51.730644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 13:59:51.731226 ==
4323 13:59:51.731606
4324 13:59:51.731952
4325 13:59:51.732282 TX Vref Scan disable
4326 13:59:51.734297 == TX Byte 0 ==
4327 13:59:51.737217 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4328 13:59:51.744088 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4329 13:59:51.744665 == TX Byte 1 ==
4330 13:59:51.747693 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4331 13:59:51.754004 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4332 13:59:51.754610 ==
4333 13:59:51.757360 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 13:59:51.760846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 13:59:51.761429 ==
4336 13:59:51.761806
4337 13:59:51.762222
4338 13:59:51.763753 TX Vref Scan disable
4339 13:59:51.767415 == TX Byte 0 ==
4340 13:59:51.770710 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4341 13:59:51.774172 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4342 13:59:51.777704 == TX Byte 1 ==
4343 13:59:51.781006 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4344 13:59:51.783925 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4345 13:59:51.784398
4346 13:59:51.784790 [DATLAT]
4347 13:59:51.787274 Freq=600, CH0 RK1
4348 13:59:51.787746
4349 13:59:51.788119 DATLAT Default: 0x9
4350 13:59:51.790738 0, 0xFFFF, sum = 0
4351 13:59:51.791322 1, 0xFFFF, sum = 0
4352 13:59:51.794173 2, 0xFFFF, sum = 0
4353 13:59:51.797494 3, 0xFFFF, sum = 0
4354 13:59:51.798125 4, 0xFFFF, sum = 0
4355 13:59:51.801193 5, 0xFFFF, sum = 0
4356 13:59:51.801781 6, 0xFFFF, sum = 0
4357 13:59:51.803962 7, 0xFFFF, sum = 0
4358 13:59:51.804546 8, 0x0, sum = 1
4359 13:59:51.804930 9, 0x0, sum = 2
4360 13:59:51.807071 10, 0x0, sum = 3
4361 13:59:51.807555 11, 0x0, sum = 4
4362 13:59:51.810398 best_step = 9
4363 13:59:51.810853
4364 13:59:51.811213 ==
4365 13:59:51.813865 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 13:59:51.817140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 13:59:51.817794 ==
4368 13:59:51.820359 RX Vref Scan: 0
4369 13:59:51.820811
4370 13:59:51.821173 RX Vref 0 -> 0, step: 1
4371 13:59:51.821512
4372 13:59:51.823630 RX Delay -179 -> 252, step: 8
4373 13:59:51.831837 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4374 13:59:51.834464 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4375 13:59:51.838007 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4376 13:59:51.841352 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4377 13:59:51.847667 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4378 13:59:51.851222 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4379 13:59:51.854357 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4380 13:59:51.857826 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4381 13:59:51.860913 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4382 13:59:51.867971 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4383 13:59:51.870920 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4384 13:59:51.874324 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4385 13:59:51.877670 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4386 13:59:51.884428 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4387 13:59:51.887558 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4388 13:59:51.890741 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4389 13:59:51.891199 ==
4390 13:59:51.894523 Dram Type= 6, Freq= 0, CH_0, rank 1
4391 13:59:51.897752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 13:59:51.898361 ==
4393 13:59:51.901118 DQS Delay:
4394 13:59:51.901676 DQS0 = 0, DQS1 = 0
4395 13:59:51.904260 DQM Delay:
4396 13:59:51.904714 DQM0 = 47, DQM1 = 41
4397 13:59:51.905073 DQ Delay:
4398 13:59:51.907829 DQ0 =44, DQ1 =48, DQ2 =40, DQ3 =44
4399 13:59:51.911013 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4400 13:59:51.914382 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4401 13:59:51.917694 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =44
4402 13:59:51.918377
4403 13:59:51.918757
4404 13:59:51.927945 [DQSOSCAuto] RK1, (LSB)MR18= 0x6635, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4405 13:59:51.931299 CH0 RK1: MR19=808, MR18=6635
4406 13:59:51.934323 CH0_RK1: MR19=0x808, MR18=0x6635, DQSOSC=390, MR23=63, INC=172, DEC=114
4407 13:59:51.937498 [RxdqsGatingPostProcess] freq 600
4408 13:59:51.944355 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4409 13:59:51.947481 Pre-setting of DQS Precalculation
4410 13:59:51.950924 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4411 13:59:51.951487 ==
4412 13:59:51.954656 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 13:59:51.961176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 13:59:51.961750 ==
4415 13:59:51.964485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 13:59:51.970786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4417 13:59:51.974040 [CA 0] Center 35 (5~66) winsize 62
4418 13:59:51.977456 [CA 1] Center 35 (5~66) winsize 62
4419 13:59:51.980972 [CA 2] Center 34 (3~65) winsize 63
4420 13:59:51.984025 [CA 3] Center 33 (3~64) winsize 62
4421 13:59:51.987334 [CA 4] Center 33 (3~64) winsize 62
4422 13:59:51.990605 [CA 5] Center 33 (3~64) winsize 62
4423 13:59:51.991067
4424 13:59:51.993803 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4425 13:59:51.994300
4426 13:59:51.997561 [CATrainingPosCal] consider 1 rank data
4427 13:59:52.001036 u2DelayCellTimex100 = 270/100 ps
4428 13:59:52.004476 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4429 13:59:52.007260 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 13:59:52.014148 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4431 13:59:52.017458 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 13:59:52.020992 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 13:59:52.023896 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 13:59:52.024390
4435 13:59:52.027396 CA PerBit enable=1, Macro0, CA PI delay=33
4436 13:59:52.027980
4437 13:59:52.030473 [CBTSetCACLKResult] CA Dly = 33
4438 13:59:52.030946 CS Dly: 4 (0~35)
4439 13:59:52.031326 ==
4440 13:59:52.034133 Dram Type= 6, Freq= 0, CH_1, rank 1
4441 13:59:52.040999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 13:59:52.041589 ==
4443 13:59:52.043943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4444 13:59:52.050786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4445 13:59:52.054396 [CA 0] Center 35 (5~66) winsize 62
4446 13:59:52.057532 [CA 1] Center 35 (5~66) winsize 62
4447 13:59:52.060582 [CA 2] Center 34 (4~65) winsize 62
4448 13:59:52.064402 [CA 3] Center 34 (4~65) winsize 62
4449 13:59:52.067501 [CA 4] Center 34 (4~65) winsize 62
4450 13:59:52.070669 [CA 5] Center 33 (3~64) winsize 62
4451 13:59:52.071144
4452 13:59:52.074196 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4453 13:59:52.074672
4454 13:59:52.077528 [CATrainingPosCal] consider 2 rank data
4455 13:59:52.080733 u2DelayCellTimex100 = 270/100 ps
4456 13:59:52.084105 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4457 13:59:52.090579 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 13:59:52.093838 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4459 13:59:52.097059 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4460 13:59:52.100472 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4461 13:59:52.104142 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 13:59:52.104702
4463 13:59:52.107553 CA PerBit enable=1, Macro0, CA PI delay=33
4464 13:59:52.108138
4465 13:59:52.110404 [CBTSetCACLKResult] CA Dly = 33
4466 13:59:52.110997 CS Dly: 5 (0~37)
4467 13:59:52.113919
4468 13:59:52.117373 ----->DramcWriteLeveling(PI) begin...
4469 13:59:52.117996 ==
4470 13:59:52.120137 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 13:59:52.123658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 13:59:52.124092 ==
4473 13:59:52.126847 Write leveling (Byte 0): 28 => 28
4474 13:59:52.130376 Write leveling (Byte 1): 32 => 32
4475 13:59:52.134031 DramcWriteLeveling(PI) end<-----
4476 13:59:52.134575
4477 13:59:52.134920 ==
4478 13:59:52.136684 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 13:59:52.139965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 13:59:52.140398 ==
4481 13:59:52.143379 [Gating] SW mode calibration
4482 13:59:52.150465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4483 13:59:52.157042 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4484 13:59:52.160732 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 13:59:52.163807 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 13:59:52.170465 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4487 13:59:52.173612 0 9 12 | B1->B0 | 2e2e 2d2d | 0 0 | (0 0) (0 0)
4488 13:59:52.177079 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 13:59:52.183526 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 13:59:52.186590 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 13:59:52.190206 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 13:59:52.193415 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 13:59:52.199940 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 13:59:52.203375 0 10 8 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
4495 13:59:52.206611 0 10 12 | B1->B0 | 3a3a 3838 | 1 0 | (0 0) (0 0)
4496 13:59:52.213674 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 13:59:52.217041 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 13:59:52.220122 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 13:59:52.227095 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 13:59:52.230361 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 13:59:52.233723 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 13:59:52.240129 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4503 13:59:52.243007 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4504 13:59:52.246571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:59:52.253232 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 13:59:52.256374 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 13:59:52.259934 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 13:59:52.266867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 13:59:52.270179 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 13:59:52.272956 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 13:59:52.279333 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 13:59:52.282922 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 13:59:52.285877 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 13:59:52.292773 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 13:59:52.296020 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 13:59:52.299156 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 13:59:52.306178 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 13:59:52.309045 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4519 13:59:52.312691 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4520 13:59:52.319159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 13:59:52.319808 Total UI for P1: 0, mck2ui 16
4522 13:59:52.326107 best dqsien dly found for B0: ( 0, 13, 10)
4523 13:59:52.326683 Total UI for P1: 0, mck2ui 16
4524 13:59:52.332676 best dqsien dly found for B1: ( 0, 13, 10)
4525 13:59:52.335806 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4526 13:59:52.339732 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4527 13:59:52.340266
4528 13:59:52.342577 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4529 13:59:52.346544 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4530 13:59:52.349826 [Gating] SW calibration Done
4531 13:59:52.350384 ==
4532 13:59:52.352832 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 13:59:52.356114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 13:59:52.356548 ==
4535 13:59:52.359691 RX Vref Scan: 0
4536 13:59:52.360231
4537 13:59:52.360577 RX Vref 0 -> 0, step: 1
4538 13:59:52.360967
4539 13:59:52.362795 RX Delay -230 -> 252, step: 16
4540 13:59:52.366105 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4541 13:59:52.372535 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4542 13:59:52.376020 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4543 13:59:52.379589 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4544 13:59:52.382471 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4545 13:59:52.389114 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4546 13:59:52.392600 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4547 13:59:52.395653 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4548 13:59:52.399073 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4549 13:59:52.402430 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4550 13:59:52.408807 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4551 13:59:52.412029 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4552 13:59:52.415715 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4553 13:59:52.418698 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4554 13:59:52.425677 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4555 13:59:52.428916 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4556 13:59:52.429344 ==
4557 13:59:52.432385 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 13:59:52.435473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 13:59:52.435904 ==
4560 13:59:52.438961 DQS Delay:
4561 13:59:52.439409 DQS0 = 0, DQS1 = 0
4562 13:59:52.439754 DQM Delay:
4563 13:59:52.442335 DQM0 = 52, DQM1 = 41
4564 13:59:52.442877 DQ Delay:
4565 13:59:52.445742 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4566 13:59:52.449116 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4567 13:59:52.452470 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4568 13:59:52.455851 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4569 13:59:52.456391
4570 13:59:52.456740
4571 13:59:52.457061 ==
4572 13:59:52.458653 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 13:59:52.465687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 13:59:52.466275 ==
4575 13:59:52.466624
4576 13:59:52.466941
4577 13:59:52.467247 TX Vref Scan disable
4578 13:59:52.469458 == TX Byte 0 ==
4579 13:59:52.472440 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4580 13:59:52.479186 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4581 13:59:52.479729 == TX Byte 1 ==
4582 13:59:52.482366 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4583 13:59:52.489003 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4584 13:59:52.489435 ==
4585 13:59:52.492328 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 13:59:52.495549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 13:59:52.495987 ==
4588 13:59:52.496331
4589 13:59:52.496647
4590 13:59:52.499043 TX Vref Scan disable
4591 13:59:52.502234 == TX Byte 0 ==
4592 13:59:52.505838 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4593 13:59:52.509205 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4594 13:59:52.512170 == TX Byte 1 ==
4595 13:59:52.515437 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4596 13:59:52.518799 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4597 13:59:52.519252
4598 13:59:52.519591 [DATLAT]
4599 13:59:52.522420 Freq=600, CH1 RK0
4600 13:59:52.522850
4601 13:59:52.523192 DATLAT Default: 0x9
4602 13:59:52.525513 0, 0xFFFF, sum = 0
4603 13:59:52.526012 1, 0xFFFF, sum = 0
4604 13:59:52.529272 2, 0xFFFF, sum = 0
4605 13:59:52.532608 3, 0xFFFF, sum = 0
4606 13:59:52.533144 4, 0xFFFF, sum = 0
4607 13:59:52.535679 5, 0xFFFF, sum = 0
4608 13:59:52.536115 6, 0xFFFF, sum = 0
4609 13:59:52.539037 7, 0xFFFF, sum = 0
4610 13:59:52.539475 8, 0x0, sum = 1
4611 13:59:52.539825 9, 0x0, sum = 2
4612 13:59:52.542514 10, 0x0, sum = 3
4613 13:59:52.542952 11, 0x0, sum = 4
4614 13:59:52.545741 best_step = 9
4615 13:59:52.546309
4616 13:59:52.546654 ==
4617 13:59:52.548974 Dram Type= 6, Freq= 0, CH_1, rank 0
4618 13:59:52.552440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 13:59:52.552967 ==
4620 13:59:52.555679 RX Vref Scan: 1
4621 13:59:52.556209
4622 13:59:52.556555 RX Vref 0 -> 0, step: 1
4623 13:59:52.556879
4624 13:59:52.558800 RX Delay -179 -> 252, step: 8
4625 13:59:52.559277
4626 13:59:52.562294 Set Vref, RX VrefLevel [Byte0]: 53
4627 13:59:52.565796 [Byte1]: 50
4628 13:59:52.570155
4629 13:59:52.570675 Final RX Vref Byte 0 = 53 to rank0
4630 13:59:52.573056 Final RX Vref Byte 1 = 50 to rank0
4631 13:59:52.576358 Final RX Vref Byte 0 = 53 to rank1
4632 13:59:52.579736 Final RX Vref Byte 1 = 50 to rank1==
4633 13:59:52.582960 Dram Type= 6, Freq= 0, CH_1, rank 0
4634 13:59:52.589821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 13:59:52.590437 ==
4636 13:59:52.590816 DQS Delay:
4637 13:59:52.591168 DQS0 = 0, DQS1 = 0
4638 13:59:52.593191 DQM Delay:
4639 13:59:52.593752 DQM0 = 48, DQM1 = 41
4640 13:59:52.596103 DQ Delay:
4641 13:59:52.599678 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4642 13:59:52.602718 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4643 13:59:52.606300 DQ8 =32, DQ9 =28, DQ10 =48, DQ11 =32
4644 13:59:52.609492 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4645 13:59:52.610077
4646 13:59:52.610432
4647 13:59:52.615798 [DQSOSCAuto] RK0, (LSB)MR18= 0x4971, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 396 ps
4648 13:59:52.619285 CH1 RK0: MR19=808, MR18=4971
4649 13:59:52.625923 CH1_RK0: MR19=0x808, MR18=0x4971, DQSOSC=388, MR23=63, INC=174, DEC=116
4650 13:59:52.626397
4651 13:59:52.629325 ----->DramcWriteLeveling(PI) begin...
4652 13:59:52.629913 ==
4653 13:59:52.632500 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 13:59:52.635817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 13:59:52.636280 ==
4656 13:59:52.638965 Write leveling (Byte 0): 29 => 29
4657 13:59:52.642633 Write leveling (Byte 1): 30 => 30
4658 13:59:52.646102 DramcWriteLeveling(PI) end<-----
4659 13:59:52.646640
4660 13:59:52.646984 ==
4661 13:59:52.649009 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 13:59:52.652365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 13:59:52.652950 ==
4664 13:59:52.655827 [Gating] SW mode calibration
4665 13:59:52.662392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4666 13:59:52.669135 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4667 13:59:52.672541 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 13:59:52.678858 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 13:59:52.682333 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
4670 13:59:52.685666 0 9 12 | B1->B0 | 2a2a 2f2f | 0 1 | (0 0) (1 0)
4671 13:59:52.692409 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 13:59:52.695230 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 13:59:52.699143 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 13:59:52.705666 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 13:59:52.708785 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 13:59:52.712099 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 13:59:52.715513 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4678 13:59:52.721827 0 10 12 | B1->B0 | 3b3b 2f2f | 0 0 | (0 0) (0 0)
4679 13:59:52.725303 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4680 13:59:52.728871 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 13:59:52.735068 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 13:59:52.738706 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 13:59:52.741750 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 13:59:52.748745 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 13:59:52.752019 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 13:59:52.755437 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4687 13:59:52.761781 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 13:59:52.765441 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 13:59:52.768523 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 13:59:52.775165 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 13:59:52.778090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 13:59:52.781498 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 13:59:52.788365 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 13:59:52.791944 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 13:59:52.794729 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 13:59:52.801630 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 13:59:52.805044 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 13:59:52.808242 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 13:59:52.814881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 13:59:52.818095 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 13:59:52.821428 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 13:59:52.828166 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4703 13:59:52.828723 Total UI for P1: 0, mck2ui 16
4704 13:59:52.834522 best dqsien dly found for B1: ( 0, 13, 10)
4705 13:59:52.838043 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 13:59:52.841098 Total UI for P1: 0, mck2ui 16
4707 13:59:52.844587 best dqsien dly found for B0: ( 0, 13, 12)
4708 13:59:52.847901 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4709 13:59:52.851430 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4710 13:59:52.851971
4711 13:59:52.854578 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4712 13:59:52.857742 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4713 13:59:52.861368 [Gating] SW calibration Done
4714 13:59:52.861908 ==
4715 13:59:52.864767 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 13:59:52.868135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 13:59:52.871945 ==
4718 13:59:52.872524 RX Vref Scan: 0
4719 13:59:52.872904
4720 13:59:52.874577 RX Vref 0 -> 0, step: 1
4721 13:59:52.875052
4722 13:59:52.877957 RX Delay -230 -> 252, step: 16
4723 13:59:52.881665 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4724 13:59:52.884926 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4725 13:59:52.888163 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4726 13:59:52.891727 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4727 13:59:52.898368 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4728 13:59:52.901511 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4729 13:59:52.904696 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4730 13:59:52.908020 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4731 13:59:52.911443 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4732 13:59:52.918074 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4733 13:59:52.921177 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4734 13:59:52.924623 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4735 13:59:52.928041 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4736 13:59:52.934368 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4737 13:59:52.937745 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4738 13:59:52.940811 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4739 13:59:52.941288 ==
4740 13:59:52.944240 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 13:59:52.950849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 13:59:52.951423 ==
4743 13:59:52.951804 DQS Delay:
4744 13:59:52.952154 DQS0 = 0, DQS1 = 0
4745 13:59:52.954415 DQM Delay:
4746 13:59:52.954992 DQM0 = 52, DQM1 = 44
4747 13:59:52.957587 DQ Delay:
4748 13:59:52.960904 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4749 13:59:52.964533 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4750 13:59:52.967954 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4751 13:59:52.970963 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4752 13:59:52.971541
4753 13:59:52.971915
4754 13:59:52.972262 ==
4755 13:59:52.974059 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 13:59:52.977600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 13:59:52.978119 ==
4758 13:59:52.978499
4759 13:59:52.978846
4760 13:59:52.980675 TX Vref Scan disable
4761 13:59:52.981147 == TX Byte 0 ==
4762 13:59:52.987316 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4763 13:59:52.990850 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4764 13:59:52.991397 == TX Byte 1 ==
4765 13:59:52.997464 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4766 13:59:53.000844 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4767 13:59:53.001347 ==
4768 13:59:53.004252 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 13:59:53.007891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 13:59:53.008440 ==
4771 13:59:53.008789
4772 13:59:53.009107
4773 13:59:53.011174 TX Vref Scan disable
4774 13:59:53.014098 == TX Byte 0 ==
4775 13:59:53.017464 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4776 13:59:53.021309 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4777 13:59:53.024310 == TX Byte 1 ==
4778 13:59:53.027391 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4779 13:59:53.031042 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4780 13:59:53.031584
4781 13:59:53.034267 [DATLAT]
4782 13:59:53.034860 Freq=600, CH1 RK1
4783 13:59:53.035373
4784 13:59:53.037424 DATLAT Default: 0x9
4785 13:59:53.038001 0, 0xFFFF, sum = 0
4786 13:59:53.040862 1, 0xFFFF, sum = 0
4787 13:59:53.041322 2, 0xFFFF, sum = 0
4788 13:59:53.044310 3, 0xFFFF, sum = 0
4789 13:59:53.044854 4, 0xFFFF, sum = 0
4790 13:59:53.047396 5, 0xFFFF, sum = 0
4791 13:59:53.047832 6, 0xFFFF, sum = 0
4792 13:59:53.050735 7, 0xFFFF, sum = 0
4793 13:59:53.051172 8, 0x0, sum = 1
4794 13:59:53.054086 9, 0x0, sum = 2
4795 13:59:53.054524 10, 0x0, sum = 3
4796 13:59:53.057752 11, 0x0, sum = 4
4797 13:59:53.058319 best_step = 9
4798 13:59:53.058665
4799 13:59:53.058984 ==
4800 13:59:53.060740 Dram Type= 6, Freq= 0, CH_1, rank 1
4801 13:59:53.064309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4802 13:59:53.067616 ==
4803 13:59:53.068146 RX Vref Scan: 0
4804 13:59:53.068534
4805 13:59:53.071309 RX Vref 0 -> 0, step: 1
4806 13:59:53.071880
4807 13:59:53.074293 RX Delay -163 -> 252, step: 8
4808 13:59:53.077406 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4809 13:59:53.081135 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4810 13:59:53.087724 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4811 13:59:53.090677 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4812 13:59:53.094654 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4813 13:59:53.097922 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4814 13:59:53.101392 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4815 13:59:53.104873 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4816 13:59:53.111025 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4817 13:59:53.114387 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4818 13:59:53.117908 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4819 13:59:53.121271 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4820 13:59:53.127937 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4821 13:59:53.131026 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4822 13:59:53.134426 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4823 13:59:53.137497 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4824 13:59:53.137992 ==
4825 13:59:53.140551 Dram Type= 6, Freq= 0, CH_1, rank 1
4826 13:59:53.147170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4827 13:59:53.147646 ==
4828 13:59:53.148166 DQS Delay:
4829 13:59:53.151216 DQS0 = 0, DQS1 = 0
4830 13:59:53.151795 DQM Delay:
4831 13:59:53.152179 DQM0 = 48, DQM1 = 42
4832 13:59:53.153858 DQ Delay:
4833 13:59:53.157680 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4834 13:59:53.160602 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4835 13:59:53.164093 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =36
4836 13:59:53.167279 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4837 13:59:53.167756
4838 13:59:53.168130
4839 13:59:53.174281 [DQSOSCAuto] RK1, (LSB)MR18= 0x541b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4840 13:59:53.177298 CH1 RK1: MR19=808, MR18=541B
4841 13:59:53.184169 CH1_RK1: MR19=0x808, MR18=0x541B, DQSOSC=393, MR23=63, INC=169, DEC=113
4842 13:59:53.187320 [RxdqsGatingPostProcess] freq 600
4843 13:59:53.190535 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4844 13:59:53.194151 Pre-setting of DQS Precalculation
4845 13:59:53.200441 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4846 13:59:53.207364 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4847 13:59:53.214101 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4848 13:59:53.214666
4849 13:59:53.215042
4850 13:59:53.217222 [Calibration Summary] 1200 Mbps
4851 13:59:53.217793 CH 0, Rank 0
4852 13:59:53.220639 SW Impedance : PASS
4853 13:59:53.223834 DUTY Scan : NO K
4854 13:59:53.224307 ZQ Calibration : PASS
4855 13:59:53.227313 Jitter Meter : NO K
4856 13:59:53.230624 CBT Training : PASS
4857 13:59:53.231199 Write leveling : PASS
4858 13:59:53.234140 RX DQS gating : PASS
4859 13:59:53.237050 RX DQ/DQS(RDDQC) : PASS
4860 13:59:53.237620 TX DQ/DQS : PASS
4861 13:59:53.240519 RX DATLAT : PASS
4862 13:59:53.243586 RX DQ/DQS(Engine): PASS
4863 13:59:53.244064 TX OE : NO K
4864 13:59:53.244448 All Pass.
4865 13:59:53.247242
4866 13:59:53.247811 CH 0, Rank 1
4867 13:59:53.250061 SW Impedance : PASS
4868 13:59:53.250535 DUTY Scan : NO K
4869 13:59:53.253818 ZQ Calibration : PASS
4870 13:59:53.254422 Jitter Meter : NO K
4871 13:59:53.256709 CBT Training : PASS
4872 13:59:53.260292 Write leveling : PASS
4873 13:59:53.260869 RX DQS gating : PASS
4874 13:59:53.263636 RX DQ/DQS(RDDQC) : PASS
4875 13:59:53.266846 TX DQ/DQS : PASS
4876 13:59:53.267322 RX DATLAT : PASS
4877 13:59:53.270323 RX DQ/DQS(Engine): PASS
4878 13:59:53.273836 TX OE : NO K
4879 13:59:53.274443 All Pass.
4880 13:59:53.274824
4881 13:59:53.275178 CH 1, Rank 0
4882 13:59:53.276717 SW Impedance : PASS
4883 13:59:53.279875 DUTY Scan : NO K
4884 13:59:53.280352 ZQ Calibration : PASS
4885 13:59:53.283288 Jitter Meter : NO K
4886 13:59:53.286525 CBT Training : PASS
4887 13:59:53.286950 Write leveling : PASS
4888 13:59:53.289790 RX DQS gating : PASS
4889 13:59:53.293300 RX DQ/DQS(RDDQC) : PASS
4890 13:59:53.293822 TX DQ/DQS : PASS
4891 13:59:53.296791 RX DATLAT : PASS
4892 13:59:53.299995 RX DQ/DQS(Engine): PASS
4893 13:59:53.300430 TX OE : NO K
4894 13:59:53.300775 All Pass.
4895 13:59:53.303538
4896 13:59:53.304064 CH 1, Rank 1
4897 13:59:53.306885 SW Impedance : PASS
4898 13:59:53.307413 DUTY Scan : NO K
4899 13:59:53.310299 ZQ Calibration : PASS
4900 13:59:53.313192 Jitter Meter : NO K
4901 13:59:53.313719 CBT Training : PASS
4902 13:59:53.316316 Write leveling : PASS
4903 13:59:53.316746 RX DQS gating : PASS
4904 13:59:53.319625 RX DQ/DQS(RDDQC) : PASS
4905 13:59:53.323000 TX DQ/DQS : PASS
4906 13:59:53.323449 RX DATLAT : PASS
4907 13:59:53.326331 RX DQ/DQS(Engine): PASS
4908 13:59:53.329902 TX OE : NO K
4909 13:59:53.330467 All Pass.
4910 13:59:53.330815
4911 13:59:53.333372 DramC Write-DBI off
4912 13:59:53.333903 PER_BANK_REFRESH: Hybrid Mode
4913 13:59:53.336774 TX_TRACKING: ON
4914 13:59:53.343166 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4915 13:59:53.349417 [FAST_K] Save calibration result to emmc
4916 13:59:53.353180 dramc_set_vcore_voltage set vcore to 662500
4917 13:59:53.353755 Read voltage for 933, 3
4918 13:59:53.356317 Vio18 = 0
4919 13:59:53.356785 Vcore = 662500
4920 13:59:53.357160 Vdram = 0
4921 13:59:53.359711 Vddq = 0
4922 13:59:53.360186 Vmddr = 0
4923 13:59:53.363019 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4924 13:59:53.369645 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4925 13:59:53.372955 MEM_TYPE=3, freq_sel=17
4926 13:59:53.376161 sv_algorithm_assistance_LP4_1600
4927 13:59:53.379877 ============ PULL DRAM RESETB DOWN ============
4928 13:59:53.383089 ========== PULL DRAM RESETB DOWN end =========
4929 13:59:53.389341 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4930 13:59:53.389823 ===================================
4931 13:59:53.392854 LPDDR4 DRAM CONFIGURATION
4932 13:59:53.396313 ===================================
4933 13:59:53.399332 EX_ROW_EN[0] = 0x0
4934 13:59:53.399857 EX_ROW_EN[1] = 0x0
4935 13:59:53.402746 LP4Y_EN = 0x0
4936 13:59:53.403223 WORK_FSP = 0x0
4937 13:59:53.406438 WL = 0x3
4938 13:59:53.407020 RL = 0x3
4939 13:59:53.409550 BL = 0x2
4940 13:59:53.413129 RPST = 0x0
4941 13:59:53.413667 RD_PRE = 0x0
4942 13:59:53.416493 WR_PRE = 0x1
4943 13:59:53.417037 WR_PST = 0x0
4944 13:59:53.419576 DBI_WR = 0x0
4945 13:59:53.420008 DBI_RD = 0x0
4946 13:59:53.423070 OTF = 0x1
4947 13:59:53.427216 ===================================
4948 13:59:53.429160 ===================================
4949 13:59:53.429628 ANA top config
4950 13:59:53.432696 ===================================
4951 13:59:53.436080 DLL_ASYNC_EN = 0
4952 13:59:53.439503 ALL_SLAVE_EN = 1
4953 13:59:53.440095 NEW_RANK_MODE = 1
4954 13:59:53.442418 DLL_IDLE_MODE = 1
4955 13:59:53.446023 LP45_APHY_COMB_EN = 1
4956 13:59:53.449001 TX_ODT_DIS = 1
4957 13:59:53.449432 NEW_8X_MODE = 1
4958 13:59:53.452595 ===================================
4959 13:59:53.455958 ===================================
4960 13:59:53.459064 data_rate = 1866
4961 13:59:53.462508 CKR = 1
4962 13:59:53.466036 DQ_P2S_RATIO = 8
4963 13:59:53.469042 ===================================
4964 13:59:53.472571 CA_P2S_RATIO = 8
4965 13:59:53.476002 DQ_CA_OPEN = 0
4966 13:59:53.476477 DQ_SEMI_OPEN = 0
4967 13:59:53.479461 CA_SEMI_OPEN = 0
4968 13:59:53.482856 CA_FULL_RATE = 0
4969 13:59:53.486051 DQ_CKDIV4_EN = 1
4970 13:59:53.489249 CA_CKDIV4_EN = 1
4971 13:59:53.492467 CA_PREDIV_EN = 0
4972 13:59:53.492911 PH8_DLY = 0
4973 13:59:53.496126 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4974 13:59:53.499387 DQ_AAMCK_DIV = 4
4975 13:59:53.502754 CA_AAMCK_DIV = 4
4976 13:59:53.505667 CA_ADMCK_DIV = 4
4977 13:59:53.509018 DQ_TRACK_CA_EN = 0
4978 13:59:53.509444 CA_PICK = 933
4979 13:59:53.513012 CA_MCKIO = 933
4980 13:59:53.515899 MCKIO_SEMI = 0
4981 13:59:53.519018 PLL_FREQ = 3732
4982 13:59:53.522378 DQ_UI_PI_RATIO = 32
4983 13:59:53.525752 CA_UI_PI_RATIO = 0
4984 13:59:53.529286 ===================================
4985 13:59:53.532643 ===================================
4986 13:59:53.533158 memory_type:LPDDR4
4987 13:59:53.535942 GP_NUM : 10
4988 13:59:53.539258 SRAM_EN : 1
4989 13:59:53.539733 MD32_EN : 0
4990 13:59:53.542210 ===================================
4991 13:59:53.545632 [ANA_INIT] >>>>>>>>>>>>>>
4992 13:59:53.549265 <<<<<< [CONFIGURE PHASE]: ANA_TX
4993 13:59:53.552244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4994 13:59:53.555734 ===================================
4995 13:59:53.559089 data_rate = 1866,PCW = 0X8f00
4996 13:59:53.562339 ===================================
4997 13:59:53.565571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4998 13:59:53.568774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4999 13:59:53.575296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5000 13:59:53.578802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5001 13:59:53.582096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5002 13:59:53.585399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5003 13:59:53.588866 [ANA_INIT] flow start
5004 13:59:53.592317 [ANA_INIT] PLL >>>>>>>>
5005 13:59:53.592776 [ANA_INIT] PLL <<<<<<<<
5006 13:59:53.595281 [ANA_INIT] MIDPI >>>>>>>>
5007 13:59:53.599131 [ANA_INIT] MIDPI <<<<<<<<
5008 13:59:53.602123 [ANA_INIT] DLL >>>>>>>>
5009 13:59:53.602572 [ANA_INIT] flow end
5010 13:59:53.605715 ============ LP4 DIFF to SE enter ============
5011 13:59:53.612088 ============ LP4 DIFF to SE exit ============
5012 13:59:53.612647 [ANA_INIT] <<<<<<<<<<<<<
5013 13:59:53.615591 [Flow] Enable top DCM control >>>>>
5014 13:59:53.618875 [Flow] Enable top DCM control <<<<<
5015 13:59:53.622017 Enable DLL master slave shuffle
5016 13:59:53.628718 ==============================================================
5017 13:59:53.629269 Gating Mode config
5018 13:59:53.635649 ==============================================================
5019 13:59:53.638729 Config description:
5020 13:59:53.648611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5021 13:59:53.652401 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5022 13:59:53.658986 SELPH_MODE 0: By rank 1: By Phase
5023 13:59:53.665563 ==============================================================
5024 13:59:53.669139 GAT_TRACK_EN = 1
5025 13:59:53.669807 RX_GATING_MODE = 2
5026 13:59:53.672408 RX_GATING_TRACK_MODE = 2
5027 13:59:53.675750 SELPH_MODE = 1
5028 13:59:53.678635 PICG_EARLY_EN = 1
5029 13:59:53.682253 VALID_LAT_VALUE = 1
5030 13:59:53.688590 ==============================================================
5031 13:59:53.691996 Enter into Gating configuration >>>>
5032 13:59:53.695508 Exit from Gating configuration <<<<
5033 13:59:53.698859 Enter into DVFS_PRE_config >>>>>
5034 13:59:53.708602 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5035 13:59:53.711880 Exit from DVFS_PRE_config <<<<<
5036 13:59:53.715187 Enter into PICG configuration >>>>
5037 13:59:53.718613 Exit from PICG configuration <<<<
5038 13:59:53.722150 [RX_INPUT] configuration >>>>>
5039 13:59:53.725328 [RX_INPUT] configuration <<<<<
5040 13:59:53.728568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5041 13:59:53.735163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5042 13:59:53.741849 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5043 13:59:53.744829 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5044 13:59:53.751379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 13:59:53.758102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 13:59:53.761565 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5047 13:59:53.768452 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5048 13:59:53.771676 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5049 13:59:53.774921 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5050 13:59:53.778217 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5051 13:59:53.784631 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5052 13:59:53.787974 ===================================
5053 13:59:53.788530 LPDDR4 DRAM CONFIGURATION
5054 13:59:53.791287 ===================================
5055 13:59:53.794908 EX_ROW_EN[0] = 0x0
5056 13:59:53.798363 EX_ROW_EN[1] = 0x0
5057 13:59:53.798987 LP4Y_EN = 0x0
5058 13:59:53.801158 WORK_FSP = 0x0
5059 13:59:53.801578 WL = 0x3
5060 13:59:53.804530 RL = 0x3
5061 13:59:53.804949 BL = 0x2
5062 13:59:53.808252 RPST = 0x0
5063 13:59:53.808793 RD_PRE = 0x0
5064 13:59:53.811349 WR_PRE = 0x1
5065 13:59:53.811767 WR_PST = 0x0
5066 13:59:53.814559 DBI_WR = 0x0
5067 13:59:53.814979 DBI_RD = 0x0
5068 13:59:53.818110 OTF = 0x1
5069 13:59:53.821255 ===================================
5070 13:59:53.824595 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5071 13:59:53.827941 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5072 13:59:53.834606 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5073 13:59:53.838008 ===================================
5074 13:59:53.838428 LPDDR4 DRAM CONFIGURATION
5075 13:59:53.841627 ===================================
5076 13:59:53.844875 EX_ROW_EN[0] = 0x10
5077 13:59:53.845297 EX_ROW_EN[1] = 0x0
5078 13:59:53.847988 LP4Y_EN = 0x0
5079 13:59:53.848515 WORK_FSP = 0x0
5080 13:59:53.851145 WL = 0x3
5081 13:59:53.854884 RL = 0x3
5082 13:59:53.855397 BL = 0x2
5083 13:59:53.858133 RPST = 0x0
5084 13:59:53.858625 RD_PRE = 0x0
5085 13:59:53.861421 WR_PRE = 0x1
5086 13:59:53.861839 WR_PST = 0x0
5087 13:59:53.864730 DBI_WR = 0x0
5088 13:59:53.865150 DBI_RD = 0x0
5089 13:59:53.868222 OTF = 0x1
5090 13:59:53.871111 ===================================
5091 13:59:53.874734 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5092 13:59:53.880125 nWR fixed to 30
5093 13:59:53.883550 [ModeRegInit_LP4] CH0 RK0
5094 13:59:53.884082 [ModeRegInit_LP4] CH0 RK1
5095 13:59:53.886612 [ModeRegInit_LP4] CH1 RK0
5096 13:59:53.890479 [ModeRegInit_LP4] CH1 RK1
5097 13:59:53.890924 match AC timing 9
5098 13:59:53.896754 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5099 13:59:53.899634 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5100 13:59:53.902991 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5101 13:59:53.909565 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5102 13:59:53.913157 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5103 13:59:53.913580 ==
5104 13:59:53.916296 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 13:59:53.919496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 13:59:53.919917 ==
5107 13:59:53.926008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 13:59:53.932998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5109 13:59:53.935965 [CA 0] Center 37 (7~68) winsize 62
5110 13:59:53.939413 [CA 1] Center 37 (7~68) winsize 62
5111 13:59:53.942645 [CA 2] Center 35 (5~66) winsize 62
5112 13:59:53.946009 [CA 3] Center 34 (4~65) winsize 62
5113 13:59:53.949320 [CA 4] Center 34 (4~64) winsize 61
5114 13:59:53.953170 [CA 5] Center 33 (3~64) winsize 62
5115 13:59:53.953688
5116 13:59:53.956190 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5117 13:59:53.956612
5118 13:59:53.959474 [CATrainingPosCal] consider 1 rank data
5119 13:59:53.962612 u2DelayCellTimex100 = 270/100 ps
5120 13:59:53.966054 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5121 13:59:53.969603 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5122 13:59:53.972818 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5123 13:59:53.975938 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5124 13:59:53.979647 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5125 13:59:53.986004 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5126 13:59:53.986461
5127 13:59:53.989065 CA PerBit enable=1, Macro0, CA PI delay=33
5128 13:59:53.989486
5129 13:59:53.992530 [CBTSetCACLKResult] CA Dly = 33
5130 13:59:53.992951 CS Dly: 6 (0~37)
5131 13:59:53.993287 ==
5132 13:59:53.996053 Dram Type= 6, Freq= 0, CH_0, rank 1
5133 13:59:54.002660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5134 13:59:54.003083 ==
5135 13:59:54.005644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5136 13:59:54.012703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5137 13:59:54.016009 [CA 0] Center 38 (7~69) winsize 63
5138 13:59:54.018893 [CA 1] Center 38 (8~69) winsize 62
5139 13:59:54.022645 [CA 2] Center 36 (6~66) winsize 61
5140 13:59:54.025878 [CA 3] Center 35 (5~66) winsize 62
5141 13:59:54.029060 [CA 4] Center 34 (4~65) winsize 62
5142 13:59:54.032089 [CA 5] Center 33 (3~64) winsize 62
5143 13:59:54.032587
5144 13:59:54.035887 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5145 13:59:54.036428
5146 13:59:54.038946 [CATrainingPosCal] consider 2 rank data
5147 13:59:54.042232 u2DelayCellTimex100 = 270/100 ps
5148 13:59:54.045718 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5149 13:59:54.048989 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5150 13:59:54.052664 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5151 13:59:54.058884 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5152 13:59:54.062125 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5153 13:59:54.065533 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5154 13:59:54.066156
5155 13:59:54.068930 CA PerBit enable=1, Macro0, CA PI delay=33
5156 13:59:54.069509
5157 13:59:54.072335 [CBTSetCACLKResult] CA Dly = 33
5158 13:59:54.072914 CS Dly: 7 (0~39)
5159 13:59:54.073295
5160 13:59:54.075398 ----->DramcWriteLeveling(PI) begin...
5161 13:59:54.078845 ==
5162 13:59:54.082088 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 13:59:54.085336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 13:59:54.085923 ==
5165 13:59:54.088447 Write leveling (Byte 0): 33 => 33
5166 13:59:54.091867 Write leveling (Byte 1): 28 => 28
5167 13:59:54.095388 DramcWriteLeveling(PI) end<-----
5168 13:59:54.095864
5169 13:59:54.096235 ==
5170 13:59:54.098214 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 13:59:54.101889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 13:59:54.102475 ==
5173 13:59:54.105391 [Gating] SW mode calibration
5174 13:59:54.111876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5175 13:59:54.118078 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5176 13:59:54.121704 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5177 13:59:54.124962 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 13:59:54.131133 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 13:59:54.134566 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 13:59:54.137983 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 13:59:54.144801 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 13:59:54.148081 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5183 13:59:54.151424 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
5184 13:59:54.158330 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5185 13:59:54.161439 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 13:59:54.164204 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 13:59:54.171156 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 13:59:54.174650 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 13:59:54.178009 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 13:59:54.184659 0 15 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5191 13:59:54.187528 0 15 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
5192 13:59:54.190652 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5193 13:59:54.197617 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 13:59:54.201041 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 13:59:54.204084 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 13:59:54.210900 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 13:59:54.214196 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 13:59:54.217353 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5199 13:59:54.224139 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5200 13:59:54.227226 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5201 13:59:54.230766 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5202 13:59:54.234195 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:59:54.240461 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 13:59:54.243933 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 13:59:54.246963 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 13:59:54.254018 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 13:59:54.257447 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 13:59:54.260460 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 13:59:54.267140 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 13:59:54.270492 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 13:59:54.273794 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 13:59:54.280215 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 13:59:54.283582 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 13:59:54.286754 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5215 13:59:54.293530 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5216 13:59:54.297312 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5217 13:59:54.300368 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 13:59:54.303707 Total UI for P1: 0, mck2ui 16
5219 13:59:54.306929 best dqsien dly found for B0: ( 1, 2, 28)
5220 13:59:54.310150 Total UI for P1: 0, mck2ui 16
5221 13:59:54.313690 best dqsien dly found for B1: ( 1, 2, 30)
5222 13:59:54.316949 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5223 13:59:54.320381 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5224 13:59:54.320944
5225 13:59:54.326893 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5226 13:59:54.330061 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5227 13:59:54.330556 [Gating] SW calibration Done
5228 13:59:54.333289 ==
5229 13:59:54.336727 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 13:59:54.340002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 13:59:54.340475 ==
5232 13:59:54.340850 RX Vref Scan: 0
5233 13:59:54.341234
5234 13:59:54.343441 RX Vref 0 -> 0, step: 1
5235 13:59:54.344023
5236 13:59:54.346804 RX Delay -80 -> 252, step: 8
5237 13:59:54.349901 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5238 13:59:54.353322 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5239 13:59:54.360161 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5240 13:59:54.363145 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5241 13:59:54.366865 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5242 13:59:54.370169 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5243 13:59:54.373565 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5244 13:59:54.377151 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5245 13:59:54.383517 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5246 13:59:54.386709 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5247 13:59:54.390019 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5248 13:59:54.393471 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5249 13:59:54.396865 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5250 13:59:54.400007 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5251 13:59:54.406555 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5252 13:59:54.409970 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5253 13:59:54.410556 ==
5254 13:59:54.413358 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 13:59:54.416544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 13:59:54.417117 ==
5257 13:59:54.419973 DQS Delay:
5258 13:59:54.420442 DQS0 = 0, DQS1 = 0
5259 13:59:54.420813 DQM Delay:
5260 13:59:54.423382 DQM0 = 106, DQM1 = 90
5261 13:59:54.423850 DQ Delay:
5262 13:59:54.426313 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =103
5263 13:59:54.429667 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5264 13:59:54.433185 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5265 13:59:54.436470 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5266 13:59:54.437054
5267 13:59:54.437479
5268 13:59:54.439716 ==
5269 13:59:54.443320 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 13:59:54.446015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 13:59:54.446486 ==
5272 13:59:54.446858
5273 13:59:54.447204
5274 13:59:54.449312 TX Vref Scan disable
5275 13:59:54.449779 == TX Byte 0 ==
5276 13:59:54.452930 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5277 13:59:54.459358 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5278 13:59:54.459832 == TX Byte 1 ==
5279 13:59:54.462835 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5280 13:59:54.469540 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5281 13:59:54.470233 ==
5282 13:59:54.472713 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 13:59:54.476180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 13:59:54.476683 ==
5285 13:59:54.477176
5286 13:59:54.477663
5287 13:59:54.479406 TX Vref Scan disable
5288 13:59:54.482692 == TX Byte 0 ==
5289 13:59:54.486024 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5290 13:59:54.489657 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5291 13:59:54.493156 == TX Byte 1 ==
5292 13:59:54.496526 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5293 13:59:54.499788 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5294 13:59:54.500317
5295 13:59:54.502542 [DATLAT]
5296 13:59:54.502963 Freq=933, CH0 RK0
5297 13:59:54.503301
5298 13:59:54.505930 DATLAT Default: 0xd
5299 13:59:54.506498 0, 0xFFFF, sum = 0
5300 13:59:54.509352 1, 0xFFFF, sum = 0
5301 13:59:54.509884 2, 0xFFFF, sum = 0
5302 13:59:54.512728 3, 0xFFFF, sum = 0
5303 13:59:54.513267 4, 0xFFFF, sum = 0
5304 13:59:54.516334 5, 0xFFFF, sum = 0
5305 13:59:54.516870 6, 0xFFFF, sum = 0
5306 13:59:54.519245 7, 0xFFFF, sum = 0
5307 13:59:54.519761 8, 0xFFFF, sum = 0
5308 13:59:54.522608 9, 0xFFFF, sum = 0
5309 13:59:54.523142 10, 0x0, sum = 1
5310 13:59:54.525998 11, 0x0, sum = 2
5311 13:59:54.526532 12, 0x0, sum = 3
5312 13:59:54.529498 13, 0x0, sum = 4
5313 13:59:54.530072 best_step = 11
5314 13:59:54.530421
5315 13:59:54.530737 ==
5316 13:59:54.532755 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 13:59:54.536044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 13:59:54.539406 ==
5319 13:59:54.540023 RX Vref Scan: 1
5320 13:59:54.540389
5321 13:59:54.542446 RX Vref 0 -> 0, step: 1
5322 13:59:54.542873
5323 13:59:54.545749 RX Delay -53 -> 252, step: 4
5324 13:59:54.546363
5325 13:59:54.548967 Set Vref, RX VrefLevel [Byte0]: 59
5326 13:59:54.552503 [Byte1]: 49
5327 13:59:54.553037
5328 13:59:54.555465 Final RX Vref Byte 0 = 59 to rank0
5329 13:59:54.558897 Final RX Vref Byte 1 = 49 to rank0
5330 13:59:54.562322 Final RX Vref Byte 0 = 59 to rank1
5331 13:59:54.565425 Final RX Vref Byte 1 = 49 to rank1==
5332 13:59:54.568815 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 13:59:54.572199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 13:59:54.572776 ==
5335 13:59:54.575414 DQS Delay:
5336 13:59:54.575941 DQS0 = 0, DQS1 = 0
5337 13:59:54.576280 DQM Delay:
5338 13:59:54.578682 DQM0 = 107, DQM1 = 91
5339 13:59:54.579110 DQ Delay:
5340 13:59:54.582167 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5341 13:59:54.585201 DQ4 =110, DQ5 =98, DQ6 =116, DQ7 =116
5342 13:59:54.588906 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5343 13:59:54.591804 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5344 13:59:54.592234
5345 13:59:54.595247
5346 13:59:54.601894 [DQSOSCAuto] RK0, (LSB)MR18= 0x2623, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5347 13:59:54.605276 CH0 RK0: MR19=505, MR18=2623
5348 13:59:54.611966 CH0_RK0: MR19=0x505, MR18=0x2623, DQSOSC=409, MR23=63, INC=64, DEC=43
5349 13:59:54.612495
5350 13:59:54.615672 ----->DramcWriteLeveling(PI) begin...
5351 13:59:54.616206 ==
5352 13:59:54.618445 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 13:59:54.621970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 13:59:54.622505 ==
5355 13:59:54.624981 Write leveling (Byte 0): 31 => 31
5356 13:59:54.628535 Write leveling (Byte 1): 30 => 30
5357 13:59:54.631985 DramcWriteLeveling(PI) end<-----
5358 13:59:54.632412
5359 13:59:54.632750 ==
5360 13:59:54.634905 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 13:59:54.638879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 13:59:54.639295 ==
5363 13:59:54.641588 [Gating] SW mode calibration
5364 13:59:54.648569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5365 13:59:54.654877 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5366 13:59:54.658436 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 13:59:54.661763 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 13:59:54.668273 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 13:59:54.672030 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 13:59:54.674910 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 13:59:54.681535 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 13:59:54.684772 0 14 24 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
5373 13:59:54.688059 0 14 28 | B1->B0 | 2626 2424 | 0 0 | (1 0) (0 0)
5374 13:59:54.694914 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5375 13:59:54.698144 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 13:59:54.701454 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 13:59:54.707744 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 13:59:54.711396 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 13:59:54.714803 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 13:59:54.721294 0 15 24 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 1)
5381 13:59:54.724529 0 15 28 | B1->B0 | 3c3c 4242 | 0 0 | (0 0) (0 0)
5382 13:59:54.728003 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 13:59:54.731289 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 13:59:54.738257 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 13:59:54.741586 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 13:59:54.744505 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 13:59:54.751464 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 13:59:54.754854 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 13:59:54.758402 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5390 13:59:54.764810 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 13:59:54.768768 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 13:59:54.771637 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 13:59:54.778683 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 13:59:54.781854 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 13:59:54.784975 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 13:59:54.791432 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 13:59:54.794743 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 13:59:54.798609 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 13:59:54.805154 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 13:59:54.808335 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 13:59:54.812154 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 13:59:54.818098 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 13:59:54.821669 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 13:59:54.824869 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 13:59:54.831433 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5406 13:59:54.834437 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 13:59:54.837983 Total UI for P1: 0, mck2ui 16
5408 13:59:54.841339 best dqsien dly found for B0: ( 1, 2, 28)
5409 13:59:54.844541 Total UI for P1: 0, mck2ui 16
5410 13:59:54.848394 best dqsien dly found for B1: ( 1, 2, 28)
5411 13:59:54.851217 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5412 13:59:54.854612 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5413 13:59:54.855168
5414 13:59:54.857895 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5415 13:59:54.861461 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5416 13:59:54.864248 [Gating] SW calibration Done
5417 13:59:54.864708 ==
5418 13:59:54.867912 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 13:59:54.871045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 13:59:54.871511 ==
5421 13:59:54.874469 RX Vref Scan: 0
5422 13:59:54.875031
5423 13:59:54.878232 RX Vref 0 -> 0, step: 1
5424 13:59:54.878787
5425 13:59:54.879154 RX Delay -80 -> 252, step: 8
5426 13:59:54.884510 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5427 13:59:54.887954 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5428 13:59:54.890653 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5429 13:59:54.894051 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5430 13:59:54.897424 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5431 13:59:54.901043 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5432 13:59:54.907486 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5433 13:59:54.911224 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5434 13:59:54.914171 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5435 13:59:54.917548 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5436 13:59:54.920569 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5437 13:59:54.927819 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5438 13:59:54.931057 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5439 13:59:54.934293 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5440 13:59:54.937787 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5441 13:59:54.941367 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5442 13:59:54.941924 ==
5443 13:59:54.943954 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 13:59:54.947810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 13:59:54.950657 ==
5446 13:59:54.951113 DQS Delay:
5447 13:59:54.951478 DQS0 = 0, DQS1 = 0
5448 13:59:54.954310 DQM Delay:
5449 13:59:54.954864 DQM0 = 104, DQM1 = 91
5450 13:59:54.957706 DQ Delay:
5451 13:59:54.961225 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5452 13:59:54.964075 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5453 13:59:54.967697 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5454 13:59:54.970889 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5455 13:59:54.971452
5456 13:59:54.971818
5457 13:59:54.972160 ==
5458 13:59:54.974332 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 13:59:54.977476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 13:59:54.977978 ==
5461 13:59:54.978362
5462 13:59:54.978701
5463 13:59:54.980879 TX Vref Scan disable
5464 13:59:54.981339 == TX Byte 0 ==
5465 13:59:54.987613 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5466 13:59:54.990534 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5467 13:59:54.991005 == TX Byte 1 ==
5468 13:59:54.997394 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5469 13:59:55.000990 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5470 13:59:55.001543 ==
5471 13:59:55.004092 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 13:59:55.007209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 13:59:55.007676 ==
5474 13:59:55.008045
5475 13:59:55.008381
5476 13:59:55.010704 TX Vref Scan disable
5477 13:59:55.014345 == TX Byte 0 ==
5478 13:59:55.017349 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5479 13:59:55.021354 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5480 13:59:55.024099 == TX Byte 1 ==
5481 13:59:55.027154 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5482 13:59:55.031148 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5483 13:59:55.031701
5484 13:59:55.033817 [DATLAT]
5485 13:59:55.034314 Freq=933, CH0 RK1
5486 13:59:55.034681
5487 13:59:55.037449 DATLAT Default: 0xb
5488 13:59:55.038034 0, 0xFFFF, sum = 0
5489 13:59:55.040577 1, 0xFFFF, sum = 0
5490 13:59:55.041043 2, 0xFFFF, sum = 0
5491 13:59:55.044056 3, 0xFFFF, sum = 0
5492 13:59:55.044636 4, 0xFFFF, sum = 0
5493 13:59:55.047039 5, 0xFFFF, sum = 0
5494 13:59:55.047509 6, 0xFFFF, sum = 0
5495 13:59:55.050622 7, 0xFFFF, sum = 0
5496 13:59:55.051179 8, 0xFFFF, sum = 0
5497 13:59:55.054010 9, 0xFFFF, sum = 0
5498 13:59:55.054574 10, 0x0, sum = 1
5499 13:59:55.057305 11, 0x0, sum = 2
5500 13:59:55.057861 12, 0x0, sum = 3
5501 13:59:55.060628 13, 0x0, sum = 4
5502 13:59:55.061186 best_step = 11
5503 13:59:55.061554
5504 13:59:55.061893 ==
5505 13:59:55.063920 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 13:59:55.070860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 13:59:55.071468 ==
5508 13:59:55.071844 RX Vref Scan: 0
5509 13:59:55.072184
5510 13:59:55.074171 RX Vref 0 -> 0, step: 1
5511 13:59:55.074721
5512 13:59:55.077427 RX Delay -53 -> 252, step: 4
5513 13:59:55.080492 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5514 13:59:55.086863 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5515 13:59:55.090194 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5516 13:59:55.093486 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5517 13:59:55.096800 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5518 13:59:55.100415 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5519 13:59:55.106521 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5520 13:59:55.110175 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5521 13:59:55.113227 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5522 13:59:55.116707 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5523 13:59:55.120275 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5524 13:59:55.123455 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5525 13:59:55.130393 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5526 13:59:55.133420 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5527 13:59:55.137140 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5528 13:59:55.140563 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5529 13:59:55.141147 ==
5530 13:59:55.143882 Dram Type= 6, Freq= 0, CH_0, rank 1
5531 13:59:55.147255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 13:59:55.150318 ==
5533 13:59:55.150897 DQS Delay:
5534 13:59:55.151386 DQS0 = 0, DQS1 = 0
5535 13:59:55.153658 DQM Delay:
5536 13:59:55.154283 DQM0 = 104, DQM1 = 93
5537 13:59:55.157011 DQ Delay:
5538 13:59:55.160421 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5539 13:59:55.163433 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5540 13:59:55.166820 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5541 13:59:55.170304 DQ12 =98, DQ13 =96, DQ14 =102, DQ15 =98
5542 13:59:55.170889
5543 13:59:55.171381
5544 13:59:55.176835 [DQSOSCAuto] RK1, (LSB)MR18= 0x2607, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5545 13:59:55.180273 CH0 RK1: MR19=505, MR18=2607
5546 13:59:55.186813 CH0_RK1: MR19=0x505, MR18=0x2607, DQSOSC=409, MR23=63, INC=64, DEC=43
5547 13:59:55.190022 [RxdqsGatingPostProcess] freq 933
5548 13:59:55.196851 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5549 13:59:55.197440 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 13:59:55.200028 best DQS1 dly(2T, 0.5T) = (0, 10)
5551 13:59:55.203441 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 13:59:55.206409 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5553 13:59:55.209704 best DQS0 dly(2T, 0.5T) = (0, 10)
5554 13:59:55.213332 best DQS1 dly(2T, 0.5T) = (0, 10)
5555 13:59:55.216696 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5556 13:59:55.220055 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5557 13:59:55.223409 Pre-setting of DQS Precalculation
5558 13:59:55.226559 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5559 13:59:55.230088 ==
5560 13:59:55.233014 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 13:59:55.236794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 13:59:55.237371 ==
5563 13:59:55.239878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5564 13:59:55.246711 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5565 13:59:55.250053 [CA 0] Center 37 (7~68) winsize 62
5566 13:59:55.253730 [CA 1] Center 37 (7~68) winsize 62
5567 13:59:55.257033 [CA 2] Center 35 (5~65) winsize 61
5568 13:59:55.260398 [CA 3] Center 34 (4~65) winsize 62
5569 13:59:55.263813 [CA 4] Center 34 (4~65) winsize 62
5570 13:59:55.267068 [CA 5] Center 34 (4~64) winsize 61
5571 13:59:55.267637
5572 13:59:55.270362 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5573 13:59:55.270836
5574 13:59:55.273387 [CATrainingPosCal] consider 1 rank data
5575 13:59:55.276944 u2DelayCellTimex100 = 270/100 ps
5576 13:59:55.280208 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5577 13:59:55.283550 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5578 13:59:55.289887 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5579 13:59:55.293358 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5580 13:59:55.296874 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5581 13:59:55.300033 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5582 13:59:55.300602
5583 13:59:55.303382 CA PerBit enable=1, Macro0, CA PI delay=34
5584 13:59:55.303946
5585 13:59:55.306506 [CBTSetCACLKResult] CA Dly = 34
5586 13:59:55.306973 CS Dly: 6 (0~37)
5587 13:59:55.309737 ==
5588 13:59:55.312819 Dram Type= 6, Freq= 0, CH_1, rank 1
5589 13:59:55.316422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 13:59:55.316993 ==
5591 13:59:55.319578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5592 13:59:55.326350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5593 13:59:55.329924 [CA 0] Center 37 (7~68) winsize 62
5594 13:59:55.333271 [CA 1] Center 38 (7~69) winsize 63
5595 13:59:55.337063 [CA 2] Center 35 (5~66) winsize 62
5596 13:59:55.339946 [CA 3] Center 35 (5~65) winsize 61
5597 13:59:55.343560 [CA 4] Center 35 (5~65) winsize 61
5598 13:59:55.346505 [CA 5] Center 34 (4~65) winsize 62
5599 13:59:55.346978
5600 13:59:55.349677 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5601 13:59:55.350194
5602 13:59:55.353362 [CATrainingPosCal] consider 2 rank data
5603 13:59:55.356347 u2DelayCellTimex100 = 270/100 ps
5604 13:59:55.359706 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5605 13:59:55.366475 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5606 13:59:55.369928 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5607 13:59:55.373336 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5608 13:59:55.376645 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5609 13:59:55.379772 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5610 13:59:55.380352
5611 13:59:55.382779 CA PerBit enable=1, Macro0, CA PI delay=34
5612 13:59:55.383278
5613 13:59:55.386858 [CBTSetCACLKResult] CA Dly = 34
5614 13:59:55.387607 CS Dly: 7 (0~39)
5615 13:59:55.388080
5616 13:59:55.393192 ----->DramcWriteLeveling(PI) begin...
5617 13:59:55.393778 ==
5618 13:59:55.396567 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 13:59:55.399948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 13:59:55.400532 ==
5621 13:59:55.403321 Write leveling (Byte 0): 28 => 28
5622 13:59:55.406646 Write leveling (Byte 1): 28 => 28
5623 13:59:55.410116 DramcWriteLeveling(PI) end<-----
5624 13:59:55.410689
5625 13:59:55.411104 ==
5626 13:59:55.412888 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 13:59:55.416613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 13:59:55.417195 ==
5629 13:59:55.419647 [Gating] SW mode calibration
5630 13:59:55.426323 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5631 13:59:55.433003 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5632 13:59:55.436209 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 13:59:55.439438 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 13:59:55.446206 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 13:59:55.449316 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 13:59:55.452745 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 13:59:55.459341 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 13:59:55.462818 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5639 13:59:55.465832 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
5640 13:59:55.469171 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 13:59:55.476401 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 13:59:55.479792 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 13:59:55.482904 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 13:59:55.489427 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 13:59:55.492659 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 13:59:55.496507 0 15 24 | B1->B0 | 2b2b 2c2c | 0 0 | (0 0) (0 0)
5647 13:59:55.502618 0 15 28 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
5648 13:59:55.505911 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 13:59:55.509142 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 13:59:55.515896 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 13:59:55.519084 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 13:59:55.522450 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 13:59:55.529366 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 13:59:55.532757 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5655 13:59:55.535738 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5656 13:59:55.542410 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 13:59:55.545796 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 13:59:55.548796 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 13:59:55.556121 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 13:59:55.559426 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 13:59:55.562480 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 13:59:55.568811 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 13:59:55.572236 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 13:59:55.575599 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 13:59:55.582388 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 13:59:55.585382 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 13:59:55.588824 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 13:59:55.594987 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 13:59:55.598828 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5670 13:59:55.602065 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5671 13:59:55.605366 Total UI for P1: 0, mck2ui 16
5672 13:59:55.608670 best dqsien dly found for B0: ( 1, 2, 20)
5673 13:59:55.615493 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 13:59:55.616073 Total UI for P1: 0, mck2ui 16
5675 13:59:55.618782 best dqsien dly found for B1: ( 1, 2, 24)
5676 13:59:55.624972 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5677 13:59:55.628644 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5678 13:59:55.629220
5679 13:59:55.632013 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5680 13:59:55.635132 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5681 13:59:55.638306 [Gating] SW calibration Done
5682 13:59:55.638773 ==
5683 13:59:55.642142 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 13:59:55.645205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 13:59:55.645678 ==
5686 13:59:55.648901 RX Vref Scan: 0
5687 13:59:55.649468
5688 13:59:55.649850 RX Vref 0 -> 0, step: 1
5689 13:59:55.650274
5690 13:59:55.651872 RX Delay -80 -> 252, step: 8
5691 13:59:55.654877 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5692 13:59:55.662214 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5693 13:59:55.664896 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5694 13:59:55.668294 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5695 13:59:55.671970 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5696 13:59:55.675291 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5697 13:59:55.678364 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5698 13:59:55.681708 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5699 13:59:55.688303 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5700 13:59:55.691637 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5701 13:59:55.694707 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5702 13:59:55.698552 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5703 13:59:55.701983 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5704 13:59:55.708229 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5705 13:59:55.711501 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5706 13:59:55.714868 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5707 13:59:55.715437 ==
5708 13:59:55.718053 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 13:59:55.721463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 13:59:55.722071 ==
5711 13:59:55.724881 DQS Delay:
5712 13:59:55.725509 DQS0 = 0, DQS1 = 0
5713 13:59:55.725893 DQM Delay:
5714 13:59:55.728139 DQM0 = 101, DQM1 = 95
5715 13:59:55.728705 DQ Delay:
5716 13:59:55.731496 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5717 13:59:55.734623 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5718 13:59:55.738043 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5719 13:59:55.741489 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5720 13:59:55.742087
5721 13:59:55.744760
5722 13:59:55.745328 ==
5723 13:59:55.748519 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 13:59:55.751439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 13:59:55.752015 ==
5726 13:59:55.752397
5727 13:59:55.752753
5728 13:59:55.754960 TX Vref Scan disable
5729 13:59:55.755434 == TX Byte 0 ==
5730 13:59:55.761498 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5731 13:59:55.764584 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5732 13:59:55.765173 == TX Byte 1 ==
5733 13:59:55.771348 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5734 13:59:55.774611 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5735 13:59:55.775087 ==
5736 13:59:55.777805 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 13:59:55.781190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 13:59:55.781780 ==
5739 13:59:55.782257
5740 13:59:55.782618
5741 13:59:55.784527 TX Vref Scan disable
5742 13:59:55.787763 == TX Byte 0 ==
5743 13:59:55.791013 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5744 13:59:55.794437 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5745 13:59:55.798108 == TX Byte 1 ==
5746 13:59:55.801127 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5747 13:59:55.804482 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5748 13:59:55.805053
5749 13:59:55.807540 [DATLAT]
5750 13:59:55.808012 Freq=933, CH1 RK0
5751 13:59:55.808385
5752 13:59:55.811186 DATLAT Default: 0xd
5753 13:59:55.811759 0, 0xFFFF, sum = 0
5754 13:59:55.814323 1, 0xFFFF, sum = 0
5755 13:59:55.814801 2, 0xFFFF, sum = 0
5756 13:59:55.817780 3, 0xFFFF, sum = 0
5757 13:59:55.818297 4, 0xFFFF, sum = 0
5758 13:59:55.821225 5, 0xFFFF, sum = 0
5759 13:59:55.821796 6, 0xFFFF, sum = 0
5760 13:59:55.824572 7, 0xFFFF, sum = 0
5761 13:59:55.825150 8, 0xFFFF, sum = 0
5762 13:59:55.827600 9, 0xFFFF, sum = 0
5763 13:59:55.828081 10, 0x0, sum = 1
5764 13:59:55.830992 11, 0x0, sum = 2
5765 13:59:55.831471 12, 0x0, sum = 3
5766 13:59:55.834376 13, 0x0, sum = 4
5767 13:59:55.834854 best_step = 11
5768 13:59:55.835231
5769 13:59:55.835580 ==
5770 13:59:55.837634 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 13:59:55.841041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 13:59:55.844396 ==
5773 13:59:55.844970 RX Vref Scan: 1
5774 13:59:55.845348
5775 13:59:55.847551 RX Vref 0 -> 0, step: 1
5776 13:59:55.848024
5777 13:59:55.850864 RX Delay -53 -> 252, step: 4
5778 13:59:55.851340
5779 13:59:55.851715 Set Vref, RX VrefLevel [Byte0]: 53
5780 13:59:55.854112 [Byte1]: 50
5781 13:59:55.859536
5782 13:59:55.860008 Final RX Vref Byte 0 = 53 to rank0
5783 13:59:55.862741 Final RX Vref Byte 1 = 50 to rank0
5784 13:59:55.865886 Final RX Vref Byte 0 = 53 to rank1
5785 13:59:55.869213 Final RX Vref Byte 1 = 50 to rank1==
5786 13:59:55.872790 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 13:59:55.879357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 13:59:55.879888 ==
5789 13:59:55.880234 DQS Delay:
5790 13:59:55.880550 DQS0 = 0, DQS1 = 0
5791 13:59:55.882603 DQM Delay:
5792 13:59:55.883031 DQM0 = 104, DQM1 = 98
5793 13:59:55.885566 DQ Delay:
5794 13:59:55.889120 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5795 13:59:55.892443 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5796 13:59:55.895863 DQ8 =88, DQ9 =86, DQ10 =102, DQ11 =92
5797 13:59:55.898988 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =104
5798 13:59:55.899418
5799 13:59:55.899755
5800 13:59:55.906057 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5801 13:59:55.909408 CH1 RK0: MR19=505, MR18=1830
5802 13:59:55.916046 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5803 13:59:55.916583
5804 13:59:55.919249 ----->DramcWriteLeveling(PI) begin...
5805 13:59:55.919783 ==
5806 13:59:55.922561 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 13:59:55.925891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 13:59:55.928782 ==
5809 13:59:55.929209 Write leveling (Byte 0): 26 => 26
5810 13:59:55.932464 Write leveling (Byte 1): 28 => 28
5811 13:59:55.935831 DramcWriteLeveling(PI) end<-----
5812 13:59:55.936362
5813 13:59:55.936706 ==
5814 13:59:55.939167 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 13:59:55.945705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 13:59:55.946278 ==
5817 13:59:55.946633 [Gating] SW mode calibration
5818 13:59:55.955835 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5819 13:59:55.959105 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5820 13:59:55.962175 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5821 13:59:55.968870 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 13:59:55.972710 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 13:59:55.975551 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 13:59:55.982107 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 13:59:55.985580 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 13:59:55.988889 0 14 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5827 13:59:55.995153 0 14 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5828 13:59:55.998731 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5829 13:59:56.001758 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 13:59:56.008736 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 13:59:56.012053 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 13:59:56.015375 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 13:59:56.021860 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 13:59:56.025178 0 15 24 | B1->B0 | 2c2c 2525 | 1 0 | (0 0) (1 1)
5835 13:59:56.028262 0 15 28 | B1->B0 | 4040 3939 | 0 1 | (0 0) (0 0)
5836 13:59:56.035202 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 13:59:56.038775 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 13:59:56.042088 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 13:59:56.048461 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 13:59:56.051940 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 13:59:56.055322 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 13:59:56.061999 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5843 13:59:56.064993 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5844 13:59:56.068916 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 13:59:56.075107 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 13:59:56.078849 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 13:59:56.081914 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 13:59:56.088404 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 13:59:56.092088 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 13:59:56.094962 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 13:59:56.098498 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 13:59:56.105165 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 13:59:56.108379 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 13:59:56.111861 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 13:59:56.118359 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 13:59:56.121518 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 13:59:56.124944 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 13:59:56.131455 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 13:59:56.135093 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5860 13:59:56.138271 Total UI for P1: 0, mck2ui 16
5861 13:59:56.141635 best dqsien dly found for B1: ( 1, 2, 26)
5862 13:59:56.144757 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 13:59:56.148076 Total UI for P1: 0, mck2ui 16
5864 13:59:56.151116 best dqsien dly found for B0: ( 1, 2, 28)
5865 13:59:56.154824 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5866 13:59:56.158570 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5867 13:59:56.161494
5868 13:59:56.165291 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5869 13:59:56.167852 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5870 13:59:56.171712 [Gating] SW calibration Done
5871 13:59:56.172280 ==
5872 13:59:56.174613 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 13:59:56.178108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 13:59:56.178682 ==
5875 13:59:56.179061 RX Vref Scan: 0
5876 13:59:56.181132
5877 13:59:56.181597 RX Vref 0 -> 0, step: 1
5878 13:59:56.182003
5879 13:59:56.184450 RX Delay -80 -> 252, step: 8
5880 13:59:56.188160 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5881 13:59:56.190871 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5882 13:59:56.197385 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5883 13:59:56.200953 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5884 13:59:56.204056 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5885 13:59:56.207930 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5886 13:59:56.211027 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5887 13:59:56.214192 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5888 13:59:56.220466 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5889 13:59:56.223845 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5890 13:59:56.227131 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5891 13:59:56.230494 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5892 13:59:56.233831 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5893 13:59:56.237236 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5894 13:59:56.243667 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5895 13:59:56.247165 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5896 13:59:56.247251 ==
5897 13:59:56.250387 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 13:59:56.253848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 13:59:56.254060 ==
5900 13:59:56.257343 DQS Delay:
5901 13:59:56.257508 DQS0 = 0, DQS1 = 0
5902 13:59:56.257583 DQM Delay:
5903 13:59:56.260482 DQM0 = 102, DQM1 = 95
5904 13:59:56.260637 DQ Delay:
5905 13:59:56.263552 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5906 13:59:56.266740 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =99
5907 13:59:56.270537 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5908 13:59:56.273574 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5909 13:59:56.273724
5910 13:59:56.273807
5911 13:59:56.277043 ==
5912 13:59:56.277246 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 13:59:56.283225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 13:59:56.283363 ==
5915 13:59:56.283463
5916 13:59:56.283556
5917 13:59:56.286673 TX Vref Scan disable
5918 13:59:56.286812 == TX Byte 0 ==
5919 13:59:56.289899 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5920 13:59:56.296541 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5921 13:59:56.296721 == TX Byte 1 ==
5922 13:59:56.300101 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5923 13:59:56.306394 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5924 13:59:56.306655 ==
5925 13:59:56.309826 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 13:59:56.313705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 13:59:56.314152 ==
5928 13:59:56.314430
5929 13:59:56.314663
5930 13:59:56.316582 TX Vref Scan disable
5931 13:59:56.320090 == TX Byte 0 ==
5932 13:59:56.323136 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5933 13:59:56.326726 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5934 13:59:56.329976 == TX Byte 1 ==
5935 13:59:56.333392 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5936 13:59:56.336637 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5937 13:59:56.337206
5938 13:59:56.339748 [DATLAT]
5939 13:59:56.340219 Freq=933, CH1 RK1
5940 13:59:56.340595
5941 13:59:56.343147 DATLAT Default: 0xb
5942 13:59:56.343617 0, 0xFFFF, sum = 0
5943 13:59:56.346413 1, 0xFFFF, sum = 0
5944 13:59:56.346891 2, 0xFFFF, sum = 0
5945 13:59:56.349690 3, 0xFFFF, sum = 0
5946 13:59:56.350224 4, 0xFFFF, sum = 0
5947 13:59:56.353284 5, 0xFFFF, sum = 0
5948 13:59:56.353862 6, 0xFFFF, sum = 0
5949 13:59:56.357059 7, 0xFFFF, sum = 0
5950 13:59:56.357631 8, 0xFFFF, sum = 0
5951 13:59:56.359669 9, 0xFFFF, sum = 0
5952 13:59:56.360148 10, 0x0, sum = 1
5953 13:59:56.363246 11, 0x0, sum = 2
5954 13:59:56.363822 12, 0x0, sum = 3
5955 13:59:56.366672 13, 0x0, sum = 4
5956 13:59:56.367256 best_step = 11
5957 13:59:56.367636
5958 13:59:56.367988 ==
5959 13:59:56.370007 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 13:59:56.373112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 13:59:56.376492 ==
5962 13:59:56.376964 RX Vref Scan: 0
5963 13:59:56.377341
5964 13:59:56.379817 RX Vref 0 -> 0, step: 1
5965 13:59:56.380289
5966 13:59:56.382986 RX Delay -53 -> 252, step: 4
5967 13:59:56.386230 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5968 13:59:56.389686 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5969 13:59:56.396093 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5970 13:59:56.399757 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5971 13:59:56.402986 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5972 13:59:56.406356 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5973 13:59:56.409228 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5974 13:59:56.416120 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5975 13:59:56.419679 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5976 13:59:56.422684 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5977 13:59:56.426307 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5978 13:59:56.429653 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5979 13:59:56.432805 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5980 13:59:56.439315 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5981 13:59:56.442481 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5982 13:59:56.446086 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5983 13:59:56.446655 ==
5984 13:59:56.449278 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 13:59:56.452430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 13:59:56.456009 ==
5987 13:59:56.456574 DQS Delay:
5988 13:59:56.456951 DQS0 = 0, DQS1 = 0
5989 13:59:56.459544 DQM Delay:
5990 13:59:56.460112 DQM0 = 104, DQM1 = 98
5991 13:59:56.462413 DQ Delay:
5992 13:59:56.465839 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5993 13:59:56.469269 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102
5994 13:59:56.472791 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5995 13:59:56.476092 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =108
5996 13:59:56.476660
5997 13:59:56.477028
5998 13:59:56.482765 [DQSOSCAuto] RK1, (LSB)MR18= 0x2400, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5999 13:59:56.486052 CH1 RK1: MR19=505, MR18=2400
6000 13:59:56.492648 CH1_RK1: MR19=0x505, MR18=0x2400, DQSOSC=410, MR23=63, INC=64, DEC=42
6001 13:59:56.495731 [RxdqsGatingPostProcess] freq 933
6002 13:59:56.499335 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6003 13:59:56.502731 best DQS0 dly(2T, 0.5T) = (0, 10)
6004 13:59:56.505813 best DQS1 dly(2T, 0.5T) = (0, 10)
6005 13:59:56.508999 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6006 13:59:56.512262 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6007 13:59:56.515434 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 13:59:56.518752 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 13:59:56.522158 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 13:59:56.525344 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 13:59:56.528831 Pre-setting of DQS Precalculation
6012 13:59:56.532233 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6013 13:59:56.541892 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6014 13:59:56.548684 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6015 13:59:56.549348
6016 13:59:56.550010
6017 13:59:56.551887 [Calibration Summary] 1866 Mbps
6018 13:59:56.552514 CH 0, Rank 0
6019 13:59:56.555783 SW Impedance : PASS
6020 13:59:56.556320 DUTY Scan : NO K
6021 13:59:56.558920 ZQ Calibration : PASS
6022 13:59:56.562174 Jitter Meter : NO K
6023 13:59:56.562713 CBT Training : PASS
6024 13:59:56.565618 Write leveling : PASS
6025 13:59:56.568925 RX DQS gating : PASS
6026 13:59:56.569348 RX DQ/DQS(RDDQC) : PASS
6027 13:59:56.572368 TX DQ/DQS : PASS
6028 13:59:56.575509 RX DATLAT : PASS
6029 13:59:56.575934 RX DQ/DQS(Engine): PASS
6030 13:59:56.578968 TX OE : NO K
6031 13:59:56.579493 All Pass.
6032 13:59:56.579838
6033 13:59:56.582560 CH 0, Rank 1
6034 13:59:56.583084 SW Impedance : PASS
6035 13:59:56.585729 DUTY Scan : NO K
6036 13:59:56.586306 ZQ Calibration : PASS
6037 13:59:56.589294 Jitter Meter : NO K
6038 13:59:56.592253 CBT Training : PASS
6039 13:59:56.592774 Write leveling : PASS
6040 13:59:56.595432 RX DQS gating : PASS
6041 13:59:56.598833 RX DQ/DQS(RDDQC) : PASS
6042 13:59:56.599321 TX DQ/DQS : PASS
6043 13:59:56.602305 RX DATLAT : PASS
6044 13:59:56.605579 RX DQ/DQS(Engine): PASS
6045 13:59:56.606150 TX OE : NO K
6046 13:59:56.608890 All Pass.
6047 13:59:56.609414
6048 13:59:56.609753 CH 1, Rank 0
6049 13:59:56.612054 SW Impedance : PASS
6050 13:59:56.612575 DUTY Scan : NO K
6051 13:59:56.615303 ZQ Calibration : PASS
6052 13:59:56.618446 Jitter Meter : NO K
6053 13:59:56.618871 CBT Training : PASS
6054 13:59:56.622032 Write leveling : PASS
6055 13:59:56.625210 RX DQS gating : PASS
6056 13:59:56.625636 RX DQ/DQS(RDDQC) : PASS
6057 13:59:56.628622 TX DQ/DQS : PASS
6058 13:59:56.631887 RX DATLAT : PASS
6059 13:59:56.632423 RX DQ/DQS(Engine): PASS
6060 13:59:56.635011 TX OE : NO K
6061 13:59:56.635439 All Pass.
6062 13:59:56.635779
6063 13:59:56.638611 CH 1, Rank 1
6064 13:59:56.639033 SW Impedance : PASS
6065 13:59:56.641646 DUTY Scan : NO K
6066 13:59:56.642193 ZQ Calibration : PASS
6067 13:59:56.645252 Jitter Meter : NO K
6068 13:59:56.648852 CBT Training : PASS
6069 13:59:56.649372 Write leveling : PASS
6070 13:59:56.652284 RX DQS gating : PASS
6071 13:59:56.655718 RX DQ/DQS(RDDQC) : PASS
6072 13:59:56.656251 TX DQ/DQS : PASS
6073 13:59:56.658501 RX DATLAT : PASS
6074 13:59:56.662009 RX DQ/DQS(Engine): PASS
6075 13:59:56.662532 TX OE : NO K
6076 13:59:56.665262 All Pass.
6077 13:59:56.665782
6078 13:59:56.666162 DramC Write-DBI off
6079 13:59:56.668293 PER_BANK_REFRESH: Hybrid Mode
6080 13:59:56.668718 TX_TRACKING: ON
6081 13:59:56.678644 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6082 13:59:56.682052 [FAST_K] Save calibration result to emmc
6083 13:59:56.685278 dramc_set_vcore_voltage set vcore to 650000
6084 13:59:56.688631 Read voltage for 400, 6
6085 13:59:56.689157 Vio18 = 0
6086 13:59:56.691723 Vcore = 650000
6087 13:59:56.692147 Vdram = 0
6088 13:59:56.692482 Vddq = 0
6089 13:59:56.692796 Vmddr = 0
6090 13:59:56.698643 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6091 13:59:56.705285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6092 13:59:56.705852 MEM_TYPE=3, freq_sel=20
6093 13:59:56.708710 sv_algorithm_assistance_LP4_800
6094 13:59:56.712071 ============ PULL DRAM RESETB DOWN ============
6095 13:59:56.718577 ========== PULL DRAM RESETB DOWN end =========
6096 13:59:56.722062 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6097 13:59:56.725270 ===================================
6098 13:59:56.728261 LPDDR4 DRAM CONFIGURATION
6099 13:59:56.731599 ===================================
6100 13:59:56.732076 EX_ROW_EN[0] = 0x0
6101 13:59:56.734919 EX_ROW_EN[1] = 0x0
6102 13:59:56.735385 LP4Y_EN = 0x0
6103 13:59:56.738430 WORK_FSP = 0x0
6104 13:59:56.738900 WL = 0x2
6105 13:59:56.741597 RL = 0x2
6106 13:59:56.744991 BL = 0x2
6107 13:59:56.745466 RPST = 0x0
6108 13:59:56.748019 RD_PRE = 0x0
6109 13:59:56.748485 WR_PRE = 0x1
6110 13:59:56.751581 WR_PST = 0x0
6111 13:59:56.752146 DBI_WR = 0x0
6112 13:59:56.755362 DBI_RD = 0x0
6113 13:59:56.755934 OTF = 0x1
6114 13:59:56.758458 ===================================
6115 13:59:56.761745 ===================================
6116 13:59:56.765045 ANA top config
6117 13:59:56.768700 ===================================
6118 13:59:56.769276 DLL_ASYNC_EN = 0
6119 13:59:56.772056 ALL_SLAVE_EN = 1
6120 13:59:56.775321 NEW_RANK_MODE = 1
6121 13:59:56.778811 DLL_IDLE_MODE = 1
6122 13:59:56.779379 LP45_APHY_COMB_EN = 1
6123 13:59:56.782078 TX_ODT_DIS = 1
6124 13:59:56.785484 NEW_8X_MODE = 1
6125 13:59:56.788307 ===================================
6126 13:59:56.792128 ===================================
6127 13:59:56.794771 data_rate = 800
6128 13:59:56.798381 CKR = 1
6129 13:59:56.798851 DQ_P2S_RATIO = 4
6130 13:59:56.801722 ===================================
6131 13:59:56.805215 CA_P2S_RATIO = 4
6132 13:59:56.808245 DQ_CA_OPEN = 0
6133 13:59:56.811739 DQ_SEMI_OPEN = 1
6134 13:59:56.814840 CA_SEMI_OPEN = 1
6135 13:59:56.818454 CA_FULL_RATE = 0
6136 13:59:56.819020 DQ_CKDIV4_EN = 0
6137 13:59:56.821573 CA_CKDIV4_EN = 1
6138 13:59:56.824896 CA_PREDIV_EN = 0
6139 13:59:56.828092 PH8_DLY = 0
6140 13:59:56.831124 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6141 13:59:56.834895 DQ_AAMCK_DIV = 0
6142 13:59:56.835486 CA_AAMCK_DIV = 0
6143 13:59:56.837738 CA_ADMCK_DIV = 4
6144 13:59:56.841416 DQ_TRACK_CA_EN = 0
6145 13:59:56.844458 CA_PICK = 800
6146 13:59:56.847817 CA_MCKIO = 400
6147 13:59:56.851470 MCKIO_SEMI = 400
6148 13:59:56.854482 PLL_FREQ = 3016
6149 13:59:56.857757 DQ_UI_PI_RATIO = 32
6150 13:59:56.858257 CA_UI_PI_RATIO = 32
6151 13:59:56.861588 ===================================
6152 13:59:56.864718 ===================================
6153 13:59:56.867789 memory_type:LPDDR4
6154 13:59:56.871110 GP_NUM : 10
6155 13:59:56.871687 SRAM_EN : 1
6156 13:59:56.874530 MD32_EN : 0
6157 13:59:56.877982 ===================================
6158 13:59:56.881386 [ANA_INIT] >>>>>>>>>>>>>>
6159 13:59:56.884792 <<<<<< [CONFIGURE PHASE]: ANA_TX
6160 13:59:56.888006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6161 13:59:56.891246 ===================================
6162 13:59:56.891828 data_rate = 800,PCW = 0X7400
6163 13:59:56.894091 ===================================
6164 13:59:56.897718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6165 13:59:56.904077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6166 13:59:56.917740 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 13:59:56.920375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6168 13:59:56.924004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6169 13:59:56.927136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6170 13:59:56.930580 [ANA_INIT] flow start
6171 13:59:56.931156 [ANA_INIT] PLL >>>>>>>>
6172 13:59:56.934229 [ANA_INIT] PLL <<<<<<<<
6173 13:59:56.937108 [ANA_INIT] MIDPI >>>>>>>>
6174 13:59:56.937732 [ANA_INIT] MIDPI <<<<<<<<
6175 13:59:56.940632 [ANA_INIT] DLL >>>>>>>>
6176 13:59:56.943618 [ANA_INIT] flow end
6177 13:59:56.947270 ============ LP4 DIFF to SE enter ============
6178 13:59:56.950363 ============ LP4 DIFF to SE exit ============
6179 13:59:56.953815 [ANA_INIT] <<<<<<<<<<<<<
6180 13:59:56.957422 [Flow] Enable top DCM control >>>>>
6181 13:59:56.960758 [Flow] Enable top DCM control <<<<<
6182 13:59:56.963994 Enable DLL master slave shuffle
6183 13:59:56.967030 ==============================================================
6184 13:59:56.970738 Gating Mode config
6185 13:59:56.977034 ==============================================================
6186 13:59:56.977592 Config description:
6187 13:59:56.987278 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6188 13:59:56.994103 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6189 13:59:56.997022 SELPH_MODE 0: By rank 1: By Phase
6190 13:59:57.003925 ==============================================================
6191 13:59:57.007104 GAT_TRACK_EN = 0
6192 13:59:57.010652 RX_GATING_MODE = 2
6193 13:59:57.013865 RX_GATING_TRACK_MODE = 2
6194 13:59:57.017503 SELPH_MODE = 1
6195 13:59:57.020860 PICG_EARLY_EN = 1
6196 13:59:57.023683 VALID_LAT_VALUE = 1
6197 13:59:57.026841 ==============================================================
6198 13:59:57.030458 Enter into Gating configuration >>>>
6199 13:59:57.033764 Exit from Gating configuration <<<<
6200 13:59:57.037120 Enter into DVFS_PRE_config >>>>>
6201 13:59:57.050387 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6202 13:59:57.053495 Exit from DVFS_PRE_config <<<<<
6203 13:59:57.054007 Enter into PICG configuration >>>>
6204 13:59:57.056572 Exit from PICG configuration <<<<
6205 13:59:57.059750 [RX_INPUT] configuration >>>>>
6206 13:59:57.063239 [RX_INPUT] configuration <<<<<
6207 13:59:57.070021 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6208 13:59:57.074055 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6209 13:59:57.080263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 13:59:57.086802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 13:59:57.093445 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 13:59:57.100181 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 13:59:57.103866 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6214 13:59:57.107137 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6215 13:59:57.110309 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6216 13:59:57.117177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6217 13:59:57.120031 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6218 13:59:57.123638 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 13:59:57.126768 ===================================
6220 13:59:57.130486 LPDDR4 DRAM CONFIGURATION
6221 13:59:57.133773 ===================================
6222 13:59:57.134396 EX_ROW_EN[0] = 0x0
6223 13:59:57.137268 EX_ROW_EN[1] = 0x0
6224 13:59:57.140181 LP4Y_EN = 0x0
6225 13:59:57.140749 WORK_FSP = 0x0
6226 13:59:57.143360 WL = 0x2
6227 13:59:57.143824 RL = 0x2
6228 13:59:57.146683 BL = 0x2
6229 13:59:57.147144 RPST = 0x0
6230 13:59:57.150100 RD_PRE = 0x0
6231 13:59:57.150681 WR_PRE = 0x1
6232 13:59:57.153175 WR_PST = 0x0
6233 13:59:57.153641 DBI_WR = 0x0
6234 13:59:57.156784 DBI_RD = 0x0
6235 13:59:57.157353 OTF = 0x1
6236 13:59:57.160019 ===================================
6237 13:59:57.163281 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6238 13:59:57.169716 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6239 13:59:57.173125 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 13:59:57.176385 ===================================
6241 13:59:57.179662 LPDDR4 DRAM CONFIGURATION
6242 13:59:57.183059 ===================================
6243 13:59:57.183632 EX_ROW_EN[0] = 0x10
6244 13:59:57.186877 EX_ROW_EN[1] = 0x0
6245 13:59:57.187448 LP4Y_EN = 0x0
6246 13:59:57.190124 WORK_FSP = 0x0
6247 13:59:57.193489 WL = 0x2
6248 13:59:57.194097 RL = 0x2
6249 13:59:57.196634 BL = 0x2
6250 13:59:57.197116 RPST = 0x0
6251 13:59:57.199690 RD_PRE = 0x0
6252 13:59:57.200263 WR_PRE = 0x1
6253 13:59:57.203407 WR_PST = 0x0
6254 13:59:57.203978 DBI_WR = 0x0
6255 13:59:57.206215 DBI_RD = 0x0
6256 13:59:57.206676 OTF = 0x1
6257 13:59:57.209500 ===================================
6258 13:59:57.216445 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6259 13:59:57.220155 nWR fixed to 30
6260 13:59:57.223688 [ModeRegInit_LP4] CH0 RK0
6261 13:59:57.224153 [ModeRegInit_LP4] CH0 RK1
6262 13:59:57.226884 [ModeRegInit_LP4] CH1 RK0
6263 13:59:57.230457 [ModeRegInit_LP4] CH1 RK1
6264 13:59:57.231022 match AC timing 19
6265 13:59:57.237277 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6266 13:59:57.240651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6267 13:59:57.243909 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6268 13:59:57.250502 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6269 13:59:57.253774 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6270 13:59:57.254404 ==
6271 13:59:57.257092 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 13:59:57.260234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 13:59:57.260820 ==
6274 13:59:57.267383 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 13:59:57.273669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6276 13:59:57.276943 [CA 0] Center 36 (8~64) winsize 57
6277 13:59:57.280324 [CA 1] Center 36 (8~64) winsize 57
6278 13:59:57.283462 [CA 2] Center 36 (8~64) winsize 57
6279 13:59:57.283951 [CA 3] Center 36 (8~64) winsize 57
6280 13:59:57.286825 [CA 4] Center 36 (8~64) winsize 57
6281 13:59:57.290106 [CA 5] Center 36 (8~64) winsize 57
6282 13:59:57.290594
6283 13:59:57.293516 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6284 13:59:57.296735
6285 13:59:57.300347 [CATrainingPosCal] consider 1 rank data
6286 13:59:57.300932 u2DelayCellTimex100 = 270/100 ps
6287 13:59:57.306913 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 13:59:57.310488 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 13:59:57.314116 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 13:59:57.316692 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 13:59:57.320221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 13:59:57.323503 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 13:59:57.324101
6294 13:59:57.326982 CA PerBit enable=1, Macro0, CA PI delay=36
6295 13:59:57.327569
6296 13:59:57.330259 [CBTSetCACLKResult] CA Dly = 36
6297 13:59:57.333743 CS Dly: 1 (0~32)
6298 13:59:57.334358 ==
6299 13:59:57.337173 Dram Type= 6, Freq= 0, CH_0, rank 1
6300 13:59:57.340476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 13:59:57.341062 ==
6302 13:59:57.346610 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6303 13:59:57.350281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6304 13:59:57.353586 [CA 0] Center 36 (8~64) winsize 57
6305 13:59:57.356827 [CA 1] Center 36 (8~64) winsize 57
6306 13:59:57.360114 [CA 2] Center 36 (8~64) winsize 57
6307 13:59:57.363637 [CA 3] Center 36 (8~64) winsize 57
6308 13:59:57.366655 [CA 4] Center 36 (8~64) winsize 57
6309 13:59:57.370034 [CA 5] Center 36 (8~64) winsize 57
6310 13:59:57.370513
6311 13:59:57.373491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6312 13:59:57.374125
6313 13:59:57.376772 [CATrainingPosCal] consider 2 rank data
6314 13:59:57.379792 u2DelayCellTimex100 = 270/100 ps
6315 13:59:57.383571 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 13:59:57.386530 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 13:59:57.389872 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 13:59:57.393559 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 13:59:57.400155 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 13:59:57.403013 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 13:59:57.403488
6322 13:59:57.406235 CA PerBit enable=1, Macro0, CA PI delay=36
6323 13:59:57.406708
6324 13:59:57.410136 [CBTSetCACLKResult] CA Dly = 36
6325 13:59:57.410842 CS Dly: 1 (0~32)
6326 13:59:57.411561
6327 13:59:57.413144 ----->DramcWriteLeveling(PI) begin...
6328 13:59:57.413624 ==
6329 13:59:57.416493 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 13:59:57.423324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 13:59:57.423898 ==
6332 13:59:57.426567 Write leveling (Byte 0): 40 => 8
6333 13:59:57.430063 Write leveling (Byte 1): 32 => 0
6334 13:59:57.430641 DramcWriteLeveling(PI) end<-----
6335 13:59:57.431028
6336 13:59:57.433595 ==
6337 13:59:57.436797 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 13:59:57.439831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 13:59:57.440311 ==
6340 13:59:57.443093 [Gating] SW mode calibration
6341 13:59:57.449793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6342 13:59:57.453216 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6343 13:59:57.459734 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6344 13:59:57.463118 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 13:59:57.466398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 13:59:57.473139 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 13:59:57.476018 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 13:59:57.479546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 13:59:57.486168 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 13:59:57.489706 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 13:59:57.493134 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 13:59:57.495840 Total UI for P1: 0, mck2ui 16
6353 13:59:57.499438 best dqsien dly found for B0: ( 0, 14, 24)
6354 13:59:57.502636 Total UI for P1: 0, mck2ui 16
6355 13:59:57.505914 best dqsien dly found for B1: ( 0, 14, 24)
6356 13:59:57.509198 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6357 13:59:57.512633 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6358 13:59:57.513096
6359 13:59:57.519408 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6360 13:59:57.522513 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 13:59:57.522967 [Gating] SW calibration Done
6362 13:59:57.526081 ==
6363 13:59:57.529318 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 13:59:57.532533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 13:59:57.533011 ==
6366 13:59:57.533405 RX Vref Scan: 0
6367 13:59:57.533754
6368 13:59:57.535852 RX Vref 0 -> 0, step: 1
6369 13:59:57.536303
6370 13:59:57.539080 RX Delay -410 -> 252, step: 16
6371 13:59:57.542671 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6372 13:59:57.545605 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6373 13:59:57.552459 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6374 13:59:57.555644 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6375 13:59:57.558825 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6376 13:59:57.562044 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6377 13:59:57.568854 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6378 13:59:57.572017 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6379 13:59:57.575621 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6380 13:59:57.579166 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6381 13:59:57.585677 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6382 13:59:57.588948 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6383 13:59:57.592225 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6384 13:59:57.595610 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6385 13:59:57.602353 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6386 13:59:57.606025 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6387 13:59:57.606468 ==
6388 13:59:57.609148 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 13:59:57.612378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 13:59:57.612811 ==
6391 13:59:57.615932 DQS Delay:
6392 13:59:57.616567 DQS0 = 27, DQS1 = 43
6393 13:59:57.619147 DQM Delay:
6394 13:59:57.619555 DQM0 = 12, DQM1 = 13
6395 13:59:57.619879 DQ Delay:
6396 13:59:57.622500 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6397 13:59:57.625636 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6398 13:59:57.629500 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6399 13:59:57.632582 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6400 13:59:57.633122
6401 13:59:57.633462
6402 13:59:57.633765 ==
6403 13:59:57.636280 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 13:59:57.642174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 13:59:57.642708 ==
6406 13:59:57.643075
6407 13:59:57.643384
6408 13:59:57.643674 TX Vref Scan disable
6409 13:59:57.645584 == TX Byte 0 ==
6410 13:59:57.648967 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 13:59:57.652225 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 13:59:57.655634 == TX Byte 1 ==
6413 13:59:57.659349 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6414 13:59:57.662417 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6415 13:59:57.662931 ==
6416 13:59:57.665675 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 13:59:57.672659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 13:59:57.673176 ==
6419 13:59:57.673508
6420 13:59:57.673809
6421 13:59:57.675550 TX Vref Scan disable
6422 13:59:57.676058 == TX Byte 0 ==
6423 13:59:57.678512 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 13:59:57.682566 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 13:59:57.685721 == TX Byte 1 ==
6426 13:59:57.688921 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6427 13:59:57.692173 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6428 13:59:57.695470
6429 13:59:57.695886 [DATLAT]
6430 13:59:57.696216 Freq=400, CH0 RK0
6431 13:59:57.696577
6432 13:59:57.699101 DATLAT Default: 0xf
6433 13:59:57.699515 0, 0xFFFF, sum = 0
6434 13:59:57.702343 1, 0xFFFF, sum = 0
6435 13:59:57.702926 2, 0xFFFF, sum = 0
6436 13:59:57.705544 3, 0xFFFF, sum = 0
6437 13:59:57.706238 4, 0xFFFF, sum = 0
6438 13:59:57.708932 5, 0xFFFF, sum = 0
6439 13:59:57.709603 6, 0xFFFF, sum = 0
6440 13:59:57.712352 7, 0xFFFF, sum = 0
6441 13:59:57.715423 8, 0xFFFF, sum = 0
6442 13:59:57.715841 9, 0xFFFF, sum = 0
6443 13:59:57.719226 10, 0xFFFF, sum = 0
6444 13:59:57.719640 11, 0xFFFF, sum = 0
6445 13:59:57.722039 12, 0xFFFF, sum = 0
6446 13:59:57.722459 13, 0x0, sum = 1
6447 13:59:57.725636 14, 0x0, sum = 2
6448 13:59:57.726092 15, 0x0, sum = 3
6449 13:59:57.728926 16, 0x0, sum = 4
6450 13:59:57.729349 best_step = 14
6451 13:59:57.729676
6452 13:59:57.730019 ==
6453 13:59:57.732125 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 13:59:57.735289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 13:59:57.735588 ==
6456 13:59:57.738898 RX Vref Scan: 1
6457 13:59:57.739194
6458 13:59:57.741973 RX Vref 0 -> 0, step: 1
6459 13:59:57.742199
6460 13:59:57.742375 RX Delay -327 -> 252, step: 8
6461 13:59:57.742546
6462 13:59:57.745447 Set Vref, RX VrefLevel [Byte0]: 59
6463 13:59:57.748668 [Byte1]: 49
6464 13:59:57.753778
6465 13:59:57.753963 Final RX Vref Byte 0 = 59 to rank0
6466 13:59:57.757014 Final RX Vref Byte 1 = 49 to rank0
6467 13:59:57.760252 Final RX Vref Byte 0 = 59 to rank1
6468 13:59:57.763630 Final RX Vref Byte 1 = 49 to rank1==
6469 13:59:57.766855 Dram Type= 6, Freq= 0, CH_0, rank 0
6470 13:59:57.774193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 13:59:57.774364 ==
6472 13:59:57.774442 DQS Delay:
6473 13:59:57.777251 DQS0 = 28, DQS1 = 48
6474 13:59:57.777421 DQM Delay:
6475 13:59:57.777499 DQM0 = 12, DQM1 = 15
6476 13:59:57.780896 DQ Delay:
6477 13:59:57.784026 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6478 13:59:57.784196 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6479 13:59:57.787260 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6480 13:59:57.790450 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6481 13:59:57.790621
6482 13:59:57.793771
6483 13:59:57.800286 [DQSOSCAuto] RK0, (LSB)MR18= 0xa59d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6484 13:59:57.803910 CH0 RK0: MR19=C0C, MR18=A59D
6485 13:59:57.810483 CH0_RK0: MR19=0xC0C, MR18=0xA59D, DQSOSC=389, MR23=63, INC=390, DEC=260
6486 13:59:57.810666 ==
6487 13:59:57.813813 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 13:59:57.816990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 13:59:57.817186 ==
6490 13:59:57.820077 [Gating] SW mode calibration
6491 13:59:57.826945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 13:59:57.833796 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6493 13:59:57.837317 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 13:59:57.840207 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 13:59:57.846870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 13:59:57.850235 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 13:59:57.854365 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 13:59:57.857487 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 13:59:57.864408 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 13:59:57.867703 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 13:59:57.870815 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 13:59:57.874098 Total UI for P1: 0, mck2ui 16
6503 13:59:57.877404 best dqsien dly found for B0: ( 0, 14, 24)
6504 13:59:57.880830 Total UI for P1: 0, mck2ui 16
6505 13:59:57.884349 best dqsien dly found for B1: ( 0, 14, 24)
6506 13:59:57.887604 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6507 13:59:57.890736 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6508 13:59:57.894077
6509 13:59:57.897246 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6510 13:59:57.900363 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 13:59:57.904095 [Gating] SW calibration Done
6512 13:59:57.904564 ==
6513 13:59:57.907155 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 13:59:57.910261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 13:59:57.910730 ==
6516 13:59:57.911100 RX Vref Scan: 0
6517 13:59:57.913627
6518 13:59:57.914123 RX Vref 0 -> 0, step: 1
6519 13:59:57.914663
6520 13:59:57.917457 RX Delay -410 -> 252, step: 16
6521 13:59:57.920424 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6522 13:59:57.927171 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6523 13:59:57.930579 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6524 13:59:57.933783 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6525 13:59:57.937200 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6526 13:59:57.944012 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6527 13:59:57.946832 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6528 13:59:57.950232 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6529 13:59:57.954041 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6530 13:59:57.960778 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6531 13:59:57.963811 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6532 13:59:57.966705 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6533 13:59:57.970799 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6534 13:59:57.976975 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6535 13:59:57.980341 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6536 13:59:57.983695 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6537 13:59:57.984269 ==
6538 13:59:57.986814 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 13:59:57.993530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 13:59:57.994139 ==
6541 13:59:57.994519 DQS Delay:
6542 13:59:57.994864 DQS0 = 27, DQS1 = 43
6543 13:59:57.997163 DQM Delay:
6544 13:59:57.997733 DQM0 = 9, DQM1 = 16
6545 13:59:58.000098 DQ Delay:
6546 13:59:58.000566 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6547 13:59:58.003342 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6548 13:59:58.006664 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6549 13:59:58.010253 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6550 13:59:58.010719
6551 13:59:58.011086
6552 13:59:58.013357 ==
6553 13:59:58.013821 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 13:59:58.020094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 13:59:58.020660 ==
6556 13:59:58.021035
6557 13:59:58.021380
6558 13:59:58.023460 TX Vref Scan disable
6559 13:59:58.024048 == TX Byte 0 ==
6560 13:59:58.026661 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6561 13:59:58.033464 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6562 13:59:58.034038 == TX Byte 1 ==
6563 13:59:58.036869 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6564 13:59:58.039922 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6565 13:59:58.043622 ==
6566 13:59:58.046455 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 13:59:58.050013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 13:59:58.050492 ==
6569 13:59:58.050865
6570 13:59:58.051211
6571 13:59:58.053469 TX Vref Scan disable
6572 13:59:58.054092 == TX Byte 0 ==
6573 13:59:58.056807 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6574 13:59:58.063544 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6575 13:59:58.064126 == TX Byte 1 ==
6576 13:59:58.066614 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6577 13:59:58.070000 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6578 13:59:58.072974
6579 13:59:58.073439 [DATLAT]
6580 13:59:58.073812 Freq=400, CH0 RK1
6581 13:59:58.074201
6582 13:59:58.076615 DATLAT Default: 0xe
6583 13:59:58.077186 0, 0xFFFF, sum = 0
6584 13:59:58.079855 1, 0xFFFF, sum = 0
6585 13:59:58.080440 2, 0xFFFF, sum = 0
6586 13:59:58.083333 3, 0xFFFF, sum = 0
6587 13:59:58.083912 4, 0xFFFF, sum = 0
6588 13:59:58.086400 5, 0xFFFF, sum = 0
6589 13:59:58.089902 6, 0xFFFF, sum = 0
6590 13:59:58.090559 7, 0xFFFF, sum = 0
6591 13:59:58.093286 8, 0xFFFF, sum = 0
6592 13:59:58.093872 9, 0xFFFF, sum = 0
6593 13:59:58.096281 10, 0xFFFF, sum = 0
6594 13:59:58.096757 11, 0xFFFF, sum = 0
6595 13:59:58.099604 12, 0xFFFF, sum = 0
6596 13:59:58.100082 13, 0x0, sum = 1
6597 13:59:58.103077 14, 0x0, sum = 2
6598 13:59:58.103553 15, 0x0, sum = 3
6599 13:59:58.106316 16, 0x0, sum = 4
6600 13:59:58.106792 best_step = 14
6601 13:59:58.107163
6602 13:59:58.107510 ==
6603 13:59:58.109786 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 13:59:58.113143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 13:59:58.113721 ==
6606 13:59:58.116631 RX Vref Scan: 0
6607 13:59:58.117205
6608 13:59:58.119914 RX Vref 0 -> 0, step: 1
6609 13:59:58.120493
6610 13:59:58.120868 RX Delay -327 -> 252, step: 8
6611 13:59:58.128420 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6612 13:59:58.131649 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6613 13:59:58.135006 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6614 13:59:58.138365 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6615 13:59:58.145388 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6616 13:59:58.148193 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6617 13:59:58.151614 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6618 13:59:58.155149 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6619 13:59:58.161907 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6620 13:59:58.165177 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6621 13:59:58.168609 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6622 13:59:58.171928 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6623 13:59:58.178662 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6624 13:59:58.182017 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6625 13:59:58.184939 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6626 13:59:58.191633 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6627 13:59:58.192211 ==
6628 13:59:58.195156 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 13:59:58.198569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 13:59:58.199149 ==
6631 13:59:58.199590 DQS Delay:
6632 13:59:58.201458 DQS0 = 28, DQS1 = 40
6633 13:59:58.202181 DQM Delay:
6634 13:59:58.205255 DQM0 = 10, DQM1 = 11
6635 13:59:58.205818 DQ Delay:
6636 13:59:58.208343 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6637 13:59:58.211451 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6638 13:59:58.215199 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6639 13:59:58.218295 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6640 13:59:58.218767
6641 13:59:58.219140
6642 13:59:58.224911 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6643 13:59:58.228485 CH0 RK1: MR19=C0C, MR18=B86B
6644 13:59:58.234745 CH0_RK1: MR19=0xC0C, MR18=0xB86B, DQSOSC=386, MR23=63, INC=396, DEC=264
6645 13:59:58.237970 [RxdqsGatingPostProcess] freq 400
6646 13:59:58.245219 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6647 13:59:58.245800 best DQS0 dly(2T, 0.5T) = (0, 10)
6648 13:59:58.247992 best DQS1 dly(2T, 0.5T) = (0, 10)
6649 13:59:58.251686 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6650 13:59:58.254861 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6651 13:59:58.258308 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 13:59:58.261408 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 13:59:58.264919 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 13:59:58.268433 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 13:59:58.271263 Pre-setting of DQS Precalculation
6656 13:59:58.274740 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6657 13:59:58.278020 ==
6658 13:59:58.281044 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 13:59:58.284222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 13:59:58.284632 ==
6661 13:59:58.287820 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 13:59:58.294625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6663 13:59:58.297879 [CA 0] Center 36 (8~64) winsize 57
6664 13:59:58.301331 [CA 1] Center 36 (8~64) winsize 57
6665 13:59:58.304878 [CA 2] Center 36 (8~64) winsize 57
6666 13:59:58.307720 [CA 3] Center 36 (8~64) winsize 57
6667 13:59:58.311294 [CA 4] Center 36 (8~64) winsize 57
6668 13:59:58.314750 [CA 5] Center 36 (8~64) winsize 57
6669 13:59:58.315320
6670 13:59:58.317784 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6671 13:59:58.318393
6672 13:59:58.321685 [CATrainingPosCal] consider 1 rank data
6673 13:59:58.324873 u2DelayCellTimex100 = 270/100 ps
6674 13:59:58.328047 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 13:59:58.330909 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 13:59:58.334200 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 13:59:58.337799 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 13:59:58.344354 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 13:59:58.347615 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 13:59:58.348085
6681 13:59:58.350904 CA PerBit enable=1, Macro0, CA PI delay=36
6682 13:59:58.351375
6683 13:59:58.354309 [CBTSetCACLKResult] CA Dly = 36
6684 13:59:58.354955 CS Dly: 1 (0~32)
6685 13:59:58.355407 ==
6686 13:59:58.357452 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 13:59:58.361203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 13:59:58.364591 ==
6689 13:59:58.368194 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6690 13:59:58.374643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6691 13:59:58.378208 [CA 0] Center 36 (8~64) winsize 57
6692 13:59:58.381100 [CA 1] Center 36 (8~64) winsize 57
6693 13:59:58.384770 [CA 2] Center 36 (8~64) winsize 57
6694 13:59:58.387980 [CA 3] Center 36 (8~64) winsize 57
6695 13:59:58.390997 [CA 4] Center 36 (8~64) winsize 57
6696 13:59:58.394408 [CA 5] Center 36 (8~64) winsize 57
6697 13:59:58.394974
6698 13:59:58.397575 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6699 13:59:58.398166
6700 13:59:58.400780 [CATrainingPosCal] consider 2 rank data
6701 13:59:58.404276 u2DelayCellTimex100 = 270/100 ps
6702 13:59:58.407733 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 13:59:58.410837 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 13:59:58.414382 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 13:59:58.417507 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 13:59:58.421360 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 13:59:58.424639 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 13:59:58.425215
6709 13:59:58.427867 CA PerBit enable=1, Macro0, CA PI delay=36
6710 13:59:58.430956
6711 13:59:58.431425 [CBTSetCACLKResult] CA Dly = 36
6712 13:59:58.434443 CS Dly: 1 (0~32)
6713 13:59:58.434912
6714 13:59:58.437584 ----->DramcWriteLeveling(PI) begin...
6715 13:59:58.438080 ==
6716 13:59:58.440682 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 13:59:58.444477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 13:59:58.445073 ==
6719 13:59:58.447594 Write leveling (Byte 0): 40 => 8
6720 13:59:58.450825 Write leveling (Byte 1): 32 => 0
6721 13:59:58.453917 DramcWriteLeveling(PI) end<-----
6722 13:59:58.454426
6723 13:59:58.454837 ==
6724 13:59:58.457627 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 13:59:58.460828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 13:59:58.461436 ==
6727 13:59:58.464547 [Gating] SW mode calibration
6728 13:59:58.470876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6729 13:59:58.477750 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6730 13:59:58.480689 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6731 13:59:58.484589 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 13:59:58.491126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 13:59:58.494586 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 13:59:58.497776 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 13:59:58.503957 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 13:59:58.507791 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 13:59:58.510641 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 13:59:58.517684 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 13:59:58.521408 Total UI for P1: 0, mck2ui 16
6740 13:59:58.524622 best dqsien dly found for B0: ( 0, 14, 24)
6741 13:59:58.525189 Total UI for P1: 0, mck2ui 16
6742 13:59:58.530865 best dqsien dly found for B1: ( 0, 14, 24)
6743 13:59:58.534199 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6744 13:59:58.537623 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6745 13:59:58.538213
6746 13:59:58.541232 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6747 13:59:58.544044 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 13:59:58.547572 [Gating] SW calibration Done
6749 13:59:58.548042 ==
6750 13:59:58.550792 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 13:59:58.554129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 13:59:58.554606 ==
6753 13:59:58.557281 RX Vref Scan: 0
6754 13:59:58.557773
6755 13:59:58.558193 RX Vref 0 -> 0, step: 1
6756 13:59:58.560616
6757 13:59:58.561173 RX Delay -410 -> 252, step: 16
6758 13:59:58.567059 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6759 13:59:58.570722 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6760 13:59:58.574049 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6761 13:59:58.577389 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6762 13:59:58.584184 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6763 13:59:58.587654 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6764 13:59:58.590704 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6765 13:59:58.593967 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6766 13:59:58.600769 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6767 13:59:58.603640 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6768 13:59:58.607362 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6769 13:59:58.610602 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6770 13:59:58.616978 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6771 13:59:58.620233 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6772 13:59:58.623977 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6773 13:59:58.627034 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6774 13:59:58.630673 ==
6775 13:59:58.633813 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 13:59:58.637210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 13:59:58.637639 ==
6778 13:59:58.638020 DQS Delay:
6779 13:59:58.640296 DQS0 = 27, DQS1 = 43
6780 13:59:58.640719 DQM Delay:
6781 13:59:58.643658 DQM0 = 6, DQM1 = 18
6782 13:59:58.644084 DQ Delay:
6783 13:59:58.647130 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6784 13:59:58.650383 DQ4 =0, DQ5 =24, DQ6 =16, DQ7 =0
6785 13:59:58.653726 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6786 13:59:58.657099 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =32
6787 13:59:58.657519
6788 13:59:58.657852
6789 13:59:58.658298 ==
6790 13:59:58.660592 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 13:59:58.663763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 13:59:58.664388 ==
6793 13:59:58.664868
6794 13:59:58.665252
6795 13:59:58.667107 TX Vref Scan disable
6796 13:59:58.667525 == TX Byte 0 ==
6797 13:59:58.673399 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 13:59:58.677063 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 13:59:58.677484 == TX Byte 1 ==
6800 13:59:58.683685 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6801 13:59:58.686916 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6802 13:59:58.687342 ==
6803 13:59:58.690219 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 13:59:58.693498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 13:59:58.694072 ==
6806 13:59:58.694415
6807 13:59:58.694724
6808 13:59:58.697176 TX Vref Scan disable
6809 13:59:58.697697 == TX Byte 0 ==
6810 13:59:58.703435 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 13:59:58.706812 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 13:59:58.707236 == TX Byte 1 ==
6813 13:59:58.713261 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6814 13:59:58.717260 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6815 13:59:58.717792
6816 13:59:58.718184 [DATLAT]
6817 13:59:58.720094 Freq=400, CH1 RK0
6818 13:59:58.720520
6819 13:59:58.720851 DATLAT Default: 0xf
6820 13:59:58.723676 0, 0xFFFF, sum = 0
6821 13:59:58.724108 1, 0xFFFF, sum = 0
6822 13:59:58.726516 2, 0xFFFF, sum = 0
6823 13:59:58.726946 3, 0xFFFF, sum = 0
6824 13:59:58.730076 4, 0xFFFF, sum = 0
6825 13:59:58.730511 5, 0xFFFF, sum = 0
6826 13:59:58.733306 6, 0xFFFF, sum = 0
6827 13:59:58.733737 7, 0xFFFF, sum = 0
6828 13:59:58.737079 8, 0xFFFF, sum = 0
6829 13:59:58.739965 9, 0xFFFF, sum = 0
6830 13:59:58.740401 10, 0xFFFF, sum = 0
6831 13:59:58.743083 11, 0xFFFF, sum = 0
6832 13:59:58.743516 12, 0xFFFF, sum = 0
6833 13:59:58.746572 13, 0x0, sum = 1
6834 13:59:58.747109 14, 0x0, sum = 2
6835 13:59:58.750044 15, 0x0, sum = 3
6836 13:59:58.750480 16, 0x0, sum = 4
6837 13:59:58.750824 best_step = 14
6838 13:59:58.751218
6839 13:59:58.753321 ==
6840 13:59:58.756665 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 13:59:58.760356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 13:59:58.760787 ==
6843 13:59:58.761126 RX Vref Scan: 1
6844 13:59:58.761442
6845 13:59:58.763212 RX Vref 0 -> 0, step: 1
6846 13:59:58.763635
6847 13:59:58.766462 RX Delay -327 -> 252, step: 8
6848 13:59:58.766889
6849 13:59:58.769858 Set Vref, RX VrefLevel [Byte0]: 53
6850 13:59:58.772904 [Byte1]: 50
6851 13:59:58.776796
6852 13:59:58.777323 Final RX Vref Byte 0 = 53 to rank0
6853 13:59:58.779951 Final RX Vref Byte 1 = 50 to rank0
6854 13:59:58.783381 Final RX Vref Byte 0 = 53 to rank1
6855 13:59:58.786876 Final RX Vref Byte 1 = 50 to rank1==
6856 13:59:58.790112 Dram Type= 6, Freq= 0, CH_1, rank 0
6857 13:59:58.796809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 13:59:58.797241 ==
6859 13:59:58.797580 DQS Delay:
6860 13:59:58.800273 DQS0 = 28, DQS1 = 40
6861 13:59:58.800718 DQM Delay:
6862 13:59:58.801052 DQM0 = 7, DQM1 = 12
6863 13:59:58.803360 DQ Delay:
6864 13:59:58.806687 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6865 13:59:58.807112 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6866 13:59:58.810036 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6867 13:59:58.813141 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6868 13:59:58.813566
6869 13:59:58.813903
6870 13:59:58.823320 [DQSOSCAuto] RK0, (LSB)MR18= 0x90cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6871 13:59:58.826693 CH1 RK0: MR19=C0C, MR18=90CB
6872 13:59:58.833610 CH1_RK0: MR19=0xC0C, MR18=0x90CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6873 13:59:58.834199 ==
6874 13:59:58.836373 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 13:59:58.839655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 13:59:58.840082 ==
6877 13:59:58.843354 [Gating] SW mode calibration
6878 13:59:58.850050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6879 13:59:58.853148 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6880 13:59:58.859895 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6881 13:59:58.862910 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 13:59:58.866146 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 13:59:58.872798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 13:59:58.876201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 13:59:58.879687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 13:59:58.886091 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 13:59:58.889355 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 13:59:58.893029 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 13:59:58.896141 Total UI for P1: 0, mck2ui 16
6890 13:59:58.899157 best dqsien dly found for B0: ( 0, 14, 24)
6891 13:59:58.902850 Total UI for P1: 0, mck2ui 16
6892 13:59:58.906027 best dqsien dly found for B1: ( 0, 14, 24)
6893 13:59:58.909386 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6894 13:59:58.915970 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6895 13:59:58.916532
6896 13:59:58.919126 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6897 13:59:58.922794 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 13:59:58.926047 [Gating] SW calibration Done
6899 13:59:58.926605 ==
6900 13:59:58.929229 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 13:59:58.932660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 13:59:58.933232 ==
6903 13:59:58.935818 RX Vref Scan: 0
6904 13:59:58.936282
6905 13:59:58.936650 RX Vref 0 -> 0, step: 1
6906 13:59:58.937219
6907 13:59:58.939195 RX Delay -410 -> 252, step: 16
6908 13:59:58.942430 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6909 13:59:58.948873 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6910 13:59:58.952475 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6911 13:59:58.955886 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6912 13:59:58.959210 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6913 13:59:58.965765 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6914 13:59:58.968915 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6915 13:59:58.972275 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6916 13:59:58.975518 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6917 13:59:58.982462 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6918 13:59:58.985391 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6919 13:59:58.989071 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6920 13:59:58.992177 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6921 13:59:58.998787 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6922 13:59:59.002140 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6923 13:59:59.005473 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6924 13:59:59.006012 ==
6925 13:59:59.008864 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 13:59:59.015609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 13:59:59.016060 ==
6928 13:59:59.016401 DQS Delay:
6929 13:59:59.016717 DQS0 = 35, DQS1 = 43
6930 13:59:59.018780 DQM Delay:
6931 13:59:59.019209 DQM0 = 18, DQM1 = 20
6932 13:59:59.022282 DQ Delay:
6933 13:59:59.025562 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6934 13:59:59.028863 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6935 13:59:59.029447 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6936 13:59:59.032423 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6937 13:59:59.035645
6938 13:59:59.036232
6939 13:59:59.036606 ==
6940 13:59:59.038867 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 13:59:59.042453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 13:59:59.043038 ==
6943 13:59:59.043419
6944 13:59:59.043768
6945 13:59:59.045613 TX Vref Scan disable
6946 13:59:59.046124 == TX Byte 0 ==
6947 13:59:59.048678 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6948 13:59:59.055401 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6949 13:59:59.055980 == TX Byte 1 ==
6950 13:59:59.058689 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6951 13:59:59.065332 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6952 13:59:59.065929 ==
6953 13:59:59.068859 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 13:59:59.072265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 13:59:59.072864 ==
6956 13:59:59.073243
6957 13:59:59.073592
6958 13:59:59.075406 TX Vref Scan disable
6959 13:59:59.075873 == TX Byte 0 ==
6960 13:59:59.078625 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6961 13:59:59.085115 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6962 13:59:59.085550 == TX Byte 1 ==
6963 13:59:59.088822 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6964 13:59:59.095166 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6965 13:59:59.095593
6966 13:59:59.095955 [DATLAT]
6967 13:59:59.098484 Freq=400, CH1 RK1
6968 13:59:59.098909
6969 13:59:59.099244 DATLAT Default: 0xe
6970 13:59:59.101430 0, 0xFFFF, sum = 0
6971 13:59:59.101882 1, 0xFFFF, sum = 0
6972 13:59:59.104937 2, 0xFFFF, sum = 0
6973 13:59:59.105507 3, 0xFFFF, sum = 0
6974 13:59:59.108428 4, 0xFFFF, sum = 0
6975 13:59:59.108926 5, 0xFFFF, sum = 0
6976 13:59:59.111629 6, 0xFFFF, sum = 0
6977 13:59:59.112113 7, 0xFFFF, sum = 0
6978 13:59:59.114742 8, 0xFFFF, sum = 0
6979 13:59:59.115204 9, 0xFFFF, sum = 0
6980 13:59:59.118288 10, 0xFFFF, sum = 0
6981 13:59:59.118727 11, 0xFFFF, sum = 0
6982 13:59:59.121598 12, 0xFFFF, sum = 0
6983 13:59:59.122074 13, 0x0, sum = 1
6984 13:59:59.124828 14, 0x0, sum = 2
6985 13:59:59.125264 15, 0x0, sum = 3
6986 13:59:59.128464 16, 0x0, sum = 4
6987 13:59:59.129018 best_step = 14
6988 13:59:59.129454
6989 13:59:59.129996 ==
6990 13:59:59.131523 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 13:59:59.138514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 13:59:59.139078 ==
6993 13:59:59.139518 RX Vref Scan: 0
6994 13:59:59.139924
6995 13:59:59.141605 RX Vref 0 -> 0, step: 1
6996 13:59:59.142146
6997 13:59:59.145185 RX Delay -327 -> 252, step: 8
6998 13:59:59.151827 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6999 13:59:59.154952 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
7000 13:59:59.158354 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7001 13:59:59.161858 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
7002 13:59:59.168336 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7003 13:59:59.171905 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7004 13:59:59.174753 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7005 13:59:59.178659 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
7006 13:59:59.184866 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7007 13:59:59.188123 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7008 13:59:59.191229 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7009 13:59:59.195145 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7010 13:59:59.201460 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7011 13:59:59.204719 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7012 13:59:59.207947 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7013 13:59:59.211248 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7014 13:59:59.214499 ==
7015 13:59:59.217723 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 13:59:59.221040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 13:59:59.221460 ==
7018 13:59:59.222007 DQS Delay:
7019 13:59:59.224658 DQS0 = 32, DQS1 = 36
7020 13:59:59.225081 DQM Delay:
7021 13:59:59.227577 DQM0 = 12, DQM1 = 11
7022 13:59:59.227998 DQ Delay:
7023 13:59:59.231288 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7024 13:59:59.234327 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
7025 13:59:59.237884 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7026 13:59:59.241373 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7027 13:59:59.241918
7028 13:59:59.242302
7029 13:59:59.247537 [DQSOSCAuto] RK1, (LSB)MR18= 0xab53, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7030 13:59:59.251140 CH1 RK1: MR19=C0C, MR18=AB53
7031 13:59:59.257697 CH1_RK1: MR19=0xC0C, MR18=0xAB53, DQSOSC=388, MR23=63, INC=392, DEC=261
7032 13:59:59.261221 [RxdqsGatingPostProcess] freq 400
7033 13:59:59.267995 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7034 13:59:59.268543 best DQS0 dly(2T, 0.5T) = (0, 10)
7035 13:59:59.271173 best DQS1 dly(2T, 0.5T) = (0, 10)
7036 13:59:59.274237 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7037 13:59:59.277822 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7038 13:59:59.280917 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 13:59:59.284076 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 13:59:59.287678 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 13:59:59.290792 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 13:59:59.294364 Pre-setting of DQS Precalculation
7043 13:59:59.297921 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7044 13:59:59.307544 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7045 13:59:59.314309 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7046 13:59:59.314731
7047 13:59:59.315062
7048 13:59:59.317526 [Calibration Summary] 800 Mbps
7049 13:59:59.317982 CH 0, Rank 0
7050 13:59:59.320955 SW Impedance : PASS
7051 13:59:59.321503 DUTY Scan : NO K
7052 13:59:59.324230 ZQ Calibration : PASS
7053 13:59:59.327637 Jitter Meter : NO K
7054 13:59:59.328190 CBT Training : PASS
7055 13:59:59.330974 Write leveling : PASS
7056 13:59:59.334052 RX DQS gating : PASS
7057 13:59:59.334524 RX DQ/DQS(RDDQC) : PASS
7058 13:59:59.337708 TX DQ/DQS : PASS
7059 13:59:59.341204 RX DATLAT : PASS
7060 13:59:59.341749 RX DQ/DQS(Engine): PASS
7061 13:59:59.344443 TX OE : NO K
7062 13:59:59.344867 All Pass.
7063 13:59:59.345203
7064 13:59:59.348048 CH 0, Rank 1
7065 13:59:59.348571 SW Impedance : PASS
7066 13:59:59.350867 DUTY Scan : NO K
7067 13:59:59.351292 ZQ Calibration : PASS
7068 13:59:59.354223 Jitter Meter : NO K
7069 13:59:59.357454 CBT Training : PASS
7070 13:59:59.357878 Write leveling : NO K
7071 13:59:59.361364 RX DQS gating : PASS
7072 13:59:59.364673 RX DQ/DQS(RDDQC) : PASS
7073 13:59:59.365321 TX DQ/DQS : PASS
7074 13:59:59.367966 RX DATLAT : PASS
7075 13:59:59.371125 RX DQ/DQS(Engine): PASS
7076 13:59:59.371719 TX OE : NO K
7077 13:59:59.374080 All Pass.
7078 13:59:59.374545
7079 13:59:59.374914 CH 1, Rank 0
7080 13:59:59.377688 SW Impedance : PASS
7081 13:59:59.378360 DUTY Scan : NO K
7082 13:59:59.381070 ZQ Calibration : PASS
7083 13:59:59.384731 Jitter Meter : NO K
7084 13:59:59.385322 CBT Training : PASS
7085 13:59:59.388090 Write leveling : PASS
7086 13:59:59.391187 RX DQS gating : PASS
7087 13:59:59.391778 RX DQ/DQS(RDDQC) : PASS
7088 13:59:59.394432 TX DQ/DQS : PASS
7089 13:59:59.395027 RX DATLAT : PASS
7090 13:59:59.397692 RX DQ/DQS(Engine): PASS
7091 13:59:59.400839 TX OE : NO K
7092 13:59:59.401333 All Pass.
7093 13:59:59.401773
7094 13:59:59.402182 CH 1, Rank 1
7095 13:59:59.404823 SW Impedance : PASS
7096 13:59:59.407654 DUTY Scan : NO K
7097 13:59:59.408135 ZQ Calibration : PASS
7098 13:59:59.410823 Jitter Meter : NO K
7099 13:59:59.414154 CBT Training : PASS
7100 13:59:59.414628 Write leveling : NO K
7101 13:59:59.417504 RX DQS gating : PASS
7102 13:59:59.420691 RX DQ/DQS(RDDQC) : PASS
7103 13:59:59.421189 TX DQ/DQS : PASS
7104 13:59:59.424048 RX DATLAT : PASS
7105 13:59:59.427731 RX DQ/DQS(Engine): PASS
7106 13:59:59.428331 TX OE : NO K
7107 13:59:59.430653 All Pass.
7108 13:59:59.431151
7109 13:59:59.431672 DramC Write-DBI off
7110 13:59:59.434131 PER_BANK_REFRESH: Hybrid Mode
7111 13:59:59.434557 TX_TRACKING: ON
7112 13:59:59.444176 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7113 13:59:59.447342 [FAST_K] Save calibration result to emmc
7114 13:59:59.451054 dramc_set_vcore_voltage set vcore to 725000
7115 13:59:59.454212 Read voltage for 1600, 0
7116 13:59:59.454641 Vio18 = 0
7117 13:59:59.456993 Vcore = 725000
7118 13:59:59.457421 Vdram = 0
7119 13:59:59.457757 Vddq = 0
7120 13:59:59.460334 Vmddr = 0
7121 13:59:59.464561 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7122 13:59:59.470681 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7123 13:59:59.471280 MEM_TYPE=3, freq_sel=13
7124 13:59:59.474267 sv_algorithm_assistance_LP4_3733
7125 13:59:59.477116 ============ PULL DRAM RESETB DOWN ============
7126 13:59:59.484210 ========== PULL DRAM RESETB DOWN end =========
7127 13:59:59.487419 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7128 13:59:59.490843 ===================================
7129 13:59:59.494529 LPDDR4 DRAM CONFIGURATION
7130 13:59:59.497166 ===================================
7131 13:59:59.497646 EX_ROW_EN[0] = 0x0
7132 13:59:59.500781 EX_ROW_EN[1] = 0x0
7133 13:59:59.501368 LP4Y_EN = 0x0
7134 13:59:59.503859 WORK_FSP = 0x1
7135 13:59:59.506948 WL = 0x5
7136 13:59:59.507422 RL = 0x5
7137 13:59:59.510675 BL = 0x2
7138 13:59:59.511148 RPST = 0x0
7139 13:59:59.513659 RD_PRE = 0x0
7140 13:59:59.514126 WR_PRE = 0x1
7141 13:59:59.517212 WR_PST = 0x1
7142 13:59:59.517763 DBI_WR = 0x0
7143 13:59:59.520486 DBI_RD = 0x0
7144 13:59:59.521012 OTF = 0x1
7145 13:59:59.523957 ===================================
7146 13:59:59.527383 ===================================
7147 13:59:59.530345 ANA top config
7148 13:59:59.533911 ===================================
7149 13:59:59.534395 DLL_ASYNC_EN = 0
7150 13:59:59.537320 ALL_SLAVE_EN = 0
7151 13:59:59.540534 NEW_RANK_MODE = 1
7152 13:59:59.544034 DLL_IDLE_MODE = 1
7153 13:59:59.544464 LP45_APHY_COMB_EN = 1
7154 13:59:59.547344 TX_ODT_DIS = 0
7155 13:59:59.550574 NEW_8X_MODE = 1
7156 13:59:59.553568 ===================================
7157 13:59:59.557215 ===================================
7158 13:59:59.560607 data_rate = 3200
7159 13:59:59.563734 CKR = 1
7160 13:59:59.567116 DQ_P2S_RATIO = 8
7161 13:59:59.570385 ===================================
7162 13:59:59.570826 CA_P2S_RATIO = 8
7163 13:59:59.573613 DQ_CA_OPEN = 0
7164 13:59:59.577341 DQ_SEMI_OPEN = 0
7165 13:59:59.580728 CA_SEMI_OPEN = 0
7166 13:59:59.584127 CA_FULL_RATE = 0
7167 13:59:59.587216 DQ_CKDIV4_EN = 0
7168 13:59:59.587768 CA_CKDIV4_EN = 0
7169 13:59:59.590598 CA_PREDIV_EN = 0
7170 13:59:59.594058 PH8_DLY = 12
7171 13:59:59.597017 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7172 13:59:59.600331 DQ_AAMCK_DIV = 4
7173 13:59:59.603400 CA_AAMCK_DIV = 4
7174 13:59:59.603915 CA_ADMCK_DIV = 4
7175 13:59:59.606807 DQ_TRACK_CA_EN = 0
7176 13:59:59.610180 CA_PICK = 1600
7177 13:59:59.613358 CA_MCKIO = 1600
7178 13:59:59.616654 MCKIO_SEMI = 0
7179 13:59:59.620630 PLL_FREQ = 3068
7180 13:59:59.623504 DQ_UI_PI_RATIO = 32
7181 13:59:59.624178 CA_UI_PI_RATIO = 0
7182 13:59:59.626604 ===================================
7183 13:59:59.629773 ===================================
7184 13:59:59.633354 memory_type:LPDDR4
7185 13:59:59.636436 GP_NUM : 10
7186 13:59:59.637019 SRAM_EN : 1
7187 13:59:59.639596 MD32_EN : 0
7188 13:59:59.642810 ===================================
7189 13:59:59.646453 [ANA_INIT] >>>>>>>>>>>>>>
7190 13:59:59.649686 <<<<<< [CONFIGURE PHASE]: ANA_TX
7191 13:59:59.652781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7192 13:59:59.656399 ===================================
7193 13:59:59.656838 data_rate = 3200,PCW = 0X7600
7194 13:59:59.659571 ===================================
7195 13:59:59.666301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7196 13:59:59.669832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7197 13:59:59.676101 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 13:59:59.679287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7199 13:59:59.682471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7200 13:59:59.685901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7201 13:59:59.689633 [ANA_INIT] flow start
7202 13:59:59.693111 [ANA_INIT] PLL >>>>>>>>
7203 13:59:59.693638 [ANA_INIT] PLL <<<<<<<<
7204 13:59:59.696311 [ANA_INIT] MIDPI >>>>>>>>
7205 13:59:59.699222 [ANA_INIT] MIDPI <<<<<<<<
7206 13:59:59.699645 [ANA_INIT] DLL >>>>>>>>
7207 13:59:59.702590 [ANA_INIT] DLL <<<<<<<<
7208 13:59:59.705812 [ANA_INIT] flow end
7209 13:59:59.709098 ============ LP4 DIFF to SE enter ============
7210 13:59:59.712356 ============ LP4 DIFF to SE exit ============
7211 13:59:59.716255 [ANA_INIT] <<<<<<<<<<<<<
7212 13:59:59.719155 [Flow] Enable top DCM control >>>>>
7213 13:59:59.722548 [Flow] Enable top DCM control <<<<<
7214 13:59:59.725932 Enable DLL master slave shuffle
7215 13:59:59.729035 ==============================================================
7216 13:59:59.732421 Gating Mode config
7217 13:59:59.739139 ==============================================================
7218 13:59:59.739625 Config description:
7219 13:59:59.749214 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7220 13:59:59.755701 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7221 13:59:59.762683 SELPH_MODE 0: By rank 1: By Phase
7222 13:59:59.765465 ==============================================================
7223 13:59:59.769112 GAT_TRACK_EN = 1
7224 13:59:59.772024 RX_GATING_MODE = 2
7225 13:59:59.775797 RX_GATING_TRACK_MODE = 2
7226 13:59:59.779061 SELPH_MODE = 1
7227 13:59:59.782103 PICG_EARLY_EN = 1
7228 13:59:59.785831 VALID_LAT_VALUE = 1
7229 13:59:59.788704 ==============================================================
7230 13:59:59.792318 Enter into Gating configuration >>>>
7231 13:59:59.795791 Exit from Gating configuration <<<<
7232 13:59:59.798736 Enter into DVFS_PRE_config >>>>>
7233 13:59:59.811958 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7234 13:59:59.815261 Exit from DVFS_PRE_config <<<<<
7235 13:59:59.815831 Enter into PICG configuration >>>>
7236 13:59:59.818850 Exit from PICG configuration <<<<
7237 13:59:59.822175 [RX_INPUT] configuration >>>>>
7238 13:59:59.825746 [RX_INPUT] configuration <<<<<
7239 13:59:59.831992 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7240 13:59:59.835327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7241 13:59:59.841752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 13:59:59.848801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 13:59:59.855281 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 13:59:59.861849 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 13:59:59.865101 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7246 13:59:59.868533 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7247 13:59:59.872137 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7248 13:59:59.878494 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7249 13:59:59.881876 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7250 13:59:59.885077 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 13:59:59.888904 ===================================
7252 13:59:59.891938 LPDDR4 DRAM CONFIGURATION
7253 13:59:59.895043 ===================================
7254 13:59:59.898660 EX_ROW_EN[0] = 0x0
7255 13:59:59.899188 EX_ROW_EN[1] = 0x0
7256 13:59:59.901927 LP4Y_EN = 0x0
7257 13:59:59.902389 WORK_FSP = 0x1
7258 13:59:59.904887 WL = 0x5
7259 13:59:59.905329 RL = 0x5
7260 13:59:59.908468 BL = 0x2
7261 13:59:59.909005 RPST = 0x0
7262 13:59:59.911766 RD_PRE = 0x0
7263 13:59:59.912208 WR_PRE = 0x1
7264 13:59:59.915050 WR_PST = 0x1
7265 13:59:59.915495 DBI_WR = 0x0
7266 13:59:59.918460 DBI_RD = 0x0
7267 13:59:59.918975 OTF = 0x1
7268 13:59:59.921612 ===================================
7269 13:59:59.924761 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7270 13:59:59.931403 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7271 13:59:59.934801 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 13:59:59.938303 ===================================
7273 13:59:59.941629 LPDDR4 DRAM CONFIGURATION
7274 13:59:59.944655 ===================================
7275 13:59:59.945092 EX_ROW_EN[0] = 0x10
7276 13:59:59.947946 EX_ROW_EN[1] = 0x0
7277 13:59:59.951516 LP4Y_EN = 0x0
7278 13:59:59.951990 WORK_FSP = 0x1
7279 13:59:59.954819 WL = 0x5
7280 13:59:59.955380 RL = 0x5
7281 13:59:59.958363 BL = 0x2
7282 13:59:59.958821 RPST = 0x0
7283 13:59:59.961218 RD_PRE = 0x0
7284 13:59:59.961641 WR_PRE = 0x1
7285 13:59:59.964736 WR_PST = 0x1
7286 13:59:59.965262 DBI_WR = 0x0
7287 13:59:59.967961 DBI_RD = 0x0
7288 13:59:59.968400 OTF = 0x1
7289 13:59:59.971376 ===================================
7290 13:59:59.977922 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7291 13:59:59.978380 ==
7292 13:59:59.981375 Dram Type= 6, Freq= 0, CH_0, rank 0
7293 13:59:59.984710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 13:59:59.985150 ==
7295 13:59:59.988197 [Duty_Offset_Calibration]
7296 13:59:59.991607 B0:2 B1:0 CA:1
7297 13:59:59.992135
7298 13:59:59.994645 [DutyScan_Calibration_Flow] k_type=0
7299 14:00:00.002840
7300 14:00:00.003371 ==CLK 0==
7301 14:00:00.005696 Final CLK duty delay cell = -4
7302 14:00:00.008907 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7303 14:00:00.012611 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7304 14:00:00.015928 [-4] AVG Duty = 4937%(X100)
7305 14:00:00.016364
7306 14:00:00.019637 CH0 CLK Duty spec in!! Max-Min= 187%
7307 14:00:00.022309 [DutyScan_Calibration_Flow] ====Done====
7308 14:00:00.022748
7309 14:00:00.025466 [DutyScan_Calibration_Flow] k_type=1
7310 14:00:00.042234
7311 14:00:00.042807 ==DQS 0 ==
7312 14:00:00.045416 Final DQS duty delay cell = 0
7313 14:00:00.048616 [0] MAX Duty = 5249%(X100), DQS PI = 32
7314 14:00:00.052106 [0] MIN Duty = 4938%(X100), DQS PI = 62
7315 14:00:00.055638 [0] AVG Duty = 5093%(X100)
7316 14:00:00.056074
7317 14:00:00.056512 ==DQS 1 ==
7318 14:00:00.058841 Final DQS duty delay cell = -4
7319 14:00:00.061809 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7320 14:00:00.065653 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7321 14:00:00.068480 [-4] AVG Duty = 4984%(X100)
7322 14:00:00.068907
7323 14:00:00.072057 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7324 14:00:00.072482
7325 14:00:00.075308 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7326 14:00:00.079150 [DutyScan_Calibration_Flow] ====Done====
7327 14:00:00.079593
7328 14:00:00.082221 [DutyScan_Calibration_Flow] k_type=3
7329 14:00:00.099582
7330 14:00:00.100153 ==DQM 0 ==
7331 14:00:00.102796 Final DQM duty delay cell = 0
7332 14:00:00.106296 [0] MAX Duty = 5093%(X100), DQS PI = 26
7333 14:00:00.109771 [0] MIN Duty = 4813%(X100), DQS PI = 50
7334 14:00:00.112647 [0] AVG Duty = 4953%(X100)
7335 14:00:00.113131
7336 14:00:00.113609 ==DQM 1 ==
7337 14:00:00.116191 Final DQM duty delay cell = 0
7338 14:00:00.119452 [0] MAX Duty = 5249%(X100), DQS PI = 30
7339 14:00:00.122779 [0] MIN Duty = 5000%(X100), DQS PI = 20
7340 14:00:00.125772 [0] AVG Duty = 5124%(X100)
7341 14:00:00.126291
7342 14:00:00.129489 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7343 14:00:00.129999
7344 14:00:00.132653 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7345 14:00:00.136060 [DutyScan_Calibration_Flow] ====Done====
7346 14:00:00.136542
7347 14:00:00.139287 [DutyScan_Calibration_Flow] k_type=2
7348 14:00:00.157488
7349 14:00:00.158131 ==DQ 0 ==
7350 14:00:00.161071 Final DQ duty delay cell = 0
7351 14:00:00.164512 [0] MAX Duty = 5156%(X100), DQS PI = 38
7352 14:00:00.167696 [0] MIN Duty = 5000%(X100), DQS PI = 0
7353 14:00:00.168281 [0] AVG Duty = 5078%(X100)
7354 14:00:00.168766
7355 14:00:00.171137 ==DQ 1 ==
7356 14:00:00.171619 Final DQ duty delay cell = 4
7357 14:00:00.177590 [4] MAX Duty = 5125%(X100), DQS PI = 2
7358 14:00:00.181592 [4] MIN Duty = 5062%(X100), DQS PI = 0
7359 14:00:00.182196 [4] AVG Duty = 5093%(X100)
7360 14:00:00.182775
7361 14:00:00.184462 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7362 14:00:00.185041
7363 14:00:00.187564 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7364 14:00:00.190966 [DutyScan_Calibration_Flow] ====Done====
7365 14:00:00.194182 ==
7366 14:00:00.197504 Dram Type= 6, Freq= 0, CH_1, rank 0
7367 14:00:00.200991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7368 14:00:00.201484 ==
7369 14:00:00.204445 [Duty_Offset_Calibration]
7370 14:00:00.204789 B0:0 B1:-1 CA:2
7371 14:00:00.205100
7372 14:00:00.207180 [DutyScan_Calibration_Flow] k_type=0
7373 14:00:00.217315
7374 14:00:00.217634 ==CLK 0==
7375 14:00:00.220534 Final CLK duty delay cell = 0
7376 14:00:00.223996 [0] MAX Duty = 5156%(X100), DQS PI = 10
7377 14:00:00.227306 [0] MIN Duty = 4906%(X100), DQS PI = 46
7378 14:00:00.227620 [0] AVG Duty = 5031%(X100)
7379 14:00:00.230780
7380 14:00:00.233866 CH1 CLK Duty spec in!! Max-Min= 250%
7381 14:00:00.237317 [DutyScan_Calibration_Flow] ====Done====
7382 14:00:00.237614
7383 14:00:00.240494 [DutyScan_Calibration_Flow] k_type=1
7384 14:00:00.257624
7385 14:00:00.258200 ==DQS 0 ==
7386 14:00:00.260617 Final DQS duty delay cell = 0
7387 14:00:00.263887 [0] MAX Duty = 5093%(X100), DQS PI = 26
7388 14:00:00.267233 [0] MIN Duty = 4969%(X100), DQS PI = 2
7389 14:00:00.270768 [0] AVG Duty = 5031%(X100)
7390 14:00:00.271227
7391 14:00:00.271586 ==DQS 1 ==
7392 14:00:00.273775 Final DQS duty delay cell = 0
7393 14:00:00.277282 [0] MAX Duty = 5187%(X100), DQS PI = 62
7394 14:00:00.280638 [0] MIN Duty = 4844%(X100), DQS PI = 32
7395 14:00:00.283506 [0] AVG Duty = 5015%(X100)
7396 14:00:00.283914
7397 14:00:00.287100 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7398 14:00:00.287560
7399 14:00:00.290649 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7400 14:00:00.293461 [DutyScan_Calibration_Flow] ====Done====
7401 14:00:00.293978
7402 14:00:00.297264 [DutyScan_Calibration_Flow] k_type=3
7403 14:00:00.315163
7404 14:00:00.315707 ==DQM 0 ==
7405 14:00:00.318091 Final DQM duty delay cell = 4
7406 14:00:00.321631 [4] MAX Duty = 5125%(X100), DQS PI = 8
7407 14:00:00.325199 [4] MIN Duty = 4969%(X100), DQS PI = 44
7408 14:00:00.325659 [4] AVG Duty = 5047%(X100)
7409 14:00:00.328485
7410 14:00:00.329036 ==DQM 1 ==
7411 14:00:00.331559 Final DQM duty delay cell = 0
7412 14:00:00.334626 [0] MAX Duty = 5249%(X100), DQS PI = 60
7413 14:00:00.338528 [0] MIN Duty = 4876%(X100), DQS PI = 34
7414 14:00:00.341880 [0] AVG Duty = 5062%(X100)
7415 14:00:00.342466
7416 14:00:00.345123 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7417 14:00:00.345582
7418 14:00:00.348476 CH1 DQM 1 Duty spec in!! Max-Min= 373%
7419 14:00:00.351602 [DutyScan_Calibration_Flow] ====Done====
7420 14:00:00.352060
7421 14:00:00.354746 [DutyScan_Calibration_Flow] k_type=2
7422 14:00:00.372117
7423 14:00:00.372634 ==DQ 0 ==
7424 14:00:00.375026 Final DQ duty delay cell = 0
7425 14:00:00.378498 [0] MAX Duty = 5093%(X100), DQS PI = 24
7426 14:00:00.381829 [0] MIN Duty = 4969%(X100), DQS PI = 46
7427 14:00:00.382391 [0] AVG Duty = 5031%(X100)
7428 14:00:00.382835
7429 14:00:00.384978 ==DQ 1 ==
7430 14:00:00.388879 Final DQ duty delay cell = 0
7431 14:00:00.391730 [0] MAX Duty = 5062%(X100), DQS PI = 2
7432 14:00:00.394952 [0] MIN Duty = 4813%(X100), DQS PI = 34
7433 14:00:00.395389 [0] AVG Duty = 4937%(X100)
7434 14:00:00.395821
7435 14:00:00.398388 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7436 14:00:00.401816
7437 14:00:00.402292 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7438 14:00:00.408427 [DutyScan_Calibration_Flow] ====Done====
7439 14:00:00.411726 nWR fixed to 30
7440 14:00:00.412193 [ModeRegInit_LP4] CH0 RK0
7441 14:00:00.415174 [ModeRegInit_LP4] CH0 RK1
7442 14:00:00.418115 [ModeRegInit_LP4] CH1 RK0
7443 14:00:00.418536 [ModeRegInit_LP4] CH1 RK1
7444 14:00:00.421815 match AC timing 5
7445 14:00:00.425050 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7446 14:00:00.428753 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7447 14:00:00.435207 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7448 14:00:00.438038 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7449 14:00:00.445064 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7450 14:00:00.445582 [MiockJmeterHQA]
7451 14:00:00.445920
7452 14:00:00.448274 [DramcMiockJmeter] u1RxGatingPI = 0
7453 14:00:00.452088 0 : 4253, 4026
7454 14:00:00.452652 4 : 4252, 4027
7455 14:00:00.453072 8 : 4259, 4031
7456 14:00:00.454642 12 : 4257, 4029
7457 14:00:00.455122 16 : 4257, 4029
7458 14:00:00.458338 20 : 4253, 4027
7459 14:00:00.458775 24 : 4253, 4027
7460 14:00:00.461266 28 : 4365, 4140
7461 14:00:00.461703 32 : 4252, 4027
7462 14:00:00.464520 36 : 4254, 4029
7463 14:00:00.464953 40 : 4252, 4027
7464 14:00:00.465299 44 : 4360, 4138
7465 14:00:00.468004 48 : 4252, 4027
7466 14:00:00.468544 52 : 4360, 4137
7467 14:00:00.471561 56 : 4250, 4027
7468 14:00:00.472154 60 : 4250, 4026
7469 14:00:00.474593 64 : 4250, 4027
7470 14:00:00.475074 68 : 4253, 4029
7471 14:00:00.477854 72 : 4360, 4137
7472 14:00:00.478369 76 : 4250, 4027
7473 14:00:00.478751 80 : 4361, 4138
7474 14:00:00.481638 84 : 4252, 4027
7475 14:00:00.482283 88 : 4250, 3430
7476 14:00:00.484686 92 : 4250, 0
7477 14:00:00.485165 96 : 4363, 0
7478 14:00:00.485546 100 : 4252, 0
7479 14:00:00.488022 104 : 4250, 0
7480 14:00:00.488504 108 : 4250, 0
7481 14:00:00.491571 112 : 4250, 0
7482 14:00:00.492182 116 : 4250, 0
7483 14:00:00.492575 120 : 4250, 0
7484 14:00:00.494649 124 : 4250, 0
7485 14:00:00.495127 128 : 4252, 0
7486 14:00:00.497740 132 : 4361, 0
7487 14:00:00.498274 136 : 4250, 0
7488 14:00:00.498659 140 : 4360, 0
7489 14:00:00.501257 144 : 4250, 0
7490 14:00:00.501690 148 : 4250, 0
7491 14:00:00.504539 152 : 4253, 0
7492 14:00:00.504974 156 : 4250, 0
7493 14:00:00.505321 160 : 4250, 0
7494 14:00:00.507613 164 : 4250, 0
7495 14:00:00.508180 168 : 4252, 0
7496 14:00:00.508540 172 : 4250, 0
7497 14:00:00.510805 176 : 4361, 0
7498 14:00:00.511240 180 : 4250, 0
7499 14:00:00.514558 184 : 4361, 0
7500 14:00:00.515005 188 : 4250, 0
7501 14:00:00.515353 192 : 4360, 0
7502 14:00:00.517574 196 : 4252, 0
7503 14:00:00.518053 200 : 4250, 4
7504 14:00:00.521008 204 : 4252, 2249
7505 14:00:00.521440 208 : 4252, 4029
7506 14:00:00.524206 212 : 4363, 4140
7507 14:00:00.524639 216 : 4360, 4137
7508 14:00:00.527934 220 : 4250, 4027
7509 14:00:00.528480 224 : 4363, 4140
7510 14:00:00.528831 228 : 4360, 4138
7511 14:00:00.530724 232 : 4250, 4027
7512 14:00:00.531158 236 : 4250, 4027
7513 14:00:00.533922 240 : 4252, 4029
7514 14:00:00.534394 244 : 4250, 4027
7515 14:00:00.537705 248 : 4250, 4027
7516 14:00:00.538313 252 : 4250, 4027
7517 14:00:00.540806 256 : 4252, 4029
7518 14:00:00.541349 260 : 4250, 4026
7519 14:00:00.544471 264 : 4361, 4137
7520 14:00:00.545013 268 : 4360, 4137
7521 14:00:00.547581 272 : 4250, 4027
7522 14:00:00.548015 276 : 4364, 4140
7523 14:00:00.550576 280 : 4360, 4137
7524 14:00:00.551119 284 : 4250, 4027
7525 14:00:00.554154 288 : 4250, 4027
7526 14:00:00.554749 292 : 4252, 4029
7527 14:00:00.555105 296 : 4250, 4027
7528 14:00:00.557815 300 : 4250, 4027
7529 14:00:00.558404 304 : 4250, 4027
7530 14:00:00.560637 308 : 4252, 4029
7531 14:00:00.561076 312 : 4250, 3779
7532 14:00:00.564065 316 : 4361, 2325
7533 14:00:00.564609 320 : 4360, 18
7534 14:00:00.564961
7535 14:00:00.567591 MIOCK jitter meter ch=0
7536 14:00:00.568133
7537 14:00:00.570832 1T = (320-92) = 228 dly cells
7538 14:00:00.574280 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7539 14:00:00.577556 ==
7540 14:00:00.580866 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 14:00:00.583803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 14:00:00.584239 ==
7543 14:00:00.590638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7544 14:00:00.593987 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7545 14:00:00.597105 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7546 14:00:00.603741 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7547 14:00:00.612178 [CA 0] Center 43 (13~73) winsize 61
7548 14:00:00.615486 [CA 1] Center 43 (13~73) winsize 61
7549 14:00:00.618664 [CA 2] Center 38 (8~68) winsize 61
7550 14:00:00.622107 [CA 3] Center 37 (8~67) winsize 60
7551 14:00:00.625275 [CA 4] Center 36 (6~66) winsize 61
7552 14:00:00.628979 [CA 5] Center 35 (5~65) winsize 61
7553 14:00:00.629559
7554 14:00:00.632200 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7555 14:00:00.632786
7556 14:00:00.635187 [CATrainingPosCal] consider 1 rank data
7557 14:00:00.638474 u2DelayCellTimex100 = 285/100 ps
7558 14:00:00.642043 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7559 14:00:00.648929 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7560 14:00:00.652060 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7561 14:00:00.655124 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7562 14:00:00.658370 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7563 14:00:00.662019 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7564 14:00:00.662549
7565 14:00:00.665016 CA PerBit enable=1, Macro0, CA PI delay=35
7566 14:00:00.665791
7567 14:00:00.668230 [CBTSetCACLKResult] CA Dly = 35
7568 14:00:00.671464 CS Dly: 9 (0~40)
7569 14:00:00.675065 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7570 14:00:00.678354 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7571 14:00:00.679031 ==
7572 14:00:00.681824 Dram Type= 6, Freq= 0, CH_0, rank 1
7573 14:00:00.684962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 14:00:00.688102 ==
7575 14:00:00.692063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7576 14:00:00.695151 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7577 14:00:00.701572 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7578 14:00:00.705154 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7579 14:00:00.715630 [CA 0] Center 43 (13~74) winsize 62
7580 14:00:00.718903 [CA 1] Center 43 (13~73) winsize 61
7581 14:00:00.722237 [CA 2] Center 38 (9~68) winsize 60
7582 14:00:00.725508 [CA 3] Center 38 (9~68) winsize 60
7583 14:00:00.728647 [CA 4] Center 37 (7~67) winsize 61
7584 14:00:00.732055 [CA 5] Center 36 (6~66) winsize 61
7585 14:00:00.732633
7586 14:00:00.735189 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7587 14:00:00.735660
7588 14:00:00.738761 [CATrainingPosCal] consider 2 rank data
7589 14:00:00.742446 u2DelayCellTimex100 = 285/100 ps
7590 14:00:00.745464 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7591 14:00:00.751814 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7592 14:00:00.755142 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7593 14:00:00.758755 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7594 14:00:00.762292 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7595 14:00:00.765418 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7596 14:00:00.766036
7597 14:00:00.768792 CA PerBit enable=1, Macro0, CA PI delay=35
7598 14:00:00.769375
7599 14:00:00.772358 [CBTSetCACLKResult] CA Dly = 35
7600 14:00:00.775475 CS Dly: 10 (0~43)
7601 14:00:00.778687 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7602 14:00:00.782040 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7603 14:00:00.782614
7604 14:00:00.785318 ----->DramcWriteLeveling(PI) begin...
7605 14:00:00.785900 ==
7606 14:00:00.788623 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 14:00:00.795465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 14:00:00.796048 ==
7609 14:00:00.798211 Write leveling (Byte 0): 37 => 37
7610 14:00:00.798782 Write leveling (Byte 1): 32 => 32
7611 14:00:00.801432 DramcWriteLeveling(PI) end<-----
7612 14:00:00.801904
7613 14:00:00.805107 ==
7614 14:00:00.805685 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 14:00:00.811944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 14:00:00.812538 ==
7617 14:00:00.814940 [Gating] SW mode calibration
7618 14:00:00.821816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7619 14:00:00.824962 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7620 14:00:00.831341 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 14:00:00.834544 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 14:00:00.837853 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
7623 14:00:00.844638 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7624 14:00:00.847842 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7625 14:00:00.851345 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7626 14:00:00.857909 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 14:00:00.861220 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 14:00:00.864457 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 14:00:00.871041 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 14:00:00.874405 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7631 14:00:00.877981 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7632 14:00:00.884336 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7633 14:00:00.887961 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
7634 14:00:00.891182 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 14:00:00.897656 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 14:00:00.900948 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 14:00:00.904463 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7638 14:00:00.910832 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
7639 14:00:00.914067 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7640 14:00:00.917213 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7641 14:00:00.924224 1 6 20 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
7642 14:00:00.927796 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 14:00:00.930289 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 14:00:00.937234 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 14:00:00.940401 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 14:00:00.943731 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7647 14:00:00.950331 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7648 14:00:00.953686 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7649 14:00:00.957049 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7650 14:00:00.963252 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 14:00:00.966728 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 14:00:00.970418 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 14:00:00.976672 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 14:00:00.980141 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 14:00:00.983585 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 14:00:00.990068 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 14:00:00.993286 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 14:00:00.996522 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 14:00:01.002996 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 14:00:01.006466 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 14:00:01.009786 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 14:00:01.016286 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 14:00:01.019704 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7664 14:00:01.022808 Total UI for P1: 0, mck2ui 16
7665 14:00:01.026525 best dqsien dly found for B0: ( 1, 9, 8)
7666 14:00:01.029422 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7667 14:00:01.036265 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7668 14:00:01.039690 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 14:00:01.042699 Total UI for P1: 0, mck2ui 16
7670 14:00:01.046192 best dqsien dly found for B1: ( 1, 9, 20)
7671 14:00:01.049193 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7672 14:00:01.052839 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7673 14:00:01.053457
7674 14:00:01.055839 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7675 14:00:01.059353 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7676 14:00:01.062713 [Gating] SW calibration Done
7677 14:00:01.063282 ==
7678 14:00:01.065699 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 14:00:01.069092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 14:00:01.069562 ==
7681 14:00:01.072304 RX Vref Scan: 0
7682 14:00:01.072771
7683 14:00:01.075598 RX Vref 0 -> 0, step: 1
7684 14:00:01.076062
7685 14:00:01.076433 RX Delay 0 -> 252, step: 8
7686 14:00:01.082450 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7687 14:00:01.085806 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7688 14:00:01.089334 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7689 14:00:01.092942 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7690 14:00:01.096198 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7691 14:00:01.102428 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7692 14:00:01.105589 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7693 14:00:01.108828 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7694 14:00:01.112210 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7695 14:00:01.115779 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7696 14:00:01.122468 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7697 14:00:01.125925 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7698 14:00:01.129038 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7699 14:00:01.132731 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7700 14:00:01.135810 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7701 14:00:01.142531 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7702 14:00:01.143100 ==
7703 14:00:01.145733 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 14:00:01.149282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 14:00:01.149857 ==
7706 14:00:01.150296 DQS Delay:
7707 14:00:01.152135 DQS0 = 0, DQS1 = 0
7708 14:00:01.152606 DQM Delay:
7709 14:00:01.155757 DQM0 = 137, DQM1 = 126
7710 14:00:01.156228 DQ Delay:
7711 14:00:01.159202 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7712 14:00:01.162341 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7713 14:00:01.165625 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7714 14:00:01.168902 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7715 14:00:01.169373
7716 14:00:01.169767
7717 14:00:01.172275 ==
7718 14:00:01.172812 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 14:00:01.178472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 14:00:01.179089 ==
7721 14:00:01.179473
7722 14:00:01.179823
7723 14:00:01.182128 TX Vref Scan disable
7724 14:00:01.182602 == TX Byte 0 ==
7725 14:00:01.185103 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7726 14:00:01.192266 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7727 14:00:01.192852 == TX Byte 1 ==
7728 14:00:01.195409 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7729 14:00:01.202298 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7730 14:00:01.202870 ==
7731 14:00:01.205176 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 14:00:01.208648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 14:00:01.209125 ==
7734 14:00:01.222147
7735 14:00:01.225375 TX Vref early break, caculate TX vref
7736 14:00:01.228513 TX Vref=16, minBit 8, minWin=22, winSum=379
7737 14:00:01.231819 TX Vref=18, minBit 6, minWin=23, winSum=384
7738 14:00:01.235297 TX Vref=20, minBit 0, minWin=24, winSum=396
7739 14:00:01.238758 TX Vref=22, minBit 7, minWin=24, winSum=406
7740 14:00:01.242029 TX Vref=24, minBit 2, minWin=25, winSum=414
7741 14:00:01.248653 TX Vref=26, minBit 7, minWin=25, winSum=425
7742 14:00:01.251917 TX Vref=28, minBit 0, minWin=26, winSum=429
7743 14:00:01.255291 TX Vref=30, minBit 0, minWin=25, winSum=421
7744 14:00:01.258488 TX Vref=32, minBit 0, minWin=25, winSum=410
7745 14:00:01.262083 TX Vref=34, minBit 2, minWin=24, winSum=400
7746 14:00:01.268622 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
7747 14:00:01.269191
7748 14:00:01.271857 Final TX Range 0 Vref 28
7749 14:00:01.272326
7750 14:00:01.272691 ==
7751 14:00:01.275416 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 14:00:01.278491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 14:00:01.279194 ==
7754 14:00:01.279602
7755 14:00:01.279956
7756 14:00:01.281752 TX Vref Scan disable
7757 14:00:01.288120 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7758 14:00:01.288593 == TX Byte 0 ==
7759 14:00:01.291463 u2DelayCellOfst[0]=17 cells (5 PI)
7760 14:00:01.294872 u2DelayCellOfst[1]=20 cells (6 PI)
7761 14:00:01.298310 u2DelayCellOfst[2]=13 cells (4 PI)
7762 14:00:01.301388 u2DelayCellOfst[3]=13 cells (4 PI)
7763 14:00:01.305291 u2DelayCellOfst[4]=10 cells (3 PI)
7764 14:00:01.308669 u2DelayCellOfst[5]=0 cells (0 PI)
7765 14:00:01.311632 u2DelayCellOfst[6]=20 cells (6 PI)
7766 14:00:01.314861 u2DelayCellOfst[7]=17 cells (5 PI)
7767 14:00:01.318061 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7768 14:00:01.321394 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7769 14:00:01.324872 == TX Byte 1 ==
7770 14:00:01.325453 u2DelayCellOfst[8]=0 cells (0 PI)
7771 14:00:01.328233 u2DelayCellOfst[9]=0 cells (0 PI)
7772 14:00:01.331330 u2DelayCellOfst[10]=6 cells (2 PI)
7773 14:00:01.334775 u2DelayCellOfst[11]=0 cells (0 PI)
7774 14:00:01.338314 u2DelayCellOfst[12]=10 cells (3 PI)
7775 14:00:01.341408 u2DelayCellOfst[13]=10 cells (3 PI)
7776 14:00:01.345111 u2DelayCellOfst[14]=13 cells (4 PI)
7777 14:00:01.348201 u2DelayCellOfst[15]=10 cells (3 PI)
7778 14:00:01.351440 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7779 14:00:01.358366 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7780 14:00:01.358933 DramC Write-DBI on
7781 14:00:01.359308 ==
7782 14:00:01.361584 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 14:00:01.365150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 14:00:01.368049 ==
7785 14:00:01.368520
7786 14:00:01.368889
7787 14:00:01.369230 TX Vref Scan disable
7788 14:00:01.371521 == TX Byte 0 ==
7789 14:00:01.374870 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7790 14:00:01.378313 == TX Byte 1 ==
7791 14:00:01.381446 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7792 14:00:01.384629 DramC Write-DBI off
7793 14:00:01.385195
7794 14:00:01.385567 [DATLAT]
7795 14:00:01.385911 Freq=1600, CH0 RK0
7796 14:00:01.386306
7797 14:00:01.388128 DATLAT Default: 0xf
7798 14:00:01.388702 0, 0xFFFF, sum = 0
7799 14:00:01.391306 1, 0xFFFF, sum = 0
7800 14:00:01.394548 2, 0xFFFF, sum = 0
7801 14:00:01.395127 3, 0xFFFF, sum = 0
7802 14:00:01.398255 4, 0xFFFF, sum = 0
7803 14:00:01.398832 5, 0xFFFF, sum = 0
7804 14:00:01.401468 6, 0xFFFF, sum = 0
7805 14:00:01.402074 7, 0xFFFF, sum = 0
7806 14:00:01.404415 8, 0xFFFF, sum = 0
7807 14:00:01.404891 9, 0xFFFF, sum = 0
7808 14:00:01.407671 10, 0xFFFF, sum = 0
7809 14:00:01.408148 11, 0xFFFF, sum = 0
7810 14:00:01.410948 12, 0xFFFF, sum = 0
7811 14:00:01.411422 13, 0xFFFF, sum = 0
7812 14:00:01.414797 14, 0x0, sum = 1
7813 14:00:01.415377 15, 0x0, sum = 2
7814 14:00:01.418003 16, 0x0, sum = 3
7815 14:00:01.418481 17, 0x0, sum = 4
7816 14:00:01.421481 best_step = 15
7817 14:00:01.422100
7818 14:00:01.422486 ==
7819 14:00:01.424789 Dram Type= 6, Freq= 0, CH_0, rank 0
7820 14:00:01.427686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7821 14:00:01.428158 ==
7822 14:00:01.431095 RX Vref Scan: 1
7823 14:00:01.431661
7824 14:00:01.432032 Set Vref Range= 24 -> 127
7825 14:00:01.432379
7826 14:00:01.434080 RX Vref 24 -> 127, step: 1
7827 14:00:01.434550
7828 14:00:01.437582 RX Delay 19 -> 252, step: 4
7829 14:00:01.438072
7830 14:00:01.441312 Set Vref, RX VrefLevel [Byte0]: 24
7831 14:00:01.444494 [Byte1]: 24
7832 14:00:01.445066
7833 14:00:01.447940 Set Vref, RX VrefLevel [Byte0]: 25
7834 14:00:01.451297 [Byte1]: 25
7835 14:00:01.451866
7836 14:00:01.454314 Set Vref, RX VrefLevel [Byte0]: 26
7837 14:00:01.457478 [Byte1]: 26
7838 14:00:01.461771
7839 14:00:01.462365 Set Vref, RX VrefLevel [Byte0]: 27
7840 14:00:01.465063 [Byte1]: 27
7841 14:00:01.469356
7842 14:00:01.469919 Set Vref, RX VrefLevel [Byte0]: 28
7843 14:00:01.472391 [Byte1]: 28
7844 14:00:01.476828
7845 14:00:01.477405 Set Vref, RX VrefLevel [Byte0]: 29
7846 14:00:01.480607 [Byte1]: 29
7847 14:00:01.484497
7848 14:00:01.485060 Set Vref, RX VrefLevel [Byte0]: 30
7849 14:00:01.487446 [Byte1]: 30
7850 14:00:01.491835
7851 14:00:01.495577 Set Vref, RX VrefLevel [Byte0]: 31
7852 14:00:01.498442 [Byte1]: 31
7853 14:00:01.498917
7854 14:00:01.501873 Set Vref, RX VrefLevel [Byte0]: 32
7855 14:00:01.504876 [Byte1]: 32
7856 14:00:01.505351
7857 14:00:01.508397 Set Vref, RX VrefLevel [Byte0]: 33
7858 14:00:01.511513 [Byte1]: 33
7859 14:00:01.511981
7860 14:00:01.514668 Set Vref, RX VrefLevel [Byte0]: 34
7861 14:00:01.518392 [Byte1]: 34
7862 14:00:01.521982
7863 14:00:01.522457 Set Vref, RX VrefLevel [Byte0]: 35
7864 14:00:01.525995 [Byte1]: 35
7865 14:00:01.530374
7866 14:00:01.530939 Set Vref, RX VrefLevel [Byte0]: 36
7867 14:00:01.533248 [Byte1]: 36
7868 14:00:01.537267
7869 14:00:01.537736 Set Vref, RX VrefLevel [Byte0]: 37
7870 14:00:01.540406 [Byte1]: 37
7871 14:00:01.545120
7872 14:00:01.545683 Set Vref, RX VrefLevel [Byte0]: 38
7873 14:00:01.548321 [Byte1]: 38
7874 14:00:01.552618
7875 14:00:01.553184 Set Vref, RX VrefLevel [Byte0]: 39
7876 14:00:01.555667 [Byte1]: 39
7877 14:00:01.560403
7878 14:00:01.560969 Set Vref, RX VrefLevel [Byte0]: 40
7879 14:00:01.563485 [Byte1]: 40
7880 14:00:01.567544
7881 14:00:01.568107 Set Vref, RX VrefLevel [Byte0]: 41
7882 14:00:01.570843 [Byte1]: 41
7883 14:00:01.575381
7884 14:00:01.575948 Set Vref, RX VrefLevel [Byte0]: 42
7885 14:00:01.578609 [Byte1]: 42
7886 14:00:01.582902
7887 14:00:01.583465 Set Vref, RX VrefLevel [Byte0]: 43
7888 14:00:01.586206 [Byte1]: 43
7889 14:00:01.590791
7890 14:00:01.591354 Set Vref, RX VrefLevel [Byte0]: 44
7891 14:00:01.593893 [Byte1]: 44
7892 14:00:01.597936
7893 14:00:01.598547 Set Vref, RX VrefLevel [Byte0]: 45
7894 14:00:01.601401 [Byte1]: 45
7895 14:00:01.605520
7896 14:00:01.606162 Set Vref, RX VrefLevel [Byte0]: 46
7897 14:00:01.608556 [Byte1]: 46
7898 14:00:01.612828
7899 14:00:01.613416 Set Vref, RX VrefLevel [Byte0]: 47
7900 14:00:01.616040 [Byte1]: 47
7901 14:00:01.620656
7902 14:00:01.621121 Set Vref, RX VrefLevel [Byte0]: 48
7903 14:00:01.624106 [Byte1]: 48
7904 14:00:01.628145
7905 14:00:01.628707 Set Vref, RX VrefLevel [Byte0]: 49
7906 14:00:01.632058 [Byte1]: 49
7907 14:00:01.636151
7908 14:00:01.636727 Set Vref, RX VrefLevel [Byte0]: 50
7909 14:00:01.639214 [Byte1]: 50
7910 14:00:01.643565
7911 14:00:01.644138 Set Vref, RX VrefLevel [Byte0]: 51
7912 14:00:01.646832 [Byte1]: 51
7913 14:00:01.651043
7914 14:00:01.651607 Set Vref, RX VrefLevel [Byte0]: 52
7915 14:00:01.654308 [Byte1]: 52
7916 14:00:01.658710
7917 14:00:01.659281 Set Vref, RX VrefLevel [Byte0]: 53
7918 14:00:01.661760 [Byte1]: 53
7919 14:00:01.666342
7920 14:00:01.666906 Set Vref, RX VrefLevel [Byte0]: 54
7921 14:00:01.669327 [Byte1]: 54
7922 14:00:01.673907
7923 14:00:01.674511 Set Vref, RX VrefLevel [Byte0]: 55
7924 14:00:01.677034 [Byte1]: 55
7925 14:00:01.681459
7926 14:00:01.682063 Set Vref, RX VrefLevel [Byte0]: 56
7927 14:00:01.684479 [Byte1]: 56
7928 14:00:01.688980
7929 14:00:01.689564 Set Vref, RX VrefLevel [Byte0]: 57
7930 14:00:01.692165 [Byte1]: 57
7931 14:00:01.696178
7932 14:00:01.696744 Set Vref, RX VrefLevel [Byte0]: 58
7933 14:00:01.699396 [Byte1]: 58
7934 14:00:01.703742
7935 14:00:01.704209 Set Vref, RX VrefLevel [Byte0]: 59
7936 14:00:01.707047 [Byte1]: 59
7937 14:00:01.711412
7938 14:00:01.712001 Set Vref, RX VrefLevel [Byte0]: 60
7939 14:00:01.714581 [Byte1]: 60
7940 14:00:01.718901
7941 14:00:01.719534 Set Vref, RX VrefLevel [Byte0]: 61
7942 14:00:01.722264 [Byte1]: 61
7943 14:00:01.726404
7944 14:00:01.726870 Set Vref, RX VrefLevel [Byte0]: 62
7945 14:00:01.729847 [Byte1]: 62
7946 14:00:01.734218
7947 14:00:01.734793 Set Vref, RX VrefLevel [Byte0]: 63
7948 14:00:01.737327 [Byte1]: 63
7949 14:00:01.741694
7950 14:00:01.742241 Set Vref, RX VrefLevel [Byte0]: 64
7951 14:00:01.745230 [Byte1]: 64
7952 14:00:01.749851
7953 14:00:01.750459 Set Vref, RX VrefLevel [Byte0]: 65
7954 14:00:01.752876 [Byte1]: 65
7955 14:00:01.756978
7956 14:00:01.757449 Set Vref, RX VrefLevel [Byte0]: 66
7957 14:00:01.760469 [Byte1]: 66
7958 14:00:01.764574
7959 14:00:01.765139 Set Vref, RX VrefLevel [Byte0]: 67
7960 14:00:01.767974 [Byte1]: 67
7961 14:00:01.772083
7962 14:00:01.772645 Set Vref, RX VrefLevel [Byte0]: 68
7963 14:00:01.775999 [Byte1]: 68
7964 14:00:01.779669
7965 14:00:01.780253 Set Vref, RX VrefLevel [Byte0]: 69
7966 14:00:01.782874 [Byte1]: 69
7967 14:00:01.787266
7968 14:00:01.787827 Set Vref, RX VrefLevel [Byte0]: 70
7969 14:00:01.790648 [Byte1]: 70
7970 14:00:01.795202
7971 14:00:01.795762 Set Vref, RX VrefLevel [Byte0]: 71
7972 14:00:01.798543 [Byte1]: 71
7973 14:00:01.802618
7974 14:00:01.803219 Set Vref, RX VrefLevel [Byte0]: 72
7975 14:00:01.805918 [Byte1]: 72
7976 14:00:01.810021
7977 14:00:01.810599 Set Vref, RX VrefLevel [Byte0]: 73
7978 14:00:01.813269 [Byte1]: 73
7979 14:00:01.817910
7980 14:00:01.818541 Set Vref, RX VrefLevel [Byte0]: 74
7981 14:00:01.820774 [Byte1]: 74
7982 14:00:01.825192
7983 14:00:01.825662 Set Vref, RX VrefLevel [Byte0]: 75
7984 14:00:01.828450 [Byte1]: 75
7985 14:00:01.832691
7986 14:00:01.833266 Set Vref, RX VrefLevel [Byte0]: 76
7987 14:00:01.835873 [Byte1]: 76
7988 14:00:01.840241
7989 14:00:01.840862 Set Vref, RX VrefLevel [Byte0]: 77
7990 14:00:01.843913 [Byte1]: 77
7991 14:00:01.847961
7992 14:00:01.848535 Set Vref, RX VrefLevel [Byte0]: 78
7993 14:00:01.851213 [Byte1]: 78
7994 14:00:01.855418
7995 14:00:01.855994 Set Vref, RX VrefLevel [Byte0]: 79
7996 14:00:01.858927 [Byte1]: 79
7997 14:00:01.862853
7998 14:00:01.863428 Set Vref, RX VrefLevel [Byte0]: 80
7999 14:00:01.866492 [Byte1]: 80
8000 14:00:01.870622
8001 14:00:01.871091 Set Vref, RX VrefLevel [Byte0]: 81
8002 14:00:01.874307 [Byte1]: 81
8003 14:00:01.878129
8004 14:00:01.878696 Final RX Vref Byte 0 = 62 to rank0
8005 14:00:01.881423 Final RX Vref Byte 1 = 63 to rank0
8006 14:00:01.885031 Final RX Vref Byte 0 = 62 to rank1
8007 14:00:01.888188 Final RX Vref Byte 1 = 63 to rank1==
8008 14:00:01.891434 Dram Type= 6, Freq= 0, CH_0, rank 0
8009 14:00:01.898158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 14:00:01.898742 ==
8011 14:00:01.899117 DQS Delay:
8012 14:00:01.899459 DQS0 = 0, DQS1 = 0
8013 14:00:01.901576 DQM Delay:
8014 14:00:01.902168 DQM0 = 135, DQM1 = 123
8015 14:00:01.904398 DQ Delay:
8016 14:00:01.907945 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
8017 14:00:01.911108 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
8018 14:00:01.914567 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8019 14:00:01.918235 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
8020 14:00:01.918840
8021 14:00:01.919217
8022 14:00:01.919564
8023 14:00:01.921140 [DramC_TX_OE_Calibration] TA2
8024 14:00:01.924802 Original DQ_B0 (3 6) =30, OEN = 27
8025 14:00:01.928032 Original DQ_B1 (3 6) =30, OEN = 27
8026 14:00:01.931087 24, 0x0, End_B0=24 End_B1=24
8027 14:00:01.931560 25, 0x0, End_B0=25 End_B1=25
8028 14:00:01.934271 26, 0x0, End_B0=26 End_B1=26
8029 14:00:01.937701 27, 0x0, End_B0=27 End_B1=27
8030 14:00:01.941092 28, 0x0, End_B0=28 End_B1=28
8031 14:00:01.944727 29, 0x0, End_B0=29 End_B1=29
8032 14:00:01.945299 30, 0x0, End_B0=30 End_B1=30
8033 14:00:01.947974 31, 0x4141, End_B0=30 End_B1=30
8034 14:00:01.951329 Byte0 end_step=30 best_step=27
8035 14:00:01.954492 Byte1 end_step=30 best_step=27
8036 14:00:01.957602 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 14:00:01.961288 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 14:00:01.961862
8039 14:00:01.962274
8040 14:00:01.968154 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8041 14:00:01.970733 CH0 RK0: MR19=303, MR18=1F1D
8042 14:00:01.978149 CH0_RK0: MR19=0x303, MR18=0x1F1D, DQSOSC=394, MR23=63, INC=23, DEC=15
8043 14:00:01.978718
8044 14:00:01.980888 ----->DramcWriteLeveling(PI) begin...
8045 14:00:01.981362 ==
8046 14:00:01.984415 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 14:00:01.987470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 14:00:01.987952 ==
8049 14:00:01.991039 Write leveling (Byte 0): 39 => 39
8050 14:00:01.994491 Write leveling (Byte 1): 27 => 27
8051 14:00:01.997887 DramcWriteLeveling(PI) end<-----
8052 14:00:01.998512
8053 14:00:01.998892 ==
8054 14:00:02.001117 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 14:00:02.004325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 14:00:02.004798 ==
8057 14:00:02.007499 [Gating] SW mode calibration
8058 14:00:02.014314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8059 14:00:02.021066 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8060 14:00:02.024444 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 14:00:02.028041 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 14:00:02.034454 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 14:00:02.037322 1 4 12 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (1 1)
8064 14:00:02.040721 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 14:00:02.047910 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 14:00:02.050912 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 14:00:02.054048 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 14:00:02.060593 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 14:00:02.064150 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 14:00:02.067681 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8071 14:00:02.074465 1 5 12 | B1->B0 | 3434 2828 | 0 0 | (1 0) (1 0)
8072 14:00:02.077384 1 5 16 | B1->B0 | 2929 2323 | 0 0 | (0 1) (1 0)
8073 14:00:02.080815 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 14:00:02.087294 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 14:00:02.091332 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 14:00:02.094112 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 14:00:02.100882 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 14:00:02.103857 1 6 8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
8079 14:00:02.107381 1 6 12 | B1->B0 | 3130 4646 | 1 0 | (1 1) (0 0)
8080 14:00:02.114397 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 14:00:02.117327 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 14:00:02.120534 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 14:00:02.127296 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 14:00:02.130832 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 14:00:02.133824 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 14:00:02.140244 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 14:00:02.143458 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8088 14:00:02.147201 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8089 14:00:02.153385 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 14:00:02.156998 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 14:00:02.160511 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 14:00:02.163587 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 14:00:02.170233 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 14:00:02.173881 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 14:00:02.177147 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 14:00:02.183697 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 14:00:02.187226 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 14:00:02.190597 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 14:00:02.197008 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 14:00:02.200384 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 14:00:02.203898 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 14:00:02.210404 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 14:00:02.214036 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8104 14:00:02.216817 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 14:00:02.220383 Total UI for P1: 0, mck2ui 16
8106 14:00:02.223217 best dqsien dly found for B0: ( 1, 9, 12)
8107 14:00:02.227033 Total UI for P1: 0, mck2ui 16
8108 14:00:02.230016 best dqsien dly found for B1: ( 1, 9, 12)
8109 14:00:02.233439 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8110 14:00:02.236868 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8111 14:00:02.237444
8112 14:00:02.243339 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8113 14:00:02.246985 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8114 14:00:02.249999 [Gating] SW calibration Done
8115 14:00:02.250471 ==
8116 14:00:02.253600 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 14:00:02.256678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 14:00:02.257154 ==
8119 14:00:02.257523 RX Vref Scan: 0
8120 14:00:02.257872
8121 14:00:02.260073 RX Vref 0 -> 0, step: 1
8122 14:00:02.260540
8123 14:00:02.263157 RX Delay 0 -> 252, step: 8
8124 14:00:02.266638 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8125 14:00:02.270431 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8126 14:00:02.273297 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8127 14:00:02.279789 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8128 14:00:02.283420 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8129 14:00:02.286492 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8130 14:00:02.290093 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8131 14:00:02.293163 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8132 14:00:02.299765 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8133 14:00:02.303035 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8134 14:00:02.306509 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8135 14:00:02.309925 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8136 14:00:02.313288 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8137 14:00:02.319719 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8138 14:00:02.323091 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8139 14:00:02.326308 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8140 14:00:02.326781 ==
8141 14:00:02.329740 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 14:00:02.333388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 14:00:02.341473 ==
8144 14:00:02.341613 DQS Delay:
8145 14:00:02.341752 DQS0 = 0, DQS1 = 0
8146 14:00:02.341862 DQM Delay:
8147 14:00:02.341986 DQM0 = 136, DQM1 = 125
8148 14:00:02.342527 DQ Delay:
8149 14:00:02.346097 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8150 14:00:02.349309 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8151 14:00:02.352828 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8152 14:00:02.355993 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8153 14:00:02.356483
8154 14:00:02.356852
8155 14:00:02.357198 ==
8156 14:00:02.360380 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 14:00:02.362797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 14:00:02.363270 ==
8159 14:00:02.363638
8160 14:00:02.366231
8161 14:00:02.366696 TX Vref Scan disable
8162 14:00:02.369375 == TX Byte 0 ==
8163 14:00:02.372638 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8164 14:00:02.376451 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8165 14:00:02.379679 == TX Byte 1 ==
8166 14:00:02.382790 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8167 14:00:02.386108 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8168 14:00:02.386679 ==
8169 14:00:02.389099 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 14:00:02.396145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 14:00:02.396735 ==
8172 14:00:02.410552
8173 14:00:02.414118 TX Vref early break, caculate TX vref
8174 14:00:02.417521 TX Vref=16, minBit 0, minWin=23, winSum=392
8175 14:00:02.420705 TX Vref=18, minBit 8, minWin=23, winSum=399
8176 14:00:02.424185 TX Vref=20, minBit 1, minWin=24, winSum=407
8177 14:00:02.427602 TX Vref=22, minBit 0, minWin=25, winSum=415
8178 14:00:02.430619 TX Vref=24, minBit 3, minWin=25, winSum=426
8179 14:00:02.437216 TX Vref=26, minBit 2, minWin=25, winSum=429
8180 14:00:02.440908 TX Vref=28, minBit 0, minWin=26, winSum=432
8181 14:00:02.443706 TX Vref=30, minBit 0, minWin=26, winSum=426
8182 14:00:02.447455 TX Vref=32, minBit 4, minWin=24, winSum=415
8183 14:00:02.450800 TX Vref=34, minBit 4, minWin=24, winSum=411
8184 14:00:02.453986 TX Vref=36, minBit 0, minWin=24, winSum=396
8185 14:00:02.460410 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8186 14:00:02.460880
8187 14:00:02.463495 Final TX Range 0 Vref 28
8188 14:00:02.463967
8189 14:00:02.464335 ==
8190 14:00:02.467112 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 14:00:02.470514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 14:00:02.471103 ==
8193 14:00:02.471638
8194 14:00:02.472115
8195 14:00:02.473815 TX Vref Scan disable
8196 14:00:02.480510 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8197 14:00:02.481130 == TX Byte 0 ==
8198 14:00:02.483711 u2DelayCellOfst[0]=13 cells (4 PI)
8199 14:00:02.487095 u2DelayCellOfst[1]=20 cells (6 PI)
8200 14:00:02.490271 u2DelayCellOfst[2]=13 cells (4 PI)
8201 14:00:02.493724 u2DelayCellOfst[3]=13 cells (4 PI)
8202 14:00:02.497049 u2DelayCellOfst[4]=10 cells (3 PI)
8203 14:00:02.500431 u2DelayCellOfst[5]=0 cells (0 PI)
8204 14:00:02.503495 u2DelayCellOfst[6]=20 cells (6 PI)
8205 14:00:02.506639 u2DelayCellOfst[7]=20 cells (6 PI)
8206 14:00:02.510139 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8207 14:00:02.513603 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8208 14:00:02.516663 == TX Byte 1 ==
8209 14:00:02.520465 u2DelayCellOfst[8]=0 cells (0 PI)
8210 14:00:02.523765 u2DelayCellOfst[9]=0 cells (0 PI)
8211 14:00:02.524238 u2DelayCellOfst[10]=6 cells (2 PI)
8212 14:00:02.526639 u2DelayCellOfst[11]=3 cells (1 PI)
8213 14:00:02.530474 u2DelayCellOfst[12]=10 cells (3 PI)
8214 14:00:02.534016 u2DelayCellOfst[13]=10 cells (3 PI)
8215 14:00:02.537032 u2DelayCellOfst[14]=13 cells (4 PI)
8216 14:00:02.540369 u2DelayCellOfst[15]=10 cells (3 PI)
8217 14:00:02.546878 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8218 14:00:02.550109 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8219 14:00:02.550689 DramC Write-DBI on
8220 14:00:02.551066 ==
8221 14:00:02.553478 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 14:00:02.560064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 14:00:02.560649 ==
8224 14:00:02.561030
8225 14:00:02.561380
8226 14:00:02.561712 TX Vref Scan disable
8227 14:00:02.564027 == TX Byte 0 ==
8228 14:00:02.567624 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8229 14:00:02.570582 == TX Byte 1 ==
8230 14:00:02.574238 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8231 14:00:02.577910 DramC Write-DBI off
8232 14:00:02.578537
8233 14:00:02.578917 [DATLAT]
8234 14:00:02.579265 Freq=1600, CH0 RK1
8235 14:00:02.579603
8236 14:00:02.580703 DATLAT Default: 0xf
8237 14:00:02.581170 0, 0xFFFF, sum = 0
8238 14:00:02.583927 1, 0xFFFF, sum = 0
8239 14:00:02.584408 2, 0xFFFF, sum = 0
8240 14:00:02.587198 3, 0xFFFF, sum = 0
8241 14:00:02.590613 4, 0xFFFF, sum = 0
8242 14:00:02.591093 5, 0xFFFF, sum = 0
8243 14:00:02.594020 6, 0xFFFF, sum = 0
8244 14:00:02.594495 7, 0xFFFF, sum = 0
8245 14:00:02.597487 8, 0xFFFF, sum = 0
8246 14:00:02.598113 9, 0xFFFF, sum = 0
8247 14:00:02.600757 10, 0xFFFF, sum = 0
8248 14:00:02.601236 11, 0xFFFF, sum = 0
8249 14:00:02.604172 12, 0xFFFF, sum = 0
8250 14:00:02.604652 13, 0xFFFF, sum = 0
8251 14:00:02.607092 14, 0x0, sum = 1
8252 14:00:02.607577 15, 0x0, sum = 2
8253 14:00:02.610665 16, 0x0, sum = 3
8254 14:00:02.611144 17, 0x0, sum = 4
8255 14:00:02.613896 best_step = 15
8256 14:00:02.614505
8257 14:00:02.614885 ==
8258 14:00:02.617153 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 14:00:02.620670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 14:00:02.621145 ==
8261 14:00:02.623952 RX Vref Scan: 0
8262 14:00:02.624421
8263 14:00:02.624794 RX Vref 0 -> 0, step: 1
8264 14:00:02.625169
8265 14:00:02.626950 RX Delay 11 -> 252, step: 4
8266 14:00:02.630326 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8267 14:00:02.637420 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8268 14:00:02.640713 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8269 14:00:02.643571 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8270 14:00:02.646888 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8271 14:00:02.650592 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8272 14:00:02.657031 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8273 14:00:02.660414 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8274 14:00:02.663287 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8275 14:00:02.667130 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8276 14:00:02.670189 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8277 14:00:02.677279 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8278 14:00:02.680507 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8279 14:00:02.683462 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8280 14:00:02.686738 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8281 14:00:02.693637 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8282 14:00:02.694239 ==
8283 14:00:02.697037 Dram Type= 6, Freq= 0, CH_0, rank 1
8284 14:00:02.700088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 14:00:02.700565 ==
8286 14:00:02.700940 DQS Delay:
8287 14:00:02.703296 DQS0 = 0, DQS1 = 0
8288 14:00:02.703767 DQM Delay:
8289 14:00:02.706747 DQM0 = 132, DQM1 = 123
8290 14:00:02.707216 DQ Delay:
8291 14:00:02.710247 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =128
8292 14:00:02.713585 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8293 14:00:02.716950 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8294 14:00:02.719976 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8295 14:00:02.720444
8296 14:00:02.720812
8297 14:00:02.721155
8298 14:00:02.723311 [DramC_TX_OE_Calibration] TA2
8299 14:00:02.726718 Original DQ_B0 (3 6) =30, OEN = 27
8300 14:00:02.730071 Original DQ_B1 (3 6) =30, OEN = 27
8301 14:00:02.733686 24, 0x0, End_B0=24 End_B1=24
8302 14:00:02.736906 25, 0x0, End_B0=25 End_B1=25
8303 14:00:02.737413 26, 0x0, End_B0=26 End_B1=26
8304 14:00:02.740024 27, 0x0, End_B0=27 End_B1=27
8305 14:00:02.743080 28, 0x0, End_B0=28 End_B1=28
8306 14:00:02.746809 29, 0x0, End_B0=29 End_B1=29
8307 14:00:02.749927 30, 0x0, End_B0=30 End_B1=30
8308 14:00:02.750388 31, 0x4141, End_B0=30 End_B1=30
8309 14:00:02.753136 Byte0 end_step=30 best_step=27
8310 14:00:02.756766 Byte1 end_step=30 best_step=27
8311 14:00:02.759981 Byte0 TX OE(2T, 0.5T) = (3, 3)
8312 14:00:02.763333 Byte1 TX OE(2T, 0.5T) = (3, 3)
8313 14:00:02.763753
8314 14:00:02.764082
8315 14:00:02.770189 [DQSOSCAuto] RK1, (LSB)MR18= 0x210d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8316 14:00:02.773410 CH0 RK1: MR19=303, MR18=210D
8317 14:00:02.780023 CH0_RK1: MR19=0x303, MR18=0x210D, DQSOSC=393, MR23=63, INC=23, DEC=15
8318 14:00:02.783155 [RxdqsGatingPostProcess] freq 1600
8319 14:00:02.789723 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8320 14:00:02.790343 best DQS0 dly(2T, 0.5T) = (1, 1)
8321 14:00:02.793467 best DQS1 dly(2T, 0.5T) = (1, 1)
8322 14:00:02.796729 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8323 14:00:02.799766 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8324 14:00:02.802863 best DQS0 dly(2T, 0.5T) = (1, 1)
8325 14:00:02.806149 best DQS1 dly(2T, 0.5T) = (1, 1)
8326 14:00:02.809834 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8327 14:00:02.812973 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8328 14:00:02.816123 Pre-setting of DQS Precalculation
8329 14:00:02.819643 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8330 14:00:02.820221 ==
8331 14:00:02.822842 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 14:00:02.829816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 14:00:02.830422 ==
8334 14:00:02.832978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8335 14:00:02.839611 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8336 14:00:02.843074 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8337 14:00:02.849609 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8338 14:00:02.857383 [CA 0] Center 42 (12~72) winsize 61
8339 14:00:02.860561 [CA 1] Center 42 (12~72) winsize 61
8340 14:00:02.863956 [CA 2] Center 38 (9~68) winsize 60
8341 14:00:02.867133 [CA 3] Center 37 (8~67) winsize 60
8342 14:00:02.870856 [CA 4] Center 37 (8~67) winsize 60
8343 14:00:02.873834 [CA 5] Center 37 (7~67) winsize 61
8344 14:00:02.874465
8345 14:00:02.877188 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8346 14:00:02.877751
8347 14:00:02.880818 [CATrainingPosCal] consider 1 rank data
8348 14:00:02.883984 u2DelayCellTimex100 = 285/100 ps
8349 14:00:02.887214 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8350 14:00:02.894179 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8351 14:00:02.897292 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8352 14:00:02.900564 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8353 14:00:02.903723 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8354 14:00:02.906745 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8355 14:00:02.907207
8356 14:00:02.910623 CA PerBit enable=1, Macro0, CA PI delay=37
8357 14:00:02.911260
8358 14:00:02.913728 [CBTSetCACLKResult] CA Dly = 37
8359 14:00:02.916843 CS Dly: 9 (0~40)
8360 14:00:02.920185 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8361 14:00:02.923484 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8362 14:00:02.923939 ==
8363 14:00:02.927024 Dram Type= 6, Freq= 0, CH_1, rank 1
8364 14:00:02.929981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 14:00:02.930448 ==
8366 14:00:02.936834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8367 14:00:02.940113 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8368 14:00:02.946742 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8369 14:00:02.950231 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8370 14:00:02.960356 [CA 0] Center 41 (12~71) winsize 60
8371 14:00:02.963931 [CA 1] Center 41 (12~71) winsize 60
8372 14:00:02.966859 [CA 2] Center 38 (9~68) winsize 60
8373 14:00:02.970056 [CA 3] Center 37 (8~67) winsize 60
8374 14:00:02.973529 [CA 4] Center 37 (8~67) winsize 60
8375 14:00:02.976849 [CA 5] Center 37 (7~67) winsize 61
8376 14:00:02.977311
8377 14:00:02.980039 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8378 14:00:02.980499
8379 14:00:02.983232 [CATrainingPosCal] consider 2 rank data
8380 14:00:02.986784 u2DelayCellTimex100 = 285/100 ps
8381 14:00:02.990263 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8382 14:00:02.997091 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8383 14:00:03.000124 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8384 14:00:03.003818 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8385 14:00:03.006750 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8386 14:00:03.010155 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8387 14:00:03.010718
8388 14:00:03.013444 CA PerBit enable=1, Macro0, CA PI delay=37
8389 14:00:03.014048
8390 14:00:03.016685 [CBTSetCACLKResult] CA Dly = 37
8391 14:00:03.019880 CS Dly: 9 (0~41)
8392 14:00:03.023398 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8393 14:00:03.026491 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8394 14:00:03.027074
8395 14:00:03.029919 ----->DramcWriteLeveling(PI) begin...
8396 14:00:03.030430 ==
8397 14:00:03.033097 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 14:00:03.036649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 14:00:03.039589 ==
8400 14:00:03.040048 Write leveling (Byte 0): 24 => 24
8401 14:00:03.042952 Write leveling (Byte 1): 27 => 27
8402 14:00:03.046381 DramcWriteLeveling(PI) end<-----
8403 14:00:03.046842
8404 14:00:03.047200 ==
8405 14:00:03.049624 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 14:00:03.056540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 14:00:03.057145 ==
8408 14:00:03.059895 [Gating] SW mode calibration
8409 14:00:03.066671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8410 14:00:03.069744 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8411 14:00:03.076824 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 14:00:03.079747 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 14:00:03.082883 1 4 8 | B1->B0 | 2f2f 3030 | 1 1 | (1 1) (1 1)
8414 14:00:03.089675 1 4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8415 14:00:03.093484 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 14:00:03.096563 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 14:00:03.102774 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 14:00:03.106050 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 14:00:03.109414 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 14:00:03.116014 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8421 14:00:03.119377 1 5 8 | B1->B0 | 2e2e 2c2c | 1 1 | (1 1) (1 0)
8422 14:00:03.122598 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8423 14:00:03.129165 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 14:00:03.132605 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 14:00:03.135598 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 14:00:03.142268 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 14:00:03.145502 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 14:00:03.149018 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8429 14:00:03.152106 1 6 8 | B1->B0 | 3b3b 3f3f | 0 0 | (0 0) (0 0)
8430 14:00:03.158783 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 14:00:03.162694 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 14:00:03.165607 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 14:00:03.172426 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 14:00:03.176241 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 14:00:03.179001 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 14:00:03.186085 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8437 14:00:03.189568 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8438 14:00:03.192415 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8439 14:00:03.199317 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 14:00:03.202313 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 14:00:03.205589 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 14:00:03.212170 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 14:00:03.215715 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 14:00:03.219126 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 14:00:03.225618 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 14:00:03.228763 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 14:00:03.232497 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 14:00:03.239024 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 14:00:03.242250 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 14:00:03.245317 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 14:00:03.252592 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 14:00:03.255416 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8453 14:00:03.259160 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8454 14:00:03.265490 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8455 14:00:03.265996 Total UI for P1: 0, mck2ui 16
8456 14:00:03.269039 best dqsien dly found for B0: ( 1, 9, 6)
8457 14:00:03.275718 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 14:00:03.278846 Total UI for P1: 0, mck2ui 16
8459 14:00:03.282052 best dqsien dly found for B1: ( 1, 9, 10)
8460 14:00:03.285438 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8461 14:00:03.288706 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8462 14:00:03.289283
8463 14:00:03.292335 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8464 14:00:03.295373 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8465 14:00:03.298858 [Gating] SW calibration Done
8466 14:00:03.299421 ==
8467 14:00:03.301988 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 14:00:03.305134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 14:00:03.305607 ==
8470 14:00:03.308707 RX Vref Scan: 0
8471 14:00:03.309275
8472 14:00:03.312139 RX Vref 0 -> 0, step: 1
8473 14:00:03.312605
8474 14:00:03.312974 RX Delay 0 -> 252, step: 8
8475 14:00:03.315160 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8476 14:00:03.321753 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8477 14:00:03.325285 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8478 14:00:03.328716 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8479 14:00:03.331830 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8480 14:00:03.335144 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8481 14:00:03.341900 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8482 14:00:03.344906 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8483 14:00:03.348868 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8484 14:00:03.352044 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8485 14:00:03.355025 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8486 14:00:03.361568 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8487 14:00:03.365092 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8488 14:00:03.368440 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8489 14:00:03.371513 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8490 14:00:03.378196 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8491 14:00:03.378828 ==
8492 14:00:03.381485 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 14:00:03.385125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 14:00:03.385699 ==
8495 14:00:03.386126 DQS Delay:
8496 14:00:03.388133 DQS0 = 0, DQS1 = 0
8497 14:00:03.388596 DQM Delay:
8498 14:00:03.391285 DQM0 = 136, DQM1 = 130
8499 14:00:03.391746 DQ Delay:
8500 14:00:03.394867 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8501 14:00:03.398388 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8502 14:00:03.401612 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8503 14:00:03.404476 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8504 14:00:03.404940
8505 14:00:03.405304
8506 14:00:03.408312 ==
8507 14:00:03.411320 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 14:00:03.414467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 14:00:03.414935 ==
8510 14:00:03.415306
8511 14:00:03.415685
8512 14:00:03.418131 TX Vref Scan disable
8513 14:00:03.418699 == TX Byte 0 ==
8514 14:00:03.421606 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8515 14:00:03.428092 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8516 14:00:03.428675 == TX Byte 1 ==
8517 14:00:03.431005 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8518 14:00:03.438120 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 14:00:03.438686 ==
8520 14:00:03.441676 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 14:00:03.444906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 14:00:03.445479 ==
8523 14:00:03.457464
8524 14:00:03.460530 TX Vref early break, caculate TX vref
8525 14:00:03.463931 TX Vref=16, minBit 10, minWin=22, winSum=369
8526 14:00:03.467301 TX Vref=18, minBit 10, minWin=22, winSum=385
8527 14:00:03.470610 TX Vref=20, minBit 10, minWin=23, winSum=394
8528 14:00:03.473989 TX Vref=22, minBit 10, minWin=23, winSum=403
8529 14:00:03.480410 TX Vref=24, minBit 10, minWin=24, winSum=411
8530 14:00:03.483622 TX Vref=26, minBit 10, minWin=25, winSum=422
8531 14:00:03.487000 TX Vref=28, minBit 14, minWin=25, winSum=422
8532 14:00:03.490415 TX Vref=30, minBit 10, minWin=23, winSum=414
8533 14:00:03.493639 TX Vref=32, minBit 10, minWin=24, winSum=405
8534 14:00:03.497556 TX Vref=34, minBit 12, minWin=23, winSum=394
8535 14:00:03.503988 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 26
8536 14:00:03.504576
8537 14:00:03.507110 Final TX Range 0 Vref 26
8538 14:00:03.507575
8539 14:00:03.507938 ==
8540 14:00:03.510579 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 14:00:03.513763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 14:00:03.514277 ==
8543 14:00:03.517144
8544 14:00:03.517609
8545 14:00:03.518077 TX Vref Scan disable
8546 14:00:03.523475 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8547 14:00:03.523941 == TX Byte 0 ==
8548 14:00:03.526976 u2DelayCellOfst[0]=13 cells (4 PI)
8549 14:00:03.530168 u2DelayCellOfst[1]=10 cells (3 PI)
8550 14:00:03.534132 u2DelayCellOfst[2]=0 cells (0 PI)
8551 14:00:03.537218 u2DelayCellOfst[3]=6 cells (2 PI)
8552 14:00:03.540122 u2DelayCellOfst[4]=6 cells (2 PI)
8553 14:00:03.543490 u2DelayCellOfst[5]=17 cells (5 PI)
8554 14:00:03.547218 u2DelayCellOfst[6]=17 cells (5 PI)
8555 14:00:03.550173 u2DelayCellOfst[7]=6 cells (2 PI)
8556 14:00:03.553328 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8557 14:00:03.556998 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8558 14:00:03.560060 == TX Byte 1 ==
8559 14:00:03.563384 u2DelayCellOfst[8]=0 cells (0 PI)
8560 14:00:03.566879 u2DelayCellOfst[9]=3 cells (1 PI)
8561 14:00:03.569989 u2DelayCellOfst[10]=10 cells (3 PI)
8562 14:00:03.573499 u2DelayCellOfst[11]=3 cells (1 PI)
8563 14:00:03.574162 u2DelayCellOfst[12]=13 cells (4 PI)
8564 14:00:03.576586 u2DelayCellOfst[13]=17 cells (5 PI)
8565 14:00:03.579596 u2DelayCellOfst[14]=17 cells (5 PI)
8566 14:00:03.583287 u2DelayCellOfst[15]=17 cells (5 PI)
8567 14:00:03.590038 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8568 14:00:03.593085 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8569 14:00:03.593551 DramC Write-DBI on
8570 14:00:03.596651 ==
8571 14:00:03.599833 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 14:00:03.602901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 14:00:03.603371 ==
8574 14:00:03.603735
8575 14:00:03.604074
8576 14:00:03.606709 TX Vref Scan disable
8577 14:00:03.607172 == TX Byte 0 ==
8578 14:00:03.613236 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8579 14:00:03.613836 == TX Byte 1 ==
8580 14:00:03.616633 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8581 14:00:03.620129 DramC Write-DBI off
8582 14:00:03.620745
8583 14:00:03.621117 [DATLAT]
8584 14:00:03.622762 Freq=1600, CH1 RK0
8585 14:00:03.623224
8586 14:00:03.623589 DATLAT Default: 0xf
8587 14:00:03.626148 0, 0xFFFF, sum = 0
8588 14:00:03.626722 1, 0xFFFF, sum = 0
8589 14:00:03.629714 2, 0xFFFF, sum = 0
8590 14:00:03.630472 3, 0xFFFF, sum = 0
8591 14:00:03.633322 4, 0xFFFF, sum = 0
8592 14:00:03.633890 5, 0xFFFF, sum = 0
8593 14:00:03.636317 6, 0xFFFF, sum = 0
8594 14:00:03.636885 7, 0xFFFF, sum = 0
8595 14:00:03.639959 8, 0xFFFF, sum = 0
8596 14:00:03.640528 9, 0xFFFF, sum = 0
8597 14:00:03.643173 10, 0xFFFF, sum = 0
8598 14:00:03.646110 11, 0xFFFF, sum = 0
8599 14:00:03.646657 12, 0xFFFF, sum = 0
8600 14:00:03.649883 13, 0xFFFF, sum = 0
8601 14:00:03.650500 14, 0x0, sum = 1
8602 14:00:03.652838 15, 0x0, sum = 2
8603 14:00:03.653408 16, 0x0, sum = 3
8604 14:00:03.653787 17, 0x0, sum = 4
8605 14:00:03.656824 best_step = 15
8606 14:00:03.657375
8607 14:00:03.657742 ==
8608 14:00:03.659473 Dram Type= 6, Freq= 0, CH_1, rank 0
8609 14:00:03.663028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8610 14:00:03.663590 ==
8611 14:00:03.666313 RX Vref Scan: 1
8612 14:00:03.666873
8613 14:00:03.669814 Set Vref Range= 24 -> 127
8614 14:00:03.670424
8615 14:00:03.670798 RX Vref 24 -> 127, step: 1
8616 14:00:03.671143
8617 14:00:03.672895 RX Delay 19 -> 252, step: 4
8618 14:00:03.673459
8619 14:00:03.676093 Set Vref, RX VrefLevel [Byte0]: 24
8620 14:00:03.679068 [Byte1]: 24
8621 14:00:03.682579
8622 14:00:03.683104 Set Vref, RX VrefLevel [Byte0]: 25
8623 14:00:03.685771 [Byte1]: 25
8624 14:00:03.690143
8625 14:00:03.690673 Set Vref, RX VrefLevel [Byte0]: 26
8626 14:00:03.693439 [Byte1]: 26
8627 14:00:03.697933
8628 14:00:03.698470 Set Vref, RX VrefLevel [Byte0]: 27
8629 14:00:03.701312 [Byte1]: 27
8630 14:00:03.705540
8631 14:00:03.706156 Set Vref, RX VrefLevel [Byte0]: 28
8632 14:00:03.708866 [Byte1]: 28
8633 14:00:03.712560
8634 14:00:03.713023 Set Vref, RX VrefLevel [Byte0]: 29
8635 14:00:03.716095 [Byte1]: 29
8636 14:00:03.720606
8637 14:00:03.721198 Set Vref, RX VrefLevel [Byte0]: 30
8638 14:00:03.723888 [Byte1]: 30
8639 14:00:03.728262
8640 14:00:03.728849 Set Vref, RX VrefLevel [Byte0]: 31
8641 14:00:03.731431 [Byte1]: 31
8642 14:00:03.736110
8643 14:00:03.736689 Set Vref, RX VrefLevel [Byte0]: 32
8644 14:00:03.738757 [Byte1]: 32
8645 14:00:03.743022
8646 14:00:03.743601 Set Vref, RX VrefLevel [Byte0]: 33
8647 14:00:03.746386 [Byte1]: 33
8648 14:00:03.750872
8649 14:00:03.751448 Set Vref, RX VrefLevel [Byte0]: 34
8650 14:00:03.754108 [Byte1]: 34
8651 14:00:03.758158
8652 14:00:03.758634 Set Vref, RX VrefLevel [Byte0]: 35
8653 14:00:03.761362 [Byte1]: 35
8654 14:00:03.765704
8655 14:00:03.766206 Set Vref, RX VrefLevel [Byte0]: 36
8656 14:00:03.768893 [Byte1]: 36
8657 14:00:03.773183
8658 14:00:03.773652 Set Vref, RX VrefLevel [Byte0]: 37
8659 14:00:03.776652 [Byte1]: 37
8660 14:00:03.781185
8661 14:00:03.781655 Set Vref, RX VrefLevel [Byte0]: 38
8662 14:00:03.784114 [Byte1]: 38
8663 14:00:03.788423
8664 14:00:03.788890 Set Vref, RX VrefLevel [Byte0]: 39
8665 14:00:03.791814 [Byte1]: 39
8666 14:00:03.795926
8667 14:00:03.796401 Set Vref, RX VrefLevel [Byte0]: 40
8668 14:00:03.799826 [Byte1]: 40
8669 14:00:03.803860
8670 14:00:03.804457 Set Vref, RX VrefLevel [Byte0]: 41
8671 14:00:03.807332 [Byte1]: 41
8672 14:00:03.811024
8673 14:00:03.811560 Set Vref, RX VrefLevel [Byte0]: 42
8674 14:00:03.814597 [Byte1]: 42
8675 14:00:03.819096
8676 14:00:03.819791 Set Vref, RX VrefLevel [Byte0]: 43
8677 14:00:03.822344 [Byte1]: 43
8678 14:00:03.826688
8679 14:00:03.827264 Set Vref, RX VrefLevel [Byte0]: 44
8680 14:00:03.829580 [Byte1]: 44
8681 14:00:03.833874
8682 14:00:03.834387 Set Vref, RX VrefLevel [Byte0]: 45
8683 14:00:03.837452 [Byte1]: 45
8684 14:00:03.842115
8685 14:00:03.842686 Set Vref, RX VrefLevel [Byte0]: 46
8686 14:00:03.844824 [Byte1]: 46
8687 14:00:03.849592
8688 14:00:03.850213 Set Vref, RX VrefLevel [Byte0]: 47
8689 14:00:03.852758 [Byte1]: 47
8690 14:00:03.857019
8691 14:00:03.857599 Set Vref, RX VrefLevel [Byte0]: 48
8692 14:00:03.859987 [Byte1]: 48
8693 14:00:03.864126
8694 14:00:03.864708 Set Vref, RX VrefLevel [Byte0]: 49
8695 14:00:03.867854 [Byte1]: 49
8696 14:00:03.871847
8697 14:00:03.872423 Set Vref, RX VrefLevel [Byte0]: 50
8698 14:00:03.875487 [Byte1]: 50
8699 14:00:03.879611
8700 14:00:03.880339 Set Vref, RX VrefLevel [Byte0]: 51
8701 14:00:03.882538 [Byte1]: 51
8702 14:00:03.887314
8703 14:00:03.887890 Set Vref, RX VrefLevel [Byte0]: 52
8704 14:00:03.890065 [Byte1]: 52
8705 14:00:03.894691
8706 14:00:03.895269 Set Vref, RX VrefLevel [Byte0]: 53
8707 14:00:03.897987 [Byte1]: 53
8708 14:00:03.902517
8709 14:00:03.903087 Set Vref, RX VrefLevel [Byte0]: 54
8710 14:00:03.905523 [Byte1]: 54
8711 14:00:03.910060
8712 14:00:03.910662 Set Vref, RX VrefLevel [Byte0]: 55
8713 14:00:03.912819 [Byte1]: 55
8714 14:00:03.917293
8715 14:00:03.917870 Set Vref, RX VrefLevel [Byte0]: 56
8716 14:00:03.920523 [Byte1]: 56
8717 14:00:03.925069
8718 14:00:03.925654 Set Vref, RX VrefLevel [Byte0]: 57
8719 14:00:03.928417 [Byte1]: 57
8720 14:00:03.932475
8721 14:00:03.932947 Set Vref, RX VrefLevel [Byte0]: 58
8722 14:00:03.935835 [Byte1]: 58
8723 14:00:03.939770
8724 14:00:03.940257 Set Vref, RX VrefLevel [Byte0]: 59
8725 14:00:03.943309 [Byte1]: 59
8726 14:00:03.947607
8727 14:00:03.948097 Set Vref, RX VrefLevel [Byte0]: 60
8728 14:00:03.950848 [Byte1]: 60
8729 14:00:03.955313
8730 14:00:03.955922 Set Vref, RX VrefLevel [Byte0]: 61
8731 14:00:03.958861 [Byte1]: 61
8732 14:00:03.962656
8733 14:00:03.963280 Set Vref, RX VrefLevel [Byte0]: 62
8734 14:00:03.966329 [Byte1]: 62
8735 14:00:03.970444
8736 14:00:03.971012 Set Vref, RX VrefLevel [Byte0]: 63
8737 14:00:03.973716 [Byte1]: 63
8738 14:00:03.978160
8739 14:00:03.978727 Set Vref, RX VrefLevel [Byte0]: 64
8740 14:00:03.981480 [Byte1]: 64
8741 14:00:03.985621
8742 14:00:03.986245 Set Vref, RX VrefLevel [Byte0]: 65
8743 14:00:03.989191 [Byte1]: 65
8744 14:00:03.993441
8745 14:00:03.994068 Set Vref, RX VrefLevel [Byte0]: 66
8746 14:00:03.996735 [Byte1]: 66
8747 14:00:04.000915
8748 14:00:04.001495 Set Vref, RX VrefLevel [Byte0]: 67
8749 14:00:04.003805 [Byte1]: 67
8750 14:00:04.008357
8751 14:00:04.008954 Set Vref, RX VrefLevel [Byte0]: 68
8752 14:00:04.011644 [Byte1]: 68
8753 14:00:04.015671
8754 14:00:04.016140 Set Vref, RX VrefLevel [Byte0]: 69
8755 14:00:04.019280 [Byte1]: 69
8756 14:00:04.023456
8757 14:00:04.024148 Set Vref, RX VrefLevel [Byte0]: 70
8758 14:00:04.026611 [Byte1]: 70
8759 14:00:04.030747
8760 14:00:04.031393 Set Vref, RX VrefLevel [Byte0]: 71
8761 14:00:04.034241 [Byte1]: 71
8762 14:00:04.038467
8763 14:00:04.039039 Set Vref, RX VrefLevel [Byte0]: 72
8764 14:00:04.042036 [Byte1]: 72
8765 14:00:04.046049
8766 14:00:04.046517 Set Vref, RX VrefLevel [Byte0]: 73
8767 14:00:04.049352 [Byte1]: 73
8768 14:00:04.054158
8769 14:00:04.054731 Set Vref, RX VrefLevel [Byte0]: 74
8770 14:00:04.056810 [Byte1]: 74
8771 14:00:04.061367
8772 14:00:04.062046 Final RX Vref Byte 0 = 60 to rank0
8773 14:00:04.064635 Final RX Vref Byte 1 = 60 to rank0
8774 14:00:04.067736 Final RX Vref Byte 0 = 60 to rank1
8775 14:00:04.071258 Final RX Vref Byte 1 = 60 to rank1==
8776 14:00:04.074714 Dram Type= 6, Freq= 0, CH_1, rank 0
8777 14:00:04.081409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 14:00:04.082077 ==
8779 14:00:04.082468 DQS Delay:
8780 14:00:04.084378 DQS0 = 0, DQS1 = 0
8781 14:00:04.084847 DQM Delay:
8782 14:00:04.085223 DQM0 = 134, DQM1 = 130
8783 14:00:04.088117 DQ Delay:
8784 14:00:04.091021 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8785 14:00:04.094335 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8786 14:00:04.097659 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8787 14:00:04.101466 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8788 14:00:04.102097
8789 14:00:04.102479
8790 14:00:04.102828
8791 14:00:04.104120 [DramC_TX_OE_Calibration] TA2
8792 14:00:04.107913 Original DQ_B0 (3 6) =30, OEN = 27
8793 14:00:04.111309 Original DQ_B1 (3 6) =30, OEN = 27
8794 14:00:04.114555 24, 0x0, End_B0=24 End_B1=24
8795 14:00:04.115036 25, 0x0, End_B0=25 End_B1=25
8796 14:00:04.117584 26, 0x0, End_B0=26 End_B1=26
8797 14:00:04.121137 27, 0x0, End_B0=27 End_B1=27
8798 14:00:04.124635 28, 0x0, End_B0=28 End_B1=28
8799 14:00:04.125209 29, 0x0, End_B0=29 End_B1=29
8800 14:00:04.127856 30, 0x0, End_B0=30 End_B1=30
8801 14:00:04.131080 31, 0x4141, End_B0=30 End_B1=30
8802 14:00:04.134520 Byte0 end_step=30 best_step=27
8803 14:00:04.137861 Byte1 end_step=30 best_step=27
8804 14:00:04.141016 Byte0 TX OE(2T, 0.5T) = (3, 3)
8805 14:00:04.141584 Byte1 TX OE(2T, 0.5T) = (3, 3)
8806 14:00:04.144115
8807 14:00:04.144589
8808 14:00:04.150689 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8809 14:00:04.154333 CH1 RK0: MR19=303, MR18=1927
8810 14:00:04.160754 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8811 14:00:04.161318
8812 14:00:04.164448 ----->DramcWriteLeveling(PI) begin...
8813 14:00:04.165034 ==
8814 14:00:04.168109 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 14:00:04.171024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 14:00:04.171604 ==
8817 14:00:04.174694 Write leveling (Byte 0): 24 => 24
8818 14:00:04.177926 Write leveling (Byte 1): 27 => 27
8819 14:00:04.180973 DramcWriteLeveling(PI) end<-----
8820 14:00:04.181555
8821 14:00:04.182255 ==
8822 14:00:04.184587 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 14:00:04.187834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 14:00:04.188418 ==
8825 14:00:04.191046 [Gating] SW mode calibration
8826 14:00:04.198254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8827 14:00:04.204922 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8828 14:00:04.207877 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 14:00:04.211229 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 14:00:04.218066 1 4 8 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
8831 14:00:04.221192 1 4 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
8832 14:00:04.224314 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 14:00:04.231028 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 14:00:04.234459 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 14:00:04.237613 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 14:00:04.243818 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 14:00:04.247405 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 14:00:04.250867 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (0 1) (1 0)
8839 14:00:04.257265 1 5 12 | B1->B0 | 2323 2f2f | 0 1 | (1 0) (1 0)
8840 14:00:04.261118 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 14:00:04.264073 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 14:00:04.270813 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 14:00:04.274016 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 14:00:04.277525 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 14:00:04.283621 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 14:00:04.287155 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8847 14:00:04.290534 1 6 12 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
8848 14:00:04.297602 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 14:00:04.300641 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 14:00:04.304139 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 14:00:04.307432 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 14:00:04.314004 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 14:00:04.317560 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 14:00:04.320866 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8855 14:00:04.326962 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8856 14:00:04.330669 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 14:00:04.333623 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 14:00:04.340409 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 14:00:04.343553 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 14:00:04.347176 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 14:00:04.354089 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 14:00:04.357167 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 14:00:04.360200 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 14:00:04.367306 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 14:00:04.370439 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 14:00:04.373727 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 14:00:04.380379 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 14:00:04.383426 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 14:00:04.386782 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 14:00:04.393643 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8871 14:00:04.396991 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8872 14:00:04.400351 Total UI for P1: 0, mck2ui 16
8873 14:00:04.403328 best dqsien dly found for B1: ( 1, 9, 8)
8874 14:00:04.406727 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 14:00:04.410017 Total UI for P1: 0, mck2ui 16
8876 14:00:04.413462 best dqsien dly found for B0: ( 1, 9, 10)
8877 14:00:04.416374 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8878 14:00:04.420053 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8879 14:00:04.420626
8880 14:00:04.426578 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8881 14:00:04.429996 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8882 14:00:04.430471 [Gating] SW calibration Done
8883 14:00:04.432949 ==
8884 14:00:04.436450 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 14:00:04.440035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 14:00:04.440605 ==
8887 14:00:04.440976 RX Vref Scan: 0
8888 14:00:04.441317
8889 14:00:04.442884 RX Vref 0 -> 0, step: 1
8890 14:00:04.443354
8891 14:00:04.446423 RX Delay 0 -> 252, step: 8
8892 14:00:04.450119 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8893 14:00:04.453376 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8894 14:00:04.456587 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8895 14:00:04.462878 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8896 14:00:04.466237 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8897 14:00:04.469882 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8898 14:00:04.473162 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8899 14:00:04.476398 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8900 14:00:04.482865 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8901 14:00:04.486186 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8902 14:00:04.489846 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8903 14:00:04.492876 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8904 14:00:04.496599 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8905 14:00:04.502844 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8906 14:00:04.506175 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8907 14:00:04.509523 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8908 14:00:04.510153 ==
8909 14:00:04.512599 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 14:00:04.516011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 14:00:04.519105 ==
8912 14:00:04.519573 DQS Delay:
8913 14:00:04.519943 DQS0 = 0, DQS1 = 0
8914 14:00:04.522575 DQM Delay:
8915 14:00:04.523139 DQM0 = 136, DQM1 = 133
8916 14:00:04.526076 DQ Delay:
8917 14:00:04.529126 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8918 14:00:04.532710 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8919 14:00:04.535666 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8920 14:00:04.539351 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8921 14:00:04.539919
8922 14:00:04.540291
8923 14:00:04.540636 ==
8924 14:00:04.542409 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 14:00:04.546008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 14:00:04.546631 ==
8927 14:00:04.547019
8928 14:00:04.549076
8929 14:00:04.549542 TX Vref Scan disable
8930 14:00:04.552436 == TX Byte 0 ==
8931 14:00:04.556023 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8932 14:00:04.559224 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8933 14:00:04.562332 == TX Byte 1 ==
8934 14:00:04.565965 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8935 14:00:04.569160 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8936 14:00:04.569734 ==
8937 14:00:04.572580 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 14:00:04.579004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 14:00:04.579591 ==
8940 14:00:04.589411
8941 14:00:04.592746 TX Vref early break, caculate TX vref
8942 14:00:04.596254 TX Vref=16, minBit 10, minWin=23, winSum=389
8943 14:00:04.599529 TX Vref=18, minBit 9, minWin=23, winSum=391
8944 14:00:04.602814 TX Vref=20, minBit 8, minWin=24, winSum=405
8945 14:00:04.605775 TX Vref=22, minBit 8, minWin=25, winSum=414
8946 14:00:04.609361 TX Vref=24, minBit 0, minWin=25, winSum=417
8947 14:00:04.615787 TX Vref=26, minBit 0, minWin=26, winSum=429
8948 14:00:04.619652 TX Vref=28, minBit 10, minWin=25, winSum=419
8949 14:00:04.622805 TX Vref=30, minBit 1, minWin=25, winSum=412
8950 14:00:04.626226 TX Vref=32, minBit 9, minWin=24, winSum=406
8951 14:00:04.632823 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
8952 14:00:04.633392
8953 14:00:04.635718 Final TX Range 0 Vref 26
8954 14:00:04.636185
8955 14:00:04.636551 ==
8956 14:00:04.639209 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 14:00:04.642651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 14:00:04.643225 ==
8959 14:00:04.643667
8960 14:00:04.644022
8961 14:00:04.645479 TX Vref Scan disable
8962 14:00:04.649377 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8963 14:00:04.652483 == TX Byte 0 ==
8964 14:00:04.655962 u2DelayCellOfst[0]=13 cells (4 PI)
8965 14:00:04.659283 u2DelayCellOfst[1]=10 cells (3 PI)
8966 14:00:04.662613 u2DelayCellOfst[2]=0 cells (0 PI)
8967 14:00:04.666125 u2DelayCellOfst[3]=3 cells (1 PI)
8968 14:00:04.669206 u2DelayCellOfst[4]=6 cells (2 PI)
8969 14:00:04.669674 u2DelayCellOfst[5]=17 cells (5 PI)
8970 14:00:04.672699 u2DelayCellOfst[6]=17 cells (5 PI)
8971 14:00:04.676320 u2DelayCellOfst[7]=3 cells (1 PI)
8972 14:00:04.682137 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8973 14:00:04.685859 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8974 14:00:04.686446 == TX Byte 1 ==
8975 14:00:04.688911 u2DelayCellOfst[8]=0 cells (0 PI)
8976 14:00:04.692522 u2DelayCellOfst[9]=3 cells (1 PI)
8977 14:00:04.695788 u2DelayCellOfst[10]=10 cells (3 PI)
8978 14:00:04.699064 u2DelayCellOfst[11]=3 cells (1 PI)
8979 14:00:04.702225 u2DelayCellOfst[12]=13 cells (4 PI)
8980 14:00:04.706051 u2DelayCellOfst[13]=17 cells (5 PI)
8981 14:00:04.709025 u2DelayCellOfst[14]=20 cells (6 PI)
8982 14:00:04.712050 u2DelayCellOfst[15]=20 cells (6 PI)
8983 14:00:04.715767 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8984 14:00:04.719013 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8985 14:00:04.721979 DramC Write-DBI on
8986 14:00:04.722441 ==
8987 14:00:04.725766 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 14:00:04.728808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 14:00:04.729280 ==
8990 14:00:04.729646
8991 14:00:04.730033
8992 14:00:04.732059 TX Vref Scan disable
8993 14:00:04.735588 == TX Byte 0 ==
8994 14:00:04.738740 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8995 14:00:04.741918 == TX Byte 1 ==
8996 14:00:04.745053 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8997 14:00:04.745388 DramC Write-DBI off
8998 14:00:04.745652
8999 14:00:04.748829 [DATLAT]
9000 14:00:04.749075 Freq=1600, CH1 RK1
9001 14:00:04.749271
9002 14:00:04.752163 DATLAT Default: 0xf
9003 14:00:04.752449 0, 0xFFFF, sum = 0
9004 14:00:04.755097 1, 0xFFFF, sum = 0
9005 14:00:04.755303 2, 0xFFFF, sum = 0
9006 14:00:04.758211 3, 0xFFFF, sum = 0
9007 14:00:04.758410 4, 0xFFFF, sum = 0
9008 14:00:04.761711 5, 0xFFFF, sum = 0
9009 14:00:04.762018 6, 0xFFFF, sum = 0
9010 14:00:04.765380 7, 0xFFFF, sum = 0
9011 14:00:04.765669 8, 0xFFFF, sum = 0
9012 14:00:04.768288 9, 0xFFFF, sum = 0
9013 14:00:04.771637 10, 0xFFFF, sum = 0
9014 14:00:04.771928 11, 0xFFFF, sum = 0
9015 14:00:04.774971 12, 0xFFFF, sum = 0
9016 14:00:04.775260 13, 0xFFFF, sum = 0
9017 14:00:04.778124 14, 0x0, sum = 1
9018 14:00:04.778434 15, 0x0, sum = 2
9019 14:00:04.781492 16, 0x0, sum = 3
9020 14:00:04.781710 17, 0x0, sum = 4
9021 14:00:04.781868 best_step = 15
9022 14:00:04.784836
9023 14:00:04.785067 ==
9024 14:00:04.788204 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 14:00:04.791412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 14:00:04.791647 ==
9027 14:00:04.791831 RX Vref Scan: 0
9028 14:00:04.792002
9029 14:00:04.794535 RX Vref 0 -> 0, step: 1
9030 14:00:04.794840
9031 14:00:04.798165 RX Delay 19 -> 252, step: 4
9032 14:00:04.801444 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9033 14:00:04.804832 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9034 14:00:04.811487 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9035 14:00:04.814690 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9036 14:00:04.817994 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9037 14:00:04.821759 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9038 14:00:04.824983 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9039 14:00:04.831823 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9040 14:00:04.834822 iDelay=195, Bit 8, Center 114 (63 ~ 166) 104
9041 14:00:04.838286 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9042 14:00:04.841553 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9043 14:00:04.845010 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9044 14:00:04.851717 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9045 14:00:04.854439 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9046 14:00:04.858078 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9047 14:00:04.861406 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9048 14:00:04.862031 ==
9049 14:00:04.865056 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 14:00:04.871121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 14:00:04.871690 ==
9052 14:00:04.872065 DQS Delay:
9053 14:00:04.874438 DQS0 = 0, DQS1 = 0
9054 14:00:04.874908 DQM Delay:
9055 14:00:04.875281 DQM0 = 133, DQM1 = 130
9056 14:00:04.878136 DQ Delay:
9057 14:00:04.881237 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9058 14:00:04.884833 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
9059 14:00:04.888005 DQ8 =114, DQ9 =120, DQ10 =130, DQ11 =126
9060 14:00:04.891255 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =140
9061 14:00:04.891850
9062 14:00:04.892231
9063 14:00:04.892578
9064 14:00:04.894341 [DramC_TX_OE_Calibration] TA2
9065 14:00:04.897669 Original DQ_B0 (3 6) =30, OEN = 27
9066 14:00:04.901133 Original DQ_B1 (3 6) =30, OEN = 27
9067 14:00:04.904594 24, 0x0, End_B0=24 End_B1=24
9068 14:00:04.905074 25, 0x0, End_B0=25 End_B1=25
9069 14:00:04.907909 26, 0x0, End_B0=26 End_B1=26
9070 14:00:04.910843 27, 0x0, End_B0=27 End_B1=27
9071 14:00:04.914184 28, 0x0, End_B0=28 End_B1=28
9072 14:00:04.917652 29, 0x0, End_B0=29 End_B1=29
9073 14:00:04.918173 30, 0x0, End_B0=30 End_B1=30
9074 14:00:04.921018 31, 0x4141, End_B0=30 End_B1=30
9075 14:00:04.924606 Byte0 end_step=30 best_step=27
9076 14:00:04.928041 Byte1 end_step=30 best_step=27
9077 14:00:04.931162 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 14:00:04.934364 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 14:00:04.934936
9080 14:00:04.935315
9081 14:00:04.940991 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9082 14:00:04.944392 CH1 RK1: MR19=303, MR18=1E09
9083 14:00:04.950898 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9084 14:00:04.954067 [RxdqsGatingPostProcess] freq 1600
9085 14:00:04.957486 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 14:00:04.960765 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 14:00:04.964078 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 14:00:04.967468 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 14:00:04.970971 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 14:00:04.974057 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 14:00:04.977309 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 14:00:04.980589 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 14:00:04.984249 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 14:00:04.987313 Pre-setting of DQS Precalculation
9095 14:00:04.990833 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 14:00:04.997083 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 14:00:05.006875 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 14:00:05.007439
9099 14:00:05.007812
9100 14:00:05.010148 [Calibration Summary] 3200 Mbps
9101 14:00:05.010621 CH 0, Rank 0
9102 14:00:05.013767 SW Impedance : PASS
9103 14:00:05.014408 DUTY Scan : NO K
9104 14:00:05.017427 ZQ Calibration : PASS
9105 14:00:05.020290 Jitter Meter : NO K
9106 14:00:05.020889 CBT Training : PASS
9107 14:00:05.024367 Write leveling : PASS
9108 14:00:05.024839 RX DQS gating : PASS
9109 14:00:05.027268 RX DQ/DQS(RDDQC) : PASS
9110 14:00:05.030504 TX DQ/DQS : PASS
9111 14:00:05.030981 RX DATLAT : PASS
9112 14:00:05.033648 RX DQ/DQS(Engine): PASS
9113 14:00:05.037302 TX OE : PASS
9114 14:00:05.037774 All Pass.
9115 14:00:05.038182
9116 14:00:05.038530 CH 0, Rank 1
9117 14:00:05.040571 SW Impedance : PASS
9118 14:00:05.044121 DUTY Scan : NO K
9119 14:00:05.044705 ZQ Calibration : PASS
9120 14:00:05.046880 Jitter Meter : NO K
9121 14:00:05.050648 CBT Training : PASS
9122 14:00:05.051118 Write leveling : PASS
9123 14:00:05.053870 RX DQS gating : PASS
9124 14:00:05.057343 RX DQ/DQS(RDDQC) : PASS
9125 14:00:05.057926 TX DQ/DQS : PASS
9126 14:00:05.060533 RX DATLAT : PASS
9127 14:00:05.061003 RX DQ/DQS(Engine): PASS
9128 14:00:05.063991 TX OE : PASS
9129 14:00:05.064577 All Pass.
9130 14:00:05.064958
9131 14:00:05.067373 CH 1, Rank 0
9132 14:00:05.067951 SW Impedance : PASS
9133 14:00:05.070387 DUTY Scan : NO K
9134 14:00:05.074022 ZQ Calibration : PASS
9135 14:00:05.074601 Jitter Meter : NO K
9136 14:00:05.077457 CBT Training : PASS
9137 14:00:05.080821 Write leveling : PASS
9138 14:00:05.081401 RX DQS gating : PASS
9139 14:00:05.083566 RX DQ/DQS(RDDQC) : PASS
9140 14:00:05.086969 TX DQ/DQS : PASS
9141 14:00:05.087443 RX DATLAT : PASS
9142 14:00:05.090186 RX DQ/DQS(Engine): PASS
9143 14:00:05.093737 TX OE : PASS
9144 14:00:05.094364 All Pass.
9145 14:00:05.094740
9146 14:00:05.095089 CH 1, Rank 1
9147 14:00:05.097002 SW Impedance : PASS
9148 14:00:05.100588 DUTY Scan : NO K
9149 14:00:05.101170 ZQ Calibration : PASS
9150 14:00:05.103959 Jitter Meter : NO K
9151 14:00:05.107033 CBT Training : PASS
9152 14:00:05.107506 Write leveling : PASS
9153 14:00:05.110421 RX DQS gating : PASS
9154 14:00:05.110893 RX DQ/DQS(RDDQC) : PASS
9155 14:00:05.113639 TX DQ/DQS : PASS
9156 14:00:05.116703 RX DATLAT : PASS
9157 14:00:05.117174 RX DQ/DQS(Engine): PASS
9158 14:00:05.120216 TX OE : PASS
9159 14:00:05.120688 All Pass.
9160 14:00:05.121064
9161 14:00:05.123685 DramC Write-DBI on
9162 14:00:05.126687 PER_BANK_REFRESH: Hybrid Mode
9163 14:00:05.127156 TX_TRACKING: ON
9164 14:00:05.136927 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 14:00:05.143787 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 14:00:05.150543 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 14:00:05.157323 [FAST_K] Save calibration result to emmc
9168 14:00:05.157900 sync common calibartion params.
9169 14:00:05.160440 sync cbt_mode0:1, 1:1
9170 14:00:05.163557 dram_init: ddr_geometry: 2
9171 14:00:05.164030 dram_init: ddr_geometry: 2
9172 14:00:05.166864 dram_init: ddr_geometry: 2
9173 14:00:05.170228 0:dram_rank_size:100000000
9174 14:00:05.173550 1:dram_rank_size:100000000
9175 14:00:05.177015 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 14:00:05.180206 DFS_SHUFFLE_HW_MODE: ON
9177 14:00:05.183806 dramc_set_vcore_voltage set vcore to 725000
9178 14:00:05.187133 Read voltage for 1600, 0
9179 14:00:05.187749 Vio18 = 0
9180 14:00:05.188135 Vcore = 725000
9181 14:00:05.189866 Vdram = 0
9182 14:00:05.190360 Vddq = 0
9183 14:00:05.190734 Vmddr = 0
9184 14:00:05.193380 switch to 3200 Mbps bootup
9185 14:00:05.197103 [DramcRunTimeConfig]
9186 14:00:05.197676 PHYPLL
9187 14:00:05.198094 DPM_CONTROL_AFTERK: ON
9188 14:00:05.200259 PER_BANK_REFRESH: ON
9189 14:00:05.203692 REFRESH_OVERHEAD_REDUCTION: ON
9190 14:00:05.204269 CMD_PICG_NEW_MODE: OFF
9191 14:00:05.206568 XRTWTW_NEW_MODE: ON
9192 14:00:05.210473 XRTRTR_NEW_MODE: ON
9193 14:00:05.211047 TX_TRACKING: ON
9194 14:00:05.213126 RDSEL_TRACKING: OFF
9195 14:00:05.213597 DQS Precalculation for DVFS: ON
9196 14:00:05.216583 RX_TRACKING: OFF
9197 14:00:05.217055 HW_GATING DBG: ON
9198 14:00:05.220191 ZQCS_ENABLE_LP4: ON
9199 14:00:05.220659 RX_PICG_NEW_MODE: ON
9200 14:00:05.223371 TX_PICG_NEW_MODE: ON
9201 14:00:05.226576 ENABLE_RX_DCM_DPHY: ON
9202 14:00:05.230013 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 14:00:05.230530 DUMMY_READ_FOR_TRACKING: OFF
9204 14:00:05.233387 !!! SPM_CONTROL_AFTERK: OFF
9205 14:00:05.236472 !!! SPM could not control APHY
9206 14:00:05.239943 IMPEDANCE_TRACKING: ON
9207 14:00:05.240639 TEMP_SENSOR: ON
9208 14:00:05.243760 HW_SAVE_FOR_SR: OFF
9209 14:00:05.244333 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 14:00:05.249796 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 14:00:05.250316 Read ODT Tracking: ON
9212 14:00:05.253586 Refresh Rate DeBounce: ON
9213 14:00:05.256815 DFS_NO_QUEUE_FLUSH: ON
9214 14:00:05.257382 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 14:00:05.259911 ENABLE_DFS_RUNTIME_MRW: OFF
9216 14:00:05.262821 DDR_RESERVE_NEW_MODE: ON
9217 14:00:05.266857 MR_CBT_SWITCH_FREQ: ON
9218 14:00:05.267426 =========================
9219 14:00:05.285840 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 14:00:05.289064 dram_init: ddr_geometry: 2
9221 14:00:05.307998 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 14:00:05.310791 dram_init: dram init end (result: 0)
9223 14:00:05.317553 DRAM-K: Full calibration passed in 24512 msecs
9224 14:00:05.320760 MRC: failed to locate region type 0.
9225 14:00:05.321325 DRAM rank0 size:0x100000000,
9226 14:00:05.324535 DRAM rank1 size=0x100000000
9227 14:00:05.334419 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 14:00:05.340621 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 14:00:05.347302 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 14:00:05.354463 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 14:00:05.357496 DRAM rank0 size:0x100000000,
9232 14:00:05.361107 DRAM rank1 size=0x100000000
9233 14:00:05.361672 CBMEM:
9234 14:00:05.364018 IMD: root @ 0xfffff000 254 entries.
9235 14:00:05.367712 IMD: root @ 0xffffec00 62 entries.
9236 14:00:05.370839 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 14:00:05.374438 WARNING: RO_VPD is uninitialized or empty.
9238 14:00:05.380880 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 14:00:05.387720 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 14:00:05.400554 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9241 14:00:05.411891 BS: romstage times (exec / console): total (unknown) / 24008 ms
9242 14:00:05.412465
9243 14:00:05.412840
9244 14:00:05.421916 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 14:00:05.425323 ARM64: Exception handlers installed.
9246 14:00:05.428632 ARM64: Testing exception
9247 14:00:05.431786 ARM64: Done test exception
9248 14:00:05.432360 Enumerating buses...
9249 14:00:05.434980 Show all devs... Before device enumeration.
9250 14:00:05.438456 Root Device: enabled 1
9251 14:00:05.441532 CPU_CLUSTER: 0: enabled 1
9252 14:00:05.442039 CPU: 00: enabled 1
9253 14:00:05.445000 Compare with tree...
9254 14:00:05.445573 Root Device: enabled 1
9255 14:00:05.448020 CPU_CLUSTER: 0: enabled 1
9256 14:00:05.451796 CPU: 00: enabled 1
9257 14:00:05.452375 Root Device scanning...
9258 14:00:05.454603 scan_static_bus for Root Device
9259 14:00:05.458248 CPU_CLUSTER: 0 enabled
9260 14:00:05.461756 scan_static_bus for Root Device done
9261 14:00:05.464719 scan_bus: bus Root Device finished in 8 msecs
9262 14:00:05.465195 done
9263 14:00:05.471896 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 14:00:05.474998 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 14:00:05.481683 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 14:00:05.484724 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 14:00:05.488093 Allocating resources...
9268 14:00:05.491824 Reading resources...
9269 14:00:05.494402 Root Device read_resources bus 0 link: 0
9270 14:00:05.494880 DRAM rank0 size:0x100000000,
9271 14:00:05.497848 DRAM rank1 size=0x100000000
9272 14:00:05.501643 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 14:00:05.504554 CPU: 00 missing read_resources
9274 14:00:05.508124 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 14:00:05.514719 Root Device read_resources bus 0 link: 0 done
9276 14:00:05.515285 Done reading resources.
9277 14:00:05.521356 Show resources in subtree (Root Device)...After reading.
9278 14:00:05.524677 Root Device child on link 0 CPU_CLUSTER: 0
9279 14:00:05.528137 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 14:00:05.537866 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 14:00:05.538485 CPU: 00
9282 14:00:05.541067 Root Device assign_resources, bus 0 link: 0
9283 14:00:05.544446 CPU_CLUSTER: 0 missing set_resources
9284 14:00:05.550735 Root Device assign_resources, bus 0 link: 0 done
9285 14:00:05.551211 Done setting resources.
9286 14:00:05.557566 Show resources in subtree (Root Device)...After assigning values.
9287 14:00:05.560670 Root Device child on link 0 CPU_CLUSTER: 0
9288 14:00:05.564508 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 14:00:05.574346 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 14:00:05.574955 CPU: 00
9291 14:00:05.577628 Done allocating resources.
9292 14:00:05.580868 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 14:00:05.584152 Enabling resources...
9294 14:00:05.584719 done.
9295 14:00:05.590580 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 14:00:05.591140 Initializing devices...
9297 14:00:05.594176 Root Device init
9298 14:00:05.594746 init hardware done!
9299 14:00:05.597490 0x00000018: ctrlr->caps
9300 14:00:05.600930 52.000 MHz: ctrlr->f_max
9301 14:00:05.601511 0.400 MHz: ctrlr->f_min
9302 14:00:05.604068 0x40ff8080: ctrlr->voltages
9303 14:00:05.607388 sclk: 390625
9304 14:00:05.607961 Bus Width = 1
9305 14:00:05.608336 sclk: 390625
9306 14:00:05.610885 Bus Width = 1
9307 14:00:05.611354 Early init status = 3
9308 14:00:05.616870 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 14:00:05.620483 in-header: 03 fc 00 00 01 00 00 00
9310 14:00:05.623564 in-data: 00
9311 14:00:05.626856 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 14:00:05.632480 in-header: 03 fd 00 00 00 00 00 00
9313 14:00:05.635674 in-data:
9314 14:00:05.638947 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 14:00:05.643490 in-header: 03 fc 00 00 01 00 00 00
9316 14:00:05.647196 in-data: 00
9317 14:00:05.650033 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 14:00:05.655914 in-header: 03 fd 00 00 00 00 00 00
9319 14:00:05.658929 in-data:
9320 14:00:05.662115 [SSUSB] Setting up USB HOST controller...
9321 14:00:05.665783 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 14:00:05.669005 [SSUSB] phy power-on done.
9323 14:00:05.672430 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 14:00:05.679084 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 14:00:05.682547 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 14:00:05.688579 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 14:00:05.695767 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9328 14:00:05.702111 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 14:00:05.708807 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 14:00:05.715392 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9331 14:00:05.718517 SPM: binary array size = 0x9dc
9332 14:00:05.722036 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 14:00:05.729032 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 14:00:05.735515 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 14:00:05.738807 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 14:00:05.745418 configure_display: Starting display init
9337 14:00:05.778710 anx7625_power_on_init: Init interface.
9338 14:00:05.782318 anx7625_disable_pd_protocol: Disabled PD feature.
9339 14:00:05.785429 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 14:00:05.813035 anx7625_start_dp_work: Secure OCM version=00
9341 14:00:05.816513 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 14:00:05.831363 sp_tx_get_edid_block: EDID Block = 1
9343 14:00:05.933993 Extracted contents:
9344 14:00:05.937408 header: 00 ff ff ff ff ff ff 00
9345 14:00:05.940704 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 14:00:05.944179 version: 01 04
9347 14:00:05.947495 basic params: 95 1f 11 78 0a
9348 14:00:05.950569 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 14:00:05.954051 established: 00 00 00
9350 14:00:05.960816 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 14:00:05.964034 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 14:00:05.970930 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 14:00:05.977645 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 14:00:05.984001 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 14:00:05.987328 extensions: 00
9356 14:00:05.987798 checksum: fb
9357 14:00:05.988170
9358 14:00:05.990444 Manufacturer: IVO Model 57d Serial Number 0
9359 14:00:05.993594 Made week 0 of 2020
9360 14:00:05.994090 EDID version: 1.4
9361 14:00:05.997111 Digital display
9362 14:00:06.000563 6 bits per primary color channel
9363 14:00:06.001032 DisplayPort interface
9364 14:00:06.003469 Maximum image size: 31 cm x 17 cm
9365 14:00:06.006930 Gamma: 220%
9366 14:00:06.007386 Check DPMS levels
9367 14:00:06.010537 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 14:00:06.013386 First detailed timing is preferred timing
9369 14:00:06.016583 Established timings supported:
9370 14:00:06.020205 Standard timings supported:
9371 14:00:06.023842 Detailed timings
9372 14:00:06.026781 Hex of detail: 383680a07038204018303c0035ae10000019
9373 14:00:06.030125 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 14:00:06.036857 0780 0798 07c8 0820 hborder 0
9375 14:00:06.040383 0438 043b 0447 0458 vborder 0
9376 14:00:06.043238 -hsync -vsync
9377 14:00:06.043717 Did detailed timing
9378 14:00:06.050213 Hex of detail: 000000000000000000000000000000000000
9379 14:00:06.050668 Manufacturer-specified data, tag 0
9380 14:00:06.057183 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 14:00:06.057737 ASCII string: InfoVision
9382 14:00:06.063481 Hex of detail: 000000fe00523134304e574635205248200a
9383 14:00:06.067345 ASCII string: R140NWF5 RH
9384 14:00:06.067898 Checksum
9385 14:00:06.068259 Checksum: 0xfb (valid)
9386 14:00:06.073739 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 14:00:06.076896 DSI data_rate: 832800000 bps
9388 14:00:06.080372 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 14:00:06.086499 anx7625_parse_edid: pixelclock(138800).
9390 14:00:06.089917 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 14:00:06.093368 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 14:00:06.096906 anx7625_dsi_config: config dsi.
9393 14:00:06.102958 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 14:00:06.116044 anx7625_dsi_config: success to config DSI
9395 14:00:06.119475 anx7625_dp_start: MIPI phy setup OK.
9396 14:00:06.122853 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 14:00:06.126013 mtk_ddp_mode_set invalid vrefresh 60
9398 14:00:06.129602 main_disp_path_setup
9399 14:00:06.130197 ovl_layer_smi_id_en
9400 14:00:06.132561 ovl_layer_smi_id_en
9401 14:00:06.133125 ccorr_config
9402 14:00:06.133483 aal_config
9403 14:00:06.136268 gamma_config
9404 14:00:06.136822 postmask_config
9405 14:00:06.139557 dither_config
9406 14:00:06.142750 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 14:00:06.149336 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 14:00:06.152942 Root Device init finished in 555 msecs
9409 14:00:06.156174 CPU_CLUSTER: 0 init
9410 14:00:06.162829 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 14:00:06.166027 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 14:00:06.169317 APU_MBOX 0x190000b0 = 0x10001
9413 14:00:06.172393 APU_MBOX 0x190001b0 = 0x10001
9414 14:00:06.176119 APU_MBOX 0x190005b0 = 0x10001
9415 14:00:06.178957 APU_MBOX 0x190006b0 = 0x10001
9416 14:00:06.182539 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 14:00:06.195123 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9418 14:00:06.207618 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 14:00:06.213906 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 14:00:06.225568 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9421 14:00:06.235331 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 14:00:06.238002 CPU_CLUSTER: 0 init finished in 81 msecs
9423 14:00:06.241403 Devices initialized
9424 14:00:06.245109 Show all devs... After init.
9425 14:00:06.245697 Root Device: enabled 1
9426 14:00:06.248319 CPU_CLUSTER: 0: enabled 1
9427 14:00:06.251455 CPU: 00: enabled 1
9428 14:00:06.254593 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9429 14:00:06.258061 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 14:00:06.261433 ELOG: NV offset 0x57f000 size 0x1000
9431 14:00:06.267634 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9432 14:00:06.274859 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 14:00:06.277977 ELOG: Event(17) added with size 13 at 2024-02-01 13:59:26 UTC
9434 14:00:06.281257 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 14:00:06.285026 in-header: 03 27 00 00 2c 00 00 00
9436 14:00:06.298703 in-data: 38 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 14:00:06.305005 ELOG: Event(A1) added with size 10 at 2024-02-01 13:59:26 UTC
9438 14:00:06.311467 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9439 14:00:06.317870 ELOG: Event(A0) added with size 9 at 2024-02-01 13:59:26 UTC
9440 14:00:06.321705 elog_add_boot_reason: Logged dev mode boot
9441 14:00:06.324905 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9442 14:00:06.328372 Finalize devices...
9443 14:00:06.328951 Devices finalized
9444 14:00:06.334545 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 14:00:06.338117 Writing coreboot table at 0xffe64000
9446 14:00:06.341165 0. 000000000010a000-0000000000113fff: RAMSTAGE
9447 14:00:06.344944 1. 0000000040000000-00000000400fffff: RAM
9448 14:00:06.351336 2. 0000000040100000-000000004032afff: RAMSTAGE
9449 14:00:06.354498 3. 000000004032b000-00000000545fffff: RAM
9450 14:00:06.358340 4. 0000000054600000-000000005465ffff: BL31
9451 14:00:06.361554 5. 0000000054660000-00000000ffe63fff: RAM
9452 14:00:06.368109 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9453 14:00:06.371642 7. 0000000100000000-000000023fffffff: RAM
9454 14:00:06.372224 Passing 5 GPIOs to payload:
9455 14:00:06.378358 NAME | PORT | POLARITY | VALUE
9456 14:00:06.381760 EC in RW | 0x000000aa | low | undefined
9457 14:00:06.388198 EC interrupt | 0x00000005 | low | undefined
9458 14:00:06.391266 TPM interrupt | 0x000000ab | high | undefined
9459 14:00:06.394724 SD card detect | 0x00000011 | high | undefined
9460 14:00:06.401154 speaker enable | 0x00000093 | high | undefined
9461 14:00:06.404450 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9462 14:00:06.407875 in-header: 03 f9 00 00 02 00 00 00
9463 14:00:06.408501 in-data: 02 00
9464 14:00:06.410790 ADC[4]: Raw value=901032 ID=7
9465 14:00:06.414510 ADC[3]: Raw value=212810 ID=1
9466 14:00:06.415102 RAM Code: 0x71
9467 14:00:06.417894 ADC[6]: Raw value=74502 ID=0
9468 14:00:06.421069 ADC[5]: Raw value=212441 ID=1
9469 14:00:06.421560 SKU Code: 0x1
9470 14:00:06.427650 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4f3d
9471 14:00:06.431162 coreboot table: 964 bytes.
9472 14:00:06.434534 IMD ROOT 0. 0xfffff000 0x00001000
9473 14:00:06.437303 IMD SMALL 1. 0xffffe000 0x00001000
9474 14:00:06.441043 RO MCACHE 2. 0xffffc000 0x00001104
9475 14:00:06.443902 CONSOLE 3. 0xfff7c000 0x00080000
9476 14:00:06.447219 FMAP 4. 0xfff7b000 0x00000452
9477 14:00:06.450507 TIME STAMP 5. 0xfff7a000 0x00000910
9478 14:00:06.454097 VBOOT WORK 6. 0xfff66000 0x00014000
9479 14:00:06.457662 RAMOOPS 7. 0xffe66000 0x00100000
9480 14:00:06.460900 COREBOOT 8. 0xffe64000 0x00002000
9481 14:00:06.461370 IMD small region:
9482 14:00:06.463960 IMD ROOT 0. 0xffffec00 0x00000400
9483 14:00:06.467556 VPD 1. 0xffffeb80 0x0000006c
9484 14:00:06.470722 MMC STATUS 2. 0xffffeb60 0x00000004
9485 14:00:06.478107 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9486 14:00:06.480944 Probing TPM: done!
9487 14:00:06.484244 Connected to device vid:did:rid of 1ae0:0028:00
9488 14:00:06.494110 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9489 14:00:06.497496 Initialized TPM device CR50 revision 0
9490 14:00:06.501672 Checking cr50 for pending updates
9491 14:00:06.504883 Reading cr50 TPM mode
9492 14:00:06.513360 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9493 14:00:06.519448 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 14:00:06.559932 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9495 14:00:06.563303 Checking segment from ROM address 0x40100000
9496 14:00:06.566188 Checking segment from ROM address 0x4010001c
9497 14:00:06.573434 Loading segment from ROM address 0x40100000
9498 14:00:06.574030 code (compression=0)
9499 14:00:06.583084 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 14:00:06.590077 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 14:00:06.590649 it's not compressed!
9502 14:00:06.596399 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 14:00:06.600025 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 14:00:06.620269 Loading segment from ROM address 0x4010001c
9505 14:00:06.620892 Entry Point 0x80000000
9506 14:00:06.623308 Loaded segments
9507 14:00:06.627296 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 14:00:06.634048 Jumping to boot code at 0x80000000(0xffe64000)
9509 14:00:06.640581 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 14:00:06.646641 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 14:00:06.654690 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9512 14:00:06.658177 Checking segment from ROM address 0x40100000
9513 14:00:06.661454 Checking segment from ROM address 0x4010001c
9514 14:00:06.668010 Loading segment from ROM address 0x40100000
9515 14:00:06.668594 code (compression=1)
9516 14:00:06.674579 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 14:00:06.684632 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 14:00:06.685218 using LZMA
9519 14:00:06.693135 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 14:00:06.700063 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 14:00:06.703154 Loading segment from ROM address 0x4010001c
9522 14:00:06.703629 Entry Point 0x54601000
9523 14:00:06.706458 Loaded segments
9524 14:00:06.709804 NOTICE: MT8192 bl31_setup
9525 14:00:06.716800 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 14:00:06.719936 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 14:00:06.723466 WARNING: region 0:
9528 14:00:06.726801 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 14:00:06.727384 WARNING: region 1:
9530 14:00:06.733519 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 14:00:06.737049 WARNING: region 2:
9532 14:00:06.740388 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 14:00:06.743216 WARNING: region 3:
9534 14:00:06.746801 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 14:00:06.749869 WARNING: region 4:
9536 14:00:06.753329 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 14:00:06.757051 WARNING: region 5:
9538 14:00:06.760429 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 14:00:06.763851 WARNING: region 6:
9540 14:00:06.766845 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 14:00:06.767321 WARNING: region 7:
9542 14:00:06.773438 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 14:00:06.780558 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 14:00:06.783908 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 14:00:06.787099 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 14:00:06.793285 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 14:00:06.796612 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 14:00:06.800238 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 14:00:06.807228 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 14:00:06.810449 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 14:00:06.813434 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 14:00:06.820308 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 14:00:06.823717 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 14:00:06.826647 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 14:00:06.833749 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 14:00:06.837356 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 14:00:06.843890 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 14:00:06.847059 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 14:00:06.850479 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 14:00:06.856674 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 14:00:06.860299 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 14:00:06.863461 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 14:00:06.870410 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 14:00:06.873747 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 14:00:06.880368 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 14:00:06.883383 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 14:00:06.886744 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 14:00:06.893658 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 14:00:06.896902 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 14:00:06.904149 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 14:00:06.907262 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 14:00:06.910585 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 14:00:06.917668 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 14:00:06.920584 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 14:00:06.923913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 14:00:06.930736 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 14:00:06.934261 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 14:00:06.937330 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 14:00:06.940804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 14:00:06.947282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 14:00:06.950820 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 14:00:06.953884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 14:00:06.957050 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 14:00:06.964081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 14:00:06.967111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 14:00:06.970318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 14:00:06.973919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 14:00:06.980675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 14:00:06.983743 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 14:00:06.987403 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 14:00:06.993797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 14:00:06.997073 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 14:00:07.000561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 14:00:07.007072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 14:00:07.010839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 14:00:07.016991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 14:00:07.020237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 14:00:07.026907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 14:00:07.030516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 14:00:07.034258 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 14:00:07.040939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 14:00:07.044018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 14:00:07.050457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 14:00:07.053685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 14:00:07.060580 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 14:00:07.064143 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 14:00:07.067226 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 14:00:07.073829 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 14:00:07.077181 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 14:00:07.083853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 14:00:07.087048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 14:00:07.093355 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 14:00:07.096994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 14:00:07.100462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 14:00:07.107075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 14:00:07.110436 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 14:00:07.117134 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 14:00:07.120663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 14:00:07.127073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 14:00:07.130994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 14:00:07.136918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 14:00:07.140861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 14:00:07.144207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 14:00:07.150441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 14:00:07.153655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 14:00:07.160522 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 14:00:07.163891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 14:00:07.166823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 14:00:07.174095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 14:00:07.177389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 14:00:07.183904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 14:00:07.187208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 14:00:07.193651 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 14:00:07.197282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 14:00:07.200490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 14:00:07.207410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 14:00:07.210573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 14:00:07.217429 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 14:00:07.220460 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 14:00:07.224244 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 14:00:07.230751 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 14:00:07.233937 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 14:00:07.237164 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 14:00:07.244098 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 14:00:07.247069 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 14:00:07.250642 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 14:00:07.256878 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 14:00:07.260333 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 14:00:07.266735 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 14:00:07.270068 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 14:00:07.273707 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 14:00:07.280015 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 14:00:07.283016 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 14:00:07.290441 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 14:00:07.293357 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 14:00:07.296900 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 14:00:07.303323 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 14:00:07.306467 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 14:00:07.310091 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 14:00:07.316672 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 14:00:07.319834 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 14:00:07.323560 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 14:00:07.329716 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 14:00:07.333325 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 14:00:07.336601 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 14:00:07.339887 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 14:00:07.346758 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 14:00:07.349662 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 14:00:07.353408 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 14:00:07.359650 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 14:00:07.363225 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 14:00:07.370347 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 14:00:07.373262 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 14:00:07.376832 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 14:00:07.383258 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 14:00:07.386718 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 14:00:07.393141 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 14:00:07.396967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 14:00:07.399815 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 14:00:07.406691 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 14:00:07.409921 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 14:00:07.413219 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 14:00:07.419859 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 14:00:07.422972 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 14:00:07.429935 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 14:00:07.433585 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 14:00:07.436539 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 14:00:07.443476 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 14:00:07.446640 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 14:00:07.449997 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 14:00:07.457069 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 14:00:07.460340 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 14:00:07.467071 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 14:00:07.470345 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 14:00:07.473005 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 14:00:07.480179 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 14:00:07.483830 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 14:00:07.490233 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 14:00:07.494040 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 14:00:07.496862 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 14:00:07.503842 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 14:00:07.507154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 14:00:07.509914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 14:00:07.516469 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 14:00:07.520056 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 14:00:07.526714 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 14:00:07.530075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 14:00:07.533235 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 14:00:07.540242 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 14:00:07.543341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 14:00:07.550002 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 14:00:07.553055 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 14:00:07.557062 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 14:00:07.563028 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 14:00:07.566518 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 14:00:07.573368 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 14:00:07.576724 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 14:00:07.580168 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 14:00:07.586756 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 14:00:07.590133 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 14:00:07.596637 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 14:00:07.599892 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 14:00:07.603143 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 14:00:07.609657 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 14:00:07.613545 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 14:00:07.616173 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 14:00:07.622662 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 14:00:07.626144 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 14:00:07.633269 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 14:00:07.636579 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 14:00:07.639580 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 14:00:07.646143 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 14:00:07.649670 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 14:00:07.656534 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 14:00:07.659827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 14:00:07.666344 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 14:00:07.669503 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 14:00:07.672741 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 14:00:07.679742 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 14:00:07.682626 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 14:00:07.689632 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 14:00:07.692894 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 14:00:07.696077 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 14:00:07.702738 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 14:00:07.705814 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 14:00:07.712540 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 14:00:07.715622 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 14:00:07.722893 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 14:00:07.726159 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 14:00:07.728912 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 14:00:07.735736 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 14:00:07.738842 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 14:00:07.745588 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 14:00:07.749124 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 14:00:07.755239 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 14:00:07.758774 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 14:00:07.762230 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 14:00:07.768938 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 14:00:07.771903 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 14:00:07.778437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 14:00:07.782637 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 14:00:07.785476 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 14:00:07.792342 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 14:00:07.795194 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 14:00:07.801815 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 14:00:07.805328 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 14:00:07.811814 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 14:00:07.815139 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 14:00:07.818835 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 14:00:07.825108 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 14:00:07.828046 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 14:00:07.831834 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 14:00:07.838188 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 14:00:07.841658 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 14:00:07.844930 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 14:00:07.848466 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 14:00:07.854562 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 14:00:07.858008 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 14:00:07.864981 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 14:00:07.868069 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 14:00:07.871575 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 14:00:07.878034 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 14:00:07.881621 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 14:00:07.884535 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 14:00:07.891172 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 14:00:07.894522 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 14:00:07.898020 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 14:00:07.904427 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 14:00:07.908490 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 14:00:07.914788 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 14:00:07.918023 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 14:00:07.921478 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 14:00:07.927926 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 14:00:07.930993 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 14:00:07.934591 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 14:00:07.941436 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 14:00:07.944650 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 14:00:07.947553 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 14:00:07.954211 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 14:00:07.957768 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 14:00:07.961016 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 14:00:07.967800 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 14:00:07.971017 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 14:00:07.977818 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 14:00:07.980788 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 14:00:07.984465 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 14:00:07.991032 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 14:00:07.994321 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 14:00:08.001035 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 14:00:08.003920 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 14:00:08.007616 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 14:00:08.010830 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 14:00:08.017547 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 14:00:08.020739 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 14:00:08.023807 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 14:00:08.027149 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 14:00:08.034079 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 14:00:08.037284 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 14:00:08.040559 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 14:00:08.044043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 14:00:08.050572 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 14:00:08.053734 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 14:00:08.057377 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 14:00:08.060788 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 14:00:08.066793 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 14:00:08.070551 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 14:00:08.077106 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 14:00:08.080558 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 14:00:08.086749 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 14:00:08.090317 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 14:00:08.093840 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 14:00:08.100194 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 14:00:08.103515 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 14:00:08.110199 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 14:00:08.113818 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 14:00:08.116672 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 14:00:08.123744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 14:00:08.126870 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 14:00:08.133731 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 14:00:08.136957 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 14:00:08.140198 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 14:00:08.146824 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 14:00:08.150242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 14:00:08.157037 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 14:00:08.160212 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 14:00:08.163438 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 14:00:08.169751 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 14:00:08.173641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 14:00:08.180140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 14:00:08.183649 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 14:00:08.190056 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 14:00:08.192807 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 14:00:08.196083 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 14:00:08.203101 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 14:00:08.206357 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 14:00:08.213161 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 14:00:08.216271 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 14:00:08.219260 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 14:00:08.226309 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 14:00:08.229541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 14:00:08.236362 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 14:00:08.239592 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 14:00:08.246096 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 14:00:08.249420 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 14:00:08.252592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 14:00:08.259787 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 14:00:08.262999 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 14:00:08.266129 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 14:00:08.272836 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 14:00:08.276181 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 14:00:08.282779 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 14:00:08.285741 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 14:00:08.289430 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 14:00:08.296067 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 14:00:08.299244 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 14:00:08.305882 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 14:00:08.309209 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 14:00:08.316003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 14:00:08.319204 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 14:00:08.322796 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 14:00:08.329475 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 14:00:08.332322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 14:00:08.339164 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 14:00:08.342398 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 14:00:08.346100 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 14:00:08.352310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 14:00:08.355615 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 14:00:08.362274 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 14:00:08.365746 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 14:00:08.368654 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 14:00:08.375856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 14:00:08.378432 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 14:00:08.385261 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 14:00:08.388934 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 14:00:08.395143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 14:00:08.398498 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 14:00:08.401884 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 14:00:08.408726 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 14:00:08.412019 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 14:00:08.418462 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 14:00:08.421928 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 14:00:08.428788 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 14:00:08.432102 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 14:00:08.435315 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 14:00:08.442077 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 14:00:08.444947 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 14:00:08.451735 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 14:00:08.454699 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 14:00:08.461390 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 14:00:08.464952 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 14:00:08.471371 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 14:00:08.474936 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 14:00:08.478173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 14:00:08.484730 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 14:00:08.488100 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 14:00:08.494702 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 14:00:08.497999 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 14:00:08.504573 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 14:00:08.507653 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 14:00:08.511059 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 14:00:08.517593 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 14:00:08.521202 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 14:00:08.527913 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 14:00:08.530904 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 14:00:08.537851 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 14:00:08.541236 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 14:00:08.547926 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 14:00:08.551293 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 14:00:08.554363 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 14:00:08.560934 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 14:00:08.564734 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 14:00:08.570732 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 14:00:08.574460 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 14:00:08.580844 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 14:00:08.584075 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 14:00:08.587356 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 14:00:08.593976 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 14:00:08.597241 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 14:00:08.603746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 14:00:08.607182 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 14:00:08.613653 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 14:00:08.617116 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 14:00:08.623619 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 14:00:08.626821 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 14:00:08.630615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 14:00:08.637466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 14:00:08.640346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 14:00:08.647417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 14:00:08.650726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 14:00:08.656778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 14:00:08.660576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 14:00:08.666853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 14:00:08.670474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 14:00:08.673805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 14:00:08.680378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 14:00:08.683675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 14:00:08.690284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 14:00:08.693573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 14:00:08.699971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 14:00:08.703476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 14:00:08.710373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 14:00:08.713741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 14:00:08.720263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 14:00:08.723543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 14:00:08.730495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 14:00:08.733172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 14:00:08.739692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 14:00:08.743055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 14:00:08.749872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 14:00:08.753105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 14:00:08.760222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 14:00:08.763399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 14:00:08.769445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 14:00:08.773024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 14:00:08.779850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 14:00:08.783229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 14:00:08.789680 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 14:00:08.790308 INFO: [APUAPC] vio 0
9979 14:00:08.796853 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 14:00:08.799950 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 14:00:08.803517 INFO: [APUAPC] D0_APC_0: 0x400510
9982 14:00:08.806681 INFO: [APUAPC] D0_APC_1: 0x0
9983 14:00:08.809642 INFO: [APUAPC] D0_APC_2: 0x1540
9984 14:00:08.813075 INFO: [APUAPC] D0_APC_3: 0x0
9985 14:00:08.816543 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 14:00:08.819728 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 14:00:08.823445 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 14:00:08.826306 INFO: [APUAPC] D1_APC_3: 0x0
9989 14:00:08.830372 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 14:00:08.832828 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 14:00:08.836416 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 14:00:08.839656 INFO: [APUAPC] D2_APC_3: 0x0
9993 14:00:08.843030 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 14:00:08.846435 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 14:00:08.849441 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 14:00:08.852889 INFO: [APUAPC] D3_APC_3: 0x0
9997 14:00:08.856118 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 14:00:08.859837 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 14:00:08.862879 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 14:00:08.863452 INFO: [APUAPC] D4_APC_3: 0x0
10001 14:00:08.866315 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 14:00:08.869995 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 14:00:08.873067 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 14:00:08.876694 INFO: [APUAPC] D5_APC_3: 0x0
10005 14:00:08.879255 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 14:00:08.882961 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 14:00:08.886338 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 14:00:08.889694 INFO: [APUAPC] D6_APC_3: 0x0
10009 14:00:08.893047 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 14:00:08.896108 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 14:00:08.899651 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 14:00:08.902705 INFO: [APUAPC] D7_APC_3: 0x0
10013 14:00:08.906205 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 14:00:08.909608 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 14:00:08.912745 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 14:00:08.916151 INFO: [APUAPC] D8_APC_3: 0x0
10017 14:00:08.919325 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 14:00:08.922650 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 14:00:08.925679 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 14:00:08.929614 INFO: [APUAPC] D9_APC_3: 0x0
10021 14:00:08.932578 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 14:00:08.935922 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 14:00:08.939318 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 14:00:08.942440 INFO: [APUAPC] D10_APC_3: 0x0
10025 14:00:08.946531 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 14:00:08.949370 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 14:00:08.952485 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 14:00:08.955597 INFO: [APUAPC] D11_APC_3: 0x0
10029 14:00:08.958872 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 14:00:08.962443 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 14:00:08.965881 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 14:00:08.969091 INFO: [APUAPC] D12_APC_3: 0x0
10033 14:00:08.972866 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 14:00:08.976061 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 14:00:08.979245 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 14:00:08.982601 INFO: [APUAPC] D13_APC_3: 0x0
10037 14:00:08.985841 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 14:00:08.989055 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 14:00:08.992847 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 14:00:08.996014 INFO: [APUAPC] D14_APC_3: 0x0
10041 14:00:08.998853 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 14:00:09.002494 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 14:00:09.005799 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 14:00:09.008769 INFO: [APUAPC] D15_APC_3: 0x0
10045 14:00:09.012275 INFO: [APUAPC] APC_CON: 0x4
10046 14:00:09.015178 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 14:00:09.018938 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 14:00:09.021779 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 14:00:09.025435 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 14:00:09.026051 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 14:00:09.028987 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 14:00:09.032766 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 14:00:09.035700 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 14:00:09.038837 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 14:00:09.042302 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 14:00:09.045723 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 14:00:09.049072 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 14:00:09.052407 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 14:00:09.055327 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 14:00:09.058676 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 14:00:09.059153 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 14:00:09.062107 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 14:00:09.065285 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 14:00:09.068633 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 14:00:09.071782 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 14:00:09.075043 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 14:00:09.079103 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 14:00:09.082518 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 14:00:09.085504 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 14:00:09.088823 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 14:00:09.092202 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 14:00:09.095434 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 14:00:09.098589 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 14:00:09.099169 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 14:00:09.102167 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 14:00:09.105497 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 14:00:09.108850 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 14:00:09.111738 INFO: [NOCDAPC] APC_CON: 0x4
10079 14:00:09.115364 INFO: [APUAPC] set_apusys_apc done
10080 14:00:09.118539 INFO: [DEVAPC] devapc_init done
10081 14:00:09.122063 INFO: GICv3 without legacy support detected.
10082 14:00:09.128601 INFO: ARM GICv3 driver initialized in EL3
10083 14:00:09.131949 INFO: Maximum SPI INTID supported: 639
10084 14:00:09.135406 INFO: BL31: Initializing runtime services
10085 14:00:09.141850 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 14:00:09.142472 INFO: SPM: enable CPC mode
10087 14:00:09.148623 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 14:00:09.151812 INFO: BL31: Preparing for EL3 exit to normal world
10089 14:00:09.158286 INFO: Entry point address = 0x80000000
10090 14:00:09.158919 INFO: SPSR = 0x8
10091 14:00:09.164655
10092 14:00:09.165226
10093 14:00:09.165603
10094 14:00:09.167925 Starting depthcharge on Spherion...
10095 14:00:09.168396
10096 14:00:09.168764 Wipe memory regions:
10097 14:00:09.169114
10098 14:00:09.171587 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10099 14:00:09.172151 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10100 14:00:09.172611 Setting prompt string to ['asurada:']
10101 14:00:09.173048 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10102 14:00:09.173778 [0x00000040000000, 0x00000054600000)
10103 14:00:09.292848
10104 14:00:09.293035 [0x00000054660000, 0x00000080000000)
10105 14:00:09.554465
10106 14:00:09.555050 [0x000000821a7280, 0x000000ffe64000)
10107 14:00:10.299152
10108 14:00:10.299732 [0x00000100000000, 0x00000240000000)
10109 14:00:12.189256
10110 14:00:12.192355 Initializing XHCI USB controller at 0x11200000.
10111 14:00:13.230162
10112 14:00:13.234015 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10113 14:00:13.234528
10114 14:00:13.234875
10115 14:00:13.235177
10116 14:00:13.235935 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 14:00:13.337187 asurada: tftpboot 192.168.201.1 12682968/tftp-deploy-k9n83o5t/kernel/image.itb 12682968/tftp-deploy-k9n83o5t/kernel/cmdline
10119 14:00:13.337852 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 14:00:13.338425 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10121 14:00:13.342813 tftpboot 192.168.201.1 12682968/tftp-deploy-k9n83o5t/kernel/image.itbtp-deploy-k9n83o5t/kernel/cmdline
10122 14:00:13.343295
10123 14:00:13.343670 Waiting for link
10124 14:00:13.503545
10125 14:00:13.504118 R8152: Initializing
10126 14:00:13.504500
10127 14:00:13.506555 Version 9 (ocp_data = 6010)
10128 14:00:13.507032
10129 14:00:13.509511 R8152: Done initializing
10130 14:00:13.510000
10131 14:00:13.510382 Adding net device
10132 14:00:15.378678
10133 14:00:15.379345 done.
10134 14:00:15.380120
10135 14:00:15.380837 MAC: 00:e0:4c:72:2d:d6
10136 14:00:15.381232
10137 14:00:15.381907 Sending DHCP discover... done.
10138 14:00:15.382323
10139 14:00:15.385677 Waiting for reply... done.
10140 14:00:15.386191
10141 14:00:15.388700 Sending DHCP request... done.
10142 14:00:15.389276
10143 14:00:15.389657 Waiting for reply... done.
10144 14:00:15.390060
10145 14:00:15.391737 My ip is 192.168.201.21
10146 14:00:15.392354
10147 14:00:15.394854 The DHCP server ip is 192.168.201.1
10148 14:00:15.395333
10149 14:00:15.397918 TFTP server IP predefined by user: 192.168.201.1
10150 14:00:15.398447
10151 14:00:15.404903 Bootfile predefined by user: 12682968/tftp-deploy-k9n83o5t/kernel/image.itb
10152 14:00:15.405478
10153 14:00:15.408652 Sending tftp read request... done.
10154 14:00:15.409250
10155 14:00:15.415300 Waiting for the transfer...
10156 14:00:15.415773
10157 14:00:15.713628 00000000 ################################################################
10158 14:00:15.713769
10159 14:00:15.996233 00080000 ################################################################
10160 14:00:15.996375
10161 14:00:16.282610 00100000 ################################################################
10162 14:00:16.282759
10163 14:00:16.582111 00180000 ################################################################
10164 14:00:16.582260
10165 14:00:16.882030 00200000 ################################################################
10166 14:00:16.882176
10167 14:00:17.176800 00280000 ################################################################
10168 14:00:17.176950
10169 14:00:17.454699 00300000 ################################################################
10170 14:00:17.454851
10171 14:00:17.743182 00380000 ################################################################
10172 14:00:17.743335
10173 14:00:18.065320 00400000 ################################################################
10174 14:00:18.065464
10175 14:00:18.347652 00480000 ################################################################
10176 14:00:18.347806
10177 14:00:18.596299 00500000 ################################################################
10178 14:00:18.596436
10179 14:00:18.846168 00580000 ################################################################
10180 14:00:18.846307
10181 14:00:19.094202 00600000 ################################################################
10182 14:00:19.094355
10183 14:00:19.348332 00680000 ################################################################
10184 14:00:19.348478
10185 14:00:19.602002 00700000 ################################################################
10186 14:00:19.602141
10187 14:00:19.859399 00780000 ################################################################
10188 14:00:19.859541
10189 14:00:20.149156 00800000 ################################################################
10190 14:00:20.149300
10191 14:00:20.432216 00880000 ################################################################
10192 14:00:20.432373
10193 14:00:20.692169 00900000 ################################################################
10194 14:00:20.692334
10195 14:00:20.951284 00980000 ################################################################
10196 14:00:20.951420
10197 14:00:21.248145 00a00000 ################################################################
10198 14:00:21.248307
10199 14:00:21.533496 00a80000 ################################################################
10200 14:00:21.533673
10201 14:00:21.793020 00b00000 ################################################################
10202 14:00:21.793209
10203 14:00:22.040667 00b80000 ################################################################
10204 14:00:22.040799
10205 14:00:22.305419 00c00000 ################################################################
10206 14:00:22.305558
10207 14:00:22.598983 00c80000 ################################################################
10208 14:00:22.599145
10209 14:00:22.884348 00d00000 ################################################################
10210 14:00:22.884489
10211 14:00:23.182882 00d80000 ################################################################
10212 14:00:23.183024
10213 14:00:23.473764 00e00000 ################################################################
10214 14:00:23.473946
10215 14:00:23.765432 00e80000 ################################################################
10216 14:00:23.765573
10217 14:00:24.037510 00f00000 ################################################################
10218 14:00:24.037651
10219 14:00:24.293933 00f80000 ################################################################
10220 14:00:24.294103
10221 14:00:24.541524 01000000 ################################################################
10222 14:00:24.541679
10223 14:00:24.798471 01080000 ################################################################
10224 14:00:24.798598
10225 14:00:25.055119 01100000 ################################################################
10226 14:00:25.055262
10227 14:00:25.303408 01180000 ################################################################
10228 14:00:25.303544
10229 14:00:25.560454 01200000 ################################################################
10230 14:00:25.560607
10231 14:00:25.809215 01280000 ################################################################
10232 14:00:25.809348
10233 14:00:26.058773 01300000 ################################################################
10234 14:00:26.058914
10235 14:00:26.313447 01380000 ################################################################
10236 14:00:26.313591
10237 14:00:26.586489 01400000 ################################################################
10238 14:00:26.586635
10239 14:00:26.837965 01480000 ################################################################
10240 14:00:26.838102
10241 14:00:27.104998 01500000 ################################################################
10242 14:00:27.105135
10243 14:00:27.370098 01580000 ################################################################
10244 14:00:27.370240
10245 14:00:27.657907 01600000 ################################################################
10246 14:00:27.658085
10247 14:00:27.956967 01680000 ################################################################
10248 14:00:27.957117
10249 14:00:28.256001 01700000 ################################################################
10250 14:00:28.256145
10251 14:00:28.552931 01780000 ################################################################
10252 14:00:28.553078
10253 14:00:28.848392 01800000 ################################################################
10254 14:00:28.848538
10255 14:00:29.146637 01880000 ################################################################
10256 14:00:29.146778
10257 14:00:29.434792 01900000 ################################################################
10258 14:00:29.434965
10259 14:00:29.718817 01980000 ################################################################
10260 14:00:29.718973
10261 14:00:30.017483 01a00000 ################################################################
10262 14:00:30.017633
10263 14:00:30.316756 01a80000 ################################################################
10264 14:00:30.316904
10265 14:00:30.684668 01b00000 ################################################################
10266 14:00:30.684840
10267 14:00:30.975305 01b80000 ################################################################
10268 14:00:30.975450
10269 14:00:31.273182 01c00000 ################################################################
10270 14:00:31.273353
10271 14:00:31.283535 01c80000 ### done.
10272 14:00:31.283618
10273 14:00:31.286673 The bootfile was 29902258 bytes long.
10274 14:00:31.286759
10275 14:00:31.290486 Sending tftp read request... done.
10276 14:00:31.290571
10277 14:00:31.293318 Waiting for the transfer...
10278 14:00:31.293408
10279 14:00:31.293480 00000000 # done.
10280 14:00:31.293549
10281 14:00:31.303572 Command line loaded dynamically from TFTP file: 12682968/tftp-deploy-k9n83o5t/kernel/cmdline
10282 14:00:31.303678
10283 14:00:31.323644 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682968/extract-nfsrootfs-oglozrbb,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10284 14:00:31.323891
10285 14:00:31.324024 Loading FIT.
10286 14:00:31.326713
10287 14:00:31.326903 Image ramdisk-1 has 17806087 bytes.
10288 14:00:31.327045
10289 14:00:31.330211 Image fdt-1 has 47278 bytes.
10290 14:00:31.330387
10291 14:00:31.333403 Image kernel-1 has 12046857 bytes.
10292 14:00:31.333717
10293 14:00:31.343467 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10294 14:00:31.343867
10295 14:00:31.360593 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10296 14:00:31.361189
10297 14:00:31.367169 Choosing best match conf-1 for compat google,spherion-rev2.
10298 14:00:31.367697
10299 14:00:31.374964 Connected to device vid:did:rid of 1ae0:0028:00
10300 14:00:31.382814
10301 14:00:31.386216 tpm_get_response: command 0x17b, return code 0x0
10302 14:00:31.386693
10303 14:00:31.389728 ec_init: CrosEC protocol v3 supported (256, 248)
10304 14:00:31.393476
10305 14:00:31.397138 tpm_cleanup: add release locality here.
10306 14:00:31.397724
10307 14:00:31.398190 Shutting down all USB controllers.
10308 14:00:31.400133
10309 14:00:31.400602 Removing current net device
10310 14:00:31.400973
10311 14:00:31.406495 Exiting depthcharge with code 4 at timestamp: 51550849
10312 14:00:31.406969
10313 14:00:31.409737 LZMA decompressing kernel-1 to 0x821a6718
10314 14:00:31.410250
10315 14:00:31.413046 LZMA decompressing kernel-1 to 0x40000000
10316 14:00:32.914060
10317 14:00:32.914626 jumping to kernel
10318 14:00:32.916322 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10319 14:00:32.916847 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10320 14:00:32.917261 Setting prompt string to ['Linux version [0-9]']
10321 14:00:32.917663 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10322 14:00:32.918092 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10323 14:00:32.995772
10324 14:00:32.999172 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10325 14:00:33.002544 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10326 14:00:33.003049 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10327 14:00:33.003451 Setting prompt string to []
10328 14:00:33.003868 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10329 14:00:33.004263 Using line separator: #'\n'#
10330 14:00:33.004606 No login prompt set.
10331 14:00:33.004954 Parsing kernel messages
10332 14:00:33.005298 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10333 14:00:33.005900 [login-action] Waiting for messages, (timeout 00:04:01)
10334 14:00:33.021820 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10335 14:00:33.025569 [ 0.000000] random: crng init done
10336 14:00:33.031775 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10337 14:00:33.034806 [ 0.000000] efi: UEFI not found.
10338 14:00:33.041571 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10339 14:00:33.051345 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10340 14:00:33.058604 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10341 14:00:33.068554 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10342 14:00:33.075089 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10343 14:00:33.081710 [ 0.000000] printk: bootconsole [mtk8250] enabled
10344 14:00:33.088717 [ 0.000000] NUMA: No NUMA configuration found
10345 14:00:33.094957 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10346 14:00:33.098266 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10347 14:00:33.101450 [ 0.000000] Zone ranges:
10348 14:00:33.108071 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10349 14:00:33.111947 [ 0.000000] DMA32 empty
10350 14:00:33.118104 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10351 14:00:33.121374 [ 0.000000] Movable zone start for each node
10352 14:00:33.124698 [ 0.000000] Early memory node ranges
10353 14:00:33.131290 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10354 14:00:33.137835 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10355 14:00:33.144626 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10356 14:00:33.151350 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10357 14:00:33.158508 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10358 14:00:33.164317 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10359 14:00:33.220585 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10360 14:00:33.227282 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10361 14:00:33.234032 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10362 14:00:33.237142 [ 0.000000] psci: probing for conduit method from DT.
10363 14:00:33.243744 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10364 14:00:33.246941 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10365 14:00:33.253705 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10366 14:00:33.256772 [ 0.000000] psci: SMC Calling Convention v1.2
10367 14:00:33.263582 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10368 14:00:33.267040 [ 0.000000] Detected VIPT I-cache on CPU0
10369 14:00:33.273649 [ 0.000000] CPU features: detected: GIC system register CPU interface
10370 14:00:33.280045 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10371 14:00:33.286633 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10372 14:00:33.293383 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10373 14:00:33.300530 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10374 14:00:33.307013 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10375 14:00:33.313857 [ 0.000000] alternatives: applying boot alternatives
10376 14:00:33.317345 [ 0.000000] Fallback order for Node 0: 0
10377 14:00:33.323517 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10378 14:00:33.326734 [ 0.000000] Policy zone: Normal
10379 14:00:33.350072 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682968/extract-nfsrootfs-oglozrbb,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10380 14:00:33.363290 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10381 14:00:33.373042 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10382 14:00:33.383191 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 14:00:33.389578 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10384 14:00:33.393212 <6>[ 0.000000] software IO TLB: area num 8.
10385 14:00:33.449163 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10386 14:00:33.598469 <6>[ 0.000000] Memory: 7949864K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402904K reserved, 32768K cma-reserved)
10387 14:00:33.605163 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10388 14:00:33.611299 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10389 14:00:33.614788 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10390 14:00:33.621757 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10391 14:00:33.628371 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10392 14:00:33.631516 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10393 14:00:33.641385 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10394 14:00:33.647824 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10395 14:00:33.651240 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10396 14:00:33.659315 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10397 14:00:33.662509 <6>[ 0.000000] GICv3: 608 SPIs implemented
10398 14:00:33.669150 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10399 14:00:33.672069 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10400 14:00:33.675554 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10401 14:00:33.685468 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10402 14:00:33.695490 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10403 14:00:33.708827 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10404 14:00:33.715111 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10405 14:00:33.724726 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10406 14:00:33.738137 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10407 14:00:33.744644 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10408 14:00:33.751600 <6>[ 0.009237] Console: colour dummy device 80x25
10409 14:00:33.760933 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10410 14:00:33.767515 <6>[ 0.024404] pid_max: default: 32768 minimum: 301
10411 14:00:33.771105 <6>[ 0.029307] LSM: Security Framework initializing
10412 14:00:33.777713 <6>[ 0.034274] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 14:00:33.788259 <6>[ 0.042088] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 14:00:33.794341 <6>[ 0.051554] cblist_init_generic: Setting adjustable number of callback queues.
10415 14:00:33.801171 <6>[ 0.058996] cblist_init_generic: Setting shift to 3 and lim to 1.
10416 14:00:33.811134 <6>[ 0.065335] cblist_init_generic: Setting adjustable number of callback queues.
10417 14:00:33.817611 <6>[ 0.072762] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 14:00:33.820596 <6>[ 0.079164] rcu: Hierarchical SRCU implementation.
10419 14:00:33.827448 <6>[ 0.084180] rcu: Max phase no-delay instances is 1000.
10420 14:00:33.834201 <6>[ 0.091201] EFI services will not be available.
10421 14:00:33.837515 <6>[ 0.096161] smp: Bringing up secondary CPUs ...
10422 14:00:33.845764 <6>[ 0.101211] Detected VIPT I-cache on CPU1
10423 14:00:33.852435 <6>[ 0.101281] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10424 14:00:33.858814 <6>[ 0.101311] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10425 14:00:33.862210 <6>[ 0.101646] Detected VIPT I-cache on CPU2
10426 14:00:33.868356 <6>[ 0.101695] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10427 14:00:33.875682 <6>[ 0.101710] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10428 14:00:33.881736 <6>[ 0.101965] Detected VIPT I-cache on CPU3
10429 14:00:33.888840 <6>[ 0.102010] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10430 14:00:33.895502 <6>[ 0.102024] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10431 14:00:33.898722 <6>[ 0.102327] CPU features: detected: Spectre-v4
10432 14:00:33.905207 <6>[ 0.102333] CPU features: detected: Spectre-BHB
10433 14:00:33.908524 <6>[ 0.102338] Detected PIPT I-cache on CPU4
10434 14:00:33.914901 <6>[ 0.102395] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10435 14:00:33.922353 <6>[ 0.102411] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10436 14:00:33.928119 <6>[ 0.102702] Detected PIPT I-cache on CPU5
10437 14:00:33.935095 <6>[ 0.102766] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10438 14:00:33.941922 <6>[ 0.102783] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10439 14:00:33.944922 <6>[ 0.103063] Detected PIPT I-cache on CPU6
10440 14:00:33.951967 <6>[ 0.103127] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10441 14:00:33.958218 <6>[ 0.103144] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10442 14:00:33.965231 <6>[ 0.103442] Detected PIPT I-cache on CPU7
10443 14:00:33.971422 <6>[ 0.103505] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10444 14:00:33.977611 <6>[ 0.103523] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10445 14:00:33.980981 <6>[ 0.103571] smp: Brought up 1 node, 8 CPUs
10446 14:00:33.988117 <6>[ 0.245024] SMP: Total of 8 processors activated.
10447 14:00:33.991006 <6>[ 0.249945] CPU features: detected: 32-bit EL0 Support
10448 14:00:34.001141 <6>[ 0.255341] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10449 14:00:34.007839 <6>[ 0.264196] CPU features: detected: Common not Private translations
10450 14:00:34.014519 <6>[ 0.270672] CPU features: detected: CRC32 instructions
10451 14:00:34.017920 <6>[ 0.276023] CPU features: detected: RCpc load-acquire (LDAPR)
10452 14:00:34.024319 <6>[ 0.281983] CPU features: detected: LSE atomic instructions
10453 14:00:34.031254 <6>[ 0.287764] CPU features: detected: Privileged Access Never
10454 14:00:34.037545 <6>[ 0.293544] CPU features: detected: RAS Extension Support
10455 14:00:34.043871 <6>[ 0.299187] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10456 14:00:34.047539 <6>[ 0.306408] CPU: All CPU(s) started at EL2
10457 14:00:34.053842 <6>[ 0.310751] alternatives: applying system-wide alternatives
10458 14:00:34.063517 <6>[ 0.321511] devtmpfs: initialized
10459 14:00:34.075685 <6>[ 0.330526] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10460 14:00:34.085674 <6>[ 0.340486] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10461 14:00:34.092474 <6>[ 0.348728] pinctrl core: initialized pinctrl subsystem
10462 14:00:34.095585 <6>[ 0.355374] DMI not present or invalid.
10463 14:00:34.102394 <6>[ 0.359788] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10464 14:00:34.111931 <6>[ 0.366678] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10465 14:00:34.118551 <6>[ 0.374255] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10466 14:00:34.128507 <6>[ 0.382488] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10467 14:00:34.131645 <6>[ 0.390731] audit: initializing netlink subsys (disabled)
10468 14:00:34.141892 <5>[ 0.396424] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10469 14:00:34.148428 <6>[ 0.397122] thermal_sys: Registered thermal governor 'step_wise'
10470 14:00:34.154969 <6>[ 0.404396] thermal_sys: Registered thermal governor 'power_allocator'
10471 14:00:34.158386 <6>[ 0.410651] cpuidle: using governor menu
10472 14:00:34.165248 <6>[ 0.421615] NET: Registered PF_QIPCRTR protocol family
10473 14:00:34.172096 <6>[ 0.427101] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10474 14:00:34.174913 <6>[ 0.434208] ASID allocator initialised with 32768 entries
10475 14:00:34.182578 <6>[ 0.440766] Serial: AMBA PL011 UART driver
10476 14:00:34.191633 <4>[ 0.449517] Trying to register duplicate clock ID: 134
10477 14:00:34.247595 <6>[ 0.508795] KASLR enabled
10478 14:00:34.261514 <6>[ 0.516576] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10479 14:00:34.268261 <6>[ 0.523593] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10480 14:00:34.274889 <6>[ 0.530085] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10481 14:00:34.281493 <6>[ 0.537092] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10482 14:00:34.288077 <6>[ 0.543583] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10483 14:00:34.294625 <6>[ 0.550592] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10484 14:00:34.301554 <6>[ 0.557081] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10485 14:00:34.308360 <6>[ 0.564089] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10486 14:00:34.310900 <6>[ 0.571604] ACPI: Interpreter disabled.
10487 14:00:34.320071 <6>[ 0.578029] iommu: Default domain type: Translated
10488 14:00:34.326842 <6>[ 0.583142] iommu: DMA domain TLB invalidation policy: strict mode
10489 14:00:34.329720 <5>[ 0.589804] SCSI subsystem initialized
10490 14:00:34.336366 <6>[ 0.593973] usbcore: registered new interface driver usbfs
10491 14:00:34.343018 <6>[ 0.599711] usbcore: registered new interface driver hub
10492 14:00:34.346217 <6>[ 0.605263] usbcore: registered new device driver usb
10493 14:00:34.353132 <6>[ 0.611365] pps_core: LinuxPPS API ver. 1 registered
10494 14:00:34.362879 <6>[ 0.616560] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10495 14:00:34.365999 <6>[ 0.625909] PTP clock support registered
10496 14:00:34.369657 <6>[ 0.630156] EDAC MC: Ver: 3.0.0
10497 14:00:34.377042 <6>[ 0.635324] FPGA manager framework
10498 14:00:34.380749 <6>[ 0.639007] Advanced Linux Sound Architecture Driver Initialized.
10499 14:00:34.384324 <6>[ 0.645785] vgaarb: loaded
10500 14:00:34.390647 <6>[ 0.648940] clocksource: Switched to clocksource arch_sys_counter
10501 14:00:34.397756 <5>[ 0.655383] VFS: Disk quotas dquot_6.6.0
10502 14:00:34.404400 <6>[ 0.659570] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10503 14:00:34.407706 <6>[ 0.666762] pnp: PnP ACPI: disabled
10504 14:00:34.415537 <6>[ 0.673492] NET: Registered PF_INET protocol family
10505 14:00:34.425178 <6>[ 0.679087] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10506 14:00:34.436614 <6>[ 0.691401] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10507 14:00:34.446432 <6>[ 0.700219] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10508 14:00:34.452934 <6>[ 0.708195] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10509 14:00:34.459885 <6>[ 0.716900] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10510 14:00:34.471760 <6>[ 0.726626] TCP: Hash tables configured (established 65536 bind 65536)
10511 14:00:34.478542 <6>[ 0.733489] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 14:00:34.484843 <6>[ 0.740691] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 14:00:34.492016 <6>[ 0.748393] NET: Registered PF_UNIX/PF_LOCAL protocol family
10514 14:00:34.498338 <6>[ 0.754551] RPC: Registered named UNIX socket transport module.
10515 14:00:34.501511 <6>[ 0.760705] RPC: Registered udp transport module.
10516 14:00:34.508511 <6>[ 0.765639] RPC: Registered tcp transport module.
10517 14:00:34.514849 <6>[ 0.770572] RPC: Registered tcp NFSv4.1 backchannel transport module.
10518 14:00:34.518553 <6>[ 0.777238] PCI: CLS 0 bytes, default 64
10519 14:00:34.521631 <6>[ 0.781567] Unpacking initramfs...
10520 14:00:34.546104 <6>[ 0.801033] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10521 14:00:34.556068 <6>[ 0.809661] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10522 14:00:34.559441 <6>[ 0.818516] kvm [1]: IPA Size Limit: 40 bits
10523 14:00:34.566202 <6>[ 0.823046] kvm [1]: GICv3: no GICV resource entry
10524 14:00:34.569116 <6>[ 0.828070] kvm [1]: disabling GICv2 emulation
10525 14:00:34.576007 <6>[ 0.832756] kvm [1]: GIC system register CPU interface enabled
10526 14:00:34.579597 <6>[ 0.838920] kvm [1]: vgic interrupt IRQ18
10527 14:00:34.585764 <6>[ 0.843272] kvm [1]: VHE mode initialized successfully
10528 14:00:34.592865 <5>[ 0.849740] Initialise system trusted keyrings
10529 14:00:34.599103 <6>[ 0.854513] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10530 14:00:34.606302 <6>[ 0.864512] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10531 14:00:34.613135 <5>[ 0.870918] NFS: Registering the id_resolver key type
10532 14:00:34.616294 <5>[ 0.876219] Key type id_resolver registered
10533 14:00:34.622966 <5>[ 0.880637] Key type id_legacy registered
10534 14:00:34.629771 <6>[ 0.884918] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10535 14:00:34.636431 <6>[ 0.891842] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10536 14:00:34.642972 <6>[ 0.899558] 9p: Installing v9fs 9p2000 file system support
10537 14:00:34.679976 <5>[ 0.937833] Key type asymmetric registered
10538 14:00:34.682836 <5>[ 0.942166] Asymmetric key parser 'x509' registered
10539 14:00:34.692853 <6>[ 0.947330] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10540 14:00:34.696067 <6>[ 0.954954] io scheduler mq-deadline registered
10541 14:00:34.699420 <6>[ 0.959732] io scheduler kyber registered
10542 14:00:34.718259 <6>[ 0.976773] EINJ: ACPI disabled.
10543 14:00:34.751407 <4>[ 1.003088] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 14:00:34.761593 <4>[ 1.013763] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 14:00:34.776736 <6>[ 1.034620] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10546 14:00:34.784077 <6>[ 1.042732] printk: console [ttyS0] disabled
10547 14:00:34.812557 <6>[ 1.067385] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10548 14:00:34.819494 <6>[ 1.076861] printk: console [ttyS0] enabled
10549 14:00:34.822512 <6>[ 1.076861] printk: console [ttyS0] enabled
10550 14:00:34.828904 <6>[ 1.085761] printk: bootconsole [mtk8250] disabled
10551 14:00:34.832037 <6>[ 1.085761] printk: bootconsole [mtk8250] disabled
10552 14:00:34.838608 <6>[ 1.097064] SuperH (H)SCI(F) driver initialized
10553 14:00:34.841935 <6>[ 1.102344] msm_serial: driver initialized
10554 14:00:34.856290 <6>[ 1.111320] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10555 14:00:34.866154 <6>[ 1.119865] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10556 14:00:34.872647 <6>[ 1.128409] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10557 14:00:34.882941 <6>[ 1.137042] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10558 14:00:34.892772 <6>[ 1.145751] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10559 14:00:34.899752 <6>[ 1.154470] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10560 14:00:34.909150 <6>[ 1.163011] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10561 14:00:34.916527 <6>[ 1.171817] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10562 14:00:34.926216 <6>[ 1.180361] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10563 14:00:34.938095 <6>[ 1.196045] loop: module loaded
10564 14:00:34.944660 <6>[ 1.202011] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10565 14:00:34.967291 <4>[ 1.225503] mtk-pmic-keys: Failed to locate of_node [id: -1]
10566 14:00:34.974325 <6>[ 1.232589] megasas: 07.719.03.00-rc1
10567 14:00:34.984163 <6>[ 1.242370] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10568 14:00:34.994128 <6>[ 1.252312] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10569 14:00:35.011117 <6>[ 1.269065] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10570 14:00:35.067643 <6>[ 1.319154] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10571 14:00:35.259934 <6>[ 1.518274] Freeing initrd memory: 17388K
10572 14:00:35.270095 <6>[ 1.528643] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10573 14:00:35.281148 <6>[ 1.539622] tun: Universal TUN/TAP device driver, 1.6
10574 14:00:35.284045 <6>[ 1.545683] thunder_xcv, ver 1.0
10575 14:00:35.287529 <6>[ 1.549194] thunder_bgx, ver 1.0
10576 14:00:35.291128 <6>[ 1.552684] nicpf, ver 1.0
10577 14:00:35.301747 <6>[ 1.556703] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10578 14:00:35.305213 <6>[ 1.564178] hns3: Copyright (c) 2017 Huawei Corporation.
10579 14:00:35.308856 <6>[ 1.569768] hclge is initializing
10580 14:00:35.315361 <6>[ 1.573342] e1000: Intel(R) PRO/1000 Network Driver
10581 14:00:35.322009 <6>[ 1.578471] e1000: Copyright (c) 1999-2006 Intel Corporation.
10582 14:00:35.325635 <6>[ 1.584484] e1000e: Intel(R) PRO/1000 Network Driver
10583 14:00:35.332239 <6>[ 1.589699] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10584 14:00:35.338598 <6>[ 1.595884] igb: Intel(R) Gigabit Ethernet Network Driver
10585 14:00:35.345103 <6>[ 1.601534] igb: Copyright (c) 2007-2014 Intel Corporation.
10586 14:00:35.351969 <6>[ 1.607369] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10587 14:00:35.355527 <6>[ 1.613887] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10588 14:00:35.362117 <6>[ 1.620348] sky2: driver version 1.30
10589 14:00:35.368817 <6>[ 1.625347] VFIO - User Level meta-driver version: 0.3
10590 14:00:35.375531 <6>[ 1.633577] usbcore: registered new interface driver usb-storage
10591 14:00:35.382202 <6>[ 1.640030] usbcore: registered new device driver onboard-usb-hub
10592 14:00:35.391472 <6>[ 1.649202] mt6397-rtc mt6359-rtc: registered as rtc0
10593 14:00:35.401080 <6>[ 1.654668] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:59:55 UTC (1706795995)
10594 14:00:35.404583 <6>[ 1.664231] i2c_dev: i2c /dev entries driver
10595 14:00:35.420731 <6>[ 1.675874] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10596 14:00:35.441498 <6>[ 1.698873] cpu cpu0: EM: created perf domain
10597 14:00:35.444008 <6>[ 1.703804] cpu cpu4: EM: created perf domain
10598 14:00:35.451012 <6>[ 1.709423] sdhci: Secure Digital Host Controller Interface driver
10599 14:00:35.457803 <6>[ 1.715853] sdhci: Copyright(c) Pierre Ossman
10600 14:00:35.464466 <6>[ 1.720799] Synopsys Designware Multimedia Card Interface Driver
10601 14:00:35.471389 <6>[ 1.727436] sdhci-pltfm: SDHCI platform and OF driver helper
10602 14:00:35.474295 <6>[ 1.727497] mmc0: CQHCI version 5.10
10603 14:00:35.481276 <6>[ 1.737746] ledtrig-cpu: registered to indicate activity on CPUs
10604 14:00:35.487589 <6>[ 1.744763] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10605 14:00:35.494175 <6>[ 1.751817] usbcore: registered new interface driver usbhid
10606 14:00:35.497342 <6>[ 1.757639] usbhid: USB HID core driver
10607 14:00:35.503917 <6>[ 1.761841] spi_master spi0: will run message pump with realtime priority
10608 14:00:35.548072 <6>[ 1.800334] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10609 14:00:35.566332 <6>[ 1.815359] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10610 14:00:35.569710 <6>[ 1.828907] mmc0: Command Queue Engine enabled
10611 14:00:35.576840 <6>[ 1.833739] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10612 14:00:35.583464 <6>[ 1.841053] mmcblk0: mmc0:0001 DA4128 116 GiB
10613 14:00:35.586677 <6>[ 1.846013] cros-ec-spi spi0.0: Chrome EC device registered
10614 14:00:35.593427 <6>[ 1.849859] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10615 14:00:35.601023 <6>[ 1.859740] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10616 14:00:35.607636 <6>[ 1.865658] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10617 14:00:35.614035 <6>[ 1.872021] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10618 14:00:35.632415 <6>[ 1.887686] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10619 14:00:35.640000 <6>[ 1.898451] NET: Registered PF_PACKET protocol family
10620 14:00:35.643161 <6>[ 1.903877] 9pnet: Installing 9P2000 support
10621 14:00:35.649908 <5>[ 1.908448] Key type dns_resolver registered
10622 14:00:35.653804 <6>[ 1.913492] registered taskstats version 1
10623 14:00:35.660043 <5>[ 1.917881] Loading compiled-in X.509 certificates
10624 14:00:35.692804 <4>[ 1.944341] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10625 14:00:35.702878 <4>[ 1.955087] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 14:00:35.709550 <3>[ 1.965618] debugfs: File 'uA_load' in directory '/' already present!
10627 14:00:35.716724 <3>[ 1.972325] debugfs: File 'min_uV' in directory '/' already present!
10628 14:00:35.722990 <3>[ 1.978932] debugfs: File 'max_uV' in directory '/' already present!
10629 14:00:35.729165 <3>[ 1.985540] debugfs: File 'constraint_flags' in directory '/' already present!
10630 14:00:35.739883 <3>[ 1.995372] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10631 14:00:35.752704 <6>[ 2.011291] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10632 14:00:35.759807 <6>[ 2.018136] xhci-mtk 11200000.usb: xHCI Host Controller
10633 14:00:35.766464 <6>[ 2.023643] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10634 14:00:35.776736 <6>[ 2.031599] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10635 14:00:35.783435 <6>[ 2.041038] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10636 14:00:35.789820 <6>[ 2.047124] xhci-mtk 11200000.usb: xHCI Host Controller
10637 14:00:35.796972 <6>[ 2.052605] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10638 14:00:35.803162 <6>[ 2.060257] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10639 14:00:35.810304 <6>[ 2.068100] hub 1-0:1.0: USB hub found
10640 14:00:35.813303 <6>[ 2.072127] hub 1-0:1.0: 1 port detected
10641 14:00:35.820012 <6>[ 2.076414] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10642 14:00:35.827014 <6>[ 2.085153] hub 2-0:1.0: USB hub found
10643 14:00:35.830452 <6>[ 2.089176] hub 2-0:1.0: 1 port detected
10644 14:00:35.837668 <6>[ 2.096078] mtk-msdc 11f70000.mmc: Got CD GPIO
10645 14:00:35.851546 <6>[ 2.106419] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10646 14:00:35.857829 <6>[ 2.114631] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10647 14:00:35.867891 <4>[ 2.122564] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10648 14:00:35.877917 <6>[ 2.132093] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10649 14:00:35.884462 <6>[ 2.140174] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10650 14:00:35.891132 <6>[ 2.148195] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10651 14:00:35.900945 <6>[ 2.156130] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10652 14:00:35.908045 <6>[ 2.163947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10653 14:00:35.917857 <6>[ 2.171764] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10654 14:00:35.927944 <6>[ 2.182352] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10655 14:00:35.934787 <6>[ 2.190722] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10656 14:00:35.944596 <6>[ 2.199072] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10657 14:00:35.950919 <6>[ 2.207411] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10658 14:00:35.960900 <6>[ 2.215749] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10659 14:00:35.967738 <6>[ 2.224088] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10660 14:00:35.977554 <6>[ 2.232426] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10661 14:00:35.984372 <6>[ 2.240765] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10662 14:00:35.994315 <6>[ 2.249106] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10663 14:00:36.003966 <6>[ 2.257445] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10664 14:00:36.010864 <6>[ 2.265785] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10665 14:00:36.020770 <6>[ 2.274123] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10666 14:00:36.027297 <6>[ 2.282473] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10667 14:00:36.037331 <6>[ 2.290811] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10668 14:00:36.043819 <6>[ 2.299151] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10669 14:00:36.050626 <6>[ 2.307930] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10670 14:00:36.057322 <6>[ 2.315071] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10671 14:00:36.063649 <6>[ 2.321830] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10672 14:00:36.070326 <6>[ 2.328588] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10673 14:00:36.080410 <6>[ 2.335519] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10674 14:00:36.087139 <6>[ 2.342375] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10675 14:00:36.097270 <6>[ 2.351503] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10676 14:00:36.107233 <6>[ 2.360621] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10677 14:00:36.117188 <6>[ 2.369914] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10678 14:00:36.126866 <6>[ 2.379381] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10679 14:00:36.133772 <6>[ 2.388846] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10680 14:00:36.143337 <6>[ 2.397966] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10681 14:00:36.153225 <6>[ 2.407434] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10682 14:00:36.163290 <6>[ 2.416552] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10683 14:00:36.173382 <6>[ 2.425846] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10684 14:00:36.182748 <6>[ 2.436006] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10685 14:00:36.192435 <6>[ 2.447640] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10686 14:00:36.199172 <6>[ 2.457295] Trying to probe devices needed for running init ...
10687 14:00:36.241730 <6>[ 2.497269] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10688 14:00:36.396077 <6>[ 2.655041] hub 1-1:1.0: USB hub found
10689 14:00:36.399196 <6>[ 2.659578] hub 1-1:1.0: 4 ports detected
10690 14:00:36.409787 <6>[ 2.668465] hub 1-1:1.0: USB hub found
10691 14:00:36.412616 <6>[ 2.672801] hub 1-1:1.0: 4 ports detected
10692 14:00:36.521843 <6>[ 2.777564] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10693 14:00:36.548104 <6>[ 2.807002] hub 2-1:1.0: USB hub found
10694 14:00:36.551526 <6>[ 2.811512] hub 2-1:1.0: 3 ports detected
10695 14:00:36.561277 <6>[ 2.819939] hub 2-1:1.0: USB hub found
10696 14:00:36.564342 <6>[ 2.824457] hub 2-1:1.0: 3 ports detected
10697 14:00:36.737507 <6>[ 2.993234] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10698 14:00:36.870065 <6>[ 3.128990] hub 1-1.4:1.0: USB hub found
10699 14:00:36.873351 <6>[ 3.133636] hub 1-1.4:1.0: 2 ports detected
10700 14:00:36.882886 <6>[ 3.141722] hub 1-1.4:1.0: USB hub found
10701 14:00:36.885970 <6>[ 3.146319] hub 1-1.4:1.0: 2 ports detected
10702 14:00:36.949883 <6>[ 3.205451] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10703 14:00:37.181554 <6>[ 3.437265] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10704 14:00:37.373320 <6>[ 3.629266] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10705 14:00:48.471088 <6>[ 14.734305] ALSA device list:
10706 14:00:48.477449 <6>[ 14.737607] No soundcards found.
10707 14:00:48.485668 <6>[ 14.745718] Freeing unused kernel memory: 8448K
10708 14:00:48.489209 <6>[ 14.750752] Run /init as init process
10709 14:00:48.500509 Loading, please wait...
10710 14:00:48.520927 Starting version 247.3-7+deb11u2
10711 14:00:48.740868 <6>[ 14.997689] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10712 14:00:48.754550 <3>[ 15.011097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 14:00:48.761310 <3>[ 15.019237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 14:00:48.771155 <3>[ 15.027321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 14:00:48.777826 <3>[ 15.035558] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 14:00:48.784104 <6>[ 15.037185] remoteproc remoteproc0: scp is available
10717 14:00:48.790879 <3>[ 15.043645] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 14:00:48.800918 <3>[ 15.043649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 14:00:48.807543 <3>[ 15.043656] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 14:00:48.817663 <3>[ 15.043659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 14:00:48.820597 <6>[ 15.049015] remoteproc remoteproc0: powering up scp
10722 14:00:48.830630 <3>[ 15.057000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 14:00:48.837486 <4>[ 15.059092] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10724 14:00:48.843996 <6>[ 15.060257] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10725 14:00:48.853784 <6>[ 15.060310] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10726 14:00:48.860773 <6>[ 15.060324] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10727 14:00:48.870653 <6>[ 15.065196] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10728 14:00:48.876992 <4>[ 15.065902] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10729 14:00:48.884403 <3>[ 15.073190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 14:00:48.890996 <6>[ 15.076784] mc: Linux media interface: v0.10
10731 14:00:48.894137 <6>[ 15.081285] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10732 14:00:48.904418 <3>[ 15.086338] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 14:00:48.911149 <6>[ 15.094510] usbcore: registered new device driver r8152-cfgselector
10734 14:00:48.918221 <6>[ 15.097291] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10735 14:00:48.925274 <3>[ 15.101720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 14:00:48.934944 <3>[ 15.101769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 14:00:48.941698 <4>[ 15.123049] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10738 14:00:48.948337 <4>[ 15.123049] Fallback method does not support PEC.
10739 14:00:48.954762 <3>[ 15.126696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 14:00:48.964708 <3>[ 15.126702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 14:00:48.971590 <3>[ 15.151801] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10742 14:00:48.981252 <3>[ 15.155111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 14:00:48.991415 <6>[ 15.157723] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10744 14:00:49.001168 <6>[ 15.158125] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10745 14:00:49.007655 <6>[ 15.180965] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10746 14:00:49.017661 <6>[ 15.182364] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10747 14:00:49.021160 <6>[ 15.182372] pci_bus 0000:00: root bus resource [bus 00-ff]
10748 14:00:49.027667 <6>[ 15.182381] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10749 14:00:49.037411 <6>[ 15.182388] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10750 14:00:49.044294 <6>[ 15.182430] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10751 14:00:49.054317 <6>[ 15.182456] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10752 14:00:49.057394 <6>[ 15.182563] pci 0000:00:00.0: supports D1 D2
10753 14:00:49.063866 <6>[ 15.182568] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10754 14:00:49.073833 <3>[ 15.183218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 14:00:49.080841 <6>[ 15.184552] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10756 14:00:49.086726 <6>[ 15.184667] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10757 14:00:49.093747 <6>[ 15.184700] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10758 14:00:49.100086 <6>[ 15.184722] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10759 14:00:49.110011 <6>[ 15.184742] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10760 14:00:49.113371 <6>[ 15.184861] pci 0000:01:00.0: supports D1 D2
10761 14:00:49.120111 <6>[ 15.184864] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10762 14:00:49.129779 <3>[ 15.193188] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10763 14:00:49.136701 <3>[ 15.199155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 14:00:49.142988 <6>[ 15.201080] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10765 14:00:49.153122 <6>[ 15.201144] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10766 14:00:49.159371 <6>[ 15.201151] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10767 14:00:49.169417 <6>[ 15.201168] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10768 14:00:49.176105 <6>[ 15.201193] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10769 14:00:49.185802 <6>[ 15.201210] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10770 14:00:49.189173 <6>[ 15.201226] pci 0000:00:00.0: PCI bridge to [bus 01]
10771 14:00:49.199220 <6>[ 15.201236] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10772 14:00:49.206126 <6>[ 15.201275] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10773 14:00:49.212537 <6>[ 15.201438] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10774 14:00:49.219317 <6>[ 15.202412] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10775 14:00:49.225867 <6>[ 15.202679] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10776 14:00:49.229074 <6>[ 15.213601] videodev: Linux video capture interface: v2.00
10777 14:00:49.238879 <6>[ 15.220028] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10778 14:00:49.245326 <6>[ 15.220030] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10779 14:00:49.252022 <6>[ 15.220040] remoteproc remoteproc0: remote processor scp is now up
10780 14:00:49.258754 <5>[ 15.225508] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10781 14:00:49.268845 <4>[ 15.227532] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10782 14:00:49.278596 <4>[ 15.227542] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10783 14:00:49.281729 <6>[ 15.238437] Bluetooth: Core ver 2.22
10784 14:00:49.288418 <6>[ 15.239475] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10785 14:00:49.298173 <6>[ 15.241124] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10786 14:00:49.304898 <5>[ 15.256047] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10787 14:00:49.308450 <6>[ 15.265167] NET: Registered PF_BLUETOOTH protocol family
10788 14:00:49.318561 <5>[ 15.274617] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10789 14:00:49.325365 <6>[ 15.281196] Bluetooth: HCI device and connection manager initialized
10790 14:00:49.331709 <6>[ 15.281220] Bluetooth: HCI socket layer initialized
10791 14:00:49.337785 <4>[ 15.287023] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10792 14:00:49.344565 <6>[ 15.289084] r8152 2-1.3:1.0 eth0: v1.12.13
10793 14:00:49.348323 <6>[ 15.289181] usbcore: registered new interface driver r8152
10794 14:00:49.355243 <6>[ 15.294062] Bluetooth: L2CAP socket layer initialized
10795 14:00:49.358030 <6>[ 15.294074] Bluetooth: SCO socket layer initialized
10796 14:00:49.364520 <6>[ 15.303967] cfg80211: failed to load regulatory.db
10797 14:00:49.371292 <6>[ 15.305439] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10798 14:00:49.384309 <6>[ 15.307362] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10799 14:00:49.390656 <6>[ 15.307494] usbcore: registered new interface driver uvcvideo
10800 14:00:49.394523 <6>[ 15.310965] usbcore: registered new interface driver cdc_ether
10801 14:00:49.400850 <6>[ 15.320147] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10802 14:00:49.407223 <6>[ 15.338030] usbcore: registered new interface driver r8153_ecm
10803 14:00:49.413926 <6>[ 15.352665] usbcore: registered new interface driver btusb
10804 14:00:49.424240 <4>[ 15.353344] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10805 14:00:49.430359 <3>[ 15.353354] Bluetooth: hci0: Failed to load firmware file (-2)
10806 14:00:49.437434 <3>[ 15.353358] Bluetooth: hci0: Failed to set up firmware (-2)
10807 14:00:49.447106 <4>[ 15.353361] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10808 14:00:49.453535 <6>[ 15.382403] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10809 14:00:49.460426 <6>[ 15.394637] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10810 14:00:49.466915 <6>[ 15.725490] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10811 14:00:49.489372 <6>[ 15.749179] mt7921e 0000:01:00.0: ASIC revision: 79610010
10812 14:00:49.591472 <6>[ 15.848396] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10813 14:00:49.595209 <6>[ 15.848396]
10814 14:00:49.598416 Begin: Loading essential drivers ... done.
10815 14:00:49.602012 Begin: Running /scripts/init-premount ... done.
10816 14:00:49.608140 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10817 14:00:49.618180 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10818 14:00:49.621434 Device /sys/class/net/enx00e04c722dd6 found
10819 14:00:49.622083 done.
10820 14:00:49.680722 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10821 14:00:49.860453 <6>[ 16.117016] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10822 14:00:50.613074 <6>[ 16.873289] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10823 14:00:50.704131 <6>[ 16.964155] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10824 14:00:50.894608 IP-Config: no response after 2 secs - giving up
10825 14:00:50.944285 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10826 14:00:50.965426 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10827 14:00:51.670460 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10828 14:00:51.677437 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10829 14:00:51.683781 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10830 14:00:51.690530 host : mt8192-asurada-spherion-r0-cbg-1
10831 14:00:51.697341 domain : lava-rack
10832 14:00:51.700294 rootserver: 192.168.201.1 rootpath:
10833 14:00:51.703303 filename :
10834 14:00:51.823775 done.
10835 14:00:51.830332 Begin: Running /scripts/nfs-bottom ... done.
10836 14:00:51.848743 Begin: Running /scripts/init-bottom ... done.
10837 14:00:53.041840 <6>[ 19.302685] NET: Registered PF_INET6 protocol family
10838 14:00:53.050492 <6>[ 19.311481] Segment Routing with IPv6
10839 14:00:53.054036 <6>[ 19.315437] In-situ OAM (IOAM) with IPv6
10840 14:00:53.188309 <30>[ 19.429260] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10841 14:00:53.194619 <30>[ 19.453876] systemd[1]: Detected architecture arm64.
10842 14:00:53.212782
10843 14:00:53.216202 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10844 14:00:53.216313
10845 14:00:53.234375 <30>[ 19.495404] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10846 14:00:54.015888 <30>[ 20.273376] systemd[1]: Queued start job for default target Graphical Interface.
10847 14:00:54.038727 <30>[ 20.299897] systemd[1]: Created slice system-getty.slice.
10848 14:00:54.045363 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10849 14:00:54.066091 <30>[ 20.326869] systemd[1]: Created slice system-modprobe.slice.
10850 14:00:54.072586 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10851 14:00:54.093537 <30>[ 20.354627] systemd[1]: Created slice system-serial\x2dgetty.slice.
10852 14:00:54.103812 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10853 14:00:54.121468 <30>[ 20.382491] systemd[1]: Created slice User and Session Slice.
10854 14:00:54.128018 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10855 14:00:54.147657 <30>[ 20.405574] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10856 14:00:54.157549 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10857 14:00:54.176359 <30>[ 20.434049] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10858 14:00:54.182824 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10859 14:00:54.207281 <30>[ 20.461851] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10860 14:00:54.214201 <30>[ 20.474157] systemd[1]: Reached target Local Encrypted Volumes.
10861 14:00:54.220923 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10862 14:00:54.236474 <30>[ 20.497436] systemd[1]: Reached target Paths.
10863 14:00:54.239829 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10864 14:00:54.256286 <30>[ 20.517250] systemd[1]: Reached target Remote File Systems.
10865 14:00:54.262863 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10866 14:00:54.279978 <30>[ 20.541222] systemd[1]: Reached target Slices.
10867 14:00:54.286942 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10868 14:00:54.300283 <30>[ 20.561267] systemd[1]: Reached target Swap.
10869 14:00:54.303304 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10870 14:00:54.324126 <30>[ 20.581721] systemd[1]: Listening on initctl Compatibility Named Pipe.
10871 14:00:54.330380 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10872 14:00:54.337270 <30>[ 20.597922] systemd[1]: Listening on Journal Audit Socket.
10873 14:00:54.343979 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10874 14:00:54.361290 <30>[ 20.622442] systemd[1]: Listening on Journal Socket (/dev/log).
10875 14:00:54.368112 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10876 14:00:54.384890 <30>[ 20.645877] systemd[1]: Listening on Journal Socket.
10877 14:00:54.391319 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10878 14:00:54.409080 <30>[ 20.666725] systemd[1]: Listening on Network Service Netlink Socket.
10879 14:00:54.415381 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10880 14:00:54.430547 <30>[ 20.691743] systemd[1]: Listening on udev Control Socket.
10881 14:00:54.437428 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10882 14:00:54.452489 <30>[ 20.713749] systemd[1]: Listening on udev Kernel Socket.
10883 14:00:54.459193 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10884 14:00:54.516215 <30>[ 20.777426] systemd[1]: Mounting Huge Pages File System...
10885 14:00:54.522916 Mounting [0;1;39mHuge Pages File System[0m...
10886 14:00:54.540880 <30>[ 20.801925] systemd[1]: Mounting POSIX Message Queue File System...
10887 14:00:54.547807 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10888 14:00:54.571644 <30>[ 20.832701] systemd[1]: Mounting Kernel Debug File System...
10889 14:00:54.578208 Mounting [0;1;39mKernel Debug File System[0m...
10890 14:00:54.595905 <30>[ 20.853792] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10891 14:00:54.648365 <30>[ 20.906079] systemd[1]: Starting Create list of static device nodes for the current kernel...
10892 14:00:54.654866 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10893 14:00:54.677471 <30>[ 20.938591] systemd[1]: Starting Load Kernel Module configfs...
10894 14:00:54.684496 Starting [0;1;39mLoad Kernel Module configfs[0m...
10895 14:00:54.705604 <30>[ 20.966582] systemd[1]: Starting Load Kernel Module drm...
10896 14:00:54.712167 Starting [0;1;39mLoad Kernel Module drm[0m...
10897 14:00:54.732897 <30>[ 20.994127] systemd[1]: Starting Load Kernel Module fuse...
10898 14:00:54.739530 Starting [0;1;39mLoad Kernel Module fuse[0m...
10899 14:00:54.759672 <30>[ 21.017750] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10900 14:00:54.776927 <6>[ 21.038322] fuse: init (API version 7.37)
10901 14:00:54.804919 <30>[ 21.066133] systemd[1]: Starting Journal Service...
10902 14:00:54.811602 Starting [0;1;39mJournal Service[0m...
10903 14:00:54.833832 <30>[ 21.094957] systemd[1]: Starting Load Kernel Modules...
10904 14:00:54.840452 Starting [0;1;39mLoad Kernel Modules[0m...
10905 14:00:54.860119 <30>[ 21.117726] systemd[1]: Starting Remount Root and Kernel File Systems...
10906 14:00:54.866397 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10907 14:00:54.885244 <30>[ 21.146239] systemd[1]: Starting Coldplug All udev Devices...
10908 14:00:54.891841 Starting [0;1;39mColdplug All udev Devices[0m...
10909 14:00:54.911093 <30>[ 21.172031] systemd[1]: Mounted Huge Pages File System.
10910 14:00:54.917333 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10911 14:00:54.932814 <30>[ 21.194043] systemd[1]: Mounted POSIX Message Queue File System.
10912 14:00:54.942941 <3>[ 21.195219] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 14:00:54.949647 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10914 14:00:54.964660 <30>[ 21.225517] systemd[1]: Mounted Kernel Debug File System.
10915 14:00:54.978382 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0<3>[ 21.235730] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 14:00:54.981726 m.
10917 14:00:55.000267 <30>[ 21.258200] systemd[1]: Finished Create list of static device nodes for the current kernel.
10918 14:00:55.010567 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10919 14:00:55.020288 <3>[ 21.277740] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 14:00:55.029091 <30>[ 21.290256] systemd[1]: modprobe@configfs.service: Succeeded.
10921 14:00:55.036108 <30>[ 21.296915] systemd[1]: Finished Load Kernel Module configfs.
10922 14:00:55.053046 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configf<3>[ 21.307985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 14:00:55.053156 s[0m.
10924 14:00:55.070213 <30>[ 21.330913] systemd[1]: modprobe@drm.service: Succeeded.
10925 14:00:55.077250 <30>[ 21.337314] systemd[1]: Finished Load Kernel Module drm.
10926 14:00:55.086884 <3>[ 21.341179] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 14:00:55.093567 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10928 14:00:55.110268 <30>[ 21.370455] systemd[1]: modprobe@fuse.service: Succeeded.
10929 14:00:55.119764 <3>[ 21.375847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 14:00:55.123293 <30>[ 21.376864] systemd[1]: Finished Load Kernel Module fuse.
10931 14:00:55.130203 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10932 14:00:55.145872 <30>[ 21.406708] systemd[1]: Finished Load Kernel Modules.
10933 14:00:55.156193 <3>[ 21.408745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 14:00:55.159500 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10935 14:00:55.178099 <30>[ 21.438153] systemd[1]: Finished Remount Root and Kernel File Systems.
10936 14:00:55.188159 <3>[ 21.444402] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 14:00:55.194700 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10938 14:00:55.221314 <3>[ 21.478563] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 14:00:55.250775 <3>[ 21.508037] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 14:00:55.257007 <30>[ 21.508893] systemd[1]: Mounting FUSE Control File System...
10941 14:00:55.263573 Mounting [0;1;39mFUSE Control File System[0m...
10942 14:00:55.283099 <30>[ 21.540458] systemd[1]: Mounting Kernel Configuration File System...
10943 14:00:55.286188 Mounting [0;1;39mKernel Configuration File System[0m...
10944 14:00:55.312264 <30>[ 21.569414] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10945 14:00:55.321719 <30>[ 21.578509] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10946 14:00:55.331277 <30>[ 21.592176] systemd[1]: Starting Load/Save Random Seed...
10947 14:00:55.337778 Starting [0;1;39mLoad/Save Random Seed[0m...
10948 14:00:55.356732 <30>[ 21.617376] systemd[1]: Starting Apply Kernel Variables...
10949 14:00:55.363075 Starting [0;1;39mApply Kernel Variables[0m...
10950 14:00:55.380416 <30>[ 21.641583] systemd[1]: Starting Create System Users...
10951 14:00:55.387208 Starting [0;1;39mCreate System Users[0m...
10952 14:00:55.406535 <30>[ 21.667354] systemd[1]: Started Journal Service.
10953 14:00:55.410005 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10954 14:00:55.426860 <4>[ 21.677389] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10955 14:00:55.433794 <3>[ 21.693273] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10956 14:00:55.440365 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10957 14:00:55.458420 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10958 14:00:55.472207 See 'systemctl status systemd-udev-trigger.service' for details.
10959 14:00:55.493212 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10960 14:00:55.509776 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10961 14:00:55.526602 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10962 14:00:55.545893 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10963 14:00:55.593295 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10964 14:00:55.610860 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10965 14:00:55.645640 <46>[ 21.903412] systemd-journald[303]: Received client request to flush runtime journal.
10966 14:00:55.664601 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10967 14:00:55.677301 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10968 14:00:55.697284 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10969 14:00:55.749089 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10970 14:00:57.037848 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10971 14:00:57.097447 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10972 14:00:57.121588 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10973 14:00:57.148509 Starting [0;1;39mNetwork Service[0m...
10974 14:00:57.452329 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10975 14:00:57.472408 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10976 14:00:57.532001 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10977 14:00:57.839760 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10978 14:00:57.859787 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10979 14:00:57.880449 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10980 14:00:57.900400 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10981 14:00:57.916750 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10982 14:00:58.016647 Starting [0;1;39mNetwork Name Resolution[0m...
10983 14:00:58.037644 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10984 14:00:58.064739 Starting [0;1;39mNetwork Time Synchronization[0m...
10985 14:00:58.083507 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10986 14:00:58.101543 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10987 14:00:58.163557 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10988 14:00:58.562668 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10989 14:00:58.580665 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10990 14:00:58.603694 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10991 14:00:58.616118 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10992 14:00:58.631866 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10993 14:00:58.653229 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10994 14:00:58.672910 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10995 14:00:58.698391 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10996 14:00:58.722226 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10997 14:00:58.736114 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10998 14:00:58.757121 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10999 14:00:58.771912 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11000 14:00:58.787825 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11001 14:00:58.844797 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11002 14:00:58.896808 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11003 14:00:58.967857 Starting [0;1;39mUser Login Management[0m...
11004 14:00:58.984307 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11005 14:00:59.003561 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11006 14:00:59.021075 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11007 14:00:59.081405 Starting [0;1;39mPermit User Sessions[0m...
11008 14:00:59.204477 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11009 14:00:59.219534 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11010 14:00:59.262859 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11011 14:00:59.282733 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11012 14:00:59.301390 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11013 14:00:59.319176 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11014 14:00:59.337915 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11015 14:00:59.356272 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11016 14:00:59.411570 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11017 14:00:59.456688 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11018 14:00:59.531457
11019 14:00:59.531575
11020 14:00:59.535007 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11021 14:00:59.535086
11022 14:00:59.538136 debian-bullseye-arm64 login: root (automatic login)
11023 14:00:59.538227
11024 14:00:59.538293
11025 14:00:59.856285 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
11026 14:00:59.856424
11027 14:00:59.863199 The programs included with the Debian GNU/Linux system are free software;
11028 14:00:59.869504 the exact distribution terms for each program are described in the
11029 14:00:59.872934 individual files in /usr/share/doc/*/copyright.
11030 14:00:59.873013
11031 14:00:59.879781 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11032 14:00:59.882703 permitted by applicable law.
11033 14:01:00.701746 Matched prompt #10: / #
11035 14:01:00.702100 Setting prompt string to ['/ #']
11036 14:01:00.702199 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11038 14:01:00.702400 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11039 14:01:00.702491 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
11040 14:01:00.702565 Setting prompt string to ['/ #']
11041 14:01:00.702630 Forcing a shell prompt, looking for ['/ #']
11043 14:01:00.752818 / #
11044 14:01:00.752921 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11045 14:01:00.753022 Waiting using forced prompt support (timeout 00:02:30)
11046 14:01:00.757782
11047 14:01:00.758078 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11048 14:01:00.758176 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11050 14:01:00.858488 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682968/extract-nfsrootfs-oglozrbb'
11051 14:01:00.863636 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682968/extract-nfsrootfs-oglozrbb'
11053 14:01:00.964095 / # export NFS_SERVER_IP='192.168.201.1'
11054 14:01:00.969585 export NFS_SERVER_IP='192.168.201.1'
11055 14:01:00.969864 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11056 14:01:00.969978 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
11057 14:01:00.970074 end: 2 depthcharge-action (duration 00:01:27) [common]
11058 14:01:00.970167 start: 3 lava-test-retry (timeout 00:07:50) [common]
11059 14:01:00.970262 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11060 14:01:00.970343 Using namespace: common
11062 14:01:01.070615 / # #
11063 14:01:01.070730 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11064 14:01:01.075828 #
11065 14:01:01.076083 Using /lava-12682968
11067 14:01:01.176378 / # export SHELL=/bin/bash
11068 14:01:01.181779 export SHELL=/bin/bash
11070 14:01:01.282268 / # . /lava-12682968/environment
11071 14:01:01.287173 . /lava-12682968/environment
11073 14:01:01.393204 / # /lava-12682968/bin/lava-test-runner /lava-12682968/0
11074 14:01:01.393323 Test shell timeout: 10s (minimum of the action and connection timeout)
11075 14:01:01.398557 /lava-12682968/bin/lava-test-runner /lava-12682968/0
11076 14:01:01.653914 + export TESTRUN_ID=0_timesync-off
11077 14:01:01.657200 + TESTRUN_ID=0_timesync-off
11078 14:01:01.660563 + cd /lava-12682968/0/tests/0_timesync-off
11079 14:01:01.663522 ++ cat uuid
11080 14:01:01.667079 + UUID=12682968_1.6.2.3.1
11081 14:01:01.667159 + set +x
11082 14:01:01.673509 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12682968_1.6.2.3.1>
11083 14:01:01.673767 Received signal: <STARTRUN> 0_timesync-off 12682968_1.6.2.3.1
11084 14:01:01.673850 Starting test lava.0_timesync-off (12682968_1.6.2.3.1)
11085 14:01:01.673958 Skipping test definition patterns.
11086 14:01:01.676971 + systemctl stop systemd-timesyncd
11087 14:01:01.717237 + set +x
11088 14:01:01.720246 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12682968_1.6.2.3.1>
11089 14:01:01.720500 Received signal: <ENDRUN> 0_timesync-off 12682968_1.6.2.3.1
11090 14:01:01.720592 Ending use of test pattern.
11091 14:01:01.720656 Ending test lava.0_timesync-off (12682968_1.6.2.3.1), duration 0.05
11093 14:01:01.782942 + export TESTRUN_ID=1_kselftest-arm64
11094 14:01:01.783031 + TESTRUN_ID=1_kselftest-arm64
11095 14:01:01.789558 + cd /lava-12682968/0/tests/1_kselftest-arm64
11096 14:01:01.789638 ++ cat uuid
11097 14:01:01.792720 + UUID=12682968_1.6.2.3.5
11098 14:01:01.792794 + set +x
11099 14:01:01.799292 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12682968_1.6.2.3.5>
11100 14:01:01.799541 Received signal: <STARTRUN> 1_kselftest-arm64 12682968_1.6.2.3.5
11101 14:01:01.799611 Starting test lava.1_kselftest-arm64 (12682968_1.6.2.3.5)
11102 14:01:01.799689 Skipping test definition patterns.
11103 14:01:01.802544 + cd ./automated/linux/kselftest/
11104 14:01:01.828631 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11105 14:01:01.858636 INFO: install_deps skipped
11106 14:01:01.970522 --2024-02-01 14:00:22-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11107 14:01:01.983763 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11108 14:01:02.112807 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11109 14:01:02.241842 HTTP request sent, awaiting response... 200 OK
11110 14:01:02.245315 Length: 2966796 (2.8M) [application/octet-stream]
11111 14:01:02.248318 Saving to: 'kselftest.tar.xz'
11112 14:01:02.248402
11113 14:01:02.248469
11114 14:01:02.500757 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11115 14:01:02.759181 kselftest.tar.xz 1%[ ] 49.22K 189KB/s
11116 14:01:03.195115 kselftest.tar.xz 7%[> ] 218.91K 419KB/s
11117 14:01:03.467821 kselftest.tar.xz 28%[====> ] 823.64K 855KB/s
11118 14:01:03.474516 kselftest.tar.xz 83%[===============> ] 2.35M 1.90MB/s
11119 14:01:03.481109 kselftest.tar.xz 100%[===================>] 2.83M 2.27MB/s in 1.2s
11120 14:01:03.481195
11121 14:01:03.738803 2024-02-01 14:00:23 (2.27 MB/s) - 'kselftest.tar.xz' saved [2966796/2966796]
11122 14:01:03.738982
11123 14:01:09.424846 skiplist:
11124 14:01:09.428208 ========================================
11125 14:01:09.431633 ========================================
11126 14:01:09.485450 arm64:tags_test
11127 14:01:09.488652 arm64:run_tags_test.sh
11128 14:01:09.488733 arm64:fake_sigreturn_bad_magic
11129 14:01:09.491579 arm64:fake_sigreturn_bad_size
11130 14:01:09.494766 arm64:fake_sigreturn_bad_size_for_magic0
11131 14:01:09.498402 arm64:fake_sigreturn_duplicated_fpsimd
11132 14:01:09.501351 arm64:fake_sigreturn_misaligned_sp
11133 14:01:09.505130 arm64:fake_sigreturn_missing_fpsimd
11134 14:01:09.508656 arm64:fake_sigreturn_sme_change_vl
11135 14:01:09.511445 arm64:fake_sigreturn_sve_change_vl
11136 14:01:09.515053 arm64:mangle_pstate_invalid_compat_toggle
11137 14:01:09.518179 arm64:mangle_pstate_invalid_daif_bits
11138 14:01:09.521524 arm64:mangle_pstate_invalid_mode_el1h
11139 14:01:09.524738 arm64:mangle_pstate_invalid_mode_el1t
11140 14:01:09.528003 arm64:mangle_pstate_invalid_mode_el2h
11141 14:01:09.531289 arm64:mangle_pstate_invalid_mode_el2t
11142 14:01:09.534516 arm64:mangle_pstate_invalid_mode_el3h
11143 14:01:09.538041 arm64:mangle_pstate_invalid_mode_el3t
11144 14:01:09.541325 arm64:sme_trap_no_sm
11145 14:01:09.544492 arm64:sme_trap_non_streaming
11146 14:01:09.544565 arm64:sme_trap_za
11147 14:01:09.548249 arm64:sme_vl
11148 14:01:09.548355 arm64:ssve_regs
11149 14:01:09.551158 arm64:sve_regs
11150 14:01:09.551234 arm64:sve_vl
11151 14:01:09.551298 arm64:za_no_regs
11152 14:01:09.554498 arm64:za_regs
11153 14:01:09.554594 arm64:pac
11154 14:01:09.554684 arm64:fp-stress
11155 14:01:09.557887 arm64:sve-ptrace
11156 14:01:09.561806 arm64:sve-probe-vls
11157 14:01:09.562306 arm64:vec-syscfg
11158 14:01:09.562647 arm64:za-fork
11159 14:01:09.565001 arm64:za-ptrace
11160 14:01:09.565449 arm64:check_buffer_fill
11161 14:01:09.568328 arm64:check_child_memory
11162 14:01:09.571683 arm64:check_gcr_el1_cswitch
11163 14:01:09.575039 arm64:check_ksm_options
11164 14:01:09.575614 arm64:check_mmap_options
11165 14:01:09.578286 arm64:check_prctl
11166 14:01:09.581720 arm64:check_tags_inclusion
11167 14:01:09.582280 arm64:check_user_mem
11168 14:01:09.582661 arm64:btitest
11169 14:01:09.584526 arm64:nobtitest
11170 14:01:09.585108 arm64:hwcap
11171 14:01:09.588220 arm64:ptrace
11172 14:01:09.588696 arm64:syscall-abi
11173 14:01:09.591579 arm64:tpidr2
11174 14:01:09.594714 ============== Tests to run ===============
11175 14:01:09.595194 arm64:tags_test
11176 14:01:09.598117 arm64:run_tags_test.sh
11177 14:01:09.601374 arm64:fake_sigreturn_bad_magic
11178 14:01:09.601966 arm64:fake_sigreturn_bad_size
11179 14:01:09.607914 arm64:fake_sigreturn_bad_size_for_magic0
11180 14:01:09.611509 arm64:fake_sigreturn_duplicated_fpsimd
11181 14:01:09.612055 arm64:fake_sigreturn_misaligned_sp
11182 14:01:09.614601 arm64:fake_sigreturn_missing_fpsimd
11183 14:01:09.617768 arm64:fake_sigreturn_sme_change_vl
11184 14:01:09.621277 arm64:fake_sigreturn_sve_change_vl
11185 14:01:09.624582 arm64:mangle_pstate_invalid_compat_toggle
11186 14:01:09.631300 arm64:mangle_pstate_invalid_daif_bits
11187 14:01:09.634440 arm64:mangle_pstate_invalid_mode_el1h
11188 14:01:09.637837 arm64:mangle_pstate_invalid_mode_el1t
11189 14:01:09.641124 arm64:mangle_pstate_invalid_mode_el2h
11190 14:01:09.644558 arm64:mangle_pstate_invalid_mode_el2t
11191 14:01:09.647814 arm64:mangle_pstate_invalid_mode_el3h
11192 14:01:09.651022 arm64:mangle_pstate_invalid_mode_el3t
11193 14:01:09.651491 arm64:sme_trap_no_sm
11194 14:01:09.654385 arm64:sme_trap_non_streaming
11195 14:01:09.657689 arm64:sme_trap_za
11196 14:01:09.658197 arm64:sme_vl
11197 14:01:09.658571 arm64:ssve_regs
11198 14:01:09.661200 arm64:sve_regs
11199 14:01:09.661665 arm64:sve_vl
11200 14:01:09.664035 arm64:za_no_regs
11201 14:01:09.664506 arm64:za_regs
11202 14:01:09.664878 arm64:pac
11203 14:01:09.667421 arm64:fp-stress
11204 14:01:09.667892 arm64:sve-ptrace
11205 14:01:09.670548 arm64:sve-probe-vls
11206 14:01:09.671011 arm64:vec-syscfg
11207 14:01:09.674395 arm64:za-fork
11208 14:01:09.674861 arm64:za-ptrace
11209 14:01:09.677163 arm64:check_buffer_fill
11210 14:01:09.677631 arm64:check_child_memory
11211 14:01:09.680694 arm64:check_gcr_el1_cswitch
11212 14:01:09.684055 arm64:check_ksm_options
11213 14:01:09.687050 arm64:check_mmap_options
11214 14:01:09.687522 arm64:check_prctl
11215 14:01:09.690427 arm64:check_tags_inclusion
11216 14:01:09.690894 arm64:check_user_mem
11217 14:01:09.693646 arm64:btitest
11218 14:01:09.694157 arm64:nobtitest
11219 14:01:09.697022 arm64:hwcap
11220 14:01:09.697443 arm64:ptrace
11221 14:01:09.697777 arm64:syscall-abi
11222 14:01:09.700314 arm64:tpidr2
11223 14:01:09.703728 ===========End Tests to run ===============
11224 14:01:09.706940 shardfile-arm64 pass
11225 14:01:09.971598 <12>[ 36.234271] kselftest: Running tests in arm64
11226 14:01:09.981289 TAP version 13
11227 14:01:09.993377 1..48
11228 14:01:10.008488 # selftests: arm64: tags_test
11229 14:01:10.464733 ok 1 selftests: arm64: tags_test
11230 14:01:10.484660 # selftests: arm64: run_tags_test.sh
11231 14:01:10.538452 # --------------------
11232 14:01:10.541169 # running tags test
11233 14:01:10.541642 # --------------------
11234 14:01:10.544751 # [PASS]
11235 14:01:10.548139 ok 2 selftests: arm64: run_tags_test.sh
11236 14:01:10.561242 # selftests: arm64: fake_sigreturn_bad_magic
11237 14:01:10.623179 # Registered handlers for all signals.
11238 14:01:10.623760 # Detected MINSTKSIGSZ:4720
11239 14:01:10.626548 # Testcase initialized.
11240 14:01:10.629841 # uc context validated.
11241 14:01:10.632963 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11242 14:01:10.636468 # Handled SIG_COPYCTX
11243 14:01:10.636963 # Available space:3568
11244 14:01:10.643114 # Using badly built context - ERR: BAD MAGIC !
11245 14:01:10.649642 # SIG_OK -- SP:0xFFFFE2B6F330 si_addr@:0xffffe2b6f330 si_code:2 token@:0xffffe2b6e0d0 offset:-4704
11246 14:01:10.652740 # ==>> completed. PASS(1)
11247 14:01:10.659537 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11248 14:01:10.666238 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE2B6E0D0
11249 14:01:10.669563 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11250 14:01:10.676131 # selftests: arm64: fake_sigreturn_bad_size
11251 14:01:10.709210 # Registered handlers for all signals.
11252 14:01:10.709789 # Detected MINSTKSIGSZ:4720
11253 14:01:10.712487 # Testcase initialized.
11254 14:01:10.715875 # uc context validated.
11255 14:01:10.719407 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11256 14:01:10.722932 # Handled SIG_COPYCTX
11257 14:01:10.723404 # Available space:3568
11258 14:01:10.725832 # uc context validated.
11259 14:01:10.732250 # Using badly built context - ERR: Bad size for esr_context
11260 14:01:10.739169 # SIG_OK -- SP:0xFFFFC6012610 si_addr@:0xffffc6012610 si_code:2 token@:0xffffc60113b0 offset:-4704
11261 14:01:10.742406 # ==>> completed. PASS(1)
11262 14:01:10.748893 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11263 14:01:10.755930 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC60113B0
11264 14:01:10.759179 ok 4 selftests: arm64: fake_sigreturn_bad_size
11265 14:01:10.765644 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11266 14:01:10.778283 # Registered handlers for all signals.
11267 14:01:10.778930 # Detected MINSTKSIGSZ:4720
11268 14:01:10.781485 # Testcase initialized.
11269 14:01:10.785196 # uc context validated.
11270 14:01:10.788337 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11271 14:01:10.791453 # Handled SIG_COPYCTX
11272 14:01:10.791878 # Available space:3568
11273 14:01:10.798201 # Using badly built context - ERR: Bad size for terminator
11274 14:01:10.807945 # SIG_OK -- SP:0xFFFFEA655E40 si_addr@:0xffffea655e40 si_code:2 token@:0xffffea654be0 offset:-4704
11275 14:01:10.808377 # ==>> completed. PASS(1)
11276 14:01:10.818122 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11277 14:01:10.825097 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEA654BE0
11278 14:01:10.828032 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11279 14:01:10.834413 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11280 14:01:10.869278 # Registered handlers for all signals.
11281 14:01:10.869809 # Detected MINSTKSIGSZ:4720
11282 14:01:10.872980 # Testcase initialized.
11283 14:01:10.876168 # uc context validated.
11284 14:01:10.879316 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11285 14:01:10.882752 # Handled SIG_COPYCTX
11286 14:01:10.883308 # Available space:3568
11287 14:01:10.889519 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11288 14:01:10.898937 # SIG_OK -- SP:0xFFFFEC412700 si_addr@:0xffffec412700 si_code:2 token@:0xffffec4114a0 offset:-4704
11289 14:01:10.899037 # ==>> completed. PASS(1)
11290 14:01:10.908690 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11291 14:01:10.915504 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEC4114A0
11292 14:01:10.918905 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11293 14:01:10.922167 # selftests: arm64: fake_sigreturn_misaligned_sp
11294 14:01:10.948419 # Registered handlers for all signals.
11295 14:01:10.948681 # Detected MINSTKSIGSZ:4720
11296 14:01:10.951476 # Testcase initialized.
11297 14:01:10.954788 # uc context validated.
11298 14:01:10.958371 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11299 14:01:10.961272 # Handled SIG_COPYCTX
11300 14:01:10.968073 # SIG_OK -- SP:0xFFFFCF7CCDF3 si_addr@:0xffffcf7ccdf3 si_code:2 token@:0xffffcf7ccdf3 offset:0
11301 14:01:10.971622 # ==>> completed. PASS(1)
11302 14:01:10.978273 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11303 14:01:10.984893 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCF7CCDF3
11304 14:01:10.991786 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11305 14:01:10.994676 # selftests: arm64: fake_sigreturn_missing_fpsimd
11306 14:01:11.028241 # Registered handlers for all signals.
11307 14:01:11.028806 # Detected MINSTKSIGSZ:4720
11308 14:01:11.031534 # Testcase initialized.
11309 14:01:11.034707 # uc context validated.
11310 14:01:11.037809 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11311 14:01:11.041243 # Handled SIG_COPYCTX
11312 14:01:11.044782 # Mangling template header. Spare space:4096
11313 14:01:11.047887 # Using badly built context - ERR: Missing FPSIMD
11314 14:01:11.057741 # SIG_OK -- SP:0xFFFFE48FAF50 si_addr@:0xffffe48faf50 si_code:2 token@:0xffffe48f9cf0 offset:-4704
11315 14:01:11.060898 # ==>> completed. PASS(1)
11316 14:01:11.067835 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11317 14:01:11.074424 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE48F9CF0
11318 14:01:11.077646 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11319 14:01:11.084058 # selftests: arm64: fake_sigreturn_sme_change_vl
11320 14:01:11.102788 # Registered handlers for all signals.
11321 14:01:11.103525 # Detected MINSTKSIGSZ:4720
11322 14:01:11.105825 # ==>> completed. SKIP.
11323 14:01:11.112529 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11324 14:01:11.115792 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11325 14:01:11.124241 # selftests: arm64: fake_sigreturn_sve_change_vl
11326 14:01:11.181918 # Registered handlers for all signals.
11327 14:01:11.182571 # Detected MINSTKSIGSZ:4720
11328 14:01:11.185319 # ==>> completed. SKIP.
11329 14:01:11.188708 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11330 14:01:11.195225 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11331 14:01:11.205412 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11332 14:01:11.274659 # Registered handlers for all signals.
11333 14:01:11.275243 # Detected MINSTKSIGSZ:4720
11334 14:01:11.278239 # Testcase initialized.
11335 14:01:11.281309 # uc context validated.
11336 14:01:11.281793 # Handled SIG_TRIG
11337 14:01:11.291184 # SIG_OK -- SP:0xFFFFC9F8A0B0 si_addr@:0xffffc9f8a0b0 si_code:2 token@:(nil) offset:-281474070257840
11338 14:01:11.294728 # ==>> completed. PASS(1)
11339 14:01:11.301106 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11340 14:01:11.308132 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11341 14:01:11.310936 # selftests: arm64: mangle_pstate_invalid_daif_bits
11342 14:01:11.358610 # Registered handlers for all signals.
11343 14:01:11.359351 # Detected MINSTKSIGSZ:4720
11344 14:01:11.361687 # Testcase initialized.
11345 14:01:11.365613 # uc context validated.
11346 14:01:11.366390 # Handled SIG_TRIG
11347 14:01:11.375542 # SIG_OK -- SP:0xFFFFDB44A0B0 si_addr@:0xffffdb44a0b0 si_code:2 token@:(nil) offset:-281474360451248
11348 14:01:11.378800 # ==>> completed. PASS(1)
11349 14:01:11.385052 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11350 14:01:11.388711 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11351 14:01:11.395186 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11352 14:01:11.436240 # Registered handlers for all signals.
11353 14:01:11.436934 # Detected MINSTKSIGSZ:4720
11354 14:01:11.439582 # Testcase initialized.
11355 14:01:11.443025 # uc context validated.
11356 14:01:11.443707 # Handled SIG_TRIG
11357 14:01:11.452873 # SIG_OK -- SP:0xFFFFE9AA8720 si_addr@:0xffffe9aa8720 si_code:2 token@:(nil) offset:-281474602010400
11358 14:01:11.456529 # ==>> completed. PASS(1)
11359 14:01:11.462903 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11360 14:01:11.466337 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11361 14:01:11.472700 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11362 14:01:11.511737 # Registered handlers for all signals.
11363 14:01:11.512259 # Detected MINSTKSIGSZ:4720
11364 14:01:11.515312 # Testcase initialized.
11365 14:01:11.518484 # uc context validated.
11366 14:01:11.518799 # Handled SIG_TRIG
11367 14:01:11.528143 # SIG_OK -- SP:0xFFFFF7FDF500 si_addr@:0xfffff7fdf500 si_code:2 token@:(nil) offset:-281474842359040
11368 14:01:11.531476 # ==>> completed. PASS(1)
11369 14:01:11.537842 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11370 14:01:11.541232 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11371 14:01:11.547956 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11372 14:01:11.572745 # Registered handlers for all signals.
11373 14:01:11.572833 # Detected MINSTKSIGSZ:4720
11374 14:01:11.575952 # Testcase initialized.
11375 14:01:11.579321 # uc context validated.
11376 14:01:11.579407 # Handled SIG_TRIG
11377 14:01:11.589511 # SIG_OK -- SP:0xFFFFCEC39820 si_addr@:0xffffcec39820 si_code:2 token@:(nil) offset:-281474150668320
11378 14:01:11.592585 # ==>> completed. PASS(1)
11379 14:01:11.599126 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11380 14:01:11.602516 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11381 14:01:11.608945 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11382 14:01:11.645700 # Registered handlers for all signals.
11383 14:01:11.646184 # Detected MINSTKSIGSZ:4720
11384 14:01:11.649066 # Testcase initialized.
11385 14:01:11.652492 # uc context validated.
11386 14:01:11.652915 # Handled SIG_TRIG
11387 14:01:11.662420 # SIG_OK -- SP:0xFFFFC58C29A0 si_addr@:0xffffc58c29a0 si_code:2 token@:(nil) offset:-281473996040608
11388 14:01:11.665996 # ==>> completed. PASS(1)
11389 14:01:11.672309 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11390 14:01:11.675777 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11391 14:01:11.682335 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11392 14:01:11.737553 # Registered handlers for all signals.
11393 14:01:11.738171 # Detected MINSTKSIGSZ:4720
11394 14:01:11.740852 # Testcase initialized.
11395 14:01:11.744156 # uc context validated.
11396 14:01:11.744734 # Handled SIG_TRIG
11397 14:01:11.753722 # SIG_OK -- SP:0xFFFFFEAAD910 si_addr@:0xfffffeaad910 si_code:2 token@:(nil) offset:-281474954352912
11398 14:01:11.757067 # ==>> completed. PASS(1)
11399 14:01:11.763606 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11400 14:01:11.766741 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11401 14:01:11.773360 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11402 14:01:11.817649 # Registered handlers for all signals.
11403 14:01:11.818233 # Detected MINSTKSIGSZ:4720
11404 14:01:11.820979 # Testcase initialized.
11405 14:01:11.824384 # uc context validated.
11406 14:01:11.824804 # Handled SIG_TRIG
11407 14:01:11.834411 # SIG_OK -- SP:0xFFFFD3FC4190 si_addr@:0xffffd3fc4190 si_code:2 token@:(nil) offset:-281474238267792
11408 14:01:11.837684 # ==>> completed. PASS(1)
11409 14:01:11.844225 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11410 14:01:11.847479 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11411 14:01:11.853601 # selftests: arm64: sme_trap_no_sm
11412 14:01:11.898951 # Registered handlers for all signals.
11413 14:01:11.899503 # Detected MINSTKSIGSZ:4720
11414 14:01:11.902452 # ==>> completed. SKIP.
11415 14:01:11.912305 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11416 14:01:11.915258 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11417 14:01:11.918685 # selftests: arm64: sme_trap_non_streaming
11418 14:01:11.975800 # Registered handlers for all signals.
11419 14:01:11.976351 # Detected MINSTKSIGSZ:4720
11420 14:01:11.979032 # ==>> completed. SKIP.
11421 14:01:11.989015 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11422 14:01:11.995831 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11423 14:01:11.998986 # selftests: arm64: sme_trap_za
11424 14:01:12.052806 # Registered handlers for all signals.
11425 14:01:12.053381 # Detected MINSTKSIGSZ:4720
11426 14:01:12.056296 # Testcase initialized.
11427 14:01:12.066085 # SIG_OK -- SP:0xFFFFD9FC38B0 si_addr@:0xaaaae1d52510 si_code:1 token@:(nil) offset:-187650910004496
11428 14:01:12.066559 # ==>> completed. PASS(1)
11429 14:01:12.076280 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11430 14:01:12.076748 ok 21 selftests: arm64: sme_trap_za
11431 14:01:12.079435 # selftests: arm64: sme_vl
11432 14:01:12.125983 # Registered handlers for all signals.
11433 14:01:12.126541 # Detected MINSTKSIGSZ:4720
11434 14:01:12.129623 # ==>> completed. SKIP.
11435 14:01:12.136179 # # SME VL :: Check that we get the right SME VL reported
11436 14:01:12.139238 ok 22 selftests: arm64: sme_vl # SKIP
11437 14:01:12.142669 # selftests: arm64: ssve_regs
11438 14:01:12.196349 # Registered handlers for all signals.
11439 14:01:12.196926 # Detected MINSTKSIGSZ:4720
11440 14:01:12.199574 # ==>> completed. SKIP.
11441 14:01:12.205666 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11442 14:01:12.212315 ok 23 selftests: arm64: ssve_regs # SKIP
11443 14:01:12.212788 # selftests: arm64: sve_regs
11444 14:01:12.284079 # Registered handlers for all signals.
11445 14:01:12.284671 # Detected MINSTKSIGSZ:4720
11446 14:01:12.287861 # ==>> completed. SKIP.
11447 14:01:12.294378 # # SVE registers :: Check that we get the right SVE registers reported
11448 14:01:12.297777 ok 24 selftests: arm64: sve_regs # SKIP
11449 14:01:12.307852 # selftests: arm64: sve_vl
11450 14:01:12.373543 # Registered handlers for all signals.
11451 14:01:12.374260 # Detected MINSTKSIGSZ:4720
11452 14:01:12.376489 # ==>> completed. SKIP.
11453 14:01:12.383076 # # SVE VL :: Check that we get the right SVE VL reported
11454 14:01:12.386108 ok 25 selftests: arm64: sve_vl # SKIP
11455 14:01:12.389428 # selftests: arm64: za_no_regs
11456 14:01:12.446608 # Registered handlers for all signals.
11457 14:01:12.447191 # Detected MINSTKSIGSZ:4720
11458 14:01:12.450006 # ==>> completed. SKIP.
11459 14:01:12.456399 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11460 14:01:12.459815 ok 26 selftests: arm64: za_no_regs # SKIP
11461 14:01:12.464168 # selftests: arm64: za_regs
11462 14:01:12.521592 # Registered handlers for all signals.
11463 14:01:12.522269 # Detected MINSTKSIGSZ:4720
11464 14:01:12.524728 # ==>> completed. SKIP.
11465 14:01:12.531475 # # ZA register :: Check that we get the right ZA registers reported
11466 14:01:12.534315 ok 27 selftests: arm64: za_regs # SKIP
11467 14:01:12.539286 # selftests: arm64: pac
11468 14:01:12.581361 # TAP version 13
11469 14:01:12.581988 # 1..7
11470 14:01:12.584455 # # Starting 7 tests from 1 test cases.
11471 14:01:12.587878 # # RUN global.corrupt_pac ...
11472 14:01:12.590923 # # SKIP PAUTH not enabled
11473 14:01:12.594215 # # OK global.corrupt_pac
11474 14:01:12.597321 # ok 1 # SKIP PAUTH not enabled
11475 14:01:12.604305 # # RUN global.pac_instructions_not_nop ...
11476 14:01:12.607660 # # SKIP PAUTH not enabled
11477 14:01:12.610680 # # OK global.pac_instructions_not_nop
11478 14:01:12.614073 # ok 2 # SKIP PAUTH not enabled
11479 14:01:12.620615 # # RUN global.pac_instructions_not_nop_generic ...
11480 14:01:12.623934 # # SKIP Generic PAUTH not enabled
11481 14:01:12.627057 # # OK global.pac_instructions_not_nop_generic
11482 14:01:12.630558 # ok 3 # SKIP Generic PAUTH not enabled
11483 14:01:12.637375 # # RUN global.single_thread_different_keys ...
11484 14:01:12.640663 # # SKIP PAUTH not enabled
11485 14:01:12.647386 # # OK global.single_thread_different_keys
11486 14:01:12.647819 # ok 4 # SKIP PAUTH not enabled
11487 14:01:12.653922 # # RUN global.exec_changed_keys ...
11488 14:01:12.657492 # # SKIP PAUTH not enabled
11489 14:01:12.660738 # # OK global.exec_changed_keys
11490 14:01:12.663653 # ok 5 # SKIP PAUTH not enabled
11491 14:01:12.667258 # # RUN global.context_switch_keep_keys ...
11492 14:01:12.670314 # # SKIP PAUTH not enabled
11493 14:01:12.677012 # # OK global.context_switch_keep_keys
11494 14:01:12.677581 # ok 6 # SKIP PAUTH not enabled
11495 14:01:12.683759 # # RUN global.context_switch_keep_keys_generic ...
11496 14:01:12.686650 # # SKIP Generic PAUTH not enabled
11497 14:01:12.693484 # # OK global.context_switch_keep_keys_generic
11498 14:01:12.696972 # ok 7 # SKIP Generic PAUTH not enabled
11499 14:01:12.699890 # # PASSED: 7 / 7 tests passed.
11500 14:01:12.703400 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11501 14:01:12.706666 ok 28 selftests: arm64: pac
11502 14:01:12.710168 # selftests: arm64: fp-stress
11503 14:01:19.754805 <6>[ 46.021648] vpu: disabling
11504 14:01:19.758030 <6>[ 46.024694] vproc2: disabling
11505 14:01:19.761521 <6>[ 46.027966] vproc1: disabling
11506 14:01:19.764787 <6>[ 46.031237] vaud18: disabling
11507 14:01:19.771322 <6>[ 46.034651] vsram_others: disabling
11508 14:01:19.771900 <6>[ 46.038531] va09: disabling
11509 14:01:19.778241 <6>[ 46.041644] vsram_md: disabling
11510 14:01:19.778821 <6>[ 46.045134] Vgpu: disabling
11511 14:01:22.635927 # TAP version 13
11512 14:01:22.636498 # 1..16
11513 14:01:22.639074 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11514 14:01:22.642260 # # Will run for 10s
11515 14:01:22.642734 # # Started FPSIMD-0-0
11516 14:01:22.645586 # # Started FPSIMD-0-1
11517 14:01:22.648947 # # Started FPSIMD-1-0
11518 14:01:22.649422 # # Started FPSIMD-1-1
11519 14:01:22.652203 # # Started FPSIMD-2-0
11520 14:01:22.652677 # # Started FPSIMD-2-1
11521 14:01:22.655378 # # Started FPSIMD-3-0
11522 14:01:22.658726 # # Started FPSIMD-3-1
11523 14:01:22.659299 # # Started FPSIMD-4-0
11524 14:01:22.662103 # # Started FPSIMD-4-1
11525 14:01:22.665493 # # Started FPSIMD-5-0
11526 14:01:22.665980 # # Started FPSIMD-5-1
11527 14:01:22.668723 # # Started FPSIMD-6-0
11528 14:01:22.669327 # # Started FPSIMD-6-1
11529 14:01:22.672021 # # Started FPSIMD-7-0
11530 14:01:22.675515 # # Started FPSIMD-7-1
11531 14:01:22.678959 # # FPSIMD-0-0: Vector length: 128 bits
11532 14:01:22.682206 # # FPSIMD-0-0: PID: 1164
11533 14:01:22.685239 # # FPSIMD-0-1: Vector length: 128 bits
11534 14:01:22.685717 # # FPSIMD-0-1: PID: 1165
11535 14:01:22.688886 # # FPSIMD-1-1: Vector length: 128 bits
11536 14:01:22.692348 # # FPSIMD-1-1: PID: 1167
11537 14:01:22.695060 # # FPSIMD-2-0: Vector length: 128 bits
11538 14:01:22.698781 # # FPSIMD-2-0: PID: 1168
11539 14:01:22.702017 # # FPSIMD-2-1: Vector length: 128 bits
11540 14:01:22.705163 # # FPSIMD-2-1: PID: 1169
11541 14:01:22.708472 # # FPSIMD-4-1: Vector length: 128 bits
11542 14:01:22.709056 # # FPSIMD-4-1: PID: 1173
11543 14:01:22.715165 # # FPSIMD-5-0: Vector length: 128 bits
11544 14:01:22.715641 # # FPSIMD-5-0: PID: 1174
11545 14:01:22.718175 # # FPSIMD-7-0: Vector length: 128 bits
11546 14:01:22.721516 # # FPSIMD-7-0: PID: 1178
11547 14:01:22.724946 # # FPSIMD-6-0: Vector length: 128 bits
11548 14:01:22.728802 # # FPSIMD-6-0: PID: 1176
11549 14:01:22.731870 # # FPSIMD-5-1: Vector length: 128 bits
11550 14:01:22.735046 # # FPSIMD-5-1: PID: 1175
11551 14:01:22.738116 # # FPSIMD-1-0: Vector length: 128 bits
11552 14:01:22.738582 # # FPSIMD-1-0: PID: 1166
11553 14:01:22.741364 # # FPSIMD-3-1: Vector length: 128 bits
11554 14:01:22.744579 # # FPSIMD-3-1: PID: 1171
11555 14:01:22.747985 # # FPSIMD-4-0: Vector length: 128 bits
11556 14:01:22.751392 # # FPSIMD-4-0: PID: 1172
11557 14:01:22.754798 # # FPSIMD-3-0: Vector length: 128 bits
11558 14:01:22.757833 # # FPSIMD-3-0: PID: 1170
11559 14:01:22.761460 # # FPSIMD-7-1: Vector length: 128 bits
11560 14:01:22.764869 # # FPSIMD-7-1: PID: 1179
11561 14:01:22.767802 # # FPSIMD-6-1: Vector length: 128 bits
11562 14:01:22.768407 # # FPSIMD-6-1: PID: 1177
11563 14:01:22.771165 # # Finishing up...
11564 14:01:22.771624 # ok 1 FPSIMD-0-0
11565 14:01:22.774311 # ok 2 FPSIMD-0-1
11566 14:01:22.774739 # ok 3 FPSIMD-1-0
11567 14:01:22.777839 # ok 4 FPSIMD-1-1
11568 14:01:22.778316 # ok 5 FPSIMD-2-0
11569 14:01:22.781499 # ok 6 FPSIMD-2-1
11570 14:01:22.782072 # ok 7 FPSIMD-3-0
11571 14:01:22.784620 # ok 8 FPSIMD-3-1
11572 14:01:22.785162 # ok 9 FPSIMD-4-0
11573 14:01:22.788007 # ok 10 FPSIMD-4-1
11574 14:01:22.788558 # ok 11 FPSIMD-5-0
11575 14:01:22.790974 # ok 12 FPSIMD-5-1
11576 14:01:22.791404 # ok 13 FPSIMD-6-0
11577 14:01:22.794295 # ok 14 FPSIMD-6-1
11578 14:01:22.797526 # ok 15 FPSIMD-7-0
11579 14:01:22.797972 # ok 16 FPSIMD-7-1
11580 14:01:22.804718 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=997216, signals=10
11581 14:01:22.810982 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1122880, signals=10
11582 14:01:22.820914 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1435867, signals=10
11583 14:01:22.827682 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1401879, signals=10
11584 14:01:22.834258 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1322129, signals=10
11585 14:01:22.840560 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1168461, signals=10
11586 14:01:22.847308 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1936890, signals=10
11587 14:01:22.854021 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1374253, signals=9
11588 14:01:22.864124 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1073049, signals=9
11589 14:01:22.870782 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1279422, signals=10
11590 14:01:22.877385 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=976053, signals=10
11591 14:01:22.884112 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1475414, signals=10
11592 14:01:22.890438 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1078912, signals=10
11593 14:01:22.896808 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1355478, signals=10
11594 14:01:22.906950 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1360267, signals=10
11595 14:01:22.913614 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1159679, signals=9
11596 14:01:22.916880 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11597 14:01:22.920230 ok 29 selftests: arm64: fp-stress
11598 14:01:22.923892 # selftests: arm64: sve-ptrace
11599 14:01:22.924426 # TAP version 13
11600 14:01:22.926768 # 1..4104
11601 14:01:22.930552 # ok 2 # SKIP SVE not available
11602 14:01:22.933603 # # Planned tests != run tests (4104 != 1)
11603 14:01:22.937140 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11604 14:01:22.940514 ok 30 selftests: arm64: sve-ptrace # SKIP
11605 14:01:22.943623 # selftests: arm64: sve-probe-vls
11606 14:01:22.946892 # TAP version 13
11607 14:01:22.947489 # 1..2
11608 14:01:22.950082 # ok 2 # SKIP SVE not available
11609 14:01:22.953515 # # Planned tests != run tests (2 != 1)
11610 14:01:22.956529 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11611 14:01:22.963367 ok 31 selftests: arm64: sve-probe-vls # SKIP
11612 14:01:22.966453 # selftests: arm64: vec-syscfg
11613 14:01:22.967006 # TAP version 13
11614 14:01:22.967557 # 1..20
11615 14:01:22.969823 # ok 1 # SKIP SVE not supported
11616 14:01:22.973368 # ok 2 # SKIP SVE not supported
11617 14:01:22.976360 # ok 3 # SKIP SVE not supported
11618 14:01:22.979791 # ok 4 # SKIP SVE not supported
11619 14:01:22.982895 # ok 5 # SKIP SVE not supported
11620 14:01:22.983424 # ok 6 # SKIP SVE not supported
11621 14:01:22.986289 # ok 7 # SKIP SVE not supported
11622 14:01:22.989554 # ok 8 # SKIP SVE not supported
11623 14:01:22.992885 # ok 9 # SKIP SVE not supported
11624 14:01:22.996162 # ok 10 # SKIP SVE not supported
11625 14:01:22.999492 # ok 11 # SKIP SME not supported
11626 14:01:23.003110 # ok 12 # SKIP SME not supported
11627 14:01:23.006462 # ok 13 # SKIP SME not supported
11628 14:01:23.006931 # ok 14 # SKIP SME not supported
11629 14:01:23.009653 # ok 15 # SKIP SME not supported
11630 14:01:23.013013 # ok 16 # SKIP SME not supported
11631 14:01:23.016019 # ok 17 # SKIP SME not supported
11632 14:01:23.019579 # ok 18 # SKIP SME not supported
11633 14:01:23.023118 # ok 19 # SKIP SME not supported
11634 14:01:23.026152 # ok 20 # SKIP SME not supported
11635 14:01:23.029463 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11636 14:01:23.032723 ok 32 selftests: arm64: vec-syscfg
11637 14:01:23.036165 # selftests: arm64: za-fork
11638 14:01:23.039716 # TAP version 13
11639 14:01:23.040283 # 1..1
11640 14:01:23.040656 # # PID: 1254
11641 14:01:23.042583 # # SME support not present
11642 14:01:23.043048 # ok 0 skipped
11643 14:01:23.049397 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11644 14:01:23.052943 ok 33 selftests: arm64: za-fork
11645 14:01:23.055635 # selftests: arm64: za-ptrace
11646 14:01:23.056108 # TAP version 13
11647 14:01:23.056477 # 1..1
11648 14:01:23.058947 # ok 2 # SKIP SME not available
11649 14:01:23.065817 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11650 14:01:23.068969 ok 34 selftests: arm64: za-ptrace # SKIP
11651 14:01:23.072039 # selftests: arm64: check_buffer_fill
11652 14:01:23.129347 # # SKIP: MTE features unavailable
11653 14:01:23.137220 ok 35 selftests: arm64: check_buffer_fill # SKIP
11654 14:01:23.156721 # selftests: arm64: check_child_memory
11655 14:01:23.217773 # # SKIP: MTE features unavailable
11656 14:01:23.225127 ok 36 selftests: arm64: check_child_memory # SKIP
11657 14:01:23.242405 # selftests: arm64: check_gcr_el1_cswitch
11658 14:01:23.296108 # # SKIP: MTE features unavailable
11659 14:01:23.303722 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11660 14:01:23.320494 # selftests: arm64: check_ksm_options
11661 14:01:23.388012 # # SKIP: MTE features unavailable
11662 14:01:23.396872 ok 38 selftests: arm64: check_ksm_options # SKIP
11663 14:01:23.416271 # selftests: arm64: check_mmap_options
11664 14:01:23.454008 # # SKIP: MTE features unavailable
11665 14:01:23.461638 ok 39 selftests: arm64: check_mmap_options # SKIP
11666 14:01:23.476964 # selftests: arm64: check_prctl
11667 14:01:23.531509 # TAP version 13
11668 14:01:23.532141 # 1..5
11669 14:01:23.534759 # ok 1 check_basic_read
11670 14:01:23.535232 # ok 2 NONE
11671 14:01:23.538284 # ok 3 # SKIP SYNC
11672 14:01:23.538759 # ok 4 # SKIP ASYNC
11673 14:01:23.541579 # ok 5 # SKIP SYNC+ASYNC
11674 14:01:23.544654 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11675 14:01:23.548123 ok 40 selftests: arm64: check_prctl
11676 14:01:23.554467 # selftests: arm64: check_tags_inclusion
11677 14:01:23.610799 # # SKIP: MTE features unavailable
11678 14:01:23.618783 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11679 14:01:23.629673 # selftests: arm64: check_user_mem
11680 14:01:23.698035 # # SKIP: MTE features unavailable
11681 14:01:23.705745 ok 42 selftests: arm64: check_user_mem # SKIP
11682 14:01:23.719025 # selftests: arm64: btitest
11683 14:01:23.776259 # TAP version 13
11684 14:01:23.776826 # 1..18
11685 14:01:23.779960 # # HWCAP_PACA not present
11686 14:01:23.783316 # # HWCAP2_BTI not present
11687 14:01:23.783956 # # Test binary built for BTI
11688 14:01:23.789552 # ok 1 nohint_func/call_using_br_x0 # SKIP
11689 14:01:23.792765 # ok 1 nohint_func/call_using_br_x16 # SKIP
11690 14:01:23.796007 # ok 1 nohint_func/call_using_blr # SKIP
11691 14:01:23.799667 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11692 14:01:23.802515 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11693 14:01:23.809331 # ok 1 bti_none_func/call_using_blr # SKIP
11694 14:01:23.812484 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11695 14:01:23.816145 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11696 14:01:23.819217 # ok 1 bti_c_func/call_using_blr # SKIP
11697 14:01:23.822626 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11698 14:01:23.825838 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11699 14:01:23.829087 # ok 1 bti_j_func/call_using_blr # SKIP
11700 14:01:23.832496 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11701 14:01:23.839238 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11702 14:01:23.842486 # ok 1 bti_jc_func/call_using_blr # SKIP
11703 14:01:23.845546 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11704 14:01:23.849297 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11705 14:01:23.852105 # ok 1 paciasp_func/call_using_blr # SKIP
11706 14:01:23.858763 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11707 14:01:23.862083 # # WARNING - EXPECTED TEST COUNT WRONG
11708 14:01:23.865920 ok 43 selftests: arm64: btitest
11709 14:01:23.866540 # selftests: arm64: nobtitest
11710 14:01:23.868968 # TAP version 13
11711 14:01:23.869532 # 1..18
11712 14:01:23.872655 # # HWCAP_PACA not present
11713 14:01:23.875402 # # HWCAP2_BTI not present
11714 14:01:23.878832 # # Test binary not built for BTI
11715 14:01:23.882012 # ok 1 nohint_func/call_using_br_x0 # SKIP
11716 14:01:23.885704 # ok 1 nohint_func/call_using_br_x16 # SKIP
11717 14:01:23.888775 # ok 1 nohint_func/call_using_blr # SKIP
11718 14:01:23.891838 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11719 14:01:23.895216 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11720 14:01:23.901796 # ok 1 bti_none_func/call_using_blr # SKIP
11721 14:01:23.905062 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11722 14:01:23.908455 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11723 14:01:23.911844 # ok 1 bti_c_func/call_using_blr # SKIP
11724 14:01:23.915533 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11725 14:01:23.918400 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11726 14:01:23.922356 # ok 1 bti_j_func/call_using_blr # SKIP
11727 14:01:23.925338 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11728 14:01:23.931644 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11729 14:01:23.935515 # ok 1 bti_jc_func/call_using_blr # SKIP
11730 14:01:23.938691 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11731 14:01:23.942316 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11732 14:01:23.945250 # ok 1 paciasp_func/call_using_blr # SKIP
11733 14:01:23.951558 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11734 14:01:23.955351 # # WARNING - EXPECTED TEST COUNT WRONG
11735 14:01:23.958159 ok 44 selftests: arm64: nobtitest
11736 14:01:23.958785 # selftests: arm64: hwcap
11737 14:01:23.961421 # TAP version 13
11738 14:01:23.961888 # 1..28
11739 14:01:23.964857 # ok 1 cpuinfo_match_RNG
11740 14:01:23.968085 # # SIGILL reported for RNG
11741 14:01:23.968560 # ok 2 # SKIP sigill_RNG
11742 14:01:23.971755 # ok 3 cpuinfo_match_SME
11743 14:01:23.974913 # ok 4 sigill_SME
11744 14:01:23.975614 # ok 5 cpuinfo_match_SVE
11745 14:01:23.978061 # ok 6 sigill_SVE
11746 14:01:23.978643 # ok 7 cpuinfo_match_SVE 2
11747 14:01:23.981369 # # SIGILL reported for SVE 2
11748 14:01:23.984968 # ok 8 # SKIP sigill_SVE 2
11749 14:01:23.987934 # ok 9 cpuinfo_match_SVE AES
11750 14:01:23.991639 # # SIGILL reported for SVE AES
11751 14:01:23.992253 # ok 10 # SKIP sigill_SVE AES
11752 14:01:23.994703 # ok 11 cpuinfo_match_SVE2 PMULL
11753 14:01:23.998096 # # SIGILL reported for SVE2 PMULL
11754 14:01:24.001450 # ok 12 # SKIP sigill_SVE2 PMULL
11755 14:01:24.004568 # ok 13 cpuinfo_match_SVE2 BITPERM
11756 14:01:24.007864 # # SIGILL reported for SVE2 BITPERM
11757 14:01:24.011284 # ok 14 # SKIP sigill_SVE2 BITPERM
11758 14:01:24.014501 # ok 15 cpuinfo_match_SVE2 SHA3
11759 14:01:24.017655 # # SIGILL reported for SVE2 SHA3
11760 14:01:24.020997 # ok 16 # SKIP sigill_SVE2 SHA3
11761 14:01:24.024753 # ok 17 cpuinfo_match_SVE2 SM4
11762 14:01:24.025311 # # SIGILL reported for SVE2 SM4
11763 14:01:24.028176 # ok 18 # SKIP sigill_SVE2 SM4
11764 14:01:24.030982 # ok 19 cpuinfo_match_SVE2 I8MM
11765 14:01:24.034034 # # SIGILL reported for SVE2 I8MM
11766 14:01:24.037416 # ok 20 # SKIP sigill_SVE2 I8MM
11767 14:01:24.040831 # ok 21 cpuinfo_match_SVE2 F32MM
11768 14:01:24.044435 # # SIGILL reported for SVE2 F32MM
11769 14:01:24.048044 # ok 22 # SKIP sigill_SVE2 F32MM
11770 14:01:24.048640 # ok 23 cpuinfo_match_SVE2 F64MM
11771 14:01:24.051052 # # SIGILL reported for SVE2 F64MM
11772 14:01:24.054724 # ok 24 # SKIP sigill_SVE2 F64MM
11773 14:01:24.057663 # ok 25 cpuinfo_match_SVE2 BF16
11774 14:01:24.060898 # # SIGILL reported for SVE2 BF16
11775 14:01:24.064372 # ok 26 # SKIP sigill_SVE2 BF16
11776 14:01:24.067548 # ok 27 cpuinfo_match_SVE2 EBF16
11777 14:01:24.070906 # ok 28 # SKIP sigill_SVE2 EBF16
11778 14:01:24.074424 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11779 14:01:24.077725 ok 45 selftests: arm64: hwcap
11780 14:01:24.081282 # selftests: arm64: ptrace
11781 14:01:24.081866 # TAP version 13
11782 14:01:24.084568 # 1..7
11783 14:01:24.085167 # # Parent is 1496, child is 1497
11784 14:01:24.087536 # ok 1 read_tpidr_one
11785 14:01:24.090745 # ok 2 write_tpidr_one
11786 14:01:24.091216 # ok 3 verify_tpidr_one
11787 14:01:24.094300 # ok 4 count_tpidrs
11788 14:01:24.094766 # ok 5 tpidr2_write
11789 14:01:24.097506 # ok 6 tpidr2_read
11790 14:01:24.100590 # ok 7 write_tpidr_only
11791 14:01:24.104061 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11792 14:01:24.107300 ok 46 selftests: arm64: ptrace
11793 14:01:24.110633 # selftests: arm64: syscall-abi
11794 14:01:24.111104 # TAP version 13
11795 14:01:24.113821 # 1..2
11796 14:01:24.114332 # ok 1 getpid() FPSIMD
11797 14:01:24.117267 # ok 2 sched_yield() FPSIMD
11798 14:01:24.124063 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11799 14:01:24.124547 ok 47 selftests: arm64: syscall-abi
11800 14:01:24.127469 # selftests: arm64: tpidr2
11801 14:01:24.163177 # TAP version 13
11802 14:01:24.163745 # 1..5
11803 14:01:24.166444 # # PID: 1533
11804 14:01:24.167014 # # SME support not present
11805 14:01:24.169688 # ok 0 skipped, TPIDR2 not supported
11806 14:01:24.173139 # ok 1 skipped, TPIDR2 not supported
11807 14:01:24.176130 # ok 2 skipped, TPIDR2 not supported
11808 14:01:24.179948 # ok 3 skipped, TPIDR2 not supported
11809 14:01:24.183218 # ok 4 skipped, TPIDR2 not supported
11810 14:01:24.189721 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11811 14:01:24.192954 ok 48 selftests: arm64: tpidr2
11812 14:01:24.845323 arm64_tags_test pass
11813 14:01:24.848889 arm64_run_tags_test_sh pass
11814 14:01:24.851997 arm64_fake_sigreturn_bad_magic pass
11815 14:01:24.855204 arm64_fake_sigreturn_bad_size pass
11816 14:01:24.858782 arm64_fake_sigreturn_bad_size_for_magic0 pass
11817 14:01:24.861819 arm64_fake_sigreturn_duplicated_fpsimd pass
11818 14:01:24.865587 arm64_fake_sigreturn_misaligned_sp pass
11819 14:01:24.868488 arm64_fake_sigreturn_missing_fpsimd pass
11820 14:01:24.871817 arm64_fake_sigreturn_sme_change_vl skip
11821 14:01:24.878465 arm64_fake_sigreturn_sve_change_vl skip
11822 14:01:24.882099 arm64_mangle_pstate_invalid_compat_toggle pass
11823 14:01:24.885198 arm64_mangle_pstate_invalid_daif_bits pass
11824 14:01:24.888692 arm64_mangle_pstate_invalid_mode_el1h pass
11825 14:01:24.891991 arm64_mangle_pstate_invalid_mode_el1t pass
11826 14:01:24.895310 arm64_mangle_pstate_invalid_mode_el2h pass
11827 14:01:24.901935 arm64_mangle_pstate_invalid_mode_el2t pass
11828 14:01:24.904963 arm64_mangle_pstate_invalid_mode_el3h pass
11829 14:01:24.908295 arm64_mangle_pstate_invalid_mode_el3t pass
11830 14:01:24.911587 arm64_sme_trap_no_sm skip
11831 14:01:24.912155 arm64_sme_trap_non_streaming skip
11832 14:01:24.915255 arm64_sme_trap_za pass
11833 14:01:24.918475 arm64_sme_vl skip
11834 14:01:24.919055 arm64_ssve_regs skip
11835 14:01:24.921435 arm64_sve_regs skip
11836 14:01:24.921901 arm64_sve_vl skip
11837 14:01:24.924524 arm64_za_no_regs skip
11838 14:01:24.924990 arm64_za_regs skip
11839 14:01:24.928201 arm64_pac_pauth_not_enabled skip
11840 14:01:24.931130 arm64_pac_pauth_not_enabled skip
11841 14:01:24.934963 arm64_pac_generic_pauth_not_enabled skip
11842 14:01:24.938349 arm64_pac_pauth_not_enabled skip
11843 14:01:24.941596 arm64_pac_pauth_not_enabled skip
11844 14:01:24.944566 arm64_pac_pauth_not_enabled skip
11845 14:01:24.947798 arm64_pac_generic_pauth_not_enabled skip
11846 14:01:24.948272 arm64_pac pass
11847 14:01:24.950982 arm64_fp-stress_FPSIMD-0-0 pass
11848 14:01:24.954058 arm64_fp-stress_FPSIMD-0-1 pass
11849 14:01:24.957690 arm64_fp-stress_FPSIMD-1-0 pass
11850 14:01:24.961039 arm64_fp-stress_FPSIMD-1-1 pass
11851 14:01:24.964295 arm64_fp-stress_FPSIMD-2-0 pass
11852 14:01:24.967351 arm64_fp-stress_FPSIMD-2-1 pass
11853 14:01:24.970661 arm64_fp-stress_FPSIMD-3-0 pass
11854 14:01:24.971139 arm64_fp-stress_FPSIMD-3-1 pass
11855 14:01:24.974157 arm64_fp-stress_FPSIMD-4-0 pass
11856 14:01:24.977632 arm64_fp-stress_FPSIMD-4-1 pass
11857 14:01:24.980583 arm64_fp-stress_FPSIMD-5-0 pass
11858 14:01:24.983970 arm64_fp-stress_FPSIMD-5-1 pass
11859 14:01:24.987453 arm64_fp-stress_FPSIMD-6-0 pass
11860 14:01:24.990731 arm64_fp-stress_FPSIMD-6-1 pass
11861 14:01:24.991200 arm64_fp-stress_FPSIMD-7-0 pass
11862 14:01:24.994374 arm64_fp-stress_FPSIMD-7-1 pass
11863 14:01:24.997200 arm64_fp-stress pass
11864 14:01:25.000345 arm64_sve-ptrace_sve_not_available skip
11865 14:01:25.003749 arm64_sve-ptrace skip
11866 14:01:25.007032 arm64_sve-probe-vls_sve_not_available skip
11867 14:01:25.007275 arm64_sve-probe-vls skip
11868 14:01:25.010788 arm64_vec-syscfg_sve_not_supported skip
11869 14:01:25.016699 arm64_vec-syscfg_sve_not_supported skip
11870 14:01:25.020446 arm64_vec-syscfg_sve_not_supported skip
11871 14:01:25.024071 arm64_vec-syscfg_sve_not_supported skip
11872 14:01:25.027063 arm64_vec-syscfg_sve_not_supported skip
11873 14:01:25.030559 arm64_vec-syscfg_sve_not_supported skip
11874 14:01:25.033578 arm64_vec-syscfg_sve_not_supported skip
11875 14:01:25.036926 arm64_vec-syscfg_sve_not_supported skip
11876 14:01:25.040071 arm64_vec-syscfg_sve_not_supported skip
11877 14:01:25.043721 arm64_vec-syscfg_sve_not_supported skip
11878 14:01:25.047069 arm64_vec-syscfg_sme_not_supported skip
11879 14:01:25.050410 arm64_vec-syscfg_sme_not_supported skip
11880 14:01:25.053597 arm64_vec-syscfg_sme_not_supported skip
11881 14:01:25.057037 arm64_vec-syscfg_sme_not_supported skip
11882 14:01:25.063372 arm64_vec-syscfg_sme_not_supported skip
11883 14:01:25.066502 arm64_vec-syscfg_sme_not_supported skip
11884 14:01:25.069993 arm64_vec-syscfg_sme_not_supported skip
11885 14:01:25.073736 arm64_vec-syscfg_sme_not_supported skip
11886 14:01:25.077007 arm64_vec-syscfg_sme_not_supported skip
11887 14:01:25.079901 arm64_vec-syscfg_sme_not_supported skip
11888 14:01:25.083513 arm64_vec-syscfg pass
11889 14:01:25.084090 arm64_za-fork_skipped pass
11890 14:01:25.086838 arm64_za-fork pass
11891 14:01:25.089888 arm64_za-ptrace_sme_not_available skip
11892 14:01:25.090493 arm64_za-ptrace skip
11893 14:01:25.093035 arm64_check_buffer_fill skip
11894 14:01:25.096446 arm64_check_child_memory skip
11895 14:01:25.099709 arm64_check_gcr_el1_cswitch skip
11896 14:01:25.103129 arm64_check_ksm_options skip
11897 14:01:25.106716 arm64_check_mmap_options skip
11898 14:01:25.109853 arm64_check_prctl_check_basic_read pass
11899 14:01:25.110362 arm64_check_prctl_NONE pass
11900 14:01:25.112910 arm64_check_prctl_sync skip
11901 14:01:25.116616 arm64_check_prctl_async skip
11902 14:01:25.120005 arm64_check_prctl_sync_async skip
11903 14:01:25.120479 arm64_check_prctl pass
11904 14:01:25.123489 arm64_check_tags_inclusion skip
11905 14:01:25.126679 arm64_check_user_mem skip
11906 14:01:25.129814 arm64_btitest_nohint_func_call_using_br_x0 skip
11907 14:01:25.136093 arm64_btitest_nohint_func_call_using_br_x16 skip
11908 14:01:25.139390 arm64_btitest_nohint_func_call_using_blr skip
11909 14:01:25.143203 arm64_btitest_bti_none_func_call_using_br_x0 skip
11910 14:01:25.149810 arm64_btitest_bti_none_func_call_using_br_x16 skip
11911 14:01:25.153004 arm64_btitest_bti_none_func_call_using_blr skip
11912 14:01:25.156481 arm64_btitest_bti_c_func_call_using_br_x0 skip
11913 14:01:25.159724 arm64_btitest_bti_c_func_call_using_br_x16 skip
11914 14:01:25.166262 arm64_btitest_bti_c_func_call_using_blr skip
11915 14:01:25.169273 arm64_btitest_bti_j_func_call_using_br_x0 skip
11916 14:01:25.172537 arm64_btitest_bti_j_func_call_using_br_x16 skip
11917 14:01:25.176037 arm64_btitest_bti_j_func_call_using_blr skip
11918 14:01:25.182349 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11919 14:01:25.186041 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11920 14:01:25.188954 arm64_btitest_bti_jc_func_call_using_blr skip
11921 14:01:25.192470 arm64_btitest_paciasp_func_call_using_br_x0 skip
11922 14:01:25.199218 arm64_btitest_paciasp_func_call_using_br_x16 skip
11923 14:01:25.202412 arm64_btitest_paciasp_func_call_using_blr skip
11924 14:01:25.205695 arm64_btitest pass
11925 14:01:25.209124 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11926 14:01:25.212523 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11927 14:01:25.218847 arm64_nobtitest_nohint_func_call_using_blr skip
11928 14:01:25.222430 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11929 14:01:25.225291 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11930 14:01:25.232129 arm64_nobtitest_bti_none_func_call_using_blr skip
11931 14:01:25.235301 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11932 14:01:25.238777 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11933 14:01:25.245594 arm64_nobtitest_bti_c_func_call_using_blr skip
11934 14:01:25.248673 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11935 14:01:25.252289 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11936 14:01:25.258770 arm64_nobtitest_bti_j_func_call_using_blr skip
11937 14:01:25.261917 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11938 14:01:25.265367 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11939 14:01:25.271862 arm64_nobtitest_bti_jc_func_call_using_blr skip
11940 14:01:25.275266 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11941 14:01:25.278309 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11942 14:01:25.285149 arm64_nobtitest_paciasp_func_call_using_blr skip
11943 14:01:25.285574 arm64_nobtitest pass
11944 14:01:25.288310 arm64_hwcap_cpuinfo_match_RNG pass
11945 14:01:25.291861 arm64_hwcap_sigill_rng skip
11946 14:01:25.295190 arm64_hwcap_cpuinfo_match_SME pass
11947 14:01:25.298372 arm64_hwcap_sigill_SME pass
11948 14:01:25.301620 arm64_hwcap_cpuinfo_match_SVE pass
11949 14:01:25.302069 arm64_hwcap_sigill_SVE pass
11950 14:01:25.305021 arm64_hwcap_cpuinfo_match_SVE_2 pass
11951 14:01:25.308418 arm64_hwcap_sigill_sve_2 skip
11952 14:01:25.311567 arm64_hwcap_cpuinfo_match_SVE_AES pass
11953 14:01:25.314767 arm64_hwcap_sigill_sve_aes skip
11954 14:01:25.318016 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11955 14:01:25.321365 arm64_hwcap_sigill_sve2_pmull skip
11956 14:01:25.324683 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11957 14:01:25.327871 arm64_hwcap_sigill_sve2_bitperm skip
11958 14:01:25.331714 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11959 14:01:25.334711 arm64_hwcap_sigill_sve2_sha3 skip
11960 14:01:25.337783 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11961 14:01:25.341447 arm64_hwcap_sigill_sve2_sm4 skip
11962 14:01:25.344614 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11963 14:01:25.347985 arm64_hwcap_sigill_sve2_i8mm skip
11964 14:01:25.351212 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11965 14:01:25.354778 arm64_hwcap_sigill_sve2_f32mm skip
11966 14:01:25.358002 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11967 14:01:25.361370 arm64_hwcap_sigill_sve2_f64mm skip
11968 14:01:25.364632 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11969 14:01:25.368042 arm64_hwcap_sigill_sve2_bf16 skip
11970 14:01:25.371511 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11971 14:01:25.374915 arm64_hwcap_sigill_sve2_ebf16 skip
11972 14:01:25.378041 arm64_hwcap pass
11973 14:01:25.381403 arm64_ptrace_read_tpidr_one pass
11974 14:01:25.384602 arm64_ptrace_write_tpidr_one pass
11975 14:01:25.387932 arm64_ptrace_verify_tpidr_one pass
11976 14:01:25.388355 arm64_ptrace_count_tpidrs pass
11977 14:01:25.391123 arm64_ptrace_tpidr2_write pass
11978 14:01:25.394638 arm64_ptrace_tpidr2_read pass
11979 14:01:25.397679 arm64_ptrace_write_tpidr_only pass
11980 14:01:25.401261 arm64_ptrace pass
11981 14:01:25.404759 arm64_syscall-abi_getpid_FPSIMD pass
11982 14:01:25.407964 arm64_syscall-abi_sched_yield_FPSIMD pass
11983 14:01:25.408389 arm64_syscall-abi pass
11984 14:01:25.414249 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11985 14:01:25.417771 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11986 14:01:25.420664 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11987 14:01:25.424704 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11988 14:01:25.431337 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11989 14:01:25.431894 arm64_tpidr2 pass
11990 14:01:25.434231 + ../../utils/send-to-lava.sh ./output/result.txt
11991 14:01:25.440923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11992 14:01:25.441773 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11994 14:01:25.447573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11995 14:01:25.448300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11997 14:01:25.453562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11998 14:01:25.453814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12000 14:01:25.460747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12001 14:01:25.461004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12003 14:01:25.484274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12004 14:01:25.484591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12006 14:01:25.540387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12007 14:01:25.541069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12009 14:01:25.588912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12010 14:01:25.589580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12012 14:01:25.637542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12013 14:01:25.638253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12015 14:01:25.693762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12016 14:01:25.694474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12018 14:01:25.744049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12019 14:01:25.744325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12021 14:01:25.803944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12022 14:01:25.804658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12024 14:01:25.861678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12025 14:01:25.862474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12027 14:01:25.912924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12028 14:01:25.913198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12030 14:01:25.959612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12031 14:01:25.960139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12033 14:01:26.016988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12034 14:01:26.017682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12036 14:01:26.078222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12037 14:01:26.079046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12039 14:01:26.133284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12040 14:01:26.134009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12042 14:01:26.193422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12043 14:01:26.194104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12045 14:01:26.255062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12046 14:01:26.255747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12048 14:01:26.308605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12049 14:01:26.309339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12051 14:01:26.370507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12053 14:01:26.373520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12054 14:01:26.422489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12055 14:01:26.423159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12057 14:01:26.469908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12058 14:01:26.470628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12060 14:01:26.520809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12061 14:01:26.521113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12063 14:01:26.571320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12064 14:01:26.572012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12066 14:01:26.632336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12067 14:01:26.633002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12069 14:01:26.680798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12070 14:01:26.681089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12072 14:01:26.727634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12073 14:01:26.727898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12075 14:01:26.777975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12077 14:01:26.780861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12078 14:01:26.829850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12080 14:01:26.832419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12081 14:01:26.887931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12082 14:01:26.888208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12084 14:01:26.940669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12086 14:01:26.943436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12087 14:01:26.982043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12089 14:01:26.985142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12090 14:01:27.038155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12092 14:01:27.041446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12093 14:01:27.091029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12094 14:01:27.091770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12096 14:01:27.153266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12097 14:01:27.153983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12099 14:01:27.215357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12100 14:01:27.216075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12102 14:01:27.275613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12103 14:01:27.276289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12105 14:01:27.335190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12106 14:01:27.335933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12108 14:01:27.379206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12109 14:01:27.379467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12111 14:01:27.419695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12112 14:01:27.420362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12114 14:01:27.466208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12115 14:01:27.466551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12117 14:01:27.520806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12118 14:01:27.521528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12120 14:01:27.571299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12121 14:01:27.572038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12123 14:01:27.630113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12124 14:01:27.630415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12126 14:01:27.684394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12127 14:01:27.685148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12129 14:01:27.732111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12130 14:01:27.732373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12132 14:01:27.785890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12133 14:01:27.786641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12135 14:01:27.844335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12136 14:01:27.844595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12138 14:01:27.902104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12139 14:01:27.902745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12141 14:01:27.963074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12142 14:01:27.963410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12144 14:01:28.024756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12145 14:01:28.025434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12147 14:01:28.084270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12148 14:01:28.085044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12150 14:01:28.147861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12151 14:01:28.148585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12153 14:01:28.202266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12154 14:01:28.202933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12156 14:01:28.269788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12157 14:01:28.270499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12159 14:01:28.326445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12160 14:01:28.327220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12162 14:01:28.385362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12163 14:01:28.386049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12165 14:01:28.441126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12166 14:01:28.441503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12168 14:01:28.494439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12169 14:01:28.495184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12171 14:01:28.546447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12172 14:01:28.547183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12174 14:01:28.604082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12175 14:01:28.604363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12177 14:01:28.660155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12178 14:01:28.660842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12180 14:01:28.716473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12181 14:01:28.717150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12183 14:01:28.774677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12184 14:01:28.775357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12186 14:01:28.831354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12187 14:01:28.832042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12189 14:01:28.881740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12190 14:01:28.882652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12192 14:01:28.932379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12193 14:01:28.932634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12195 14:01:28.982277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12196 14:01:28.982543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12198 14:01:29.029616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12199 14:01:29.029872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12201 14:01:29.072256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12202 14:01:29.072532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12204 14:01:29.116494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12205 14:01:29.116760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12207 14:01:29.163979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12208 14:01:29.164825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12210 14:01:29.224608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12211 14:01:29.224970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12213 14:01:29.276437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12214 14:01:29.276732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12216 14:01:29.327793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12217 14:01:29.328619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12219 14:01:29.384544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12220 14:01:29.385303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12222 14:01:29.437699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12223 14:01:29.438401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12225 14:01:29.498762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12226 14:01:29.499501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12228 14:01:29.558761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12229 14:01:29.559608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12231 14:01:29.622520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12232 14:01:29.623272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12234 14:01:29.679413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12235 14:01:29.680093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12237 14:01:29.733464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12238 14:01:29.733724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12240 14:01:29.785778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12241 14:01:29.786578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12243 14:01:29.836632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12244 14:01:29.836889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12246 14:01:29.879588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12247 14:01:29.879916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12249 14:01:29.926436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12250 14:01:29.927174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12252 14:01:29.981804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12253 14:01:29.982058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12255 14:01:30.028822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12256 14:01:30.029094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12258 14:01:30.083237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12259 14:01:30.083595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12261 14:01:30.137211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12262 14:01:30.137507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12264 14:01:30.186353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12266 14:01:30.189408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12267 14:01:30.238206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12268 14:01:30.238887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12270 14:01:30.289656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12271 14:01:30.290372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12273 14:01:30.344230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12274 14:01:30.344518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12276 14:01:30.394959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12277 14:01:30.395285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12279 14:01:30.443490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12280 14:01:30.443755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12282 14:01:30.496616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12283 14:01:30.496875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12285 14:01:30.547502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12286 14:01:30.547870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12288 14:01:30.594558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12289 14:01:30.594929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12291 14:01:30.645290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12292 14:01:30.645591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12294 14:01:30.688178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12295 14:01:30.688569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12297 14:01:30.742253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12298 14:01:30.742517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12300 14:01:30.789733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12301 14:01:30.789964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12303 14:01:30.836040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12304 14:01:30.836296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12306 14:01:30.882057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12307 14:01:30.882753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12309 14:01:30.929756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12310 14:01:30.930473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12312 14:01:30.984588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12313 14:01:30.985264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12315 14:01:31.042457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12316 14:01:31.042801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12318 14:01:31.093587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12319 14:01:31.093845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12321 14:01:31.138008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12322 14:01:31.138264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12324 14:01:31.179860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12325 14:01:31.180136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12327 14:01:31.222302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12328 14:01:31.222562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12330 14:01:31.269048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12331 14:01:31.269716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12333 14:01:31.322019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12334 14:01:31.322723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12336 14:01:31.383764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12337 14:01:31.384534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12339 14:01:31.438393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12340 14:01:31.438663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12342 14:01:31.499152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12343 14:01:31.499842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12345 14:01:31.553099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12346 14:01:31.553361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12348 14:01:31.608662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12349 14:01:31.609481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12351 14:01:31.664569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12352 14:01:31.664827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12354 14:01:31.717221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12355 14:01:31.718001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12357 14:01:31.769711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12358 14:01:31.769991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12360 14:01:31.812680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12361 14:01:31.812944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12363 14:01:31.866182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12364 14:01:31.866442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12366 14:01:31.915487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12367 14:01:31.915757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12369 14:01:31.966505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12370 14:01:31.966765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12372 14:01:32.017738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12373 14:01:32.017962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12375 14:01:32.069387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12376 14:01:32.069662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12378 14:01:32.129302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12379 14:01:32.130024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12381 14:01:32.183529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12382 14:01:32.183786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12384 14:01:32.226990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12385 14:01:32.227246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12387 14:01:32.266720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12388 14:01:32.266985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12390 14:01:32.320954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12391 14:01:32.321228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12393 14:01:32.369326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12394 14:01:32.369596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12396 14:01:32.424368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12397 14:01:32.424628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12399 14:01:32.467808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12400 14:01:32.468067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12402 14:01:32.512372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12403 14:01:32.512632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12405 14:01:32.545640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12406 14:01:32.545893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12408 14:01:32.591898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12409 14:01:32.592182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12411 14:01:32.642142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12412 14:01:32.642402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12414 14:01:32.694631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12415 14:01:32.695319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12417 14:01:32.748160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12418 14:01:32.748835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12420 14:01:32.795729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12421 14:01:32.796003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12423 14:01:32.840572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12424 14:01:32.841191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12426 14:01:32.889925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12427 14:01:32.890256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12429 14:01:32.946101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12430 14:01:32.946393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12432 14:01:32.997294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12433 14:01:32.998039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12435 14:01:33.048405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12437 14:01:33.051666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12438 14:01:33.105597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12439 14:01:33.106343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12441 14:01:33.162134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12443 14:01:33.165205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12444 14:01:33.228444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12445 14:01:33.228700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12447 14:01:33.277773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12449 14:01:33.280522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12450 14:01:33.334263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12451 14:01:33.334611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12453 14:01:33.389104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12454 14:01:33.389792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12456 14:01:33.439216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12457 14:01:33.439488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12459 14:01:33.483957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12460 14:01:33.484696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12462 14:01:33.535327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12463 14:01:33.535599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12465 14:01:33.586108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12467 14:01:33.588976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12468 14:01:33.644484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12469 14:01:33.644756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12471 14:01:33.692055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12472 14:01:33.692590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12474 14:01:33.749768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12475 14:01:33.750478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12477 14:01:33.805635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12479 14:01:33.808623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12480 14:01:33.859880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12482 14:01:33.862932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12483 14:01:33.907460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12484 14:01:33.907725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12486 14:01:33.960783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12487 14:01:33.961043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12489 14:01:34.013195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12490 14:01:34.013458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12492 14:01:34.065799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12493 14:01:34.066625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12495 14:01:34.124900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12496 14:01:34.125622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12498 14:01:34.178958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12499 14:01:34.179690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12501 14:01:34.238150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12502 14:01:34.238415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12504 14:01:34.291563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12505 14:01:34.291938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12507 14:01:34.336951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12508 14:01:34.337216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12510 14:01:34.396786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12511 14:01:34.397512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12513 14:01:34.449126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12514 14:01:34.449383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12516 14:01:34.495857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12517 14:01:34.496133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12519 14:01:34.546002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12520 14:01:34.546687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12522 14:01:34.600513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12523 14:01:34.600839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12525 14:01:34.650458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12526 14:01:34.650547 + set +x
12527 14:01:34.650784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12529 14:01:34.656950 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12682968_1.6.2.3.5>
12530 14:01:34.657205 Received signal: <ENDRUN> 1_kselftest-arm64 12682968_1.6.2.3.5
12531 14:01:34.657283 Ending use of test pattern.
12532 14:01:34.657347 Ending test lava.1_kselftest-arm64 (12682968_1.6.2.3.5), duration 32.86
12534 14:01:34.661045 <LAVA_TEST_RUNNER EXIT>
12535 14:01:34.661405 ok: lava_test_shell seems to have completed
12536 14:01:34.662496 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12537 14:01:34.662667 end: 3.1 lava-test-shell (duration 00:00:34) [common]
12538 14:01:34.662763 end: 3 lava-test-retry (duration 00:00:34) [common]
12539 14:01:34.662862 start: 4 finalize (timeout 00:07:16) [common]
12540 14:01:34.662957 start: 4.1 power-off (timeout 00:00:30) [common]
12541 14:01:34.663136 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
12542 14:01:34.740451 >> Command sent successfully.
12543 14:01:34.744997 Returned 0 in 0 seconds
12544 14:01:34.845902 end: 4.1 power-off (duration 00:00:00) [common]
12546 14:01:34.847696 start: 4.2 read-feedback (timeout 00:07:16) [common]
12547 14:01:34.848999 Listened to connection for namespace 'common' for up to 1s
12548 14:01:35.849586 Finalising connection for namespace 'common'
12549 14:01:35.850339 Disconnecting from shell: Finalise
12550 14:01:35.850753 / #
12551 14:01:35.951891 end: 4.2 read-feedback (duration 00:00:01) [common]
12552 14:01:35.952678 end: 4 finalize (duration 00:00:01) [common]
12553 14:01:35.953328 Cleaning after the job
12554 14:01:35.953867 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/ramdisk
12555 14:01:35.963764 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/kernel
12556 14:01:35.997184 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/dtb
12557 14:01:35.997517 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/nfsrootfs
12558 14:01:36.070357 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682968/tftp-deploy-k9n83o5t/modules
12559 14:01:36.075949 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682968
12560 14:01:36.599834 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682968
12561 14:01:36.600019 Job finished correctly