Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 38
1 13:52:20.186436 lava-dispatcher, installed at version: 2023.10
2 13:52:20.186645 start: 0 validate
3 13:52:20.186777 Start time: 2024-02-01 13:52:20.186770+00:00 (UTC)
4 13:52:20.186892 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:52:20.187024 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 13:52:20.446049 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:52:20.446253 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:52:50.227768 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:52:50.228495 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:52:50.497934 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:52:50.498679 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:52:51.027436 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:52:51.028179 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:52:57.034218 validate duration: 36.85
16 13:52:57.034473 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:52:57.034571 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:52:57.034657 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:52:57.034819 Not decompressing ramdisk as can be used compressed.
20 13:52:57.034903 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 13:52:57.034965 saving as /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/ramdisk/initrd.cpio.gz
22 13:52:57.035033 total size: 4665395 (4 MB)
23 13:52:57.293623 progress 0 % (0 MB)
24 13:52:57.295199 progress 5 % (0 MB)
25 13:52:57.296476 progress 10 % (0 MB)
26 13:52:57.297841 progress 15 % (0 MB)
27 13:52:57.299145 progress 20 % (0 MB)
28 13:52:57.300480 progress 25 % (1 MB)
29 13:52:57.301820 progress 30 % (1 MB)
30 13:52:57.303029 progress 35 % (1 MB)
31 13:52:57.304274 progress 40 % (1 MB)
32 13:52:57.305718 progress 45 % (2 MB)
33 13:52:57.306923 progress 50 % (2 MB)
34 13:52:57.308283 progress 55 % (2 MB)
35 13:52:57.309557 progress 60 % (2 MB)
36 13:52:57.310800 progress 65 % (2 MB)
37 13:52:57.312108 progress 70 % (3 MB)
38 13:52:57.313374 progress 75 % (3 MB)
39 13:52:57.314608 progress 80 % (3 MB)
40 13:52:57.316129 progress 85 % (3 MB)
41 13:52:57.317435 progress 90 % (4 MB)
42 13:52:57.318661 progress 95 % (4 MB)
43 13:52:57.319913 progress 100 % (4 MB)
44 13:52:57.320093 4 MB downloaded in 0.29 s (15.61 MB/s)
45 13:52:57.320243 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:52:57.320515 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:52:57.320600 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:52:57.320681 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:52:57.320875 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:52:57.320961 saving as /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/kernel/Image
52 13:52:57.321021 total size: 51532288 (49 MB)
53 13:52:57.321080 No compression specified
54 13:52:57.322325 progress 0 % (0 MB)
55 13:52:57.335822 progress 5 % (2 MB)
56 13:52:57.349235 progress 10 % (4 MB)
57 13:52:57.362518 progress 15 % (7 MB)
58 13:52:57.376069 progress 20 % (9 MB)
59 13:52:57.389766 progress 25 % (12 MB)
60 13:52:57.403165 progress 30 % (14 MB)
61 13:52:57.416969 progress 35 % (17 MB)
62 13:52:57.430445 progress 40 % (19 MB)
63 13:52:57.443786 progress 45 % (22 MB)
64 13:52:57.457274 progress 50 % (24 MB)
65 13:52:57.470524 progress 55 % (27 MB)
66 13:52:57.483846 progress 60 % (29 MB)
67 13:52:57.497391 progress 65 % (31 MB)
68 13:52:57.510609 progress 70 % (34 MB)
69 13:52:57.524190 progress 75 % (36 MB)
70 13:52:57.537740 progress 80 % (39 MB)
71 13:52:57.550940 progress 85 % (41 MB)
72 13:52:57.564287 progress 90 % (44 MB)
73 13:52:57.577448 progress 95 % (46 MB)
74 13:52:57.590492 progress 100 % (49 MB)
75 13:52:57.590733 49 MB downloaded in 0.27 s (182.22 MB/s)
76 13:52:57.590887 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:52:57.591117 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:52:57.591207 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:52:57.591292 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:52:57.591434 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:52:57.591503 saving as /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/dtb/mt8192-asurada-spherion-r0.dtb
83 13:52:57.591564 total size: 47278 (0 MB)
84 13:52:57.591626 No compression specified
85 13:52:57.592774 progress 69 % (0 MB)
86 13:52:57.593051 progress 100 % (0 MB)
87 13:52:57.593209 0 MB downloaded in 0.00 s (27.46 MB/s)
88 13:52:57.593331 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:52:57.593554 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:52:57.593641 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:52:57.593723 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:52:57.593833 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 13:52:57.593899 saving as /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/nfsrootfs/full.rootfs.tar
95 13:52:57.593959 total size: 200813988 (191 MB)
96 13:52:57.594019 Using unxz to decompress xz
97 13:52:57.598166 progress 0 % (0 MB)
98 13:52:58.125491 progress 5 % (9 MB)
99 13:52:58.643318 progress 10 % (19 MB)
100 13:52:59.247168 progress 15 % (28 MB)
101 13:52:59.621320 progress 20 % (38 MB)
102 13:52:59.957243 progress 25 % (47 MB)
103 13:53:00.557531 progress 30 % (57 MB)
104 13:53:01.102411 progress 35 % (67 MB)
105 13:53:01.690127 progress 40 % (76 MB)
106 13:53:02.245098 progress 45 % (86 MB)
107 13:53:02.823407 progress 50 % (95 MB)
108 13:53:03.451168 progress 55 % (105 MB)
109 13:53:04.116635 progress 60 % (114 MB)
110 13:53:04.234119 progress 65 % (124 MB)
111 13:53:04.374368 progress 70 % (134 MB)
112 13:53:04.470011 progress 75 % (143 MB)
113 13:53:04.544567 progress 80 % (153 MB)
114 13:53:04.617761 progress 85 % (162 MB)
115 13:53:04.717668 progress 90 % (172 MB)
116 13:53:04.999386 progress 95 % (181 MB)
117 13:53:05.585372 progress 100 % (191 MB)
118 13:53:05.590630 191 MB downloaded in 8.00 s (23.95 MB/s)
119 13:53:05.590908 end: 1.4.1 http-download (duration 00:00:08) [common]
121 13:53:05.591171 end: 1.4 download-retry (duration 00:00:08) [common]
122 13:53:05.591260 start: 1.5 download-retry (timeout 00:09:51) [common]
123 13:53:05.591345 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 13:53:05.591508 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:53:05.591579 saving as /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/modules/modules.tar
126 13:53:05.591640 total size: 8623988 (8 MB)
127 13:53:05.591704 Using unxz to decompress xz
128 13:53:05.861192 progress 0 % (0 MB)
129 13:53:05.882438 progress 5 % (0 MB)
130 13:53:05.906428 progress 10 % (0 MB)
131 13:53:05.930105 progress 15 % (1 MB)
132 13:53:05.954159 progress 20 % (1 MB)
133 13:53:05.978294 progress 25 % (2 MB)
134 13:53:06.004390 progress 30 % (2 MB)
135 13:53:06.030848 progress 35 % (2 MB)
136 13:53:06.054527 progress 40 % (3 MB)
137 13:53:06.079047 progress 45 % (3 MB)
138 13:53:06.104746 progress 50 % (4 MB)
139 13:53:06.129334 progress 55 % (4 MB)
140 13:53:06.154614 progress 60 % (4 MB)
141 13:53:06.182386 progress 65 % (5 MB)
142 13:53:06.207863 progress 70 % (5 MB)
143 13:53:06.231487 progress 75 % (6 MB)
144 13:53:06.258718 progress 80 % (6 MB)
145 13:53:06.284821 progress 85 % (7 MB)
146 13:53:06.310225 progress 90 % (7 MB)
147 13:53:06.342595 progress 95 % (7 MB)
148 13:53:06.370819 progress 100 % (8 MB)
149 13:53:06.375696 8 MB downloaded in 0.78 s (10.49 MB/s)
150 13:53:06.375965 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:53:06.376228 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:53:06.376320 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 13:53:06.376416 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 13:53:09.898471 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12682950/extract-nfsrootfs-t8gplle7
156 13:53:09.898687 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:53:09.898790 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 13:53:09.898968 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1
159 13:53:09.899101 makedir: /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin
160 13:53:09.899203 makedir: /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/tests
161 13:53:09.899300 makedir: /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/results
162 13:53:09.899407 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-add-keys
163 13:53:09.899552 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-add-sources
164 13:53:09.899684 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-background-process-start
165 13:53:09.899813 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-background-process-stop
166 13:53:09.899940 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-common-functions
167 13:53:09.900067 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-echo-ipv4
168 13:53:09.900193 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-install-packages
169 13:53:09.900318 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-installed-packages
170 13:53:09.900442 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-os-build
171 13:53:09.900566 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-probe-channel
172 13:53:09.900691 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-probe-ip
173 13:53:09.901013 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-target-ip
174 13:53:09.901141 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-target-mac
175 13:53:09.901296 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-target-storage
176 13:53:09.901538 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-test-case
177 13:53:09.901689 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-test-event
178 13:53:09.901834 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-test-feedback
179 13:53:09.901978 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-test-raise
180 13:53:09.902121 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-test-reference
181 13:53:09.902268 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-test-runner
182 13:53:09.902436 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-test-set
183 13:53:09.902583 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-test-shell
184 13:53:09.902757 Updating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-add-keys (debian)
185 13:53:09.902956 Updating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-add-sources (debian)
186 13:53:09.903117 Updating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-install-packages (debian)
187 13:53:09.903274 Updating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-installed-packages (debian)
188 13:53:09.903429 Updating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/bin/lava-os-build (debian)
189 13:53:09.903566 Creating /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/environment
190 13:53:09.903681 LAVA metadata
191 13:53:09.903785 - LAVA_JOB_ID=12682950
192 13:53:09.903885 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:53:09.904039 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 13:53:09.904137 skipped lava-vland-overlay
195 13:53:09.904256 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:53:09.904378 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 13:53:09.904470 skipped lava-multinode-overlay
198 13:53:09.904586 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:53:09.904711 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 13:53:09.904824 Loading test definitions
201 13:53:09.904961 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 13:53:09.905070 Using /lava-12682950 at stage 0
203 13:53:09.905457 uuid=12682950_1.6.2.3.1 testdef=None
204 13:53:09.905579 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:53:09.905704 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 13:53:09.906328 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:53:09.906702 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 13:53:09.907474 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:53:09.907852 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 13:53:09.908409 runner path: /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/0/tests/0_timesync-off test_uuid 12682950_1.6.2.3.1
213 13:53:09.908582 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:53:09.909012 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 13:53:09.909096 Using /lava-12682950 at stage 0
217 13:53:09.909220 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:53:09.909307 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/0/tests/1_kselftest-dt'
219 13:53:18.308240 Running '/usr/bin/git checkout kernelci.org
220 13:53:18.454666 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 13:53:18.455418 uuid=12682950_1.6.2.3.5 testdef=None
222 13:53:18.455587 end: 1.6.2.3.5 git-repo-action (duration 00:00:09) [common]
224 13:53:18.455864 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 13:53:18.456621 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:53:18.456925 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 13:53:18.457898 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:53:18.458158 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 13:53:18.459712 runner path: /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/0/tests/1_kselftest-dt test_uuid 12682950_1.6.2.3.5
232 13:53:18.459833 BOARD='mt8192-asurada-spherion-r0'
233 13:53:18.459908 BRANCH='cip'
234 13:53:18.459985 SKIPFILE='/dev/null'
235 13:53:18.460079 SKIP_INSTALL='True'
236 13:53:18.460171 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 13:53:18.460264 TST_CASENAME=''
238 13:53:18.460366 TST_CMDFILES='dt'
239 13:53:18.460560 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:53:18.460946 Creating lava-test-runner.conf files
242 13:53:18.461045 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682950/lava-overlay-7n3g_wk1/lava-12682950/0 for stage 0
243 13:53:18.461184 - 0_timesync-off
244 13:53:18.461281 - 1_kselftest-dt
245 13:53:18.461439 end: 1.6.2.3 test-definition (duration 00:00:09) [common]
246 13:53:18.461578 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 13:53:25.885615 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 13:53:25.885772 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:31) [common]
249 13:53:25.885864 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:53:25.885962 end: 1.6.2 lava-overlay (duration 00:00:16) [common]
251 13:53:25.886053 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:31) [common]
252 13:53:26.004858 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:53:26.005253 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
254 13:53:26.005364 extracting modules file /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682950/extract-nfsrootfs-t8gplle7
255 13:53:26.225615 extracting modules file /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682950/extract-overlay-ramdisk-p50gyliv/ramdisk
256 13:53:26.448597 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:53:26.448806 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 13:53:26.448905 [common] Applying overlay to NFS
259 13:53:26.448973 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682950/compress-overlay-b07dyg_g/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682950/extract-nfsrootfs-t8gplle7
260 13:53:27.365607 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:53:27.365772 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 13:53:27.365863 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:53:27.365951 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 13:53:27.366029 Building ramdisk /var/lib/lava/dispatcher/tmp/12682950/extract-overlay-ramdisk-p50gyliv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682950/extract-overlay-ramdisk-p50gyliv/ramdisk
265 13:53:27.694967 >> 119414 blocks
266 13:53:29.617277 rename /var/lib/lava/dispatcher/tmp/12682950/extract-overlay-ramdisk-p50gyliv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/ramdisk/ramdisk.cpio.gz
267 13:53:29.617741 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:53:29.617878 start: 1.6.8 prepare-kernel (timeout 00:09:27) [common]
269 13:53:29.617984 start: 1.6.8.1 prepare-fit (timeout 00:09:27) [common]
270 13:53:29.618094 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/kernel/Image'
271 13:53:42.698286 Returned 0 in 13 seconds
272 13:53:42.798948 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/kernel/image.itb
273 13:53:43.155610 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:53:43.155990 output: Created: Thu Feb 1 13:53:43 2024
275 13:53:43.156069 output: Image 0 (kernel-1)
276 13:53:43.156133 output: Description:
277 13:53:43.156194 output: Created: Thu Feb 1 13:53:43 2024
278 13:53:43.156256 output: Type: Kernel Image
279 13:53:43.156315 output: Compression: lzma compressed
280 13:53:43.156374 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
281 13:53:43.156434 output: Architecture: AArch64
282 13:53:43.156492 output: OS: Linux
283 13:53:43.156549 output: Load Address: 0x00000000
284 13:53:43.156609 output: Entry Point: 0x00000000
285 13:53:43.156666 output: Hash algo: crc32
286 13:53:43.156730 output: Hash value: 5aa40db2
287 13:53:43.156790 output: Image 1 (fdt-1)
288 13:53:43.156843 output: Description: mt8192-asurada-spherion-r0
289 13:53:43.156896 output: Created: Thu Feb 1 13:53:43 2024
290 13:53:43.156948 output: Type: Flat Device Tree
291 13:53:43.157001 output: Compression: uncompressed
292 13:53:43.157054 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 13:53:43.157107 output: Architecture: AArch64
294 13:53:43.157160 output: Hash algo: crc32
295 13:53:43.157213 output: Hash value: cc4352de
296 13:53:43.157265 output: Image 2 (ramdisk-1)
297 13:53:43.157316 output: Description: unavailable
298 13:53:43.157368 output: Created: Thu Feb 1 13:53:43 2024
299 13:53:43.157420 output: Type: RAMDisk Image
300 13:53:43.157473 output: Compression: Unknown Compression
301 13:53:43.157525 output: Data Size: 17800010 Bytes = 17382.82 KiB = 16.98 MiB
302 13:53:43.157577 output: Architecture: AArch64
303 13:53:43.157629 output: OS: Linux
304 13:53:43.157680 output: Load Address: unavailable
305 13:53:43.157732 output: Entry Point: unavailable
306 13:53:43.157783 output: Hash algo: crc32
307 13:53:43.157834 output: Hash value: 9114c8b7
308 13:53:43.157886 output: Default Configuration: 'conf-1'
309 13:53:43.157938 output: Configuration 0 (conf-1)
310 13:53:43.157990 output: Description: mt8192-asurada-spherion-r0
311 13:53:43.158042 output: Kernel: kernel-1
312 13:53:43.158094 output: Init Ramdisk: ramdisk-1
313 13:53:43.158146 output: FDT: fdt-1
314 13:53:43.158197 output: Loadables: kernel-1
315 13:53:43.158249 output:
316 13:53:43.158453 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 13:53:43.158547 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 13:53:43.158657 end: 1.6 prepare-tftp-overlay (duration 00:00:37) [common]
319 13:53:43.158749 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
320 13:53:43.158827 No LXC device requested
321 13:53:43.158907 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:53:43.158989 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
323 13:53:43.159064 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:53:43.159136 Checking files for TFTP limit of 4294967296 bytes.
325 13:53:43.159669 end: 1 tftp-deploy (duration 00:00:46) [common]
326 13:53:43.159776 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:53:43.159871 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:53:43.159997 substitutions:
329 13:53:43.160065 - {DTB}: 12682950/tftp-deploy-xlqbxold/dtb/mt8192-asurada-spherion-r0.dtb
330 13:53:43.160129 - {INITRD}: 12682950/tftp-deploy-xlqbxold/ramdisk/ramdisk.cpio.gz
331 13:53:43.160188 - {KERNEL}: 12682950/tftp-deploy-xlqbxold/kernel/Image
332 13:53:43.160245 - {LAVA_MAC}: None
333 13:53:43.160301 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12682950/extract-nfsrootfs-t8gplle7
334 13:53:43.160357 - {NFS_SERVER_IP}: 192.168.201.1
335 13:53:43.160411 - {PRESEED_CONFIG}: None
336 13:53:43.160465 - {PRESEED_LOCAL}: None
337 13:53:43.160519 - {RAMDISK}: 12682950/tftp-deploy-xlqbxold/ramdisk/ramdisk.cpio.gz
338 13:53:43.160573 - {ROOT_PART}: None
339 13:53:43.160627 - {ROOT}: None
340 13:53:43.160680 - {SERVER_IP}: 192.168.201.1
341 13:53:43.160778 - {TEE}: None
342 13:53:43.160833 Parsed boot commands:
343 13:53:43.160886 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:53:43.161076 Parsed boot commands: tftpboot 192.168.201.1 12682950/tftp-deploy-xlqbxold/kernel/image.itb 12682950/tftp-deploy-xlqbxold/kernel/cmdline
345 13:53:43.161165 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:53:43.161247 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:53:43.161341 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:53:43.161432 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:53:43.161504 Not connected, no need to disconnect.
350 13:53:43.161577 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:53:43.161657 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:53:43.161725 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 13:53:43.165883 Setting prompt string to ['lava-test: # ']
354 13:53:43.166246 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:53:43.166359 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:53:43.166460 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:53:43.166583 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:53:43.166781 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 13:53:48.303804 >> Command sent successfully.
360 13:53:48.306227 Returned 0 in 5 seconds
361 13:53:48.406604 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 13:53:48.406928 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 13:53:48.407027 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 13:53:48.407118 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:53:48.407185 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:53:48.407254 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:53:48.407516 [Enter `^Ec?' for help]
369 13:53:48.589897
370 13:53:48.590034
371 13:53:48.590104 F0: 102B 0000
372 13:53:48.590169
373 13:53:48.590229 F3: 1001 0000 [0200]
374 13:53:48.590287
375 13:53:48.593929 F3: 1001 0000
376 13:53:48.594012
377 13:53:48.594076 F7: 102D 0000
378 13:53:48.594136
379 13:53:48.594195 F1: 0000 0000
380 13:53:48.594251
381 13:53:48.597579 V0: 0000 0000 [0001]
382 13:53:48.597665
383 13:53:48.597730 00: 0007 8000
384 13:53:48.597795
385 13:53:48.601571 01: 0000 0000
386 13:53:48.601655
387 13:53:48.601720 BP: 0C00 0209 [0000]
388 13:53:48.601779
389 13:53:48.604956 G0: 1182 0000
390 13:53:48.605037
391 13:53:48.605100 EC: 0000 0021 [4000]
392 13:53:48.605162
393 13:53:48.608160 S7: 0000 0000 [0000]
394 13:53:48.608242
395 13:53:48.608306 CC: 0000 0000 [0001]
396 13:53:48.608366
397 13:53:48.612131 T0: 0000 0040 [010F]
398 13:53:48.612214
399 13:53:48.612278 Jump to BL
400 13:53:48.612339
401 13:53:48.636399
402 13:53:48.636486
403 13:53:48.636551
404 13:53:48.643144 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 13:53:48.647386 ARM64: Exception handlers installed.
406 13:53:48.650094 ARM64: Testing exception
407 13:53:48.653626 ARM64: Done test exception
408 13:53:48.661069 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 13:53:48.669940 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 13:53:48.677228 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 13:53:48.687108 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 13:53:48.693617 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 13:53:48.703960 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 13:53:48.715891 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 13:53:48.720974 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 13:53:48.739190 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 13:53:48.742850 WDT: Last reset was cold boot
418 13:53:48.745813 SPI1(PAD0) initialized at 2873684 Hz
419 13:53:48.749426 SPI5(PAD0) initialized at 992727 Hz
420 13:53:48.752688 VBOOT: Loading verstage.
421 13:53:48.759223 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 13:53:48.763441 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 13:53:48.766246 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 13:53:48.769104 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 13:53:48.776729 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 13:53:48.783504 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 13:53:48.795017 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 13:53:48.795107
429 13:53:48.795171
430 13:53:48.803910 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 13:53:48.807424 ARM64: Exception handlers installed.
432 13:53:48.810546 ARM64: Testing exception
433 13:53:48.810628 ARM64: Done test exception
434 13:53:48.817592 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 13:53:48.820622 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 13:53:48.835589 Probing TPM: . done!
437 13:53:48.835671 TPM ready after 0 ms
438 13:53:48.842055 Connected to device vid:did:rid of 1ae0:0028:00
439 13:53:48.848601 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 13:53:48.890783 Initialized TPM device CR50 revision 0
441 13:53:48.902072 tlcl_send_startup: Startup return code is 0
442 13:53:48.902156 TPM: setup succeeded
443 13:53:48.912782 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 13:53:48.921981 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 13:53:48.932857 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 13:53:48.941120 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 13:53:48.945032 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 13:53:48.948166 in-header: 03 07 00 00 08 00 00 00
449 13:53:48.951176 in-data: aa e4 47 04 13 02 00 00
450 13:53:48.954471 Chrome EC: UHEPI supported
451 13:53:48.961752 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 13:53:48.964868 in-header: 03 9d 00 00 08 00 00 00
453 13:53:48.967601 in-data: 10 20 20 08 00 00 00 00
454 13:53:48.967683 Phase 1
455 13:53:48.970968 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 13:53:48.977984 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 13:53:48.984181 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 13:53:48.987514 Recovery requested (1009000e)
459 13:53:48.995152 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 13:53:48.999885 tlcl_extend: response is 0
461 13:53:49.008384 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 13:53:49.012892 tlcl_extend: response is 0
463 13:53:49.019812 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 13:53:49.040625 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 13:53:49.047160 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 13:53:49.047242
467 13:53:49.047307
468 13:53:49.057785 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 13:53:49.061453 ARM64: Exception handlers installed.
470 13:53:49.064095 ARM64: Testing exception
471 13:53:49.064178 ARM64: Done test exception
472 13:53:49.084062 pmic_efuse_setting: Set efuses in 11 msecs
473 13:53:49.091617 pmwrap_interface_init: Select PMIF_VLD_RDY
474 13:53:49.095053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 13:53:49.102004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 13:53:49.104553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 13:53:49.108749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 13:53:49.115414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 13:53:49.119352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 13:53:49.122843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 13:53:49.129745 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 13:53:49.133403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 13:53:49.140602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 13:53:49.143570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 13:53:49.146734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 13:53:49.153691 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 13:53:49.161270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 13:53:49.163140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 13:53:49.170427 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 13:53:49.176552 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 13:53:49.180547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 13:53:49.187775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 13:53:49.192069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 13:53:49.198112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 13:53:49.204297 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 13:53:49.207926 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 13:53:49.214262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 13:53:49.221162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 13:53:49.224543 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 13:53:49.231412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 13:53:49.234162 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 13:53:49.241295 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 13:53:49.244893 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 13:53:49.251435 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 13:53:49.255418 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 13:53:49.261411 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 13:53:49.264474 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 13:53:49.271301 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 13:53:49.274548 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 13:53:49.281403 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 13:53:49.284312 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 13:53:49.288156 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 13:53:49.294488 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 13:53:49.298064 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 13:53:49.302070 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 13:53:49.307449 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 13:53:49.311636 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 13:53:49.314556 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 13:53:49.321658 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 13:53:49.325092 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 13:53:49.328034 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 13:53:49.334151 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 13:53:49.337667 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 13:53:49.340881 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 13:53:49.347379 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 13:53:49.357783 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 13:53:49.360922 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 13:53:49.370997 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 13:53:49.377705 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 13:53:49.384364 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 13:53:49.387659 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:53:49.391018 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 13:53:49.398595 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 13:53:49.405620 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 13:53:49.409404 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 13:53:49.411920 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 13:53:49.423130 [RTC]rtc_get_frequency_meter,154: input=15, output=765
538 13:53:49.433172 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 13:53:49.442099 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 13:53:49.452570 [RTC]rtc_get_frequency_meter,154: input=17, output=811
541 13:53:49.461319 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 13:53:49.470442 [RTC]rtc_get_frequency_meter,154: input=16, output=786
543 13:53:49.480332 [RTC]rtc_get_frequency_meter,154: input=17, output=810
544 13:53:49.484215 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 13:53:49.490532 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 13:53:49.494272 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 13:53:49.497580 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 13:53:49.503898 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 13:53:49.507580 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 13:53:49.511327 ADC[4]: Raw value=670063 ID=5
551 13:53:49.511410 ADC[3]: Raw value=212917 ID=1
552 13:53:49.514147 RAM Code: 0x51
553 13:53:49.518472 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 13:53:49.525024 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 13:53:49.530763 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 13:53:49.537061 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 13:53:49.540572 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 13:53:49.543655 in-header: 03 07 00 00 08 00 00 00
559 13:53:49.547683 in-data: aa e4 47 04 13 02 00 00
560 13:53:49.550288 Chrome EC: UHEPI supported
561 13:53:49.557178 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 13:53:49.560679 in-header: 03 d5 00 00 08 00 00 00
563 13:53:49.564078 in-data: 98 20 60 08 00 00 00 00
564 13:53:49.567157 MRC: failed to locate region type 0.
565 13:53:49.573989 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 13:53:49.577387 DRAM-K: Running full calibration
567 13:53:49.580384 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 13:53:49.583934 header.status = 0x0
569 13:53:49.586986 header.version = 0x6 (expected: 0x6)
570 13:53:49.590251 header.size = 0xd00 (expected: 0xd00)
571 13:53:49.590332 header.flags = 0x0
572 13:53:49.597201 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 13:53:49.616030 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 13:53:49.622285 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 13:53:49.626531 dram_init: ddr_geometry: 0
576 13:53:49.628943 [EMI] MDL number = 0
577 13:53:49.629025 [EMI] Get MDL freq = 0
578 13:53:49.632412 dram_init: ddr_type: 0
579 13:53:49.632494 is_discrete_lpddr4: 1
580 13:53:49.636056 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 13:53:49.636139
582 13:53:49.636206
583 13:53:49.639691 [Bian_co] ETT version 0.0.0.1
584 13:53:49.643295 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 13:53:49.643377
586 13:53:49.649961 dramc_set_vcore_voltage set vcore to 650000
587 13:53:49.650042 Read voltage for 800, 4
588 13:53:49.652964 Vio18 = 0
589 13:53:49.653046 Vcore = 650000
590 13:53:49.653111 Vdram = 0
591 13:53:49.653172 Vddq = 0
592 13:53:49.656619 Vmddr = 0
593 13:53:49.656700 dram_init: config_dvfs: 1
594 13:53:49.664486 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 13:53:49.670534 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 13:53:49.673618 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 13:53:49.676911 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 13:53:49.680181 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 13:53:49.683525 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 13:53:49.686672 MEM_TYPE=3, freq_sel=18
601 13:53:49.690118 sv_algorithm_assistance_LP4_1600
602 13:53:49.693422 ============ PULL DRAM RESETB DOWN ============
603 13:53:49.696456 ========== PULL DRAM RESETB DOWN end =========
604 13:53:49.703249 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 13:53:49.706777 ===================================
606 13:53:49.706859 LPDDR4 DRAM CONFIGURATION
607 13:53:49.709608 ===================================
608 13:53:49.713351 EX_ROW_EN[0] = 0x0
609 13:53:49.713465 EX_ROW_EN[1] = 0x0
610 13:53:49.716522 LP4Y_EN = 0x0
611 13:53:49.716632 WORK_FSP = 0x0
612 13:53:49.719933 WL = 0x2
613 13:53:49.723332 RL = 0x2
614 13:53:49.723414 BL = 0x2
615 13:53:49.726811 RPST = 0x0
616 13:53:49.726893 RD_PRE = 0x0
617 13:53:49.730120 WR_PRE = 0x1
618 13:53:49.730202 WR_PST = 0x0
619 13:53:49.733053 DBI_WR = 0x0
620 13:53:49.733135 DBI_RD = 0x0
621 13:53:49.736419 OTF = 0x1
622 13:53:49.739638 ===================================
623 13:53:49.743029 ===================================
624 13:53:49.743111 ANA top config
625 13:53:49.746579 ===================================
626 13:53:49.749474 DLL_ASYNC_EN = 0
627 13:53:49.752960 ALL_SLAVE_EN = 1
628 13:53:49.753042 NEW_RANK_MODE = 1
629 13:53:49.757477 DLL_IDLE_MODE = 1
630 13:53:49.759665 LP45_APHY_COMB_EN = 1
631 13:53:49.763193 TX_ODT_DIS = 1
632 13:53:49.763276 NEW_8X_MODE = 1
633 13:53:49.766717 ===================================
634 13:53:49.770019 ===================================
635 13:53:49.773262 data_rate = 1600
636 13:53:49.777001 CKR = 1
637 13:53:49.779837 DQ_P2S_RATIO = 8
638 13:53:49.783173 ===================================
639 13:53:49.786118 CA_P2S_RATIO = 8
640 13:53:49.789970 DQ_CA_OPEN = 0
641 13:53:49.792579 DQ_SEMI_OPEN = 0
642 13:53:49.792689 CA_SEMI_OPEN = 0
643 13:53:49.796029 CA_FULL_RATE = 0
644 13:53:49.799214 DQ_CKDIV4_EN = 1
645 13:53:49.802825 CA_CKDIV4_EN = 1
646 13:53:49.807104 CA_PREDIV_EN = 0
647 13:53:49.807186 PH8_DLY = 0
648 13:53:49.809738 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 13:53:49.812862 DQ_AAMCK_DIV = 4
650 13:53:49.816272 CA_AAMCK_DIV = 4
651 13:53:49.819548 CA_ADMCK_DIV = 4
652 13:53:49.822978 DQ_TRACK_CA_EN = 0
653 13:53:49.826008 CA_PICK = 800
654 13:53:49.826090 CA_MCKIO = 800
655 13:53:49.829820 MCKIO_SEMI = 0
656 13:53:49.832550 PLL_FREQ = 3068
657 13:53:49.836900 DQ_UI_PI_RATIO = 32
658 13:53:49.839880 CA_UI_PI_RATIO = 0
659 13:53:49.842634 ===================================
660 13:53:49.846218 ===================================
661 13:53:49.849270 memory_type:LPDDR4
662 13:53:49.849378 GP_NUM : 10
663 13:53:49.852646 SRAM_EN : 1
664 13:53:49.852779 MD32_EN : 0
665 13:53:49.856022 ===================================
666 13:53:49.859234 [ANA_INIT] >>>>>>>>>>>>>>
667 13:53:49.862930 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 13:53:49.866030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 13:53:49.869688 ===================================
670 13:53:49.872733 data_rate = 1600,PCW = 0X7600
671 13:53:49.876024 ===================================
672 13:53:49.879470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 13:53:49.882567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 13:53:49.889550 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 13:53:49.892762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 13:53:49.895850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 13:53:49.902637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 13:53:49.902719 [ANA_INIT] flow start
679 13:53:49.907138 [ANA_INIT] PLL >>>>>>>>
680 13:53:49.907219 [ANA_INIT] PLL <<<<<<<<
681 13:53:49.909920 [ANA_INIT] MIDPI >>>>>>>>
682 13:53:49.913153 [ANA_INIT] MIDPI <<<<<<<<
683 13:53:49.916892 [ANA_INIT] DLL >>>>>>>>
684 13:53:49.916974 [ANA_INIT] flow end
685 13:53:49.919747 ============ LP4 DIFF to SE enter ============
686 13:53:49.925961 ============ LP4 DIFF to SE exit ============
687 13:53:49.926044 [ANA_INIT] <<<<<<<<<<<<<
688 13:53:49.929803 [Flow] Enable top DCM control >>>>>
689 13:53:49.932888 [Flow] Enable top DCM control <<<<<
690 13:53:49.935978 Enable DLL master slave shuffle
691 13:53:49.943552 ==============================================================
692 13:53:49.943635 Gating Mode config
693 13:53:49.950543 ==============================================================
694 13:53:49.953467 Config description:
695 13:53:49.959946 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 13:53:49.966555 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 13:53:49.973341 SELPH_MODE 0: By rank 1: By Phase
698 13:53:49.979336 ==============================================================
699 13:53:49.979419 GAT_TRACK_EN = 1
700 13:53:49.982652 RX_GATING_MODE = 2
701 13:53:49.986726 RX_GATING_TRACK_MODE = 2
702 13:53:49.989376 SELPH_MODE = 1
703 13:53:49.992613 PICG_EARLY_EN = 1
704 13:53:49.996441 VALID_LAT_VALUE = 1
705 13:53:50.003379 ==============================================================
706 13:53:50.006296 Enter into Gating configuration >>>>
707 13:53:50.009432 Exit from Gating configuration <<<<
708 13:53:50.013049 Enter into DVFS_PRE_config >>>>>
709 13:53:50.023649 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 13:53:50.027018 Exit from DVFS_PRE_config <<<<<
711 13:53:50.030158 Enter into PICG configuration >>>>
712 13:53:50.032870 Exit from PICG configuration <<<<
713 13:53:50.036376 [RX_INPUT] configuration >>>>>
714 13:53:50.036457 [RX_INPUT] configuration <<<<<
715 13:53:50.042986 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 13:53:50.049570 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 13:53:50.053017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 13:53:50.059519 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 13:53:50.066865 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 13:53:50.073123 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 13:53:50.076138 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 13:53:50.079495 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 13:53:50.086444 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 13:53:50.089424 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 13:53:50.092849 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 13:53:50.096238 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 13:53:50.099688 ===================================
728 13:53:50.102966 LPDDR4 DRAM CONFIGURATION
729 13:53:50.105962 ===================================
730 13:53:50.109349 EX_ROW_EN[0] = 0x0
731 13:53:50.109431 EX_ROW_EN[1] = 0x0
732 13:53:50.112608 LP4Y_EN = 0x0
733 13:53:50.112690 WORK_FSP = 0x0
734 13:53:50.116357 WL = 0x2
735 13:53:50.116440 RL = 0x2
736 13:53:50.119391 BL = 0x2
737 13:53:50.119472 RPST = 0x0
738 13:53:50.122911 RD_PRE = 0x0
739 13:53:50.122993 WR_PRE = 0x1
740 13:53:50.126425 WR_PST = 0x0
741 13:53:50.129148 DBI_WR = 0x0
742 13:53:50.129230 DBI_RD = 0x0
743 13:53:50.132928 OTF = 0x1
744 13:53:50.136909 ===================================
745 13:53:50.139441 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 13:53:50.144270 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 13:53:50.146221 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 13:53:50.150618 ===================================
749 13:53:50.153014 LPDDR4 DRAM CONFIGURATION
750 13:53:50.156350 ===================================
751 13:53:50.159855 EX_ROW_EN[0] = 0x10
752 13:53:50.159937 EX_ROW_EN[1] = 0x0
753 13:53:50.163360 LP4Y_EN = 0x0
754 13:53:50.163442 WORK_FSP = 0x0
755 13:53:50.166288 WL = 0x2
756 13:53:50.166371 RL = 0x2
757 13:53:50.169393 BL = 0x2
758 13:53:50.169475 RPST = 0x0
759 13:53:50.174193 RD_PRE = 0x0
760 13:53:50.174276 WR_PRE = 0x1
761 13:53:50.177205 WR_PST = 0x0
762 13:53:50.177287 DBI_WR = 0x0
763 13:53:50.179504 DBI_RD = 0x0
764 13:53:50.179585 OTF = 0x1
765 13:53:50.183068 ===================================
766 13:53:50.189674 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 13:53:50.194540 nWR fixed to 40
768 13:53:50.197280 [ModeRegInit_LP4] CH0 RK0
769 13:53:50.197362 [ModeRegInit_LP4] CH0 RK1
770 13:53:50.200991 [ModeRegInit_LP4] CH1 RK0
771 13:53:50.204890 [ModeRegInit_LP4] CH1 RK1
772 13:53:50.204973 match AC timing 12
773 13:53:50.210716 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 13:53:50.213737 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 13:53:50.217122 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 13:53:50.223966 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 13:53:50.227244 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 13:53:50.227326 [EMI DOE] emi_dcm 0
779 13:53:50.234362 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 13:53:50.234444 ==
781 13:53:50.237676 Dram Type= 6, Freq= 0, CH_0, rank 0
782 13:53:50.240735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 13:53:50.240831 ==
784 13:53:50.247343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 13:53:50.254314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 13:53:50.262212 [CA 0] Center 37 (7~68) winsize 62
787 13:53:50.264432 [CA 1] Center 37 (7~68) winsize 62
788 13:53:50.268372 [CA 2] Center 35 (5~66) winsize 62
789 13:53:50.271883 [CA 3] Center 35 (5~66) winsize 62
790 13:53:50.274637 [CA 4] Center 34 (4~65) winsize 62
791 13:53:50.278142 [CA 5] Center 34 (4~65) winsize 62
792 13:53:50.278225
793 13:53:50.281480 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 13:53:50.281563
795 13:53:50.284570 [CATrainingPosCal] consider 1 rank data
796 13:53:50.287841 u2DelayCellTimex100 = 270/100 ps
797 13:53:50.291162 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 13:53:50.294690 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
799 13:53:50.301909 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 13:53:50.304856 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
801 13:53:50.307848 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
802 13:53:50.311343 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
803 13:53:50.311425
804 13:53:50.314807 CA PerBit enable=1, Macro0, CA PI delay=34
805 13:53:50.314890
806 13:53:50.317991 [CBTSetCACLKResult] CA Dly = 34
807 13:53:50.318074 CS Dly: 5 (0~36)
808 13:53:50.318138 ==
809 13:53:50.321411 Dram Type= 6, Freq= 0, CH_0, rank 1
810 13:53:50.328223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 13:53:50.328307 ==
812 13:53:50.331936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 13:53:50.338280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 13:53:50.347905 [CA 0] Center 37 (6~68) winsize 63
815 13:53:50.350745 [CA 1] Center 37 (6~68) winsize 63
816 13:53:50.353904 [CA 2] Center 35 (4~66) winsize 63
817 13:53:50.356998 [CA 3] Center 34 (4~65) winsize 62
818 13:53:50.360644 [CA 4] Center 33 (3~64) winsize 62
819 13:53:50.363765 [CA 5] Center 33 (3~64) winsize 62
820 13:53:50.363872
821 13:53:50.367035 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 13:53:50.367118
823 13:53:50.370540 [CATrainingPosCal] consider 2 rank data
824 13:53:50.374211 u2DelayCellTimex100 = 270/100 ps
825 13:53:50.377802 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 13:53:50.380602 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 13:53:50.386972 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 13:53:50.390630 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
829 13:53:50.393877 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
830 13:53:50.397016 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 13:53:50.397098
832 13:53:50.400753 CA PerBit enable=1, Macro0, CA PI delay=34
833 13:53:50.400849
834 13:53:50.403781 [CBTSetCACLKResult] CA Dly = 34
835 13:53:50.403863 CS Dly: 6 (0~38)
836 13:53:50.403929
837 13:53:50.407831 ----->DramcWriteLeveling(PI) begin...
838 13:53:50.407915 ==
839 13:53:50.410779 Dram Type= 6, Freq= 0, CH_0, rank 0
840 13:53:50.416914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 13:53:50.416998 ==
842 13:53:50.420718 Write leveling (Byte 0): 30 => 30
843 13:53:50.423557 Write leveling (Byte 1): 30 => 30
844 13:53:50.427099 DramcWriteLeveling(PI) end<-----
845 13:53:50.427188
846 13:53:50.427253 ==
847 13:53:50.430671 Dram Type= 6, Freq= 0, CH_0, rank 0
848 13:53:50.433541 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 13:53:50.433652 ==
850 13:53:50.439165 [Gating] SW mode calibration
851 13:53:50.443551 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 13:53:50.447596 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 13:53:50.453808 0 6 0 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 0)
854 13:53:50.457062 0 6 4 | B1->B0 | 2c2c 2626 | 0 0 | (1 1) (1 1)
855 13:53:50.460270 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:53:50.466978 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:53:50.471013 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:53:50.474187 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:53:50.480173 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:53:50.483995 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:53:50.486913 0 7 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
862 13:53:50.494073 0 7 4 | B1->B0 | 3737 3c3c | 0 1 | (0 0) (0 0)
863 13:53:50.496750 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 13:53:50.499848 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 13:53:50.507133 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 13:53:50.509730 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 13:53:50.513647 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 13:53:50.519726 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 13:53:50.523129 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 13:53:50.526672 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
871 13:53:50.533340 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 13:53:50.536527 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 13:53:50.540181 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 13:53:50.546460 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 13:53:50.550250 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 13:53:50.553516 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 13:53:50.559866 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 13:53:50.563378 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 13:53:50.567143 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 13:53:50.573644 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 13:53:50.577222 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 13:53:50.580518 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 13:53:50.583455 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 13:53:50.590170 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 13:53:50.593185 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 13:53:50.596567 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 13:53:50.599841 Total UI for P1: 0, mck2ui 16
888 13:53:50.603158 best dqsien dly found for B0: ( 0, 10, 0)
889 13:53:50.606803 Total UI for P1: 0, mck2ui 16
890 13:53:50.609992 best dqsien dly found for B1: ( 0, 10, 0)
891 13:53:50.613551 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 13:53:50.617347 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 13:53:50.617430
894 13:53:50.623646 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 13:53:50.626736 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 13:53:50.631213 [Gating] SW calibration Done
897 13:53:50.631295 ==
898 13:53:50.633482 Dram Type= 6, Freq= 0, CH_0, rank 0
899 13:53:50.636852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 13:53:50.636934 ==
901 13:53:50.637000 RX Vref Scan: 0
902 13:53:50.637062
903 13:53:50.640288 RX Vref 0 -> 0, step: 1
904 13:53:50.640464
905 13:53:50.643703 RX Delay -130 -> 252, step: 16
906 13:53:50.646914 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 13:53:50.650318 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 13:53:50.653672 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 13:53:50.660393 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 13:53:50.663852 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 13:53:50.667029 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 13:53:50.670435 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 13:53:50.673968 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
914 13:53:50.680424 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
915 13:53:50.683778 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
916 13:53:50.687301 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 13:53:50.690517 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 13:53:50.693911 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 13:53:50.700468 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
920 13:53:50.704033 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 13:53:50.707346 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 13:53:50.707429 ==
923 13:53:50.710753 Dram Type= 6, Freq= 0, CH_0, rank 0
924 13:53:50.713989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 13:53:50.714096 ==
926 13:53:50.716772 DQS Delay:
927 13:53:50.716854 DQS0 = 0, DQS1 = 0
928 13:53:50.720647 DQM Delay:
929 13:53:50.720770 DQM0 = 83, DQM1 = 75
930 13:53:50.720837 DQ Delay:
931 13:53:50.723491 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 13:53:50.727056 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
933 13:53:50.729901 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
934 13:53:50.733307 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
935 13:53:50.733389
936 13:53:50.733453
937 13:53:50.737214 ==
938 13:53:50.740920 Dram Type= 6, Freq= 0, CH_0, rank 0
939 13:53:50.744040 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 13:53:50.744122 ==
941 13:53:50.744188
942 13:53:50.744248
943 13:53:50.746580 TX Vref Scan disable
944 13:53:50.746662 == TX Byte 0 ==
945 13:53:50.753277 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 13:53:50.756730 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 13:53:50.756812 == TX Byte 1 ==
948 13:53:50.761327 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 13:53:50.766898 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 13:53:50.766980 ==
951 13:53:50.770270 Dram Type= 6, Freq= 0, CH_0, rank 0
952 13:53:50.773385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 13:53:50.773467 ==
954 13:53:50.786450 TX Vref=22, minBit 0, minWin=27, winSum=443
955 13:53:50.789993 TX Vref=24, minBit 0, minWin=27, winSum=448
956 13:53:50.793755 TX Vref=26, minBit 1, minWin=28, winSum=455
957 13:53:50.796873 TX Vref=28, minBit 4, minWin=27, winSum=455
958 13:53:50.799661 TX Vref=30, minBit 0, minWin=28, winSum=457
959 13:53:50.803030 TX Vref=32, minBit 0, minWin=28, winSum=453
960 13:53:50.810709 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
961 13:53:50.810792
962 13:53:50.813298 Final TX Range 1 Vref 30
963 13:53:50.813381
964 13:53:50.813445 ==
965 13:53:50.816746 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:53:50.819787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 13:53:50.819868 ==
968 13:53:50.819933
969 13:53:50.819993
970 13:53:50.823437 TX Vref Scan disable
971 13:53:50.827185 == TX Byte 0 ==
972 13:53:50.831126 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 13:53:50.833449 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 13:53:50.836756 == TX Byte 1 ==
975 13:53:50.839959 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
976 13:53:50.843252 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
977 13:53:50.847490
978 13:53:50.847571 [DATLAT]
979 13:53:50.847636 Freq=800, CH0 RK0
980 13:53:50.847697
981 13:53:50.850188 DATLAT Default: 0xa
982 13:53:50.850271 0, 0xFFFF, sum = 0
983 13:53:50.853759 1, 0xFFFF, sum = 0
984 13:53:50.853872 2, 0xFFFF, sum = 0
985 13:53:50.856320 3, 0xFFFF, sum = 0
986 13:53:50.856403 4, 0xFFFF, sum = 0
987 13:53:50.859852 5, 0xFFFF, sum = 0
988 13:53:50.859935 6, 0xFFFF, sum = 0
989 13:53:50.862953 7, 0xFFFF, sum = 0
990 13:53:50.863039 8, 0x0, sum = 1
991 13:53:50.866542 9, 0x0, sum = 2
992 13:53:50.866625 10, 0x0, sum = 3
993 13:53:50.869914 11, 0x0, sum = 4
994 13:53:50.869998 best_step = 9
995 13:53:50.870063
996 13:53:50.870124 ==
997 13:53:50.873322 Dram Type= 6, Freq= 0, CH_0, rank 0
998 13:53:50.879959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 13:53:50.880041 ==
1000 13:53:50.880107 RX Vref Scan: 1
1001 13:53:50.880167
1002 13:53:50.882868 Set Vref Range= 32 -> 127
1003 13:53:50.882950
1004 13:53:50.886628 RX Vref 32 -> 127, step: 1
1005 13:53:50.886724
1006 13:53:50.886789 RX Delay -95 -> 252, step: 8
1007 13:53:50.889942
1008 13:53:50.890052 Set Vref, RX VrefLevel [Byte0]: 32
1009 13:53:50.892984 [Byte1]: 32
1010 13:53:50.896986
1011 13:53:50.897068 Set Vref, RX VrefLevel [Byte0]: 33
1012 13:53:50.900500 [Byte1]: 33
1013 13:53:50.905042
1014 13:53:50.905123 Set Vref, RX VrefLevel [Byte0]: 34
1015 13:53:50.907856 [Byte1]: 34
1016 13:53:50.912366
1017 13:53:50.912448 Set Vref, RX VrefLevel [Byte0]: 35
1018 13:53:50.915854 [Byte1]: 35
1019 13:53:50.920133
1020 13:53:50.920215 Set Vref, RX VrefLevel [Byte0]: 36
1021 13:53:50.923363 [Byte1]: 36
1022 13:53:50.927951
1023 13:53:50.928032 Set Vref, RX VrefLevel [Byte0]: 37
1024 13:53:50.931833 [Byte1]: 37
1025 13:53:50.935353
1026 13:53:50.935433 Set Vref, RX VrefLevel [Byte0]: 38
1027 13:53:50.938529 [Byte1]: 38
1028 13:53:50.942684
1029 13:53:50.942764 Set Vref, RX VrefLevel [Byte0]: 39
1030 13:53:50.946422 [Byte1]: 39
1031 13:53:50.952090
1032 13:53:50.952170 Set Vref, RX VrefLevel [Byte0]: 40
1033 13:53:50.953454 [Byte1]: 40
1034 13:53:50.958310
1035 13:53:50.958389 Set Vref, RX VrefLevel [Byte0]: 41
1036 13:53:50.962045 [Byte1]: 41
1037 13:53:50.965953
1038 13:53:50.966033 Set Vref, RX VrefLevel [Byte0]: 42
1039 13:53:50.968961 [Byte1]: 42
1040 13:53:50.973128
1041 13:53:50.973229 Set Vref, RX VrefLevel [Byte0]: 43
1042 13:53:50.976561 [Byte1]: 43
1043 13:53:50.981034
1044 13:53:50.981115 Set Vref, RX VrefLevel [Byte0]: 44
1045 13:53:50.983872 [Byte1]: 44
1046 13:53:50.988251
1047 13:53:50.988331 Set Vref, RX VrefLevel [Byte0]: 45
1048 13:53:50.991715 [Byte1]: 45
1049 13:53:50.996207
1050 13:53:50.996287 Set Vref, RX VrefLevel [Byte0]: 46
1051 13:53:50.999434 [Byte1]: 46
1052 13:53:51.003344
1053 13:53:51.003424 Set Vref, RX VrefLevel [Byte0]: 47
1054 13:53:51.007149 [Byte1]: 47
1055 13:53:51.010965
1056 13:53:51.011044 Set Vref, RX VrefLevel [Byte0]: 48
1057 13:53:51.014595 [Byte1]: 48
1058 13:53:51.020028
1059 13:53:51.020108 Set Vref, RX VrefLevel [Byte0]: 49
1060 13:53:51.021894 [Byte1]: 49
1061 13:53:51.026224
1062 13:53:51.026304 Set Vref, RX VrefLevel [Byte0]: 50
1063 13:53:51.029968 [Byte1]: 50
1064 13:53:51.034236
1065 13:53:51.034316 Set Vref, RX VrefLevel [Byte0]: 51
1066 13:53:51.037632 [Byte1]: 51
1067 13:53:51.041587
1068 13:53:51.041697 Set Vref, RX VrefLevel [Byte0]: 52
1069 13:53:51.045246 [Byte1]: 52
1070 13:53:51.049167
1071 13:53:51.049247 Set Vref, RX VrefLevel [Byte0]: 53
1072 13:53:51.052893 [Byte1]: 53
1073 13:53:51.056963
1074 13:53:51.057043 Set Vref, RX VrefLevel [Byte0]: 54
1075 13:53:51.060043 [Byte1]: 54
1076 13:53:51.064385
1077 13:53:51.064465 Set Vref, RX VrefLevel [Byte0]: 55
1078 13:53:51.067828 [Byte1]: 55
1079 13:53:51.071961
1080 13:53:51.072042 Set Vref, RX VrefLevel [Byte0]: 56
1081 13:53:51.075296 [Byte1]: 56
1082 13:53:51.079391
1083 13:53:51.079471 Set Vref, RX VrefLevel [Byte0]: 57
1084 13:53:51.082900 [Byte1]: 57
1085 13:53:51.087771
1086 13:53:51.087852 Set Vref, RX VrefLevel [Byte0]: 58
1087 13:53:51.090542 [Byte1]: 58
1088 13:53:51.095000
1089 13:53:51.095080 Set Vref, RX VrefLevel [Byte0]: 59
1090 13:53:51.097899 [Byte1]: 59
1091 13:53:51.103056
1092 13:53:51.103137 Set Vref, RX VrefLevel [Byte0]: 60
1093 13:53:51.105571 [Byte1]: 60
1094 13:53:51.110062
1095 13:53:51.110142 Set Vref, RX VrefLevel [Byte0]: 61
1096 13:53:51.113246 [Byte1]: 61
1097 13:53:51.118024
1098 13:53:51.118104 Set Vref, RX VrefLevel [Byte0]: 62
1099 13:53:51.120813 [Byte1]: 62
1100 13:53:51.125190
1101 13:53:51.125294 Set Vref, RX VrefLevel [Byte0]: 63
1102 13:53:51.128486 [Byte1]: 63
1103 13:53:51.132793
1104 13:53:51.132904 Set Vref, RX VrefLevel [Byte0]: 64
1105 13:53:51.135678 [Byte1]: 64
1106 13:53:51.140847
1107 13:53:51.140953 Set Vref, RX VrefLevel [Byte0]: 65
1108 13:53:51.143679 [Byte1]: 65
1109 13:53:51.148041
1110 13:53:51.148122 Set Vref, RX VrefLevel [Byte0]: 66
1111 13:53:51.151632 [Byte1]: 66
1112 13:53:51.155488
1113 13:53:51.155569 Set Vref, RX VrefLevel [Byte0]: 67
1114 13:53:51.159169 [Byte1]: 67
1115 13:53:51.163110
1116 13:53:51.163189 Set Vref, RX VrefLevel [Byte0]: 68
1117 13:53:51.166351 [Byte1]: 68
1118 13:53:51.170510
1119 13:53:51.170590 Set Vref, RX VrefLevel [Byte0]: 69
1120 13:53:51.173803 [Byte1]: 69
1121 13:53:51.178088
1122 13:53:51.178168 Set Vref, RX VrefLevel [Byte0]: 70
1123 13:53:51.182190 [Byte1]: 70
1124 13:53:51.185848
1125 13:53:51.185928 Set Vref, RX VrefLevel [Byte0]: 71
1126 13:53:51.189735 [Byte1]: 71
1127 13:53:51.193592
1128 13:53:51.193672 Set Vref, RX VrefLevel [Byte0]: 72
1129 13:53:51.196525 [Byte1]: 72
1130 13:53:51.201111
1131 13:53:51.201195 Set Vref, RX VrefLevel [Byte0]: 73
1132 13:53:51.204944 [Byte1]: 73
1133 13:53:51.208686
1134 13:53:51.208772 Set Vref, RX VrefLevel [Byte0]: 74
1135 13:53:51.211810 [Byte1]: 74
1136 13:53:51.216060
1137 13:53:51.216139 Set Vref, RX VrefLevel [Byte0]: 75
1138 13:53:51.219932 [Byte1]: 75
1139 13:53:51.224123
1140 13:53:51.224204 Final RX Vref Byte 0 = 51 to rank0
1141 13:53:51.226900 Final RX Vref Byte 1 = 57 to rank0
1142 13:53:51.230573 Final RX Vref Byte 0 = 51 to rank1
1143 13:53:51.234172 Final RX Vref Byte 1 = 57 to rank1==
1144 13:53:51.237382 Dram Type= 6, Freq= 0, CH_0, rank 0
1145 13:53:51.244043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1146 13:53:51.244125 ==
1147 13:53:51.244189 DQS Delay:
1148 13:53:51.244248 DQS0 = 0, DQS1 = 0
1149 13:53:51.247187 DQM Delay:
1150 13:53:51.247267 DQM0 = 84, DQM1 = 73
1151 13:53:51.250614 DQ Delay:
1152 13:53:51.253783 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1153 13:53:51.253864 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1154 13:53:51.257526 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1155 13:53:51.260137 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1156 13:53:51.264632
1157 13:53:51.264718
1158 13:53:51.271151 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1159 13:53:51.273901 CH0 RK0: MR19=606, MR18=3636
1160 13:53:51.280238 CH0_RK0: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1161 13:53:51.280320
1162 13:53:51.284108 ----->DramcWriteLeveling(PI) begin...
1163 13:53:51.284189 ==
1164 13:53:51.287427 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 13:53:51.290729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1166 13:53:51.290810 ==
1167 13:53:51.294127 Write leveling (Byte 0): 32 => 32
1168 13:53:51.297384 Write leveling (Byte 1): 28 => 28
1169 13:53:51.300596 DramcWriteLeveling(PI) end<-----
1170 13:53:51.300702
1171 13:53:51.300787 ==
1172 13:53:51.303966 Dram Type= 6, Freq= 0, CH_0, rank 1
1173 13:53:51.307056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1174 13:53:51.307137 ==
1175 13:53:51.310494 [Gating] SW mode calibration
1176 13:53:51.317716 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1177 13:53:51.323555 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1178 13:53:51.326910 0 6 0 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 1)
1179 13:53:51.330170 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1180 13:53:51.336895 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:53:51.340583 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:53:51.344139 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:53:51.351058 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:53:51.354265 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:53:51.356812 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:53:51.365505 0 7 0 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (0 0)
1187 13:53:51.367029 0 7 4 | B1->B0 | 4040 3e3e | 0 0 | (1 1) (0 0)
1188 13:53:51.370531 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 13:53:51.377382 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 13:53:51.380488 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 13:53:51.384085 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 13:53:51.387163 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 13:53:51.393497 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:53:51.397697 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1195 13:53:51.400394 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 13:53:51.407566 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:53:51.410698 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:53:51.414603 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:53:51.420501 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:53:51.424004 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:53:51.427275 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:53:51.433937 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:53:51.437609 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:53:51.440668 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:53:51.447103 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:53:51.450411 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:53:51.454348 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:53:51.461568 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:53:51.463699 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:53:51.467832 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1211 13:53:51.473626 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1212 13:53:51.477325 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 13:53:51.480369 Total UI for P1: 0, mck2ui 16
1214 13:53:51.483970 best dqsien dly found for B0: ( 0, 10, 2)
1215 13:53:51.487645 Total UI for P1: 0, mck2ui 16
1216 13:53:51.490214 best dqsien dly found for B1: ( 0, 10, 2)
1217 13:53:51.494112 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1218 13:53:51.496983 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1219 13:53:51.497064
1220 13:53:51.500243 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1221 13:53:51.503624 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1222 13:53:51.507408 [Gating] SW calibration Done
1223 13:53:51.507488 ==
1224 13:53:51.510138 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 13:53:51.514054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1226 13:53:51.514136 ==
1227 13:53:51.558361 RX Vref Scan: 0
1228 13:53:51.558450
1229 13:53:51.558514 RX Vref 0 -> 0, step: 1
1230 13:53:51.558574
1231 13:53:51.559375 RX Delay -130 -> 252, step: 16
1232 13:53:51.559456 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1233 13:53:51.560561 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1234 13:53:51.562210 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1235 13:53:51.563061 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1236 13:53:51.563161 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1237 13:53:51.563486 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1238 13:53:51.563841 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1239 13:53:51.563923 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1240 13:53:51.564171 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1241 13:53:51.564523 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1242 13:53:51.572619 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1243 13:53:51.572724 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1244 13:53:51.575446 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1245 13:53:51.579104 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1246 13:53:51.582241 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1247 13:53:51.585633 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1248 13:53:51.585714 ==
1249 13:53:51.588864 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 13:53:51.592635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1251 13:53:51.592724 ==
1252 13:53:51.595218 DQS Delay:
1253 13:53:51.595298 DQS0 = 0, DQS1 = 0
1254 13:53:51.598649 DQM Delay:
1255 13:53:51.598729 DQM0 = 82, DQM1 = 74
1256 13:53:51.598792 DQ Delay:
1257 13:53:51.602198 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =69
1258 13:53:51.605352 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1259 13:53:51.609243 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1260 13:53:51.612305 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1261 13:53:51.612386
1262 13:53:51.612448
1263 13:53:51.615115 ==
1264 13:53:51.615195 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 13:53:51.622849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1266 13:53:51.622931 ==
1267 13:53:51.622995
1268 13:53:51.623054
1269 13:53:51.625519 TX Vref Scan disable
1270 13:53:51.625599 == TX Byte 0 ==
1271 13:53:51.628628 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1272 13:53:51.635344 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1273 13:53:51.635425 == TX Byte 1 ==
1274 13:53:51.639501 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1275 13:53:51.645524 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1276 13:53:51.645605 ==
1277 13:53:51.649018 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 13:53:51.652107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1279 13:53:51.652188 ==
1280 13:53:51.665360 TX Vref=22, minBit 14, minWin=27, winSum=447
1281 13:53:51.668765 TX Vref=24, minBit 0, minWin=28, winSum=452
1282 13:53:51.672388 TX Vref=26, minBit 2, minWin=28, winSum=458
1283 13:53:51.675571 TX Vref=28, minBit 2, minWin=28, winSum=456
1284 13:53:51.679194 TX Vref=30, minBit 0, minWin=28, winSum=454
1285 13:53:51.685581 TX Vref=32, minBit 1, minWin=28, winSum=455
1286 13:53:51.689182 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 26
1287 13:53:51.689262
1288 13:53:51.692431 Final TX Range 1 Vref 26
1289 13:53:51.692511
1290 13:53:51.692574 ==
1291 13:53:51.696266 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 13:53:51.698952 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1293 13:53:51.699037 ==
1294 13:53:51.699100
1295 13:53:51.702081
1296 13:53:51.702161 TX Vref Scan disable
1297 13:53:51.705491 == TX Byte 0 ==
1298 13:53:51.709089 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1299 13:53:51.713025 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1300 13:53:51.716905 == TX Byte 1 ==
1301 13:53:51.718616 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1302 13:53:51.722172 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1303 13:53:51.726375
1304 13:53:51.726454 [DATLAT]
1305 13:53:51.726518 Freq=800, CH0 RK1
1306 13:53:51.726579
1307 13:53:51.729147 DATLAT Default: 0x9
1308 13:53:51.729228 0, 0xFFFF, sum = 0
1309 13:53:51.732094 1, 0xFFFF, sum = 0
1310 13:53:51.732176 2, 0xFFFF, sum = 0
1311 13:53:51.736437 3, 0xFFFF, sum = 0
1312 13:53:51.736518 4, 0xFFFF, sum = 0
1313 13:53:51.739374 5, 0xFFFF, sum = 0
1314 13:53:51.739457 6, 0xFFFF, sum = 0
1315 13:53:51.742146 7, 0xFFFF, sum = 0
1316 13:53:51.742227 8, 0x0, sum = 1
1317 13:53:51.746205 9, 0x0, sum = 2
1318 13:53:51.746286 10, 0x0, sum = 3
1319 13:53:51.748892 11, 0x0, sum = 4
1320 13:53:51.748974 best_step = 9
1321 13:53:51.749037
1322 13:53:51.749095 ==
1323 13:53:51.752597 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 13:53:51.758855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1325 13:53:51.758936 ==
1326 13:53:51.759000 RX Vref Scan: 0
1327 13:53:51.759059
1328 13:53:51.762263 RX Vref 0 -> 0, step: 1
1329 13:53:51.762344
1330 13:53:51.765571 RX Delay -111 -> 252, step: 8
1331 13:53:51.768805 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1332 13:53:51.772664 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1333 13:53:51.779070 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1334 13:53:51.782331 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1335 13:53:51.785716 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1336 13:53:51.789626 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1337 13:53:51.792966 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1338 13:53:51.798885 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1339 13:53:51.802179 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1340 13:53:51.807858 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1341 13:53:51.808650 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1342 13:53:51.811669 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1343 13:53:51.818534 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1344 13:53:51.822146 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1345 13:53:51.825383 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1346 13:53:51.828518 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1347 13:53:51.828598 ==
1348 13:53:51.832217 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 13:53:51.839110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1350 13:53:51.839191 ==
1351 13:53:51.839255 DQS Delay:
1352 13:53:51.839314 DQS0 = 0, DQS1 = 0
1353 13:53:51.842238 DQM Delay:
1354 13:53:51.842319 DQM0 = 86, DQM1 = 74
1355 13:53:51.845316 DQ Delay:
1356 13:53:51.848829 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1357 13:53:51.848909 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1358 13:53:51.851676 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1359 13:53:51.858492 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1360 13:53:51.858577
1361 13:53:51.858639
1362 13:53:51.865599 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1363 13:53:51.868533 CH0 RK1: MR19=606, MR18=4C4C
1364 13:53:51.875920 CH0_RK1: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1365 13:53:51.878442 [RxdqsGatingPostProcess] freq 800
1366 13:53:51.881670 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1367 13:53:51.885032 Pre-setting of DQS Precalculation
1368 13:53:51.892592 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1369 13:53:51.892672 ==
1370 13:53:51.895617 Dram Type= 6, Freq= 0, CH_1, rank 0
1371 13:53:51.898151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1372 13:53:51.898285 ==
1373 13:53:51.905267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1374 13:53:51.908361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1375 13:53:51.918500 [CA 0] Center 36 (6~67) winsize 62
1376 13:53:51.922664 [CA 1] Center 36 (5~67) winsize 63
1377 13:53:51.925454 [CA 2] Center 34 (4~65) winsize 62
1378 13:53:51.928680 [CA 3] Center 34 (4~64) winsize 61
1379 13:53:51.931886 [CA 4] Center 33 (2~64) winsize 63
1380 13:53:51.935377 [CA 5] Center 33 (3~64) winsize 62
1381 13:53:51.935456
1382 13:53:51.938708 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1383 13:53:51.938788
1384 13:53:51.941902 [CATrainingPosCal] consider 1 rank data
1385 13:53:51.944930 u2DelayCellTimex100 = 270/100 ps
1386 13:53:51.948445 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1387 13:53:51.952177 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1388 13:53:51.958136 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 13:53:51.961701 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1390 13:53:51.965576 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1391 13:53:51.968920 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1392 13:53:51.968999
1393 13:53:51.971560 CA PerBit enable=1, Macro0, CA PI delay=33
1394 13:53:51.971640
1395 13:53:51.975380 [CBTSetCACLKResult] CA Dly = 33
1396 13:53:51.975460 CS Dly: 4 (0~35)
1397 13:53:51.975523 ==
1398 13:53:51.978350 Dram Type= 6, Freq= 0, CH_1, rank 1
1399 13:53:51.985140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1400 13:53:51.985221 ==
1401 13:53:51.988850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1402 13:53:51.994939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1403 13:53:52.004403 [CA 0] Center 36 (6~67) winsize 62
1404 13:53:52.007742 [CA 1] Center 36 (5~67) winsize 63
1405 13:53:52.011249 [CA 2] Center 34 (4~65) winsize 62
1406 13:53:52.013974 [CA 3] Center 33 (3~64) winsize 62
1407 13:53:52.017960 [CA 4] Center 33 (3~64) winsize 62
1408 13:53:52.021899 [CA 5] Center 33 (3~64) winsize 62
1409 13:53:52.021978
1410 13:53:52.023941 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1411 13:53:52.024021
1412 13:53:52.027352 [CATrainingPosCal] consider 2 rank data
1413 13:53:52.031226 u2DelayCellTimex100 = 270/100 ps
1414 13:53:52.033900 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1415 13:53:52.037683 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1416 13:53:52.044164 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 13:53:52.047346 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1418 13:53:52.050834 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1419 13:53:52.054649 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1420 13:53:52.054730
1421 13:53:52.058103 CA PerBit enable=1, Macro0, CA PI delay=33
1422 13:53:52.058183
1423 13:53:52.060841 [CBTSetCACLKResult] CA Dly = 33
1424 13:53:52.060922 CS Dly: 4 (0~36)
1425 13:53:52.060985
1426 13:53:52.064351 ----->DramcWriteLeveling(PI) begin...
1427 13:53:52.067591 ==
1428 13:53:52.067672 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 13:53:52.074704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1430 13:53:52.074784 ==
1431 13:53:52.077970 Write leveling (Byte 0): 23 => 23
1432 13:53:52.080978 Write leveling (Byte 1): 24 => 24
1433 13:53:52.084496 DramcWriteLeveling(PI) end<-----
1434 13:53:52.084576
1435 13:53:52.084638 ==
1436 13:53:52.087109 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 13:53:52.090572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1438 13:53:52.090653 ==
1439 13:53:52.093875 [Gating] SW mode calibration
1440 13:53:52.100590 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1441 13:53:52.104557 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1442 13:53:52.111183 0 6 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1443 13:53:52.114671 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 13:53:52.117645 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 13:53:52.123931 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 13:53:52.128616 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 13:53:52.130869 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:53:52.137351 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:53:52.141588 0 6 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1450 13:53:52.144107 0 7 0 | B1->B0 | 2e2e 4242 | 0 0 | (0 0) (0 0)
1451 13:53:52.150997 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1452 13:53:52.154245 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 13:53:52.157590 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 13:53:52.164092 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 13:53:52.167970 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1456 13:53:52.170609 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1457 13:53:52.174359 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1458 13:53:52.181197 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1459 13:53:52.184688 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 13:53:52.187514 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 13:53:52.193965 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 13:53:52.197455 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 13:53:52.200892 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 13:53:52.208141 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 13:53:52.211499 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 13:53:52.214244 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 13:53:52.221040 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 13:53:52.224456 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 13:53:52.227439 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 13:53:52.235121 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 13:53:52.237274 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1472 13:53:52.240616 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1473 13:53:52.247505 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1474 13:53:52.250817 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1475 13:53:52.254358 Total UI for P1: 0, mck2ui 16
1476 13:53:52.257477 best dqsien dly found for B0: ( 0, 9, 28)
1477 13:53:52.261019 Total UI for P1: 0, mck2ui 16
1478 13:53:52.263942 best dqsien dly found for B1: ( 0, 9, 30)
1479 13:53:52.268273 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1480 13:53:52.270934 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1481 13:53:52.271015
1482 13:53:52.274136 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1483 13:53:52.277587 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1484 13:53:52.281157 [Gating] SW calibration Done
1485 13:53:52.281246 ==
1486 13:53:52.284242 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 13:53:52.287742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1488 13:53:52.287823 ==
1489 13:53:52.291233 RX Vref Scan: 0
1490 13:53:52.291313
1491 13:53:52.294753 RX Vref 0 -> 0, step: 1
1492 13:53:52.294833
1493 13:53:52.294896 RX Delay -130 -> 252, step: 16
1494 13:53:52.301033 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1495 13:53:52.304132 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1496 13:53:52.307750 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1497 13:53:52.310569 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1498 13:53:52.313904 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1499 13:53:52.321040 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1500 13:53:52.324144 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1501 13:53:52.327499 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1502 13:53:52.330537 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1503 13:53:52.334366 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1504 13:53:52.341155 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1505 13:53:52.344633 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1506 13:53:52.348930 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1507 13:53:52.351686 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1508 13:53:52.357347 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1509 13:53:52.360613 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1510 13:53:52.360696 ==
1511 13:53:52.364017 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 13:53:52.367584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1513 13:53:52.367667 ==
1514 13:53:52.370584 DQS Delay:
1515 13:53:52.370667 DQS0 = 0, DQS1 = 0
1516 13:53:52.370753 DQM Delay:
1517 13:53:52.373848 DQM0 = 81, DQM1 = 70
1518 13:53:52.373932 DQ Delay:
1519 13:53:52.377343 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1520 13:53:52.381323 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1521 13:53:52.383598 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1522 13:53:52.387268 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1523 13:53:52.387351
1524 13:53:52.387435
1525 13:53:52.387515 ==
1526 13:53:52.390425 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 13:53:52.393720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1528 13:53:52.397118 ==
1529 13:53:52.397201
1530 13:53:52.397285
1531 13:53:52.397366 TX Vref Scan disable
1532 13:53:52.400695 == TX Byte 0 ==
1533 13:53:52.404195 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1534 13:53:52.406903 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1535 13:53:52.410494 == TX Byte 1 ==
1536 13:53:52.413969 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1537 13:53:52.417791 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1538 13:53:52.420582 ==
1539 13:53:52.420736 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 13:53:52.427015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1541 13:53:52.427098 ==
1542 13:53:52.439351 TX Vref=22, minBit 13, minWin=27, winSum=452
1543 13:53:52.442666 TX Vref=24, minBit 0, minWin=28, winSum=456
1544 13:53:52.446084 TX Vref=26, minBit 3, minWin=28, winSum=459
1545 13:53:52.449890 TX Vref=28, minBit 3, minWin=28, winSum=460
1546 13:53:52.454442 TX Vref=30, minBit 3, minWin=28, winSum=461
1547 13:53:52.457148 TX Vref=32, minBit 2, minWin=28, winSum=460
1548 13:53:52.462999 [TxChooseVref] Worse bit 3, Min win 28, Win sum 461, Final Vref 30
1549 13:53:52.463083
1550 13:53:52.466012 Final TX Range 1 Vref 30
1551 13:53:52.466095
1552 13:53:52.466179 ==
1553 13:53:52.469776 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 13:53:52.472321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1555 13:53:52.472404 ==
1556 13:53:52.475845
1557 13:53:52.475927
1558 13:53:52.476012 TX Vref Scan disable
1559 13:53:52.478981 == TX Byte 0 ==
1560 13:53:52.483144 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1561 13:53:52.489632 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1562 13:53:52.489715 == TX Byte 1 ==
1563 13:53:52.492507 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1564 13:53:52.498922 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1565 13:53:52.499005
1566 13:53:52.499104 [DATLAT]
1567 13:53:52.499223 Freq=800, CH1 RK0
1568 13:53:52.499316
1569 13:53:52.502495 DATLAT Default: 0xa
1570 13:53:52.502593 0, 0xFFFF, sum = 0
1571 13:53:52.505786 1, 0xFFFF, sum = 0
1572 13:53:52.505876 2, 0xFFFF, sum = 0
1573 13:53:52.508687 3, 0xFFFF, sum = 0
1574 13:53:52.508780 4, 0xFFFF, sum = 0
1575 13:53:52.512693 5, 0xFFFF, sum = 0
1576 13:53:52.516658 6, 0xFFFF, sum = 0
1577 13:53:52.516751 7, 0xFFFF, sum = 0
1578 13:53:52.516838 8, 0x0, sum = 1
1579 13:53:52.519458 9, 0x0, sum = 2
1580 13:53:52.519542 10, 0x0, sum = 3
1581 13:53:52.523062 11, 0x0, sum = 4
1582 13:53:52.523147 best_step = 9
1583 13:53:52.523231
1584 13:53:52.523311 ==
1585 13:53:52.525582 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 13:53:52.532875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1587 13:53:52.532961 ==
1588 13:53:52.533046 RX Vref Scan: 1
1589 13:53:52.533125
1590 13:53:52.535966 Set Vref Range= 32 -> 127
1591 13:53:52.536049
1592 13:53:52.539049 RX Vref 32 -> 127, step: 1
1593 13:53:52.539131
1594 13:53:52.539216 RX Delay -111 -> 252, step: 8
1595 13:53:52.542764
1596 13:53:52.542847 Set Vref, RX VrefLevel [Byte0]: 32
1597 13:53:52.545895 [Byte1]: 32
1598 13:53:52.550011
1599 13:53:52.550094 Set Vref, RX VrefLevel [Byte0]: 33
1600 13:53:52.553200 [Byte1]: 33
1601 13:53:52.557497
1602 13:53:52.557579 Set Vref, RX VrefLevel [Byte0]: 34
1603 13:53:52.561215 [Byte1]: 34
1604 13:53:52.565298
1605 13:53:52.565380 Set Vref, RX VrefLevel [Byte0]: 35
1606 13:53:52.568791 [Byte1]: 35
1607 13:53:52.573643
1608 13:53:52.573729 Set Vref, RX VrefLevel [Byte0]: 36
1609 13:53:52.576371 [Byte1]: 36
1610 13:53:52.580571
1611 13:53:52.580655 Set Vref, RX VrefLevel [Byte0]: 37
1612 13:53:52.583947 [Byte1]: 37
1613 13:53:52.588726
1614 13:53:52.588809 Set Vref, RX VrefLevel [Byte0]: 38
1615 13:53:52.591552 [Byte1]: 38
1616 13:53:52.596077
1617 13:53:52.596160 Set Vref, RX VrefLevel [Byte0]: 39
1618 13:53:52.599176 [Byte1]: 39
1619 13:53:52.604022
1620 13:53:52.604106 Set Vref, RX VrefLevel [Byte0]: 40
1621 13:53:52.606509 [Byte1]: 40
1622 13:53:52.611000
1623 13:53:52.611083 Set Vref, RX VrefLevel [Byte0]: 41
1624 13:53:52.614647 [Byte1]: 41
1625 13:53:52.619098
1626 13:53:52.619181 Set Vref, RX VrefLevel [Byte0]: 42
1627 13:53:52.621841 [Byte1]: 42
1628 13:53:52.627319
1629 13:53:52.627402 Set Vref, RX VrefLevel [Byte0]: 43
1630 13:53:52.629576 [Byte1]: 43
1631 13:53:52.634135
1632 13:53:52.634218 Set Vref, RX VrefLevel [Byte0]: 44
1633 13:53:52.637859 [Byte1]: 44
1634 13:53:52.641529
1635 13:53:52.641611 Set Vref, RX VrefLevel [Byte0]: 45
1636 13:53:52.645435 [Byte1]: 45
1637 13:53:52.649559
1638 13:53:52.649641 Set Vref, RX VrefLevel [Byte0]: 46
1639 13:53:52.652555 [Byte1]: 46
1640 13:53:52.656905
1641 13:53:52.656988 Set Vref, RX VrefLevel [Byte0]: 47
1642 13:53:52.663299 [Byte1]: 47
1643 13:53:52.663383
1644 13:53:52.667177 Set Vref, RX VrefLevel [Byte0]: 48
1645 13:53:52.670864 [Byte1]: 48
1646 13:53:52.670947
1647 13:53:52.673481 Set Vref, RX VrefLevel [Byte0]: 49
1648 13:53:52.677494 [Byte1]: 49
1649 13:53:52.677577
1650 13:53:52.680253 Set Vref, RX VrefLevel [Byte0]: 50
1651 13:53:52.683222 [Byte1]: 50
1652 13:53:52.688886
1653 13:53:52.688969 Set Vref, RX VrefLevel [Byte0]: 51
1654 13:53:52.691899 [Byte1]: 51
1655 13:53:52.695538
1656 13:53:52.695620 Set Vref, RX VrefLevel [Byte0]: 52
1657 13:53:52.698748 [Byte1]: 52
1658 13:53:52.702742
1659 13:53:52.702825 Set Vref, RX VrefLevel [Byte0]: 53
1660 13:53:52.706148 [Byte1]: 53
1661 13:53:52.710879
1662 13:53:52.710961 Set Vref, RX VrefLevel [Byte0]: 54
1663 13:53:52.714059 [Byte1]: 54
1664 13:53:52.718587
1665 13:53:52.718670 Set Vref, RX VrefLevel [Byte0]: 55
1666 13:53:52.721609 [Byte1]: 55
1667 13:53:52.725931
1668 13:53:52.726014 Set Vref, RX VrefLevel [Byte0]: 56
1669 13:53:52.729498 [Byte1]: 56
1670 13:53:52.733947
1671 13:53:52.734029 Set Vref, RX VrefLevel [Byte0]: 57
1672 13:53:52.737209 [Byte1]: 57
1673 13:53:52.741190
1674 13:53:52.741277 Set Vref, RX VrefLevel [Byte0]: 58
1675 13:53:52.744729 [Byte1]: 58
1676 13:53:52.748841
1677 13:53:52.748924 Set Vref, RX VrefLevel [Byte0]: 59
1678 13:53:52.752207 [Byte1]: 59
1679 13:53:52.756520
1680 13:53:52.756603 Set Vref, RX VrefLevel [Byte0]: 60
1681 13:53:52.759712 [Byte1]: 60
1682 13:53:52.764922
1683 13:53:52.765006 Set Vref, RX VrefLevel [Byte0]: 61
1684 13:53:52.767273 [Byte1]: 61
1685 13:53:52.772180
1686 13:53:52.772263 Set Vref, RX VrefLevel [Byte0]: 62
1687 13:53:52.774846 [Byte1]: 62
1688 13:53:52.779911
1689 13:53:52.779994 Set Vref, RX VrefLevel [Byte0]: 63
1690 13:53:52.782663 [Byte1]: 63
1691 13:53:52.787844
1692 13:53:52.787928 Set Vref, RX VrefLevel [Byte0]: 64
1693 13:53:52.790483 [Byte1]: 64
1694 13:53:52.794771
1695 13:53:52.794854 Set Vref, RX VrefLevel [Byte0]: 65
1696 13:53:52.799953 [Byte1]: 65
1697 13:53:52.802753
1698 13:53:52.802836 Set Vref, RX VrefLevel [Byte0]: 66
1699 13:53:52.805806 [Byte1]: 66
1700 13:53:52.810429
1701 13:53:52.810511 Set Vref, RX VrefLevel [Byte0]: 67
1702 13:53:52.813400 [Byte1]: 67
1703 13:53:52.817502
1704 13:53:52.817585 Set Vref, RX VrefLevel [Byte0]: 68
1705 13:53:52.820857 [Byte1]: 68
1706 13:53:52.825222
1707 13:53:52.828842 Set Vref, RX VrefLevel [Byte0]: 69
1708 13:53:52.828923 [Byte1]: 69
1709 13:53:52.833240
1710 13:53:52.833320 Set Vref, RX VrefLevel [Byte0]: 70
1711 13:53:52.837070 [Byte1]: 70
1712 13:53:52.840398
1713 13:53:52.840478 Set Vref, RX VrefLevel [Byte0]: 71
1714 13:53:52.844544 [Byte1]: 71
1715 13:53:52.848333
1716 13:53:52.848412 Set Vref, RX VrefLevel [Byte0]: 72
1717 13:53:52.851801 [Byte1]: 72
1718 13:53:52.855904
1719 13:53:52.855984 Set Vref, RX VrefLevel [Byte0]: 73
1720 13:53:52.859226 [Byte1]: 73
1721 13:53:52.863273
1722 13:53:52.863354 Set Vref, RX VrefLevel [Byte0]: 74
1723 13:53:52.866728 [Byte1]: 74
1724 13:53:52.871335
1725 13:53:52.871416 Final RX Vref Byte 0 = 59 to rank0
1726 13:53:52.874581 Final RX Vref Byte 1 = 55 to rank0
1727 13:53:52.878271 Final RX Vref Byte 0 = 59 to rank1
1728 13:53:52.881016 Final RX Vref Byte 1 = 55 to rank1==
1729 13:53:52.884544 Dram Type= 6, Freq= 0, CH_1, rank 0
1730 13:53:52.891070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1731 13:53:52.891152 ==
1732 13:53:52.891216 DQS Delay:
1733 13:53:52.891275 DQS0 = 0, DQS1 = 0
1734 13:53:52.894977 DQM Delay:
1735 13:53:52.895057 DQM0 = 79, DQM1 = 72
1736 13:53:52.898028 DQ Delay:
1737 13:53:52.901505 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
1738 13:53:52.901586 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1739 13:53:52.904998 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1740 13:53:52.908348 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1741 13:53:52.908428
1742 13:53:52.911616
1743 13:53:52.918106 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1744 13:53:52.921241 CH1 RK0: MR19=606, MR18=5656
1745 13:53:52.928201 CH1_RK0: MR19=0x606, MR18=0x5656, DQSOSC=388, MR23=63, INC=98, DEC=65
1746 13:53:52.928286
1747 13:53:52.931187 ----->DramcWriteLeveling(PI) begin...
1748 13:53:52.931271 ==
1749 13:53:52.934584 Dram Type= 6, Freq= 0, CH_1, rank 1
1750 13:53:52.938070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1751 13:53:52.938154 ==
1752 13:53:52.941347 Write leveling (Byte 0): 23 => 23
1753 13:53:52.945420 Write leveling (Byte 1): 23 => 23
1754 13:53:52.948384 DramcWriteLeveling(PI) end<-----
1755 13:53:52.948467
1756 13:53:52.948565 ==
1757 13:53:52.951082 Dram Type= 6, Freq= 0, CH_1, rank 1
1758 13:53:52.954878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1759 13:53:52.954962 ==
1760 13:53:52.958018 [Gating] SW mode calibration
1761 13:53:52.964443 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1762 13:53:52.971255 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1763 13:53:52.974685 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1764 13:53:52.978305 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1765 13:53:52.984810 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1766 13:53:52.988723 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1767 13:53:52.991367 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1768 13:53:52.998192 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1769 13:53:53.001275 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1770 13:53:53.004305 0 6 28 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
1771 13:53:53.011186 0 7 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
1772 13:53:53.015131 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 13:53:53.018136 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1774 13:53:53.024596 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1775 13:53:53.027627 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1776 13:53:53.031323 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1777 13:53:53.034616 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1778 13:53:53.041613 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1779 13:53:53.044610 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1780 13:53:53.048154 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 13:53:53.055287 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 13:53:53.058431 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 13:53:53.062695 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 13:53:53.067928 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 13:53:53.071064 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 13:53:53.074391 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 13:53:53.081504 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 13:53:53.084640 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 13:53:53.087831 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 13:53:53.094260 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 13:53:53.098319 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 13:53:53.100971 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 13:53:53.107805 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 13:53:53.111483 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1795 13:53:53.114420 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1796 13:53:53.117889 Total UI for P1: 0, mck2ui 16
1797 13:53:53.121736 best dqsien dly found for B0: ( 0, 9, 28)
1798 13:53:53.124950 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1799 13:53:53.127701 Total UI for P1: 0, mck2ui 16
1800 13:53:53.130876 best dqsien dly found for B1: ( 0, 10, 0)
1801 13:53:53.134484 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1802 13:53:53.141630 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1803 13:53:53.141710
1804 13:53:53.145353 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1805 13:53:53.147848 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1806 13:53:53.151522 [Gating] SW calibration Done
1807 13:53:53.151602 ==
1808 13:53:53.154791 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 13:53:53.158083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1810 13:53:53.158164 ==
1811 13:53:53.158228 RX Vref Scan: 0
1812 13:53:53.161317
1813 13:53:53.161397 RX Vref 0 -> 0, step: 1
1814 13:53:53.161461
1815 13:53:53.165185 RX Delay -130 -> 252, step: 16
1816 13:53:53.168224 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1817 13:53:53.171017 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1818 13:53:53.178262 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1819 13:53:53.181311 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1820 13:53:53.184762 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1821 13:53:53.188166 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1822 13:53:53.191105 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1823 13:53:53.198343 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1824 13:53:53.201919 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1825 13:53:53.204473 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1826 13:53:53.207645 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1827 13:53:53.211563 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1828 13:53:53.217405 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1829 13:53:53.221568 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1830 13:53:53.224160 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1831 13:53:53.227851 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1832 13:53:53.227932 ==
1833 13:53:53.231128 Dram Type= 6, Freq= 0, CH_1, rank 1
1834 13:53:53.238203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1835 13:53:53.238284 ==
1836 13:53:53.238348 DQS Delay:
1837 13:53:53.241123 DQS0 = 0, DQS1 = 0
1838 13:53:53.241203 DQM Delay:
1839 13:53:53.241268 DQM0 = 82, DQM1 = 72
1840 13:53:53.245846 DQ Delay:
1841 13:53:53.247832 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1842 13:53:53.251185 DQ4 =77, DQ5 =101, DQ6 =93, DQ7 =77
1843 13:53:53.254398 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1844 13:53:53.257800 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1845 13:53:53.257880
1846 13:53:53.257944
1847 13:53:53.258003 ==
1848 13:53:53.261606 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 13:53:53.264023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1850 13:53:53.264105 ==
1851 13:53:53.264171
1852 13:53:53.264229
1853 13:53:53.267403 TX Vref Scan disable
1854 13:53:53.267484 == TX Byte 0 ==
1855 13:53:53.274676 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1856 13:53:53.277943 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1857 13:53:53.278023 == TX Byte 1 ==
1858 13:53:53.284224 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1859 13:53:53.287866 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1860 13:53:53.287946 ==
1861 13:53:53.291457 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 13:53:53.294486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1863 13:53:53.294567 ==
1864 13:53:53.308363 TX Vref=22, minBit 0, minWin=28, winSum=455
1865 13:53:53.312069 TX Vref=24, minBit 0, minWin=28, winSum=453
1866 13:53:53.315221 TX Vref=26, minBit 0, minWin=28, winSum=457
1867 13:53:53.318333 TX Vref=28, minBit 3, minWin=28, winSum=460
1868 13:53:53.321390 TX Vref=30, minBit 0, minWin=28, winSum=458
1869 13:53:53.328245 TX Vref=32, minBit 0, minWin=28, winSum=459
1870 13:53:53.331214 [TxChooseVref] Worse bit 3, Min win 28, Win sum 460, Final Vref 28
1871 13:53:53.331295
1872 13:53:53.335076 Final TX Range 1 Vref 28
1873 13:53:53.335157
1874 13:53:53.335220 ==
1875 13:53:53.338863 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 13:53:53.341536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1877 13:53:53.341616 ==
1878 13:53:53.344771
1879 13:53:53.344852
1880 13:53:53.344915 TX Vref Scan disable
1881 13:53:53.348053 == TX Byte 0 ==
1882 13:53:53.352089 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1883 13:53:53.354518 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1884 13:53:53.358754 == TX Byte 1 ==
1885 13:53:53.361060 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1886 13:53:53.368567 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1887 13:53:53.368647
1888 13:53:53.368719 [DATLAT]
1889 13:53:53.368781 Freq=800, CH1 RK1
1890 13:53:53.368839
1891 13:53:53.371543 DATLAT Default: 0x9
1892 13:53:53.371623 0, 0xFFFF, sum = 0
1893 13:53:53.375021 1, 0xFFFF, sum = 0
1894 13:53:53.375103 2, 0xFFFF, sum = 0
1895 13:53:53.378304 3, 0xFFFF, sum = 0
1896 13:53:53.378386 4, 0xFFFF, sum = 0
1897 13:53:53.381393 5, 0xFFFF, sum = 0
1898 13:53:53.384572 6, 0xFFFF, sum = 0
1899 13:53:53.384653 7, 0xFFFF, sum = 0
1900 13:53:53.384723 8, 0x0, sum = 1
1901 13:53:53.388322 9, 0x0, sum = 2
1902 13:53:53.388403 10, 0x0, sum = 3
1903 13:53:53.392453 11, 0x0, sum = 4
1904 13:53:53.392534 best_step = 9
1905 13:53:53.392597
1906 13:53:53.392656 ==
1907 13:53:53.394548 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 13:53:53.401450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1909 13:53:53.401531 ==
1910 13:53:53.401595 RX Vref Scan: 0
1911 13:53:53.401654
1912 13:53:53.405056 RX Vref 0 -> 0, step: 1
1913 13:53:53.405136
1914 13:53:53.408612 RX Delay -111 -> 252, step: 8
1915 13:53:53.411832 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1916 13:53:53.415065 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1917 13:53:53.421348 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1918 13:53:53.425177 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1919 13:53:53.428198 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1920 13:53:53.431187 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1921 13:53:53.434608 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1922 13:53:53.438989 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1923 13:53:53.444842 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1924 13:53:53.448311 iDelay=217, Bit 9, Center 56 (-63 ~ 176) 240
1925 13:53:53.451650 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1926 13:53:53.454856 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1927 13:53:53.458007 iDelay=217, Bit 12, Center 84 (-39 ~ 208) 248
1928 13:53:53.465331 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1929 13:53:53.468017 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1930 13:53:53.471742 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1931 13:53:53.471823 ==
1932 13:53:53.474538 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 13:53:53.478437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1934 13:53:53.481549 ==
1935 13:53:53.481630 DQS Delay:
1936 13:53:53.481693 DQS0 = 0, DQS1 = 0
1937 13:53:53.485323 DQM Delay:
1938 13:53:53.485403 DQM0 = 82, DQM1 = 71
1939 13:53:53.487886 DQ Delay:
1940 13:53:53.487966 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1941 13:53:53.491597 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1942 13:53:53.494640 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1943 13:53:53.498129 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1944 13:53:53.498210
1945 13:53:53.501733
1946 13:53:53.507968 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1947 13:53:53.512057 CH1 RK1: MR19=606, MR18=3E3E
1948 13:53:53.518270 CH1_RK1: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1949 13:53:53.518351 [RxdqsGatingPostProcess] freq 800
1950 13:53:53.525039 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1951 13:53:53.528691 Pre-setting of DQS Precalculation
1952 13:53:53.531522 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1953 13:53:53.541152 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1954 13:53:53.549213 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1955 13:53:53.549294
1956 13:53:53.549357
1957 13:53:53.551661 [Calibration Summary] 1600 Mbps
1958 13:53:53.551741 CH 0, Rank 0
1959 13:53:53.554753 SW Impedance : PASS
1960 13:53:53.554834 DUTY Scan : NO K
1961 13:53:53.557982 ZQ Calibration : PASS
1962 13:53:53.562487 Jitter Meter : NO K
1963 13:53:53.562567 CBT Training : PASS
1964 13:53:53.564804 Write leveling : PASS
1965 13:53:53.567922 RX DQS gating : PASS
1966 13:53:53.568002 RX DQ/DQS(RDDQC) : PASS
1967 13:53:53.571528 TX DQ/DQS : PASS
1968 13:53:53.571609 RX DATLAT : PASS
1969 13:53:53.575388 RX DQ/DQS(Engine): PASS
1970 13:53:53.578084 TX OE : NO K
1971 13:53:53.578165 All Pass.
1972 13:53:53.578227
1973 13:53:53.578286 CH 0, Rank 1
1974 13:53:53.581758 SW Impedance : PASS
1975 13:53:53.584727 DUTY Scan : NO K
1976 13:53:53.584808 ZQ Calibration : PASS
1977 13:53:53.588970 Jitter Meter : NO K
1978 13:53:53.591892 CBT Training : PASS
1979 13:53:53.591972 Write leveling : PASS
1980 13:53:53.596010 RX DQS gating : PASS
1981 13:53:53.598899 RX DQ/DQS(RDDQC) : PASS
1982 13:53:53.598979 TX DQ/DQS : PASS
1983 13:53:53.602342 RX DATLAT : PASS
1984 13:53:53.605288 RX DQ/DQS(Engine): PASS
1985 13:53:53.605412 TX OE : NO K
1986 13:53:53.605480 All Pass.
1987 13:53:53.608648
1988 13:53:53.608773 CH 1, Rank 0
1989 13:53:53.611847 SW Impedance : PASS
1990 13:53:53.612002 DUTY Scan : NO K
1991 13:53:53.615679 ZQ Calibration : PASS
1992 13:53:53.615779 Jitter Meter : NO K
1993 13:53:53.618822 CBT Training : PASS
1994 13:53:53.621665 Write leveling : PASS
1995 13:53:53.621774 RX DQS gating : PASS
1996 13:53:53.625622 RX DQ/DQS(RDDQC) : PASS
1997 13:53:53.630068 TX DQ/DQS : PASS
1998 13:53:53.630580 RX DATLAT : PASS
1999 13:53:53.631935 RX DQ/DQS(Engine): PASS
2000 13:53:53.635840 TX OE : NO K
2001 13:53:53.636365 All Pass.
2002 13:53:53.636777
2003 13:53:53.637144 CH 1, Rank 1
2004 13:53:53.639021 SW Impedance : PASS
2005 13:53:53.642066 DUTY Scan : NO K
2006 13:53:53.642527 ZQ Calibration : PASS
2007 13:53:53.645805 Jitter Meter : NO K
2008 13:53:53.649003 CBT Training : PASS
2009 13:53:53.649418 Write leveling : PASS
2010 13:53:53.652666 RX DQS gating : PASS
2011 13:53:53.653149 RX DQ/DQS(RDDQC) : PASS
2012 13:53:53.655605 TX DQ/DQS : PASS
2013 13:53:53.658791 RX DATLAT : PASS
2014 13:53:53.659353 RX DQ/DQS(Engine): PASS
2015 13:53:53.662319 TX OE : NO K
2016 13:53:53.662736 All Pass.
2017 13:53:53.663062
2018 13:53:53.666316 DramC Write-DBI off
2019 13:53:53.669976 PER_BANK_REFRESH: Hybrid Mode
2020 13:53:53.670458 TX_TRACKING: ON
2021 13:53:53.672691 [GetDramInforAfterCalByMRR] Vendor 6.
2022 13:53:53.676310 [GetDramInforAfterCalByMRR] Revision 606.
2023 13:53:53.679580 [GetDramInforAfterCalByMRR] Revision 2 0.
2024 13:53:53.682100 MR0 0x3939
2025 13:53:53.682515 MR8 0x1111
2026 13:53:53.685985 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2027 13:53:53.686494
2028 13:53:53.689964 MR0 0x3939
2029 13:53:53.690377 MR8 0x1111
2030 13:53:53.692369 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2031 13:53:53.692852
2032 13:53:53.703162 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2033 13:53:53.705785 [FAST_K] Save calibration result to emmc
2034 13:53:53.709047 [FAST_K] Save calibration result to emmc
2035 13:53:53.712212 dram_init: config_dvfs: 1
2036 13:53:53.716079 dramc_set_vcore_voltage set vcore to 662500
2037 13:53:53.716592 Read voltage for 1200, 2
2038 13:53:53.719309 Vio18 = 0
2039 13:53:53.719834 Vcore = 662500
2040 13:53:53.720163 Vdram = 0
2041 13:53:53.722275 Vddq = 0
2042 13:53:53.722791 Vmddr = 0
2043 13:53:53.726197 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2044 13:53:53.732809 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2045 13:53:53.735531 MEM_TYPE=3, freq_sel=15
2046 13:53:53.740308 sv_algorithm_assistance_LP4_1600
2047 13:53:53.743229 ============ PULL DRAM RESETB DOWN ============
2048 13:53:53.746317 ========== PULL DRAM RESETB DOWN end =========
2049 13:53:53.749398 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2050 13:53:53.752243 ===================================
2051 13:53:53.756045 LPDDR4 DRAM CONFIGURATION
2052 13:53:53.759654 ===================================
2053 13:53:53.762193 EX_ROW_EN[0] = 0x0
2054 13:53:53.762608 EX_ROW_EN[1] = 0x0
2055 13:53:53.766406 LP4Y_EN = 0x0
2056 13:53:53.766918 WORK_FSP = 0x0
2057 13:53:53.769037 WL = 0x4
2058 13:53:53.769450 RL = 0x4
2059 13:53:53.772638 BL = 0x2
2060 13:53:53.773169 RPST = 0x0
2061 13:53:53.776747 RD_PRE = 0x0
2062 13:53:53.777285 WR_PRE = 0x1
2063 13:53:53.779803 WR_PST = 0x0
2064 13:53:53.780217 DBI_WR = 0x0
2065 13:53:53.783198 DBI_RD = 0x0
2066 13:53:53.783753 OTF = 0x1
2067 13:53:53.786000 ===================================
2068 13:53:53.789094 ===================================
2069 13:53:53.792227 ANA top config
2070 13:53:53.796028 ===================================
2071 13:53:53.799229 DLL_ASYNC_EN = 0
2072 13:53:53.799739 ALL_SLAVE_EN = 0
2073 13:53:53.802452 NEW_RANK_MODE = 1
2074 13:53:53.806253 DLL_IDLE_MODE = 1
2075 13:53:53.810071 LP45_APHY_COMB_EN = 1
2076 13:53:53.812839 TX_ODT_DIS = 1
2077 13:53:53.813348 NEW_8X_MODE = 1
2078 13:53:53.815380 ===================================
2079 13:53:53.819396 ===================================
2080 13:53:53.822079 data_rate = 2400
2081 13:53:53.825601 CKR = 1
2082 13:53:53.828870 DQ_P2S_RATIO = 8
2083 13:53:53.832147 ===================================
2084 13:53:53.835838 CA_P2S_RATIO = 8
2085 13:53:53.836394 DQ_CA_OPEN = 0
2086 13:53:53.839348 DQ_SEMI_OPEN = 0
2087 13:53:53.843389 CA_SEMI_OPEN = 0
2088 13:53:53.845602 CA_FULL_RATE = 0
2089 13:53:53.849577 DQ_CKDIV4_EN = 0
2090 13:53:53.852225 CA_CKDIV4_EN = 0
2091 13:53:53.852638 CA_PREDIV_EN = 0
2092 13:53:53.855645 PH8_DLY = 17
2093 13:53:53.859261 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2094 13:53:53.861975 DQ_AAMCK_DIV = 4
2095 13:53:53.865549 CA_AAMCK_DIV = 4
2096 13:53:53.869428 CA_ADMCK_DIV = 4
2097 13:53:53.869941 DQ_TRACK_CA_EN = 0
2098 13:53:53.872324 CA_PICK = 1200
2099 13:53:53.875725 CA_MCKIO = 1200
2100 13:53:53.878874 MCKIO_SEMI = 0
2101 13:53:53.882095 PLL_FREQ = 2366
2102 13:53:53.885637 DQ_UI_PI_RATIO = 32
2103 13:53:53.889411 CA_UI_PI_RATIO = 0
2104 13:53:53.892172 ===================================
2105 13:53:53.895925 ===================================
2106 13:53:53.896446 memory_type:LPDDR4
2107 13:53:53.898775 GP_NUM : 10
2108 13:53:53.902505 SRAM_EN : 1
2109 13:53:53.903025 MD32_EN : 0
2110 13:53:53.906043 ===================================
2111 13:53:53.908831 [ANA_INIT] >>>>>>>>>>>>>>
2112 13:53:53.912340 <<<<<< [CONFIGURE PHASE]: ANA_TX
2113 13:53:53.915091 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2114 13:53:53.919548 ===================================
2115 13:53:53.921976 data_rate = 2400,PCW = 0X5b00
2116 13:53:53.925811 ===================================
2117 13:53:53.928558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2118 13:53:53.933000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2119 13:53:53.938532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2120 13:53:53.942078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2121 13:53:53.945697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2122 13:53:53.948860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2123 13:53:53.952177 [ANA_INIT] flow start
2124 13:53:53.955584 [ANA_INIT] PLL >>>>>>>>
2125 13:53:53.956045 [ANA_INIT] PLL <<<<<<<<
2126 13:53:53.958567 [ANA_INIT] MIDPI >>>>>>>>
2127 13:53:53.962227 [ANA_INIT] MIDPI <<<<<<<<
2128 13:53:53.962777 [ANA_INIT] DLL >>>>>>>>
2129 13:53:53.965685 [ANA_INIT] DLL <<<<<<<<
2130 13:53:53.969065 [ANA_INIT] flow end
2131 13:53:53.972543 ============ LP4 DIFF to SE enter ============
2132 13:53:53.976783 ============ LP4 DIFF to SE exit ============
2133 13:53:53.979301 [ANA_INIT] <<<<<<<<<<<<<
2134 13:53:53.982208 [Flow] Enable top DCM control >>>>>
2135 13:53:53.985328 [Flow] Enable top DCM control <<<<<
2136 13:53:53.989138 Enable DLL master slave shuffle
2137 13:53:53.993341 ==============================================================
2138 13:53:53.995801 Gating Mode config
2139 13:53:54.003415 ==============================================================
2140 13:53:54.003964 Config description:
2141 13:53:54.012027 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2142 13:53:54.018715 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2143 13:53:54.025083 SELPH_MODE 0: By rank 1: By Phase
2144 13:53:54.029097 ==============================================================
2145 13:53:54.032034 GAT_TRACK_EN = 1
2146 13:53:54.036004 RX_GATING_MODE = 2
2147 13:53:54.038422 RX_GATING_TRACK_MODE = 2
2148 13:53:54.042204 SELPH_MODE = 1
2149 13:53:54.045897 PICG_EARLY_EN = 1
2150 13:53:54.048479 VALID_LAT_VALUE = 1
2151 13:53:54.051806 ==============================================================
2152 13:53:54.054828 Enter into Gating configuration >>>>
2153 13:53:54.058915 Exit from Gating configuration <<<<
2154 13:53:54.062149 Enter into DVFS_PRE_config >>>>>
2155 13:53:54.075400 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2156 13:53:54.075953 Exit from DVFS_PRE_config <<<<<
2157 13:53:54.078148 Enter into PICG configuration >>>>
2158 13:53:54.081973 Exit from PICG configuration <<<<
2159 13:53:54.085634 [RX_INPUT] configuration >>>>>
2160 13:53:54.088575 [RX_INPUT] configuration <<<<<
2161 13:53:54.096196 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2162 13:53:54.098570 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2163 13:53:54.105673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2164 13:53:54.111831 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2165 13:53:54.119214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2166 13:53:54.124886 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2167 13:53:54.128998 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2168 13:53:54.131408 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2169 13:53:54.135547 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2170 13:53:54.141820 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2171 13:53:54.145079 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2172 13:53:54.148446 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2173 13:53:54.151685 ===================================
2174 13:53:54.155332 LPDDR4 DRAM CONFIGURATION
2175 13:53:54.158765 ===================================
2176 13:53:54.159248 EX_ROW_EN[0] = 0x0
2177 13:53:54.161972 EX_ROW_EN[1] = 0x0
2178 13:53:54.164651 LP4Y_EN = 0x0
2179 13:53:54.165143 WORK_FSP = 0x0
2180 13:53:54.168250 WL = 0x4
2181 13:53:54.168704 RL = 0x4
2182 13:53:54.171987 BL = 0x2
2183 13:53:54.172534 RPST = 0x0
2184 13:53:54.175087 RD_PRE = 0x0
2185 13:53:54.175623 WR_PRE = 0x1
2186 13:53:54.178340 WR_PST = 0x0
2187 13:53:54.178793 DBI_WR = 0x0
2188 13:53:54.181765 DBI_RD = 0x0
2189 13:53:54.182221 OTF = 0x1
2190 13:53:54.184956 ===================================
2191 13:53:54.188285 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2192 13:53:54.194879 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2193 13:53:54.198435 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2194 13:53:54.201571 ===================================
2195 13:53:54.205025 LPDDR4 DRAM CONFIGURATION
2196 13:53:54.208766 ===================================
2197 13:53:54.209316 EX_ROW_EN[0] = 0x10
2198 13:53:54.211838 EX_ROW_EN[1] = 0x0
2199 13:53:54.212354 LP4Y_EN = 0x0
2200 13:53:54.215073 WORK_FSP = 0x0
2201 13:53:54.215619 WL = 0x4
2202 13:53:54.218779 RL = 0x4
2203 13:53:54.219329 BL = 0x2
2204 13:53:54.221918 RPST = 0x0
2205 13:53:54.224609 RD_PRE = 0x0
2206 13:53:54.225303 WR_PRE = 0x1
2207 13:53:54.228569 WR_PST = 0x0
2208 13:53:54.229078 DBI_WR = 0x0
2209 13:53:54.231389 DBI_RD = 0x0
2210 13:53:54.231844 OTF = 0x1
2211 13:53:54.235457 ===================================
2212 13:53:54.241392 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2213 13:53:54.241930 ==
2214 13:53:54.245012 Dram Type= 6, Freq= 0, CH_0, rank 0
2215 13:53:54.248073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2216 13:53:54.248580 ==
2217 13:53:54.251583 [Duty_Offset_Calibration]
2218 13:53:54.252130 B0:0 B1:2 CA:1
2219 13:53:54.254826
2220 13:53:54.258034 [DutyScan_Calibration_Flow] k_type=0
2221 13:53:54.265859
2222 13:53:54.266404 ==CLK 0==
2223 13:53:54.269366 Final CLK duty delay cell = 0
2224 13:53:54.272568 [0] MAX Duty = 5093%(X100), DQS PI = 12
2225 13:53:54.276403 [0] MIN Duty = 4938%(X100), DQS PI = 52
2226 13:53:54.276997 [0] AVG Duty = 5015%(X100)
2227 13:53:54.279862
2228 13:53:54.280314 CH0 CLK Duty spec in!! Max-Min= 155%
2229 13:53:54.286322 [DutyScan_Calibration_Flow] ====Done====
2230 13:53:54.286931
2231 13:53:54.289633 [DutyScan_Calibration_Flow] k_type=1
2232 13:53:54.305506
2233 13:53:54.306052 ==DQS 0 ==
2234 13:53:54.308664 Final DQS duty delay cell = 0
2235 13:53:54.312297 [0] MAX Duty = 5125%(X100), DQS PI = 30
2236 13:53:54.315104 [0] MIN Duty = 5031%(X100), DQS PI = 6
2237 13:53:54.315560 [0] AVG Duty = 5078%(X100)
2238 13:53:54.318748
2239 13:53:54.319295 ==DQS 1 ==
2240 13:53:54.321982 Final DQS duty delay cell = 0
2241 13:53:54.325519 [0] MAX Duty = 5031%(X100), DQS PI = 50
2242 13:53:54.328393 [0] MIN Duty = 4906%(X100), DQS PI = 16
2243 13:53:54.328886 [0] AVG Duty = 4968%(X100)
2244 13:53:54.332063
2245 13:53:54.335638 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2246 13:53:54.336193
2247 13:53:54.338501 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2248 13:53:54.342084 [DutyScan_Calibration_Flow] ====Done====
2249 13:53:54.342541
2250 13:53:54.344921 [DutyScan_Calibration_Flow] k_type=3
2251 13:53:54.361786
2252 13:53:54.362330 ==DQM 0 ==
2253 13:53:54.365078 Final DQM duty delay cell = 0
2254 13:53:54.369025 [0] MAX Duty = 5187%(X100), DQS PI = 22
2255 13:53:54.372343 [0] MIN Duty = 4969%(X100), DQS PI = 42
2256 13:53:54.375343 [0] AVG Duty = 5078%(X100)
2257 13:53:54.375893
2258 13:53:54.376254 ==DQM 1 ==
2259 13:53:54.378697 Final DQM duty delay cell = 0
2260 13:53:54.381895 [0] MAX Duty = 4969%(X100), DQS PI = 54
2261 13:53:54.385462 [0] MIN Duty = 4844%(X100), DQS PI = 0
2262 13:53:54.386017 [0] AVG Duty = 4906%(X100)
2263 13:53:54.388842
2264 13:53:54.392870 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2265 13:53:54.393474
2266 13:53:54.394920 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2267 13:53:54.398231 [DutyScan_Calibration_Flow] ====Done====
2268 13:53:54.398779
2269 13:53:54.401364 [DutyScan_Calibration_Flow] k_type=2
2270 13:53:54.417311
2271 13:53:54.417854 ==DQ 0 ==
2272 13:53:54.420530 Final DQ duty delay cell = -4
2273 13:53:54.423353 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2274 13:53:54.426270 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2275 13:53:54.430097 [-4] AVG Duty = 4937%(X100)
2276 13:53:54.430646
2277 13:53:54.431010 ==DQ 1 ==
2278 13:53:54.433260 Final DQ duty delay cell = -4
2279 13:53:54.437150 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2280 13:53:54.440206 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2281 13:53:54.444031 [-4] AVG Duty = 4969%(X100)
2282 13:53:54.444592
2283 13:53:54.447169 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2284 13:53:54.447628
2285 13:53:54.451259 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2286 13:53:54.453571 [DutyScan_Calibration_Flow] ====Done====
2287 13:53:54.454091 ==
2288 13:53:54.456958 Dram Type= 6, Freq= 0, CH_1, rank 0
2289 13:53:54.459518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2290 13:53:54.459977 ==
2291 13:53:54.463377 [Duty_Offset_Calibration]
2292 13:53:54.463950 B0:0 B1:5 CA:-5
2293 13:53:54.464318
2294 13:53:54.466615 [DutyScan_Calibration_Flow] k_type=0
2295 13:53:54.477478
2296 13:53:54.478061 ==CLK 0==
2297 13:53:54.480418 Final CLK duty delay cell = 0
2298 13:53:54.484522 [0] MAX Duty = 5094%(X100), DQS PI = 24
2299 13:53:54.487643 [0] MIN Duty = 4876%(X100), DQS PI = 50
2300 13:53:54.488197 [0] AVG Duty = 4985%(X100)
2301 13:53:54.488557
2302 13:53:54.490862 CH1 CLK Duty spec in!! Max-Min= 218%
2303 13:53:54.497365 [DutyScan_Calibration_Flow] ====Done====
2304 13:53:54.497913
2305 13:53:54.501491 [DutyScan_Calibration_Flow] k_type=1
2306 13:53:54.516034
2307 13:53:54.516660 ==DQS 0 ==
2308 13:53:54.519181 Final DQS duty delay cell = 0
2309 13:53:54.522344 [0] MAX Duty = 5125%(X100), DQS PI = 16
2310 13:53:54.525298 [0] MIN Duty = 4875%(X100), DQS PI = 40
2311 13:53:54.529556 [0] AVG Duty = 5000%(X100)
2312 13:53:54.530106
2313 13:53:54.530464 ==DQS 1 ==
2314 13:53:54.533104 Final DQS duty delay cell = -4
2315 13:53:54.536075 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2316 13:53:54.538803 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2317 13:53:54.542314 [-4] AVG Duty = 4953%(X100)
2318 13:53:54.542924
2319 13:53:54.546078 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2320 13:53:54.546634
2321 13:53:54.548970 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2322 13:53:54.552586 [DutyScan_Calibration_Flow] ====Done====
2323 13:53:54.553182
2324 13:53:54.555386 [DutyScan_Calibration_Flow] k_type=3
2325 13:53:54.570656
2326 13:53:54.571210 ==DQM 0 ==
2327 13:53:54.574699 Final DQM duty delay cell = -4
2328 13:53:54.577391 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2329 13:53:54.581211 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2330 13:53:54.583992 [-4] AVG Duty = 4969%(X100)
2331 13:53:54.584594
2332 13:53:54.585029 ==DQM 1 ==
2333 13:53:54.587637 Final DQM duty delay cell = -4
2334 13:53:54.592174 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2335 13:53:54.593960 [-4] MIN Duty = 4906%(X100), DQS PI = 58
2336 13:53:54.597149 [-4] AVG Duty = 5000%(X100)
2337 13:53:54.597605
2338 13:53:54.601281 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2339 13:53:54.601825
2340 13:53:54.604296 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2341 13:53:54.608100 [DutyScan_Calibration_Flow] ====Done====
2342 13:53:54.608650
2343 13:53:54.610752 [DutyScan_Calibration_Flow] k_type=2
2344 13:53:54.628060
2345 13:53:54.628604 ==DQ 0 ==
2346 13:53:54.631421 Final DQ duty delay cell = 0
2347 13:53:54.634717 [0] MAX Duty = 5093%(X100), DQS PI = 0
2348 13:53:54.638212 [0] MIN Duty = 4969%(X100), DQS PI = 42
2349 13:53:54.638764 [0] AVG Duty = 5031%(X100)
2350 13:53:54.639129
2351 13:53:54.641542 ==DQ 1 ==
2352 13:53:54.644621 Final DQ duty delay cell = 0
2353 13:53:54.647991 [0] MAX Duty = 5000%(X100), DQS PI = 6
2354 13:53:54.651634 [0] MIN Duty = 4907%(X100), DQS PI = 0
2355 13:53:54.652190 [0] AVG Duty = 4953%(X100)
2356 13:53:54.652555
2357 13:53:54.654659 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2358 13:53:54.655118
2359 13:53:54.658375 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2360 13:53:54.661267 [DutyScan_Calibration_Flow] ====Done====
2361 13:53:54.666854 nWR fixed to 30
2362 13:53:54.669924 [ModeRegInit_LP4] CH0 RK0
2363 13:53:54.670376 [ModeRegInit_LP4] CH0 RK1
2364 13:53:54.674074 [ModeRegInit_LP4] CH1 RK0
2365 13:53:54.677014 [ModeRegInit_LP4] CH1 RK1
2366 13:53:54.677465 match AC timing 6
2367 13:53:54.683614 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2368 13:53:54.686723 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2369 13:53:54.690019 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2370 13:53:54.696803 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2371 13:53:54.700013 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2372 13:53:54.700464 ==
2373 13:53:54.704251 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 13:53:54.706449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2375 13:53:54.706904 ==
2376 13:53:54.713431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2377 13:53:54.720680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2378 13:53:54.727612 [CA 0] Center 39 (9~70) winsize 62
2379 13:53:54.730995 [CA 1] Center 39 (8~70) winsize 63
2380 13:53:54.734072 [CA 2] Center 36 (5~67) winsize 63
2381 13:53:54.737439 [CA 3] Center 35 (4~66) winsize 63
2382 13:53:54.741264 [CA 4] Center 34 (3~65) winsize 63
2383 13:53:54.744331 [CA 5] Center 33 (3~64) winsize 62
2384 13:53:54.744830
2385 13:53:54.747446 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2386 13:53:54.747895
2387 13:53:54.750969 [CATrainingPosCal] consider 1 rank data
2388 13:53:54.754171 u2DelayCellTimex100 = 270/100 ps
2389 13:53:54.757863 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2390 13:53:54.760875 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2391 13:53:54.768921 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2392 13:53:54.771267 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2393 13:53:54.774310 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2394 13:53:54.777890 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2395 13:53:54.778436
2396 13:53:54.781197 CA PerBit enable=1, Macro0, CA PI delay=33
2397 13:53:54.781745
2398 13:53:54.785632 [CBTSetCACLKResult] CA Dly = 33
2399 13:53:54.786191 CS Dly: 7 (0~38)
2400 13:53:54.786550 ==
2401 13:53:54.787501 Dram Type= 6, Freq= 0, CH_0, rank 1
2402 13:53:54.794326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2403 13:53:54.794885 ==
2404 13:53:54.798231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2405 13:53:54.804925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2406 13:53:54.813549 [CA 0] Center 39 (8~70) winsize 63
2407 13:53:54.816517 [CA 1] Center 39 (8~70) winsize 63
2408 13:53:54.819649 [CA 2] Center 36 (5~67) winsize 63
2409 13:53:54.825081 [CA 3] Center 35 (4~66) winsize 63
2410 13:53:54.826056 [CA 4] Center 33 (3~64) winsize 62
2411 13:53:54.829660 [CA 5] Center 33 (3~64) winsize 62
2412 13:53:54.830115
2413 13:53:54.833438 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2414 13:53:54.833895
2415 13:53:54.836927 [CATrainingPosCal] consider 2 rank data
2416 13:53:54.839754 u2DelayCellTimex100 = 270/100 ps
2417 13:53:54.844327 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2418 13:53:54.847029 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2419 13:53:54.853219 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2420 13:53:54.856930 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2421 13:53:54.859532 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2422 13:53:54.863144 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2423 13:53:54.863599
2424 13:53:54.866171 CA PerBit enable=1, Macro0, CA PI delay=33
2425 13:53:54.866625
2426 13:53:54.869872 [CBTSetCACLKResult] CA Dly = 33
2427 13:53:54.870375 CS Dly: 7 (0~39)
2428 13:53:54.870923
2429 13:53:54.874265 ----->DramcWriteLeveling(PI) begin...
2430 13:53:54.877065 ==
2431 13:53:54.877615 Dram Type= 6, Freq= 0, CH_0, rank 0
2432 13:53:54.883381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2433 13:53:54.883937 ==
2434 13:53:54.886414 Write leveling (Byte 0): 27 => 27
2435 13:53:54.890205 Write leveling (Byte 1): 26 => 26
2436 13:53:54.895051 DramcWriteLeveling(PI) end<-----
2437 13:53:54.895601
2438 13:53:54.895964 ==
2439 13:53:54.896665 Dram Type= 6, Freq= 0, CH_0, rank 0
2440 13:53:54.899481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2441 13:53:54.899869 ==
2442 13:53:54.903533 [Gating] SW mode calibration
2443 13:53:54.909758 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2444 13:53:54.913650 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2445 13:53:54.920130 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2446 13:53:54.923302 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2447 13:53:54.926378 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2448 13:53:54.933665 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2449 13:53:54.936638 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2450 13:53:54.939964 0 11 20 | B1->B0 | 2f2f 2828 | 0 0 | (0 1) (0 1)
2451 13:53:54.947465 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 13:53:54.950188 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2453 13:53:54.953478 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 13:53:54.959857 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2455 13:53:54.963807 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2456 13:53:54.966992 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2457 13:53:54.973987 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2458 13:53:54.977105 0 12 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2459 13:53:54.979876 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2460 13:53:54.983604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2461 13:53:54.990916 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 13:53:54.993944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2463 13:53:54.997440 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2464 13:53:55.003397 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2465 13:53:55.007236 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2466 13:53:55.010813 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2467 13:53:55.016508 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 13:53:55.020192 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 13:53:55.023111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 13:53:55.030676 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 13:53:55.033926 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 13:53:55.036653 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 13:53:55.043904 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 13:53:55.048376 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 13:53:55.050067 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 13:53:55.056408 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 13:53:55.061332 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 13:53:55.063138 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 13:53:55.070037 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 13:53:55.073984 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 13:53:55.077218 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 13:53:55.080240 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2483 13:53:55.086575 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2484 13:53:55.089931 Total UI for P1: 0, mck2ui 16
2485 13:53:55.093887 best dqsien dly found for B0: ( 0, 15, 20)
2486 13:53:55.097001 Total UI for P1: 0, mck2ui 16
2487 13:53:55.100159 best dqsien dly found for B1: ( 0, 15, 20)
2488 13:53:55.104331 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2489 13:53:55.106837 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2490 13:53:55.107388
2491 13:53:55.110435 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2492 13:53:55.113236 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2493 13:53:55.116429 [Gating] SW calibration Done
2494 13:53:55.116918 ==
2495 13:53:55.120048 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 13:53:55.123527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2497 13:53:55.123988 ==
2498 13:53:55.126647 RX Vref Scan: 0
2499 13:53:55.127193
2500 13:53:55.127552 RX Vref 0 -> 0, step: 1
2501 13:53:55.130365
2502 13:53:55.130924 RX Delay -40 -> 252, step: 8
2503 13:53:55.137552 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2504 13:53:55.140105 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2505 13:53:55.143538 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2506 13:53:55.146906 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2507 13:53:55.149981 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2508 13:53:55.158252 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2509 13:53:55.159843 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2510 13:53:55.163340 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2511 13:53:55.167086 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2512 13:53:55.170315 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2513 13:53:55.173657 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2514 13:53:55.180508 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2515 13:53:55.183100 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2516 13:53:55.187399 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2517 13:53:55.189997 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2518 13:53:55.196179 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2519 13:53:55.196760 ==
2520 13:53:55.199595 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 13:53:55.203221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2522 13:53:55.203777 ==
2523 13:53:55.204140 DQS Delay:
2524 13:53:55.206645 DQS0 = 0, DQS1 = 0
2525 13:53:55.207253 DQM Delay:
2526 13:53:55.209982 DQM0 = 115, DQM1 = 106
2527 13:53:55.210529 DQ Delay:
2528 13:53:55.213264 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2529 13:53:55.216665 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2530 13:53:55.220115 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2531 13:53:55.222780 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2532 13:53:55.223239
2533 13:53:55.223595
2534 13:53:55.223928 ==
2535 13:53:55.226862 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 13:53:55.233026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2537 13:53:55.233483 ==
2538 13:53:55.233845
2539 13:53:55.234180
2540 13:53:55.234521 TX Vref Scan disable
2541 13:53:55.236326 == TX Byte 0 ==
2542 13:53:55.239790 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2543 13:53:55.247440 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2544 13:53:55.247993 == TX Byte 1 ==
2545 13:53:55.250229 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2546 13:53:55.256938 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2547 13:53:55.257396 ==
2548 13:53:55.259959 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 13:53:55.263650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2550 13:53:55.264111 ==
2551 13:53:55.275136 TX Vref=22, minBit 9, minWin=25, winSum=416
2552 13:53:55.277748 TX Vref=24, minBit 9, minWin=25, winSum=422
2553 13:53:55.281664 TX Vref=26, minBit 10, minWin=25, winSum=429
2554 13:53:55.285158 TX Vref=28, minBit 8, minWin=26, winSum=432
2555 13:53:55.287997 TX Vref=30, minBit 8, minWin=26, winSum=435
2556 13:53:55.294961 TX Vref=32, minBit 10, minWin=26, winSum=429
2557 13:53:55.297958 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2558 13:53:55.298511
2559 13:53:55.301671 Final TX Range 1 Vref 30
2560 13:53:55.302220
2561 13:53:55.302577 ==
2562 13:53:55.304225 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 13:53:55.308234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2564 13:53:55.308842 ==
2565 13:53:55.311170
2566 13:53:55.311622
2567 13:53:55.311980 TX Vref Scan disable
2568 13:53:55.314957 == TX Byte 0 ==
2569 13:53:55.317988 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2570 13:53:55.324029 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2571 13:53:55.324563 == TX Byte 1 ==
2572 13:53:55.328156 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2573 13:53:55.331888 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2574 13:53:55.335796
2575 13:53:55.336343 [DATLAT]
2576 13:53:55.336702 Freq=1200, CH0 RK0
2577 13:53:55.337107
2578 13:53:55.338276 DATLAT Default: 0xd
2579 13:53:55.338730 0, 0xFFFF, sum = 0
2580 13:53:55.341047 1, 0xFFFF, sum = 0
2581 13:53:55.341511 2, 0xFFFF, sum = 0
2582 13:53:55.343975 3, 0xFFFF, sum = 0
2583 13:53:55.348029 4, 0xFFFF, sum = 0
2584 13:53:55.348590 5, 0xFFFF, sum = 0
2585 13:53:55.350562 6, 0xFFFF, sum = 0
2586 13:53:55.351024 7, 0xFFFF, sum = 0
2587 13:53:55.355369 8, 0xFFFF, sum = 0
2588 13:53:55.355916 9, 0xFFFF, sum = 0
2589 13:53:55.357544 10, 0xFFFF, sum = 0
2590 13:53:55.358115 11, 0x0, sum = 1
2591 13:53:55.360887 12, 0x0, sum = 2
2592 13:53:55.361351 13, 0x0, sum = 3
2593 13:53:55.363980 14, 0x0, sum = 4
2594 13:53:55.364442 best_step = 12
2595 13:53:55.364854
2596 13:53:55.365195 ==
2597 13:53:55.368258 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 13:53:55.370928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2599 13:53:55.371391 ==
2600 13:53:55.374952 RX Vref Scan: 1
2601 13:53:55.375500
2602 13:53:55.378173 Set Vref Range= 32 -> 127
2603 13:53:55.378722
2604 13:53:55.379083 RX Vref 32 -> 127, step: 1
2605 13:53:55.379423
2606 13:53:55.380782 RX Delay -21 -> 252, step: 4
2607 13:53:55.381239
2608 13:53:55.384404 Set Vref, RX VrefLevel [Byte0]: 32
2609 13:53:55.387967 [Byte1]: 32
2610 13:53:55.391340
2611 13:53:55.391793 Set Vref, RX VrefLevel [Byte0]: 33
2612 13:53:55.394627 [Byte1]: 33
2613 13:53:55.399160
2614 13:53:55.399705 Set Vref, RX VrefLevel [Byte0]: 34
2615 13:53:55.402594 [Byte1]: 34
2616 13:53:55.407047
2617 13:53:55.407594 Set Vref, RX VrefLevel [Byte0]: 35
2618 13:53:55.410308 [Byte1]: 35
2619 13:53:55.415264
2620 13:53:55.415811 Set Vref, RX VrefLevel [Byte0]: 36
2621 13:53:55.418160 [Byte1]: 36
2622 13:53:55.422920
2623 13:53:55.423467 Set Vref, RX VrefLevel [Byte0]: 37
2624 13:53:55.426498 [Byte1]: 37
2625 13:53:55.430712
2626 13:53:55.431401 Set Vref, RX VrefLevel [Byte0]: 38
2627 13:53:55.434251 [Byte1]: 38
2628 13:53:55.439262
2629 13:53:55.439715 Set Vref, RX VrefLevel [Byte0]: 39
2630 13:53:55.441729 [Byte1]: 39
2631 13:53:55.446721
2632 13:53:55.447275 Set Vref, RX VrefLevel [Byte0]: 40
2633 13:53:55.450165 [Byte1]: 40
2634 13:53:55.454920
2635 13:53:55.455467 Set Vref, RX VrefLevel [Byte0]: 41
2636 13:53:55.457783 [Byte1]: 41
2637 13:53:55.462974
2638 13:53:55.463429 Set Vref, RX VrefLevel [Byte0]: 42
2639 13:53:55.466543 [Byte1]: 42
2640 13:53:55.470516
2641 13:53:55.470986 Set Vref, RX VrefLevel [Byte0]: 43
2642 13:53:55.473508 [Byte1]: 43
2643 13:53:55.478197
2644 13:53:55.478743 Set Vref, RX VrefLevel [Byte0]: 44
2645 13:53:55.482331 [Byte1]: 44
2646 13:53:55.486523
2647 13:53:55.487071 Set Vref, RX VrefLevel [Byte0]: 45
2648 13:53:55.489558 [Byte1]: 45
2649 13:53:55.494531
2650 13:53:55.495080 Set Vref, RX VrefLevel [Byte0]: 46
2651 13:53:55.497546 [Byte1]: 46
2652 13:53:55.502756
2653 13:53:55.503303 Set Vref, RX VrefLevel [Byte0]: 47
2654 13:53:55.505428 [Byte1]: 47
2655 13:53:55.510552
2656 13:53:55.511100 Set Vref, RX VrefLevel [Byte0]: 48
2657 13:53:55.513657 [Byte1]: 48
2658 13:53:55.518030
2659 13:53:55.518583 Set Vref, RX VrefLevel [Byte0]: 49
2660 13:53:55.521493 [Byte1]: 49
2661 13:53:55.525765
2662 13:53:55.526440 Set Vref, RX VrefLevel [Byte0]: 50
2663 13:53:55.529705 [Byte1]: 50
2664 13:53:55.533808
2665 13:53:55.536895 Set Vref, RX VrefLevel [Byte0]: 51
2666 13:53:55.540468 [Byte1]: 51
2667 13:53:55.540978
2668 13:53:55.543546 Set Vref, RX VrefLevel [Byte0]: 52
2669 13:53:55.547441 [Byte1]: 52
2670 13:53:55.547990
2671 13:53:55.549841 Set Vref, RX VrefLevel [Byte0]: 53
2672 13:53:55.553273 [Byte1]: 53
2673 13:53:55.557481
2674 13:53:55.557935 Set Vref, RX VrefLevel [Byte0]: 54
2675 13:53:55.560846 [Byte1]: 54
2676 13:53:55.565715
2677 13:53:55.566165 Set Vref, RX VrefLevel [Byte0]: 55
2678 13:53:55.568775 [Byte1]: 55
2679 13:53:55.573168
2680 13:53:55.573706 Set Vref, RX VrefLevel [Byte0]: 56
2681 13:53:55.576831 [Byte1]: 56
2682 13:53:55.581584
2683 13:53:55.582164 Set Vref, RX VrefLevel [Byte0]: 57
2684 13:53:55.585276 [Byte1]: 57
2685 13:53:55.589320
2686 13:53:55.589777 Set Vref, RX VrefLevel [Byte0]: 58
2687 13:53:55.592343 [Byte1]: 58
2688 13:53:55.597372
2689 13:53:55.597897 Set Vref, RX VrefLevel [Byte0]: 59
2690 13:53:55.600749 [Byte1]: 59
2691 13:53:55.605204
2692 13:53:55.605721 Set Vref, RX VrefLevel [Byte0]: 60
2693 13:53:55.607973 [Byte1]: 60
2694 13:53:55.613695
2695 13:53:55.614238 Set Vref, RX VrefLevel [Byte0]: 61
2696 13:53:55.616372 [Byte1]: 61
2697 13:53:55.620886
2698 13:53:55.621413 Set Vref, RX VrefLevel [Byte0]: 62
2699 13:53:55.624298 [Byte1]: 62
2700 13:53:55.628666
2701 13:53:55.629151 Set Vref, RX VrefLevel [Byte0]: 63
2702 13:53:55.632038 [Byte1]: 63
2703 13:53:55.636997
2704 13:53:55.637470 Set Vref, RX VrefLevel [Byte0]: 64
2705 13:53:55.640555 [Byte1]: 64
2706 13:53:55.644600
2707 13:53:55.645205 Set Vref, RX VrefLevel [Byte0]: 65
2708 13:53:55.647709 [Byte1]: 65
2709 13:53:55.653579
2710 13:53:55.654030 Set Vref, RX VrefLevel [Byte0]: 66
2711 13:53:55.655834 [Byte1]: 66
2712 13:53:55.660855
2713 13:53:55.661394 Final RX Vref Byte 0 = 53 to rank0
2714 13:53:55.664927 Final RX Vref Byte 1 = 49 to rank0
2715 13:53:55.667173 Final RX Vref Byte 0 = 53 to rank1
2716 13:53:55.670354 Final RX Vref Byte 1 = 49 to rank1==
2717 13:53:55.673503 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 13:53:55.680683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2719 13:53:55.681273 ==
2720 13:53:55.681631 DQS Delay:
2721 13:53:55.681997 DQS0 = 0, DQS1 = 0
2722 13:53:55.684046 DQM Delay:
2723 13:53:55.684593 DQM0 = 114, DQM1 = 105
2724 13:53:55.687123 DQ Delay:
2725 13:53:55.690542 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2726 13:53:55.693489 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2727 13:53:55.696938 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2728 13:53:55.700589 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2729 13:53:55.701105
2730 13:53:55.701457
2731 13:53:55.707187 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2732 13:53:55.711144 CH0 RK0: MR19=404, MR18=B0B
2733 13:53:55.717386 CH0_RK0: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2734 13:53:55.717849
2735 13:53:55.720788 ----->DramcWriteLeveling(PI) begin...
2736 13:53:55.721339 ==
2737 13:53:55.724252 Dram Type= 6, Freq= 0, CH_0, rank 1
2738 13:53:55.726681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2739 13:53:55.727132 ==
2740 13:53:55.729932 Write leveling (Byte 0): 28 => 28
2741 13:53:55.733335 Write leveling (Byte 1): 26 => 26
2742 13:53:55.737272 DramcWriteLeveling(PI) end<-----
2743 13:53:55.737792
2744 13:53:55.738154 ==
2745 13:53:55.739978 Dram Type= 6, Freq= 0, CH_0, rank 1
2746 13:53:55.746882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2747 13:53:55.747335 ==
2748 13:53:55.747687 [Gating] SW mode calibration
2749 13:53:55.756581 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2750 13:53:55.760082 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2751 13:53:55.763338 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2752 13:53:55.770236 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 13:53:55.773478 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2754 13:53:55.776863 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2755 13:53:55.783565 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2756 13:53:55.786514 0 11 20 | B1->B0 | 2d2d 2424 | 0 0 | (1 0) (0 0)
2757 13:53:55.790267 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 13:53:55.797672 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 13:53:55.800054 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 13:53:55.803814 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 13:53:55.810657 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2762 13:53:55.813490 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2763 13:53:55.817272 0 12 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2764 13:53:55.823964 0 12 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2765 13:53:55.827036 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 13:53:55.830293 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 13:53:55.834957 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 13:53:55.839903 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 13:53:55.843998 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2770 13:53:55.847503 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2771 13:53:55.853626 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2772 13:53:55.857211 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2773 13:53:55.860464 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 13:53:55.866803 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 13:53:55.871089 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 13:53:55.873874 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 13:53:55.881132 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 13:53:55.884622 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 13:53:55.887937 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 13:53:55.894157 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 13:53:55.897399 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 13:53:55.900364 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 13:53:55.907460 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 13:53:55.911096 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 13:53:55.914177 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 13:53:55.920583 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 13:53:55.926366 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 13:53:55.927174 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2789 13:53:55.930404 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2790 13:53:55.933627 Total UI for P1: 0, mck2ui 16
2791 13:53:55.938845 best dqsien dly found for B0: ( 0, 15, 20)
2792 13:53:55.940835 Total UI for P1: 0, mck2ui 16
2793 13:53:55.944220 best dqsien dly found for B1: ( 0, 15, 20)
2794 13:53:55.947651 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2795 13:53:55.953590 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2796 13:53:55.954109
2797 13:53:55.957017 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2798 13:53:55.960010 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2799 13:53:55.963265 [Gating] SW calibration Done
2800 13:53:55.963725 ==
2801 13:53:55.967403 Dram Type= 6, Freq= 0, CH_0, rank 1
2802 13:53:55.970704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2803 13:53:55.971163 ==
2804 13:53:55.971526 RX Vref Scan: 0
2805 13:53:55.974109
2806 13:53:55.974562 RX Vref 0 -> 0, step: 1
2807 13:53:55.974924
2808 13:53:55.977089 RX Delay -40 -> 252, step: 8
2809 13:53:55.980785 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2810 13:53:55.983439 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2811 13:53:55.991439 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2812 13:53:55.993623 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2813 13:53:55.997118 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2814 13:53:56.000378 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2815 13:53:56.003509 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2816 13:53:56.010484 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2817 13:53:56.013770 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2818 13:53:56.017215 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2819 13:53:56.020251 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2820 13:53:56.023599 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2821 13:53:56.026989 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2822 13:53:56.033685 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2823 13:53:56.036847 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2824 13:53:56.040198 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2825 13:53:56.040619 ==
2826 13:53:56.043748 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 13:53:56.047170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2828 13:53:56.050335 ==
2829 13:53:56.050864 DQS Delay:
2830 13:53:56.051304 DQS0 = 0, DQS1 = 0
2831 13:53:56.053477 DQM Delay:
2832 13:53:56.053896 DQM0 = 115, DQM1 = 108
2833 13:53:56.056941 DQ Delay:
2834 13:53:56.059961 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2835 13:53:56.063369 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2836 13:53:56.066855 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
2837 13:53:56.070520 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2838 13:53:56.071241
2839 13:53:56.071714
2840 13:53:56.072074 ==
2841 13:53:56.073584 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 13:53:56.076599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2843 13:53:56.077202 ==
2844 13:53:56.077682
2845 13:53:56.078126
2846 13:53:56.080099 TX Vref Scan disable
2847 13:53:56.084452 == TX Byte 0 ==
2848 13:53:56.087469 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2849 13:53:56.090362 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2850 13:53:56.093458 == TX Byte 1 ==
2851 13:53:56.096848 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2852 13:53:56.100277 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2853 13:53:56.100775 ==
2854 13:53:56.103822 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 13:53:56.106646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2856 13:53:56.110569 ==
2857 13:53:56.120576 TX Vref=22, minBit 12, minWin=24, winSum=414
2858 13:53:56.123758 TX Vref=24, minBit 8, minWin=26, winSum=427
2859 13:53:56.127079 TX Vref=26, minBit 8, minWin=26, winSum=429
2860 13:53:56.130335 TX Vref=28, minBit 8, minWin=25, winSum=432
2861 13:53:56.133821 TX Vref=30, minBit 10, minWin=25, winSum=435
2862 13:53:56.140380 TX Vref=32, minBit 8, minWin=25, winSum=434
2863 13:53:56.144049 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 26
2864 13:53:56.144511
2865 13:53:56.147951 Final TX Range 1 Vref 26
2866 13:53:56.148410
2867 13:53:56.148825 ==
2868 13:53:56.150159 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 13:53:56.153336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2870 13:53:56.153797 ==
2871 13:53:56.156684
2872 13:53:56.157177
2873 13:53:56.157670 TX Vref Scan disable
2874 13:53:56.160098 == TX Byte 0 ==
2875 13:53:56.163577 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2876 13:53:56.166936 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2877 13:53:56.170642 == TX Byte 1 ==
2878 13:53:56.173818 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2879 13:53:56.176667 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2880 13:53:56.180527
2881 13:53:56.181057 [DATLAT]
2882 13:53:56.181391 Freq=1200, CH0 RK1
2883 13:53:56.181701
2884 13:53:56.183855 DATLAT Default: 0xc
2885 13:53:56.184266 0, 0xFFFF, sum = 0
2886 13:53:56.187253 1, 0xFFFF, sum = 0
2887 13:53:56.187783 2, 0xFFFF, sum = 0
2888 13:53:56.190636 3, 0xFFFF, sum = 0
2889 13:53:56.193265 4, 0xFFFF, sum = 0
2890 13:53:56.193688 5, 0xFFFF, sum = 0
2891 13:53:56.196799 6, 0xFFFF, sum = 0
2892 13:53:56.197314 7, 0xFFFF, sum = 0
2893 13:53:56.200315 8, 0xFFFF, sum = 0
2894 13:53:56.200779 9, 0xFFFF, sum = 0
2895 13:53:56.203525 10, 0xFFFF, sum = 0
2896 13:53:56.204029 11, 0x0, sum = 1
2897 13:53:56.207140 12, 0x0, sum = 2
2898 13:53:56.207631 13, 0x0, sum = 3
2899 13:53:56.209858 14, 0x0, sum = 4
2900 13:53:56.210278 best_step = 12
2901 13:53:56.210601
2902 13:53:56.210904 ==
2903 13:53:56.213778 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 13:53:56.216703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2905 13:53:56.217183 ==
2906 13:53:56.220572 RX Vref Scan: 0
2907 13:53:56.221118
2908 13:53:56.223185 RX Vref 0 -> 0, step: 1
2909 13:53:56.223597
2910 13:53:56.223925 RX Delay -21 -> 252, step: 4
2911 13:53:56.230674 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2912 13:53:56.233537 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2913 13:53:56.237242 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2914 13:53:56.241210 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2915 13:53:56.243679 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2916 13:53:56.251456 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2917 13:53:56.253971 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2918 13:53:56.257335 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2919 13:53:56.260397 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2920 13:53:56.264009 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2921 13:53:56.270879 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2922 13:53:56.273674 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2923 13:53:56.277370 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2924 13:53:56.280570 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2925 13:53:56.283848 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
2926 13:53:56.291181 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2927 13:53:56.291710 ==
2928 13:53:56.293686 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 13:53:56.296673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2930 13:53:56.297170 ==
2931 13:53:56.297640 DQS Delay:
2932 13:53:56.300271 DQS0 = 0, DQS1 = 0
2933 13:53:56.300772 DQM Delay:
2934 13:53:56.303884 DQM0 = 114, DQM1 = 105
2935 13:53:56.304440 DQ Delay:
2936 13:53:56.306670 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2937 13:53:56.310655 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2938 13:53:56.313847 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2939 13:53:56.317455 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2940 13:53:56.317919
2941 13:53:56.318387
2942 13:53:56.327666 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2943 13:53:56.330181 CH0 RK1: MR19=404, MR18=D0D
2944 13:53:56.334581 CH0_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
2945 13:53:56.336522 [RxdqsGatingPostProcess] freq 1200
2946 13:53:56.343927 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2947 13:53:56.346746 Pre-setting of DQS Precalculation
2948 13:53:56.349872 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2949 13:53:56.353812 ==
2950 13:53:56.354277 Dram Type= 6, Freq= 0, CH_1, rank 0
2951 13:53:56.360207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2952 13:53:56.360678 ==
2953 13:53:56.364046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2954 13:53:56.370297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2955 13:53:56.379505 [CA 0] Center 37 (7~68) winsize 62
2956 13:53:56.382592 [CA 1] Center 37 (7~68) winsize 62
2957 13:53:56.386160 [CA 2] Center 34 (4~65) winsize 62
2958 13:53:56.389005 [CA 3] Center 33 (3~64) winsize 62
2959 13:53:56.392813 [CA 4] Center 32 (2~63) winsize 62
2960 13:53:56.395648 [CA 5] Center 32 (1~63) winsize 63
2961 13:53:56.396199
2962 13:53:56.399109 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2963 13:53:56.399560
2964 13:53:56.403159 [CATrainingPosCal] consider 1 rank data
2965 13:53:56.405351 u2DelayCellTimex100 = 270/100 ps
2966 13:53:56.409212 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2967 13:53:56.416025 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2968 13:53:56.419305 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2969 13:53:56.421877 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2970 13:53:56.426126 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2971 13:53:56.428939 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2972 13:53:56.429394
2973 13:53:56.432582 CA PerBit enable=1, Macro0, CA PI delay=32
2974 13:53:56.433094
2975 13:53:56.436224 [CBTSetCACLKResult] CA Dly = 32
2976 13:53:56.436928 CS Dly: 6 (0~37)
2977 13:53:56.438584 ==
2978 13:53:56.442164 Dram Type= 6, Freq= 0, CH_1, rank 1
2979 13:53:56.445382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2980 13:53:56.445835 ==
2981 13:53:56.448909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2982 13:53:56.455704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2983 13:53:56.464260 [CA 0] Center 37 (6~68) winsize 63
2984 13:53:56.467883 [CA 1] Center 37 (7~68) winsize 62
2985 13:53:56.471105 [CA 2] Center 33 (3~64) winsize 62
2986 13:53:56.474106 [CA 3] Center 33 (3~64) winsize 62
2987 13:53:56.477652 [CA 4] Center 32 (2~63) winsize 62
2988 13:53:56.481342 [CA 5] Center 32 (1~63) winsize 63
2989 13:53:56.481901
2990 13:53:56.484462 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2991 13:53:56.485055
2992 13:53:56.488679 [CATrainingPosCal] consider 2 rank data
2993 13:53:56.490910 u2DelayCellTimex100 = 270/100 ps
2994 13:53:56.494098 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2995 13:53:56.497685 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2996 13:53:56.504156 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2997 13:53:56.508028 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2998 13:53:56.511714 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2999 13:53:56.514149 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
3000 13:53:56.514609
3001 13:53:56.518508 CA PerBit enable=1, Macro0, CA PI delay=32
3002 13:53:56.519100
3003 13:53:56.520859 [CBTSetCACLKResult] CA Dly = 32
3004 13:53:56.521317 CS Dly: 6 (0~38)
3005 13:53:56.521677
3006 13:53:56.525266 ----->DramcWriteLeveling(PI) begin...
3007 13:53:56.529269 ==
3008 13:53:56.529820 Dram Type= 6, Freq= 0, CH_1, rank 0
3009 13:53:56.534859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3010 13:53:56.535322 ==
3011 13:53:56.538859 Write leveling (Byte 0): 23 => 23
3012 13:53:56.541281 Write leveling (Byte 1): 23 => 23
3013 13:53:56.541741 DramcWriteLeveling(PI) end<-----
3014 13:53:56.544422
3015 13:53:56.544913 ==
3016 13:53:56.547470 Dram Type= 6, Freq= 0, CH_1, rank 0
3017 13:53:56.551493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3018 13:53:56.551952 ==
3019 13:53:56.554422 [Gating] SW mode calibration
3020 13:53:56.561464 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3021 13:53:56.564625 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3022 13:53:56.571557 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3023 13:53:56.574216 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3024 13:53:56.577886 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3025 13:53:56.584436 0 11 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3026 13:53:56.588320 0 11 16 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
3027 13:53:56.590883 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 13:53:56.598579 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 13:53:56.601294 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 13:53:56.604919 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 13:53:56.612201 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3032 13:53:56.614566 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3033 13:53:56.618108 0 12 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3034 13:53:56.624529 0 12 16 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
3035 13:53:56.628013 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 13:53:56.632575 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 13:53:56.637651 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 13:53:56.641791 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 13:53:56.645092 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 13:53:56.652556 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3041 13:53:56.654411 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3042 13:53:56.657547 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3043 13:53:56.660921 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 13:53:56.667702 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 13:53:56.670773 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 13:53:56.674885 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 13:53:56.680546 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 13:53:56.684698 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 13:53:56.687779 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 13:53:56.694016 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 13:53:56.697923 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 13:53:56.700923 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 13:53:56.707342 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 13:53:56.714797 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 13:53:56.715332 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 13:53:56.720839 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 13:53:56.723919 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3058 13:53:56.727640 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3059 13:53:56.734348 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3060 13:53:56.734810 Total UI for P1: 0, mck2ui 16
3061 13:53:56.737543 best dqsien dly found for B0: ( 0, 15, 14)
3062 13:53:56.744215 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3063 13:53:56.748063 Total UI for P1: 0, mck2ui 16
3064 13:53:56.750713 best dqsien dly found for B1: ( 0, 15, 18)
3065 13:53:56.754262 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3066 13:53:56.758805 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3067 13:53:56.759351
3068 13:53:56.761305 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3069 13:53:56.764067 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3070 13:53:56.767843 [Gating] SW calibration Done
3071 13:53:56.768300 ==
3072 13:53:56.770716 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 13:53:56.774146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3074 13:53:56.774728 ==
3075 13:53:56.777666 RX Vref Scan: 0
3076 13:53:56.778205
3077 13:53:56.780803 RX Vref 0 -> 0, step: 1
3078 13:53:56.781263
3079 13:53:56.781617 RX Delay -40 -> 252, step: 8
3080 13:53:56.787797 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3081 13:53:56.790787 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3082 13:53:56.794749 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3083 13:53:56.798080 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3084 13:53:56.801156 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3085 13:53:56.807860 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3086 13:53:56.811166 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3087 13:53:56.814591 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3088 13:53:56.817514 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3089 13:53:56.821022 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3090 13:53:56.824597 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3091 13:53:56.831158 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3092 13:53:56.835060 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3093 13:53:56.837354 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3094 13:53:56.840673 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3095 13:53:56.847471 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3096 13:53:56.847938 ==
3097 13:53:56.850849 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 13:53:56.855060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3099 13:53:56.855635 ==
3100 13:53:56.856114 DQS Delay:
3101 13:53:56.857819 DQS0 = 0, DQS1 = 0
3102 13:53:56.858285 DQM Delay:
3103 13:53:56.861449 DQM0 = 116, DQM1 = 107
3104 13:53:56.861993 DQ Delay:
3105 13:53:56.864265 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3106 13:53:56.869739 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3107 13:53:56.870972 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3108 13:53:56.874231 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3109 13:53:56.874693
3110 13:53:56.875134
3111 13:53:56.875535 ==
3112 13:53:56.877560 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 13:53:56.885251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3114 13:53:56.885792 ==
3115 13:53:56.886270
3116 13:53:56.886711
3117 13:53:56.887126 TX Vref Scan disable
3118 13:53:56.887882 == TX Byte 0 ==
3119 13:53:56.890969 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3120 13:53:56.897363 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3121 13:53:56.897857 == TX Byte 1 ==
3122 13:53:56.901496 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3123 13:53:56.907539 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3124 13:53:56.908060 ==
3125 13:53:56.910645 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 13:53:56.914056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3127 13:53:56.914464 ==
3128 13:53:56.926541 TX Vref=22, minBit 0, minWin=25, winSum=414
3129 13:53:56.929760 TX Vref=24, minBit 11, minWin=25, winSum=425
3130 13:53:56.932138 TX Vref=26, minBit 15, minWin=25, winSum=429
3131 13:53:56.935337 TX Vref=28, minBit 8, minWin=26, winSum=436
3132 13:53:56.938763 TX Vref=30, minBit 8, minWin=26, winSum=436
3133 13:53:56.945700 TX Vref=32, minBit 9, minWin=25, winSum=429
3134 13:53:56.948253 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
3135 13:53:56.948765
3136 13:53:56.952275 Final TX Range 1 Vref 28
3137 13:53:56.952796
3138 13:53:56.953276 ==
3139 13:53:56.955889 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 13:53:56.959079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3141 13:53:56.961787 ==
3142 13:53:56.962252
3143 13:53:56.962721
3144 13:53:56.963168 TX Vref Scan disable
3145 13:53:56.965141 == TX Byte 0 ==
3146 13:53:56.968559 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3147 13:53:56.975407 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3148 13:53:56.975875 == TX Byte 1 ==
3149 13:53:56.978730 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3150 13:53:56.985442 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3151 13:53:56.985900
3152 13:53:56.986455 [DATLAT]
3153 13:53:56.987016 Freq=1200, CH1 RK0
3154 13:53:56.987576
3155 13:53:56.989041 DATLAT Default: 0xd
3156 13:53:56.989457 0, 0xFFFF, sum = 0
3157 13:53:56.992095 1, 0xFFFF, sum = 0
3158 13:53:56.992641 2, 0xFFFF, sum = 0
3159 13:53:56.995315 3, 0xFFFF, sum = 0
3160 13:53:56.998226 4, 0xFFFF, sum = 0
3161 13:53:56.998784 5, 0xFFFF, sum = 0
3162 13:53:57.001535 6, 0xFFFF, sum = 0
3163 13:53:57.001998 7, 0xFFFF, sum = 0
3164 13:53:57.004593 8, 0xFFFF, sum = 0
3165 13:53:57.005286 9, 0xFFFF, sum = 0
3166 13:53:57.008137 10, 0xFFFF, sum = 0
3167 13:53:57.008930 11, 0x0, sum = 1
3168 13:53:57.011548 12, 0x0, sum = 2
3169 13:53:57.012172 13, 0x0, sum = 3
3170 13:53:57.014892 14, 0x0, sum = 4
3171 13:53:57.015446 best_step = 12
3172 13:53:57.015808
3173 13:53:57.016143 ==
3174 13:53:57.018417 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 13:53:57.021638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3176 13:53:57.022102 ==
3177 13:53:57.025229 RX Vref Scan: 1
3178 13:53:57.025753
3179 13:53:57.028524 Set Vref Range= 32 -> 127
3180 13:53:57.029117
3181 13:53:57.029480 RX Vref 32 -> 127, step: 1
3182 13:53:57.029822
3183 13:53:57.031744 RX Delay -29 -> 252, step: 4
3184 13:53:57.032225
3185 13:53:57.035051 Set Vref, RX VrefLevel [Byte0]: 32
3186 13:53:57.038158 [Byte1]: 32
3187 13:53:57.042699
3188 13:53:57.043129 Set Vref, RX VrefLevel [Byte0]: 33
3189 13:53:57.045362 [Byte1]: 33
3190 13:53:57.050115
3191 13:53:57.050631 Set Vref, RX VrefLevel [Byte0]: 34
3192 13:53:57.053102 [Byte1]: 34
3193 13:53:57.058196
3194 13:53:57.058707 Set Vref, RX VrefLevel [Byte0]: 35
3195 13:53:57.061173 [Byte1]: 35
3196 13:53:57.065531
3197 13:53:57.065946 Set Vref, RX VrefLevel [Byte0]: 36
3198 13:53:57.069036 [Byte1]: 36
3199 13:53:57.073853
3200 13:53:57.074382 Set Vref, RX VrefLevel [Byte0]: 37
3201 13:53:57.077432 [Byte1]: 37
3202 13:53:57.082601
3203 13:53:57.083161 Set Vref, RX VrefLevel [Byte0]: 38
3204 13:53:57.086303 [Byte1]: 38
3205 13:53:57.089423
3206 13:53:57.089878 Set Vref, RX VrefLevel [Byte0]: 39
3207 13:53:57.093623 [Byte1]: 39
3208 13:53:57.097605
3209 13:53:57.098171 Set Vref, RX VrefLevel [Byte0]: 40
3210 13:53:57.100799 [Byte1]: 40
3211 13:53:57.105497
3212 13:53:57.105950 Set Vref, RX VrefLevel [Byte0]: 41
3213 13:53:57.110479 [Byte1]: 41
3214 13:53:57.113877
3215 13:53:57.114332 Set Vref, RX VrefLevel [Byte0]: 42
3216 13:53:57.117300 [Byte1]: 42
3217 13:53:57.121510
3218 13:53:57.122067 Set Vref, RX VrefLevel [Byte0]: 43
3219 13:53:57.124831 [Byte1]: 43
3220 13:53:57.130224
3221 13:53:57.130782 Set Vref, RX VrefLevel [Byte0]: 44
3222 13:53:57.133325 [Byte1]: 44
3223 13:53:57.137620
3224 13:53:57.138076 Set Vref, RX VrefLevel [Byte0]: 45
3225 13:53:57.140918 [Byte1]: 45
3226 13:53:57.145710
3227 13:53:57.146166 Set Vref, RX VrefLevel [Byte0]: 46
3228 13:53:57.148444 [Byte1]: 46
3229 13:53:57.153877
3230 13:53:57.154402 Set Vref, RX VrefLevel [Byte0]: 47
3231 13:53:57.156841 [Byte1]: 47
3232 13:53:57.161048
3233 13:53:57.161518 Set Vref, RX VrefLevel [Byte0]: 48
3234 13:53:57.164531 [Byte1]: 48
3235 13:53:57.169169
3236 13:53:57.169625 Set Vref, RX VrefLevel [Byte0]: 49
3237 13:53:57.173189 [Byte1]: 49
3238 13:53:57.177481
3239 13:53:57.177939 Set Vref, RX VrefLevel [Byte0]: 50
3240 13:53:57.181676 [Byte1]: 50
3241 13:53:57.185675
3242 13:53:57.188191 Set Vref, RX VrefLevel [Byte0]: 51
3243 13:53:57.188649 [Byte1]: 51
3244 13:53:57.192825
3245 13:53:57.193278 Set Vref, RX VrefLevel [Byte0]: 52
3246 13:53:57.196852 [Byte1]: 52
3247 13:53:57.201293
3248 13:53:57.201872 Set Vref, RX VrefLevel [Byte0]: 53
3249 13:53:57.204170 [Byte1]: 53
3250 13:53:57.209656
3251 13:53:57.210213 Set Vref, RX VrefLevel [Byte0]: 54
3252 13:53:57.212433 [Byte1]: 54
3253 13:53:57.217202
3254 13:53:57.217765 Set Vref, RX VrefLevel [Byte0]: 55
3255 13:53:57.220211 [Byte1]: 55
3256 13:53:57.224913
3257 13:53:57.225469 Set Vref, RX VrefLevel [Byte0]: 56
3258 13:53:57.227949 [Byte1]: 56
3259 13:53:57.233077
3260 13:53:57.233607 Set Vref, RX VrefLevel [Byte0]: 57
3261 13:53:57.236765 [Byte1]: 57
3262 13:53:57.240671
3263 13:53:57.241376 Set Vref, RX VrefLevel [Byte0]: 58
3264 13:53:57.244101 [Byte1]: 58
3265 13:53:57.249245
3266 13:53:57.249699 Set Vref, RX VrefLevel [Byte0]: 59
3267 13:53:57.253167 [Byte1]: 59
3268 13:53:57.257158
3269 13:53:57.257608 Set Vref, RX VrefLevel [Byte0]: 60
3270 13:53:57.260555 [Byte1]: 60
3271 13:53:57.264638
3272 13:53:57.265178 Set Vref, RX VrefLevel [Byte0]: 61
3273 13:53:57.268382 [Byte1]: 61
3274 13:53:57.272534
3275 13:53:57.272989 Set Vref, RX VrefLevel [Byte0]: 62
3276 13:53:57.276238 [Byte1]: 62
3277 13:53:57.280906
3278 13:53:57.281436 Set Vref, RX VrefLevel [Byte0]: 63
3279 13:53:57.284828 [Byte1]: 63
3280 13:53:57.288820
3281 13:53:57.289412 Set Vref, RX VrefLevel [Byte0]: 64
3282 13:53:57.292672 [Byte1]: 64
3283 13:53:57.296804
3284 13:53:57.297262 Set Vref, RX VrefLevel [Byte0]: 65
3285 13:53:57.299793 [Byte1]: 65
3286 13:53:57.305166
3287 13:53:57.305621 Set Vref, RX VrefLevel [Byte0]: 66
3288 13:53:57.307434 [Byte1]: 66
3289 13:53:57.313220
3290 13:53:57.313731 Set Vref, RX VrefLevel [Byte0]: 67
3291 13:53:57.315854 [Byte1]: 67
3292 13:53:57.320486
3293 13:53:57.321041 Final RX Vref Byte 0 = 51 to rank0
3294 13:53:57.324614 Final RX Vref Byte 1 = 50 to rank0
3295 13:53:57.326756 Final RX Vref Byte 0 = 51 to rank1
3296 13:53:57.330446 Final RX Vref Byte 1 = 50 to rank1==
3297 13:53:57.333978 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 13:53:57.340276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3299 13:53:57.340692 ==
3300 13:53:57.341055 DQS Delay:
3301 13:53:57.341621 DQS0 = 0, DQS1 = 0
3302 13:53:57.343613 DQM Delay:
3303 13:53:57.344028 DQM0 = 115, DQM1 = 106
3304 13:53:57.347069 DQ Delay:
3305 13:53:57.349788 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3306 13:53:57.353647 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3307 13:53:57.356620 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3308 13:53:57.361405 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3309 13:53:57.361818
3310 13:53:57.362155
3311 13:53:57.366757 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3312 13:53:57.370750 CH1 RK0: MR19=404, MR18=1919
3313 13:53:57.377426 CH1_RK0: MR19=0x404, MR18=0x1919, DQSOSC=400, MR23=63, INC=40, DEC=27
3314 13:53:57.377890
3315 13:53:57.380441 ----->DramcWriteLeveling(PI) begin...
3316 13:53:57.381188 ==
3317 13:53:57.383695 Dram Type= 6, Freq= 0, CH_1, rank 1
3318 13:53:57.387728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3319 13:53:57.388189 ==
3320 13:53:57.390920 Write leveling (Byte 0): 23 => 23
3321 13:53:57.394681 Write leveling (Byte 1): 21 => 21
3322 13:53:57.396968 DramcWriteLeveling(PI) end<-----
3323 13:53:57.397443
3324 13:53:57.398064 ==
3325 13:53:57.402114 Dram Type= 6, Freq= 0, CH_1, rank 1
3326 13:53:57.406701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3327 13:53:57.407140 ==
3328 13:53:57.407601 [Gating] SW mode calibration
3329 13:53:57.416902 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3330 13:53:57.420008 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3331 13:53:57.423714 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3332 13:53:57.430445 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3333 13:53:57.433673 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3334 13:53:57.436609 0 11 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
3335 13:53:57.444059 0 11 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
3336 13:53:57.446832 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3337 13:53:57.451181 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3338 13:53:57.457095 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3339 13:53:57.460216 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3340 13:53:57.463615 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3341 13:53:57.470179 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3342 13:53:57.473143 0 12 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (1 1)
3343 13:53:57.476762 0 12 16 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
3344 13:53:57.483587 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3345 13:53:57.487433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3346 13:53:57.490869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3347 13:53:57.497033 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 13:53:57.500854 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 13:53:57.503925 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3350 13:53:57.511061 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3351 13:53:57.513419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3352 13:53:57.516662 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3353 13:53:57.523467 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 13:53:57.526971 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 13:53:57.530559 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 13:53:57.534094 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 13:53:57.539919 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 13:53:57.543351 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 13:53:57.546701 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 13:53:57.553534 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 13:53:57.556399 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 13:53:57.560051 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 13:53:57.566846 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 13:53:57.570164 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 13:53:57.573390 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 13:53:57.580593 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3367 13:53:57.583706 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3368 13:53:57.586717 Total UI for P1: 0, mck2ui 16
3369 13:53:57.590052 best dqsien dly found for B0: ( 0, 15, 12)
3370 13:53:57.592976 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3371 13:53:57.596668 Total UI for P1: 0, mck2ui 16
3372 13:53:57.600083 best dqsien dly found for B1: ( 0, 15, 14)
3373 13:53:57.602658 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3374 13:53:57.606752 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3375 13:53:57.607210
3376 13:53:57.613129 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3377 13:53:57.617166 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3378 13:53:57.619702 [Gating] SW calibration Done
3379 13:53:57.620158 ==
3380 13:53:57.623652 Dram Type= 6, Freq= 0, CH_1, rank 1
3381 13:53:57.626477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3382 13:53:57.627037 ==
3383 13:53:57.627397 RX Vref Scan: 0
3384 13:53:57.627729
3385 13:53:57.629881 RX Vref 0 -> 0, step: 1
3386 13:53:57.630437
3387 13:53:57.633620 RX Delay -40 -> 252, step: 8
3388 13:53:57.637336 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3389 13:53:57.640376 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3390 13:53:57.646563 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3391 13:53:57.649456 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3392 13:53:57.653234 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3393 13:53:57.657165 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3394 13:53:57.659831 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3395 13:53:57.663067 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3396 13:53:57.671249 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3397 13:53:57.673249 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3398 13:53:57.676612 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3399 13:53:57.680199 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3400 13:53:57.683407 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3401 13:53:57.689805 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3402 13:53:57.693553 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3403 13:53:57.697369 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3404 13:53:57.697914 ==
3405 13:53:57.700057 Dram Type= 6, Freq= 0, CH_1, rank 1
3406 13:53:57.703040 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3407 13:53:57.706806 ==
3408 13:53:57.707350 DQS Delay:
3409 13:53:57.707711 DQS0 = 0, DQS1 = 0
3410 13:53:57.710017 DQM Delay:
3411 13:53:57.710559 DQM0 = 116, DQM1 = 106
3412 13:53:57.713356 DQ Delay:
3413 13:53:57.716339 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3414 13:53:57.720374 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3415 13:53:57.726654 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3416 13:53:57.727684 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3417 13:53:57.728070
3418 13:53:57.728409
3419 13:53:57.728791 ==
3420 13:53:57.730572 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 13:53:57.733331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3422 13:53:57.733789 ==
3423 13:53:57.734145
3424 13:53:57.734470
3425 13:53:57.736554 TX Vref Scan disable
3426 13:53:57.740207 == TX Byte 0 ==
3427 13:53:57.742781 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3428 13:53:57.746304 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3429 13:53:57.749646 == TX Byte 1 ==
3430 13:53:57.753291 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3431 13:53:57.756796 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3432 13:53:57.757340 ==
3433 13:53:57.759962 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 13:53:57.763016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3435 13:53:57.766396 ==
3436 13:53:57.776365 TX Vref=22, minBit 1, minWin=25, winSum=420
3437 13:53:57.779775 TX Vref=24, minBit 1, minWin=26, winSum=425
3438 13:53:57.783032 TX Vref=26, minBit 9, minWin=25, winSum=424
3439 13:53:57.786849 TX Vref=28, minBit 9, minWin=26, winSum=433
3440 13:53:57.789761 TX Vref=30, minBit 8, minWin=26, winSum=433
3441 13:53:57.793264 TX Vref=32, minBit 0, minWin=26, winSum=432
3442 13:53:57.800512 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3443 13:53:57.801124
3444 13:53:57.802744 Final TX Range 1 Vref 28
3445 13:53:57.803196
3446 13:53:57.803549 ==
3447 13:53:57.807078 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 13:53:57.809409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3449 13:53:57.809868 ==
3450 13:53:57.810223
3451 13:53:57.812923
3452 13:53:57.813374 TX Vref Scan disable
3453 13:53:57.817001 == TX Byte 0 ==
3454 13:53:57.820174 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3455 13:53:57.822807 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3456 13:53:57.826173 == TX Byte 1 ==
3457 13:53:57.829982 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3458 13:53:57.832852 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3459 13:53:57.833328
3460 13:53:57.836272 [DATLAT]
3461 13:53:57.836887 Freq=1200, CH1 RK1
3462 13:53:57.837377
3463 13:53:57.840689 DATLAT Default: 0xc
3464 13:53:57.841335 0, 0xFFFF, sum = 0
3465 13:53:57.843246 1, 0xFFFF, sum = 0
3466 13:53:57.843738 2, 0xFFFF, sum = 0
3467 13:53:57.846017 3, 0xFFFF, sum = 0
3468 13:53:57.846507 4, 0xFFFF, sum = 0
3469 13:53:57.849969 5, 0xFFFF, sum = 0
3470 13:53:57.850527 6, 0xFFFF, sum = 0
3471 13:53:57.853570 7, 0xFFFF, sum = 0
3472 13:53:57.854035 8, 0xFFFF, sum = 0
3473 13:53:57.856685 9, 0xFFFF, sum = 0
3474 13:53:57.859845 10, 0xFFFF, sum = 0
3475 13:53:57.860404 11, 0x0, sum = 1
3476 13:53:57.860910 12, 0x0, sum = 2
3477 13:53:57.863065 13, 0x0, sum = 3
3478 13:53:57.863529 14, 0x0, sum = 4
3479 13:53:57.866123 best_step = 12
3480 13:53:57.866630
3481 13:53:57.866989 ==
3482 13:53:57.869666 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 13:53:57.872918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3484 13:53:57.873380 ==
3485 13:53:57.876142 RX Vref Scan: 0
3486 13:53:57.876595
3487 13:53:57.877013 RX Vref 0 -> 0, step: 1
3488 13:53:57.877354
3489 13:53:57.880067 RX Delay -29 -> 252, step: 4
3490 13:53:57.886179 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3491 13:53:57.890541 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3492 13:53:57.893964 iDelay=199, Bit 2, Center 106 (35 ~ 178) 144
3493 13:53:57.897092 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3494 13:53:57.899434 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3495 13:53:57.906745 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3496 13:53:57.910028 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3497 13:53:57.913020 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3498 13:53:57.916403 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3499 13:53:57.920099 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3500 13:53:57.926343 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3501 13:53:57.929369 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3502 13:53:57.933149 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3503 13:53:57.936195 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3504 13:53:57.939747 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3505 13:53:57.946468 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3506 13:53:57.946885 ==
3507 13:53:57.950430 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 13:53:57.954067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3509 13:53:57.954588 ==
3510 13:53:57.954921 DQS Delay:
3511 13:53:57.956697 DQS0 = 0, DQS1 = 0
3512 13:53:57.957170 DQM Delay:
3513 13:53:57.959521 DQM0 = 114, DQM1 = 104
3514 13:53:57.959938 DQ Delay:
3515 13:53:57.962991 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =112
3516 13:53:57.966383 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3517 13:53:57.970141 DQ8 =86, DQ9 =94, DQ10 =106, DQ11 =98
3518 13:53:57.972675 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =110
3519 13:53:57.973136
3520 13:53:57.973460
3521 13:53:57.983114 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3522 13:53:57.986502 CH1 RK1: MR19=404, MR18=B0B
3523 13:53:57.989793 CH1_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3524 13:53:57.993335 [RxdqsGatingPostProcess] freq 1200
3525 13:53:57.999772 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3526 13:53:58.003269 Pre-setting of DQS Precalculation
3527 13:53:58.006078 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3528 13:53:58.016658 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3529 13:53:58.023928 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3530 13:53:58.024451
3531 13:53:58.024837
3532 13:53:58.026599 [Calibration Summary] 2400 Mbps
3533 13:53:58.027013 CH 0, Rank 0
3534 13:53:58.029922 SW Impedance : PASS
3535 13:53:58.030443 DUTY Scan : NO K
3536 13:53:58.034278 ZQ Calibration : PASS
3537 13:53:58.036104 Jitter Meter : NO K
3538 13:53:58.036626 CBT Training : PASS
3539 13:53:58.039930 Write leveling : PASS
3540 13:53:58.042951 RX DQS gating : PASS
3541 13:53:58.043372 RX DQ/DQS(RDDQC) : PASS
3542 13:53:58.046816 TX DQ/DQS : PASS
3543 13:53:58.047231 RX DATLAT : PASS
3544 13:53:58.050384 RX DQ/DQS(Engine): PASS
3545 13:53:58.053228 TX OE : NO K
3546 13:53:58.053643 All Pass.
3547 13:53:58.053966
3548 13:53:58.054268 CH 0, Rank 1
3549 13:53:58.057111 SW Impedance : PASS
3550 13:53:58.061339 DUTY Scan : NO K
3551 13:53:58.061869 ZQ Calibration : PASS
3552 13:53:58.063336 Jitter Meter : NO K
3553 13:53:58.066910 CBT Training : PASS
3554 13:53:58.067322 Write leveling : PASS
3555 13:53:58.069502 RX DQS gating : PASS
3556 13:53:58.073364 RX DQ/DQS(RDDQC) : PASS
3557 13:53:58.073882 TX DQ/DQS : PASS
3558 13:53:58.076283 RX DATLAT : PASS
3559 13:53:58.079645 RX DQ/DQS(Engine): PASS
3560 13:53:58.080065 TX OE : NO K
3561 13:53:58.083535 All Pass.
3562 13:53:58.084075
3563 13:53:58.084411 CH 1, Rank 0
3564 13:53:58.086703 SW Impedance : PASS
3565 13:53:58.087223 DUTY Scan : NO K
3566 13:53:58.089231 ZQ Calibration : PASS
3567 13:53:58.092385 Jitter Meter : NO K
3568 13:53:58.092840 CBT Training : PASS
3569 13:53:58.096263 Write leveling : PASS
3570 13:53:58.100029 RX DQS gating : PASS
3571 13:53:58.100550 RX DQ/DQS(RDDQC) : PASS
3572 13:53:58.102934 TX DQ/DQS : PASS
3573 13:53:58.103349 RX DATLAT : PASS
3574 13:53:58.106149 RX DQ/DQS(Engine): PASS
3575 13:53:58.109720 TX OE : NO K
3576 13:53:58.110261 All Pass.
3577 13:53:58.110591
3578 13:53:58.110894 CH 1, Rank 1
3579 13:53:58.112849 SW Impedance : PASS
3580 13:53:58.116467 DUTY Scan : NO K
3581 13:53:58.117033 ZQ Calibration : PASS
3582 13:53:58.119938 Jitter Meter : NO K
3583 13:53:58.122799 CBT Training : PASS
3584 13:53:58.123320 Write leveling : PASS
3585 13:53:58.126233 RX DQS gating : PASS
3586 13:53:58.130616 RX DQ/DQS(RDDQC) : PASS
3587 13:53:58.131136 TX DQ/DQS : PASS
3588 13:53:58.132493 RX DATLAT : PASS
3589 13:53:58.136553 RX DQ/DQS(Engine): PASS
3590 13:53:58.137159 TX OE : NO K
3591 13:53:58.137500 All Pass.
3592 13:53:58.139747
3593 13:53:58.140254 DramC Write-DBI off
3594 13:53:58.142514 PER_BANK_REFRESH: Hybrid Mode
3595 13:53:58.142927 TX_TRACKING: ON
3596 13:53:58.152672 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3597 13:53:58.155852 [FAST_K] Save calibration result to emmc
3598 13:53:58.159034 dramc_set_vcore_voltage set vcore to 650000
3599 13:53:58.162499 Read voltage for 600, 5
3600 13:53:58.162915 Vio18 = 0
3601 13:53:58.165736 Vcore = 650000
3602 13:53:58.166286 Vdram = 0
3603 13:53:58.166702 Vddq = 0
3604 13:53:58.167171 Vmddr = 0
3605 13:53:58.172813 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3606 13:53:58.179205 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3607 13:53:58.179622 MEM_TYPE=3, freq_sel=19
3608 13:53:58.182303 sv_algorithm_assistance_LP4_1600
3609 13:53:58.185780 ============ PULL DRAM RESETB DOWN ============
3610 13:53:58.192268 ========== PULL DRAM RESETB DOWN end =========
3611 13:53:58.195568 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3612 13:53:58.199111 ===================================
3613 13:53:58.202399 LPDDR4 DRAM CONFIGURATION
3614 13:53:58.205411 ===================================
3615 13:53:58.205541 EX_ROW_EN[0] = 0x0
3616 13:53:58.208546 EX_ROW_EN[1] = 0x0
3617 13:53:58.208675 LP4Y_EN = 0x0
3618 13:53:58.212157 WORK_FSP = 0x0
3619 13:53:58.212269 WL = 0x2
3620 13:53:58.215388 RL = 0x2
3621 13:53:58.215489 BL = 0x2
3622 13:53:58.218817 RPST = 0x0
3623 13:53:58.222200 RD_PRE = 0x0
3624 13:53:58.222291 WR_PRE = 0x1
3625 13:53:58.225790 WR_PST = 0x0
3626 13:53:58.225872 DBI_WR = 0x0
3627 13:53:58.228461 DBI_RD = 0x0
3628 13:53:58.228543 OTF = 0x1
3629 13:53:58.232376 ===================================
3630 13:53:58.235391 ===================================
3631 13:53:58.238654 ANA top config
3632 13:53:58.238737 ===================================
3633 13:53:58.241733 DLL_ASYNC_EN = 0
3634 13:53:58.245150 ALL_SLAVE_EN = 1
3635 13:53:58.248630 NEW_RANK_MODE = 1
3636 13:53:58.252114 DLL_IDLE_MODE = 1
3637 13:53:58.252236 LP45_APHY_COMB_EN = 1
3638 13:53:58.255519 TX_ODT_DIS = 1
3639 13:53:58.259247 NEW_8X_MODE = 1
3640 13:53:58.261933 ===================================
3641 13:53:58.265398 ===================================
3642 13:53:58.268910 data_rate = 1200
3643 13:53:58.272493 CKR = 1
3644 13:53:58.272957 DQ_P2S_RATIO = 8
3645 13:53:58.275242 ===================================
3646 13:53:58.278751 CA_P2S_RATIO = 8
3647 13:53:58.281738 DQ_CA_OPEN = 0
3648 13:53:58.284949 DQ_SEMI_OPEN = 0
3649 13:53:58.288673 CA_SEMI_OPEN = 0
3650 13:53:58.291723 CA_FULL_RATE = 0
3651 13:53:58.291875 DQ_CKDIV4_EN = 1
3652 13:53:58.295227 CA_CKDIV4_EN = 1
3653 13:53:58.298243 CA_PREDIV_EN = 0
3654 13:53:58.301707 PH8_DLY = 0
3655 13:53:58.304997 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3656 13:53:58.308220 DQ_AAMCK_DIV = 4
3657 13:53:58.308320 CA_AAMCK_DIV = 4
3658 13:53:58.311774 CA_ADMCK_DIV = 4
3659 13:53:58.315369 DQ_TRACK_CA_EN = 0
3660 13:53:58.318219 CA_PICK = 600
3661 13:53:58.321799 CA_MCKIO = 600
3662 13:53:58.324682 MCKIO_SEMI = 0
3663 13:53:58.328039 PLL_FREQ = 2288
3664 13:53:58.331644 DQ_UI_PI_RATIO = 32
3665 13:53:58.331777 CA_UI_PI_RATIO = 0
3666 13:53:58.336044 ===================================
3667 13:53:58.338659 ===================================
3668 13:53:58.341448 memory_type:LPDDR4
3669 13:53:58.344732 GP_NUM : 10
3670 13:53:58.344871 SRAM_EN : 1
3671 13:53:58.347677 MD32_EN : 0
3672 13:53:58.351189 ===================================
3673 13:53:58.354654 [ANA_INIT] >>>>>>>>>>>>>>
3674 13:53:58.358768 <<<<<< [CONFIGURE PHASE]: ANA_TX
3675 13:53:58.361011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3676 13:53:58.364574 ===================================
3677 13:53:58.364767 data_rate = 1200,PCW = 0X5800
3678 13:53:58.368081 ===================================
3679 13:53:58.371167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3680 13:53:58.378482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3681 13:53:58.386262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3682 13:53:58.388345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3683 13:53:58.391086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3684 13:53:58.394535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3685 13:53:58.398042 [ANA_INIT] flow start
3686 13:53:58.400894 [ANA_INIT] PLL >>>>>>>>
3687 13:53:58.401353 [ANA_INIT] PLL <<<<<<<<
3688 13:53:58.404260 [ANA_INIT] MIDPI >>>>>>>>
3689 13:53:58.407611 [ANA_INIT] MIDPI <<<<<<<<
3690 13:53:58.408143 [ANA_INIT] DLL >>>>>>>>
3691 13:53:58.410980 [ANA_INIT] flow end
3692 13:53:58.414250 ============ LP4 DIFF to SE enter ============
3693 13:53:58.417614 ============ LP4 DIFF to SE exit ============
3694 13:53:58.421553 [ANA_INIT] <<<<<<<<<<<<<
3695 13:53:58.424780 [Flow] Enable top DCM control >>>>>
3696 13:53:58.427784 [Flow] Enable top DCM control <<<<<
3697 13:53:58.430933 Enable DLL master slave shuffle
3698 13:53:58.438034 ==============================================================
3699 13:53:58.438551 Gating Mode config
3700 13:53:58.444193 ==============================================================
3701 13:53:58.444754 Config description:
3702 13:53:58.454350 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3703 13:53:58.460880 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3704 13:53:58.467181 SELPH_MODE 0: By rank 1: By Phase
3705 13:53:58.470635 ==============================================================
3706 13:53:58.473884 GAT_TRACK_EN = 1
3707 13:53:58.477302 RX_GATING_MODE = 2
3708 13:53:58.480823 RX_GATING_TRACK_MODE = 2
3709 13:53:58.484059 SELPH_MODE = 1
3710 13:53:58.487758 PICG_EARLY_EN = 1
3711 13:53:58.491295 VALID_LAT_VALUE = 1
3712 13:53:58.497861 ==============================================================
3713 13:53:58.501525 Enter into Gating configuration >>>>
3714 13:53:58.504069 Exit from Gating configuration <<<<
3715 13:53:58.508170 Enter into DVFS_PRE_config >>>>>
3716 13:53:58.516551 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3717 13:53:58.521099 Exit from DVFS_PRE_config <<<<<
3718 13:53:58.523576 Enter into PICG configuration >>>>
3719 13:53:58.527619 Exit from PICG configuration <<<<
3720 13:53:58.530217 [RX_INPUT] configuration >>>>>
3721 13:53:58.530775 [RX_INPUT] configuration <<<<<
3722 13:53:58.536814 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3723 13:53:58.543555 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3724 13:53:58.549821 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3725 13:53:58.553439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3726 13:53:58.559495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3727 13:53:58.565935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3728 13:53:58.571334 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3729 13:53:58.576204 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3730 13:53:58.579780 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3731 13:53:58.583114 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3732 13:53:58.586209 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3733 13:53:58.592779 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3734 13:53:58.596047 ===================================
3735 13:53:58.596501 LPDDR4 DRAM CONFIGURATION
3736 13:53:58.599442 ===================================
3737 13:53:58.602515 EX_ROW_EN[0] = 0x0
3738 13:53:58.606362 EX_ROW_EN[1] = 0x0
3739 13:53:58.606813 LP4Y_EN = 0x0
3740 13:53:58.609529 WORK_FSP = 0x0
3741 13:53:58.609981 WL = 0x2
3742 13:53:58.612821 RL = 0x2
3743 13:53:58.613343 BL = 0x2
3744 13:53:58.615872 RPST = 0x0
3745 13:53:58.616323 RD_PRE = 0x0
3746 13:53:58.619859 WR_PRE = 0x1
3747 13:53:58.620379 WR_PST = 0x0
3748 13:53:58.622626 DBI_WR = 0x0
3749 13:53:58.623194 DBI_RD = 0x0
3750 13:53:58.626659 OTF = 0x1
3751 13:53:58.629111 ===================================
3752 13:53:58.632466 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3753 13:53:58.636302 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3754 13:53:58.642423 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3755 13:53:58.645530 ===================================
3756 13:53:58.646044 LPDDR4 DRAM CONFIGURATION
3757 13:53:58.649038 ===================================
3758 13:53:58.653032 EX_ROW_EN[0] = 0x10
3759 13:53:58.656021 EX_ROW_EN[1] = 0x0
3760 13:53:58.656569 LP4Y_EN = 0x0
3761 13:53:58.658694 WORK_FSP = 0x0
3762 13:53:58.659139 WL = 0x2
3763 13:53:58.662362 RL = 0x2
3764 13:53:58.662824 BL = 0x2
3765 13:53:58.665504 RPST = 0x0
3766 13:53:58.665951 RD_PRE = 0x0
3767 13:53:58.668668 WR_PRE = 0x1
3768 13:53:58.669151 WR_PST = 0x0
3769 13:53:58.672361 DBI_WR = 0x0
3770 13:53:58.672868 DBI_RD = 0x0
3771 13:53:58.675299 OTF = 0x1
3772 13:53:58.679313 ===================================
3773 13:53:58.685339 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3774 13:53:58.688994 nWR fixed to 30
3775 13:53:58.689546 [ModeRegInit_LP4] CH0 RK0
3776 13:53:58.691914 [ModeRegInit_LP4] CH0 RK1
3777 13:53:58.695548 [ModeRegInit_LP4] CH1 RK0
3778 13:53:58.699055 [ModeRegInit_LP4] CH1 RK1
3779 13:53:58.699507 match AC timing 16
3780 13:53:58.705077 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3781 13:53:58.708672 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3782 13:53:58.712520 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3783 13:53:58.718595 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3784 13:53:58.721823 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3785 13:53:58.722371 ==
3786 13:53:58.724884 Dram Type= 6, Freq= 0, CH_0, rank 0
3787 13:53:58.728389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3788 13:53:58.728984 ==
3789 13:53:58.735984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3790 13:53:58.742186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3791 13:53:58.746164 [CA 0] Center 35 (5~66) winsize 62
3792 13:53:58.748456 [CA 1] Center 35 (5~66) winsize 62
3793 13:53:58.752218 [CA 2] Center 34 (4~65) winsize 62
3794 13:53:58.755622 [CA 3] Center 34 (3~65) winsize 63
3795 13:53:58.758553 [CA 4] Center 33 (3~64) winsize 62
3796 13:53:58.761415 [CA 5] Center 33 (3~64) winsize 62
3797 13:53:58.761870
3798 13:53:58.764967 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3799 13:53:58.765425
3800 13:53:58.768302 [CATrainingPosCal] consider 1 rank data
3801 13:53:58.771500 u2DelayCellTimex100 = 270/100 ps
3802 13:53:58.774656 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3803 13:53:58.777729 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3804 13:53:58.781219 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3805 13:53:58.784743 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3806 13:53:58.787575 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3807 13:53:58.791104 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3808 13:53:58.794494
3809 13:53:58.798157 CA PerBit enable=1, Macro0, CA PI delay=33
3810 13:53:58.798611
3811 13:53:58.801478 [CBTSetCACLKResult] CA Dly = 33
3812 13:53:58.802031 CS Dly: 5 (0~36)
3813 13:53:58.802396 ==
3814 13:53:58.804062 Dram Type= 6, Freq= 0, CH_0, rank 1
3815 13:53:58.807752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3816 13:53:58.808310 ==
3817 13:53:58.814402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3818 13:53:58.821175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3819 13:53:58.823888 [CA 0] Center 35 (5~66) winsize 62
3820 13:53:58.828735 [CA 1] Center 35 (5~66) winsize 62
3821 13:53:58.831139 [CA 2] Center 34 (4~65) winsize 62
3822 13:53:58.834548 [CA 3] Center 34 (4~65) winsize 62
3823 13:53:58.838393 [CA 4] Center 33 (3~64) winsize 62
3824 13:53:58.840543 [CA 5] Center 33 (3~64) winsize 62
3825 13:53:58.841144
3826 13:53:58.844291 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3827 13:53:58.844907
3828 13:53:58.847887 [CATrainingPosCal] consider 2 rank data
3829 13:53:58.850760 u2DelayCellTimex100 = 270/100 ps
3830 13:53:58.854271 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3831 13:53:58.857718 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3832 13:53:58.861107 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3833 13:53:58.863997 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3834 13:53:58.870632 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3835 13:53:58.873843 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3836 13:53:58.874298
3837 13:53:58.877220 CA PerBit enable=1, Macro0, CA PI delay=33
3838 13:53:58.877676
3839 13:53:58.881645 [CBTSetCACLKResult] CA Dly = 33
3840 13:53:58.882204 CS Dly: 5 (0~36)
3841 13:53:58.882565
3842 13:53:58.883851 ----->DramcWriteLeveling(PI) begin...
3843 13:53:58.884316 ==
3844 13:53:58.887486 Dram Type= 6, Freq= 0, CH_0, rank 0
3845 13:53:58.893879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3846 13:53:58.894438 ==
3847 13:53:58.897349 Write leveling (Byte 0): 31 => 31
3848 13:53:58.900744 Write leveling (Byte 1): 30 => 30
3849 13:53:58.901305 DramcWriteLeveling(PI) end<-----
3850 13:53:58.901668
3851 13:53:58.904141 ==
3852 13:53:58.907287 Dram Type= 6, Freq= 0, CH_0, rank 0
3853 13:53:58.910371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3854 13:53:58.910916 ==
3855 13:53:58.914016 [Gating] SW mode calibration
3856 13:53:58.921413 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3857 13:53:58.923895 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3858 13:53:58.930483 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3859 13:53:58.933594 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3860 13:53:58.936846 0 5 8 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
3861 13:53:58.943937 0 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3862 13:53:58.948786 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3863 13:53:58.950349 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3864 13:53:58.956843 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3865 13:53:58.959874 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3866 13:53:58.963670 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3867 13:53:58.971029 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3868 13:53:58.973366 0 6 8 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
3869 13:53:58.976900 0 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
3870 13:53:58.982889 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3871 13:53:58.986473 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3872 13:53:58.989695 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3873 13:53:58.997149 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3874 13:53:59.000261 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3875 13:53:59.003882 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3876 13:53:59.009921 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3877 13:53:59.013037 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 13:53:59.016974 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 13:53:59.023024 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 13:53:59.026035 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 13:53:59.029577 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 13:53:59.036510 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 13:53:59.039987 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 13:53:59.043065 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 13:53:59.049269 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 13:53:59.052769 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 13:53:59.056858 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 13:53:59.060805 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 13:53:59.065987 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 13:53:59.069219 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 13:53:59.072820 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 13:53:59.079691 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3893 13:53:59.082768 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3894 13:53:59.086409 Total UI for P1: 0, mck2ui 16
3895 13:53:59.089372 best dqsien dly found for B0: ( 0, 9, 8)
3896 13:53:59.092439 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3897 13:53:59.096476 Total UI for P1: 0, mck2ui 16
3898 13:53:59.100109 best dqsien dly found for B1: ( 0, 9, 10)
3899 13:53:59.103089 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3900 13:53:59.105921 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3901 13:53:59.106377
3902 13:53:59.112857 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3903 13:53:59.116284 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3904 13:53:59.119812 [Gating] SW calibration Done
3905 13:53:59.120268 ==
3906 13:53:59.122499 Dram Type= 6, Freq= 0, CH_0, rank 0
3907 13:53:59.125809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3908 13:53:59.126271 ==
3909 13:53:59.126629 RX Vref Scan: 0
3910 13:53:59.127040
3911 13:53:59.129655 RX Vref 0 -> 0, step: 1
3912 13:53:59.130137
3913 13:53:59.132579 RX Delay -230 -> 252, step: 16
3914 13:53:59.136051 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3915 13:53:59.139169 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3916 13:53:59.146418 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3917 13:53:59.149190 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3918 13:53:59.153086 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3919 13:53:59.156247 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3920 13:53:59.163460 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3921 13:53:59.165805 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3922 13:53:59.170346 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3923 13:53:59.172195 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3924 13:53:59.176330 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3925 13:53:59.183328 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3926 13:53:59.186143 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3927 13:53:59.189013 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3928 13:53:59.192430 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3929 13:53:59.198756 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3930 13:53:59.199308 ==
3931 13:53:59.202449 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 13:53:59.207157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3933 13:53:59.207621 ==
3934 13:53:59.207981 DQS Delay:
3935 13:53:59.208669 DQS0 = 0, DQS1 = 0
3936 13:53:59.209062 DQM Delay:
3937 13:53:59.213051 DQM0 = 38, DQM1 = 33
3938 13:53:59.213584 DQ Delay:
3939 13:53:59.215767 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3940 13:53:59.219274 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3941 13:53:59.222102 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3942 13:53:59.225639 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3943 13:53:59.226190
3944 13:53:59.226548
3945 13:53:59.226881 ==
3946 13:53:59.228827 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 13:53:59.232170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3948 13:53:59.235576 ==
3949 13:53:59.236151
3950 13:53:59.236515
3951 13:53:59.236909 TX Vref Scan disable
3952 13:53:59.238719 == TX Byte 0 ==
3953 13:53:59.242445 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3954 13:53:59.245900 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3955 13:53:59.248579 == TX Byte 1 ==
3956 13:53:59.252031 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3957 13:53:59.255393 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3958 13:53:59.258789 ==
3959 13:53:59.262121 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 13:53:59.264786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3961 13:53:59.265248 ==
3962 13:53:59.265609
3963 13:53:59.265944
3964 13:53:59.268357 TX Vref Scan disable
3965 13:53:59.269003 == TX Byte 0 ==
3966 13:53:59.276418 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3967 13:53:59.278546 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3968 13:53:59.282623 == TX Byte 1 ==
3969 13:53:59.284643 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3970 13:53:59.288554 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3971 13:53:59.289127
3972 13:53:59.289488 [DATLAT]
3973 13:53:59.292012 Freq=600, CH0 RK0
3974 13:53:59.292536
3975 13:53:59.292935 DATLAT Default: 0x9
3976 13:53:59.294872 0, 0xFFFF, sum = 0
3977 13:53:59.295335 1, 0xFFFF, sum = 0
3978 13:53:59.298759 2, 0xFFFF, sum = 0
3979 13:53:59.301492 3, 0xFFFF, sum = 0
3980 13:53:59.301955 4, 0xFFFF, sum = 0
3981 13:53:59.304812 5, 0xFFFF, sum = 0
3982 13:53:59.305393 6, 0xFFFF, sum = 0
3983 13:53:59.307855 7, 0x0, sum = 1
3984 13:53:59.308319 8, 0x0, sum = 2
3985 13:53:59.308683 9, 0x0, sum = 3
3986 13:53:59.311439 10, 0x0, sum = 4
3987 13:53:59.312003 best_step = 8
3988 13:53:59.312365
3989 13:53:59.312700 ==
3990 13:53:59.314712 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 13:53:59.322694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3992 13:53:59.323260 ==
3993 13:53:59.323623 RX Vref Scan: 1
3994 13:53:59.323954
3995 13:53:59.324631 RX Vref 0 -> 0, step: 1
3996 13:53:59.325026
3997 13:53:59.327863 RX Delay -195 -> 252, step: 8
3998 13:53:59.328410
3999 13:53:59.331363 Set Vref, RX VrefLevel [Byte0]: 53
4000 13:53:59.334823 [Byte1]: 49
4001 13:53:59.335353
4002 13:53:59.339794 Final RX Vref Byte 0 = 53 to rank0
4003 13:53:59.341916 Final RX Vref Byte 1 = 49 to rank0
4004 13:53:59.344870 Final RX Vref Byte 0 = 53 to rank1
4005 13:53:59.347611 Final RX Vref Byte 1 = 49 to rank1==
4006 13:53:59.350990 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 13:53:59.354169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4008 13:53:59.354699 ==
4009 13:53:59.357486 DQS Delay:
4010 13:53:59.357934 DQS0 = 0, DQS1 = 0
4011 13:53:59.361744 DQM Delay:
4012 13:53:59.362191 DQM0 = 40, DQM1 = 30
4013 13:53:59.362543 DQ Delay:
4014 13:53:59.365591 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
4015 13:53:59.367560 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4016 13:53:59.370902 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
4017 13:53:59.374467 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4018 13:53:59.374921
4019 13:53:59.375273
4020 13:53:59.383987 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4021 13:53:59.387761 CH0 RK0: MR19=808, MR18=5050
4022 13:53:59.394634 CH0_RK0: MR19=0x808, MR18=0x5050, DQSOSC=394, MR23=63, INC=168, DEC=112
4023 13:53:59.395153
4024 13:53:59.397179 ----->DramcWriteLeveling(PI) begin...
4025 13:53:59.397637 ==
4026 13:53:59.401754 Dram Type= 6, Freq= 0, CH_0, rank 1
4027 13:53:59.404144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4028 13:53:59.404598 ==
4029 13:53:59.406954 Write leveling (Byte 0): 31 => 31
4030 13:53:59.410542 Write leveling (Byte 1): 29 => 29
4031 13:53:59.414211 DramcWriteLeveling(PI) end<-----
4032 13:53:59.414753
4033 13:53:59.415104 ==
4034 13:53:59.417540 Dram Type= 6, Freq= 0, CH_0, rank 1
4035 13:53:59.421041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4036 13:53:59.421586 ==
4037 13:53:59.424352 [Gating] SW mode calibration
4038 13:53:59.430716 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4039 13:53:59.437416 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4040 13:53:59.440870 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 13:53:59.443726 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 13:53:59.450263 0 5 8 | B1->B0 | 3232 3030 | 1 1 | (0 1) (1 0)
4043 13:53:59.453537 0 5 12 | B1->B0 | 2323 2323 | 1 1 | (1 0) (1 0)
4044 13:53:59.457489 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 13:53:59.463787 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 13:53:59.466770 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 13:53:59.470249 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 13:53:59.476966 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 13:53:59.480516 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 13:53:59.483426 0 6 8 | B1->B0 | 2727 3737 | 0 0 | (0 0) (0 0)
4051 13:53:59.490347 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4052 13:53:59.494487 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 13:53:59.497000 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 13:53:59.503913 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 13:53:59.506661 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 13:53:59.510572 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 13:53:59.516807 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 13:53:59.520002 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4059 13:53:59.523417 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4060 13:53:59.530311 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 13:53:59.532952 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 13:53:59.537326 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 13:53:59.543024 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:53:59.546268 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:53:59.549449 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 13:53:59.556184 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 13:53:59.560341 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 13:53:59.562909 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 13:53:59.570210 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 13:53:59.572913 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:53:59.575811 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:53:59.582999 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:53:59.586313 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 13:53:59.589141 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4075 13:53:59.595608 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 13:53:59.596146 Total UI for P1: 0, mck2ui 16
4077 13:53:59.602495 best dqsien dly found for B0: ( 0, 9, 8)
4078 13:53:59.602946 Total UI for P1: 0, mck2ui 16
4079 13:53:59.609234 best dqsien dly found for B1: ( 0, 9, 8)
4080 13:53:59.612814 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4081 13:53:59.615629 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4082 13:53:59.616263
4083 13:53:59.619693 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4084 13:53:59.622452 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4085 13:53:59.626821 [Gating] SW calibration Done
4086 13:53:59.627372 ==
4087 13:53:59.628758 Dram Type= 6, Freq= 0, CH_0, rank 1
4088 13:53:59.632591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4089 13:53:59.633211 ==
4090 13:53:59.635407 RX Vref Scan: 0
4091 13:53:59.635949
4092 13:53:59.636303 RX Vref 0 -> 0, step: 1
4093 13:53:59.636629
4094 13:53:59.638664 RX Delay -230 -> 252, step: 16
4095 13:53:59.642260 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4096 13:53:59.648652 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4097 13:53:59.652156 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4098 13:53:59.655620 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4099 13:53:59.658543 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4100 13:53:59.665327 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4101 13:53:59.668452 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4102 13:53:59.671416 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4103 13:53:59.674961 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4104 13:53:59.678681 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4105 13:53:59.685534 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4106 13:53:59.688610 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4107 13:53:59.692211 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4108 13:53:59.695562 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4109 13:53:59.701824 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4110 13:53:59.705561 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4111 13:53:59.706113 ==
4112 13:53:59.708676 Dram Type= 6, Freq= 0, CH_0, rank 1
4113 13:53:59.711793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4114 13:53:59.712247 ==
4115 13:53:59.714899 DQS Delay:
4116 13:53:59.715347 DQS0 = 0, DQS1 = 0
4117 13:53:59.719185 DQM Delay:
4118 13:53:59.719753 DQM0 = 40, DQM1 = 34
4119 13:53:59.720110 DQ Delay:
4120 13:53:59.721363 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4121 13:53:59.724889 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4122 13:53:59.728672 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4123 13:53:59.731622 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4124 13:53:59.732165
4125 13:53:59.732559
4126 13:53:59.735041 ==
4127 13:53:59.738476 Dram Type= 6, Freq= 0, CH_0, rank 1
4128 13:53:59.742073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4129 13:53:59.742623 ==
4130 13:53:59.742990
4131 13:53:59.743409
4132 13:53:59.746497 TX Vref Scan disable
4133 13:53:59.747065 == TX Byte 0 ==
4134 13:53:59.751176 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4135 13:53:59.754930 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4136 13:53:59.755488 == TX Byte 1 ==
4137 13:53:59.761046 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4138 13:53:59.765304 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4139 13:53:59.765856 ==
4140 13:53:59.767363 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 13:53:59.770664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4142 13:53:59.771228 ==
4143 13:53:59.771629
4144 13:53:59.771965
4145 13:53:59.774251 TX Vref Scan disable
4146 13:53:59.777595 == TX Byte 0 ==
4147 13:53:59.781171 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4148 13:53:59.784136 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4149 13:53:59.787621 == TX Byte 1 ==
4150 13:53:59.791484 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4151 13:53:59.794125 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4152 13:53:59.794676
4153 13:53:59.798444 [DATLAT]
4154 13:53:59.798889 Freq=600, CH0 RK1
4155 13:53:59.799247
4156 13:53:59.800514 DATLAT Default: 0x8
4157 13:53:59.800988 0, 0xFFFF, sum = 0
4158 13:53:59.803994 1, 0xFFFF, sum = 0
4159 13:53:59.804551 2, 0xFFFF, sum = 0
4160 13:53:59.807037 3, 0xFFFF, sum = 0
4161 13:53:59.807490 4, 0xFFFF, sum = 0
4162 13:53:59.810671 5, 0xFFFF, sum = 0
4163 13:53:59.811128 6, 0xFFFF, sum = 0
4164 13:53:59.814269 7, 0x0, sum = 1
4165 13:53:59.814823 8, 0x0, sum = 2
4166 13:53:59.817602 9, 0x0, sum = 3
4167 13:53:59.818057 10, 0x0, sum = 4
4168 13:53:59.820201 best_step = 8
4169 13:53:59.820648
4170 13:53:59.821073 ==
4171 13:53:59.823919 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 13:53:59.827371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4173 13:53:59.827927 ==
4174 13:53:59.830295 RX Vref Scan: 0
4175 13:53:59.830744
4176 13:53:59.831131 RX Vref 0 -> 0, step: 1
4177 13:53:59.831457
4178 13:53:59.833717 RX Delay -179 -> 252, step: 8
4179 13:53:59.840529 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4180 13:53:59.843836 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4181 13:53:59.847296 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4182 13:53:59.850704 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4183 13:53:59.856963 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4184 13:53:59.860901 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4185 13:53:59.864153 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4186 13:53:59.868088 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4187 13:53:59.873814 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4188 13:53:59.877353 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4189 13:53:59.880580 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4190 13:53:59.883741 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4191 13:53:59.887075 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4192 13:53:59.893797 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4193 13:53:59.896949 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4194 13:53:59.900919 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4195 13:53:59.901369 ==
4196 13:53:59.903367 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 13:53:59.910391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4198 13:53:59.910926 ==
4199 13:53:59.911285 DQS Delay:
4200 13:53:59.911613 DQS0 = 0, DQS1 = 0
4201 13:53:59.913398 DQM Delay:
4202 13:53:59.913849 DQM0 = 41, DQM1 = 32
4203 13:53:59.917203 DQ Delay:
4204 13:53:59.920597 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36
4205 13:53:59.923994 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4206 13:53:59.927091 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4207 13:53:59.930019 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4208 13:53:59.930573
4209 13:53:59.930928
4210 13:53:59.937358 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b6b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4211 13:53:59.940044 CH0 RK1: MR19=808, MR18=6B6B
4212 13:53:59.946678 CH0_RK1: MR19=0x808, MR18=0x6B6B, DQSOSC=389, MR23=63, INC=173, DEC=115
4213 13:53:59.949995 [RxdqsGatingPostProcess] freq 600
4214 13:53:59.953642 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4215 13:53:59.956136 Pre-setting of DQS Precalculation
4216 13:53:59.963070 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4217 13:53:59.963702 ==
4218 13:53:59.966995 Dram Type= 6, Freq= 0, CH_1, rank 0
4219 13:53:59.969801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4220 13:53:59.970274 ==
4221 13:53:59.976847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4222 13:53:59.983041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4223 13:53:59.986870 [CA 0] Center 35 (5~66) winsize 62
4224 13:53:59.989319 [CA 1] Center 35 (5~65) winsize 61
4225 13:53:59.993015 [CA 2] Center 33 (3~64) winsize 62
4226 13:53:59.996682 [CA 3] Center 33 (3~64) winsize 62
4227 13:53:59.999143 [CA 4] Center 33 (2~64) winsize 63
4228 13:54:00.002918 [CA 5] Center 33 (2~64) winsize 63
4229 13:54:00.003445
4230 13:54:00.005785 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4231 13:54:00.006266
4232 13:54:00.009373 [CATrainingPosCal] consider 1 rank data
4233 13:54:00.013048 u2DelayCellTimex100 = 270/100 ps
4234 13:54:00.016061 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4235 13:54:00.019281 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4236 13:54:00.023045 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4237 13:54:00.025856 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4238 13:54:00.029278 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4239 13:54:00.033419 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4240 13:54:00.033973
4241 13:54:00.036509 CA PerBit enable=1, Macro0, CA PI delay=33
4242 13:54:00.039551
4243 13:54:00.040095 [CBTSetCACLKResult] CA Dly = 33
4244 13:54:00.042720 CS Dly: 5 (0~36)
4245 13:54:00.043166 ==
4246 13:54:00.045865 Dram Type= 6, Freq= 0, CH_1, rank 1
4247 13:54:00.049417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4248 13:54:00.049975 ==
4249 13:54:00.055841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4250 13:54:00.062652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4251 13:54:00.066131 [CA 0] Center 35 (4~66) winsize 63
4252 13:54:00.069781 [CA 1] Center 34 (4~65) winsize 62
4253 13:54:00.072434 [CA 2] Center 33 (3~64) winsize 62
4254 13:54:00.075865 [CA 3] Center 33 (3~64) winsize 62
4255 13:54:00.079039 [CA 4] Center 32 (2~63) winsize 62
4256 13:54:00.082446 [CA 5] Center 32 (2~63) winsize 62
4257 13:54:00.083025
4258 13:54:00.086631 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4259 13:54:00.087192
4260 13:54:00.089124 [CATrainingPosCal] consider 2 rank data
4261 13:54:00.092549 u2DelayCellTimex100 = 270/100 ps
4262 13:54:00.096082 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4263 13:54:00.098919 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4264 13:54:00.102523 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4265 13:54:00.105697 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4266 13:54:00.110373 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4267 13:54:00.112391 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4268 13:54:00.115814
4269 13:54:00.118357 CA PerBit enable=1, Macro0, CA PI delay=32
4270 13:54:00.118815
4271 13:54:00.122242 [CBTSetCACLKResult] CA Dly = 32
4272 13:54:00.122804 CS Dly: 4 (0~35)
4273 13:54:00.123171
4274 13:54:00.125519 ----->DramcWriteLeveling(PI) begin...
4275 13:54:00.126081 ==
4276 13:54:00.128994 Dram Type= 6, Freq= 0, CH_1, rank 0
4277 13:54:00.131915 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4278 13:54:00.135557 ==
4279 13:54:00.136015 Write leveling (Byte 0): 29 => 29
4280 13:54:00.138434 Write leveling (Byte 1): 28 => 28
4281 13:54:00.142612 DramcWriteLeveling(PI) end<-----
4282 13:54:00.143184
4283 13:54:00.143552 ==
4284 13:54:00.145174 Dram Type= 6, Freq= 0, CH_1, rank 0
4285 13:54:00.151533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4286 13:54:00.152078 ==
4287 13:54:00.155470 [Gating] SW mode calibration
4288 13:54:00.162408 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4289 13:54:00.164856 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4290 13:54:00.168249 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4291 13:54:00.175750 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4292 13:54:00.178434 0 5 8 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
4293 13:54:00.181976 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 13:54:00.188306 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 13:54:00.192190 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4296 13:54:00.195800 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 13:54:00.202384 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4298 13:54:00.205340 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4299 13:54:00.208703 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4300 13:54:00.216014 0 6 8 | B1->B0 | 3636 4343 | 1 0 | (0 0) (0 0)
4301 13:54:00.218092 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 13:54:00.221416 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 13:54:00.229023 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 13:54:00.231678 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 13:54:00.235176 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 13:54:00.241430 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 13:54:00.244574 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4308 13:54:00.248039 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4309 13:54:00.254314 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 13:54:00.257934 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 13:54:00.261239 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 13:54:00.268060 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 13:54:00.271091 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 13:54:00.274375 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 13:54:00.282584 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 13:54:00.284489 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 13:54:00.288093 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 13:54:00.294160 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 13:54:00.297767 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 13:54:00.301232 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 13:54:00.308571 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 13:54:00.310532 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 13:54:00.314172 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4324 13:54:00.321053 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4325 13:54:00.321610 Total UI for P1: 0, mck2ui 16
4326 13:54:00.327073 best dqsien dly found for B0: ( 0, 9, 4)
4327 13:54:00.331576 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4328 13:54:00.334256 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4329 13:54:00.337166 Total UI for P1: 0, mck2ui 16
4330 13:54:00.341626 best dqsien dly found for B1: ( 0, 9, 10)
4331 13:54:00.344143 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4332 13:54:00.348877 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4333 13:54:00.349449
4334 13:54:00.353700 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4335 13:54:00.356887 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4336 13:54:00.357359 [Gating] SW calibration Done
4337 13:54:00.360921 ==
4338 13:54:00.363970 Dram Type= 6, Freq= 0, CH_1, rank 0
4339 13:54:00.367612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4340 13:54:00.368077 ==
4341 13:54:00.368442 RX Vref Scan: 0
4342 13:54:00.368812
4343 13:54:00.370403 RX Vref 0 -> 0, step: 1
4344 13:54:00.370907
4345 13:54:00.374166 RX Delay -230 -> 252, step: 16
4346 13:54:00.376806 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4347 13:54:00.380208 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4348 13:54:00.386965 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4349 13:54:00.389972 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4350 13:54:00.393453 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4351 13:54:00.397479 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4352 13:54:00.403518 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4353 13:54:00.407486 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4354 13:54:00.409734 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4355 13:54:00.413597 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4356 13:54:00.417301 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4357 13:54:00.423289 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4358 13:54:00.426701 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4359 13:54:00.430290 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4360 13:54:00.433282 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4361 13:54:00.440207 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4362 13:54:00.440661 ==
4363 13:54:00.442929 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 13:54:00.446097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4365 13:54:00.446554 ==
4366 13:54:00.446913 DQS Delay:
4367 13:54:00.449912 DQS0 = 0, DQS1 = 0
4368 13:54:00.450367 DQM Delay:
4369 13:54:00.453798 DQM0 = 39, DQM1 = 32
4370 13:54:00.454249 DQ Delay:
4371 13:54:00.455961 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4372 13:54:00.459427 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4373 13:54:00.463760 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4374 13:54:00.465864 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4375 13:54:00.466419
4376 13:54:00.466822
4377 13:54:00.467357 ==
4378 13:54:00.469274 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 13:54:00.476198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4380 13:54:00.476785 ==
4381 13:54:00.477151
4382 13:54:00.477484
4383 13:54:00.477802 TX Vref Scan disable
4384 13:54:00.479381 == TX Byte 0 ==
4385 13:54:00.483055 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4386 13:54:00.490429 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4387 13:54:00.490977 == TX Byte 1 ==
4388 13:54:00.492570 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4389 13:54:00.500083 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4390 13:54:00.500538 ==
4391 13:54:00.503000 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 13:54:00.505907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4393 13:54:00.506484 ==
4394 13:54:00.506846
4395 13:54:00.507177
4396 13:54:00.509229 TX Vref Scan disable
4397 13:54:00.512292 == TX Byte 0 ==
4398 13:54:00.515926 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4399 13:54:00.519438 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4400 13:54:00.522745 == TX Byte 1 ==
4401 13:54:00.526031 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4402 13:54:00.528879 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4403 13:54:00.529434
4404 13:54:00.529791 [DATLAT]
4405 13:54:00.533017 Freq=600, CH1 RK0
4406 13:54:00.533576
4407 13:54:00.536056 DATLAT Default: 0x9
4408 13:54:00.536609 0, 0xFFFF, sum = 0
4409 13:54:00.538636 1, 0xFFFF, sum = 0
4410 13:54:00.539094 2, 0xFFFF, sum = 0
4411 13:54:00.542446 3, 0xFFFF, sum = 0
4412 13:54:00.543007 4, 0xFFFF, sum = 0
4413 13:54:00.545605 5, 0xFFFF, sum = 0
4414 13:54:00.546173 6, 0xFFFF, sum = 0
4415 13:54:00.549028 7, 0x0, sum = 1
4416 13:54:00.549484 8, 0x0, sum = 2
4417 13:54:00.549853 9, 0x0, sum = 3
4418 13:54:00.552388 10, 0x0, sum = 4
4419 13:54:00.552978 best_step = 8
4420 13:54:00.553333
4421 13:54:00.555556 ==
4422 13:54:00.556008 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 13:54:00.561874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4424 13:54:00.562436 ==
4425 13:54:00.562797 RX Vref Scan: 1
4426 13:54:00.563127
4427 13:54:00.565307 RX Vref 0 -> 0, step: 1
4428 13:54:00.565760
4429 13:54:00.568482 RX Delay -195 -> 252, step: 8
4430 13:54:00.568986
4431 13:54:00.572188 Set Vref, RX VrefLevel [Byte0]: 51
4432 13:54:00.575750 [Byte1]: 50
4433 13:54:00.576202
4434 13:54:00.578980 Final RX Vref Byte 0 = 51 to rank0
4435 13:54:00.581977 Final RX Vref Byte 1 = 50 to rank0
4436 13:54:00.585211 Final RX Vref Byte 0 = 51 to rank1
4437 13:54:00.588849 Final RX Vref Byte 1 = 50 to rank1==
4438 13:54:00.591727 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 13:54:00.595394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4440 13:54:00.595944 ==
4441 13:54:00.598458 DQS Delay:
4442 13:54:00.598910 DQS0 = 0, DQS1 = 0
4443 13:54:00.602301 DQM Delay:
4444 13:54:00.602843 DQM0 = 37, DQM1 = 31
4445 13:54:00.603201 DQ Delay:
4446 13:54:00.605988 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4447 13:54:00.608687 DQ4 =40, DQ5 =44, DQ6 =44, DQ7 =36
4448 13:54:00.611861 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =24
4449 13:54:00.615389 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4450 13:54:00.615935
4451 13:54:00.616292
4452 13:54:00.625174 [DQSOSCAuto] RK0, (LSB)MR18= 0x7676, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4453 13:54:00.628604 CH1 RK0: MR19=808, MR18=7676
4454 13:54:00.635574 CH1_RK0: MR19=0x808, MR18=0x7676, DQSOSC=387, MR23=63, INC=175, DEC=116
4455 13:54:00.636126
4456 13:54:00.638532 ----->DramcWriteLeveling(PI) begin...
4457 13:54:00.639087 ==
4458 13:54:00.642268 Dram Type= 6, Freq= 0, CH_1, rank 1
4459 13:54:00.645070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4460 13:54:00.645628 ==
4461 13:54:00.648684 Write leveling (Byte 0): 27 => 27
4462 13:54:00.651351 Write leveling (Byte 1): 27 => 27
4463 13:54:00.655007 DramcWriteLeveling(PI) end<-----
4464 13:54:00.655492
4465 13:54:00.655855 ==
4466 13:54:00.658501 Dram Type= 6, Freq= 0, CH_1, rank 1
4467 13:54:00.661120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4468 13:54:00.661570 ==
4469 13:54:00.664918 [Gating] SW mode calibration
4470 13:54:00.671314 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4471 13:54:00.678153 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4472 13:54:00.681145 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4473 13:54:00.684540 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4474 13:54:00.691179 0 5 8 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 1)
4475 13:54:00.694931 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 13:54:00.697824 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 13:54:00.704945 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 13:54:00.707856 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 13:54:00.711072 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 13:54:00.717747 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 13:54:00.721207 0 6 4 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
4482 13:54:00.724438 0 6 8 | B1->B0 | 3636 4040 | 0 0 | (1 1) (0 0)
4483 13:54:00.731554 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 13:54:00.734589 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 13:54:00.738130 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 13:54:00.744844 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 13:54:00.747312 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 13:54:00.751740 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4489 13:54:00.757361 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4490 13:54:00.760835 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 13:54:00.764419 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 13:54:00.770979 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 13:54:00.774337 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 13:54:00.777335 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 13:54:00.784157 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 13:54:00.787509 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 13:54:00.790516 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 13:54:00.798919 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 13:54:00.800342 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 13:54:00.804634 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 13:54:00.810521 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 13:54:00.814303 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 13:54:00.817127 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 13:54:00.823649 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:54:00.827364 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4506 13:54:00.830656 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 13:54:00.833418 Total UI for P1: 0, mck2ui 16
4508 13:54:00.836867 best dqsien dly found for B0: ( 0, 9, 4)
4509 13:54:00.840390 Total UI for P1: 0, mck2ui 16
4510 13:54:00.843372 best dqsien dly found for B1: ( 0, 9, 6)
4511 13:54:00.846547 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4512 13:54:00.849775 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4513 13:54:00.850228
4514 13:54:00.853290 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4515 13:54:00.859983 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4516 13:54:00.860436 [Gating] SW calibration Done
4517 13:54:00.860846 ==
4518 13:54:00.863137 Dram Type= 6, Freq= 0, CH_1, rank 1
4519 13:54:00.870254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4520 13:54:00.870710 ==
4521 13:54:00.871067 RX Vref Scan: 0
4522 13:54:00.871396
4523 13:54:00.873494 RX Vref 0 -> 0, step: 1
4524 13:54:00.873942
4525 13:54:00.876941 RX Delay -230 -> 252, step: 16
4526 13:54:00.880463 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4527 13:54:00.883276 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4528 13:54:00.886833 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4529 13:54:00.893706 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4530 13:54:00.896754 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4531 13:54:00.899968 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4532 13:54:00.903500 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4533 13:54:00.910716 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4534 13:54:00.913305 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4535 13:54:00.917159 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4536 13:54:00.919829 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4537 13:54:00.923898 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4538 13:54:00.929967 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4539 13:54:00.933514 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4540 13:54:00.936443 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4541 13:54:00.940398 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4542 13:54:00.943480 ==
4543 13:54:00.946260 Dram Type= 6, Freq= 0, CH_1, rank 1
4544 13:54:00.949789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4545 13:54:00.950440 ==
4546 13:54:00.950827 DQS Delay:
4547 13:54:00.953101 DQS0 = 0, DQS1 = 0
4548 13:54:00.953554 DQM Delay:
4549 13:54:00.956496 DQM0 = 42, DQM1 = 35
4550 13:54:00.956995 DQ Delay:
4551 13:54:00.959515 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4552 13:54:00.963275 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4553 13:54:00.966315 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4554 13:54:00.969697 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4555 13:54:00.970204
4556 13:54:00.970565
4557 13:54:00.970898 ==
4558 13:54:00.972949 Dram Type= 6, Freq= 0, CH_1, rank 1
4559 13:54:00.976554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4560 13:54:00.977240 ==
4561 13:54:00.977609
4562 13:54:00.977939
4563 13:54:00.979721 TX Vref Scan disable
4564 13:54:00.983371 == TX Byte 0 ==
4565 13:54:00.986567 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4566 13:54:00.989473 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4567 13:54:00.993559 == TX Byte 1 ==
4568 13:54:00.996257 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4569 13:54:00.999716 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4570 13:54:01.000301 ==
4571 13:54:01.003169 Dram Type= 6, Freq= 0, CH_1, rank 1
4572 13:54:01.007231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4573 13:54:01.009426 ==
4574 13:54:01.009877
4575 13:54:01.010228
4576 13:54:01.010553 TX Vref Scan disable
4577 13:54:01.014102 == TX Byte 0 ==
4578 13:54:01.017165 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4579 13:54:01.023339 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4580 13:54:01.023898 == TX Byte 1 ==
4581 13:54:01.026814 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4582 13:54:01.033605 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4583 13:54:01.034162
4584 13:54:01.034517 [DATLAT]
4585 13:54:01.034849 Freq=600, CH1 RK1
4586 13:54:01.035167
4587 13:54:01.037241 DATLAT Default: 0x8
4588 13:54:01.037690 0, 0xFFFF, sum = 0
4589 13:54:01.039764 1, 0xFFFF, sum = 0
4590 13:54:01.043481 2, 0xFFFF, sum = 0
4591 13:54:01.044044 3, 0xFFFF, sum = 0
4592 13:54:01.046643 4, 0xFFFF, sum = 0
4593 13:54:01.047102 5, 0xFFFF, sum = 0
4594 13:54:01.050507 6, 0xFFFF, sum = 0
4595 13:54:01.050989 7, 0x0, sum = 1
4596 13:54:01.053220 8, 0x0, sum = 2
4597 13:54:01.053677 9, 0x0, sum = 3
4598 13:54:01.054038 10, 0x0, sum = 4
4599 13:54:01.055993 best_step = 8
4600 13:54:01.056442
4601 13:54:01.056854 ==
4602 13:54:01.059695 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 13:54:01.063149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4604 13:54:01.063707 ==
4605 13:54:01.066670 RX Vref Scan: 0
4606 13:54:01.067123
4607 13:54:01.067650 RX Vref 0 -> 0, step: 1
4608 13:54:01.068017
4609 13:54:01.070872 RX Delay -195 -> 252, step: 8
4610 13:54:01.077135 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4611 13:54:01.080941 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4612 13:54:01.083652 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4613 13:54:01.086992 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4614 13:54:01.094531 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4615 13:54:01.097090 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4616 13:54:01.100373 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4617 13:54:01.103826 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4618 13:54:01.107333 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4619 13:54:01.113652 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4620 13:54:01.117115 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4621 13:54:01.120827 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4622 13:54:01.123644 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4623 13:54:01.130239 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4624 13:54:01.133401 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4625 13:54:01.136622 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4626 13:54:01.137110 ==
4627 13:54:01.140963 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 13:54:01.146787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4629 13:54:01.147391 ==
4630 13:54:01.147767 DQS Delay:
4631 13:54:01.148103 DQS0 = 0, DQS1 = 0
4632 13:54:01.150095 DQM Delay:
4633 13:54:01.150687 DQM0 = 37, DQM1 = 29
4634 13:54:01.152974 DQ Delay:
4635 13:54:01.156632 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4636 13:54:01.159886 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4637 13:54:01.162890 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4638 13:54:01.166655 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4639 13:54:01.167109
4640 13:54:01.167523
4641 13:54:01.173250 [DQSOSCAuto] RK1, (LSB)MR18= 0x6363, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4642 13:54:01.176486 CH1 RK1: MR19=808, MR18=6363
4643 13:54:01.182933 CH1_RK1: MR19=0x808, MR18=0x6363, DQSOSC=391, MR23=63, INC=171, DEC=114
4644 13:54:01.185862 [RxdqsGatingPostProcess] freq 600
4645 13:54:01.189312 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4646 13:54:01.192583 Pre-setting of DQS Precalculation
4647 13:54:01.199606 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4648 13:54:01.206111 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4649 13:54:01.212433 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4650 13:54:01.213034
4651 13:54:01.213395
4652 13:54:01.216661 [Calibration Summary] 1200 Mbps
4653 13:54:01.217160 CH 0, Rank 0
4654 13:54:01.219273 SW Impedance : PASS
4655 13:54:01.222912 DUTY Scan : NO K
4656 13:54:01.223467 ZQ Calibration : PASS
4657 13:54:01.226269 Jitter Meter : NO K
4658 13:54:01.229694 CBT Training : PASS
4659 13:54:01.230251 Write leveling : PASS
4660 13:54:01.232668 RX DQS gating : PASS
4661 13:54:01.236377 RX DQ/DQS(RDDQC) : PASS
4662 13:54:01.236864 TX DQ/DQS : PASS
4663 13:54:01.239612 RX DATLAT : PASS
4664 13:54:01.242474 RX DQ/DQS(Engine): PASS
4665 13:54:01.243026 TX OE : NO K
4666 13:54:01.243389 All Pass.
4667 13:54:01.246047
4668 13:54:01.246494 CH 0, Rank 1
4669 13:54:01.250071 SW Impedance : PASS
4670 13:54:01.250523 DUTY Scan : NO K
4671 13:54:01.252851 ZQ Calibration : PASS
4672 13:54:01.253303 Jitter Meter : NO K
4673 13:54:01.255470 CBT Training : PASS
4674 13:54:01.260106 Write leveling : PASS
4675 13:54:01.260563 RX DQS gating : PASS
4676 13:54:01.262009 RX DQ/DQS(RDDQC) : PASS
4677 13:54:01.266552 TX DQ/DQS : PASS
4678 13:54:01.267003 RX DATLAT : PASS
4679 13:54:01.268952 RX DQ/DQS(Engine): PASS
4680 13:54:01.272470 TX OE : NO K
4681 13:54:01.273033 All Pass.
4682 13:54:01.273438
4683 13:54:01.273774 CH 1, Rank 0
4684 13:54:01.276084 SW Impedance : PASS
4685 13:54:01.279220 DUTY Scan : NO K
4686 13:54:01.279776 ZQ Calibration : PASS
4687 13:54:01.282049 Jitter Meter : NO K
4688 13:54:01.285440 CBT Training : PASS
4689 13:54:01.286004 Write leveling : PASS
4690 13:54:01.288640 RX DQS gating : PASS
4691 13:54:01.292288 RX DQ/DQS(RDDQC) : PASS
4692 13:54:01.292970 TX DQ/DQS : PASS
4693 13:54:01.295804 RX DATLAT : PASS
4694 13:54:01.298895 RX DQ/DQS(Engine): PASS
4695 13:54:01.299448 TX OE : NO K
4696 13:54:01.302539 All Pass.
4697 13:54:01.302989
4698 13:54:01.303343 CH 1, Rank 1
4699 13:54:01.305274 SW Impedance : PASS
4700 13:54:01.305726 DUTY Scan : NO K
4701 13:54:01.308668 ZQ Calibration : PASS
4702 13:54:01.311883 Jitter Meter : NO K
4703 13:54:01.312333 CBT Training : PASS
4704 13:54:01.315311 Write leveling : PASS
4705 13:54:01.315862 RX DQS gating : PASS
4706 13:54:01.319132 RX DQ/DQS(RDDQC) : PASS
4707 13:54:01.322533 TX DQ/DQS : PASS
4708 13:54:01.323065 RX DATLAT : PASS
4709 13:54:01.325534 RX DQ/DQS(Engine): PASS
4710 13:54:01.328972 TX OE : NO K
4711 13:54:01.329529 All Pass.
4712 13:54:01.329885
4713 13:54:01.332160 DramC Write-DBI off
4714 13:54:01.332758 PER_BANK_REFRESH: Hybrid Mode
4715 13:54:01.336329 TX_TRACKING: ON
4716 13:54:01.345486 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4717 13:54:01.348561 [FAST_K] Save calibration result to emmc
4718 13:54:01.353070 dramc_set_vcore_voltage set vcore to 662500
4719 13:54:01.353623 Read voltage for 933, 3
4720 13:54:01.354936 Vio18 = 0
4721 13:54:01.355388 Vcore = 662500
4722 13:54:01.355742 Vdram = 0
4723 13:54:01.359021 Vddq = 0
4724 13:54:01.359472 Vmddr = 0
4725 13:54:01.362082 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4726 13:54:01.368419 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4727 13:54:01.371600 MEM_TYPE=3, freq_sel=17
4728 13:54:01.375633 sv_algorithm_assistance_LP4_1600
4729 13:54:01.377841 ============ PULL DRAM RESETB DOWN ============
4730 13:54:01.381534 ========== PULL DRAM RESETB DOWN end =========
4731 13:54:01.388278 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4732 13:54:01.391535 ===================================
4733 13:54:01.392090 LPDDR4 DRAM CONFIGURATION
4734 13:54:01.395283 ===================================
4735 13:54:01.398226 EX_ROW_EN[0] = 0x0
4736 13:54:01.401338 EX_ROW_EN[1] = 0x0
4737 13:54:01.401894 LP4Y_EN = 0x0
4738 13:54:01.404303 WORK_FSP = 0x0
4739 13:54:01.404786 WL = 0x3
4740 13:54:01.407878 RL = 0x3
4741 13:54:01.408439 BL = 0x2
4742 13:54:01.411408 RPST = 0x0
4743 13:54:01.411858 RD_PRE = 0x0
4744 13:54:01.414931 WR_PRE = 0x1
4745 13:54:01.415486 WR_PST = 0x0
4746 13:54:01.417787 DBI_WR = 0x0
4747 13:54:01.418340 DBI_RD = 0x0
4748 13:54:01.420818 OTF = 0x1
4749 13:54:01.424323 ===================================
4750 13:54:01.428374 ===================================
4751 13:54:01.428978 ANA top config
4752 13:54:01.431068 ===================================
4753 13:54:01.434462 DLL_ASYNC_EN = 0
4754 13:54:01.437409 ALL_SLAVE_EN = 1
4755 13:54:01.441123 NEW_RANK_MODE = 1
4756 13:54:01.441914 DLL_IDLE_MODE = 1
4757 13:54:01.444124 LP45_APHY_COMB_EN = 1
4758 13:54:01.448006 TX_ODT_DIS = 1
4759 13:54:01.451551 NEW_8X_MODE = 1
4760 13:54:01.454233 ===================================
4761 13:54:01.457260 ===================================
4762 13:54:01.457713 data_rate = 1866
4763 13:54:01.461735 CKR = 1
4764 13:54:01.464947 DQ_P2S_RATIO = 8
4765 13:54:01.467355 ===================================
4766 13:54:01.471199 CA_P2S_RATIO = 8
4767 13:54:01.474238 DQ_CA_OPEN = 0
4768 13:54:01.477403 DQ_SEMI_OPEN = 0
4769 13:54:01.477859 CA_SEMI_OPEN = 0
4770 13:54:01.481291 CA_FULL_RATE = 0
4771 13:54:01.484165 DQ_CKDIV4_EN = 1
4772 13:54:01.487362 CA_CKDIV4_EN = 1
4773 13:54:01.491204 CA_PREDIV_EN = 0
4774 13:54:01.493955 PH8_DLY = 0
4775 13:54:01.497332 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4776 13:54:01.497906 DQ_AAMCK_DIV = 4
4777 13:54:01.501099 CA_AAMCK_DIV = 4
4778 13:54:01.504214 CA_ADMCK_DIV = 4
4779 13:54:01.507808 DQ_TRACK_CA_EN = 0
4780 13:54:01.510603 CA_PICK = 933
4781 13:54:01.514106 CA_MCKIO = 933
4782 13:54:01.514660 MCKIO_SEMI = 0
4783 13:54:01.517592 PLL_FREQ = 3732
4784 13:54:01.520826 DQ_UI_PI_RATIO = 32
4785 13:54:01.523760 CA_UI_PI_RATIO = 0
4786 13:54:01.526948 ===================================
4787 13:54:01.530452 ===================================
4788 13:54:01.535028 memory_type:LPDDR4
4789 13:54:01.535581 GP_NUM : 10
4790 13:54:01.537049 SRAM_EN : 1
4791 13:54:01.540102 MD32_EN : 0
4792 13:54:01.543703 ===================================
4793 13:54:01.544266 [ANA_INIT] >>>>>>>>>>>>>>
4794 13:54:01.546627 <<<<<< [CONFIGURE PHASE]: ANA_TX
4795 13:54:01.550086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4796 13:54:01.553628 ===================================
4797 13:54:01.556760 data_rate = 1866,PCW = 0X8f00
4798 13:54:01.560105 ===================================
4799 13:54:01.563236 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4800 13:54:01.569545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4801 13:54:01.573259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4802 13:54:01.581798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4803 13:54:01.583120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4804 13:54:01.586575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4805 13:54:01.589632 [ANA_INIT] flow start
4806 13:54:01.590136 [ANA_INIT] PLL >>>>>>>>
4807 13:54:01.593252 [ANA_INIT] PLL <<<<<<<<
4808 13:54:01.596750 [ANA_INIT] MIDPI >>>>>>>>
4809 13:54:01.597310 [ANA_INIT] MIDPI <<<<<<<<
4810 13:54:01.600353 [ANA_INIT] DLL >>>>>>>>
4811 13:54:01.602963 [ANA_INIT] flow end
4812 13:54:01.606193 ============ LP4 DIFF to SE enter ============
4813 13:54:01.609889 ============ LP4 DIFF to SE exit ============
4814 13:54:01.613181 [ANA_INIT] <<<<<<<<<<<<<
4815 13:54:01.616477 [Flow] Enable top DCM control >>>>>
4816 13:54:01.619542 [Flow] Enable top DCM control <<<<<
4817 13:54:01.623092 Enable DLL master slave shuffle
4818 13:54:01.626686 ==============================================================
4819 13:54:01.629925 Gating Mode config
4820 13:54:01.636395 ==============================================================
4821 13:54:01.637018 Config description:
4822 13:54:01.646109 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4823 13:54:01.653521 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4824 13:54:01.656127 SELPH_MODE 0: By rank 1: By Phase
4825 13:54:01.662969 ==============================================================
4826 13:54:01.665757 GAT_TRACK_EN = 1
4827 13:54:01.669065 RX_GATING_MODE = 2
4828 13:54:01.672342 RX_GATING_TRACK_MODE = 2
4829 13:54:01.676005 SELPH_MODE = 1
4830 13:54:01.678693 PICG_EARLY_EN = 1
4831 13:54:01.682893 VALID_LAT_VALUE = 1
4832 13:54:01.685365 ==============================================================
4833 13:54:01.689037 Enter into Gating configuration >>>>
4834 13:54:01.692843 Exit from Gating configuration <<<<
4835 13:54:01.695636 Enter into DVFS_PRE_config >>>>>
4836 13:54:01.709202 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4837 13:54:01.709767 Exit from DVFS_PRE_config <<<<<
4838 13:54:01.713007 Enter into PICG configuration >>>>
4839 13:54:01.718594 Exit from PICG configuration <<<<
4840 13:54:01.719055 [RX_INPUT] configuration >>>>>
4841 13:54:01.722023 [RX_INPUT] configuration <<<<<
4842 13:54:01.728858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4843 13:54:01.732456 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4844 13:54:01.738573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4845 13:54:01.745832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4846 13:54:01.752142 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4847 13:54:01.758746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4848 13:54:01.762228 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4849 13:54:01.765556 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4850 13:54:01.769470 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4851 13:54:01.775849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4852 13:54:01.778500 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4853 13:54:01.782705 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4854 13:54:01.786131 ===================================
4855 13:54:01.788967 LPDDR4 DRAM CONFIGURATION
4856 13:54:01.792681 ===================================
4857 13:54:01.795360 EX_ROW_EN[0] = 0x0
4858 13:54:01.795913 EX_ROW_EN[1] = 0x0
4859 13:54:01.798367 LP4Y_EN = 0x0
4860 13:54:01.798817 WORK_FSP = 0x0
4861 13:54:01.801687 WL = 0x3
4862 13:54:01.802170 RL = 0x3
4863 13:54:01.805751 BL = 0x2
4864 13:54:01.806310 RPST = 0x0
4865 13:54:01.809048 RD_PRE = 0x0
4866 13:54:01.809603 WR_PRE = 0x1
4867 13:54:01.811965 WR_PST = 0x0
4868 13:54:01.812524 DBI_WR = 0x0
4869 13:54:01.815612 DBI_RD = 0x0
4870 13:54:01.816179 OTF = 0x1
4871 13:54:01.818487 ===================================
4872 13:54:01.822033 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4873 13:54:01.828438 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4874 13:54:01.832485 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4875 13:54:01.834814 ===================================
4876 13:54:01.839142 LPDDR4 DRAM CONFIGURATION
4877 13:54:01.842189 ===================================
4878 13:54:01.842745 EX_ROW_EN[0] = 0x10
4879 13:54:01.845225 EX_ROW_EN[1] = 0x0
4880 13:54:01.848244 LP4Y_EN = 0x0
4881 13:54:01.848862 WORK_FSP = 0x0
4882 13:54:01.851846 WL = 0x3
4883 13:54:01.852478 RL = 0x3
4884 13:54:01.855706 BL = 0x2
4885 13:54:01.856260 RPST = 0x0
4886 13:54:01.858078 RD_PRE = 0x0
4887 13:54:01.858469 WR_PRE = 0x1
4888 13:54:01.861363 WR_PST = 0x0
4889 13:54:01.861818 DBI_WR = 0x0
4890 13:54:01.864932 DBI_RD = 0x0
4891 13:54:01.865381 OTF = 0x1
4892 13:54:01.868319 ===================================
4893 13:54:01.875391 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4894 13:54:01.878937 nWR fixed to 30
4895 13:54:01.882631 [ModeRegInit_LP4] CH0 RK0
4896 13:54:01.883187 [ModeRegInit_LP4] CH0 RK1
4897 13:54:01.886270 [ModeRegInit_LP4] CH1 RK0
4898 13:54:01.889296 [ModeRegInit_LP4] CH1 RK1
4899 13:54:01.889851 match AC timing 8
4900 13:54:01.895962 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4901 13:54:01.898812 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4902 13:54:01.902547 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4903 13:54:01.909095 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4904 13:54:01.912470 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4905 13:54:01.913084 ==
4906 13:54:01.915605 Dram Type= 6, Freq= 0, CH_0, rank 0
4907 13:54:01.918931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4908 13:54:01.919497 ==
4909 13:54:01.925358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4910 13:54:01.932355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4911 13:54:01.935650 [CA 0] Center 38 (8~69) winsize 62
4912 13:54:01.938524 [CA 1] Center 38 (8~69) winsize 62
4913 13:54:01.941786 [CA 2] Center 36 (6~67) winsize 62
4914 13:54:01.945391 [CA 3] Center 36 (6~67) winsize 62
4915 13:54:01.948628 [CA 4] Center 34 (4~65) winsize 62
4916 13:54:01.952428 [CA 5] Center 34 (4~65) winsize 62
4917 13:54:01.953042
4918 13:54:01.955524 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4919 13:54:01.955978
4920 13:54:01.958528 [CATrainingPosCal] consider 1 rank data
4921 13:54:01.962404 u2DelayCellTimex100 = 270/100 ps
4922 13:54:01.965172 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4923 13:54:01.969390 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4924 13:54:01.972039 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4925 13:54:01.974844 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4926 13:54:01.978607 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4927 13:54:01.985624 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4928 13:54:01.986093
4929 13:54:01.988289 CA PerBit enable=1, Macro0, CA PI delay=34
4930 13:54:01.988767
4931 13:54:01.992168 [CBTSetCACLKResult] CA Dly = 34
4932 13:54:01.992764 CS Dly: 7 (0~38)
4933 13:54:01.993137 ==
4934 13:54:01.995989 Dram Type= 6, Freq= 0, CH_0, rank 1
4935 13:54:01.998435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4936 13:54:01.998894 ==
4937 13:54:02.005361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4938 13:54:02.012308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4939 13:54:02.015926 [CA 0] Center 38 (8~69) winsize 62
4940 13:54:02.018952 [CA 1] Center 38 (8~69) winsize 62
4941 13:54:02.022942 [CA 2] Center 36 (6~67) winsize 62
4942 13:54:02.025009 [CA 3] Center 35 (5~66) winsize 62
4943 13:54:02.028750 [CA 4] Center 34 (4~65) winsize 62
4944 13:54:02.032065 [CA 5] Center 34 (4~65) winsize 62
4945 13:54:02.032614
4946 13:54:02.035137 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4947 13:54:02.035691
4948 13:54:02.038476 [CATrainingPosCal] consider 2 rank data
4949 13:54:02.042673 u2DelayCellTimex100 = 270/100 ps
4950 13:54:02.045736 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4951 13:54:02.048443 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4952 13:54:02.052384 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4953 13:54:02.054661 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4954 13:54:02.061437 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4955 13:54:02.064535 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4956 13:54:02.065030
4957 13:54:02.067710 CA PerBit enable=1, Macro0, CA PI delay=34
4958 13:54:02.068195
4959 13:54:02.071507 [CBTSetCACLKResult] CA Dly = 34
4960 13:54:02.072033 CS Dly: 7 (0~39)
4961 13:54:02.072433
4962 13:54:02.076053 ----->DramcWriteLeveling(PI) begin...
4963 13:54:02.076624 ==
4964 13:54:02.078670 Dram Type= 6, Freq= 0, CH_0, rank 0
4965 13:54:02.084801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4966 13:54:02.085260 ==
4967 13:54:02.088202 Write leveling (Byte 0): 31 => 31
4968 13:54:02.091152 Write leveling (Byte 1): 29 => 29
4969 13:54:02.091700 DramcWriteLeveling(PI) end<-----
4970 13:54:02.092063
4971 13:54:02.095068 ==
4972 13:54:02.098045 Dram Type= 6, Freq= 0, CH_0, rank 0
4973 13:54:02.101974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4974 13:54:02.102527 ==
4975 13:54:02.105298 [Gating] SW mode calibration
4976 13:54:02.111159 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4977 13:54:02.116106 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4978 13:54:02.121571 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4979 13:54:02.124484 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4980 13:54:02.127761 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4981 13:54:02.134673 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4982 13:54:02.138141 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4983 13:54:02.141451 0 10 20 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 1)
4984 13:54:02.147356 0 10 24 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (1 0)
4985 13:54:02.150969 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4986 13:54:02.154516 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4987 13:54:02.160618 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4988 13:54:02.164234 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4989 13:54:02.167170 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4990 13:54:02.174922 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4991 13:54:02.177964 0 11 20 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4992 13:54:02.181049 0 11 24 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
4993 13:54:02.187614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4994 13:54:02.190647 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4995 13:54:02.193986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 13:54:02.200612 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4997 13:54:02.204329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4998 13:54:02.207749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4999 13:54:02.214200 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5000 13:54:02.217064 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 13:54:02.221323 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 13:54:02.228288 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 13:54:02.231247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 13:54:02.234473 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 13:54:02.240844 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 13:54:02.243745 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 13:54:02.247361 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 13:54:02.251299 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 13:54:02.256777 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 13:54:02.260950 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 13:54:02.264041 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 13:54:02.270133 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 13:54:02.273613 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 13:54:02.277247 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5015 13:54:02.284533 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5016 13:54:02.287744 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5017 13:54:02.290103 Total UI for P1: 0, mck2ui 16
5018 13:54:02.293565 best dqsien dly found for B1: ( 0, 14, 20)
5019 13:54:02.297260 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5020 13:54:02.300802 Total UI for P1: 0, mck2ui 16
5021 13:54:02.303313 best dqsien dly found for B0: ( 0, 14, 20)
5022 13:54:02.306452 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5023 13:54:02.313503 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5024 13:54:02.313961
5025 13:54:02.316456 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5026 13:54:02.320050 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5027 13:54:02.323164 [Gating] SW calibration Done
5028 13:54:02.323623 ==
5029 13:54:02.326887 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 13:54:02.329504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5031 13:54:02.329961 ==
5032 13:54:02.332818 RX Vref Scan: 0
5033 13:54:02.333290
5034 13:54:02.333648 RX Vref 0 -> 0, step: 1
5035 13:54:02.333981
5036 13:54:02.336996 RX Delay -80 -> 252, step: 8
5037 13:54:02.339636 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5038 13:54:02.343582 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5039 13:54:02.349868 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5040 13:54:02.352757 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5041 13:54:02.356595 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5042 13:54:02.359716 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5043 13:54:02.362977 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5044 13:54:02.369817 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5045 13:54:02.373219 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5046 13:54:02.376203 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5047 13:54:02.379495 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5048 13:54:02.382910 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5049 13:54:02.386305 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5050 13:54:02.392550 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5051 13:54:02.395908 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5052 13:54:02.399356 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5053 13:54:02.399936 ==
5054 13:54:02.402612 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 13:54:02.406583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5056 13:54:02.407146 ==
5057 13:54:02.409459 DQS Delay:
5058 13:54:02.410016 DQS0 = 0, DQS1 = 0
5059 13:54:02.412668 DQM Delay:
5060 13:54:02.413278 DQM0 = 95, DQM1 = 87
5061 13:54:02.413641 DQ Delay:
5062 13:54:02.415999 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5063 13:54:02.420411 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5064 13:54:02.422621 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5065 13:54:02.426012 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5066 13:54:02.426567
5067 13:54:02.426928
5068 13:54:02.429059 ==
5069 13:54:02.432898 Dram Type= 6, Freq= 0, CH_0, rank 0
5070 13:54:02.436964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5071 13:54:02.437527 ==
5072 13:54:02.437886
5073 13:54:02.438216
5074 13:54:02.438897 TX Vref Scan disable
5075 13:54:02.439288 == TX Byte 0 ==
5076 13:54:02.445348 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5077 13:54:02.448936 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5078 13:54:02.449489 == TX Byte 1 ==
5079 13:54:02.455316 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5080 13:54:02.459541 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5081 13:54:02.460105 ==
5082 13:54:02.462448 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 13:54:02.465600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5084 13:54:02.466166 ==
5085 13:54:02.466530
5086 13:54:02.466876
5087 13:54:02.468654 TX Vref Scan disable
5088 13:54:02.471777 == TX Byte 0 ==
5089 13:54:02.475457 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5090 13:54:02.478413 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5091 13:54:02.482609 == TX Byte 1 ==
5092 13:54:02.484928 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5093 13:54:02.488515 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5094 13:54:02.489129
5095 13:54:02.491789 [DATLAT]
5096 13:54:02.492348 Freq=933, CH0 RK0
5097 13:54:02.492752
5098 13:54:02.495560 DATLAT Default: 0xd
5099 13:54:02.496299 0, 0xFFFF, sum = 0
5100 13:54:02.498689 1, 0xFFFF, sum = 0
5101 13:54:02.499260 2, 0xFFFF, sum = 0
5102 13:54:02.501233 3, 0xFFFF, sum = 0
5103 13:54:02.501696 4, 0xFFFF, sum = 0
5104 13:54:02.504906 5, 0xFFFF, sum = 0
5105 13:54:02.505480 6, 0xFFFF, sum = 0
5106 13:54:02.508552 7, 0xFFFF, sum = 0
5107 13:54:02.509164 8, 0xFFFF, sum = 0
5108 13:54:02.511471 9, 0xFFFF, sum = 0
5109 13:54:02.512037 10, 0x0, sum = 1
5110 13:54:02.515105 11, 0x0, sum = 2
5111 13:54:02.515569 12, 0x0, sum = 3
5112 13:54:02.518696 13, 0x0, sum = 4
5113 13:54:02.519266 best_step = 11
5114 13:54:02.519627
5115 13:54:02.519962 ==
5116 13:54:02.521761 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 13:54:02.528881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5118 13:54:02.529444 ==
5119 13:54:02.529811 RX Vref Scan: 1
5120 13:54:02.530151
5121 13:54:02.532554 RX Vref 0 -> 0, step: 1
5122 13:54:02.533154
5123 13:54:02.534575 RX Delay -69 -> 252, step: 4
5124 13:54:02.535029
5125 13:54:02.538158 Set Vref, RX VrefLevel [Byte0]: 53
5126 13:54:02.541545 [Byte1]: 49
5127 13:54:02.542107
5128 13:54:02.544690 Final RX Vref Byte 0 = 53 to rank0
5129 13:54:02.548284 Final RX Vref Byte 1 = 49 to rank0
5130 13:54:02.551657 Final RX Vref Byte 0 = 53 to rank1
5131 13:54:02.554518 Final RX Vref Byte 1 = 49 to rank1==
5132 13:54:02.558234 Dram Type= 6, Freq= 0, CH_0, rank 0
5133 13:54:02.561222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5134 13:54:02.561813 ==
5135 13:54:02.564747 DQS Delay:
5136 13:54:02.565317 DQS0 = 0, DQS1 = 0
5137 13:54:02.568077 DQM Delay:
5138 13:54:02.568544 DQM0 = 97, DQM1 = 87
5139 13:54:02.569060 DQ Delay:
5140 13:54:02.571050 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =94
5141 13:54:02.574893 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5142 13:54:02.577873 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =80
5143 13:54:02.581028 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5144 13:54:02.581497
5145 13:54:02.581968
5146 13:54:02.591586 [DQSOSCAuto] RK0, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5147 13:54:02.594937 CH0 RK0: MR19=505, MR18=2222
5148 13:54:02.600928 CH0_RK0: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5149 13:54:02.601498
5150 13:54:02.604945 ----->DramcWriteLeveling(PI) begin...
5151 13:54:02.605521 ==
5152 13:54:02.607706 Dram Type= 6, Freq= 0, CH_0, rank 1
5153 13:54:02.611039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5154 13:54:02.611614 ==
5155 13:54:02.614442 Write leveling (Byte 0): 25 => 25
5156 13:54:02.618064 Write leveling (Byte 1): 24 => 24
5157 13:54:02.621337 DramcWriteLeveling(PI) end<-----
5158 13:54:02.621911
5159 13:54:02.622401 ==
5160 13:54:02.624629 Dram Type= 6, Freq= 0, CH_0, rank 1
5161 13:54:02.628145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5162 13:54:02.628763 ==
5163 13:54:02.630709 [Gating] SW mode calibration
5164 13:54:02.637331 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5165 13:54:02.645174 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5166 13:54:02.646678 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 13:54:02.653410 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 13:54:02.657277 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 13:54:02.660743 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 13:54:02.664032 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 13:54:02.670019 0 10 20 | B1->B0 | 3131 2c2c | 0 0 | (0 1) (1 0)
5172 13:54:02.673238 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
5173 13:54:02.676643 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 13:54:02.683881 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 13:54:02.686489 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 13:54:02.689919 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 13:54:02.697222 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 13:54:02.700405 0 11 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5179 13:54:02.702980 0 11 20 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
5180 13:54:02.709938 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 13:54:02.713551 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 13:54:02.716197 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 13:54:02.723683 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 13:54:02.727350 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 13:54:02.730283 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 13:54:02.737413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 13:54:02.740290 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5188 13:54:02.743698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5189 13:54:02.750055 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 13:54:02.752624 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 13:54:02.756425 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 13:54:02.762908 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 13:54:02.766535 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 13:54:02.769163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 13:54:02.775898 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 13:54:02.779534 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 13:54:02.783059 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 13:54:02.789138 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 13:54:02.792367 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 13:54:02.795884 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 13:54:02.802805 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 13:54:02.805953 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:54:02.809234 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5204 13:54:02.816177 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 13:54:02.816792 Total UI for P1: 0, mck2ui 16
5206 13:54:02.822992 best dqsien dly found for B0: ( 0, 14, 22)
5207 13:54:02.823560 Total UI for P1: 0, mck2ui 16
5208 13:54:02.828944 best dqsien dly found for B1: ( 0, 14, 20)
5209 13:54:02.832876 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5210 13:54:02.835832 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5211 13:54:02.836396
5212 13:54:02.839298 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5213 13:54:02.842804 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5214 13:54:02.846174 [Gating] SW calibration Done
5215 13:54:02.846737 ==
5216 13:54:02.849148 Dram Type= 6, Freq= 0, CH_0, rank 1
5217 13:54:02.852287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5218 13:54:02.852788 ==
5219 13:54:02.855845 RX Vref Scan: 0
5220 13:54:02.856551
5221 13:54:02.857086 RX Vref 0 -> 0, step: 1
5222 13:54:02.857538
5223 13:54:02.858879 RX Delay -80 -> 252, step: 8
5224 13:54:02.865459 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5225 13:54:02.868776 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5226 13:54:02.872909 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5227 13:54:02.875311 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5228 13:54:02.879254 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5229 13:54:02.881929 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5230 13:54:02.888482 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5231 13:54:02.891737 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5232 13:54:02.895655 iDelay=208, Bit 8, Center 79 (-8 ~ 167) 176
5233 13:54:02.898275 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5234 13:54:02.901728 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5235 13:54:02.905043 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5236 13:54:02.912236 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5237 13:54:02.914857 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5238 13:54:02.918530 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5239 13:54:02.921535 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5240 13:54:02.922069 ==
5241 13:54:02.924816 Dram Type= 6, Freq= 0, CH_0, rank 1
5242 13:54:02.927994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5243 13:54:02.931161 ==
5244 13:54:02.931632 DQS Delay:
5245 13:54:02.932111 DQS0 = 0, DQS1 = 0
5246 13:54:02.934270 DQM Delay:
5247 13:54:02.934735 DQM0 = 96, DQM1 = 87
5248 13:54:02.938601 DQ Delay:
5249 13:54:02.941108 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5250 13:54:02.945169 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5251 13:54:02.948174 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5252 13:54:02.952144 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5253 13:54:02.952756
5254 13:54:02.953243
5255 13:54:02.953695 ==
5256 13:54:02.954497 Dram Type= 6, Freq= 0, CH_0, rank 1
5257 13:54:02.957969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5258 13:54:02.958585 ==
5259 13:54:02.959070
5260 13:54:02.959519
5261 13:54:02.961061 TX Vref Scan disable
5262 13:54:02.961527 == TX Byte 0 ==
5263 13:54:02.968048 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5264 13:54:02.971242 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5265 13:54:02.971740 == TX Byte 1 ==
5266 13:54:02.977576 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5267 13:54:02.981369 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5268 13:54:02.981928 ==
5269 13:54:02.984536 Dram Type= 6, Freq= 0, CH_0, rank 1
5270 13:54:02.987513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5271 13:54:02.988068 ==
5272 13:54:02.988424
5273 13:54:02.991275
5274 13:54:02.991829 TX Vref Scan disable
5275 13:54:02.995435 == TX Byte 0 ==
5276 13:54:02.997880 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5277 13:54:03.001707 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5278 13:54:03.004017 == TX Byte 1 ==
5279 13:54:03.007684 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5280 13:54:03.011224 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5281 13:54:03.011786
5282 13:54:03.014777 [DATLAT]
5283 13:54:03.015333 Freq=933, CH0 RK1
5284 13:54:03.015695
5285 13:54:03.017208 DATLAT Default: 0xb
5286 13:54:03.017660 0, 0xFFFF, sum = 0
5287 13:54:03.021654 1, 0xFFFF, sum = 0
5288 13:54:03.022217 2, 0xFFFF, sum = 0
5289 13:54:03.023699 3, 0xFFFF, sum = 0
5290 13:54:03.024156 4, 0xFFFF, sum = 0
5291 13:54:03.027222 5, 0xFFFF, sum = 0
5292 13:54:03.027679 6, 0xFFFF, sum = 0
5293 13:54:03.031205 7, 0xFFFF, sum = 0
5294 13:54:03.033781 8, 0xFFFF, sum = 0
5295 13:54:03.034344 9, 0xFFFF, sum = 0
5296 13:54:03.037289 10, 0x0, sum = 1
5297 13:54:03.037751 11, 0x0, sum = 2
5298 13:54:03.038114 12, 0x0, sum = 3
5299 13:54:03.040393 13, 0x0, sum = 4
5300 13:54:03.040888 best_step = 11
5301 13:54:03.041251
5302 13:54:03.041584 ==
5303 13:54:03.043861 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 13:54:03.050568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5305 13:54:03.051199 ==
5306 13:54:03.051567 RX Vref Scan: 0
5307 13:54:03.051900
5308 13:54:03.053682 RX Vref 0 -> 0, step: 1
5309 13:54:03.054136
5310 13:54:03.057086 RX Delay -69 -> 252, step: 4
5311 13:54:03.060894 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5312 13:54:03.067149 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5313 13:54:03.070638 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5314 13:54:03.074356 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5315 13:54:03.077097 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5316 13:54:03.080290 iDelay=203, Bit 5, Center 88 (-1 ~ 178) 180
5317 13:54:03.084541 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5318 13:54:03.090425 iDelay=203, Bit 7, Center 106 (11 ~ 202) 192
5319 13:54:03.093335 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5320 13:54:03.096597 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5321 13:54:03.100474 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5322 13:54:03.103796 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5323 13:54:03.110501 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5324 13:54:03.113780 iDelay=203, Bit 13, Center 92 (3 ~ 182) 180
5325 13:54:03.117089 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5326 13:54:03.120861 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5327 13:54:03.121425 ==
5328 13:54:03.123235 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 13:54:03.127071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5330 13:54:03.130396 ==
5331 13:54:03.130949 DQS Delay:
5332 13:54:03.131311 DQS0 = 0, DQS1 = 0
5333 13:54:03.132984 DQM Delay:
5334 13:54:03.133435 DQM0 = 97, DQM1 = 86
5335 13:54:03.136203 DQ Delay:
5336 13:54:03.136657 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5337 13:54:03.140109 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =106
5338 13:54:03.142836 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5339 13:54:03.150940 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5340 13:54:03.151521
5341 13:54:03.151881
5342 13:54:03.156387 [DQSOSCAuto] RK1, (LSB)MR18= 0x3030, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5343 13:54:03.159953 CH0 RK1: MR19=505, MR18=3030
5344 13:54:03.166126 CH0_RK1: MR19=0x505, MR18=0x3030, DQSOSC=406, MR23=63, INC=65, DEC=43
5345 13:54:03.169320 [RxdqsGatingPostProcess] freq 933
5346 13:54:03.172795 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5347 13:54:03.176413 Pre-setting of DQS Precalculation
5348 13:54:03.182500 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5349 13:54:03.182973 ==
5350 13:54:03.185967 Dram Type= 6, Freq= 0, CH_1, rank 0
5351 13:54:03.189660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5352 13:54:03.190233 ==
5353 13:54:03.196259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5354 13:54:03.203442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5355 13:54:03.206395 [CA 0] Center 37 (7~68) winsize 62
5356 13:54:03.209447 [CA 1] Center 37 (6~68) winsize 63
5357 13:54:03.212366 [CA 2] Center 34 (4~65) winsize 62
5358 13:54:03.215962 [CA 3] Center 34 (4~65) winsize 62
5359 13:54:03.219197 [CA 4] Center 33 (3~64) winsize 62
5360 13:54:03.219801 [CA 5] Center 33 (3~64) winsize 62
5361 13:54:03.222828
5362 13:54:03.225430 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5363 13:54:03.225991
5364 13:54:03.229558 [CATrainingPosCal] consider 1 rank data
5365 13:54:03.232056 u2DelayCellTimex100 = 270/100 ps
5366 13:54:03.235445 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5367 13:54:03.239001 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5368 13:54:03.242071 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5369 13:54:03.246000 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5370 13:54:03.249136 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5371 13:54:03.252649 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5372 13:54:03.252945
5373 13:54:03.255413 CA PerBit enable=1, Macro0, CA PI delay=33
5374 13:54:03.255683
5375 13:54:03.258886 [CBTSetCACLKResult] CA Dly = 33
5376 13:54:03.262466 CS Dly: 5 (0~36)
5377 13:54:03.262737 ==
5378 13:54:03.265112 Dram Type= 6, Freq= 0, CH_1, rank 1
5379 13:54:03.268778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5380 13:54:03.269051 ==
5381 13:54:03.275628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5382 13:54:03.281988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5383 13:54:03.286334 [CA 0] Center 37 (7~68) winsize 62
5384 13:54:03.289067 [CA 1] Center 37 (7~68) winsize 62
5385 13:54:03.292126 [CA 2] Center 34 (4~65) winsize 62
5386 13:54:03.295512 [CA 3] Center 34 (4~65) winsize 62
5387 13:54:03.298871 [CA 4] Center 33 (3~64) winsize 62
5388 13:54:03.302621 [CA 5] Center 33 (3~64) winsize 62
5389 13:54:03.303071
5390 13:54:03.305318 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5391 13:54:03.305767
5392 13:54:03.309646 [CATrainingPosCal] consider 2 rank data
5393 13:54:03.311826 u2DelayCellTimex100 = 270/100 ps
5394 13:54:03.315114 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5395 13:54:03.318777 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5396 13:54:03.321971 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5397 13:54:03.325807 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5398 13:54:03.329331 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5399 13:54:03.332602 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5400 13:54:03.333373
5401 13:54:03.338755 CA PerBit enable=1, Macro0, CA PI delay=33
5402 13:54:03.339283
5403 13:54:03.339635 [CBTSetCACLKResult] CA Dly = 33
5404 13:54:03.341620 CS Dly: 5 (0~37)
5405 13:54:03.342164
5406 13:54:03.345300 ----->DramcWriteLeveling(PI) begin...
5407 13:54:03.345847 ==
5408 13:54:03.348423 Dram Type= 6, Freq= 0, CH_1, rank 0
5409 13:54:03.351638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5410 13:54:03.352192 ==
5411 13:54:03.354474 Write leveling (Byte 0): 25 => 25
5412 13:54:03.358012 Write leveling (Byte 1): 26 => 26
5413 13:54:03.362255 DramcWriteLeveling(PI) end<-----
5414 13:54:03.362840
5415 13:54:03.363200 ==
5416 13:54:03.365286 Dram Type= 6, Freq= 0, CH_1, rank 0
5417 13:54:03.371334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5418 13:54:03.372012 ==
5419 13:54:03.372421 [Gating] SW mode calibration
5420 13:54:03.380975 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5421 13:54:03.384268 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5422 13:54:03.391250 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5423 13:54:03.394090 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 13:54:03.397570 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 13:54:03.403154 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5426 13:54:03.407491 0 10 16 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5427 13:54:03.411334 0 10 20 | B1->B0 | 3131 2525 | 1 0 | (1 0) (0 0)
5428 13:54:03.414234 0 10 24 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
5429 13:54:03.420822 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5430 13:54:03.424304 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 13:54:03.428365 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 13:54:03.434449 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 13:54:03.437823 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 13:54:03.441092 0 11 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5435 13:54:03.447923 0 11 20 | B1->B0 | 2e2e 4545 | 0 0 | (0 0) (0 0)
5436 13:54:03.451002 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5437 13:54:03.454324 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 13:54:03.461736 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 13:54:03.464850 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 13:54:03.467268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 13:54:03.473677 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 13:54:03.477387 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5443 13:54:03.480391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5444 13:54:03.486897 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5445 13:54:03.490993 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 13:54:03.494386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 13:54:03.500756 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 13:54:03.503531 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 13:54:03.506878 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 13:54:03.513539 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 13:54:03.517115 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 13:54:03.521649 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 13:54:03.527186 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 13:54:03.530357 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 13:54:03.533777 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 13:54:03.540327 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 13:54:03.543048 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 13:54:03.546421 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5459 13:54:03.550532 Total UI for P1: 0, mck2ui 16
5460 13:54:03.553742 best dqsien dly found for B0: ( 0, 14, 14)
5461 13:54:03.559976 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5462 13:54:03.560429 Total UI for P1: 0, mck2ui 16
5463 13:54:03.566860 best dqsien dly found for B1: ( 0, 14, 16)
5464 13:54:03.569756 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5465 13:54:03.573905 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5466 13:54:03.574505
5467 13:54:03.576511 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5468 13:54:03.579737 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5469 13:54:03.582974 [Gating] SW calibration Done
5470 13:54:03.583428 ==
5471 13:54:03.586405 Dram Type= 6, Freq= 0, CH_1, rank 0
5472 13:54:03.589520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5473 13:54:03.589979 ==
5474 13:54:03.592779 RX Vref Scan: 0
5475 13:54:03.593234
5476 13:54:03.593592 RX Vref 0 -> 0, step: 1
5477 13:54:03.593924
5478 13:54:03.596408 RX Delay -80 -> 252, step: 8
5479 13:54:03.599567 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5480 13:54:03.606365 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5481 13:54:03.609595 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5482 13:54:03.613162 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5483 13:54:03.615978 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5484 13:54:03.619457 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5485 13:54:03.625941 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5486 13:54:03.629656 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5487 13:54:03.632593 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5488 13:54:03.635901 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5489 13:54:03.639268 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5490 13:54:03.646233 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5491 13:54:03.649706 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5492 13:54:03.653613 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5493 13:54:03.657155 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5494 13:54:03.659506 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5495 13:54:03.660059 ==
5496 13:54:03.662952 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 13:54:03.669372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5498 13:54:03.669928 ==
5499 13:54:03.670288 DQS Delay:
5500 13:54:03.670623 DQS0 = 0, DQS1 = 0
5501 13:54:03.671860 DQM Delay:
5502 13:54:03.672313 DQM0 = 95, DQM1 = 88
5503 13:54:03.675466 DQ Delay:
5504 13:54:03.679556 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5505 13:54:03.682352 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =95
5506 13:54:03.685137 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =83
5507 13:54:03.688939 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5508 13:54:03.689496
5509 13:54:03.689857
5510 13:54:03.690190 ==
5511 13:54:03.692704 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 13:54:03.695662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5513 13:54:03.696211 ==
5514 13:54:03.696569
5515 13:54:03.696988
5516 13:54:03.699120 TX Vref Scan disable
5517 13:54:03.699665 == TX Byte 0 ==
5518 13:54:03.705672 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5519 13:54:03.708817 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5520 13:54:03.709272 == TX Byte 1 ==
5521 13:54:03.715720 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5522 13:54:03.718575 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5523 13:54:03.719031 ==
5524 13:54:03.722230 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 13:54:03.726072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5526 13:54:03.726627 ==
5527 13:54:03.726985
5528 13:54:03.729107
5529 13:54:03.729653 TX Vref Scan disable
5530 13:54:03.732375 == TX Byte 0 ==
5531 13:54:03.735197 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5532 13:54:03.738972 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5533 13:54:03.742023 == TX Byte 1 ==
5534 13:54:03.745670 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5535 13:54:03.751897 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5536 13:54:03.752446
5537 13:54:03.752857 [DATLAT]
5538 13:54:03.753205 Freq=933, CH1 RK0
5539 13:54:03.753532
5540 13:54:03.754594 DATLAT Default: 0xd
5541 13:54:03.755049 0, 0xFFFF, sum = 0
5542 13:54:03.758251 1, 0xFFFF, sum = 0
5543 13:54:03.758711 2, 0xFFFF, sum = 0
5544 13:54:03.761857 3, 0xFFFF, sum = 0
5545 13:54:03.765587 4, 0xFFFF, sum = 0
5546 13:54:03.766145 5, 0xFFFF, sum = 0
5547 13:54:03.768112 6, 0xFFFF, sum = 0
5548 13:54:03.768668 7, 0xFFFF, sum = 0
5549 13:54:03.771322 8, 0xFFFF, sum = 0
5550 13:54:03.771872 9, 0xFFFF, sum = 0
5551 13:54:03.774520 10, 0x0, sum = 1
5552 13:54:03.774978 11, 0x0, sum = 2
5553 13:54:03.778250 12, 0x0, sum = 3
5554 13:54:03.778709 13, 0x0, sum = 4
5555 13:54:03.779071 best_step = 11
5556 13:54:03.779401
5557 13:54:03.780906 ==
5558 13:54:03.784589 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 13:54:03.787858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5560 13:54:03.788416 ==
5561 13:54:03.788850 RX Vref Scan: 1
5562 13:54:03.789202
5563 13:54:03.791831 RX Vref 0 -> 0, step: 1
5564 13:54:03.792283
5565 13:54:03.794712 RX Delay -69 -> 252, step: 4
5566 13:54:03.795259
5567 13:54:03.798046 Set Vref, RX VrefLevel [Byte0]: 51
5568 13:54:03.801098 [Byte1]: 50
5569 13:54:03.801585
5570 13:54:03.804236 Final RX Vref Byte 0 = 51 to rank0
5571 13:54:03.808076 Final RX Vref Byte 1 = 50 to rank0
5572 13:54:03.811555 Final RX Vref Byte 0 = 51 to rank1
5573 13:54:03.814772 Final RX Vref Byte 1 = 50 to rank1==
5574 13:54:03.818176 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 13:54:03.824549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5576 13:54:03.825130 ==
5577 13:54:03.825491 DQS Delay:
5578 13:54:03.825826 DQS0 = 0, DQS1 = 0
5579 13:54:03.827804 DQM Delay:
5580 13:54:03.828356 DQM0 = 95, DQM1 = 90
5581 13:54:03.831318 DQ Delay:
5582 13:54:03.834799 DQ0 =100, DQ1 =90, DQ2 =88, DQ3 =92
5583 13:54:03.838108 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =92
5584 13:54:03.841029 DQ8 =74, DQ9 =78, DQ10 =92, DQ11 =82
5585 13:54:03.844532 DQ12 =98, DQ13 =102, DQ14 =98, DQ15 =100
5586 13:54:03.845152
5587 13:54:03.845515
5588 13:54:03.850739 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5589 13:54:03.854647 CH1 RK0: MR19=505, MR18=3434
5590 13:54:03.861420 CH1_RK0: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5591 13:54:03.861970
5592 13:54:03.864265 ----->DramcWriteLeveling(PI) begin...
5593 13:54:03.864858 ==
5594 13:54:03.867920 Dram Type= 6, Freq= 0, CH_1, rank 1
5595 13:54:03.871387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5596 13:54:03.871942 ==
5597 13:54:03.873601 Write leveling (Byte 0): 24 => 24
5598 13:54:03.877115 Write leveling (Byte 1): 24 => 24
5599 13:54:03.880301 DramcWriteLeveling(PI) end<-----
5600 13:54:03.880863
5601 13:54:03.881229 ==
5602 13:54:03.883733 Dram Type= 6, Freq= 0, CH_1, rank 1
5603 13:54:03.887079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5604 13:54:03.891620 ==
5605 13:54:03.892168 [Gating] SW mode calibration
5606 13:54:03.900395 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5607 13:54:03.903521 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5608 13:54:03.907005 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 13:54:03.913420 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 13:54:03.916876 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 13:54:03.920528 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5612 13:54:03.926572 0 10 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
5613 13:54:03.930056 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5614 13:54:03.933418 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 13:54:03.940297 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 13:54:03.943175 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 13:54:03.946818 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 13:54:03.953652 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 13:54:03.956811 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5620 13:54:03.960395 0 11 16 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)
5621 13:54:03.966949 0 11 20 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5622 13:54:03.970466 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 13:54:03.973363 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:54:03.979903 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 13:54:03.983914 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 13:54:03.986721 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 13:54:03.993049 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 13:54:03.999062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5629 13:54:04.000271 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:54:04.003631 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:54:04.009498 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:54:04.013151 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:54:04.016401 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:54:04.023406 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:54:04.026798 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:54:04.029666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:54:04.036558 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 13:54:04.040202 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 13:54:04.043386 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 13:54:04.049714 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 13:54:04.052838 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 13:54:04.056502 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 13:54:04.063160 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 13:54:04.067453 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5645 13:54:04.069774 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5646 13:54:04.073683 Total UI for P1: 0, mck2ui 16
5647 13:54:04.076460 best dqsien dly found for B0: ( 0, 14, 16)
5648 13:54:04.082681 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 13:54:04.083230 Total UI for P1: 0, mck2ui 16
5650 13:54:04.089578 best dqsien dly found for B1: ( 0, 14, 18)
5651 13:54:04.092557 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5652 13:54:04.095635 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5653 13:54:04.096087
5654 13:54:04.098758 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5655 13:54:04.102556 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5656 13:54:04.105597 [Gating] SW calibration Done
5657 13:54:04.106051 ==
5658 13:54:04.109411 Dram Type= 6, Freq= 0, CH_1, rank 1
5659 13:54:04.112791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5660 13:54:04.113342 ==
5661 13:54:04.115853 RX Vref Scan: 0
5662 13:54:04.116390
5663 13:54:04.119067 RX Vref 0 -> 0, step: 1
5664 13:54:04.119616
5665 13:54:04.119976 RX Delay -80 -> 252, step: 8
5666 13:54:04.125627 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5667 13:54:04.128791 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5668 13:54:04.132551 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5669 13:54:04.135514 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5670 13:54:04.138810 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5671 13:54:04.143541 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5672 13:54:04.148804 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5673 13:54:04.152246 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5674 13:54:04.155037 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5675 13:54:04.158615 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5676 13:54:04.162006 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5677 13:54:04.168874 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5678 13:54:04.172351 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5679 13:54:04.174765 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5680 13:54:04.178542 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5681 13:54:04.181420 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5682 13:54:04.181875 ==
5683 13:54:04.185262 Dram Type= 6, Freq= 0, CH_1, rank 1
5684 13:54:04.192155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5685 13:54:04.192746 ==
5686 13:54:04.193132 DQS Delay:
5687 13:54:04.195481 DQS0 = 0, DQS1 = 0
5688 13:54:04.196025 DQM Delay:
5689 13:54:04.196387 DQM0 = 97, DQM1 = 91
5690 13:54:04.198765 DQ Delay:
5691 13:54:04.201789 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =99
5692 13:54:04.205352 DQ4 =99, DQ5 =107, DQ6 =103, DQ7 =95
5693 13:54:04.208579 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5694 13:54:04.212092 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5695 13:54:04.212639
5696 13:54:04.213037
5697 13:54:04.213368 ==
5698 13:54:04.215462 Dram Type= 6, Freq= 0, CH_1, rank 1
5699 13:54:04.218523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5700 13:54:04.219077 ==
5701 13:54:04.219436
5702 13:54:04.219764
5703 13:54:04.221183 TX Vref Scan disable
5704 13:54:04.225090 == TX Byte 0 ==
5705 13:54:04.228301 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5706 13:54:04.231958 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5707 13:54:04.234605 == TX Byte 1 ==
5708 13:54:04.237830 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5709 13:54:04.241102 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5710 13:54:04.241654 ==
5711 13:54:04.244196 Dram Type= 6, Freq= 0, CH_1, rank 1
5712 13:54:04.248128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5713 13:54:04.251716 ==
5714 13:54:04.252270
5715 13:54:04.252624
5716 13:54:04.252999 TX Vref Scan disable
5717 13:54:04.255043 == TX Byte 0 ==
5718 13:54:04.257870 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5719 13:54:04.261823 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5720 13:54:04.265381 == TX Byte 1 ==
5721 13:54:04.268386 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5722 13:54:04.274766 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5723 13:54:04.275304
5724 13:54:04.275696 [DATLAT]
5725 13:54:04.276056 Freq=933, CH1 RK1
5726 13:54:04.276383
5727 13:54:04.278193 DATLAT Default: 0xb
5728 13:54:04.278643 0, 0xFFFF, sum = 0
5729 13:54:04.280957 1, 0xFFFF, sum = 0
5730 13:54:04.281489 2, 0xFFFF, sum = 0
5731 13:54:04.284868 3, 0xFFFF, sum = 0
5732 13:54:04.287998 4, 0xFFFF, sum = 0
5733 13:54:04.288461 5, 0xFFFF, sum = 0
5734 13:54:04.291417 6, 0xFFFF, sum = 0
5735 13:54:04.291969 7, 0xFFFF, sum = 0
5736 13:54:04.295554 8, 0xFFFF, sum = 0
5737 13:54:04.296130 9, 0xFFFF, sum = 0
5738 13:54:04.297587 10, 0x0, sum = 1
5739 13:54:04.298044 11, 0x0, sum = 2
5740 13:54:04.301713 12, 0x0, sum = 3
5741 13:54:04.302266 13, 0x0, sum = 4
5742 13:54:04.302628 best_step = 11
5743 13:54:04.302962
5744 13:54:04.305119 ==
5745 13:54:04.307951 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 13:54:04.311291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5747 13:54:04.311843 ==
5748 13:54:04.312206 RX Vref Scan: 0
5749 13:54:04.312543
5750 13:54:04.315216 RX Vref 0 -> 0, step: 1
5751 13:54:04.315768
5752 13:54:04.319242 RX Delay -61 -> 252, step: 4
5753 13:54:04.321427 iDelay=203, Bit 0, Center 98 (11 ~ 186) 176
5754 13:54:04.327945 iDelay=203, Bit 1, Center 92 (3 ~ 182) 180
5755 13:54:04.331504 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5756 13:54:04.334360 iDelay=203, Bit 3, Center 94 (7 ~ 182) 176
5757 13:54:04.337678 iDelay=203, Bit 4, Center 98 (7 ~ 190) 184
5758 13:54:04.341164 iDelay=203, Bit 5, Center 110 (19 ~ 202) 184
5759 13:54:04.344558 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5760 13:54:04.351397 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5761 13:54:04.354970 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5762 13:54:04.359169 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5763 13:54:04.361480 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184
5764 13:54:04.365059 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5765 13:54:04.371061 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5766 13:54:04.374245 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5767 13:54:04.377391 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5768 13:54:04.381550 iDelay=203, Bit 15, Center 98 (11 ~ 186) 176
5769 13:54:04.382140 ==
5770 13:54:04.383960 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 13:54:04.387234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5772 13:54:04.390970 ==
5773 13:54:04.391571 DQS Delay:
5774 13:54:04.391932 DQS0 = 0, DQS1 = 0
5775 13:54:04.394128 DQM Delay:
5776 13:54:04.394578 DQM0 = 98, DQM1 = 89
5777 13:54:04.397726 DQ Delay:
5778 13:54:04.398175 DQ0 =98, DQ1 =92, DQ2 =90, DQ3 =94
5779 13:54:04.400903 DQ4 =98, DQ5 =110, DQ6 =106, DQ7 =96
5780 13:54:04.403787 DQ8 =76, DQ9 =78, DQ10 =90, DQ11 =82
5781 13:54:04.411007 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5782 13:54:04.411568
5783 13:54:04.412046
5784 13:54:04.417605 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5785 13:54:04.421103 CH1 RK1: MR19=505, MR18=2626
5786 13:54:04.428197 CH1_RK1: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5787 13:54:04.430520 [RxdqsGatingPostProcess] freq 933
5788 13:54:04.434781 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5789 13:54:04.438142 Pre-setting of DQS Precalculation
5790 13:54:04.443880 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5791 13:54:04.450813 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5792 13:54:04.457701 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5793 13:54:04.458254
5794 13:54:04.458606
5795 13:54:04.460287 [Calibration Summary] 1866 Mbps
5796 13:54:04.460782 CH 0, Rank 0
5797 13:54:04.464325 SW Impedance : PASS
5798 13:54:04.467422 DUTY Scan : NO K
5799 13:54:04.467869 ZQ Calibration : PASS
5800 13:54:04.471667 Jitter Meter : NO K
5801 13:54:04.473535 CBT Training : PASS
5802 13:54:04.473995 Write leveling : PASS
5803 13:54:04.476582 RX DQS gating : PASS
5804 13:54:04.480068 RX DQ/DQS(RDDQC) : PASS
5805 13:54:04.480896 TX DQ/DQS : PASS
5806 13:54:04.483587 RX DATLAT : PASS
5807 13:54:04.486377 RX DQ/DQS(Engine): PASS
5808 13:54:04.486830 TX OE : NO K
5809 13:54:04.487189 All Pass.
5810 13:54:04.490338
5811 13:54:04.490788 CH 0, Rank 1
5812 13:54:04.493137 SW Impedance : PASS
5813 13:54:04.493590 DUTY Scan : NO K
5814 13:54:04.496646 ZQ Calibration : PASS
5815 13:54:04.497131 Jitter Meter : NO K
5816 13:54:04.501184 CBT Training : PASS
5817 13:54:04.503723 Write leveling : PASS
5818 13:54:04.504174 RX DQS gating : PASS
5819 13:54:04.506567 RX DQ/DQS(RDDQC) : PASS
5820 13:54:04.510230 TX DQ/DQS : PASS
5821 13:54:04.510784 RX DATLAT : PASS
5822 13:54:04.513229 RX DQ/DQS(Engine): PASS
5823 13:54:04.516309 TX OE : NO K
5824 13:54:04.516924 All Pass.
5825 13:54:04.517290
5826 13:54:04.517623 CH 1, Rank 0
5827 13:54:04.520217 SW Impedance : PASS
5828 13:54:04.523322 DUTY Scan : NO K
5829 13:54:04.523875 ZQ Calibration : PASS
5830 13:54:04.526174 Jitter Meter : NO K
5831 13:54:04.530365 CBT Training : PASS
5832 13:54:04.530939 Write leveling : PASS
5833 13:54:04.533069 RX DQS gating : PASS
5834 13:54:04.536258 RX DQ/DQS(RDDQC) : PASS
5835 13:54:04.536843 TX DQ/DQS : PASS
5836 13:54:04.540240 RX DATLAT : PASS
5837 13:54:04.543814 RX DQ/DQS(Engine): PASS
5838 13:54:04.544369 TX OE : NO K
5839 13:54:04.547229 All Pass.
5840 13:54:04.547709
5841 13:54:04.548063 CH 1, Rank 1
5842 13:54:04.550002 SW Impedance : PASS
5843 13:54:04.550448 DUTY Scan : NO K
5844 13:54:04.552580 ZQ Calibration : PASS
5845 13:54:04.556191 Jitter Meter : NO K
5846 13:54:04.556777 CBT Training : PASS
5847 13:54:04.559411 Write leveling : PASS
5848 13:54:04.562591 RX DQS gating : PASS
5849 13:54:04.563144 RX DQ/DQS(RDDQC) : PASS
5850 13:54:04.566690 TX DQ/DQS : PASS
5851 13:54:04.569171 RX DATLAT : PASS
5852 13:54:04.569737 RX DQ/DQS(Engine): PASS
5853 13:54:04.573255 TX OE : NO K
5854 13:54:04.573811 All Pass.
5855 13:54:04.574167
5856 13:54:04.575597 DramC Write-DBI off
5857 13:54:04.579173 PER_BANK_REFRESH: Hybrid Mode
5858 13:54:04.579621 TX_TRACKING: ON
5859 13:54:04.588881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5860 13:54:04.592336 [FAST_K] Save calibration result to emmc
5861 13:54:04.595347 dramc_set_vcore_voltage set vcore to 650000
5862 13:54:04.599321 Read voltage for 400, 6
5863 13:54:04.599884 Vio18 = 0
5864 13:54:04.600245 Vcore = 650000
5865 13:54:04.601767 Vdram = 0
5866 13:54:04.602279 Vddq = 0
5867 13:54:04.602647 Vmddr = 0
5868 13:54:04.608765 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5869 13:54:04.612841 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5870 13:54:04.615907 MEM_TYPE=3, freq_sel=20
5871 13:54:04.618766 sv_algorithm_assistance_LP4_800
5872 13:54:04.622080 ============ PULL DRAM RESETB DOWN ============
5873 13:54:04.625860 ========== PULL DRAM RESETB DOWN end =========
5874 13:54:04.632676 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5875 13:54:04.635262 ===================================
5876 13:54:04.635820 LPDDR4 DRAM CONFIGURATION
5877 13:54:04.639304 ===================================
5878 13:54:04.642414 EX_ROW_EN[0] = 0x0
5879 13:54:04.645676 EX_ROW_EN[1] = 0x0
5880 13:54:04.646237 LP4Y_EN = 0x0
5881 13:54:04.648625 WORK_FSP = 0x0
5882 13:54:04.649109 WL = 0x2
5883 13:54:04.651964 RL = 0x2
5884 13:54:04.652522 BL = 0x2
5885 13:54:04.655475 RPST = 0x0
5886 13:54:04.656032 RD_PRE = 0x0
5887 13:54:04.658553 WR_PRE = 0x1
5888 13:54:04.659003 WR_PST = 0x0
5889 13:54:04.661888 DBI_WR = 0x0
5890 13:54:04.662444 DBI_RD = 0x0
5891 13:54:04.665012 OTF = 0x1
5892 13:54:04.668552 ===================================
5893 13:54:04.671846 ===================================
5894 13:54:04.672408 ANA top config
5895 13:54:04.675207 ===================================
5896 13:54:04.678407 DLL_ASYNC_EN = 0
5897 13:54:04.681496 ALL_SLAVE_EN = 1
5898 13:54:04.684941 NEW_RANK_MODE = 1
5899 13:54:04.685496 DLL_IDLE_MODE = 1
5900 13:54:04.688340 LP45_APHY_COMB_EN = 1
5901 13:54:04.691608 TX_ODT_DIS = 1
5902 13:54:04.694604 NEW_8X_MODE = 1
5903 13:54:04.699225 ===================================
5904 13:54:04.701315 ===================================
5905 13:54:04.704879 data_rate = 800
5906 13:54:04.705432 CKR = 1
5907 13:54:04.707752 DQ_P2S_RATIO = 4
5908 13:54:04.711605 ===================================
5909 13:54:04.714711 CA_P2S_RATIO = 4
5910 13:54:04.718399 DQ_CA_OPEN = 0
5911 13:54:04.721788 DQ_SEMI_OPEN = 1
5912 13:54:04.725028 CA_SEMI_OPEN = 1
5913 13:54:04.725581 CA_FULL_RATE = 0
5914 13:54:04.728470 DQ_CKDIV4_EN = 0
5915 13:54:04.731426 CA_CKDIV4_EN = 1
5916 13:54:04.735379 CA_PREDIV_EN = 0
5917 13:54:04.737410 PH8_DLY = 0
5918 13:54:04.741524 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5919 13:54:04.742067 DQ_AAMCK_DIV = 0
5920 13:54:04.744889 CA_AAMCK_DIV = 0
5921 13:54:04.747727 CA_ADMCK_DIV = 4
5922 13:54:04.751361 DQ_TRACK_CA_EN = 0
5923 13:54:04.754882 CA_PICK = 800
5924 13:54:04.757699 CA_MCKIO = 400
5925 13:54:04.760939 MCKIO_SEMI = 400
5926 13:54:04.764306 PLL_FREQ = 3016
5927 13:54:04.764899 DQ_UI_PI_RATIO = 32
5928 13:54:04.768020 CA_UI_PI_RATIO = 32
5929 13:54:04.771760 ===================================
5930 13:54:04.774382 ===================================
5931 13:54:04.777788 memory_type:LPDDR4
5932 13:54:04.780907 GP_NUM : 10
5933 13:54:04.781365 SRAM_EN : 1
5934 13:54:04.784163 MD32_EN : 0
5935 13:54:04.788032 ===================================
5936 13:54:04.791603 [ANA_INIT] >>>>>>>>>>>>>>
5937 13:54:04.792157 <<<<<< [CONFIGURE PHASE]: ANA_TX
5938 13:54:04.794424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5939 13:54:04.797384 ===================================
5940 13:54:04.802316 data_rate = 800,PCW = 0X7400
5941 13:54:04.803640 ===================================
5942 13:54:04.806685 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5943 13:54:04.813439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5944 13:54:04.823826 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5945 13:54:04.831478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5946 13:54:04.833218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5947 13:54:04.837331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5948 13:54:04.839921 [ANA_INIT] flow start
5949 13:54:04.840371 [ANA_INIT] PLL >>>>>>>>
5950 13:54:04.843686 [ANA_INIT] PLL <<<<<<<<
5951 13:54:04.846489 [ANA_INIT] MIDPI >>>>>>>>
5952 13:54:04.847045 [ANA_INIT] MIDPI <<<<<<<<
5953 13:54:04.849823 [ANA_INIT] DLL >>>>>>>>
5954 13:54:04.853132 [ANA_INIT] flow end
5955 13:54:04.856359 ============ LP4 DIFF to SE enter ============
5956 13:54:04.859823 ============ LP4 DIFF to SE exit ============
5957 13:54:04.863094 [ANA_INIT] <<<<<<<<<<<<<
5958 13:54:04.866741 [Flow] Enable top DCM control >>>>>
5959 13:54:04.869779 [Flow] Enable top DCM control <<<<<
5960 13:54:04.872836 Enable DLL master slave shuffle
5961 13:54:04.876668 ==============================================================
5962 13:54:04.879334 Gating Mode config
5963 13:54:04.886198 ==============================================================
5964 13:54:04.886658 Config description:
5965 13:54:04.896265 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5966 13:54:04.902843 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5967 13:54:04.907386 SELPH_MODE 0: By rank 1: By Phase
5968 13:54:04.913235 ==============================================================
5969 13:54:04.916240 GAT_TRACK_EN = 0
5970 13:54:04.919380 RX_GATING_MODE = 2
5971 13:54:04.923172 RX_GATING_TRACK_MODE = 2
5972 13:54:04.925854 SELPH_MODE = 1
5973 13:54:04.929319 PICG_EARLY_EN = 1
5974 13:54:04.933653 VALID_LAT_VALUE = 1
5975 13:54:04.936052 ==============================================================
5976 13:54:04.940166 Enter into Gating configuration >>>>
5977 13:54:04.942696 Exit from Gating configuration <<<<
5978 13:54:04.946013 Enter into DVFS_PRE_config >>>>>
5979 13:54:04.958657 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5980 13:54:04.962367 Exit from DVFS_PRE_config <<<<<
5981 13:54:04.965597 Enter into PICG configuration >>>>
5982 13:54:04.966139 Exit from PICG configuration <<<<
5983 13:54:04.968950 [RX_INPUT] configuration >>>>>
5984 13:54:04.972306 [RX_INPUT] configuration <<<<<
5985 13:54:04.978681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5986 13:54:04.981897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5987 13:54:04.988486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5988 13:54:04.996118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5989 13:54:05.001946 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5990 13:54:05.009065 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5991 13:54:05.012054 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5992 13:54:05.016283 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5993 13:54:05.022599 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5994 13:54:05.024774 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5995 13:54:05.028452 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5996 13:54:05.032225 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5997 13:54:05.035053 ===================================
5998 13:54:05.038893 LPDDR4 DRAM CONFIGURATION
5999 13:54:05.041634 ===================================
6000 13:54:05.045160 EX_ROW_EN[0] = 0x0
6001 13:54:05.045711 EX_ROW_EN[1] = 0x0
6002 13:54:05.048246 LP4Y_EN = 0x0
6003 13:54:05.048833 WORK_FSP = 0x0
6004 13:54:05.051266 WL = 0x2
6005 13:54:05.051820 RL = 0x2
6006 13:54:05.054662 BL = 0x2
6007 13:54:05.055213 RPST = 0x0
6008 13:54:05.058005 RD_PRE = 0x0
6009 13:54:05.062353 WR_PRE = 0x1
6010 13:54:05.062900 WR_PST = 0x0
6011 13:54:05.064686 DBI_WR = 0x0
6012 13:54:05.065299 DBI_RD = 0x0
6013 13:54:05.067878 OTF = 0x1
6014 13:54:05.071766 ===================================
6015 13:54:05.074508 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6016 13:54:05.077380 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6017 13:54:05.081231 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6018 13:54:05.084498 ===================================
6019 13:54:05.087351 LPDDR4 DRAM CONFIGURATION
6020 13:54:05.091433 ===================================
6021 13:54:05.094267 EX_ROW_EN[0] = 0x10
6022 13:54:05.094814 EX_ROW_EN[1] = 0x0
6023 13:54:05.097586 LP4Y_EN = 0x0
6024 13:54:05.098121 WORK_FSP = 0x0
6025 13:54:05.101194 WL = 0x2
6026 13:54:05.101649 RL = 0x2
6027 13:54:05.104113 BL = 0x2
6028 13:54:05.104701 RPST = 0x0
6029 13:54:05.107696 RD_PRE = 0x0
6030 13:54:05.108235 WR_PRE = 0x1
6031 13:54:05.111189 WR_PST = 0x0
6032 13:54:05.114701 DBI_WR = 0x0
6033 13:54:05.115246 DBI_RD = 0x0
6034 13:54:05.117420 OTF = 0x1
6035 13:54:05.120615 ===================================
6036 13:54:05.123977 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6037 13:54:05.129941 nWR fixed to 30
6038 13:54:05.133811 [ModeRegInit_LP4] CH0 RK0
6039 13:54:05.134358 [ModeRegInit_LP4] CH0 RK1
6040 13:54:05.137052 [ModeRegInit_LP4] CH1 RK0
6041 13:54:05.140170 [ModeRegInit_LP4] CH1 RK1
6042 13:54:05.140756 match AC timing 18
6043 13:54:05.146099 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6044 13:54:05.148941 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6045 13:54:05.152594 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6046 13:54:05.159046 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6047 13:54:05.162802 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6048 13:54:05.163350 ==
6049 13:54:05.165619 Dram Type= 6, Freq= 0, CH_0, rank 0
6050 13:54:05.169182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6051 13:54:05.169730 ==
6052 13:54:05.175504 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6053 13:54:05.182259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6054 13:54:05.185554 [CA 0] Center 36 (8~64) winsize 57
6055 13:54:05.188678 [CA 1] Center 36 (8~64) winsize 57
6056 13:54:05.192104 [CA 2] Center 36 (8~64) winsize 57
6057 13:54:05.195416 [CA 3] Center 36 (8~64) winsize 57
6058 13:54:05.195973 [CA 4] Center 36 (8~64) winsize 57
6059 13:54:05.198684 [CA 5] Center 36 (8~64) winsize 57
6060 13:54:05.199140
6061 13:54:05.205269 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6062 13:54:05.205821
6063 13:54:05.208880 [CATrainingPosCal] consider 1 rank data
6064 13:54:05.211857 u2DelayCellTimex100 = 270/100 ps
6065 13:54:05.215434 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 13:54:05.219111 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6067 13:54:05.222586 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6068 13:54:05.225627 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 13:54:05.228793 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 13:54:05.231937 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 13:54:05.232488
6072 13:54:05.235456 CA PerBit enable=1, Macro0, CA PI delay=36
6073 13:54:05.236001
6074 13:54:05.238328 [CBTSetCACLKResult] CA Dly = 36
6075 13:54:05.241786 CS Dly: 1 (0~32)
6076 13:54:05.242332 ==
6077 13:54:05.245576 Dram Type= 6, Freq= 0, CH_0, rank 1
6078 13:54:05.248580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6079 13:54:05.249176 ==
6080 13:54:05.256830 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6081 13:54:05.261644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6082 13:54:05.265485 [CA 0] Center 36 (8~64) winsize 57
6083 13:54:05.266039 [CA 1] Center 36 (8~64) winsize 57
6084 13:54:05.268747 [CA 2] Center 36 (8~64) winsize 57
6085 13:54:05.271712 [CA 3] Center 36 (8~64) winsize 57
6086 13:54:05.274977 [CA 4] Center 36 (8~64) winsize 57
6087 13:54:05.278954 [CA 5] Center 36 (8~64) winsize 57
6088 13:54:05.279501
6089 13:54:05.281456 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6090 13:54:05.281915
6091 13:54:05.288265 [CATrainingPosCal] consider 2 rank data
6092 13:54:05.288855 u2DelayCellTimex100 = 270/100 ps
6093 13:54:05.294975 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6094 13:54:05.298217 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6095 13:54:05.301160 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6096 13:54:05.304703 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6097 13:54:05.308083 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 13:54:05.311203 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 13:54:05.311657
6100 13:54:05.314474 CA PerBit enable=1, Macro0, CA PI delay=36
6101 13:54:05.315026
6102 13:54:05.318173 [CBTSetCACLKResult] CA Dly = 36
6103 13:54:05.321524 CS Dly: 1 (0~32)
6104 13:54:05.322074
6105 13:54:05.324971 ----->DramcWriteLeveling(PI) begin...
6106 13:54:05.325549 ==
6107 13:54:05.328013 Dram Type= 6, Freq= 0, CH_0, rank 0
6108 13:54:05.331257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6109 13:54:05.331814 ==
6110 13:54:05.334756 Write leveling (Byte 0): 32 => 0
6111 13:54:05.337844 Write leveling (Byte 1): 32 => 0
6112 13:54:05.340906 DramcWriteLeveling(PI) end<-----
6113 13:54:05.341361
6114 13:54:05.341720 ==
6115 13:54:05.344894 Dram Type= 6, Freq= 0, CH_0, rank 0
6116 13:54:05.347617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6117 13:54:05.348169 ==
6118 13:54:05.350986 [Gating] SW mode calibration
6119 13:54:05.357907 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6120 13:54:05.366225 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6121 13:54:05.368364 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6122 13:54:05.370602 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6123 13:54:05.377172 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6124 13:54:05.381147 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6125 13:54:05.384137 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6126 13:54:05.390759 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6127 13:54:05.393888 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6128 13:54:05.397547 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6129 13:54:05.404154 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6130 13:54:05.404745 Total UI for P1: 0, mck2ui 16
6131 13:54:05.410531 best dqsien dly found for B0: ( 0, 10, 16)
6132 13:54:05.411064 Total UI for P1: 0, mck2ui 16
6133 13:54:05.417346 best dqsien dly found for B1: ( 0, 10, 16)
6134 13:54:05.420497 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6135 13:54:05.423699 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6136 13:54:05.424262
6137 13:54:05.427258 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6138 13:54:05.430355 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6139 13:54:05.433556 [Gating] SW calibration Done
6140 13:54:05.434104 ==
6141 13:54:05.436737 Dram Type= 6, Freq= 0, CH_0, rank 0
6142 13:54:05.440839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6143 13:54:05.441402 ==
6144 13:54:05.444204 RX Vref Scan: 0
6145 13:54:05.444970
6146 13:54:05.445460 RX Vref 0 -> 0, step: 1
6147 13:54:05.445808
6148 13:54:05.447079 RX Delay -410 -> 252, step: 16
6149 13:54:05.454332 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6150 13:54:05.456944 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6151 13:54:05.460421 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6152 13:54:05.463347 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6153 13:54:05.471044 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6154 13:54:05.474276 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6155 13:54:05.477340 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6156 13:54:05.480331 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6157 13:54:05.487148 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6158 13:54:05.490336 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6159 13:54:05.494193 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6160 13:54:05.496829 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6161 13:54:05.503423 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6162 13:54:05.506860 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6163 13:54:05.510024 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6164 13:54:05.513410 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6165 13:54:05.516259 ==
6166 13:54:05.519576 Dram Type= 6, Freq= 0, CH_0, rank 0
6167 13:54:05.523908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6168 13:54:05.524461 ==
6169 13:54:05.524869 DQS Delay:
6170 13:54:05.526627 DQS0 = 43, DQS1 = 59
6171 13:54:05.527185 DQM Delay:
6172 13:54:05.529849 DQM0 = 7, DQM1 = 13
6173 13:54:05.530403 DQ Delay:
6174 13:54:05.533364 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6175 13:54:05.536822 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6176 13:54:05.539523 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6177 13:54:05.543155 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6178 13:54:05.543707
6179 13:54:05.544065
6180 13:54:05.544397 ==
6181 13:54:05.546220 Dram Type= 6, Freq= 0, CH_0, rank 0
6182 13:54:05.549575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6183 13:54:05.550031 ==
6184 13:54:05.550387
6185 13:54:05.550718
6186 13:54:05.552629 TX Vref Scan disable
6187 13:54:05.553128 == TX Byte 0 ==
6188 13:54:05.560063 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6189 13:54:05.563234 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6190 13:54:05.563809 == TX Byte 1 ==
6191 13:54:05.569886 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6192 13:54:05.572815 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6193 13:54:05.573291 ==
6194 13:54:05.577146 Dram Type= 6, Freq= 0, CH_0, rank 0
6195 13:54:05.579642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6196 13:54:05.580096 ==
6197 13:54:05.580451
6198 13:54:05.580854
6199 13:54:05.582592 TX Vref Scan disable
6200 13:54:05.586298 == TX Byte 0 ==
6201 13:54:05.589396 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6202 13:54:05.593559 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6203 13:54:05.596590 == TX Byte 1 ==
6204 13:54:05.600441 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6205 13:54:05.603081 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6206 13:54:05.603628
6207 13:54:05.603983 [DATLAT]
6208 13:54:05.606749 Freq=400, CH0 RK0
6209 13:54:05.607300
6210 13:54:05.609335 DATLAT Default: 0xf
6211 13:54:05.609784 0, 0xFFFF, sum = 0
6212 13:54:05.612469 1, 0xFFFF, sum = 0
6213 13:54:05.612967 2, 0xFFFF, sum = 0
6214 13:54:05.616661 3, 0xFFFF, sum = 0
6215 13:54:05.617258 4, 0xFFFF, sum = 0
6216 13:54:05.619356 5, 0xFFFF, sum = 0
6217 13:54:05.619942 6, 0xFFFF, sum = 0
6218 13:54:05.623003 7, 0xFFFF, sum = 0
6219 13:54:05.623596 8, 0xFFFF, sum = 0
6220 13:54:05.625942 9, 0xFFFF, sum = 0
6221 13:54:05.626498 10, 0xFFFF, sum = 0
6222 13:54:05.629655 11, 0xFFFF, sum = 0
6223 13:54:05.630211 12, 0x0, sum = 1
6224 13:54:05.632486 13, 0x0, sum = 2
6225 13:54:05.633093 14, 0x0, sum = 3
6226 13:54:05.636688 15, 0x0, sum = 4
6227 13:54:05.637294 best_step = 13
6228 13:54:05.637652
6229 13:54:05.637983 ==
6230 13:54:05.639961 Dram Type= 6, Freq= 0, CH_0, rank 0
6231 13:54:05.643009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6232 13:54:05.646150 ==
6233 13:54:05.646600 RX Vref Scan: 1
6234 13:54:05.646951
6235 13:54:05.649074 RX Vref 0 -> 0, step: 1
6236 13:54:05.649640
6237 13:54:05.652149 RX Delay -359 -> 252, step: 8
6238 13:54:05.652702
6239 13:54:05.655523 Set Vref, RX VrefLevel [Byte0]: 53
6240 13:54:05.658630 [Byte1]: 49
6241 13:54:05.659183
6242 13:54:05.661611 Final RX Vref Byte 0 = 53 to rank0
6243 13:54:05.665511 Final RX Vref Byte 1 = 49 to rank0
6244 13:54:05.668646 Final RX Vref Byte 0 = 53 to rank1
6245 13:54:05.672684 Final RX Vref Byte 1 = 49 to rank1==
6246 13:54:05.675781 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 13:54:05.679931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6248 13:54:05.682655 ==
6249 13:54:05.683384 DQS Delay:
6250 13:54:05.683777 DQS0 = 56, DQS1 = 68
6251 13:54:05.685580 DQM Delay:
6252 13:54:05.686027 DQM0 = 12, DQM1 = 16
6253 13:54:05.689112 DQ Delay:
6254 13:54:05.692646 DQ0 =8, DQ1 =12, DQ2 =12, DQ3 =8
6255 13:54:05.693146 DQ4 =16, DQ5 =0, DQ6 =20, DQ7 =20
6256 13:54:05.695708 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6257 13:54:05.698837 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6258 13:54:05.699388
6259 13:54:05.699744
6260 13:54:05.708339 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a9a, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6261 13:54:05.711716 CH0 RK0: MR19=C0C, MR18=9A9A
6262 13:54:05.719064 CH0_RK0: MR19=0xC0C, MR18=0x9A9A, DQSOSC=390, MR23=63, INC=388, DEC=258
6263 13:54:05.719618 ==
6264 13:54:05.721418 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 13:54:05.725015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6266 13:54:05.725617 ==
6267 13:54:05.728426 [Gating] SW mode calibration
6268 13:54:05.734857 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 13:54:05.741126 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6270 13:54:05.744834 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 13:54:05.747848 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 13:54:05.754903 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 13:54:05.757746 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6274 13:54:05.761294 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 13:54:05.767912 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 13:54:05.771349 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 13:54:05.774690 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6278 13:54:05.781402 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 13:54:05.781954 Total UI for P1: 0, mck2ui 16
6280 13:54:05.784453 best dqsien dly found for B0: ( 0, 10, 16)
6281 13:54:05.787684 Total UI for P1: 0, mck2ui 16
6282 13:54:05.791353 best dqsien dly found for B1: ( 0, 10, 16)
6283 13:54:05.797250 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6284 13:54:05.801144 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6285 13:54:05.801693
6286 13:54:05.804031 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6287 13:54:05.807325 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6288 13:54:05.811043 [Gating] SW calibration Done
6289 13:54:05.811588 ==
6290 13:54:05.813972 Dram Type= 6, Freq= 0, CH_0, rank 1
6291 13:54:05.817484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6292 13:54:05.818036 ==
6293 13:54:05.821059 RX Vref Scan: 0
6294 13:54:05.821609
6295 13:54:05.821961 RX Vref 0 -> 0, step: 1
6296 13:54:05.822289
6297 13:54:05.823720 RX Delay -410 -> 252, step: 16
6298 13:54:05.830834 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6299 13:54:05.834209 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6300 13:54:05.837080 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6301 13:54:05.840759 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6302 13:54:05.847342 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6303 13:54:05.850125 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6304 13:54:05.853477 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6305 13:54:05.857017 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6306 13:54:05.863250 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6307 13:54:05.866306 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6308 13:54:05.870438 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6309 13:54:05.873261 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6310 13:54:05.880173 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6311 13:54:05.884283 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6312 13:54:05.886928 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6313 13:54:05.892941 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6314 13:54:05.893541 ==
6315 13:54:05.896533 Dram Type= 6, Freq= 0, CH_0, rank 1
6316 13:54:05.900331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6317 13:54:05.900937 ==
6318 13:54:05.901306 DQS Delay:
6319 13:54:05.904131 DQS0 = 43, DQS1 = 59
6320 13:54:05.904684 DQM Delay:
6321 13:54:05.907409 DQM0 = 6, DQM1 = 15
6322 13:54:05.907991 DQ Delay:
6323 13:54:05.909636 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6324 13:54:05.913289 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6325 13:54:05.916396 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6326 13:54:05.919945 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6327 13:54:05.920493
6328 13:54:05.920889
6329 13:54:05.921217 ==
6330 13:54:05.922688 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 13:54:05.926740 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6332 13:54:05.927293 ==
6333 13:54:05.927648
6334 13:54:05.927973
6335 13:54:05.929260 TX Vref Scan disable
6336 13:54:05.929707 == TX Byte 0 ==
6337 13:54:05.936376 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6338 13:54:05.939568 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6339 13:54:05.940120 == TX Byte 1 ==
6340 13:54:05.945871 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6341 13:54:05.949373 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6342 13:54:05.949923 ==
6343 13:54:05.952935 Dram Type= 6, Freq= 0, CH_0, rank 1
6344 13:54:05.956382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6345 13:54:05.956995 ==
6346 13:54:05.957421
6347 13:54:05.957755
6348 13:54:05.959413 TX Vref Scan disable
6349 13:54:05.959875 == TX Byte 0 ==
6350 13:54:05.966375 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6351 13:54:05.969463 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6352 13:54:05.969910 == TX Byte 1 ==
6353 13:54:05.975656 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6354 13:54:05.979309 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6355 13:54:05.979764
6356 13:54:05.980122 [DATLAT]
6357 13:54:05.982424 Freq=400, CH0 RK1
6358 13:54:05.982906
6359 13:54:05.983293 DATLAT Default: 0xd
6360 13:54:05.985533 0, 0xFFFF, sum = 0
6361 13:54:05.986008 1, 0xFFFF, sum = 0
6362 13:54:05.989322 2, 0xFFFF, sum = 0
6363 13:54:05.989776 3, 0xFFFF, sum = 0
6364 13:54:05.992303 4, 0xFFFF, sum = 0
6365 13:54:05.992794 5, 0xFFFF, sum = 0
6366 13:54:05.995625 6, 0xFFFF, sum = 0
6367 13:54:05.998602 7, 0xFFFF, sum = 0
6368 13:54:05.999050 8, 0xFFFF, sum = 0
6369 13:54:06.002228 9, 0xFFFF, sum = 0
6370 13:54:06.002680 10, 0xFFFF, sum = 0
6371 13:54:06.005618 11, 0xFFFF, sum = 0
6372 13:54:06.006124 12, 0x0, sum = 1
6373 13:54:06.008542 13, 0x0, sum = 2
6374 13:54:06.009034 14, 0x0, sum = 3
6375 13:54:06.011882 15, 0x0, sum = 4
6376 13:54:06.012539 best_step = 13
6377 13:54:06.013023
6378 13:54:06.013368 ==
6379 13:54:06.015448 Dram Type= 6, Freq= 0, CH_0, rank 1
6380 13:54:06.019076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6381 13:54:06.019698 ==
6382 13:54:06.022282 RX Vref Scan: 0
6383 13:54:06.022728
6384 13:54:06.025597 RX Vref 0 -> 0, step: 1
6385 13:54:06.026142
6386 13:54:06.026494 RX Delay -359 -> 252, step: 8
6387 13:54:06.034735 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6388 13:54:06.037648 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6389 13:54:06.041404 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6390 13:54:06.044162 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6391 13:54:06.051015 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6392 13:54:06.054780 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6393 13:54:06.057358 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6394 13:54:06.060495 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6395 13:54:06.067186 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6396 13:54:06.070396 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6397 13:54:06.074599 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6398 13:54:06.080773 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6399 13:54:06.084070 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6400 13:54:06.087051 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6401 13:54:06.090161 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6402 13:54:06.096677 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6403 13:54:06.097155 ==
6404 13:54:06.100253 Dram Type= 6, Freq= 0, CH_0, rank 1
6405 13:54:06.103725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6406 13:54:06.104295 ==
6407 13:54:06.104648 DQS Delay:
6408 13:54:06.107037 DQS0 = 52, DQS1 = 60
6409 13:54:06.107690 DQM Delay:
6410 13:54:06.109843 DQM0 = 9, DQM1 = 10
6411 13:54:06.110288 DQ Delay:
6412 13:54:06.113334 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6413 13:54:06.116904 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6414 13:54:06.120349 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6415 13:54:06.123700 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6416 13:54:06.124242
6417 13:54:06.124588
6418 13:54:06.129791 [DQSOSCAuto] RK1, (LSB)MR18= 0xcbcb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6419 13:54:06.134041 CH0 RK1: MR19=C0C, MR18=CBCB
6420 13:54:06.141050 CH0_RK1: MR19=0xC0C, MR18=0xCBCB, DQSOSC=384, MR23=63, INC=400, DEC=267
6421 13:54:06.143388 [RxdqsGatingPostProcess] freq 400
6422 13:54:06.151385 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6423 13:54:06.153707 Pre-setting of DQS Precalculation
6424 13:54:06.156894 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6425 13:54:06.157432 ==
6426 13:54:06.159816 Dram Type= 6, Freq= 0, CH_1, rank 0
6427 13:54:06.163057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6428 13:54:06.163510 ==
6429 13:54:06.169676 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6430 13:54:06.176643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6431 13:54:06.180021 [CA 0] Center 36 (8~64) winsize 57
6432 13:54:06.183047 [CA 1] Center 36 (8~64) winsize 57
6433 13:54:06.186374 [CA 2] Center 36 (8~64) winsize 57
6434 13:54:06.189305 [CA 3] Center 36 (8~64) winsize 57
6435 13:54:06.192869 [CA 4] Center 36 (8~64) winsize 57
6436 13:54:06.193429 [CA 5] Center 36 (8~64) winsize 57
6437 13:54:06.195794
6438 13:54:06.199903 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6439 13:54:06.200455
6440 13:54:06.202801 [CATrainingPosCal] consider 1 rank data
6441 13:54:06.206488 u2DelayCellTimex100 = 270/100 ps
6442 13:54:06.209456 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 13:54:06.212642 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6444 13:54:06.216360 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6445 13:54:06.219720 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 13:54:06.223081 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 13:54:06.226317 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 13:54:06.226868
6449 13:54:06.230221 CA PerBit enable=1, Macro0, CA PI delay=36
6450 13:54:06.230670
6451 13:54:06.232602 [CBTSetCACLKResult] CA Dly = 36
6452 13:54:06.236395 CS Dly: 1 (0~32)
6453 13:54:06.236990 ==
6454 13:54:06.239697 Dram Type= 6, Freq= 0, CH_1, rank 1
6455 13:54:06.242640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6456 13:54:06.243188 ==
6457 13:54:06.249744 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6458 13:54:06.256812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6459 13:54:06.259701 [CA 0] Center 36 (8~64) winsize 57
6460 13:54:06.262347 [CA 1] Center 36 (8~64) winsize 57
6461 13:54:06.262845 [CA 2] Center 36 (8~64) winsize 57
6462 13:54:06.265766 [CA 3] Center 36 (8~64) winsize 57
6463 13:54:06.269726 [CA 4] Center 36 (8~64) winsize 57
6464 13:54:06.272189 [CA 5] Center 36 (8~64) winsize 57
6465 13:54:06.272792
6466 13:54:06.275895 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6467 13:54:06.278776
6468 13:54:06.282371 [CATrainingPosCal] consider 2 rank data
6469 13:54:06.282922 u2DelayCellTimex100 = 270/100 ps
6470 13:54:06.289693 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6471 13:54:06.292974 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6472 13:54:06.295488 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6473 13:54:06.299417 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6474 13:54:06.302656 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6475 13:54:06.305285 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6476 13:54:06.305735
6477 13:54:06.309457 CA PerBit enable=1, Macro0, CA PI delay=36
6478 13:54:06.310012
6479 13:54:06.312068 [CBTSetCACLKResult] CA Dly = 36
6480 13:54:06.316214 CS Dly: 1 (0~32)
6481 13:54:06.316825
6482 13:54:06.319754 ----->DramcWriteLeveling(PI) begin...
6483 13:54:06.320309 ==
6484 13:54:06.322512 Dram Type= 6, Freq= 0, CH_1, rank 0
6485 13:54:06.325232 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6486 13:54:06.325687 ==
6487 13:54:06.329377 Write leveling (Byte 0): 32 => 0
6488 13:54:06.332111 Write leveling (Byte 1): 32 => 0
6489 13:54:06.335333 DramcWriteLeveling(PI) end<-----
6490 13:54:06.335878
6491 13:54:06.336234 ==
6492 13:54:06.339174 Dram Type= 6, Freq= 0, CH_1, rank 0
6493 13:54:06.341910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6494 13:54:06.342363 ==
6495 13:54:06.345677 [Gating] SW mode calibration
6496 13:54:06.353441 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 13:54:06.358827 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6498 13:54:06.362513 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 13:54:06.364936 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 13:54:06.372036 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 13:54:06.375171 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6502 13:54:06.378385 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 13:54:06.384800 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 13:54:06.388019 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 13:54:06.391220 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6506 13:54:06.398660 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 13:54:06.399222 Total UI for P1: 0, mck2ui 16
6508 13:54:06.404585 best dqsien dly found for B0: ( 0, 10, 16)
6509 13:54:06.405188 Total UI for P1: 0, mck2ui 16
6510 13:54:06.411861 best dqsien dly found for B1: ( 0, 10, 16)
6511 13:54:06.414773 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6512 13:54:06.417942 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6513 13:54:06.418500
6514 13:54:06.422177 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6515 13:54:06.424442 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6516 13:54:06.428590 [Gating] SW calibration Done
6517 13:54:06.429192 ==
6518 13:54:06.431336 Dram Type= 6, Freq= 0, CH_1, rank 0
6519 13:54:06.434246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6520 13:54:06.434700 ==
6521 13:54:06.438701 RX Vref Scan: 0
6522 13:54:06.439254
6523 13:54:06.439611 RX Vref 0 -> 0, step: 1
6524 13:54:06.442551
6525 13:54:06.443105 RX Delay -410 -> 252, step: 16
6526 13:54:06.447803 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6527 13:54:06.451471 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6528 13:54:06.454812 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6529 13:54:06.457724 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6530 13:54:06.463845 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6531 13:54:06.467854 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6532 13:54:06.470957 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6533 13:54:06.475235 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6534 13:54:06.480898 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6535 13:54:06.484083 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6536 13:54:06.487679 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6537 13:54:06.491538 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6538 13:54:06.497542 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6539 13:54:06.500583 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6540 13:54:06.504190 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6541 13:54:06.510258 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6542 13:54:06.510805 ==
6543 13:54:06.513360 Dram Type= 6, Freq= 0, CH_1, rank 0
6544 13:54:06.517619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6545 13:54:06.518182 ==
6546 13:54:06.518548 DQS Delay:
6547 13:54:06.520137 DQS0 = 43, DQS1 = 59
6548 13:54:06.520593 DQM Delay:
6549 13:54:06.523840 DQM0 = 6, DQM1 = 15
6550 13:54:06.524400 DQ Delay:
6551 13:54:06.526468 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6552 13:54:06.530998 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6553 13:54:06.533984 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6554 13:54:06.538062 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6555 13:54:06.538644
6556 13:54:06.539007
6557 13:54:06.539346 ==
6558 13:54:06.540034 Dram Type= 6, Freq= 0, CH_1, rank 0
6559 13:54:06.544053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6560 13:54:06.544616 ==
6561 13:54:06.545022
6562 13:54:06.545359
6563 13:54:06.546446 TX Vref Scan disable
6564 13:54:06.549985 == TX Byte 0 ==
6565 13:54:06.553454 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6566 13:54:06.557071 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6567 13:54:06.560453 == TX Byte 1 ==
6568 13:54:06.562969 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6569 13:54:06.566863 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6570 13:54:06.567415 ==
6571 13:54:06.569872 Dram Type= 6, Freq= 0, CH_1, rank 0
6572 13:54:06.573046 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6573 13:54:06.576165 ==
6574 13:54:06.576622
6575 13:54:06.577038
6576 13:54:06.577374 TX Vref Scan disable
6577 13:54:06.579218 == TX Byte 0 ==
6578 13:54:06.583234 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6579 13:54:06.586438 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6580 13:54:06.589215 == TX Byte 1 ==
6581 13:54:06.592533 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6582 13:54:06.596269 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6583 13:54:06.596865
6584 13:54:06.599129 [DATLAT]
6585 13:54:06.599625 Freq=400, CH1 RK0
6586 13:54:06.600104
6587 13:54:06.603070 DATLAT Default: 0xf
6588 13:54:06.603850 0, 0xFFFF, sum = 0
6589 13:54:06.606796 1, 0xFFFF, sum = 0
6590 13:54:06.607364 2, 0xFFFF, sum = 0
6591 13:54:06.610260 3, 0xFFFF, sum = 0
6592 13:54:06.610723 4, 0xFFFF, sum = 0
6593 13:54:06.612408 5, 0xFFFF, sum = 0
6594 13:54:06.612904 6, 0xFFFF, sum = 0
6595 13:54:06.616668 7, 0xFFFF, sum = 0
6596 13:54:06.617292 8, 0xFFFF, sum = 0
6597 13:54:06.618915 9, 0xFFFF, sum = 0
6598 13:54:06.622324 10, 0xFFFF, sum = 0
6599 13:54:06.622888 11, 0xFFFF, sum = 0
6600 13:54:06.625579 12, 0x0, sum = 1
6601 13:54:06.626063 13, 0x0, sum = 2
6602 13:54:06.626551 14, 0x0, sum = 3
6603 13:54:06.629640 15, 0x0, sum = 4
6604 13:54:06.630174 best_step = 13
6605 13:54:06.630655
6606 13:54:06.632249 ==
6607 13:54:06.632745 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 13:54:06.639619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6609 13:54:06.640201 ==
6610 13:54:06.640699 RX Vref Scan: 1
6611 13:54:06.641208
6612 13:54:06.642376 RX Vref 0 -> 0, step: 1
6613 13:54:06.642845
6614 13:54:06.646108 RX Delay -359 -> 252, step: 8
6615 13:54:06.646577
6616 13:54:06.649278 Set Vref, RX VrefLevel [Byte0]: 51
6617 13:54:06.652515 [Byte1]: 50
6618 13:54:06.656697
6619 13:54:06.657320 Final RX Vref Byte 0 = 51 to rank0
6620 13:54:06.659642 Final RX Vref Byte 1 = 50 to rank0
6621 13:54:06.662684 Final RX Vref Byte 0 = 51 to rank1
6622 13:54:06.666914 Final RX Vref Byte 1 = 50 to rank1==
6623 13:54:06.668811 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 13:54:06.676470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6625 13:54:06.677105 ==
6626 13:54:06.677599 DQS Delay:
6627 13:54:06.679150 DQS0 = 48, DQS1 = 64
6628 13:54:06.679587 DQM Delay:
6629 13:54:06.680049 DQM0 = 9, DQM1 = 16
6630 13:54:06.682029 DQ Delay:
6631 13:54:06.685786 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6632 13:54:06.686368 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6633 13:54:06.688809 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6634 13:54:06.691992 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6635 13:54:06.692450
6636 13:54:06.695398
6637 13:54:06.704460 [DQSOSCAuto] RK0, (LSB)MR18= 0xd7d7, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6638 13:54:06.706132 CH1 RK0: MR19=C0C, MR18=D7D7
6639 13:54:06.712647 CH1_RK0: MR19=0xC0C, MR18=0xD7D7, DQSOSC=383, MR23=63, INC=402, DEC=268
6640 13:54:06.713282 ==
6641 13:54:06.715396 Dram Type= 6, Freq= 0, CH_1, rank 1
6642 13:54:06.720506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6643 13:54:06.720995 ==
6644 13:54:06.721774 [Gating] SW mode calibration
6645 13:54:06.728396 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6646 13:54:06.735619 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6647 13:54:06.738438 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 13:54:06.741693 0 7 16 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
6649 13:54:06.748621 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 13:54:06.751445 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6651 13:54:06.754779 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 13:54:06.761230 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 13:54:06.764161 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 13:54:06.768540 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6655 13:54:06.772076 Total UI for P1: 0, mck2ui 16
6656 13:54:06.774352 best dqsien dly found for B0: ( 0, 10, 8)
6657 13:54:06.781625 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 13:54:06.782173 Total UI for P1: 0, mck2ui 16
6659 13:54:06.787974 best dqsien dly found for B1: ( 0, 10, 16)
6660 13:54:06.791416 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6661 13:54:06.794130 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6662 13:54:06.794584
6663 13:54:06.798100 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6664 13:54:06.800645 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6665 13:54:06.804193 [Gating] SW calibration Done
6666 13:54:06.804852 ==
6667 13:54:06.807673 Dram Type= 6, Freq= 0, CH_1, rank 1
6668 13:54:06.810950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6669 13:54:06.811515 ==
6670 13:54:06.813585 RX Vref Scan: 0
6671 13:54:06.814041
6672 13:54:06.817226 RX Vref 0 -> 0, step: 1
6673 13:54:06.817683
6674 13:54:06.818041 RX Delay -410 -> 252, step: 16
6675 13:54:06.825849 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6676 13:54:06.827001 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6677 13:54:06.830859 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6678 13:54:06.838389 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6679 13:54:06.840555 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6680 13:54:06.843846 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6681 13:54:06.847193 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6682 13:54:06.850554 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6683 13:54:06.857180 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6684 13:54:06.860224 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6685 13:54:06.864112 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6686 13:54:06.870076 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6687 13:54:06.873339 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6688 13:54:06.876879 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6689 13:54:06.879867 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6690 13:54:06.886912 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6691 13:54:06.887548 ==
6692 13:54:06.890149 Dram Type= 6, Freq= 0, CH_1, rank 1
6693 13:54:06.893052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6694 13:54:06.893513 ==
6695 13:54:06.893868 DQS Delay:
6696 13:54:06.896541 DQS0 = 43, DQS1 = 59
6697 13:54:06.897164 DQM Delay:
6698 13:54:06.900127 DQM0 = 10, DQM1 = 18
6699 13:54:06.900690 DQ Delay:
6700 13:54:06.903393 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6701 13:54:06.906730 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6702 13:54:06.910117 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6703 13:54:06.913548 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6704 13:54:06.914107
6705 13:54:06.914470
6706 13:54:06.914804 ==
6707 13:54:06.917223 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 13:54:06.920212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6709 13:54:06.920813 ==
6710 13:54:06.921182
6711 13:54:06.921514
6712 13:54:06.924106 TX Vref Scan disable
6713 13:54:06.924663 == TX Byte 0 ==
6714 13:54:06.930685 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6715 13:54:06.933568 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6716 13:54:06.934029 == TX Byte 1 ==
6717 13:54:06.940092 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6718 13:54:06.942722 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6719 13:54:06.943182 ==
6720 13:54:06.946426 Dram Type= 6, Freq= 0, CH_1, rank 1
6721 13:54:06.950400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6722 13:54:06.951001 ==
6723 13:54:06.951371
6724 13:54:06.951708
6725 13:54:06.952688 TX Vref Scan disable
6726 13:54:06.955929 == TX Byte 0 ==
6727 13:54:06.959626 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6728 13:54:06.962864 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6729 13:54:06.965659 == TX Byte 1 ==
6730 13:54:06.969360 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6731 13:54:06.972888 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6732 13:54:06.973345
6733 13:54:06.973704 [DATLAT]
6734 13:54:06.976812 Freq=400, CH1 RK1
6735 13:54:06.977369
6736 13:54:06.977728 DATLAT Default: 0xd
6737 13:54:06.979958 0, 0xFFFF, sum = 0
6738 13:54:06.982323 1, 0xFFFF, sum = 0
6739 13:54:06.982784 2, 0xFFFF, sum = 0
6740 13:54:06.985918 3, 0xFFFF, sum = 0
6741 13:54:06.986488 4, 0xFFFF, sum = 0
6742 13:54:06.989512 5, 0xFFFF, sum = 0
6743 13:54:06.989974 6, 0xFFFF, sum = 0
6744 13:54:06.992493 7, 0xFFFF, sum = 0
6745 13:54:06.993011 8, 0xFFFF, sum = 0
6746 13:54:06.996449 9, 0xFFFF, sum = 0
6747 13:54:06.997073 10, 0xFFFF, sum = 0
6748 13:54:06.998990 11, 0xFFFF, sum = 0
6749 13:54:06.999556 12, 0x0, sum = 1
6750 13:54:07.002357 13, 0x0, sum = 2
6751 13:54:07.002928 14, 0x0, sum = 3
6752 13:54:07.006043 15, 0x0, sum = 4
6753 13:54:07.006615 best_step = 13
6754 13:54:07.006979
6755 13:54:07.007310 ==
6756 13:54:07.009564 Dram Type= 6, Freq= 0, CH_1, rank 1
6757 13:54:07.012894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6758 13:54:07.015546 ==
6759 13:54:07.016104 RX Vref Scan: 0
6760 13:54:07.016466
6761 13:54:07.018883 RX Vref 0 -> 0, step: 1
6762 13:54:07.019439
6763 13:54:07.022647 RX Delay -359 -> 252, step: 8
6764 13:54:07.029268 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6765 13:54:07.032015 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6766 13:54:07.035889 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6767 13:54:07.038483 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6768 13:54:07.045496 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6769 13:54:07.048879 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6770 13:54:07.052305 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6771 13:54:07.055786 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6772 13:54:07.062190 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6773 13:54:07.064922 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6774 13:54:07.068849 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6775 13:54:07.072098 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6776 13:54:07.078391 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6777 13:54:07.082193 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6778 13:54:07.085175 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6779 13:54:07.088535 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6780 13:54:07.089043 ==
6781 13:54:07.094576 Dram Type= 6, Freq= 0, CH_1, rank 1
6782 13:54:07.098755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6783 13:54:07.099316 ==
6784 13:54:07.099681 DQS Delay:
6785 13:54:07.101397 DQS0 = 48, DQS1 = 64
6786 13:54:07.101854 DQM Delay:
6787 13:54:07.105044 DQM0 = 9, DQM1 = 15
6788 13:54:07.105500 DQ Delay:
6789 13:54:07.108656 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6790 13:54:07.111081 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6791 13:54:07.114795 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6792 13:54:07.118859 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6793 13:54:07.119420
6794 13:54:07.119784
6795 13:54:07.125693 [DQSOSCAuto] RK1, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6796 13:54:07.128069 CH1 RK1: MR19=C0C, MR18=ADAD
6797 13:54:07.134898 CH1_RK1: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6798 13:54:07.138117 [RxdqsGatingPostProcess] freq 400
6799 13:54:07.141285 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6800 13:54:07.144977 Pre-setting of DQS Precalculation
6801 13:54:07.151747 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6802 13:54:07.158073 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6803 13:54:07.164263 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6804 13:54:07.164863
6805 13:54:07.165230
6806 13:54:07.167336 [Calibration Summary] 800 Mbps
6807 13:54:07.171218 CH 0, Rank 0
6808 13:54:07.171773 SW Impedance : PASS
6809 13:54:07.174859 DUTY Scan : NO K
6810 13:54:07.175425 ZQ Calibration : PASS
6811 13:54:07.177376 Jitter Meter : NO K
6812 13:54:07.180482 CBT Training : PASS
6813 13:54:07.180974 Write leveling : PASS
6814 13:54:07.184360 RX DQS gating : PASS
6815 13:54:07.187519 RX DQ/DQS(RDDQC) : PASS
6816 13:54:07.188005 TX DQ/DQS : PASS
6817 13:54:07.190953 RX DATLAT : PASS
6818 13:54:07.194405 RX DQ/DQS(Engine): PASS
6819 13:54:07.194973 TX OE : NO K
6820 13:54:07.197528 All Pass.
6821 13:54:07.197985
6822 13:54:07.198345 CH 0, Rank 1
6823 13:54:07.201222 SW Impedance : PASS
6824 13:54:07.201680 DUTY Scan : NO K
6825 13:54:07.203931 ZQ Calibration : PASS
6826 13:54:07.207782 Jitter Meter : NO K
6827 13:54:07.208543 CBT Training : PASS
6828 13:54:07.210893 Write leveling : NO K
6829 13:54:07.213534 RX DQS gating : PASS
6830 13:54:07.213993 RX DQ/DQS(RDDQC) : PASS
6831 13:54:07.217017 TX DQ/DQS : PASS
6832 13:54:07.220391 RX DATLAT : PASS
6833 13:54:07.220893 RX DQ/DQS(Engine): PASS
6834 13:54:07.224476 TX OE : NO K
6835 13:54:07.225096 All Pass.
6836 13:54:07.225463
6837 13:54:07.227329 CH 1, Rank 0
6838 13:54:07.227882 SW Impedance : PASS
6839 13:54:07.231198 DUTY Scan : NO K
6840 13:54:07.234257 ZQ Calibration : PASS
6841 13:54:07.234809 Jitter Meter : NO K
6842 13:54:07.237564 CBT Training : PASS
6843 13:54:07.238118 Write leveling : PASS
6844 13:54:07.240840 RX DQS gating : PASS
6845 13:54:07.243965 RX DQ/DQS(RDDQC) : PASS
6846 13:54:07.244522 TX DQ/DQS : PASS
6847 13:54:07.246930 RX DATLAT : PASS
6848 13:54:07.250197 RX DQ/DQS(Engine): PASS
6849 13:54:07.250829 TX OE : NO K
6850 13:54:07.253763 All Pass.
6851 13:54:07.254317
6852 13:54:07.254681 CH 1, Rank 1
6853 13:54:07.256837 SW Impedance : PASS
6854 13:54:07.257398 DUTY Scan : NO K
6855 13:54:07.261084 ZQ Calibration : PASS
6856 13:54:07.264380 Jitter Meter : NO K
6857 13:54:07.264997 CBT Training : PASS
6858 13:54:07.267358 Write leveling : NO K
6859 13:54:07.270468 RX DQS gating : PASS
6860 13:54:07.271023 RX DQ/DQS(RDDQC) : PASS
6861 13:54:07.273536 TX DQ/DQS : PASS
6862 13:54:07.277648 RX DATLAT : PASS
6863 13:54:07.278203 RX DQ/DQS(Engine): PASS
6864 13:54:07.279591 TX OE : NO K
6865 13:54:07.280218 All Pass.
6866 13:54:07.280611
6867 13:54:07.283573 DramC Write-DBI off
6868 13:54:07.287273 PER_BANK_REFRESH: Hybrid Mode
6869 13:54:07.287735 TX_TRACKING: ON
6870 13:54:07.296776 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6871 13:54:07.300008 [FAST_K] Save calibration result to emmc
6872 13:54:07.303454 dramc_set_vcore_voltage set vcore to 725000
6873 13:54:07.306140 Read voltage for 1600, 0
6874 13:54:07.306706 Vio18 = 0
6875 13:54:07.307067 Vcore = 725000
6876 13:54:07.309603 Vdram = 0
6877 13:54:07.310057 Vddq = 0
6878 13:54:07.310414 Vmddr = 0
6879 13:54:07.316249 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6880 13:54:07.319559 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6881 13:54:07.323292 MEM_TYPE=3, freq_sel=13
6882 13:54:07.326169 sv_algorithm_assistance_LP4_3733
6883 13:54:07.329923 ============ PULL DRAM RESETB DOWN ============
6884 13:54:07.333114 ========== PULL DRAM RESETB DOWN end =========
6885 13:54:07.339681 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6886 13:54:07.343663 ===================================
6887 13:54:07.345838 LPDDR4 DRAM CONFIGURATION
6888 13:54:07.349649 ===================================
6889 13:54:07.350207 EX_ROW_EN[0] = 0x0
6890 13:54:07.352443 EX_ROW_EN[1] = 0x0
6891 13:54:07.353059 LP4Y_EN = 0x0
6892 13:54:07.356408 WORK_FSP = 0x1
6893 13:54:07.357025 WL = 0x5
6894 13:54:07.359536 RL = 0x5
6895 13:54:07.360090 BL = 0x2
6896 13:54:07.362530 RPST = 0x0
6897 13:54:07.363083 RD_PRE = 0x0
6898 13:54:07.365907 WR_PRE = 0x1
6899 13:54:07.366362 WR_PST = 0x1
6900 13:54:07.369508 DBI_WR = 0x0
6901 13:54:07.370066 DBI_RD = 0x0
6902 13:54:07.373660 OTF = 0x1
6903 13:54:07.376586 ===================================
6904 13:54:07.378901 ===================================
6905 13:54:07.379358 ANA top config
6906 13:54:07.382234 ===================================
6907 13:54:07.386300 DLL_ASYNC_EN = 0
6908 13:54:07.389325 ALL_SLAVE_EN = 0
6909 13:54:07.392606 NEW_RANK_MODE = 1
6910 13:54:07.393490 DLL_IDLE_MODE = 1
6911 13:54:07.395622 LP45_APHY_COMB_EN = 1
6912 13:54:07.399138 TX_ODT_DIS = 0
6913 13:54:07.403065 NEW_8X_MODE = 1
6914 13:54:07.405982 ===================================
6915 13:54:07.409679 ===================================
6916 13:54:07.412368 data_rate = 3200
6917 13:54:07.415564 CKR = 1
6918 13:54:07.416115 DQ_P2S_RATIO = 8
6919 13:54:07.419081 ===================================
6920 13:54:07.422382 CA_P2S_RATIO = 8
6921 13:54:07.425953 DQ_CA_OPEN = 0
6922 13:54:07.428658 DQ_SEMI_OPEN = 0
6923 13:54:07.433080 CA_SEMI_OPEN = 0
6924 13:54:07.436498 CA_FULL_RATE = 0
6925 13:54:07.437128 DQ_CKDIV4_EN = 0
6926 13:54:07.438584 CA_CKDIV4_EN = 0
6927 13:54:07.442301 CA_PREDIV_EN = 0
6928 13:54:07.445314 PH8_DLY = 12
6929 13:54:07.450133 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6930 13:54:07.452552 DQ_AAMCK_DIV = 4
6931 13:54:07.453150 CA_AAMCK_DIV = 4
6932 13:54:07.455394 CA_ADMCK_DIV = 4
6933 13:54:07.459140 DQ_TRACK_CA_EN = 0
6934 13:54:07.461769 CA_PICK = 1600
6935 13:54:07.465335 CA_MCKIO = 1600
6936 13:54:07.468617 MCKIO_SEMI = 0
6937 13:54:07.471732 PLL_FREQ = 3068
6938 13:54:07.475401 DQ_UI_PI_RATIO = 32
6939 13:54:07.475960 CA_UI_PI_RATIO = 0
6940 13:54:07.479213 ===================================
6941 13:54:07.481440 ===================================
6942 13:54:07.485770 memory_type:LPDDR4
6943 13:54:07.488152 GP_NUM : 10
6944 13:54:07.488647 SRAM_EN : 1
6945 13:54:07.491761 MD32_EN : 0
6946 13:54:07.494751 ===================================
6947 13:54:07.498001 [ANA_INIT] >>>>>>>>>>>>>>
6948 13:54:07.501577 <<<<<< [CONFIGURE PHASE]: ANA_TX
6949 13:54:07.505818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6950 13:54:07.508218 ===================================
6951 13:54:07.508828 data_rate = 3200,PCW = 0X7600
6952 13:54:07.511343 ===================================
6953 13:54:07.515035 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6954 13:54:07.521666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6955 13:54:07.528644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6956 13:54:07.531609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6957 13:54:07.534625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6958 13:54:07.537610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6959 13:54:07.541097 [ANA_INIT] flow start
6960 13:54:07.544967 [ANA_INIT] PLL >>>>>>>>
6961 13:54:07.545519 [ANA_INIT] PLL <<<<<<<<
6962 13:54:07.548350 [ANA_INIT] MIDPI >>>>>>>>
6963 13:54:07.551019 [ANA_INIT] MIDPI <<<<<<<<
6964 13:54:07.551572 [ANA_INIT] DLL >>>>>>>>
6965 13:54:07.554458 [ANA_INIT] DLL <<<<<<<<
6966 13:54:07.557943 [ANA_INIT] flow end
6967 13:54:07.560985 ============ LP4 DIFF to SE enter ============
6968 13:54:07.564306 ============ LP4 DIFF to SE exit ============
6969 13:54:07.567779 [ANA_INIT] <<<<<<<<<<<<<
6970 13:54:07.571187 [Flow] Enable top DCM control >>>>>
6971 13:54:07.574453 [Flow] Enable top DCM control <<<<<
6972 13:54:07.577394 Enable DLL master slave shuffle
6973 13:54:07.580939 ==============================================================
6974 13:54:07.584517 Gating Mode config
6975 13:54:07.590453 ==============================================================
6976 13:54:07.590916 Config description:
6977 13:54:07.600383 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6978 13:54:07.607787 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6979 13:54:07.611062 SELPH_MODE 0: By rank 1: By Phase
6980 13:54:07.616887 ==============================================================
6981 13:54:07.621010 GAT_TRACK_EN = 1
6982 13:54:07.623990 RX_GATING_MODE = 2
6983 13:54:07.627692 RX_GATING_TRACK_MODE = 2
6984 13:54:07.630130 SELPH_MODE = 1
6985 13:54:07.633348 PICG_EARLY_EN = 1
6986 13:54:07.636905 VALID_LAT_VALUE = 1
6987 13:54:07.640205 ==============================================================
6988 13:54:07.643645 Enter into Gating configuration >>>>
6989 13:54:07.647193 Exit from Gating configuration <<<<
6990 13:54:07.651383 Enter into DVFS_PRE_config >>>>>
6991 13:54:07.663247 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6992 13:54:07.666575 Exit from DVFS_PRE_config <<<<<
6993 13:54:07.670522 Enter into PICG configuration >>>>
6994 13:54:07.670993 Exit from PICG configuration <<<<
6995 13:54:07.672982 [RX_INPUT] configuration >>>>>
6996 13:54:07.677055 [RX_INPUT] configuration <<<<<
6997 13:54:07.683034 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6998 13:54:07.686544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6999 13:54:07.692472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7000 13:54:07.699696 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7001 13:54:07.706486 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7002 13:54:07.712846 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7003 13:54:07.717014 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7004 13:54:07.720041 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7005 13:54:07.725938 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7006 13:54:07.731141 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7007 13:54:07.734150 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7008 13:54:07.736102 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7009 13:54:07.739267 ===================================
7010 13:54:07.742387 LPDDR4 DRAM CONFIGURATION
7011 13:54:07.745453 ===================================
7012 13:54:07.749457 EX_ROW_EN[0] = 0x0
7013 13:54:07.750011 EX_ROW_EN[1] = 0x0
7014 13:54:07.753562 LP4Y_EN = 0x0
7015 13:54:07.754115 WORK_FSP = 0x1
7016 13:54:07.756435 WL = 0x5
7017 13:54:07.757069 RL = 0x5
7018 13:54:07.759841 BL = 0x2
7019 13:54:07.760299 RPST = 0x0
7020 13:54:07.763068 RD_PRE = 0x0
7021 13:54:07.763623 WR_PRE = 0x1
7022 13:54:07.765542 WR_PST = 0x1
7023 13:54:07.769061 DBI_WR = 0x0
7024 13:54:07.769615 DBI_RD = 0x0
7025 13:54:07.772400 OTF = 0x1
7026 13:54:07.776368 ===================================
7027 13:54:07.779158 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7028 13:54:07.782655 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7029 13:54:07.785431 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7030 13:54:07.788875 ===================================
7031 13:54:07.792429 LPDDR4 DRAM CONFIGURATION
7032 13:54:07.795168 ===================================
7033 13:54:07.799362 EX_ROW_EN[0] = 0x10
7034 13:54:07.799917 EX_ROW_EN[1] = 0x0
7035 13:54:07.801924 LP4Y_EN = 0x0
7036 13:54:07.802571 WORK_FSP = 0x1
7037 13:54:07.805356 WL = 0x5
7038 13:54:07.805814 RL = 0x5
7039 13:54:07.809314 BL = 0x2
7040 13:54:07.809868 RPST = 0x0
7041 13:54:07.811774 RD_PRE = 0x0
7042 13:54:07.812329 WR_PRE = 0x1
7043 13:54:07.815907 WR_PST = 0x1
7044 13:54:07.818684 DBI_WR = 0x0
7045 13:54:07.819236 DBI_RD = 0x0
7046 13:54:07.821754 OTF = 0x1
7047 13:54:07.825436 ===================================
7048 13:54:07.828466 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7049 13:54:07.831760 ==
7050 13:54:07.835138 Dram Type= 6, Freq= 0, CH_0, rank 0
7051 13:54:07.838539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7052 13:54:07.839099 ==
7053 13:54:07.841428 [Duty_Offset_Calibration]
7054 13:54:07.841987 B0:0 B1:2 CA:1
7055 13:54:07.842347
7056 13:54:07.844639 [DutyScan_Calibration_Flow] k_type=0
7057 13:54:07.854937
7058 13:54:07.855488 ==CLK 0==
7059 13:54:07.858123 Final CLK duty delay cell = 0
7060 13:54:07.861621 [0] MAX Duty = 5156%(X100), DQS PI = 20
7061 13:54:07.864645 [0] MIN Duty = 4938%(X100), DQS PI = 50
7062 13:54:07.868305 [0] AVG Duty = 5047%(X100)
7063 13:54:07.868910
7064 13:54:07.871311 CH0 CLK Duty spec in!! Max-Min= 218%
7065 13:54:07.875200 [DutyScan_Calibration_Flow] ====Done====
7066 13:54:07.875753
7067 13:54:07.879204 [DutyScan_Calibration_Flow] k_type=1
7068 13:54:07.895169
7069 13:54:07.895721 ==DQS 0 ==
7070 13:54:07.898131 Final DQS duty delay cell = 0
7071 13:54:07.901632 [0] MAX Duty = 5125%(X100), DQS PI = 22
7072 13:54:07.905078 [0] MIN Duty = 5031%(X100), DQS PI = 8
7073 13:54:07.905636 [0] AVG Duty = 5078%(X100)
7074 13:54:07.908325
7075 13:54:07.908935 ==DQS 1 ==
7076 13:54:07.911800 Final DQS duty delay cell = 0
7077 13:54:07.915804 [0] MAX Duty = 5031%(X100), DQS PI = 4
7078 13:54:07.919533 [0] MIN Duty = 4876%(X100), DQS PI = 16
7079 13:54:07.920095 [0] AVG Duty = 4953%(X100)
7080 13:54:07.921068
7081 13:54:07.924895 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7082 13:54:07.925451
7083 13:54:07.928150 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7084 13:54:07.931535 [DutyScan_Calibration_Flow] ====Done====
7085 13:54:07.932095
7086 13:54:07.934734 [DutyScan_Calibration_Flow] k_type=3
7087 13:54:07.952490
7088 13:54:07.953087 ==DQM 0 ==
7089 13:54:07.955467 Final DQM duty delay cell = 0
7090 13:54:07.958324 [0] MAX Duty = 5187%(X100), DQS PI = 22
7091 13:54:07.962221 [0] MIN Duty = 4907%(X100), DQS PI = 44
7092 13:54:07.965452 [0] AVG Duty = 5047%(X100)
7093 13:54:07.966017
7094 13:54:07.966376 ==DQM 1 ==
7095 13:54:07.968258 Final DQM duty delay cell = 0
7096 13:54:07.971774 [0] MAX Duty = 5000%(X100), DQS PI = 2
7097 13:54:07.974930 [0] MIN Duty = 4782%(X100), DQS PI = 14
7098 13:54:07.978761 [0] AVG Duty = 4891%(X100)
7099 13:54:07.979322
7100 13:54:07.981450 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7101 13:54:07.981989
7102 13:54:07.984957 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7103 13:54:07.988212 [DutyScan_Calibration_Flow] ====Done====
7104 13:54:07.988821
7105 13:54:07.991906 [DutyScan_Calibration_Flow] k_type=2
7106 13:54:08.008374
7107 13:54:08.008964 ==DQ 0 ==
7108 13:54:08.011526 Final DQ duty delay cell = 0
7109 13:54:08.015129 [0] MAX Duty = 5218%(X100), DQS PI = 18
7110 13:54:08.018597 [0] MIN Duty = 4938%(X100), DQS PI = 56
7111 13:54:08.019158 [0] AVG Duty = 5078%(X100)
7112 13:54:08.021967
7113 13:54:08.022520 ==DQ 1 ==
7114 13:54:08.024304 Final DQ duty delay cell = -4
7115 13:54:08.027832 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7116 13:54:08.031568 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7117 13:54:08.035821 [-4] AVG Duty = 4953%(X100)
7118 13:54:08.036385
7119 13:54:08.037603 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7120 13:54:08.038059
7121 13:54:08.041180 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7122 13:54:08.044649 [DutyScan_Calibration_Flow] ====Done====
7123 13:54:08.045255 ==
7124 13:54:08.047804 Dram Type= 6, Freq= 0, CH_1, rank 0
7125 13:54:08.051132 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7126 13:54:08.051690 ==
7127 13:54:08.054700 [Duty_Offset_Calibration]
7128 13:54:08.055255 B0:0 B1:4 CA:-5
7129 13:54:08.055618
7130 13:54:08.057710 [DutyScan_Calibration_Flow] k_type=0
7131 13:54:08.068808
7132 13:54:08.069407 ==CLK 0==
7133 13:54:08.071677 Final CLK duty delay cell = 0
7134 13:54:08.075357 [0] MAX Duty = 5156%(X100), DQS PI = 20
7135 13:54:08.078802 [0] MIN Duty = 4906%(X100), DQS PI = 52
7136 13:54:08.079387 [0] AVG Duty = 5031%(X100)
7137 13:54:08.082582
7138 13:54:08.083034 CH1 CLK Duty spec in!! Max-Min= 250%
7139 13:54:08.088616 [DutyScan_Calibration_Flow] ====Done====
7140 13:54:08.089232
7141 13:54:08.091899 [DutyScan_Calibration_Flow] k_type=1
7142 13:54:08.107714
7143 13:54:08.108269 ==DQS 0 ==
7144 13:54:08.110914 Final DQS duty delay cell = 0
7145 13:54:08.113903 [0] MAX Duty = 5187%(X100), DQS PI = 20
7146 13:54:08.117293 [0] MIN Duty = 4907%(X100), DQS PI = 42
7147 13:54:08.121419 [0] AVG Duty = 5047%(X100)
7148 13:54:08.121977
7149 13:54:08.122337 ==DQS 1 ==
7150 13:54:08.124232 Final DQS duty delay cell = -4
7151 13:54:08.127233 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7152 13:54:08.131176 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7153 13:54:08.134407 [-4] AVG Duty = 4922%(X100)
7154 13:54:08.134971
7155 13:54:08.137432 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7156 13:54:08.137996
7157 13:54:08.140966 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7158 13:54:08.144060 [DutyScan_Calibration_Flow] ====Done====
7159 13:54:08.144618
7160 13:54:08.148058 [DutyScan_Calibration_Flow] k_type=3
7161 13:54:08.163334
7162 13:54:08.164050 ==DQM 0 ==
7163 13:54:08.167139 Final DQM duty delay cell = -4
7164 13:54:08.170447 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7165 13:54:08.173518 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7166 13:54:08.176729 [-4] AVG Duty = 4937%(X100)
7167 13:54:08.177306
7168 13:54:08.177669 ==DQM 1 ==
7169 13:54:08.179986 Final DQM duty delay cell = -4
7170 13:54:08.183762 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7171 13:54:08.186430 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7172 13:54:08.189578 [-4] AVG Duty = 4984%(X100)
7173 13:54:08.190037
7174 13:54:08.193188 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7175 13:54:08.193819
7176 13:54:08.196100 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7177 13:54:08.199175 [DutyScan_Calibration_Flow] ====Done====
7178 13:54:08.199634
7179 13:54:08.202432 [DutyScan_Calibration_Flow] k_type=2
7180 13:54:08.221844
7181 13:54:08.222397 ==DQ 0 ==
7182 13:54:08.224313 Final DQ duty delay cell = 0
7183 13:54:08.227992 [0] MAX Duty = 5093%(X100), DQS PI = 20
7184 13:54:08.230777 [0] MIN Duty = 4969%(X100), DQS PI = 46
7185 13:54:08.231236 [0] AVG Duty = 5031%(X100)
7186 13:54:08.235368
7187 13:54:08.235929 ==DQ 1 ==
7188 13:54:08.237268 Final DQ duty delay cell = 0
7189 13:54:08.241294 [0] MAX Duty = 5031%(X100), DQS PI = 2
7190 13:54:08.244400 [0] MIN Duty = 4876%(X100), DQS PI = 28
7191 13:54:08.245002 [0] AVG Duty = 4953%(X100)
7192 13:54:08.245367
7193 13:54:08.251328 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7194 13:54:08.251889
7195 13:54:08.254402 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7196 13:54:08.258483 [DutyScan_Calibration_Flow] ====Done====
7197 13:54:08.261369 nWR fixed to 30
7198 13:54:08.261830 [ModeRegInit_LP4] CH0 RK0
7199 13:54:08.264186 [ModeRegInit_LP4] CH0 RK1
7200 13:54:08.267738 [ModeRegInit_LP4] CH1 RK0
7201 13:54:08.270641 [ModeRegInit_LP4] CH1 RK1
7202 13:54:08.271100 match AC timing 4
7203 13:54:08.278252 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7204 13:54:08.281140 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7205 13:54:08.283907 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7206 13:54:08.290247 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7207 13:54:08.293745 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7208 13:54:08.294311 [MiockJmeterHQA]
7209 13:54:08.294677
7210 13:54:08.296943 [DramcMiockJmeter] u1RxGatingPI = 0
7211 13:54:08.300408 0 : 4252, 4027
7212 13:54:08.300920 4 : 4252, 4027
7213 13:54:08.303331 8 : 4363, 4138
7214 13:54:08.303794 12 : 4368, 4140
7215 13:54:08.304163 16 : 4368, 4138
7216 13:54:08.307301 20 : 4252, 4026
7217 13:54:08.307762 24 : 4252, 4027
7218 13:54:08.310033 28 : 4252, 4027
7219 13:54:08.310498 32 : 4363, 4137
7220 13:54:08.313479 36 : 4252, 4027
7221 13:54:08.313940 40 : 4362, 4137
7222 13:54:08.316523 44 : 4250, 4027
7223 13:54:08.317030 48 : 4252, 4027
7224 13:54:08.317396 52 : 4252, 4026
7225 13:54:08.321252 56 : 4255, 4030
7226 13:54:08.321713 60 : 4361, 4137
7227 13:54:08.323257 64 : 4250, 4027
7228 13:54:08.323719 68 : 4361, 4137
7229 13:54:08.327068 72 : 4250, 4026
7230 13:54:08.327637 76 : 4250, 4027
7231 13:54:08.331137 80 : 4249, 4027
7232 13:54:08.331706 84 : 4361, 4137
7233 13:54:08.332071 88 : 4250, 4027
7234 13:54:08.334149 92 : 4360, 4137
7235 13:54:08.334715 96 : 4250, 4027
7236 13:54:08.336413 100 : 4250, 2138
7237 13:54:08.336926 104 : 4361, 0
7238 13:54:08.340449 108 : 4361, 0
7239 13:54:08.340966 112 : 4252, 0
7240 13:54:08.341332 116 : 4250, 0
7241 13:54:08.343033 120 : 4361, 0
7242 13:54:08.343496 124 : 4250, 0
7243 13:54:08.343857 128 : 4250, 0
7244 13:54:08.346814 132 : 4249, 0
7245 13:54:08.347388 136 : 4252, 0
7246 13:54:08.350380 140 : 4361, 0
7247 13:54:08.350950 144 : 4250, 0
7248 13:54:08.351324 148 : 4250, 0
7249 13:54:08.353114 152 : 4250, 0
7250 13:54:08.353580 156 : 4360, 0
7251 13:54:08.356859 160 : 4360, 0
7252 13:54:08.357324 164 : 4249, 0
7253 13:54:08.357690 168 : 4250, 0
7254 13:54:08.359574 172 : 4363, 0
7255 13:54:08.360035 176 : 4250, 0
7256 13:54:08.363020 180 : 4250, 0
7257 13:54:08.363485 184 : 4250, 0
7258 13:54:08.363854 188 : 4252, 0
7259 13:54:08.366310 192 : 4250, 0
7260 13:54:08.366775 196 : 4250, 0
7261 13:54:08.370280 200 : 4253, 0
7262 13:54:08.370901 204 : 4360, 0
7263 13:54:08.371277 208 : 4360, 0
7264 13:54:08.372698 212 : 4363, 0
7265 13:54:08.373369 216 : 4250, 0
7266 13:54:08.377159 220 : 4252, 750
7267 13:54:08.377728 224 : 4252, 4007
7268 13:54:08.378099 228 : 4360, 4138
7269 13:54:08.381033 232 : 4250, 4027
7270 13:54:08.381499 236 : 4250, 4026
7271 13:54:08.383082 240 : 4250, 4027
7272 13:54:08.383543 244 : 4252, 4029
7273 13:54:08.386453 248 : 4249, 4027
7274 13:54:08.387030 252 : 4250, 4026
7275 13:54:08.389396 256 : 4250, 4027
7276 13:54:08.389860 260 : 4252, 4030
7277 13:54:08.393189 264 : 4250, 4027
7278 13:54:08.393651 268 : 4360, 4137
7279 13:54:08.396595 272 : 4361, 4137
7280 13:54:08.397230 276 : 4250, 4027
7281 13:54:08.399367 280 : 4363, 4140
7282 13:54:08.399834 284 : 4249, 4027
7283 13:54:08.400202 288 : 4250, 4026
7284 13:54:08.403623 292 : 4250, 4027
7285 13:54:08.404196 296 : 4252, 4030
7286 13:54:08.406216 300 : 4249, 4027
7287 13:54:08.406786 304 : 4250, 4026
7288 13:54:08.409428 308 : 4250, 4027
7289 13:54:08.409892 312 : 4252, 4030
7290 13:54:08.412503 316 : 4249, 4027
7291 13:54:08.413019 320 : 4360, 4137
7292 13:54:08.416122 324 : 4361, 4137
7293 13:54:08.416690 328 : 4250, 4027
7294 13:54:08.419571 332 : 4363, 4140
7295 13:54:08.420133 336 : 4249, 3895
7296 13:54:08.422873 340 : 4250, 1788
7297 13:54:08.423340
7298 13:54:08.423699 MIOCK jitter meter ch=0
7299 13:54:08.424033
7300 13:54:08.426572 1T = (340-104) = 236 dly cells
7301 13:54:08.432754 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7302 13:54:08.433402 ==
7303 13:54:08.436333 Dram Type= 6, Freq= 0, CH_0, rank 0
7304 13:54:08.439588 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7305 13:54:08.440153 ==
7306 13:54:08.445895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7307 13:54:08.449521 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7308 13:54:08.452843 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7309 13:54:08.459650 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7310 13:54:08.468134 [CA 0] Center 42 (12~73) winsize 62
7311 13:54:08.471411 [CA 1] Center 42 (12~73) winsize 62
7312 13:54:08.474925 [CA 2] Center 39 (9~69) winsize 61
7313 13:54:08.478043 [CA 3] Center 38 (9~68) winsize 60
7314 13:54:08.481095 [CA 4] Center 37 (7~67) winsize 61
7315 13:54:08.484977 [CA 5] Center 36 (6~66) winsize 61
7316 13:54:08.485446
7317 13:54:08.488774 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7318 13:54:08.489232
7319 13:54:08.491461 [CATrainingPosCal] consider 1 rank data
7320 13:54:08.494619 u2DelayCellTimex100 = 275/100 ps
7321 13:54:08.498040 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7322 13:54:08.504444 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7323 13:54:08.507945 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7324 13:54:08.511427 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7325 13:54:08.514782 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7326 13:54:08.517865 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7327 13:54:08.518322
7328 13:54:08.521298 CA PerBit enable=1, Macro0, CA PI delay=36
7329 13:54:08.521861
7330 13:54:08.525061 [CBTSetCACLKResult] CA Dly = 36
7331 13:54:08.527901 CS Dly: 10 (0~41)
7332 13:54:08.531071 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7333 13:54:08.535096 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7334 13:54:08.535658 ==
7335 13:54:08.538329 Dram Type= 6, Freq= 0, CH_0, rank 1
7336 13:54:08.544524 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7337 13:54:08.545141 ==
7338 13:54:08.547512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7339 13:54:08.551317 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7340 13:54:08.557385 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7341 13:54:08.564247 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7342 13:54:08.571090 [CA 0] Center 42 (12~73) winsize 62
7343 13:54:08.574701 [CA 1] Center 41 (11~72) winsize 62
7344 13:54:08.579043 [CA 2] Center 38 (9~68) winsize 60
7345 13:54:08.580555 [CA 3] Center 37 (7~67) winsize 61
7346 13:54:08.584521 [CA 4] Center 35 (5~65) winsize 61
7347 13:54:08.587367 [CA 5] Center 35 (5~66) winsize 62
7348 13:54:08.587924
7349 13:54:08.590421 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7350 13:54:08.590879
7351 13:54:08.594636 [CATrainingPosCal] consider 2 rank data
7352 13:54:08.597439 u2DelayCellTimex100 = 275/100 ps
7353 13:54:08.601111 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7354 13:54:08.607754 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7355 13:54:08.612260 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7356 13:54:08.613648 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7357 13:54:08.617012 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7358 13:54:08.620840 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7359 13:54:08.621390
7360 13:54:08.623792 CA PerBit enable=1, Macro0, CA PI delay=36
7361 13:54:08.624241
7362 13:54:08.627149 [CBTSetCACLKResult] CA Dly = 36
7363 13:54:08.630530 CS Dly: 11 (0~43)
7364 13:54:08.633916 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7365 13:54:08.637627 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7366 13:54:08.638078
7367 13:54:08.640175 ----->DramcWriteLeveling(PI) begin...
7368 13:54:08.640856 ==
7369 13:54:08.643368 Dram Type= 6, Freq= 0, CH_0, rank 0
7370 13:54:08.650488 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7371 13:54:08.651040 ==
7372 13:54:08.654128 Write leveling (Byte 0): 29 => 29
7373 13:54:08.654678 Write leveling (Byte 1): 25 => 25
7374 13:54:08.656866 DramcWriteLeveling(PI) end<-----
7375 13:54:08.657316
7376 13:54:08.661582 ==
7377 13:54:08.665752 Dram Type= 6, Freq= 0, CH_0, rank 0
7378 13:54:08.666678 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7379 13:54:08.667076 ==
7380 13:54:08.670275 [Gating] SW mode calibration
7381 13:54:08.676781 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7382 13:54:08.680001 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7383 13:54:08.687397 0 12 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7384 13:54:08.691903 0 12 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7385 13:54:08.693244 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7386 13:54:08.700855 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7387 13:54:08.703752 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7388 13:54:08.706375 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7389 13:54:08.712911 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7390 13:54:08.716289 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7391 13:54:08.719437 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7392 13:54:08.726889 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
7393 13:54:08.729331 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7394 13:54:08.732651 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7395 13:54:08.739914 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7396 13:54:08.742580 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7397 13:54:08.746048 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7398 13:54:08.752394 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 13:54:08.756449 0 14 0 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7400 13:54:08.759723 0 14 4 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
7401 13:54:08.766066 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7402 13:54:08.769391 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7403 13:54:08.772583 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7404 13:54:08.779442 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7405 13:54:08.782398 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 13:54:08.785493 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 13:54:08.792654 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7408 13:54:08.796105 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7409 13:54:08.799372 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 13:54:08.805427 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 13:54:08.808914 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 13:54:08.812470 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 13:54:08.819045 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 13:54:08.822291 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 13:54:08.825999 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 13:54:08.832005 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 13:54:08.835364 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 13:54:08.838604 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 13:54:08.845281 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 13:54:08.848669 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 13:54:08.852117 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 13:54:08.858554 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7423 13:54:08.862193 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7424 13:54:08.865119 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7425 13:54:08.868617 Total UI for P1: 0, mck2ui 16
7426 13:54:08.872414 best dqsien dly found for B0: ( 1, 0, 30)
7427 13:54:08.878851 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7428 13:54:08.881569 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7429 13:54:08.884676 Total UI for P1: 0, mck2ui 16
7430 13:54:08.888250 best dqsien dly found for B1: ( 1, 1, 4)
7431 13:54:08.891356 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7432 13:54:08.894402 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7433 13:54:08.894862
7434 13:54:08.898517 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7435 13:54:08.901359 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7436 13:54:08.904455 [Gating] SW calibration Done
7437 13:54:08.904949 ==
7438 13:54:08.908112 Dram Type= 6, Freq= 0, CH_0, rank 0
7439 13:54:08.911928 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7440 13:54:08.912502 ==
7441 13:54:08.914898 RX Vref Scan: 0
7442 13:54:08.915446
7443 13:54:08.919096 RX Vref 0 -> 0, step: 1
7444 13:54:08.919663
7445 13:54:08.920031 RX Delay 0 -> 252, step: 8
7446 13:54:08.924241 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7447 13:54:08.928213 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7448 13:54:08.931128 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7449 13:54:08.934426 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7450 13:54:08.937361 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7451 13:54:08.944942 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7452 13:54:08.947827 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7453 13:54:08.951199 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7454 13:54:08.953998 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7455 13:54:08.957084 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7456 13:54:08.964941 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7457 13:54:08.967622 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7458 13:54:08.970689 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7459 13:54:08.974261 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7460 13:54:08.980618 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7461 13:54:08.983884 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7462 13:54:08.984425 ==
7463 13:54:08.987315 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 13:54:08.990597 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7465 13:54:08.991057 ==
7466 13:54:08.991431 DQS Delay:
7467 13:54:08.994071 DQS0 = 0, DQS1 = 0
7468 13:54:08.994523 DQM Delay:
7469 13:54:08.997026 DQM0 = 129, DQM1 = 123
7470 13:54:08.997579 DQ Delay:
7471 13:54:09.000607 DQ0 =123, DQ1 =131, DQ2 =123, DQ3 =127
7472 13:54:09.003391 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7473 13:54:09.007465 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7474 13:54:09.013578 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7475 13:54:09.014134
7476 13:54:09.014617
7477 13:54:09.015072 ==
7478 13:54:09.017301 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 13:54:09.020892 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7480 13:54:09.021467 ==
7481 13:54:09.021953
7482 13:54:09.022408
7483 13:54:09.023508 TX Vref Scan disable
7484 13:54:09.023981 == TX Byte 0 ==
7485 13:54:09.030546 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7486 13:54:09.034091 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7487 13:54:09.034654 == TX Byte 1 ==
7488 13:54:09.040939 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7489 13:54:09.043169 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7490 13:54:09.043646 ==
7491 13:54:09.047368 Dram Type= 6, Freq= 0, CH_0, rank 0
7492 13:54:09.049895 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7493 13:54:09.050459 ==
7494 13:54:09.065049
7495 13:54:09.067621 TX Vref early break, caculate TX vref
7496 13:54:09.070843 TX Vref=16, minBit 8, minWin=21, winSum=367
7497 13:54:09.074398 TX Vref=18, minBit 8, minWin=22, winSum=379
7498 13:54:09.077078 TX Vref=20, minBit 8, minWin=23, winSum=385
7499 13:54:09.081344 TX Vref=22, minBit 8, minWin=23, winSum=395
7500 13:54:09.083867 TX Vref=24, minBit 8, minWin=24, winSum=406
7501 13:54:09.090914 TX Vref=26, minBit 9, minWin=24, winSum=412
7502 13:54:09.093623 TX Vref=28, minBit 0, minWin=25, winSum=417
7503 13:54:09.097138 TX Vref=30, minBit 8, minWin=24, winSum=410
7504 13:54:09.100413 TX Vref=32, minBit 7, minWin=24, winSum=401
7505 13:54:09.103489 TX Vref=34, minBit 1, minWin=24, winSum=393
7506 13:54:09.111561 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
7507 13:54:09.112112
7508 13:54:09.113866 Final TX Range 0 Vref 28
7509 13:54:09.114323
7510 13:54:09.114677 ==
7511 13:54:09.117195 Dram Type= 6, Freq= 0, CH_0, rank 0
7512 13:54:09.120660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7513 13:54:09.121258 ==
7514 13:54:09.121618
7515 13:54:09.121949
7516 13:54:09.123654 TX Vref Scan disable
7517 13:54:09.130178 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7518 13:54:09.130733 == TX Byte 0 ==
7519 13:54:09.133602 u2DelayCellOfst[0]=14 cells (4 PI)
7520 13:54:09.136861 u2DelayCellOfst[1]=17 cells (5 PI)
7521 13:54:09.140906 u2DelayCellOfst[2]=14 cells (4 PI)
7522 13:54:09.144399 u2DelayCellOfst[3]=14 cells (4 PI)
7523 13:54:09.146724 u2DelayCellOfst[4]=7 cells (2 PI)
7524 13:54:09.150363 u2DelayCellOfst[5]=0 cells (0 PI)
7525 13:54:09.153748 u2DelayCellOfst[6]=17 cells (5 PI)
7526 13:54:09.156958 u2DelayCellOfst[7]=14 cells (4 PI)
7527 13:54:09.160841 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7528 13:54:09.163438 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7529 13:54:09.166750 == TX Byte 1 ==
7530 13:54:09.169775 u2DelayCellOfst[8]=3 cells (1 PI)
7531 13:54:09.170327 u2DelayCellOfst[9]=0 cells (0 PI)
7532 13:54:09.173178 u2DelayCellOfst[10]=10 cells (3 PI)
7533 13:54:09.177096 u2DelayCellOfst[11]=3 cells (1 PI)
7534 13:54:09.180175 u2DelayCellOfst[12]=14 cells (4 PI)
7535 13:54:09.183327 u2DelayCellOfst[13]=14 cells (4 PI)
7536 13:54:09.186247 u2DelayCellOfst[14]=17 cells (5 PI)
7537 13:54:09.189884 u2DelayCellOfst[15]=14 cells (4 PI)
7538 13:54:09.192700 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7539 13:54:09.200118 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7540 13:54:09.200654 DramC Write-DBI on
7541 13:54:09.201109 ==
7542 13:54:09.202743 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 13:54:09.209442 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7544 13:54:09.209904 ==
7545 13:54:09.210262
7546 13:54:09.210590
7547 13:54:09.210907 TX Vref Scan disable
7548 13:54:09.214242 == TX Byte 0 ==
7549 13:54:09.217235 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7550 13:54:09.220482 == TX Byte 1 ==
7551 13:54:09.223602 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7552 13:54:09.227081 DramC Write-DBI off
7553 13:54:09.227635
7554 13:54:09.227996 [DATLAT]
7555 13:54:09.228330 Freq=1600, CH0 RK0
7556 13:54:09.228652
7557 13:54:09.229955 DATLAT Default: 0xf
7558 13:54:09.230452 0, 0xFFFF, sum = 0
7559 13:54:09.233138 1, 0xFFFF, sum = 0
7560 13:54:09.237428 2, 0xFFFF, sum = 0
7561 13:54:09.237982 3, 0xFFFF, sum = 0
7562 13:54:09.240219 4, 0xFFFF, sum = 0
7563 13:54:09.240815 5, 0xFFFF, sum = 0
7564 13:54:09.243893 6, 0xFFFF, sum = 0
7565 13:54:09.244446 7, 0xFFFF, sum = 0
7566 13:54:09.246423 8, 0xFFFF, sum = 0
7567 13:54:09.246887 9, 0xFFFF, sum = 0
7568 13:54:09.250237 10, 0xFFFF, sum = 0
7569 13:54:09.250800 11, 0xFFFF, sum = 0
7570 13:54:09.253276 12, 0x8FFF, sum = 0
7571 13:54:09.253739 13, 0x0, sum = 1
7572 13:54:09.257606 14, 0x0, sum = 2
7573 13:54:09.258166 15, 0x0, sum = 3
7574 13:54:09.259878 16, 0x0, sum = 4
7575 13:54:09.260344 best_step = 14
7576 13:54:09.260742
7577 13:54:09.261121 ==
7578 13:54:09.263520 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 13:54:09.270453 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7580 13:54:09.271004 ==
7581 13:54:09.271372 RX Vref Scan: 1
7582 13:54:09.271710
7583 13:54:09.272905 Set Vref Range= 24 -> 127
7584 13:54:09.273372
7585 13:54:09.276798 RX Vref 24 -> 127, step: 1
7586 13:54:09.277359
7587 13:54:09.277841 RX Delay 11 -> 252, step: 4
7588 13:54:09.278294
7589 13:54:09.279420 Set Vref, RX VrefLevel [Byte0]: 24
7590 13:54:09.283435 [Byte1]: 24
7591 13:54:09.286758
7592 13:54:09.287210 Set Vref, RX VrefLevel [Byte0]: 25
7593 13:54:09.290656 [Byte1]: 25
7594 13:54:09.295115
7595 13:54:09.295566 Set Vref, RX VrefLevel [Byte0]: 26
7596 13:54:09.299094 [Byte1]: 26
7597 13:54:09.301895
7598 13:54:09.302346 Set Vref, RX VrefLevel [Byte0]: 27
7599 13:54:09.305785 [Byte1]: 27
7600 13:54:09.309553
7601 13:54:09.310097 Set Vref, RX VrefLevel [Byte0]: 28
7602 13:54:09.313104 [Byte1]: 28
7603 13:54:09.317991
7604 13:54:09.318536 Set Vref, RX VrefLevel [Byte0]: 29
7605 13:54:09.320836 [Byte1]: 29
7606 13:54:09.324856
7607 13:54:09.325423 Set Vref, RX VrefLevel [Byte0]: 30
7608 13:54:09.328407 [Byte1]: 30
7609 13:54:09.332422
7610 13:54:09.332924 Set Vref, RX VrefLevel [Byte0]: 31
7611 13:54:09.336087 [Byte1]: 31
7612 13:54:09.340996
7613 13:54:09.341624 Set Vref, RX VrefLevel [Byte0]: 32
7614 13:54:09.343515 [Byte1]: 32
7615 13:54:09.348125
7616 13:54:09.348683 Set Vref, RX VrefLevel [Byte0]: 33
7617 13:54:09.350904 [Byte1]: 33
7618 13:54:09.355421
7619 13:54:09.355987 Set Vref, RX VrefLevel [Byte0]: 34
7620 13:54:09.358945 [Byte1]: 34
7621 13:54:09.363396
7622 13:54:09.363974 Set Vref, RX VrefLevel [Byte0]: 35
7623 13:54:09.366595 [Byte1]: 35
7624 13:54:09.370551
7625 13:54:09.371094 Set Vref, RX VrefLevel [Byte0]: 36
7626 13:54:09.374332 [Byte1]: 36
7627 13:54:09.378757
7628 13:54:09.379300 Set Vref, RX VrefLevel [Byte0]: 37
7629 13:54:09.381497 [Byte1]: 37
7630 13:54:09.386742
7631 13:54:09.387201 Set Vref, RX VrefLevel [Byte0]: 38
7632 13:54:09.388817 [Byte1]: 38
7633 13:54:09.393988
7634 13:54:09.394533 Set Vref, RX VrefLevel [Byte0]: 39
7635 13:54:09.396672 [Byte1]: 39
7636 13:54:09.400989
7637 13:54:09.401449 Set Vref, RX VrefLevel [Byte0]: 40
7638 13:54:09.404150 [Byte1]: 40
7639 13:54:09.408963
7640 13:54:09.409501 Set Vref, RX VrefLevel [Byte0]: 41
7641 13:54:09.411873 [Byte1]: 41
7642 13:54:09.416515
7643 13:54:09.417114 Set Vref, RX VrefLevel [Byte0]: 42
7644 13:54:09.420074 [Byte1]: 42
7645 13:54:09.424028
7646 13:54:09.424595 Set Vref, RX VrefLevel [Byte0]: 43
7647 13:54:09.427336 [Byte1]: 43
7648 13:54:09.431505
7649 13:54:09.432056 Set Vref, RX VrefLevel [Byte0]: 44
7650 13:54:09.435427 [Byte1]: 44
7651 13:54:09.439256
7652 13:54:09.439709 Set Vref, RX VrefLevel [Byte0]: 45
7653 13:54:09.443185 [Byte1]: 45
7654 13:54:09.446972
7655 13:54:09.447423 Set Vref, RX VrefLevel [Byte0]: 46
7656 13:54:09.450305 [Byte1]: 46
7657 13:54:09.454615
7658 13:54:09.455164 Set Vref, RX VrefLevel [Byte0]: 47
7659 13:54:09.458018 [Byte1]: 47
7660 13:54:09.462312
7661 13:54:09.462859 Set Vref, RX VrefLevel [Byte0]: 48
7662 13:54:09.465979 [Byte1]: 48
7663 13:54:09.469818
7664 13:54:09.470271 Set Vref, RX VrefLevel [Byte0]: 49
7665 13:54:09.473164 [Byte1]: 49
7666 13:54:09.477515
7667 13:54:09.478065 Set Vref, RX VrefLevel [Byte0]: 50
7668 13:54:09.480938 [Byte1]: 50
7669 13:54:09.484987
7670 13:54:09.485440 Set Vref, RX VrefLevel [Byte0]: 51
7671 13:54:09.487828 [Byte1]: 51
7672 13:54:09.493059
7673 13:54:09.493634 Set Vref, RX VrefLevel [Byte0]: 52
7674 13:54:09.495646 [Byte1]: 52
7675 13:54:09.501112
7676 13:54:09.501659 Set Vref, RX VrefLevel [Byte0]: 53
7677 13:54:09.503362 [Byte1]: 53
7678 13:54:09.507642
7679 13:54:09.508098 Set Vref, RX VrefLevel [Byte0]: 54
7680 13:54:09.511144 [Byte1]: 54
7681 13:54:09.515346
7682 13:54:09.515895 Set Vref, RX VrefLevel [Byte0]: 55
7683 13:54:09.519808 [Byte1]: 55
7684 13:54:09.523156
7685 13:54:09.523701 Set Vref, RX VrefLevel [Byte0]: 56
7686 13:54:09.526155 [Byte1]: 56
7687 13:54:09.530727
7688 13:54:09.531481 Set Vref, RX VrefLevel [Byte0]: 57
7689 13:54:09.533961 [Byte1]: 57
7690 13:54:09.538511
7691 13:54:09.539059 Set Vref, RX VrefLevel [Byte0]: 58
7692 13:54:09.541670 [Byte1]: 58
7693 13:54:09.545705
7694 13:54:09.546256 Set Vref, RX VrefLevel [Byte0]: 59
7695 13:54:09.550134 [Byte1]: 59
7696 13:54:09.554544
7697 13:54:09.555093 Set Vref, RX VrefLevel [Byte0]: 60
7698 13:54:09.556938 [Byte1]: 60
7699 13:54:09.561188
7700 13:54:09.561802 Set Vref, RX VrefLevel [Byte0]: 61
7701 13:54:09.565224 [Byte1]: 61
7702 13:54:09.568971
7703 13:54:09.569459 Set Vref, RX VrefLevel [Byte0]: 62
7704 13:54:09.571779 [Byte1]: 62
7705 13:54:09.576979
7706 13:54:09.577533 Set Vref, RX VrefLevel [Byte0]: 63
7707 13:54:09.579498 [Byte1]: 63
7708 13:54:09.584614
7709 13:54:09.585265 Set Vref, RX VrefLevel [Byte0]: 64
7710 13:54:09.587129 [Byte1]: 64
7711 13:54:09.591818
7712 13:54:09.592364 Set Vref, RX VrefLevel [Byte0]: 65
7713 13:54:09.594636 [Byte1]: 65
7714 13:54:09.599488
7715 13:54:09.600037 Set Vref, RX VrefLevel [Byte0]: 66
7716 13:54:09.603052 [Byte1]: 66
7717 13:54:09.607261
7718 13:54:09.607733 Set Vref, RX VrefLevel [Byte0]: 67
7719 13:54:09.610145 [Byte1]: 67
7720 13:54:09.614156
7721 13:54:09.614717 Set Vref, RX VrefLevel [Byte0]: 68
7722 13:54:09.617771 [Byte1]: 68
7723 13:54:09.622114
7724 13:54:09.622657 Set Vref, RX VrefLevel [Byte0]: 69
7725 13:54:09.625244 [Byte1]: 69
7726 13:54:09.629583
7727 13:54:09.630126 Set Vref, RX VrefLevel [Byte0]: 70
7728 13:54:09.633197 [Byte1]: 70
7729 13:54:09.636983
7730 13:54:09.637544 Final RX Vref Byte 0 = 53 to rank0
7731 13:54:09.640606 Final RX Vref Byte 1 = 57 to rank0
7732 13:54:09.643734 Final RX Vref Byte 0 = 53 to rank1
7733 13:54:09.647158 Final RX Vref Byte 1 = 57 to rank1==
7734 13:54:09.650402 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 13:54:09.657018 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7736 13:54:09.657557 ==
7737 13:54:09.657918 DQS Delay:
7738 13:54:09.658253 DQS0 = 0, DQS1 = 0
7739 13:54:09.661399 DQM Delay:
7740 13:54:09.661954 DQM0 = 126, DQM1 = 120
7741 13:54:09.664131 DQ Delay:
7742 13:54:09.666755 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7743 13:54:09.671085 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7744 13:54:09.674693 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7745 13:54:09.677649 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7746 13:54:09.678110
7747 13:54:09.678469
7748 13:54:09.678802
7749 13:54:09.679964 [DramC_TX_OE_Calibration] TA2
7750 13:54:09.683956 Original DQ_B0 (3 6) =30, OEN = 27
7751 13:54:09.687347 Original DQ_B1 (3 6) =30, OEN = 27
7752 13:54:09.690940 24, 0x0, End_B0=24 End_B1=24
7753 13:54:09.691504 25, 0x0, End_B0=25 End_B1=25
7754 13:54:09.693974 26, 0x0, End_B0=26 End_B1=26
7755 13:54:09.697088 27, 0x0, End_B0=27 End_B1=27
7756 13:54:09.699865 28, 0x0, End_B0=28 End_B1=28
7757 13:54:09.704271 29, 0x0, End_B0=29 End_B1=29
7758 13:54:09.704874 30, 0x0, End_B0=30 End_B1=30
7759 13:54:09.706416 31, 0x4545, End_B0=30 End_B1=30
7760 13:54:09.710339 Byte0 end_step=30 best_step=27
7761 13:54:09.713314 Byte1 end_step=30 best_step=27
7762 13:54:09.716539 Byte0 TX OE(2T, 0.5T) = (3, 3)
7763 13:54:09.720418 Byte1 TX OE(2T, 0.5T) = (3, 3)
7764 13:54:09.721031
7765 13:54:09.721402
7766 13:54:09.726616 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7767 13:54:09.730132 CH0 RK0: MR19=303, MR18=1F1F
7768 13:54:09.737248 CH0_RK0: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
7769 13:54:09.737802
7770 13:54:09.739443 ----->DramcWriteLeveling(PI) begin...
7771 13:54:09.739905 ==
7772 13:54:09.743144 Dram Type= 6, Freq= 0, CH_0, rank 1
7773 13:54:09.746930 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7774 13:54:09.747480 ==
7775 13:54:09.749331 Write leveling (Byte 0): 29 => 29
7776 13:54:09.754226 Write leveling (Byte 1): 25 => 25
7777 13:54:09.756482 DramcWriteLeveling(PI) end<-----
7778 13:54:09.756969
7779 13:54:09.757326 ==
7780 13:54:09.760698 Dram Type= 6, Freq= 0, CH_0, rank 1
7781 13:54:09.763010 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7782 13:54:09.763562 ==
7783 13:54:09.766063 [Gating] SW mode calibration
7784 13:54:09.772820 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7785 13:54:09.779829 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7786 13:54:09.782548 0 12 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7787 13:54:09.792005 0 12 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7788 13:54:09.794808 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7789 13:54:09.795621 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7790 13:54:09.802871 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7791 13:54:09.805650 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7792 13:54:09.808756 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7793 13:54:09.815980 0 12 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7794 13:54:09.818767 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
7795 13:54:09.823002 0 13 4 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7796 13:54:09.829087 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7797 13:54:09.832327 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7798 13:54:09.835382 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7799 13:54:09.842699 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7800 13:54:09.845311 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7801 13:54:09.848427 0 13 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7802 13:54:09.855351 0 14 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7803 13:54:09.858542 0 14 4 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7804 13:54:09.861694 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7805 13:54:09.868096 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7806 13:54:09.872304 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7807 13:54:09.875644 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7808 13:54:09.881643 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7809 13:54:09.885765 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7810 13:54:09.888683 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7811 13:54:09.894515 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7812 13:54:09.898674 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 13:54:09.901294 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 13:54:09.908018 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 13:54:09.911698 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 13:54:09.915312 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 13:54:09.921112 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 13:54:09.924906 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 13:54:09.928547 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 13:54:09.934872 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 13:54:09.938421 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 13:54:09.941323 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 13:54:09.947698 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 13:54:09.951591 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 13:54:09.954705 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7826 13:54:09.961080 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7827 13:54:09.964377 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7828 13:54:09.967446 Total UI for P1: 0, mck2ui 16
7829 13:54:09.970716 best dqsien dly found for B0: ( 1, 0, 30)
7830 13:54:09.974356 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7831 13:54:09.977187 Total UI for P1: 0, mck2ui 16
7832 13:54:09.981377 best dqsien dly found for B1: ( 1, 1, 2)
7833 13:54:09.984019 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7834 13:54:09.987133 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7835 13:54:09.987604
7836 13:54:09.991362 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7837 13:54:09.997634 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7838 13:54:09.998206 [Gating] SW calibration Done
7839 13:54:09.998695 ==
7840 13:54:10.001630 Dram Type= 6, Freq= 0, CH_0, rank 1
7841 13:54:10.007139 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7842 13:54:10.007707 ==
7843 13:54:10.008196 RX Vref Scan: 0
7844 13:54:10.008654
7845 13:54:10.011270 RX Vref 0 -> 0, step: 1
7846 13:54:10.011743
7847 13:54:10.014019 RX Delay 0 -> 252, step: 8
7848 13:54:10.019354 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7849 13:54:10.021271 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7850 13:54:10.023666 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7851 13:54:10.030449 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7852 13:54:10.033398 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7853 13:54:10.037172 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7854 13:54:10.040330 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7855 13:54:10.044010 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7856 13:54:10.047488 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7857 13:54:10.053324 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7858 13:54:10.056853 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7859 13:54:10.059933 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7860 13:54:10.064389 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7861 13:54:10.070088 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7862 13:54:10.073337 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7863 13:54:10.076347 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7864 13:54:10.076861 ==
7865 13:54:10.079948 Dram Type= 6, Freq= 0, CH_0, rank 1
7866 13:54:10.083548 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7867 13:54:10.084112 ==
7868 13:54:10.086994 DQS Delay:
7869 13:54:10.087469 DQS0 = 0, DQS1 = 0
7870 13:54:10.089819 DQM Delay:
7871 13:54:10.090292 DQM0 = 130, DQM1 = 124
7872 13:54:10.090778 DQ Delay:
7873 13:54:10.096944 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7874 13:54:10.100210 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7875 13:54:10.103319 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7876 13:54:10.107820 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7877 13:54:10.108389
7878 13:54:10.108983
7879 13:54:10.109446 ==
7880 13:54:10.110426 Dram Type= 6, Freq= 0, CH_0, rank 1
7881 13:54:10.113297 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7882 13:54:10.113773 ==
7883 13:54:10.114250
7884 13:54:10.114699
7885 13:54:10.116061 TX Vref Scan disable
7886 13:54:10.119759 == TX Byte 0 ==
7887 13:54:10.123336 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7888 13:54:10.126459 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7889 13:54:10.129297 == TX Byte 1 ==
7890 13:54:10.132910 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7891 13:54:10.135775 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7892 13:54:10.136342 ==
7893 13:54:10.139911 Dram Type= 6, Freq= 0, CH_0, rank 1
7894 13:54:10.145606 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7895 13:54:10.146152 ==
7896 13:54:10.157852
7897 13:54:10.161533 TX Vref early break, caculate TX vref
7898 13:54:10.165295 TX Vref=16, minBit 8, minWin=22, winSum=372
7899 13:54:10.167760 TX Vref=18, minBit 11, minWin=22, winSum=380
7900 13:54:10.170947 TX Vref=20, minBit 8, minWin=23, winSum=390
7901 13:54:10.174378 TX Vref=22, minBit 9, minWin=23, winSum=397
7902 13:54:10.177848 TX Vref=24, minBit 1, minWin=24, winSum=400
7903 13:54:10.183884 TX Vref=26, minBit 8, minWin=24, winSum=406
7904 13:54:10.187707 TX Vref=28, minBit 8, minWin=24, winSum=412
7905 13:54:10.191178 TX Vref=30, minBit 8, minWin=24, winSum=415
7906 13:54:10.193904 TX Vref=32, minBit 7, minWin=24, winSum=402
7907 13:54:10.197781 TX Vref=34, minBit 8, minWin=23, winSum=393
7908 13:54:10.204352 [TxChooseVref] Worse bit 8, Min win 24, Win sum 415, Final Vref 30
7909 13:54:10.204840
7910 13:54:10.207711 Final TX Range 0 Vref 30
7911 13:54:10.208264
7912 13:54:10.208623 ==
7913 13:54:10.210439 Dram Type= 6, Freq= 0, CH_0, rank 1
7914 13:54:10.215081 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7915 13:54:10.215635 ==
7916 13:54:10.215998
7917 13:54:10.216332
7918 13:54:10.218283 TX Vref Scan disable
7919 13:54:10.224303 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7920 13:54:10.224924 == TX Byte 0 ==
7921 13:54:10.227804 u2DelayCellOfst[0]=14 cells (4 PI)
7922 13:54:10.230820 u2DelayCellOfst[1]=17 cells (5 PI)
7923 13:54:10.234649 u2DelayCellOfst[2]=14 cells (4 PI)
7924 13:54:10.237443 u2DelayCellOfst[3]=14 cells (4 PI)
7925 13:54:10.240533 u2DelayCellOfst[4]=10 cells (3 PI)
7926 13:54:10.245294 u2DelayCellOfst[5]=0 cells (0 PI)
7927 13:54:10.246889 u2DelayCellOfst[6]=21 cells (6 PI)
7928 13:54:10.251778 u2DelayCellOfst[7]=17 cells (5 PI)
7929 13:54:10.254340 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7930 13:54:10.257419 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7931 13:54:10.260386 == TX Byte 1 ==
7932 13:54:10.263553 u2DelayCellOfst[8]=0 cells (0 PI)
7933 13:54:10.264107 u2DelayCellOfst[9]=0 cells (0 PI)
7934 13:54:10.266743 u2DelayCellOfst[10]=10 cells (3 PI)
7935 13:54:10.270337 u2DelayCellOfst[11]=3 cells (1 PI)
7936 13:54:10.273601 u2DelayCellOfst[12]=14 cells (4 PI)
7937 13:54:10.277047 u2DelayCellOfst[13]=14 cells (4 PI)
7938 13:54:10.280550 u2DelayCellOfst[14]=14 cells (4 PI)
7939 13:54:10.283747 u2DelayCellOfst[15]=14 cells (4 PI)
7940 13:54:10.287253 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7941 13:54:10.293825 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7942 13:54:10.294363 DramC Write-DBI on
7943 13:54:10.294716 ==
7944 13:54:10.297182 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 13:54:10.303817 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7946 13:54:10.304371 ==
7947 13:54:10.304782
7948 13:54:10.305132
7949 13:54:10.305454 TX Vref Scan disable
7950 13:54:10.308082 == TX Byte 0 ==
7951 13:54:10.311784 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7952 13:54:10.313606 == TX Byte 1 ==
7953 13:54:10.317216 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7954 13:54:10.321563 DramC Write-DBI off
7955 13:54:10.322031
7956 13:54:10.322510 [DATLAT]
7957 13:54:10.322964 Freq=1600, CH0 RK1
7958 13:54:10.323410
7959 13:54:10.324195 DATLAT Default: 0xe
7960 13:54:10.324589 0, 0xFFFF, sum = 0
7961 13:54:10.326858 1, 0xFFFF, sum = 0
7962 13:54:10.330260 2, 0xFFFF, sum = 0
7963 13:54:10.330837 3, 0xFFFF, sum = 0
7964 13:54:10.334673 4, 0xFFFF, sum = 0
7965 13:54:10.335252 5, 0xFFFF, sum = 0
7966 13:54:10.337048 6, 0xFFFF, sum = 0
7967 13:54:10.337531 7, 0xFFFF, sum = 0
7968 13:54:10.340877 8, 0xFFFF, sum = 0
7969 13:54:10.341452 9, 0xFFFF, sum = 0
7970 13:54:10.347467 10, 0xFFFF, sum = 0
7971 13:54:10.348043 11, 0xFFFF, sum = 0
7972 13:54:10.348546 12, 0x8FFF, sum = 0
7973 13:54:10.349056 13, 0x0, sum = 1
7974 13:54:10.350469 14, 0x0, sum = 2
7975 13:54:10.350947 15, 0x0, sum = 3
7976 13:54:10.353463 16, 0x0, sum = 4
7977 13:54:10.353944 best_step = 14
7978 13:54:10.354430
7979 13:54:10.354887 ==
7980 13:54:10.357285 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 13:54:10.363592 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7982 13:54:10.364161 ==
7983 13:54:10.364653 RX Vref Scan: 0
7984 13:54:10.365154
7985 13:54:10.366516 RX Vref 0 -> 0, step: 1
7986 13:54:10.366988
7987 13:54:10.369892 RX Delay 11 -> 252, step: 4
7988 13:54:10.373645 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7989 13:54:10.377398 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7990 13:54:10.380484 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7991 13:54:10.386788 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7992 13:54:10.390550 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7993 13:54:10.393170 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7994 13:54:10.396503 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7995 13:54:10.399914 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7996 13:54:10.407475 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7997 13:54:10.409661 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7998 13:54:10.413510 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7999 13:54:10.416533 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8000 13:54:10.420004 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8001 13:54:10.426551 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8002 13:54:10.429429 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8003 13:54:10.432862 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8004 13:54:10.433479 ==
8005 13:54:10.436651 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 13:54:10.440225 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8007 13:54:10.442775 ==
8008 13:54:10.443328 DQS Delay:
8009 13:54:10.443694 DQS0 = 0, DQS1 = 0
8010 13:54:10.446815 DQM Delay:
8011 13:54:10.447368 DQM0 = 128, DQM1 = 120
8012 13:54:10.449614 DQ Delay:
8013 13:54:10.453031 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
8014 13:54:10.456333 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
8015 13:54:10.459756 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8016 13:54:10.463660 DQ12 =126, DQ13 =126, DQ14 =130, DQ15 =130
8017 13:54:10.464216
8018 13:54:10.464575
8019 13:54:10.464965
8020 13:54:10.465848 [DramC_TX_OE_Calibration] TA2
8021 13:54:10.469274 Original DQ_B0 (3 6) =30, OEN = 27
8022 13:54:10.472825 Original DQ_B1 (3 6) =30, OEN = 27
8023 13:54:10.476012 24, 0x0, End_B0=24 End_B1=24
8024 13:54:10.476576 25, 0x0, End_B0=25 End_B1=25
8025 13:54:10.479599 26, 0x0, End_B0=26 End_B1=26
8026 13:54:10.483055 27, 0x0, End_B0=27 End_B1=27
8027 13:54:10.487332 28, 0x0, End_B0=28 End_B1=28
8028 13:54:10.487794 29, 0x0, End_B0=29 End_B1=29
8029 13:54:10.489337 30, 0x0, End_B0=30 End_B1=30
8030 13:54:10.492819 31, 0x4141, End_B0=30 End_B1=30
8031 13:54:10.496095 Byte0 end_step=30 best_step=27
8032 13:54:10.499296 Byte1 end_step=30 best_step=27
8033 13:54:10.502529 Byte0 TX OE(2T, 0.5T) = (3, 3)
8034 13:54:10.502991 Byte1 TX OE(2T, 0.5T) = (3, 3)
8035 13:54:10.503349
8036 13:54:10.503683
8037 13:54:10.512489 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8038 13:54:10.516814 CH0 RK1: MR19=303, MR18=2020
8039 13:54:10.523182 CH0_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8040 13:54:10.523746 [RxdqsGatingPostProcess] freq 1600
8041 13:54:10.529389 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8042 13:54:10.532883 Pre-setting of DQS Precalculation
8043 13:54:10.539352 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8044 13:54:10.539929 ==
8045 13:54:10.542360 Dram Type= 6, Freq= 0, CH_1, rank 0
8046 13:54:10.546410 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8047 13:54:10.546970 ==
8048 13:54:10.552756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8049 13:54:10.556789 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8050 13:54:10.559194 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8051 13:54:10.565960 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8052 13:54:10.574412 [CA 0] Center 41 (11~71) winsize 61
8053 13:54:10.576652 [CA 1] Center 40 (10~71) winsize 62
8054 13:54:10.579975 [CA 2] Center 36 (6~66) winsize 61
8055 13:54:10.583129 [CA 3] Center 35 (5~65) winsize 61
8056 13:54:10.589974 [CA 4] Center 33 (3~63) winsize 61
8057 13:54:10.590799 [CA 5] Center 33 (4~63) winsize 60
8058 13:54:10.591189
8059 13:54:10.592977 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8060 13:54:10.593612
8061 13:54:10.596820 [CATrainingPosCal] consider 1 rank data
8062 13:54:10.600018 u2DelayCellTimex100 = 275/100 ps
8063 13:54:10.603954 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8064 13:54:10.609716 CA1 delay=40 (10~71),Diff = 7 PI (24 cell)
8065 13:54:10.613272 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8066 13:54:10.616609 CA3 delay=35 (5~65),Diff = 2 PI (7 cell)
8067 13:54:10.619730 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8068 13:54:10.622876 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8069 13:54:10.623455
8070 13:54:10.626309 CA PerBit enable=1, Macro0, CA PI delay=33
8071 13:54:10.626878
8072 13:54:10.629319 [CBTSetCACLKResult] CA Dly = 33
8073 13:54:10.633095 CS Dly: 9 (0~40)
8074 13:54:10.636478 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8075 13:54:10.639609 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8076 13:54:10.640211 ==
8077 13:54:10.642632 Dram Type= 6, Freq= 0, CH_1, rank 1
8078 13:54:10.649673 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8079 13:54:10.650236 ==
8080 13:54:10.652958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8081 13:54:10.656241 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8082 13:54:10.662946 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8083 13:54:10.670100 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8084 13:54:10.676244 [CA 0] Center 40 (10~70) winsize 61
8085 13:54:10.679406 [CA 1] Center 39 (9~70) winsize 62
8086 13:54:10.682768 [CA 2] Center 35 (6~65) winsize 60
8087 13:54:10.685893 [CA 3] Center 35 (6~65) winsize 60
8088 13:54:10.689988 [CA 4] Center 33 (3~63) winsize 61
8089 13:54:10.693497 [CA 5] Center 33 (3~63) winsize 61
8090 13:54:10.694099
8091 13:54:10.696049 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8092 13:54:10.696501
8093 13:54:10.698753 [CATrainingPosCal] consider 2 rank data
8094 13:54:10.701878 u2DelayCellTimex100 = 275/100 ps
8095 13:54:10.705241 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8096 13:54:10.712189 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8097 13:54:10.715231 CA2 delay=35 (6~65),Diff = 2 PI (7 cell)
8098 13:54:10.719055 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8099 13:54:10.722031 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8100 13:54:10.725222 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8101 13:54:10.725695
8102 13:54:10.728614 CA PerBit enable=1, Macro0, CA PI delay=33
8103 13:54:10.729120
8104 13:54:10.731648 [CBTSetCACLKResult] CA Dly = 33
8105 13:54:10.735499 CS Dly: 9 (0~41)
8106 13:54:10.738841 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8107 13:54:10.742474 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8108 13:54:10.743037
8109 13:54:10.745788 ----->DramcWriteLeveling(PI) begin...
8110 13:54:10.746359 ==
8111 13:54:10.748548 Dram Type= 6, Freq= 0, CH_1, rank 0
8112 13:54:10.755446 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8113 13:54:10.756007 ==
8114 13:54:10.758805 Write leveling (Byte 0): 23 => 23
8115 13:54:10.759263 Write leveling (Byte 1): 23 => 23
8116 13:54:10.761965 DramcWriteLeveling(PI) end<-----
8117 13:54:10.762527
8118 13:54:10.762893 ==
8119 13:54:10.765284 Dram Type= 6, Freq= 0, CH_1, rank 0
8120 13:54:10.771572 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8121 13:54:10.772122 ==
8122 13:54:10.774994 [Gating] SW mode calibration
8123 13:54:10.781671 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8124 13:54:10.785416 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8125 13:54:10.791457 0 12 0 | B1->B0 | 2e2d 3434 | 1 1 | (1 1) (1 1)
8126 13:54:10.794704 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8127 13:54:10.798107 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8128 13:54:10.804490 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8129 13:54:10.807668 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 13:54:10.811769 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 13:54:10.817978 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8132 13:54:10.821570 0 12 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8133 13:54:10.824314 0 13 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8134 13:54:10.831578 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8135 13:54:10.834897 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8136 13:54:10.838117 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8137 13:54:10.844558 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8138 13:54:10.848178 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 13:54:10.851179 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8140 13:54:10.857545 0 13 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8141 13:54:10.861661 0 14 0 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
8142 13:54:10.864109 0 14 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8143 13:54:10.871591 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 13:54:10.874595 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 13:54:10.877720 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 13:54:10.883792 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 13:54:10.887113 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8148 13:54:10.890239 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8149 13:54:10.897714 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8150 13:54:10.900680 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8151 13:54:10.905105 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 13:54:10.910494 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 13:54:10.913745 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 13:54:10.917264 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 13:54:10.920571 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 13:54:10.926911 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 13:54:10.930699 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 13:54:10.933248 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 13:54:10.941260 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 13:54:10.944313 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 13:54:10.946857 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 13:54:10.953177 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 13:54:10.956545 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8164 13:54:10.960241 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8165 13:54:10.966375 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8166 13:54:10.969618 Total UI for P1: 0, mck2ui 16
8167 13:54:10.972881 best dqsien dly found for B0: ( 1, 0, 26)
8168 13:54:10.975992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8169 13:54:10.979932 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8170 13:54:10.982928 Total UI for P1: 0, mck2ui 16
8171 13:54:10.985904 best dqsien dly found for B1: ( 1, 1, 0)
8172 13:54:10.989802 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8173 13:54:10.992909 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8174 13:54:10.996407
8175 13:54:10.999064 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8176 13:54:11.002511 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8177 13:54:11.005648 [Gating] SW calibration Done
8178 13:54:11.005755 ==
8179 13:54:11.009452 Dram Type= 6, Freq= 0, CH_1, rank 0
8180 13:54:11.012640 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8181 13:54:11.012797 ==
8182 13:54:11.012890 RX Vref Scan: 0
8183 13:54:11.016288
8184 13:54:11.016373 RX Vref 0 -> 0, step: 1
8185 13:54:11.016473
8186 13:54:11.019541 RX Delay 0 -> 252, step: 8
8187 13:54:11.023178 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8188 13:54:11.026718 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8189 13:54:11.032853 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8190 13:54:11.035445 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8191 13:54:11.039272 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8192 13:54:11.042408 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8193 13:54:11.046419 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8194 13:54:11.052329 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8195 13:54:11.055905 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8196 13:54:11.059559 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8197 13:54:11.064047 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8198 13:54:11.065681 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8199 13:54:11.072548 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8200 13:54:11.075618 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8201 13:54:11.079286 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8202 13:54:11.083133 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8203 13:54:11.083683 ==
8204 13:54:11.086505 Dram Type= 6, Freq= 0, CH_1, rank 0
8205 13:54:11.092898 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8206 13:54:11.093450 ==
8207 13:54:11.093814 DQS Delay:
8208 13:54:11.096767 DQS0 = 0, DQS1 = 0
8209 13:54:11.097398 DQM Delay:
8210 13:54:11.097760 DQM0 = 129, DQM1 = 125
8211 13:54:11.099347 DQ Delay:
8212 13:54:11.102075 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8213 13:54:11.105321 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8214 13:54:11.109518 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8215 13:54:11.112913 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8216 13:54:11.113477
8217 13:54:11.113916
8218 13:54:11.114255 ==
8219 13:54:11.115400 Dram Type= 6, Freq= 0, CH_1, rank 0
8220 13:54:11.122364 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8221 13:54:11.122922 ==
8222 13:54:11.123287
8223 13:54:11.123620
8224 13:54:11.123938 TX Vref Scan disable
8225 13:54:11.125406 == TX Byte 0 ==
8226 13:54:11.128683 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8227 13:54:11.132131 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8228 13:54:11.135927 == TX Byte 1 ==
8229 13:54:11.139278 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8230 13:54:11.142083 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8231 13:54:11.145674 ==
8232 13:54:11.149106 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 13:54:11.152633 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8234 13:54:11.153238 ==
8235 13:54:11.164016
8236 13:54:11.168397 TX Vref early break, caculate TX vref
8237 13:54:11.170001 TX Vref=16, minBit 0, minWin=21, winSum=364
8238 13:54:11.173433 TX Vref=18, minBit 3, minWin=22, winSum=376
8239 13:54:11.177570 TX Vref=20, minBit 3, minWin=22, winSum=382
8240 13:54:11.181110 TX Vref=22, minBit 2, minWin=23, winSum=391
8241 13:54:11.183815 TX Vref=24, minBit 0, minWin=24, winSum=399
8242 13:54:11.190372 TX Vref=26, minBit 0, minWin=24, winSum=410
8243 13:54:11.193633 TX Vref=28, minBit 0, minWin=25, winSum=410
8244 13:54:11.197410 TX Vref=30, minBit 1, minWin=24, winSum=404
8245 13:54:11.199991 TX Vref=32, minBit 3, minWin=24, winSum=396
8246 13:54:11.203212 TX Vref=34, minBit 1, minWin=23, winSum=385
8247 13:54:11.210305 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 28
8248 13:54:11.210844
8249 13:54:11.214184 Final TX Range 0 Vref 28
8250 13:54:11.214635
8251 13:54:11.214986 ==
8252 13:54:11.217280 Dram Type= 6, Freq= 0, CH_1, rank 0
8253 13:54:11.219936 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8254 13:54:11.220407 ==
8255 13:54:11.220972
8256 13:54:11.221431
8257 13:54:11.223542 TX Vref Scan disable
8258 13:54:11.229955 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8259 13:54:11.230527 == TX Byte 0 ==
8260 13:54:11.233016 u2DelayCellOfst[0]=14 cells (4 PI)
8261 13:54:11.236820 u2DelayCellOfst[1]=10 cells (3 PI)
8262 13:54:11.239621 u2DelayCellOfst[2]=0 cells (0 PI)
8263 13:54:11.243630 u2DelayCellOfst[3]=7 cells (2 PI)
8264 13:54:11.247074 u2DelayCellOfst[4]=7 cells (2 PI)
8265 13:54:11.249450 u2DelayCellOfst[5]=14 cells (4 PI)
8266 13:54:11.253372 u2DelayCellOfst[6]=14 cells (4 PI)
8267 13:54:11.253925 u2DelayCellOfst[7]=7 cells (2 PI)
8268 13:54:11.259728 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8269 13:54:11.263252 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8270 13:54:11.266290 == TX Byte 1 ==
8271 13:54:11.266745 u2DelayCellOfst[8]=0 cells (0 PI)
8272 13:54:11.269445 u2DelayCellOfst[9]=7 cells (2 PI)
8273 13:54:11.272957 u2DelayCellOfst[10]=10 cells (3 PI)
8274 13:54:11.276222 u2DelayCellOfst[11]=3 cells (1 PI)
8275 13:54:11.279760 u2DelayCellOfst[12]=17 cells (5 PI)
8276 13:54:11.283372 u2DelayCellOfst[13]=21 cells (6 PI)
8277 13:54:11.286309 u2DelayCellOfst[14]=21 cells (6 PI)
8278 13:54:11.289948 u2DelayCellOfst[15]=21 cells (6 PI)
8279 13:54:11.292500 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8280 13:54:11.299833 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8281 13:54:11.300387 DramC Write-DBI on
8282 13:54:11.300804 ==
8283 13:54:11.302438 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 13:54:11.306001 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8285 13:54:11.309257 ==
8286 13:54:11.309707
8287 13:54:11.310063
8288 13:54:11.310393 TX Vref Scan disable
8289 13:54:11.313222 == TX Byte 0 ==
8290 13:54:11.316265 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8291 13:54:11.319187 == TX Byte 1 ==
8292 13:54:11.323523 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8293 13:54:11.326402 DramC Write-DBI off
8294 13:54:11.326955
8295 13:54:11.327309 [DATLAT]
8296 13:54:11.327639 Freq=1600, CH1 RK0
8297 13:54:11.327962
8298 13:54:11.329198 DATLAT Default: 0xf
8299 13:54:11.329646 0, 0xFFFF, sum = 0
8300 13:54:11.332377 1, 0xFFFF, sum = 0
8301 13:54:11.332883 2, 0xFFFF, sum = 0
8302 13:54:11.336615 3, 0xFFFF, sum = 0
8303 13:54:11.340249 4, 0xFFFF, sum = 0
8304 13:54:11.340921 5, 0xFFFF, sum = 0
8305 13:54:11.342698 6, 0xFFFF, sum = 0
8306 13:54:11.343155 7, 0xFFFF, sum = 0
8307 13:54:11.346782 8, 0xFFFF, sum = 0
8308 13:54:11.347358 9, 0xFFFF, sum = 0
8309 13:54:11.349393 10, 0xFFFF, sum = 0
8310 13:54:11.349853 11, 0xFFFF, sum = 0
8311 13:54:11.352287 12, 0xF7F, sum = 0
8312 13:54:11.352794 13, 0x0, sum = 1
8313 13:54:11.356066 14, 0x0, sum = 2
8314 13:54:11.356545 15, 0x0, sum = 3
8315 13:54:11.359587 16, 0x0, sum = 4
8316 13:54:11.360047 best_step = 14
8317 13:54:11.360404
8318 13:54:11.360781 ==
8319 13:54:11.363331 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 13:54:11.366416 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8321 13:54:11.369835 ==
8322 13:54:11.370397 RX Vref Scan: 1
8323 13:54:11.370758
8324 13:54:11.372165 Set Vref Range= 24 -> 127
8325 13:54:11.372615
8326 13:54:11.373016 RX Vref 24 -> 127, step: 1
8327 13:54:11.375905
8328 13:54:11.376393 RX Delay 3 -> 252, step: 4
8329 13:54:11.376800
8330 13:54:11.379167 Set Vref, RX VrefLevel [Byte0]: 24
8331 13:54:11.382290 [Byte1]: 24
8332 13:54:11.385823
8333 13:54:11.386366 Set Vref, RX VrefLevel [Byte0]: 25
8334 13:54:11.389179 [Byte1]: 25
8335 13:54:11.393685
8336 13:54:11.394172 Set Vref, RX VrefLevel [Byte0]: 26
8337 13:54:11.396961 [Byte1]: 26
8338 13:54:11.401334
8339 13:54:11.401835 Set Vref, RX VrefLevel [Byte0]: 27
8340 13:54:11.405945 [Byte1]: 27
8341 13:54:11.409173
8342 13:54:11.409719 Set Vref, RX VrefLevel [Byte0]: 28
8343 13:54:11.412293 [Byte1]: 28
8344 13:54:11.416625
8345 13:54:11.417234 Set Vref, RX VrefLevel [Byte0]: 29
8346 13:54:11.419969 [Byte1]: 29
8347 13:54:11.424468
8348 13:54:11.425086 Set Vref, RX VrefLevel [Byte0]: 30
8349 13:54:11.427519 [Byte1]: 30
8350 13:54:11.432884
8351 13:54:11.433433 Set Vref, RX VrefLevel [Byte0]: 31
8352 13:54:11.435035 [Byte1]: 31
8353 13:54:11.439840
8354 13:54:11.440390 Set Vref, RX VrefLevel [Byte0]: 32
8355 13:54:11.443067 [Byte1]: 32
8356 13:54:11.447119
8357 13:54:11.447669 Set Vref, RX VrefLevel [Byte0]: 33
8358 13:54:11.450899 [Byte1]: 33
8359 13:54:11.454625
8360 13:54:11.455070 Set Vref, RX VrefLevel [Byte0]: 34
8361 13:54:11.459386 [Byte1]: 34
8362 13:54:11.463355
8363 13:54:11.463799 Set Vref, RX VrefLevel [Byte0]: 35
8364 13:54:11.466219 [Byte1]: 35
8365 13:54:11.469807
8366 13:54:11.470317 Set Vref, RX VrefLevel [Byte0]: 36
8367 13:54:11.474353 [Byte1]: 36
8368 13:54:11.477927
8369 13:54:11.478484 Set Vref, RX VrefLevel [Byte0]: 37
8370 13:54:11.481620 [Byte1]: 37
8371 13:54:11.485356
8372 13:54:11.485922 Set Vref, RX VrefLevel [Byte0]: 38
8373 13:54:11.488982 [Byte1]: 38
8374 13:54:11.493026
8375 13:54:11.493474 Set Vref, RX VrefLevel [Byte0]: 39
8376 13:54:11.496434 [Byte1]: 39
8377 13:54:11.500997
8378 13:54:11.501447 Set Vref, RX VrefLevel [Byte0]: 40
8379 13:54:11.504214 [Byte1]: 40
8380 13:54:11.508316
8381 13:54:11.508801 Set Vref, RX VrefLevel [Byte0]: 41
8382 13:54:11.511890 [Byte1]: 41
8383 13:54:11.515945
8384 13:54:11.516493 Set Vref, RX VrefLevel [Byte0]: 42
8385 13:54:11.519536 [Byte1]: 42
8386 13:54:11.523440
8387 13:54:11.523973 Set Vref, RX VrefLevel [Byte0]: 43
8388 13:54:11.526904 [Byte1]: 43
8389 13:54:11.531630
8390 13:54:11.532071 Set Vref, RX VrefLevel [Byte0]: 44
8391 13:54:11.534863 [Byte1]: 44
8392 13:54:11.538649
8393 13:54:11.539096 Set Vref, RX VrefLevel [Byte0]: 45
8394 13:54:11.542547 [Byte1]: 45
8395 13:54:11.547662
8396 13:54:11.548202 Set Vref, RX VrefLevel [Byte0]: 46
8397 13:54:11.550359 [Byte1]: 46
8398 13:54:11.554380
8399 13:54:11.554928 Set Vref, RX VrefLevel [Byte0]: 47
8400 13:54:11.558067 [Byte1]: 47
8401 13:54:11.562413
8402 13:54:11.562951 Set Vref, RX VrefLevel [Byte0]: 48
8403 13:54:11.565328 [Byte1]: 48
8404 13:54:11.570042
8405 13:54:11.570580 Set Vref, RX VrefLevel [Byte0]: 49
8406 13:54:11.573223 [Byte1]: 49
8407 13:54:11.577358
8408 13:54:11.577898 Set Vref, RX VrefLevel [Byte0]: 50
8409 13:54:11.581320 [Byte1]: 50
8410 13:54:11.585247
8411 13:54:11.585787 Set Vref, RX VrefLevel [Byte0]: 51
8412 13:54:11.588147 [Byte1]: 51
8413 13:54:11.593097
8414 13:54:11.593642 Set Vref, RX VrefLevel [Byte0]: 52
8415 13:54:11.596453 [Byte1]: 52
8416 13:54:11.600556
8417 13:54:11.601159 Set Vref, RX VrefLevel [Byte0]: 53
8418 13:54:11.603566 [Byte1]: 53
8419 13:54:11.607855
8420 13:54:11.608299 Set Vref, RX VrefLevel [Byte0]: 54
8421 13:54:11.611602 [Byte1]: 54
8422 13:54:11.616228
8423 13:54:11.616831 Set Vref, RX VrefLevel [Byte0]: 55
8424 13:54:11.618718 [Byte1]: 55
8425 13:54:11.623413
8426 13:54:11.623958 Set Vref, RX VrefLevel [Byte0]: 56
8427 13:54:11.626830 [Byte1]: 56
8428 13:54:11.631051
8429 13:54:11.631599 Set Vref, RX VrefLevel [Byte0]: 57
8430 13:54:11.634407 [Byte1]: 57
8431 13:54:11.638808
8432 13:54:11.639253 Set Vref, RX VrefLevel [Byte0]: 58
8433 13:54:11.641639 [Byte1]: 58
8434 13:54:11.646757
8435 13:54:11.647302 Set Vref, RX VrefLevel [Byte0]: 59
8436 13:54:11.649277 [Byte1]: 59
8437 13:54:11.654095
8438 13:54:11.654648 Set Vref, RX VrefLevel [Byte0]: 60
8439 13:54:11.657485 [Byte1]: 60
8440 13:54:11.661651
8441 13:54:11.662194 Set Vref, RX VrefLevel [Byte0]: 61
8442 13:54:11.665307 [Byte1]: 61
8443 13:54:11.669548
8444 13:54:11.670096 Set Vref, RX VrefLevel [Byte0]: 62
8445 13:54:11.673274 [Byte1]: 62
8446 13:54:11.676915
8447 13:54:11.677461 Set Vref, RX VrefLevel [Byte0]: 63
8448 13:54:11.679773 [Byte1]: 63
8449 13:54:11.684501
8450 13:54:11.685098 Set Vref, RX VrefLevel [Byte0]: 64
8451 13:54:11.687713 [Byte1]: 64
8452 13:54:11.692076
8453 13:54:11.692531 Set Vref, RX VrefLevel [Byte0]: 65
8454 13:54:11.695198 [Byte1]: 65
8455 13:54:11.700076
8456 13:54:11.700629 Set Vref, RX VrefLevel [Byte0]: 66
8457 13:54:11.703050 [Byte1]: 66
8458 13:54:11.707509
8459 13:54:11.707992 Set Vref, RX VrefLevel [Byte0]: 67
8460 13:54:11.710971 [Byte1]: 67
8461 13:54:11.715810
8462 13:54:11.716354 Set Vref, RX VrefLevel [Byte0]: 68
8463 13:54:11.718954 [Byte1]: 68
8464 13:54:11.722993
8465 13:54:11.723465 Set Vref, RX VrefLevel [Byte0]: 69
8466 13:54:11.727196 [Byte1]: 69
8467 13:54:11.730535
8468 13:54:11.731079 Set Vref, RX VrefLevel [Byte0]: 70
8469 13:54:11.734249 [Byte1]: 70
8470 13:54:11.737971
8471 13:54:11.738413 Set Vref, RX VrefLevel [Byte0]: 71
8472 13:54:11.741554 [Byte1]: 71
8473 13:54:11.745361
8474 13:54:11.745808 Set Vref, RX VrefLevel [Byte0]: 72
8475 13:54:11.749355 [Byte1]: 72
8476 13:54:11.753558
8477 13:54:11.754132 Set Vref, RX VrefLevel [Byte0]: 73
8478 13:54:11.756541 [Byte1]: 73
8479 13:54:11.761156
8480 13:54:11.761703 Set Vref, RX VrefLevel [Byte0]: 74
8481 13:54:11.765338 [Byte1]: 74
8482 13:54:11.768562
8483 13:54:11.769158 Set Vref, RX VrefLevel [Byte0]: 75
8484 13:54:11.772261 [Byte1]: 75
8485 13:54:11.777065
8486 13:54:11.777615 Final RX Vref Byte 0 = 58 to rank0
8487 13:54:11.780655 Final RX Vref Byte 1 = 53 to rank0
8488 13:54:11.782909 Final RX Vref Byte 0 = 58 to rank1
8489 13:54:11.786586 Final RX Vref Byte 1 = 53 to rank1==
8490 13:54:11.789548 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 13:54:11.796249 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8492 13:54:11.796700 ==
8493 13:54:11.797118 DQS Delay:
8494 13:54:11.797449 DQS0 = 0, DQS1 = 0
8495 13:54:11.799129 DQM Delay:
8496 13:54:11.799576 DQM0 = 128, DQM1 = 122
8497 13:54:11.803670 DQ Delay:
8498 13:54:11.806548 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8499 13:54:11.809365 DQ4 =130, DQ5 =138, DQ6 =136, DQ7 =126
8500 13:54:11.812618 DQ8 =104, DQ9 =112, DQ10 =124, DQ11 =112
8501 13:54:11.815925 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8502 13:54:11.816503
8503 13:54:11.816947
8504 13:54:11.817300
8505 13:54:11.819763 [DramC_TX_OE_Calibration] TA2
8506 13:54:11.823158 Original DQ_B0 (3 6) =30, OEN = 27
8507 13:54:11.825548 Original DQ_B1 (3 6) =30, OEN = 27
8508 13:54:11.829425 24, 0x0, End_B0=24 End_B1=24
8509 13:54:11.829987 25, 0x0, End_B0=25 End_B1=25
8510 13:54:11.833107 26, 0x0, End_B0=26 End_B1=26
8511 13:54:11.836621 27, 0x0, End_B0=27 End_B1=27
8512 13:54:11.839274 28, 0x0, End_B0=28 End_B1=28
8513 13:54:11.842359 29, 0x0, End_B0=29 End_B1=29
8514 13:54:11.842920 30, 0x0, End_B0=30 End_B1=30
8515 13:54:11.845728 31, 0x5151, End_B0=30 End_B1=30
8516 13:54:11.849013 Byte0 end_step=30 best_step=27
8517 13:54:11.852335 Byte1 end_step=30 best_step=27
8518 13:54:11.856150 Byte0 TX OE(2T, 0.5T) = (3, 3)
8519 13:54:11.859240 Byte1 TX OE(2T, 0.5T) = (3, 3)
8520 13:54:11.859791
8521 13:54:11.860147
8522 13:54:11.865347 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8523 13:54:11.868867 CH1 RK0: MR19=303, MR18=2929
8524 13:54:11.875374 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8525 13:54:11.875914
8526 13:54:11.879146 ----->DramcWriteLeveling(PI) begin...
8527 13:54:11.879705 ==
8528 13:54:11.881997 Dram Type= 6, Freq= 0, CH_1, rank 1
8529 13:54:11.885456 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8530 13:54:11.886014 ==
8531 13:54:11.888301 Write leveling (Byte 0): 22 => 22
8532 13:54:11.892063 Write leveling (Byte 1): 20 => 20
8533 13:54:11.895763 DramcWriteLeveling(PI) end<-----
8534 13:54:11.896316
8535 13:54:11.896673 ==
8536 13:54:11.898448 Dram Type= 6, Freq= 0, CH_1, rank 1
8537 13:54:11.901608 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8538 13:54:11.905149 ==
8539 13:54:11.905725 [Gating] SW mode calibration
8540 13:54:11.914884 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8541 13:54:11.918839 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8542 13:54:11.921219 0 12 0 | B1->B0 | 3333 101 | 0 1 | (0 0) (1 1)
8543 13:54:11.928186 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8544 13:54:11.931654 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8545 13:54:11.934718 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8546 13:54:11.941252 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8547 13:54:11.944956 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8548 13:54:11.947967 0 12 24 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
8549 13:54:11.955138 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8550 13:54:11.957945 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8551 13:54:11.961876 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8552 13:54:11.969764 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8553 13:54:11.971358 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8554 13:54:11.975145 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8555 13:54:11.981677 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8556 13:54:11.985075 0 13 24 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8557 13:54:11.988267 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8558 13:54:11.991409 0 14 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8559 13:54:11.997685 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8560 13:54:12.001298 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8561 13:54:12.004498 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8562 13:54:12.011152 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8563 13:54:12.014947 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8564 13:54:12.018791 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8565 13:54:12.024653 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8566 13:54:12.027917 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8567 13:54:12.031298 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 13:54:12.038605 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 13:54:12.040827 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 13:54:12.044699 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 13:54:12.051362 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 13:54:12.054308 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 13:54:12.057753 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 13:54:12.063977 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 13:54:12.067410 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 13:54:12.070769 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 13:54:12.077431 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 13:54:12.080650 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 13:54:12.083835 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8580 13:54:12.090466 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8581 13:54:12.094678 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8582 13:54:12.096825 Total UI for P1: 0, mck2ui 16
8583 13:54:12.100601 best dqsien dly found for B0: ( 1, 0, 22)
8584 13:54:12.103536 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8585 13:54:12.106699 Total UI for P1: 0, mck2ui 16
8586 13:54:12.110341 best dqsien dly found for B1: ( 1, 0, 30)
8587 13:54:12.113388 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8588 13:54:12.117084 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8589 13:54:12.120275
8590 13:54:12.123870 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8591 13:54:12.128077 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8592 13:54:12.130634 [Gating] SW calibration Done
8593 13:54:12.131187 ==
8594 13:54:12.134806 Dram Type= 6, Freq= 0, CH_1, rank 1
8595 13:54:12.139300 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8596 13:54:12.139849 ==
8597 13:54:12.140251 RX Vref Scan: 0
8598 13:54:12.140693
8599 13:54:12.141480 RX Vref 0 -> 0, step: 1
8600 13:54:12.141855
8601 13:54:12.143706 RX Delay 0 -> 252, step: 8
8602 13:54:12.146842 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8603 13:54:12.150099 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8604 13:54:12.157915 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8605 13:54:12.160398 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8606 13:54:12.163569 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8607 13:54:12.166713 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8608 13:54:12.170314 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8609 13:54:12.173296 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8610 13:54:12.180454 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8611 13:54:12.183240 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8612 13:54:12.186978 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8613 13:54:12.189615 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8614 13:54:12.196613 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8615 13:54:12.199948 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8616 13:54:12.203922 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8617 13:54:12.206953 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8618 13:54:12.207504 ==
8619 13:54:12.209448 Dram Type= 6, Freq= 0, CH_1, rank 1
8620 13:54:12.216584 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8621 13:54:12.217190 ==
8622 13:54:12.217559 DQS Delay:
8623 13:54:12.220243 DQS0 = 0, DQS1 = 0
8624 13:54:12.220845 DQM Delay:
8625 13:54:12.221217 DQM0 = 130, DQM1 = 126
8626 13:54:12.223218 DQ Delay:
8627 13:54:12.226670 DQ0 =131, DQ1 =123, DQ2 =115, DQ3 =131
8628 13:54:12.229881 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8629 13:54:12.233258 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8630 13:54:12.236456 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8631 13:54:12.237077
8632 13:54:12.237446
8633 13:54:12.237781 ==
8634 13:54:12.239841 Dram Type= 6, Freq= 0, CH_1, rank 1
8635 13:54:12.243133 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8636 13:54:12.246214 ==
8637 13:54:12.246819
8638 13:54:12.247359
8639 13:54:12.247736 TX Vref Scan disable
8640 13:54:12.249886 == TX Byte 0 ==
8641 13:54:12.253831 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8642 13:54:12.256204 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8643 13:54:12.260044 == TX Byte 1 ==
8644 13:54:12.262746 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8645 13:54:12.265864 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8646 13:54:12.269368 ==
8647 13:54:12.269917 Dram Type= 6, Freq= 0, CH_1, rank 1
8648 13:54:12.276249 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8649 13:54:12.276847 ==
8650 13:54:12.288875
8651 13:54:12.292534 TX Vref early break, caculate TX vref
8652 13:54:12.295339 TX Vref=16, minBit 7, minWin=22, winSum=381
8653 13:54:12.299221 TX Vref=18, minBit 3, minWin=22, winSum=385
8654 13:54:12.301995 TX Vref=20, minBit 0, minWin=22, winSum=394
8655 13:54:12.305753 TX Vref=22, minBit 1, minWin=24, winSum=406
8656 13:54:12.308680 TX Vref=24, minBit 3, minWin=23, winSum=409
8657 13:54:12.315534 TX Vref=26, minBit 2, minWin=24, winSum=419
8658 13:54:12.318711 TX Vref=28, minBit 0, minWin=25, winSum=421
8659 13:54:12.321975 TX Vref=30, minBit 0, minWin=24, winSum=412
8660 13:54:12.325202 TX Vref=32, minBit 0, minWin=24, winSum=410
8661 13:54:12.328473 TX Vref=34, minBit 0, minWin=23, winSum=399
8662 13:54:12.332076 TX Vref=36, minBit 0, minWin=22, winSum=390
8663 13:54:12.339889 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8664 13:54:12.340445
8665 13:54:12.341696 Final TX Range 0 Vref 28
8666 13:54:12.342149
8667 13:54:12.342506 ==
8668 13:54:12.345406 Dram Type= 6, Freq= 0, CH_1, rank 1
8669 13:54:12.348653 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8670 13:54:12.349235 ==
8671 13:54:12.349674
8672 13:54:12.351309
8673 13:54:12.351873 TX Vref Scan disable
8674 13:54:12.359099 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8675 13:54:12.359626 == TX Byte 0 ==
8676 13:54:12.361393 u2DelayCellOfst[0]=14 cells (4 PI)
8677 13:54:12.364662 u2DelayCellOfst[1]=10 cells (3 PI)
8678 13:54:12.368379 u2DelayCellOfst[2]=0 cells (0 PI)
8679 13:54:12.371587 u2DelayCellOfst[3]=3 cells (1 PI)
8680 13:54:12.374792 u2DelayCellOfst[4]=7 cells (2 PI)
8681 13:54:12.378483 u2DelayCellOfst[5]=14 cells (4 PI)
8682 13:54:12.381555 u2DelayCellOfst[6]=14 cells (4 PI)
8683 13:54:12.385308 u2DelayCellOfst[7]=3 cells (1 PI)
8684 13:54:12.388271 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8685 13:54:12.391380 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8686 13:54:12.394617 == TX Byte 1 ==
8687 13:54:12.397771 u2DelayCellOfst[8]=0 cells (0 PI)
8688 13:54:12.400927 u2DelayCellOfst[9]=3 cells (1 PI)
8689 13:54:12.404996 u2DelayCellOfst[10]=10 cells (3 PI)
8690 13:54:12.405547 u2DelayCellOfst[11]=0 cells (0 PI)
8691 13:54:12.407844 u2DelayCellOfst[12]=14 cells (4 PI)
8692 13:54:12.411218 u2DelayCellOfst[13]=17 cells (5 PI)
8693 13:54:12.414122 u2DelayCellOfst[14]=17 cells (5 PI)
8694 13:54:12.417930 u2DelayCellOfst[15]=17 cells (5 PI)
8695 13:54:12.424527 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8696 13:54:12.428196 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8697 13:54:12.428802 DramC Write-DBI on
8698 13:54:12.429176 ==
8699 13:54:12.431367 Dram Type= 6, Freq= 0, CH_1, rank 1
8700 13:54:12.438473 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8701 13:54:12.439032 ==
8702 13:54:12.439394
8703 13:54:12.439722
8704 13:54:12.441191 TX Vref Scan disable
8705 13:54:12.441640 == TX Byte 0 ==
8706 13:54:12.448914 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8707 13:54:12.449464 == TX Byte 1 ==
8708 13:54:12.451591 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8709 13:54:12.454566 DramC Write-DBI off
8710 13:54:12.455118
8711 13:54:12.455478 [DATLAT]
8712 13:54:12.457050 Freq=1600, CH1 RK1
8713 13:54:12.457501
8714 13:54:12.457851 DATLAT Default: 0xe
8715 13:54:12.460518 0, 0xFFFF, sum = 0
8716 13:54:12.461082 1, 0xFFFF, sum = 0
8717 13:54:12.464857 2, 0xFFFF, sum = 0
8718 13:54:12.465415 3, 0xFFFF, sum = 0
8719 13:54:12.467102 4, 0xFFFF, sum = 0
8720 13:54:12.467561 5, 0xFFFF, sum = 0
8721 13:54:12.470340 6, 0xFFFF, sum = 0
8722 13:54:12.470902 7, 0xFFFF, sum = 0
8723 13:54:12.473909 8, 0xFFFF, sum = 0
8724 13:54:12.477883 9, 0xFFFF, sum = 0
8725 13:54:12.478445 10, 0xFFFF, sum = 0
8726 13:54:12.480870 11, 0xFFFF, sum = 0
8727 13:54:12.481432 12, 0xF7F, sum = 0
8728 13:54:12.483848 13, 0x0, sum = 1
8729 13:54:12.484404 14, 0x0, sum = 2
8730 13:54:12.487107 15, 0x0, sum = 3
8731 13:54:12.487665 16, 0x0, sum = 4
8732 13:54:12.488027 best_step = 14
8733 13:54:12.488356
8734 13:54:12.490536 ==
8735 13:54:12.493825 Dram Type= 6, Freq= 0, CH_1, rank 1
8736 13:54:12.496848 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8737 13:54:12.497299 ==
8738 13:54:12.497659 RX Vref Scan: 0
8739 13:54:12.497994
8740 13:54:12.500506 RX Vref 0 -> 0, step: 1
8741 13:54:12.501106
8742 13:54:12.503708 RX Delay 3 -> 252, step: 4
8743 13:54:12.507862 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8744 13:54:12.510564 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8745 13:54:12.517099 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8746 13:54:12.520580 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8747 13:54:12.523663 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8748 13:54:12.526815 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8749 13:54:12.531004 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8750 13:54:12.537463 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8751 13:54:12.540142 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8752 13:54:12.543695 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8753 13:54:12.547157 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8754 13:54:12.551204 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8755 13:54:12.556976 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8756 13:54:12.560539 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8757 13:54:12.563586 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8758 13:54:12.566539 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8759 13:54:12.567004 ==
8760 13:54:12.569795 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 13:54:12.577089 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8762 13:54:12.577557 ==
8763 13:54:12.577915 DQS Delay:
8764 13:54:12.580040 DQS0 = 0, DQS1 = 0
8765 13:54:12.580581 DQM Delay:
8766 13:54:12.581017 DQM0 = 127, DQM1 = 122
8767 13:54:12.584083 DQ Delay:
8768 13:54:12.587181 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =122
8769 13:54:12.590216 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8770 13:54:12.593059 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8771 13:54:12.596343 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8772 13:54:12.596960
8773 13:54:12.597333
8774 13:54:12.597671
8775 13:54:12.599462 [DramC_TX_OE_Calibration] TA2
8776 13:54:12.602996 Original DQ_B0 (3 6) =30, OEN = 27
8777 13:54:12.606274 Original DQ_B1 (3 6) =30, OEN = 27
8778 13:54:12.610130 24, 0x0, End_B0=24 End_B1=24
8779 13:54:12.613325 25, 0x0, End_B0=25 End_B1=25
8780 13:54:12.613788 26, 0x0, End_B0=26 End_B1=26
8781 13:54:12.616436 27, 0x0, End_B0=27 End_B1=27
8782 13:54:12.619488 28, 0x0, End_B0=28 End_B1=28
8783 13:54:12.622630 29, 0x0, End_B0=29 End_B1=29
8784 13:54:12.623096 30, 0x0, End_B0=30 End_B1=30
8785 13:54:12.626487 31, 0x4545, End_B0=30 End_B1=30
8786 13:54:12.629671 Byte0 end_step=30 best_step=27
8787 13:54:12.632879 Byte1 end_step=30 best_step=27
8788 13:54:12.635941 Byte0 TX OE(2T, 0.5T) = (3, 3)
8789 13:54:12.639204 Byte1 TX OE(2T, 0.5T) = (3, 3)
8790 13:54:12.639618
8791 13:54:12.639946
8792 13:54:12.645736 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8793 13:54:12.649432 CH1 RK1: MR19=303, MR18=1D1D
8794 13:54:12.656345 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8795 13:54:12.659435 [RxdqsGatingPostProcess] freq 1600
8796 13:54:12.662504 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8797 13:54:12.665619 Pre-setting of DQS Precalculation
8798 13:54:12.672622 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8799 13:54:12.678892 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8800 13:54:12.686142 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8801 13:54:12.686711
8802 13:54:12.687072
8803 13:54:12.688755 [Calibration Summary] 3200 Mbps
8804 13:54:12.692321 CH 0, Rank 0
8805 13:54:12.692950 SW Impedance : PASS
8806 13:54:12.695652 DUTY Scan : NO K
8807 13:54:12.698943 ZQ Calibration : PASS
8808 13:54:12.699497 Jitter Meter : NO K
8809 13:54:12.702342 CBT Training : PASS
8810 13:54:12.705654 Write leveling : PASS
8811 13:54:12.706155 RX DQS gating : PASS
8812 13:54:12.709113 RX DQ/DQS(RDDQC) : PASS
8813 13:54:12.709571 TX DQ/DQS : PASS
8814 13:54:12.712653 RX DATLAT : PASS
8815 13:54:12.715764 RX DQ/DQS(Engine): PASS
8816 13:54:12.716238 TX OE : PASS
8817 13:54:12.718845 All Pass.
8818 13:54:12.719400
8819 13:54:12.719767 CH 0, Rank 1
8820 13:54:12.722175 SW Impedance : PASS
8821 13:54:12.722724 DUTY Scan : NO K
8822 13:54:12.725617 ZQ Calibration : PASS
8823 13:54:12.728679 Jitter Meter : NO K
8824 13:54:12.729186 CBT Training : PASS
8825 13:54:12.731944 Write leveling : PASS
8826 13:54:12.736882 RX DQS gating : PASS
8827 13:54:12.737430 RX DQ/DQS(RDDQC) : PASS
8828 13:54:12.738719 TX DQ/DQS : PASS
8829 13:54:12.741670 RX DATLAT : PASS
8830 13:54:12.742128 RX DQ/DQS(Engine): PASS
8831 13:54:12.747115 TX OE : PASS
8832 13:54:12.747662 All Pass.
8833 13:54:12.748029
8834 13:54:12.748810 CH 1, Rank 0
8835 13:54:12.749178 SW Impedance : PASS
8836 13:54:12.751889 DUTY Scan : NO K
8837 13:54:12.755746 ZQ Calibration : PASS
8838 13:54:12.756293 Jitter Meter : NO K
8839 13:54:12.758974 CBT Training : PASS
8840 13:54:12.762548 Write leveling : PASS
8841 13:54:12.763100 RX DQS gating : PASS
8842 13:54:12.765345 RX DQ/DQS(RDDQC) : PASS
8843 13:54:12.768800 TX DQ/DQS : PASS
8844 13:54:12.769352 RX DATLAT : PASS
8845 13:54:12.772215 RX DQ/DQS(Engine): PASS
8846 13:54:12.772817 TX OE : PASS
8847 13:54:12.775289 All Pass.
8848 13:54:12.775837
8849 13:54:12.776278 CH 1, Rank 1
8850 13:54:12.778922 SW Impedance : PASS
8851 13:54:12.779470 DUTY Scan : NO K
8852 13:54:12.782177 ZQ Calibration : PASS
8853 13:54:12.784933 Jitter Meter : NO K
8854 13:54:12.785483 CBT Training : PASS
8855 13:54:12.788599 Write leveling : PASS
8856 13:54:12.791283 RX DQS gating : PASS
8857 13:54:12.791741 RX DQ/DQS(RDDQC) : PASS
8858 13:54:12.795182 TX DQ/DQS : PASS
8859 13:54:12.798263 RX DATLAT : PASS
8860 13:54:12.798724 RX DQ/DQS(Engine): PASS
8861 13:54:12.801693 TX OE : PASS
8862 13:54:12.802152 All Pass.
8863 13:54:12.802517
8864 13:54:12.805295 DramC Write-DBI on
8865 13:54:12.808088 PER_BANK_REFRESH: Hybrid Mode
8866 13:54:12.808631 TX_TRACKING: ON
8867 13:54:12.818534 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8868 13:54:12.825359 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8869 13:54:12.831335 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8870 13:54:12.834717 [FAST_K] Save calibration result to emmc
8871 13:54:12.838564 sync common calibartion params.
8872 13:54:12.841136 sync cbt_mode0:0, 1:0
8873 13:54:12.845122 dram_init: ddr_geometry: 0
8874 13:54:12.845590 dram_init: ddr_geometry: 0
8875 13:54:12.848012 dram_init: ddr_geometry: 0
8876 13:54:12.851301 0:dram_rank_size:80000000
8877 13:54:12.854776 1:dram_rank_size:80000000
8878 13:54:12.857938 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8879 13:54:12.861176 DFS_SHUFFLE_HW_MODE: ON
8880 13:54:12.864566 dramc_set_vcore_voltage set vcore to 725000
8881 13:54:12.867735 Read voltage for 1600, 0
8882 13:54:12.868294 Vio18 = 0
8883 13:54:12.868660 Vcore = 725000
8884 13:54:12.870726 Vdram = 0
8885 13:54:12.871180 Vddq = 0
8886 13:54:12.871588 Vmddr = 0
8887 13:54:12.874082 switch to 3200 Mbps bootup
8888 13:54:12.878402 [DramcRunTimeConfig]
8889 13:54:12.878964 PHYPLL
8890 13:54:12.879331 DPM_CONTROL_AFTERK: ON
8891 13:54:12.880794 PER_BANK_REFRESH: ON
8892 13:54:12.884404 REFRESH_OVERHEAD_REDUCTION: ON
8893 13:54:12.885007 CMD_PICG_NEW_MODE: OFF
8894 13:54:12.887330 XRTWTW_NEW_MODE: ON
8895 13:54:12.887782 XRTRTR_NEW_MODE: ON
8896 13:54:12.890706 TX_TRACKING: ON
8897 13:54:12.891165 RDSEL_TRACKING: OFF
8898 13:54:12.893981 DQS Precalculation for DVFS: ON
8899 13:54:12.897446 RX_TRACKING: OFF
8900 13:54:12.897906 HW_GATING DBG: ON
8901 13:54:12.900610 ZQCS_ENABLE_LP4: ON
8902 13:54:12.901069 RX_PICG_NEW_MODE: ON
8903 13:54:12.905497 TX_PICG_NEW_MODE: ON
8904 13:54:12.907761 ENABLE_RX_DCM_DPHY: ON
8905 13:54:12.908295 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8906 13:54:12.910555 DUMMY_READ_FOR_TRACKING: OFF
8907 13:54:12.914451 !!! SPM_CONTROL_AFTERK: OFF
8908 13:54:12.918429 !!! SPM could not control APHY
8909 13:54:12.920659 IMPEDANCE_TRACKING: ON
8910 13:54:12.921274 TEMP_SENSOR: ON
8911 13:54:12.924315 HW_SAVE_FOR_SR: OFF
8912 13:54:12.924851 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8913 13:54:12.930804 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8914 13:54:12.931350 Read ODT Tracking: ON
8915 13:54:12.933884 Refresh Rate DeBounce: ON
8916 13:54:12.934439 DFS_NO_QUEUE_FLUSH: ON
8917 13:54:12.937277 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8918 13:54:12.940521 ENABLE_DFS_RUNTIME_MRW: OFF
8919 13:54:12.944355 DDR_RESERVE_NEW_MODE: ON
8920 13:54:12.944844 MR_CBT_SWITCH_FREQ: ON
8921 13:54:12.947682 =========================
8922 13:54:12.967381 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8923 13:54:12.969398 dram_init: ddr_geometry: 0
8924 13:54:12.988002 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8925 13:54:12.991090 dram_init: dram init end (result: 0)
8926 13:54:12.997570 DRAM-K: Full calibration passed in 23409 msecs
8927 13:54:13.001366 MRC: failed to locate region type 0.
8928 13:54:13.002077 DRAM rank0 size:0x80000000,
8929 13:54:13.004484 DRAM rank1 size=0x80000000
8930 13:54:13.014242 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8931 13:54:13.021675 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8932 13:54:13.027399 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8933 13:54:13.034877 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8934 13:54:13.038958 DRAM rank0 size:0x80000000,
8935 13:54:13.040993 DRAM rank1 size=0x80000000
8936 13:54:13.041449 CBMEM:
8937 13:54:13.043910 IMD: root @ 0xfffff000 254 entries.
8938 13:54:13.047191 IMD: root @ 0xffffec00 62 entries.
8939 13:54:13.050736 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8940 13:54:13.053939 WARNING: RO_VPD is uninitialized or empty.
8941 13:54:13.060343 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8942 13:54:13.067510 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8943 13:54:13.080172 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8944 13:54:13.091718 BS: romstage times (exec / console): total (unknown) / 22952 ms
8945 13:54:13.092270
8946 13:54:13.092629
8947 13:54:13.101077 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8948 13:54:13.104425 ARM64: Exception handlers installed.
8949 13:54:13.108372 ARM64: Testing exception
8950 13:54:13.112043 ARM64: Done test exception
8951 13:54:13.112668 Enumerating buses...
8952 13:54:13.115643 Show all devs... Before device enumeration.
8953 13:54:13.118326 Root Device: enabled 1
8954 13:54:13.121589 CPU_CLUSTER: 0: enabled 1
8955 13:54:13.122141 CPU: 00: enabled 1
8956 13:54:13.124207 Compare with tree...
8957 13:54:13.124657 Root Device: enabled 1
8958 13:54:13.127839 CPU_CLUSTER: 0: enabled 1
8959 13:54:13.131274 CPU: 00: enabled 1
8960 13:54:13.131945 Root Device scanning...
8961 13:54:13.134598 scan_static_bus for Root Device
8962 13:54:13.137602 CPU_CLUSTER: 0 enabled
8963 13:54:13.141090 scan_static_bus for Root Device done
8964 13:54:13.144675 scan_bus: bus Root Device finished in 8 msecs
8965 13:54:13.145168 done
8966 13:54:13.150868 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8967 13:54:13.154593 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8968 13:54:13.161171 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8969 13:54:13.165056 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8970 13:54:13.167433 Allocating resources...
8971 13:54:13.170887 Reading resources...
8972 13:54:13.174423 Root Device read_resources bus 0 link: 0
8973 13:54:13.175096 DRAM rank0 size:0x80000000,
8974 13:54:13.178093 DRAM rank1 size=0x80000000
8975 13:54:13.180423 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8976 13:54:13.184555 CPU: 00 missing read_resources
8977 13:54:13.191137 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8978 13:54:13.194529 Root Device read_resources bus 0 link: 0 done
8979 13:54:13.195013 Done reading resources.
8980 13:54:13.200589 Show resources in subtree (Root Device)...After reading.
8981 13:54:13.203494 Root Device child on link 0 CPU_CLUSTER: 0
8982 13:54:13.207289 CPU_CLUSTER: 0 child on link 0 CPU: 00
8983 13:54:13.217195 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8984 13:54:13.217802 CPU: 00
8985 13:54:13.221313 Root Device assign_resources, bus 0 link: 0
8986 13:54:13.223893 CPU_CLUSTER: 0 missing set_resources
8987 13:54:13.230359 Root Device assign_resources, bus 0 link: 0 done
8988 13:54:13.230818 Done setting resources.
8989 13:54:13.236813 Show resources in subtree (Root Device)...After assigning values.
8990 13:54:13.239873 Root Device child on link 0 CPU_CLUSTER: 0
8991 13:54:13.243997 CPU_CLUSTER: 0 child on link 0 CPU: 00
8992 13:54:13.253941 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8993 13:54:13.254465 CPU: 00
8994 13:54:13.256891 Done allocating resources.
8995 13:54:13.263085 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8996 13:54:13.263498 Enabling resources...
8997 13:54:13.263859 done.
8998 13:54:13.270267 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8999 13:54:13.270786 Initializing devices...
9000 13:54:13.273289 Root Device init
9001 13:54:13.273741 init hardware done!
9002 13:54:13.277283 0x00000018: ctrlr->caps
9003 13:54:13.279646 52.000 MHz: ctrlr->f_max
9004 13:54:13.280112 0.400 MHz: ctrlr->f_min
9005 13:54:13.283335 0x40ff8080: ctrlr->voltages
9006 13:54:13.286802 sclk: 390625
9007 13:54:13.287258 Bus Width = 1
9008 13:54:13.287615 sclk: 390625
9009 13:54:13.290031 Bus Width = 1
9010 13:54:13.290584 Early init status = 3
9011 13:54:13.296930 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9012 13:54:13.300327 in-header: 03 fc 00 00 01 00 00 00
9013 13:54:13.303160 in-data: 00
9014 13:54:13.306367 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9015 13:54:13.310376 in-header: 03 fd 00 00 00 00 00 00
9016 13:54:13.313606 in-data:
9017 13:54:13.318671 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9018 13:54:13.320105 in-header: 03 fc 00 00 01 00 00 00
9019 13:54:13.323641 in-data: 00
9020 13:54:13.326680 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9021 13:54:13.332039 in-header: 03 fd 00 00 00 00 00 00
9022 13:54:13.334667 in-data:
9023 13:54:13.338663 [SSUSB] Setting up USB HOST controller...
9024 13:54:13.341554 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9025 13:54:13.344893 [SSUSB] phy power-on done.
9026 13:54:13.348498 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9027 13:54:13.355443 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9028 13:54:13.358853 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9029 13:54:13.365024 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9030 13:54:13.371568 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9031 13:54:13.378235 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9032 13:54:13.384832 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9033 13:54:13.391273 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9034 13:54:13.394490 SPM: binary array size = 0x9dc
9035 13:54:13.398468 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9036 13:54:13.405638 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9037 13:54:13.411182 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9038 13:54:13.414062 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9039 13:54:13.421668 configure_display: Starting display init
9040 13:54:13.455056 anx7625_power_on_init: Init interface.
9041 13:54:13.457751 anx7625_disable_pd_protocol: Disabled PD feature.
9042 13:54:13.461874 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9043 13:54:13.489385 anx7625_start_dp_work: Secure OCM version=00
9044 13:54:13.492213 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9045 13:54:13.507141 sp_tx_get_edid_block: EDID Block = 1
9046 13:54:13.610422 Extracted contents:
9047 13:54:13.613139 header: 00 ff ff ff ff ff ff 00
9048 13:54:13.615977 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9049 13:54:13.620006 version: 01 04
9050 13:54:13.622907 basic params: 95 1f 11 78 0a
9051 13:54:13.626844 chroma info: 76 90 94 55 54 90 27 21 50 54
9052 13:54:13.630586 established: 00 00 00
9053 13:54:13.636382 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9054 13:54:13.640500 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9055 13:54:13.646022 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9056 13:54:13.653167 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9057 13:54:13.659684 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9058 13:54:13.663280 extensions: 00
9059 13:54:13.663827 checksum: fb
9060 13:54:13.664183
9061 13:54:13.666190 Manufacturer: IVO Model 57d Serial Number 0
9062 13:54:13.668925 Made week 0 of 2020
9063 13:54:13.672293 EDID version: 1.4
9064 13:54:13.672792 Digital display
9065 13:54:13.675849 6 bits per primary color channel
9066 13:54:13.676307 DisplayPort interface
9067 13:54:13.679624 Maximum image size: 31 cm x 17 cm
9068 13:54:13.682973 Gamma: 220%
9069 13:54:13.683727 Check DPMS levels
9070 13:54:13.686302 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9071 13:54:13.692276 First detailed timing is preferred timing
9072 13:54:13.692878 Established timings supported:
9073 13:54:13.695615 Standard timings supported:
9074 13:54:13.699112 Detailed timings
9075 13:54:13.702131 Hex of detail: 383680a07038204018303c0035ae10000019
9076 13:54:13.709420 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9077 13:54:13.712419 0780 0798 07c8 0820 hborder 0
9078 13:54:13.715802 0438 043b 0447 0458 vborder 0
9079 13:54:13.718812 -hsync -vsync
9080 13:54:13.719268 Did detailed timing
9081 13:54:13.725798 Hex of detail: 000000000000000000000000000000000000
9082 13:54:13.728897 Manufacturer-specified data, tag 0
9083 13:54:13.732086 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9084 13:54:13.735656 ASCII string: InfoVision
9085 13:54:13.739267 Hex of detail: 000000fe00523134304e574635205248200a
9086 13:54:13.742355 ASCII string: R140NWF5 RH
9087 13:54:13.742815 Checksum
9088 13:54:13.745345 Checksum: 0xfb (valid)
9089 13:54:13.749297 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9090 13:54:13.752341 DSI data_rate: 832800000 bps
9091 13:54:13.758475 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9092 13:54:13.761678 anx7625_parse_edid: pixelclock(138800).
9093 13:54:13.765121 hactive(1920), hsync(48), hfp(24), hbp(88)
9094 13:54:13.768338 vactive(1080), vsync(12), vfp(3), vbp(17)
9095 13:54:13.771979 anx7625_dsi_config: config dsi.
9096 13:54:13.778007 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9097 13:54:13.791481 anx7625_dsi_config: success to config DSI
9098 13:54:13.795331 anx7625_dp_start: MIPI phy setup OK.
9099 13:54:13.798381 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9100 13:54:13.801725 mtk_ddp_mode_set invalid vrefresh 60
9101 13:54:13.805295 main_disp_path_setup
9102 13:54:13.805794 ovl_layer_smi_id_en
9103 13:54:13.808368 ovl_layer_smi_id_en
9104 13:54:13.808984 ccorr_config
9105 13:54:13.809353 aal_config
9106 13:54:13.811602 gamma_config
9107 13:54:13.812055 postmask_config
9108 13:54:13.815239 dither_config
9109 13:54:13.817945 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9110 13:54:13.825485 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9111 13:54:13.829171 Root Device init finished in 551 msecs
9112 13:54:13.831667 CPU_CLUSTER: 0 init
9113 13:54:13.838689 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9114 13:54:13.841832 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9115 13:54:13.845036 APU_MBOX 0x190000b0 = 0x10001
9116 13:54:13.848603 APU_MBOX 0x190001b0 = 0x10001
9117 13:54:13.851780 APU_MBOX 0x190005b0 = 0x10001
9118 13:54:13.855859 APU_MBOX 0x190006b0 = 0x10001
9119 13:54:13.858369 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9120 13:54:13.870923 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9121 13:54:13.883109 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9122 13:54:13.889919 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9123 13:54:13.901115 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9124 13:54:13.910900 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9125 13:54:13.914412 CPU_CLUSTER: 0 init finished in 81 msecs
9126 13:54:13.916863 Devices initialized
9127 13:54:13.920217 Show all devs... After init.
9128 13:54:13.920773 Root Device: enabled 1
9129 13:54:13.923387 CPU_CLUSTER: 0: enabled 1
9130 13:54:13.927507 CPU: 00: enabled 1
9131 13:54:13.930794 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9132 13:54:13.933441 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9133 13:54:13.937115 ELOG: NV offset 0x57f000 size 0x1000
9134 13:54:13.943748 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9135 13:54:13.950572 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9136 13:54:13.953683 ELOG: Event(17) added with size 13 at 2024-02-01 13:54:14 UTC
9137 13:54:13.956695 out: cmd=0x121: 03 db 21 01 00 00 00 00
9138 13:54:13.961991 in-header: 03 0e 00 00 2c 00 00 00
9139 13:54:13.973988 in-data: 55 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9140 13:54:13.981197 ELOG: Event(A1) added with size 10 at 2024-02-01 13:54:14 UTC
9141 13:54:13.987841 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9142 13:54:13.994510 ELOG: Event(A0) added with size 9 at 2024-02-01 13:54:14 UTC
9143 13:54:13.997522 elog_add_boot_reason: Logged dev mode boot
9144 13:54:14.001133 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9145 13:54:14.004324 Finalize devices...
9146 13:54:14.004975 Devices finalized
9147 13:54:14.010687 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9148 13:54:14.014788 Writing coreboot table at 0xffe64000
9149 13:54:14.017622 0. 000000000010a000-0000000000113fff: RAMSTAGE
9150 13:54:14.020813 1. 0000000040000000-00000000400fffff: RAM
9151 13:54:14.028128 2. 0000000040100000-000000004032afff: RAMSTAGE
9152 13:54:14.031321 3. 000000004032b000-00000000545fffff: RAM
9153 13:54:14.034322 4. 0000000054600000-000000005465ffff: BL31
9154 13:54:14.036857 5. 0000000054660000-00000000ffe63fff: RAM
9155 13:54:14.043654 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9156 13:54:14.046970 7. 0000000100000000-000000013fffffff: RAM
9157 13:54:14.050317 Passing 5 GPIOs to payload:
9158 13:54:14.054051 NAME | PORT | POLARITY | VALUE
9159 13:54:14.056781 EC in RW | 0x000000aa | low | undefined
9160 13:54:14.064088 EC interrupt | 0x00000005 | low | undefined
9161 13:54:14.067869 TPM interrupt | 0x000000ab | high | undefined
9162 13:54:14.074237 SD card detect | 0x00000011 | high | undefined
9163 13:54:14.076942 speaker enable | 0x00000093 | high | undefined
9164 13:54:14.079931 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9165 13:54:14.084016 in-header: 03 ee 00 00 02 00 00 00
9166 13:54:14.086897 in-data: 0d 00
9167 13:54:14.087505 ADC[4]: Raw value=668590 ID=5
9168 13:54:14.089938 ADC[3]: Raw value=212549 ID=1
9169 13:54:14.093209 RAM Code: 0x51
9170 13:54:14.093684 ADC[6]: Raw value=74410 ID=0
9171 13:54:14.096783 ADC[5]: Raw value=211444 ID=1
9172 13:54:14.099786 SKU Code: 0x1
9173 13:54:14.103412 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e1b
9174 13:54:14.106909 coreboot table: 964 bytes.
9175 13:54:14.111897 IMD ROOT 0. 0xfffff000 0x00001000
9176 13:54:14.113390 IMD SMALL 1. 0xffffe000 0x00001000
9177 13:54:14.117058 RO MCACHE 2. 0xffffc000 0x00001104
9178 13:54:14.119683 CONSOLE 3. 0xfff7c000 0x00080000
9179 13:54:14.123193 FMAP 4. 0xfff7b000 0x00000452
9180 13:54:14.127251 TIME STAMP 5. 0xfff7a000 0x00000910
9181 13:54:14.129497 VBOOT WORK 6. 0xfff66000 0x00014000
9182 13:54:14.133219 RAMOOPS 7. 0xffe66000 0x00100000
9183 13:54:14.136083 COREBOOT 8. 0xffe64000 0x00002000
9184 13:54:14.136544 IMD small region:
9185 13:54:14.140099 IMD ROOT 0. 0xffffec00 0x00000400
9186 13:54:14.146409 VPD 1. 0xffffeb80 0x0000006c
9187 13:54:14.149429 MMC STATUS 2. 0xffffeb60 0x00000004
9188 13:54:14.153303 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9189 13:54:14.156678 Probing TPM: done!
9190 13:54:14.159947 Connected to device vid:did:rid of 1ae0:0028:00
9191 13:54:14.170222 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9192 13:54:14.173626 Initialized TPM device CR50 revision 0
9193 13:54:14.176789 Checking cr50 for pending updates
9194 13:54:14.180635 Reading cr50 TPM mode
9195 13:54:14.189688 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9196 13:54:14.196009 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9197 13:54:14.236061 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9198 13:54:14.239505 Checking segment from ROM address 0x40100000
9199 13:54:14.242957 Checking segment from ROM address 0x4010001c
9200 13:54:14.248981 Loading segment from ROM address 0x40100000
9201 13:54:14.249444 code (compression=0)
9202 13:54:14.259406 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9203 13:54:14.265862 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9204 13:54:14.266321 it's not compressed!
9205 13:54:14.272602 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9206 13:54:14.279486 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9207 13:54:14.296540 Loading segment from ROM address 0x4010001c
9208 13:54:14.297153 Entry Point 0x80000000
9209 13:54:14.299984 Loaded segments
9210 13:54:14.303478 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9211 13:54:14.309763 Jumping to boot code at 0x80000000(0xffe64000)
9212 13:54:14.316877 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9213 13:54:14.323990 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9214 13:54:14.331260 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9215 13:54:14.333933 Checking segment from ROM address 0x40100000
9216 13:54:14.338725 Checking segment from ROM address 0x4010001c
9217 13:54:14.343896 Loading segment from ROM address 0x40100000
9218 13:54:14.344460 code (compression=1)
9219 13:54:14.351287 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9220 13:54:14.360826 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9221 13:54:14.361390 using LZMA
9222 13:54:14.369313 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9223 13:54:14.375825 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9224 13:54:14.379060 Loading segment from ROM address 0x4010001c
9225 13:54:14.379521 Entry Point 0x54601000
9226 13:54:14.382682 Loaded segments
9227 13:54:14.385421 NOTICE: MT8192 bl31_setup
9228 13:54:14.393486 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9229 13:54:14.395643 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9230 13:54:14.399396 WARNING: region 0:
9231 13:54:14.402579 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9232 13:54:14.403145 WARNING: region 1:
9233 13:54:14.409617 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9234 13:54:14.412433 WARNING: region 2:
9235 13:54:14.416155 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9236 13:54:14.419382 WARNING: region 3:
9237 13:54:14.424201 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9238 13:54:14.426412 WARNING: region 4:
9239 13:54:14.433416 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9240 13:54:14.433986 WARNING: region 5:
9241 13:54:14.436154 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9242 13:54:14.439573 WARNING: region 6:
9243 13:54:14.443012 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9244 13:54:14.443582 WARNING: region 7:
9245 13:54:14.449701 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9246 13:54:14.456523 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9247 13:54:14.459435 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9248 13:54:14.463511 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9249 13:54:14.469580 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9250 13:54:14.472812 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9251 13:54:14.476183 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9252 13:54:14.482560 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9253 13:54:14.486328 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9254 13:54:14.492965 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9255 13:54:14.495971 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9256 13:54:14.499377 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9257 13:54:14.505721 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9258 13:54:14.509370 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9259 13:54:14.512472 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9260 13:54:14.519416 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9261 13:54:14.522853 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9262 13:54:14.529135 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9263 13:54:14.533635 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9264 13:54:14.535780 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9265 13:54:14.542639 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9266 13:54:14.545806 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9267 13:54:14.550663 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9268 13:54:14.556317 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9269 13:54:14.560098 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9270 13:54:14.566727 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9271 13:54:14.569509 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9272 13:54:14.572503 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9273 13:54:14.579692 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9274 13:54:14.582792 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9275 13:54:14.589233 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9276 13:54:14.593062 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9277 13:54:14.595824 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9278 13:54:14.602704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9279 13:54:14.605788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9280 13:54:14.609247 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9281 13:54:14.612474 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9282 13:54:14.619754 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9283 13:54:14.622670 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9284 13:54:14.625549 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9285 13:54:14.629080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9286 13:54:14.632120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9287 13:54:14.639065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9288 13:54:14.642488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9289 13:54:14.645578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9290 13:54:14.652455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9291 13:54:14.656339 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9292 13:54:14.659835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9293 13:54:14.663559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9294 13:54:14.668975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9295 13:54:14.672584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9296 13:54:14.678897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9297 13:54:14.682614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9298 13:54:14.686131 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9299 13:54:14.692668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9300 13:54:14.695886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9301 13:54:14.702236 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9302 13:54:14.705784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9303 13:54:14.712453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9304 13:54:14.715857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9305 13:54:14.718970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9306 13:54:14.725803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9307 13:54:14.728970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9308 13:54:14.735613 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9309 13:54:14.739305 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9310 13:54:14.745645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9311 13:54:14.749305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9312 13:54:14.752848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9313 13:54:14.759526 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9314 13:54:14.762943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9315 13:54:14.769098 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9316 13:54:14.772502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9317 13:54:14.779249 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9318 13:54:14.782994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9319 13:54:14.785908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9320 13:54:14.792602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9321 13:54:14.795714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9322 13:54:14.802553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9323 13:54:14.805510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9324 13:54:14.812821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9325 13:54:14.815914 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9326 13:54:14.822761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9327 13:54:14.826071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9328 13:54:14.829461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9329 13:54:14.835754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9330 13:54:14.839208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9331 13:54:14.846141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9332 13:54:14.849241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9333 13:54:14.855892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9334 13:54:14.859380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9335 13:54:14.862260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9336 13:54:14.869041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9337 13:54:14.872462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9338 13:54:14.879304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9339 13:54:14.882664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9340 13:54:14.889551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9341 13:54:14.892567 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9342 13:54:14.895430 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9343 13:54:14.903041 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9344 13:54:14.905914 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9345 13:54:14.909381 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9346 13:54:14.912619 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9347 13:54:14.919353 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9348 13:54:14.922179 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9349 13:54:14.929321 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9350 13:54:14.932349 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9351 13:54:14.935656 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9352 13:54:14.942593 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9353 13:54:14.946123 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9354 13:54:14.949017 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9355 13:54:14.955847 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9356 13:54:14.959133 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9357 13:54:14.965703 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9358 13:54:14.971809 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9359 13:54:14.973286 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9360 13:54:14.979010 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9361 13:54:14.982687 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9362 13:54:14.986224 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9363 13:54:14.992161 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9364 13:54:14.995546 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9365 13:54:14.999265 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9366 13:54:15.005487 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9367 13:54:15.009306 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9368 13:54:15.012604 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9369 13:54:15.015498 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9370 13:54:15.021916 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9371 13:54:15.025930 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9372 13:54:15.028916 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9373 13:54:15.035620 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9374 13:54:15.038761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9375 13:54:15.046695 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9376 13:54:15.049535 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9377 13:54:15.052133 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9378 13:54:15.059161 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9379 13:54:15.062102 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9380 13:54:15.069002 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9381 13:54:15.072332 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9382 13:54:15.076005 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9383 13:54:15.083201 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9384 13:54:15.085891 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9385 13:54:15.089187 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9386 13:54:15.096526 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9387 13:54:15.099303 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9388 13:54:15.106273 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9389 13:54:15.109227 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9390 13:54:15.112398 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9391 13:54:15.119738 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9392 13:54:15.122294 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9393 13:54:15.129156 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9394 13:54:15.132177 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9395 13:54:15.135535 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9396 13:54:15.142862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9397 13:54:15.146287 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9398 13:54:15.149094 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9399 13:54:15.155727 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9400 13:54:15.159731 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9401 13:54:15.165711 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9402 13:54:15.169317 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9403 13:54:15.172545 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9404 13:54:15.179124 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9405 13:54:15.183051 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9406 13:54:15.189767 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9407 13:54:15.192552 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9408 13:54:15.196233 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9409 13:54:15.202294 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9410 13:54:15.205604 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9411 13:54:15.209272 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9412 13:54:15.215305 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9413 13:54:15.219030 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9414 13:54:15.225674 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9415 13:54:15.228729 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9416 13:54:15.233143 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9417 13:54:15.239108 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9418 13:54:15.242431 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9419 13:54:15.249222 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9420 13:54:15.252139 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9421 13:54:15.255535 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9422 13:54:15.262214 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9423 13:54:15.265420 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9424 13:54:15.272051 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9425 13:54:15.275925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9426 13:54:15.278496 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9427 13:54:15.285595 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9428 13:54:15.288615 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9429 13:54:15.295076 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9430 13:54:15.299057 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9431 13:54:15.301997 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9432 13:54:15.308387 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9433 13:54:15.311399 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9434 13:54:15.318672 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9435 13:54:15.321788 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9436 13:54:15.325342 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9437 13:54:15.331661 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9438 13:54:15.334809 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9439 13:54:15.341284 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9440 13:54:15.345105 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9441 13:54:15.351506 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9442 13:54:15.354677 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9443 13:54:15.358517 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9444 13:54:15.364619 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9445 13:54:15.368071 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9446 13:54:15.375600 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9447 13:54:15.378593 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9448 13:54:15.381947 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9449 13:54:15.388539 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9450 13:54:15.391363 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9451 13:54:15.397937 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9452 13:54:15.401185 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9453 13:54:15.408098 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9454 13:54:15.411427 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9455 13:54:15.415089 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9456 13:54:15.420995 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9457 13:54:15.424476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9458 13:54:15.431303 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9459 13:54:15.434401 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9460 13:54:15.437367 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9461 13:54:15.444695 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9462 13:54:15.448530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9463 13:54:15.454224 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9464 13:54:15.457464 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9465 13:54:15.464406 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9466 13:54:15.467607 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9467 13:54:15.470872 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9468 13:54:15.478193 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9469 13:54:15.481538 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9470 13:54:15.487907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9471 13:54:15.491295 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9472 13:54:15.494238 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9473 13:54:15.501224 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9474 13:54:15.504769 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9475 13:54:15.507506 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9476 13:54:15.514487 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9477 13:54:15.517329 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9478 13:54:15.520791 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9479 13:54:15.524619 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9480 13:54:15.531167 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9481 13:54:15.533950 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9482 13:54:15.540603 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9483 13:54:15.543934 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9484 13:54:15.547285 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9485 13:54:15.554400 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9486 13:54:15.557031 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9487 13:54:15.560958 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9488 13:54:15.566822 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9489 13:54:15.570922 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9490 13:54:15.573635 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9491 13:54:15.581189 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9492 13:54:15.584456 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9493 13:54:15.590879 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9494 13:54:15.593658 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9495 13:54:15.597210 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9496 13:54:15.603271 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9497 13:54:15.606733 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9498 13:54:15.613310 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9499 13:54:15.616641 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9500 13:54:15.620170 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9501 13:54:15.627007 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9502 13:54:15.630063 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9503 13:54:15.633757 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9504 13:54:15.640062 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9505 13:54:15.643266 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9506 13:54:15.646440 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9507 13:54:15.653123 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9508 13:54:15.656462 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9509 13:54:15.659307 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9510 13:54:15.666692 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9511 13:54:15.670241 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9512 13:54:15.676424 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9513 13:54:15.679812 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9514 13:54:15.682735 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9515 13:54:15.689398 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9516 13:54:15.693126 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9517 13:54:15.695888 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9518 13:54:15.699191 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9519 13:54:15.702560 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9520 13:54:15.709638 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9521 13:54:15.712880 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9522 13:54:15.716478 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9523 13:54:15.719429 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9524 13:54:15.725744 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9525 13:54:15.729239 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9526 13:54:15.732891 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9527 13:54:15.738892 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9528 13:54:15.743051 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9529 13:54:15.745477 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9530 13:54:15.752355 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9531 13:54:15.756567 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9532 13:54:15.762135 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9533 13:54:15.765441 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9534 13:54:15.772372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9535 13:54:15.775422 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9536 13:54:15.778635 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9537 13:54:15.786351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9538 13:54:15.788541 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9539 13:54:15.795238 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9540 13:54:15.798756 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9541 13:54:15.802182 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9542 13:54:15.808648 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9543 13:54:15.812464 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9544 13:54:15.818644 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9545 13:54:15.821934 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9546 13:54:15.828871 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9547 13:54:15.832248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9548 13:54:15.834908 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9549 13:54:15.841256 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9550 13:54:15.845438 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9551 13:54:15.851784 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9552 13:54:15.854626 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9553 13:54:15.858382 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9554 13:54:15.864745 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9555 13:54:15.868136 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9556 13:54:15.874543 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9557 13:54:15.878667 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9558 13:54:15.884949 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9559 13:54:15.888196 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9560 13:54:15.891790 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9561 13:54:15.897428 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9562 13:54:15.901651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9563 13:54:15.907641 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9564 13:54:15.910598 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9565 13:54:15.915153 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9566 13:54:15.921004 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9567 13:54:15.924066 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9568 13:54:15.930845 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9569 13:54:15.934493 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9570 13:54:15.941041 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9571 13:54:15.943925 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9572 13:54:15.947272 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9573 13:54:15.954341 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9574 13:54:15.956914 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9575 13:54:15.963926 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9576 13:54:15.967459 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9577 13:54:15.970534 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9578 13:54:15.976974 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9579 13:54:15.979869 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9580 13:54:15.987547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9581 13:54:15.990394 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9582 13:54:15.996501 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9583 13:54:16.000819 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9584 13:54:16.003719 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9585 13:54:16.009746 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9586 13:54:16.013076 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9587 13:54:16.020034 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9588 13:54:16.023243 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9589 13:54:16.026638 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9590 13:54:16.033435 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9591 13:54:16.036392 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9592 13:54:16.043424 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9593 13:54:16.046104 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9594 13:54:16.050041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9595 13:54:16.056490 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9596 13:54:16.059986 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9597 13:54:16.066652 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9598 13:54:16.069256 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9599 13:54:16.073367 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9600 13:54:16.080501 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9601 13:54:16.082334 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9602 13:54:16.089307 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9603 13:54:16.093058 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9604 13:54:16.099393 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9605 13:54:16.103084 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9606 13:54:16.110012 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9607 13:54:16.112453 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9608 13:54:16.115999 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9609 13:54:16.122256 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9610 13:54:16.125409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9611 13:54:16.132159 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9612 13:54:16.135755 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9613 13:54:16.142150 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9614 13:54:16.145337 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9615 13:54:16.152152 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9616 13:54:16.155237 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9617 13:54:16.158554 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9618 13:54:16.165257 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9619 13:54:16.168811 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9620 13:54:16.175910 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9621 13:54:16.178537 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9622 13:54:16.185435 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9623 13:54:16.189423 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9624 13:54:16.195042 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9625 13:54:16.198578 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9626 13:54:16.201851 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9627 13:54:16.208621 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9628 13:54:16.211235 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9629 13:54:16.217992 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9630 13:54:16.221030 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9631 13:54:16.227989 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9632 13:54:16.231342 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9633 13:54:16.237520 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9634 13:54:16.241762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9635 13:54:16.245003 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9636 13:54:16.251182 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9637 13:54:16.254476 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9638 13:54:16.260790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9639 13:54:16.264670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9640 13:54:16.270746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9641 13:54:16.274290 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9642 13:54:16.278330 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9643 13:54:16.284495 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9644 13:54:16.287630 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9645 13:54:16.294231 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9646 13:54:16.297851 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9647 13:54:16.305428 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9648 13:54:16.307410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9649 13:54:16.311252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9650 13:54:16.317540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9651 13:54:16.320931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9652 13:54:16.327866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9653 13:54:16.330781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9654 13:54:16.337023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9655 13:54:16.341100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9656 13:54:16.347061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9657 13:54:16.350436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9658 13:54:16.357128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9659 13:54:16.360011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9660 13:54:16.367299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9661 13:54:16.370242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9662 13:54:16.376745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9663 13:54:16.380102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9664 13:54:16.387107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9665 13:54:16.390038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9666 13:54:16.396684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9667 13:54:16.399691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9668 13:54:16.406893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9669 13:54:16.409780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9670 13:54:16.416981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9671 13:54:16.419918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9672 13:54:16.426360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9673 13:54:16.429671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9674 13:54:16.436983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9675 13:54:16.440416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9676 13:54:16.446225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9677 13:54:16.449913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9678 13:54:16.456443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9679 13:54:16.459478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9680 13:54:16.466307 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9681 13:54:16.466857 INFO: [APUAPC] vio 0
9682 13:54:16.472414 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9683 13:54:16.475912 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9684 13:54:16.479318 INFO: [APUAPC] D0_APC_0: 0x400510
9685 13:54:16.482666 INFO: [APUAPC] D0_APC_1: 0x0
9686 13:54:16.485562 INFO: [APUAPC] D0_APC_2: 0x1540
9687 13:54:16.489326 INFO: [APUAPC] D0_APC_3: 0x0
9688 13:54:16.492909 INFO: [APUAPC] D1_APC_0: 0xffffffff
9689 13:54:16.495876 INFO: [APUAPC] D1_APC_1: 0xffffffff
9690 13:54:16.498917 INFO: [APUAPC] D1_APC_2: 0x3fffff
9691 13:54:16.502810 INFO: [APUAPC] D1_APC_3: 0x0
9692 13:54:16.505479 INFO: [APUAPC] D2_APC_0: 0xffffffff
9693 13:54:16.508685 INFO: [APUAPC] D2_APC_1: 0xffffffff
9694 13:54:16.512195 INFO: [APUAPC] D2_APC_2: 0x3fffff
9695 13:54:16.516780 INFO: [APUAPC] D2_APC_3: 0x0
9696 13:54:16.518895 INFO: [APUAPC] D3_APC_0: 0xffffffff
9697 13:54:16.522349 INFO: [APUAPC] D3_APC_1: 0xffffffff
9698 13:54:16.525435 INFO: [APUAPC] D3_APC_2: 0x3fffff
9699 13:54:16.528778 INFO: [APUAPC] D3_APC_3: 0x0
9700 13:54:16.532338 INFO: [APUAPC] D4_APC_0: 0xffffffff
9701 13:54:16.535550 INFO: [APUAPC] D4_APC_1: 0xffffffff
9702 13:54:16.538683 INFO: [APUAPC] D4_APC_2: 0x3fffff
9703 13:54:16.539139 INFO: [APUAPC] D4_APC_3: 0x0
9704 13:54:16.545058 INFO: [APUAPC] D5_APC_0: 0xffffffff
9705 13:54:16.548775 INFO: [APUAPC] D5_APC_1: 0xffffffff
9706 13:54:16.552184 INFO: [APUAPC] D5_APC_2: 0x3fffff
9707 13:54:16.552781 INFO: [APUAPC] D5_APC_3: 0x0
9708 13:54:16.555413 INFO: [APUAPC] D6_APC_0: 0xffffffff
9709 13:54:16.561667 INFO: [APUAPC] D6_APC_1: 0xffffffff
9710 13:54:16.562181 INFO: [APUAPC] D6_APC_2: 0x3fffff
9711 13:54:16.565381 INFO: [APUAPC] D6_APC_3: 0x0
9712 13:54:16.568117 INFO: [APUAPC] D7_APC_0: 0xffffffff
9713 13:54:16.573054 INFO: [APUAPC] D7_APC_1: 0xffffffff
9714 13:54:16.575491 INFO: [APUAPC] D7_APC_2: 0x3fffff
9715 13:54:16.578201 INFO: [APUAPC] D7_APC_3: 0x0
9716 13:54:16.582047 INFO: [APUAPC] D8_APC_0: 0xffffffff
9717 13:54:16.585433 INFO: [APUAPC] D8_APC_1: 0xffffffff
9718 13:54:16.588880 INFO: [APUAPC] D8_APC_2: 0x3fffff
9719 13:54:16.591754 INFO: [APUAPC] D8_APC_3: 0x0
9720 13:54:16.594936 INFO: [APUAPC] D9_APC_0: 0xffffffff
9721 13:54:16.598543 INFO: [APUAPC] D9_APC_1: 0xffffffff
9722 13:54:16.601299 INFO: [APUAPC] D9_APC_2: 0x3fffff
9723 13:54:16.604814 INFO: [APUAPC] D9_APC_3: 0x0
9724 13:54:16.608761 INFO: [APUAPC] D10_APC_0: 0xffffffff
9725 13:54:16.611306 INFO: [APUAPC] D10_APC_1: 0xffffffff
9726 13:54:16.614934 INFO: [APUAPC] D10_APC_2: 0x3fffff
9727 13:54:16.617774 INFO: [APUAPC] D10_APC_3: 0x0
9728 13:54:16.621351 INFO: [APUAPC] D11_APC_0: 0xffffffff
9729 13:54:16.626268 INFO: [APUAPC] D11_APC_1: 0xffffffff
9730 13:54:16.628755 INFO: [APUAPC] D11_APC_2: 0x3fffff
9731 13:54:16.632021 INFO: [APUAPC] D11_APC_3: 0x0
9732 13:54:16.634723 INFO: [APUAPC] D12_APC_0: 0xffffffff
9733 13:54:16.637616 INFO: [APUAPC] D12_APC_1: 0xffffffff
9734 13:54:16.640953 INFO: [APUAPC] D12_APC_2: 0x3fffff
9735 13:54:16.644516 INFO: [APUAPC] D12_APC_3: 0x0
9736 13:54:16.647946 INFO: [APUAPC] D13_APC_0: 0xffffffff
9737 13:54:16.651393 INFO: [APUAPC] D13_APC_1: 0xffffffff
9738 13:54:16.654541 INFO: [APUAPC] D13_APC_2: 0x3fffff
9739 13:54:16.658365 INFO: [APUAPC] D13_APC_3: 0x0
9740 13:54:16.660899 INFO: [APUAPC] D14_APC_0: 0xffffffff
9741 13:54:16.664527 INFO: [APUAPC] D14_APC_1: 0xffffffff
9742 13:54:16.668217 INFO: [APUAPC] D14_APC_2: 0x3fffff
9743 13:54:16.671356 INFO: [APUAPC] D14_APC_3: 0x0
9744 13:54:16.674473 INFO: [APUAPC] D15_APC_0: 0xffffffff
9745 13:54:16.677633 INFO: [APUAPC] D15_APC_1: 0xffffffff
9746 13:54:16.681554 INFO: [APUAPC] D15_APC_2: 0x3fffff
9747 13:54:16.685182 INFO: [APUAPC] D15_APC_3: 0x0
9748 13:54:16.687511 INFO: [APUAPC] APC_CON: 0x4
9749 13:54:16.690949 INFO: [NOCDAPC] D0_APC_0: 0x0
9750 13:54:16.694725 INFO: [NOCDAPC] D0_APC_1: 0x0
9751 13:54:16.697650 INFO: [NOCDAPC] D1_APC_0: 0x0
9752 13:54:16.701285 INFO: [NOCDAPC] D1_APC_1: 0xfff
9753 13:54:16.704023 INFO: [NOCDAPC] D2_APC_0: 0x0
9754 13:54:16.707804 INFO: [NOCDAPC] D2_APC_1: 0xfff
9755 13:54:16.708276 INFO: [NOCDAPC] D3_APC_0: 0x0
9756 13:54:16.711083 INFO: [NOCDAPC] D3_APC_1: 0xfff
9757 13:54:16.714584 INFO: [NOCDAPC] D4_APC_0: 0x0
9758 13:54:16.717753 INFO: [NOCDAPC] D4_APC_1: 0xfff
9759 13:54:16.720921 INFO: [NOCDAPC] D5_APC_0: 0x0
9760 13:54:16.723977 INFO: [NOCDAPC] D5_APC_1: 0xfff
9761 13:54:16.727354 INFO: [NOCDAPC] D6_APC_0: 0x0
9762 13:54:16.730794 INFO: [NOCDAPC] D6_APC_1: 0xfff
9763 13:54:16.733835 INFO: [NOCDAPC] D7_APC_0: 0x0
9764 13:54:16.739699 INFO: [NOCDAPC] D7_APC_1: 0xfff
9765 13:54:16.741337 INFO: [NOCDAPC] D8_APC_0: 0x0
9766 13:54:16.744794 INFO: [NOCDAPC] D8_APC_1: 0xfff
9767 13:54:16.745291 INFO: [NOCDAPC] D9_APC_0: 0x0
9768 13:54:16.747284 INFO: [NOCDAPC] D9_APC_1: 0xfff
9769 13:54:16.750438 INFO: [NOCDAPC] D10_APC_0: 0x0
9770 13:54:16.754083 INFO: [NOCDAPC] D10_APC_1: 0xfff
9771 13:54:16.757030 INFO: [NOCDAPC] D11_APC_0: 0x0
9772 13:54:16.760081 INFO: [NOCDAPC] D11_APC_1: 0xfff
9773 13:54:16.763935 INFO: [NOCDAPC] D12_APC_0: 0x0
9774 13:54:16.767475 INFO: [NOCDAPC] D12_APC_1: 0xfff
9775 13:54:16.770607 INFO: [NOCDAPC] D13_APC_0: 0x0
9776 13:54:16.774368 INFO: [NOCDAPC] D13_APC_1: 0xfff
9777 13:54:16.777241 INFO: [NOCDAPC] D14_APC_0: 0x0
9778 13:54:16.780398 INFO: [NOCDAPC] D14_APC_1: 0xfff
9779 13:54:16.784885 INFO: [NOCDAPC] D15_APC_0: 0x0
9780 13:54:16.787162 INFO: [NOCDAPC] D15_APC_1: 0xfff
9781 13:54:16.787713 INFO: [NOCDAPC] APC_CON: 0x4
9782 13:54:16.790600 INFO: [APUAPC] set_apusys_apc done
9783 13:54:16.794585 INFO: [DEVAPC] devapc_init done
9784 13:54:16.800218 INFO: GICv3 without legacy support detected.
9785 13:54:16.804295 INFO: ARM GICv3 driver initialized in EL3
9786 13:54:16.806807 INFO: Maximum SPI INTID supported: 639
9787 13:54:16.810586 INFO: BL31: Initializing runtime services
9788 13:54:16.816702 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9789 13:54:16.819679 INFO: SPM: enable CPC mode
9790 13:54:16.823656 INFO: mcdi ready for mcusys-off-idle and system suspend
9791 13:54:16.830091 INFO: BL31: Preparing for EL3 exit to normal world
9792 13:54:16.833615 INFO: Entry point address = 0x80000000
9793 13:54:16.834191 INFO: SPSR = 0x8
9794 13:54:16.840604
9795 13:54:16.841222
9796 13:54:16.841581
9797 13:54:16.843928 Starting depthcharge on Spherion...
9798 13:54:16.844481
9799 13:54:16.844907 Wipe memory regions:
9800 13:54:16.845255
9801 13:54:16.847880 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9802 13:54:16.848407 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9803 13:54:16.848989 Setting prompt string to ['asurada:']
9804 13:54:16.849585 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9805 13:54:16.850318 [0x00000040000000, 0x00000054600000)
9806 13:54:16.969222
9807 13:54:16.969742 [0x00000054660000, 0x00000080000000)
9808 13:54:17.230688
9809 13:54:17.231235 [0x000000821a7280, 0x000000ffe64000)
9810 13:54:17.975172
9811 13:54:17.975724 [0x00000100000000, 0x00000140000000)
9812 13:54:18.356229
9813 13:54:18.359129 Initializing XHCI USB controller at 0x11200000.
9814 13:54:19.398687
9815 13:54:19.401773 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9816 13:54:19.402327
9817 13:54:19.402684
9818 13:54:19.403012
9819 13:54:19.403841 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9821 13:54:19.505235 asurada: tftpboot 192.168.201.1 12682950/tftp-deploy-xlqbxold/kernel/image.itb 12682950/tftp-deploy-xlqbxold/kernel/cmdline
9822 13:54:19.505995 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9823 13:54:19.506511 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9824 13:54:19.511194 tftpboot 192.168.201.1 12682950/tftp-deploy-xlqbxold/kernel/image.ittp-deploy-xlqbxold/kernel/cmdline
9825 13:54:19.511773
9826 13:54:19.512130 Waiting for link
9827 13:54:19.671701
9828 13:54:19.672253 R8152: Initializing
9829 13:54:19.672761
9830 13:54:19.675410 Version 9 (ocp_data = 6010)
9831 13:54:19.675969
9832 13:54:19.679385 R8152: Done initializing
9833 13:54:19.679932
9834 13:54:19.680286 Adding net device
9835 13:54:21.560230
9836 13:54:21.560817 done.
9837 13:54:21.561176
9838 13:54:21.561497 MAC: 00:e0:4c:68:03:bd
9839 13:54:21.561809
9840 13:54:21.563019 Sending DHCP discover... done.
9841 13:54:21.563393
9842 13:54:24.586797 Waiting for reply... done.
9843 13:54:24.587377
9844 13:54:24.587766 Sending DHCP request... done.
9845 13:54:24.591155
9846 13:54:24.591699 Waiting for reply... done.
9847 13:54:24.592053
9848 13:54:24.593700 My ip is 192.168.201.16
9849 13:54:24.594173
9850 13:54:24.596248 The DHCP server ip is 192.168.201.1
9851 13:54:24.596696
9852 13:54:24.599586 TFTP server IP predefined by user: 192.168.201.1
9853 13:54:24.600142
9854 13:54:24.606616 Bootfile predefined by user: 12682950/tftp-deploy-xlqbxold/kernel/image.itb
9855 13:54:24.607168
9856 13:54:24.610460 Sending tftp read request... done.
9857 13:54:24.611014
9858 13:54:24.618555 Waiting for the transfer...
9859 13:54:24.619004
9860 13:54:24.912976 00000000 ################################################################
9861 13:54:24.913111
9862 13:54:25.204237 00080000 ################################################################
9863 13:54:25.204364
9864 13:54:25.485747 00100000 ################################################################
9865 13:54:25.485872
9866 13:54:25.774260 00180000 ################################################################
9867 13:54:25.774389
9868 13:54:26.055188 00200000 ################################################################
9869 13:54:26.055322
9870 13:54:26.338283 00280000 ################################################################
9871 13:54:26.338412
9872 13:54:26.620966 00300000 ################################################################
9873 13:54:26.621096
9874 13:54:26.902695 00380000 ################################################################
9875 13:54:26.902826
9876 13:54:27.187419 00400000 ################################################################
9877 13:54:27.187563
9878 13:54:27.469830 00480000 ################################################################
9879 13:54:27.469971
9880 13:54:27.750484 00500000 ################################################################
9881 13:54:27.750627
9882 13:54:28.044865 00580000 ################################################################
9883 13:54:28.045003
9884 13:54:28.329248 00600000 ################################################################
9885 13:54:28.329383
9886 13:54:28.618913 00680000 ################################################################
9887 13:54:28.619068
9888 13:54:28.900165 00700000 ################################################################
9889 13:54:28.900311
9890 13:54:29.186771 00780000 ################################################################
9891 13:54:29.186914
9892 13:54:29.474934 00800000 ################################################################
9893 13:54:29.475073
9894 13:54:29.766050 00880000 ################################################################
9895 13:54:29.766191
9896 13:54:30.058282 00900000 ################################################################
9897 13:54:30.058449
9898 13:54:30.354283 00980000 ################################################################
9899 13:54:30.354421
9900 13:54:30.645682 00a00000 ################################################################
9901 13:54:30.645817
9902 13:54:30.927946 00a80000 ################################################################
9903 13:54:30.928075
9904 13:54:31.196845 00b00000 ################################################################
9905 13:54:31.196978
9906 13:54:31.477070 00b80000 ################################################################
9907 13:54:31.477208
9908 13:54:31.725691 00c00000 ################################################################
9909 13:54:31.725848
9910 13:54:31.977596 00c80000 ################################################################
9911 13:54:31.977731
9912 13:54:32.234439 00d00000 ################################################################
9913 13:54:32.234574
9914 13:54:32.491370 00d80000 ################################################################
9915 13:54:32.491500
9916 13:54:32.774758 00e00000 ################################################################
9917 13:54:32.774900
9918 13:54:33.056094 00e80000 ################################################################
9919 13:54:33.056229
9920 13:54:33.340048 00f00000 ################################################################
9921 13:54:33.340185
9922 13:54:33.627139 00f80000 ################################################################
9923 13:54:33.627282
9924 13:54:33.914680 01000000 ################################################################
9925 13:54:33.914813
9926 13:54:34.214634 01080000 ################################################################
9927 13:54:34.214781
9928 13:54:34.517453 01100000 ################################################################
9929 13:54:34.517598
9930 13:54:34.816002 01180000 ################################################################
9931 13:54:34.816139
9932 13:54:35.117682 01200000 ################################################################
9933 13:54:35.117816
9934 13:54:35.417327 01280000 ################################################################
9935 13:54:35.417459
9936 13:54:35.704850 01300000 ################################################################
9937 13:54:35.704981
9938 13:54:35.986657 01380000 ################################################################
9939 13:54:35.986795
9940 13:54:36.275141 01400000 ################################################################
9941 13:54:36.275279
9942 13:54:36.555847 01480000 ################################################################
9943 13:54:36.555985
9944 13:54:36.837374 01500000 ################################################################
9945 13:54:36.837510
9946 13:54:37.125564 01580000 ################################################################
9947 13:54:37.125713
9948 13:54:37.421189 01600000 ################################################################
9949 13:54:37.421329
9950 13:54:37.705317 01680000 ################################################################
9951 13:54:37.705457
9952 13:54:37.979423 01700000 ################################################################
9953 13:54:37.979556
9954 13:54:38.238805 01780000 ################################################################
9955 13:54:38.238947
9956 13:54:38.530170 01800000 ################################################################
9957 13:54:38.530309
9958 13:54:38.828456 01880000 ################################################################
9959 13:54:38.828617
9960 13:54:39.128485 01900000 ################################################################
9961 13:54:39.128636
9962 13:54:39.416856 01980000 ################################################################
9963 13:54:39.417047
9964 13:54:39.701884 01a00000 ################################################################
9965 13:54:39.702026
9966 13:54:40.000028 01a80000 ################################################################
9967 13:54:40.000170
9968 13:54:40.283884 01b00000 ################################################################
9969 13:54:40.284065
9970 13:54:40.571751 01b80000 ################################################################
9971 13:54:40.571892
9972 13:54:40.875527 01c00000 ################################################################
9973 13:54:40.875670
9974 13:54:40.881412 01c80000 ## done.
9975 13:54:40.881495
9976 13:54:40.885326 The bootfile was 29896182 bytes long.
9977 13:54:40.885737
9978 13:54:40.888311 Sending tftp read request... done.
9979 13:54:40.888749
9980 13:54:40.891862 Waiting for the transfer...
9981 13:54:40.892270
9982 13:54:40.895742 00000000 # done.
9983 13:54:40.896162
9984 13:54:40.901985 Command line loaded dynamically from TFTP file: 12682950/tftp-deploy-xlqbxold/kernel/cmdline
9985 13:54:40.902505
9986 13:54:40.925174 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682950/extract-nfsrootfs-t8gplle7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9987 13:54:40.925762
9988 13:54:40.926143 Loading FIT.
9989 13:54:40.926733
9990 13:54:40.928055 Image ramdisk-1 has 17800010 bytes.
9991 13:54:40.928426
9992 13:54:40.931742 Image fdt-1 has 47278 bytes.
9993 13:54:40.932304
9994 13:54:40.935071 Image kernel-1 has 12046857 bytes.
9995 13:54:40.935527
9996 13:54:40.941541 Compat preference: google,spherion-rev13-sku1 google,spherion-rev13 google,spherion-sku1 google,spherion
9997 13:54:40.945027
9998 13:54:40.961577 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
9999 13:54:40.962145
10000 13:54:40.964496 Choosing best match conf-1 for compat google,spherion.
10001 13:54:40.969658
10002 13:54:40.974319 Connected to device vid:did:rid of 1ae0:0028:00
10003 13:54:40.981313
10004 13:54:40.984118 tpm_get_response: command 0x17b, return code 0x0
10005 13:54:40.984575
10006 13:54:40.987618 ec_init: CrosEC protocol v3 supported (256, 248)
10007 13:54:40.991704
10008 13:54:40.995827 tpm_cleanup: add release locality here.
10009 13:54:40.996281
10010 13:54:40.996637 Shutting down all USB controllers.
10011 13:54:40.998426
10012 13:54:40.998875 Removing current net device
10013 13:54:40.999231
10014 13:54:41.006349 Exiting depthcharge with code 4 at timestamp: 52364724
10015 13:54:41.006910
10016 13:54:41.008669 LZMA decompressing kernel-1 to 0x821a6718
10017 13:54:41.009160
10018 13:54:41.012059 LZMA decompressing kernel-1 to 0x40000000
10019 13:54:42.512140
10020 13:54:42.512693 jumping to kernel
10021 13:54:42.514419 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
10022 13:54:42.514942 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10023 13:54:42.515346 Setting prompt string to ['Linux version [0-9]']
10024 13:54:42.515716 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 13:54:42.516089 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10026 13:54:42.561971
10027 13:54:42.564578 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10028 13:54:42.568431 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10029 13:54:42.569075 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10030 13:54:42.569470 Setting prompt string to []
10031 13:54:42.569884 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10032 13:54:42.570262 Using line separator: #'\n'#
10033 13:54:42.570589 No login prompt set.
10034 13:54:42.570921 Parsing kernel messages
10035 13:54:42.571224 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10036 13:54:42.571775 [login-action] Waiting for messages, (timeout 00:04:01)
10037 13:54:42.589146 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10038 13:54:42.592531 [ 0.000000] random: crng init done
10039 13:54:42.597913 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10040 13:54:42.601292 [ 0.000000] efi: UEFI not found.
10041 13:54:42.607768 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10042 13:54:42.614507 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10043 13:54:42.624768 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10044 13:54:42.635447 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10045 13:54:42.641019 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10046 13:54:42.647255 [ 0.000000] printk: bootconsole [mtk8250] enabled
10047 13:54:42.653501 [ 0.000000] NUMA: No NUMA configuration found
10048 13:54:42.661270 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10049 13:54:42.663518 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10050 13:54:42.667168 [ 0.000000] Zone ranges:
10051 13:54:42.673854 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10052 13:54:42.677102 [ 0.000000] DMA32 empty
10053 13:54:42.684141 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10054 13:54:42.687239 [ 0.000000] Movable zone start for each node
10055 13:54:42.690231 [ 0.000000] Early memory node ranges
10056 13:54:42.696937 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10057 13:54:42.703408 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10058 13:54:42.710349 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10059 13:54:42.716474 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10060 13:54:42.722985 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10061 13:54:42.729401 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10062 13:54:42.760147 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10063 13:54:42.767025 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10064 13:54:42.773618 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10065 13:54:42.776803 [ 0.000000] psci: probing for conduit method from DT.
10066 13:54:42.783305 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10067 13:54:42.786772 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10068 13:54:42.793304 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10069 13:54:42.796569 [ 0.000000] psci: SMC Calling Convention v1.2
10070 13:54:42.803267 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10071 13:54:42.807192 [ 0.000000] Detected VIPT I-cache on CPU0
10072 13:54:42.813988 [ 0.000000] CPU features: detected: GIC system register CPU interface
10073 13:54:42.819505 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10074 13:54:42.826346 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10075 13:54:42.832701 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10076 13:54:42.842703 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10077 13:54:42.849033 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10078 13:54:42.852687 [ 0.000000] alternatives: applying boot alternatives
10079 13:54:42.859545 [ 0.000000] Fallback order for Node 0: 0
10080 13:54:42.865167 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10081 13:54:42.869797 [ 0.000000] Policy zone: Normal
10082 13:54:42.892201 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682950/extract-nfsrootfs-t8gplle7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10083 13:54:42.901827 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10084 13:54:42.913051 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10085 13:54:42.918655 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10086 13:54:42.924765 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10087 13:54:42.931615 <6>[ 0.000000] software IO TLB: area num 8.
10088 13:54:42.987109 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10089 13:54:43.066900 <6>[ 0.000000] Memory: 3835460K/4191232K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 323004K reserved, 32768K cma-reserved)
10090 13:54:43.073925 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10091 13:54:43.080000 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10092 13:54:43.084145 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10093 13:54:43.089899 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10094 13:54:43.096881 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10095 13:54:43.099758 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10096 13:54:43.109953 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10097 13:54:43.116431 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10098 13:54:43.123192 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10099 13:54:43.130138 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10100 13:54:43.136311 <6>[ 0.000000] GICv3: 608 SPIs implemented
10101 13:54:43.137436 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10102 13:54:43.143209 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10103 13:54:43.145706 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10104 13:54:43.152384 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10105 13:54:43.165729 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10106 13:54:43.179226 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10107 13:54:43.185680 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10108 13:54:43.193397 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10109 13:54:43.206749 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10110 13:54:43.213082 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10111 13:54:43.220882 <6>[ 0.009182] Console: colour dummy device 80x25
10112 13:54:43.230275 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10113 13:54:43.236773 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10114 13:54:43.239865 <6>[ 0.029222] LSM: Security Framework initializing
10115 13:54:43.247615 <6>[ 0.034136] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10116 13:54:43.256286 <6>[ 0.041743] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10117 13:54:43.262857 <6>[ 0.050972] cblist_init_generic: Setting adjustable number of callback queues.
10118 13:54:43.269296 <6>[ 0.058462] cblist_init_generic: Setting shift to 3 and lim to 1.
10119 13:54:43.280123 <6>[ 0.064800] cblist_init_generic: Setting adjustable number of callback queues.
10120 13:54:43.285905 <6>[ 0.072227] cblist_init_generic: Setting shift to 3 and lim to 1.
10121 13:54:43.289018 <6>[ 0.078626] rcu: Hierarchical SRCU implementation.
10122 13:54:43.296330 <6>[ 0.083641] rcu: Max phase no-delay instances is 1000.
10123 13:54:43.303172 <6>[ 0.090649] EFI services will not be available.
10124 13:54:43.306933 <6>[ 0.095602] smp: Bringing up secondary CPUs ...
10125 13:54:43.313687 <6>[ 0.100680] Detected VIPT I-cache on CPU1
10126 13:54:43.320420 <6>[ 0.100747] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10127 13:54:43.326816 <6>[ 0.100778] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10128 13:54:43.330643 <6>[ 0.101107] Detected VIPT I-cache on CPU2
10129 13:54:43.337212 <6>[ 0.101155] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10130 13:54:43.346894 <6>[ 0.101171] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10131 13:54:43.350374 <6>[ 0.101424] Detected VIPT I-cache on CPU3
10132 13:54:43.357116 <6>[ 0.101470] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10133 13:54:43.364073 <6>[ 0.101484] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10134 13:54:43.366582 <6>[ 0.101785] CPU features: detected: Spectre-v4
10135 13:54:43.372961 <6>[ 0.101792] CPU features: detected: Spectre-BHB
10136 13:54:43.376606 <6>[ 0.101797] Detected PIPT I-cache on CPU4
10137 13:54:43.382785 <6>[ 0.101853] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10138 13:54:43.390050 <6>[ 0.101869] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10139 13:54:43.396401 <6>[ 0.102159] Detected PIPT I-cache on CPU5
10140 13:54:43.403137 <6>[ 0.102221] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10141 13:54:43.409809 <6>[ 0.102238] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10142 13:54:43.414298 <6>[ 0.102519] Detected PIPT I-cache on CPU6
10143 13:54:43.419639 <6>[ 0.102579] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10144 13:54:43.426075 <6>[ 0.102596] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10145 13:54:43.433156 <6>[ 0.102896] Detected PIPT I-cache on CPU7
10146 13:54:43.439566 <6>[ 0.102959] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10147 13:54:43.445947 <6>[ 0.102976] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10148 13:54:43.449531 <6>[ 0.103024] smp: Brought up 1 node, 8 CPUs
10149 13:54:43.456401 <6>[ 0.244303] SMP: Total of 8 processors activated.
10150 13:54:43.458678 <6>[ 0.249224] CPU features: detected: 32-bit EL0 Support
10151 13:54:43.470581 <6>[ 0.254586] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10152 13:54:43.475749 <6>[ 0.263386] CPU features: detected: Common not Private translations
10153 13:54:43.482395 <6>[ 0.269902] CPU features: detected: CRC32 instructions
10154 13:54:43.486117 <6>[ 0.275286] CPU features: detected: RCpc load-acquire (LDAPR)
10155 13:54:43.492008 <6>[ 0.281283] CPU features: detected: LSE atomic instructions
10156 13:54:43.499062 <6>[ 0.287064] CPU features: detected: Privileged Access Never
10157 13:54:43.505408 <6>[ 0.292844] CPU features: detected: RAS Extension Support
10158 13:54:43.512811 <6>[ 0.298453] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10159 13:54:43.515308 <6>[ 0.305672] CPU: All CPU(s) started at EL2
10160 13:54:43.522561 <6>[ 0.309989] alternatives: applying system-wide alternatives
10161 13:54:43.531056 <6>[ 0.319936] devtmpfs: initialized
10162 13:54:43.542166 <6>[ 0.328117] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10163 13:54:43.551589 <6>[ 0.338076] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10164 13:54:43.558219 <6>[ 0.346278] pinctrl core: initialized pinctrl subsystem
10165 13:54:43.561799 <6>[ 0.352918] DMI not present or invalid.
10166 13:54:43.568941 <6>[ 0.357242] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10167 13:54:43.579465 <6>[ 0.364096] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10168 13:54:43.585499 <6>[ 0.371543] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10169 13:54:43.595019 <6>[ 0.379631] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10170 13:54:43.598010 <6>[ 0.387785] audit: initializing netlink subsys (disabled)
10171 13:54:43.608139 <5>[ 0.393481] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10172 13:54:43.615087 <6>[ 0.394161] thermal_sys: Registered thermal governor 'step_wise'
10173 13:54:43.621040 <6>[ 0.401445] thermal_sys: Registered thermal governor 'power_allocator'
10174 13:54:43.625108 <6>[ 0.407699] cpuidle: using governor menu
10175 13:54:43.631301 <6>[ 0.418658] NET: Registered PF_QIPCRTR protocol family
10176 13:54:43.637516 <6>[ 0.424134] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10177 13:54:43.640589 <6>[ 0.431232] ASID allocator initialised with 32768 entries
10178 13:54:43.648059 <6>[ 0.437770] Serial: AMBA PL011 UART driver
10179 13:54:43.656900 <4>[ 0.446511] Trying to register duplicate clock ID: 134
10180 13:54:43.711299 <6>[ 0.503831] KASLR enabled
10181 13:54:43.725488 <6>[ 0.511587] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10182 13:54:43.732143 <6>[ 0.518599] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10183 13:54:43.738522 <6>[ 0.525088] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10184 13:54:43.745806 <6>[ 0.532092] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10185 13:54:43.751969 <6>[ 0.538580] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10186 13:54:43.758723 <6>[ 0.545583] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10187 13:54:43.764678 <6>[ 0.552072] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10188 13:54:43.771557 <6>[ 0.559073] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10189 13:54:43.775183 <6>[ 0.566514] ACPI: Interpreter disabled.
10190 13:54:43.784014 <6>[ 0.572910] iommu: Default domain type: Translated
10191 13:54:43.790249 <6>[ 0.578067] iommu: DMA domain TLB invalidation policy: strict mode
10192 13:54:43.793706 <5>[ 0.584731] SCSI subsystem initialized
10193 13:54:43.800828 <6>[ 0.588989] usbcore: registered new interface driver usbfs
10194 13:54:43.807710 <6>[ 0.594720] usbcore: registered new interface driver hub
10195 13:54:43.809499 <6>[ 0.600273] usbcore: registered new device driver usb
10196 13:54:43.817318 <6>[ 0.606393] pps_core: LinuxPPS API ver. 1 registered
10197 13:54:43.826464 <6>[ 0.611588] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10198 13:54:43.829673 <6>[ 0.620932] PTP clock support registered
10199 13:54:43.833615 <6>[ 0.625172] EDAC MC: Ver: 3.0.0
10200 13:54:43.840829 <6>[ 0.630337] FPGA manager framework
10201 13:54:43.847506 <6>[ 0.634016] Advanced Linux Sound Architecture Driver Initialized.
10202 13:54:43.850752 <6>[ 0.640779] vgaarb: loaded
10203 13:54:43.857688 <6>[ 0.643929] clocksource: Switched to clocksource arch_sys_counter
10204 13:54:43.860593 <5>[ 0.650383] VFS: Disk quotas dquot_6.6.0
10205 13:54:43.868241 <6>[ 0.654568] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10206 13:54:43.870413 <6>[ 0.661761] pnp: PnP ACPI: disabled
10207 13:54:43.879124 <6>[ 0.668488] NET: Registered PF_INET protocol family
10208 13:54:43.885673 <6>[ 0.673871] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10209 13:54:43.897741 <6>[ 0.683895] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10210 13:54:43.907780 <6>[ 0.692676] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10211 13:54:43.914389 <6>[ 0.700643] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10212 13:54:43.922027 <6>[ 0.709035] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10213 13:54:43.931595 <6>[ 0.717696] TCP: Hash tables configured (established 32768 bind 32768)
10214 13:54:43.938092 <6>[ 0.724551] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10215 13:54:43.944917 <6>[ 0.731572] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10216 13:54:43.951075 <6>[ 0.739097] NET: Registered PF_UNIX/PF_LOCAL protocol family
10217 13:54:43.957905 <6>[ 0.745236] RPC: Registered named UNIX socket transport module.
10218 13:54:43.961612 <6>[ 0.751388] RPC: Registered udp transport module.
10219 13:54:43.968150 <6>[ 0.756322] RPC: Registered tcp transport module.
10220 13:54:43.974788 <6>[ 0.761252] RPC: Registered tcp NFSv4.1 backchannel transport module.
10221 13:54:43.977504 <6>[ 0.767924] PCI: CLS 0 bytes, default 64
10222 13:54:43.981675 <6>[ 0.772284] Unpacking initramfs...
10223 13:54:43.991835 <6>[ 0.775986] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10224 13:54:43.998083 <6>[ 0.784620] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10225 13:54:44.005007 <6>[ 0.793421] kvm [1]: IPA Size Limit: 40 bits
10226 13:54:44.009252 <6>[ 0.797949] kvm [1]: GICv3: no GICV resource entry
10227 13:54:44.014301 <6>[ 0.802970] kvm [1]: disabling GICv2 emulation
10228 13:54:44.021390 <6>[ 0.807657] kvm [1]: GIC system register CPU interface enabled
10229 13:54:44.024910 <6>[ 0.813823] kvm [1]: vgic interrupt IRQ18
10230 13:54:44.027334 <6>[ 0.818185] kvm [1]: VHE mode initialized successfully
10231 13:54:44.035176 <5>[ 0.824693] Initialise system trusted keyrings
10232 13:54:44.041865 <6>[ 0.829520] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10233 13:54:44.050085 <6>[ 0.839479] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10234 13:54:44.056415 <5>[ 0.845834] NFS: Registering the id_resolver key type
10235 13:54:44.060256 <5>[ 0.851131] Key type id_resolver registered
10236 13:54:44.066211 <5>[ 0.855547] Key type id_legacy registered
10237 13:54:44.073341 <6>[ 0.859825] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10238 13:54:44.080261 <6>[ 0.866748] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10239 13:54:44.086426 <6>[ 0.874477] 9p: Installing v9fs 9p2000 file system support
10240 13:54:44.124331 <5>[ 0.912776] Key type asymmetric registered
10241 13:54:44.126782 <5>[ 0.917110] Asymmetric key parser 'x509' registered
10242 13:54:44.138290 <6>[ 0.922254] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10243 13:54:44.139980 <6>[ 0.929869] io scheduler mq-deadline registered
10244 13:54:44.142717 <6>[ 0.934634] io scheduler kyber registered
10245 13:54:44.161894 <6>[ 0.951628] EINJ: ACPI disabled.
10246 13:54:44.194265 <4>[ 0.976626] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10247 13:54:44.203551 <4>[ 0.987245] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10248 13:54:44.219176 <6>[ 1.008309] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10249 13:54:44.227140 <6>[ 1.016357] printk: console [ttyS0] disabled
10250 13:54:44.254817 <6>[ 1.041002] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10251 13:54:44.261577 <6>[ 1.050477] printk: console [ttyS0] enabled
10252 13:54:44.264897 <6>[ 1.050477] printk: console [ttyS0] enabled
10253 13:54:44.272102 <6>[ 1.059372] printk: bootconsole [mtk8250] disabled
10254 13:54:44.274938 <6>[ 1.059372] printk: bootconsole [mtk8250] disabled
10255 13:54:44.281380 <6>[ 1.070577] SuperH (H)SCI(F) driver initialized
10256 13:54:44.284823 <6>[ 1.075864] msm_serial: driver initialized
10257 13:54:44.299096 <6>[ 1.084833] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10258 13:54:44.308613 <6>[ 1.093381] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10259 13:54:44.315260 <6>[ 1.101925] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10260 13:54:44.326105 <6>[ 1.110553] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10261 13:54:44.335356 <6>[ 1.119261] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10262 13:54:44.343282 <6>[ 1.127976] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10263 13:54:44.351581 <6>[ 1.136524] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10264 13:54:44.359375 <6>[ 1.145330] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10265 13:54:44.368072 <6>[ 1.153874] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10266 13:54:44.380153 <6>[ 1.169650] loop: module loaded
10267 13:54:44.386584 <6>[ 1.175649] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10268 13:54:44.409274 <4>[ 1.198887] mtk-pmic-keys: Failed to locate of_node [id: -1]
10269 13:54:44.416550 <6>[ 1.205929] megasas: 07.719.03.00-rc1
10270 13:54:44.425744 <6>[ 1.215510] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10271 13:54:44.434072 <6>[ 1.223410] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10272 13:54:44.450598 <6>[ 1.239943] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10273 13:54:44.507040 <6>[ 1.289322] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10274 13:54:44.716643 <6>[ 1.506463] Freeing initrd memory: 17380K
10275 13:54:44.727055 <6>[ 1.516563] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10276 13:54:44.737700 <6>[ 1.527432] tun: Universal TUN/TAP device driver, 1.6
10277 13:54:44.740860 <6>[ 1.533491] thunder_xcv, ver 1.0
10278 13:54:44.745164 <6>[ 1.537009] thunder_bgx, ver 1.0
10279 13:54:44.747971 <6>[ 1.540503] nicpf, ver 1.0
10280 13:54:44.758402 <6>[ 1.544514] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10281 13:54:44.761426 <6>[ 1.551991] hns3: Copyright (c) 2017 Huawei Corporation.
10282 13:54:44.768207 <6>[ 1.557577] hclge is initializing
10283 13:54:44.771312 <6>[ 1.561156] e1000: Intel(R) PRO/1000 Network Driver
10284 13:54:44.778264 <6>[ 1.566285] e1000: Copyright (c) 1999-2006 Intel Corporation.
10285 13:54:44.782009 <6>[ 1.572296] e1000e: Intel(R) PRO/1000 Network Driver
10286 13:54:44.788276 <6>[ 1.577511] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10287 13:54:44.794644 <6>[ 1.583699] igb: Intel(R) Gigabit Ethernet Network Driver
10288 13:54:44.801422 <6>[ 1.589349] igb: Copyright (c) 2007-2014 Intel Corporation.
10289 13:54:44.808323 <6>[ 1.595185] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10290 13:54:44.814684 <6>[ 1.601703] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10291 13:54:44.818211 <6>[ 1.608165] sky2: driver version 1.30
10292 13:54:44.824890 <6>[ 1.613144] VFIO - User Level meta-driver version: 0.3
10293 13:54:44.831814 <6>[ 1.621340] usbcore: registered new interface driver usb-storage
10294 13:54:44.838378 <6>[ 1.627782] usbcore: registered new device driver onboard-usb-hub
10295 13:54:44.847255 <6>[ 1.636921] mt6397-rtc mt6359-rtc: registered as rtc0
10296 13:54:44.857291 <6>[ 1.642395] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:54:45 UTC (1706795685)
10297 13:54:44.861459 <6>[ 1.652003] i2c_dev: i2c /dev entries driver
10298 13:54:44.877508 <6>[ 1.663614] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10299 13:54:44.897620 <6>[ 1.686582] cpu cpu0: EM: created perf domain
10300 13:54:44.900429 <6>[ 1.691485] cpu cpu4: EM: created perf domain
10301 13:54:44.907562 <6>[ 1.696972] sdhci: Secure Digital Host Controller Interface driver
10302 13:54:44.914706 <6>[ 1.703405] sdhci: Copyright(c) Pierre Ossman
10303 13:54:44.922003 <6>[ 1.708326] Synopsys Designware Multimedia Card Interface Driver
10304 13:54:44.927512 <6>[ 1.714896] sdhci-pltfm: SDHCI platform and OF driver helper
10305 13:54:44.931646 <6>[ 1.714940] mmc0: CQHCI version 5.10
10306 13:54:44.937480 <6>[ 1.724906] ledtrig-cpu: registered to indicate activity on CPUs
10307 13:54:44.944276 <6>[ 1.731640] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10308 13:54:44.950432 <6>[ 1.738687] usbcore: registered new interface driver usbhid
10309 13:54:44.953949 <6>[ 1.744509] usbhid: USB HID core driver
10310 13:54:44.960589 <6>[ 1.748734] spi_master spi0: will run message pump with realtime priority
10311 13:54:45.007166 <6>[ 1.790242] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10312 13:54:45.027898 <6>[ 1.805827] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10313 13:54:45.030196 <6>[ 1.819484] mmc0: Command Queue Engine enabled
10314 13:54:45.037232 <6>[ 1.820836] cros-ec-spi spi0.0: Chrome EC device registered
10315 13:54:45.043244 <6>[ 1.824211] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10316 13:54:45.046805 <6>[ 1.837434] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10317 13:54:45.057532 <6>[ 1.843657] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10318 13:54:45.064129 <6>[ 1.848276] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10319 13:54:45.071187 <6>[ 1.853859] NET: Registered PF_PACKET protocol family
10320 13:54:45.073517 <6>[ 1.860320] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10321 13:54:45.080798 <6>[ 1.864261] 9pnet: Installing 9P2000 support
10322 13:54:45.084117 <6>[ 1.870142] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10323 13:54:45.090399 <5>[ 1.873954] Key type dns_resolver registered
10324 13:54:45.097185 <6>[ 1.879699] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10325 13:54:45.100869 <6>[ 1.884086] registered taskstats version 1
10326 13:54:45.103713 <5>[ 1.894544] Loading compiled-in X.509 certificates
10327 13:54:45.131937 <4>[ 1.914096] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10328 13:54:45.141629 <4>[ 1.924716] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10329 13:54:45.147806 <3>[ 1.935234] debugfs: File 'uA_load' in directory '/' already present!
10330 13:54:45.154176 <3>[ 1.941928] debugfs: File 'min_uV' in directory '/' already present!
10331 13:54:45.160836 <3>[ 1.948528] debugfs: File 'max_uV' in directory '/' already present!
10332 13:54:45.167620 <3>[ 1.955172] debugfs: File 'constraint_flags' in directory '/' already present!
10333 13:54:45.178125 <3>[ 1.964114] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10334 13:54:45.186177 <6>[ 1.975803] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10335 13:54:45.192695 <6>[ 1.982558] xhci-mtk 11200000.usb: xHCI Host Controller
10336 13:54:45.199617 <6>[ 1.988093] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10337 13:54:45.210453 <6>[ 1.995976] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10338 13:54:45.217208 <6>[ 2.005390] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10339 13:54:45.223205 <6>[ 2.011449] xhci-mtk 11200000.usb: xHCI Host Controller
10340 13:54:45.229531 <6>[ 2.016924] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10341 13:54:45.236560 <6>[ 2.024570] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10342 13:54:45.242783 <6>[ 2.032314] hub 1-0:1.0: USB hub found
10343 13:54:45.246124 <6>[ 2.036328] hub 1-0:1.0: 1 port detected
10344 13:54:45.252841 <6>[ 2.040593] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10345 13:54:45.259808 <6>[ 2.049300] hub 2-0:1.0: USB hub found
10346 13:54:45.263200 <6>[ 2.053314] hub 2-0:1.0: 1 port detected
10347 13:54:45.272160 <6>[ 2.061078] mtk-msdc 11f70000.mmc: Got CD GPIO
10348 13:54:45.287519 <6>[ 2.073290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10349 13:54:45.293734 <6>[ 2.081320] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10350 13:54:45.304267 <4>[ 2.089226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10351 13:54:45.314508 <6>[ 2.098743] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10352 13:54:45.320324 <6>[ 2.106818] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10353 13:54:45.327460 <6>[ 2.114824] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10354 13:54:45.337224 <6>[ 2.122742] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10355 13:54:45.343764 <6>[ 2.130559] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10356 13:54:45.353871 <6>[ 2.138376] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10357 13:54:45.363566 <6>[ 2.148811] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10358 13:54:45.370524 <6>[ 2.157180] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10359 13:54:45.380009 <6>[ 2.165528] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10360 13:54:45.386719 <6>[ 2.173867] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10361 13:54:45.396903 <6>[ 2.182204] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10362 13:54:45.403167 <6>[ 2.190543] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10363 13:54:45.412918 <6>[ 2.198881] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10364 13:54:45.419781 <6>[ 2.207218] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10365 13:54:45.429636 <6>[ 2.215557] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10366 13:54:45.436464 <6>[ 2.223895] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10367 13:54:45.446157 <6>[ 2.232233] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10368 13:54:45.453709 <6>[ 2.240570] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10369 13:54:45.462998 <6>[ 2.248910] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10370 13:54:45.469512 <6>[ 2.257256] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10371 13:54:45.479404 <6>[ 2.265594] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10372 13:54:45.486926 <6>[ 2.274310] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10373 13:54:45.493176 <6>[ 2.281441] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10374 13:54:45.499361 <6>[ 2.288181] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10375 13:54:45.506201 <6>[ 2.294911] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10376 13:54:45.512580 <6>[ 2.301833] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10377 13:54:45.522345 <6>[ 2.308678] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10378 13:54:45.532979 <6>[ 2.317811] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10379 13:54:45.543263 <6>[ 2.326929] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10380 13:54:45.551905 <6>[ 2.336223] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10381 13:54:45.562725 <6>[ 2.345689] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10382 13:54:45.568901 <6>[ 2.355154] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10383 13:54:45.579469 <6>[ 2.364272] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10384 13:54:45.588488 <6>[ 2.373737] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10385 13:54:45.598980 <6>[ 2.382855] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10386 13:54:45.608750 <6>[ 2.392148] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10387 13:54:45.618189 <6>[ 2.402308] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10388 13:54:45.628606 <6>[ 2.413859] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10389 13:54:45.634648 <6>[ 2.423524] Trying to probe devices needed for running init ...
10390 13:54:45.678112 <6>[ 2.464194] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10391 13:54:45.832878 <6>[ 2.621984] hub 1-1:1.0: USB hub found
10392 13:54:45.835497 <6>[ 2.626488] hub 1-1:1.0: 4 ports detected
10393 13:54:45.845343 <6>[ 2.635149] hub 1-1:1.0: USB hub found
10394 13:54:45.849071 <6>[ 2.639520] hub 1-1:1.0: 4 ports detected
10395 13:54:45.958138 <6>[ 2.744463] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10396 13:54:45.983538 <6>[ 2.773258] hub 2-1:1.0: USB hub found
10397 13:54:45.987245 <6>[ 2.777700] hub 2-1:1.0: 3 ports detected
10398 13:54:45.996169 <6>[ 2.784708] hub 2-1:1.0: USB hub found
10399 13:54:45.998687 <6>[ 2.789149] hub 2-1:1.0: 3 ports detected
10400 13:54:46.174504 <6>[ 2.960216] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10401 13:54:46.306135 <6>[ 3.095270] hub 1-1.4:1.0: USB hub found
10402 13:54:46.308677 <6>[ 3.099780] hub 1-1.4:1.0: 2 ports detected
10403 13:54:46.321631 <6>[ 3.106830] hub 1-1.4:1.0: USB hub found
10404 13:54:46.322892 <6>[ 3.111462] hub 1-1.4:1.0: 2 ports detected
10405 13:54:46.390479 <6>[ 3.176256] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10406 13:54:46.618308 <6>[ 3.404244] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10407 13:54:46.810267 <6>[ 3.596213] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10408 13:54:57.914991 <6>[ 14.709260] ALSA device list:
10409 13:54:57.920731 <6>[ 14.712552] No soundcards found.
10410 13:54:57.929004 <6>[ 14.720341] Freeing unused kernel memory: 8448K
10411 13:54:57.932501 <6>[ 14.725368] Run /init as init process
10412 13:54:57.943376 Loading, please wait...
10413 13:54:57.968678 Starting version 247.3-7+deb11u2
10414 13:54:58.202878 <6>[ 14.989512] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10415 13:54:58.212086 <3>[ 14.999526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10416 13:54:58.218000 <3>[ 15.007809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10417 13:54:58.224826 <6>[ 15.008656] mc: Linux media interface: v0.10
10418 13:54:58.231421 <6>[ 15.008764] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10419 13:54:58.241506 <6>[ 15.008787] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10420 13:54:58.248491 <6>[ 15.008792] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10421 13:54:58.254971 <6>[ 15.008891] usbcore: registered new device driver r8152-cfgselector
10422 13:54:58.261827 <6>[ 15.011713] remoteproc remoteproc0: scp is available
10423 13:54:58.268332 <6>[ 15.011767] remoteproc remoteproc0: powering up scp
10424 13:54:58.274524 <6>[ 15.011772] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10425 13:54:58.281514 <6>[ 15.011790] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10426 13:54:58.288915 <3>[ 15.016146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 13:54:58.295043 <4>[ 15.031761] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10428 13:54:58.304449 <3>[ 15.037184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10429 13:54:58.311764 <6>[ 15.037396] videodev: Linux video capture interface: v2.00
10430 13:54:58.318394 <4>[ 15.049082] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10431 13:54:58.324796 <3>[ 15.052219] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10432 13:54:58.334674 <3>[ 15.052235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10433 13:54:58.342471 <3>[ 15.052241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10434 13:54:58.348766 <3>[ 15.052245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10435 13:54:58.359262 <3>[ 15.052324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10436 13:54:58.365449 <3>[ 15.052383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10437 13:54:58.372551 <3>[ 15.052388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10438 13:54:58.382544 <3>[ 15.052390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10439 13:54:58.389398 <3>[ 15.052443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10440 13:54:58.399112 <6>[ 15.058304] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10441 13:54:58.405241 <3>[ 15.062786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10442 13:54:58.415612 <3>[ 15.062791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10443 13:54:58.421743 <3>[ 15.062797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10444 13:54:58.428643 <3>[ 15.062800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10445 13:54:58.438151 <4>[ 15.089190] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10446 13:54:58.444855 <4>[ 15.089190] Fallback method does not support PEC.
10447 13:54:58.451727 <3>[ 15.092308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10448 13:54:58.462396 <3>[ 15.114154] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10449 13:54:58.467948 <6>[ 15.124331] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10450 13:54:58.475788 <6>[ 15.134801] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10451 13:54:58.484931 <6>[ 15.137216] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10452 13:54:58.491226 <6>[ 15.137222] remoteproc remoteproc0: remote processor scp is now up
10453 13:54:58.498110 <6>[ 15.137231] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10454 13:54:58.507637 <3>[ 15.150749] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10455 13:54:58.511648 <6>[ 15.153983] pci_bus 0000:00: root bus resource [bus 00-ff]
10456 13:54:58.521070 <4>[ 15.160223] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10457 13:54:58.531114 <4>[ 15.160235] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10458 13:54:58.541920 <6>[ 15.161460] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10459 13:54:58.547363 <6>[ 15.161840] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10460 13:54:58.557619 <6>[ 15.174403] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10461 13:54:58.565041 <6>[ 15.178075] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10462 13:54:58.574263 <6>[ 15.178078] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10463 13:54:58.580061 <6>[ 15.178109] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10464 13:54:58.590697 <6>[ 15.206052] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10465 13:54:58.596861 <6>[ 15.209981] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10466 13:54:58.600490 <6>[ 15.210069] pci 0000:00:00.0: supports D1 D2
10467 13:54:58.610576 <6>[ 15.221035] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10468 13:54:58.617792 <6>[ 15.226200] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10469 13:54:58.625148 <6>[ 15.227210] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10470 13:54:58.629878 <6>[ 15.227717] Bluetooth: Core ver 2.22
10471 13:54:58.634235 <6>[ 15.227983] NET: Registered PF_BLUETOOTH protocol family
10472 13:54:58.639898 <6>[ 15.227988] Bluetooth: HCI device and connection manager initialized
10473 13:54:58.646342 <6>[ 15.228041] Bluetooth: HCI socket layer initialized
10474 13:54:58.649274 <6>[ 15.228053] Bluetooth: L2CAP socket layer initialized
10475 13:54:58.656868 <6>[ 15.228069] Bluetooth: SCO socket layer initialized
10476 13:54:58.659992 <6>[ 15.228159] r8152 2-1.3:1.0 eth0: v1.12.13
10477 13:54:58.666648 <6>[ 15.228286] usbcore: registered new interface driver r8152
10478 13:54:58.673691 <6>[ 15.249775] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10479 13:54:58.679234 <6>[ 15.256853] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10480 13:54:58.686116 <6>[ 15.257138] usbcore: registered new interface driver cdc_ether
10481 13:54:58.699464 <6>[ 15.266403] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10482 13:54:58.706107 <6>[ 15.271948] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10483 13:54:58.712567 <6>[ 15.272300] usbcore: registered new interface driver r8153_ecm
10484 13:54:58.718838 <6>[ 15.272815] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10485 13:54:58.725921 <6>[ 15.280640] usbcore: registered new interface driver uvcvideo
10486 13:54:58.732167 <6>[ 15.286886] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10487 13:54:58.738697 <6>[ 15.289654] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10488 13:54:58.741935 <6>[ 15.303151] usbcore: registered new interface driver btusb
10489 13:54:58.755669 <4>[ 15.303704] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10490 13:54:58.759337 <3>[ 15.303709] Bluetooth: hci0: Failed to load firmware file (-2)
10491 13:54:58.766202 <3>[ 15.303711] Bluetooth: hci0: Failed to set up firmware (-2)
10492 13:54:58.775071 <4>[ 15.303713] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10493 13:54:58.785931 <6>[ 15.308428] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10494 13:54:58.788081 <6>[ 15.579895] pci 0000:01:00.0: supports D1 D2
10495 13:54:58.794869 <6>[ 15.584414] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10496 13:54:58.812491 <6>[ 15.599966] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10497 13:54:58.818765 <6>[ 15.606859] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10498 13:54:58.825629 <6>[ 15.614940] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10499 13:54:58.835722 <6>[ 15.622938] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10500 13:54:58.841994 <6>[ 15.630939] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10501 13:54:58.852177 <6>[ 15.638939] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10502 13:54:58.856077 <6>[ 15.646941] pci 0000:00:00.0: PCI bridge to [bus 01]
10503 13:54:58.865067 <6>[ 15.652156] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10504 13:54:58.871730 <6>[ 15.660262] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10505 13:54:58.878620 <6>[ 15.667117] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10506 13:54:58.884419 <6>[ 15.673841] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10507 13:54:58.899310 <5>[ 15.687511] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10508 13:54:58.921239 <5>[ 15.708120] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10509 13:54:58.926790 <5>[ 15.715447] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10510 13:54:58.936667 <4>[ 15.723881] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10511 13:54:58.940481 <6>[ 15.732792] cfg80211: failed to load regulatory.db
10512 13:54:58.982718 <6>[ 15.770146] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10513 13:54:58.989786 <6>[ 15.777647] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10514 13:54:59.013093 <6>[ 15.804359] mt7921e 0000:01:00.0: ASIC revision: 79610010
10515 13:54:59.115529 <6>[ 15.903204] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10516 13:54:59.119137 <6>[ 15.903204]
10517 13:54:59.122589 Begin: Loading essential drivers ... done.
10518 13:54:59.124930 Begin: Running /scripts/init-premount ... done.
10519 13:54:59.132003 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10520 13:54:59.141884 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10521 13:54:59.144910 Device /sys/class/net/enx00e04c6803bd found
10522 13:54:59.145364 done.
10523 13:54:59.213148 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10524 13:54:59.386975 <6>[ 16.173711] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10525 13:55:00.012826 <6>[ 16.804660] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10526 13:55:00.226449 <6>[ 17.017896] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10527 13:55:00.351146 IP-Config: no response after 2 secs - giving up
10528 13:55:00.390034 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10529 13:55:01.100834 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10530 13:55:01.103670 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10531 13:55:01.110321 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10532 13:55:01.119760 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10533 13:55:01.126368 host : mt8192-asurada-spherion-r0-cbg-4
10534 13:55:01.132516 domain : lava-rack
10535 13:55:01.136028 rootserver: 192.168.201.1 rootpath:
10536 13:55:01.136906 filename :
10537 13:55:01.211203 done.
10538 13:55:01.214057 Begin: Running /scripts/nfs-bottom ... done.
10539 13:55:01.232403 Begin: Running /scripts/init-bottom ... done.
10540 13:55:02.375419 <6>[ 19.167262] NET: Registered PF_INET6 protocol family
10541 13:55:02.383597 <6>[ 19.175067] Segment Routing with IPv6
10542 13:55:02.387069 <6>[ 19.179027] In-situ OAM (IOAM) with IPv6
10543 13:55:02.525082 <30>[ 19.297724] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10544 13:55:02.529509 <30>[ 19.322131] systemd[1]: Detected architecture arm64.
10545 13:55:02.548819
10546 13:55:02.552183 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10547 13:55:02.552271
10548 13:55:02.570040 <30>[ 19.362359] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10549 13:55:03.341835 <30>[ 20.130594] systemd[1]: Queued start job for default target Graphical Interface.
10550 13:55:03.374295 <30>[ 20.166526] systemd[1]: Created slice system-getty.slice.
10551 13:55:03.380921 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10552 13:55:03.397713 <30>[ 20.189610] systemd[1]: Created slice system-modprobe.slice.
10553 13:55:03.404047 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10554 13:55:03.420899 <30>[ 20.213427] systemd[1]: Created slice system-serial\x2dgetty.slice.
10555 13:55:03.431332 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10556 13:55:03.445497 <30>[ 20.237273] systemd[1]: Created slice User and Session Slice.
10557 13:55:03.451859 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10558 13:55:03.473095 <30>[ 20.260974] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10559 13:55:03.481856 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10560 13:55:03.500369 <30>[ 20.288971] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10561 13:55:03.506622 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10562 13:55:03.530572 <30>[ 20.316383] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10563 13:55:03.537695 <30>[ 20.328530] systemd[1]: Reached target Local Encrypted Volumes.
10564 13:55:03.543759 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10565 13:55:03.561075 <30>[ 20.352786] systemd[1]: Reached target Paths.
10566 13:55:03.564572 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10567 13:55:03.580000 <30>[ 20.372219] systemd[1]: Reached target Remote File Systems.
10568 13:55:03.586591 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10569 13:55:03.604337 <30>[ 20.396579] systemd[1]: Reached target Slices.
10570 13:55:03.610707 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10571 13:55:03.625060 <30>[ 20.416233] systemd[1]: Reached target Swap.
10572 13:55:03.627072 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10573 13:55:03.647543 <30>[ 20.436735] systemd[1]: Listening on initctl Compatibility Named Pipe.
10574 13:55:03.654213 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10575 13:55:03.660660 <30>[ 20.452761] systemd[1]: Listening on Journal Audit Socket.
10576 13:55:03.667578 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10577 13:55:03.685211 <30>[ 20.477413] systemd[1]: Listening on Journal Socket (/dev/log).
10578 13:55:03.691772 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10579 13:55:03.708535 <30>[ 20.500819] systemd[1]: Listening on Journal Socket.
10580 13:55:03.715225 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10581 13:55:03.732867 <30>[ 20.521543] systemd[1]: Listening on Network Service Netlink Socket.
10582 13:55:03.739450 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10583 13:55:03.754306 <30>[ 20.546651] systemd[1]: Listening on udev Control Socket.
10584 13:55:03.760888 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10585 13:55:03.776834 <30>[ 20.568657] systemd[1]: Listening on udev Kernel Socket.
10586 13:55:03.783053 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10587 13:55:03.834638 <30>[ 20.624631] systemd[1]: Mounting Huge Pages File System...
10588 13:55:03.838862 Mounting [0;1;39mHuge Pages File System[0m...
10589 13:55:03.856635 <30>[ 20.648867] systemd[1]: Mounting POSIX Message Queue File System...
10590 13:55:03.863337 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10591 13:55:03.883051 <30>[ 20.675318] systemd[1]: Mounting Kernel Debug File System...
10592 13:55:03.889431 Mounting [0;1;39mKernel Debug File System[0m...
10593 13:55:03.907576 <30>[ 20.696826] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10594 13:55:03.956869 <30>[ 20.744974] systemd[1]: Starting Create list of static device nodes for the current kernel...
10595 13:55:03.962788 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10596 13:55:03.988411 <30>[ 20.780934] systemd[1]: Starting Load Kernel Module configfs...
10597 13:55:03.995176 Starting [0;1;39mLoad Kernel Module configfs[0m...
10598 13:55:04.016690 <30>[ 20.809155] systemd[1]: Starting Load Kernel Module drm...
10599 13:55:04.024488 Starting [0;1;39mLoad Kernel Module drm[0m...
10600 13:55:04.044594 <30>[ 20.837129] systemd[1]: Starting Load Kernel Module fuse...
10601 13:55:04.051785 Starting [0;1;39mLoad Kernel Module fuse[0m...
10602 13:55:04.079524 <6>[ 20.871897] fuse: init (API version 7.37)
10603 13:55:04.089689 <30>[ 20.872557] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10604 13:55:04.132911 <30>[ 20.924987] systemd[1]: Starting Journal Service...
10605 13:55:04.139765 Starting [0;1;39mJournal Service[0m...
10606 13:55:04.161959 <30>[ 20.954564] systemd[1]: Starting Load Kernel Modules...
10607 13:55:04.168718 Starting [0;1;39mLoad Kernel Modules[0m...
10608 13:55:04.192202 <30>[ 20.980166] systemd[1]: Starting Remount Root and Kernel File Systems...
10609 13:55:04.197418 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10610 13:55:04.216252 <30>[ 21.008430] systemd[1]: Starting Coldplug All udev Devices...
10611 13:55:04.222365 Starting [0;1;39mColdplug All udev Devices[0m...
10612 13:55:04.245703 <3>[ 21.033640] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10613 13:55:04.252048 <30>[ 21.034939] systemd[1]: Mounted Huge Pages File System.
10614 13:55:04.258094 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10615 13:55:04.272678 <30>[ 21.064813] systemd[1]: Mounted POSIX Message Queue File System.
10616 13:55:04.282995 <3>[ 21.066250] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10617 13:55:04.289705 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10618 13:55:04.304517 <30>[ 21.096650] systemd[1]: Mounted Kernel Debug File System.
10619 13:55:04.311682 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10620 13:55:04.323296 <3>[ 21.112446] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10621 13:55:04.334242 <30>[ 21.123182] systemd[1]: Finished Create list of static device nodes for the current kernel.
10622 13:55:04.344574 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10623 13:55:04.355272 <3>[ 21.142325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10624 13:55:04.361052 <30>[ 21.153017] systemd[1]: modprobe@configfs.service: Succeeded.
10625 13:55:04.368252 <30>[ 21.160057] systemd[1]: Finished Load Kernel Module configfs.
10626 13:55:04.375704 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10627 13:55:04.385992 <3>[ 21.173248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10628 13:55:04.392283 <30>[ 21.183195] systemd[1]: modprobe@drm.service: Succeeded.
10629 13:55:04.400338 <30>[ 21.189491] systemd[1]: Finished Load Kernel Module drm.
10630 13:55:04.402352 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10631 13:55:04.415492 <3>[ 21.204101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10632 13:55:04.422006 <30>[ 21.214198] systemd[1]: modprobe@fuse.service: Succeeded.
10633 13:55:04.428539 <30>[ 21.220777] systemd[1]: Finished Load Kernel Module fuse.
10634 13:55:04.435751 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10635 13:55:04.445684 <3>[ 21.233431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10636 13:55:04.453514 <30>[ 21.245306] systemd[1]: Finished Load Kernel Modules.
10637 13:55:04.460400 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10638 13:55:04.475251 <3>[ 21.264627] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10639 13:55:04.482384 <30>[ 21.266084] systemd[1]: Finished Remount Root and Kernel File Systems.
10640 13:55:04.492150 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10641 13:55:04.505500 <3>[ 21.294488] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10642 13:55:04.532952 <3>[ 21.321680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 13:55:04.539248 <30>[ 21.323691] systemd[1]: Mounting FUSE Control File System...
10644 13:55:04.545988 Mounting [0;1;39mFUSE Control File System[0m...
10645 13:55:04.566657 <30>[ 21.354790] systemd[1]: Mounting Kernel Configuration File System...
10646 13:55:04.569420 Mounting [0;1;39mKernel Configuration File System[0m...
10647 13:55:04.592126 <30>[ 21.381050] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10648 13:55:04.601907 <30>[ 21.390054] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10649 13:55:04.611273 <30>[ 21.403305] systemd[1]: Starting Load/Save Random Seed...
10650 13:55:04.617969 Starting [0;1;39mLoad/Save Random Seed[0m...
10651 13:55:04.640518 <30>[ 21.431917] systemd[1]: Starting Apply Kernel Variables...
10652 13:55:04.647706 Starting [0;1;39mApply Kernel Variables[0m...
10653 13:55:04.665574 <30>[ 21.458145] systemd[1]: Starting Create System Users...
10654 13:55:04.672424 Starting [0;1;39mCreate System Users[0m...
10655 13:55:04.693548 <4>[ 21.476031] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10656 13:55:04.704023 <3>[ 21.491773] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10657 13:55:04.707857 <30>[ 21.493343] systemd[1]: Started Journal Service.
10658 13:55:04.713639 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10659 13:55:04.733548 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10660 13:55:04.744134 See 'systemctl status systemd-udev-trigger.service' for details.
10661 13:55:04.765876 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10662 13:55:04.780621 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10663 13:55:04.797283 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10664 13:55:04.814206 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10665 13:55:04.830496 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10666 13:55:04.893820 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10667 13:55:04.910760 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10668 13:55:04.928700 <46>[ 21.717811] systemd-journald[300]: Received client request to flush runtime journal.
10669 13:55:05.684514 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10670 13:55:05.696661 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10671 13:55:05.711781 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10672 13:55:05.772249 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10673 13:55:06.329989 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10674 13:55:06.372544 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10675 13:55:06.421091 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10676 13:55:06.478027 Starting [0;1;39mNetwork Service[0m...
10677 13:55:06.773187 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10678 13:55:06.791245 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10679 13:55:06.813481 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10680 13:55:06.851986 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10681 13:55:07.113071 Starting [0;1;39mNetwork Time Synchronization[0m...
10682 13:55:07.148576 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10683 13:55:07.205625 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10684 13:55:07.224489 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10685 13:55:07.314565 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10686 13:55:07.328298 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10687 13:55:07.802762 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10688 13:55:07.815493 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10689 13:55:07.835066 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10690 13:55:07.847802 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10691 13:55:07.863168 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10692 13:55:08.135361 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10693 13:55:08.466166 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10694 13:55:08.485101 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10695 13:55:08.509918 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10696 13:55:08.523922 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10697 13:55:08.545202 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10698 13:55:08.555786 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10699 13:55:08.572145 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10700 13:55:08.591373 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10701 13:55:08.624104 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10702 13:55:08.653040 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10703 13:55:08.693620 Starting [0;1;39mUser Login Management[0m...
10704 13:55:08.731542 Starting [0;1;39mNetwork Name Resolution[0m...
10705 13:55:08.756879 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10706 13:55:08.972157 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10707 13:55:09.025839 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10708 13:55:09.045329 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10709 13:55:09.631139 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10710 13:55:09.653403 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10711 13:55:09.676364 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10712 13:55:09.726054 Starting [0;1;39mPermit User Sessions[0m...
10713 13:55:09.760161 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10714 13:55:09.776060 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10715 13:55:09.795902 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10716 13:55:09.813215 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10717 13:55:09.828081 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10718 13:55:09.844402 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10719 13:55:09.905828 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10720 13:55:09.951727 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10721 13:55:10.011634
10722 13:55:10.011790
10723 13:55:10.015511 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10724 13:55:10.015597
10725 13:55:10.017954 debian-bullseye-arm64 login: root (automatic login)
10726 13:55:10.018036
10727 13:55:10.018098
10728 13:55:10.347808 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
10729 13:55:10.347961
10730 13:55:10.354453 The programs included with the Debian GNU/Linux system are free software;
10731 13:55:10.360970 the exact distribution terms for each program are described in the
10732 13:55:10.364459 individual files in /usr/share/doc/*/copyright.
10733 13:55:10.364554
10734 13:55:10.371023 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10735 13:55:10.374384 permitted by applicable law.
10736 13:55:11.187055 Matched prompt #10: / #
10738 13:55:11.187339 Setting prompt string to ['/ #']
10739 13:55:11.187432 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10741 13:55:11.187622 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10742 13:55:11.187706 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10743 13:55:11.187777 Setting prompt string to ['/ #']
10744 13:55:11.187836 Forcing a shell prompt, looking for ['/ #']
10746 13:55:11.238039 / #
10747 13:55:11.238223 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10748 13:55:11.238313 Waiting using forced prompt support (timeout 00:02:30)
10749 13:55:11.243035
10750 13:55:11.243325 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10751 13:55:11.243419 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10753 13:55:11.343816 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682950/extract-nfsrootfs-t8gplle7'
10754 13:55:11.349266 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682950/extract-nfsrootfs-t8gplle7'
10756 13:55:11.449834 / # export NFS_SERVER_IP='192.168.201.1'
10757 13:55:11.455079 export NFS_SERVER_IP='192.168.201.1'
10758 13:55:11.455392 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10759 13:55:11.455498 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10760 13:55:11.455585 end: 2 depthcharge-action (duration 00:01:28) [common]
10761 13:55:11.455678 start: 3 lava-test-retry (timeout 00:07:46) [common]
10762 13:55:11.455763 start: 3.1 lava-test-shell (timeout 00:07:46) [common]
10763 13:55:11.455835 Using namespace: common
10765 13:55:11.556217 / # #
10766 13:55:11.556422 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10767 13:55:11.562042 #
10768 13:55:11.562342 Using /lava-12682950
10770 13:55:11.662701 / # export SHELL=/bin/bash
10771 13:55:11.668035 export SHELL=/bin/bash
10773 13:55:11.768633 / # . /lava-12682950/environment
10774 13:55:11.775162 . /lava-12682950/environment
10776 13:55:11.880196 / # /lava-12682950/bin/lava-test-runner /lava-12682950/0
10777 13:55:11.880415 Test shell timeout: 10s (minimum of the action and connection timeout)
10778 13:55:11.885864 /lava-12682950/bin/lava-test-runner /lava-12682950/0
10779 13:55:12.121311 + export TESTRUN_ID=0_timesync-off
10780 13:55:12.124264 + TESTRUN_ID=0_timesync-off
10781 13:55:12.127529 + cd /lava-12682950/0/tests/0_timesync-off
10782 13:55:12.130895 ++ cat uuid
10783 13:55:12.131013 + UUID=12682950_1.6.2.3.1
10784 13:55:12.134110 + set +x
10785 13:55:12.137741 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12682950_1.6.2.3.1>
10786 13:55:12.137998 Received signal: <STARTRUN> 0_timesync-off 12682950_1.6.2.3.1
10787 13:55:12.138078 Starting test lava.0_timesync-off (12682950_1.6.2.3.1)
10788 13:55:12.138166 Skipping test definition patterns.
10789 13:55:12.140327 + systemctl stop systemd-timesyncd
10790 13:55:12.220934 + set +x
10791 13:55:12.225002 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12682950_1.6.2.3.1>
10792 13:55:12.225268 Received signal: <ENDRUN> 0_timesync-off 12682950_1.6.2.3.1
10793 13:55:12.225356 Ending use of test pattern.
10794 13:55:12.225418 Ending test lava.0_timesync-off (12682950_1.6.2.3.1), duration 0.09
10796 13:55:12.277796 + export TESTRUN_ID=1_kselftest-dt
10797 13:55:12.281232 + TESTRUN_ID=1_kselftest-dt
10798 13:55:12.284561 + cd /lava-12682950/0/tests/1_kselftest-dt
10799 13:55:12.289603 ++ cat uuid
10800 13:55:12.289684 + UUID=12682950_1.6.2.3.5
10801 13:55:12.291573 + set +x
10802 13:55:12.294222 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12682950_1.6.2.3.5>
10803 13:55:12.294478 Received signal: <STARTRUN> 1_kselftest-dt 12682950_1.6.2.3.5
10804 13:55:12.294546 Starting test lava.1_kselftest-dt (12682950_1.6.2.3.5)
10805 13:55:12.294628 Skipping test definition patterns.
10806 13:55:12.297847 + cd ./automated/linux/kselftest/
10807 13:55:12.323775 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10808 13:55:12.350745 INFO: install_deps skipped
10809 13:55:12.458399 --2024-02-01 13:55:12-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10810 13:55:12.474368 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10811 13:55:12.606832 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10812 13:55:12.745822 HTTP request sent, awaiting response... 200 OK
10813 13:55:12.748307 Length: 2966796 (2.8M) [application/octet-stream]
10814 13:55:12.751319 Saving to: 'kselftest.tar.xz'
10815 13:55:12.751401
10816 13:55:12.751463
10817 13:55:13.013513 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10818 13:55:13.279788 kselftest.tar.xz 1%[ ] 49.22K 184KB/s
10819 13:55:13.594624 kselftest.tar.xz 7%[> ] 218.91K 410KB/s
10820 13:55:13.821711 kselftest.tar.xz 28%[====> ] 824.13K 972KB/s
10821 13:55:14.078162 kselftest.tar.xz 58%[==========> ] 1.64M 1.53MB/s
10822 13:55:14.215092 kselftest.tar.xz 98%[==================> ] 2.78M 2.09MB/s
10823 13:55:14.222652 kselftest.tar.xz 100%[===================>] 2.83M 1.93MB/s in 1.5s
10824 13:55:14.222755
10825 13:55:14.483024 2024-02-01 13:55:14 (1.93 MB/s) - 'kselftest.tar.xz' saved [2966796/2966796]
10826 13:55:14.483179
10827 13:55:19.716132 skiplist:
10828 13:55:19.718044 ========================================
10829 13:55:19.720088 ========================================
10830 13:55:19.786286 ============== Tests to run ===============
10831 13:55:19.789724 ===========End Tests to run ===============
10832 13:55:19.796580 shardfile-dt fail
10833 13:55:19.820512 ./kselftest.sh: 131: cannot open /lava-12682950/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
10834 13:55:19.823861 + ../../utils/send-to-lava.sh ./output/result.txt
10835 13:55:19.895642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
10836 13:55:19.896167 + set +x
10837 13:55:19.896845 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
10839 13:55:19.902370 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12682950_1.6.2.3.5>
10840 13:55:19.903166 Received signal: <ENDRUN> 1_kselftest-dt 12682950_1.6.2.3.5
10841 13:55:19.903534 Ending use of test pattern.
10842 13:55:19.903844 Ending test lava.1_kselftest-dt (12682950_1.6.2.3.5), duration 7.61
10844 13:55:19.904960 ok: lava_test_shell seems to have completed
10845 13:55:19.905522 shardfile-dt: fail
10846 13:55:19.905928 end: 3.1 lava-test-shell (duration 00:00:08) [common]
10847 13:55:19.906338 end: 3 lava-test-retry (duration 00:00:08) [common]
10848 13:55:19.906770 start: 4 finalize (timeout 00:07:37) [common]
10849 13:55:19.907231 start: 4.1 power-off (timeout 00:00:30) [common]
10850 13:55:19.908134 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10851 13:55:19.988201 >> Command sent successfully.
10852 13:55:19.992133 Returned 0 in 0 seconds
10853 13:55:20.093118 end: 4.1 power-off (duration 00:00:00) [common]
10855 13:55:20.094765 start: 4.2 read-feedback (timeout 00:07:37) [common]
10857 13:55:20.097499 Listened to connection for namespace 'common' for up to 1s
10858 13:55:21.096648 Finalising connection for namespace 'common'
10859 13:55:21.097363 Disconnecting from shell: Finalise
10860 13:55:21.097779 / #
10861 13:55:21.198771 end: 4.2 read-feedback (duration 00:00:01) [common]
10862 13:55:21.199494 end: 4 finalize (duration 00:00:01) [common]
10863 13:55:21.200080 Cleaning after the job
10864 13:55:21.200580 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/ramdisk
10865 13:55:21.214165 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/kernel
10866 13:55:21.244438 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/dtb
10867 13:55:21.244703 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/nfsrootfs
10868 13:55:21.339791 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682950/tftp-deploy-xlqbxold/modules
10869 13:55:21.347351 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682950
10870 13:55:21.985594 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682950
10871 13:55:21.985778 Job finished correctly