Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 38
1 13:55:59.978823 lava-dispatcher, installed at version: 2023.10
2 13:55:59.979092 start: 0 validate
3 13:55:59.979233 Start time: 2024-02-01 13:55:59.979225+00:00 (UTC)
4 13:55:59.979350 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:55:59.979482 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 13:56:00.251439 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:56:00.252184 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:56:00.526594 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:56:00.527359 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:56:00.790466 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:56:00.791350 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:56:01.063389 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:56:01.064181 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:56:01.343435 validate duration: 1.36
16 13:56:01.344831 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:56:01.345345 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:56:01.345814 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:56:01.346783 Not decompressing ramdisk as can be used compressed.
20 13:56:01.347253 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 13:56:01.347615 saving as /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/ramdisk/initrd.cpio.gz
22 13:56:01.347977 total size: 4665395 (4 MB)
23 13:56:01.352886 progress 0 % (0 MB)
24 13:56:01.360835 progress 5 % (0 MB)
25 13:56:01.366996 progress 10 % (0 MB)
26 13:56:01.371600 progress 15 % (0 MB)
27 13:56:01.375058 progress 20 % (0 MB)
28 13:56:01.378156 progress 25 % (1 MB)
29 13:56:01.381073 progress 30 % (1 MB)
30 13:56:01.383572 progress 35 % (1 MB)
31 13:56:01.385871 progress 40 % (1 MB)
32 13:56:01.388106 progress 45 % (2 MB)
33 13:56:01.390074 progress 50 % (2 MB)
34 13:56:01.391936 progress 55 % (2 MB)
35 13:56:01.393667 progress 60 % (2 MB)
36 13:56:01.395384 progress 65 % (2 MB)
37 13:56:01.397002 progress 70 % (3 MB)
38 13:56:01.398533 progress 75 % (3 MB)
39 13:56:01.400061 progress 80 % (3 MB)
40 13:56:01.401747 progress 85 % (3 MB)
41 13:56:01.403125 progress 90 % (4 MB)
42 13:56:01.404505 progress 95 % (4 MB)
43 13:56:01.405910 progress 100 % (4 MB)
44 13:56:01.406079 4 MB downloaded in 0.06 s (76.54 MB/s)
45 13:56:01.406234 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:56:01.406493 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:56:01.406582 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:56:01.406668 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:56:01.406805 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:56:01.406880 saving as /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/kernel/Image
52 13:56:01.406942 total size: 51532288 (49 MB)
53 13:56:01.407004 No compression specified
54 13:56:01.408124 progress 0 % (0 MB)
55 13:56:01.421470 progress 5 % (2 MB)
56 13:56:01.434929 progress 10 % (4 MB)
57 13:56:01.448107 progress 15 % (7 MB)
58 13:56:01.461706 progress 20 % (9 MB)
59 13:56:01.475121 progress 25 % (12 MB)
60 13:56:01.488461 progress 30 % (14 MB)
61 13:56:01.501794 progress 35 % (17 MB)
62 13:56:01.515098 progress 40 % (19 MB)
63 13:56:01.528423 progress 45 % (22 MB)
64 13:56:01.541923 progress 50 % (24 MB)
65 13:56:01.555076 progress 55 % (27 MB)
66 13:56:01.568568 progress 60 % (29 MB)
67 13:56:01.582187 progress 65 % (31 MB)
68 13:56:01.595428 progress 70 % (34 MB)
69 13:56:01.608729 progress 75 % (36 MB)
70 13:56:01.622036 progress 80 % (39 MB)
71 13:56:01.635195 progress 85 % (41 MB)
72 13:56:01.648557 progress 90 % (44 MB)
73 13:56:01.661615 progress 95 % (46 MB)
74 13:56:01.674635 progress 100 % (49 MB)
75 13:56:01.674841 49 MB downloaded in 0.27 s (183.45 MB/s)
76 13:56:01.674994 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:56:01.675222 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:56:01.675310 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:56:01.675395 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:56:01.675536 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:56:01.675606 saving as /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/dtb/mt8192-asurada-spherion-r0.dtb
83 13:56:01.675667 total size: 47278 (0 MB)
84 13:56:01.675728 No compression specified
85 13:56:01.676873 progress 69 % (0 MB)
86 13:56:01.677144 progress 100 % (0 MB)
87 13:56:01.677297 0 MB downloaded in 0.00 s (27.70 MB/s)
88 13:56:01.677416 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:56:01.677638 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:56:01.677724 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:56:01.677806 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:56:01.677917 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 13:56:01.677984 saving as /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/nfsrootfs/full.rootfs.tar
95 13:56:01.678042 total size: 200813988 (191 MB)
96 13:56:01.678103 Using unxz to decompress xz
97 13:56:01.682414 progress 0 % (0 MB)
98 13:56:02.203539 progress 5 % (9 MB)
99 13:56:02.713018 progress 10 % (19 MB)
100 13:56:03.290084 progress 15 % (28 MB)
101 13:56:03.659131 progress 20 % (38 MB)
102 13:56:03.977818 progress 25 % (47 MB)
103 13:56:04.558175 progress 30 % (57 MB)
104 13:56:05.104684 progress 35 % (67 MB)
105 13:56:05.690027 progress 40 % (76 MB)
106 13:56:06.242205 progress 45 % (86 MB)
107 13:56:06.818653 progress 50 % (95 MB)
108 13:56:07.438522 progress 55 % (105 MB)
109 13:56:08.093771 progress 60 % (114 MB)
110 13:56:08.209493 progress 65 % (124 MB)
111 13:56:08.347500 progress 70 % (134 MB)
112 13:56:08.442815 progress 75 % (143 MB)
113 13:56:08.513146 progress 80 % (153 MB)
114 13:56:08.580422 progress 85 % (162 MB)
115 13:56:08.680116 progress 90 % (172 MB)
116 13:56:08.953871 progress 95 % (181 MB)
117 13:56:09.523831 progress 100 % (191 MB)
118 13:56:09.529006 191 MB downloaded in 7.85 s (24.39 MB/s)
119 13:56:09.529274 end: 1.4.1 http-download (duration 00:00:08) [common]
121 13:56:09.529538 end: 1.4 download-retry (duration 00:00:08) [common]
122 13:56:09.529627 start: 1.5 download-retry (timeout 00:09:52) [common]
123 13:56:09.529715 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 13:56:09.529876 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:56:09.529948 saving as /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/modules/modules.tar
126 13:56:09.530009 total size: 8623988 (8 MB)
127 13:56:09.530072 Using unxz to decompress xz
128 13:56:09.534469 progress 0 % (0 MB)
129 13:56:09.555405 progress 5 % (0 MB)
130 13:56:09.578927 progress 10 % (0 MB)
131 13:56:09.602835 progress 15 % (1 MB)
132 13:56:09.626157 progress 20 % (1 MB)
133 13:56:09.650137 progress 25 % (2 MB)
134 13:56:09.676107 progress 30 % (2 MB)
135 13:56:09.702784 progress 35 % (2 MB)
136 13:56:09.726641 progress 40 % (3 MB)
137 13:56:09.751575 progress 45 % (3 MB)
138 13:56:09.777280 progress 50 % (4 MB)
139 13:56:09.806100 progress 55 % (4 MB)
140 13:56:09.831024 progress 60 % (4 MB)
141 13:56:09.859153 progress 65 % (5 MB)
142 13:56:09.884654 progress 70 % (5 MB)
143 13:56:09.908513 progress 75 % (6 MB)
144 13:56:09.935711 progress 80 % (6 MB)
145 13:56:09.961342 progress 85 % (7 MB)
146 13:56:09.986262 progress 90 % (7 MB)
147 13:56:10.018017 progress 95 % (7 MB)
148 13:56:10.047421 progress 100 % (8 MB)
149 13:56:10.052449 8 MB downloaded in 0.52 s (15.74 MB/s)
150 13:56:10.052718 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:56:10.053022 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:56:10.053117 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 13:56:10.053215 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 13:56:13.572290 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12682951/extract-nfsrootfs-0eemlskl
156 13:56:13.572479 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:56:13.572575 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 13:56:13.573003 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1
159 13:56:13.573143 makedir: /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin
160 13:56:13.573248 makedir: /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/tests
161 13:56:13.573348 makedir: /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/results
162 13:56:13.573449 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-add-keys
163 13:56:13.573596 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-add-sources
164 13:56:13.573726 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-background-process-start
165 13:56:13.573854 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-background-process-stop
166 13:56:13.573980 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-common-functions
167 13:56:13.574106 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-echo-ipv4
168 13:56:13.574232 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-install-packages
169 13:56:13.574355 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-installed-packages
170 13:56:13.574477 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-os-build
171 13:56:13.574600 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-probe-channel
172 13:56:13.574722 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-probe-ip
173 13:56:13.574844 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-target-ip
174 13:56:13.574968 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-target-mac
175 13:56:13.575091 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-target-storage
176 13:56:13.575217 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-test-case
177 13:56:13.575343 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-test-event
178 13:56:13.575467 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-test-feedback
179 13:56:13.575592 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-test-raise
180 13:56:13.575715 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-test-reference
181 13:56:13.575839 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-test-runner
182 13:56:13.575962 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-test-set
183 13:56:13.576089 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-test-shell
184 13:56:13.576215 Updating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-add-keys (debian)
185 13:56:13.576364 Updating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-add-sources (debian)
186 13:56:13.576502 Updating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-install-packages (debian)
187 13:56:13.576640 Updating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-installed-packages (debian)
188 13:56:13.576818 Updating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/bin/lava-os-build (debian)
189 13:56:13.576940 Creating /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/environment
190 13:56:13.577038 LAVA metadata
191 13:56:13.577107 - LAVA_JOB_ID=12682951
192 13:56:13.577169 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:56:13.577267 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 13:56:13.577332 skipped lava-vland-overlay
195 13:56:13.577404 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:56:13.577482 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 13:56:13.577542 skipped lava-multinode-overlay
198 13:56:13.577612 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:56:13.577688 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 13:56:13.577758 Loading test definitions
201 13:56:13.577845 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 13:56:13.577914 Using /lava-12682951 at stage 0
203 13:56:13.578195 uuid=12682951_1.6.2.3.1 testdef=None
204 13:56:13.578281 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:56:13.578364 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 13:56:13.578813 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:56:13.579029 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 13:56:13.579570 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:56:13.579796 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 13:56:13.580465 runner path: /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/0/tests/0_timesync-off test_uuid 12682951_1.6.2.3.1
213 13:56:13.580617 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:56:13.580886 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 13:56:13.580982 Using /lava-12682951 at stage 0
217 13:56:13.581127 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:56:13.581205 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/0/tests/1_kselftest-rtc'
219 13:56:21.519888 Running '/usr/bin/git checkout kernelci.org
220 13:56:21.666675 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 13:56:21.667424 uuid=12682951_1.6.2.3.5 testdef=None
222 13:56:21.667580 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 13:56:21.667822 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 13:56:21.668550 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:56:21.668823 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 13:56:21.669799 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:56:21.670026 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 13:56:21.670958 runner path: /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/0/tests/1_kselftest-rtc test_uuid 12682951_1.6.2.3.5
232 13:56:21.671048 BOARD='mt8192-asurada-spherion-r0'
233 13:56:21.671112 BRANCH='cip'
234 13:56:21.671170 SKIPFILE='/dev/null'
235 13:56:21.671226 SKIP_INSTALL='True'
236 13:56:21.671281 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 13:56:21.671336 TST_CASENAME=''
238 13:56:21.671390 TST_CMDFILES='rtc'
239 13:56:21.671528 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:56:21.671726 Creating lava-test-runner.conf files
242 13:56:21.671788 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682951/lava-overlay-aokl_8b1/lava-12682951/0 for stage 0
243 13:56:21.671879 - 0_timesync-off
244 13:56:21.671948 - 1_kselftest-rtc
245 13:56:21.672042 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 13:56:21.672126 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 13:56:29.093854 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 13:56:29.094014 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 13:56:29.094105 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:56:29.094202 end: 1.6.2 lava-overlay (duration 00:00:16) [common]
251 13:56:29.094292 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 13:56:29.213232 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:56:29.213626 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 13:56:29.213735 extracting modules file /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682951/extract-nfsrootfs-0eemlskl
255 13:56:29.434312 extracting modules file /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682951/extract-overlay-ramdisk-xcr2zqrk/ramdisk
256 13:56:29.660899 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:56:29.661066 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 13:56:29.661158 [common] Applying overlay to NFS
259 13:56:29.661229 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682951/compress-overlay-2ms9jdbt/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682951/extract-nfsrootfs-0eemlskl
260 13:56:30.577015 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:56:30.577180 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 13:56:30.577275 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:56:30.577367 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 13:56:30.577446 Building ramdisk /var/lib/lava/dispatcher/tmp/12682951/extract-overlay-ramdisk-xcr2zqrk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682951/extract-overlay-ramdisk-xcr2zqrk/ramdisk
265 13:56:30.915916 >> 119414 blocks
266 13:56:32.841893 rename /var/lib/lava/dispatcher/tmp/12682951/extract-overlay-ramdisk-xcr2zqrk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/ramdisk/ramdisk.cpio.gz
267 13:56:32.842359 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:56:32.842485 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 13:56:32.842587 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 13:56:32.842698 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/kernel/Image'
271 13:56:45.141240 Returned 0 in 12 seconds
272 13:56:45.242241 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/kernel/image.itb
273 13:56:45.625867 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:56:45.626253 output: Created: Thu Feb 1 13:56:45 2024
275 13:56:45.626326 output: Image 0 (kernel-1)
276 13:56:45.626390 output: Description:
277 13:56:45.626454 output: Created: Thu Feb 1 13:56:45 2024
278 13:56:45.626519 output: Type: Kernel Image
279 13:56:45.626576 output: Compression: lzma compressed
280 13:56:45.626636 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
281 13:56:45.626696 output: Architecture: AArch64
282 13:56:45.626756 output: OS: Linux
283 13:56:45.626811 output: Load Address: 0x00000000
284 13:56:45.626870 output: Entry Point: 0x00000000
285 13:56:45.626927 output: Hash algo: crc32
286 13:56:45.626986 output: Hash value: 5aa40db2
287 13:56:45.627042 output: Image 1 (fdt-1)
288 13:56:45.627094 output: Description: mt8192-asurada-spherion-r0
289 13:56:45.627147 output: Created: Thu Feb 1 13:56:45 2024
290 13:56:45.627200 output: Type: Flat Device Tree
291 13:56:45.627253 output: Compression: uncompressed
292 13:56:45.627305 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 13:56:45.627358 output: Architecture: AArch64
294 13:56:45.627409 output: Hash algo: crc32
295 13:56:45.627462 output: Hash value: cc4352de
296 13:56:45.627514 output: Image 2 (ramdisk-1)
297 13:56:45.627565 output: Description: unavailable
298 13:56:45.627617 output: Created: Thu Feb 1 13:56:45 2024
299 13:56:45.627670 output: Type: RAMDisk Image
300 13:56:45.627722 output: Compression: Unknown Compression
301 13:56:45.627774 output: Data Size: 17799567 Bytes = 17382.39 KiB = 16.97 MiB
302 13:56:45.627827 output: Architecture: AArch64
303 13:56:45.627879 output: OS: Linux
304 13:56:45.627930 output: Load Address: unavailable
305 13:56:45.627982 output: Entry Point: unavailable
306 13:56:45.628034 output: Hash algo: crc32
307 13:56:45.628085 output: Hash value: 8889db4a
308 13:56:45.628137 output: Default Configuration: 'conf-1'
309 13:56:45.628189 output: Configuration 0 (conf-1)
310 13:56:45.628241 output: Description: mt8192-asurada-spherion-r0
311 13:56:45.628294 output: Kernel: kernel-1
312 13:56:45.628345 output: Init Ramdisk: ramdisk-1
313 13:56:45.628397 output: FDT: fdt-1
314 13:56:45.628449 output: Loadables: kernel-1
315 13:56:45.628501 output:
316 13:56:45.628703 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 13:56:45.628812 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 13:56:45.628920 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 13:56:45.629014 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 13:56:45.629099 No LXC device requested
321 13:56:45.629179 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:56:45.629264 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 13:56:45.629339 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:56:45.629422 Checking files for TFTP limit of 4294967296 bytes.
325 13:56:45.629924 end: 1 tftp-deploy (duration 00:00:44) [common]
326 13:56:45.630026 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:56:45.630119 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:56:45.630247 substitutions:
329 13:56:45.630316 - {DTB}: 12682951/tftp-deploy-j9f43ni9/dtb/mt8192-asurada-spherion-r0.dtb
330 13:56:45.630381 - {INITRD}: 12682951/tftp-deploy-j9f43ni9/ramdisk/ramdisk.cpio.gz
331 13:56:45.630441 - {KERNEL}: 12682951/tftp-deploy-j9f43ni9/kernel/Image
332 13:56:45.630500 - {LAVA_MAC}: None
333 13:56:45.630555 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12682951/extract-nfsrootfs-0eemlskl
334 13:56:45.630611 - {NFS_SERVER_IP}: 192.168.201.1
335 13:56:45.630666 - {PRESEED_CONFIG}: None
336 13:56:45.630721 - {PRESEED_LOCAL}: None
337 13:56:45.630774 - {RAMDISK}: 12682951/tftp-deploy-j9f43ni9/ramdisk/ramdisk.cpio.gz
338 13:56:45.630828 - {ROOT_PART}: None
339 13:56:45.630881 - {ROOT}: None
340 13:56:45.630935 - {SERVER_IP}: 192.168.201.1
341 13:56:45.630988 - {TEE}: None
342 13:56:45.631041 Parsed boot commands:
343 13:56:45.631094 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:56:45.631281 Parsed boot commands: tftpboot 192.168.201.1 12682951/tftp-deploy-j9f43ni9/kernel/image.itb 12682951/tftp-deploy-j9f43ni9/kernel/cmdline
345 13:56:45.631368 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:56:45.631453 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:56:45.631552 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:56:45.631640 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:56:45.631711 Not connected, no need to disconnect.
350 13:56:45.631784 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:56:45.631864 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:56:45.631931 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 13:56:45.636032 Setting prompt string to ['lava-test: # ']
354 13:56:45.636404 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:56:45.636516 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:56:45.636616 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:56:45.636735 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:56:45.636942 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 13:56:50.785694 >> Command sent successfully.
360 13:56:50.797182 Returned 0 in 5 seconds
361 13:56:50.898561 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 13:56:50.900147 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 13:56:50.900772 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 13:56:50.901309 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:56:50.901689 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:56:50.902067 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:56:50.903491 [Enter `^Ec?' for help]
369 13:56:51.071563
370 13:56:51.072146
371 13:56:51.072553 F0: 102B 0000
372 13:56:51.072979
373 13:56:51.073330 F3: 1001 0000 [0200]
374 13:56:51.073664
375 13:56:51.075297 F3: 1001 0000
376 13:56:51.075769
377 13:56:51.076145 F7: 102D 0000
378 13:56:51.076514
379 13:56:51.076893 F1: 0000 0000
380 13:56:51.077233
381 13:56:51.078816 V0: 0000 0000 [0001]
382 13:56:51.079286
383 13:56:51.079657 00: 0007 8000
384 13:56:51.080028
385 13:56:51.082411 01: 0000 0000
386 13:56:51.082893
387 13:56:51.083264 BP: 0C00 0209 [0000]
388 13:56:51.083611
389 13:56:51.086755 G0: 1182 0000
390 13:56:51.087419
391 13:56:51.087804 EC: 0000 0021 [4000]
392 13:56:51.088157
393 13:56:51.089879 S7: 0000 0000 [0000]
394 13:56:51.090351
395 13:56:51.090728 CC: 0000 0000 [0001]
396 13:56:51.091076
397 13:56:51.094236 T0: 0000 0040 [010F]
398 13:56:51.094710
399 13:56:51.095087 Jump to BL
400 13:56:51.095436
401 13:56:51.118685
402 13:56:51.119277
403 13:56:51.119661
404 13:56:51.125246 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 13:56:51.129141 ARM64: Exception handlers installed.
406 13:56:51.131692 ARM64: Testing exception
407 13:56:51.135653 ARM64: Done test exception
408 13:56:51.142106 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 13:56:51.151923 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 13:56:51.158758 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 13:56:51.168904 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 13:56:51.175382 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 13:56:51.186228 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 13:56:51.198905 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 13:56:51.203521 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 13:56:51.221659 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 13:56:51.224993 WDT: Last reset was cold boot
418 13:56:51.228329 SPI1(PAD0) initialized at 2873684 Hz
419 13:56:51.231781 SPI5(PAD0) initialized at 992727 Hz
420 13:56:51.234414 VBOOT: Loading verstage.
421 13:56:51.241503 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 13:56:51.244272 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 13:56:51.248314 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 13:56:51.251552 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 13:56:51.260365 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 13:56:51.265372 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 13:56:51.276387 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 13:56:51.277000
429 13:56:51.277397
430 13:56:51.286057 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 13:56:51.289367 ARM64: Exception handlers installed.
432 13:56:51.293611 ARM64: Testing exception
433 13:56:51.294190 ARM64: Done test exception
434 13:56:51.299998 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 13:56:51.303226 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 13:56:51.317296 Probing TPM: . done!
437 13:56:51.317875 TPM ready after 0 ms
438 13:56:51.324185 Connected to device vid:did:rid of 1ae0:0028:00
439 13:56:51.330734 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 13:56:51.333957 Initialized TPM device CR50 revision 0
441 13:56:51.383806 tlcl_send_startup: Startup return code is 0
442 13:56:51.384380 TPM: setup succeeded
443 13:56:51.395317 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 13:56:51.404260 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 13:56:51.414965 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 13:56:51.423968 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 13:56:51.426553 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 13:56:51.430886 in-header: 03 07 00 00 08 00 00 00
449 13:56:51.433372 in-data: aa e4 47 04 13 02 00 00
450 13:56:51.436536 Chrome EC: UHEPI supported
451 13:56:51.443099 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 13:56:51.446830 in-header: 03 9d 00 00 08 00 00 00
453 13:56:51.449774 in-data: 10 20 20 08 00 00 00 00
454 13:56:51.450345 Phase 1
455 13:56:51.454622 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 13:56:51.459505 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 13:56:51.466233 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 13:56:51.470404 Recovery requested (1009000e)
459 13:56:51.476914 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 13:56:51.482258 tlcl_extend: response is 0
461 13:56:51.489917 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 13:56:51.495711 tlcl_extend: response is 0
463 13:56:51.501899 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 13:56:51.522270 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 13:56:51.529284 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 13:56:51.529844
467 13:56:51.530223
468 13:56:51.539486 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 13:56:51.542349 ARM64: Exception handlers installed.
470 13:56:51.546014 ARM64: Testing exception
471 13:56:51.546583 ARM64: Done test exception
472 13:56:51.568538 pmic_efuse_setting: Set efuses in 11 msecs
473 13:56:51.571741 pmwrap_interface_init: Select PMIF_VLD_RDY
474 13:56:51.578612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 13:56:51.582965 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 13:56:51.585655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 13:56:51.592499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 13:56:51.597367 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 13:56:51.599989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 13:56:51.607857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 13:56:51.611099 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 13:56:51.614343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 13:56:51.621920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 13:56:51.623857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 13:56:51.630572 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 13:56:51.633870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 13:56:51.640889 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 13:56:51.647451 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 13:56:51.650603 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 13:56:51.657380 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 13:56:51.664643 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 13:56:51.668233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 13:56:51.676022 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 13:56:51.679268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 13:56:51.685256 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 13:56:51.691816 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 13:56:51.694855 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 13:56:51.702472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 13:56:51.708997 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 13:56:51.711941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 13:56:51.719052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 13:56:51.723063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 13:56:51.728547 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 13:56:51.732055 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 13:56:51.738025 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 13:56:51.741679 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 13:56:51.748377 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 13:56:51.751402 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 13:56:51.758603 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 13:56:51.761884 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 13:56:51.768075 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 13:56:51.771682 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 13:56:51.777638 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 13:56:51.782590 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 13:56:51.784807 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 13:56:51.788414 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 13:56:51.795073 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 13:56:51.798170 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 13:56:51.801590 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 13:56:51.805762 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 13:56:51.811867 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 13:56:51.814969 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 13:56:51.818489 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 13:56:51.821714 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 13:56:51.831989 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 13:56:51.838370 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 13:56:51.845535 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 13:56:51.851942 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 13:56:51.861802 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 13:56:51.865071 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 13:56:51.868658 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:56:51.874996 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 13:56:51.881261 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 13:56:51.888336 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 13:56:51.891453 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 13:56:51.895059 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 13:56:51.905217 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 13:56:51.915166 [RTC]rtc_get_frequency_meter,154: input=23, output=948
539 13:56:51.925411 [RTC]rtc_get_frequency_meter,154: input=19, output=856
540 13:56:51.934555 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 13:56:51.943976 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 13:56:51.953188 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 13:56:51.962361 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 13:56:51.965925 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 13:56:51.972848 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 13:56:51.976289 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 13:56:51.979749 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 13:56:51.986843 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 13:56:51.990430 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 13:56:51.993505 ADC[4]: Raw value=669695 ID=5
551 13:56:51.994079 ADC[3]: Raw value=212549 ID=1
552 13:56:51.996259 RAM Code: 0x51
553 13:56:52.000206 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 13:56:52.006309 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 13:56:52.012638 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 13:56:52.019723 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 13:56:52.023025 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 13:56:52.026290 in-header: 03 07 00 00 08 00 00 00
559 13:56:52.029419 in-data: aa e4 47 04 13 02 00 00
560 13:56:52.033617 Chrome EC: UHEPI supported
561 13:56:52.041234 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 13:56:52.042750 in-header: 03 d5 00 00 08 00 00 00
563 13:56:52.047478 in-data: 98 20 60 08 00 00 00 00
564 13:56:52.049415 MRC: failed to locate region type 0.
565 13:56:52.056280 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 13:56:52.060343 DRAM-K: Running full calibration
567 13:56:52.063312 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 13:56:52.067545 header.status = 0x0
569 13:56:52.069840 header.version = 0x6 (expected: 0x6)
570 13:56:52.072700 header.size = 0xd00 (expected: 0xd00)
571 13:56:52.076352 header.flags = 0x0
572 13:56:52.079325 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 13:56:52.098221 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 13:56:52.105689 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 13:56:52.108683 dram_init: ddr_geometry: 0
576 13:56:52.111937 [EMI] MDL number = 0
577 13:56:52.112407 [EMI] Get MDL freq = 0
578 13:56:52.115230 dram_init: ddr_type: 0
579 13:56:52.115813 is_discrete_lpddr4: 1
580 13:56:52.117988 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 13:56:52.118465
582 13:56:52.118843
583 13:56:52.122462 [Bian_co] ETT version 0.0.0.1
584 13:56:52.125785 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 13:56:52.126275
586 13:56:52.132116 dramc_set_vcore_voltage set vcore to 650000
587 13:56:52.132589 Read voltage for 800, 4
588 13:56:52.135628 Vio18 = 0
589 13:56:52.136212 Vcore = 650000
590 13:56:52.136593 Vdram = 0
591 13:56:52.139715 Vddq = 0
592 13:56:52.140293 Vmddr = 0
593 13:56:52.143003 dram_init: config_dvfs: 1
594 13:56:52.145425 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 13:56:52.152028 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 13:56:52.155592 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 13:56:52.159285 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 13:56:52.162274 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 13:56:52.165681 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 13:56:52.169489 MEM_TYPE=3, freq_sel=18
601 13:56:52.172386 sv_algorithm_assistance_LP4_1600
602 13:56:52.175995 ============ PULL DRAM RESETB DOWN ============
603 13:56:52.178854 ========== PULL DRAM RESETB DOWN end =========
604 13:56:52.185543 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 13:56:52.188403 ===================================
606 13:56:52.188899 LPDDR4 DRAM CONFIGURATION
607 13:56:52.192081 ===================================
608 13:56:52.195768 EX_ROW_EN[0] = 0x0
609 13:56:52.199225 EX_ROW_EN[1] = 0x0
610 13:56:52.199810 LP4Y_EN = 0x0
611 13:56:52.201810 WORK_FSP = 0x0
612 13:56:52.202281 WL = 0x2
613 13:56:52.205333 RL = 0x2
614 13:56:52.205821 BL = 0x2
615 13:56:52.208703 RPST = 0x0
616 13:56:52.209223 RD_PRE = 0x0
617 13:56:52.211812 WR_PRE = 0x1
618 13:56:52.212284 WR_PST = 0x0
619 13:56:52.215506 DBI_WR = 0x0
620 13:56:52.216081 DBI_RD = 0x0
621 13:56:52.218367 OTF = 0x1
622 13:56:52.222089 ===================================
623 13:56:52.225275 ===================================
624 13:56:52.225906 ANA top config
625 13:56:52.229936 ===================================
626 13:56:52.232187 DLL_ASYNC_EN = 0
627 13:56:52.235673 ALL_SLAVE_EN = 1
628 13:56:52.236275 NEW_RANK_MODE = 1
629 13:56:52.238327 DLL_IDLE_MODE = 1
630 13:56:52.241930 LP45_APHY_COMB_EN = 1
631 13:56:52.245462 TX_ODT_DIS = 1
632 13:56:52.250938 NEW_8X_MODE = 1
633 13:56:52.252067 ===================================
634 13:56:52.252541 ===================================
635 13:56:52.255430 data_rate = 1600
636 13:56:52.258854 CKR = 1
637 13:56:52.262831 DQ_P2S_RATIO = 8
638 13:56:52.266166 ===================================
639 13:56:52.268820 CA_P2S_RATIO = 8
640 13:56:52.272222 DQ_CA_OPEN = 0
641 13:56:52.275835 DQ_SEMI_OPEN = 0
642 13:56:52.276407 CA_SEMI_OPEN = 0
643 13:56:52.278367 CA_FULL_RATE = 0
644 13:56:52.282123 DQ_CKDIV4_EN = 1
645 13:56:52.285174 CA_CKDIV4_EN = 1
646 13:56:52.288431 CA_PREDIV_EN = 0
647 13:56:52.291905 PH8_DLY = 0
648 13:56:52.292482 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 13:56:52.296013 DQ_AAMCK_DIV = 4
650 13:56:52.298533 CA_AAMCK_DIV = 4
651 13:56:52.302124 CA_ADMCK_DIV = 4
652 13:56:52.305181 DQ_TRACK_CA_EN = 0
653 13:56:52.308460 CA_PICK = 800
654 13:56:52.309306 CA_MCKIO = 800
655 13:56:52.311588 MCKIO_SEMI = 0
656 13:56:52.315353 PLL_FREQ = 3068
657 13:56:52.318486 DQ_UI_PI_RATIO = 32
658 13:56:52.321572 CA_UI_PI_RATIO = 0
659 13:56:52.325716 ===================================
660 13:56:52.328648 ===================================
661 13:56:52.331867 memory_type:LPDDR4
662 13:56:52.332339 GP_NUM : 10
663 13:56:52.335007 SRAM_EN : 1
664 13:56:52.335661 MD32_EN : 0
665 13:56:52.338042 ===================================
666 13:56:52.342766 [ANA_INIT] >>>>>>>>>>>>>>
667 13:56:52.345024 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 13:56:52.348365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 13:56:52.351775 ===================================
670 13:56:52.354857 data_rate = 1600,PCW = 0X7600
671 13:56:52.359116 ===================================
672 13:56:52.362353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 13:56:52.365403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 13:56:52.371997 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 13:56:52.375914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 13:56:52.381801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 13:56:52.386040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 13:56:52.386619 [ANA_INIT] flow start
679 13:56:52.388687 [ANA_INIT] PLL >>>>>>>>
680 13:56:52.389208 [ANA_INIT] PLL <<<<<<<<
681 13:56:52.394424 [ANA_INIT] MIDPI >>>>>>>>
682 13:56:52.395620 [ANA_INIT] MIDPI <<<<<<<<
683 13:56:52.399416 [ANA_INIT] DLL >>>>>>>>
684 13:56:52.399992 [ANA_INIT] flow end
685 13:56:52.402342 ============ LP4 DIFF to SE enter ============
686 13:56:52.408824 ============ LP4 DIFF to SE exit ============
687 13:56:52.409596 [ANA_INIT] <<<<<<<<<<<<<
688 13:56:52.412147 [Flow] Enable top DCM control >>>>>
689 13:56:52.415406 [Flow] Enable top DCM control <<<<<
690 13:56:52.418403 Enable DLL master slave shuffle
691 13:56:52.425924 ==============================================================
692 13:56:52.426504 Gating Mode config
693 13:56:52.431971 ==============================================================
694 13:56:52.435434 Config description:
695 13:56:52.445115 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 13:56:52.452189 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 13:56:52.455488 SELPH_MODE 0: By rank 1: By Phase
698 13:56:52.462030 ==============================================================
699 13:56:52.465597 GAT_TRACK_EN = 1
700 13:56:52.466077 RX_GATING_MODE = 2
701 13:56:52.468511 RX_GATING_TRACK_MODE = 2
702 13:56:52.472059 SELPH_MODE = 1
703 13:56:52.475195 PICG_EARLY_EN = 1
704 13:56:52.478721 VALID_LAT_VALUE = 1
705 13:56:52.485210 ==============================================================
706 13:56:52.488884 Enter into Gating configuration >>>>
707 13:56:52.491887 Exit from Gating configuration <<<<
708 13:56:52.495881 Enter into DVFS_PRE_config >>>>>
709 13:56:52.505279 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 13:56:52.508680 Exit from DVFS_PRE_config <<<<<
711 13:56:52.512416 Enter into PICG configuration >>>>
712 13:56:52.515995 Exit from PICG configuration <<<<
713 13:56:52.518587 [RX_INPUT] configuration >>>>>
714 13:56:52.519060 [RX_INPUT] configuration <<<<<
715 13:56:52.525657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 13:56:52.532241 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 13:56:52.535634 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 13:56:52.542323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 13:56:52.549420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 13:56:52.555960 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 13:56:52.558357 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 13:56:52.562024 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 13:56:52.568619 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 13:56:52.572551 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 13:56:52.575423 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 13:56:52.582102 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 13:56:52.582664 ===================================
728 13:56:52.585512 LPDDR4 DRAM CONFIGURATION
729 13:56:52.588628 ===================================
730 13:56:52.591949 EX_ROW_EN[0] = 0x0
731 13:56:52.592518 EX_ROW_EN[1] = 0x0
732 13:56:52.595301 LP4Y_EN = 0x0
733 13:56:52.595868 WORK_FSP = 0x0
734 13:56:52.598911 WL = 0x2
735 13:56:52.599508 RL = 0x2
736 13:56:52.601668 BL = 0x2
737 13:56:52.602157 RPST = 0x0
738 13:56:52.605837 RD_PRE = 0x0
739 13:56:52.606494 WR_PRE = 0x1
740 13:56:52.608494 WR_PST = 0x0
741 13:56:52.609022 DBI_WR = 0x0
742 13:56:52.612298 DBI_RD = 0x0
743 13:56:52.616562 OTF = 0x1
744 13:56:52.617211 ===================================
745 13:56:52.622660 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 13:56:52.625539 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 13:56:52.628512 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 13:56:52.632828 ===================================
749 13:56:52.635696 LPDDR4 DRAM CONFIGURATION
750 13:56:52.637969 ===================================
751 13:56:52.642113 EX_ROW_EN[0] = 0x10
752 13:56:52.642697 EX_ROW_EN[1] = 0x0
753 13:56:52.645562 LP4Y_EN = 0x0
754 13:56:52.646147 WORK_FSP = 0x0
755 13:56:52.649018 WL = 0x2
756 13:56:52.649495 RL = 0x2
757 13:56:52.652151 BL = 0x2
758 13:56:52.652778 RPST = 0x0
759 13:56:52.655668 RD_PRE = 0x0
760 13:56:52.656252 WR_PRE = 0x1
761 13:56:52.658566 WR_PST = 0x0
762 13:56:52.659047 DBI_WR = 0x0
763 13:56:52.662633 DBI_RD = 0x0
764 13:56:52.663227 OTF = 0x1
765 13:56:52.664790 ===================================
766 13:56:52.672068 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 13:56:52.678160 nWR fixed to 40
768 13:56:52.680452 [ModeRegInit_LP4] CH0 RK0
769 13:56:52.681082 [ModeRegInit_LP4] CH0 RK1
770 13:56:52.683482 [ModeRegInit_LP4] CH1 RK0
771 13:56:52.686739 [ModeRegInit_LP4] CH1 RK1
772 13:56:52.687308 match AC timing 12
773 13:56:52.693409 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 13:56:52.697037 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 13:56:52.699986 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 13:56:52.706472 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 13:56:52.709990 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 13:56:52.710642 [EMI DOE] emi_dcm 0
779 13:56:52.717618 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 13:56:52.718209 ==
781 13:56:52.720015 Dram Type= 6, Freq= 0, CH_0, rank 0
782 13:56:52.723326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 13:56:52.723915 ==
784 13:56:52.729941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 13:56:52.736768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 13:56:52.744088 [CA 0] Center 37 (7~68) winsize 62
787 13:56:52.748150 [CA 1] Center 37 (7~68) winsize 62
788 13:56:52.750941 [CA 2] Center 35 (5~66) winsize 62
789 13:56:52.754274 [CA 3] Center 35 (4~66) winsize 63
790 13:56:52.757215 [CA 4] Center 34 (4~65) winsize 62
791 13:56:52.761149 [CA 5] Center 33 (3~64) winsize 62
792 13:56:52.761733
793 13:56:52.765215 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 13:56:52.765803
795 13:56:52.767797 [CATrainingPosCal] consider 1 rank data
796 13:56:52.770330 u2DelayCellTimex100 = 270/100 ps
797 13:56:52.773818 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 13:56:52.777293 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 13:56:52.784564 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 13:56:52.787165 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 13:56:52.790666 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 13:56:52.794007 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 13:56:52.794481
804 13:56:52.797172 CA PerBit enable=1, Macro0, CA PI delay=33
805 13:56:52.797645
806 13:56:52.800131 [CBTSetCACLKResult] CA Dly = 33
807 13:56:52.800600 CS Dly: 5 (0~36)
808 13:56:52.803448 ==
809 13:56:52.806636 Dram Type= 6, Freq= 0, CH_0, rank 1
810 13:56:52.810825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 13:56:52.811405 ==
812 13:56:52.813450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 13:56:52.820036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 13:56:52.830705 [CA 0] Center 37 (6~68) winsize 63
815 13:56:52.833359 [CA 1] Center 37 (6~68) winsize 63
816 13:56:52.836913 [CA 2] Center 35 (4~66) winsize 63
817 13:56:52.839975 [CA 3] Center 34 (4~65) winsize 62
818 13:56:52.844405 [CA 4] Center 33 (3~64) winsize 62
819 13:56:52.846461 [CA 5] Center 33 (3~64) winsize 62
820 13:56:52.846933
821 13:56:52.849624 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 13:56:52.850098
823 13:56:52.853449 [CATrainingPosCal] consider 2 rank data
824 13:56:52.856974 u2DelayCellTimex100 = 270/100 ps
825 13:56:52.860376 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 13:56:52.864385 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 13:56:52.869676 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 13:56:52.873186 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 13:56:52.876505 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 13:56:52.880357 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 13:56:52.880998
832 13:56:52.883352 CA PerBit enable=1, Macro0, CA PI delay=33
833 13:56:52.883938
834 13:56:52.886543 [CBTSetCACLKResult] CA Dly = 33
835 13:56:52.887128 CS Dly: 6 (0~38)
836 13:56:52.887509
837 13:56:52.890136 ----->DramcWriteLeveling(PI) begin...
838 13:56:52.893169 ==
839 13:56:52.896129 Dram Type= 6, Freq= 0, CH_0, rank 0
840 13:56:52.900192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 13:56:52.900844 ==
842 13:56:52.902972 Write leveling (Byte 0): 28 => 28
843 13:56:52.906255 Write leveling (Byte 1): 29 => 29
844 13:56:52.910514 DramcWriteLeveling(PI) end<-----
845 13:56:52.911107
846 13:56:52.911493 ==
847 13:56:52.913742 Dram Type= 6, Freq= 0, CH_0, rank 0
848 13:56:52.916509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 13:56:52.917037 ==
850 13:56:52.920031 [Gating] SW mode calibration
851 13:56:52.926768 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 13:56:52.929759 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 13:56:52.936648 0 6 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
854 13:56:52.940060 0 6 4 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
855 13:56:52.943383 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:56:52.950045 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:56:52.953239 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:56:52.957701 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:56:52.963245 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:56:52.966886 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:56:52.970151 0 7 0 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (1 1)
862 13:56:52.976884 0 7 4 | B1->B0 | 3b3b 3d3d | 0 0 | (0 0) (1 1)
863 13:56:52.979908 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 13:56:52.982863 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 13:56:52.990442 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 13:56:52.993195 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 13:56:52.997703 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 13:56:53.002889 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 13:56:53.006498 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 13:56:53.009332 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 13:56:53.015975 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 13:56:53.019625 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 13:56:53.023011 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 13:56:53.030378 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 13:56:53.032799 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 13:56:53.036491 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 13:56:53.040106 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 13:56:53.046606 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 13:56:53.049474 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 13:56:53.053576 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 13:56:53.059523 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 13:56:53.064276 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 13:56:53.066550 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 13:56:53.072865 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 13:56:53.077507 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 13:56:53.079852 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 13:56:53.082812 Total UI for P1: 0, mck2ui 16
888 13:56:53.086369 best dqsien dly found for B0: ( 0, 10, 0)
889 13:56:53.090104 Total UI for P1: 0, mck2ui 16
890 13:56:53.093586 best dqsien dly found for B1: ( 0, 10, 0)
891 13:56:53.097595 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 13:56:53.100061 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 13:56:53.100641
894 13:56:53.103443 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 13:56:53.110583 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 13:56:53.111155 [Gating] SW calibration Done
897 13:56:53.111537 ==
898 13:56:53.113020 Dram Type= 6, Freq= 0, CH_0, rank 0
899 13:56:53.120976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 13:56:53.121470 ==
901 13:56:53.122039 RX Vref Scan: 0
902 13:56:53.122616
903 13:56:53.123632 RX Vref 0 -> 0, step: 1
904 13:56:53.124108
905 13:56:53.127397 RX Delay -130 -> 252, step: 16
906 13:56:53.131140 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 13:56:53.133584 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 13:56:53.137179 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 13:56:53.140600 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 13:56:53.147047 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 13:56:53.150406 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 13:56:53.154049 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 13:56:53.157433 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 13:56:53.160927 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
915 13:56:53.167730 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 13:56:53.170823 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 13:56:53.174187 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 13:56:53.177636 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 13:56:53.180679 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 13:56:53.188325 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 13:56:53.190606 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 13:56:53.191186 ==
923 13:56:53.193515 Dram Type= 6, Freq= 0, CH_0, rank 0
924 13:56:53.196811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 13:56:53.197294 ==
926 13:56:53.200848 DQS Delay:
927 13:56:53.201433 DQS0 = 0, DQS1 = 0
928 13:56:53.201816 DQM Delay:
929 13:56:53.204303 DQM0 = 82, DQM1 = 73
930 13:56:53.204933 DQ Delay:
931 13:56:53.208241 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 13:56:53.210046 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 13:56:53.213679 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
934 13:56:53.216828 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 13:56:53.217302
936 13:56:53.217674
937 13:56:53.218023 ==
938 13:56:53.220103 Dram Type= 6, Freq= 0, CH_0, rank 0
939 13:56:53.227052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 13:56:53.227540 ==
941 13:56:53.227918
942 13:56:53.228264
943 13:56:53.228594 TX Vref Scan disable
944 13:56:53.229987 == TX Byte 0 ==
945 13:56:53.233971 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
946 13:56:53.237283 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
947 13:56:53.240478 == TX Byte 1 ==
948 13:56:53.244041 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
949 13:56:53.250388 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
950 13:56:53.250867 ==
951 13:56:53.254518 Dram Type= 6, Freq= 0, CH_0, rank 0
952 13:56:53.256920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 13:56:53.257396 ==
954 13:56:53.268776 TX Vref=22, minBit 0, minWin=27, winSum=445
955 13:56:53.272482 TX Vref=24, minBit 3, minWin=27, winSum=449
956 13:56:53.275681 TX Vref=26, minBit 4, minWin=27, winSum=451
957 13:56:53.279213 TX Vref=28, minBit 0, minWin=28, winSum=454
958 13:56:53.282331 TX Vref=30, minBit 0, minWin=28, winSum=456
959 13:56:53.285571 TX Vref=32, minBit 0, minWin=28, winSum=454
960 13:56:53.291817 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
961 13:56:53.292064
962 13:56:53.295867 Final TX Range 1 Vref 30
963 13:56:53.296061
964 13:56:53.296214 ==
965 13:56:53.298365 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:56:53.301887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 13:56:53.302049 ==
968 13:56:53.305314
969 13:56:53.305450
970 13:56:53.305560 TX Vref Scan disable
971 13:56:53.308614 == TX Byte 0 ==
972 13:56:53.311778 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
973 13:56:53.319122 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
974 13:56:53.319265 == TX Byte 1 ==
975 13:56:53.322276 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 13:56:53.329680 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 13:56:53.329818
978 13:56:53.329929 [DATLAT]
979 13:56:53.330031 Freq=800, CH0 RK0
980 13:56:53.330131
981 13:56:53.332165 DATLAT Default: 0xa
982 13:56:53.332302 0, 0xFFFF, sum = 0
983 13:56:53.334970 1, 0xFFFF, sum = 0
984 13:56:53.335109 2, 0xFFFF, sum = 0
985 13:56:53.338891 3, 0xFFFF, sum = 0
986 13:56:53.341524 4, 0xFFFF, sum = 0
987 13:56:53.341664 5, 0xFFFF, sum = 0
988 13:56:53.344746 6, 0xFFFF, sum = 0
989 13:56:53.344885 7, 0xFFFF, sum = 0
990 13:56:53.348443 8, 0x0, sum = 1
991 13:56:53.348583 9, 0x0, sum = 2
992 13:56:53.348694 10, 0x0, sum = 3
993 13:56:53.351845 11, 0x0, sum = 4
994 13:56:53.351995 best_step = 9
995 13:56:53.352105
996 13:56:53.352206 ==
997 13:56:53.355371 Dram Type= 6, Freq= 0, CH_0, rank 0
998 13:56:53.361827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 13:56:53.362054 ==
1000 13:56:53.362181 RX Vref Scan: 1
1001 13:56:53.362291
1002 13:56:53.365828 Set Vref Range= 32 -> 127
1003 13:56:53.365969
1004 13:56:53.368686 RX Vref 32 -> 127, step: 1
1005 13:56:53.368839
1006 13:56:53.371493 RX Delay -111 -> 252, step: 8
1007 13:56:53.371632
1008 13:56:53.375206 Set Vref, RX VrefLevel [Byte0]: 32
1009 13:56:53.378422 [Byte1]: 32
1010 13:56:53.378663
1011 13:56:53.381631 Set Vref, RX VrefLevel [Byte0]: 33
1012 13:56:53.385555 [Byte1]: 33
1013 13:56:53.385849
1014 13:56:53.388471 Set Vref, RX VrefLevel [Byte0]: 34
1015 13:56:53.392105 [Byte1]: 34
1016 13:56:53.395353
1017 13:56:53.395759 Set Vref, RX VrefLevel [Byte0]: 35
1018 13:56:53.398712 [Byte1]: 35
1019 13:56:53.403395
1020 13:56:53.403887 Set Vref, RX VrefLevel [Byte0]: 36
1021 13:56:53.406319 [Byte1]: 36
1022 13:56:53.410590
1023 13:56:53.411171 Set Vref, RX VrefLevel [Byte0]: 37
1024 13:56:53.413643 [Byte1]: 37
1025 13:56:53.418680
1026 13:56:53.419237 Set Vref, RX VrefLevel [Byte0]: 38
1027 13:56:53.422179 [Byte1]: 38
1028 13:56:53.425614
1029 13:56:53.426130 Set Vref, RX VrefLevel [Byte0]: 39
1030 13:56:53.430754 [Byte1]: 39
1031 13:56:53.433963
1032 13:56:53.434424 Set Vref, RX VrefLevel [Byte0]: 40
1033 13:56:53.436497 [Byte1]: 40
1034 13:56:53.441450
1035 13:56:53.442010 Set Vref, RX VrefLevel [Byte0]: 41
1036 13:56:53.444743 [Byte1]: 41
1037 13:56:53.448541
1038 13:56:53.449050 Set Vref, RX VrefLevel [Byte0]: 42
1039 13:56:53.452852 [Byte1]: 42
1040 13:56:53.457113
1041 13:56:53.457671 Set Vref, RX VrefLevel [Byte0]: 43
1042 13:56:53.460151 [Byte1]: 43
1043 13:56:53.464059
1044 13:56:53.464613 Set Vref, RX VrefLevel [Byte0]: 44
1045 13:56:53.467469 [Byte1]: 44
1046 13:56:53.471958
1047 13:56:53.472518 Set Vref, RX VrefLevel [Byte0]: 45
1048 13:56:53.475231 [Byte1]: 45
1049 13:56:53.479434
1050 13:56:53.479994 Set Vref, RX VrefLevel [Byte0]: 46
1051 13:56:53.482675 [Byte1]: 46
1052 13:56:53.486998
1053 13:56:53.487576 Set Vref, RX VrefLevel [Byte0]: 47
1054 13:56:53.490710 [Byte1]: 47
1055 13:56:53.495453
1056 13:56:53.496015 Set Vref, RX VrefLevel [Byte0]: 48
1057 13:56:53.497620 [Byte1]: 48
1058 13:56:53.502775
1059 13:56:53.503329 Set Vref, RX VrefLevel [Byte0]: 49
1060 13:56:53.505593 [Byte1]: 49
1061 13:56:53.511852
1062 13:56:53.512433 Set Vref, RX VrefLevel [Byte0]: 50
1063 13:56:53.513314 [Byte1]: 50
1064 13:56:53.517852
1065 13:56:53.518417 Set Vref, RX VrefLevel [Byte0]: 51
1066 13:56:53.521411 [Byte1]: 51
1067 13:56:53.526404
1068 13:56:53.526964 Set Vref, RX VrefLevel [Byte0]: 52
1069 13:56:53.528142 [Byte1]: 52
1070 13:56:53.533316
1071 13:56:53.533874 Set Vref, RX VrefLevel [Byte0]: 53
1072 13:56:53.536353 [Byte1]: 53
1073 13:56:53.540543
1074 13:56:53.541172 Set Vref, RX VrefLevel [Byte0]: 54
1075 13:56:53.544226 [Byte1]: 54
1076 13:56:53.549447
1077 13:56:53.550006 Set Vref, RX VrefLevel [Byte0]: 55
1078 13:56:53.552331 [Byte1]: 55
1079 13:56:53.555800
1080 13:56:53.556359 Set Vref, RX VrefLevel [Byte0]: 56
1081 13:56:53.559947 [Byte1]: 56
1082 13:56:53.563752
1083 13:56:53.564212 Set Vref, RX VrefLevel [Byte0]: 57
1084 13:56:53.566538 [Byte1]: 57
1085 13:56:53.571083
1086 13:56:53.571546 Set Vref, RX VrefLevel [Byte0]: 58
1087 13:56:53.574774 [Byte1]: 58
1088 13:56:53.578800
1089 13:56:53.579262 Set Vref, RX VrefLevel [Byte0]: 59
1090 13:56:53.582295 [Byte1]: 59
1091 13:56:53.586403
1092 13:56:53.586866 Set Vref, RX VrefLevel [Byte0]: 60
1093 13:56:53.589450 [Byte1]: 60
1094 13:56:53.594303
1095 13:56:53.594894 Set Vref, RX VrefLevel [Byte0]: 61
1096 13:56:53.597438 [Byte1]: 61
1097 13:56:53.601894
1098 13:56:53.602452 Set Vref, RX VrefLevel [Byte0]: 62
1099 13:56:53.605191 [Byte1]: 62
1100 13:56:53.609263
1101 13:56:53.609841 Set Vref, RX VrefLevel [Byte0]: 63
1102 13:56:53.612482 [Byte1]: 63
1103 13:56:53.617691
1104 13:56:53.618165 Set Vref, RX VrefLevel [Byte0]: 64
1105 13:56:53.620571 [Byte1]: 64
1106 13:56:53.625534
1107 13:56:53.626095 Set Vref, RX VrefLevel [Byte0]: 65
1108 13:56:53.628189 [Byte1]: 65
1109 13:56:53.632082
1110 13:56:53.632639 Set Vref, RX VrefLevel [Byte0]: 66
1111 13:56:53.636425 [Byte1]: 66
1112 13:56:53.639994
1113 13:56:53.640551 Set Vref, RX VrefLevel [Byte0]: 67
1114 13:56:53.644562 [Byte1]: 67
1115 13:56:53.648065
1116 13:56:53.648623 Set Vref, RX VrefLevel [Byte0]: 68
1117 13:56:53.651783 [Byte1]: 68
1118 13:56:53.655792
1119 13:56:53.656351 Set Vref, RX VrefLevel [Byte0]: 69
1120 13:56:53.658535 [Byte1]: 69
1121 13:56:53.663089
1122 13:56:53.663647 Set Vref, RX VrefLevel [Byte0]: 70
1123 13:56:53.666654 [Byte1]: 70
1124 13:56:53.670601
1125 13:56:53.671156 Set Vref, RX VrefLevel [Byte0]: 71
1126 13:56:53.673843 [Byte1]: 71
1127 13:56:53.678161
1128 13:56:53.678717 Set Vref, RX VrefLevel [Byte0]: 72
1129 13:56:53.682009 [Byte1]: 72
1130 13:56:53.686832
1131 13:56:53.687394 Set Vref, RX VrefLevel [Byte0]: 73
1132 13:56:53.689142 [Byte1]: 73
1133 13:56:53.693304
1134 13:56:53.693867 Set Vref, RX VrefLevel [Byte0]: 74
1135 13:56:53.696561 [Byte1]: 74
1136 13:56:53.701278
1137 13:56:53.701988 Set Vref, RX VrefLevel [Byte0]: 75
1138 13:56:53.704278 [Byte1]: 75
1139 13:56:53.708537
1140 13:56:53.709240 Final RX Vref Byte 0 = 49 to rank0
1141 13:56:53.712134 Final RX Vref Byte 1 = 55 to rank0
1142 13:56:53.715832 Final RX Vref Byte 0 = 49 to rank1
1143 13:56:53.718281 Final RX Vref Byte 1 = 55 to rank1==
1144 13:56:53.721564 Dram Type= 6, Freq= 0, CH_0, rank 0
1145 13:56:53.728671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1146 13:56:53.729369 ==
1147 13:56:53.729752 DQS Delay:
1148 13:56:53.733094 DQS0 = 0, DQS1 = 0
1149 13:56:53.733668 DQM Delay:
1150 13:56:53.734044 DQM0 = 84, DQM1 = 74
1151 13:56:53.735187 DQ Delay:
1152 13:56:53.738812 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1153 13:56:53.741790 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1154 13:56:53.746813 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1155 13:56:53.748850 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1156 13:56:53.749320
1157 13:56:53.749691
1158 13:56:53.755280 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1159 13:56:53.758870 CH0 RK0: MR19=606, MR18=3A3A
1160 13:56:53.765592 CH0_RK0: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1161 13:56:53.766161
1162 13:56:53.768146 ----->DramcWriteLeveling(PI) begin...
1163 13:56:53.768619 ==
1164 13:56:53.772504 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 13:56:53.775118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1166 13:56:53.775690 ==
1167 13:56:53.778816 Write leveling (Byte 0): 31 => 31
1168 13:56:53.783003 Write leveling (Byte 1): 30 => 30
1169 13:56:53.786238 DramcWriteLeveling(PI) end<-----
1170 13:56:53.786793
1171 13:56:53.787180 ==
1172 13:56:53.789234 Dram Type= 6, Freq= 0, CH_0, rank 1
1173 13:56:53.792134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1174 13:56:53.792778 ==
1175 13:56:53.795188 [Gating] SW mode calibration
1176 13:56:53.801987 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1177 13:56:53.809306 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1178 13:56:53.811776 0 6 0 | B1->B0 | 3232 3131 | 0 1 | (0 1) (1 0)
1179 13:56:53.815086 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:56:53.821504 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:56:53.825634 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:56:53.829026 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:56:53.834720 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:56:53.839279 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:56:53.841597 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:56:53.848961 0 7 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
1187 13:56:53.851612 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
1188 13:56:53.855706 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 13:56:53.862091 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 13:56:53.865675 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 13:56:53.869019 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 13:56:53.875597 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 13:56:53.878056 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:56:53.881747 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:56:53.889164 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 13:56:53.891627 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:56:53.895084 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:56:53.898922 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:56:53.905110 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:56:53.908111 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:56:53.912327 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:56:53.918553 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:56:53.921535 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:56:53.925822 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:56:53.931616 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:56:53.934546 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:56:53.937896 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:56:53.944834 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:56:53.948127 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:56:53.951807 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1211 13:56:53.958001 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1212 13:56:53.961309 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 13:56:53.965181 Total UI for P1: 0, mck2ui 16
1214 13:56:53.967955 best dqsien dly found for B0: ( 0, 10, 2)
1215 13:56:53.971845 Total UI for P1: 0, mck2ui 16
1216 13:56:53.975473 best dqsien dly found for B1: ( 0, 10, 2)
1217 13:56:53.978720 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1218 13:56:53.981505 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1219 13:56:53.982083
1220 13:56:53.985354 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1221 13:56:53.988306 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1222 13:56:53.991398 [Gating] SW calibration Done
1223 13:56:53.991973 ==
1224 13:56:53.995880 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 13:56:54.038840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1226 13:56:54.039459 ==
1227 13:56:54.039953 RX Vref Scan: 0
1228 13:56:54.040404
1229 13:56:54.041365 RX Vref 0 -> 0, step: 1
1230 13:56:54.041778
1231 13:56:54.042232 RX Delay -130 -> 252, step: 16
1232 13:56:54.042694 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1233 13:56:54.043153 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1234 13:56:54.043585 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1235 13:56:54.044025 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1236 13:56:54.044453 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1237 13:56:54.045053 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1238 13:56:54.045452 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1239 13:56:54.045875 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1240 13:56:54.054994 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1241 13:56:54.055953 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1242 13:56:54.056354 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1243 13:56:54.059303 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1244 13:56:54.061603 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1245 13:56:54.062070 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1246 13:56:54.067820 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1247 13:56:54.071068 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1248 13:56:54.071578 ==
1249 13:56:54.075297 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 13:56:54.078877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1251 13:56:54.079445 ==
1252 13:56:54.079819 DQS Delay:
1253 13:56:54.081900 DQS0 = 0, DQS1 = 0
1254 13:56:54.082459 DQM Delay:
1255 13:56:54.085440 DQM0 = 83, DQM1 = 73
1256 13:56:54.086007 DQ Delay:
1257 13:56:54.087749 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1258 13:56:54.091868 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1259 13:56:54.094670 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1260 13:56:54.098021 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1261 13:56:54.098585
1262 13:56:54.098955
1263 13:56:54.099295 ==
1264 13:56:54.100845 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 13:56:54.104818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1266 13:56:54.107983 ==
1267 13:56:54.108539
1268 13:56:54.108972
1269 13:56:54.109316 TX Vref Scan disable
1270 13:56:54.110875 == TX Byte 0 ==
1271 13:56:54.114947 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1272 13:56:54.117675 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1273 13:56:54.121155 == TX Byte 1 ==
1274 13:56:54.124691 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1275 13:56:54.128104 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1276 13:56:54.131396 ==
1277 13:56:54.134794 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 13:56:54.137821 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1279 13:56:54.138385 ==
1280 13:56:54.149679 TX Vref=22, minBit 0, minWin=27, winSum=450
1281 13:56:54.153289 TX Vref=24, minBit 13, minWin=27, winSum=449
1282 13:56:54.156899 TX Vref=26, minBit 2, minWin=28, winSum=455
1283 13:56:54.160862 TX Vref=28, minBit 2, minWin=28, winSum=459
1284 13:56:54.165462 TX Vref=30, minBit 2, minWin=28, winSum=458
1285 13:56:54.169978 TX Vref=32, minBit 0, minWin=28, winSum=456
1286 13:56:54.173350 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 28
1287 13:56:54.173916
1288 13:56:54.176677 Final TX Range 1 Vref 28
1289 13:56:54.177282
1290 13:56:54.177648 ==
1291 13:56:54.180000 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 13:56:54.183602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1293 13:56:54.184182 ==
1294 13:56:54.184550
1295 13:56:54.187193
1296 13:56:54.187754 TX Vref Scan disable
1297 13:56:54.189962 == TX Byte 0 ==
1298 13:56:54.193457 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1299 13:56:54.198050 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1300 13:56:54.200221 == TX Byte 1 ==
1301 13:56:54.203847 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1302 13:56:54.206327 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1303 13:56:54.210083
1304 13:56:54.210709 [DATLAT]
1305 13:56:54.211078 Freq=800, CH0 RK1
1306 13:56:54.211420
1307 13:56:54.214148 DATLAT Default: 0x9
1308 13:56:54.214606 0, 0xFFFF, sum = 0
1309 13:56:54.216787 1, 0xFFFF, sum = 0
1310 13:56:54.217253 2, 0xFFFF, sum = 0
1311 13:56:54.220341 3, 0xFFFF, sum = 0
1312 13:56:54.223826 4, 0xFFFF, sum = 0
1313 13:56:54.224388 5, 0xFFFF, sum = 0
1314 13:56:54.226128 6, 0xFFFF, sum = 0
1315 13:56:54.226594 7, 0xFFFF, sum = 0
1316 13:56:54.226968 8, 0x0, sum = 1
1317 13:56:54.230669 9, 0x0, sum = 2
1318 13:56:54.231136 10, 0x0, sum = 3
1319 13:56:54.233464 11, 0x0, sum = 4
1320 13:56:54.233933 best_step = 9
1321 13:56:54.234359
1322 13:56:54.234716 ==
1323 13:56:54.236215 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 13:56:54.243876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1325 13:56:54.244433 ==
1326 13:56:54.244861 RX Vref Scan: 0
1327 13:56:54.245212
1328 13:56:54.246331 RX Vref 0 -> 0, step: 1
1329 13:56:54.246787
1330 13:56:54.249628 RX Delay -111 -> 252, step: 8
1331 13:56:54.252965 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1332 13:56:54.256629 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1333 13:56:54.262882 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1334 13:56:54.266494 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1335 13:56:54.270020 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1336 13:56:54.274154 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1337 13:56:54.276684 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1338 13:56:54.283398 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1339 13:56:54.286162 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1340 13:56:54.289405 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1341 13:56:54.293137 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1342 13:56:54.296678 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1343 13:56:54.303431 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1344 13:56:54.306402 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1345 13:56:54.309513 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1346 13:56:54.312519 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1347 13:56:54.313019 ==
1348 13:56:54.316750 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 13:56:54.322782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1350 13:56:54.323335 ==
1351 13:56:54.323707 DQS Delay:
1352 13:56:54.326079 DQS0 = 0, DQS1 = 0
1353 13:56:54.326540 DQM Delay:
1354 13:56:54.326903 DQM0 = 86, DQM1 = 75
1355 13:56:54.329524 DQ Delay:
1356 13:56:54.332393 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1357 13:56:54.335943 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1358 13:56:54.339708 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1359 13:56:54.342620 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1360 13:56:54.343081
1361 13:56:54.343509
1362 13:56:54.349673 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1363 13:56:54.352738 CH0 RK1: MR19=606, MR18=4141
1364 13:56:54.359413 CH0_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1365 13:56:54.362323 [RxdqsGatingPostProcess] freq 800
1366 13:56:54.365479 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1367 13:56:54.369040 Pre-setting of DQS Precalculation
1368 13:56:54.375420 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1369 13:56:54.375642 ==
1370 13:56:54.379178 Dram Type= 6, Freq= 0, CH_1, rank 0
1371 13:56:54.383991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1372 13:56:54.384309 ==
1373 13:56:54.389845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1374 13:56:54.392439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1375 13:56:54.402767 [CA 0] Center 36 (6~67) winsize 62
1376 13:56:54.406652 [CA 1] Center 36 (5~67) winsize 63
1377 13:56:54.409393 [CA 2] Center 34 (4~65) winsize 62
1378 13:56:54.412570 [CA 3] Center 34 (4~65) winsize 62
1379 13:56:54.415851 [CA 4] Center 33 (3~64) winsize 62
1380 13:56:54.419469 [CA 5] Center 33 (3~64) winsize 62
1381 13:56:54.419929
1382 13:56:54.422484 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1383 13:56:54.423057
1384 13:56:54.425746 [CATrainingPosCal] consider 1 rank data
1385 13:56:54.428978 u2DelayCellTimex100 = 270/100 ps
1386 13:56:54.433375 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1387 13:56:54.439371 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1388 13:56:54.443106 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 13:56:54.445620 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 13:56:54.449664 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1391 13:56:54.452761 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1392 13:56:54.453324
1393 13:56:54.457165 CA PerBit enable=1, Macro0, CA PI delay=33
1394 13:56:54.457724
1395 13:56:54.459046 [CBTSetCACLKResult] CA Dly = 33
1396 13:56:54.459503 CS Dly: 4 (0~35)
1397 13:56:54.462369 ==
1398 13:56:54.462823 Dram Type= 6, Freq= 0, CH_1, rank 1
1399 13:56:54.470391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1400 13:56:54.470952 ==
1401 13:56:54.472359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1402 13:56:54.479156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1403 13:56:54.489357 [CA 0] Center 36 (6~67) winsize 62
1404 13:56:54.492564 [CA 1] Center 36 (5~67) winsize 63
1405 13:56:54.496019 [CA 2] Center 34 (4~65) winsize 62
1406 13:56:54.498576 [CA 3] Center 34 (4~64) winsize 61
1407 13:56:54.502981 [CA 4] Center 33 (3~64) winsize 62
1408 13:56:54.506022 [CA 5] Center 33 (2~64) winsize 63
1409 13:56:54.506574
1410 13:56:54.508651 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1411 13:56:54.509202
1412 13:56:54.511836 [CATrainingPosCal] consider 2 rank data
1413 13:56:54.514979 u2DelayCellTimex100 = 270/100 ps
1414 13:56:54.518139 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1415 13:56:54.522910 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1416 13:56:54.529630 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 13:56:54.531920 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1418 13:56:54.535001 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1419 13:56:54.538557 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1420 13:56:54.539111
1421 13:56:54.542152 CA PerBit enable=1, Macro0, CA PI delay=33
1422 13:56:54.542614
1423 13:56:54.545800 [CBTSetCACLKResult] CA Dly = 33
1424 13:56:54.546258 CS Dly: 4 (0~36)
1425 13:56:54.546626
1426 13:56:54.549493 ----->DramcWriteLeveling(PI) begin...
1427 13:56:54.552217 ==
1428 13:56:54.552830 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 13:56:54.558653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1430 13:56:54.559226 ==
1431 13:56:54.561873 Write leveling (Byte 0): 23 => 23
1432 13:56:54.565419 Write leveling (Byte 1): 27 => 27
1433 13:56:54.568927 DramcWriteLeveling(PI) end<-----
1434 13:56:54.569490
1435 13:56:54.569859 ==
1436 13:56:54.572921 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 13:56:54.575247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1438 13:56:54.575814 ==
1439 13:56:54.579745 [Gating] SW mode calibration
1440 13:56:54.584916 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1441 13:56:54.588352 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1442 13:56:54.596249 0 6 0 | B1->B0 | 3232 2626 | 1 0 | (1 0) (0 0)
1443 13:56:54.598868 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 13:56:54.602323 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 13:56:54.608407 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 13:56:54.611869 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 13:56:54.615358 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:56:54.621273 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:56:54.625484 0 6 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1450 13:56:54.628591 0 7 0 | B1->B0 | 3030 4444 | 1 0 | (0 0) (0 0)
1451 13:56:54.635031 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1452 13:56:54.638279 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 13:56:54.641732 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 13:56:54.648193 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 13:56:54.651582 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1456 13:56:54.654436 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1457 13:56:54.661669 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1458 13:56:54.664874 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1459 13:56:54.668486 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 13:56:54.675734 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 13:56:54.678412 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 13:56:54.681642 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 13:56:54.688370 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 13:56:54.692165 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 13:56:54.694360 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 13:56:54.701359 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 13:56:54.704832 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 13:56:54.708986 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 13:56:54.712183 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 13:56:54.718330 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 13:56:54.721730 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1472 13:56:54.725231 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1473 13:56:54.731539 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1474 13:56:54.734735 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1475 13:56:54.737951 Total UI for P1: 0, mck2ui 16
1476 13:56:54.741646 best dqsien dly found for B0: ( 0, 9, 28)
1477 13:56:54.744624 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1478 13:56:54.748937 Total UI for P1: 0, mck2ui 16
1479 13:56:54.751111 best dqsien dly found for B1: ( 0, 10, 0)
1480 13:56:54.754298 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1481 13:56:54.757828 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1482 13:56:54.758292
1483 13:56:54.764761 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1484 13:56:54.767855 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1485 13:56:54.771884 [Gating] SW calibration Done
1486 13:56:54.772463 ==
1487 13:56:54.775337 Dram Type= 6, Freq= 0, CH_1, rank 0
1488 13:56:54.778494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1489 13:56:54.779067 ==
1490 13:56:54.779441 RX Vref Scan: 0
1491 13:56:54.779785
1492 13:56:54.783244 RX Vref 0 -> 0, step: 1
1493 13:56:54.783812
1494 13:56:54.784916 RX Delay -130 -> 252, step: 16
1495 13:56:54.788266 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1496 13:56:54.791760 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1497 13:56:54.798116 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1498 13:56:54.801379 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1499 13:56:54.804595 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1500 13:56:54.808662 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1501 13:56:54.811661 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1502 13:56:54.820322 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1503 13:56:54.821287 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1504 13:56:54.825026 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1505 13:56:54.828131 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1506 13:56:54.831136 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1507 13:56:54.837549 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1508 13:56:54.840897 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1509 13:56:54.844360 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1510 13:56:54.847865 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1511 13:56:54.848453 ==
1512 13:56:54.851420 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 13:56:54.857691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1514 13:56:54.858269 ==
1515 13:56:54.858644 DQS Delay:
1516 13:56:54.858989 DQS0 = 0, DQS1 = 0
1517 13:56:54.860772 DQM Delay:
1518 13:56:54.861237 DQM0 = 81, DQM1 = 70
1519 13:56:54.864377 DQ Delay:
1520 13:56:54.867722 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1521 13:56:54.868303 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1522 13:56:54.871667 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1523 13:56:54.874123 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1524 13:56:54.878425
1525 13:56:54.878990
1526 13:56:54.879361 ==
1527 13:56:54.881628 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 13:56:54.884882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1529 13:56:54.885458 ==
1530 13:56:54.885835
1531 13:56:54.886186
1532 13:56:54.887994 TX Vref Scan disable
1533 13:56:54.888563 == TX Byte 0 ==
1534 13:56:54.894523 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1535 13:56:54.898088 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1536 13:56:54.898662 == TX Byte 1 ==
1537 13:56:54.904764 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1538 13:56:54.908685 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1539 13:56:54.909223 ==
1540 13:56:54.911105 Dram Type= 6, Freq= 0, CH_1, rank 0
1541 13:56:54.914090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1542 13:56:54.914667 ==
1543 13:56:54.928209 TX Vref=22, minBit 8, minWin=27, winSum=448
1544 13:56:54.933427 TX Vref=24, minBit 8, minWin=27, winSum=450
1545 13:56:54.935531 TX Vref=26, minBit 0, minWin=28, winSum=452
1546 13:56:54.938998 TX Vref=28, minBit 3, minWin=28, winSum=454
1547 13:56:54.941591 TX Vref=30, minBit 9, minWin=27, winSum=455
1548 13:56:54.944662 TX Vref=32, minBit 8, minWin=28, winSum=456
1549 13:56:54.951533 [TxChooseVref] Worse bit 8, Min win 28, Win sum 456, Final Vref 32
1550 13:56:54.952108
1551 13:56:54.955103 Final TX Range 1 Vref 32
1552 13:56:54.955674
1553 13:56:54.956045 ==
1554 13:56:54.958364 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 13:56:54.961676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1556 13:56:54.962249 ==
1557 13:56:54.962626
1558 13:56:54.963160
1559 13:56:54.964870 TX Vref Scan disable
1560 13:56:54.968887 == TX Byte 0 ==
1561 13:56:54.972107 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1562 13:56:54.974663 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1563 13:56:54.978733 == TX Byte 1 ==
1564 13:56:54.981632 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1565 13:56:54.984936 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1566 13:56:54.988735
1567 13:56:54.989309 [DATLAT]
1568 13:56:54.989685 Freq=800, CH1 RK0
1569 13:56:54.990041
1570 13:56:54.991448 DATLAT Default: 0xa
1571 13:56:54.991915 0, 0xFFFF, sum = 0
1572 13:56:54.995416 1, 0xFFFF, sum = 0
1573 13:56:54.995996 2, 0xFFFF, sum = 0
1574 13:56:54.998396 3, 0xFFFF, sum = 0
1575 13:56:54.998944 4, 0xFFFF, sum = 0
1576 13:56:55.001974 5, 0xFFFF, sum = 0
1577 13:56:55.002548 6, 0xFFFF, sum = 0
1578 13:56:55.005023 7, 0xFFFF, sum = 0
1579 13:56:55.005606 8, 0x0, sum = 1
1580 13:56:55.008540 9, 0x0, sum = 2
1581 13:56:55.009168 10, 0x0, sum = 3
1582 13:56:55.011691 11, 0x0, sum = 4
1583 13:56:55.012268 best_step = 9
1584 13:56:55.012639
1585 13:56:55.013029 ==
1586 13:56:55.015472 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 13:56:55.021401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1588 13:56:55.021876 ==
1589 13:56:55.022246 RX Vref Scan: 1
1590 13:56:55.022589
1591 13:56:55.025203 Set Vref Range= 32 -> 127
1592 13:56:55.025666
1593 13:56:55.028120 RX Vref 32 -> 127, step: 1
1594 13:56:55.028584
1595 13:56:55.028998 RX Delay -111 -> 252, step: 8
1596 13:56:55.031551
1597 13:56:55.032016 Set Vref, RX VrefLevel [Byte0]: 32
1598 13:56:55.035447 [Byte1]: 32
1599 13:56:55.041034
1600 13:56:55.041598 Set Vref, RX VrefLevel [Byte0]: 33
1601 13:56:55.043231 [Byte1]: 33
1602 13:56:55.048528
1603 13:56:55.049159 Set Vref, RX VrefLevel [Byte0]: 34
1604 13:56:55.050428 [Byte1]: 34
1605 13:56:55.054487
1606 13:56:55.054953 Set Vref, RX VrefLevel [Byte0]: 35
1607 13:56:55.058489 [Byte1]: 35
1608 13:56:55.062457
1609 13:56:55.062941 Set Vref, RX VrefLevel [Byte0]: 36
1610 13:56:55.065502 [Byte1]: 36
1611 13:56:55.070162
1612 13:56:55.070744 Set Vref, RX VrefLevel [Byte0]: 37
1613 13:56:55.072830 [Byte1]: 37
1614 13:56:55.077506
1615 13:56:55.077973 Set Vref, RX VrefLevel [Byte0]: 38
1616 13:56:55.081550 [Byte1]: 38
1617 13:56:55.084874
1618 13:56:55.085442 Set Vref, RX VrefLevel [Byte0]: 39
1619 13:56:55.088799 [Byte1]: 39
1620 13:56:55.093067
1621 13:56:55.093639 Set Vref, RX VrefLevel [Byte0]: 40
1622 13:56:55.096482 [Byte1]: 40
1623 13:56:55.100670
1624 13:56:55.101304 Set Vref, RX VrefLevel [Byte0]: 41
1625 13:56:55.104546 [Byte1]: 41
1626 13:56:55.108657
1627 13:56:55.109289 Set Vref, RX VrefLevel [Byte0]: 42
1628 13:56:55.111006 [Byte1]: 42
1629 13:56:55.116405
1630 13:56:55.117037 Set Vref, RX VrefLevel [Byte0]: 43
1631 13:56:55.118787 [Byte1]: 43
1632 13:56:55.123649
1633 13:56:55.124292 Set Vref, RX VrefLevel [Byte0]: 44
1634 13:56:55.126647 [Byte1]: 44
1635 13:56:55.131299
1636 13:56:55.131761 Set Vref, RX VrefLevel [Byte0]: 45
1637 13:56:55.134303 [Byte1]: 45
1638 13:56:55.139356
1639 13:56:55.139907 Set Vref, RX VrefLevel [Byte0]: 46
1640 13:56:55.141412 [Byte1]: 46
1641 13:56:55.146239
1642 13:56:55.146701 Set Vref, RX VrefLevel [Byte0]: 47
1643 13:56:55.151843 [Byte1]: 47
1644 13:56:55.153505
1645 13:56:55.154144 Set Vref, RX VrefLevel [Byte0]: 48
1646 13:56:55.158631 [Byte1]: 48
1647 13:56:55.162206
1648 13:56:55.162762 Set Vref, RX VrefLevel [Byte0]: 49
1649 13:56:55.164877 [Byte1]: 49
1650 13:56:55.169598
1651 13:56:55.170158 Set Vref, RX VrefLevel [Byte0]: 50
1652 13:56:55.172162 [Byte1]: 50
1653 13:56:55.176604
1654 13:56:55.177206 Set Vref, RX VrefLevel [Byte0]: 51
1655 13:56:55.180471 [Byte1]: 51
1656 13:56:55.184790
1657 13:56:55.185370 Set Vref, RX VrefLevel [Byte0]: 52
1658 13:56:55.187915 [Byte1]: 52
1659 13:56:55.192234
1660 13:56:55.192846 Set Vref, RX VrefLevel [Byte0]: 53
1661 13:56:55.195236 [Byte1]: 53
1662 13:56:55.200368
1663 13:56:55.201070 Set Vref, RX VrefLevel [Byte0]: 54
1664 13:56:55.203566 [Byte1]: 54
1665 13:56:55.208058
1666 13:56:55.208613 Set Vref, RX VrefLevel [Byte0]: 55
1667 13:56:55.211070 [Byte1]: 55
1668 13:56:55.215314
1669 13:56:55.215876 Set Vref, RX VrefLevel [Byte0]: 56
1670 13:56:55.218140 [Byte1]: 56
1671 13:56:55.224269
1672 13:56:55.225082 Set Vref, RX VrefLevel [Byte0]: 57
1673 13:56:55.225962 [Byte1]: 57
1674 13:56:55.231187
1675 13:56:55.231769 Set Vref, RX VrefLevel [Byte0]: 58
1676 13:56:55.233420 [Byte1]: 58
1677 13:56:55.237921
1678 13:56:55.238474 Set Vref, RX VrefLevel [Byte0]: 59
1679 13:56:55.241368 [Byte1]: 59
1680 13:56:55.245854
1681 13:56:55.246324 Set Vref, RX VrefLevel [Byte0]: 60
1682 13:56:55.249057 [Byte1]: 60
1683 13:56:55.254401
1684 13:56:55.254961 Set Vref, RX VrefLevel [Byte0]: 61
1685 13:56:55.257366 [Byte1]: 61
1686 13:56:55.261681
1687 13:56:55.262251 Set Vref, RX VrefLevel [Byte0]: 62
1688 13:56:55.265499 [Byte1]: 62
1689 13:56:55.268357
1690 13:56:55.268872 Set Vref, RX VrefLevel [Byte0]: 63
1691 13:56:55.273630 [Byte1]: 63
1692 13:56:55.276274
1693 13:56:55.276774 Set Vref, RX VrefLevel [Byte0]: 64
1694 13:56:55.279803 [Byte1]: 64
1695 13:56:55.283745
1696 13:56:55.284309 Set Vref, RX VrefLevel [Byte0]: 65
1697 13:56:55.287758 [Byte1]: 65
1698 13:56:55.291470
1699 13:56:55.292027 Set Vref, RX VrefLevel [Byte0]: 66
1700 13:56:55.295091 [Byte1]: 66
1701 13:56:55.299000
1702 13:56:55.299470 Set Vref, RX VrefLevel [Byte0]: 67
1703 13:56:55.302506 [Byte1]: 67
1704 13:56:55.307111
1705 13:56:55.307669 Set Vref, RX VrefLevel [Byte0]: 68
1706 13:56:55.311001 [Byte1]: 68
1707 13:56:55.314972
1708 13:56:55.315532 Set Vref, RX VrefLevel [Byte0]: 69
1709 13:56:55.317495 [Byte1]: 69
1710 13:56:55.322202
1711 13:56:55.322764 Set Vref, RX VrefLevel [Byte0]: 70
1712 13:56:55.325425 [Byte1]: 70
1713 13:56:55.329698
1714 13:56:55.330161 Set Vref, RX VrefLevel [Byte0]: 71
1715 13:56:55.333192 [Byte1]: 71
1716 13:56:55.338139
1717 13:56:55.338700 Set Vref, RX VrefLevel [Byte0]: 72
1718 13:56:55.341374 [Byte1]: 72
1719 13:56:55.345417
1720 13:56:55.345882 Set Vref, RX VrefLevel [Byte0]: 73
1721 13:56:55.348146 [Byte1]: 73
1722 13:56:55.352553
1723 13:56:55.353176 Set Vref, RX VrefLevel [Byte0]: 74
1724 13:56:55.356290 [Byte1]: 74
1725 13:56:55.361485
1726 13:56:55.362044 Set Vref, RX VrefLevel [Byte0]: 75
1727 13:56:55.364281 [Byte1]: 75
1728 13:56:55.367901
1729 13:56:55.368465 Set Vref, RX VrefLevel [Byte0]: 76
1730 13:56:55.371284 [Byte1]: 76
1731 13:56:55.375702
1732 13:56:55.376170 Final RX Vref Byte 0 = 60 to rank0
1733 13:56:55.381628 Final RX Vref Byte 1 = 55 to rank0
1734 13:56:55.382542 Final RX Vref Byte 0 = 60 to rank1
1735 13:56:55.385257 Final RX Vref Byte 1 = 55 to rank1==
1736 13:56:55.389034 Dram Type= 6, Freq= 0, CH_1, rank 0
1737 13:56:55.395951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1738 13:56:55.396518 ==
1739 13:56:55.396938 DQS Delay:
1740 13:56:55.397284 DQS0 = 0, DQS1 = 0
1741 13:56:55.399291 DQM Delay:
1742 13:56:55.399880 DQM0 = 79, DQM1 = 72
1743 13:56:55.403383 DQ Delay:
1744 13:56:55.405946 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1745 13:56:55.406617 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1746 13:56:55.408916 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1747 13:56:55.412218 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1748 13:56:55.416056
1749 13:56:55.416614
1750 13:56:55.421891 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1751 13:56:55.425581 CH1 RK0: MR19=606, MR18=5252
1752 13:56:55.432139 CH1_RK0: MR19=0x606, MR18=0x5252, DQSOSC=389, MR23=63, INC=97, DEC=65
1753 13:56:55.432752
1754 13:56:55.435422 ----->DramcWriteLeveling(PI) begin...
1755 13:56:55.435988 ==
1756 13:56:55.439536 Dram Type= 6, Freq= 0, CH_1, rank 1
1757 13:56:55.442397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1758 13:56:55.442961 ==
1759 13:56:55.446152 Write leveling (Byte 0): 24 => 24
1760 13:56:55.448843 Write leveling (Byte 1): 24 => 24
1761 13:56:55.452747 DramcWriteLeveling(PI) end<-----
1762 13:56:55.453318
1763 13:56:55.453685 ==
1764 13:56:55.455746 Dram Type= 6, Freq= 0, CH_1, rank 1
1765 13:56:55.459026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1766 13:56:55.459594 ==
1767 13:56:55.462341 [Gating] SW mode calibration
1768 13:56:55.469771 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1769 13:56:55.475887 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1770 13:56:55.479282 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
1771 13:56:55.482898 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1772 13:56:55.489562 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1773 13:56:55.492325 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1774 13:56:55.496452 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1775 13:56:55.502389 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 13:56:55.505397 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1777 13:56:55.509166 0 6 28 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1778 13:56:55.515976 0 7 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
1779 13:56:55.519023 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1780 13:56:55.522248 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1781 13:56:55.528624 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1782 13:56:55.531939 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 13:56:55.535570 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 13:56:55.538589 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1785 13:56:55.546425 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1786 13:56:55.548559 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1787 13:56:55.552518 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 13:56:55.558339 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 13:56:55.561725 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 13:56:55.567125 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 13:56:55.572175 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 13:56:55.575513 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 13:56:55.578549 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 13:56:55.585349 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 13:56:55.588826 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 13:56:55.592061 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 13:56:55.598611 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 13:56:55.603122 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 13:56:55.605097 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 13:56:55.611865 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 13:56:55.615269 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1802 13:56:55.618811 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1803 13:56:55.622115 Total UI for P1: 0, mck2ui 16
1804 13:56:55.625131 best dqsien dly found for B0: ( 0, 9, 28)
1805 13:56:55.628770 Total UI for P1: 0, mck2ui 16
1806 13:56:55.631757 best dqsien dly found for B1: ( 0, 9, 30)
1807 13:56:55.635675 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1808 13:56:55.639342 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1809 13:56:55.639904
1810 13:56:55.641992 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1811 13:56:55.648601 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1812 13:56:55.649124 [Gating] SW calibration Done
1813 13:56:55.652816 ==
1814 13:56:55.653383 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 13:56:55.659050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1816 13:56:55.659621 ==
1817 13:56:55.659997 RX Vref Scan: 0
1818 13:56:55.660343
1819 13:56:55.661662 RX Vref 0 -> 0, step: 1
1820 13:56:55.662128
1821 13:56:55.665576 RX Delay -130 -> 252, step: 16
1822 13:56:55.668415 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1823 13:56:55.672229 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1824 13:56:55.675366 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1825 13:56:55.682695 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1826 13:56:55.685610 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1827 13:56:55.688748 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1828 13:56:55.692021 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1829 13:56:55.695762 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1830 13:56:55.701614 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1831 13:56:55.705427 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1832 13:56:55.710773 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1833 13:56:55.711781 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1834 13:56:55.715820 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1835 13:56:55.721853 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1836 13:56:55.725147 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1837 13:56:55.728589 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1838 13:56:55.729393 ==
1839 13:56:55.731773 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 13:56:55.735617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1841 13:56:55.739181 ==
1842 13:56:55.739743 DQS Delay:
1843 13:56:55.740114 DQS0 = 0, DQS1 = 0
1844 13:56:55.742028 DQM Delay:
1845 13:56:55.742586 DQM0 = 82, DQM1 = 71
1846 13:56:55.745255 DQ Delay:
1847 13:56:55.745714 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1848 13:56:55.748443 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1849 13:56:55.751566 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1850 13:56:55.755234 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1851 13:56:55.755793
1852 13:56:55.758022
1853 13:56:55.758477 ==
1854 13:56:55.761675 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 13:56:55.764733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1856 13:56:55.765217 ==
1857 13:56:55.765592
1858 13:56:55.765934
1859 13:56:55.768740 TX Vref Scan disable
1860 13:56:55.769203 == TX Byte 0 ==
1861 13:56:55.774947 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1862 13:56:55.778621 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1863 13:56:55.779189 == TX Byte 1 ==
1864 13:56:55.785055 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1865 13:56:55.788900 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1866 13:56:55.789469 ==
1867 13:56:55.792324 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 13:56:55.794492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1869 13:56:55.794954 ==
1870 13:56:55.808144 TX Vref=22, minBit 10, minWin=27, winSum=448
1871 13:56:55.811360 TX Vref=24, minBit 0, minWin=28, winSum=456
1872 13:56:55.814535 TX Vref=26, minBit 2, minWin=28, winSum=455
1873 13:56:55.818126 TX Vref=28, minBit 3, minWin=28, winSum=459
1874 13:56:55.821580 TX Vref=30, minBit 0, minWin=28, winSum=460
1875 13:56:55.828015 TX Vref=32, minBit 0, minWin=28, winSum=456
1876 13:56:55.831476 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1877 13:56:55.832041
1878 13:56:55.835297 Final TX Range 1 Vref 30
1879 13:56:55.835901
1880 13:56:55.836295 ==
1881 13:56:55.838423 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 13:56:55.841859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1883 13:56:55.842635 ==
1884 13:56:55.843028
1885 13:56:55.844676
1886 13:56:55.845161 TX Vref Scan disable
1887 13:56:55.848483 == TX Byte 0 ==
1888 13:56:55.851449 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1889 13:56:55.855912 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1890 13:56:55.858091 == TX Byte 1 ==
1891 13:56:55.861526 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1892 13:56:55.865234 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1893 13:56:55.870067
1894 13:56:55.870626 [DATLAT]
1895 13:56:55.871115 Freq=800, CH1 RK1
1896 13:56:55.871486
1897 13:56:55.872179 DATLAT Default: 0x9
1898 13:56:55.872610 0, 0xFFFF, sum = 0
1899 13:56:55.875451 1, 0xFFFF, sum = 0
1900 13:56:55.876011 2, 0xFFFF, sum = 0
1901 13:56:55.878428 3, 0xFFFF, sum = 0
1902 13:56:55.879006 4, 0xFFFF, sum = 0
1903 13:56:55.882346 5, 0xFFFF, sum = 0
1904 13:56:55.882917 6, 0xFFFF, sum = 0
1905 13:56:55.885336 7, 0xFFFF, sum = 0
1906 13:56:55.885903 8, 0x0, sum = 1
1907 13:56:55.888639 9, 0x0, sum = 2
1908 13:56:55.889241 10, 0x0, sum = 3
1909 13:56:55.891959 11, 0x0, sum = 4
1910 13:56:55.892525 best_step = 9
1911 13:56:55.893016
1912 13:56:55.893373 ==
1913 13:56:55.894654 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 13:56:55.901711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1915 13:56:55.902271 ==
1916 13:56:55.902646 RX Vref Scan: 0
1917 13:56:55.902996
1918 13:56:55.905853 RX Vref 0 -> 0, step: 1
1919 13:56:55.906415
1920 13:56:55.908776 RX Delay -111 -> 252, step: 8
1921 13:56:55.912080 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1922 13:56:55.915631 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1923 13:56:55.918989 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1924 13:56:55.924668 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1925 13:56:55.928375 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1926 13:56:55.932833 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1927 13:56:55.935486 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1928 13:56:55.937865 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1929 13:56:55.944892 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1930 13:56:55.948550 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1931 13:56:55.951623 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1932 13:56:55.955085 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1933 13:56:55.958213 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1934 13:56:55.964518 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1935 13:56:55.968148 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1936 13:56:55.971980 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1937 13:56:55.972548 ==
1938 13:56:55.975260 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 13:56:55.977685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1940 13:56:55.981381 ==
1941 13:56:55.981953 DQS Delay:
1942 13:56:55.982333 DQS0 = 0, DQS1 = 0
1943 13:56:55.984910 DQM Delay:
1944 13:56:55.985466 DQM0 = 82, DQM1 = 72
1945 13:56:55.988115 DQ Delay:
1946 13:56:55.988692 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1947 13:56:55.991584 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1948 13:56:55.994893 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1949 13:56:55.998116 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =80
1950 13:56:55.998670
1951 13:56:56.002251
1952 13:56:56.008920 [DQSOSCAuto] RK1, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1953 13:56:56.011943 CH1 RK1: MR19=606, MR18=3737
1954 13:56:56.018135 CH1_RK1: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1955 13:56:56.018685 [RxdqsGatingPostProcess] freq 800
1956 13:56:56.025321 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1957 13:56:56.028325 Pre-setting of DQS Precalculation
1958 13:56:56.031642 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1959 13:56:56.041708 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1960 13:56:56.048400 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1961 13:56:56.049015
1962 13:56:56.049391
1963 13:56:56.052336 [Calibration Summary] 1600 Mbps
1964 13:56:56.052969 CH 0, Rank 0
1965 13:56:56.054558 SW Impedance : PASS
1966 13:56:56.055021 DUTY Scan : NO K
1967 13:56:56.059058 ZQ Calibration : PASS
1968 13:56:56.061353 Jitter Meter : NO K
1969 13:56:56.061820 CBT Training : PASS
1970 13:56:56.065371 Write leveling : PASS
1971 13:56:56.068061 RX DQS gating : PASS
1972 13:56:56.068623 RX DQ/DQS(RDDQC) : PASS
1973 13:56:56.071743 TX DQ/DQS : PASS
1974 13:56:56.074751 RX DATLAT : PASS
1975 13:56:56.075315 RX DQ/DQS(Engine): PASS
1976 13:56:56.079937 TX OE : NO K
1977 13:56:56.080399 All Pass.
1978 13:56:56.080837
1979 13:56:56.081200 CH 0, Rank 1
1980 13:56:56.081872 SW Impedance : PASS
1981 13:56:56.084863 DUTY Scan : NO K
1982 13:56:56.085324 ZQ Calibration : PASS
1983 13:56:56.087953 Jitter Meter : NO K
1984 13:56:56.091910 CBT Training : PASS
1985 13:56:56.092479 Write leveling : PASS
1986 13:56:56.095243 RX DQS gating : PASS
1987 13:56:56.098433 RX DQ/DQS(RDDQC) : PASS
1988 13:56:56.098892 TX DQ/DQS : PASS
1989 13:56:56.101543 RX DATLAT : PASS
1990 13:56:56.105859 RX DQ/DQS(Engine): PASS
1991 13:56:56.106423 TX OE : NO K
1992 13:56:56.107904 All Pass.
1993 13:56:56.108360
1994 13:56:56.108759 CH 1, Rank 0
1995 13:56:56.111460 SW Impedance : PASS
1996 13:56:56.112025 DUTY Scan : NO K
1997 13:56:56.114788 ZQ Calibration : PASS
1998 13:56:56.117805 Jitter Meter : NO K
1999 13:56:56.118267 CBT Training : PASS
2000 13:56:56.121845 Write leveling : PASS
2001 13:56:56.122410 RX DQS gating : PASS
2002 13:56:56.124401 RX DQ/DQS(RDDQC) : PASS
2003 13:56:56.128205 TX DQ/DQS : PASS
2004 13:56:56.128669 RX DATLAT : PASS
2005 13:56:56.131397 RX DQ/DQS(Engine): PASS
2006 13:56:56.135142 TX OE : NO K
2007 13:56:56.135603 All Pass.
2008 13:56:56.135969
2009 13:56:56.136308 CH 1, Rank 1
2010 13:56:56.138466 SW Impedance : PASS
2011 13:56:56.142014 DUTY Scan : NO K
2012 13:56:56.142581 ZQ Calibration : PASS
2013 13:56:56.145956 Jitter Meter : NO K
2014 13:56:56.148527 CBT Training : PASS
2015 13:56:56.149025 Write leveling : PASS
2016 13:56:56.151411 RX DQS gating : PASS
2017 13:56:56.154550 RX DQ/DQS(RDDQC) : PASS
2018 13:56:56.155008 TX DQ/DQS : PASS
2019 13:56:56.157673 RX DATLAT : PASS
2020 13:56:56.161675 RX DQ/DQS(Engine): PASS
2021 13:56:56.162240 TX OE : NO K
2022 13:56:56.162612 All Pass.
2023 13:56:56.165495
2024 13:56:56.166086 DramC Write-DBI off
2025 13:56:56.168564 PER_BANK_REFRESH: Hybrid Mode
2026 13:56:56.169174 TX_TRACKING: ON
2027 13:56:56.171401 [GetDramInforAfterCalByMRR] Vendor 6.
2028 13:56:56.174834 [GetDramInforAfterCalByMRR] Revision 606.
2029 13:56:56.181501 [GetDramInforAfterCalByMRR] Revision 2 0.
2030 13:56:56.182064 MR0 0x3939
2031 13:56:56.182496 MR8 0x1111
2032 13:56:56.184609 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2033 13:56:56.185105
2034 13:56:56.188601 MR0 0x3939
2035 13:56:56.189224 MR8 0x1111
2036 13:56:56.191752 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2037 13:56:56.192317
2038 13:56:56.201344 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2039 13:56:56.204858 [FAST_K] Save calibration result to emmc
2040 13:56:56.207916 [FAST_K] Save calibration result to emmc
2041 13:56:56.212253 dram_init: config_dvfs: 1
2042 13:56:56.214670 dramc_set_vcore_voltage set vcore to 662500
2043 13:56:56.218002 Read voltage for 1200, 2
2044 13:56:56.218562 Vio18 = 0
2045 13:56:56.218930 Vcore = 662500
2046 13:56:56.221568 Vdram = 0
2047 13:56:56.222026 Vddq = 0
2048 13:56:56.222391 Vmddr = 0
2049 13:56:56.227578 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2050 13:56:56.231189 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2051 13:56:56.234290 MEM_TYPE=3, freq_sel=15
2052 13:56:56.238291 sv_algorithm_assistance_LP4_1600
2053 13:56:56.240884 ============ PULL DRAM RESETB DOWN ============
2054 13:56:56.244422 ========== PULL DRAM RESETB DOWN end =========
2055 13:56:56.251777 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2056 13:56:56.255242 ===================================
2057 13:56:56.255807 LPDDR4 DRAM CONFIGURATION
2058 13:56:56.257614 ===================================
2059 13:56:56.261502 EX_ROW_EN[0] = 0x0
2060 13:56:56.264978 EX_ROW_EN[1] = 0x0
2061 13:56:56.265545 LP4Y_EN = 0x0
2062 13:56:56.267696 WORK_FSP = 0x0
2063 13:56:56.268247 WL = 0x4
2064 13:56:56.271820 RL = 0x4
2065 13:56:56.272373 BL = 0x2
2066 13:56:56.275433 RPST = 0x0
2067 13:56:56.275986 RD_PRE = 0x0
2068 13:56:56.278074 WR_PRE = 0x1
2069 13:56:56.278536 WR_PST = 0x0
2070 13:56:56.281296 DBI_WR = 0x0
2071 13:56:56.281852 DBI_RD = 0x0
2072 13:56:56.284597 OTF = 0x1
2073 13:56:56.287830 ===================================
2074 13:56:56.290704 ===================================
2075 13:56:56.291165 ANA top config
2076 13:56:56.294412 ===================================
2077 13:56:56.298058 DLL_ASYNC_EN = 0
2078 13:56:56.301272 ALL_SLAVE_EN = 0
2079 13:56:56.301834 NEW_RANK_MODE = 1
2080 13:56:56.304539 DLL_IDLE_MODE = 1
2081 13:56:56.307997 LP45_APHY_COMB_EN = 1
2082 13:56:56.310999 TX_ODT_DIS = 1
2083 13:56:56.314447 NEW_8X_MODE = 1
2084 13:56:56.315014 ===================================
2085 13:56:56.318296 ===================================
2086 13:56:56.321094 data_rate = 2400
2087 13:56:56.325112 CKR = 1
2088 13:56:56.327832 DQ_P2S_RATIO = 8
2089 13:56:56.331616 ===================================
2090 13:56:56.334854 CA_P2S_RATIO = 8
2091 13:56:56.337956 DQ_CA_OPEN = 0
2092 13:56:56.340521 DQ_SEMI_OPEN = 0
2093 13:56:56.341084 CA_SEMI_OPEN = 0
2094 13:56:56.345319 CA_FULL_RATE = 0
2095 13:56:56.348361 DQ_CKDIV4_EN = 0
2096 13:56:56.351037 CA_CKDIV4_EN = 0
2097 13:56:56.353900 CA_PREDIV_EN = 0
2098 13:56:56.358341 PH8_DLY = 17
2099 13:56:56.358800 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2100 13:56:56.361019 DQ_AAMCK_DIV = 4
2101 13:56:56.364101 CA_AAMCK_DIV = 4
2102 13:56:56.367580 CA_ADMCK_DIV = 4
2103 13:56:56.370856 DQ_TRACK_CA_EN = 0
2104 13:56:56.374608 CA_PICK = 1200
2105 13:56:56.377059 CA_MCKIO = 1200
2106 13:56:56.377552 MCKIO_SEMI = 0
2107 13:56:56.380875 PLL_FREQ = 2366
2108 13:56:56.384508 DQ_UI_PI_RATIO = 32
2109 13:56:56.387801 CA_UI_PI_RATIO = 0
2110 13:56:56.390367 ===================================
2111 13:56:56.394727 ===================================
2112 13:56:56.397079 memory_type:LPDDR4
2113 13:56:56.397539 GP_NUM : 10
2114 13:56:56.401086 SRAM_EN : 1
2115 13:56:56.404202 MD32_EN : 0
2116 13:56:56.404814 ===================================
2117 13:56:56.407836 [ANA_INIT] >>>>>>>>>>>>>>
2118 13:56:56.411045 <<<<<< [CONFIGURE PHASE]: ANA_TX
2119 13:56:56.413853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2120 13:56:56.417594 ===================================
2121 13:56:56.420568 data_rate = 2400,PCW = 0X5b00
2122 13:56:56.423800 ===================================
2123 13:56:56.426820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2124 13:56:56.433662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2125 13:56:56.437162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2126 13:56:56.444255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2127 13:56:56.447852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2128 13:56:56.451812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2129 13:56:56.452374 [ANA_INIT] flow start
2130 13:56:56.453827 [ANA_INIT] PLL >>>>>>>>
2131 13:56:56.456973 [ANA_INIT] PLL <<<<<<<<
2132 13:56:56.457430 [ANA_INIT] MIDPI >>>>>>>>
2133 13:56:56.460404 [ANA_INIT] MIDPI <<<<<<<<
2134 13:56:56.463496 [ANA_INIT] DLL >>>>>>>>
2135 13:56:56.463953 [ANA_INIT] DLL <<<<<<<<
2136 13:56:56.468438 [ANA_INIT] flow end
2137 13:56:56.473223 ============ LP4 DIFF to SE enter ============
2138 13:56:56.477268 ============ LP4 DIFF to SE exit ============
2139 13:56:56.477837 [ANA_INIT] <<<<<<<<<<<<<
2140 13:56:56.481072 [Flow] Enable top DCM control >>>>>
2141 13:56:56.483881 [Flow] Enable top DCM control <<<<<
2142 13:56:56.486998 Enable DLL master slave shuffle
2143 13:56:56.494064 ==============================================================
2144 13:56:56.494626 Gating Mode config
2145 13:56:56.501070 ==============================================================
2146 13:56:56.503427 Config description:
2147 13:56:56.510927 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2148 13:56:56.517208 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2149 13:56:56.523684 SELPH_MODE 0: By rank 1: By Phase
2150 13:56:56.530091 ==============================================================
2151 13:56:56.530557 GAT_TRACK_EN = 1
2152 13:56:56.533641 RX_GATING_MODE = 2
2153 13:56:56.536687 RX_GATING_TRACK_MODE = 2
2154 13:56:56.540439 SELPH_MODE = 1
2155 13:56:56.543480 PICG_EARLY_EN = 1
2156 13:56:56.546996 VALID_LAT_VALUE = 1
2157 13:56:56.553491 ==============================================================
2158 13:56:56.557290 Enter into Gating configuration >>>>
2159 13:56:56.560033 Exit from Gating configuration <<<<
2160 13:56:56.563581 Enter into DVFS_PRE_config >>>>>
2161 13:56:56.575271 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2162 13:56:56.577344 Exit from DVFS_PRE_config <<<<<
2163 13:56:56.580206 Enter into PICG configuration >>>>
2164 13:56:56.584080 Exit from PICG configuration <<<<
2165 13:56:56.586745 [RX_INPUT] configuration >>>>>
2166 13:56:56.587210 [RX_INPUT] configuration <<<<<
2167 13:56:56.593380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2168 13:56:56.600196 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2169 13:56:56.603788 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2170 13:56:56.610209 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2171 13:56:56.616969 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2172 13:56:56.623460 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2173 13:56:56.627126 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2174 13:56:56.630460 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2175 13:56:56.636616 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2176 13:56:56.640253 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2177 13:56:56.643661 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2178 13:56:56.647471 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2179 13:56:56.650056 ===================================
2180 13:56:56.653311 LPDDR4 DRAM CONFIGURATION
2181 13:56:56.657263 ===================================
2182 13:56:56.661036 EX_ROW_EN[0] = 0x0
2183 13:56:56.661493 EX_ROW_EN[1] = 0x0
2184 13:56:56.663212 LP4Y_EN = 0x0
2185 13:56:56.663668 WORK_FSP = 0x0
2186 13:56:56.667113 WL = 0x4
2187 13:56:56.667572 RL = 0x4
2188 13:56:56.670161 BL = 0x2
2189 13:56:56.670618 RPST = 0x0
2190 13:56:56.673171 RD_PRE = 0x0
2191 13:56:56.673730 WR_PRE = 0x1
2192 13:56:56.677175 WR_PST = 0x0
2193 13:56:56.680248 DBI_WR = 0x0
2194 13:56:56.680861 DBI_RD = 0x0
2195 13:56:56.684078 OTF = 0x1
2196 13:56:56.687093 ===================================
2197 13:56:56.690553 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2198 13:56:56.693583 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2199 13:56:56.696669 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2200 13:56:56.700459 ===================================
2201 13:56:56.703453 LPDDR4 DRAM CONFIGURATION
2202 13:56:56.707048 ===================================
2203 13:56:56.710078 EX_ROW_EN[0] = 0x10
2204 13:56:56.710641 EX_ROW_EN[1] = 0x0
2205 13:56:56.713425 LP4Y_EN = 0x0
2206 13:56:56.713985 WORK_FSP = 0x0
2207 13:56:56.716687 WL = 0x4
2208 13:56:56.717281 RL = 0x4
2209 13:56:56.719940 BL = 0x2
2210 13:56:56.720395 RPST = 0x0
2211 13:56:56.723635 RD_PRE = 0x0
2212 13:56:56.724211 WR_PRE = 0x1
2213 13:56:56.726108 WR_PST = 0x0
2214 13:56:56.726566 DBI_WR = 0x0
2215 13:56:56.730019 DBI_RD = 0x0
2216 13:56:56.730477 OTF = 0x1
2217 13:56:56.733424 ===================================
2218 13:56:56.739690 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2219 13:56:56.740276 ==
2220 13:56:56.742869 Dram Type= 6, Freq= 0, CH_0, rank 0
2221 13:56:56.749900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2222 13:56:56.750466 ==
2223 13:56:56.750834 [Duty_Offset_Calibration]
2224 13:56:56.753006 B0:0 B1:2 CA:1
2225 13:56:56.753465
2226 13:56:56.756109 [DutyScan_Calibration_Flow] k_type=0
2227 13:56:56.765745
2228 13:56:56.766201 ==CLK 0==
2229 13:56:56.768869 Final CLK duty delay cell = 0
2230 13:56:56.771915 [0] MAX Duty = 5093%(X100), DQS PI = 12
2231 13:56:56.775440 [0] MIN Duty = 4938%(X100), DQS PI = 52
2232 13:56:56.776000 [0] AVG Duty = 5015%(X100)
2233 13:56:56.778793
2234 13:56:56.782432 CH0 CLK Duty spec in!! Max-Min= 155%
2235 13:56:56.785610 [DutyScan_Calibration_Flow] ====Done====
2236 13:56:56.786171
2237 13:56:56.788613 [DutyScan_Calibration_Flow] k_type=1
2238 13:56:56.804520
2239 13:56:56.805104 ==DQS 0 ==
2240 13:56:56.808302 Final DQS duty delay cell = 0
2241 13:56:56.812137 [0] MAX Duty = 5125%(X100), DQS PI = 30
2242 13:56:56.814535 [0] MIN Duty = 5031%(X100), DQS PI = 6
2243 13:56:56.815099 [0] AVG Duty = 5078%(X100)
2244 13:56:56.818089
2245 13:56:56.818649 ==DQS 1 ==
2246 13:56:56.821429 Final DQS duty delay cell = 0
2247 13:56:56.824676 [0] MAX Duty = 5031%(X100), DQS PI = 50
2248 13:56:56.828665 [0] MIN Duty = 4906%(X100), DQS PI = 16
2249 13:56:56.830972 [0] AVG Duty = 4968%(X100)
2250 13:56:56.831437
2251 13:56:56.834449 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2252 13:56:56.834915
2253 13:56:56.837925 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2254 13:56:56.841364 [DutyScan_Calibration_Flow] ====Done====
2255 13:56:56.841828
2256 13:56:56.844434 [DutyScan_Calibration_Flow] k_type=3
2257 13:56:56.861160
2258 13:56:56.861733 ==DQM 0 ==
2259 13:56:56.864690 Final DQM duty delay cell = 0
2260 13:56:56.867552 [0] MAX Duty = 5156%(X100), DQS PI = 20
2261 13:56:56.870740 [0] MIN Duty = 5000%(X100), DQS PI = 40
2262 13:56:56.874616 [0] AVG Duty = 5078%(X100)
2263 13:56:56.875188
2264 13:56:56.875560 ==DQM 1 ==
2265 13:56:56.877402 Final DQM duty delay cell = 0
2266 13:56:56.880681 [0] MAX Duty = 5000%(X100), DQS PI = 56
2267 13:56:56.885502 [0] MIN Duty = 4844%(X100), DQS PI = 0
2268 13:56:56.886066 [0] AVG Duty = 4922%(X100)
2269 13:56:56.887544
2270 13:56:56.891760 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2271 13:56:56.892326
2272 13:56:56.894899 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2273 13:56:56.898284 [DutyScan_Calibration_Flow] ====Done====
2274 13:56:56.898842
2275 13:56:56.901092 [DutyScan_Calibration_Flow] k_type=2
2276 13:56:56.916528
2277 13:56:56.917138 ==DQ 0 ==
2278 13:56:56.919993 Final DQ duty delay cell = -4
2279 13:56:56.923224 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2280 13:56:56.926106 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2281 13:56:56.929006 [-4] AVG Duty = 4937%(X100)
2282 13:56:56.929468
2283 13:56:56.929840 ==DQ 1 ==
2284 13:56:56.932374 Final DQ duty delay cell = -4
2285 13:56:56.935839 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2286 13:56:56.939775 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2287 13:56:56.942140 [-4] AVG Duty = 4969%(X100)
2288 13:56:56.942606
2289 13:56:56.945324 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2290 13:56:56.945784
2291 13:56:56.949800 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2292 13:56:56.952391 [DutyScan_Calibration_Flow] ====Done====
2293 13:56:56.952990 ==
2294 13:56:56.955730 Dram Type= 6, Freq= 0, CH_1, rank 0
2295 13:56:56.959677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2296 13:56:56.960239 ==
2297 13:56:56.962315 [Duty_Offset_Calibration]
2298 13:56:56.962821 B0:0 B1:4 CA:-5
2299 13:56:56.963277
2300 13:56:56.965774 [DutyScan_Calibration_Flow] k_type=0
2301 13:56:56.976652
2302 13:56:56.977261 ==CLK 0==
2303 13:56:56.979744 Final CLK duty delay cell = 0
2304 13:56:56.983545 [0] MAX Duty = 5094%(X100), DQS PI = 24
2305 13:56:56.986721 [0] MIN Duty = 4875%(X100), DQS PI = 46
2306 13:56:56.987289 [0] AVG Duty = 4984%(X100)
2307 13:56:56.987658
2308 13:56:56.990127 CH1 CLK Duty spec in!! Max-Min= 219%
2309 13:56:56.996650 [DutyScan_Calibration_Flow] ====Done====
2310 13:56:56.997260
2311 13:56:56.999814 [DutyScan_Calibration_Flow] k_type=1
2312 13:56:57.014933
2313 13:56:57.015488 ==DQS 0 ==
2314 13:56:57.018197 Final DQS duty delay cell = 0
2315 13:56:57.022620 [0] MAX Duty = 5125%(X100), DQS PI = 16
2316 13:56:57.025740 [0] MIN Duty = 4875%(X100), DQS PI = 40
2317 13:56:57.026303 [0] AVG Duty = 5000%(X100)
2318 13:56:57.027803
2319 13:56:57.028256 ==DQS 1 ==
2320 13:56:57.031738 Final DQS duty delay cell = -4
2321 13:56:57.035363 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2322 13:56:57.039606 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2323 13:56:57.041527 [-4] AVG Duty = 4953%(X100)
2324 13:56:57.041986
2325 13:56:57.044777 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2326 13:56:57.045340
2327 13:56:57.048856 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2328 13:56:57.051786 [DutyScan_Calibration_Flow] ====Done====
2329 13:56:57.052347
2330 13:56:57.055386 [DutyScan_Calibration_Flow] k_type=3
2331 13:56:57.070047
2332 13:56:57.070606 ==DQM 0 ==
2333 13:56:57.073567 Final DQM duty delay cell = -4
2334 13:56:57.076847 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2335 13:56:57.079911 [-4] MIN Duty = 4844%(X100), DQS PI = 38
2336 13:56:57.083217 [-4] AVG Duty = 4969%(X100)
2337 13:56:57.083789
2338 13:56:57.084158 ==DQM 1 ==
2339 13:56:57.087631 Final DQM duty delay cell = -4
2340 13:56:57.089755 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2341 13:56:57.094032 [-4] MIN Duty = 4907%(X100), DQS PI = 58
2342 13:56:57.097383 [-4] AVG Duty = 4984%(X100)
2343 13:56:57.097950
2344 13:56:57.099716 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2345 13:56:57.100176
2346 13:56:57.103418 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2347 13:56:57.106531 [DutyScan_Calibration_Flow] ====Done====
2348 13:56:57.106996
2349 13:56:57.110308 [DutyScan_Calibration_Flow] k_type=2
2350 13:56:57.129036
2351 13:56:57.129762 ==DQ 0 ==
2352 13:56:57.130524 Final DQ duty delay cell = 0
2353 13:56:57.135204 [0] MAX Duty = 5062%(X100), DQS PI = 0
2354 13:56:57.136812 [0] MIN Duty = 4969%(X100), DQS PI = 42
2355 13:56:57.137248 [0] AVG Duty = 5015%(X100)
2356 13:56:57.140503
2357 13:56:57.141132 ==DQ 1 ==
2358 13:56:57.144066 Final DQ duty delay cell = 0
2359 13:56:57.147464 [0] MAX Duty = 5000%(X100), DQS PI = 8
2360 13:56:57.150599 [0] MIN Duty = 4875%(X100), DQS PI = 30
2361 13:56:57.151059 [0] AVG Duty = 4937%(X100)
2362 13:56:57.151422
2363 13:56:57.154068 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2364 13:56:57.154523
2365 13:56:57.157215 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2366 13:56:57.163428 [DutyScan_Calibration_Flow] ====Done====
2367 13:56:57.167083 nWR fixed to 30
2368 13:56:57.167721 [ModeRegInit_LP4] CH0 RK0
2369 13:56:57.170909 [ModeRegInit_LP4] CH0 RK1
2370 13:56:57.173795 [ModeRegInit_LP4] CH1 RK0
2371 13:56:57.174251 [ModeRegInit_LP4] CH1 RK1
2372 13:56:57.177317 match AC timing 6
2373 13:56:57.180900 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2374 13:56:57.183889 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2375 13:56:57.190877 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2376 13:56:57.193176 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2377 13:56:57.200115 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2378 13:56:57.200654 ==
2379 13:56:57.204106 Dram Type= 6, Freq= 0, CH_0, rank 0
2380 13:56:57.206783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2381 13:56:57.207244 ==
2382 13:56:57.213179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2383 13:56:57.220010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2384 13:56:57.226730 [CA 0] Center 39 (9~70) winsize 62
2385 13:56:57.230970 [CA 1] Center 39 (9~70) winsize 62
2386 13:56:57.233931 [CA 2] Center 36 (5~67) winsize 63
2387 13:56:57.237048 [CA 3] Center 35 (5~66) winsize 62
2388 13:56:57.240540 [CA 4] Center 34 (3~65) winsize 63
2389 13:56:57.244558 [CA 5] Center 33 (3~64) winsize 62
2390 13:56:57.245173
2391 13:56:57.247125 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2392 13:56:57.247680
2393 13:56:57.249854 [CATrainingPosCal] consider 1 rank data
2394 13:56:57.253201 u2DelayCellTimex100 = 270/100 ps
2395 13:56:57.256519 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2396 13:56:57.263152 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2397 13:56:57.266692 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2398 13:56:57.270081 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2399 13:56:57.273210 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2400 13:56:57.276592 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2401 13:56:57.277200
2402 13:56:57.280094 CA PerBit enable=1, Macro0, CA PI delay=33
2403 13:56:57.280650
2404 13:56:57.282978 [CBTSetCACLKResult] CA Dly = 33
2405 13:56:57.283432 CS Dly: 7 (0~38)
2406 13:56:57.286684 ==
2407 13:56:57.290057 Dram Type= 6, Freq= 0, CH_0, rank 1
2408 13:56:57.293529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2409 13:56:57.294087 ==
2410 13:56:57.296942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2411 13:56:57.303317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2412 13:56:57.312689 [CA 0] Center 39 (8~70) winsize 63
2413 13:56:57.315808 [CA 1] Center 39 (8~70) winsize 63
2414 13:56:57.320417 [CA 2] Center 36 (5~67) winsize 63
2415 13:56:57.321838 [CA 3] Center 35 (4~66) winsize 63
2416 13:56:57.325599 [CA 4] Center 33 (3~64) winsize 62
2417 13:56:57.328780 [CA 5] Center 34 (3~65) winsize 63
2418 13:56:57.329391
2419 13:56:57.332409 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2420 13:56:57.333074
2421 13:56:57.335867 [CATrainingPosCal] consider 2 rank data
2422 13:56:57.339273 u2DelayCellTimex100 = 270/100 ps
2423 13:56:57.342652 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2424 13:56:57.349191 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2425 13:56:57.352383 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2426 13:56:57.356046 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2427 13:56:57.359187 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2428 13:56:57.363789 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2429 13:56:57.364355
2430 13:56:57.365391 CA PerBit enable=1, Macro0, CA PI delay=33
2431 13:56:57.365848
2432 13:56:57.368552 [CBTSetCACLKResult] CA Dly = 33
2433 13:56:57.372412 CS Dly: 7 (0~39)
2434 13:56:57.373045
2435 13:56:57.375038 ----->DramcWriteLeveling(PI) begin...
2436 13:56:57.375603 ==
2437 13:56:57.378197 Dram Type= 6, Freq= 0, CH_0, rank 0
2438 13:56:57.381794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2439 13:56:57.382364 ==
2440 13:56:57.385341 Write leveling (Byte 0): 27 => 27
2441 13:56:57.388434 Write leveling (Byte 1): 27 => 27
2442 13:56:57.391986 DramcWriteLeveling(PI) end<-----
2443 13:56:57.392578
2444 13:56:57.393060 ==
2445 13:56:57.395075 Dram Type= 6, Freq= 0, CH_0, rank 0
2446 13:56:57.398173 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2447 13:56:57.398740 ==
2448 13:56:57.401467 [Gating] SW mode calibration
2449 13:56:57.408656 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2450 13:56:57.415102 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2451 13:56:57.418273 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2452 13:56:57.421623 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2453 13:56:57.427979 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2454 13:56:57.431562 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2455 13:56:57.435204 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2456 13:56:57.442350 0 11 20 | B1->B0 | 2f2f 2c2c | 0 0 | (0 1) (1 0)
2457 13:56:57.444699 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2458 13:56:57.447719 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2459 13:56:57.454693 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2460 13:56:57.457357 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2461 13:56:57.461576 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2462 13:56:57.470252 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2463 13:56:57.472927 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 13:56:57.475045 0 12 20 | B1->B0 | 3535 3f3f | 0 1 | (0 0) (0 0)
2465 13:56:57.481115 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2466 13:56:57.484758 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2467 13:56:57.487798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2468 13:56:57.491348 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2469 13:56:57.498059 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2470 13:56:57.501800 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 13:56:57.504823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2472 13:56:57.511717 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2473 13:56:57.515143 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2474 13:56:57.518238 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 13:56:57.525169 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 13:56:57.527979 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 13:56:57.531991 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 13:56:57.537710 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 13:56:57.541520 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 13:56:57.544737 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 13:56:57.552058 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 13:56:57.555024 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 13:56:57.558358 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 13:56:57.564821 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 13:56:57.568662 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 13:56:57.571521 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 13:56:57.580998 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 13:56:57.583903 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2489 13:56:57.584951 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2490 13:56:57.587928 Total UI for P1: 0, mck2ui 16
2491 13:56:57.591319 best dqsien dly found for B0: ( 0, 15, 20)
2492 13:56:57.595520 Total UI for P1: 0, mck2ui 16
2493 13:56:57.598110 best dqsien dly found for B1: ( 0, 15, 20)
2494 13:56:57.602130 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2495 13:56:57.604645 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2496 13:56:57.605137
2497 13:56:57.607714 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2498 13:56:57.615094 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2499 13:56:57.615682 [Gating] SW calibration Done
2500 13:56:57.616078 ==
2501 13:56:57.618506 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 13:56:57.625234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2503 13:56:57.625814 ==
2504 13:56:57.626186 RX Vref Scan: 0
2505 13:56:57.626531
2506 13:56:57.627942 RX Vref 0 -> 0, step: 1
2507 13:56:57.628409
2508 13:56:57.631097 RX Delay -40 -> 252, step: 8
2509 13:56:57.634560 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2510 13:56:57.638376 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2511 13:56:57.641100 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2512 13:56:57.645196 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2513 13:56:57.651376 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2514 13:56:57.654695 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2515 13:56:57.658012 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2516 13:56:57.661301 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2517 13:56:57.664906 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2518 13:56:57.671506 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2519 13:56:57.675292 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2520 13:56:57.678170 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2521 13:56:57.681755 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2522 13:56:57.685659 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2523 13:56:57.691389 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2524 13:56:57.696239 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2525 13:56:57.696322 ==
2526 13:56:57.697859 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 13:56:57.700743 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2528 13:56:57.700847 ==
2529 13:56:57.704607 DQS Delay:
2530 13:56:57.704738 DQS0 = 0, DQS1 = 0
2531 13:56:57.704811 DQM Delay:
2532 13:56:57.707611 DQM0 = 115, DQM1 = 106
2533 13:56:57.707734 DQ Delay:
2534 13:56:57.711095 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2535 13:56:57.714395 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2536 13:56:57.717577 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2537 13:56:57.724994 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2538 13:56:57.725167
2539 13:56:57.725264
2540 13:56:57.725359 ==
2541 13:56:57.728030 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 13:56:57.731268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2543 13:56:57.731487 ==
2544 13:56:57.731664
2545 13:56:57.731820
2546 13:56:57.734390 TX Vref Scan disable
2547 13:56:57.734551 == TX Byte 0 ==
2548 13:56:57.742995 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2549 13:56:57.744686 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2550 13:56:57.744962 == TX Byte 1 ==
2551 13:56:57.750985 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2552 13:56:57.754952 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2553 13:56:57.755359 ==
2554 13:56:57.758342 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 13:56:57.761258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2556 13:56:57.761748 ==
2557 13:56:57.774531 TX Vref=22, minBit 10, minWin=24, winSum=420
2558 13:56:57.777729 TX Vref=24, minBit 7, minWin=26, winSum=431
2559 13:56:57.780012 TX Vref=26, minBit 10, minWin=25, winSum=430
2560 13:56:57.783998 TX Vref=28, minBit 9, minWin=26, winSum=436
2561 13:56:57.787598 TX Vref=30, minBit 5, minWin=26, winSum=431
2562 13:56:57.794674 TX Vref=32, minBit 10, minWin=26, winSum=436
2563 13:56:57.796794 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 28
2564 13:56:57.797379
2565 13:56:57.800573 Final TX Range 1 Vref 28
2566 13:56:57.801205
2567 13:56:57.801806 ==
2568 13:56:57.804579 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 13:56:57.807571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2570 13:56:57.808212 ==
2571 13:56:57.812122
2572 13:56:57.812694
2573 13:56:57.813237 TX Vref Scan disable
2574 13:56:57.814065 == TX Byte 0 ==
2575 13:56:57.816561 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2576 13:56:57.819928 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2577 13:56:57.823629 == TX Byte 1 ==
2578 13:56:57.827583 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2579 13:56:57.829969 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2580 13:56:57.833681
2581 13:56:57.834271 [DATLAT]
2582 13:56:57.834672 Freq=1200, CH0 RK0
2583 13:56:57.835217
2584 13:56:57.836959 DATLAT Default: 0xd
2585 13:56:57.837424 0, 0xFFFF, sum = 0
2586 13:56:57.840388 1, 0xFFFF, sum = 0
2587 13:56:57.840899 2, 0xFFFF, sum = 0
2588 13:56:57.844139 3, 0xFFFF, sum = 0
2589 13:56:57.844744 4, 0xFFFF, sum = 0
2590 13:56:57.846439 5, 0xFFFF, sum = 0
2591 13:56:57.852031 6, 0xFFFF, sum = 0
2592 13:56:57.852631 7, 0xFFFF, sum = 0
2593 13:56:57.853457 8, 0xFFFF, sum = 0
2594 13:56:57.853875 9, 0xFFFF, sum = 0
2595 13:56:57.856523 10, 0xFFFF, sum = 0
2596 13:56:57.857092 11, 0x0, sum = 1
2597 13:56:57.860676 12, 0x0, sum = 2
2598 13:56:57.861196 13, 0x0, sum = 3
2599 13:56:57.861570 14, 0x0, sum = 4
2600 13:56:57.863392 best_step = 12
2601 13:56:57.863849
2602 13:56:57.864211 ==
2603 13:56:57.867518 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 13:56:57.870333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2605 13:56:57.870800 ==
2606 13:56:57.873660 RX Vref Scan: 1
2607 13:56:57.874160
2608 13:56:57.876876 Set Vref Range= 32 -> 127
2609 13:56:57.877340
2610 13:56:57.877706 RX Vref 32 -> 127, step: 1
2611 13:56:57.878054
2612 13:56:57.880015 RX Delay -21 -> 252, step: 4
2613 13:56:57.880538
2614 13:56:57.883657 Set Vref, RX VrefLevel [Byte0]: 32
2615 13:56:57.886477 [Byte1]: 32
2616 13:56:57.890292
2617 13:56:57.890849 Set Vref, RX VrefLevel [Byte0]: 33
2618 13:56:57.893501 [Byte1]: 33
2619 13:56:57.898262
2620 13:56:57.898816 Set Vref, RX VrefLevel [Byte0]: 34
2621 13:56:57.902142 [Byte1]: 34
2622 13:56:57.907414
2623 13:56:57.907970 Set Vref, RX VrefLevel [Byte0]: 35
2624 13:56:57.909558 [Byte1]: 35
2625 13:56:57.914069
2626 13:56:57.914712 Set Vref, RX VrefLevel [Byte0]: 36
2627 13:56:57.917356 [Byte1]: 36
2628 13:56:57.921922
2629 13:56:57.922494 Set Vref, RX VrefLevel [Byte0]: 37
2630 13:56:57.925548 [Byte1]: 37
2631 13:56:57.931424
2632 13:56:57.931882 Set Vref, RX VrefLevel [Byte0]: 38
2633 13:56:57.933022 [Byte1]: 38
2634 13:56:57.937409
2635 13:56:57.937868 Set Vref, RX VrefLevel [Byte0]: 39
2636 13:56:57.941243 [Byte1]: 39
2637 13:56:57.945516
2638 13:56:57.946071 Set Vref, RX VrefLevel [Byte0]: 40
2639 13:56:57.949135 [Byte1]: 40
2640 13:56:57.953510
2641 13:56:57.954075 Set Vref, RX VrefLevel [Byte0]: 41
2642 13:56:57.956967 [Byte1]: 41
2643 13:56:57.961295
2644 13:56:57.961852 Set Vref, RX VrefLevel [Byte0]: 42
2645 13:56:57.964656 [Byte1]: 42
2646 13:56:57.969653
2647 13:56:57.970115 Set Vref, RX VrefLevel [Byte0]: 43
2648 13:56:57.972921 [Byte1]: 43
2649 13:56:57.977641
2650 13:56:57.978193 Set Vref, RX VrefLevel [Byte0]: 44
2651 13:56:57.981713 [Byte1]: 44
2652 13:56:57.985321
2653 13:56:57.985876 Set Vref, RX VrefLevel [Byte0]: 45
2654 13:56:57.989091 [Byte1]: 45
2655 13:56:57.993768
2656 13:56:57.994322 Set Vref, RX VrefLevel [Byte0]: 46
2657 13:56:57.996475 [Byte1]: 46
2658 13:56:58.001621
2659 13:56:58.002181 Set Vref, RX VrefLevel [Byte0]: 47
2660 13:56:58.005492 [Byte1]: 47
2661 13:56:58.009286
2662 13:56:58.009844 Set Vref, RX VrefLevel [Byte0]: 48
2663 13:56:58.012223 [Byte1]: 48
2664 13:56:58.017336
2665 13:56:58.017894 Set Vref, RX VrefLevel [Byte0]: 49
2666 13:56:58.020271 [Byte1]: 49
2667 13:56:58.025576
2668 13:56:58.026140 Set Vref, RX VrefLevel [Byte0]: 50
2669 13:56:58.028172 [Byte1]: 50
2670 13:56:58.033589
2671 13:56:58.034153 Set Vref, RX VrefLevel [Byte0]: 51
2672 13:56:58.037847 [Byte1]: 51
2673 13:56:58.041461
2674 13:56:58.041941 Set Vref, RX VrefLevel [Byte0]: 52
2675 13:56:58.044127 [Byte1]: 52
2676 13:56:58.048600
2677 13:56:58.049219 Set Vref, RX VrefLevel [Byte0]: 53
2678 13:56:58.055084 [Byte1]: 53
2679 13:56:58.055648
2680 13:56:58.059098 Set Vref, RX VrefLevel [Byte0]: 54
2681 13:56:58.061966 [Byte1]: 54
2682 13:56:58.062451
2683 13:56:58.064963 Set Vref, RX VrefLevel [Byte0]: 55
2684 13:56:58.068134 [Byte1]: 55
2685 13:56:58.072567
2686 13:56:58.073194 Set Vref, RX VrefLevel [Byte0]: 56
2687 13:56:58.075586 [Byte1]: 56
2688 13:56:58.079954
2689 13:56:58.080417 Set Vref, RX VrefLevel [Byte0]: 57
2690 13:56:58.084695 [Byte1]: 57
2691 13:56:58.089283
2692 13:56:58.089835 Set Vref, RX VrefLevel [Byte0]: 58
2693 13:56:58.092433 [Byte1]: 58
2694 13:56:58.096110
2695 13:56:58.096666 Set Vref, RX VrefLevel [Byte0]: 59
2696 13:56:58.100095 [Byte1]: 59
2697 13:56:58.104148
2698 13:56:58.104703 Set Vref, RX VrefLevel [Byte0]: 60
2699 13:56:58.107679 [Byte1]: 60
2700 13:56:58.112308
2701 13:56:58.112916 Set Vref, RX VrefLevel [Byte0]: 61
2702 13:56:58.116034 [Byte1]: 61
2703 13:56:58.120128
2704 13:56:58.120689 Set Vref, RX VrefLevel [Byte0]: 62
2705 13:56:58.124250 [Byte1]: 62
2706 13:56:58.128556
2707 13:56:58.129177 Set Vref, RX VrefLevel [Byte0]: 63
2708 13:56:58.134456 [Byte1]: 63
2709 13:56:58.135023
2710 13:56:58.137931 Set Vref, RX VrefLevel [Byte0]: 64
2711 13:56:58.141354 [Byte1]: 64
2712 13:56:58.141845
2713 13:56:58.144415 Set Vref, RX VrefLevel [Byte0]: 65
2714 13:56:58.148108 [Byte1]: 65
2715 13:56:58.151636
2716 13:56:58.152123 Set Vref, RX VrefLevel [Byte0]: 66
2717 13:56:58.156793 [Byte1]: 66
2718 13:56:58.159294
2719 13:56:58.159754 Set Vref, RX VrefLevel [Byte0]: 67
2720 13:56:58.163150 [Byte1]: 67
2721 13:56:58.168188
2722 13:56:58.168800 Final RX Vref Byte 0 = 47 to rank0
2723 13:56:58.171415 Final RX Vref Byte 1 = 49 to rank0
2724 13:56:58.173922 Final RX Vref Byte 0 = 47 to rank1
2725 13:56:58.177378 Final RX Vref Byte 1 = 49 to rank1==
2726 13:56:58.180508 Dram Type= 6, Freq= 0, CH_0, rank 0
2727 13:56:58.187291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2728 13:56:58.187851 ==
2729 13:56:58.188278 DQS Delay:
2730 13:56:58.188623 DQS0 = 0, DQS1 = 0
2731 13:56:58.191130 DQM Delay:
2732 13:56:58.191686 DQM0 = 114, DQM1 = 105
2733 13:56:58.194429 DQ Delay:
2734 13:56:58.198110 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2735 13:56:58.200788 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2736 13:56:58.204125 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2737 13:56:58.207304 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2738 13:56:58.207864
2739 13:56:58.208234
2740 13:56:58.213577 [DQSOSCAuto] RK0, (LSB)MR18= 0x404, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2741 13:56:58.217714 CH0 RK0: MR19=404, MR18=404
2742 13:56:58.224332 CH0_RK0: MR19=0x404, MR18=0x404, DQSOSC=408, MR23=63, INC=39, DEC=26
2743 13:56:58.224948
2744 13:56:58.227323 ----->DramcWriteLeveling(PI) begin...
2745 13:56:58.227893 ==
2746 13:56:58.230943 Dram Type= 6, Freq= 0, CH_0, rank 1
2747 13:56:58.234232 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2748 13:56:58.234797 ==
2749 13:56:58.237324 Write leveling (Byte 0): 27 => 27
2750 13:56:58.240390 Write leveling (Byte 1): 24 => 24
2751 13:56:58.244283 DramcWriteLeveling(PI) end<-----
2752 13:56:58.244906
2753 13:56:58.245287 ==
2754 13:56:58.247135 Dram Type= 6, Freq= 0, CH_0, rank 1
2755 13:56:58.250682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2756 13:56:58.253569 ==
2757 13:56:58.254039 [Gating] SW mode calibration
2758 13:56:58.263701 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2759 13:56:58.267204 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2760 13:56:58.270824 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2761 13:56:58.277708 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2762 13:56:58.280405 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2763 13:56:58.283588 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2764 13:56:58.291037 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2765 13:56:58.293593 0 11 20 | B1->B0 | 2e2e 2424 | 1 1 | (1 0) (1 0)
2766 13:56:58.297547 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2767 13:56:58.304124 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2768 13:56:58.308108 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2769 13:56:58.310880 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2770 13:56:58.317450 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2771 13:56:58.320078 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2772 13:56:58.323998 0 12 16 | B1->B0 | 2424 3534 | 0 1 | (1 1) (0 0)
2773 13:56:58.330043 0 12 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2774 13:56:58.334594 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2775 13:56:58.337735 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2776 13:56:58.343798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 13:56:58.347701 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2778 13:56:58.350754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2779 13:56:58.354548 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2780 13:56:58.360856 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2781 13:56:58.364568 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2782 13:56:58.367456 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2783 13:56:58.374242 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 13:56:58.378276 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 13:56:58.380822 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 13:56:58.386819 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 13:56:58.391190 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 13:56:58.393427 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 13:56:58.400119 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 13:56:58.403634 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 13:56:58.407225 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 13:56:58.413925 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 13:56:58.417477 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 13:56:58.420536 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 13:56:58.427616 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2796 13:56:58.430631 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2797 13:56:58.433949 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2798 13:56:58.440415 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2799 13:56:58.440930 Total UI for P1: 0, mck2ui 16
2800 13:56:58.443728 best dqsien dly found for B0: ( 0, 15, 18)
2801 13:56:58.447204 Total UI for P1: 0, mck2ui 16
2802 13:56:58.451026 best dqsien dly found for B1: ( 0, 15, 18)
2803 13:56:58.453547 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2804 13:56:58.461066 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2805 13:56:58.461620
2806 13:56:58.463827 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2807 13:56:58.467786 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2808 13:56:58.470903 [Gating] SW calibration Done
2809 13:56:58.471363 ==
2810 13:56:58.473751 Dram Type= 6, Freq= 0, CH_0, rank 1
2811 13:56:58.477854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2812 13:56:58.478423 ==
2813 13:56:58.478793 RX Vref Scan: 0
2814 13:56:58.480638
2815 13:56:58.481245 RX Vref 0 -> 0, step: 1
2816 13:56:58.481619
2817 13:56:58.484165 RX Delay -40 -> 252, step: 8
2818 13:56:58.487811 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2819 13:56:58.491420 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2820 13:56:58.498170 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2821 13:56:58.501053 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2822 13:56:58.505325 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2823 13:56:58.507399 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2824 13:56:58.510562 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2825 13:56:58.517447 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2826 13:56:58.520666 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2827 13:56:58.523941 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2828 13:56:58.527536 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2829 13:56:58.530300 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2830 13:56:58.537524 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2831 13:56:58.540386 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2832 13:56:58.544069 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2833 13:56:58.547325 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2834 13:56:58.547890 ==
2835 13:56:58.550944 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 13:56:58.553633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2837 13:56:58.557245 ==
2838 13:56:58.557811 DQS Delay:
2839 13:56:58.558181 DQS0 = 0, DQS1 = 0
2840 13:56:58.560764 DQM Delay:
2841 13:56:58.561337 DQM0 = 115, DQM1 = 107
2842 13:56:58.564287 DQ Delay:
2843 13:56:58.567247 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2844 13:56:58.571139 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2845 13:56:58.573670 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2846 13:56:58.577562 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2847 13:56:58.578126
2848 13:56:58.578491
2849 13:56:58.578827 ==
2850 13:56:58.581276 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 13:56:58.583957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2852 13:56:58.584524 ==
2853 13:56:58.584961
2854 13:56:58.585301
2855 13:56:58.587412 TX Vref Scan disable
2856 13:56:58.590421 == TX Byte 0 ==
2857 13:56:58.594026 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2858 13:56:58.597627 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2859 13:56:58.600809 == TX Byte 1 ==
2860 13:56:58.604223 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2861 13:56:58.607408 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2862 13:56:58.607970 ==
2863 13:56:58.611877 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 13:56:58.617148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2865 13:56:58.617699 ==
2866 13:56:58.627122 TX Vref=22, minBit 8, minWin=25, winSum=417
2867 13:56:58.630531 TX Vref=24, minBit 9, minWin=25, winSum=421
2868 13:56:58.634319 TX Vref=26, minBit 1, minWin=26, winSum=428
2869 13:56:58.637543 TX Vref=28, minBit 8, minWin=25, winSum=433
2870 13:56:58.640671 TX Vref=30, minBit 8, minWin=25, winSum=429
2871 13:56:58.647319 TX Vref=32, minBit 8, minWin=26, winSum=432
2872 13:56:58.650388 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 32
2873 13:56:58.650850
2874 13:56:58.654092 Final TX Range 1 Vref 32
2875 13:56:58.654550
2876 13:56:58.654911 ==
2877 13:56:58.658039 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 13:56:58.660830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2879 13:56:58.661400 ==
2880 13:56:58.663838
2881 13:56:58.664410
2882 13:56:58.664830 TX Vref Scan disable
2883 13:56:58.667378 == TX Byte 0 ==
2884 13:56:58.670950 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2885 13:56:58.677986 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2886 13:56:58.678557 == TX Byte 1 ==
2887 13:56:58.680896 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2888 13:56:58.684075 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2889 13:56:58.687129
2890 13:56:58.687687 [DATLAT]
2891 13:56:58.688051 Freq=1200, CH0 RK1
2892 13:56:58.688391
2893 13:56:58.691184 DATLAT Default: 0xc
2894 13:56:58.691746 0, 0xFFFF, sum = 0
2895 13:56:58.693943 1, 0xFFFF, sum = 0
2896 13:56:58.694515 2, 0xFFFF, sum = 0
2897 13:56:58.697598 3, 0xFFFF, sum = 0
2898 13:56:58.698168 4, 0xFFFF, sum = 0
2899 13:56:58.701456 5, 0xFFFF, sum = 0
2900 13:56:58.704147 6, 0xFFFF, sum = 0
2901 13:56:58.704767 7, 0xFFFF, sum = 0
2902 13:56:58.707863 8, 0xFFFF, sum = 0
2903 13:56:58.708429 9, 0xFFFF, sum = 0
2904 13:56:58.710789 10, 0xFFFF, sum = 0
2905 13:56:58.711391 11, 0x0, sum = 1
2906 13:56:58.714410 12, 0x0, sum = 2
2907 13:56:58.714973 13, 0x0, sum = 3
2908 13:56:58.717371 14, 0x0, sum = 4
2909 13:56:58.717843 best_step = 12
2910 13:56:58.718210
2911 13:56:58.718548 ==
2912 13:56:58.720767 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 13:56:58.725391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2914 13:56:58.725954 ==
2915 13:56:58.726954 RX Vref Scan: 0
2916 13:56:58.727467
2917 13:56:58.730795 RX Vref 0 -> 0, step: 1
2918 13:56:58.731324
2919 13:56:58.731705 RX Delay -21 -> 252, step: 4
2920 13:56:58.737909 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2921 13:56:58.740867 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2922 13:56:58.744416 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2923 13:56:58.748297 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2924 13:56:58.750960 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2925 13:56:58.757503 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2926 13:56:58.761096 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2927 13:56:58.764367 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2928 13:56:58.767860 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2929 13:56:58.771020 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2930 13:56:58.778121 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2931 13:56:58.781633 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2932 13:56:58.784818 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2933 13:56:58.789234 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2934 13:56:58.791012 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2935 13:56:58.798034 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
2936 13:56:58.798595 ==
2937 13:56:58.801165 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 13:56:58.804620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2939 13:56:58.805245 ==
2940 13:56:58.805620 DQS Delay:
2941 13:56:58.808132 DQS0 = 0, DQS1 = 0
2942 13:56:58.808690 DQM Delay:
2943 13:56:58.811137 DQM0 = 115, DQM1 = 106
2944 13:56:58.811699 DQ Delay:
2945 13:56:58.814197 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2946 13:56:58.817652 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2947 13:56:58.821191 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2948 13:56:58.824190 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =116
2949 13:56:58.824795
2950 13:56:58.825168
2951 13:56:58.833955 [DQSOSCAuto] RK1, (LSB)MR18= 0x1212, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2952 13:56:58.837427 CH0 RK1: MR19=404, MR18=1212
2953 13:56:58.841713 CH0_RK1: MR19=0x404, MR18=0x1212, DQSOSC=403, MR23=63, INC=40, DEC=26
2954 13:56:58.844089 [RxdqsGatingPostProcess] freq 1200
2955 13:56:58.851452 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2956 13:56:58.854138 Pre-setting of DQS Precalculation
2957 13:56:58.858900 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2958 13:56:58.859490 ==
2959 13:56:58.861278 Dram Type= 6, Freq= 0, CH_1, rank 0
2960 13:56:58.867763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2961 13:56:58.868465 ==
2962 13:56:58.871776 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2963 13:56:58.878158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2964 13:56:58.887005 [CA 0] Center 37 (7~68) winsize 62
2965 13:56:58.890338 [CA 1] Center 37 (7~68) winsize 62
2966 13:56:58.892883 [CA 2] Center 34 (4~65) winsize 62
2967 13:56:58.896325 [CA 3] Center 33 (3~64) winsize 62
2968 13:56:58.899694 [CA 4] Center 32 (1~63) winsize 63
2969 13:56:58.902832 [CA 5] Center 32 (2~63) winsize 62
2970 13:56:58.903395
2971 13:56:58.906351 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2972 13:56:58.906912
2973 13:56:58.910680 [CATrainingPosCal] consider 1 rank data
2974 13:56:58.913095 u2DelayCellTimex100 = 270/100 ps
2975 13:56:58.917715 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2976 13:56:58.919890 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2977 13:56:58.926558 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2978 13:56:58.929980 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2979 13:56:58.933605 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2980 13:56:58.937387 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2981 13:56:58.937953
2982 13:56:58.941704 CA PerBit enable=1, Macro0, CA PI delay=32
2983 13:56:58.942173
2984 13:56:58.944578 [CBTSetCACLKResult] CA Dly = 32
2985 13:56:58.945291 CS Dly: 6 (0~37)
2986 13:56:58.945687 ==
2987 13:56:58.946383 Dram Type= 6, Freq= 0, CH_1, rank 1
2988 13:56:58.952803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2989 13:56:58.953357 ==
2990 13:56:58.955979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2991 13:56:58.963534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2992 13:56:58.971858 [CA 0] Center 37 (7~68) winsize 62
2993 13:56:58.975201 [CA 1] Center 37 (7~68) winsize 62
2994 13:56:58.978151 [CA 2] Center 33 (3~64) winsize 62
2995 13:56:58.982335 [CA 3] Center 33 (3~64) winsize 62
2996 13:56:58.984924 [CA 4] Center 32 (2~63) winsize 62
2997 13:56:58.988493 [CA 5] Center 32 (1~63) winsize 63
2998 13:56:58.989100
2999 13:56:58.992104 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3000 13:56:58.992783
3001 13:56:58.994554 [CATrainingPosCal] consider 2 rank data
3002 13:56:58.998810 u2DelayCellTimex100 = 270/100 ps
3003 13:56:59.001392 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3004 13:56:59.005248 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3005 13:56:59.011821 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
3006 13:56:59.015970 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3007 13:56:59.018607 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3008 13:56:59.021754 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3009 13:56:59.022317
3010 13:56:59.025152 CA PerBit enable=1, Macro0, CA PI delay=32
3011 13:56:59.025757
3012 13:56:59.028399 [CBTSetCACLKResult] CA Dly = 32
3013 13:56:59.029010 CS Dly: 6 (0~38)
3014 13:56:59.029393
3015 13:56:59.032951 ----->DramcWriteLeveling(PI) begin...
3016 13:56:59.033522 ==
3017 13:56:59.035072 Dram Type= 6, Freq= 0, CH_1, rank 0
3018 13:56:59.041901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3019 13:56:59.042592 ==
3020 13:56:59.045279 Write leveling (Byte 0): 21 => 21
3021 13:56:59.048796 Write leveling (Byte 1): 21 => 21
3022 13:56:59.049265 DramcWriteLeveling(PI) end<-----
3023 13:56:59.052864
3024 13:56:59.053418 ==
3025 13:56:59.055097 Dram Type= 6, Freq= 0, CH_1, rank 0
3026 13:56:59.058333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3027 13:56:59.058899 ==
3028 13:56:59.061405 [Gating] SW mode calibration
3029 13:56:59.068820 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3030 13:56:59.072277 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3031 13:56:59.078556 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3032 13:56:59.081961 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3033 13:56:59.084641 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3034 13:56:59.091497 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3035 13:56:59.095142 0 11 16 | B1->B0 | 3232 2626 | 0 0 | (0 1) (1 0)
3036 13:56:59.098285 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3037 13:56:59.104936 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3038 13:56:59.107948 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3039 13:56:59.111902 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3040 13:56:59.118008 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3041 13:56:59.122172 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3042 13:56:59.125169 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3043 13:56:59.131246 0 12 16 | B1->B0 | 3636 4343 | 0 0 | (1 1) (0 0)
3044 13:56:59.134776 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3045 13:56:59.138229 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3046 13:56:59.145463 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3047 13:56:59.147822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3048 13:56:59.152645 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3049 13:56:59.157956 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3050 13:56:59.161093 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3051 13:56:59.164662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3052 13:56:59.171096 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3053 13:56:59.174650 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 13:56:59.178165 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 13:56:59.184804 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 13:56:59.187830 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 13:56:59.191046 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 13:56:59.194934 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 13:56:59.201030 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 13:56:59.204234 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 13:56:59.207732 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 13:56:59.215034 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 13:56:59.217991 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 13:56:59.221129 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3065 13:56:59.228494 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3066 13:56:59.231794 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3067 13:56:59.235042 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3068 13:56:59.241297 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3069 13:56:59.241872 Total UI for P1: 0, mck2ui 16
3070 13:56:59.248357 best dqsien dly found for B0: ( 0, 15, 16)
3071 13:56:59.251316 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3072 13:56:59.257878 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3073 13:56:59.258845 Total UI for P1: 0, mck2ui 16
3074 13:56:59.260868 best dqsien dly found for B1: ( 0, 15, 20)
3075 13:56:59.264604 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3076 13:56:59.267805 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3077 13:56:59.268376
3078 13:56:59.274451 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3079 13:56:59.277608 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3080 13:56:59.278178 [Gating] SW calibration Done
3081 13:56:59.281361 ==
3082 13:56:59.284507 Dram Type= 6, Freq= 0, CH_1, rank 0
3083 13:56:59.287693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3084 13:56:59.288161 ==
3085 13:56:59.288529 RX Vref Scan: 0
3086 13:56:59.288910
3087 13:56:59.291943 RX Vref 0 -> 0, step: 1
3088 13:56:59.292511
3089 13:56:59.295308 RX Delay -40 -> 252, step: 8
3090 13:56:59.298246 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3091 13:56:59.300969 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3092 13:56:59.304376 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3093 13:56:59.310467 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3094 13:56:59.314037 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3095 13:56:59.317622 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3096 13:56:59.321132 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3097 13:56:59.324819 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3098 13:56:59.330743 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3099 13:56:59.334057 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3100 13:56:59.337771 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3101 13:56:59.340955 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3102 13:56:59.344624 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3103 13:56:59.351078 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3104 13:56:59.354274 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3105 13:56:59.357632 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3106 13:56:59.358133 ==
3107 13:56:59.362730 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 13:56:59.363735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3109 13:56:59.364137 ==
3110 13:56:59.367735 DQS Delay:
3111 13:56:59.368292 DQS0 = 0, DQS1 = 0
3112 13:56:59.372268 DQM Delay:
3113 13:56:59.373024 DQM0 = 116, DQM1 = 108
3114 13:56:59.373398 DQ Delay:
3115 13:56:59.377624 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3116 13:56:59.381176 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3117 13:56:59.385391 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3118 13:56:59.387469 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3119 13:56:59.388033
3120 13:56:59.388397
3121 13:56:59.388789 ==
3122 13:56:59.391256 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 13:56:59.394333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3124 13:56:59.394902 ==
3125 13:56:59.395276
3126 13:56:59.395620
3127 13:56:59.397361 TX Vref Scan disable
3128 13:56:59.397822 == TX Byte 0 ==
3129 13:56:59.404410 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3130 13:56:59.408537 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3131 13:56:59.411243 == TX Byte 1 ==
3132 13:56:59.414501 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3133 13:56:59.417502 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3134 13:56:59.418114 ==
3135 13:56:59.421222 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 13:56:59.424298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3137 13:56:59.425005 ==
3138 13:56:59.436844 TX Vref=22, minBit 3, minWin=25, winSum=415
3139 13:56:59.441056 TX Vref=24, minBit 3, minWin=25, winSum=419
3140 13:56:59.443213 TX Vref=26, minBit 3, minWin=25, winSum=422
3141 13:56:59.446544 TX Vref=28, minBit 0, minWin=26, winSum=426
3142 13:56:59.450485 TX Vref=30, minBit 0, minWin=26, winSum=429
3143 13:56:59.457078 TX Vref=32, minBit 0, minWin=26, winSum=430
3144 13:56:59.460503 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 32
3145 13:56:59.461130
3146 13:56:59.465115 Final TX Range 1 Vref 32
3147 13:56:59.465680
3148 13:56:59.466050 ==
3149 13:56:59.468287 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 13:56:59.471531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3151 13:56:59.472097 ==
3152 13:56:59.472627
3153 13:56:59.473661
3154 13:56:59.474119 TX Vref Scan disable
3155 13:56:59.477089 == TX Byte 0 ==
3156 13:56:59.481339 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3157 13:56:59.484533 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3158 13:56:59.487149 == TX Byte 1 ==
3159 13:56:59.490425 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3160 13:56:59.494126 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3161 13:56:59.494687
3162 13:56:59.497347 [DATLAT]
3163 13:56:59.497904 Freq=1200, CH1 RK0
3164 13:56:59.498276
3165 13:56:59.500336 DATLAT Default: 0xd
3166 13:56:59.500942 0, 0xFFFF, sum = 0
3167 13:56:59.504082 1, 0xFFFF, sum = 0
3168 13:56:59.504652 2, 0xFFFF, sum = 0
3169 13:56:59.507279 3, 0xFFFF, sum = 0
3170 13:56:59.507847 4, 0xFFFF, sum = 0
3171 13:56:59.511196 5, 0xFFFF, sum = 0
3172 13:56:59.511760 6, 0xFFFF, sum = 0
3173 13:56:59.513369 7, 0xFFFF, sum = 0
3174 13:56:59.513841 8, 0xFFFF, sum = 0
3175 13:56:59.517289 9, 0xFFFF, sum = 0
3176 13:56:59.520554 10, 0xFFFF, sum = 0
3177 13:56:59.521166 11, 0x0, sum = 1
3178 13:56:59.521546 12, 0x0, sum = 2
3179 13:56:59.523730 13, 0x0, sum = 3
3180 13:56:59.524298 14, 0x0, sum = 4
3181 13:56:59.527323 best_step = 12
3182 13:56:59.527895
3183 13:56:59.528268 ==
3184 13:56:59.530099 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 13:56:59.533726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3186 13:56:59.534292 ==
3187 13:56:59.537661 RX Vref Scan: 1
3188 13:56:59.538224
3189 13:56:59.538595 Set Vref Range= 32 -> 127
3190 13:56:59.538938
3191 13:56:59.540561 RX Vref 32 -> 127, step: 1
3192 13:56:59.541153
3193 13:56:59.543858 RX Delay -29 -> 252, step: 4
3194 13:56:59.544540
3195 13:56:59.546939 Set Vref, RX VrefLevel [Byte0]: 32
3196 13:56:59.550078 [Byte1]: 32
3197 13:56:59.550644
3198 13:56:59.554692 Set Vref, RX VrefLevel [Byte0]: 33
3199 13:56:59.556785 [Byte1]: 33
3200 13:56:59.561377
3201 13:56:59.562093 Set Vref, RX VrefLevel [Byte0]: 34
3202 13:56:59.564344 [Byte1]: 34
3203 13:56:59.570059
3204 13:56:59.570524 Set Vref, RX VrefLevel [Byte0]: 35
3205 13:56:59.572581 [Byte1]: 35
3206 13:56:59.577286
3207 13:56:59.577846 Set Vref, RX VrefLevel [Byte0]: 36
3208 13:56:59.580570 [Byte1]: 36
3209 13:56:59.585058
3210 13:56:59.585519 Set Vref, RX VrefLevel [Byte0]: 37
3211 13:56:59.589008 [Byte1]: 37
3212 13:56:59.593477
3213 13:56:59.594033 Set Vref, RX VrefLevel [Byte0]: 38
3214 13:56:59.596245 [Byte1]: 38
3215 13:56:59.601097
3216 13:56:59.601659 Set Vref, RX VrefLevel [Byte0]: 39
3217 13:56:59.604801 [Byte1]: 39
3218 13:56:59.609853
3219 13:56:59.610410 Set Vref, RX VrefLevel [Byte0]: 40
3220 13:56:59.612996 [Byte1]: 40
3221 13:56:59.617260
3222 13:56:59.617816 Set Vref, RX VrefLevel [Byte0]: 41
3223 13:56:59.620224 [Byte1]: 41
3224 13:56:59.625753
3225 13:56:59.626310 Set Vref, RX VrefLevel [Byte0]: 42
3226 13:56:59.628271 [Byte1]: 42
3227 13:56:59.633100
3228 13:56:59.633567 Set Vref, RX VrefLevel [Byte0]: 43
3229 13:56:59.635950 [Byte1]: 43
3230 13:56:59.640865
3231 13:56:59.641377 Set Vref, RX VrefLevel [Byte0]: 44
3232 13:56:59.644217 [Byte1]: 44
3233 13:56:59.648678
3234 13:56:59.649203 Set Vref, RX VrefLevel [Byte0]: 45
3235 13:56:59.652177 [Byte1]: 45
3236 13:56:59.657060
3237 13:56:59.657631 Set Vref, RX VrefLevel [Byte0]: 46
3238 13:56:59.660227 [Byte1]: 46
3239 13:56:59.666135
3240 13:56:59.666706 Set Vref, RX VrefLevel [Byte0]: 47
3241 13:56:59.667854 [Byte1]: 47
3242 13:56:59.673036
3243 13:56:59.673617 Set Vref, RX VrefLevel [Byte0]: 48
3244 13:56:59.676289 [Byte1]: 48
3245 13:56:59.681178
3246 13:56:59.681742 Set Vref, RX VrefLevel [Byte0]: 49
3247 13:56:59.683921 [Byte1]: 49
3248 13:56:59.689512
3249 13:56:59.690085 Set Vref, RX VrefLevel [Byte0]: 50
3250 13:56:59.692595 [Byte1]: 50
3251 13:56:59.697315
3252 13:56:59.697880 Set Vref, RX VrefLevel [Byte0]: 51
3253 13:56:59.699921 [Byte1]: 51
3254 13:56:59.704496
3255 13:56:59.705109 Set Vref, RX VrefLevel [Byte0]: 52
3256 13:56:59.708616 [Byte1]: 52
3257 13:56:59.712448
3258 13:56:59.713080 Set Vref, RX VrefLevel [Byte0]: 53
3259 13:56:59.716196 [Byte1]: 53
3260 13:56:59.721080
3261 13:56:59.721647 Set Vref, RX VrefLevel [Byte0]: 54
3262 13:56:59.724290 [Byte1]: 54
3263 13:56:59.728616
3264 13:56:59.729251 Set Vref, RX VrefLevel [Byte0]: 55
3265 13:56:59.732309 [Byte1]: 55
3266 13:56:59.736348
3267 13:56:59.736856 Set Vref, RX VrefLevel [Byte0]: 56
3268 13:56:59.739513 [Byte1]: 56
3269 13:56:59.745448
3270 13:56:59.746164 Set Vref, RX VrefLevel [Byte0]: 57
3271 13:56:59.748003 [Byte1]: 57
3272 13:56:59.752988
3273 13:56:59.753717 Set Vref, RX VrefLevel [Byte0]: 58
3274 13:56:59.755623 [Byte1]: 58
3275 13:56:59.760001
3276 13:56:59.760467 Set Vref, RX VrefLevel [Byte0]: 59
3277 13:56:59.763643 [Byte1]: 59
3278 13:56:59.768046
3279 13:56:59.768515 Set Vref, RX VrefLevel [Byte0]: 60
3280 13:56:59.772171 [Byte1]: 60
3281 13:56:59.775994
3282 13:56:59.776456 Set Vref, RX VrefLevel [Byte0]: 61
3283 13:56:59.779222 [Byte1]: 61
3284 13:56:59.785418
3285 13:56:59.785884 Set Vref, RX VrefLevel [Byte0]: 62
3286 13:56:59.787197 [Byte1]: 62
3287 13:56:59.792108
3288 13:56:59.792433 Set Vref, RX VrefLevel [Byte0]: 63
3289 13:56:59.794918 [Byte1]: 63
3290 13:56:59.800179
3291 13:56:59.800420 Set Vref, RX VrefLevel [Byte0]: 64
3292 13:56:59.803736 [Byte1]: 64
3293 13:56:59.808309
3294 13:56:59.808569 Set Vref, RX VrefLevel [Byte0]: 65
3295 13:56:59.810857 [Byte1]: 65
3296 13:56:59.815305
3297 13:56:59.815440 Final RX Vref Byte 0 = 50 to rank0
3298 13:56:59.818769 Final RX Vref Byte 1 = 49 to rank0
3299 13:56:59.821944 Final RX Vref Byte 0 = 50 to rank1
3300 13:56:59.826819 Final RX Vref Byte 1 = 49 to rank1==
3301 13:56:59.828978 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 13:56:59.836386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3303 13:56:59.836503 ==
3304 13:56:59.836597 DQS Delay:
3305 13:56:59.836686 DQS0 = 0, DQS1 = 0
3306 13:56:59.839226 DQM Delay:
3307 13:56:59.839308 DQM0 = 115, DQM1 = 105
3308 13:56:59.842458 DQ Delay:
3309 13:56:59.845693 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3310 13:56:59.848839 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3311 13:56:59.852010 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3312 13:56:59.855275 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =116
3313 13:56:59.855360
3314 13:56:59.855425
3315 13:56:59.862308 [DQSOSCAuto] RK0, (LSB)MR18= 0x1616, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3316 13:56:59.865354 CH1 RK0: MR19=404, MR18=1616
3317 13:56:59.872637 CH1_RK0: MR19=0x404, MR18=0x1616, DQSOSC=401, MR23=63, INC=40, DEC=27
3318 13:56:59.872805
3319 13:56:59.875447 ----->DramcWriteLeveling(PI) begin...
3320 13:56:59.875532 ==
3321 13:56:59.879084 Dram Type= 6, Freq= 0, CH_1, rank 1
3322 13:56:59.881928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3323 13:56:59.882012 ==
3324 13:56:59.885117 Write leveling (Byte 0): 22 => 22
3325 13:56:59.889566 Write leveling (Byte 1): 22 => 22
3326 13:56:59.892586 DramcWriteLeveling(PI) end<-----
3327 13:56:59.892675
3328 13:56:59.892747 ==
3329 13:56:59.897096 Dram Type= 6, Freq= 0, CH_1, rank 1
3330 13:56:59.902024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3331 13:56:59.902121 ==
3332 13:56:59.902188 [Gating] SW mode calibration
3333 13:56:59.911830 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3334 13:56:59.916011 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3335 13:56:59.918936 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3336 13:56:59.925019 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3337 13:56:59.928924 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3338 13:56:59.932075 0 11 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3339 13:56:59.939216 0 11 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
3340 13:56:59.942320 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3341 13:56:59.945615 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3342 13:56:59.952302 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3343 13:56:59.955510 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3344 13:56:59.959250 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3345 13:56:59.965194 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3346 13:56:59.968442 0 12 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3347 13:56:59.971693 0 12 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3348 13:56:59.978938 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 13:56:59.982693 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3350 13:56:59.985487 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3351 13:56:59.988628 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3352 13:56:59.995396 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 13:56:59.999063 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3354 13:57:00.002014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3355 13:57:00.009038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3356 13:57:00.012685 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 13:57:00.018130 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 13:57:00.022106 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 13:57:00.025502 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 13:57:00.028540 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 13:57:00.036424 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 13:57:00.039819 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 13:57:00.042165 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 13:57:00.049233 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 13:57:00.052730 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 13:57:00.056202 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 13:57:00.062250 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 13:57:00.065061 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3369 13:57:00.068818 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3370 13:57:00.075983 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3371 13:57:00.079097 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3372 13:57:00.082876 Total UI for P1: 0, mck2ui 16
3373 13:57:00.086688 best dqsien dly found for B0: ( 0, 15, 12)
3374 13:57:00.089929 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3375 13:57:00.093510 Total UI for P1: 0, mck2ui 16
3376 13:57:00.095515 best dqsien dly found for B1: ( 0, 15, 16)
3377 13:57:00.098988 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3378 13:57:00.102138 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3379 13:57:00.102708
3380 13:57:00.108832 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3381 13:57:00.112099 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3382 13:57:00.112684 [Gating] SW calibration Done
3383 13:57:00.115323 ==
3384 13:57:00.119187 Dram Type= 6, Freq= 0, CH_1, rank 1
3385 13:57:00.122547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3386 13:57:00.123118 ==
3387 13:57:00.123589 RX Vref Scan: 0
3388 13:57:00.123944
3389 13:57:00.125579 RX Vref 0 -> 0, step: 1
3390 13:57:00.126044
3391 13:57:00.129790 RX Delay -40 -> 252, step: 8
3392 13:57:00.132760 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3393 13:57:00.136188 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3394 13:57:00.141908 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3395 13:57:00.145346 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3396 13:57:00.148090 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3397 13:57:00.151748 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3398 13:57:00.155681 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3399 13:57:00.158987 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3400 13:57:00.165094 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3401 13:57:00.168265 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3402 13:57:00.171935 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3403 13:57:00.175996 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3404 13:57:00.181608 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3405 13:57:00.185165 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3406 13:57:00.188338 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3407 13:57:00.191802 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3408 13:57:00.192365 ==
3409 13:57:00.195017 Dram Type= 6, Freq= 0, CH_1, rank 1
3410 13:57:00.199366 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3411 13:57:00.201465 ==
3412 13:57:00.201925 DQS Delay:
3413 13:57:00.202286 DQS0 = 0, DQS1 = 0
3414 13:57:00.205006 DQM Delay:
3415 13:57:00.205562 DQM0 = 115, DQM1 = 106
3416 13:57:00.208358 DQ Delay:
3417 13:57:00.212337 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3418 13:57:00.214800 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3419 13:57:00.218323 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3420 13:57:00.221652 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =111
3421 13:57:00.222218
3422 13:57:00.222583
3423 13:57:00.222919 ==
3424 13:57:00.225794 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 13:57:00.228023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3426 13:57:00.228590 ==
3427 13:57:00.229004
3428 13:57:00.229347
3429 13:57:00.231212 TX Vref Scan disable
3430 13:57:00.234588 == TX Byte 0 ==
3431 13:57:00.238112 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3432 13:57:00.243932 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3433 13:57:00.245038 == TX Byte 1 ==
3434 13:57:00.248148 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3435 13:57:00.251120 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3436 13:57:00.251585 ==
3437 13:57:00.255105 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 13:57:00.257939 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3439 13:57:00.261397 ==
3440 13:57:00.272754 TX Vref=22, minBit 8, minWin=25, winSum=423
3441 13:57:00.274732 TX Vref=24, minBit 9, minWin=25, winSum=425
3442 13:57:00.278403 TX Vref=26, minBit 3, minWin=26, winSum=429
3443 13:57:00.281684 TX Vref=28, minBit 3, minWin=26, winSum=428
3444 13:57:00.284640 TX Vref=30, minBit 9, minWin=26, winSum=431
3445 13:57:00.288207 TX Vref=32, minBit 0, minWin=26, winSum=433
3446 13:57:00.294346 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 32
3447 13:57:00.294900
3448 13:57:00.298106 Final TX Range 1 Vref 32
3449 13:57:00.298673
3450 13:57:00.299042 ==
3451 13:57:00.301076 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 13:57:00.305824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3453 13:57:00.306413 ==
3454 13:57:00.306789
3455 13:57:00.307525
3456 13:57:00.307890 TX Vref Scan disable
3457 13:57:00.311611 == TX Byte 0 ==
3458 13:57:00.315401 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3459 13:57:00.318089 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3460 13:57:00.321786 == TX Byte 1 ==
3461 13:57:00.325439 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3462 13:57:00.328026 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3463 13:57:00.328613
3464 13:57:00.331210 [DATLAT]
3465 13:57:00.331672 Freq=1200, CH1 RK1
3466 13:57:00.332040
3467 13:57:00.335284 DATLAT Default: 0xc
3468 13:57:00.335745 0, 0xFFFF, sum = 0
3469 13:57:00.337812 1, 0xFFFF, sum = 0
3470 13:57:00.338281 2, 0xFFFF, sum = 0
3471 13:57:00.341227 3, 0xFFFF, sum = 0
3472 13:57:00.341795 4, 0xFFFF, sum = 0
3473 13:57:00.344876 5, 0xFFFF, sum = 0
3474 13:57:00.345346 6, 0xFFFF, sum = 0
3475 13:57:00.349406 7, 0xFFFF, sum = 0
3476 13:57:00.349876 8, 0xFFFF, sum = 0
3477 13:57:00.352586 9, 0xFFFF, sum = 0
3478 13:57:00.355271 10, 0xFFFF, sum = 0
3479 13:57:00.355743 11, 0x0, sum = 1
3480 13:57:00.356114 12, 0x0, sum = 2
3481 13:57:00.358426 13, 0x0, sum = 3
3482 13:57:00.358896 14, 0x0, sum = 4
3483 13:57:00.361143 best_step = 12
3484 13:57:00.361604
3485 13:57:00.361967 ==
3486 13:57:00.364994 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 13:57:00.367956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3488 13:57:00.368546 ==
3489 13:57:00.371194 RX Vref Scan: 0
3490 13:57:00.371755
3491 13:57:00.372124 RX Vref 0 -> 0, step: 1
3492 13:57:00.372470
3493 13:57:00.374658 RX Delay -29 -> 252, step: 4
3494 13:57:00.382212 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3495 13:57:00.384598 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3496 13:57:00.388915 iDelay=199, Bit 2, Center 106 (35 ~ 178) 144
3497 13:57:00.391817 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3498 13:57:00.395152 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3499 13:57:00.401410 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3500 13:57:00.405272 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3501 13:57:00.409113 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3502 13:57:00.411822 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3503 13:57:00.415744 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3504 13:57:00.421421 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3505 13:57:00.425042 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3506 13:57:00.428146 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3507 13:57:00.431384 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3508 13:57:00.435068 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3509 13:57:00.441846 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3510 13:57:00.442409 ==
3511 13:57:00.444565 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 13:57:00.447961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3513 13:57:00.448427 ==
3514 13:57:00.448897 DQS Delay:
3515 13:57:00.452301 DQS0 = 0, DQS1 = 0
3516 13:57:00.452804 DQM Delay:
3517 13:57:00.454427 DQM0 = 114, DQM1 = 103
3518 13:57:00.454888 DQ Delay:
3519 13:57:00.457944 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =112
3520 13:57:00.462512 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3521 13:57:00.464978 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3522 13:57:00.468997 DQ12 =114, DQ13 =112, DQ14 =112, DQ15 =110
3523 13:57:00.469559
3524 13:57:00.469929
3525 13:57:00.477794 [DQSOSCAuto] RK1, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3526 13:57:00.481388 CH1 RK1: MR19=404, MR18=707
3527 13:57:00.484872 CH1_RK1: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
3528 13:57:00.487943 [RxdqsGatingPostProcess] freq 1200
3529 13:57:00.494614 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3530 13:57:00.499121 Pre-setting of DQS Precalculation
3531 13:57:00.501535 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3532 13:57:00.511535 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3533 13:57:00.517761 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3534 13:57:00.518336
3535 13:57:00.518703
3536 13:57:00.522298 [Calibration Summary] 2400 Mbps
3537 13:57:00.522869 CH 0, Rank 0
3538 13:57:00.524378 SW Impedance : PASS
3539 13:57:00.524871 DUTY Scan : NO K
3540 13:57:00.528286 ZQ Calibration : PASS
3541 13:57:00.532135 Jitter Meter : NO K
3542 13:57:00.532737 CBT Training : PASS
3543 13:57:00.534594 Write leveling : PASS
3544 13:57:00.537958 RX DQS gating : PASS
3545 13:57:00.538421 RX DQ/DQS(RDDQC) : PASS
3546 13:57:00.542584 TX DQ/DQS : PASS
3547 13:57:00.543153 RX DATLAT : PASS
3548 13:57:00.544861 RX DQ/DQS(Engine): PASS
3549 13:57:00.548612 TX OE : NO K
3550 13:57:00.549235 All Pass.
3551 13:57:00.549743
3552 13:57:00.550262 CH 0, Rank 1
3553 13:57:00.551605 SW Impedance : PASS
3554 13:57:00.554335 DUTY Scan : NO K
3555 13:57:00.554800 ZQ Calibration : PASS
3556 13:57:00.558338 Jitter Meter : NO K
3557 13:57:00.561245 CBT Training : PASS
3558 13:57:00.561852 Write leveling : PASS
3559 13:57:00.564880 RX DQS gating : PASS
3560 13:57:00.567863 RX DQ/DQS(RDDQC) : PASS
3561 13:57:00.568429 TX DQ/DQS : PASS
3562 13:57:00.572871 RX DATLAT : PASS
3563 13:57:00.574609 RX DQ/DQS(Engine): PASS
3564 13:57:00.575097 TX OE : NO K
3565 13:57:00.578777 All Pass.
3566 13:57:00.579343
3567 13:57:00.579714 CH 1, Rank 0
3568 13:57:00.580886 SW Impedance : PASS
3569 13:57:00.581353 DUTY Scan : NO K
3570 13:57:00.584559 ZQ Calibration : PASS
3571 13:57:00.587499 Jitter Meter : NO K
3572 13:57:00.587966 CBT Training : PASS
3573 13:57:00.591415 Write leveling : PASS
3574 13:57:00.594238 RX DQS gating : PASS
3575 13:57:00.594704 RX DQ/DQS(RDDQC) : PASS
3576 13:57:00.598188 TX DQ/DQS : PASS
3577 13:57:00.600968 RX DATLAT : PASS
3578 13:57:00.601541 RX DQ/DQS(Engine): PASS
3579 13:57:00.604604 TX OE : NO K
3580 13:57:00.605208 All Pass.
3581 13:57:00.605579
3582 13:57:00.607824 CH 1, Rank 1
3583 13:57:00.608410 SW Impedance : PASS
3584 13:57:00.611088 DUTY Scan : NO K
3585 13:57:00.611655 ZQ Calibration : PASS
3586 13:57:00.614154 Jitter Meter : NO K
3587 13:57:00.617939 CBT Training : PASS
3588 13:57:00.618508 Write leveling : PASS
3589 13:57:00.621299 RX DQS gating : PASS
3590 13:57:00.624548 RX DQ/DQS(RDDQC) : PASS
3591 13:57:00.625155 TX DQ/DQS : PASS
3592 13:57:00.627722 RX DATLAT : PASS
3593 13:57:00.631242 RX DQ/DQS(Engine): PASS
3594 13:57:00.631807 TX OE : NO K
3595 13:57:00.634560 All Pass.
3596 13:57:00.635135
3597 13:57:00.635507 DramC Write-DBI off
3598 13:57:00.638177 PER_BANK_REFRESH: Hybrid Mode
3599 13:57:00.638643 TX_TRACKING: ON
3600 13:57:00.647570 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3601 13:57:00.650827 [FAST_K] Save calibration result to emmc
3602 13:57:00.654836 dramc_set_vcore_voltage set vcore to 650000
3603 13:57:00.657556 Read voltage for 600, 5
3604 13:57:00.658013 Vio18 = 0
3605 13:57:00.660845 Vcore = 650000
3606 13:57:00.661308 Vdram = 0
3607 13:57:00.661678 Vddq = 0
3608 13:57:00.664546 Vmddr = 0
3609 13:57:00.668210 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3610 13:57:00.675242 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3611 13:57:00.675813 MEM_TYPE=3, freq_sel=19
3612 13:57:00.677924 sv_algorithm_assistance_LP4_1600
3613 13:57:00.680803 ============ PULL DRAM RESETB DOWN ============
3614 13:57:00.687820 ========== PULL DRAM RESETB DOWN end =========
3615 13:57:00.690603 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3616 13:57:00.695377 ===================================
3617 13:57:00.697531 LPDDR4 DRAM CONFIGURATION
3618 13:57:00.700672 ===================================
3619 13:57:00.701281 EX_ROW_EN[0] = 0x0
3620 13:57:00.704353 EX_ROW_EN[1] = 0x0
3621 13:57:00.708354 LP4Y_EN = 0x0
3622 13:57:00.708965 WORK_FSP = 0x0
3623 13:57:00.711149 WL = 0x2
3624 13:57:00.711715 RL = 0x2
3625 13:57:00.713725 BL = 0x2
3626 13:57:00.714187 RPST = 0x0
3627 13:57:00.718395 RD_PRE = 0x0
3628 13:57:00.718963 WR_PRE = 0x1
3629 13:57:00.720369 WR_PST = 0x0
3630 13:57:00.720873 DBI_WR = 0x0
3631 13:57:00.724099 DBI_RD = 0x0
3632 13:57:00.724665 OTF = 0x1
3633 13:57:00.728018 ===================================
3634 13:57:00.731068 ===================================
3635 13:57:00.733572 ANA top config
3636 13:57:00.737715 ===================================
3637 13:57:00.738316 DLL_ASYNC_EN = 0
3638 13:57:00.740175 ALL_SLAVE_EN = 1
3639 13:57:00.744468 NEW_RANK_MODE = 1
3640 13:57:00.747353 DLL_IDLE_MODE = 1
3641 13:57:00.747936 LP45_APHY_COMB_EN = 1
3642 13:57:00.750340 TX_ODT_DIS = 1
3643 13:57:00.754249 NEW_8X_MODE = 1
3644 13:57:00.756891 ===================================
3645 13:57:00.760449 ===================================
3646 13:57:00.763434 data_rate = 1200
3647 13:57:00.767567 CKR = 1
3648 13:57:00.770375 DQ_P2S_RATIO = 8
3649 13:57:00.774444 ===================================
3650 13:57:00.775104 CA_P2S_RATIO = 8
3651 13:57:00.776836 DQ_CA_OPEN = 0
3652 13:57:00.780988 DQ_SEMI_OPEN = 0
3653 13:57:00.784119 CA_SEMI_OPEN = 0
3654 13:57:00.787207 CA_FULL_RATE = 0
3655 13:57:00.790819 DQ_CKDIV4_EN = 1
3656 13:57:00.791289 CA_CKDIV4_EN = 1
3657 13:57:00.793948 CA_PREDIV_EN = 0
3658 13:57:00.796675 PH8_DLY = 0
3659 13:57:00.799938 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3660 13:57:00.803141 DQ_AAMCK_DIV = 4
3661 13:57:00.806833 CA_AAMCK_DIV = 4
3662 13:57:00.807408 CA_ADMCK_DIV = 4
3663 13:57:00.811732 DQ_TRACK_CA_EN = 0
3664 13:57:00.813737 CA_PICK = 600
3665 13:57:00.817626 CA_MCKIO = 600
3666 13:57:00.820195 MCKIO_SEMI = 0
3667 13:57:00.823429 PLL_FREQ = 2288
3668 13:57:00.827187 DQ_UI_PI_RATIO = 32
3669 13:57:00.827753 CA_UI_PI_RATIO = 0
3670 13:57:00.830059 ===================================
3671 13:57:00.833468 ===================================
3672 13:57:00.836899 memory_type:LPDDR4
3673 13:57:00.840064 GP_NUM : 10
3674 13:57:00.840624 SRAM_EN : 1
3675 13:57:00.843174 MD32_EN : 0
3676 13:57:00.846492 ===================================
3677 13:57:00.849671 [ANA_INIT] >>>>>>>>>>>>>>
3678 13:57:00.853005 <<<<<< [CONFIGURE PHASE]: ANA_TX
3679 13:57:00.856637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3680 13:57:00.859469 ===================================
3681 13:57:00.859942 data_rate = 1200,PCW = 0X5800
3682 13:57:00.862909 ===================================
3683 13:57:00.869680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3684 13:57:00.873448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3685 13:57:00.879753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3686 13:57:00.883192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3687 13:57:00.886717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3688 13:57:00.890277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3689 13:57:00.893039 [ANA_INIT] flow start
3690 13:57:00.896044 [ANA_INIT] PLL >>>>>>>>
3691 13:57:00.896867 [ANA_INIT] PLL <<<<<<<<
3692 13:57:00.899288 [ANA_INIT] MIDPI >>>>>>>>
3693 13:57:00.903076 [ANA_INIT] MIDPI <<<<<<<<
3694 13:57:00.903653 [ANA_INIT] DLL >>>>>>>>
3695 13:57:00.906045 [ANA_INIT] flow end
3696 13:57:00.909256 ============ LP4 DIFF to SE enter ============
3697 13:57:00.912666 ============ LP4 DIFF to SE exit ============
3698 13:57:00.915908 [ANA_INIT] <<<<<<<<<<<<<
3699 13:57:00.918948 [Flow] Enable top DCM control >>>>>
3700 13:57:00.922960 [Flow] Enable top DCM control <<<<<
3701 13:57:00.926016 Enable DLL master slave shuffle
3702 13:57:00.932992 ==============================================================
3703 13:57:00.933574 Gating Mode config
3704 13:57:00.940510 ==============================================================
3705 13:57:00.942100 Config description:
3706 13:57:00.950040 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3707 13:57:00.955863 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3708 13:57:00.962455 SELPH_MODE 0: By rank 1: By Phase
3709 13:57:00.968649 ==============================================================
3710 13:57:00.969161 GAT_TRACK_EN = 1
3711 13:57:00.972034 RX_GATING_MODE = 2
3712 13:57:00.975052 RX_GATING_TRACK_MODE = 2
3713 13:57:00.978731 SELPH_MODE = 1
3714 13:57:00.982165 PICG_EARLY_EN = 1
3715 13:57:00.985768 VALID_LAT_VALUE = 1
3716 13:57:00.992022 ==============================================================
3717 13:57:00.995485 Enter into Gating configuration >>>>
3718 13:57:00.998367 Exit from Gating configuration <<<<
3719 13:57:01.002938 Enter into DVFS_PRE_config >>>>>
3720 13:57:01.012172 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3721 13:57:01.015011 Exit from DVFS_PRE_config <<<<<
3722 13:57:01.018691 Enter into PICG configuration >>>>
3723 13:57:01.021537 Exit from PICG configuration <<<<
3724 13:57:01.025827 [RX_INPUT] configuration >>>>>
3725 13:57:01.026399 [RX_INPUT] configuration <<<<<
3726 13:57:01.031632 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3727 13:57:01.038952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3728 13:57:01.045545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3729 13:57:01.048508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3730 13:57:01.054746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3731 13:57:01.062812 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3732 13:57:01.065502 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3733 13:57:01.071275 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3734 13:57:01.074407 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3735 13:57:01.078373 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3736 13:57:01.081274 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3737 13:57:01.087592 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3738 13:57:01.091031 ===================================
3739 13:57:01.091503 LPDDR4 DRAM CONFIGURATION
3740 13:57:01.094549 ===================================
3741 13:57:01.098610 EX_ROW_EN[0] = 0x0
3742 13:57:01.100641 EX_ROW_EN[1] = 0x0
3743 13:57:01.101013 LP4Y_EN = 0x0
3744 13:57:01.103899 WORK_FSP = 0x0
3745 13:57:01.104191 WL = 0x2
3746 13:57:01.107747 RL = 0x2
3747 13:57:01.107997 BL = 0x2
3748 13:57:01.111804 RPST = 0x0
3749 13:57:01.111994 RD_PRE = 0x0
3750 13:57:01.114648 WR_PRE = 0x1
3751 13:57:01.114806 WR_PST = 0x0
3752 13:57:01.117487 DBI_WR = 0x0
3753 13:57:01.117644 DBI_RD = 0x0
3754 13:57:01.120497 OTF = 0x1
3755 13:57:01.123614 ===================================
3756 13:57:01.127383 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3757 13:57:01.130855 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3758 13:57:01.137374 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3759 13:57:01.140337 ===================================
3760 13:57:01.140423 LPDDR4 DRAM CONFIGURATION
3761 13:57:01.143878 ===================================
3762 13:57:01.146958 EX_ROW_EN[0] = 0x10
3763 13:57:01.149875 EX_ROW_EN[1] = 0x0
3764 13:57:01.149956 LP4Y_EN = 0x0
3765 13:57:01.153490 WORK_FSP = 0x0
3766 13:57:01.153573 WL = 0x2
3767 13:57:01.156838 RL = 0x2
3768 13:57:01.156921 BL = 0x2
3769 13:57:01.160108 RPST = 0x0
3770 13:57:01.160190 RD_PRE = 0x0
3771 13:57:01.164187 WR_PRE = 0x1
3772 13:57:01.164269 WR_PST = 0x0
3773 13:57:01.167805 DBI_WR = 0x0
3774 13:57:01.167887 DBI_RD = 0x0
3775 13:57:01.170180 OTF = 0x1
3776 13:57:01.173324 ===================================
3777 13:57:01.180078 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3778 13:57:01.183038 nWR fixed to 30
3779 13:57:01.187172 [ModeRegInit_LP4] CH0 RK0
3780 13:57:01.187255 [ModeRegInit_LP4] CH0 RK1
3781 13:57:01.190242 [ModeRegInit_LP4] CH1 RK0
3782 13:57:01.194119 [ModeRegInit_LP4] CH1 RK1
3783 13:57:01.194201 match AC timing 16
3784 13:57:01.199612 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3785 13:57:01.203522 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3786 13:57:01.206169 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3787 13:57:01.212818 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3788 13:57:01.216583 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3789 13:57:01.216666 ==
3790 13:57:01.221671 Dram Type= 6, Freq= 0, CH_0, rank 0
3791 13:57:01.223200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3792 13:57:01.223284 ==
3793 13:57:01.229729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3794 13:57:01.235870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3795 13:57:01.239584 [CA 0] Center 36 (6~66) winsize 61
3796 13:57:01.242954 [CA 1] Center 35 (5~66) winsize 62
3797 13:57:01.245895 [CA 2] Center 34 (4~65) winsize 62
3798 13:57:01.249765 [CA 3] Center 34 (3~65) winsize 63
3799 13:57:01.252624 [CA 4] Center 33 (3~64) winsize 62
3800 13:57:01.256404 [CA 5] Center 33 (3~64) winsize 62
3801 13:57:01.256488
3802 13:57:01.259943 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3803 13:57:01.260027
3804 13:57:01.263093 [CATrainingPosCal] consider 1 rank data
3805 13:57:01.266356 u2DelayCellTimex100 = 270/100 ps
3806 13:57:01.269619 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3807 13:57:01.272897 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3808 13:57:01.277925 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3809 13:57:01.279479 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3810 13:57:01.282980 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3811 13:57:01.286571 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3812 13:57:01.286654
3813 13:57:01.293054 CA PerBit enable=1, Macro0, CA PI delay=33
3814 13:57:01.293138
3815 13:57:01.296159 [CBTSetCACLKResult] CA Dly = 33
3816 13:57:01.296241 CS Dly: 4 (0~35)
3817 13:57:01.296307 ==
3818 13:57:01.299333 Dram Type= 6, Freq= 0, CH_0, rank 1
3819 13:57:01.303004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3820 13:57:01.303087 ==
3821 13:57:01.309313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3822 13:57:01.315788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3823 13:57:01.319346 [CA 0] Center 35 (5~66) winsize 62
3824 13:57:01.322301 [CA 1] Center 35 (5~66) winsize 62
3825 13:57:01.325918 [CA 2] Center 34 (4~65) winsize 62
3826 13:57:01.330242 [CA 3] Center 34 (4~65) winsize 62
3827 13:57:01.332217 [CA 4] Center 33 (3~64) winsize 62
3828 13:57:01.335468 [CA 5] Center 33 (3~64) winsize 62
3829 13:57:01.335551
3830 13:57:01.339925 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3831 13:57:01.340037
3832 13:57:01.342587 [CATrainingPosCal] consider 2 rank data
3833 13:57:01.346289 u2DelayCellTimex100 = 270/100 ps
3834 13:57:01.349346 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3835 13:57:01.352408 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3836 13:57:01.355835 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3837 13:57:01.359844 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3838 13:57:01.362598 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3839 13:57:01.369098 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3840 13:57:01.369183
3841 13:57:01.373609 CA PerBit enable=1, Macro0, CA PI delay=33
3842 13:57:01.373692
3843 13:57:01.375185 [CBTSetCACLKResult] CA Dly = 33
3844 13:57:01.375268 CS Dly: 4 (0~36)
3845 13:57:01.375334
3846 13:57:01.378665 ----->DramcWriteLeveling(PI) begin...
3847 13:57:01.378750 ==
3848 13:57:01.382711 Dram Type= 6, Freq= 0, CH_0, rank 0
3849 13:57:01.388838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3850 13:57:01.388923 ==
3851 13:57:01.392188 Write leveling (Byte 0): 30 => 30
3852 13:57:01.392270 Write leveling (Byte 1): 30 => 30
3853 13:57:01.395261 DramcWriteLeveling(PI) end<-----
3854 13:57:01.395344
3855 13:57:01.395409 ==
3856 13:57:01.399237 Dram Type= 6, Freq= 0, CH_0, rank 0
3857 13:57:01.405125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3858 13:57:01.405209 ==
3859 13:57:01.408522 [Gating] SW mode calibration
3860 13:57:01.415082 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3861 13:57:01.418663 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3862 13:57:01.425843 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3863 13:57:01.429279 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3864 13:57:01.431831 0 5 8 | B1->B0 | 3434 3131 | 0 0 | (1 0) (0 1)
3865 13:57:01.439184 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3866 13:57:01.441664 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3867 13:57:01.444656 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3868 13:57:01.452467 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3869 13:57:01.455357 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3870 13:57:01.458349 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3871 13:57:01.464678 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3872 13:57:01.469275 0 6 8 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
3873 13:57:01.472891 0 6 12 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
3874 13:57:01.478011 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3875 13:57:01.481795 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3876 13:57:01.484524 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3877 13:57:01.491233 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 13:57:01.495043 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3879 13:57:01.498033 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 13:57:01.504355 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3881 13:57:01.508178 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3882 13:57:01.510839 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 13:57:01.517636 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 13:57:01.521305 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 13:57:01.524352 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 13:57:01.530886 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 13:57:01.534390 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 13:57:01.537566 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 13:57:01.542119 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 13:57:01.547479 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 13:57:01.550769 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 13:57:01.554140 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 13:57:01.561234 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 13:57:01.564076 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 13:57:01.567322 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3896 13:57:01.574430 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3897 13:57:01.577945 Total UI for P1: 0, mck2ui 16
3898 13:57:01.580236 best dqsien dly found for B0: ( 0, 9, 6)
3899 13:57:01.584445 Total UI for P1: 0, mck2ui 16
3900 13:57:01.587109 best dqsien dly found for B1: ( 0, 9, 6)
3901 13:57:01.590789 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3902 13:57:01.593860 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
3903 13:57:01.593943
3904 13:57:01.597046 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3905 13:57:01.600626 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
3906 13:57:01.604445 [Gating] SW calibration Done
3907 13:57:01.604527 ==
3908 13:57:01.606686 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 13:57:01.610421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3910 13:57:01.610504 ==
3911 13:57:01.613796 RX Vref Scan: 0
3912 13:57:01.613881
3913 13:57:01.613947 RX Vref 0 -> 0, step: 1
3914 13:57:01.616679
3915 13:57:01.616812 RX Delay -230 -> 252, step: 16
3916 13:57:01.624054 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3917 13:57:01.626821 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3918 13:57:01.630055 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3919 13:57:01.633522 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3920 13:57:01.640083 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3921 13:57:01.644146 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3922 13:57:01.646796 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3923 13:57:01.650843 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3924 13:57:01.653020 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3925 13:57:01.659800 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3926 13:57:01.663395 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3927 13:57:01.666672 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3928 13:57:01.669975 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3929 13:57:01.676687 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3930 13:57:01.679754 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3931 13:57:01.683279 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3932 13:57:01.683366 ==
3933 13:57:01.686421 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 13:57:01.693772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3935 13:57:01.693855 ==
3936 13:57:01.693921 DQS Delay:
3937 13:57:01.693982 DQS0 = 0, DQS1 = 0
3938 13:57:01.696854 DQM Delay:
3939 13:57:01.696929 DQM0 = 40, DQM1 = 33
3940 13:57:01.699148 DQ Delay:
3941 13:57:01.703169 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =33
3942 13:57:01.705966 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3943 13:57:01.709601 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3944 13:57:01.712720 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3945 13:57:01.712797
3946 13:57:01.712860
3947 13:57:01.712925 ==
3948 13:57:01.716220 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 13:57:01.719397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 13:57:01.719501 ==
3951 13:57:01.719604
3952 13:57:01.719692
3953 13:57:01.722849 TX Vref Scan disable
3954 13:57:01.722922 == TX Byte 0 ==
3955 13:57:01.729199 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3956 13:57:01.732512 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3957 13:57:01.732587 == TX Byte 1 ==
3958 13:57:01.739013 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3959 13:57:01.742526 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3960 13:57:01.742609 ==
3961 13:57:01.745983 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 13:57:01.750284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3963 13:57:01.750367 ==
3964 13:57:01.750431
3965 13:57:01.750492
3966 13:57:01.752237 TX Vref Scan disable
3967 13:57:01.757408 == TX Byte 0 ==
3968 13:57:01.758951 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3969 13:57:01.762373 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3970 13:57:01.766047 == TX Byte 1 ==
3971 13:57:01.769091 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3972 13:57:01.775665 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3973 13:57:01.775749
3974 13:57:01.775813 [DATLAT]
3975 13:57:01.775874 Freq=600, CH0 RK0
3976 13:57:01.775933
3977 13:57:01.779119 DATLAT Default: 0x9
3978 13:57:01.779202 0, 0xFFFF, sum = 0
3979 13:57:01.782333 1, 0xFFFF, sum = 0
3980 13:57:01.782416 2, 0xFFFF, sum = 0
3981 13:57:01.786213 3, 0xFFFF, sum = 0
3982 13:57:01.789274 4, 0xFFFF, sum = 0
3983 13:57:01.789356 5, 0xFFFF, sum = 0
3984 13:57:01.792318 6, 0xFFFF, sum = 0
3985 13:57:01.792400 7, 0x0, sum = 1
3986 13:57:01.792467 8, 0x0, sum = 2
3987 13:57:01.795791 9, 0x0, sum = 3
3988 13:57:01.795874 10, 0x0, sum = 4
3989 13:57:01.800001 best_step = 8
3990 13:57:01.800082
3991 13:57:01.800147 ==
3992 13:57:01.802204 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 13:57:01.805625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3994 13:57:01.805707 ==
3995 13:57:01.809166 RX Vref Scan: 1
3996 13:57:01.809247
3997 13:57:01.809312 RX Vref 0 -> 0, step: 1
3998 13:57:01.809373
3999 13:57:01.812678 RX Delay -195 -> 252, step: 8
4000 13:57:01.812780
4001 13:57:01.815381 Set Vref, RX VrefLevel [Byte0]: 47
4002 13:57:01.819929 [Byte1]: 49
4003 13:57:01.822808
4004 13:57:01.822888 Final RX Vref Byte 0 = 47 to rank0
4005 13:57:01.826749 Final RX Vref Byte 1 = 49 to rank0
4006 13:57:01.829551 Final RX Vref Byte 0 = 47 to rank1
4007 13:57:01.833193 Final RX Vref Byte 1 = 49 to rank1==
4008 13:57:01.835895 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 13:57:01.842853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4010 13:57:01.842937 ==
4011 13:57:01.843002 DQS Delay:
4012 13:57:01.843062 DQS0 = 0, DQS1 = 0
4013 13:57:01.846090 DQM Delay:
4014 13:57:01.846171 DQM0 = 41, DQM1 = 30
4015 13:57:01.849621 DQ Delay:
4016 13:57:01.852632 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4017 13:57:01.856979 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4018 13:57:01.859815 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4019 13:57:01.862984 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4020 13:57:01.863066
4021 13:57:01.863132
4022 13:57:01.868851 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4023 13:57:01.872926 CH0 RK0: MR19=808, MR18=5151
4024 13:57:01.879050 CH0_RK0: MR19=0x808, MR18=0x5151, DQSOSC=394, MR23=63, INC=168, DEC=112
4025 13:57:01.879135
4026 13:57:01.882163 ----->DramcWriteLeveling(PI) begin...
4027 13:57:01.882247 ==
4028 13:57:01.886080 Dram Type= 6, Freq= 0, CH_0, rank 1
4029 13:57:01.889313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4030 13:57:01.889396 ==
4031 13:57:01.892588 Write leveling (Byte 0): 31 => 31
4032 13:57:01.895834 Write leveling (Byte 1): 31 => 31
4033 13:57:01.898938 DramcWriteLeveling(PI) end<-----
4034 13:57:01.899021
4035 13:57:01.899086 ==
4036 13:57:01.902341 Dram Type= 6, Freq= 0, CH_0, rank 1
4037 13:57:01.905897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4038 13:57:01.905980 ==
4039 13:57:01.908661 [Gating] SW mode calibration
4040 13:57:01.915315 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4041 13:57:01.922143 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4042 13:57:01.925452 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 13:57:01.932121 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 13:57:01.935318 0 5 8 | B1->B0 | 3333 2f2f | 0 1 | (0 1) (0 0)
4045 13:57:01.938616 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 13:57:01.945165 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 13:57:01.948568 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 13:57:01.952447 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 13:57:01.958316 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 13:57:01.962557 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 13:57:01.965505 0 6 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4052 13:57:01.972124 0 6 8 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (0 0)
4053 13:57:01.975324 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 13:57:01.978163 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 13:57:01.985603 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 13:57:01.988279 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 13:57:01.992199 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 13:57:01.998038 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 13:57:02.001427 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 13:57:02.004723 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4061 13:57:02.012390 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4062 13:57:02.014624 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 13:57:02.017757 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:57:02.024998 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:57:02.027948 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 13:57:02.032004 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 13:57:02.034422 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 13:57:02.041297 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 13:57:02.044518 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 13:57:02.047690 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:57:02.054763 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:57:02.057918 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:57:02.061356 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 13:57:02.068107 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 13:57:02.071425 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 13:57:02.076419 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4077 13:57:02.081266 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 13:57:02.084506 Total UI for P1: 0, mck2ui 16
4079 13:57:02.087636 best dqsien dly found for B0: ( 0, 9, 8)
4080 13:57:02.087719 Total UI for P1: 0, mck2ui 16
4081 13:57:02.094015 best dqsien dly found for B1: ( 0, 9, 8)
4082 13:57:02.097653 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4083 13:57:02.101019 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4084 13:57:02.101101
4085 13:57:02.104214 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4086 13:57:02.107570 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4087 13:57:02.111141 [Gating] SW calibration Done
4088 13:57:02.111223 ==
4089 13:57:02.114177 Dram Type= 6, Freq= 0, CH_0, rank 1
4090 13:57:02.117375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4091 13:57:02.117458 ==
4092 13:57:02.121078 RX Vref Scan: 0
4093 13:57:02.121160
4094 13:57:02.121225 RX Vref 0 -> 0, step: 1
4095 13:57:02.121285
4096 13:57:02.124372 RX Delay -230 -> 252, step: 16
4097 13:57:02.131103 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4098 13:57:02.133912 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4099 13:57:02.137081 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4100 13:57:02.141121 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4101 13:57:02.144129 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4102 13:57:02.150978 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4103 13:57:02.154134 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4104 13:57:02.157315 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4105 13:57:02.160636 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4106 13:57:02.167186 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4107 13:57:02.170751 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4108 13:57:02.173943 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4109 13:57:02.176787 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4110 13:57:02.183437 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4111 13:57:02.187368 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4112 13:57:02.191546 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4113 13:57:02.191629 ==
4114 13:57:02.193490 Dram Type= 6, Freq= 0, CH_0, rank 1
4115 13:57:02.196851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4116 13:57:02.196937 ==
4117 13:57:02.200855 DQS Delay:
4118 13:57:02.200938 DQS0 = 0, DQS1 = 0
4119 13:57:02.203886 DQM Delay:
4120 13:57:02.203968 DQM0 = 41, DQM1 = 33
4121 13:57:02.204033 DQ Delay:
4122 13:57:02.206675 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4123 13:57:02.209908 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4124 13:57:02.213422 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4125 13:57:02.216755 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4126 13:57:02.216837
4127 13:57:02.220050
4128 13:57:02.220132 ==
4129 13:57:02.223354 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 13:57:02.227079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4131 13:57:02.227221 ==
4132 13:57:02.227340
4133 13:57:02.227399
4134 13:57:02.229936 TX Vref Scan disable
4135 13:57:02.230017 == TX Byte 0 ==
4136 13:57:02.236591 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4137 13:57:02.239630 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4138 13:57:02.239712 == TX Byte 1 ==
4139 13:57:02.246210 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4140 13:57:02.249687 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4141 13:57:02.249768 ==
4142 13:57:02.253688 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 13:57:02.256922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4144 13:57:02.257012 ==
4145 13:57:02.257077
4146 13:57:02.257137
4147 13:57:02.260335 TX Vref Scan disable
4148 13:57:02.263407 == TX Byte 0 ==
4149 13:57:02.266826 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4150 13:57:02.271467 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4151 13:57:02.273450 == TX Byte 1 ==
4152 13:57:02.277321 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4153 13:57:02.279630 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4154 13:57:02.279710
4155 13:57:02.282797 [DATLAT]
4156 13:57:02.282877 Freq=600, CH0 RK1
4157 13:57:02.282942
4158 13:57:02.286533 DATLAT Default: 0x8
4159 13:57:02.286614 0, 0xFFFF, sum = 0
4160 13:57:02.289341 1, 0xFFFF, sum = 0
4161 13:57:02.289423 2, 0xFFFF, sum = 0
4162 13:57:02.293781 3, 0xFFFF, sum = 0
4163 13:57:02.293863 4, 0xFFFF, sum = 0
4164 13:57:02.296172 5, 0xFFFF, sum = 0
4165 13:57:02.296254 6, 0xFFFF, sum = 0
4166 13:57:02.300015 7, 0x0, sum = 1
4167 13:57:02.300098 8, 0x0, sum = 2
4168 13:57:02.303622 9, 0x0, sum = 3
4169 13:57:02.303704 10, 0x0, sum = 4
4170 13:57:02.305746 best_step = 8
4171 13:57:02.305827
4172 13:57:02.305890 ==
4173 13:57:02.309414 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 13:57:02.312307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4175 13:57:02.312389 ==
4176 13:57:02.316150 RX Vref Scan: 0
4177 13:57:02.316234
4178 13:57:02.316298 RX Vref 0 -> 0, step: 1
4179 13:57:02.316358
4180 13:57:02.318881 RX Delay -195 -> 252, step: 8
4181 13:57:02.326055 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4182 13:57:02.330129 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4183 13:57:02.333010 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4184 13:57:02.336292 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4185 13:57:02.342524 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4186 13:57:02.346255 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4187 13:57:02.349440 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4188 13:57:02.352463 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4189 13:57:02.359451 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4190 13:57:02.362609 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4191 13:57:02.366107 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4192 13:57:02.370125 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4193 13:57:02.372673 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4194 13:57:02.379157 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4195 13:57:02.382850 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4196 13:57:02.386016 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4197 13:57:02.386099 ==
4198 13:57:02.389033 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 13:57:02.395665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4200 13:57:02.395748 ==
4201 13:57:02.395814 DQS Delay:
4202 13:57:02.395875 DQS0 = 0, DQS1 = 0
4203 13:57:02.400183 DQM Delay:
4204 13:57:02.400266 DQM0 = 41, DQM1 = 33
4205 13:57:02.402816 DQ Delay:
4206 13:57:02.405852 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4207 13:57:02.408838 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4208 13:57:02.413656 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4209 13:57:02.415269 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4210 13:57:02.415351
4211 13:57:02.415415
4212 13:57:02.421842 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4213 13:57:02.425578 CH0 RK1: MR19=808, MR18=6464
4214 13:57:02.432376 CH0_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4215 13:57:02.435200 [RxdqsGatingPostProcess] freq 600
4216 13:57:02.438973 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4217 13:57:02.442230 Pre-setting of DQS Precalculation
4218 13:57:02.448082 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4219 13:57:02.448164 ==
4220 13:57:02.452162 Dram Type= 6, Freq= 0, CH_1, rank 0
4221 13:57:02.454791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4222 13:57:02.454872 ==
4223 13:57:02.461756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4224 13:57:02.469329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4225 13:57:02.471997 [CA 0] Center 35 (5~66) winsize 62
4226 13:57:02.475517 [CA 1] Center 35 (5~66) winsize 62
4227 13:57:02.479162 [CA 2] Center 33 (3~64) winsize 62
4228 13:57:02.481798 [CA 3] Center 33 (3~64) winsize 62
4229 13:57:02.485604 [CA 4] Center 33 (2~64) winsize 63
4230 13:57:02.488278 [CA 5] Center 33 (2~64) winsize 63
4231 13:57:02.488360
4232 13:57:02.492093 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4233 13:57:02.492175
4234 13:57:02.494654 [CATrainingPosCal] consider 1 rank data
4235 13:57:02.497920 u2DelayCellTimex100 = 270/100 ps
4236 13:57:02.501494 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4237 13:57:02.504690 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4238 13:57:02.509057 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4239 13:57:02.512866 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4240 13:57:02.515991 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4241 13:57:02.518188 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4242 13:57:02.518269
4243 13:57:02.524633 CA PerBit enable=1, Macro0, CA PI delay=33
4244 13:57:02.524726
4245 13:57:02.524795 [CBTSetCACLKResult] CA Dly = 33
4246 13:57:02.528574 CS Dly: 4 (0~35)
4247 13:57:02.528656 ==
4248 13:57:02.531282 Dram Type= 6, Freq= 0, CH_1, rank 1
4249 13:57:02.535115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4250 13:57:02.535198 ==
4251 13:57:02.541353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4252 13:57:02.547980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4253 13:57:02.551519 [CA 0] Center 35 (5~66) winsize 62
4254 13:57:02.554471 [CA 1] Center 34 (4~65) winsize 62
4255 13:57:02.557337 [CA 2] Center 33 (3~64) winsize 62
4256 13:57:02.560827 [CA 3] Center 33 (3~64) winsize 62
4257 13:57:02.564340 [CA 4] Center 32 (2~63) winsize 62
4258 13:57:02.567381 [CA 5] Center 32 (2~63) winsize 62
4259 13:57:02.567463
4260 13:57:02.570911 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4261 13:57:02.570993
4262 13:57:02.574119 [CATrainingPosCal] consider 2 rank data
4263 13:57:02.578044 u2DelayCellTimex100 = 270/100 ps
4264 13:57:02.580681 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4265 13:57:02.584012 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4266 13:57:02.587389 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4267 13:57:02.592371 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4268 13:57:02.594591 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4269 13:57:02.601016 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4270 13:57:02.601098
4271 13:57:02.604440 CA PerBit enable=1, Macro0, CA PI delay=32
4272 13:57:02.604522
4273 13:57:02.607190 [CBTSetCACLKResult] CA Dly = 32
4274 13:57:02.607273 CS Dly: 4 (0~36)
4275 13:57:02.607338
4276 13:57:02.610471 ----->DramcWriteLeveling(PI) begin...
4277 13:57:02.610555 ==
4278 13:57:02.613932 Dram Type= 6, Freq= 0, CH_1, rank 0
4279 13:57:02.623582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4280 13:57:02.623669 ==
4281 13:57:02.623920 Write leveling (Byte 0): 29 => 29
4282 13:57:02.623990 Write leveling (Byte 1): 28 => 28
4283 13:57:02.627338 DramcWriteLeveling(PI) end<-----
4284 13:57:02.627418
4285 13:57:02.627482 ==
4286 13:57:02.630392 Dram Type= 6, Freq= 0, CH_1, rank 0
4287 13:57:02.636956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4288 13:57:02.637037 ==
4289 13:57:02.640384 [Gating] SW mode calibration
4290 13:57:02.648361 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4291 13:57:02.650503 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4292 13:57:02.656950 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4293 13:57:02.660446 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4294 13:57:02.664063 0 5 8 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4295 13:57:02.670740 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4296 13:57:02.673924 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 13:57:02.676946 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4298 13:57:02.683486 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4299 13:57:02.687183 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4300 13:57:02.690826 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4301 13:57:02.694049 0 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4302 13:57:02.700111 0 6 8 | B1->B0 | 3636 4343 | 0 0 | (1 1) (0 0)
4303 13:57:02.703681 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 13:57:02.708139 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 13:57:02.713612 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 13:57:02.716973 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 13:57:02.720422 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4308 13:57:02.728017 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 13:57:02.732215 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4310 13:57:02.733491 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4311 13:57:02.739938 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4312 13:57:02.743342 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 13:57:02.747022 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 13:57:02.753737 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 13:57:02.756446 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 13:57:02.760061 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 13:57:02.766764 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 13:57:02.769737 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 13:57:02.772989 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 13:57:02.779944 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 13:57:02.783424 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 13:57:02.786931 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 13:57:02.793598 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 13:57:02.796534 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 13:57:02.799318 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4326 13:57:02.807155 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4327 13:57:02.807238 Total UI for P1: 0, mck2ui 16
4328 13:57:02.812842 best dqsien dly found for B0: ( 0, 9, 4)
4329 13:57:02.817124 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4330 13:57:02.820049 Total UI for P1: 0, mck2ui 16
4331 13:57:02.822879 best dqsien dly found for B1: ( 0, 9, 8)
4332 13:57:02.826046 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4333 13:57:02.829785 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4334 13:57:02.829866
4335 13:57:02.833263 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4336 13:57:02.838628 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4337 13:57:02.839125 [Gating] SW calibration Done
4338 13:57:02.839205 ==
4339 13:57:02.842668 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 13:57:02.845726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4341 13:57:02.848964 ==
4342 13:57:02.849046 RX Vref Scan: 0
4343 13:57:02.849110
4344 13:57:02.852916 RX Vref 0 -> 0, step: 1
4345 13:57:02.852997
4346 13:57:02.855754 RX Delay -230 -> 252, step: 16
4347 13:57:02.859663 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4348 13:57:02.862252 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4349 13:57:02.865798 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4350 13:57:02.872288 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4351 13:57:02.876262 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4352 13:57:02.879294 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4353 13:57:02.882381 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4354 13:57:02.886033 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4355 13:57:02.892294 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4356 13:57:02.895229 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4357 13:57:02.898823 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4358 13:57:02.902195 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4359 13:57:02.908623 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4360 13:57:02.913047 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4361 13:57:02.914930 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4362 13:57:02.918868 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4363 13:57:02.918948 ==
4364 13:57:02.922271 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 13:57:02.928561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 13:57:02.928642 ==
4367 13:57:02.928712 DQS Delay:
4368 13:57:02.931705 DQS0 = 0, DQS1 = 0
4369 13:57:02.931785 DQM Delay:
4370 13:57:02.936536 DQM0 = 39, DQM1 = 32
4371 13:57:02.936617 DQ Delay:
4372 13:57:02.938903 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4373 13:57:02.943221 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4374 13:57:02.944859 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4375 13:57:02.947945 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4376 13:57:02.948025
4377 13:57:02.948088
4378 13:57:02.948147 ==
4379 13:57:02.951950 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 13:57:02.955164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4381 13:57:02.955247 ==
4382 13:57:02.955311
4383 13:57:02.955370
4384 13:57:02.957928 TX Vref Scan disable
4385 13:57:02.961166 == TX Byte 0 ==
4386 13:57:02.965956 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4387 13:57:02.967875 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4388 13:57:02.971525 == TX Byte 1 ==
4389 13:57:02.974448 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4390 13:57:02.977846 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4391 13:57:02.977929 ==
4392 13:57:02.981698 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 13:57:02.988257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4394 13:57:02.988341 ==
4395 13:57:02.988406
4396 13:57:02.988467
4397 13:57:02.988525 TX Vref Scan disable
4398 13:57:02.991931 == TX Byte 0 ==
4399 13:57:02.995253 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4400 13:57:03.002135 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4401 13:57:03.002221 == TX Byte 1 ==
4402 13:57:03.007575 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4403 13:57:03.011824 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4404 13:57:03.011906
4405 13:57:03.011971 [DATLAT]
4406 13:57:03.012032 Freq=600, CH1 RK0
4407 13:57:03.012090
4408 13:57:03.014922 DATLAT Default: 0x9
4409 13:57:03.015003 0, 0xFFFF, sum = 0
4410 13:57:03.019057 1, 0xFFFF, sum = 0
4411 13:57:03.021531 2, 0xFFFF, sum = 0
4412 13:57:03.021614 3, 0xFFFF, sum = 0
4413 13:57:03.024905 4, 0xFFFF, sum = 0
4414 13:57:03.024987 5, 0xFFFF, sum = 0
4415 13:57:03.028221 6, 0xFFFF, sum = 0
4416 13:57:03.028303 7, 0x0, sum = 1
4417 13:57:03.028369 8, 0x0, sum = 2
4418 13:57:03.031446 9, 0x0, sum = 3
4419 13:57:03.031530 10, 0x0, sum = 4
4420 13:57:03.035552 best_step = 8
4421 13:57:03.035634
4422 13:57:03.035699 ==
4423 13:57:03.038163 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 13:57:03.041603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4425 13:57:03.041703 ==
4426 13:57:03.045530 RX Vref Scan: 1
4427 13:57:03.045612
4428 13:57:03.045676 RX Vref 0 -> 0, step: 1
4429 13:57:03.045736
4430 13:57:03.047987 RX Delay -195 -> 252, step: 8
4431 13:57:03.048068
4432 13:57:03.051452 Set Vref, RX VrefLevel [Byte0]: 50
4433 13:57:03.055230 [Byte1]: 49
4434 13:57:03.059085
4435 13:57:03.059166 Final RX Vref Byte 0 = 50 to rank0
4436 13:57:03.062342 Final RX Vref Byte 1 = 49 to rank0
4437 13:57:03.066604 Final RX Vref Byte 0 = 50 to rank1
4438 13:57:03.068958 Final RX Vref Byte 1 = 49 to rank1==
4439 13:57:03.072845 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 13:57:03.079157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4441 13:57:03.079240 ==
4442 13:57:03.079305 DQS Delay:
4443 13:57:03.079365 DQS0 = 0, DQS1 = 0
4444 13:57:03.082736 DQM Delay:
4445 13:57:03.082817 DQM0 = 36, DQM1 = 30
4446 13:57:03.085488 DQ Delay:
4447 13:57:03.088896 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4448 13:57:03.091993 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4449 13:57:03.095559 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4450 13:57:03.098789 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4451 13:57:03.098871
4452 13:57:03.098935
4453 13:57:03.105513 [DQSOSCAuto] RK0, (LSB)MR18= 0x7878, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4454 13:57:03.109235 CH1 RK0: MR19=808, MR18=7878
4455 13:57:03.115561 CH1_RK0: MR19=0x808, MR18=0x7878, DQSOSC=387, MR23=63, INC=175, DEC=116
4456 13:57:03.115644
4457 13:57:03.118823 ----->DramcWriteLeveling(PI) begin...
4458 13:57:03.118910 ==
4459 13:57:03.122070 Dram Type= 6, Freq= 0, CH_1, rank 1
4460 13:57:03.125082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4461 13:57:03.125165 ==
4462 13:57:03.129082 Write leveling (Byte 0): 25 => 25
4463 13:57:03.132025 Write leveling (Byte 1): 25 => 25
4464 13:57:03.135130 DramcWriteLeveling(PI) end<-----
4465 13:57:03.135213
4466 13:57:03.135278 ==
4467 13:57:03.138458 Dram Type= 6, Freq= 0, CH_1, rank 1
4468 13:57:03.141983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4469 13:57:03.142069 ==
4470 13:57:03.145153 [Gating] SW mode calibration
4471 13:57:03.153361 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4472 13:57:03.158616 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4473 13:57:03.161567 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 13:57:03.168777 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4475 13:57:03.171651 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4476 13:57:03.175404 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 13:57:03.181258 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 13:57:03.184865 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 13:57:03.188096 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 13:57:03.194963 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 13:57:03.198725 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 13:57:03.202190 0 6 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
4483 13:57:03.207971 0 6 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4484 13:57:03.211078 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 13:57:03.214651 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 13:57:03.221280 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 13:57:03.225053 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 13:57:03.228189 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 13:57:03.234231 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4490 13:57:03.238755 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 13:57:03.241079 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4492 13:57:03.248006 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 13:57:03.251358 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 13:57:03.254840 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 13:57:03.261481 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 13:57:03.264693 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 13:57:03.267749 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 13:57:03.271226 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 13:57:03.277273 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 13:57:03.280736 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 13:57:03.287315 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 13:57:03.291354 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 13:57:03.293950 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 13:57:03.297457 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:57:03.304021 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4506 13:57:03.307486 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4507 13:57:03.310382 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4508 13:57:03.317207 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 13:57:03.320431 Total UI for P1: 0, mck2ui 16
4510 13:57:03.323967 best dqsien dly found for B0: ( 0, 9, 4)
4511 13:57:03.327410 Total UI for P1: 0, mck2ui 16
4512 13:57:03.330781 best dqsien dly found for B1: ( 0, 9, 10)
4513 13:57:03.334259 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4514 13:57:03.336756 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4515 13:57:03.336838
4516 13:57:03.340279 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4517 13:57:03.343505 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4518 13:57:03.346709 [Gating] SW calibration Done
4519 13:57:03.346792 ==
4520 13:57:03.350367 Dram Type= 6, Freq= 0, CH_1, rank 1
4521 13:57:03.353636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4522 13:57:03.353720 ==
4523 13:57:03.357681 RX Vref Scan: 0
4524 13:57:03.357764
4525 13:57:03.360428 RX Vref 0 -> 0, step: 1
4526 13:57:03.360536
4527 13:57:03.360629 RX Delay -230 -> 252, step: 16
4528 13:57:03.366423 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4529 13:57:03.369625 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4530 13:57:03.373375 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4531 13:57:03.376691 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4532 13:57:03.383074 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4533 13:57:03.386445 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4534 13:57:03.389981 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4535 13:57:03.393979 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4536 13:57:03.396408 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4537 13:57:03.402745 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4538 13:57:03.406277 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4539 13:57:03.409300 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4540 13:57:03.413161 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4541 13:57:03.420216 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4542 13:57:03.422679 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4543 13:57:03.426357 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4544 13:57:03.426439 ==
4545 13:57:03.429159 Dram Type= 6, Freq= 0, CH_1, rank 1
4546 13:57:03.436275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4547 13:57:03.436358 ==
4548 13:57:03.436423 DQS Delay:
4549 13:57:03.436484 DQS0 = 0, DQS1 = 0
4550 13:57:03.439093 DQM Delay:
4551 13:57:03.439175 DQM0 = 39, DQM1 = 33
4552 13:57:03.442811 DQ Delay:
4553 13:57:03.446168 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4554 13:57:03.449246 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4555 13:57:03.452116 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4556 13:57:03.455715 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4557 13:57:03.455797
4558 13:57:03.455862
4559 13:57:03.455922 ==
4560 13:57:03.459271 Dram Type= 6, Freq= 0, CH_1, rank 1
4561 13:57:03.462868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4562 13:57:03.462951 ==
4563 13:57:03.463017
4564 13:57:03.463076
4565 13:57:03.465692 TX Vref Scan disable
4566 13:57:03.465774 == TX Byte 0 ==
4567 13:57:03.472481 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4568 13:57:03.476260 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4569 13:57:03.476342 == TX Byte 1 ==
4570 13:57:03.483093 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4571 13:57:03.486053 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4572 13:57:03.486135 ==
4573 13:57:03.488603 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 13:57:03.492204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4575 13:57:03.492287 ==
4576 13:57:03.492352
4577 13:57:03.495576
4578 13:57:03.495657 TX Vref Scan disable
4579 13:57:03.498783 == TX Byte 0 ==
4580 13:57:03.502500 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4581 13:57:03.505547 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4582 13:57:03.509002 == TX Byte 1 ==
4583 13:57:03.512288 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4584 13:57:03.519063 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4585 13:57:03.519174
4586 13:57:03.519271 [DATLAT]
4587 13:57:03.519362 Freq=600, CH1 RK1
4588 13:57:03.519452
4589 13:57:03.522801 DATLAT Default: 0x8
4590 13:57:03.522903 0, 0xFFFF, sum = 0
4591 13:57:03.525517 1, 0xFFFF, sum = 0
4592 13:57:03.529565 2, 0xFFFF, sum = 0
4593 13:57:03.529650 3, 0xFFFF, sum = 0
4594 13:57:03.532052 4, 0xFFFF, sum = 0
4595 13:57:03.532138 5, 0xFFFF, sum = 0
4596 13:57:03.535284 6, 0xFFFF, sum = 0
4597 13:57:03.535371 7, 0x0, sum = 1
4598 13:57:03.535439 8, 0x0, sum = 2
4599 13:57:03.538746 9, 0x0, sum = 3
4600 13:57:03.538831 10, 0x0, sum = 4
4601 13:57:03.542178 best_step = 8
4602 13:57:03.542338
4603 13:57:03.542446 ==
4604 13:57:03.545368 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 13:57:03.548652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4606 13:57:03.548798 ==
4607 13:57:03.552730 RX Vref Scan: 0
4608 13:57:03.552831
4609 13:57:03.552918 RX Vref 0 -> 0, step: 1
4610 13:57:03.553003
4611 13:57:03.555230 RX Delay -195 -> 252, step: 8
4612 13:57:03.562704 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4613 13:57:03.565974 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4614 13:57:03.568588 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4615 13:57:03.572513 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4616 13:57:03.579068 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4617 13:57:03.583191 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4618 13:57:03.587034 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4619 13:57:03.590663 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4620 13:57:03.596016 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4621 13:57:03.598521 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4622 13:57:03.601995 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4623 13:57:03.605177 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4624 13:57:03.612021 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4625 13:57:03.615925 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4626 13:57:03.619403 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4627 13:57:03.622046 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4628 13:57:03.622128 ==
4629 13:57:03.624978 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 13:57:03.631476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4631 13:57:03.631563 ==
4632 13:57:03.631629 DQS Delay:
4633 13:57:03.634892 DQS0 = 0, DQS1 = 0
4634 13:57:03.634974 DQM Delay:
4635 13:57:03.635039 DQM0 = 37, DQM1 = 29
4636 13:57:03.638258 DQ Delay:
4637 13:57:03.641975 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4638 13:57:03.645557 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4639 13:57:03.648176 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4640 13:57:03.651322 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4641 13:57:03.651405
4642 13:57:03.651468
4643 13:57:03.658287 [DQSOSCAuto] RK1, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4644 13:57:03.663026 CH1 RK1: MR19=808, MR18=5454
4645 13:57:03.668140 CH1_RK1: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4646 13:57:03.671339 [RxdqsGatingPostProcess] freq 600
4647 13:57:03.674923 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4648 13:57:03.677965 Pre-setting of DQS Precalculation
4649 13:57:03.684574 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4650 13:57:03.691184 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4651 13:57:03.698135 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4652 13:57:03.698231
4653 13:57:03.698298
4654 13:57:03.701469 [Calibration Summary] 1200 Mbps
4655 13:57:03.704271 CH 0, Rank 0
4656 13:57:03.704353 SW Impedance : PASS
4657 13:57:03.708149 DUTY Scan : NO K
4658 13:57:03.708231 ZQ Calibration : PASS
4659 13:57:03.711161 Jitter Meter : NO K
4660 13:57:03.714401 CBT Training : PASS
4661 13:57:03.714484 Write leveling : PASS
4662 13:57:03.718322 RX DQS gating : PASS
4663 13:57:03.720822 RX DQ/DQS(RDDQC) : PASS
4664 13:57:03.720905 TX DQ/DQS : PASS
4665 13:57:03.724836 RX DATLAT : PASS
4666 13:57:03.728352 RX DQ/DQS(Engine): PASS
4667 13:57:03.728437 TX OE : NO K
4668 13:57:03.730840 All Pass.
4669 13:57:03.730922
4670 13:57:03.730987 CH 0, Rank 1
4671 13:57:03.734260 SW Impedance : PASS
4672 13:57:03.734342 DUTY Scan : NO K
4673 13:57:03.738311 ZQ Calibration : PASS
4674 13:57:03.740934 Jitter Meter : NO K
4675 13:57:03.741016 CBT Training : PASS
4676 13:57:03.745142 Write leveling : PASS
4677 13:57:03.747436 RX DQS gating : PASS
4678 13:57:03.747518 RX DQ/DQS(RDDQC) : PASS
4679 13:57:03.751084 TX DQ/DQS : PASS
4680 13:57:03.754455 RX DATLAT : PASS
4681 13:57:03.754538 RX DQ/DQS(Engine): PASS
4682 13:57:03.757477 TX OE : NO K
4683 13:57:03.757559 All Pass.
4684 13:57:03.757624
4685 13:57:03.761041 CH 1, Rank 0
4686 13:57:03.761127 SW Impedance : PASS
4687 13:57:03.764160 DUTY Scan : NO K
4688 13:57:03.767216 ZQ Calibration : PASS
4689 13:57:03.767300 Jitter Meter : NO K
4690 13:57:03.770468 CBT Training : PASS
4691 13:57:03.770550 Write leveling : PASS
4692 13:57:03.773736 RX DQS gating : PASS
4693 13:57:03.777153 RX DQ/DQS(RDDQC) : PASS
4694 13:57:03.777235 TX DQ/DQS : PASS
4695 13:57:03.780398 RX DATLAT : PASS
4696 13:57:03.783897 RX DQ/DQS(Engine): PASS
4697 13:57:03.783980 TX OE : NO K
4698 13:57:03.787354 All Pass.
4699 13:57:03.787437
4700 13:57:03.787502 CH 1, Rank 1
4701 13:57:03.790371 SW Impedance : PASS
4702 13:57:03.790454 DUTY Scan : NO K
4703 13:57:03.793647 ZQ Calibration : PASS
4704 13:57:03.797490 Jitter Meter : NO K
4705 13:57:03.797572 CBT Training : PASS
4706 13:57:03.802289 Write leveling : PASS
4707 13:57:03.804269 RX DQS gating : PASS
4708 13:57:03.804351 RX DQ/DQS(RDDQC) : PASS
4709 13:57:03.807811 TX DQ/DQS : PASS
4710 13:57:03.810113 RX DATLAT : PASS
4711 13:57:03.810194 RX DQ/DQS(Engine): PASS
4712 13:57:03.813191 TX OE : NO K
4713 13:57:03.813273 All Pass.
4714 13:57:03.813338
4715 13:57:03.816946 DramC Write-DBI off
4716 13:57:03.820229 PER_BANK_REFRESH: Hybrid Mode
4717 13:57:03.820311 TX_TRACKING: ON
4718 13:57:03.829809 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4719 13:57:03.833443 [FAST_K] Save calibration result to emmc
4720 13:57:03.836886 dramc_set_vcore_voltage set vcore to 662500
4721 13:57:03.840378 Read voltage for 933, 3
4722 13:57:03.840458 Vio18 = 0
4723 13:57:03.840521 Vcore = 662500
4724 13:57:03.843074 Vdram = 0
4725 13:57:03.843155 Vddq = 0
4726 13:57:03.843218 Vmddr = 0
4727 13:57:03.850591 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4728 13:57:03.853182 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4729 13:57:03.856822 MEM_TYPE=3, freq_sel=17
4730 13:57:03.861608 sv_algorithm_assistance_LP4_1600
4731 13:57:03.863404 ============ PULL DRAM RESETB DOWN ============
4732 13:57:03.866406 ========== PULL DRAM RESETB DOWN end =========
4733 13:57:03.872972 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4734 13:57:03.876498 ===================================
4735 13:57:03.879383 LPDDR4 DRAM CONFIGURATION
4736 13:57:03.883014 ===================================
4737 13:57:03.883096 EX_ROW_EN[0] = 0x0
4738 13:57:03.886202 EX_ROW_EN[1] = 0x0
4739 13:57:03.886284 LP4Y_EN = 0x0
4740 13:57:03.889745 WORK_FSP = 0x0
4741 13:57:03.889825 WL = 0x3
4742 13:57:03.892397 RL = 0x3
4743 13:57:03.892477 BL = 0x2
4744 13:57:03.896199 RPST = 0x0
4745 13:57:03.896279 RD_PRE = 0x0
4746 13:57:03.900534 WR_PRE = 0x1
4747 13:57:03.900640 WR_PST = 0x0
4748 13:57:03.902546 DBI_WR = 0x0
4749 13:57:03.902629 DBI_RD = 0x0
4750 13:57:03.906648 OTF = 0x1
4751 13:57:03.909846 ===================================
4752 13:57:03.914023 ===================================
4753 13:57:03.914104 ANA top config
4754 13:57:03.916016 ===================================
4755 13:57:03.919520 DLL_ASYNC_EN = 0
4756 13:57:03.923255 ALL_SLAVE_EN = 1
4757 13:57:03.925470 NEW_RANK_MODE = 1
4758 13:57:03.925552 DLL_IDLE_MODE = 1
4759 13:57:03.929615 LP45_APHY_COMB_EN = 1
4760 13:57:03.932342 TX_ODT_DIS = 1
4761 13:57:03.935595 NEW_8X_MODE = 1
4762 13:57:03.939024 ===================================
4763 13:57:03.942312 ===================================
4764 13:57:03.945819 data_rate = 1866
4765 13:57:03.948784 CKR = 1
4766 13:57:03.948865 DQ_P2S_RATIO = 8
4767 13:57:03.952239 ===================================
4768 13:57:03.955907 CA_P2S_RATIO = 8
4769 13:57:03.959352 DQ_CA_OPEN = 0
4770 13:57:03.962158 DQ_SEMI_OPEN = 0
4771 13:57:03.966172 CA_SEMI_OPEN = 0
4772 13:57:03.966254 CA_FULL_RATE = 0
4773 13:57:03.969954 DQ_CKDIV4_EN = 1
4774 13:57:03.972160 CA_CKDIV4_EN = 1
4775 13:57:03.975479 CA_PREDIV_EN = 0
4776 13:57:03.978830 PH8_DLY = 0
4777 13:57:03.981906 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4778 13:57:03.981988 DQ_AAMCK_DIV = 4
4779 13:57:03.985553 CA_AAMCK_DIV = 4
4780 13:57:03.988744 CA_ADMCK_DIV = 4
4781 13:57:03.993090 DQ_TRACK_CA_EN = 0
4782 13:57:03.995934 CA_PICK = 933
4783 13:57:03.998959 CA_MCKIO = 933
4784 13:57:04.002049 MCKIO_SEMI = 0
4785 13:57:04.005754 PLL_FREQ = 3732
4786 13:57:04.005836 DQ_UI_PI_RATIO = 32
4787 13:57:04.009074 CA_UI_PI_RATIO = 0
4788 13:57:04.012158 ===================================
4789 13:57:04.015584 ===================================
4790 13:57:04.019739 memory_type:LPDDR4
4791 13:57:04.022323 GP_NUM : 10
4792 13:57:04.022403 SRAM_EN : 1
4793 13:57:04.025330 MD32_EN : 0
4794 13:57:04.028522 ===================================
4795 13:57:04.028630 [ANA_INIT] >>>>>>>>>>>>>>
4796 13:57:04.031796 <<<<<< [CONFIGURE PHASE]: ANA_TX
4797 13:57:04.034815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4798 13:57:04.038347 ===================================
4799 13:57:04.041339 data_rate = 1866,PCW = 0X8f00
4800 13:57:04.044934 ===================================
4801 13:57:04.048051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4802 13:57:04.055311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4803 13:57:04.061911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4804 13:57:04.064848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4805 13:57:04.068099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4806 13:57:04.071367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4807 13:57:04.075258 [ANA_INIT] flow start
4808 13:57:04.075339 [ANA_INIT] PLL >>>>>>>>
4809 13:57:04.077923 [ANA_INIT] PLL <<<<<<<<
4810 13:57:04.081493 [ANA_INIT] MIDPI >>>>>>>>
4811 13:57:04.084135 [ANA_INIT] MIDPI <<<<<<<<
4812 13:57:04.084215 [ANA_INIT] DLL >>>>>>>>
4813 13:57:04.088945 [ANA_INIT] flow end
4814 13:57:04.091201 ============ LP4 DIFF to SE enter ============
4815 13:57:04.094103 ============ LP4 DIFF to SE exit ============
4816 13:57:04.097124 [ANA_INIT] <<<<<<<<<<<<<
4817 13:57:04.100410 [Flow] Enable top DCM control >>>>>
4818 13:57:04.104131 [Flow] Enable top DCM control <<<<<
4819 13:57:04.107237 Enable DLL master slave shuffle
4820 13:57:04.114600 ==============================================================
4821 13:57:04.114683 Gating Mode config
4822 13:57:04.120318 ==============================================================
4823 13:57:04.120400 Config description:
4824 13:57:04.131116 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4825 13:57:04.137740 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4826 13:57:04.143616 SELPH_MODE 0: By rank 1: By Phase
4827 13:57:04.147031 ==============================================================
4828 13:57:04.150583 GAT_TRACK_EN = 1
4829 13:57:04.153725 RX_GATING_MODE = 2
4830 13:57:04.156874 RX_GATING_TRACK_MODE = 2
4831 13:57:04.160886 SELPH_MODE = 1
4832 13:57:04.163816 PICG_EARLY_EN = 1
4833 13:57:04.167009 VALID_LAT_VALUE = 1
4834 13:57:04.173552 ==============================================================
4835 13:57:04.176879 Enter into Gating configuration >>>>
4836 13:57:04.180549 Exit from Gating configuration <<<<
4837 13:57:04.183909 Enter into DVFS_PRE_config >>>>>
4838 13:57:04.193207 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4839 13:57:04.196558 Exit from DVFS_PRE_config <<<<<
4840 13:57:04.199866 Enter into PICG configuration >>>>
4841 13:57:04.203036 Exit from PICG configuration <<<<
4842 13:57:04.206725 [RX_INPUT] configuration >>>>>
4843 13:57:04.206807 [RX_INPUT] configuration <<<<<
4844 13:57:04.213595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4845 13:57:04.219591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4846 13:57:04.226013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4847 13:57:04.229912 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4848 13:57:04.237988 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4849 13:57:04.243288 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4850 13:57:04.246231 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4851 13:57:04.249366 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4852 13:57:04.256097 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4853 13:57:04.259939 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4854 13:57:04.262260 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4855 13:57:04.269488 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4856 13:57:04.273139 ===================================
4857 13:57:04.273226 LPDDR4 DRAM CONFIGURATION
4858 13:57:04.275838 ===================================
4859 13:57:04.279282 EX_ROW_EN[0] = 0x0
4860 13:57:04.282203 EX_ROW_EN[1] = 0x0
4861 13:57:04.282287 LP4Y_EN = 0x0
4862 13:57:04.285855 WORK_FSP = 0x0
4863 13:57:04.285940 WL = 0x3
4864 13:57:04.289381 RL = 0x3
4865 13:57:04.289465 BL = 0x2
4866 13:57:04.292344 RPST = 0x0
4867 13:57:04.292429 RD_PRE = 0x0
4868 13:57:04.296612 WR_PRE = 0x1
4869 13:57:04.296728 WR_PST = 0x0
4870 13:57:04.298900 DBI_WR = 0x0
4871 13:57:04.298984 DBI_RD = 0x0
4872 13:57:04.302491 OTF = 0x1
4873 13:57:04.305723 ===================================
4874 13:57:04.308485 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4875 13:57:04.312237 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4876 13:57:04.319061 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4877 13:57:04.321912 ===================================
4878 13:57:04.321997 LPDDR4 DRAM CONFIGURATION
4879 13:57:04.325761 ===================================
4880 13:57:04.328958 EX_ROW_EN[0] = 0x10
4881 13:57:04.332099 EX_ROW_EN[1] = 0x0
4882 13:57:04.332182 LP4Y_EN = 0x0
4883 13:57:04.335160 WORK_FSP = 0x0
4884 13:57:04.335244 WL = 0x3
4885 13:57:04.338238 RL = 0x3
4886 13:57:04.338322 BL = 0x2
4887 13:57:04.341863 RPST = 0x0
4888 13:57:04.341946 RD_PRE = 0x0
4889 13:57:04.345062 WR_PRE = 0x1
4890 13:57:04.345146 WR_PST = 0x0
4891 13:57:04.348878 DBI_WR = 0x0
4892 13:57:04.348961 DBI_RD = 0x0
4893 13:57:04.353166 OTF = 0x1
4894 13:57:04.355023 ===================================
4895 13:57:04.361992 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4896 13:57:04.364836 nWR fixed to 30
4897 13:57:04.368696 [ModeRegInit_LP4] CH0 RK0
4898 13:57:04.368834 [ModeRegInit_LP4] CH0 RK1
4899 13:57:04.372626 [ModeRegInit_LP4] CH1 RK0
4900 13:57:04.375148 [ModeRegInit_LP4] CH1 RK1
4901 13:57:04.375229 match AC timing 8
4902 13:57:04.381821 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4903 13:57:04.385857 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4904 13:57:04.387889 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4905 13:57:04.395116 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4906 13:57:04.398664 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4907 13:57:04.398745 ==
4908 13:57:04.401749 Dram Type= 6, Freq= 0, CH_0, rank 0
4909 13:57:04.404518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4910 13:57:04.404599 ==
4911 13:57:04.411239 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4912 13:57:04.418235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4913 13:57:04.421169 [CA 0] Center 38 (8~69) winsize 62
4914 13:57:04.424743 [CA 1] Center 38 (8~69) winsize 62
4915 13:57:04.428677 [CA 2] Center 36 (6~67) winsize 62
4916 13:57:04.431440 [CA 3] Center 36 (6~66) winsize 61
4917 13:57:04.434714 [CA 4] Center 34 (4~65) winsize 62
4918 13:57:04.438214 [CA 5] Center 34 (4~65) winsize 62
4919 13:57:04.438297
4920 13:57:04.441439 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4921 13:57:04.441522
4922 13:57:04.444453 [CATrainingPosCal] consider 1 rank data
4923 13:57:04.448496 u2DelayCellTimex100 = 270/100 ps
4924 13:57:04.450809 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4925 13:57:04.455282 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4926 13:57:04.459760 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4927 13:57:04.461522 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4928 13:57:04.464329 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4929 13:57:04.472004 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4930 13:57:04.472089
4931 13:57:04.473930 CA PerBit enable=1, Macro0, CA PI delay=34
4932 13:57:04.474014
4933 13:57:04.477598 [CBTSetCACLKResult] CA Dly = 34
4934 13:57:04.477683 CS Dly: 7 (0~38)
4935 13:57:04.477768 ==
4936 13:57:04.480356 Dram Type= 6, Freq= 0, CH_0, rank 1
4937 13:57:04.484154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4938 13:57:04.487368 ==
4939 13:57:04.490560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4940 13:57:04.496976 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4941 13:57:04.500165 [CA 0] Center 38 (8~69) winsize 62
4942 13:57:04.503517 [CA 1] Center 38 (8~69) winsize 62
4943 13:57:04.506808 [CA 2] Center 36 (6~67) winsize 62
4944 13:57:04.510419 [CA 3] Center 35 (5~66) winsize 62
4945 13:57:04.513613 [CA 4] Center 34 (4~65) winsize 62
4946 13:57:04.517178 [CA 5] Center 34 (4~65) winsize 62
4947 13:57:04.517263
4948 13:57:04.520565 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4949 13:57:04.520650
4950 13:57:04.523796 [CATrainingPosCal] consider 2 rank data
4951 13:57:04.526967 u2DelayCellTimex100 = 270/100 ps
4952 13:57:04.530904 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4953 13:57:04.533273 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4954 13:57:04.536585 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4955 13:57:04.544093 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4956 13:57:04.547391 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4957 13:57:04.550263 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4958 13:57:04.550346
4959 13:57:04.553249 CA PerBit enable=1, Macro0, CA PI delay=34
4960 13:57:04.553333
4961 13:57:04.556574 [CBTSetCACLKResult] CA Dly = 34
4962 13:57:04.556691 CS Dly: 7 (0~39)
4963 13:57:04.556771
4964 13:57:04.559953 ----->DramcWriteLeveling(PI) begin...
4965 13:57:04.563631 ==
4966 13:57:04.563715 Dram Type= 6, Freq= 0, CH_0, rank 0
4967 13:57:04.570126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4968 13:57:04.570210 ==
4969 13:57:04.573084 Write leveling (Byte 0): 27 => 27
4970 13:57:04.577358 Write leveling (Byte 1): 27 => 27
4971 13:57:04.579434 DramcWriteLeveling(PI) end<-----
4972 13:57:04.579516
4973 13:57:04.579581 ==
4974 13:57:04.582794 Dram Type= 6, Freq= 0, CH_0, rank 0
4975 13:57:04.585983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4976 13:57:04.586066 ==
4977 13:57:04.589441 [Gating] SW mode calibration
4978 13:57:04.596200 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4979 13:57:04.599851 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4980 13:57:04.606413 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4981 13:57:04.609874 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4982 13:57:04.613167 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4983 13:57:04.619856 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4984 13:57:04.623188 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4985 13:57:04.629620 0 10 20 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4986 13:57:04.632491 0 10 24 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
4987 13:57:04.636000 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4988 13:57:04.643230 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4989 13:57:04.645784 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4990 13:57:04.649888 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4991 13:57:04.652982 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4992 13:57:04.659177 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4993 13:57:04.662458 0 11 20 | B1->B0 | 2727 3838 | 0 0 | (0 0) (1 1)
4994 13:57:04.665920 0 11 24 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
4995 13:57:04.672532 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 13:57:04.675993 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4997 13:57:04.680058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4998 13:57:04.685447 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4999 13:57:04.688615 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 13:57:04.691950 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5001 13:57:04.698527 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5002 13:57:04.701827 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 13:57:04.705642 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 13:57:04.712645 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 13:57:04.714988 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 13:57:04.718865 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 13:57:04.725489 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 13:57:04.728653 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 13:57:04.732249 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 13:57:04.738357 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 13:57:04.741599 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 13:57:04.744918 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 13:57:04.751943 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 13:57:04.754677 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 13:57:04.758680 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 13:57:04.766274 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5017 13:57:04.768063 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5018 13:57:04.771308 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5019 13:57:04.778575 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5020 13:57:04.781652 Total UI for P1: 0, mck2ui 16
5021 13:57:04.785165 best dqsien dly found for B0: ( 0, 14, 22)
5022 13:57:04.785284 Total UI for P1: 0, mck2ui 16
5023 13:57:04.793127 best dqsien dly found for B1: ( 0, 14, 22)
5024 13:57:04.794494 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5025 13:57:04.798298 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5026 13:57:04.798495
5027 13:57:04.802002 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5028 13:57:04.805064 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5029 13:57:04.808585 [Gating] SW calibration Done
5030 13:57:04.808803 ==
5031 13:57:04.811453 Dram Type= 6, Freq= 0, CH_0, rank 0
5032 13:57:04.814459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5033 13:57:04.814580 ==
5034 13:57:04.818289 RX Vref Scan: 0
5035 13:57:04.818407
5036 13:57:04.818502 RX Vref 0 -> 0, step: 1
5037 13:57:04.821259
5038 13:57:04.821378 RX Delay -80 -> 252, step: 8
5039 13:57:04.827915 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5040 13:57:04.830866 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5041 13:57:04.834667 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5042 13:57:04.837668 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5043 13:57:04.841255 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5044 13:57:04.844382 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5045 13:57:04.851691 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5046 13:57:04.854697 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5047 13:57:04.857889 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5048 13:57:04.861753 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5049 13:57:04.864122 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5050 13:57:04.871174 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5051 13:57:04.874629 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5052 13:57:04.877278 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5053 13:57:04.880502 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5054 13:57:04.884018 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5055 13:57:04.884099 ==
5056 13:57:04.887325 Dram Type= 6, Freq= 0, CH_0, rank 0
5057 13:57:04.893693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5058 13:57:04.893776 ==
5059 13:57:04.893841 DQS Delay:
5060 13:57:04.897428 DQS0 = 0, DQS1 = 0
5061 13:57:04.897509 DQM Delay:
5062 13:57:04.897574 DQM0 = 96, DQM1 = 84
5063 13:57:04.901499 DQ Delay:
5064 13:57:04.903669 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5065 13:57:04.907326 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5066 13:57:04.910824 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5067 13:57:04.914160 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5068 13:57:04.914242
5069 13:57:04.914305
5070 13:57:04.914365 ==
5071 13:57:04.916921 Dram Type= 6, Freq= 0, CH_0, rank 0
5072 13:57:04.920581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5073 13:57:04.920664 ==
5074 13:57:04.920734
5075 13:57:04.920795
5076 13:57:04.924370 TX Vref Scan disable
5077 13:57:04.927011 == TX Byte 0 ==
5078 13:57:04.930549 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5079 13:57:04.933341 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5080 13:57:04.937054 == TX Byte 1 ==
5081 13:57:04.940274 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5082 13:57:04.943348 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5083 13:57:04.943429 ==
5084 13:57:04.946497 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 13:57:04.949906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5086 13:57:04.953608 ==
5087 13:57:04.953689
5088 13:57:04.953753
5089 13:57:04.953812 TX Vref Scan disable
5090 13:57:04.956889 == TX Byte 0 ==
5091 13:57:04.960147 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5092 13:57:04.967179 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5093 13:57:04.967264 == TX Byte 1 ==
5094 13:57:04.970415 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5095 13:57:04.976957 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5096 13:57:04.977038
5097 13:57:04.977103 [DATLAT]
5098 13:57:04.977163 Freq=933, CH0 RK0
5099 13:57:04.977222
5100 13:57:04.980975 DATLAT Default: 0xd
5101 13:57:04.981056 0, 0xFFFF, sum = 0
5102 13:57:04.983562 1, 0xFFFF, sum = 0
5103 13:57:04.986580 2, 0xFFFF, sum = 0
5104 13:57:04.986662 3, 0xFFFF, sum = 0
5105 13:57:04.991154 4, 0xFFFF, sum = 0
5106 13:57:04.991237 5, 0xFFFF, sum = 0
5107 13:57:04.994037 6, 0xFFFF, sum = 0
5108 13:57:04.994120 7, 0xFFFF, sum = 0
5109 13:57:04.997390 8, 0xFFFF, sum = 0
5110 13:57:04.997473 9, 0xFFFF, sum = 0
5111 13:57:05.000666 10, 0x0, sum = 1
5112 13:57:05.000770 11, 0x0, sum = 2
5113 13:57:05.004251 12, 0x0, sum = 3
5114 13:57:05.004333 13, 0x0, sum = 4
5115 13:57:05.004399 best_step = 11
5116 13:57:05.007314
5117 13:57:05.007395 ==
5118 13:57:05.010012 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 13:57:05.013392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5120 13:57:05.013474 ==
5121 13:57:05.013539 RX Vref Scan: 1
5122 13:57:05.013598
5123 13:57:05.016972 RX Vref 0 -> 0, step: 1
5124 13:57:05.017053
5125 13:57:05.020211 RX Delay -69 -> 252, step: 4
5126 13:57:05.020291
5127 13:57:05.023246 Set Vref, RX VrefLevel [Byte0]: 47
5128 13:57:05.026816 [Byte1]: 49
5129 13:57:05.029427
5130 13:57:05.029509 Final RX Vref Byte 0 = 47 to rank0
5131 13:57:05.033764 Final RX Vref Byte 1 = 49 to rank0
5132 13:57:05.036262 Final RX Vref Byte 0 = 47 to rank1
5133 13:57:05.039846 Final RX Vref Byte 1 = 49 to rank1==
5134 13:57:05.042833 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 13:57:05.049287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5136 13:57:05.049369 ==
5137 13:57:05.049434 DQS Delay:
5138 13:57:05.052823 DQS0 = 0, DQS1 = 0
5139 13:57:05.052904 DQM Delay:
5140 13:57:05.052969 DQM0 = 97, DQM1 = 87
5141 13:57:05.056129 DQ Delay:
5142 13:57:05.059609 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =94
5143 13:57:05.062633 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5144 13:57:05.066746 DQ8 =78, DQ9 =70, DQ10 =88, DQ11 =78
5145 13:57:05.069457 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =98
5146 13:57:05.069538
5147 13:57:05.069603
5148 13:57:05.075587 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5149 13:57:05.079115 CH0 RK0: MR19=505, MR18=1B1B
5150 13:57:05.085495 CH0_RK0: MR19=0x505, MR18=0x1B1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5151 13:57:05.085591
5152 13:57:05.089043 ----->DramcWriteLeveling(PI) begin...
5153 13:57:05.089127 ==
5154 13:57:05.092390 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 13:57:05.095349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5156 13:57:05.095432 ==
5157 13:57:05.098754 Write leveling (Byte 0): 31 => 31
5158 13:57:05.103619 Write leveling (Byte 1): 26 => 26
5159 13:57:05.105920 DramcWriteLeveling(PI) end<-----
5160 13:57:05.106001
5161 13:57:05.106066 ==
5162 13:57:05.109674 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 13:57:05.115433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5164 13:57:05.115515 ==
5165 13:57:05.115581 [Gating] SW mode calibration
5166 13:57:05.125100 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5167 13:57:05.128463 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5168 13:57:05.131681 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 13:57:05.138379 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 13:57:05.142032 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 13:57:05.145740 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 13:57:05.151439 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 13:57:05.155486 0 10 20 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 1)
5174 13:57:05.161627 0 10 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
5175 13:57:05.164996 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 13:57:05.167984 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 13:57:05.171803 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 13:57:05.177920 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 13:57:05.181420 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 13:57:05.184466 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 13:57:05.191292 0 11 20 | B1->B0 | 2a2a 3535 | 0 0 | (1 1) (0 0)
5182 13:57:05.194405 0 11 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5183 13:57:05.198118 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 13:57:05.204236 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 13:57:05.208038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 13:57:05.211215 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 13:57:05.217979 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 13:57:05.221423 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 13:57:05.224397 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5190 13:57:05.231634 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5191 13:57:05.234361 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 13:57:05.237346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 13:57:05.244079 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 13:57:05.247277 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 13:57:05.254021 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 13:57:05.256871 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 13:57:05.260239 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 13:57:05.266999 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 13:57:05.270472 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 13:57:05.275265 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 13:57:05.277289 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 13:57:05.283898 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:57:05.287212 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 13:57:05.289807 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 13:57:05.296474 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5206 13:57:05.300698 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5207 13:57:05.303722 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 13:57:05.306558 Total UI for P1: 0, mck2ui 16
5209 13:57:05.309913 best dqsien dly found for B0: ( 0, 14, 22)
5210 13:57:05.314173 Total UI for P1: 0, mck2ui 16
5211 13:57:05.316276 best dqsien dly found for B1: ( 0, 14, 22)
5212 13:57:05.320080 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5213 13:57:05.326535 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5214 13:57:05.326618
5215 13:57:05.329560 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5216 13:57:05.333886 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5217 13:57:05.338391 [Gating] SW calibration Done
5218 13:57:05.338475 ==
5219 13:57:05.340975 Dram Type= 6, Freq= 0, CH_0, rank 1
5220 13:57:05.343648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5221 13:57:05.343733 ==
5222 13:57:05.348493 RX Vref Scan: 0
5223 13:57:05.348577
5224 13:57:05.348679 RX Vref 0 -> 0, step: 1
5225 13:57:05.348776
5226 13:57:05.349150 RX Delay -80 -> 252, step: 8
5227 13:57:05.353837 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5228 13:57:05.359194 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5229 13:57:05.362444 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5230 13:57:05.366573 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5231 13:57:05.369615 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5232 13:57:05.372650 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5233 13:57:05.375896 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5234 13:57:05.382427 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5235 13:57:05.385890 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5236 13:57:05.389220 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5237 13:57:05.392510 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5238 13:57:05.396251 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5239 13:57:05.402175 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5240 13:57:05.406304 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5241 13:57:05.409037 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5242 13:57:05.412843 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5243 13:57:05.412927 ==
5244 13:57:05.415718 Dram Type= 6, Freq= 0, CH_0, rank 1
5245 13:57:05.418899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5246 13:57:05.422098 ==
5247 13:57:05.422182 DQS Delay:
5248 13:57:05.422268 DQS0 = 0, DQS1 = 0
5249 13:57:05.425242 DQM Delay:
5250 13:57:05.425326 DQM0 = 95, DQM1 = 87
5251 13:57:05.428632 DQ Delay:
5252 13:57:05.428724 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5253 13:57:05.432650 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5254 13:57:05.435337 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5255 13:57:05.438756 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5256 13:57:05.442017
5257 13:57:05.442101
5258 13:57:05.442187 ==
5259 13:57:05.445225 Dram Type= 6, Freq= 0, CH_0, rank 1
5260 13:57:05.449175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5261 13:57:05.449259 ==
5262 13:57:05.449345
5263 13:57:05.449425
5264 13:57:05.452429 TX Vref Scan disable
5265 13:57:05.452513 == TX Byte 0 ==
5266 13:57:05.458384 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5267 13:57:05.464123 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5268 13:57:05.464208 == TX Byte 1 ==
5269 13:57:05.468086 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5270 13:57:05.471572 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5271 13:57:05.471657 ==
5272 13:57:05.475071 Dram Type= 6, Freq= 0, CH_0, rank 1
5273 13:57:05.478056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5274 13:57:05.478141 ==
5275 13:57:05.478227
5276 13:57:05.478308
5277 13:57:05.481274 TX Vref Scan disable
5278 13:57:05.484425 == TX Byte 0 ==
5279 13:57:05.488155 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5280 13:57:05.491715 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5281 13:57:05.494907 == TX Byte 1 ==
5282 13:57:05.498130 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5283 13:57:05.504681 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5284 13:57:05.504774
5285 13:57:05.504858 [DATLAT]
5286 13:57:05.504938 Freq=933, CH0 RK1
5287 13:57:05.505017
5288 13:57:05.509269 DATLAT Default: 0xb
5289 13:57:05.509369 0, 0xFFFF, sum = 0
5290 13:57:05.511640 1, 0xFFFF, sum = 0
5291 13:57:05.511726 2, 0xFFFF, sum = 0
5292 13:57:05.514407 3, 0xFFFF, sum = 0
5293 13:57:05.518925 4, 0xFFFF, sum = 0
5294 13:57:05.519011 5, 0xFFFF, sum = 0
5295 13:57:05.521018 6, 0xFFFF, sum = 0
5296 13:57:05.521104 7, 0xFFFF, sum = 0
5297 13:57:05.524833 8, 0xFFFF, sum = 0
5298 13:57:05.524918 9, 0xFFFF, sum = 0
5299 13:57:05.527917 10, 0x0, sum = 1
5300 13:57:05.528002 11, 0x0, sum = 2
5301 13:57:05.531127 12, 0x0, sum = 3
5302 13:57:05.531213 13, 0x0, sum = 4
5303 13:57:05.531300 best_step = 11
5304 13:57:05.531381
5305 13:57:05.534413 ==
5306 13:57:05.537774 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 13:57:05.541317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5308 13:57:05.541402 ==
5309 13:57:05.541488 RX Vref Scan: 0
5310 13:57:05.541569
5311 13:57:05.544750 RX Vref 0 -> 0, step: 1
5312 13:57:05.544834
5313 13:57:05.548198 RX Delay -69 -> 252, step: 4
5314 13:57:05.551307 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5315 13:57:05.557620 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5316 13:57:05.560611 iDelay=199, Bit 2, Center 98 (7 ~ 190) 184
5317 13:57:05.564860 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5318 13:57:05.568695 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5319 13:57:05.571560 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5320 13:57:05.575272 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5321 13:57:05.580498 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5322 13:57:05.583887 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5323 13:57:05.587722 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5324 13:57:05.590476 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5325 13:57:05.593605 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5326 13:57:05.600922 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5327 13:57:05.605026 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5328 13:57:05.607084 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5329 13:57:05.610403 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5330 13:57:05.610487 ==
5331 13:57:05.614543 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 13:57:05.617591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5333 13:57:05.620381 ==
5334 13:57:05.620465 DQS Delay:
5335 13:57:05.620551 DQS0 = 0, DQS1 = 0
5336 13:57:05.624587 DQM Delay:
5337 13:57:05.624671 DQM0 = 97, DQM1 = 86
5338 13:57:05.627742 DQ Delay:
5339 13:57:05.630480 DQ0 =94, DQ1 =98, DQ2 =98, DQ3 =92
5340 13:57:05.634243 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5341 13:57:05.637667 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =80
5342 13:57:05.640900 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5343 13:57:05.640983
5344 13:57:05.641068
5345 13:57:05.647140 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5346 13:57:05.650806 CH0 RK1: MR19=505, MR18=2E2E
5347 13:57:05.657080 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5348 13:57:05.660323 [RxdqsGatingPostProcess] freq 933
5349 13:57:05.663422 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5350 13:57:05.667252 Pre-setting of DQS Precalculation
5351 13:57:05.673539 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5352 13:57:05.673623 ==
5353 13:57:05.677155 Dram Type= 6, Freq= 0, CH_1, rank 0
5354 13:57:05.680112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5355 13:57:05.680197 ==
5356 13:57:05.686985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5357 13:57:05.694601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5358 13:57:05.696570 [CA 0] Center 37 (7~68) winsize 62
5359 13:57:05.700014 [CA 1] Center 37 (6~68) winsize 63
5360 13:57:05.703002 [CA 2] Center 34 (4~65) winsize 62
5361 13:57:05.706522 [CA 3] Center 34 (4~65) winsize 62
5362 13:57:05.710202 [CA 4] Center 33 (2~64) winsize 63
5363 13:57:05.712690 [CA 5] Center 33 (2~64) winsize 63
5364 13:57:05.712780
5365 13:57:05.716627 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5366 13:57:05.716715
5367 13:57:05.719969 [CATrainingPosCal] consider 1 rank data
5368 13:57:05.722942 u2DelayCellTimex100 = 270/100 ps
5369 13:57:05.727041 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5370 13:57:05.729787 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5371 13:57:05.733106 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5372 13:57:05.737241 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5373 13:57:05.739195 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5374 13:57:05.742903 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5375 13:57:05.742984
5376 13:57:05.749569 CA PerBit enable=1, Macro0, CA PI delay=33
5377 13:57:05.749651
5378 13:57:05.749715 [CBTSetCACLKResult] CA Dly = 33
5379 13:57:05.752568 CS Dly: 5 (0~36)
5380 13:57:05.752650 ==
5381 13:57:05.755953 Dram Type= 6, Freq= 0, CH_1, rank 1
5382 13:57:05.758985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5383 13:57:05.759066 ==
5384 13:57:05.766281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5385 13:57:05.772146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5386 13:57:05.775504 [CA 0] Center 37 (6~68) winsize 63
5387 13:57:05.778907 [CA 1] Center 37 (6~68) winsize 63
5388 13:57:05.782359 [CA 2] Center 34 (4~65) winsize 62
5389 13:57:05.785970 [CA 3] Center 34 (4~64) winsize 61
5390 13:57:05.789192 [CA 4] Center 33 (3~64) winsize 62
5391 13:57:05.792808 [CA 5] Center 33 (3~64) winsize 62
5392 13:57:05.792889
5393 13:57:05.795621 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5394 13:57:05.795702
5395 13:57:05.799257 [CATrainingPosCal] consider 2 rank data
5396 13:57:05.802189 u2DelayCellTimex100 = 270/100 ps
5397 13:57:05.805382 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5398 13:57:05.808839 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5399 13:57:05.812456 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5400 13:57:05.815650 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5401 13:57:05.819870 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5402 13:57:05.825364 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5403 13:57:05.825445
5404 13:57:05.829046 CA PerBit enable=1, Macro0, CA PI delay=33
5405 13:57:05.829126
5406 13:57:05.832238 [CBTSetCACLKResult] CA Dly = 33
5407 13:57:05.832318 CS Dly: 5 (0~37)
5408 13:57:05.832381
5409 13:57:05.835121 ----->DramcWriteLeveling(PI) begin...
5410 13:57:05.835202 ==
5411 13:57:05.838865 Dram Type= 6, Freq= 0, CH_1, rank 0
5412 13:57:05.845393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5413 13:57:05.845474 ==
5414 13:57:05.849241 Write leveling (Byte 0): 22 => 22
5415 13:57:05.849323 Write leveling (Byte 1): 22 => 22
5416 13:57:05.851568 DramcWriteLeveling(PI) end<-----
5417 13:57:05.851648
5418 13:57:05.851712 ==
5419 13:57:05.854949 Dram Type= 6, Freq= 0, CH_1, rank 0
5420 13:57:05.861474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5421 13:57:05.861583 ==
5422 13:57:05.865074 [Gating] SW mode calibration
5423 13:57:05.872237 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5424 13:57:05.875052 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5425 13:57:05.881648 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 13:57:05.885436 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 13:57:05.887867 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5428 13:57:05.894869 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5429 13:57:05.899053 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5430 13:57:05.902822 0 10 20 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
5431 13:57:05.909219 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5432 13:57:05.911835 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 13:57:05.914579 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 13:57:05.920664 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 13:57:05.925757 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5436 13:57:05.927764 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5437 13:57:05.934390 0 11 16 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
5438 13:57:05.937576 0 11 20 | B1->B0 | 2b2b 4545 | 0 1 | (0 0) (0 0)
5439 13:57:05.941056 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5440 13:57:05.948570 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 13:57:05.950422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 13:57:05.954361 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 13:57:05.961225 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 13:57:05.964649 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5445 13:57:05.967192 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5446 13:57:05.973916 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5447 13:57:05.976987 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 13:57:05.980282 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 13:57:05.987494 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 13:57:05.991008 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 13:57:05.993571 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 13:57:06.000436 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 13:57:06.003467 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 13:57:06.007712 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 13:57:06.014202 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 13:57:06.017736 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 13:57:06.020844 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 13:57:06.027929 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 13:57:06.030146 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 13:57:06.033022 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 13:57:06.039991 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5462 13:57:06.043160 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5463 13:57:06.046550 Total UI for P1: 0, mck2ui 16
5464 13:57:06.050378 best dqsien dly found for B0: ( 0, 14, 16)
5465 13:57:06.052919 Total UI for P1: 0, mck2ui 16
5466 13:57:06.056520 best dqsien dly found for B1: ( 0, 14, 18)
5467 13:57:06.060577 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5468 13:57:06.062981 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5469 13:57:06.063065
5470 13:57:06.066610 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5471 13:57:06.069290 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5472 13:57:06.072825 [Gating] SW calibration Done
5473 13:57:06.072909 ==
5474 13:57:06.075836 Dram Type= 6, Freq= 0, CH_1, rank 0
5475 13:57:06.079356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5476 13:57:06.083282 ==
5477 13:57:06.083367 RX Vref Scan: 0
5478 13:57:06.083452
5479 13:57:06.086174 RX Vref 0 -> 0, step: 1
5480 13:57:06.086258
5481 13:57:06.089166 RX Delay -80 -> 252, step: 8
5482 13:57:06.093624 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5483 13:57:06.095711 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5484 13:57:06.099910 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5485 13:57:06.102620 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5486 13:57:06.106539 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5487 13:57:06.113189 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5488 13:57:06.115767 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5489 13:57:06.119154 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5490 13:57:06.123304 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5491 13:57:06.125800 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5492 13:57:06.132895 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5493 13:57:06.137118 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5494 13:57:06.140314 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5495 13:57:06.142391 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5496 13:57:06.145536 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5497 13:57:06.152407 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5498 13:57:06.152491 ==
5499 13:57:06.155898 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 13:57:06.159054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5501 13:57:06.159139 ==
5502 13:57:06.159225 DQS Delay:
5503 13:57:06.162164 DQS0 = 0, DQS1 = 0
5504 13:57:06.162247 DQM Delay:
5505 13:57:06.165393 DQM0 = 94, DQM1 = 88
5506 13:57:06.165478 DQ Delay:
5507 13:57:06.169044 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5508 13:57:06.172202 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5509 13:57:06.175799 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5510 13:57:06.179086 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5511 13:57:06.179170
5512 13:57:06.179256
5513 13:57:06.179335 ==
5514 13:57:06.182253 Dram Type= 6, Freq= 0, CH_1, rank 0
5515 13:57:06.186133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5516 13:57:06.186218 ==
5517 13:57:06.186303
5518 13:57:06.186383
5519 13:57:06.189382 TX Vref Scan disable
5520 13:57:06.192115 == TX Byte 0 ==
5521 13:57:06.195529 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5522 13:57:06.198895 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5523 13:57:06.202392 == TX Byte 1 ==
5524 13:57:06.205678 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5525 13:57:06.208728 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5526 13:57:06.208813 ==
5527 13:57:06.211690 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 13:57:06.218574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5529 13:57:06.218661 ==
5530 13:57:06.218747
5531 13:57:06.218827
5532 13:57:06.218905 TX Vref Scan disable
5533 13:57:06.223237 == TX Byte 0 ==
5534 13:57:06.225933 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5535 13:57:06.232316 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5536 13:57:06.232401 == TX Byte 1 ==
5537 13:57:06.235888 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5538 13:57:06.242526 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5539 13:57:06.242610
5540 13:57:06.242696 [DATLAT]
5541 13:57:06.242777 Freq=933, CH1 RK0
5542 13:57:06.242856
5543 13:57:06.245898 DATLAT Default: 0xd
5544 13:57:06.245981 0, 0xFFFF, sum = 0
5545 13:57:06.251274 1, 0xFFFF, sum = 0
5546 13:57:06.251358 2, 0xFFFF, sum = 0
5547 13:57:06.252906 3, 0xFFFF, sum = 0
5548 13:57:06.256501 4, 0xFFFF, sum = 0
5549 13:57:06.256624 5, 0xFFFF, sum = 0
5550 13:57:06.258967 6, 0xFFFF, sum = 0
5551 13:57:06.259068 7, 0xFFFF, sum = 0
5552 13:57:06.262420 8, 0xFFFF, sum = 0
5553 13:57:06.262503 9, 0xFFFF, sum = 0
5554 13:57:06.265921 10, 0x0, sum = 1
5555 13:57:06.266004 11, 0x0, sum = 2
5556 13:57:06.269012 12, 0x0, sum = 3
5557 13:57:06.269095 13, 0x0, sum = 4
5558 13:57:06.269161 best_step = 11
5559 13:57:06.269222
5560 13:57:06.272411 ==
5561 13:57:06.275728 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 13:57:06.278932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5563 13:57:06.279015 ==
5564 13:57:06.279080 RX Vref Scan: 1
5565 13:57:06.279140
5566 13:57:06.282496 RX Vref 0 -> 0, step: 1
5567 13:57:06.282578
5568 13:57:06.285462 RX Delay -69 -> 252, step: 4
5569 13:57:06.285544
5570 13:57:06.288599 Set Vref, RX VrefLevel [Byte0]: 50
5571 13:57:06.292142 [Byte1]: 49
5572 13:57:06.292224
5573 13:57:06.295498 Final RX Vref Byte 0 = 50 to rank0
5574 13:57:06.299454 Final RX Vref Byte 1 = 49 to rank0
5575 13:57:06.301944 Final RX Vref Byte 0 = 50 to rank1
5576 13:57:06.305230 Final RX Vref Byte 1 = 49 to rank1==
5577 13:57:06.309875 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 13:57:06.312395 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5579 13:57:06.316365 ==
5580 13:57:06.316447 DQS Delay:
5581 13:57:06.316513 DQS0 = 0, DQS1 = 0
5582 13:57:06.319139 DQM Delay:
5583 13:57:06.319220 DQM0 = 94, DQM1 = 87
5584 13:57:06.322111 DQ Delay:
5585 13:57:06.322194 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =92
5586 13:57:06.325562 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5587 13:57:06.328690 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
5588 13:57:06.332154 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5589 13:57:06.335344
5590 13:57:06.335428
5591 13:57:06.342341 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5592 13:57:06.345183 CH1 RK0: MR19=505, MR18=3838
5593 13:57:06.351841 CH1_RK0: MR19=0x505, MR18=0x3838, DQSOSC=404, MR23=63, INC=66, DEC=44
5594 13:57:06.351926
5595 13:57:06.355336 ----->DramcWriteLeveling(PI) begin...
5596 13:57:06.355421 ==
5597 13:57:06.359644 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 13:57:06.363287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5599 13:57:06.363372 ==
5600 13:57:06.365662 Write leveling (Byte 0): 25 => 25
5601 13:57:06.368256 Write leveling (Byte 1): 26 => 26
5602 13:57:06.371926 DramcWriteLeveling(PI) end<-----
5603 13:57:06.372010
5604 13:57:06.372095 ==
5605 13:57:06.374920 Dram Type= 6, Freq= 0, CH_1, rank 1
5606 13:57:06.378439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5607 13:57:06.378525 ==
5608 13:57:06.381630 [Gating] SW mode calibration
5609 13:57:06.388609 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5610 13:57:06.394743 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5611 13:57:06.398554 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 13:57:06.405865 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 13:57:06.408390 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 13:57:06.411599 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 13:57:06.418038 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
5616 13:57:06.421617 0 10 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5617 13:57:06.424901 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 13:57:06.431362 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 13:57:06.435199 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 13:57:06.438002 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 13:57:06.441331 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 13:57:06.448219 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 13:57:06.450920 0 11 16 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
5624 13:57:06.455153 0 11 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5625 13:57:06.461080 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5626 13:57:06.465020 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 13:57:06.467501 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 13:57:06.474730 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 13:57:06.477560 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 13:57:06.481094 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 13:57:06.488384 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5632 13:57:06.490831 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5633 13:57:06.494142 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:57:06.501975 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:57:06.503954 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:57:06.507660 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:57:06.515585 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 13:57:06.517272 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 13:57:06.520580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 13:57:06.527641 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 13:57:06.530760 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 13:57:06.533685 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 13:57:06.540323 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 13:57:06.544119 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 13:57:06.547313 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 13:57:06.554137 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 13:57:06.557101 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5648 13:57:06.560673 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 13:57:06.563746 Total UI for P1: 0, mck2ui 16
5650 13:57:06.567894 best dqsien dly found for B0: ( 0, 14, 16)
5651 13:57:06.570922 Total UI for P1: 0, mck2ui 16
5652 13:57:06.574627 best dqsien dly found for B1: ( 0, 14, 18)
5653 13:57:06.576710 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5654 13:57:06.579979 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5655 13:57:06.580061
5656 13:57:06.587125 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5657 13:57:06.590323 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5658 13:57:06.590406 [Gating] SW calibration Done
5659 13:57:06.593968 ==
5660 13:57:06.597618 Dram Type= 6, Freq= 0, CH_1, rank 1
5661 13:57:06.599975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5662 13:57:06.600056 ==
5663 13:57:06.600121 RX Vref Scan: 0
5664 13:57:06.600181
5665 13:57:06.603697 RX Vref 0 -> 0, step: 1
5666 13:57:06.603778
5667 13:57:06.607110 RX Delay -80 -> 252, step: 8
5668 13:57:06.610006 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5669 13:57:06.613626 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5670 13:57:06.617117 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5671 13:57:06.623628 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5672 13:57:06.626419 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5673 13:57:06.630044 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5674 13:57:06.633195 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5675 13:57:06.636919 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5676 13:57:06.640148 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5677 13:57:06.646499 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5678 13:57:06.650491 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5679 13:57:06.653051 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5680 13:57:06.656453 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5681 13:57:06.659734 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5682 13:57:06.666656 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5683 13:57:06.669792 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5684 13:57:06.669872 ==
5685 13:57:06.673484 Dram Type= 6, Freq= 0, CH_1, rank 1
5686 13:57:06.676376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5687 13:57:06.676456 ==
5688 13:57:06.676520 DQS Delay:
5689 13:57:06.679810 DQS0 = 0, DQS1 = 0
5690 13:57:06.679889 DQM Delay:
5691 13:57:06.682918 DQM0 = 96, DQM1 = 87
5692 13:57:06.682999 DQ Delay:
5693 13:57:06.686005 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =95
5694 13:57:06.689919 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5695 13:57:06.692978 DQ8 =71, DQ9 =75, DQ10 =83, DQ11 =79
5696 13:57:06.696053 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5697 13:57:06.696132
5698 13:57:06.696195
5699 13:57:06.696253 ==
5700 13:57:06.699402 Dram Type= 6, Freq= 0, CH_1, rank 1
5701 13:57:06.706195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5702 13:57:06.706275 ==
5703 13:57:06.706338
5704 13:57:06.706397
5705 13:57:06.706453 TX Vref Scan disable
5706 13:57:06.709514 == TX Byte 0 ==
5707 13:57:06.712831 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5708 13:57:06.719164 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5709 13:57:06.719246 == TX Byte 1 ==
5710 13:57:06.722538 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5711 13:57:06.729605 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5712 13:57:06.729686 ==
5713 13:57:06.733150 Dram Type= 6, Freq= 0, CH_1, rank 1
5714 13:57:06.735988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5715 13:57:06.736099 ==
5716 13:57:06.736168
5717 13:57:06.736229
5718 13:57:06.739296 TX Vref Scan disable
5719 13:57:06.739377 == TX Byte 0 ==
5720 13:57:06.746572 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5721 13:57:06.749985 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5722 13:57:06.750066 == TX Byte 1 ==
5723 13:57:06.755828 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 13:57:06.759228 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 13:57:06.759309
5726 13:57:06.759373 [DATLAT]
5727 13:57:06.762418 Freq=933, CH1 RK1
5728 13:57:06.762499
5729 13:57:06.762563 DATLAT Default: 0xb
5730 13:57:06.766367 0, 0xFFFF, sum = 0
5731 13:57:06.766450 1, 0xFFFF, sum = 0
5732 13:57:06.769801 2, 0xFFFF, sum = 0
5733 13:57:06.769884 3, 0xFFFF, sum = 0
5734 13:57:06.772677 4, 0xFFFF, sum = 0
5735 13:57:06.775582 5, 0xFFFF, sum = 0
5736 13:57:06.775665 6, 0xFFFF, sum = 0
5737 13:57:06.779545 7, 0xFFFF, sum = 0
5738 13:57:06.779627 8, 0xFFFF, sum = 0
5739 13:57:06.782422 9, 0xFFFF, sum = 0
5740 13:57:06.782505 10, 0x0, sum = 1
5741 13:57:06.785676 11, 0x0, sum = 2
5742 13:57:06.785760 12, 0x0, sum = 3
5743 13:57:06.785825 13, 0x0, sum = 4
5744 13:57:06.789926 best_step = 11
5745 13:57:06.790008
5746 13:57:06.790073 ==
5747 13:57:06.792026 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 13:57:06.795832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5749 13:57:06.795915 ==
5750 13:57:06.799183 RX Vref Scan: 0
5751 13:57:06.799265
5752 13:57:06.802091 RX Vref 0 -> 0, step: 1
5753 13:57:06.802174
5754 13:57:06.802239 RX Delay -77 -> 252, step: 4
5755 13:57:06.809712 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5756 13:57:06.813476 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5757 13:57:06.817118 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5758 13:57:06.820407 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5759 13:57:06.823433 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5760 13:57:06.829973 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5761 13:57:06.833047 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5762 13:57:06.836986 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5763 13:57:06.839525 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5764 13:57:06.843032 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5765 13:57:06.846615 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5766 13:57:06.852885 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5767 13:57:06.855950 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5768 13:57:06.860165 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5769 13:57:06.862761 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5770 13:57:06.867130 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5771 13:57:06.867255 ==
5772 13:57:06.869545 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 13:57:06.876676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5774 13:57:06.876797 ==
5775 13:57:06.876863 DQS Delay:
5776 13:57:06.879901 DQS0 = 0, DQS1 = 0
5777 13:57:06.879983 DQM Delay:
5778 13:57:06.880047 DQM0 = 95, DQM1 = 87
5779 13:57:06.884525 DQ Delay:
5780 13:57:06.887719 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =90
5781 13:57:06.889329 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5782 13:57:06.893551 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5783 13:57:06.896483 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5784 13:57:06.896564
5785 13:57:06.896629
5786 13:57:06.902657 [DQSOSCAuto] RK1, (LSB)MR18= 0x2828, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5787 13:57:06.906681 CH1 RK1: MR19=505, MR18=2828
5788 13:57:06.912677 CH1_RK1: MR19=0x505, MR18=0x2828, DQSOSC=409, MR23=63, INC=64, DEC=43
5789 13:57:06.915657 [RxdqsGatingPostProcess] freq 933
5790 13:57:06.919552 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5791 13:57:06.922907 Pre-setting of DQS Precalculation
5792 13:57:06.929260 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5793 13:57:06.935875 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5794 13:57:06.942108 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5795 13:57:06.942190
5796 13:57:06.942255
5797 13:57:06.946565 [Calibration Summary] 1866 Mbps
5798 13:57:06.949579 CH 0, Rank 0
5799 13:57:06.949662 SW Impedance : PASS
5800 13:57:06.952500 DUTY Scan : NO K
5801 13:57:06.952582 ZQ Calibration : PASS
5802 13:57:06.956196 Jitter Meter : NO K
5803 13:57:06.958980 CBT Training : PASS
5804 13:57:06.959062 Write leveling : PASS
5805 13:57:06.962141 RX DQS gating : PASS
5806 13:57:06.965857 RX DQ/DQS(RDDQC) : PASS
5807 13:57:06.965939 TX DQ/DQS : PASS
5808 13:57:06.969427 RX DATLAT : PASS
5809 13:57:06.972275 RX DQ/DQS(Engine): PASS
5810 13:57:06.972356 TX OE : NO K
5811 13:57:06.976220 All Pass.
5812 13:57:06.976302
5813 13:57:06.976366 CH 0, Rank 1
5814 13:57:06.978738 SW Impedance : PASS
5815 13:57:06.978820 DUTY Scan : NO K
5816 13:57:06.982364 ZQ Calibration : PASS
5817 13:57:06.987784 Jitter Meter : NO K
5818 13:57:06.987866 CBT Training : PASS
5819 13:57:06.988607 Write leveling : PASS
5820 13:57:06.991911 RX DQS gating : PASS
5821 13:57:06.991993 RX DQ/DQS(RDDQC) : PASS
5822 13:57:06.995401 TX DQ/DQS : PASS
5823 13:57:06.999209 RX DATLAT : PASS
5824 13:57:06.999291 RX DQ/DQS(Engine): PASS
5825 13:57:07.001864 TX OE : NO K
5826 13:57:07.001947 All Pass.
5827 13:57:07.002012
5828 13:57:07.005598 CH 1, Rank 0
5829 13:57:07.005681 SW Impedance : PASS
5830 13:57:07.009068 DUTY Scan : NO K
5831 13:57:07.012330 ZQ Calibration : PASS
5832 13:57:07.012412 Jitter Meter : NO K
5833 13:57:07.015464 CBT Training : PASS
5834 13:57:07.015546 Write leveling : PASS
5835 13:57:07.019189 RX DQS gating : PASS
5836 13:57:07.021711 RX DQ/DQS(RDDQC) : PASS
5837 13:57:07.021793 TX DQ/DQS : PASS
5838 13:57:07.025725 RX DATLAT : PASS
5839 13:57:07.029176 RX DQ/DQS(Engine): PASS
5840 13:57:07.029260 TX OE : NO K
5841 13:57:07.031955 All Pass.
5842 13:57:07.032038
5843 13:57:07.032123 CH 1, Rank 1
5844 13:57:07.035699 SW Impedance : PASS
5845 13:57:07.035784 DUTY Scan : NO K
5846 13:57:07.038464 ZQ Calibration : PASS
5847 13:57:07.042267 Jitter Meter : NO K
5848 13:57:07.042352 CBT Training : PASS
5849 13:57:07.045173 Write leveling : PASS
5850 13:57:07.048274 RX DQS gating : PASS
5851 13:57:07.048358 RX DQ/DQS(RDDQC) : PASS
5852 13:57:07.051610 TX DQ/DQS : PASS
5853 13:57:07.056073 RX DATLAT : PASS
5854 13:57:07.056157 RX DQ/DQS(Engine): PASS
5855 13:57:07.058612 TX OE : NO K
5856 13:57:07.058699 All Pass.
5857 13:57:07.058785
5858 13:57:07.061596 DramC Write-DBI off
5859 13:57:07.065409 PER_BANK_REFRESH: Hybrid Mode
5860 13:57:07.065494 TX_TRACKING: ON
5861 13:57:07.074873 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5862 13:57:07.078231 [FAST_K] Save calibration result to emmc
5863 13:57:07.081535 dramc_set_vcore_voltage set vcore to 650000
5864 13:57:07.085240 Read voltage for 400, 6
5865 13:57:07.085324 Vio18 = 0
5866 13:57:07.085410 Vcore = 650000
5867 13:57:07.088149 Vdram = 0
5868 13:57:07.088232 Vddq = 0
5869 13:57:07.088318 Vmddr = 0
5870 13:57:07.096456 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5871 13:57:07.098100 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5872 13:57:07.101379 MEM_TYPE=3, freq_sel=20
5873 13:57:07.104734 sv_algorithm_assistance_LP4_800
5874 13:57:07.109960 ============ PULL DRAM RESETB DOWN ============
5875 13:57:07.111371 ========== PULL DRAM RESETB DOWN end =========
5876 13:57:07.118017 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5877 13:57:07.121312 ===================================
5878 13:57:07.121397 LPDDR4 DRAM CONFIGURATION
5879 13:57:07.124746 ===================================
5880 13:57:07.127888 EX_ROW_EN[0] = 0x0
5881 13:57:07.131115 EX_ROW_EN[1] = 0x0
5882 13:57:07.131197 LP4Y_EN = 0x0
5883 13:57:07.134478 WORK_FSP = 0x0
5884 13:57:07.134560 WL = 0x2
5885 13:57:07.138075 RL = 0x2
5886 13:57:07.138158 BL = 0x2
5887 13:57:07.141167 RPST = 0x0
5888 13:57:07.141249 RD_PRE = 0x0
5889 13:57:07.144396 WR_PRE = 0x1
5890 13:57:07.144478 WR_PST = 0x0
5891 13:57:07.147808 DBI_WR = 0x0
5892 13:57:07.147890 DBI_RD = 0x0
5893 13:57:07.151965 OTF = 0x1
5894 13:57:07.154503 ===================================
5895 13:57:07.158016 ===================================
5896 13:57:07.158098 ANA top config
5897 13:57:07.161085 ===================================
5898 13:57:07.164240 DLL_ASYNC_EN = 0
5899 13:57:07.168975 ALL_SLAVE_EN = 1
5900 13:57:07.171105 NEW_RANK_MODE = 1
5901 13:57:07.171186 DLL_IDLE_MODE = 1
5902 13:57:07.174692 LP45_APHY_COMB_EN = 1
5903 13:57:07.177623 TX_ODT_DIS = 1
5904 13:57:07.180971 NEW_8X_MODE = 1
5905 13:57:07.184266 ===================================
5906 13:57:07.188515 ===================================
5907 13:57:07.190947 data_rate = 800
5908 13:57:07.191026 CKR = 1
5909 13:57:07.194400 DQ_P2S_RATIO = 4
5910 13:57:07.198023 ===================================
5911 13:57:07.200884 CA_P2S_RATIO = 4
5912 13:57:07.207468 DQ_CA_OPEN = 0
5913 13:57:07.207907 DQ_SEMI_OPEN = 1
5914 13:57:07.210949 CA_SEMI_OPEN = 1
5915 13:57:07.211028 CA_FULL_RATE = 0
5916 13:57:07.213904 DQ_CKDIV4_EN = 0
5917 13:57:07.217623 CA_CKDIV4_EN = 1
5918 13:57:07.221255 CA_PREDIV_EN = 0
5919 13:57:07.223736 PH8_DLY = 0
5920 13:57:07.227409 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5921 13:57:07.227491 DQ_AAMCK_DIV = 0
5922 13:57:07.230885 CA_AAMCK_DIV = 0
5923 13:57:07.233886 CA_ADMCK_DIV = 4
5924 13:57:07.237312 DQ_TRACK_CA_EN = 0
5925 13:57:07.240565 CA_PICK = 800
5926 13:57:07.243433 CA_MCKIO = 400
5927 13:57:07.247403 MCKIO_SEMI = 400
5928 13:57:07.247485 PLL_FREQ = 3016
5929 13:57:07.250287 DQ_UI_PI_RATIO = 32
5930 13:57:07.253620 CA_UI_PI_RATIO = 32
5931 13:57:07.257199 ===================================
5932 13:57:07.260284 ===================================
5933 13:57:07.263640 memory_type:LPDDR4
5934 13:57:07.266829 GP_NUM : 10
5935 13:57:07.266912 SRAM_EN : 1
5936 13:57:07.270206 MD32_EN : 0
5937 13:57:07.273614 ===================================
5938 13:57:07.273696 [ANA_INIT] >>>>>>>>>>>>>>
5939 13:57:07.277046 <<<<<< [CONFIGURE PHASE]: ANA_TX
5940 13:57:07.280348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5941 13:57:07.283931 ===================================
5942 13:57:07.287418 data_rate = 800,PCW = 0X7400
5943 13:57:07.290826 ===================================
5944 13:57:07.293451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5945 13:57:07.300939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5946 13:57:07.310224 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5947 13:57:07.316586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5948 13:57:07.319769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5949 13:57:07.323220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5950 13:57:07.323303 [ANA_INIT] flow start
5951 13:57:07.326691 [ANA_INIT] PLL >>>>>>>>
5952 13:57:07.330016 [ANA_INIT] PLL <<<<<<<<
5953 13:57:07.330097 [ANA_INIT] MIDPI >>>>>>>>
5954 13:57:07.333483 [ANA_INIT] MIDPI <<<<<<<<
5955 13:57:07.336523 [ANA_INIT] DLL >>>>>>>>
5956 13:57:07.336604 [ANA_INIT] flow end
5957 13:57:07.343818 ============ LP4 DIFF to SE enter ============
5958 13:57:07.346431 ============ LP4 DIFF to SE exit ============
5959 13:57:07.349658 [ANA_INIT] <<<<<<<<<<<<<
5960 13:57:07.352961 [Flow] Enable top DCM control >>>>>
5961 13:57:07.356932 [Flow] Enable top DCM control <<<<<
5962 13:57:07.360242 Enable DLL master slave shuffle
5963 13:57:07.363318 ==============================================================
5964 13:57:07.366498 Gating Mode config
5965 13:57:07.370046 ==============================================================
5966 13:57:07.373092 Config description:
5967 13:57:07.383140 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5968 13:57:07.389288 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5969 13:57:07.392855 SELPH_MODE 0: By rank 1: By Phase
5970 13:57:07.398940 ==============================================================
5971 13:57:07.402305 GAT_TRACK_EN = 0
5972 13:57:07.405895 RX_GATING_MODE = 2
5973 13:57:07.409501 RX_GATING_TRACK_MODE = 2
5974 13:57:07.412627 SELPH_MODE = 1
5975 13:57:07.415754 PICG_EARLY_EN = 1
5976 13:57:07.419114 VALID_LAT_VALUE = 1
5977 13:57:07.422544 ==============================================================
5978 13:57:07.425600 Enter into Gating configuration >>>>
5979 13:57:07.429142 Exit from Gating configuration <<<<
5980 13:57:07.432394 Enter into DVFS_PRE_config >>>>>
5981 13:57:07.445286 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5982 13:57:07.445673 Exit from DVFS_PRE_config <<<<<
5983 13:57:07.448852 Enter into PICG configuration >>>>
5984 13:57:07.452611 Exit from PICG configuration <<<<
5985 13:57:07.455479 [RX_INPUT] configuration >>>>>
5986 13:57:07.459265 [RX_INPUT] configuration <<<<<
5987 13:57:07.465291 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5988 13:57:07.468335 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5989 13:57:07.476965 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5990 13:57:07.481911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5991 13:57:07.488661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5992 13:57:07.495388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5993 13:57:07.498775 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5994 13:57:07.501607 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5995 13:57:07.504958 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5996 13:57:07.512048 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5997 13:57:07.515985 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5998 13:57:07.518500 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5999 13:57:07.521534 ===================================
6000 13:57:07.527147 LPDDR4 DRAM CONFIGURATION
6001 13:57:07.528288 ===================================
6002 13:57:07.531663 EX_ROW_EN[0] = 0x0
6003 13:57:07.531746 EX_ROW_EN[1] = 0x0
6004 13:57:07.534723 LP4Y_EN = 0x0
6005 13:57:07.534805 WORK_FSP = 0x0
6006 13:57:07.538652 WL = 0x2
6007 13:57:07.538734 RL = 0x2
6008 13:57:07.541921 BL = 0x2
6009 13:57:07.542003 RPST = 0x0
6010 13:57:07.545243 RD_PRE = 0x0
6011 13:57:07.545324 WR_PRE = 0x1
6012 13:57:07.548470 WR_PST = 0x0
6013 13:57:07.548553 DBI_WR = 0x0
6014 13:57:07.551381 DBI_RD = 0x0
6015 13:57:07.551463 OTF = 0x1
6016 13:57:07.555169 ===================================
6017 13:57:07.558625 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6018 13:57:07.564729 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6019 13:57:07.567946 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6020 13:57:07.571357 ===================================
6021 13:57:07.574775 LPDDR4 DRAM CONFIGURATION
6022 13:57:07.578644 ===================================
6023 13:57:07.578726 EX_ROW_EN[0] = 0x10
6024 13:57:07.581328 EX_ROW_EN[1] = 0x0
6025 13:57:07.585128 LP4Y_EN = 0x0
6026 13:57:07.585210 WORK_FSP = 0x0
6027 13:57:07.587913 WL = 0x2
6028 13:57:07.587995 RL = 0x2
6029 13:57:07.591387 BL = 0x2
6030 13:57:07.591469 RPST = 0x0
6031 13:57:07.594164 RD_PRE = 0x0
6032 13:57:07.594245 WR_PRE = 0x1
6033 13:57:07.597397 WR_PST = 0x0
6034 13:57:07.597479 DBI_WR = 0x0
6035 13:57:07.601232 DBI_RD = 0x0
6036 13:57:07.601313 OTF = 0x1
6037 13:57:07.604076 ===================================
6038 13:57:07.611141 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6039 13:57:07.615233 nWR fixed to 30
6040 13:57:07.619162 [ModeRegInit_LP4] CH0 RK0
6041 13:57:07.619244 [ModeRegInit_LP4] CH0 RK1
6042 13:57:07.622244 [ModeRegInit_LP4] CH1 RK0
6043 13:57:07.625368 [ModeRegInit_LP4] CH1 RK1
6044 13:57:07.625448 match AC timing 18
6045 13:57:07.631901 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6046 13:57:07.635221 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6047 13:57:07.639764 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6048 13:57:07.646779 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6049 13:57:07.648428 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6050 13:57:07.648511 ==
6051 13:57:07.651651 Dram Type= 6, Freq= 0, CH_0, rank 0
6052 13:57:07.655279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6053 13:57:07.655360 ==
6054 13:57:07.661957 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6055 13:57:07.668891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6056 13:57:07.671928 [CA 0] Center 36 (8~64) winsize 57
6057 13:57:07.675552 [CA 1] Center 36 (8~64) winsize 57
6058 13:57:07.678925 [CA 2] Center 36 (8~64) winsize 57
6059 13:57:07.681676 [CA 3] Center 36 (8~64) winsize 57
6060 13:57:07.681756 [CA 4] Center 36 (8~64) winsize 57
6061 13:57:07.684955 [CA 5] Center 36 (8~64) winsize 57
6062 13:57:07.685036
6063 13:57:07.692136 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6064 13:57:07.692231
6065 13:57:07.694715 [CATrainingPosCal] consider 1 rank data
6066 13:57:07.698174 u2DelayCellTimex100 = 270/100 ps
6067 13:57:07.701508 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6068 13:57:07.704841 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 13:57:07.707962 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 13:57:07.711315 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 13:57:07.715071 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 13:57:07.718579 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6073 13:57:07.718659
6074 13:57:07.721708 CA PerBit enable=1, Macro0, CA PI delay=36
6075 13:57:07.721788
6076 13:57:07.724969 [CBTSetCACLKResult] CA Dly = 36
6077 13:57:07.727782 CS Dly: 1 (0~32)
6078 13:57:07.727862 ==
6079 13:57:07.730926 Dram Type= 6, Freq= 0, CH_0, rank 1
6080 13:57:07.734458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6081 13:57:07.734555 ==
6082 13:57:07.743216 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6083 13:57:07.748123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6084 13:57:07.750904 [CA 0] Center 36 (8~64) winsize 57
6085 13:57:07.751006 [CA 1] Center 36 (8~64) winsize 57
6086 13:57:07.754429 [CA 2] Center 36 (8~64) winsize 57
6087 13:57:07.757620 [CA 3] Center 36 (8~64) winsize 57
6088 13:57:07.761746 [CA 4] Center 36 (8~64) winsize 57
6089 13:57:07.764302 [CA 5] Center 36 (8~64) winsize 57
6090 13:57:07.764382
6091 13:57:07.767857 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6092 13:57:07.767938
6093 13:57:07.774515 [CATrainingPosCal] consider 2 rank data
6094 13:57:07.774602 u2DelayCellTimex100 = 270/100 ps
6095 13:57:07.777810 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6096 13:57:07.784663 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6097 13:57:07.788174 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 13:57:07.790707 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 13:57:07.794218 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6100 13:57:07.797257 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6101 13:57:07.797339
6102 13:57:07.800682 CA PerBit enable=1, Macro0, CA PI delay=36
6103 13:57:07.800805
6104 13:57:07.804214 [CBTSetCACLKResult] CA Dly = 36
6105 13:57:07.808012 CS Dly: 1 (0~32)
6106 13:57:07.808094
6107 13:57:07.811569 ----->DramcWriteLeveling(PI) begin...
6108 13:57:07.811653 ==
6109 13:57:07.814116 Dram Type= 6, Freq= 0, CH_0, rank 0
6110 13:57:07.817666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6111 13:57:07.817749 ==
6112 13:57:07.820291 Write leveling (Byte 0): 32 => 0
6113 13:57:07.823534 Write leveling (Byte 1): 32 => 0
6114 13:57:07.827020 DramcWriteLeveling(PI) end<-----
6115 13:57:07.827104
6116 13:57:07.827189 ==
6117 13:57:07.830742 Dram Type= 6, Freq= 0, CH_0, rank 0
6118 13:57:07.833512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6119 13:57:07.833597 ==
6120 13:57:07.837259 [Gating] SW mode calibration
6121 13:57:07.843862 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6122 13:57:07.851568 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6123 13:57:07.854109 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6124 13:57:07.856559 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6125 13:57:07.863528 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6126 13:57:07.866498 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6127 13:57:07.869832 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6128 13:57:07.876994 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6129 13:57:07.879800 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6130 13:57:07.883554 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6131 13:57:07.890544 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6132 13:57:07.890629 Total UI for P1: 0, mck2ui 16
6133 13:57:07.896278 best dqsien dly found for B0: ( 0, 10, 16)
6134 13:57:07.896362 Total UI for P1: 0, mck2ui 16
6135 13:57:07.903419 best dqsien dly found for B1: ( 0, 10, 24)
6136 13:57:07.907120 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6137 13:57:07.910325 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6138 13:57:07.910409
6139 13:57:07.913154 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6140 13:57:07.916079 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6141 13:57:07.919877 [Gating] SW calibration Done
6142 13:57:07.919961 ==
6143 13:57:07.922893 Dram Type= 6, Freq= 0, CH_0, rank 0
6144 13:57:07.926577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6145 13:57:07.926699 ==
6146 13:57:07.929303 RX Vref Scan: 0
6147 13:57:07.929382
6148 13:57:07.929445 RX Vref 0 -> 0, step: 1
6149 13:57:07.932959
6150 13:57:07.933038 RX Delay -410 -> 252, step: 16
6151 13:57:07.939403 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6152 13:57:07.943211 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6153 13:57:07.946569 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6154 13:57:07.949795 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6155 13:57:07.955964 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6156 13:57:07.959458 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6157 13:57:07.962525 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6158 13:57:07.966394 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6159 13:57:07.974078 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6160 13:57:07.976242 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6161 13:57:07.979297 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6162 13:57:07.983267 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6163 13:57:07.990131 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6164 13:57:07.992988 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6165 13:57:07.996390 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6166 13:57:07.999450 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6167 13:57:08.003380 ==
6168 13:57:08.006214 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 13:57:08.009580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 13:57:08.009660 ==
6171 13:57:08.009724 DQS Delay:
6172 13:57:08.013106 DQS0 = 43, DQS1 = 59
6173 13:57:08.013186 DQM Delay:
6174 13:57:08.016146 DQM0 = 5, DQM1 = 14
6175 13:57:08.016225 DQ Delay:
6176 13:57:08.019185 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6177 13:57:08.022670 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6178 13:57:08.026083 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6179 13:57:08.029292 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6180 13:57:08.029372
6181 13:57:08.029436
6182 13:57:08.029494 ==
6183 13:57:08.033223 Dram Type= 6, Freq= 0, CH_0, rank 0
6184 13:57:08.036144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6185 13:57:08.036225 ==
6186 13:57:08.036287
6187 13:57:08.036347
6188 13:57:08.039138 TX Vref Scan disable
6189 13:57:08.039218 == TX Byte 0 ==
6190 13:57:08.045712 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6191 13:57:08.049164 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6192 13:57:08.049244 == TX Byte 1 ==
6193 13:57:08.055340 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6194 13:57:08.058973 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6195 13:57:08.059052 ==
6196 13:57:08.062487 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 13:57:08.065455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6198 13:57:08.065536 ==
6199 13:57:08.065599
6200 13:57:08.065673
6201 13:57:08.069105 TX Vref Scan disable
6202 13:57:08.072101 == TX Byte 0 ==
6203 13:57:08.075596 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6204 13:57:08.079151 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6205 13:57:08.082437 == TX Byte 1 ==
6206 13:57:08.088117 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6207 13:57:08.089291 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6208 13:57:08.089372
6209 13:57:08.089435 [DATLAT]
6210 13:57:08.091960 Freq=400, CH0 RK0
6211 13:57:08.092040
6212 13:57:08.095325 DATLAT Default: 0xf
6213 13:57:08.095405 0, 0xFFFF, sum = 0
6214 13:57:08.099175 1, 0xFFFF, sum = 0
6215 13:57:08.099257 2, 0xFFFF, sum = 0
6216 13:57:08.102128 3, 0xFFFF, sum = 0
6217 13:57:08.102210 4, 0xFFFF, sum = 0
6218 13:57:08.104928 5, 0xFFFF, sum = 0
6219 13:57:08.105010 6, 0xFFFF, sum = 0
6220 13:57:08.108956 7, 0xFFFF, sum = 0
6221 13:57:08.109037 8, 0xFFFF, sum = 0
6222 13:57:08.111899 9, 0xFFFF, sum = 0
6223 13:57:08.111979 10, 0xFFFF, sum = 0
6224 13:57:08.114944 11, 0xFFFF, sum = 0
6225 13:57:08.115025 12, 0x0, sum = 1
6226 13:57:08.118997 13, 0x0, sum = 2
6227 13:57:08.119078 14, 0x0, sum = 3
6228 13:57:08.121651 15, 0x0, sum = 4
6229 13:57:08.121732 best_step = 13
6230 13:57:08.121796
6231 13:57:08.121854 ==
6232 13:57:08.124921 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 13:57:08.128562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6234 13:57:08.131944 ==
6235 13:57:08.132025 RX Vref Scan: 1
6236 13:57:08.132088
6237 13:57:08.135771 RX Vref 0 -> 0, step: 1
6238 13:57:08.135852
6239 13:57:08.138182 RX Delay -359 -> 252, step: 8
6240 13:57:08.138264
6241 13:57:08.142370 Set Vref, RX VrefLevel [Byte0]: 47
6242 13:57:08.144716 [Byte1]: 49
6243 13:57:08.144823
6244 13:57:08.149044 Final RX Vref Byte 0 = 47 to rank0
6245 13:57:08.151717 Final RX Vref Byte 1 = 49 to rank0
6246 13:57:08.155462 Final RX Vref Byte 0 = 47 to rank1
6247 13:57:08.158669 Final RX Vref Byte 1 = 49 to rank1==
6248 13:57:08.162151 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 13:57:08.164920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6250 13:57:08.165002 ==
6251 13:57:08.168113 DQS Delay:
6252 13:57:08.168193 DQS0 = 52, DQS1 = 68
6253 13:57:08.171481 DQM Delay:
6254 13:57:08.171562 DQM0 = 9, DQM1 = 16
6255 13:57:08.171626 DQ Delay:
6256 13:57:08.175468 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6257 13:57:08.178540 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6258 13:57:08.181644 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6259 13:57:08.184851 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6260 13:57:08.184932
6261 13:57:08.184997
6262 13:57:08.197171 [DQSOSCAuto] RK0, (LSB)MR18= 0xaeae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6263 13:57:08.198763 CH0 RK0: MR19=C0C, MR18=AEAE
6264 13:57:08.201620 CH0_RK0: MR19=0xC0C, MR18=0xAEAE, DQSOSC=388, MR23=63, INC=392, DEC=261
6265 13:57:08.204543 ==
6266 13:57:08.207861 Dram Type= 6, Freq= 0, CH_0, rank 1
6267 13:57:08.210969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6268 13:57:08.211052 ==
6269 13:57:08.215488 [Gating] SW mode calibration
6270 13:57:08.221391 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 13:57:08.224047 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6272 13:57:08.231327 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 13:57:08.234373 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 13:57:08.237682 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 13:57:08.244143 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6276 13:57:08.248201 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 13:57:08.250792 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 13:57:08.257250 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 13:57:08.260445 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6280 13:57:08.264110 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 13:57:08.267841 Total UI for P1: 0, mck2ui 16
6282 13:57:08.270798 best dqsien dly found for B0: ( 0, 10, 16)
6283 13:57:08.274727 Total UI for P1: 0, mck2ui 16
6284 13:57:08.277632 best dqsien dly found for B1: ( 0, 10, 16)
6285 13:57:08.280655 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6286 13:57:08.283831 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6287 13:57:08.283913
6288 13:57:08.290773 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6289 13:57:08.294010 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6290 13:57:08.297974 [Gating] SW calibration Done
6291 13:57:08.298056 ==
6292 13:57:08.300960 Dram Type= 6, Freq= 0, CH_0, rank 1
6293 13:57:08.303890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6294 13:57:08.303972 ==
6295 13:57:08.304037 RX Vref Scan: 0
6296 13:57:08.304097
6297 13:57:08.307581 RX Vref 0 -> 0, step: 1
6298 13:57:08.307663
6299 13:57:08.311896 RX Delay -410 -> 252, step: 16
6300 13:57:08.313671 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6301 13:57:08.320335 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6302 13:57:08.324025 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6303 13:57:08.326888 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6304 13:57:08.330595 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6305 13:57:08.337551 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6306 13:57:08.340125 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6307 13:57:08.343544 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6308 13:57:08.347018 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6309 13:57:08.353652 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6310 13:57:08.357540 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6311 13:57:08.360304 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6312 13:57:08.364063 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6313 13:57:08.370468 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6314 13:57:08.373739 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6315 13:57:08.377407 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6316 13:57:08.377489 ==
6317 13:57:08.380203 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 13:57:08.386593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6319 13:57:08.386676 ==
6320 13:57:08.386742 DQS Delay:
6321 13:57:08.390192 DQS0 = 43, DQS1 = 59
6322 13:57:08.390275 DQM Delay:
6323 13:57:08.390340 DQM0 = 7, DQM1 = 15
6324 13:57:08.393085 DQ Delay:
6325 13:57:08.393167 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6326 13:57:08.396746 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6327 13:57:08.399545 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6328 13:57:08.403352 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6329 13:57:08.403434
6330 13:57:08.403499
6331 13:57:08.407413 ==
6332 13:57:08.410074 Dram Type= 6, Freq= 0, CH_0, rank 1
6333 13:57:08.414036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6334 13:57:08.414119 ==
6335 13:57:08.414184
6336 13:57:08.414244
6337 13:57:08.416399 TX Vref Scan disable
6338 13:57:08.416481 == TX Byte 0 ==
6339 13:57:08.420058 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6340 13:57:08.427075 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6341 13:57:08.427156 == TX Byte 1 ==
6342 13:57:08.429877 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6343 13:57:08.436463 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6344 13:57:08.436544 ==
6345 13:57:08.439560 Dram Type= 6, Freq= 0, CH_0, rank 1
6346 13:57:08.443268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6347 13:57:08.443397 ==
6348 13:57:08.443478
6349 13:57:08.443538
6350 13:57:08.446026 TX Vref Scan disable
6351 13:57:08.446106 == TX Byte 0 ==
6352 13:57:08.449159 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6353 13:57:08.456347 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6354 13:57:08.456427 == TX Byte 1 ==
6355 13:57:08.459528 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6356 13:57:08.466173 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6357 13:57:08.466269
6358 13:57:08.466360 [DATLAT]
6359 13:57:08.466421 Freq=400, CH0 RK1
6360 13:57:08.466480
6361 13:57:08.469580 DATLAT Default: 0xd
6362 13:57:08.473563 0, 0xFFFF, sum = 0
6363 13:57:08.473645 1, 0xFFFF, sum = 0
6364 13:57:08.476211 2, 0xFFFF, sum = 0
6365 13:57:08.476291 3, 0xFFFF, sum = 0
6366 13:57:08.479690 4, 0xFFFF, sum = 0
6367 13:57:08.479770 5, 0xFFFF, sum = 0
6368 13:57:08.483415 6, 0xFFFF, sum = 0
6369 13:57:08.483508 7, 0xFFFF, sum = 0
6370 13:57:08.486242 8, 0xFFFF, sum = 0
6371 13:57:08.486323 9, 0xFFFF, sum = 0
6372 13:57:08.488992 10, 0xFFFF, sum = 0
6373 13:57:08.489073 11, 0xFFFF, sum = 0
6374 13:57:08.492385 12, 0x0, sum = 1
6375 13:57:08.492475 13, 0x0, sum = 2
6376 13:57:08.495471 14, 0x0, sum = 3
6377 13:57:08.495552 15, 0x0, sum = 4
6378 13:57:08.498545 best_step = 13
6379 13:57:08.498626
6380 13:57:08.498691 ==
6381 13:57:08.502908 Dram Type= 6, Freq= 0, CH_0, rank 1
6382 13:57:08.505473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6383 13:57:08.505593 ==
6384 13:57:08.508678 RX Vref Scan: 0
6385 13:57:08.508807
6386 13:57:08.508871 RX Vref 0 -> 0, step: 1
6387 13:57:08.508930
6388 13:57:08.512010 RX Delay -359 -> 252, step: 8
6389 13:57:08.520328 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6390 13:57:08.523479 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6391 13:57:08.526263 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6392 13:57:08.532932 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6393 13:57:08.536623 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6394 13:57:08.539554 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6395 13:57:08.543008 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6396 13:57:08.550373 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6397 13:57:08.553232 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6398 13:57:08.556559 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6399 13:57:08.559706 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6400 13:57:08.566261 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6401 13:57:08.569171 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6402 13:57:08.572977 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6403 13:57:08.575822 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6404 13:57:08.583025 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6405 13:57:08.583107 ==
6406 13:57:08.585833 Dram Type= 6, Freq= 0, CH_0, rank 1
6407 13:57:08.589977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6408 13:57:08.590059 ==
6409 13:57:08.590125 DQS Delay:
6410 13:57:08.592725 DQS0 = 52, DQS1 = 64
6411 13:57:08.592806 DQM Delay:
6412 13:57:08.595982 DQM0 = 9, DQM1 = 13
6413 13:57:08.596063 DQ Delay:
6414 13:57:08.599353 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6415 13:57:08.602539 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6416 13:57:08.606030 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6417 13:57:08.609331 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6418 13:57:08.609412
6419 13:57:08.609476
6420 13:57:08.616319 [DQSOSCAuto] RK1, (LSB)MR18= 0xcccc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6421 13:57:08.619499 CH0 RK1: MR19=C0C, MR18=CCCC
6422 13:57:08.627044 CH0_RK1: MR19=0xC0C, MR18=0xCCCC, DQSOSC=384, MR23=63, INC=400, DEC=267
6423 13:57:08.629841 [RxdqsGatingPostProcess] freq 400
6424 13:57:08.635913 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6425 13:57:08.635996 Pre-setting of DQS Precalculation
6426 13:57:08.643022 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6427 13:57:08.643105 ==
6428 13:57:08.645653 Dram Type= 6, Freq= 0, CH_1, rank 0
6429 13:57:08.649133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6430 13:57:08.649217 ==
6431 13:57:08.656190 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6432 13:57:08.662630 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6433 13:57:08.665557 [CA 0] Center 36 (8~64) winsize 57
6434 13:57:08.669394 [CA 1] Center 36 (8~64) winsize 57
6435 13:57:08.672507 [CA 2] Center 36 (8~64) winsize 57
6436 13:57:08.675899 [CA 3] Center 36 (8~64) winsize 57
6437 13:57:08.675983 [CA 4] Center 36 (8~64) winsize 57
6438 13:57:08.678989 [CA 5] Center 36 (8~64) winsize 57
6439 13:57:08.679074
6440 13:57:08.685522 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6441 13:57:08.685606
6442 13:57:08.688966 [CATrainingPosCal] consider 1 rank data
6443 13:57:08.692003 u2DelayCellTimex100 = 270/100 ps
6444 13:57:08.695720 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6445 13:57:08.698916 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 13:57:08.702066 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 13:57:08.705261 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 13:57:08.709649 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 13:57:08.712057 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6450 13:57:08.712141
6451 13:57:08.715602 CA PerBit enable=1, Macro0, CA PI delay=36
6452 13:57:08.715686
6453 13:57:08.718986 [CBTSetCACLKResult] CA Dly = 36
6454 13:57:08.722424 CS Dly: 1 (0~32)
6455 13:57:08.722507 ==
6456 13:57:08.725098 Dram Type= 6, Freq= 0, CH_1, rank 1
6457 13:57:08.728811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6458 13:57:08.728896 ==
6459 13:57:08.736373 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6460 13:57:08.742092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6461 13:57:08.745152 [CA 0] Center 36 (8~64) winsize 57
6462 13:57:08.745236 [CA 1] Center 36 (8~64) winsize 57
6463 13:57:08.749208 [CA 2] Center 36 (8~64) winsize 57
6464 13:57:08.751611 [CA 3] Center 36 (8~64) winsize 57
6465 13:57:08.755349 [CA 4] Center 36 (8~64) winsize 57
6466 13:57:08.759297 [CA 5] Center 36 (8~64) winsize 57
6467 13:57:08.759381
6468 13:57:08.762400 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6469 13:57:08.762484
6470 13:57:08.764897 [CATrainingPosCal] consider 2 rank data
6471 13:57:08.768270 u2DelayCellTimex100 = 270/100 ps
6472 13:57:08.771871 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6473 13:57:08.779368 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6474 13:57:08.781863 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6475 13:57:08.785308 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6476 13:57:08.788566 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6477 13:57:08.791812 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6478 13:57:08.791896
6479 13:57:08.795241 CA PerBit enable=1, Macro0, CA PI delay=36
6480 13:57:08.795325
6481 13:57:08.798630 [CBTSetCACLKResult] CA Dly = 36
6482 13:57:08.798714 CS Dly: 1 (0~32)
6483 13:57:08.798800
6484 13:57:08.805307 ----->DramcWriteLeveling(PI) begin...
6485 13:57:08.805392 ==
6486 13:57:08.808370 Dram Type= 6, Freq= 0, CH_1, rank 0
6487 13:57:08.811681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6488 13:57:08.811766 ==
6489 13:57:08.814907 Write leveling (Byte 0): 32 => 0
6490 13:57:08.818381 Write leveling (Byte 1): 32 => 0
6491 13:57:08.821762 DramcWriteLeveling(PI) end<-----
6492 13:57:08.821846
6493 13:57:08.821932 ==
6494 13:57:08.825134 Dram Type= 6, Freq= 0, CH_1, rank 0
6495 13:57:08.828255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6496 13:57:08.828338 ==
6497 13:57:08.832489 [Gating] SW mode calibration
6498 13:57:08.839623 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6499 13:57:08.844575 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6500 13:57:08.848023 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 13:57:08.851962 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6502 13:57:08.858000 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 13:57:08.861494 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6504 13:57:08.864296 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 13:57:08.871248 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 13:57:08.874867 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 13:57:08.877842 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6508 13:57:08.884918 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 13:57:08.885041 Total UI for P1: 0, mck2ui 16
6510 13:57:08.888220 best dqsien dly found for B0: ( 0, 10, 16)
6511 13:57:08.891940 Total UI for P1: 0, mck2ui 16
6512 13:57:08.894535 best dqsien dly found for B1: ( 0, 10, 16)
6513 13:57:08.901121 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6514 13:57:08.904168 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6515 13:57:08.904250
6516 13:57:08.907330 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6517 13:57:08.911402 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6518 13:57:08.915247 [Gating] SW calibration Done
6519 13:57:08.915329 ==
6520 13:57:08.918135 Dram Type= 6, Freq= 0, CH_1, rank 0
6521 13:57:08.920830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6522 13:57:08.920913 ==
6523 13:57:08.924003 RX Vref Scan: 0
6524 13:57:08.924084
6525 13:57:08.924169 RX Vref 0 -> 0, step: 1
6526 13:57:08.924249
6527 13:57:08.927835 RX Delay -410 -> 252, step: 16
6528 13:57:08.933613 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6529 13:57:08.937492 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6530 13:57:08.940962 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6531 13:57:08.946786 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6532 13:57:08.950768 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6533 13:57:08.953637 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6534 13:57:08.957144 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6535 13:57:08.960662 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6536 13:57:08.967614 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6537 13:57:08.970218 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6538 13:57:08.973820 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6539 13:57:08.976613 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6540 13:57:08.983559 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6541 13:57:08.987535 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6542 13:57:08.990507 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6543 13:57:08.993791 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6544 13:57:08.997150 ==
6545 13:57:09.000301 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 13:57:09.003699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 13:57:09.003782 ==
6548 13:57:09.003911 DQS Delay:
6549 13:57:09.006611 DQS0 = 43, DQS1 = 59
6550 13:57:09.006693 DQM Delay:
6551 13:57:09.010148 DQM0 = 6, DQM1 = 16
6552 13:57:09.010231 DQ Delay:
6553 13:57:09.014124 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6554 13:57:09.016605 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6555 13:57:09.020498 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6556 13:57:09.024153 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6557 13:57:09.024237
6558 13:57:09.024323
6559 13:57:09.024404 ==
6560 13:57:09.026694 Dram Type= 6, Freq= 0, CH_1, rank 0
6561 13:57:09.030643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6562 13:57:09.030728 ==
6563 13:57:09.030814
6564 13:57:09.030894
6565 13:57:09.033643 TX Vref Scan disable
6566 13:57:09.033727 == TX Byte 0 ==
6567 13:57:09.040054 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6568 13:57:09.043260 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6569 13:57:09.043345 == TX Byte 1 ==
6570 13:57:09.051008 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6571 13:57:09.054768 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6572 13:57:09.054852 ==
6573 13:57:09.056509 Dram Type= 6, Freq= 0, CH_1, rank 0
6574 13:57:09.059615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6575 13:57:09.059700 ==
6576 13:57:09.059786
6577 13:57:09.059868
6578 13:57:09.063039 TX Vref Scan disable
6579 13:57:09.066795 == TX Byte 0 ==
6580 13:57:09.070007 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6581 13:57:09.073430 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6582 13:57:09.076519 == TX Byte 1 ==
6583 13:57:09.079818 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6584 13:57:09.082904 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6585 13:57:09.082989
6586 13:57:09.083074 [DATLAT]
6587 13:57:09.086168 Freq=400, CH1 RK0
6588 13:57:09.086253
6589 13:57:09.090382 DATLAT Default: 0xf
6590 13:57:09.090466 0, 0xFFFF, sum = 0
6591 13:57:09.092941 1, 0xFFFF, sum = 0
6592 13:57:09.093026 2, 0xFFFF, sum = 0
6593 13:57:09.096190 3, 0xFFFF, sum = 0
6594 13:57:09.096275 4, 0xFFFF, sum = 0
6595 13:57:09.099658 5, 0xFFFF, sum = 0
6596 13:57:09.099744 6, 0xFFFF, sum = 0
6597 13:57:09.102710 7, 0xFFFF, sum = 0
6598 13:57:09.102795 8, 0xFFFF, sum = 0
6599 13:57:09.106193 9, 0xFFFF, sum = 0
6600 13:57:09.106281 10, 0xFFFF, sum = 0
6601 13:57:09.109636 11, 0xFFFF, sum = 0
6602 13:57:09.109722 12, 0x0, sum = 1
6603 13:57:09.113479 13, 0x0, sum = 2
6604 13:57:09.113564 14, 0x0, sum = 3
6605 13:57:09.116167 15, 0x0, sum = 4
6606 13:57:09.116253 best_step = 13
6607 13:57:09.116339
6608 13:57:09.116420 ==
6609 13:57:09.119019 Dram Type= 6, Freq= 0, CH_1, rank 0
6610 13:57:09.122447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6611 13:57:09.125925 ==
6612 13:57:09.126009 RX Vref Scan: 1
6613 13:57:09.126094
6614 13:57:09.129733 RX Vref 0 -> 0, step: 1
6615 13:57:09.129818
6616 13:57:09.132671 RX Delay -359 -> 252, step: 8
6617 13:57:09.132764
6618 13:57:09.135794 Set Vref, RX VrefLevel [Byte0]: 50
6619 13:57:09.138967 [Byte1]: 49
6620 13:57:09.139051
6621 13:57:09.142210 Final RX Vref Byte 0 = 50 to rank0
6622 13:57:09.145511 Final RX Vref Byte 1 = 49 to rank0
6623 13:57:09.148839 Final RX Vref Byte 0 = 50 to rank1
6624 13:57:09.153184 Final RX Vref Byte 1 = 49 to rank1==
6625 13:57:09.155399 Dram Type= 6, Freq= 0, CH_1, rank 0
6626 13:57:09.159455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6627 13:57:09.161771 ==
6628 13:57:09.161856 DQS Delay:
6629 13:57:09.161942 DQS0 = 48, DQS1 = 64
6630 13:57:09.165682 DQM Delay:
6631 13:57:09.165766 DQM0 = 7, DQM1 = 15
6632 13:57:09.169177 DQ Delay:
6633 13:57:09.169262 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6634 13:57:09.171927 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6635 13:57:09.175052 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6636 13:57:09.178199 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6637 13:57:09.178284
6638 13:57:09.178370
6639 13:57:09.188872 [DQSOSCAuto] RK0, (LSB)MR18= 0xd4d4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6640 13:57:09.192165 CH1 RK0: MR19=C0C, MR18=D4D4
6641 13:57:09.198851 CH1_RK0: MR19=0xC0C, MR18=0xD4D4, DQSOSC=383, MR23=63, INC=402, DEC=268
6642 13:57:09.198933 ==
6643 13:57:09.201360 Dram Type= 6, Freq= 0, CH_1, rank 1
6644 13:57:09.204806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6645 13:57:09.204889 ==
6646 13:57:09.208096 [Gating] SW mode calibration
6647 13:57:09.214574 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6648 13:57:09.217822 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6649 13:57:09.224791 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 13:57:09.227795 0 7 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
6651 13:57:09.231191 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 13:57:09.237760 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6653 13:57:09.240984 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 13:57:09.244692 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 13:57:09.251159 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 13:57:09.254380 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6657 13:57:09.258781 Total UI for P1: 0, mck2ui 16
6658 13:57:09.261110 best dqsien dly found for B0: ( 0, 10, 8)
6659 13:57:09.264211 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 13:57:09.267649 Total UI for P1: 0, mck2ui 16
6661 13:57:09.272410 best dqsien dly found for B1: ( 0, 10, 16)
6662 13:57:09.275503 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6663 13:57:09.281088 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6664 13:57:09.281173
6665 13:57:09.284235 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6666 13:57:09.287620 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6667 13:57:09.290850 [Gating] SW calibration Done
6668 13:57:09.290934 ==
6669 13:57:09.294033 Dram Type= 6, Freq= 0, CH_1, rank 1
6670 13:57:09.297066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6671 13:57:09.297151 ==
6672 13:57:09.300370 RX Vref Scan: 0
6673 13:57:09.300478
6674 13:57:09.300579 RX Vref 0 -> 0, step: 1
6675 13:57:09.300679
6676 13:57:09.303643 RX Delay -410 -> 252, step: 16
6677 13:57:09.310440 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6678 13:57:09.313558 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6679 13:57:09.316836 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6680 13:57:09.320258 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6681 13:57:09.326958 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6682 13:57:09.330132 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6683 13:57:09.333862 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6684 13:57:09.336530 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6685 13:57:09.343649 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6686 13:57:09.347105 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6687 13:57:09.350071 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6688 13:57:09.353960 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6689 13:57:09.360020 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6690 13:57:09.362970 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6691 13:57:09.366370 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6692 13:57:09.370471 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6693 13:57:09.373860 ==
6694 13:57:09.373943 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 13:57:09.380360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6696 13:57:09.380443 ==
6697 13:57:09.380544 DQS Delay:
6698 13:57:09.383177 DQS0 = 43, DQS1 = 59
6699 13:57:09.383259 DQM Delay:
6700 13:57:09.386247 DQM0 = 10, DQM1 = 17
6701 13:57:09.386329 DQ Delay:
6702 13:57:09.390121 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6703 13:57:09.393672 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6704 13:57:09.396128 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6705 13:57:09.399953 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6706 13:57:09.400036
6707 13:57:09.400120
6708 13:57:09.400199 ==
6709 13:57:09.403042 Dram Type= 6, Freq= 0, CH_1, rank 1
6710 13:57:09.406147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6711 13:57:09.406230 ==
6712 13:57:09.406329
6713 13:57:09.406425
6714 13:57:09.409720 TX Vref Scan disable
6715 13:57:09.409803 == TX Byte 0 ==
6716 13:57:09.416603 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6717 13:57:09.419550 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6718 13:57:09.419632 == TX Byte 1 ==
6719 13:57:09.423128 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6720 13:57:09.429378 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6721 13:57:09.429462 ==
6722 13:57:09.432811 Dram Type= 6, Freq= 0, CH_1, rank 1
6723 13:57:09.435974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6724 13:57:09.436057 ==
6725 13:57:09.436141
6726 13:57:09.436220
6727 13:57:09.439620 TX Vref Scan disable
6728 13:57:09.439702 == TX Byte 0 ==
6729 13:57:09.445754 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6730 13:57:09.449137 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6731 13:57:09.449220 == TX Byte 1 ==
6732 13:57:09.455977 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6733 13:57:09.459019 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6734 13:57:09.459102
6735 13:57:09.459186 [DATLAT]
6736 13:57:09.462143 Freq=400, CH1 RK1
6737 13:57:09.462226
6738 13:57:09.462310 DATLAT Default: 0xd
6739 13:57:09.466098 0, 0xFFFF, sum = 0
6740 13:57:09.466182 1, 0xFFFF, sum = 0
6741 13:57:09.469039 2, 0xFFFF, sum = 0
6742 13:57:09.469139 3, 0xFFFF, sum = 0
6743 13:57:09.473195 4, 0xFFFF, sum = 0
6744 13:57:09.473279 5, 0xFFFF, sum = 0
6745 13:57:09.475513 6, 0xFFFF, sum = 0
6746 13:57:09.475597 7, 0xFFFF, sum = 0
6747 13:57:09.479139 8, 0xFFFF, sum = 0
6748 13:57:09.479223 9, 0xFFFF, sum = 0
6749 13:57:09.482085 10, 0xFFFF, sum = 0
6750 13:57:09.486016 11, 0xFFFF, sum = 0
6751 13:57:09.486101 12, 0x0, sum = 1
6752 13:57:09.486186 13, 0x0, sum = 2
6753 13:57:09.489321 14, 0x0, sum = 3
6754 13:57:09.489405 15, 0x0, sum = 4
6755 13:57:09.491899 best_step = 13
6756 13:57:09.491981
6757 13:57:09.492065 ==
6758 13:57:09.495816 Dram Type= 6, Freq= 0, CH_1, rank 1
6759 13:57:09.499333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6760 13:57:09.499416 ==
6761 13:57:09.502047 RX Vref Scan: 0
6762 13:57:09.502127
6763 13:57:09.502192 RX Vref 0 -> 0, step: 1
6764 13:57:09.505934
6765 13:57:09.506015 RX Delay -359 -> 252, step: 8
6766 13:57:09.514402 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6767 13:57:09.517272 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6768 13:57:09.521286 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6769 13:57:09.525027 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6770 13:57:09.530562 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6771 13:57:09.533738 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6772 13:57:09.537273 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6773 13:57:09.540144 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6774 13:57:09.547291 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6775 13:57:09.549964 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6776 13:57:09.554159 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6777 13:57:09.560024 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6778 13:57:09.563543 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6779 13:57:09.566887 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6780 13:57:09.570904 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6781 13:57:09.577399 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6782 13:57:09.577482 ==
6783 13:57:09.580145 Dram Type= 6, Freq= 0, CH_1, rank 1
6784 13:57:09.583540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6785 13:57:09.583623 ==
6786 13:57:09.583689 DQS Delay:
6787 13:57:09.587056 DQS0 = 48, DQS1 = 64
6788 13:57:09.587138 DQM Delay:
6789 13:57:09.590255 DQM0 = 10, DQM1 = 15
6790 13:57:09.590337 DQ Delay:
6791 13:57:09.593287 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6792 13:57:09.597125 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =12
6793 13:57:09.600277 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6794 13:57:09.603190 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6795 13:57:09.603272
6796 13:57:09.603337
6797 13:57:09.610517 [DQSOSCAuto] RK1, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6798 13:57:09.613087 CH1 RK1: MR19=C0C, MR18=A3A3
6799 13:57:09.620113 CH1_RK1: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6800 13:57:09.623310 [RxdqsGatingPostProcess] freq 400
6801 13:57:09.630193 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6802 13:57:09.633602 Pre-setting of DQS Precalculation
6803 13:57:09.636636 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6804 13:57:09.643193 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6805 13:57:09.650166 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6806 13:57:09.650249
6807 13:57:09.650313
6808 13:57:09.653585 [Calibration Summary] 800 Mbps
6809 13:57:09.656623 CH 0, Rank 0
6810 13:57:09.656765 SW Impedance : PASS
6811 13:57:09.659676 DUTY Scan : NO K
6812 13:57:09.663170 ZQ Calibration : PASS
6813 13:57:09.663253 Jitter Meter : NO K
6814 13:57:09.666549 CBT Training : PASS
6815 13:57:09.670624 Write leveling : PASS
6816 13:57:09.670706 RX DQS gating : PASS
6817 13:57:09.673092 RX DQ/DQS(RDDQC) : PASS
6818 13:57:09.676612 TX DQ/DQS : PASS
6819 13:57:09.676742 RX DATLAT : PASS
6820 13:57:09.679517 RX DQ/DQS(Engine): PASS
6821 13:57:09.679599 TX OE : NO K
6822 13:57:09.682794 All Pass.
6823 13:57:09.682876
6824 13:57:09.682941 CH 0, Rank 1
6825 13:57:09.686556 SW Impedance : PASS
6826 13:57:09.686638 DUTY Scan : NO K
6827 13:57:09.689953 ZQ Calibration : PASS
6828 13:57:09.694105 Jitter Meter : NO K
6829 13:57:09.694187 CBT Training : PASS
6830 13:57:09.696619 Write leveling : NO K
6831 13:57:09.699904 RX DQS gating : PASS
6832 13:57:09.699986 RX DQ/DQS(RDDQC) : PASS
6833 13:57:09.702784 TX DQ/DQS : PASS
6834 13:57:09.706373 RX DATLAT : PASS
6835 13:57:09.706455 RX DQ/DQS(Engine): PASS
6836 13:57:09.710185 TX OE : NO K
6837 13:57:09.710267 All Pass.
6838 13:57:09.710332
6839 13:57:09.712856 CH 1, Rank 0
6840 13:57:09.712938 SW Impedance : PASS
6841 13:57:09.716466 DUTY Scan : NO K
6842 13:57:09.719574 ZQ Calibration : PASS
6843 13:57:09.719656 Jitter Meter : NO K
6844 13:57:09.722880 CBT Training : PASS
6845 13:57:09.726219 Write leveling : PASS
6846 13:57:09.726301 RX DQS gating : PASS
6847 13:57:09.729227 RX DQ/DQS(RDDQC) : PASS
6848 13:57:09.733389 TX DQ/DQS : PASS
6849 13:57:09.733471 RX DATLAT : PASS
6850 13:57:09.736835 RX DQ/DQS(Engine): PASS
6851 13:57:09.736916 TX OE : NO K
6852 13:57:09.739439 All Pass.
6853 13:57:09.739521
6854 13:57:09.739586 CH 1, Rank 1
6855 13:57:09.742857 SW Impedance : PASS
6856 13:57:09.742938 DUTY Scan : NO K
6857 13:57:09.745958 ZQ Calibration : PASS
6858 13:57:09.749409 Jitter Meter : NO K
6859 13:57:09.749490 CBT Training : PASS
6860 13:57:09.752669 Write leveling : NO K
6861 13:57:09.756596 RX DQS gating : PASS
6862 13:57:09.756678 RX DQ/DQS(RDDQC) : PASS
6863 13:57:09.759138 TX DQ/DQS : PASS
6864 13:57:09.762313 RX DATLAT : PASS
6865 13:57:09.762394 RX DQ/DQS(Engine): PASS
6866 13:57:09.766048 TX OE : NO K
6867 13:57:09.766131 All Pass.
6868 13:57:09.766196
6869 13:57:09.768838 DramC Write-DBI off
6870 13:57:09.773427 PER_BANK_REFRESH: Hybrid Mode
6871 13:57:09.773535 TX_TRACKING: ON
6872 13:57:09.782315 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6873 13:57:09.786374 [FAST_K] Save calibration result to emmc
6874 13:57:09.789098 dramc_set_vcore_voltage set vcore to 725000
6875 13:57:09.792295 Read voltage for 1600, 0
6876 13:57:09.792396 Vio18 = 0
6877 13:57:09.792489 Vcore = 725000
6878 13:57:09.796174 Vdram = 0
6879 13:57:09.796280 Vddq = 0
6880 13:57:09.796372 Vmddr = 0
6881 13:57:09.802039 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6882 13:57:09.806215 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6883 13:57:09.809830 MEM_TYPE=3, freq_sel=13
6884 13:57:09.812480 sv_algorithm_assistance_LP4_3733
6885 13:57:09.817086 ============ PULL DRAM RESETB DOWN ============
6886 13:57:09.819412 ========== PULL DRAM RESETB DOWN end =========
6887 13:57:09.825436 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6888 13:57:09.828661 ===================================
6889 13:57:09.832340 LPDDR4 DRAM CONFIGURATION
6890 13:57:09.836306 ===================================
6891 13:57:09.836412 EX_ROW_EN[0] = 0x0
6892 13:57:09.839062 EX_ROW_EN[1] = 0x0
6893 13:57:09.839167 LP4Y_EN = 0x0
6894 13:57:09.843231 WORK_FSP = 0x1
6895 13:57:09.843336 WL = 0x5
6896 13:57:09.845259 RL = 0x5
6897 13:57:09.845363 BL = 0x2
6898 13:57:09.848981 RPST = 0x0
6899 13:57:09.849086 RD_PRE = 0x0
6900 13:57:09.852431 WR_PRE = 0x1
6901 13:57:09.852537 WR_PST = 0x1
6902 13:57:09.855625 DBI_WR = 0x0
6903 13:57:09.858503 DBI_RD = 0x0
6904 13:57:09.858608 OTF = 0x1
6905 13:57:09.862250 ===================================
6906 13:57:09.864962 ===================================
6907 13:57:09.865068 ANA top config
6908 13:57:09.868991 ===================================
6909 13:57:09.871738 DLL_ASYNC_EN = 0
6910 13:57:09.874912 ALL_SLAVE_EN = 0
6911 13:57:09.878861 NEW_RANK_MODE = 1
6912 13:57:09.881440 DLL_IDLE_MODE = 1
6913 13:57:09.881546 LP45_APHY_COMB_EN = 1
6914 13:57:09.885164 TX_ODT_DIS = 0
6915 13:57:09.888549 NEW_8X_MODE = 1
6916 13:57:09.892314 ===================================
6917 13:57:09.895686 ===================================
6918 13:57:09.898646 data_rate = 3200
6919 13:57:09.901281 CKR = 1
6920 13:57:09.901383 DQ_P2S_RATIO = 8
6921 13:57:09.904800 ===================================
6922 13:57:09.908594 CA_P2S_RATIO = 8
6923 13:57:09.911937 DQ_CA_OPEN = 0
6924 13:57:09.914923 DQ_SEMI_OPEN = 0
6925 13:57:09.917913 CA_SEMI_OPEN = 0
6926 13:57:09.922164 CA_FULL_RATE = 0
6927 13:57:09.922269 DQ_CKDIV4_EN = 0
6928 13:57:09.926259 CA_CKDIV4_EN = 0
6929 13:57:09.929820 CA_PREDIV_EN = 0
6930 13:57:09.932614 PH8_DLY = 12
6931 13:57:09.934618 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6932 13:57:09.938051 DQ_AAMCK_DIV = 4
6933 13:57:09.938152 CA_AAMCK_DIV = 4
6934 13:57:09.941168 CA_ADMCK_DIV = 4
6935 13:57:09.944313 DQ_TRACK_CA_EN = 0
6936 13:57:09.947957 CA_PICK = 1600
6937 13:57:09.951517 CA_MCKIO = 1600
6938 13:57:09.954331 MCKIO_SEMI = 0
6939 13:57:09.958824 PLL_FREQ = 3068
6940 13:57:09.961270 DQ_UI_PI_RATIO = 32
6941 13:57:09.961373 CA_UI_PI_RATIO = 0
6942 13:57:09.964169 ===================================
6943 13:57:09.968246 ===================================
6944 13:57:09.970758 memory_type:LPDDR4
6945 13:57:09.974929 GP_NUM : 10
6946 13:57:09.975030 SRAM_EN : 1
6947 13:57:09.977384 MD32_EN : 0
6948 13:57:09.980947 ===================================
6949 13:57:09.984402 [ANA_INIT] >>>>>>>>>>>>>>
6950 13:57:09.987539 <<<<<< [CONFIGURE PHASE]: ANA_TX
6951 13:57:09.990898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6952 13:57:09.994420 ===================================
6953 13:57:09.994525 data_rate = 3200,PCW = 0X7600
6954 13:57:09.998166 ===================================
6955 13:57:10.000683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6956 13:57:10.007384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6957 13:57:10.013801 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6958 13:57:10.017651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6959 13:57:10.020856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6960 13:57:10.024109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6961 13:57:10.027871 [ANA_INIT] flow start
6962 13:57:10.030874 [ANA_INIT] PLL >>>>>>>>
6963 13:57:10.030977 [ANA_INIT] PLL <<<<<<<<
6964 13:57:10.033765 [ANA_INIT] MIDPI >>>>>>>>
6965 13:57:10.038421 [ANA_INIT] MIDPI <<<<<<<<
6966 13:57:10.038525 [ANA_INIT] DLL >>>>>>>>
6967 13:57:10.040100 [ANA_INIT] DLL <<<<<<<<
6968 13:57:10.044082 [ANA_INIT] flow end
6969 13:57:10.047182 ============ LP4 DIFF to SE enter ============
6970 13:57:10.050234 ============ LP4 DIFF to SE exit ============
6971 13:57:10.053457 [ANA_INIT] <<<<<<<<<<<<<
6972 13:57:10.057802 [Flow] Enable top DCM control >>>>>
6973 13:57:10.061095 [Flow] Enable top DCM control <<<<<
6974 13:57:10.063851 Enable DLL master slave shuffle
6975 13:57:10.066764 ==============================================================
6976 13:57:10.070689 Gating Mode config
6977 13:57:10.077007 ==============================================================
6978 13:57:10.077117 Config description:
6979 13:57:10.087318 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6980 13:57:10.093582 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6981 13:57:10.096782 SELPH_MODE 0: By rank 1: By Phase
6982 13:57:10.104212 ==============================================================
6983 13:57:10.106559 GAT_TRACK_EN = 1
6984 13:57:10.110251 RX_GATING_MODE = 2
6985 13:57:10.112972 RX_GATING_TRACK_MODE = 2
6986 13:57:10.116434 SELPH_MODE = 1
6987 13:57:10.120222 PICG_EARLY_EN = 1
6988 13:57:10.123616 VALID_LAT_VALUE = 1
6989 13:57:10.126824 ==============================================================
6990 13:57:10.129498 Enter into Gating configuration >>>>
6991 13:57:10.132701 Exit from Gating configuration <<<<
6992 13:57:10.136165 Enter into DVFS_PRE_config >>>>>
6993 13:57:10.149225 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6994 13:57:10.153271 Exit from DVFS_PRE_config <<<<<
6995 13:57:10.156928 Enter into PICG configuration >>>>
6996 13:57:10.157034 Exit from PICG configuration <<<<
6997 13:57:10.159361 [RX_INPUT] configuration >>>>>
6998 13:57:10.162867 [RX_INPUT] configuration <<<<<
6999 13:57:10.169301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7000 13:57:10.172369 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7001 13:57:10.179271 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7002 13:57:10.185517 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7003 13:57:10.192579 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7004 13:57:10.199047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7005 13:57:10.202179 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7006 13:57:10.206009 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7007 13:57:10.212507 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7008 13:57:10.215388 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7009 13:57:10.218555 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7010 13:57:10.222318 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7011 13:57:10.225329 ===================================
7012 13:57:10.228924 LPDDR4 DRAM CONFIGURATION
7013 13:57:10.232033 ===================================
7014 13:57:10.236029 EX_ROW_EN[0] = 0x0
7015 13:57:10.236133 EX_ROW_EN[1] = 0x0
7016 13:57:10.238453 LP4Y_EN = 0x0
7017 13:57:10.238556 WORK_FSP = 0x1
7018 13:57:10.242229 WL = 0x5
7019 13:57:10.242333 RL = 0x5
7020 13:57:10.246387 BL = 0x2
7021 13:57:10.246491 RPST = 0x0
7022 13:57:10.249214 RD_PRE = 0x0
7023 13:57:10.249316 WR_PRE = 0x1
7024 13:57:10.252216 WR_PST = 0x1
7025 13:57:10.252321 DBI_WR = 0x0
7026 13:57:10.255332 DBI_RD = 0x0
7027 13:57:10.258721 OTF = 0x1
7028 13:57:10.262219 ===================================
7029 13:57:10.265308 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7030 13:57:10.268861 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7031 13:57:10.271832 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7032 13:57:10.275328 ===================================
7033 13:57:10.278246 LPDDR4 DRAM CONFIGURATION
7034 13:57:10.281667 ===================================
7035 13:57:10.285488 EX_ROW_EN[0] = 0x10
7036 13:57:10.285586 EX_ROW_EN[1] = 0x0
7037 13:57:10.288141 LP4Y_EN = 0x0
7038 13:57:10.288245 WORK_FSP = 0x1
7039 13:57:10.291419 WL = 0x5
7040 13:57:10.291519 RL = 0x5
7041 13:57:10.295018 BL = 0x2
7042 13:57:10.295119 RPST = 0x0
7043 13:57:10.298629 RD_PRE = 0x0
7044 13:57:10.298732 WR_PRE = 0x1
7045 13:57:10.301490 WR_PST = 0x1
7046 13:57:10.301592 DBI_WR = 0x0
7047 13:57:10.304859 DBI_RD = 0x0
7048 13:57:10.304959 OTF = 0x1
7049 13:57:10.309255 ===================================
7050 13:57:10.314968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7051 13:57:10.315073 ==
7052 13:57:10.318261 Dram Type= 6, Freq= 0, CH_0, rank 0
7053 13:57:10.324976 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7054 13:57:10.325084 ==
7055 13:57:10.325175 [Duty_Offset_Calibration]
7056 13:57:10.327858 B0:0 B1:2 CA:1
7057 13:57:10.327961
7058 13:57:10.331456 [DutyScan_Calibration_Flow] k_type=0
7059 13:57:10.340559
7060 13:57:10.340662 ==CLK 0==
7061 13:57:10.344100 Final CLK duty delay cell = 0
7062 13:57:10.348930 [0] MAX Duty = 5156%(X100), DQS PI = 22
7063 13:57:10.351145 [0] MIN Duty = 4938%(X100), DQS PI = 50
7064 13:57:10.351249 [0] AVG Duty = 5047%(X100)
7065 13:57:10.354090
7066 13:57:10.357947 CH0 CLK Duty spec in!! Max-Min= 218%
7067 13:57:10.360926 [DutyScan_Calibration_Flow] ====Done====
7068 13:57:10.361025
7069 13:57:10.364389 [DutyScan_Calibration_Flow] k_type=1
7070 13:57:10.381160
7071 13:57:10.381263 ==DQS 0 ==
7072 13:57:10.384019 Final DQS duty delay cell = 0
7073 13:57:10.387643 [0] MAX Duty = 5156%(X100), DQS PI = 34
7074 13:57:10.390919 [0] MIN Duty = 5031%(X100), DQS PI = 8
7075 13:57:10.394437 [0] AVG Duty = 5093%(X100)
7076 13:57:10.394539
7077 13:57:10.394627 ==DQS 1 ==
7078 13:57:10.397506 Final DQS duty delay cell = 0
7079 13:57:10.400497 [0] MAX Duty = 5031%(X100), DQS PI = 4
7080 13:57:10.404380 [0] MIN Duty = 4876%(X100), DQS PI = 16
7081 13:57:10.407105 [0] AVG Duty = 4953%(X100)
7082 13:57:10.407208
7083 13:57:10.410821 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7084 13:57:10.410926
7085 13:57:10.413936 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7086 13:57:10.418016 [DutyScan_Calibration_Flow] ====Done====
7087 13:57:10.418122
7088 13:57:10.420298 [DutyScan_Calibration_Flow] k_type=3
7089 13:57:10.438308
7090 13:57:10.438414 ==DQM 0 ==
7091 13:57:10.441122 Final DQM duty delay cell = 0
7092 13:57:10.444675 [0] MAX Duty = 5187%(X100), DQS PI = 22
7093 13:57:10.447928 [0] MIN Duty = 4907%(X100), DQS PI = 44
7094 13:57:10.453505 [0] AVG Duty = 5047%(X100)
7095 13:57:10.453612
7096 13:57:10.453704 ==DQM 1 ==
7097 13:57:10.454851 Final DQM duty delay cell = 0
7098 13:57:10.458164 [0] MAX Duty = 5031%(X100), DQS PI = 4
7099 13:57:10.461188 [0] MIN Duty = 4782%(X100), DQS PI = 14
7100 13:57:10.465337 [0] AVG Duty = 4906%(X100)
7101 13:57:10.465443
7102 13:57:10.468098 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7103 13:57:10.468203
7104 13:57:10.471888 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7105 13:57:10.474486 [DutyScan_Calibration_Flow] ====Done====
7106 13:57:10.474592
7107 13:57:10.477609 [DutyScan_Calibration_Flow] k_type=2
7108 13:57:10.494561
7109 13:57:10.494668 ==DQ 0 ==
7110 13:57:10.497765 Final DQ duty delay cell = 0
7111 13:57:10.501159 [0] MAX Duty = 5218%(X100), DQS PI = 20
7112 13:57:10.504897 [0] MIN Duty = 4938%(X100), DQS PI = 56
7113 13:57:10.505000 [0] AVG Duty = 5078%(X100)
7114 13:57:10.507622
7115 13:57:10.507725 ==DQ 1 ==
7116 13:57:10.510836 Final DQ duty delay cell = -4
7117 13:57:10.513955 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7118 13:57:10.517400 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7119 13:57:10.520702 [-4] AVG Duty = 4953%(X100)
7120 13:57:10.520813
7121 13:57:10.524050 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7122 13:57:10.524167
7123 13:57:10.528851 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7124 13:57:10.530638 [DutyScan_Calibration_Flow] ====Done====
7125 13:57:10.530740 ==
7126 13:57:10.534060 Dram Type= 6, Freq= 0, CH_1, rank 0
7127 13:57:10.537498 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7128 13:57:10.537600 ==
7129 13:57:10.541346 [Duty_Offset_Calibration]
7130 13:57:10.541448 B0:0 B1:5 CA:-5
7131 13:57:10.541537
7132 13:57:10.544266 [DutyScan_Calibration_Flow] k_type=0
7133 13:57:10.555954
7134 13:57:10.556057 ==CLK 0==
7135 13:57:10.558922 Final CLK duty delay cell = 0
7136 13:57:10.561998 [0] MAX Duty = 5156%(X100), DQS PI = 22
7137 13:57:10.564936 [0] MIN Duty = 4906%(X100), DQS PI = 50
7138 13:57:10.565041 [0] AVG Duty = 5031%(X100)
7139 13:57:10.568237
7140 13:57:10.571506 CH1 CLK Duty spec in!! Max-Min= 250%
7141 13:57:10.574812 [DutyScan_Calibration_Flow] ====Done====
7142 13:57:10.574915
7143 13:57:10.577897 [DutyScan_Calibration_Flow] k_type=1
7144 13:57:10.593711
7145 13:57:10.593816 ==DQS 0 ==
7146 13:57:10.597511 Final DQS duty delay cell = 0
7147 13:57:10.600068 [0] MAX Duty = 5187%(X100), DQS PI = 20
7148 13:57:10.603918 [0] MIN Duty = 4876%(X100), DQS PI = 44
7149 13:57:10.607004 [0] AVG Duty = 5031%(X100)
7150 13:57:10.607109
7151 13:57:10.607200 ==DQS 1 ==
7152 13:57:10.610486 Final DQS duty delay cell = -4
7153 13:57:10.613646 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7154 13:57:10.617276 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7155 13:57:10.620466 [-4] AVG Duty = 4922%(X100)
7156 13:57:10.620571
7157 13:57:10.623406 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7158 13:57:10.623510
7159 13:57:10.626868 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7160 13:57:10.631110 [DutyScan_Calibration_Flow] ====Done====
7161 13:57:10.631215
7162 13:57:10.633180 [DutyScan_Calibration_Flow] k_type=3
7163 13:57:10.649469
7164 13:57:10.649576 ==DQM 0 ==
7165 13:57:10.652907 Final DQM duty delay cell = -4
7166 13:57:10.656593 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7167 13:57:10.659874 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7168 13:57:10.662878 [-4] AVG Duty = 4922%(X100)
7169 13:57:10.662980
7170 13:57:10.663070 ==DQM 1 ==
7171 13:57:10.666551 Final DQM duty delay cell = -4
7172 13:57:10.669697 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7173 13:57:10.672830 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7174 13:57:10.675851 [-4] AVG Duty = 4984%(X100)
7175 13:57:10.675951
7176 13:57:10.680121 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7177 13:57:10.680224
7178 13:57:10.682942 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7179 13:57:10.686002 [DutyScan_Calibration_Flow] ====Done====
7180 13:57:10.686108
7181 13:57:10.689105 [DutyScan_Calibration_Flow] k_type=2
7182 13:57:10.708154
7183 13:57:10.708259 ==DQ 0 ==
7184 13:57:10.710308 Final DQ duty delay cell = 0
7185 13:57:10.714170 [0] MAX Duty = 5093%(X100), DQS PI = 18
7186 13:57:10.717081 [0] MIN Duty = 4969%(X100), DQS PI = 46
7187 13:57:10.717186 [0] AVG Duty = 5031%(X100)
7188 13:57:10.720814
7189 13:57:10.720919 ==DQ 1 ==
7190 13:57:10.723626 Final DQ duty delay cell = 0
7191 13:57:10.727334 [0] MAX Duty = 5031%(X100), DQS PI = 4
7192 13:57:10.730067 [0] MIN Duty = 4875%(X100), DQS PI = 28
7193 13:57:10.730172 [0] AVG Duty = 4953%(X100)
7194 13:57:10.733214
7195 13:57:10.736507 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7196 13:57:10.736612
7197 13:57:10.739901 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7198 13:57:10.743110 [DutyScan_Calibration_Flow] ====Done====
7199 13:57:10.746813 nWR fixed to 30
7200 13:57:10.749598 [ModeRegInit_LP4] CH0 RK0
7201 13:57:10.749699 [ModeRegInit_LP4] CH0 RK1
7202 13:57:10.754009 [ModeRegInit_LP4] CH1 RK0
7203 13:57:10.756669 [ModeRegInit_LP4] CH1 RK1
7204 13:57:10.756810 match AC timing 4
7205 13:57:10.762966 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7206 13:57:10.766224 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7207 13:57:10.769923 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7208 13:57:10.776122 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7209 13:57:10.779603 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7210 13:57:10.779707 [MiockJmeterHQA]
7211 13:57:10.779796
7212 13:57:10.782499 [DramcMiockJmeter] u1RxGatingPI = 0
7213 13:57:10.786711 0 : 4252, 4027
7214 13:57:10.786819 4 : 4252, 4027
7215 13:57:10.789484 8 : 4366, 4140
7216 13:57:10.789595 12 : 4366, 4140
7217 13:57:10.793148 16 : 4363, 4137
7218 13:57:10.793257 20 : 4252, 4027
7219 13:57:10.793349 24 : 4252, 4027
7220 13:57:10.796008 28 : 4252, 4027
7221 13:57:10.796113 32 : 4255, 4030
7222 13:57:10.799169 36 : 4253, 4026
7223 13:57:10.799274 40 : 4363, 4138
7224 13:57:10.802478 44 : 4252, 4026
7225 13:57:10.802583 48 : 4252, 4027
7226 13:57:10.806043 52 : 4252, 4027
7227 13:57:10.806150 56 : 4253, 4026
7228 13:57:10.806243 60 : 4250, 4027
7229 13:57:10.809547 64 : 4361, 4137
7230 13:57:10.809652 68 : 4361, 4137
7231 13:57:10.812382 72 : 4250, 4027
7232 13:57:10.812489 76 : 4249, 4027
7233 13:57:10.816758 80 : 4250, 4027
7234 13:57:10.816866 84 : 4250, 4027
7235 13:57:10.816960 88 : 4250, 4026
7236 13:57:10.819624 92 : 4360, 4138
7237 13:57:10.819731 96 : 4252, 4026
7238 13:57:10.822111 100 : 4250, 2107
7239 13:57:10.822216 104 : 4360, 0
7240 13:57:10.826506 108 : 4361, 0
7241 13:57:10.826611 112 : 4363, 0
7242 13:57:10.826702 116 : 4249, 0
7243 13:57:10.829515 120 : 4360, 0
7244 13:57:10.829619 124 : 4249, 0
7245 13:57:10.833279 128 : 4249, 0
7246 13:57:10.833383 132 : 4250, 0
7247 13:57:10.833475 136 : 4252, 0
7248 13:57:10.836499 140 : 4249, 0
7249 13:57:10.836602 144 : 4250, 0
7250 13:57:10.839270 148 : 4250, 0
7251 13:57:10.839373 152 : 4361, 0
7252 13:57:10.839458 156 : 4249, 0
7253 13:57:10.842719 160 : 4361, 0
7254 13:57:10.842823 164 : 4250, 0
7255 13:57:10.842915 168 : 4250, 0
7256 13:57:10.845439 172 : 4363, 0
7257 13:57:10.845544 176 : 4252, 0
7258 13:57:10.848762 180 : 4250, 0
7259 13:57:10.848880 184 : 4250, 0
7260 13:57:10.848973 188 : 4250, 0
7261 13:57:10.852095 192 : 4249, 0
7262 13:57:10.852200 196 : 4250, 0
7263 13:57:10.855753 200 : 4250, 0
7264 13:57:10.855857 204 : 4361, 0
7265 13:57:10.855950 208 : 4360, 0
7266 13:57:10.859252 212 : 4361, 0
7267 13:57:10.859358 216 : 4249, 0
7268 13:57:10.862863 220 : 4249, 472
7269 13:57:10.862968 224 : 4249, 4006
7270 13:57:10.866802 228 : 4363, 4140
7271 13:57:10.866907 232 : 4250, 4027
7272 13:57:10.866999 236 : 4250, 4027
7273 13:57:10.869275 240 : 4249, 4027
7274 13:57:10.869380 244 : 4250, 4027
7275 13:57:10.872582 248 : 4250, 4027
7276 13:57:10.872690 252 : 4249, 4027
7277 13:57:10.875567 256 : 4361, 4137
7278 13:57:10.875671 260 : 4250, 4026
7279 13:57:10.878904 264 : 4250, 4027
7280 13:57:10.879009 268 : 4360, 4138
7281 13:57:10.882858 272 : 4250, 4027
7282 13:57:10.882961 276 : 4249, 4027
7283 13:57:10.886318 280 : 4361, 4137
7284 13:57:10.886423 284 : 4250, 4027
7285 13:57:10.890213 288 : 4250, 4027
7286 13:57:10.890320 292 : 4250, 4026
7287 13:57:10.892394 296 : 4250, 4026
7288 13:57:10.892499 300 : 4250, 4027
7289 13:57:10.892590 304 : 4250, 4027
7290 13:57:10.895397 308 : 4361, 4137
7291 13:57:10.895502 312 : 4250, 4026
7292 13:57:10.898575 316 : 4250, 4027
7293 13:57:10.898680 320 : 4360, 4138
7294 13:57:10.901967 324 : 4250, 4027
7295 13:57:10.902071 328 : 4250, 4027
7296 13:57:10.905383 332 : 4361, 4137
7297 13:57:10.905489 336 : 4250, 3860
7298 13:57:10.908613 340 : 4250, 1888
7299 13:57:10.908765
7300 13:57:10.908853 MIOCK jitter meter ch=0
7301 13:57:10.908946
7302 13:57:10.911807 1T = (340-100) = 240 dly cells
7303 13:57:10.918319 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7304 13:57:10.918425 ==
7305 13:57:10.921768 Dram Type= 6, Freq= 0, CH_0, rank 0
7306 13:57:10.925314 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7307 13:57:10.925443 ==
7308 13:57:10.931964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7309 13:57:10.934937 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7310 13:57:10.941938 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7311 13:57:10.944653 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7312 13:57:10.954387 [CA 0] Center 42 (12~72) winsize 61
7313 13:57:10.957743 [CA 1] Center 41 (11~72) winsize 62
7314 13:57:10.961537 [CA 2] Center 37 (7~68) winsize 62
7315 13:57:10.965676 [CA 3] Center 37 (7~67) winsize 61
7316 13:57:10.967662 [CA 4] Center 35 (5~66) winsize 62
7317 13:57:10.970770 [CA 5] Center 35 (5~65) winsize 61
7318 13:57:10.970871
7319 13:57:10.974240 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7320 13:57:10.974325
7321 13:57:10.978101 [CATrainingPosCal] consider 1 rank data
7322 13:57:10.981469 u2DelayCellTimex100 = 271/100 ps
7323 13:57:10.984154 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7324 13:57:10.990650 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7325 13:57:10.993954 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7326 13:57:10.998822 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7327 13:57:11.001060 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7328 13:57:11.004353 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7329 13:57:11.004436
7330 13:57:11.008024 CA PerBit enable=1, Macro0, CA PI delay=35
7331 13:57:11.008107
7332 13:57:11.011635 [CBTSetCACLKResult] CA Dly = 35
7333 13:57:11.013798 CS Dly: 11 (0~42)
7334 13:57:11.017139 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7335 13:57:11.021450 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7336 13:57:11.021533 ==
7337 13:57:11.023818 Dram Type= 6, Freq= 0, CH_0, rank 1
7338 13:57:11.026893 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7339 13:57:11.030439 ==
7340 13:57:11.033988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7341 13:57:11.037924 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7342 13:57:11.044129 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7343 13:57:11.049986 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7344 13:57:11.058292 [CA 0] Center 42 (12~73) winsize 62
7345 13:57:11.059942 [CA 1] Center 42 (12~73) winsize 62
7346 13:57:11.063259 [CA 2] Center 38 (9~68) winsize 60
7347 13:57:11.067434 [CA 3] Center 38 (9~68) winsize 60
7348 13:57:11.070198 [CA 4] Center 36 (6~66) winsize 61
7349 13:57:11.073577 [CA 5] Center 36 (6~66) winsize 61
7350 13:57:11.073685
7351 13:57:11.076545 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7352 13:57:11.076628
7353 13:57:11.080886 [CATrainingPosCal] consider 2 rank data
7354 13:57:11.083354 u2DelayCellTimex100 = 271/100 ps
7355 13:57:11.090550 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7356 13:57:11.093413 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7357 13:57:11.096549 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7358 13:57:11.099773 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7359 13:57:11.103781 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7360 13:57:11.106452 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7361 13:57:11.106538
7362 13:57:11.110356 CA PerBit enable=1, Macro0, CA PI delay=35
7363 13:57:11.110438
7364 13:57:11.112701 [CBTSetCACLKResult] CA Dly = 35
7365 13:57:11.116227 CS Dly: 11 (0~42)
7366 13:57:11.120063 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7367 13:57:11.123467 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7368 13:57:11.123555
7369 13:57:11.126232 ----->DramcWriteLeveling(PI) begin...
7370 13:57:11.126313 ==
7371 13:57:11.129466 Dram Type= 6, Freq= 0, CH_0, rank 0
7372 13:57:11.135971 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7373 13:57:11.136074 ==
7374 13:57:11.139339 Write leveling (Byte 0): 29 => 29
7375 13:57:11.143323 Write leveling (Byte 1): 25 => 25
7376 13:57:11.146247 DramcWriteLeveling(PI) end<-----
7377 13:57:11.146329
7378 13:57:11.146391 ==
7379 13:57:11.149440 Dram Type= 6, Freq= 0, CH_0, rank 0
7380 13:57:11.153051 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7381 13:57:11.153135 ==
7382 13:57:11.156009 [Gating] SW mode calibration
7383 13:57:11.163022 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7384 13:57:11.168888 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7385 13:57:11.172667 0 12 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7386 13:57:11.175449 0 12 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
7387 13:57:11.179534 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7388 13:57:11.185501 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7389 13:57:11.189462 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7390 13:57:11.192631 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7391 13:57:11.198631 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7392 13:57:11.202046 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7393 13:57:11.205368 0 13 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7394 13:57:11.211903 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
7395 13:57:11.216605 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7396 13:57:11.218414 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7397 13:57:11.226679 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7398 13:57:11.229045 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 13:57:11.232423 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7400 13:57:11.238971 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7401 13:57:11.241787 0 14 0 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7402 13:57:11.245230 0 14 4 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
7403 13:57:11.251881 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7404 13:57:11.254718 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7405 13:57:11.258132 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 13:57:11.264921 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 13:57:11.268203 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7408 13:57:11.272221 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7409 13:57:11.277765 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7410 13:57:11.281407 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7411 13:57:11.286300 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7412 13:57:11.291953 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 13:57:11.294500 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 13:57:11.297551 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 13:57:11.305208 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 13:57:11.307770 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 13:57:11.311386 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 13:57:11.317836 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 13:57:11.320974 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 13:57:11.324035 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 13:57:11.331076 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 13:57:11.333956 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 13:57:11.337196 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 13:57:11.345218 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7425 13:57:11.348095 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7426 13:57:11.351525 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7427 13:57:11.354471 Total UI for P1: 0, mck2ui 16
7428 13:57:11.358250 best dqsien dly found for B0: ( 1, 0, 30)
7429 13:57:11.364043 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7430 13:57:11.364136 Total UI for P1: 0, mck2ui 16
7431 13:57:11.370389 best dqsien dly found for B1: ( 1, 1, 4)
7432 13:57:11.373965 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7433 13:57:11.377840 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7434 13:57:11.377934
7435 13:57:11.381488 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7436 13:57:11.384006 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7437 13:57:11.388144 [Gating] SW calibration Done
7438 13:57:11.388248 ==
7439 13:57:11.390320 Dram Type= 6, Freq= 0, CH_0, rank 0
7440 13:57:11.394196 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7441 13:57:11.394281 ==
7442 13:57:11.397245 RX Vref Scan: 0
7443 13:57:11.397329
7444 13:57:11.397394 RX Vref 0 -> 0, step: 1
7445 13:57:11.397499
7446 13:57:11.400512 RX Delay 0 -> 252, step: 8
7447 13:57:11.403715 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7448 13:57:11.410377 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7449 13:57:11.414951 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7450 13:57:11.417335 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7451 13:57:11.420347 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7452 13:57:11.423752 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7453 13:57:11.430622 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7454 13:57:11.434295 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7455 13:57:11.436681 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7456 13:57:11.440370 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7457 13:57:11.444198 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7458 13:57:11.449958 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7459 13:57:11.453819 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7460 13:57:11.456312 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7461 13:57:11.461030 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7462 13:57:11.466716 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7463 13:57:11.466811 ==
7464 13:57:11.470673 Dram Type= 6, Freq= 0, CH_0, rank 0
7465 13:57:11.473896 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7466 13:57:11.473990 ==
7467 13:57:11.474057 DQS Delay:
7468 13:57:11.476277 DQS0 = 0, DQS1 = 0
7469 13:57:11.476363 DQM Delay:
7470 13:57:11.480173 DQM0 = 129, DQM1 = 124
7471 13:57:11.480259 DQ Delay:
7472 13:57:11.483238 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7473 13:57:11.486350 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7474 13:57:11.489598 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7475 13:57:11.492864 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7476 13:57:11.492951
7477 13:57:11.493018
7478 13:57:11.496903 ==
7479 13:57:11.496990 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 13:57:11.502825 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7481 13:57:11.502915 ==
7482 13:57:11.502982
7483 13:57:11.503042
7484 13:57:11.506373 TX Vref Scan disable
7485 13:57:11.506458 == TX Byte 0 ==
7486 13:57:11.509769 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7487 13:57:11.516173 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7488 13:57:11.516262 == TX Byte 1 ==
7489 13:57:11.519314 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7490 13:57:11.525939 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7491 13:57:11.526029 ==
7492 13:57:11.529450 Dram Type= 6, Freq= 0, CH_0, rank 0
7493 13:57:11.532815 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7494 13:57:11.532902 ==
7495 13:57:11.546750
7496 13:57:11.551121 TX Vref early break, caculate TX vref
7497 13:57:11.553664 TX Vref=16, minBit 9, minWin=22, winSum=371
7498 13:57:11.557304 TX Vref=18, minBit 10, minWin=22, winSum=382
7499 13:57:11.560232 TX Vref=20, minBit 8, minWin=23, winSum=388
7500 13:57:11.563815 TX Vref=22, minBit 10, minWin=23, winSum=398
7501 13:57:11.566580 TX Vref=24, minBit 8, minWin=24, winSum=406
7502 13:57:11.573548 TX Vref=26, minBit 7, minWin=25, winSum=413
7503 13:57:11.576763 TX Vref=28, minBit 4, minWin=25, winSum=414
7504 13:57:11.580540 TX Vref=30, minBit 8, minWin=24, winSum=407
7505 13:57:11.583715 TX Vref=32, minBit 8, minWin=23, winSum=400
7506 13:57:11.587180 TX Vref=34, minBit 3, minWin=24, winSum=395
7507 13:57:11.590852 TX Vref=36, minBit 6, minWin=23, winSum=384
7508 13:57:11.596869 [TxChooseVref] Worse bit 4, Min win 25, Win sum 414, Final Vref 28
7509 13:57:11.596968
7510 13:57:11.600219 Final TX Range 0 Vref 28
7511 13:57:11.600306
7512 13:57:11.600371 ==
7513 13:57:11.603317 Dram Type= 6, Freq= 0, CH_0, rank 0
7514 13:57:11.606657 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7515 13:57:11.606748 ==
7516 13:57:11.606814
7517 13:57:11.609687
7518 13:57:11.609816 TX Vref Scan disable
7519 13:57:11.616454 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7520 13:57:11.616554 == TX Byte 0 ==
7521 13:57:11.619976 u2DelayCellOfst[0]=10 cells (3 PI)
7522 13:57:11.623707 u2DelayCellOfst[1]=18 cells (5 PI)
7523 13:57:11.626567 u2DelayCellOfst[2]=14 cells (4 PI)
7524 13:57:11.630774 u2DelayCellOfst[3]=14 cells (4 PI)
7525 13:57:11.633259 u2DelayCellOfst[4]=7 cells (2 PI)
7526 13:57:11.636165 u2DelayCellOfst[5]=0 cells (0 PI)
7527 13:57:11.639735 u2DelayCellOfst[6]=18 cells (5 PI)
7528 13:57:11.642673 u2DelayCellOfst[7]=18 cells (5 PI)
7529 13:57:11.646230 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7530 13:57:11.649523 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7531 13:57:11.653313 == TX Byte 1 ==
7532 13:57:11.656324 u2DelayCellOfst[8]=3 cells (1 PI)
7533 13:57:11.659636 u2DelayCellOfst[9]=0 cells (0 PI)
7534 13:57:11.662688 u2DelayCellOfst[10]=10 cells (3 PI)
7535 13:57:11.666030 u2DelayCellOfst[11]=3 cells (1 PI)
7536 13:57:11.666116 u2DelayCellOfst[12]=18 cells (5 PI)
7537 13:57:11.669423 u2DelayCellOfst[13]=14 cells (4 PI)
7538 13:57:11.673187 u2DelayCellOfst[14]=18 cells (5 PI)
7539 13:57:11.675847 u2DelayCellOfst[15]=14 cells (4 PI)
7540 13:57:11.684541 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7541 13:57:11.686067 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7542 13:57:11.686154 DramC Write-DBI on
7543 13:57:11.689991 ==
7544 13:57:11.692406 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 13:57:11.696376 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7546 13:57:11.696464 ==
7547 13:57:11.696530
7548 13:57:11.696590
7549 13:57:11.699178 TX Vref Scan disable
7550 13:57:11.699261 == TX Byte 0 ==
7551 13:57:11.706550 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7552 13:57:11.706653 == TX Byte 1 ==
7553 13:57:11.709417 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7554 13:57:11.713165 DramC Write-DBI off
7555 13:57:11.713256
7556 13:57:11.713322 [DATLAT]
7557 13:57:11.716490 Freq=1600, CH0 RK0
7558 13:57:11.716576
7559 13:57:11.716641 DATLAT Default: 0xf
7560 13:57:11.719237 0, 0xFFFF, sum = 0
7561 13:57:11.719335 1, 0xFFFF, sum = 0
7562 13:57:11.722513 2, 0xFFFF, sum = 0
7563 13:57:11.722599 3, 0xFFFF, sum = 0
7564 13:57:11.726624 4, 0xFFFF, sum = 0
7565 13:57:11.726716 5, 0xFFFF, sum = 0
7566 13:57:11.729374 6, 0xFFFF, sum = 0
7567 13:57:11.729460 7, 0xFFFF, sum = 0
7568 13:57:11.732495 8, 0xFFFF, sum = 0
7569 13:57:11.736160 9, 0xFFFF, sum = 0
7570 13:57:11.736249 10, 0xFFFF, sum = 0
7571 13:57:11.739523 11, 0xFFFF, sum = 0
7572 13:57:11.739610 12, 0xFFF, sum = 0
7573 13:57:11.742660 13, 0x0, sum = 1
7574 13:57:11.742748 14, 0x0, sum = 2
7575 13:57:11.746232 15, 0x0, sum = 3
7576 13:57:11.746320 16, 0x0, sum = 4
7577 13:57:11.746389 best_step = 14
7578 13:57:11.746449
7579 13:57:11.749477 ==
7580 13:57:11.752628 Dram Type= 6, Freq= 0, CH_0, rank 0
7581 13:57:11.755717 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7582 13:57:11.755806 ==
7583 13:57:11.755871 RX Vref Scan: 1
7584 13:57:11.755932
7585 13:57:11.758737 Set Vref Range= 24 -> 127
7586 13:57:11.758822
7587 13:57:11.762327 RX Vref 24 -> 127, step: 1
7588 13:57:11.762414
7589 13:57:11.765350 RX Delay 11 -> 252, step: 4
7590 13:57:11.765435
7591 13:57:11.768935 Set Vref, RX VrefLevel [Byte0]: 24
7592 13:57:11.771813 [Byte1]: 24
7593 13:57:11.771898
7594 13:57:11.776011 Set Vref, RX VrefLevel [Byte0]: 25
7595 13:57:11.779626 [Byte1]: 25
7596 13:57:11.779722
7597 13:57:11.782532 Set Vref, RX VrefLevel [Byte0]: 26
7598 13:57:11.786816 [Byte1]: 26
7599 13:57:11.790229
7600 13:57:11.790321 Set Vref, RX VrefLevel [Byte0]: 27
7601 13:57:11.792369 [Byte1]: 27
7602 13:57:11.796667
7603 13:57:11.796797 Set Vref, RX VrefLevel [Byte0]: 28
7604 13:57:11.800115 [Byte1]: 28
7605 13:57:11.803973
7606 13:57:11.804060 Set Vref, RX VrefLevel [Byte0]: 29
7607 13:57:11.808132 [Byte1]: 29
7608 13:57:11.812925
7609 13:57:11.813030 Set Vref, RX VrefLevel [Byte0]: 30
7610 13:57:11.815128 [Byte1]: 30
7611 13:57:11.820079
7612 13:57:11.820187 Set Vref, RX VrefLevel [Byte0]: 31
7613 13:57:11.823182 [Byte1]: 31
7614 13:57:11.827570
7615 13:57:11.827660 Set Vref, RX VrefLevel [Byte0]: 32
7616 13:57:11.830277 [Byte1]: 32
7617 13:57:11.834451
7618 13:57:11.834542 Set Vref, RX VrefLevel [Byte0]: 33
7619 13:57:11.838060 [Byte1]: 33
7620 13:57:11.842691
7621 13:57:11.842785 Set Vref, RX VrefLevel [Byte0]: 34
7622 13:57:11.846316 [Byte1]: 34
7623 13:57:11.849604
7624 13:57:11.849691 Set Vref, RX VrefLevel [Byte0]: 35
7625 13:57:11.853418 [Byte1]: 35
7626 13:57:11.857675
7627 13:57:11.857774 Set Vref, RX VrefLevel [Byte0]: 36
7628 13:57:11.860657 [Byte1]: 36
7629 13:57:11.865209
7630 13:57:11.865298 Set Vref, RX VrefLevel [Byte0]: 37
7631 13:57:11.869884 [Byte1]: 37
7632 13:57:11.872813
7633 13:57:11.872929 Set Vref, RX VrefLevel [Byte0]: 38
7634 13:57:11.875882 [Byte1]: 38
7635 13:57:11.880347
7636 13:57:11.880444 Set Vref, RX VrefLevel [Byte0]: 39
7637 13:57:11.883416 [Byte1]: 39
7638 13:57:11.888267
7639 13:57:11.888360 Set Vref, RX VrefLevel [Byte0]: 40
7640 13:57:11.892939 [Byte1]: 40
7641 13:57:11.895657
7642 13:57:11.895747 Set Vref, RX VrefLevel [Byte0]: 41
7643 13:57:11.898543 [Byte1]: 41
7644 13:57:11.902970
7645 13:57:11.903068 Set Vref, RX VrefLevel [Byte0]: 42
7646 13:57:11.906735 [Byte1]: 42
7647 13:57:11.910648
7648 13:57:11.910738 Set Vref, RX VrefLevel [Byte0]: 43
7649 13:57:11.914470 [Byte1]: 43
7650 13:57:11.918912
7651 13:57:11.919004 Set Vref, RX VrefLevel [Byte0]: 44
7652 13:57:11.922188 [Byte1]: 44
7653 13:57:11.926823
7654 13:57:11.926914 Set Vref, RX VrefLevel [Byte0]: 45
7655 13:57:11.929888 [Byte1]: 45
7656 13:57:11.933696
7657 13:57:11.933784 Set Vref, RX VrefLevel [Byte0]: 46
7658 13:57:11.937381 [Byte1]: 46
7659 13:57:11.941058
7660 13:57:11.941145 Set Vref, RX VrefLevel [Byte0]: 47
7661 13:57:11.945187 [Byte1]: 47
7662 13:57:11.948674
7663 13:57:11.948786 Set Vref, RX VrefLevel [Byte0]: 48
7664 13:57:11.955624 [Byte1]: 48
7665 13:57:11.955725
7666 13:57:11.958612 Set Vref, RX VrefLevel [Byte0]: 49
7667 13:57:11.962632 [Byte1]: 49
7668 13:57:11.962721
7669 13:57:11.965392 Set Vref, RX VrefLevel [Byte0]: 50
7670 13:57:11.968835 [Byte1]: 50
7671 13:57:11.972299
7672 13:57:11.972387 Set Vref, RX VrefLevel [Byte0]: 51
7673 13:57:11.974998 [Byte1]: 51
7674 13:57:11.979540
7675 13:57:11.979633 Set Vref, RX VrefLevel [Byte0]: 52
7676 13:57:11.982461 [Byte1]: 52
7677 13:57:11.986703
7678 13:57:11.986797 Set Vref, RX VrefLevel [Byte0]: 53
7679 13:57:11.990023 [Byte1]: 53
7680 13:57:11.996263
7681 13:57:11.996362 Set Vref, RX VrefLevel [Byte0]: 54
7682 13:57:11.998072 [Byte1]: 54
7683 13:57:12.003288
7684 13:57:12.003381 Set Vref, RX VrefLevel [Byte0]: 55
7685 13:57:12.005373 [Byte1]: 55
7686 13:57:12.009656
7687 13:57:12.009744 Set Vref, RX VrefLevel [Byte0]: 56
7688 13:57:12.013016 [Byte1]: 56
7689 13:57:12.017300
7690 13:57:12.017389 Set Vref, RX VrefLevel [Byte0]: 57
7691 13:57:12.021380 [Byte1]: 57
7692 13:57:12.024964
7693 13:57:12.025101 Set Vref, RX VrefLevel [Byte0]: 58
7694 13:57:12.027991 [Byte1]: 58
7695 13:57:12.032617
7696 13:57:12.032712 Set Vref, RX VrefLevel [Byte0]: 59
7697 13:57:12.035758 [Byte1]: 59
7698 13:57:12.040049
7699 13:57:12.040134 Set Vref, RX VrefLevel [Byte0]: 60
7700 13:57:12.043835 [Byte1]: 60
7701 13:57:12.048605
7702 13:57:12.048698 Set Vref, RX VrefLevel [Byte0]: 61
7703 13:57:12.051589 [Byte1]: 61
7704 13:57:12.055513
7705 13:57:12.055602 Set Vref, RX VrefLevel [Byte0]: 62
7706 13:57:12.058492 [Byte1]: 62
7707 13:57:12.063150
7708 13:57:12.063240 Set Vref, RX VrefLevel [Byte0]: 63
7709 13:57:12.066648 [Byte1]: 63
7710 13:57:12.070659
7711 13:57:12.070747 Set Vref, RX VrefLevel [Byte0]: 64
7712 13:57:12.073802 [Byte1]: 64
7713 13:57:12.078077
7714 13:57:12.078183 Set Vref, RX VrefLevel [Byte0]: 65
7715 13:57:12.082687 [Byte1]: 65
7716 13:57:12.086534
7717 13:57:12.086623 Set Vref, RX VrefLevel [Byte0]: 66
7718 13:57:12.088879 [Byte1]: 66
7719 13:57:12.093535
7720 13:57:12.093625 Set Vref, RX VrefLevel [Byte0]: 67
7721 13:57:12.096838 [Byte1]: 67
7722 13:57:12.101806
7723 13:57:12.101900 Set Vref, RX VrefLevel [Byte0]: 68
7724 13:57:12.104472 [Byte1]: 68
7725 13:57:12.108821
7726 13:57:12.108912 Set Vref, RX VrefLevel [Byte0]: 69
7727 13:57:12.112611 [Byte1]: 69
7728 13:57:12.116946
7729 13:57:12.117039 Set Vref, RX VrefLevel [Byte0]: 70
7730 13:57:12.120085 [Byte1]: 70
7731 13:57:12.123886
7732 13:57:12.123975 Set Vref, RX VrefLevel [Byte0]: 71
7733 13:57:12.127488 [Byte1]: 71
7734 13:57:12.131665
7735 13:57:12.131754 Set Vref, RX VrefLevel [Byte0]: 72
7736 13:57:12.134512 [Byte1]: 72
7737 13:57:12.140277
7738 13:57:12.140368 Final RX Vref Byte 0 = 53 to rank0
7739 13:57:12.142818 Final RX Vref Byte 1 = 55 to rank0
7740 13:57:12.145779 Final RX Vref Byte 0 = 53 to rank1
7741 13:57:12.149510 Final RX Vref Byte 1 = 55 to rank1==
7742 13:57:12.152885 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 13:57:12.158915 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7744 13:57:12.159037 ==
7745 13:57:12.159145 DQS Delay:
7746 13:57:12.159213 DQS0 = 0, DQS1 = 0
7747 13:57:12.162452 DQM Delay:
7748 13:57:12.162538 DQM0 = 126, DQM1 = 121
7749 13:57:12.165897 DQ Delay:
7750 13:57:12.169345 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7751 13:57:12.172276 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7752 13:57:12.175534 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7753 13:57:12.179255 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7754 13:57:12.179347
7755 13:57:12.179416
7756 13:57:12.179476
7757 13:57:12.182324 [DramC_TX_OE_Calibration] TA2
7758 13:57:12.185747 Original DQ_B0 (3 6) =30, OEN = 27
7759 13:57:12.189862 Original DQ_B1 (3 6) =30, OEN = 27
7760 13:57:12.192567 24, 0x0, End_B0=24 End_B1=24
7761 13:57:12.192685 25, 0x0, End_B0=25 End_B1=25
7762 13:57:12.196513 26, 0x0, End_B0=26 End_B1=26
7763 13:57:12.198992 27, 0x0, End_B0=27 End_B1=27
7764 13:57:12.202506 28, 0x0, End_B0=28 End_B1=28
7765 13:57:12.202598 29, 0x0, End_B0=29 End_B1=29
7766 13:57:12.205452 30, 0x0, End_B0=30 End_B1=30
7767 13:57:12.208941 31, 0x5151, End_B0=30 End_B1=30
7768 13:57:12.211954 Byte0 end_step=30 best_step=27
7769 13:57:12.215346 Byte1 end_step=30 best_step=27
7770 13:57:12.219116 Byte0 TX OE(2T, 0.5T) = (3, 3)
7771 13:57:12.222151 Byte1 TX OE(2T, 0.5T) = (3, 3)
7772 13:57:12.222242
7773 13:57:12.222310
7774 13:57:12.229646 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7775 13:57:12.231750 CH0 RK0: MR19=303, MR18=1B1B
7776 13:57:12.239936 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7777 13:57:12.240053
7778 13:57:12.242090 ----->DramcWriteLeveling(PI) begin...
7779 13:57:12.242176 ==
7780 13:57:12.245384 Dram Type= 6, Freq= 0, CH_0, rank 1
7781 13:57:12.248212 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7782 13:57:12.248301 ==
7783 13:57:12.251795 Write leveling (Byte 0): 30 => 30
7784 13:57:12.254867 Write leveling (Byte 1): 25 => 25
7785 13:57:12.258106 DramcWriteLeveling(PI) end<-----
7786 13:57:12.258198
7787 13:57:12.258264 ==
7788 13:57:12.262108 Dram Type= 6, Freq= 0, CH_0, rank 1
7789 13:57:12.265253 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7790 13:57:12.265342 ==
7791 13:57:12.268178 [Gating] SW mode calibration
7792 13:57:12.275063 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7793 13:57:12.282952 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7794 13:57:12.284933 0 12 0 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
7795 13:57:12.291795 0 12 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
7796 13:57:12.294738 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7797 13:57:12.298050 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7798 13:57:12.305155 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7799 13:57:12.308677 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7800 13:57:12.311495 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7801 13:57:12.318103 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7802 13:57:12.322273 0 13 0 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7803 13:57:12.324814 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
7804 13:57:12.331515 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7805 13:57:12.334965 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7806 13:57:12.338100 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7807 13:57:12.341453 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7808 13:57:12.348181 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7809 13:57:12.351053 0 13 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7810 13:57:12.358311 0 14 0 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7811 13:57:12.361421 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7812 13:57:12.364168 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7813 13:57:12.371824 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7814 13:57:12.374425 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 13:57:12.377277 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7816 13:57:12.383757 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7817 13:57:12.387083 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7818 13:57:12.390686 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7819 13:57:12.396993 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7820 13:57:12.401297 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 13:57:12.403511 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 13:57:12.407610 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 13:57:12.413446 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 13:57:12.416980 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 13:57:12.421105 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 13:57:12.427655 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 13:57:12.429932 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 13:57:12.433551 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7829 13:57:12.440655 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7830 13:57:12.443703 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 13:57:12.447317 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7832 13:57:12.453654 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7833 13:57:12.456628 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7834 13:57:12.460502 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7835 13:57:12.467355 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7836 13:57:12.469826 Total UI for P1: 0, mck2ui 16
7837 13:57:12.474141 best dqsien dly found for B0: ( 1, 1, 0)
7838 13:57:12.476527 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7839 13:57:12.480408 Total UI for P1: 0, mck2ui 16
7840 13:57:12.484892 best dqsien dly found for B1: ( 1, 1, 2)
7841 13:57:12.487472 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7842 13:57:12.490046 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7843 13:57:12.490134
7844 13:57:12.493215 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7845 13:57:12.496657 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7846 13:57:12.499854 [Gating] SW calibration Done
7847 13:57:12.499945 ==
7848 13:57:12.503379 Dram Type= 6, Freq= 0, CH_0, rank 1
7849 13:57:12.506844 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7850 13:57:12.509888 ==
7851 13:57:12.509976 RX Vref Scan: 0
7852 13:57:12.510042
7853 13:57:12.512922 RX Vref 0 -> 0, step: 1
7854 13:57:12.513006
7855 13:57:12.513072 RX Delay 0 -> 252, step: 8
7856 13:57:12.520057 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7857 13:57:12.523092 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7858 13:57:12.526104 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7859 13:57:12.529909 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7860 13:57:12.533015 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7861 13:57:12.539576 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7862 13:57:12.543344 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7863 13:57:12.546175 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7864 13:57:12.549766 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7865 13:57:12.553250 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7866 13:57:12.560263 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7867 13:57:12.563228 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7868 13:57:12.566039 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7869 13:57:12.569220 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7870 13:57:12.576519 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7871 13:57:12.580033 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7872 13:57:12.580129 ==
7873 13:57:12.582576 Dram Type= 6, Freq= 0, CH_0, rank 1
7874 13:57:12.586372 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7875 13:57:12.586461 ==
7876 13:57:12.589670 DQS Delay:
7877 13:57:12.589787 DQS0 = 0, DQS1 = 0
7878 13:57:12.589903 DQM Delay:
7879 13:57:12.594765 DQM0 = 131, DQM1 = 124
7880 13:57:12.594852 DQ Delay:
7881 13:57:12.595528 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =123
7882 13:57:12.599083 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7883 13:57:12.602304 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7884 13:57:12.609034 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7885 13:57:12.609136
7886 13:57:12.609247
7887 13:57:12.609309 ==
7888 13:57:12.612428 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 13:57:12.615607 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 13:57:12.615693 ==
7891 13:57:12.615761
7892 13:57:12.615821
7893 13:57:12.619251 TX Vref Scan disable
7894 13:57:12.619337 == TX Byte 0 ==
7895 13:57:12.626148 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7896 13:57:12.629313 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7897 13:57:12.629412 == TX Byte 1 ==
7898 13:57:12.635666 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7899 13:57:12.638721 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7900 13:57:12.638809 ==
7901 13:57:12.643256 Dram Type= 6, Freq= 0, CH_0, rank 1
7902 13:57:12.645823 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7903 13:57:12.645909 ==
7904 13:57:12.660991
7905 13:57:12.664344 TX Vref early break, caculate TX vref
7906 13:57:12.667353 TX Vref=16, minBit 8, minWin=22, winSum=370
7907 13:57:12.670701 TX Vref=18, minBit 1, minWin=23, winSum=381
7908 13:57:12.674003 TX Vref=20, minBit 10, minWin=23, winSum=388
7909 13:57:12.677652 TX Vref=22, minBit 1, minWin=23, winSum=395
7910 13:57:12.681198 TX Vref=24, minBit 8, minWin=24, winSum=402
7911 13:57:12.687828 TX Vref=26, minBit 2, minWin=25, winSum=408
7912 13:57:12.690968 TX Vref=28, minBit 0, minWin=25, winSum=408
7913 13:57:12.694454 TX Vref=30, minBit 0, minWin=25, winSum=408
7914 13:57:12.697255 TX Vref=32, minBit 4, minWin=24, winSum=404
7915 13:57:12.701466 TX Vref=34, minBit 8, minWin=23, winSum=394
7916 13:57:12.704179 TX Vref=36, minBit 8, minWin=22, winSum=383
7917 13:57:12.711628 [TxChooseVref] Worse bit 2, Min win 25, Win sum 408, Final Vref 26
7918 13:57:12.711736
7919 13:57:12.714265 Final TX Range 0 Vref 26
7920 13:57:12.714354
7921 13:57:12.714421 ==
7922 13:57:12.717483 Dram Type= 6, Freq= 0, CH_0, rank 1
7923 13:57:12.720692 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7924 13:57:12.720788 ==
7925 13:57:12.720855
7926 13:57:12.723892
7927 13:57:12.723975 TX Vref Scan disable
7928 13:57:12.730477 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7929 13:57:12.730574 == TX Byte 0 ==
7930 13:57:12.733908 u2DelayCellOfst[0]=10 cells (3 PI)
7931 13:57:12.738007 u2DelayCellOfst[1]=18 cells (5 PI)
7932 13:57:12.740240 u2DelayCellOfst[2]=10 cells (3 PI)
7933 13:57:12.743984 u2DelayCellOfst[3]=14 cells (4 PI)
7934 13:57:12.747237 u2DelayCellOfst[4]=7 cells (2 PI)
7935 13:57:12.750631 u2DelayCellOfst[5]=0 cells (0 PI)
7936 13:57:12.753426 u2DelayCellOfst[6]=18 cells (5 PI)
7937 13:57:12.757260 u2DelayCellOfst[7]=18 cells (5 PI)
7938 13:57:12.760913 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7939 13:57:12.764684 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7940 13:57:12.767025 == TX Byte 1 ==
7941 13:57:12.771776 u2DelayCellOfst[8]=3 cells (1 PI)
7942 13:57:12.773668 u2DelayCellOfst[9]=0 cells (0 PI)
7943 13:57:12.777258 u2DelayCellOfst[10]=14 cells (4 PI)
7944 13:57:12.780407 u2DelayCellOfst[11]=7 cells (2 PI)
7945 13:57:12.783454 u2DelayCellOfst[12]=18 cells (5 PI)
7946 13:57:12.783540 u2DelayCellOfst[13]=18 cells (5 PI)
7947 13:57:12.786680 u2DelayCellOfst[14]=21 cells (6 PI)
7948 13:57:12.789907 u2DelayCellOfst[15]=18 cells (5 PI)
7949 13:57:12.796534 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7950 13:57:12.799736 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7951 13:57:12.799850 DramC Write-DBI on
7952 13:57:12.803924 ==
7953 13:57:12.806941 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 13:57:12.809750 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7955 13:57:12.809866 ==
7956 13:57:12.809960
7957 13:57:12.810051
7958 13:57:12.813680 TX Vref Scan disable
7959 13:57:12.813776 == TX Byte 0 ==
7960 13:57:12.819650 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7961 13:57:12.819760 == TX Byte 1 ==
7962 13:57:12.824682 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7963 13:57:12.826468 DramC Write-DBI off
7964 13:57:12.826553
7965 13:57:12.826618 [DATLAT]
7966 13:57:12.829938 Freq=1600, CH0 RK1
7967 13:57:12.830023
7968 13:57:12.830090 DATLAT Default: 0xe
7969 13:57:12.833930 0, 0xFFFF, sum = 0
7970 13:57:12.834017 1, 0xFFFF, sum = 0
7971 13:57:12.836218 2, 0xFFFF, sum = 0
7972 13:57:12.836304 3, 0xFFFF, sum = 0
7973 13:57:12.839318 4, 0xFFFF, sum = 0
7974 13:57:12.842530 5, 0xFFFF, sum = 0
7975 13:57:12.842619 6, 0xFFFF, sum = 0
7976 13:57:12.845975 7, 0xFFFF, sum = 0
7977 13:57:12.846063 8, 0xFFFF, sum = 0
7978 13:57:12.850201 9, 0xFFFF, sum = 0
7979 13:57:12.850289 10, 0xFFFF, sum = 0
7980 13:57:12.853041 11, 0xFFFF, sum = 0
7981 13:57:12.853128 12, 0xCFFF, sum = 0
7982 13:57:12.855898 13, 0x0, sum = 1
7983 13:57:12.855986 14, 0x0, sum = 2
7984 13:57:12.859482 15, 0x0, sum = 3
7985 13:57:12.859570 16, 0x0, sum = 4
7986 13:57:12.863310 best_step = 14
7987 13:57:12.863396
7988 13:57:12.863462 ==
7989 13:57:12.865942 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 13:57:12.869265 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7991 13:57:12.869351 ==
7992 13:57:12.869417 RX Vref Scan: 0
7993 13:57:12.873163
7994 13:57:12.873250 RX Vref 0 -> 0, step: 1
7995 13:57:12.873316
7996 13:57:12.875683 RX Delay 11 -> 252, step: 4
7997 13:57:12.879125 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7998 13:57:12.886075 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7999 13:57:12.889002 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8000 13:57:12.892962 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8001 13:57:12.896100 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8002 13:57:12.899044 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8003 13:57:12.907162 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8004 13:57:12.910261 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8005 13:57:12.912304 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8006 13:57:12.915800 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8007 13:57:12.918809 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8008 13:57:12.925489 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8009 13:57:12.930071 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8010 13:57:12.932383 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8011 13:57:12.936266 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8012 13:57:12.943546 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8013 13:57:12.943652 ==
8014 13:57:12.945504 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 13:57:12.950019 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8016 13:57:12.950109 ==
8017 13:57:12.950176 DQS Delay:
8018 13:57:12.951681 DQS0 = 0, DQS1 = 0
8019 13:57:12.951764 DQM Delay:
8020 13:57:12.955302 DQM0 = 129, DQM1 = 120
8021 13:57:12.955447 DQ Delay:
8022 13:57:12.959013 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
8023 13:57:12.961760 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8024 13:57:12.965679 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
8025 13:57:12.968680 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8026 13:57:12.968809
8027 13:57:12.968876
8028 13:57:12.971583
8029 13:57:12.971668 [DramC_TX_OE_Calibration] TA2
8030 13:57:12.975111 Original DQ_B0 (3 6) =30, OEN = 27
8031 13:57:12.978590 Original DQ_B1 (3 6) =30, OEN = 27
8032 13:57:12.981667 24, 0x0, End_B0=24 End_B1=24
8033 13:57:12.985374 25, 0x0, End_B0=25 End_B1=25
8034 13:57:12.988650 26, 0x0, End_B0=26 End_B1=26
8035 13:57:12.988783 27, 0x0, End_B0=27 End_B1=27
8036 13:57:12.991684 28, 0x0, End_B0=28 End_B1=28
8037 13:57:12.995065 29, 0x0, End_B0=29 End_B1=29
8038 13:57:12.997700 30, 0x0, End_B0=30 End_B1=30
8039 13:57:13.001379 31, 0x4141, End_B0=30 End_B1=30
8040 13:57:13.001472 Byte0 end_step=30 best_step=27
8041 13:57:13.004859 Byte1 end_step=30 best_step=27
8042 13:57:13.007682 Byte0 TX OE(2T, 0.5T) = (3, 3)
8043 13:57:13.011314 Byte1 TX OE(2T, 0.5T) = (3, 3)
8044 13:57:13.011415
8045 13:57:13.011481
8046 13:57:13.017652 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8047 13:57:13.021997 CH0 RK1: MR19=303, MR18=2121
8048 13:57:13.028163 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8049 13:57:13.032488 [RxdqsGatingPostProcess] freq 1600
8050 13:57:13.037552 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8051 13:57:13.041366 Pre-setting of DQS Precalculation
8052 13:57:13.044280 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8053 13:57:13.044372 ==
8054 13:57:13.047967 Dram Type= 6, Freq= 0, CH_1, rank 0
8055 13:57:13.051072 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8056 13:57:13.054280 ==
8057 13:57:13.057356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8058 13:57:13.060718 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8059 13:57:13.068686 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8060 13:57:13.074582 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8061 13:57:13.080295 [CA 0] Center 41 (11~71) winsize 61
8062 13:57:13.084466 [CA 1] Center 40 (10~71) winsize 62
8063 13:57:13.086974 [CA 2] Center 36 (6~66) winsize 61
8064 13:57:13.090422 [CA 3] Center 35 (6~65) winsize 60
8065 13:57:13.093651 [CA 4] Center 33 (4~63) winsize 60
8066 13:57:13.096702 [CA 5] Center 33 (4~63) winsize 60
8067 13:57:13.096832
8068 13:57:13.100214 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8069 13:57:13.100300
8070 13:57:13.103512 [CATrainingPosCal] consider 1 rank data
8071 13:57:13.107330 u2DelayCellTimex100 = 271/100 ps
8072 13:57:13.113575 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8073 13:57:13.117103 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8074 13:57:13.120670 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8075 13:57:13.124325 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8076 13:57:13.126789 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8077 13:57:13.130619 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8078 13:57:13.130712
8079 13:57:13.133170 CA PerBit enable=1, Macro0, CA PI delay=33
8080 13:57:13.133255
8081 13:57:13.136807 [CBTSetCACLKResult] CA Dly = 33
8082 13:57:13.139947 CS Dly: 9 (0~40)
8083 13:57:13.143966 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8084 13:57:13.147087 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8085 13:57:13.147175 ==
8086 13:57:13.149729 Dram Type= 6, Freq= 0, CH_1, rank 1
8087 13:57:13.156391 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8088 13:57:13.156495 ==
8089 13:57:13.160593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8090 13:57:13.162919 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8091 13:57:13.169494 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8092 13:57:13.176852 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8093 13:57:13.183425 [CA 0] Center 41 (11~71) winsize 61
8094 13:57:13.186625 [CA 1] Center 40 (10~71) winsize 62
8095 13:57:13.189210 [CA 2] Center 36 (7~66) winsize 60
8096 13:57:13.192620 [CA 3] Center 36 (7~65) winsize 59
8097 13:57:13.196595 [CA 4] Center 34 (4~64) winsize 61
8098 13:57:13.199798 [CA 5] Center 34 (4~64) winsize 61
8099 13:57:13.199890
8100 13:57:13.202558 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8101 13:57:13.202643
8102 13:57:13.205809 [CATrainingPosCal] consider 2 rank data
8103 13:57:13.209876 u2DelayCellTimex100 = 271/100 ps
8104 13:57:13.212907 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8105 13:57:13.219103 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8106 13:57:13.222848 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8107 13:57:13.226267 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8108 13:57:13.230937 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8109 13:57:13.233489 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8110 13:57:13.233575
8111 13:57:13.235772 CA PerBit enable=1, Macro0, CA PI delay=33
8112 13:57:13.235870
8113 13:57:13.239440 [CBTSetCACLKResult] CA Dly = 33
8114 13:57:13.242425 CS Dly: 9 (0~41)
8115 13:57:13.245806 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8116 13:57:13.248760 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8117 13:57:13.248845
8118 13:57:13.252250 ----->DramcWriteLeveling(PI) begin...
8119 13:57:13.252336 ==
8120 13:57:13.255589 Dram Type= 6, Freq= 0, CH_1, rank 0
8121 13:57:13.262552 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8122 13:57:13.262657 ==
8123 13:57:13.266127 Write leveling (Byte 0): 22 => 22
8124 13:57:13.268701 Write leveling (Byte 1): 22 => 22
8125 13:57:13.268824 DramcWriteLeveling(PI) end<-----
8126 13:57:13.272043
8127 13:57:13.272129 ==
8128 13:57:13.275375 Dram Type= 6, Freq= 0, CH_1, rank 0
8129 13:57:13.278657 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8130 13:57:13.278751 ==
8131 13:57:13.281877 [Gating] SW mode calibration
8132 13:57:13.288292 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8133 13:57:13.292427 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8134 13:57:13.298605 0 12 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
8135 13:57:13.301903 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8136 13:57:13.305524 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8137 13:57:13.312410 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8138 13:57:13.316532 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8139 13:57:13.318769 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8140 13:57:13.325537 0 12 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8141 13:57:13.329465 0 12 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8142 13:57:13.331968 0 13 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8143 13:57:13.338686 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8144 13:57:13.342560 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8145 13:57:13.344906 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8146 13:57:13.351310 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8147 13:57:13.355204 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8148 13:57:13.358035 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8149 13:57:13.364495 0 13 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8150 13:57:13.368148 0 14 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
8151 13:57:13.371007 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8152 13:57:13.377725 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 13:57:13.381105 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 13:57:13.384148 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8155 13:57:13.391413 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 13:57:13.395250 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8157 13:57:13.398144 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8158 13:57:13.404432 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8159 13:57:13.407619 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8160 13:57:13.410738 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 13:57:13.417330 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 13:57:13.421925 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 13:57:13.424229 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 13:57:13.430461 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 13:57:13.434013 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 13:57:13.437406 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8167 13:57:13.443920 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8168 13:57:13.447150 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8169 13:57:13.451285 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 13:57:13.456985 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 13:57:13.460156 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8172 13:57:13.464183 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8173 13:57:13.470245 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8174 13:57:13.474064 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8175 13:57:13.477451 Total UI for P1: 0, mck2ui 16
8176 13:57:13.481292 best dqsien dly found for B0: ( 1, 0, 28)
8177 13:57:13.483337 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8178 13:57:13.490325 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8179 13:57:13.490437 Total UI for P1: 0, mck2ui 16
8180 13:57:13.496537 best dqsien dly found for B1: ( 1, 1, 0)
8181 13:57:13.500889 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8182 13:57:13.502965 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8183 13:57:13.503052
8184 13:57:13.506698 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8185 13:57:13.509702 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8186 13:57:13.513224 [Gating] SW calibration Done
8187 13:57:13.513316 ==
8188 13:57:13.516338 Dram Type= 6, Freq= 0, CH_1, rank 0
8189 13:57:13.519826 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8190 13:57:13.519909 ==
8191 13:57:13.522843 RX Vref Scan: 0
8192 13:57:13.522927
8193 13:57:13.522992 RX Vref 0 -> 0, step: 1
8194 13:57:13.523053
8195 13:57:13.526939 RX Delay 0 -> 252, step: 8
8196 13:57:13.529929 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8197 13:57:13.538024 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8198 13:57:13.539599 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8199 13:57:13.543197 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8200 13:57:13.545966 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8201 13:57:13.549361 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8202 13:57:13.557243 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8203 13:57:13.563444 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8204 13:57:13.564436 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8205 13:57:13.566336 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8206 13:57:13.569755 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8207 13:57:13.576212 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8208 13:57:13.579388 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8209 13:57:13.582666 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8210 13:57:13.586270 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8211 13:57:13.589006 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8212 13:57:13.592650 ==
8213 13:57:13.595663 Dram Type= 6, Freq= 0, CH_1, rank 0
8214 13:57:13.600110 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8215 13:57:13.600206 ==
8216 13:57:13.600273 DQS Delay:
8217 13:57:13.602274 DQS0 = 0, DQS1 = 0
8218 13:57:13.602357 DQM Delay:
8219 13:57:13.606011 DQM0 = 130, DQM1 = 126
8220 13:57:13.606099 DQ Delay:
8221 13:57:13.609629 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8222 13:57:13.612236 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8223 13:57:13.616329 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8224 13:57:13.620357 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8225 13:57:13.620449
8226 13:57:13.620516
8227 13:57:13.620577 ==
8228 13:57:13.622800 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 13:57:13.629236 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8230 13:57:13.629331 ==
8231 13:57:13.629398
8232 13:57:13.629459
8233 13:57:13.632151 TX Vref Scan disable
8234 13:57:13.632234 == TX Byte 0 ==
8235 13:57:13.635495 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8236 13:57:13.642409 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8237 13:57:13.642513 == TX Byte 1 ==
8238 13:57:13.645825 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8239 13:57:13.652830 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8240 13:57:13.652936 ==
8241 13:57:13.656352 Dram Type= 6, Freq= 0, CH_1, rank 0
8242 13:57:13.659367 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8243 13:57:13.659455 ==
8244 13:57:13.671064
8245 13:57:13.674231 TX Vref early break, caculate TX vref
8246 13:57:13.678526 TX Vref=16, minBit 1, minWin=21, winSum=360
8247 13:57:13.681026 TX Vref=18, minBit 0, minWin=22, winSum=376
8248 13:57:13.684277 TX Vref=20, minBit 1, minWin=22, winSum=382
8249 13:57:13.688080 TX Vref=22, minBit 3, minWin=23, winSum=392
8250 13:57:13.691225 TX Vref=24, minBit 0, minWin=24, winSum=402
8251 13:57:13.697652 TX Vref=26, minBit 3, minWin=24, winSum=408
8252 13:57:13.701027 TX Vref=28, minBit 0, minWin=25, winSum=410
8253 13:57:13.704616 TX Vref=30, minBit 3, minWin=24, winSum=408
8254 13:57:13.707247 TX Vref=32, minBit 3, minWin=23, winSum=397
8255 13:57:13.710173 TX Vref=34, minBit 1, minWin=23, winSum=388
8256 13:57:13.717190 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 28
8257 13:57:13.717295
8258 13:57:13.720569 Final TX Range 0 Vref 28
8259 13:57:13.720656
8260 13:57:13.720727 ==
8261 13:57:13.723865 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 13:57:13.727863 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8263 13:57:13.727952 ==
8264 13:57:13.728018
8265 13:57:13.728078
8266 13:57:13.730513 TX Vref Scan disable
8267 13:57:13.737206 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8268 13:57:13.737300 == TX Byte 0 ==
8269 13:57:13.740696 u2DelayCellOfst[0]=18 cells (5 PI)
8270 13:57:13.743440 u2DelayCellOfst[1]=14 cells (4 PI)
8271 13:57:13.747063 u2DelayCellOfst[2]=0 cells (0 PI)
8272 13:57:13.750228 u2DelayCellOfst[3]=10 cells (3 PI)
8273 13:57:13.753591 u2DelayCellOfst[4]=10 cells (3 PI)
8274 13:57:13.756782 u2DelayCellOfst[5]=18 cells (5 PI)
8275 13:57:13.761402 u2DelayCellOfst[6]=18 cells (5 PI)
8276 13:57:13.763858 u2DelayCellOfst[7]=7 cells (2 PI)
8277 13:57:13.767034 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8278 13:57:13.771265 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8279 13:57:13.775060 == TX Byte 1 ==
8280 13:57:13.777087 u2DelayCellOfst[8]=0 cells (0 PI)
8281 13:57:13.777177 u2DelayCellOfst[9]=7 cells (2 PI)
8282 13:57:13.780252 u2DelayCellOfst[10]=10 cells (3 PI)
8283 13:57:13.783674 u2DelayCellOfst[11]=3 cells (1 PI)
8284 13:57:13.787577 u2DelayCellOfst[12]=18 cells (5 PI)
8285 13:57:13.791252 u2DelayCellOfst[13]=18 cells (5 PI)
8286 13:57:13.794410 u2DelayCellOfst[14]=18 cells (5 PI)
8287 13:57:13.797059 u2DelayCellOfst[15]=21 cells (6 PI)
8288 13:57:13.800095 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8289 13:57:13.806541 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8290 13:57:13.806640 DramC Write-DBI on
8291 13:57:13.806705 ==
8292 13:57:13.809755 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 13:57:13.816381 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8294 13:57:13.816485 ==
8295 13:57:13.816553
8296 13:57:13.816614
8297 13:57:13.816671 TX Vref Scan disable
8298 13:57:13.820731 == TX Byte 0 ==
8299 13:57:13.823769 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8300 13:57:13.826940 == TX Byte 1 ==
8301 13:57:13.830572 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8302 13:57:13.833512 DramC Write-DBI off
8303 13:57:13.833598
8304 13:57:13.833662 [DATLAT]
8305 13:57:13.833723 Freq=1600, CH1 RK0
8306 13:57:13.833781
8307 13:57:13.837193 DATLAT Default: 0xf
8308 13:57:13.837276 0, 0xFFFF, sum = 0
8309 13:57:13.840084 1, 0xFFFF, sum = 0
8310 13:57:13.840168 2, 0xFFFF, sum = 0
8311 13:57:13.843507 3, 0xFFFF, sum = 0
8312 13:57:13.847275 4, 0xFFFF, sum = 0
8313 13:57:13.847366 5, 0xFFFF, sum = 0
8314 13:57:13.849983 6, 0xFFFF, sum = 0
8315 13:57:13.850068 7, 0xFFFF, sum = 0
8316 13:57:13.853295 8, 0xFFFF, sum = 0
8317 13:57:13.853380 9, 0xFFFF, sum = 0
8318 13:57:13.856523 10, 0xFFFF, sum = 0
8319 13:57:13.856636 11, 0xFFFF, sum = 0
8320 13:57:13.860309 12, 0x8FFF, sum = 0
8321 13:57:13.860397 13, 0x0, sum = 1
8322 13:57:13.863284 14, 0x0, sum = 2
8323 13:57:13.863371 15, 0x0, sum = 3
8324 13:57:13.866760 16, 0x0, sum = 4
8325 13:57:13.866847 best_step = 14
8326 13:57:13.866912
8327 13:57:13.866972 ==
8328 13:57:13.869963 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 13:57:13.873495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8330 13:57:13.876402 ==
8331 13:57:13.876488 RX Vref Scan: 1
8332 13:57:13.876553
8333 13:57:13.881018 Set Vref Range= 24 -> 127
8334 13:57:13.881116
8335 13:57:13.883448 RX Vref 24 -> 127, step: 1
8336 13:57:13.883531
8337 13:57:13.883597 RX Delay 3 -> 252, step: 4
8338 13:57:13.883658
8339 13:57:13.888122 Set Vref, RX VrefLevel [Byte0]: 24
8340 13:57:13.889634 [Byte1]: 24
8341 13:57:13.893792
8342 13:57:13.893897 Set Vref, RX VrefLevel [Byte0]: 25
8343 13:57:13.897147 [Byte1]: 25
8344 13:57:13.901692
8345 13:57:13.901786 Set Vref, RX VrefLevel [Byte0]: 26
8346 13:57:13.904375 [Byte1]: 26
8347 13:57:13.909393
8348 13:57:13.909488 Set Vref, RX VrefLevel [Byte0]: 27
8349 13:57:13.912380 [Byte1]: 27
8350 13:57:13.916525
8351 13:57:13.916642 Set Vref, RX VrefLevel [Byte0]: 28
8352 13:57:13.919684 [Byte1]: 28
8353 13:57:13.924683
8354 13:57:13.924791 Set Vref, RX VrefLevel [Byte0]: 29
8355 13:57:13.927669 [Byte1]: 29
8356 13:57:13.932003
8357 13:57:13.932095 Set Vref, RX VrefLevel [Byte0]: 30
8358 13:57:13.935297 [Byte1]: 30
8359 13:57:13.939388
8360 13:57:13.939482 Set Vref, RX VrefLevel [Byte0]: 31
8361 13:57:13.943048 [Byte1]: 31
8362 13:57:13.947697
8363 13:57:13.947792 Set Vref, RX VrefLevel [Byte0]: 32
8364 13:57:13.950626 [Byte1]: 32
8365 13:57:13.954980
8366 13:57:13.955068 Set Vref, RX VrefLevel [Byte0]: 33
8367 13:57:13.958157 [Byte1]: 33
8368 13:57:13.962499
8369 13:57:13.962589 Set Vref, RX VrefLevel [Byte0]: 34
8370 13:57:13.965628 [Byte1]: 34
8371 13:57:13.970015
8372 13:57:13.970104 Set Vref, RX VrefLevel [Byte0]: 35
8373 13:57:13.974048 [Byte1]: 35
8374 13:57:13.977929
8375 13:57:13.978025 Set Vref, RX VrefLevel [Byte0]: 36
8376 13:57:13.981015 [Byte1]: 36
8377 13:57:13.985447
8378 13:57:13.985540 Set Vref, RX VrefLevel [Byte0]: 37
8379 13:57:13.988548 [Byte1]: 37
8380 13:57:13.994128
8381 13:57:13.994225 Set Vref, RX VrefLevel [Byte0]: 38
8382 13:57:13.996477 [Byte1]: 38
8383 13:57:14.000587
8384 13:57:14.000736 Set Vref, RX VrefLevel [Byte0]: 39
8385 13:57:14.004046 [Byte1]: 39
8386 13:57:14.008255
8387 13:57:14.008345 Set Vref, RX VrefLevel [Byte0]: 40
8388 13:57:14.012180 [Byte1]: 40
8389 13:57:14.016119
8390 13:57:14.016206 Set Vref, RX VrefLevel [Byte0]: 41
8391 13:57:14.019182 [Byte1]: 41
8392 13:57:14.023635
8393 13:57:14.023721 Set Vref, RX VrefLevel [Byte0]: 42
8394 13:57:14.027198 [Byte1]: 42
8395 13:57:14.031242
8396 13:57:14.031329 Set Vref, RX VrefLevel [Byte0]: 43
8397 13:57:14.034580 [Byte1]: 43
8398 13:57:14.038999
8399 13:57:14.039091 Set Vref, RX VrefLevel [Byte0]: 44
8400 13:57:14.042816 [Byte1]: 44
8401 13:57:14.046671
8402 13:57:14.046759 Set Vref, RX VrefLevel [Byte0]: 45
8403 13:57:14.049982 [Byte1]: 45
8404 13:57:14.055178
8405 13:57:14.055269 Set Vref, RX VrefLevel [Byte0]: 46
8406 13:57:14.058036 [Byte1]: 46
8407 13:57:14.062588
8408 13:57:14.062674 Set Vref, RX VrefLevel [Byte0]: 47
8409 13:57:14.066020 [Byte1]: 47
8410 13:57:14.069851
8411 13:57:14.069936 Set Vref, RX VrefLevel [Byte0]: 48
8412 13:57:14.073221 [Byte1]: 48
8413 13:57:14.077289
8414 13:57:14.077380 Set Vref, RX VrefLevel [Byte0]: 49
8415 13:57:14.080399 [Byte1]: 49
8416 13:57:14.085589
8417 13:57:14.085684 Set Vref, RX VrefLevel [Byte0]: 50
8418 13:57:14.088235 [Byte1]: 50
8419 13:57:14.092216
8420 13:57:14.092308 Set Vref, RX VrefLevel [Byte0]: 51
8421 13:57:14.097371 [Byte1]: 51
8422 13:57:14.100348
8423 13:57:14.100434 Set Vref, RX VrefLevel [Byte0]: 52
8424 13:57:14.104418 [Byte1]: 52
8425 13:57:14.107708
8426 13:57:14.107793 Set Vref, RX VrefLevel [Byte0]: 53
8427 13:57:14.111150 [Byte1]: 53
8428 13:57:14.116071
8429 13:57:14.116164 Set Vref, RX VrefLevel [Byte0]: 54
8430 13:57:14.118961 [Byte1]: 54
8431 13:57:14.123750
8432 13:57:14.123839 Set Vref, RX VrefLevel [Byte0]: 55
8433 13:57:14.127573 [Byte1]: 55
8434 13:57:14.131085
8435 13:57:14.131173 Set Vref, RX VrefLevel [Byte0]: 56
8436 13:57:14.133993 [Byte1]: 56
8437 13:57:14.138788
8438 13:57:14.138875 Set Vref, RX VrefLevel [Byte0]: 57
8439 13:57:14.141441 [Byte1]: 57
8440 13:57:14.146795
8441 13:57:14.146885 Set Vref, RX VrefLevel [Byte0]: 58
8442 13:57:14.149704 [Byte1]: 58
8443 13:57:14.154344
8444 13:57:14.154435 Set Vref, RX VrefLevel [Byte0]: 59
8445 13:57:14.157276 [Byte1]: 59
8446 13:57:14.162484
8447 13:57:14.162576 Set Vref, RX VrefLevel [Byte0]: 60
8448 13:57:14.164501 [Byte1]: 60
8449 13:57:14.169517
8450 13:57:14.169607 Set Vref, RX VrefLevel [Byte0]: 61
8451 13:57:14.172605 [Byte1]: 61
8452 13:57:14.176685
8453 13:57:14.176796 Set Vref, RX VrefLevel [Byte0]: 62
8454 13:57:14.180419 [Byte1]: 62
8455 13:57:14.184165
8456 13:57:14.184253 Set Vref, RX VrefLevel [Byte0]: 63
8457 13:57:14.188303 [Byte1]: 63
8458 13:57:14.192949
8459 13:57:14.193042 Set Vref, RX VrefLevel [Byte0]: 64
8460 13:57:14.195128 [Byte1]: 64
8461 13:57:14.200541
8462 13:57:14.200636 Set Vref, RX VrefLevel [Byte0]: 65
8463 13:57:14.203142 [Byte1]: 65
8464 13:57:14.207036
8465 13:57:14.207121 Set Vref, RX VrefLevel [Byte0]: 66
8466 13:57:14.210436 [Byte1]: 66
8467 13:57:14.215728
8468 13:57:14.215817 Set Vref, RX VrefLevel [Byte0]: 67
8469 13:57:14.218248 [Byte1]: 67
8470 13:57:14.222764
8471 13:57:14.222852 Set Vref, RX VrefLevel [Byte0]: 68
8472 13:57:14.226291 [Byte1]: 68
8473 13:57:14.230045
8474 13:57:14.230132 Set Vref, RX VrefLevel [Byte0]: 69
8475 13:57:14.233396 [Byte1]: 69
8476 13:57:14.237743
8477 13:57:14.237834 Set Vref, RX VrefLevel [Byte0]: 70
8478 13:57:14.241520 [Byte1]: 70
8479 13:57:14.245594
8480 13:57:14.245681 Set Vref, RX VrefLevel [Byte0]: 71
8481 13:57:14.249006 [Byte1]: 71
8482 13:57:14.253451
8483 13:57:14.253540 Set Vref, RX VrefLevel [Byte0]: 72
8484 13:57:14.256480 [Byte1]: 72
8485 13:57:14.261089
8486 13:57:14.261182 Set Vref, RX VrefLevel [Byte0]: 73
8487 13:57:14.264195 [Byte1]: 73
8488 13:57:14.268830
8489 13:57:14.268919 Set Vref, RX VrefLevel [Byte0]: 74
8490 13:57:14.272178 [Byte1]: 74
8491 13:57:14.276309
8492 13:57:14.276396 Set Vref, RX VrefLevel [Byte0]: 75
8493 13:57:14.279874 [Byte1]: 75
8494 13:57:14.284894
8495 13:57:14.284990 Set Vref, RX VrefLevel [Byte0]: 76
8496 13:57:14.287162 [Byte1]: 76
8497 13:57:14.291443
8498 13:57:14.291531 Final RX Vref Byte 0 = 62 to rank0
8499 13:57:14.295310 Final RX Vref Byte 1 = 52 to rank0
8500 13:57:14.298211 Final RX Vref Byte 0 = 62 to rank1
8501 13:57:14.301457 Final RX Vref Byte 1 = 52 to rank1==
8502 13:57:14.304648 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 13:57:14.311258 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8504 13:57:14.311362 ==
8505 13:57:14.311428 DQS Delay:
8506 13:57:14.311489 DQS0 = 0, DQS1 = 0
8507 13:57:14.314616 DQM Delay:
8508 13:57:14.314700 DQM0 = 129, DQM1 = 123
8509 13:57:14.318177 DQ Delay:
8510 13:57:14.321328 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =128
8511 13:57:14.324822 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8512 13:57:14.329684 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =114
8513 13:57:14.331361 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8514 13:57:14.331450
8515 13:57:14.331516
8516 13:57:14.331576
8517 13:57:14.334708 [DramC_TX_OE_Calibration] TA2
8518 13:57:14.338112 Original DQ_B0 (3 6) =30, OEN = 27
8519 13:57:14.341466 Original DQ_B1 (3 6) =30, OEN = 27
8520 13:57:14.344816 24, 0x0, End_B0=24 End_B1=24
8521 13:57:14.344906 25, 0x0, End_B0=25 End_B1=25
8522 13:57:14.348117 26, 0x0, End_B0=26 End_B1=26
8523 13:57:14.351095 27, 0x0, End_B0=27 End_B1=27
8524 13:57:14.354147 28, 0x0, End_B0=28 End_B1=28
8525 13:57:14.357486 29, 0x0, End_B0=29 End_B1=29
8526 13:57:14.357593 30, 0x0, End_B0=30 End_B1=30
8527 13:57:14.362038 31, 0x4141, End_B0=30 End_B1=30
8528 13:57:14.364239 Byte0 end_step=30 best_step=27
8529 13:57:14.368375 Byte1 end_step=30 best_step=27
8530 13:57:14.370915 Byte0 TX OE(2T, 0.5T) = (3, 3)
8531 13:57:14.374471 Byte1 TX OE(2T, 0.5T) = (3, 3)
8532 13:57:14.374560
8533 13:57:14.374645
8534 13:57:14.380904 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8535 13:57:14.384454 CH1 RK0: MR19=303, MR18=2727
8536 13:57:14.390901 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8537 13:57:14.391014
8538 13:57:14.394111 ----->DramcWriteLeveling(PI) begin...
8539 13:57:14.394200 ==
8540 13:57:14.397182 Dram Type= 6, Freq= 0, CH_1, rank 1
8541 13:57:14.400604 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8542 13:57:14.400691 ==
8543 13:57:14.403767 Write leveling (Byte 0): 20 => 20
8544 13:57:14.407435 Write leveling (Byte 1): 19 => 19
8545 13:57:14.410394 DramcWriteLeveling(PI) end<-----
8546 13:57:14.410481
8547 13:57:14.410566 ==
8548 13:57:14.413852 Dram Type= 6, Freq= 0, CH_1, rank 1
8549 13:57:14.417975 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8550 13:57:14.418086 ==
8551 13:57:14.420296 [Gating] SW mode calibration
8552 13:57:14.426981 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8553 13:57:14.434103 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8554 13:57:14.437553 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8555 13:57:14.443732 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8556 13:57:14.446789 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8557 13:57:14.449958 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8558 13:57:14.456564 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8559 13:57:14.460490 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8560 13:57:14.463641 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8561 13:57:14.470040 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8562 13:57:14.473240 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8563 13:57:14.476691 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8564 13:57:14.483107 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8565 13:57:14.487513 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8566 13:57:14.489735 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8567 13:57:14.496449 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8568 13:57:14.501014 0 13 24 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
8569 13:57:14.502909 0 13 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8570 13:57:14.509475 0 14 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8571 13:57:14.513603 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8572 13:57:14.516842 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8573 13:57:14.522741 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8574 13:57:14.526050 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8575 13:57:14.529589 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8576 13:57:14.535934 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8577 13:57:14.539789 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8578 13:57:14.542789 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8579 13:57:14.549881 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 13:57:14.553064 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 13:57:14.556677 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 13:57:14.562787 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 13:57:14.566504 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 13:57:14.569542 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 13:57:14.575691 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 13:57:14.579122 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 13:57:14.582410 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8588 13:57:14.589230 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8589 13:57:14.593283 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8590 13:57:14.595457 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8591 13:57:14.602335 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8592 13:57:14.605433 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8593 13:57:14.608931 Total UI for P1: 0, mck2ui 16
8594 13:57:14.611833 best dqsien dly found for B0: ( 1, 0, 22)
8595 13:57:14.615559 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8596 13:57:14.618767 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8597 13:57:14.626328 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8598 13:57:14.630215 Total UI for P1: 0, mck2ui 16
8599 13:57:14.632340 best dqsien dly found for B1: ( 1, 1, 0)
8600 13:57:14.635317 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8601 13:57:14.638584 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8602 13:57:14.638677
8603 13:57:14.643021 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8604 13:57:14.644960 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8605 13:57:14.648663 [Gating] SW calibration Done
8606 13:57:14.648792 ==
8607 13:57:14.651924 Dram Type= 6, Freq= 0, CH_1, rank 1
8608 13:57:14.655256 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8609 13:57:14.655343 ==
8610 13:57:14.658557 RX Vref Scan: 0
8611 13:57:14.658642
8612 13:57:14.662244 RX Vref 0 -> 0, step: 1
8613 13:57:14.662330
8614 13:57:14.662396 RX Delay 0 -> 252, step: 8
8615 13:57:14.668344 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8616 13:57:14.671456 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8617 13:57:14.674759 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8618 13:57:14.678097 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8619 13:57:14.681010 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8620 13:57:14.687870 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8621 13:57:14.690919 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8622 13:57:14.694991 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8623 13:57:14.697992 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8624 13:57:14.700961 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8625 13:57:14.708173 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8626 13:57:14.710658 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8627 13:57:14.714378 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8628 13:57:14.717299 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8629 13:57:14.723997 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8630 13:57:14.727395 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8631 13:57:14.727488 ==
8632 13:57:14.732114 Dram Type= 6, Freq= 0, CH_1, rank 1
8633 13:57:14.734298 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8634 13:57:14.734386 ==
8635 13:57:14.737176 DQS Delay:
8636 13:57:14.737259 DQS0 = 0, DQS1 = 0
8637 13:57:14.737325 DQM Delay:
8638 13:57:14.740846 DQM0 = 129, DQM1 = 124
8639 13:57:14.740931 DQ Delay:
8640 13:57:14.744094 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =127
8641 13:57:14.747402 DQ4 =123, DQ5 =143, DQ6 =139, DQ7 =127
8642 13:57:14.751110 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8643 13:57:14.757213 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8644 13:57:14.757312
8645 13:57:14.757379
8646 13:57:14.757440 ==
8647 13:57:14.760532 Dram Type= 6, Freq= 0, CH_1, rank 1
8648 13:57:14.763842 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8649 13:57:14.763930 ==
8650 13:57:14.763997
8651 13:57:14.764057
8652 13:57:14.767223 TX Vref Scan disable
8653 13:57:14.767307 == TX Byte 0 ==
8654 13:57:14.774185 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8655 13:57:14.778175 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8656 13:57:14.778268 == TX Byte 1 ==
8657 13:57:14.783747 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8658 13:57:14.786923 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8659 13:57:14.787020 ==
8660 13:57:14.790250 Dram Type= 6, Freq= 0, CH_1, rank 1
8661 13:57:14.794025 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8662 13:57:14.794117 ==
8663 13:57:14.809608
8664 13:57:14.812201 TX Vref early break, caculate TX vref
8665 13:57:14.816092 TX Vref=16, minBit 3, minWin=22, winSum=386
8666 13:57:14.818800 TX Vref=18, minBit 3, minWin=23, winSum=394
8667 13:57:14.823137 TX Vref=20, minBit 3, minWin=23, winSum=399
8668 13:57:14.825818 TX Vref=22, minBit 3, minWin=24, winSum=409
8669 13:57:14.829043 TX Vref=24, minBit 0, minWin=24, winSum=414
8670 13:57:14.835649 TX Vref=26, minBit 0, minWin=25, winSum=420
8671 13:57:14.839340 TX Vref=28, minBit 7, minWin=25, winSum=422
8672 13:57:14.842285 TX Vref=30, minBit 0, minWin=25, winSum=420
8673 13:57:14.845878 TX Vref=32, minBit 0, minWin=24, winSum=416
8674 13:57:14.849336 TX Vref=34, minBit 0, minWin=24, winSum=407
8675 13:57:14.852121 TX Vref=36, minBit 0, minWin=24, winSum=401
8676 13:57:14.859183 TX Vref=38, minBit 1, minWin=22, winSum=386
8677 13:57:14.862979 [TxChooseVref] Worse bit 7, Min win 25, Win sum 422, Final Vref 28
8678 13:57:14.863074
8679 13:57:14.865840 Final TX Range 0 Vref 28
8680 13:57:14.865924
8681 13:57:14.865990 ==
8682 13:57:14.868960 Dram Type= 6, Freq= 0, CH_1, rank 1
8683 13:57:14.872038 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8684 13:57:14.875438 ==
8685 13:57:14.875524
8686 13:57:14.875590
8687 13:57:14.875650 TX Vref Scan disable
8688 13:57:14.882220 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8689 13:57:14.882333 == TX Byte 0 ==
8690 13:57:14.885774 u2DelayCellOfst[0]=18 cells (5 PI)
8691 13:57:14.889043 u2DelayCellOfst[1]=10 cells (3 PI)
8692 13:57:14.892269 u2DelayCellOfst[2]=0 cells (0 PI)
8693 13:57:14.895226 u2DelayCellOfst[3]=7 cells (2 PI)
8694 13:57:14.898708 u2DelayCellOfst[4]=10 cells (3 PI)
8695 13:57:14.902362 u2DelayCellOfst[5]=14 cells (4 PI)
8696 13:57:14.905227 u2DelayCellOfst[6]=14 cells (4 PI)
8697 13:57:14.908952 u2DelayCellOfst[7]=7 cells (2 PI)
8698 13:57:14.911898 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8699 13:57:14.915559 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8700 13:57:14.918599 == TX Byte 1 ==
8701 13:57:14.922412 u2DelayCellOfst[8]=0 cells (0 PI)
8702 13:57:14.925456 u2DelayCellOfst[9]=3 cells (1 PI)
8703 13:57:14.928445 u2DelayCellOfst[10]=10 cells (3 PI)
8704 13:57:14.931815 u2DelayCellOfst[11]=3 cells (1 PI)
8705 13:57:14.936042 u2DelayCellOfst[12]=14 cells (4 PI)
8706 13:57:14.938858 u2DelayCellOfst[13]=18 cells (5 PI)
8707 13:57:14.938947 u2DelayCellOfst[14]=18 cells (5 PI)
8708 13:57:14.942955 u2DelayCellOfst[15]=18 cells (5 PI)
8709 13:57:14.948189 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8710 13:57:14.951452 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8711 13:57:14.954885 DramC Write-DBI on
8712 13:57:14.955007 ==
8713 13:57:14.958517 Dram Type= 6, Freq= 0, CH_1, rank 1
8714 13:57:14.961348 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8715 13:57:14.961439 ==
8716 13:57:14.961526
8717 13:57:14.961607
8718 13:57:14.964864 TX Vref Scan disable
8719 13:57:14.964988 == TX Byte 0 ==
8720 13:57:14.971627 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8721 13:57:14.971757 == TX Byte 1 ==
8722 13:57:14.975205 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8723 13:57:14.979111 DramC Write-DBI off
8724 13:57:14.979217
8725 13:57:14.979303 [DATLAT]
8726 13:57:14.981385 Freq=1600, CH1 RK1
8727 13:57:14.981471
8728 13:57:14.981557 DATLAT Default: 0xe
8729 13:57:14.985318 0, 0xFFFF, sum = 0
8730 13:57:14.985408 1, 0xFFFF, sum = 0
8731 13:57:14.988089 2, 0xFFFF, sum = 0
8732 13:57:14.988176 3, 0xFFFF, sum = 0
8733 13:57:14.991127 4, 0xFFFF, sum = 0
8734 13:57:14.991214 5, 0xFFFF, sum = 0
8735 13:57:14.996075 6, 0xFFFF, sum = 0
8736 13:57:14.998382 7, 0xFFFF, sum = 0
8737 13:57:14.998470 8, 0xFFFF, sum = 0
8738 13:57:15.001801 9, 0xFFFF, sum = 0
8739 13:57:15.001888 10, 0xFFFF, sum = 0
8740 13:57:15.006508 11, 0xFFFF, sum = 0
8741 13:57:15.006602 12, 0xF5F, sum = 0
8742 13:57:15.008397 13, 0x0, sum = 1
8743 13:57:15.008483 14, 0x0, sum = 2
8744 13:57:15.011978 15, 0x0, sum = 3
8745 13:57:15.012066 16, 0x0, sum = 4
8746 13:57:15.012153 best_step = 14
8747 13:57:15.012233
8748 13:57:15.015126 ==
8749 13:57:15.018159 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 13:57:15.021739 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8751 13:57:15.021830 ==
8752 13:57:15.021916 RX Vref Scan: 0
8753 13:57:15.021997
8754 13:57:15.025145 RX Vref 0 -> 0, step: 1
8755 13:57:15.025233
8756 13:57:15.027847 RX Delay 3 -> 252, step: 4
8757 13:57:15.031119 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8758 13:57:15.034303 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8759 13:57:15.042390 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8760 13:57:15.044409 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8761 13:57:15.047596 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8762 13:57:15.051119 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8763 13:57:15.058853 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8764 13:57:15.061012 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8765 13:57:15.064851 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8766 13:57:15.067303 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8767 13:57:15.070711 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8768 13:57:15.077527 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8769 13:57:15.080419 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8770 13:57:15.084266 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8771 13:57:15.087322 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8772 13:57:15.090617 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8773 13:57:15.093896 ==
8774 13:57:15.097466 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 13:57:15.100420 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8776 13:57:15.100509 ==
8777 13:57:15.100610 DQS Delay:
8778 13:57:15.103950 DQS0 = 0, DQS1 = 0
8779 13:57:15.104035 DQM Delay:
8780 13:57:15.107360 DQM0 = 127, DQM1 = 121
8781 13:57:15.107452 DQ Delay:
8782 13:57:15.110279 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =124
8783 13:57:15.113968 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8784 13:57:15.117372 DQ8 =104, DQ9 =110, DQ10 =122, DQ11 =112
8785 13:57:15.120549 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8786 13:57:15.120637
8787 13:57:15.120742
8788 13:57:15.120824
8789 13:57:15.123945 [DramC_TX_OE_Calibration] TA2
8790 13:57:15.126990 Original DQ_B0 (3 6) =30, OEN = 27
8791 13:57:15.130401 Original DQ_B1 (3 6) =30, OEN = 27
8792 13:57:15.134307 24, 0x0, End_B0=24 End_B1=24
8793 13:57:15.137106 25, 0x0, End_B0=25 End_B1=25
8794 13:57:15.137197 26, 0x0, End_B0=26 End_B1=26
8795 13:57:15.140358 27, 0x0, End_B0=27 End_B1=27
8796 13:57:15.143669 28, 0x0, End_B0=28 End_B1=28
8797 13:57:15.146843 29, 0x0, End_B0=29 End_B1=29
8798 13:57:15.152007 30, 0x0, End_B0=30 End_B1=30
8799 13:57:15.152108 31, 0x4141, End_B0=30 End_B1=30
8800 13:57:15.154002 Byte0 end_step=30 best_step=27
8801 13:57:15.157063 Byte1 end_step=30 best_step=27
8802 13:57:15.159853 Byte0 TX OE(2T, 0.5T) = (3, 3)
8803 13:57:15.162940 Byte1 TX OE(2T, 0.5T) = (3, 3)
8804 13:57:15.163030
8805 13:57:15.163115
8806 13:57:15.171143 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8807 13:57:15.173484 CH1 RK1: MR19=303, MR18=2020
8808 13:57:15.180202 CH1_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8809 13:57:15.183819 [RxdqsGatingPostProcess] freq 1600
8810 13:57:15.189905 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8811 13:57:15.192894 Pre-setting of DQS Precalculation
8812 13:57:15.196617 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8813 13:57:15.203215 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8814 13:57:15.210414 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8815 13:57:15.210537
8816 13:57:15.210602
8817 13:57:15.213584 [Calibration Summary] 3200 Mbps
8818 13:57:15.216653 CH 0, Rank 0
8819 13:57:15.216745 SW Impedance : PASS
8820 13:57:15.219438 DUTY Scan : NO K
8821 13:57:15.223110 ZQ Calibration : PASS
8822 13:57:15.223197 Jitter Meter : NO K
8823 13:57:15.226311 CBT Training : PASS
8824 13:57:15.229609 Write leveling : PASS
8825 13:57:15.229694 RX DQS gating : PASS
8826 13:57:15.232845 RX DQ/DQS(RDDQC) : PASS
8827 13:57:15.236218 TX DQ/DQS : PASS
8828 13:57:15.236303 RX DATLAT : PASS
8829 13:57:15.239504 RX DQ/DQS(Engine): PASS
8830 13:57:15.239588 TX OE : PASS
8831 13:57:15.243929 All Pass.
8832 13:57:15.244015
8833 13:57:15.244079 CH 0, Rank 1
8834 13:57:15.246126 SW Impedance : PASS
8835 13:57:15.249685 DUTY Scan : NO K
8836 13:57:15.249769 ZQ Calibration : PASS
8837 13:57:15.252734 Jitter Meter : NO K
8838 13:57:15.252830 CBT Training : PASS
8839 13:57:15.256051 Write leveling : PASS
8840 13:57:15.259606 RX DQS gating : PASS
8841 13:57:15.259696 RX DQ/DQS(RDDQC) : PASS
8842 13:57:15.262761 TX DQ/DQS : PASS
8843 13:57:15.266290 RX DATLAT : PASS
8844 13:57:15.266377 RX DQ/DQS(Engine): PASS
8845 13:57:15.271111 TX OE : PASS
8846 13:57:15.271198 All Pass.
8847 13:57:15.271263
8848 13:57:15.273173 CH 1, Rank 0
8849 13:57:15.273254 SW Impedance : PASS
8850 13:57:15.276997 DUTY Scan : NO K
8851 13:57:15.279463 ZQ Calibration : PASS
8852 13:57:15.279596 Jitter Meter : NO K
8853 13:57:15.283880 CBT Training : PASS
8854 13:57:15.286260 Write leveling : PASS
8855 13:57:15.286350 RX DQS gating : PASS
8856 13:57:15.289543 RX DQ/DQS(RDDQC) : PASS
8857 13:57:15.293413 TX DQ/DQS : PASS
8858 13:57:15.293505 RX DATLAT : PASS
8859 13:57:15.296597 RX DQ/DQS(Engine): PASS
8860 13:57:15.296683 TX OE : PASS
8861 13:57:15.299463 All Pass.
8862 13:57:15.299548
8863 13:57:15.299633 CH 1, Rank 1
8864 13:57:15.302760 SW Impedance : PASS
8865 13:57:15.302845 DUTY Scan : NO K
8866 13:57:15.305893 ZQ Calibration : PASS
8867 13:57:15.309924 Jitter Meter : NO K
8868 13:57:15.310014 CBT Training : PASS
8869 13:57:15.312392 Write leveling : PASS
8870 13:57:15.315751 RX DQS gating : PASS
8871 13:57:15.315839 RX DQ/DQS(RDDQC) : PASS
8872 13:57:15.318993 TX DQ/DQS : PASS
8873 13:57:15.322142 RX DATLAT : PASS
8874 13:57:15.322232 RX DQ/DQS(Engine): PASS
8875 13:57:15.326232 TX OE : PASS
8876 13:57:15.326320 All Pass.
8877 13:57:15.326406
8878 13:57:15.328822 DramC Write-DBI on
8879 13:57:15.332376 PER_BANK_REFRESH: Hybrid Mode
8880 13:57:15.332464 TX_TRACKING: ON
8881 13:57:15.342106 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8882 13:57:15.348933 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8883 13:57:15.355737 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8884 13:57:15.362094 [FAST_K] Save calibration result to emmc
8885 13:57:15.362213 sync common calibartion params.
8886 13:57:15.365677 sync cbt_mode0:0, 1:0
8887 13:57:15.368601 dram_init: ddr_geometry: 0
8888 13:57:15.368692 dram_init: ddr_geometry: 0
8889 13:57:15.371736 dram_init: ddr_geometry: 0
8890 13:57:15.375137 0:dram_rank_size:80000000
8891 13:57:15.378301 1:dram_rank_size:80000000
8892 13:57:15.381782 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8893 13:57:15.385238 DFS_SHUFFLE_HW_MODE: ON
8894 13:57:15.388590 dramc_set_vcore_voltage set vcore to 725000
8895 13:57:15.393996 Read voltage for 1600, 0
8896 13:57:15.394103 Vio18 = 0
8897 13:57:15.394191 Vcore = 725000
8898 13:57:15.395455 Vdram = 0
8899 13:57:15.395540 Vddq = 0
8900 13:57:15.395626 Vmddr = 0
8901 13:57:15.398610 switch to 3200 Mbps bootup
8902 13:57:15.402016 [DramcRunTimeConfig]
8903 13:57:15.402102 PHYPLL
8904 13:57:15.402189 DPM_CONTROL_AFTERK: ON
8905 13:57:15.405342 PER_BANK_REFRESH: ON
8906 13:57:15.408492 REFRESH_OVERHEAD_REDUCTION: ON
8907 13:57:15.408581 CMD_PICG_NEW_MODE: OFF
8908 13:57:15.412024 XRTWTW_NEW_MODE: ON
8909 13:57:15.412111 XRTRTR_NEW_MODE: ON
8910 13:57:15.415940 TX_TRACKING: ON
8911 13:57:15.416028 RDSEL_TRACKING: OFF
8912 13:57:15.418453 DQS Precalculation for DVFS: ON
8913 13:57:15.422018 RX_TRACKING: OFF
8914 13:57:15.422106 HW_GATING DBG: ON
8915 13:57:15.424849 ZQCS_ENABLE_LP4: ON
8916 13:57:15.424932 RX_PICG_NEW_MODE: ON
8917 13:57:15.428442 TX_PICG_NEW_MODE: ON
8918 13:57:15.432892 ENABLE_RX_DCM_DPHY: ON
8919 13:57:15.432982 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8920 13:57:15.435232 DUMMY_READ_FOR_TRACKING: OFF
8921 13:57:15.438690 !!! SPM_CONTROL_AFTERK: OFF
8922 13:57:15.441882 !!! SPM could not control APHY
8923 13:57:15.441972 IMPEDANCE_TRACKING: ON
8924 13:57:15.445299 TEMP_SENSOR: ON
8925 13:57:15.445384 HW_SAVE_FOR_SR: OFF
8926 13:57:15.448198 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8927 13:57:15.451836 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8928 13:57:15.454850 Read ODT Tracking: ON
8929 13:57:15.458974 Refresh Rate DeBounce: ON
8930 13:57:15.459063 DFS_NO_QUEUE_FLUSH: ON
8931 13:57:15.461847 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8932 13:57:15.465044 ENABLE_DFS_RUNTIME_MRW: OFF
8933 13:57:15.468787 DDR_RESERVE_NEW_MODE: ON
8934 13:57:15.468874 MR_CBT_SWITCH_FREQ: ON
8935 13:57:15.471341 =========================
8936 13:57:15.490717 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8937 13:57:15.494660 dram_init: ddr_geometry: 0
8938 13:57:15.512038 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8939 13:57:15.515627 dram_init: dram init end (result: 0)
8940 13:57:15.521846 DRAM-K: Full calibration passed in 23452 msecs
8941 13:57:15.525154 MRC: failed to locate region type 0.
8942 13:57:15.525255 DRAM rank0 size:0x80000000,
8943 13:57:15.529269 DRAM rank1 size=0x80000000
8944 13:57:15.539269 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8945 13:57:15.545256 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8946 13:57:15.551502 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8947 13:57:15.558411 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8948 13:57:15.561980 DRAM rank0 size:0x80000000,
8949 13:57:15.565051 DRAM rank1 size=0x80000000
8950 13:57:15.565145 CBMEM:
8951 13:57:15.568353 IMD: root @ 0xfffff000 254 entries.
8952 13:57:15.571499 IMD: root @ 0xffffec00 62 entries.
8953 13:57:15.574944 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8954 13:57:15.578091 WARNING: RO_VPD is uninitialized or empty.
8955 13:57:15.585020 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8956 13:57:15.592673 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8957 13:57:15.604623 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8958 13:57:15.616355 BS: romstage times (exec / console): total (unknown) / 22985 ms
8959 13:57:15.616502
8960 13:57:15.616594
8961 13:57:15.625692 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8962 13:57:15.630492 ARM64: Exception handlers installed.
8963 13:57:15.633141 ARM64: Testing exception
8964 13:57:15.636604 ARM64: Done test exception
8965 13:57:15.636696 Enumerating buses...
8966 13:57:15.639198 Show all devs... Before device enumeration.
8967 13:57:15.642517 Root Device: enabled 1
8968 13:57:15.646296 CPU_CLUSTER: 0: enabled 1
8969 13:57:15.646385 CPU: 00: enabled 1
8970 13:57:15.648636 Compare with tree...
8971 13:57:15.648729 Root Device: enabled 1
8972 13:57:15.652597 CPU_CLUSTER: 0: enabled 1
8973 13:57:15.655439 CPU: 00: enabled 1
8974 13:57:15.655525 Root Device scanning...
8975 13:57:15.658556 scan_static_bus for Root Device
8976 13:57:15.662127 CPU_CLUSTER: 0 enabled
8977 13:57:15.665370 scan_static_bus for Root Device done
8978 13:57:15.668835 scan_bus: bus Root Device finished in 8 msecs
8979 13:57:15.668927 done
8980 13:57:15.675648 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8981 13:57:15.678898 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8982 13:57:15.685037 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8983 13:57:15.688634 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8984 13:57:15.692004 Allocating resources...
8985 13:57:15.695236 Reading resources...
8986 13:57:15.698473 Root Device read_resources bus 0 link: 0
8987 13:57:15.698565 DRAM rank0 size:0x80000000,
8988 13:57:15.702230 DRAM rank1 size=0x80000000
8989 13:57:15.705423 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8990 13:57:15.708375 CPU: 00 missing read_resources
8991 13:57:15.714866 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8992 13:57:15.720426 Root Device read_resources bus 0 link: 0 done
8993 13:57:15.720530 Done reading resources.
8994 13:57:15.727760 Show resources in subtree (Root Device)...After reading.
8995 13:57:15.729585 Root Device child on link 0 CPU_CLUSTER: 0
8996 13:57:15.731479 CPU_CLUSTER: 0 child on link 0 CPU: 00
8997 13:57:15.741893 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8998 13:57:15.742027 CPU: 00
8999 13:57:15.745083 Root Device assign_resources, bus 0 link: 0
9000 13:57:15.747992 CPU_CLUSTER: 0 missing set_resources
9001 13:57:15.754840 Root Device assign_resources, bus 0 link: 0 done
9002 13:57:15.754950 Done setting resources.
9003 13:57:15.761291 Show resources in subtree (Root Device)...After assigning values.
9004 13:57:15.764557 Root Device child on link 0 CPU_CLUSTER: 0
9005 13:57:15.768618 CPU_CLUSTER: 0 child on link 0 CPU: 00
9006 13:57:15.778097 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9007 13:57:15.778227 CPU: 00
9008 13:57:15.781433 Done allocating resources.
9009 13:57:15.784821 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9010 13:57:15.787753 Enabling resources...
9011 13:57:15.787840 done.
9012 13:57:15.794897 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9013 13:57:15.795006 Initializing devices...
9014 13:57:15.798627 Root Device init
9015 13:57:15.798712 init hardware done!
9016 13:57:15.801305 0x00000018: ctrlr->caps
9017 13:57:15.805307 52.000 MHz: ctrlr->f_max
9018 13:57:15.805395 0.400 MHz: ctrlr->f_min
9019 13:57:15.807733 0x40ff8080: ctrlr->voltages
9020 13:57:15.811570 sclk: 390625
9021 13:57:15.811656 Bus Width = 1
9022 13:57:15.811740 sclk: 390625
9023 13:57:15.814576 Bus Width = 1
9024 13:57:15.814658 Early init status = 3
9025 13:57:15.820880 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9026 13:57:15.824838 in-header: 03 fc 00 00 01 00 00 00
9027 13:57:15.824931 in-data: 00
9028 13:57:15.831269 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9029 13:57:15.835500 in-header: 03 fd 00 00 00 00 00 00
9030 13:57:15.841039 in-data:
9031 13:57:15.841791 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9032 13:57:15.847718 in-header: 03 fc 00 00 01 00 00 00
9033 13:57:15.848683 in-data: 00
9034 13:57:15.851039 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9035 13:57:15.855610 in-header: 03 fd 00 00 00 00 00 00
9036 13:57:15.859544 in-data:
9037 13:57:15.862429 [SSUSB] Setting up USB HOST controller...
9038 13:57:15.865707 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9039 13:57:15.869748 [SSUSB] phy power-on done.
9040 13:57:15.873016 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9041 13:57:15.878843 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9042 13:57:15.883385 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9043 13:57:15.888984 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9044 13:57:15.895804 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9045 13:57:15.901978 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9046 13:57:15.909635 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9047 13:57:15.915349 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9048 13:57:15.918514 SPM: binary array size = 0x9dc
9049 13:57:15.922468 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9050 13:57:15.928605 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9051 13:57:15.935401 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9052 13:57:15.942200 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9053 13:57:15.945170 configure_display: Starting display init
9054 13:57:15.979152 anx7625_power_on_init: Init interface.
9055 13:57:15.983569 anx7625_disable_pd_protocol: Disabled PD feature.
9056 13:57:15.986093 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9057 13:57:16.013890 anx7625_start_dp_work: Secure OCM version=00
9058 13:57:16.016694 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9059 13:57:16.031366 sp_tx_get_edid_block: EDID Block = 1
9060 13:57:16.134655 Extracted contents:
9061 13:57:16.138235 header: 00 ff ff ff ff ff ff 00
9062 13:57:16.140983 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9063 13:57:16.144166 version: 01 04
9064 13:57:16.147623 basic params: 95 1f 11 78 0a
9065 13:57:16.150969 chroma info: 76 90 94 55 54 90 27 21 50 54
9066 13:57:16.153679 established: 00 00 00
9067 13:57:16.161238 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9068 13:57:16.164236 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9069 13:57:16.171053 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9070 13:57:16.179190 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9071 13:57:16.183552 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9072 13:57:16.187130 extensions: 00
9073 13:57:16.187227 checksum: fb
9074 13:57:16.187292
9075 13:57:16.190616 Manufacturer: IVO Model 57d Serial Number 0
9076 13:57:16.193771 Made week 0 of 2020
9077 13:57:16.196768 EDID version: 1.4
9078 13:57:16.196922 Digital display
9079 13:57:16.200341 6 bits per primary color channel
9080 13:57:16.200426 DisplayPort interface
9081 13:57:16.204172 Maximum image size: 31 cm x 17 cm
9082 13:57:16.207097 Gamma: 220%
9083 13:57:16.207181 Check DPMS levels
9084 13:57:16.210197 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9085 13:57:16.217680 First detailed timing is preferred timing
9086 13:57:16.217791 Established timings supported:
9087 13:57:16.220168 Standard timings supported:
9088 13:57:16.223354 Detailed timings
9089 13:57:16.227108 Hex of detail: 383680a07038204018303c0035ae10000019
9090 13:57:16.233215 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9091 13:57:16.236593 0780 0798 07c8 0820 hborder 0
9092 13:57:16.239707 0438 043b 0447 0458 vborder 0
9093 13:57:16.243324 -hsync -vsync
9094 13:57:16.243411 Did detailed timing
9095 13:57:16.250359 Hex of detail: 000000000000000000000000000000000000
9096 13:57:16.253601 Manufacturer-specified data, tag 0
9097 13:57:16.257102 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9098 13:57:16.259898 ASCII string: InfoVision
9099 13:57:16.262870 Hex of detail: 000000fe00523134304e574635205248200a
9100 13:57:16.265983 ASCII string: R140NWF5 RH
9101 13:57:16.266071 Checksum
9102 13:57:16.269822 Checksum: 0xfb (valid)
9103 13:57:16.273459 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9104 13:57:16.275914 DSI data_rate: 832800000 bps
9105 13:57:16.283103 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9106 13:57:16.287137 anx7625_parse_edid: pixelclock(138800).
9107 13:57:16.291110 hactive(1920), hsync(48), hfp(24), hbp(88)
9108 13:57:16.293124 vactive(1080), vsync(12), vfp(3), vbp(17)
9109 13:57:16.296649 anx7625_dsi_config: config dsi.
9110 13:57:16.302879 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9111 13:57:16.316087 anx7625_dsi_config: success to config DSI
9112 13:57:16.319906 anx7625_dp_start: MIPI phy setup OK.
9113 13:57:16.323064 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9114 13:57:16.326247 mtk_ddp_mode_set invalid vrefresh 60
9115 13:57:16.329264 main_disp_path_setup
9116 13:57:16.329359 ovl_layer_smi_id_en
9117 13:57:16.333021 ovl_layer_smi_id_en
9118 13:57:16.333109 ccorr_config
9119 13:57:16.333174 aal_config
9120 13:57:16.336553 gamma_config
9121 13:57:16.336638 postmask_config
9122 13:57:16.339600 dither_config
9123 13:57:16.343640 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9124 13:57:16.349334 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9125 13:57:16.353076 Root Device init finished in 551 msecs
9126 13:57:16.355952 CPU_CLUSTER: 0 init
9127 13:57:16.363018 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9128 13:57:16.369155 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9129 13:57:16.369266 APU_MBOX 0x190000b0 = 0x10001
9130 13:57:16.372751 APU_MBOX 0x190001b0 = 0x10001
9131 13:57:16.375696 APU_MBOX 0x190005b0 = 0x10001
9132 13:57:16.378741 APU_MBOX 0x190006b0 = 0x10001
9133 13:57:16.385939 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9134 13:57:16.395581 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9135 13:57:16.407601 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9136 13:57:16.414210 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9137 13:57:16.426710 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9138 13:57:16.435246 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9139 13:57:16.437912 CPU_CLUSTER: 0 init finished in 81 msecs
9140 13:57:16.441185 Devices initialized
9141 13:57:16.444973 Show all devs... After init.
9142 13:57:16.445070 Root Device: enabled 1
9143 13:57:16.448323 CPU_CLUSTER: 0: enabled 1
9144 13:57:16.450990 CPU: 00: enabled 1
9145 13:57:16.454646 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9146 13:57:16.457882 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9147 13:57:16.461369 ELOG: NV offset 0x57f000 size 0x1000
9148 13:57:16.467780 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9149 13:57:16.474989 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9150 13:57:16.477741 ELOG: Event(17) added with size 13 at 2024-02-01 13:57:16 UTC
9151 13:57:16.485287 out: cmd=0x121: 03 db 21 01 00 00 00 00
9152 13:57:16.487841 in-header: 03 e1 00 00 2c 00 00 00
9153 13:57:16.501384 in-data: 82 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9154 13:57:16.504186 ELOG: Event(A1) added with size 10 at 2024-02-01 13:57:16 UTC
9155 13:57:16.513156 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9156 13:57:16.517507 ELOG: Event(A0) added with size 9 at 2024-02-01 13:57:16 UTC
9157 13:57:16.520745 elog_add_boot_reason: Logged dev mode boot
9158 13:57:16.527531 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9159 13:57:16.527646 Finalize devices...
9160 13:57:16.530586 Devices finalized
9161 13:57:16.534158 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9162 13:57:16.537578 Writing coreboot table at 0xffe64000
9163 13:57:16.543799 0. 000000000010a000-0000000000113fff: RAMSTAGE
9164 13:57:16.547252 1. 0000000040000000-00000000400fffff: RAM
9165 13:57:16.550804 2. 0000000040100000-000000004032afff: RAMSTAGE
9166 13:57:16.553728 3. 000000004032b000-00000000545fffff: RAM
9167 13:57:16.557395 4. 0000000054600000-000000005465ffff: BL31
9168 13:57:16.560747 5. 0000000054660000-00000000ffe63fff: RAM
9169 13:57:16.567563 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9170 13:57:16.570893 7. 0000000100000000-000000013fffffff: RAM
9171 13:57:16.573685 Passing 5 GPIOs to payload:
9172 13:57:16.577130 NAME | PORT | POLARITY | VALUE
9173 13:57:16.583663 EC in RW | 0x000000aa | low | undefined
9174 13:57:16.587308 EC interrupt | 0x00000005 | low | undefined
9175 13:57:16.590382 TPM interrupt | 0x000000ab | high | undefined
9176 13:57:16.598369 SD card detect | 0x00000011 | high | undefined
9177 13:57:16.600389 speaker enable | 0x00000093 | high | undefined
9178 13:57:16.603858 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9179 13:57:16.607216 in-header: 03 f8 00 00 02 00 00 00
9180 13:57:16.609990 in-data: 03 00
9181 13:57:16.613747 ADC[4]: Raw value=668590 ID=5
9182 13:57:16.617448 ADC[3]: Raw value=212549 ID=1
9183 13:57:16.617539 RAM Code: 0x51
9184 13:57:16.622117 ADC[6]: Raw value=74410 ID=0
9185 13:57:16.623292 ADC[5]: Raw value=211812 ID=1
9186 13:57:16.623376 SKU Code: 0x1
9187 13:57:16.629923 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e25
9188 13:57:16.630023 coreboot table: 964 bytes.
9189 13:57:16.633158 IMD ROOT 0. 0xfffff000 0x00001000
9190 13:57:16.636543 IMD SMALL 1. 0xffffe000 0x00001000
9191 13:57:16.639860 RO MCACHE 2. 0xffffc000 0x00001104
9192 13:57:16.643661 CONSOLE 3. 0xfff7c000 0x00080000
9193 13:57:16.646415 FMAP 4. 0xfff7b000 0x00000452
9194 13:57:16.650220 TIME STAMP 5. 0xfff7a000 0x00000910
9195 13:57:16.653083 VBOOT WORK 6. 0xfff66000 0x00014000
9196 13:57:16.656814 RAMOOPS 7. 0xffe66000 0x00100000
9197 13:57:16.660316 COREBOOT 8. 0xffe64000 0x00002000
9198 13:57:16.663333 IMD small region:
9199 13:57:16.666938 IMD ROOT 0. 0xffffec00 0x00000400
9200 13:57:16.669617 VPD 1. 0xffffeb80 0x0000006c
9201 13:57:16.672945 MMC STATUS 2. 0xffffeb60 0x00000004
9202 13:57:16.676043 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9203 13:57:16.679756 Probing TPM: done!
9204 13:57:16.683193 Connected to device vid:did:rid of 1ae0:0028:00
9205 13:57:16.694726 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9206 13:57:16.697684 Initialized TPM device CR50 revision 0
9207 13:57:16.701916 Checking cr50 for pending updates
9208 13:57:16.705322 Reading cr50 TPM mode
9209 13:57:16.713669 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9210 13:57:16.719810 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9211 13:57:16.760103 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9212 13:57:16.763549 Checking segment from ROM address 0x40100000
9213 13:57:16.766601 Checking segment from ROM address 0x4010001c
9214 13:57:16.773618 Loading segment from ROM address 0x40100000
9215 13:57:16.773727 code (compression=0)
9216 13:57:16.783519 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9217 13:57:16.790442 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9218 13:57:16.790572 it's not compressed!
9219 13:57:16.797032 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9220 13:57:16.803326 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9221 13:57:16.820481 Loading segment from ROM address 0x4010001c
9222 13:57:16.820631 Entry Point 0x80000000
9223 13:57:16.823938 Loaded segments
9224 13:57:16.827075 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9225 13:57:16.834704 Jumping to boot code at 0x80000000(0xffe64000)
9226 13:57:16.841136 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9227 13:57:16.847223 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9228 13:57:16.854877 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9229 13:57:16.858435 Checking segment from ROM address 0x40100000
9230 13:57:16.861480 Checking segment from ROM address 0x4010001c
9231 13:57:16.868370 Loading segment from ROM address 0x40100000
9232 13:57:16.868495 code (compression=1)
9233 13:57:16.875556 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9234 13:57:16.884849 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9235 13:57:16.884987 using LZMA
9236 13:57:16.893520 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9237 13:57:16.899937 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9238 13:57:16.903499 Loading segment from ROM address 0x4010001c
9239 13:57:16.903597 Entry Point 0x54601000
9240 13:57:16.906427 Loaded segments
9241 13:57:16.910315 NOTICE: MT8192 bl31_setup
9242 13:57:16.917119 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9243 13:57:16.920905 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9244 13:57:16.923953 WARNING: region 0:
9245 13:57:16.926637 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9246 13:57:16.926723 WARNING: region 1:
9247 13:57:16.934588 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9248 13:57:16.937042 WARNING: region 2:
9249 13:57:16.940218 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9250 13:57:16.943637 WARNING: region 3:
9251 13:57:16.946907 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9252 13:57:16.951143 WARNING: region 4:
9253 13:57:16.957529 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9254 13:57:16.957636 WARNING: region 5:
9255 13:57:16.961755 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9256 13:57:16.963814 WARNING: region 6:
9257 13:57:16.967005 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9258 13:57:16.970206 WARNING: region 7:
9259 13:57:16.973504 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9260 13:57:16.980517 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9261 13:57:16.983507 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9262 13:57:16.987124 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9263 13:57:16.993587 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9264 13:57:16.997096 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9265 13:57:17.000235 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9266 13:57:17.006775 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9267 13:57:17.009950 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9268 13:57:17.016509 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9269 13:57:17.020247 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9270 13:57:17.023367 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9271 13:57:17.030198 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9272 13:57:17.033396 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9273 13:57:17.036891 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9274 13:57:17.043098 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9275 13:57:17.046700 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9276 13:57:17.053992 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9277 13:57:17.057202 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9278 13:57:17.060656 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9279 13:57:17.067338 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9280 13:57:17.070135 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9281 13:57:17.073789 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9282 13:57:17.079759 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9283 13:57:17.083615 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9284 13:57:17.090125 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9285 13:57:17.093247 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9286 13:57:17.096672 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9287 13:57:17.103389 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9288 13:57:17.106565 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9289 13:57:17.113414 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9290 13:57:17.117337 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9291 13:57:17.120953 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9292 13:57:17.126504 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9293 13:57:17.129952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9294 13:57:17.133642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9295 13:57:17.136642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9296 13:57:17.143092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9297 13:57:17.146799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9298 13:57:17.149659 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9299 13:57:17.153462 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9300 13:57:17.160452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9301 13:57:17.163245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9302 13:57:17.166395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9303 13:57:17.170004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9304 13:57:17.176605 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9305 13:57:17.179896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9306 13:57:17.183235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9307 13:57:17.186879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9308 13:57:17.193361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9309 13:57:17.196503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9310 13:57:17.204115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9311 13:57:17.206639 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9312 13:57:17.212993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9313 13:57:17.217160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9314 13:57:17.220136 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9315 13:57:17.226511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9316 13:57:17.229546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9317 13:57:17.236288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9318 13:57:17.240122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9319 13:57:17.246413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9320 13:57:17.249592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9321 13:57:17.254382 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9322 13:57:17.259850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9323 13:57:17.263288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9324 13:57:17.269449 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9325 13:57:17.272886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9326 13:57:17.280104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9327 13:57:17.283103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9328 13:57:17.289522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9329 13:57:17.293107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9330 13:57:17.296244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9331 13:57:17.303030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9332 13:57:17.306152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9333 13:57:17.312654 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9334 13:57:17.316073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9335 13:57:17.322569 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9336 13:57:17.326461 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9337 13:57:17.329162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9338 13:57:17.336929 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9339 13:57:17.339256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9340 13:57:17.346236 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9341 13:57:17.350261 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9342 13:57:17.355767 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9343 13:57:17.358881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9344 13:57:17.365416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9345 13:57:17.369627 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9346 13:57:17.372587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9347 13:57:17.379418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9348 13:57:17.382466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9349 13:57:17.388741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9350 13:57:17.392349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9351 13:57:17.398931 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9352 13:57:17.402286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9353 13:57:17.408983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9354 13:57:17.412030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9355 13:57:17.415898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9356 13:57:17.422797 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9357 13:57:17.425449 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9358 13:57:17.428979 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9359 13:57:17.432457 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9360 13:57:17.439724 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9361 13:57:17.442302 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9362 13:57:17.445478 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9363 13:57:17.452214 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9364 13:57:17.455325 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9365 13:57:17.462219 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9366 13:57:17.465438 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9367 13:57:17.468534 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9368 13:57:17.475802 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9369 13:57:17.479284 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9370 13:57:17.485272 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9371 13:57:17.488664 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9372 13:57:17.495185 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9373 13:57:17.499271 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9374 13:57:17.502211 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9375 13:57:17.508754 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9376 13:57:17.512216 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9377 13:57:17.515895 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9378 13:57:17.522219 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9379 13:57:17.525576 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9380 13:57:17.529500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9381 13:57:17.532005 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9382 13:57:17.535872 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9383 13:57:17.541918 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9384 13:57:17.545514 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9385 13:57:17.552531 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9386 13:57:17.555887 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9387 13:57:17.559125 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9388 13:57:17.565443 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9389 13:57:17.568823 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9390 13:57:17.572290 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9391 13:57:17.579292 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9392 13:57:17.583156 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9393 13:57:17.588854 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9394 13:57:17.591852 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9395 13:57:17.595162 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9396 13:57:17.602931 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9397 13:57:17.605262 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9398 13:57:17.611724 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9399 13:57:17.615302 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9400 13:57:17.619629 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9401 13:57:17.625212 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9402 13:57:17.628333 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9403 13:57:17.635206 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9404 13:57:17.638238 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9405 13:57:17.641817 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9406 13:57:17.648541 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9407 13:57:17.651901 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9408 13:57:17.655171 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9409 13:57:17.662048 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9410 13:57:17.665450 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9411 13:57:17.671581 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9412 13:57:17.675193 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9413 13:57:17.678614 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9414 13:57:17.684928 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9415 13:57:17.688398 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9416 13:57:17.695345 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9417 13:57:17.698475 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9418 13:57:17.702900 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9419 13:57:17.708737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9420 13:57:17.711914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9421 13:57:17.715167 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9422 13:57:17.721659 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9423 13:57:17.725297 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9424 13:57:17.731589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9425 13:57:17.734910 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9426 13:57:17.738130 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9427 13:57:17.745404 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9428 13:57:17.748436 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9429 13:57:17.755299 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9430 13:57:17.758586 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9431 13:57:17.761500 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9432 13:57:17.767816 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9433 13:57:17.771280 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9434 13:57:17.778125 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9435 13:57:17.781732 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9436 13:57:17.784846 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9437 13:57:17.791915 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9438 13:57:17.794865 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9439 13:57:17.801627 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9440 13:57:17.804336 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9441 13:57:17.807732 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9442 13:57:17.814849 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9443 13:57:17.817943 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9444 13:57:17.824866 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9445 13:57:17.828450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9446 13:57:17.830909 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9447 13:57:17.837566 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9448 13:57:17.840912 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9449 13:57:17.847455 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9450 13:57:17.851134 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9451 13:57:17.853989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9452 13:57:17.860869 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9453 13:57:17.863857 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9454 13:57:17.870809 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9455 13:57:17.873655 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9456 13:57:17.880564 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9457 13:57:17.883870 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9458 13:57:17.887485 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9459 13:57:17.894268 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9460 13:57:17.897202 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9461 13:57:17.903654 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9462 13:57:17.906802 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9463 13:57:17.913583 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9464 13:57:17.916521 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9465 13:57:17.920124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9466 13:57:17.927029 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9467 13:57:17.930005 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9468 13:57:17.937303 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9469 13:57:17.940368 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9470 13:57:17.943219 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9471 13:57:17.949654 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9472 13:57:17.953308 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9473 13:57:17.959677 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9474 13:57:17.963340 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9475 13:57:17.970911 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9476 13:57:17.973113 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9477 13:57:17.976713 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9478 13:57:17.982888 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9479 13:57:17.988302 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9480 13:57:17.992942 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9481 13:57:17.996531 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9482 13:57:17.999790 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9483 13:57:18.006558 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9484 13:57:18.009605 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9485 13:57:18.015987 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9486 13:57:18.019890 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9487 13:57:18.026390 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9488 13:57:18.029579 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9489 13:57:18.033087 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9490 13:57:18.036226 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9491 13:57:18.043864 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9492 13:57:18.046994 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9493 13:57:18.049488 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9494 13:57:18.052682 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9495 13:57:18.059481 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9496 13:57:18.063519 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9497 13:57:18.069202 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9498 13:57:18.072838 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9499 13:57:18.075601 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9500 13:57:18.082529 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9501 13:57:18.085673 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9502 13:57:18.092456 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9503 13:57:18.095857 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9504 13:57:18.099167 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9505 13:57:18.105847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9506 13:57:18.109406 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9507 13:57:18.112004 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9508 13:57:18.118996 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9509 13:57:18.121980 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9510 13:57:18.126101 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9511 13:57:18.131971 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9512 13:57:18.135336 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9513 13:57:18.138895 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9514 13:57:18.145410 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9515 13:57:18.148956 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9516 13:57:18.155716 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9517 13:57:18.158955 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9518 13:57:18.161655 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9519 13:57:18.168539 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9520 13:57:18.172152 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9521 13:57:18.178629 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9522 13:57:18.181649 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9523 13:57:18.185017 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9524 13:57:18.191763 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9525 13:57:18.195063 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9526 13:57:18.198495 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9527 13:57:18.204955 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9528 13:57:18.207932 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9529 13:57:18.213431 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9530 13:57:18.215308 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9531 13:57:18.221521 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9532 13:57:18.224781 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9533 13:57:18.228483 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9534 13:57:18.231464 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9535 13:57:18.237657 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9536 13:57:18.241326 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9537 13:57:18.244514 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9538 13:57:18.248234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9539 13:57:18.254358 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9540 13:57:18.258951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9541 13:57:18.260834 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9542 13:57:18.267821 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9543 13:57:18.270848 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9544 13:57:18.277843 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9545 13:57:18.280692 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9546 13:57:18.284580 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9547 13:57:18.290856 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9548 13:57:18.294430 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9549 13:57:18.301818 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9550 13:57:18.304964 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9551 13:57:18.308375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9552 13:57:18.314063 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9553 13:57:18.318170 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9554 13:57:18.323768 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9555 13:57:18.327573 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9556 13:57:18.334275 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9557 13:57:18.337638 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9558 13:57:18.342167 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9559 13:57:18.347818 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9560 13:57:18.350224 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9561 13:57:18.357231 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9562 13:57:18.360603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9563 13:57:18.363689 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9564 13:57:18.370795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9565 13:57:18.374707 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9566 13:57:18.381614 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9567 13:57:18.384196 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9568 13:57:18.387173 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9569 13:57:18.394257 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9570 13:57:18.396739 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9571 13:57:18.404389 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9572 13:57:18.407054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9573 13:57:18.410214 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9574 13:57:18.418000 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9575 13:57:18.421855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9576 13:57:18.427165 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9577 13:57:18.430406 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9578 13:57:18.436663 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9579 13:57:18.440428 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9580 13:57:18.443263 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9581 13:57:18.450160 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9582 13:57:18.453411 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9583 13:57:18.459797 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9584 13:57:18.463411 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9585 13:57:18.467193 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9586 13:57:18.473306 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9587 13:57:18.476539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9588 13:57:18.483346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9589 13:57:18.486692 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9590 13:57:18.490212 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9591 13:57:18.496927 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9592 13:57:18.499840 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9593 13:57:18.508024 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9594 13:57:18.509801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9595 13:57:18.516614 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9596 13:57:18.519571 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9597 13:57:18.523125 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9598 13:57:18.530267 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9599 13:57:18.532975 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9600 13:57:18.539453 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9601 13:57:18.543014 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9602 13:57:18.546562 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9603 13:57:18.553528 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9604 13:57:18.556015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9605 13:57:18.563422 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9606 13:57:18.566428 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9607 13:57:18.569282 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9608 13:57:18.576300 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9609 13:57:18.579189 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9610 13:57:18.585821 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9611 13:57:18.589314 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9612 13:57:18.595525 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9613 13:57:18.598846 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9614 13:57:18.602253 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9615 13:57:18.608649 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9616 13:57:18.613830 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9617 13:57:18.619213 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9618 13:57:18.622068 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9619 13:57:18.628535 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9620 13:57:18.631757 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9621 13:57:18.634992 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9622 13:57:18.641743 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9623 13:57:18.645116 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9624 13:57:18.652000 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9625 13:57:18.655563 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9626 13:57:18.661855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9627 13:57:18.665591 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9628 13:57:18.671653 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9629 13:57:18.674608 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9630 13:57:18.678441 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9631 13:57:18.685220 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9632 13:57:18.688271 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9633 13:57:18.695109 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9634 13:57:18.698207 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9635 13:57:18.705008 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9636 13:57:18.707871 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9637 13:57:18.714492 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9638 13:57:18.718289 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9639 13:57:18.722810 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9640 13:57:18.728427 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9641 13:57:18.731012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9642 13:57:18.737859 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9643 13:57:18.741483 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9644 13:57:18.747658 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9645 13:57:18.751072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9646 13:57:18.754370 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9647 13:57:18.761460 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9648 13:57:18.764226 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9649 13:57:18.770926 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9650 13:57:18.773967 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9651 13:57:18.781717 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9652 13:57:18.784039 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9653 13:57:18.791010 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9654 13:57:18.793888 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9655 13:57:18.797505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9656 13:57:18.803757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9657 13:57:18.807480 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9658 13:57:18.814040 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9659 13:57:18.816738 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9660 13:57:18.823645 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9661 13:57:18.827501 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9662 13:57:18.832105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9663 13:57:18.836663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9664 13:57:18.840268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9665 13:57:18.846592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9666 13:57:18.850476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9667 13:57:18.856586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9668 13:57:18.860423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9669 13:57:18.866882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9670 13:57:18.871415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9671 13:57:18.876752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9672 13:57:18.880113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9673 13:57:18.886808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9674 13:57:18.889826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9675 13:57:18.896689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9676 13:57:18.899789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9677 13:57:18.906311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9678 13:57:18.909625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9679 13:57:18.917082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9680 13:57:18.920072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9681 13:57:18.926155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9682 13:57:18.930188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9683 13:57:18.936264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9684 13:57:18.940056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9685 13:57:18.946327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9686 13:57:18.949024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9687 13:57:18.955668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9688 13:57:18.958839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9689 13:57:18.965674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9690 13:57:18.968611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9691 13:57:18.975657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9692 13:57:18.979080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9693 13:57:18.985564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9694 13:57:18.990259 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9695 13:57:18.993287 INFO: [APUAPC] vio 0
9696 13:57:18.996027 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9697 13:57:18.999421 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9698 13:57:19.002500 INFO: [APUAPC] D0_APC_0: 0x400510
9699 13:57:19.005878 INFO: [APUAPC] D0_APC_1: 0x0
9700 13:57:19.009035 INFO: [APUAPC] D0_APC_2: 0x1540
9701 13:57:19.012258 INFO: [APUAPC] D0_APC_3: 0x0
9702 13:57:19.015403 INFO: [APUAPC] D1_APC_0: 0xffffffff
9703 13:57:19.018664 INFO: [APUAPC] D1_APC_1: 0xffffffff
9704 13:57:19.021938 INFO: [APUAPC] D1_APC_2: 0x3fffff
9705 13:57:19.025558 INFO: [APUAPC] D1_APC_3: 0x0
9706 13:57:19.028856 INFO: [APUAPC] D2_APC_0: 0xffffffff
9707 13:57:19.032209 INFO: [APUAPC] D2_APC_1: 0xffffffff
9708 13:57:19.035380 INFO: [APUAPC] D2_APC_2: 0x3fffff
9709 13:57:19.039610 INFO: [APUAPC] D2_APC_3: 0x0
9710 13:57:19.041676 INFO: [APUAPC] D3_APC_0: 0xffffffff
9711 13:57:19.046223 INFO: [APUAPC] D3_APC_1: 0xffffffff
9712 13:57:19.048622 INFO: [APUAPC] D3_APC_2: 0x3fffff
9713 13:57:19.051809 INFO: [APUAPC] D3_APC_3: 0x0
9714 13:57:19.055892 INFO: [APUAPC] D4_APC_0: 0xffffffff
9715 13:57:19.059361 INFO: [APUAPC] D4_APC_1: 0xffffffff
9716 13:57:19.061471 INFO: [APUAPC] D4_APC_2: 0x3fffff
9717 13:57:19.064908 INFO: [APUAPC] D4_APC_3: 0x0
9718 13:57:19.068825 INFO: [APUAPC] D5_APC_0: 0xffffffff
9719 13:57:19.071767 INFO: [APUAPC] D5_APC_1: 0xffffffff
9720 13:57:19.075464 INFO: [APUAPC] D5_APC_2: 0x3fffff
9721 13:57:19.078587 INFO: [APUAPC] D5_APC_3: 0x0
9722 13:57:19.081347 INFO: [APUAPC] D6_APC_0: 0xffffffff
9723 13:57:19.084701 INFO: [APUAPC] D6_APC_1: 0xffffffff
9724 13:57:19.088452 INFO: [APUAPC] D6_APC_2: 0x3fffff
9725 13:57:19.091759 INFO: [APUAPC] D6_APC_3: 0x0
9726 13:57:19.094865 INFO: [APUAPC] D7_APC_0: 0xffffffff
9727 13:57:19.098356 INFO: [APUAPC] D7_APC_1: 0xffffffff
9728 13:57:19.101716 INFO: [APUAPC] D7_APC_2: 0x3fffff
9729 13:57:19.105041 INFO: [APUAPC] D7_APC_3: 0x0
9730 13:57:19.108296 INFO: [APUAPC] D8_APC_0: 0xffffffff
9731 13:57:19.111295 INFO: [APUAPC] D8_APC_1: 0xffffffff
9732 13:57:19.115037 INFO: [APUAPC] D8_APC_2: 0x3fffff
9733 13:57:19.118253 INFO: [APUAPC] D8_APC_3: 0x0
9734 13:57:19.121707 INFO: [APUAPC] D9_APC_0: 0xffffffff
9735 13:57:19.125529 INFO: [APUAPC] D9_APC_1: 0xffffffff
9736 13:57:19.128489 INFO: [APUAPC] D9_APC_2: 0x3fffff
9737 13:57:19.131327 INFO: [APUAPC] D9_APC_3: 0x0
9738 13:57:19.134546 INFO: [APUAPC] D10_APC_0: 0xffffffff
9739 13:57:19.138774 INFO: [APUAPC] D10_APC_1: 0xffffffff
9740 13:57:19.142245 INFO: [APUAPC] D10_APC_2: 0x3fffff
9741 13:57:19.144624 INFO: [APUAPC] D10_APC_3: 0x0
9742 13:57:19.148320 INFO: [APUAPC] D11_APC_0: 0xffffffff
9743 13:57:19.150931 INFO: [APUAPC] D11_APC_1: 0xffffffff
9744 13:57:19.156110 INFO: [APUAPC] D11_APC_2: 0x3fffff
9745 13:57:19.159529 INFO: [APUAPC] D11_APC_3: 0x0
9746 13:57:19.160981 INFO: [APUAPC] D12_APC_0: 0xffffffff
9747 13:57:19.164768 INFO: [APUAPC] D12_APC_1: 0xffffffff
9748 13:57:19.167381 INFO: [APUAPC] D12_APC_2: 0x3fffff
9749 13:57:19.171090 INFO: [APUAPC] D12_APC_3: 0x0
9750 13:57:19.173968 INFO: [APUAPC] D13_APC_0: 0xffffffff
9751 13:57:19.178481 INFO: [APUAPC] D13_APC_1: 0xffffffff
9752 13:57:19.180953 INFO: [APUAPC] D13_APC_2: 0x3fffff
9753 13:57:19.183621 INFO: [APUAPC] D13_APC_3: 0x0
9754 13:57:19.187860 INFO: [APUAPC] D14_APC_0: 0xffffffff
9755 13:57:19.190624 INFO: [APUAPC] D14_APC_1: 0xffffffff
9756 13:57:19.193634 INFO: [APUAPC] D14_APC_2: 0x3fffff
9757 13:57:19.197355 INFO: [APUAPC] D14_APC_3: 0x0
9758 13:57:19.200902 INFO: [APUAPC] D15_APC_0: 0xffffffff
9759 13:57:19.203784 INFO: [APUAPC] D15_APC_1: 0xffffffff
9760 13:57:19.206992 INFO: [APUAPC] D15_APC_2: 0x3fffff
9761 13:57:19.210236 INFO: [APUAPC] D15_APC_3: 0x0
9762 13:57:19.214097 INFO: [APUAPC] APC_CON: 0x4
9763 13:57:19.217230 INFO: [NOCDAPC] D0_APC_0: 0x0
9764 13:57:19.217314 INFO: [NOCDAPC] D0_APC_1: 0x0
9765 13:57:19.220694 INFO: [NOCDAPC] D1_APC_0: 0x0
9766 13:57:19.223942 INFO: [NOCDAPC] D1_APC_1: 0xfff
9767 13:57:19.227017 INFO: [NOCDAPC] D2_APC_0: 0x0
9768 13:57:19.230939 INFO: [NOCDAPC] D2_APC_1: 0xfff
9769 13:57:19.233490 INFO: [NOCDAPC] D3_APC_0: 0x0
9770 13:57:19.236631 INFO: [NOCDAPC] D3_APC_1: 0xfff
9771 13:57:19.240010 INFO: [NOCDAPC] D4_APC_0: 0x0
9772 13:57:19.243187 INFO: [NOCDAPC] D4_APC_1: 0xfff
9773 13:57:19.246458 INFO: [NOCDAPC] D5_APC_0: 0x0
9774 13:57:19.250375 INFO: [NOCDAPC] D5_APC_1: 0xfff
9775 13:57:19.250456 INFO: [NOCDAPC] D6_APC_0: 0x0
9776 13:57:19.254087 INFO: [NOCDAPC] D6_APC_1: 0xfff
9777 13:57:19.257320 INFO: [NOCDAPC] D7_APC_0: 0x0
9778 13:57:19.259642 INFO: [NOCDAPC] D7_APC_1: 0xfff
9779 13:57:19.264214 INFO: [NOCDAPC] D8_APC_0: 0x0
9780 13:57:19.267068 INFO: [NOCDAPC] D8_APC_1: 0xfff
9781 13:57:19.269698 INFO: [NOCDAPC] D9_APC_0: 0x0
9782 13:57:19.273211 INFO: [NOCDAPC] D9_APC_1: 0xfff
9783 13:57:19.276343 INFO: [NOCDAPC] D10_APC_0: 0x0
9784 13:57:19.280314 INFO: [NOCDAPC] D10_APC_1: 0xfff
9785 13:57:19.283284 INFO: [NOCDAPC] D11_APC_0: 0x0
9786 13:57:19.286361 INFO: [NOCDAPC] D11_APC_1: 0xfff
9787 13:57:19.289624 INFO: [NOCDAPC] D12_APC_0: 0x0
9788 13:57:19.293372 INFO: [NOCDAPC] D12_APC_1: 0xfff
9789 13:57:19.293453 INFO: [NOCDAPC] D13_APC_0: 0x0
9790 13:57:19.296144 INFO: [NOCDAPC] D13_APC_1: 0xfff
9791 13:57:19.300454 INFO: [NOCDAPC] D14_APC_0: 0x0
9792 13:57:19.303088 INFO: [NOCDAPC] D14_APC_1: 0xfff
9793 13:57:19.306370 INFO: [NOCDAPC] D15_APC_0: 0x0
9794 13:57:19.309641 INFO: [NOCDAPC] D15_APC_1: 0xfff
9795 13:57:19.312604 INFO: [NOCDAPC] APC_CON: 0x4
9796 13:57:19.316089 INFO: [APUAPC] set_apusys_apc done
9797 13:57:19.319472 INFO: [DEVAPC] devapc_init done
9798 13:57:19.322554 INFO: GICv3 without legacy support detected.
9799 13:57:19.326218 INFO: ARM GICv3 driver initialized in EL3
9800 13:57:19.330534 INFO: Maximum SPI INTID supported: 639
9801 13:57:19.336095 INFO: BL31: Initializing runtime services
9802 13:57:19.339317 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9803 13:57:19.342448 INFO: SPM: enable CPC mode
9804 13:57:19.349033 INFO: mcdi ready for mcusys-off-idle and system suspend
9805 13:57:19.352949 INFO: BL31: Preparing for EL3 exit to normal world
9806 13:57:19.355398 INFO: Entry point address = 0x80000000
9807 13:57:19.359545 INFO: SPSR = 0x8
9808 13:57:19.366514
9809 13:57:19.366605
9810 13:57:19.366670
9811 13:57:19.369124 Starting depthcharge on Spherion...
9812 13:57:19.369207
9813 13:57:19.369271 Wipe memory regions:
9814 13:57:19.369334
9815 13:57:19.369997 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9816 13:57:19.370101 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9817 13:57:19.370187 Setting prompt string to ['asurada:']
9818 13:57:19.370267 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9819 13:57:19.371740 [0x00000040000000, 0x00000054600000)
9820 13:57:19.493626
9821 13:57:19.493783 [0x00000054660000, 0x00000080000000)
9822 13:57:19.755019
9823 13:57:19.755178 [0x000000821a7280, 0x000000ffe64000)
9824 13:57:20.499255
9825 13:57:20.499408 [0x00000100000000, 0x00000140000000)
9826 13:57:20.881008
9827 13:57:20.883818 Initializing XHCI USB controller at 0x11200000.
9828 13:57:21.921663
9829 13:57:21.924996 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9830 13:57:21.925083
9831 13:57:21.925147
9832 13:57:21.925206
9833 13:57:21.925484 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9835 13:57:22.025871 asurada: tftpboot 192.168.201.1 12682951/tftp-deploy-j9f43ni9/kernel/image.itb 12682951/tftp-deploy-j9f43ni9/kernel/cmdline
9836 13:57:22.026082 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9837 13:57:22.026182 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9838 13:57:22.030505 tftpboot 192.168.201.1 12682951/tftp-deploy-j9f43ni9/kernel/image.itbtp-deploy-j9f43ni9/kernel/cmdline
9839 13:57:22.030588
9840 13:57:22.030652 Waiting for link
9841 13:57:22.191569
9842 13:57:22.191728 R8152: Initializing
9843 13:57:22.191793
9844 13:57:22.194673 Version 9 (ocp_data = 6010)
9845 13:57:22.194755
9846 13:57:22.197678 R8152: Done initializing
9847 13:57:22.197758
9848 13:57:22.197821 Adding net device
9849 13:57:24.139442
9850 13:57:24.139600 done.
9851 13:57:24.139664
9852 13:57:24.139723 MAC: 00:e0:4c:68:03:bd
9853 13:57:24.139779
9854 13:57:24.142258 Sending DHCP discover... done.
9855 13:57:24.142338
9856 13:57:24.146889 Waiting for reply... done.
9857 13:57:24.146969
9858 13:57:24.148947 Sending DHCP request... done.
9859 13:57:24.149026
9860 13:57:24.149089 Waiting for reply... done.
9861 13:57:24.149147
9862 13:57:24.152671 My ip is 192.168.201.16
9863 13:57:24.152806
9864 13:57:24.155484 The DHCP server ip is 192.168.201.1
9865 13:57:24.155563
9866 13:57:24.160452 TFTP server IP predefined by user: 192.168.201.1
9867 13:57:24.160532
9868 13:57:24.165824 Bootfile predefined by user: 12682951/tftp-deploy-j9f43ni9/kernel/image.itb
9869 13:57:24.165904
9870 13:57:24.168667 Sending tftp read request... done.
9871 13:57:24.168797
9872 13:57:24.172667 Waiting for the transfer...
9873 13:57:24.172809
9874 13:57:24.451613 00000000 ################################################################
9875 13:57:24.451758
9876 13:57:24.745002 00080000 ################################################################
9877 13:57:24.745146
9878 13:57:25.000955 00100000 ################################################################
9879 13:57:25.001105
9880 13:57:25.252950 00180000 ################################################################
9881 13:57:25.253084
9882 13:57:25.519549 00200000 ################################################################
9883 13:57:25.519685
9884 13:57:25.770347 00280000 ################################################################
9885 13:57:25.770488
9886 13:57:26.021800 00300000 ################################################################
9887 13:57:26.021944
9888 13:57:26.272243 00380000 ################################################################
9889 13:57:26.272377
9890 13:57:26.523352 00400000 ################################################################
9891 13:57:26.523501
9892 13:57:26.773784 00480000 ################################################################
9893 13:57:26.773915
9894 13:57:27.024762 00500000 ################################################################
9895 13:57:27.024896
9896 13:57:27.275200 00580000 ################################################################
9897 13:57:27.275334
9898 13:57:27.526038 00600000 ################################################################
9899 13:57:27.526173
9900 13:57:27.776982 00680000 ################################################################
9901 13:57:27.777111
9902 13:57:28.027811 00700000 ################################################################
9903 13:57:28.027959
9904 13:57:28.281261 00780000 ################################################################
9905 13:57:28.281408
9906 13:57:28.532306 00800000 ################################################################
9907 13:57:28.532441
9908 13:57:28.783528 00880000 ################################################################
9909 13:57:28.783668
9910 13:57:29.034525 00900000 ################################################################
9911 13:57:29.034663
9912 13:57:29.284794 00980000 ################################################################
9913 13:57:29.284935
9914 13:57:29.535400 00a00000 ################################################################
9915 13:57:29.535535
9916 13:57:29.789268 00a80000 ################################################################
9917 13:57:29.789410
9918 13:57:30.055206 00b00000 ################################################################
9919 13:57:30.055335
9920 13:57:30.305825 00b80000 ################################################################
9921 13:57:30.305969
9922 13:57:30.556700 00c00000 ################################################################
9923 13:57:30.556835
9924 13:57:30.808876 00c80000 ################################################################
9925 13:57:30.809004
9926 13:57:31.058781 00d00000 ################################################################
9927 13:57:31.058907
9928 13:57:31.315953 00d80000 ################################################################
9929 13:57:31.316086
9930 13:57:31.586397 00e00000 ################################################################
9931 13:57:31.586523
9932 13:57:31.859682 00e80000 ################################################################
9933 13:57:31.859835
9934 13:57:32.132030 00f00000 ################################################################
9935 13:57:32.132155
9936 13:57:32.412182 00f80000 ################################################################
9937 13:57:32.412322
9938 13:57:32.666056 01000000 ################################################################
9939 13:57:32.666205
9940 13:57:32.917114 01080000 ################################################################
9941 13:57:32.917250
9942 13:57:33.169029 01100000 ################################################################
9943 13:57:33.169164
9944 13:57:33.424999 01180000 ################################################################
9945 13:57:33.425138
9946 13:57:33.674933 01200000 ################################################################
9947 13:57:33.675057
9948 13:57:33.925482 01280000 ################################################################
9949 13:57:33.925615
9950 13:57:34.178780 01300000 ################################################################
9951 13:57:34.178916
9952 13:57:34.433352 01380000 ################################################################
9953 13:57:34.433506
9954 13:57:34.686716 01400000 ################################################################
9955 13:57:34.686957
9956 13:57:34.937196 01480000 ################################################################
9957 13:57:34.937346
9958 13:57:35.189636 01500000 ################################################################
9959 13:57:35.189776
9960 13:57:35.442384 01580000 ################################################################
9961 13:57:35.442525
9962 13:57:35.693746 01600000 ################################################################
9963 13:57:35.693884
9964 13:57:35.946678 01680000 ################################################################
9965 13:57:35.946818
9966 13:57:36.199804 01700000 ################################################################
9967 13:57:36.199941
9968 13:57:36.451064 01780000 ################################################################
9969 13:57:36.451225
9970 13:57:36.705440 01800000 ################################################################
9971 13:57:36.705574
9972 13:57:36.960061 01880000 ################################################################
9973 13:57:36.960193
9974 13:57:37.210986 01900000 ################################################################
9975 13:57:37.211119
9976 13:57:37.463068 01980000 ################################################################
9977 13:57:37.463195
9978 13:57:37.718265 01a00000 ################################################################
9979 13:57:37.718427
9980 13:57:37.969683 01a80000 ################################################################
9981 13:57:37.969818
9982 13:57:38.222928 01b00000 ################################################################
9983 13:57:38.223068
9984 13:57:38.477869 01b80000 ################################################################
9985 13:57:38.478003
9986 13:57:38.731227 01c00000 ################################################################
9987 13:57:38.731401
9988 13:57:38.735843 01c80000 ## done.
9989 13:57:38.735927
9990 13:57:38.738438 The bootfile was 29895738 bytes long.
9991 13:57:38.738510
9992 13:57:38.741229 Sending tftp read request... done.
9993 13:57:38.741314
9994 13:57:38.746184 Waiting for the transfer...
9995 13:57:38.746263
9996 13:57:38.746333 00000000 # done.
9997 13:57:38.746399
9998 13:57:38.754742 Command line loaded dynamically from TFTP file: 12682951/tftp-deploy-j9f43ni9/kernel/cmdline
9999 13:57:38.754828
10000 13:57:38.775160 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682951/extract-nfsrootfs-0eemlskl,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10001 13:57:38.775278
10002 13:57:38.778505 Loading FIT.
10003 13:57:38.778576
10004 13:57:38.782169 Image ramdisk-1 has 17799567 bytes.
10005 13:57:38.782246
10006 13:57:38.784352 Image fdt-1 has 47278 bytes.
10007 13:57:38.784429
10008 13:57:38.784494 Image kernel-1 has 12046857 bytes.
10009 13:57:38.787900
10010 13:57:38.794316 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10011 13:57:38.794392
10012 13:57:38.813963 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10013 13:57:38.814051
10014 13:57:38.818137 Choosing best match conf-1 for compat google,spherion-rev3.
10015 13:57:38.822351
10016 13:57:38.826539 Connected to device vid:did:rid of 1ae0:0028:00
10017 13:57:38.833827
10018 13:57:38.837156 tpm_get_response: command 0x17b, return code 0x0
10019 13:57:38.837232
10020 13:57:38.840107 ec_init: CrosEC protocol v3 supported (256, 248)
10021 13:57:38.844514
10022 13:57:38.847697 tpm_cleanup: add release locality here.
10023 13:57:38.847781
10024 13:57:38.847856 Shutting down all USB controllers.
10025 13:57:38.851585
10026 13:57:38.851666 Removing current net device
10027 13:57:38.851730
10028 13:57:38.857449 Exiting depthcharge with code 4 at timestamp: 47736057
10029 13:57:38.857531
10030 13:57:38.860724 LZMA decompressing kernel-1 to 0x821a6718
10031 13:57:38.860805
10032 13:57:38.864031 LZMA decompressing kernel-1 to 0x40000000
10033 13:57:40.363612
10034 13:57:40.363748 jumping to kernel
10035 13:57:40.364196 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10036 13:57:40.364292 start: 2.2.5 auto-login-action (timeout 00:04:05) [common]
10037 13:57:40.364369 Setting prompt string to ['Linux version [0-9]']
10038 13:57:40.364436 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 13:57:40.364504 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10040 13:57:40.414190
10041 13:57:40.417601 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10042 13:57:40.421409 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
10043 13:57:40.421502 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10044 13:57:40.421571 Setting prompt string to []
10045 13:57:40.421645 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10046 13:57:40.421715 Using line separator: #'\n'#
10047 13:57:40.421773 No login prompt set.
10048 13:57:40.421835 Parsing kernel messages
10049 13:57:40.421893 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10050 13:57:40.422068 [login-action] Waiting for messages, (timeout 00:04:05)
10051 13:57:40.440581 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10052 13:57:40.444649 [ 0.000000] random: crng init done
10053 13:57:40.450661 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10054 13:57:40.455291 [ 0.000000] efi: UEFI not found.
10055 13:57:40.460197 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10056 13:57:40.466679 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10057 13:57:40.476974 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10058 13:57:40.486915 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10059 13:57:40.493834 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10060 13:57:40.499843 [ 0.000000] printk: bootconsole [mtk8250] enabled
10061 13:57:40.506481 [ 0.000000] NUMA: No NUMA configuration found
10062 13:57:40.513317 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10063 13:57:40.516831 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10064 13:57:40.519734 [ 0.000000] Zone ranges:
10065 13:57:40.526352 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10066 13:57:40.530093 [ 0.000000] DMA32 empty
10067 13:57:40.536316 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10068 13:57:40.539426 [ 0.000000] Movable zone start for each node
10069 13:57:40.542716 [ 0.000000] Early memory node ranges
10070 13:57:40.550277 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10071 13:57:40.555810 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10072 13:57:40.562868 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10073 13:57:40.569639 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10074 13:57:40.576473 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10075 13:57:40.582244 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10076 13:57:40.612901 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10077 13:57:40.618833 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10078 13:57:40.625644 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10079 13:57:40.629285 [ 0.000000] psci: probing for conduit method from DT.
10080 13:57:40.635665 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10081 13:57:40.638636 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10082 13:57:40.645315 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10083 13:57:40.649064 [ 0.000000] psci: SMC Calling Convention v1.2
10084 13:57:40.655479 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10085 13:57:40.659129 [ 0.000000] Detected VIPT I-cache on CPU0
10086 13:57:40.665765 [ 0.000000] CPU features: detected: GIC system register CPU interface
10087 13:57:40.671980 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10088 13:57:40.678957 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10089 13:57:40.685418 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10090 13:57:40.691691 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10091 13:57:40.702052 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10092 13:57:40.705100 [ 0.000000] alternatives: applying boot alternatives
10093 13:57:40.712176 [ 0.000000] Fallback order for Node 0: 0
10094 13:57:40.718536 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10095 13:57:40.721609 [ 0.000000] Policy zone: Normal
10096 13:57:40.744385 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682951/extract-nfsrootfs-0eemlskl,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10097 13:57:40.754545 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10098 13:57:40.764846 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10099 13:57:40.771657 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10100 13:57:40.777298 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10101 13:57:40.783851 <6>[ 0.000000] software IO TLB: area num 8.
10102 13:57:40.839328 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10103 13:57:40.919568 <6>[ 0.000000] Memory: 3835460K/4191232K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 323004K reserved, 32768K cma-reserved)
10104 13:57:40.925829 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10105 13:57:40.932324 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10106 13:57:40.935763 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10107 13:57:40.943354 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10108 13:57:40.948609 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10109 13:57:40.952233 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10110 13:57:40.962273 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10111 13:57:40.969372 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10112 13:57:40.975295 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10113 13:57:40.981640 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10114 13:57:40.985499 <6>[ 0.000000] GICv3: 608 SPIs implemented
10115 13:57:40.988746 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10116 13:57:40.995571 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10117 13:57:40.998826 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10118 13:57:41.004765 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10119 13:57:41.018378 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10120 13:57:41.031520 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10121 13:57:41.038141 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10122 13:57:41.045712 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10123 13:57:41.059124 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10124 13:57:41.065312 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10125 13:57:41.072788 <6>[ 0.009177] Console: colour dummy device 80x25
10126 13:57:41.082159 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10127 13:57:41.088494 <6>[ 0.024411] pid_max: default: 32768 minimum: 301
10128 13:57:41.092425 <6>[ 0.029281] LSM: Security Framework initializing
10129 13:57:41.099593 <6>[ 0.034194] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10130 13:57:41.108691 <6>[ 0.041803] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10131 13:57:41.115243 <6>[ 0.051070] cblist_init_generic: Setting adjustable number of callback queues.
10132 13:57:41.121931 <6>[ 0.058512] cblist_init_generic: Setting shift to 3 and lim to 1.
10133 13:57:41.131739 <6>[ 0.064849] cblist_init_generic: Setting adjustable number of callback queues.
10134 13:57:41.135172 <6>[ 0.072322] cblist_init_generic: Setting shift to 3 and lim to 1.
10135 13:57:41.141741 <6>[ 0.078722] rcu: Hierarchical SRCU implementation.
10136 13:57:41.148075 <6>[ 0.083737] rcu: Max phase no-delay instances is 1000.
10137 13:57:41.155358 <6>[ 0.090760] EFI services will not be available.
10138 13:57:41.158599 <6>[ 0.095744] smp: Bringing up secondary CPUs ...
10139 13:57:41.166569 <6>[ 0.100792] Detected VIPT I-cache on CPU1
10140 13:57:41.172509 <6>[ 0.100861] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10141 13:57:41.179082 <6>[ 0.100891] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10142 13:57:41.183117 <6>[ 0.101225] Detected VIPT I-cache on CPU2
10143 13:57:41.189970 <6>[ 0.101273] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10144 13:57:41.199672 <6>[ 0.101288] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10145 13:57:41.202545 <6>[ 0.101543] Detected VIPT I-cache on CPU3
10146 13:57:41.208958 <6>[ 0.101588] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10147 13:57:41.215510 <6>[ 0.101602] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10148 13:57:41.219216 <6>[ 0.101902] CPU features: detected: Spectre-v4
10149 13:57:41.226031 <6>[ 0.101908] CPU features: detected: Spectre-BHB
10150 13:57:41.229196 <6>[ 0.101913] Detected PIPT I-cache on CPU4
10151 13:57:41.235789 <6>[ 0.101969] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10152 13:57:41.242189 <6>[ 0.101985] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10153 13:57:41.248727 <6>[ 0.102272] Detected PIPT I-cache on CPU5
10154 13:57:41.256139 <6>[ 0.102331] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10155 13:57:41.261994 <6>[ 0.102347] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10156 13:57:41.265269 <6>[ 0.102613] Detected PIPT I-cache on CPU6
10157 13:57:41.271965 <6>[ 0.102668] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10158 13:57:41.279013 <6>[ 0.102684] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10159 13:57:41.285543 <6>[ 0.102977] Detected PIPT I-cache on CPU7
10160 13:57:41.291773 <6>[ 0.103040] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10161 13:57:41.299045 <6>[ 0.103057] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10162 13:57:41.301699 <6>[ 0.103103] smp: Brought up 1 node, 8 CPUs
10163 13:57:41.308417 <6>[ 0.244415] SMP: Total of 8 processors activated.
10164 13:57:41.311903 <6>[ 0.249336] CPU features: detected: 32-bit EL0 Support
10165 13:57:41.321783 <6>[ 0.254699] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10166 13:57:41.328268 <6>[ 0.263499] CPU features: detected: Common not Private translations
10167 13:57:41.335076 <6>[ 0.269975] CPU features: detected: CRC32 instructions
10168 13:57:41.337995 <6>[ 0.275326] CPU features: detected: RCpc load-acquire (LDAPR)
10169 13:57:41.344632 <6>[ 0.281323] CPU features: detected: LSE atomic instructions
10170 13:57:41.351770 <6>[ 0.287104] CPU features: detected: Privileged Access Never
10171 13:57:41.358397 <6>[ 0.292884] CPU features: detected: RAS Extension Support
10172 13:57:41.364486 <6>[ 0.298493] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10173 13:57:41.367702 <6>[ 0.305710] CPU: All CPU(s) started at EL2
10174 13:57:41.374139 <6>[ 0.310026] alternatives: applying system-wide alternatives
10175 13:57:41.382964 <6>[ 0.319938] devtmpfs: initialized
10176 13:57:41.398357 <6>[ 0.328164] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10177 13:57:41.404207 <6>[ 0.338125] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10178 13:57:41.411827 <6>[ 0.346374] pinctrl core: initialized pinctrl subsystem
10179 13:57:41.414160 <6>[ 0.353013] DMI not present or invalid.
10180 13:57:41.420663 <6>[ 0.357415] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10181 13:57:41.430707 <6>[ 0.364268] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10182 13:57:41.437817 <6>[ 0.371720] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10183 13:57:41.447066 <6>[ 0.379812] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10184 13:57:41.450957 <6>[ 0.387968] audit: initializing netlink subsys (disabled)
10185 13:57:41.460851 <5>[ 0.393663] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10186 13:57:41.467221 <6>[ 0.394348] thermal_sys: Registered thermal governor 'step_wise'
10187 13:57:41.473913 <6>[ 0.401632] thermal_sys: Registered thermal governor 'power_allocator'
10188 13:57:41.477232 <6>[ 0.407887] cpuidle: using governor menu
10189 13:57:41.483639 <6>[ 0.418842] NET: Registered PF_QIPCRTR protocol family
10190 13:57:41.490817 <6>[ 0.424327] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10191 13:57:41.493779 <6>[ 0.431430] ASID allocator initialised with 32768 entries
10192 13:57:41.500642 <6>[ 0.437959] Serial: AMBA PL011 UART driver
10193 13:57:41.510198 <4>[ 0.446673] Trying to register duplicate clock ID: 134
10194 13:57:41.563946 <6>[ 0.503923] KASLR enabled
10195 13:57:41.578204 <6>[ 0.511588] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10196 13:57:41.584709 <6>[ 0.518604] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10197 13:57:41.591382 <6>[ 0.525093] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10198 13:57:41.597480 <6>[ 0.532098] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10199 13:57:41.604234 <6>[ 0.538586] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10200 13:57:41.610614 <6>[ 0.545590] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10201 13:57:41.617908 <6>[ 0.552078] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10202 13:57:41.624141 <6>[ 0.559084] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10203 13:57:41.627647 <6>[ 0.566511] ACPI: Interpreter disabled.
10204 13:57:41.636158 <6>[ 0.572877] iommu: Default domain type: Translated
10205 13:57:41.642467 <6>[ 0.578028] iommu: DMA domain TLB invalidation policy: strict mode
10206 13:57:41.645621 <5>[ 0.584686] SCSI subsystem initialized
10207 13:57:41.653233 <6>[ 0.588906] usbcore: registered new interface driver usbfs
10208 13:57:41.659740 <6>[ 0.594636] usbcore: registered new interface driver hub
10209 13:57:41.662155 <6>[ 0.600189] usbcore: registered new device driver usb
10210 13:57:41.669388 <6>[ 0.606293] pps_core: LinuxPPS API ver. 1 registered
10211 13:57:41.679011 <6>[ 0.611487] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10212 13:57:41.683116 <6>[ 0.620832] PTP clock support registered
10213 13:57:41.685847 <6>[ 0.625074] EDAC MC: Ver: 3.0.0
10214 13:57:41.693421 <6>[ 0.630245] FPGA manager framework
10215 13:57:41.699866 <6>[ 0.633919] Advanced Linux Sound Architecture Driver Initialized.
10216 13:57:41.703453 <6>[ 0.640680] vgaarb: loaded
10217 13:57:41.709963 <6>[ 0.643825] clocksource: Switched to clocksource arch_sys_counter
10218 13:57:41.713569 <5>[ 0.650271] VFS: Disk quotas dquot_6.6.0
10219 13:57:41.720208 <6>[ 0.654457] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10220 13:57:41.723068 <6>[ 0.661648] pnp: PnP ACPI: disabled
10221 13:57:41.731778 <6>[ 0.668305] NET: Registered PF_INET protocol family
10222 13:57:41.738039 <6>[ 0.673684] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10223 13:57:41.749933 <6>[ 0.683704] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10224 13:57:41.760230 <6>[ 0.692490] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10225 13:57:41.766704 <6>[ 0.700459] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10226 13:57:41.773239 <6>[ 0.708862] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10227 13:57:41.784350 <6>[ 0.717525] TCP: Hash tables configured (established 32768 bind 32768)
10228 13:57:41.790318 <6>[ 0.724382] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10229 13:57:41.797419 <6>[ 0.731402] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10230 13:57:41.803374 <6>[ 0.738925] NET: Registered PF_UNIX/PF_LOCAL protocol family
10231 13:57:41.810248 <6>[ 0.745069] RPC: Registered named UNIX socket transport module.
10232 13:57:41.813513 <6>[ 0.751222] RPC: Registered udp transport module.
10233 13:57:41.820573 <6>[ 0.756153] RPC: Registered tcp transport module.
10234 13:57:41.826770 <6>[ 0.761085] RPC: Registered tcp NFSv4.1 backchannel transport module.
10235 13:57:41.829928 <6>[ 0.767751] PCI: CLS 0 bytes, default 64
10236 13:57:41.832993 <6>[ 0.772107] Unpacking initramfs...
10237 13:57:41.843131 <6>[ 0.775831] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10238 13:57:41.849813 <6>[ 0.784465] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10239 13:57:41.856624 <6>[ 0.793305] kvm [1]: IPA Size Limit: 40 bits
10240 13:57:41.859985 <6>[ 0.797833] kvm [1]: GICv3: no GICV resource entry
10241 13:57:41.866234 <6>[ 0.802856] kvm [1]: disabling GICv2 emulation
10242 13:57:41.873578 <6>[ 0.807542] kvm [1]: GIC system register CPU interface enabled
10243 13:57:41.876248 <6>[ 0.813707] kvm [1]: vgic interrupt IRQ18
10244 13:57:41.882811 <6>[ 0.818067] kvm [1]: VHE mode initialized successfully
10245 13:57:41.887347 <5>[ 0.824557] Initialise system trusted keyrings
10246 13:57:41.892369 <6>[ 0.829406] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10247 13:57:41.902823 <6>[ 0.839354] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10248 13:57:41.909191 <5>[ 0.845727] NFS: Registering the id_resolver key type
10249 13:57:41.912205 <5>[ 0.851027] Key type id_resolver registered
10250 13:57:41.918585 <5>[ 0.855438] Key type id_legacy registered
10251 13:57:41.925865 <6>[ 0.859716] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10252 13:57:41.932541 <6>[ 0.866641] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10253 13:57:41.938769 <6>[ 0.874387] 9p: Installing v9fs 9p2000 file system support
10254 13:57:41.975695 <5>[ 0.912749] Key type asymmetric registered
10255 13:57:41.979166 <5>[ 0.917081] Asymmetric key parser 'x509' registered
10256 13:57:41.989665 <6>[ 0.922232] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10257 13:57:41.993127 <6>[ 0.929844] io scheduler mq-deadline registered
10258 13:57:41.995723 <6>[ 0.934605] io scheduler kyber registered
10259 13:57:42.014925 <6>[ 0.951559] EINJ: ACPI disabled.
10260 13:57:42.046670 <4>[ 0.976886] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10261 13:57:42.056915 <4>[ 0.987526] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10262 13:57:42.071334 <6>[ 1.008395] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10263 13:57:42.079839 <6>[ 1.016483] printk: console [ttyS0] disabled
10264 13:57:42.107862 <6>[ 1.041128] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10265 13:57:42.114762 <6>[ 1.050601] printk: console [ttyS0] enabled
10266 13:57:42.117630 <6>[ 1.050601] printk: console [ttyS0] enabled
10267 13:57:42.124829 <6>[ 1.059499] printk: bootconsole [mtk8250] disabled
10268 13:57:42.127258 <6>[ 1.059499] printk: bootconsole [mtk8250] disabled
10269 13:57:42.134319 <6>[ 1.070805] SuperH (H)SCI(F) driver initialized
10270 13:57:42.137148 <6>[ 1.076111] msm_serial: driver initialized
10271 13:57:42.151401 <6>[ 1.085090] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10272 13:57:42.161597 <6>[ 1.093644] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10273 13:57:42.167901 <6>[ 1.102186] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10274 13:57:42.178359 <6>[ 1.110815] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10275 13:57:42.188324 <6>[ 1.119522] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10276 13:57:42.194807 <6>[ 1.128236] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10277 13:57:42.204141 <6>[ 1.136777] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10278 13:57:42.210755 <6>[ 1.145584] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10279 13:57:42.221062 <6>[ 1.154127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10280 13:57:42.232841 <6>[ 1.169965] loop: module loaded
10281 13:57:42.239769 <6>[ 1.175896] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10282 13:57:42.261913 <4>[ 1.199065] mtk-pmic-keys: Failed to locate of_node [id: -1]
10283 13:57:42.269830 <6>[ 1.206136] megasas: 07.719.03.00-rc1
10284 13:57:42.278606 <6>[ 1.215772] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10285 13:57:42.286416 <6>[ 1.223190] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10286 13:57:42.302768 <6>[ 1.239620] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10287 13:57:42.358120 <6>[ 1.288581] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10288 13:57:42.569883 <6>[ 1.507021] Freeing initrd memory: 17380K
10289 13:57:42.579908 <6>[ 1.517128] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10290 13:57:42.590995 <6>[ 1.527862] tun: Universal TUN/TAP device driver, 1.6
10291 13:57:42.594142 <6>[ 1.533909] thunder_xcv, ver 1.0
10292 13:57:42.597532 <6>[ 1.537418] thunder_bgx, ver 1.0
10293 13:57:42.600657 <6>[ 1.540912] nicpf, ver 1.0
10294 13:57:42.611836 <6>[ 1.544909] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10295 13:57:42.614634 <6>[ 1.552385] hns3: Copyright (c) 2017 Huawei Corporation.
10296 13:57:42.621147 <6>[ 1.557970] hclge is initializing
10297 13:57:42.624249 <6>[ 1.561550] e1000: Intel(R) PRO/1000 Network Driver
10298 13:57:42.631357 <6>[ 1.566679] e1000: Copyright (c) 1999-2006 Intel Corporation.
10299 13:57:42.634391 <6>[ 1.572690] e1000e: Intel(R) PRO/1000 Network Driver
10300 13:57:42.640932 <6>[ 1.577905] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10301 13:57:42.647437 <6>[ 1.584090] igb: Intel(R) Gigabit Ethernet Network Driver
10302 13:57:42.654445 <6>[ 1.589739] igb: Copyright (c) 2007-2014 Intel Corporation.
10303 13:57:42.661132 <6>[ 1.595578] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10304 13:57:42.667328 <6>[ 1.602096] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10305 13:57:42.670561 <6>[ 1.608554] sky2: driver version 1.30
10306 13:57:42.678325 <6>[ 1.613530] VFIO - User Level meta-driver version: 0.3
10307 13:57:42.684683 <6>[ 1.621744] usbcore: registered new interface driver usb-storage
10308 13:57:42.691975 <6>[ 1.628191] usbcore: registered new device driver onboard-usb-hub
10309 13:57:42.700279 <6>[ 1.637318] mt6397-rtc mt6359-rtc: registered as rtc0
10310 13:57:42.711162 <6>[ 1.642786] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:57:42 UTC (1706795862)
10311 13:57:42.713763 <6>[ 1.652379] i2c_dev: i2c /dev entries driver
10312 13:57:42.731101 <6>[ 1.664036] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10313 13:57:42.750310 <6>[ 1.687001] cpu cpu0: EM: created perf domain
10314 13:57:42.753187 <6>[ 1.691907] cpu cpu4: EM: created perf domain
10315 13:57:42.760558 <6>[ 1.697429] sdhci: Secure Digital Host Controller Interface driver
10316 13:57:42.767248 <6>[ 1.703863] sdhci: Copyright(c) Pierre Ossman
10317 13:57:42.774092 <6>[ 1.708773] Synopsys Designware Multimedia Card Interface Driver
10318 13:57:42.780529 <6>[ 1.715367] sdhci-pltfm: SDHCI platform and OF driver helper
10319 13:57:42.783668 <6>[ 1.715422] mmc0: CQHCI version 5.10
10320 13:57:42.790996 <6>[ 1.725650] ledtrig-cpu: registered to indicate activity on CPUs
10321 13:57:42.796476 <6>[ 1.732672] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10322 13:57:42.803133 <6>[ 1.739694] usbcore: registered new interface driver usbhid
10323 13:57:42.806595 <6>[ 1.745515] usbhid: USB HID core driver
10324 13:57:42.813277 <6>[ 1.749721] spi_master spi0: will run message pump with realtime priority
10325 13:57:42.856055 <6>[ 1.786716] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10326 13:57:42.871523 <6>[ 1.801698] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10327 13:57:42.878662 <6>[ 1.815320] mmc0: Command Queue Engine enabled
10328 13:57:42.885335 <6>[ 1.820105] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10329 13:57:42.892001 <6>[ 1.827024] cros-ec-spi spi0.0: Chrome EC device registered
10330 13:57:42.894820 <6>[ 1.827295] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10331 13:57:42.905170 <6>[ 1.842141] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10332 13:57:42.912654 <6>[ 1.849591] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10333 13:57:42.919338 <6>[ 1.855444] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10334 13:57:42.926187 <6>[ 1.861349] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10335 13:57:42.939324 <6>[ 1.873317] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10336 13:57:42.946609 <6>[ 1.883991] NET: Registered PF_PACKET protocol family
10337 13:57:42.950508 <6>[ 1.889376] 9pnet: Installing 9P2000 support
10338 13:57:42.957350 <5>[ 1.893939] Key type dns_resolver registered
10339 13:57:42.960173 <6>[ 1.898892] registered taskstats version 1
10340 13:57:42.966848 <5>[ 1.903276] Loading compiled-in X.509 certificates
10341 13:57:42.996394 <4>[ 1.926882] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10342 13:57:43.006742 <4>[ 1.937611] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10343 13:57:43.013280 <3>[ 1.948204] debugfs: File 'uA_load' in directory '/' already present!
10344 13:57:43.019820 <3>[ 1.954909] debugfs: File 'min_uV' in directory '/' already present!
10345 13:57:43.026698 <3>[ 1.961518] debugfs: File 'max_uV' in directory '/' already present!
10346 13:57:43.033146 <3>[ 1.968125] debugfs: File 'constraint_flags' in directory '/' already present!
10347 13:57:43.044173 <3>[ 1.977797] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10348 13:57:43.054581 <6>[ 1.991079] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10349 13:57:43.061313 <6>[ 1.997861] xhci-mtk 11200000.usb: xHCI Host Controller
10350 13:57:43.067391 <6>[ 2.003356] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10351 13:57:43.077849 <6>[ 2.011188] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10352 13:57:43.084421 <6>[ 2.020602] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10353 13:57:43.090769 <6>[ 2.026667] xhci-mtk 11200000.usb: xHCI Host Controller
10354 13:57:43.097454 <6>[ 2.032142] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10355 13:57:43.103673 <6>[ 2.039785] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10356 13:57:43.110870 <6>[ 2.047417] hub 1-0:1.0: USB hub found
10357 13:57:43.113895 <6>[ 2.051424] hub 1-0:1.0: 1 port detected
10358 13:57:43.120539 <6>[ 2.055690] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10359 13:57:43.127180 <6>[ 2.064221] hub 2-0:1.0: USB hub found
10360 13:57:43.130894 <6>[ 2.068223] hub 2-0:1.0: 1 port detected
10361 13:57:43.137454 <6>[ 2.074408] mtk-msdc 11f70000.mmc: Got CD GPIO
10362 13:57:43.149187 <6>[ 2.082978] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10363 13:57:43.155997 <6>[ 2.091021] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10364 13:57:43.166048 <4>[ 2.098913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10365 13:57:43.175956 <6>[ 2.108439] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10366 13:57:43.182181 <6>[ 2.116516] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10367 13:57:43.188919 <6>[ 2.124552] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10368 13:57:43.198937 <6>[ 2.132470] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10369 13:57:43.205512 <6>[ 2.140286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10370 13:57:43.216693 <6>[ 2.148101] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10371 13:57:43.225974 <6>[ 2.158459] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10372 13:57:43.231923 <6>[ 2.166816] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10373 13:57:43.242179 <6>[ 2.175159] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10374 13:57:43.248689 <6>[ 2.183496] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10375 13:57:43.259014 <6>[ 2.191838] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10376 13:57:43.265455 <6>[ 2.200177] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10377 13:57:43.274934 <6>[ 2.208515] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10378 13:57:43.281756 <6>[ 2.216853] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10379 13:57:43.291934 <6>[ 2.225191] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10380 13:57:43.298914 <6>[ 2.233530] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10381 13:57:43.308260 <6>[ 2.241881] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10382 13:57:43.318187 <6>[ 2.250219] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10383 13:57:43.324979 <6>[ 2.258569] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10384 13:57:43.334676 <6>[ 2.266908] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10385 13:57:43.341516 <6>[ 2.275245] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10386 13:57:43.348275 <6>[ 2.283935] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10387 13:57:43.354570 <6>[ 2.291057] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10388 13:57:43.361695 <6>[ 2.297786] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10389 13:57:43.367600 <6>[ 2.304507] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10390 13:57:43.377627 <6>[ 2.311453] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10391 13:57:43.384267 <6>[ 2.318314] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10392 13:57:43.393965 <6>[ 2.327443] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10393 13:57:43.404398 <6>[ 2.336562] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10394 13:57:43.413798 <6>[ 2.345854] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10395 13:57:43.424256 <6>[ 2.355320] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10396 13:57:43.430762 <6>[ 2.364786] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10397 13:57:43.440349 <6>[ 2.373904] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10398 13:57:43.449964 <6>[ 2.383368] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10399 13:57:43.460125 <6>[ 2.392485] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10400 13:57:43.470738 <6>[ 2.401778] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10401 13:57:43.479819 <6>[ 2.411939] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10402 13:57:43.489993 <6>[ 2.423532] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10403 13:57:43.496626 <6>[ 2.432936] Trying to probe devices needed for running init ...
10404 13:57:43.539203 <6>[ 2.472099] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10405 13:57:43.692982 <6>[ 2.630144] hub 1-1:1.0: USB hub found
10406 13:57:43.697174 <6>[ 2.634658] hub 1-1:1.0: 4 ports detected
10407 13:57:43.706152 <6>[ 2.643550] hub 1-1:1.0: USB hub found
10408 13:57:43.709279 <6>[ 2.648040] hub 1-1:1.0: 4 ports detected
10409 13:57:43.818298 <6>[ 2.752486] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10410 13:57:43.846698 <6>[ 2.783510] hub 2-1:1.0: USB hub found
10411 13:57:43.851091 <6>[ 2.788051] hub 2-1:1.0: 3 ports detected
10412 13:57:43.859178 <6>[ 2.796529] hub 2-1:1.0: USB hub found
10413 13:57:43.862973 <6>[ 2.800917] hub 2-1:1.0: 3 ports detected
10414 13:57:44.030157 <6>[ 2.964190] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10415 13:57:44.161875 <6>[ 3.099129] hub 1-1.4:1.0: USB hub found
10416 13:57:44.165853 <6>[ 3.103801] hub 1-1.4:1.0: 2 ports detected
10417 13:57:44.173956 <6>[ 3.110963] hub 1-1.4:1.0: USB hub found
10418 13:57:44.176783 <6>[ 3.115512] hub 1-1.4:1.0: 2 ports detected
10419 13:57:44.246546 <6>[ 3.180152] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10420 13:57:44.474756 <6>[ 3.408134] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10421 13:57:44.666431 <6>[ 3.600116] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10422 13:57:55.766993 <6>[ 14.709106] ALSA device list:
10423 13:57:55.773862 <6>[ 14.712399] No soundcards found.
10424 13:57:55.782330 <6>[ 14.720222] Freeing unused kernel memory: 8448K
10425 13:57:55.785255 <6>[ 14.725271] Run /init as init process
10426 13:57:55.796535 Loading, please wait...
10427 13:57:55.816370 Starting version 247.3-7+deb11u2
10428 13:57:56.004406 <6>[ 14.939525] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10429 13:57:56.017489 <6>[ 14.953009] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10430 13:57:56.024322 <6>[ 14.960887] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10431 13:57:56.030731 <6>[ 14.964193] remoteproc remoteproc0: scp is available
10432 13:57:56.041369 <6>[ 14.969613] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10433 13:57:56.044302 <6>[ 14.974912] remoteproc remoteproc0: powering up scp
10434 13:57:56.054651 <6>[ 14.988673] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10435 13:57:56.061922 <6>[ 14.997114] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10436 13:57:56.072745 <3>[ 15.007720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10437 13:57:56.080152 <3>[ 15.015982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10438 13:57:56.089235 <4>[ 15.022477] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10439 13:57:56.096304 <3>[ 15.024090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10440 13:57:56.102828 <4>[ 15.033721] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10441 13:57:56.109508 <6>[ 15.035647] mc: Linux media interface: v0.10
10442 13:57:56.116492 <6>[ 15.035872] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10443 13:57:56.122579 <3>[ 15.039809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10444 13:57:56.129233 <6>[ 15.040708] usbcore: registered new device driver r8152-cfgselector
10445 13:57:56.135478 <6>[ 15.054300] videodev: Linux video capture interface: v2.00
10446 13:57:56.146205 <3>[ 15.059352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10447 13:57:56.152670 <4>[ 15.073713] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10448 13:57:56.159624 <4>[ 15.073713] Fallback method does not support PEC.
10449 13:57:56.165732 <3>[ 15.074177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10450 13:57:56.175866 <3>[ 15.094597] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10451 13:57:56.183718 <3>[ 15.101686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10452 13:57:56.190178 <6>[ 15.114798] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10453 13:57:56.196991 <3>[ 15.118336] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10454 13:57:56.207145 <3>[ 15.118373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10455 13:57:56.213960 <3>[ 15.118398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10456 13:57:56.220420 <6>[ 15.126459] pci_bus 0000:00: root bus resource [bus 00-ff]
10457 13:57:56.226123 <6>[ 15.128259] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10458 13:57:56.237112 <6>[ 15.128336] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10459 13:57:56.243131 <6>[ 15.128342] remoteproc remoteproc0: remote processor scp is now up
10460 13:57:56.249123 <3>[ 15.129887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10461 13:57:56.259187 <3>[ 15.133317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10462 13:57:56.266009 <6>[ 15.141402] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10463 13:57:56.272398 <6>[ 15.141725] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10464 13:57:56.283522 <6>[ 15.142683] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10465 13:57:56.289602 <6>[ 15.145201] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10466 13:57:56.298953 <3>[ 15.149468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10467 13:57:56.309117 <6>[ 15.153135] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10468 13:57:56.318553 <6>[ 15.153571] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10469 13:57:56.325446 <6>[ 15.156115] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10470 13:57:56.335772 <6>[ 15.157580] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10471 13:57:56.345386 <3>[ 15.163337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10472 13:57:56.355177 <4>[ 15.167118] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10473 13:57:56.361699 <4>[ 15.167127] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10474 13:57:56.368331 <6>[ 15.170369] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10475 13:57:56.374666 <3>[ 15.178841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10476 13:57:56.384783 <6>[ 15.185276] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10477 13:57:56.391552 <3>[ 15.194035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10478 13:57:56.398515 <6>[ 15.202189] pci 0000:00:00.0: supports D1 D2
10479 13:57:56.401005 <6>[ 15.202558] Bluetooth: Core ver 2.22
10480 13:57:56.404687 <6>[ 15.202604] NET: Registered PF_BLUETOOTH protocol family
10481 13:57:56.411003 <6>[ 15.202605] Bluetooth: HCI device and connection manager initialized
10482 13:57:56.417954 <6>[ 15.202619] Bluetooth: HCI socket layer initialized
10483 13:57:56.424070 <6>[ 15.202623] Bluetooth: L2CAP socket layer initialized
10484 13:57:56.427898 <6>[ 15.202629] Bluetooth: SCO socket layer initialized
10485 13:57:56.437524 <3>[ 15.209238] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10486 13:57:56.444588 <6>[ 15.217575] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10487 13:57:56.447528 <6>[ 15.220052] r8152 2-1.3:1.0 eth0: v1.12.13
10488 13:57:56.455496 <6>[ 15.220149] usbcore: registered new interface driver r8152
10489 13:57:56.460653 <3>[ 15.225824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10490 13:57:56.467771 <6>[ 15.227138] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10491 13:57:56.480699 <6>[ 15.228247] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10492 13:57:56.487362 <6>[ 15.228385] usbcore: registered new interface driver uvcvideo
10493 13:57:56.494016 <6>[ 15.234943] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10494 13:57:56.503727 <3>[ 15.242184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10495 13:57:56.510362 <6>[ 15.242876] usbcore: registered new interface driver cdc_ether
10496 13:57:56.516950 <6>[ 15.252421] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10497 13:57:56.519947 <6>[ 15.261951] usbcore: registered new interface driver r8153_ecm
10498 13:57:56.529843 <6>[ 15.270621] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10499 13:57:56.536417 <6>[ 15.270642] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10500 13:57:56.543818 <6>[ 15.270657] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10501 13:57:56.550420 <6>[ 15.270774] pci 0000:01:00.0: supports D1 D2
10502 13:57:56.554157 <6>[ 15.271271] usbcore: registered new interface driver btusb
10503 13:57:56.559416 <6>[ 15.272363] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10504 13:57:56.569824 <4>[ 15.281074] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10505 13:57:56.579362 <6>[ 15.288637] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10506 13:57:56.583067 <6>[ 15.294320] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10507 13:57:56.589599 <3>[ 15.297712] Bluetooth: hci0: Failed to load firmware file (-2)
10508 13:57:56.596191 <3>[ 15.297718] Bluetooth: hci0: Failed to set up firmware (-2)
10509 13:57:56.606172 <4>[ 15.297723] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10510 13:57:56.612885 <6>[ 15.299870] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10511 13:57:56.622701 <6>[ 15.556816] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10512 13:57:56.629255 <6>[ 15.564899] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10513 13:57:56.635621 <6>[ 15.572900] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10514 13:57:56.645802 <6>[ 15.580902] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10515 13:57:56.653720 <6>[ 15.588903] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10516 13:57:56.658721 <6>[ 15.596901] pci 0000:00:00.0: PCI bridge to [bus 01]
10517 13:57:56.665734 <6>[ 15.602117] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10518 13:57:56.672226 <6>[ 15.610322] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10519 13:57:56.678643 <6>[ 15.617130] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10520 13:57:56.685092 <6>[ 15.623628] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10521 13:57:56.706719 <5>[ 15.642308] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10522 13:57:56.725234 <5>[ 15.660814] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10523 13:57:56.732130 <5>[ 15.668288] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10524 13:57:56.742389 <4>[ 15.676775] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10525 13:57:56.749265 <6>[ 15.685679] cfg80211: failed to load regulatory.db
10526 13:57:56.807698 <6>[ 15.742826] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10527 13:57:56.814033 <6>[ 15.750391] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10528 13:57:56.838019 <6>[ 15.776065] mt7921e 0000:01:00.0: ASIC revision: 79610010
10529 13:57:56.940973 <6>[ 15.876043] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10530 13:57:56.944614 <6>[ 15.876043]
10531 13:57:56.967493 Begin: Loading essential drivers ... done.
10532 13:57:56.971196 Begin: Running /scripts/init-premount ... done.
10533 13:57:56.977617 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10534 13:57:56.987471 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10535 13:57:56.990339 Device /sys/class/net/enx00e04c6803bd found
10536 13:57:56.990421 done.
10537 13:57:57.072489 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10538 13:57:57.210990 <6>[ 16.146245] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10539 13:57:57.865803 <6>[ 16.804449] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10540 13:57:58.050564 <6>[ 16.989398] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10541 13:57:58.204168 IP-Config: no response after 2 secs - giving up
10542 13:57:58.233454 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10543 13:57:58.952636 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10544 13:57:58.955978 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10545 13:57:58.962429 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10546 13:57:58.969863 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10547 13:57:58.975403 host : mt8192-asurada-spherion-r0-cbg-4
10548 13:57:58.983051 domain : lava-rack
10549 13:57:58.986002 rootserver: 192.168.201.1 rootpath:
10550 13:57:58.988580 filename :
10551 13:57:59.055510 done.
10552 13:57:59.058649 Begin: Running /scripts/nfs-bottom ... done.
10553 13:57:59.076189 Begin: Running /scripts/init-bottom ... done.
10554 13:58:00.229755 <6>[ 19.168687] NET: Registered PF_INET6 protocol family
10555 13:58:00.236908 <6>[ 19.176161] Segment Routing with IPv6
10556 13:58:00.241133 <6>[ 19.180125] In-situ OAM (IOAM) with IPv6
10557 13:58:00.368208 <30>[ 19.287774] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10558 13:58:00.371868 <30>[ 19.312221] systemd[1]: Detected architecture arm64.
10559 13:58:00.392229
10560 13:58:00.394990 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10561 13:58:00.395072
10562 13:58:00.411041 <30>[ 19.350054] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10563 13:58:01.139508 <30>[ 20.075218] systemd[1]: Queued start job for default target Graphical Interface.
10564 13:58:01.183289 <30>[ 20.122635] systemd[1]: Created slice system-getty.slice.
10565 13:58:01.190589 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10566 13:58:01.208239 <30>[ 20.145576] systemd[1]: Created slice system-modprobe.slice.
10567 13:58:01.213583 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10568 13:58:01.233367 <30>[ 20.169363] systemd[1]: Created slice system-serial\x2dgetty.slice.
10569 13:58:01.239541 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10570 13:58:01.254071 <30>[ 20.193185] systemd[1]: Created slice User and Session Slice.
10571 13:58:01.260353 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10572 13:58:01.280960 <30>[ 20.216952] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10573 13:58:01.291133 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10574 13:58:01.309297 <30>[ 20.244864] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10575 13:58:01.315629 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10576 13:58:01.339847 <30>[ 20.272268] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10577 13:58:01.346422 <30>[ 20.284413] systemd[1]: Reached target Local Encrypted Volumes.
10578 13:58:01.352569 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10579 13:58:01.369176 <30>[ 20.308624] systemd[1]: Reached target Paths.
10580 13:58:01.376194 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10581 13:58:01.389055 <30>[ 20.328102] systemd[1]: Reached target Remote File Systems.
10582 13:58:01.395054 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10583 13:58:01.413521 <30>[ 20.352473] systemd[1]: Reached target Slices.
10584 13:58:01.421197 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10585 13:58:01.433204 <30>[ 20.372118] systemd[1]: Reached target Swap.
10586 13:58:01.436625 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10587 13:58:01.456737 <30>[ 20.392632] systemd[1]: Listening on initctl Compatibility Named Pipe.
10588 13:58:01.463446 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10589 13:58:01.470309 <30>[ 20.408710] systemd[1]: Listening on Journal Audit Socket.
10590 13:58:01.476820 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10591 13:58:01.494393 <30>[ 20.433341] systemd[1]: Listening on Journal Socket (/dev/log).
10592 13:58:01.500604 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10593 13:58:01.517403 <30>[ 20.456676] systemd[1]: Listening on Journal Socket.
10594 13:58:01.523991 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10595 13:58:01.541648 <30>[ 20.477504] systemd[1]: Listening on Network Service Netlink Socket.
10596 13:58:01.548244 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10597 13:58:01.563894 <30>[ 20.502914] systemd[1]: Listening on udev Control Socket.
10598 13:58:01.570309 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10599 13:58:01.585198 <30>[ 20.524547] systemd[1]: Listening on udev Kernel Socket.
10600 13:58:01.592248 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10601 13:58:01.649656 <30>[ 20.588249] systemd[1]: Mounting Huge Pages File System...
10602 13:58:01.655464 Mounting [0;1;39mHuge Pages File System[0m...
10603 13:58:01.673744 <30>[ 20.612607] systemd[1]: Mounting POSIX Message Queue File System...
10604 13:58:01.679906 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10605 13:58:01.701337 <30>[ 20.640455] systemd[1]: Mounting Kernel Debug File System...
10606 13:58:01.708138 Mounting [0;1;39mKernel Debug File System[0m...
10607 13:58:01.724624 <30>[ 20.660701] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10608 13:58:01.740767 <30>[ 20.676802] systemd[1]: Starting Create list of static device nodes for the current kernel...
10609 13:58:01.747564 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10610 13:58:01.769781 <30>[ 20.709008] systemd[1]: Starting Load Kernel Module configfs...
10611 13:58:01.776332 Starting [0;1;39mLoad Kernel Module configfs[0m...
10612 13:58:01.797481 <30>[ 20.736731] systemd[1]: Starting Load Kernel Module drm...
10613 13:58:01.804628 Starting [0;1;39mLoad Kernel Module drm[0m...
10614 13:58:01.821696 <30>[ 20.760790] systemd[1]: Starting Load Kernel Module fuse...
10615 13:58:01.828279 Starting [0;1;39mLoad Kernel Module fuse[0m...
10616 13:58:01.855499 <6>[ 20.794749] fuse: init (API version 7.37)
10617 13:58:01.865116 <30>[ 20.796263] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10618 13:58:01.877754 <30>[ 20.817087] systemd[1]: Starting Journal Service...
10619 13:58:01.884406 Starting [0;1;39mJournal Service[0m...
10620 13:58:01.907133 <30>[ 20.846366] systemd[1]: Starting Load Kernel Modules...
10621 13:58:01.914339 Starting [0;1;39mLoad Kernel Modules[0m...
10622 13:58:01.937058 <30>[ 20.872784] systemd[1]: Starting Remount Root and Kernel File Systems...
10623 13:58:01.942995 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10624 13:58:01.960868 <30>[ 20.899716] systemd[1]: Starting Coldplug All udev Devices...
10625 13:58:01.967384 Starting [0;1;39mColdplug All udev Devices[0m...
10626 13:58:01.989729 <3>[ 20.925613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 13:58:01.996606 <30>[ 20.928286] systemd[1]: Mounted Huge Pages File System.
10628 13:58:02.002549 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10629 13:58:02.018416 <30>[ 20.956818] systemd[1]: Mounted POSIX Message Queue File System.
10630 13:58:02.028340 <3>[ 20.958998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 13:58:02.035541 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10632 13:58:02.049400 <30>[ 20.988514] systemd[1]: Mounted Kernel Debug File System.
10633 13:58:02.056208 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10634 13:58:02.066627 <3>[ 21.002889] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10635 13:58:02.077926 <30>[ 21.014045] systemd[1]: Finished Create list of static device nodes for the current kernel.
10636 13:58:02.085417 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10637 13:58:02.096179 <3>[ 21.031879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10638 13:58:02.107054 <30>[ 21.045933] systemd[1]: modprobe@configfs.service: Succeeded.
10639 13:58:02.113423 <30>[ 21.052719] systemd[1]: Finished Load Kernel Module configfs.
10640 13:58:02.121022 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10641 13:58:02.131066 <3>[ 21.066566] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10642 13:58:02.138026 <30>[ 21.077325] systemd[1]: modprobe@drm.service: Succeeded.
10643 13:58:02.144845 <30>[ 21.083905] systemd[1]: Finished Load Kernel Module drm.
10644 13:58:02.151341 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10645 13:58:02.166393 <3>[ 21.101914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10646 13:58:02.174573 <30>[ 21.113289] systemd[1]: modprobe@fuse.service: Succeeded.
10647 13:58:02.181176 <30>[ 21.119755] systemd[1]: Finished Load Kernel Module fuse.
10648 13:58:02.188376 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10649 13:58:02.198589 <3>[ 21.134539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10650 13:58:02.206549 <30>[ 21.145242] systemd[1]: Finished Load Kernel Modules.
10651 13:58:02.212753 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10652 13:58:02.227945 <3>[ 21.163459] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10653 13:58:02.238132 <30>[ 21.174049] systemd[1]: Finished Remount Root and Kernel File Systems.
10654 13:58:02.244702 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10655 13:58:02.257203 <3>[ 21.192849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 13:58:02.288738 <3>[ 21.224427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10657 13:58:02.303260 <30>[ 21.242457] systemd[1]: Mounting FUSE Control File System...
10658 13:58:02.310010 Mounting [0;1;39mFUSE Control File System[0m...
10659 13:58:02.329362 <30>[ 21.268183] systemd[1]: Mounting Kernel Configuration File System...
10660 13:58:02.335969 Mounting [0;1;39mKernel Configuration File System[0m...
10661 13:58:02.360324 <30>[ 21.296350] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10662 13:58:02.370379 <30>[ 21.305509] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10663 13:58:02.409309 <30>[ 21.348642] systemd[1]: Starting Load/Save Random Seed...
10664 13:58:02.416152 Starting [0;1;39mLoad/Save Random Seed[0m...
10665 13:58:02.432667 <4>[ 21.361200] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10666 13:58:02.439999 <3>[ 21.376867] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10667 13:58:02.446134 <30>[ 21.380941] systemd[1]: Starting Apply Kernel Variables...
10668 13:58:02.452585 Starting [0;1;39mApply Kernel Variables[0m...
10669 13:58:02.469622 <30>[ 21.408838] systemd[1]: Starting Create System Users...
10670 13:58:02.476030 Starting [0;1;39mCreate System Users[0m...
10671 13:58:02.492930 <30>[ 21.431535] systemd[1]: Started Journal Service.
10672 13:58:02.498609 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10673 13:58:02.521990 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10674 13:58:02.536635 See 'systemctl status systemd-udev-trigger.service' for details.
10675 13:58:02.554037 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10676 13:58:02.569234 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10677 13:58:02.587036 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10678 13:58:02.602529 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10679 13:58:02.618594 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10680 13:58:02.660885 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10681 13:58:02.679445 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10682 13:58:02.708136 <46>[ 21.644442] systemd-journald[291]: Received client request to flush runtime journal.
10683 13:58:02.736949 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10684 13:58:02.753912 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10685 13:58:02.773147 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10686 13:58:02.833041 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10687 13:58:04.092408 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10688 13:58:04.158572 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10689 13:58:04.177693 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10690 13:58:04.213424 Starting [0;1;39mNetwork Service[0m...
10691 13:58:04.519861 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10692 13:58:04.541482 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10693 13:58:04.593114 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10694 13:58:04.870270 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10695 13:58:04.887968 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10696 13:58:04.918106 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10697 13:58:04.938819 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10698 13:58:04.968805 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10699 13:58:05.004824 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10700 13:58:05.021012 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10701 13:58:05.077944 Starting [0;1;39mNetwork Name Resolution[0m...
10702 13:58:05.104095 Starting [0;1;39mNetwork Time Synchronization[0m...
10703 13:58:05.124715 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10704 13:58:05.175726 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10705 13:58:05.302526 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10706 13:58:05.320874 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10707 13:58:05.339944 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10708 13:58:05.356614 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10709 13:58:05.376888 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10710 13:58:05.489933 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10711 13:58:05.526277 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10712 13:58:05.555022 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10713 13:58:05.579932 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10714 13:58:05.592404 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10715 13:58:05.615685 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10716 13:58:05.628306 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10717 13:58:05.644574 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10718 13:58:05.685474 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10719 13:58:05.776618 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10720 13:58:05.845850 Starting [0;1;39mUser Login Management[0m...
10721 13:58:05.862696 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10722 13:58:05.885153 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10723 13:58:05.904467 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10724 13:58:05.948838 Starting [0;1;39mPermit User Sessions[0m...
10725 13:58:06.038643 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10726 13:58:06.093659 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10727 13:58:06.150639 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10728 13:58:06.169268 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10729 13:58:06.193178 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10730 13:58:06.212677 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10731 13:58:06.231262 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10732 13:58:06.248384 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10733 13:58:06.308766 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10734 13:58:06.354357 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10735 13:58:06.433921
10736 13:58:06.434035
10737 13:58:06.437216 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10738 13:58:06.437299
10739 13:58:06.440295 debian-bullseye-arm64 login: root (automatic login)
10740 13:58:06.440377
10741 13:58:06.440442
10742 13:58:06.751079 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
10743 13:58:06.751215
10744 13:58:06.757181 The programs included with the Debian GNU/Linux system are free software;
10745 13:58:06.764142 the exact distribution terms for each program are described in the
10746 13:58:06.768981 individual files in /usr/share/doc/*/copyright.
10747 13:58:06.769065
10748 13:58:06.774261 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10749 13:58:06.777695 permitted by applicable law.
10750 13:58:07.527873 Matched prompt #10: / #
10752 13:58:07.528141 Setting prompt string to ['/ #']
10753 13:58:07.528236 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10755 13:58:07.528449 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10756 13:58:07.528549 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
10757 13:58:07.528634 Setting prompt string to ['/ #']
10758 13:58:07.528742 Forcing a shell prompt, looking for ['/ #']
10760 13:58:07.578964 / #
10761 13:58:07.579085 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10762 13:58:07.579162 Waiting using forced prompt support (timeout 00:02:30)
10763 13:58:07.584674
10764 13:58:07.584984 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10765 13:58:07.585083 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
10767 13:58:07.685398 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682951/extract-nfsrootfs-0eemlskl'
10768 13:58:07.691000 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682951/extract-nfsrootfs-0eemlskl'
10770 13:58:07.791582 / # export NFS_SERVER_IP='192.168.201.1'
10771 13:58:07.796743 export NFS_SERVER_IP='192.168.201.1'
10772 13:58:07.797026 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10773 13:58:07.797132 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
10774 13:58:07.797223 end: 2 depthcharge-action (duration 00:01:22) [common]
10775 13:58:07.797316 start: 3 lava-test-retry (timeout 00:07:54) [common]
10776 13:58:07.797405 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
10777 13:58:07.797480 Using namespace: common
10779 13:58:07.897807 / # #
10780 13:58:07.897931 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10781 13:58:07.902923 #
10782 13:58:07.903187 Using /lava-12682951
10784 13:58:08.003514 / # export SHELL=/bin/bash
10785 13:58:08.008475 export SHELL=/bin/bash
10787 13:58:08.108985 / # . /lava-12682951/environment
10788 13:58:08.114440 . /lava-12682951/environment
10790 13:58:08.220166 / # /lava-12682951/bin/lava-test-runner /lava-12682951/0
10791 13:58:08.220307 Test shell timeout: 10s (minimum of the action and connection timeout)
10792 13:58:08.225698 /lava-12682951/bin/lava-test-runner /lava-12682951/0
10793 13:58:08.458328 + export TESTRUN_ID=0_timesync-off
10794 13:58:08.461938 + TESTRUN_ID=0_timesync-off
10795 13:58:08.464391 + cd /lava-12682951/0/tests/0_timesync-off
10796 13:58:08.467718 ++ cat uuid
10797 13:58:08.467802 + UUID=12682951_1.6.2.3.1
10798 13:58:08.470621 + set +x
10799 13:58:08.473845 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12682951_1.6.2.3.1>
10800 13:58:08.474108 Received signal: <STARTRUN> 0_timesync-off 12682951_1.6.2.3.1
10801 13:58:08.474183 Starting test lava.0_timesync-off (12682951_1.6.2.3.1)
10802 13:58:08.474272 Skipping test definition patterns.
10803 13:58:08.477848 + systemctl stop systemd-timesyncd
10804 13:58:08.526021 + set +x
10805 13:58:08.528995 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12682951_1.6.2.3.1>
10806 13:58:08.529252 Received signal: <ENDRUN> 0_timesync-off 12682951_1.6.2.3.1
10807 13:58:08.529340 Ending use of test pattern.
10808 13:58:08.529403 Ending test lava.0_timesync-off (12682951_1.6.2.3.1), duration 0.06
10810 13:58:08.585572 + export TESTRUN_ID=1_kselftest-rtc
10811 13:58:08.589021 + TESTRUN_ID=1_kselftest-rtc
10812 13:58:08.592460 + cd /lava-12682951/0/tests/1_kselftest-rtc
10813 13:58:08.597497 ++ cat uuid
10814 13:58:08.597581 + UUID=12682951_1.6.2.3.5
10815 13:58:08.599531 + set +x
10816 13:58:08.602156 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12682951_1.6.2.3.5>
10817 13:58:08.602412 Received signal: <STARTRUN> 1_kselftest-rtc 12682951_1.6.2.3.5
10818 13:58:08.602483 Starting test lava.1_kselftest-rtc (12682951_1.6.2.3.5)
10819 13:58:08.602562 Skipping test definition patterns.
10820 13:58:08.605362 + cd ./automated/linux/kselftest/
10821 13:58:08.632251 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10822 13:58:08.656862 INFO: install_deps skipped
10823 13:58:08.770132 --2024-02-01 13:58:08-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10824 13:58:08.783565 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10825 13:58:08.916614 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10826 13:58:09.050038 HTTP request sent, awaiting response... 200 OK
10827 13:58:09.053675 Length: 2966796 (2.8M) [application/octet-stream]
10828 13:58:09.056425 Saving to: 'kselftest.tar.xz'
10829 13:58:09.056507
10830 13:58:09.056573
10831 13:58:09.316943 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10832 13:58:09.586199 kselftest.tar.xz 1%[ ] 46.39K 172KB/s
10833 13:58:09.986483 kselftest.tar.xz 7%[> ] 217.50K 401KB/s
10834 13:58:10.260921 kselftest.tar.xz 30%[=====> ] 877.86K 924KB/s
10835 13:58:10.284466 kselftest.tar.xz 72%[=============> ] 2.06M 1.68MB/s
10836 13:58:10.290623 kselftest.tar.xz 100%[===================>] 2.83M 2.26MB/s in 1.3s
10837 13:58:10.290708
10838 13:58:10.547457 2024-02-01 13:58:10 (2.26 MB/s) - 'kselftest.tar.xz' saved [2966796/2966796]
10839 13:58:10.547614
10840 13:58:15.875234 skiplist:
10841 13:58:15.878310 ========================================
10842 13:58:15.882101 ========================================
10843 13:58:15.917882 rtc:rtctest
10844 13:58:15.936762 ============== Tests to run ===============
10845 13:58:15.937226 rtc:rtctest
10846 13:58:15.939822 ===========End Tests to run ===============
10847 13:58:15.945109 shardfile-rtc pass
10848 13:58:16.047409 <12>[ 34.987930] kselftest: Running tests in rtc
10849 13:58:16.056959 TAP version 13
10850 13:58:16.070171 1..1
10851 13:58:16.103693 # selftests: rtc: rtctest
10852 13:58:16.555163 # TAP version 13
10853 13:58:16.555744 # 1..8
10854 13:58:16.559222 # # Starting 8 tests from 2 test cases.
10855 13:58:16.562031 # # RUN rtc.date_read ...
10856 13:58:16.568784 # # rtctest.c:49:date_read:Current RTC date/time is 01/02/2024 13:58:15.
10857 13:58:16.572263 # # OK rtc.date_read
10858 13:58:16.575077 # ok 1 rtc.date_read
10859 13:58:16.578781 # # RUN rtc.date_read_loop ...
10860 13:58:16.588829 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
10861 13:58:27.034044 <6>[ 45.977937] vpu: disabling
10862 13:58:27.036096 <6>[ 45.981339] vproc2: disabling
10863 13:58:27.040106 <6>[ 45.984736] vproc1: disabling
10864 13:58:27.043016 <6>[ 45.988344] vaud18: disabling
10865 13:58:27.049677 <6>[ 45.991873] vsram_others: disabling
10866 13:58:27.053443 <6>[ 45.995834] va09: disabling
10867 13:58:27.056769 <6>[ 45.999004] vsram_md: disabling
10868 13:58:27.060069 <6>[ 46.002900] Vgpu: disabling
10869 13:58:46.183405 # # rtctest.c:115:date_read_loop:Performed 2608 RTC time reads.
10870 13:58:46.187258 # # OK rtc.date_read_loop
10871 13:58:46.190072 # ok 2 rtc.date_read_loop
10872 13:58:46.192893 # # RUN rtc.uie_read ...
10873 13:58:49.168746 # # OK rtc.uie_read
10874 13:58:49.172116 # ok 3 rtc.uie_read
10875 13:58:49.175292 # # RUN rtc.uie_select ...
10876 13:58:52.168394 # # OK rtc.uie_select
10877 13:58:52.171175 # ok 4 rtc.uie_select
10878 13:58:52.176029 # # RUN rtc.alarm_alm_set ...
10879 13:58:52.180948 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 13:58:55.
10880 13:58:52.184837 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
10881 13:58:52.191972 # # alarm_alm_set: Test terminated by assertion
10882 13:58:52.194520 # # FAIL rtc.alarm_alm_set
10883 13:58:52.195077 # not ok 5 rtc.alarm_alm_set
10884 13:58:52.202008 # # RUN rtc.alarm_wkalm_set ...
10885 13:58:52.207452 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 01/02/2024 13:58:55.
10886 13:58:55.170351 # # OK rtc.alarm_wkalm_set
10887 13:58:55.170906 # ok 6 rtc.alarm_wkalm_set
10888 13:58:55.177909 # # RUN rtc.alarm_alm_set_minute ...
10889 13:58:55.180746 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 13:59:00.
10890 13:58:55.187280 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
10891 13:58:55.193558 # # alarm_alm_set_minute: Test terminated by assertion
10892 13:58:55.197449 # # FAIL rtc.alarm_alm_set_minute
10893 13:58:55.200797 # not ok 7 rtc.alarm_alm_set_minute
10894 13:58:55.203722 # # RUN rtc.alarm_wkalm_set_minute ...
10895 13:58:55.210806 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 01/02/2024 13:59:00.
10896 13:59:00.170570 # # OK rtc.alarm_wkalm_set_minute
10897 13:59:00.173061 # ok 8 rtc.alarm_wkalm_set_minute
10898 13:59:00.176703 # # FAILED: 6 / 8 tests passed.
10899 13:59:00.179645 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
10900 13:59:00.183619 not ok 1 selftests: rtc: rtctest # exit=1
10901 13:59:00.803564 rtc_rtctest_rtc_date_read pass
10902 13:59:00.807823 rtc_rtctest_rtc_date_read_loop pass
10903 13:59:00.810022 rtc_rtctest_rtc_uie_read pass
10904 13:59:00.813093 rtc_rtctest_rtc_uie_select pass
10905 13:59:00.816601 rtc_rtctest_rtc_alarm_alm_set fail
10906 13:59:00.819776 rtc_rtctest_rtc_alarm_wkalm_set pass
10907 13:59:00.822803 rtc_rtctest_rtc_alarm_alm_set_minute fail
10908 13:59:00.826111 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
10909 13:59:00.829581 rtc_rtctest fail
10910 13:59:00.837038 + ../../utils/send-to-lava.sh ./output/result.txt
10911 13:59:00.921012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
10912 13:59:00.921821 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
10914 13:59:00.967074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
10915 13:59:00.967341 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
10917 13:59:01.020440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
10918 13:59:01.020787 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
10920 13:59:01.064443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
10921 13:59:01.065301 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
10923 13:59:01.120214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
10924 13:59:01.120931 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
10926 13:59:01.183634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
10927 13:59:01.184499 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
10929 13:59:01.236861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
10930 13:59:01.237593 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
10932 13:59:01.298520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
10933 13:59:01.299315 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
10935 13:59:01.355742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
10936 13:59:01.356528 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
10938 13:59:01.406317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
10939 13:59:01.406754 + set +x
10940 13:59:01.407342 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
10942 13:59:01.413061 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12682951_1.6.2.3.5>
10943 13:59:01.413849 Received signal: <ENDRUN> 1_kselftest-rtc 12682951_1.6.2.3.5
10944 13:59:01.414216 Ending use of test pattern.
10945 13:59:01.414528 Ending test lava.1_kselftest-rtc (12682951_1.6.2.3.5), duration 52.81
10947 13:59:01.415660 ok: lava_test_shell seems to have completed
10948 13:59:01.416322 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
10949 13:59:01.416780 end: 3.1 lava-test-shell (duration 00:00:54) [common]
10950 13:59:01.417209 end: 3 lava-test-retry (duration 00:00:54) [common]
10951 13:59:01.417629 start: 4 finalize (timeout 00:07:00) [common]
10952 13:59:01.418082 start: 4.1 power-off (timeout 00:00:30) [common]
10953 13:59:01.418876 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10954 13:59:01.510335 >> Command sent successfully.
10955 13:59:01.515618 Returned 0 in 0 seconds
10956 13:59:01.616673 end: 4.1 power-off (duration 00:00:00) [common]
10958 13:59:01.618658 start: 4.2 read-feedback (timeout 00:07:00) [common]
10960 13:59:01.621201 Listened to connection for namespace 'common' for up to 1s
10961 13:59:02.620661 Finalising connection for namespace 'common'
10962 13:59:02.621393 Disconnecting from shell: Finalise
10963 13:59:02.621811 / #
10964 13:59:02.722839 end: 4.2 read-feedback (duration 00:00:01) [common]
10965 13:59:02.723556 end: 4 finalize (duration 00:00:01) [common]
10966 13:59:02.724159 Cleaning after the job
10967 13:59:02.724885 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/ramdisk
10968 13:59:02.738814 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/kernel
10969 13:59:02.776083 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/dtb
10970 13:59:02.776469 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/nfsrootfs
10971 13:59:02.881896 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682951/tftp-deploy-j9f43ni9/modules
10972 13:59:02.889532 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682951
10973 13:59:03.523389 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682951
10974 13:59:03.523572 Job finished correctly