Boot log: mt8192-asurada-spherion-r0

    1 13:53:09.394787  lava-dispatcher, installed at version: 2023.10
    2 13:53:09.395041  start: 0 validate
    3 13:53:09.395209  Start time: 2024-02-01 13:53:09.395201+00:00 (UTC)
    4 13:53:09.395367  Using caching service: 'http://localhost/cache/?uri=%s'
    5 13:53:09.395552  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
    6 13:53:09.663699  Using caching service: 'http://localhost/cache/?uri=%s'
    7 13:53:09.663872  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 13:53:27.934502  Using caching service: 'http://localhost/cache/?uri=%s'
    9 13:53:27.934684  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 13:53:28.193114  Using caching service: 'http://localhost/cache/?uri=%s'
   11 13:53:28.193325  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 13:53:28.715701  Using caching service: 'http://localhost/cache/?uri=%s'
   13 13:53:28.716396  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   14 13:53:31.224756  validate duration: 21.83
   16 13:53:31.225008  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 13:53:31.225106  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 13:53:31.225193  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 13:53:31.225305  Not decompressing ramdisk as can be used compressed.
   20 13:53:31.225388  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
   21 13:53:31.225453  saving as /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/ramdisk/initrd.cpio.gz
   22 13:53:31.225519  total size: 4665395 (4 MB)
   23 13:53:31.491530  progress   0 % (0 MB)
   24 13:53:31.493068  progress   5 % (0 MB)
   25 13:53:31.494353  progress  10 % (0 MB)
   26 13:53:31.495574  progress  15 % (0 MB)
   27 13:53:31.496825  progress  20 % (0 MB)
   28 13:53:31.498104  progress  25 % (1 MB)
   29 13:53:31.499336  progress  30 % (1 MB)
   30 13:53:31.500545  progress  35 % (1 MB)
   31 13:53:31.501760  progress  40 % (1 MB)
   32 13:53:31.503159  progress  45 % (2 MB)
   33 13:53:31.504415  progress  50 % (2 MB)
   34 13:53:31.505608  progress  55 % (2 MB)
   35 13:53:31.506843  progress  60 % (2 MB)
   36 13:53:31.508032  progress  65 % (2 MB)
   37 13:53:31.509222  progress  70 % (3 MB)
   38 13:53:31.510462  progress  75 % (3 MB)
   39 13:53:31.511696  progress  80 % (3 MB)
   40 13:53:31.513097  progress  85 % (3 MB)
   41 13:53:31.514361  progress  90 % (4 MB)
   42 13:53:31.515558  progress  95 % (4 MB)
   43 13:53:31.516774  progress 100 % (4 MB)
   44 13:53:31.516927  4 MB downloaded in 0.29 s (15.27 MB/s)
   45 13:53:31.517078  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 13:53:31.517315  end: 1.1 download-retry (duration 00:00:00) [common]
   48 13:53:31.517401  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 13:53:31.517484  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 13:53:31.517611  downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   51 13:53:31.517681  saving as /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/kernel/Image
   52 13:53:31.517742  total size: 51532288 (49 MB)
   53 13:53:31.517803  No compression specified
   54 13:53:31.519094  progress   0 % (0 MB)
   55 13:53:31.532486  progress   5 % (2 MB)
   56 13:53:31.545667  progress  10 % (4 MB)
   57 13:53:31.558615  progress  15 % (7 MB)
   58 13:53:31.571859  progress  20 % (9 MB)
   59 13:53:31.585274  progress  25 % (12 MB)
   60 13:53:31.598464  progress  30 % (14 MB)
   61 13:53:31.611651  progress  35 % (17 MB)
   62 13:53:31.624909  progress  40 % (19 MB)
   63 13:53:31.638069  progress  45 % (22 MB)
   64 13:53:31.651242  progress  50 % (24 MB)
   65 13:53:31.664235  progress  55 % (27 MB)
   66 13:53:31.677367  progress  60 % (29 MB)
   67 13:53:31.690732  progress  65 % (31 MB)
   68 13:53:31.703960  progress  70 % (34 MB)
   69 13:53:31.717023  progress  75 % (36 MB)
   70 13:53:31.730641  progress  80 % (39 MB)
   71 13:53:31.743588  progress  85 % (41 MB)
   72 13:53:31.756422  progress  90 % (44 MB)
   73 13:53:31.769117  progress  95 % (46 MB)
   74 13:53:31.781681  progress 100 % (49 MB)
   75 13:53:31.781907  49 MB downloaded in 0.26 s (186.04 MB/s)
   76 13:53:31.782088  end: 1.2.1 http-download (duration 00:00:00) [common]
   78 13:53:31.782322  end: 1.2 download-retry (duration 00:00:00) [common]
   79 13:53:31.782414  start: 1.3 download-retry (timeout 00:09:59) [common]
   80 13:53:31.782498  start: 1.3.1 http-download (timeout 00:09:59) [common]
   81 13:53:31.782627  downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   82 13:53:31.782696  saving as /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/dtb/mt8192-asurada-spherion-r0.dtb
   83 13:53:31.782757  total size: 47278 (0 MB)
   84 13:53:31.782819  No compression specified
   85 13:53:31.784159  progress  69 % (0 MB)
   86 13:53:31.784458  progress 100 % (0 MB)
   87 13:53:31.784641  0 MB downloaded in 0.00 s (23.97 MB/s)
   88 13:53:31.784811  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 13:53:31.785168  end: 1.3 download-retry (duration 00:00:00) [common]
   91 13:53:31.785287  start: 1.4 download-retry (timeout 00:09:59) [common]
   92 13:53:31.785402  start: 1.4.1 http-download (timeout 00:09:59) [common]
   93 13:53:31.785546  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
   94 13:53:31.785640  saving as /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/nfsrootfs/full.rootfs.tar
   95 13:53:31.785720  total size: 200813988 (191 MB)
   96 13:53:31.785783  Using unxz to decompress xz
   97 13:53:31.789398  progress   0 % (0 MB)
   98 13:53:32.313639  progress   5 % (9 MB)
   99 13:53:32.825181  progress  10 % (19 MB)
  100 13:53:33.404793  progress  15 % (28 MB)
  101 13:53:33.775557  progress  20 % (38 MB)
  102 13:53:34.100020  progress  25 % (47 MB)
  103 13:53:34.682619  progress  30 % (57 MB)
  104 13:53:35.222359  progress  35 % (67 MB)
  105 13:53:35.807799  progress  40 % (76 MB)
  106 13:53:36.369821  progress  45 % (86 MB)
  107 13:53:36.957803  progress  50 % (95 MB)
  108 13:53:37.592848  progress  55 % (105 MB)
  109 13:53:38.258046  progress  60 % (114 MB)
  110 13:53:38.378062  progress  65 % (124 MB)
  111 13:53:38.517371  progress  70 % (134 MB)
  112 13:53:38.613937  progress  75 % (143 MB)
  113 13:53:38.685294  progress  80 % (153 MB)
  114 13:53:38.753795  progress  85 % (162 MB)
  115 13:53:38.854663  progress  90 % (172 MB)
  116 13:53:39.144524  progress  95 % (181 MB)
  117 13:53:39.734357  progress 100 % (191 MB)
  118 13:53:39.739734  191 MB downloaded in 7.95 s (24.08 MB/s)
  119 13:53:39.740028  end: 1.4.1 http-download (duration 00:00:08) [common]
  121 13:53:39.740294  end: 1.4 download-retry (duration 00:00:08) [common]
  122 13:53:39.740386  start: 1.5 download-retry (timeout 00:09:51) [common]
  123 13:53:39.740475  start: 1.5.1 http-download (timeout 00:09:51) [common]
  124 13:53:39.740636  downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
  125 13:53:39.740711  saving as /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/modules/modules.tar
  126 13:53:39.740774  total size: 8623988 (8 MB)
  127 13:53:39.740839  Using unxz to decompress xz
  128 13:53:40.001507  progress   0 % (0 MB)
  129 13:53:40.022545  progress   5 % (0 MB)
  130 13:53:40.046221  progress  10 % (0 MB)
  131 13:53:40.070054  progress  15 % (1 MB)
  132 13:53:40.094548  progress  20 % (1 MB)
  133 13:53:40.119022  progress  25 % (2 MB)
  134 13:53:40.144936  progress  30 % (2 MB)
  135 13:53:40.171416  progress  35 % (2 MB)
  136 13:53:40.195153  progress  40 % (3 MB)
  137 13:53:40.219851  progress  45 % (3 MB)
  138 13:53:40.245340  progress  50 % (4 MB)
  139 13:53:40.269917  progress  55 % (4 MB)
  140 13:53:40.295118  progress  60 % (4 MB)
  141 13:53:40.323088  progress  65 % (5 MB)
  142 13:53:40.348450  progress  70 % (5 MB)
  143 13:53:40.372358  progress  75 % (6 MB)
  144 13:53:40.399580  progress  80 % (6 MB)
  145 13:53:40.427776  progress  85 % (7 MB)
  146 13:53:40.453092  progress  90 % (7 MB)
  147 13:53:40.484799  progress  95 % (7 MB)
  148 13:53:40.512839  progress 100 % (8 MB)
  149 13:53:40.518034  8 MB downloaded in 0.78 s (10.58 MB/s)
  150 13:53:40.518413  end: 1.5.1 http-download (duration 00:00:01) [common]
  152 13:53:40.518803  end: 1.5 download-retry (duration 00:00:01) [common]
  153 13:53:40.518934  start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
  154 13:53:40.519071  start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
  155 13:53:43.750890  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12682923/extract-nfsrootfs-dxzindgm
  156 13:53:43.751103  end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
  157 13:53:43.751208  start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
  158 13:53:43.751377  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5
  159 13:53:43.751504  makedir: /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin
  160 13:53:43.751606  makedir: /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/tests
  161 13:53:43.751702  makedir: /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/results
  162 13:53:43.751805  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-add-keys
  163 13:53:43.751945  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-add-sources
  164 13:53:43.752069  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-background-process-start
  165 13:53:43.752190  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-background-process-stop
  166 13:53:43.752312  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-common-functions
  167 13:53:43.752431  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-echo-ipv4
  168 13:53:43.752549  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-install-packages
  169 13:53:43.752666  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-installed-packages
  170 13:53:43.752782  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-os-build
  171 13:53:43.752900  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-probe-channel
  172 13:53:43.753018  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-probe-ip
  173 13:53:43.753135  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-target-ip
  174 13:53:43.753255  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-target-mac
  175 13:53:43.753372  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-target-storage
  176 13:53:43.753491  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-test-case
  177 13:53:43.753610  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-test-event
  178 13:53:43.753728  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-test-feedback
  179 13:53:43.753846  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-test-raise
  180 13:53:43.753995  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-test-reference
  181 13:53:43.754130  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-test-runner
  182 13:53:43.754249  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-test-set
  183 13:53:43.754367  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-test-shell
  184 13:53:43.754487  Updating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-add-keys (debian)
  185 13:53:43.754634  Updating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-add-sources (debian)
  186 13:53:43.754768  Updating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-install-packages (debian)
  187 13:53:43.754901  Updating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-installed-packages (debian)
  188 13:53:43.755032  Updating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/bin/lava-os-build (debian)
  189 13:53:43.755146  Creating /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/environment
  190 13:53:43.755247  LAVA metadata
  191 13:53:43.755317  - LAVA_JOB_ID=12682923
  192 13:53:43.755384  - LAVA_DISPATCHER_IP=192.168.201.1
  193 13:53:43.755485  start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
  194 13:53:43.755549  skipped lava-vland-overlay
  195 13:53:43.755622  end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
  196 13:53:43.755701  start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
  197 13:53:43.755760  skipped lava-multinode-overlay
  198 13:53:43.755831  end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  199 13:53:43.755908  start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
  200 13:53:43.755980  Loading test definitions
  201 13:53:43.756067  start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
  202 13:53:43.756137  Using /lava-12682923 at stage 0
  203 13:53:43.756407  uuid=12682923_1.6.2.3.1 testdef=None
  204 13:53:43.756494  end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
  205 13:53:43.756578  start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
  206 13:53:43.757012  end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
  208 13:53:43.757234  start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
  209 13:53:43.757775  end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
  211 13:53:43.758635  start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
  212 13:53:43.759167  runner path: /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/0/tests/0_timesync-off test_uuid 12682923_1.6.2.3.1
  213 13:53:43.759320  end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  215 13:53:43.759544  start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
  216 13:53:43.759616  Using /lava-12682923 at stage 0
  217 13:53:43.759712  Fetching tests from https://github.com/kernelci/test-definitions.git
  218 13:53:43.759791  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/0/tests/1_kselftest-tpm2'
  219 13:53:47.420633  Running '/usr/bin/git checkout kernelci.org
  220 13:53:47.563748  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
  221 13:53:47.564477  uuid=12682923_1.6.2.3.5 testdef=None
  222 13:53:47.564642  end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
  224 13:53:47.564923  start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
  225 13:53:47.565679  end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
  227 13:53:47.565975  start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
  228 13:53:47.566974  end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
  230 13:53:47.567241  start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
  231 13:53:47.568831  runner path: /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/0/tests/1_kselftest-tpm2 test_uuid 12682923_1.6.2.3.5
  232 13:53:47.568957  BOARD='mt8192-asurada-spherion-r0'
  233 13:53:47.569037  BRANCH='cip'
  234 13:53:47.569119  SKIPFILE='/dev/null'
  235 13:53:47.569219  SKIP_INSTALL='True'
  236 13:53:47.569317  TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
  237 13:53:47.569417  TST_CASENAME=''
  238 13:53:47.569514  TST_CMDFILES='tpm2'
  239 13:53:47.569713  end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
  241 13:53:47.570081  Creating lava-test-runner.conf files
  242 13:53:47.570186  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682923/lava-overlay-iw1ka6k5/lava-12682923/0 for stage 0
  243 13:53:47.570323  - 0_timesync-off
  244 13:53:47.570427  - 1_kselftest-tpm2
  245 13:53:47.570569  end: 1.6.2.3 test-definition (duration 00:00:04) [common]
  246 13:53:47.570699  start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
  247 13:53:55.060218  end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
  248 13:53:55.060369  start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
  249 13:53:55.060462  end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  250 13:53:55.060561  end: 1.6.2 lava-overlay (duration 00:00:11) [common]
  251 13:53:55.060653  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
  252 13:53:55.174667  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  253 13:53:55.175022  start: 1.6.4 extract-modules (timeout 00:09:36) [common]
  254 13:53:55.175138  extracting modules file /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682923/extract-nfsrootfs-dxzindgm
  255 13:53:55.379323  extracting modules file /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682923/extract-overlay-ramdisk-24yupgfs/ramdisk
  256 13:53:55.585923  end: 1.6.4 extract-modules (duration 00:00:00) [common]
  257 13:53:55.586097  start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
  258 13:53:55.586197  [common] Applying overlay to NFS
  259 13:53:55.586270  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682923/compress-overlay-f55thk50/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682923/extract-nfsrootfs-dxzindgm
  260 13:53:56.487239  end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
  261 13:53:56.487412  start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
  262 13:53:56.487506  end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
  263 13:53:56.487597  start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
  264 13:53:56.487683  Building ramdisk /var/lib/lava/dispatcher/tmp/12682923/extract-overlay-ramdisk-24yupgfs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682923/extract-overlay-ramdisk-24yupgfs/ramdisk
  265 13:53:56.788180  >> 119414 blocks

  266 13:53:58.720825  rename /var/lib/lava/dispatcher/tmp/12682923/extract-overlay-ramdisk-24yupgfs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/ramdisk/ramdisk.cpio.gz
  267 13:53:58.721250  end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
  268 13:53:58.721368  start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
  269 13:53:58.721469  start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
  270 13:53:58.721576  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/kernel/Image'
  271 13:54:11.305321  Returned 0 in 12 seconds
  272 13:54:11.405924  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/kernel/image.itb
  273 13:54:11.745366  output: FIT description: Kernel Image image with one or more FDT blobs
  274 13:54:11.745714  output: Created:         Thu Feb  1 13:54:11 2024
  275 13:54:11.745820  output:  Image 0 (kernel-1)
  276 13:54:11.745915  output:   Description:  
  277 13:54:11.746025  output:   Created:      Thu Feb  1 13:54:11 2024
  278 13:54:11.746090  output:   Type:         Kernel Image
  279 13:54:11.746152  output:   Compression:  lzma compressed
  280 13:54:11.746214  output:   Data Size:    12046857 Bytes = 11764.51 KiB = 11.49 MiB
  281 13:54:11.746274  output:   Architecture: AArch64
  282 13:54:11.746333  output:   OS:           Linux
  283 13:54:11.746394  output:   Load Address: 0x00000000
  284 13:54:11.746451  output:   Entry Point:  0x00000000
  285 13:54:11.746508  output:   Hash algo:    crc32
  286 13:54:11.746567  output:   Hash value:   5aa40db2
  287 13:54:11.746626  output:  Image 1 (fdt-1)
  288 13:54:11.746683  output:   Description:  mt8192-asurada-spherion-r0
  289 13:54:11.746736  output:   Created:      Thu Feb  1 13:54:11 2024
  290 13:54:11.746791  output:   Type:         Flat Device Tree
  291 13:54:11.746845  output:   Compression:  uncompressed
  292 13:54:11.746899  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  293 13:54:11.746953  output:   Architecture: AArch64
  294 13:54:11.747006  output:   Hash algo:    crc32
  295 13:54:11.747060  output:   Hash value:   cc4352de
  296 13:54:11.747114  output:  Image 2 (ramdisk-1)
  297 13:54:11.747168  output:   Description:  unavailable
  298 13:54:11.747222  output:   Created:      Thu Feb  1 13:54:11 2024
  299 13:54:11.747276  output:   Type:         RAMDisk Image
  300 13:54:11.747329  output:   Compression:  Unknown Compression
  301 13:54:11.747383  output:   Data Size:    17805982 Bytes = 17388.65 KiB = 16.98 MiB
  302 13:54:11.747436  output:   Architecture: AArch64
  303 13:54:11.747489  output:   OS:           Linux
  304 13:54:11.747542  output:   Load Address: unavailable
  305 13:54:11.747596  output:   Entry Point:  unavailable
  306 13:54:11.747649  output:   Hash algo:    crc32
  307 13:54:11.747702  output:   Hash value:   732af844
  308 13:54:11.747755  output:  Default Configuration: 'conf-1'
  309 13:54:11.747808  output:  Configuration 0 (conf-1)
  310 13:54:11.747861  output:   Description:  mt8192-asurada-spherion-r0
  311 13:54:11.747915  output:   Kernel:       kernel-1
  312 13:54:11.747968  output:   Init Ramdisk: ramdisk-1
  313 13:54:11.748022  output:   FDT:          fdt-1
  314 13:54:11.748075  output:   Loadables:    kernel-1
  315 13:54:11.748128  output: 
  316 13:54:11.748317  end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
  317 13:54:11.748411  end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
  318 13:54:11.748515  end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
  319 13:54:11.748604  start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
  320 13:54:11.748683  No LXC device requested
  321 13:54:11.748763  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  322 13:54:11.748851  start: 1.8 deploy-device-env (timeout 00:09:19) [common]
  323 13:54:11.748931  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  324 13:54:11.749013  Checking files for TFTP limit of 4294967296 bytes.
  325 13:54:11.749499  end: 1 tftp-deploy (duration 00:00:41) [common]
  326 13:54:11.749606  start: 2 depthcharge-action (timeout 00:05:00) [common]
  327 13:54:11.749727  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  328 13:54:11.749913  substitutions:
  329 13:54:11.750032  - {DTB}: 12682923/tftp-deploy-7f8pea4e/dtb/mt8192-asurada-spherion-r0.dtb
  330 13:54:11.750098  - {INITRD}: 12682923/tftp-deploy-7f8pea4e/ramdisk/ramdisk.cpio.gz
  331 13:54:11.750158  - {KERNEL}: 12682923/tftp-deploy-7f8pea4e/kernel/Image
  332 13:54:11.750218  - {LAVA_MAC}: None
  333 13:54:11.750276  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12682923/extract-nfsrootfs-dxzindgm
  334 13:54:11.750333  - {NFS_SERVER_IP}: 192.168.201.1
  335 13:54:11.750389  - {PRESEED_CONFIG}: None
  336 13:54:11.750445  - {PRESEED_LOCAL}: None
  337 13:54:11.750501  - {RAMDISK}: 12682923/tftp-deploy-7f8pea4e/ramdisk/ramdisk.cpio.gz
  338 13:54:11.750557  - {ROOT_PART}: None
  339 13:54:11.750613  - {ROOT}: None
  340 13:54:11.750668  - {SERVER_IP}: 192.168.201.1
  341 13:54:11.750724  - {TEE}: None
  342 13:54:11.750779  Parsed boot commands:
  343 13:54:11.750837  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  344 13:54:11.751016  Parsed boot commands: tftpboot 192.168.201.1 12682923/tftp-deploy-7f8pea4e/kernel/image.itb 12682923/tftp-deploy-7f8pea4e/kernel/cmdline 
  345 13:54:11.751107  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  346 13:54:11.751191  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  347 13:54:11.751284  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  348 13:54:11.751374  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  349 13:54:11.751448  Not connected, no need to disconnect.
  350 13:54:11.751526  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  351 13:54:11.751606  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  352 13:54:11.751675  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
  353 13:54:11.755117  Setting prompt string to ['lava-test: # ']
  354 13:54:11.755462  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  355 13:54:11.755573  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  356 13:54:11.755708  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  357 13:54:11.755819  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  358 13:54:11.756013  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
  359 13:54:16.902137  >> Command sent successfully.

  360 13:54:16.904848  Returned 0 in 5 seconds
  361 13:54:17.005613  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  363 13:54:17.007020  end: 2.2.2 reset-device (duration 00:00:05) [common]
  364 13:54:17.007556  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  365 13:54:17.008027  Setting prompt string to 'Starting depthcharge on Spherion...'
  366 13:54:17.008459  Changing prompt to 'Starting depthcharge on Spherion...'
  367 13:54:17.008874  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  368 13:54:17.010210  [Enter `^Ec?' for help]

  369 13:54:17.181749  

  370 13:54:17.182396  

  371 13:54:17.182800  F0: 102B 0000

  372 13:54:17.183181  

  373 13:54:17.183540  F3: 1001 0000 [0200]

  374 13:54:17.185150  

  375 13:54:17.185644  F3: 1001 0000

  376 13:54:17.186063  

  377 13:54:17.186421  F7: 102D 0000

  378 13:54:17.186764  

  379 13:54:17.188438  F1: 0000 0000

  380 13:54:17.188920  

  381 13:54:17.189301  V0: 0000 0000 [0001]

  382 13:54:17.189658  

  383 13:54:17.191518  00: 0007 8000

  384 13:54:17.192007  

  385 13:54:17.192387  01: 0000 0000

  386 13:54:17.192757  

  387 13:54:17.194735  BP: 0C00 0209 [0000]

  388 13:54:17.195347  

  389 13:54:17.195742  G0: 1182 0000

  390 13:54:17.196202  

  391 13:54:17.198422  EC: 0000 0021 [4000]

  392 13:54:17.198993  

  393 13:54:17.199381  S7: 0000 0000 [0000]

  394 13:54:17.199734  

  395 13:54:17.202032  CC: 0000 0000 [0001]

  396 13:54:17.202596  

  397 13:54:17.202989  T0: 0000 0040 [010F]

  398 13:54:17.203348  

  399 13:54:17.205252  Jump to BL

  400 13:54:17.205847  

  401 13:54:17.228749  

  402 13:54:17.229339  

  403 13:54:17.229722  

  404 13:54:17.236188  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  405 13:54:17.239632  ARM64: Exception handlers installed.

  406 13:54:17.243282  ARM64: Testing exception

  407 13:54:17.246210  ARM64: Done test exception

  408 13:54:17.253001  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  409 13:54:17.263328  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  410 13:54:17.270494  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  411 13:54:17.280300  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  412 13:54:17.286623  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  413 13:54:17.293236  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  414 13:54:17.305551  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  415 13:54:17.312648  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  416 13:54:17.332050  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  417 13:54:17.334899  WDT: Last reset was cold boot

  418 13:54:17.338494  SPI1(PAD0) initialized at 2873684 Hz

  419 13:54:17.341882  SPI5(PAD0) initialized at 992727 Hz

  420 13:54:17.344764  VBOOT: Loading verstage.

  421 13:54:17.351758  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  422 13:54:17.355241  FMAP: Found "FLASH" version 1.1 at 0x20000.

  423 13:54:17.358593  FMAP: base = 0x0 size = 0x800000 #areas = 25

  424 13:54:17.361830  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  425 13:54:17.369567  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  426 13:54:17.376013  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  427 13:54:17.386548  read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps

  428 13:54:17.387129  

  429 13:54:17.387504  

  430 13:54:17.396614  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  431 13:54:17.400252  ARM64: Exception handlers installed.

  432 13:54:17.403427  ARM64: Testing exception

  433 13:54:17.403904  ARM64: Done test exception

  434 13:54:17.409742  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  435 13:54:17.413347  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  436 13:54:17.427855  Probing TPM: . done!

  437 13:54:17.428454  TPM ready after 0 ms

  438 13:54:17.434656  Connected to device vid:did:rid of 1ae0:0028:00

  439 13:54:17.441557  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  440 13:54:17.445243  Initialized TPM device CR50 revision 0

  441 13:54:17.509920  tlcl_send_startup: Startup return code is 0

  442 13:54:17.510516  TPM: setup succeeded

  443 13:54:17.521761  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  444 13:54:17.531017  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  445 13:54:17.540797  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  446 13:54:17.550561  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  447 13:54:17.553684  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  448 13:54:17.560577  in-header: 03 07 00 00 08 00 00 00 

  449 13:54:17.564297  in-data: aa e4 47 04 13 02 00 00 

  450 13:54:17.567887  Chrome EC: UHEPI supported

  451 13:54:17.574935  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  452 13:54:17.578945  in-header: 03 ad 00 00 08 00 00 00 

  453 13:54:17.582379  in-data: 00 20 20 08 00 00 00 00 

  454 13:54:17.582861  Phase 1

  455 13:54:17.586578  FMAP: area GBB found @ 3f5000 (12032 bytes)

  456 13:54:17.593360  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  457 13:54:17.597387  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  458 13:54:17.601204  Recovery requested (1009000e)

  459 13:54:17.609913  TPM: Extending digest for VBOOT: boot mode into PCR 0

  460 13:54:17.615441  tlcl_extend: response is 0

  461 13:54:17.625062  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  462 13:54:17.630314  tlcl_extend: response is 0

  463 13:54:17.637393  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  464 13:54:17.657445  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  465 13:54:17.664682  BS: bootblock times (exec / console): total (unknown) / 148 ms

  466 13:54:17.665170  

  467 13:54:17.665549  

  468 13:54:17.674611  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  469 13:54:17.678477  ARM64: Exception handlers installed.

  470 13:54:17.679064  ARM64: Testing exception

  471 13:54:17.681868  ARM64: Done test exception

  472 13:54:17.703068  pmic_efuse_setting: Set efuses in 11 msecs

  473 13:54:17.706824  pmwrap_interface_init: Select PMIF_VLD_RDY

  474 13:54:17.713163  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  475 13:54:17.716720  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  476 13:54:17.720125  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  477 13:54:17.727292  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  478 13:54:17.730427  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  479 13:54:17.737576  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  480 13:54:17.741316  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  481 13:54:17.744954  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  482 13:54:17.748530  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  483 13:54:17.755938  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  484 13:54:17.759437  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  485 13:54:17.763881  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  486 13:54:17.767128  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  487 13:54:17.774613  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  488 13:54:17.781178  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  489 13:54:17.788546  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  490 13:54:17.791952  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  491 13:54:17.799085  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  492 13:54:17.803024  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  493 13:54:17.809816  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  494 13:54:17.812762  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  495 13:54:17.820539  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  496 13:54:17.826816  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  497 13:54:17.830264  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  498 13:54:17.836816  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  499 13:54:17.843911  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  500 13:54:17.846961  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  501 13:54:17.850395  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  502 13:54:17.857229  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  503 13:54:17.860103  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  504 13:54:17.867085  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  505 13:54:17.870391  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  506 13:54:17.877358  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  507 13:54:17.880432  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  508 13:54:17.887559  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  509 13:54:17.890531  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  510 13:54:17.897121  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  511 13:54:17.900739  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  512 13:54:17.907103  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  513 13:54:17.910975  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  514 13:54:17.914453  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  515 13:54:17.918199  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  516 13:54:17.924833  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  517 13:54:17.928284  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  518 13:54:17.931620  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  519 13:54:17.939075  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  520 13:54:17.942559  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  521 13:54:17.946182  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  522 13:54:17.950064  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  523 13:54:17.954224  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  524 13:54:17.957532  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  525 13:54:17.965450  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  526 13:54:17.976320  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  527 13:54:17.979382  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  528 13:54:17.987095  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  529 13:54:17.994726  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  530 13:54:18.001067  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  531 13:54:18.004318  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  532 13:54:18.007643  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  533 13:54:18.015848  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2f

  534 13:54:18.022409  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  535 13:54:18.025561  [RTC]rtc_osc_init,62: osc32con val = 0xde70

  536 13:54:18.028696  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  537 13:54:18.039806  [RTC]rtc_get_frequency_meter,154: input=15, output=772

  538 13:54:18.049487  [RTC]rtc_get_frequency_meter,154: input=23, output=958

  539 13:54:18.058983  [RTC]rtc_get_frequency_meter,154: input=19, output=864

  540 13:54:18.068566  [RTC]rtc_get_frequency_meter,154: input=17, output=818

  541 13:54:18.078547  [RTC]rtc_get_frequency_meter,154: input=16, output=796

  542 13:54:18.081913  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70

  543 13:54:18.085245  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  544 13:54:18.091959  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  545 13:54:18.095002  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  546 13:54:18.098387  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  547 13:54:18.102026  ADC[4]: Raw value=902507 ID=7

  548 13:54:18.105026  ADC[3]: Raw value=213179 ID=1

  549 13:54:18.105506  RAM Code: 0x71

  550 13:54:18.111983  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  551 13:54:18.115191  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  552 13:54:18.124847  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  553 13:54:18.131731  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  554 13:54:18.135320  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  555 13:54:18.138830  in-header: 03 07 00 00 08 00 00 00 

  556 13:54:18.142128  in-data: aa e4 47 04 13 02 00 00 

  557 13:54:18.142568  Chrome EC: UHEPI supported

  558 13:54:18.148454  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  559 13:54:18.151705  in-header: 03 ed 00 00 08 00 00 00 

  560 13:54:18.155458  in-data: 80 20 60 08 00 00 00 00 

  561 13:54:18.158780  MRC: failed to locate region type 0.

  562 13:54:18.165347  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  563 13:54:18.168867  DRAM-K: Running full calibration

  564 13:54:18.175295  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  565 13:54:18.178424  header.status = 0x0

  566 13:54:18.181901  header.version = 0x6 (expected: 0x6)

  567 13:54:18.185402  header.size = 0xd00 (expected: 0xd00)

  568 13:54:18.185835  header.flags = 0x0

  569 13:54:18.191733  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  570 13:54:18.209571  read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps

  571 13:54:18.216736  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  572 13:54:18.220003  dram_init: ddr_geometry: 2

  573 13:54:18.223102  [EMI] MDL number = 2

  574 13:54:18.223537  [EMI] Get MDL freq = 0

  575 13:54:18.226284  dram_init: ddr_type: 0

  576 13:54:18.226719  is_discrete_lpddr4: 1

  577 13:54:18.229617  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  578 13:54:18.230079  

  579 13:54:18.230423  

  580 13:54:18.233384  [Bian_co] ETT version 0.0.0.1

  581 13:54:18.239443   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  582 13:54:18.239879  

  583 13:54:18.242989  dramc_set_vcore_voltage set vcore to 650000

  584 13:54:18.243422  Read voltage for 800, 4

  585 13:54:18.246085  Vio18 = 0

  586 13:54:18.246536  Vcore = 650000

  587 13:54:18.246883  Vdram = 0

  588 13:54:18.249492  Vddq = 0

  589 13:54:18.249928  Vmddr = 0

  590 13:54:18.252690  dram_init: config_dvfs: 1

  591 13:54:18.255897  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  592 13:54:18.262885  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  593 13:54:18.265992  [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9

  594 13:54:18.269552  freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9

  595 13:54:18.272679  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  596 13:54:18.276596  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  597 13:54:18.279451  MEM_TYPE=3, freq_sel=18

  598 13:54:18.282763  sv_algorithm_assistance_LP4_1600 

  599 13:54:18.285980  ============ PULL DRAM RESETB DOWN ============

  600 13:54:18.289637  ========== PULL DRAM RESETB DOWN end =========

  601 13:54:18.296427  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  602 13:54:18.299736  =================================== 

  603 13:54:18.302791  LPDDR4 DRAM CONFIGURATION

  604 13:54:18.306391  =================================== 

  605 13:54:18.306580  EX_ROW_EN[0]    = 0x0

  606 13:54:18.309326  EX_ROW_EN[1]    = 0x0

  607 13:54:18.309514  LP4Y_EN      = 0x0

  608 13:54:18.312780  WORK_FSP     = 0x0

  609 13:54:18.312968  WL           = 0x2

  610 13:54:18.316239  RL           = 0x2

  611 13:54:18.316429  BL           = 0x2

  612 13:54:18.319532  RPST         = 0x0

  613 13:54:18.319722  RD_PRE       = 0x0

  614 13:54:18.322920  WR_PRE       = 0x1

  615 13:54:18.323109  WR_PST       = 0x0

  616 13:54:18.326377  DBI_WR       = 0x0

  617 13:54:18.326568  DBI_RD       = 0x0

  618 13:54:18.329671  OTF          = 0x1

  619 13:54:18.333039  =================================== 

  620 13:54:18.336088  =================================== 

  621 13:54:18.336278  ANA top config

  622 13:54:18.339699  =================================== 

  623 13:54:18.342867  DLL_ASYNC_EN            =  0

  624 13:54:18.346010  ALL_SLAVE_EN            =  1

  625 13:54:18.349660  NEW_RANK_MODE           =  1

  626 13:54:18.349858  DLL_IDLE_MODE           =  1

  627 13:54:18.352898  LP45_APHY_COMB_EN       =  1

  628 13:54:18.356134  TX_ODT_DIS              =  1

  629 13:54:18.359699  NEW_8X_MODE             =  1

  630 13:54:18.363489  =================================== 

  631 13:54:18.366417  =================================== 

  632 13:54:18.366607  data_rate                  = 1600

  633 13:54:18.369742  CKR                        = 1

  634 13:54:18.373016  DQ_P2S_RATIO               = 8

  635 13:54:18.376625  =================================== 

  636 13:54:18.380004  CA_P2S_RATIO               = 8

  637 13:54:18.383080  DQ_CA_OPEN                 = 0

  638 13:54:18.386416  DQ_SEMI_OPEN               = 0

  639 13:54:18.386639  CA_SEMI_OPEN               = 0

  640 13:54:18.390067  CA_FULL_RATE               = 0

  641 13:54:18.393616  DQ_CKDIV4_EN               = 1

  642 13:54:18.397133  CA_CKDIV4_EN               = 1

  643 13:54:18.400616  CA_PREDIV_EN               = 0

  644 13:54:18.401095  PH8_DLY                    = 0

  645 13:54:18.403797  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  646 13:54:18.406970  DQ_AAMCK_DIV               = 4

  647 13:54:18.410541  CA_AAMCK_DIV               = 4

  648 13:54:18.414220  CA_ADMCK_DIV               = 4

  649 13:54:18.417541  DQ_TRACK_CA_EN             = 0

  650 13:54:18.418156  CA_PICK                    = 800

  651 13:54:18.420564  CA_MCKIO                   = 800

  652 13:54:18.424050  MCKIO_SEMI                 = 0

  653 13:54:18.427304  PLL_FREQ                   = 3068

  654 13:54:18.430487  DQ_UI_PI_RATIO             = 32

  655 13:54:18.433616  CA_UI_PI_RATIO             = 0

  656 13:54:18.437217  =================================== 

  657 13:54:18.440330  =================================== 

  658 13:54:18.440815  memory_type:LPDDR4         

  659 13:54:18.443554  GP_NUM     : 10       

  660 13:54:18.447012  SRAM_EN    : 1       

  661 13:54:18.447532  MD32_EN    : 0       

  662 13:54:18.450549  =================================== 

  663 13:54:18.454065  [ANA_INIT] >>>>>>>>>>>>>> 

  664 13:54:18.457482  <<<<<< [CONFIGURE PHASE]: ANA_TX

  665 13:54:18.460902  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  666 13:54:18.464907  =================================== 

  667 13:54:18.465610  data_rate = 1600,PCW = 0X7600

  668 13:54:18.468674  =================================== 

  669 13:54:18.471819  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  670 13:54:18.479384  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  671 13:54:18.482869  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  672 13:54:18.486795  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  673 13:54:18.490458  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  674 13:54:18.493712  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  675 13:54:18.497418  [ANA_INIT] flow start 

  676 13:54:18.497504  [ANA_INIT] PLL >>>>>>>> 

  677 13:54:18.501362  [ANA_INIT] PLL <<<<<<<< 

  678 13:54:18.505159  [ANA_INIT] MIDPI >>>>>>>> 

  679 13:54:18.505238  [ANA_INIT] MIDPI <<<<<<<< 

  680 13:54:18.508370  [ANA_INIT] DLL >>>>>>>> 

  681 13:54:18.512070  [ANA_INIT] flow end 

  682 13:54:18.515727  ============ LP4 DIFF to SE enter ============

  683 13:54:18.519571  ============ LP4 DIFF to SE exit  ============

  684 13:54:18.519657  [ANA_INIT] <<<<<<<<<<<<< 

  685 13:54:18.523321  [Flow] Enable top DCM control >>>>> 

  686 13:54:18.526915  [Flow] Enable top DCM control <<<<< 

  687 13:54:18.530681  Enable DLL master slave shuffle 

  688 13:54:18.538126  ============================================================== 

  689 13:54:18.538245  Gating Mode config

  690 13:54:18.544995  ============================================================== 

  691 13:54:18.545083  Config description: 

  692 13:54:18.556789  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  693 13:54:18.560233  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  694 13:54:18.567797  SELPH_MODE            0: By rank         1: By Phase 

  695 13:54:18.571889  ============================================================== 

  696 13:54:18.575847  GAT_TRACK_EN                 =  1

  697 13:54:18.579467  RX_GATING_MODE               =  2

  698 13:54:18.583224  RX_GATING_TRACK_MODE         =  2

  699 13:54:18.583824  SELPH_MODE                   =  1

  700 13:54:18.587110  PICG_EARLY_EN                =  1

  701 13:54:18.590882  VALID_LAT_VALUE              =  1

  702 13:54:18.594233  ============================================================== 

  703 13:54:18.597798  Enter into Gating configuration >>>> 

  704 13:54:18.601556  Exit from Gating configuration <<<< 

  705 13:54:18.605594  Enter into  DVFS_PRE_config >>>>> 

  706 13:54:18.617071  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  707 13:54:18.620642  Exit from  DVFS_PRE_config <<<<< 

  708 13:54:18.624321  Enter into PICG configuration >>>> 

  709 13:54:18.624705  Exit from PICG configuration <<<< 

  710 13:54:18.628496  [RX_INPUT] configuration >>>>> 

  711 13:54:18.631835  [RX_INPUT] configuration <<<<< 

  712 13:54:18.635337  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  713 13:54:18.642955  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  714 13:54:18.646901  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  715 13:54:18.654030  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  716 13:54:18.661234  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  717 13:54:18.665330  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  718 13:54:18.672491  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  719 13:54:18.676231  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  720 13:54:18.679829  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  721 13:54:18.683325  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  722 13:54:18.687428  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  723 13:54:18.690767  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  724 13:54:18.694886  =================================== 

  725 13:54:18.698748  LPDDR4 DRAM CONFIGURATION

  726 13:54:18.702093  =================================== 

  727 13:54:18.702179  EX_ROW_EN[0]    = 0x0

  728 13:54:18.705574  EX_ROW_EN[1]    = 0x0

  729 13:54:18.705666  LP4Y_EN      = 0x0

  730 13:54:18.709552  WORK_FSP     = 0x0

  731 13:54:18.709655  WL           = 0x2

  732 13:54:18.709779  RL           = 0x2

  733 13:54:18.713401  BL           = 0x2

  734 13:54:18.713486  RPST         = 0x0

  735 13:54:18.716898  RD_PRE       = 0x0

  736 13:54:18.716983  WR_PRE       = 0x1

  737 13:54:18.720783  WR_PST       = 0x0

  738 13:54:18.720868  DBI_WR       = 0x0

  739 13:54:18.724919  DBI_RD       = 0x0

  740 13:54:18.725010  OTF          = 0x1

  741 13:54:18.728235  =================================== 

  742 13:54:18.731971  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  743 13:54:18.735798  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  744 13:54:18.739542  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  745 13:54:18.743319  =================================== 

  746 13:54:18.747195  LPDDR4 DRAM CONFIGURATION

  747 13:54:18.750562  =================================== 

  748 13:54:18.750757  EX_ROW_EN[0]    = 0x10

  749 13:54:18.754495  EX_ROW_EN[1]    = 0x0

  750 13:54:18.754651  LP4Y_EN      = 0x0

  751 13:54:18.758343  WORK_FSP     = 0x0

  752 13:54:18.758547  WL           = 0x2

  753 13:54:18.761862  RL           = 0x2

  754 13:54:18.762102  BL           = 0x2

  755 13:54:18.765976  RPST         = 0x0

  756 13:54:18.766132  RD_PRE       = 0x0

  757 13:54:18.769739  WR_PRE       = 0x1

  758 13:54:18.769962  WR_PST       = 0x0

  759 13:54:18.773470  DBI_WR       = 0x0

  760 13:54:18.773630  DBI_RD       = 0x0

  761 13:54:18.773773  OTF          = 0x1

  762 13:54:18.776920  =================================== 

  763 13:54:18.784277  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  764 13:54:18.788152  nWR fixed to 40

  765 13:54:18.792713  [ModeRegInit_LP4] CH0 RK0

  766 13:54:18.792869  [ModeRegInit_LP4] CH0 RK1

  767 13:54:18.795468  [ModeRegInit_LP4] CH1 RK0

  768 13:54:18.795622  [ModeRegInit_LP4] CH1 RK1

  769 13:54:18.798985  match AC timing 13

  770 13:54:18.802694  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  771 13:54:18.805624  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  772 13:54:18.812623  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  773 13:54:18.815629  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  774 13:54:18.822770  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  775 13:54:18.822984  [EMI DOE] emi_dcm 0

  776 13:54:18.826183  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  777 13:54:18.826428  ==

  778 13:54:18.829411  Dram Type= 6, Freq= 0, CH_0, rank 0

  779 13:54:18.836126  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  780 13:54:18.836439  ==

  781 13:54:18.839600  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  782 13:54:18.846282  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  783 13:54:18.855527  [CA 0] Center 38 (7~69) winsize 63

  784 13:54:18.859279  [CA 1] Center 38 (7~69) winsize 63

  785 13:54:18.862180  [CA 2] Center 35 (5~66) winsize 62

  786 13:54:18.865733  [CA 3] Center 35 (4~66) winsize 63

  787 13:54:18.869083  [CA 4] Center 34 (4~65) winsize 62

  788 13:54:18.872409  [CA 5] Center 33 (3~64) winsize 62

  789 13:54:18.872493  

  790 13:54:18.875407  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  791 13:54:18.875493  

  792 13:54:18.879169  [CATrainingPosCal] consider 1 rank data

  793 13:54:18.882123  u2DelayCellTimex100 = 270/100 ps

  794 13:54:18.886201  CA0 delay=38 (7~69),Diff = 5 PI (36 cell)

  795 13:54:18.888833  CA1 delay=38 (7~69),Diff = 5 PI (36 cell)

  796 13:54:18.895596  CA2 delay=35 (5~66),Diff = 2 PI (14 cell)

  797 13:54:18.898976  CA3 delay=35 (4~66),Diff = 2 PI (14 cell)

  798 13:54:18.902128  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

  799 13:54:18.905546  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  800 13:54:18.905663  

  801 13:54:18.908783  CA PerBit enable=1, Macro0, CA PI delay=33

  802 13:54:18.908887  

  803 13:54:18.912311  [CBTSetCACLKResult] CA Dly = 33

  804 13:54:18.912409  CS Dly: 6 (0~37)

  805 13:54:18.912501  ==

  806 13:54:18.915648  Dram Type= 6, Freq= 0, CH_0, rank 1

  807 13:54:18.922284  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  808 13:54:18.922415  ==

  809 13:54:18.925686  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  810 13:54:18.932094  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  811 13:54:18.941569  [CA 0] Center 38 (7~69) winsize 63

  812 13:54:18.945160  [CA 1] Center 38 (8~69) winsize 62

  813 13:54:18.948486  [CA 2] Center 36 (6~67) winsize 62

  814 13:54:18.951905  [CA 3] Center 35 (5~66) winsize 62

  815 13:54:18.955164  [CA 4] Center 35 (4~66) winsize 63

  816 13:54:18.958912  [CA 5] Center 34 (4~65) winsize 62

  817 13:54:18.959015  

  818 13:54:18.961907  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  819 13:54:18.962027  

  820 13:54:18.965774  [CATrainingPosCal] consider 2 rank data

  821 13:54:18.969002  u2DelayCellTimex100 = 270/100 ps

  822 13:54:18.972082  CA0 delay=38 (7~69),Diff = 4 PI (28 cell)

  823 13:54:18.975395  CA1 delay=38 (8~69),Diff = 4 PI (28 cell)

  824 13:54:18.981984  CA2 delay=36 (6~66),Diff = 2 PI (14 cell)

  825 13:54:18.985206  CA3 delay=35 (5~66),Diff = 1 PI (7 cell)

  826 13:54:18.988398  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

  827 13:54:18.991735  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

  828 13:54:18.991915  

  829 13:54:18.994928  CA PerBit enable=1, Macro0, CA PI delay=34

  830 13:54:18.995110  

  831 13:54:18.998893  [CBTSetCACLKResult] CA Dly = 34

  832 13:54:18.999075  CS Dly: 6 (0~38)

  833 13:54:18.999219  

  834 13:54:19.001931  ----->DramcWriteLeveling(PI) begin...

  835 13:54:19.004963  ==

  836 13:54:19.008319  Dram Type= 6, Freq= 0, CH_0, rank 0

  837 13:54:19.011957  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  838 13:54:19.012125  ==

  839 13:54:19.015055  Write leveling (Byte 0): 29 => 29

  840 13:54:19.018682  Write leveling (Byte 1): 29 => 29

  841 13:54:19.021737  DramcWriteLeveling(PI) end<-----

  842 13:54:19.021823  

  843 13:54:19.021906  ==

  844 13:54:19.025002  Dram Type= 6, Freq= 0, CH_0, rank 0

  845 13:54:19.028320  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  846 13:54:19.028435  ==

  847 13:54:19.031843  [Gating] SW mode calibration

  848 13:54:19.039156  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  849 13:54:19.042846  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  850 13:54:19.046672   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  851 13:54:19.050531   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  852 13:54:19.057250   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  853 13:54:19.060746   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  854 13:54:19.064691   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  855 13:54:19.071151   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  856 13:54:19.074378   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  857 13:54:19.077761   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  858 13:54:19.084341   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  859 13:54:19.087626   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  860 13:54:19.090966   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  861 13:54:19.097950   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  862 13:54:19.101046   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  863 13:54:19.104413   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  864 13:54:19.107841   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  865 13:54:19.114609   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  866 13:54:19.118018   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  867 13:54:19.121481   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  868 13:54:19.127863   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

  869 13:54:19.131282   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  870 13:54:19.134647   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  871 13:54:19.141047   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  872 13:54:19.144666   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  873 13:54:19.148083   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  874 13:54:19.154755   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  875 13:54:19.158138   0  9  4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)

  876 13:54:19.161035   0  9  8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)

  877 13:54:19.167802   0  9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

  878 13:54:19.171164   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  879 13:54:19.174546   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  880 13:54:19.180942   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  881 13:54:19.184701   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  882 13:54:19.187847   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

  883 13:54:19.194442   0 10  4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)

  884 13:54:19.197787   0 10  8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)

  885 13:54:19.201519   0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

  886 13:54:19.204706   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  887 13:54:19.211403   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  888 13:54:19.214440   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  889 13:54:19.218381   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  890 13:54:19.224630   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  891 13:54:19.227982   0 11  4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)

  892 13:54:19.231412   0 11  8 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)

  893 13:54:19.237750   0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

  894 13:54:19.241448   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  895 13:54:19.244900   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  896 13:54:19.251590   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  897 13:54:19.254651   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  898 13:54:19.258044   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  899 13:54:19.264729   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  900 13:54:19.268076   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  901 13:54:19.271181   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  902 13:54:19.274861   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  903 13:54:19.281181   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  904 13:54:19.284625   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  905 13:54:19.288055   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  906 13:54:19.294752   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  907 13:54:19.297823   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  908 13:54:19.301376   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  909 13:54:19.308245   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  910 13:54:19.311366   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  911 13:54:19.314774   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  912 13:54:19.321539   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  913 13:54:19.324849   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  914 13:54:19.327988   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  915 13:54:19.334528   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  916 13:54:19.337763   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  917 13:54:19.341146  Total UI for P1: 0, mck2ui 16

  918 13:54:19.344590  best dqsien dly found for B0: ( 0, 14,  2)

  919 13:54:19.348090   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  920 13:54:19.351535  Total UI for P1: 0, mck2ui 16

  921 13:54:19.354594  best dqsien dly found for B1: ( 0, 14,  8)

  922 13:54:19.357880  best DQS0 dly(MCK, UI, PI) = (0, 14, 2)

  923 13:54:19.361399  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

  924 13:54:19.361486  

  925 13:54:19.365139  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)

  926 13:54:19.367978  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

  927 13:54:19.371673  [Gating] SW calibration Done

  928 13:54:19.372108  ==

  929 13:54:19.375413  Dram Type= 6, Freq= 0, CH_0, rank 0

  930 13:54:19.382274  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  931 13:54:19.382826  ==

  932 13:54:19.383275  RX Vref Scan: 0

  933 13:54:19.383682  

  934 13:54:19.385278  RX Vref 0 -> 0, step: 1

  935 13:54:19.385819  

  936 13:54:19.388454  RX Delay -130 -> 252, step: 16

  937 13:54:19.392260  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

  938 13:54:19.395456  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

  939 13:54:19.399135  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  940 13:54:19.401845  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  941 13:54:19.408519  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

  942 13:54:19.411991  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  943 13:54:19.415685  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

  944 13:54:19.418784  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

  945 13:54:19.421857  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

  946 13:54:19.429107  iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224

  947 13:54:19.432081  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

  948 13:54:19.435473  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

  949 13:54:19.438829  iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224

  950 13:54:19.441727  iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208

  951 13:54:19.448790  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

  952 13:54:19.452172  iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208

  953 13:54:19.452601  ==

  954 13:54:19.455046  Dram Type= 6, Freq= 0, CH_0, rank 0

  955 13:54:19.458661  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  956 13:54:19.459090  ==

  957 13:54:19.462194  DQS Delay:

  958 13:54:19.462619  DQS0 = 0, DQS1 = 0

  959 13:54:19.462959  DQM Delay:

  960 13:54:19.465438  DQM0 = 89, DQM1 = 79

  961 13:54:19.465934  DQ Delay:

  962 13:54:19.468799  DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85

  963 13:54:19.472044  DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101

  964 13:54:19.475357  DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77

  965 13:54:19.478698  DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85

  966 13:54:19.479215  

  967 13:54:19.479718  

  968 13:54:19.480049  ==

  969 13:54:19.482238  Dram Type= 6, Freq= 0, CH_0, rank 0

  970 13:54:19.489035  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  971 13:54:19.489467  ==

  972 13:54:19.489909  

  973 13:54:19.490403  

  974 13:54:19.490826  	TX Vref Scan disable

  975 13:54:19.492155   == TX Byte 0 ==

  976 13:54:19.495552  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  977 13:54:19.498869  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  978 13:54:19.502312   == TX Byte 1 ==

  979 13:54:19.505743  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  980 13:54:19.509260  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  981 13:54:19.512818  ==

  982 13:54:19.513369  Dram Type= 6, Freq= 0, CH_0, rank 0

  983 13:54:19.519211  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  984 13:54:19.519771  ==

  985 13:54:19.530950  TX Vref=22, minBit 5, minWin=27, winSum=442

  986 13:54:19.534649  TX Vref=24, minBit 5, minWin=27, winSum=445

  987 13:54:19.537571  TX Vref=26, minBit 5, minWin=27, winSum=449

  988 13:54:19.540795  TX Vref=28, minBit 6, minWin=27, winSum=449

  989 13:54:19.544084  TX Vref=30, minBit 6, minWin=28, winSum=457

  990 13:54:19.550564  TX Vref=32, minBit 11, minWin=27, winSum=453

  991 13:54:19.553901  [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 30

  992 13:54:19.554008  

  993 13:54:19.557286  Final TX Range 1 Vref 30

  994 13:54:19.557372  

  995 13:54:19.557454  ==

  996 13:54:19.560566  Dram Type= 6, Freq= 0, CH_0, rank 0

  997 13:54:19.563812  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  998 13:54:19.563899  ==

  999 13:54:19.567230  

 1000 13:54:19.567314  

 1001 13:54:19.567381  	TX Vref Scan disable

 1002 13:54:19.570758   == TX Byte 0 ==

 1003 13:54:19.573999  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1004 13:54:19.577441  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1005 13:54:19.581070   == TX Byte 1 ==

 1006 13:54:19.584149  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1007 13:54:19.587474  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1008 13:54:19.590803  

 1009 13:54:19.590908  [DATLAT]

 1010 13:54:19.591006  Freq=800, CH0 RK0

 1011 13:54:19.591093  

 1012 13:54:19.593999  DATLAT Default: 0xa

 1013 13:54:19.594115  0, 0xFFFF, sum = 0

 1014 13:54:19.597600  1, 0xFFFF, sum = 0

 1015 13:54:19.597728  2, 0xFFFF, sum = 0

 1016 13:54:19.600711  3, 0xFFFF, sum = 0

 1017 13:54:19.600839  4, 0xFFFF, sum = 0

 1018 13:54:19.604229  5, 0xFFFF, sum = 0

 1019 13:54:19.607393  6, 0xFFFF, sum = 0

 1020 13:54:19.607552  7, 0xFFFF, sum = 0

 1021 13:54:19.610587  8, 0xFFFF, sum = 0

 1022 13:54:19.610746  9, 0x0, sum = 1

 1023 13:54:19.610871  10, 0x0, sum = 2

 1024 13:54:19.614382  11, 0x0, sum = 3

 1025 13:54:19.614553  12, 0x0, sum = 4

 1026 13:54:19.617775  best_step = 10

 1027 13:54:19.618243  

 1028 13:54:19.618592  ==

 1029 13:54:19.620816  Dram Type= 6, Freq= 0, CH_0, rank 0

 1030 13:54:19.624591  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1031 13:54:19.625447  ==

 1032 13:54:19.627474  RX Vref Scan: 1

 1033 13:54:19.627899  

 1034 13:54:19.628239  Set Vref Range= 32 -> 127

 1035 13:54:19.631025  

 1036 13:54:19.631450  RX Vref 32 -> 127, step: 1

 1037 13:54:19.631784  

 1038 13:54:19.634238  RX Delay -95 -> 252, step: 8

 1039 13:54:19.634664  

 1040 13:54:19.637895  Set Vref, RX VrefLevel [Byte0]: 32

 1041 13:54:19.641182                           [Byte1]: 32

 1042 13:54:19.641608  

 1043 13:54:19.644113  Set Vref, RX VrefLevel [Byte0]: 33

 1044 13:54:19.647457                           [Byte1]: 33

 1045 13:54:19.651349  

 1046 13:54:19.651772  Set Vref, RX VrefLevel [Byte0]: 34

 1047 13:54:19.654889                           [Byte1]: 34

 1048 13:54:19.658812  

 1049 13:54:19.659230  Set Vref, RX VrefLevel [Byte0]: 35

 1050 13:54:19.662057                           [Byte1]: 35

 1051 13:54:19.666606  

 1052 13:54:19.667028  Set Vref, RX VrefLevel [Byte0]: 36

 1053 13:54:19.669873                           [Byte1]: 36

 1054 13:54:19.674063  

 1055 13:54:19.674496  Set Vref, RX VrefLevel [Byte0]: 37

 1056 13:54:19.677757                           [Byte1]: 37

 1057 13:54:19.682440  

 1058 13:54:19.682962  Set Vref, RX VrefLevel [Byte0]: 38

 1059 13:54:19.685752                           [Byte1]: 38

 1060 13:54:19.689741  

 1061 13:54:19.690207  Set Vref, RX VrefLevel [Byte0]: 39

 1062 13:54:19.692647                           [Byte1]: 39

 1063 13:54:19.697030  

 1064 13:54:19.697563  Set Vref, RX VrefLevel [Byte0]: 40

 1065 13:54:19.700584                           [Byte1]: 40

 1066 13:54:19.704873  

 1067 13:54:19.705578  Set Vref, RX VrefLevel [Byte0]: 41

 1068 13:54:19.708132                           [Byte1]: 41

 1069 13:54:19.712459  

 1070 13:54:19.712927  Set Vref, RX VrefLevel [Byte0]: 42

 1071 13:54:19.715900                           [Byte1]: 42

 1072 13:54:19.720301  

 1073 13:54:19.720826  Set Vref, RX VrefLevel [Byte0]: 43

 1074 13:54:19.723403                           [Byte1]: 43

 1075 13:54:19.727785  

 1076 13:54:19.728307  Set Vref, RX VrefLevel [Byte0]: 44

 1077 13:54:19.731028                           [Byte1]: 44

 1078 13:54:19.735185  

 1079 13:54:19.738394  Set Vref, RX VrefLevel [Byte0]: 45

 1080 13:54:19.738821                           [Byte1]: 45

 1081 13:54:19.742945  

 1082 13:54:19.743468  Set Vref, RX VrefLevel [Byte0]: 46

 1083 13:54:19.746317                           [Byte1]: 46

 1084 13:54:19.750401  

 1085 13:54:19.750977  Set Vref, RX VrefLevel [Byte0]: 47

 1086 13:54:19.753691                           [Byte1]: 47

 1087 13:54:19.758400  

 1088 13:54:19.758985  Set Vref, RX VrefLevel [Byte0]: 48

 1089 13:54:19.761129                           [Byte1]: 48

 1090 13:54:19.765169  

 1091 13:54:19.765641  Set Vref, RX VrefLevel [Byte0]: 49

 1092 13:54:19.769112                           [Byte1]: 49

 1093 13:54:19.773353  

 1094 13:54:19.773989  Set Vref, RX VrefLevel [Byte0]: 50

 1095 13:54:19.776400                           [Byte1]: 50

 1096 13:54:19.780628  

 1097 13:54:19.781199  Set Vref, RX VrefLevel [Byte0]: 51

 1098 13:54:19.784210                           [Byte1]: 51

 1099 13:54:19.788201  

 1100 13:54:19.788669  Set Vref, RX VrefLevel [Byte0]: 52

 1101 13:54:19.791837                           [Byte1]: 52

 1102 13:54:19.796183  

 1103 13:54:19.796749  Set Vref, RX VrefLevel [Byte0]: 53

 1104 13:54:19.799206                           [Byte1]: 53

 1105 13:54:19.803635  

 1106 13:54:19.804202  Set Vref, RX VrefLevel [Byte0]: 54

 1107 13:54:19.806907                           [Byte1]: 54

 1108 13:54:19.811399  

 1109 13:54:19.811994  Set Vref, RX VrefLevel [Byte0]: 55

 1110 13:54:19.814588                           [Byte1]: 55

 1111 13:54:19.818733  

 1112 13:54:19.819201  Set Vref, RX VrefLevel [Byte0]: 56

 1113 13:54:19.822005                           [Byte1]: 56

 1114 13:54:19.826510  

 1115 13:54:19.827084  Set Vref, RX VrefLevel [Byte0]: 57

 1116 13:54:19.829523                           [Byte1]: 57

 1117 13:54:19.834093  

 1118 13:54:19.834663  Set Vref, RX VrefLevel [Byte0]: 58

 1119 13:54:19.837351                           [Byte1]: 58

 1120 13:54:19.841682  

 1121 13:54:19.842302  Set Vref, RX VrefLevel [Byte0]: 59

 1122 13:54:19.844826                           [Byte1]: 59

 1123 13:54:19.849181  

 1124 13:54:19.849752  Set Vref, RX VrefLevel [Byte0]: 60

 1125 13:54:19.852562                           [Byte1]: 60

 1126 13:54:19.857024  

 1127 13:54:19.857593  Set Vref, RX VrefLevel [Byte0]: 61

 1128 13:54:19.860109                           [Byte1]: 61

 1129 13:54:19.864186  

 1130 13:54:19.864768  Set Vref, RX VrefLevel [Byte0]: 62

 1131 13:54:19.867588                           [Byte1]: 62

 1132 13:54:19.871625  

 1133 13:54:19.872200  Set Vref, RX VrefLevel [Byte0]: 63

 1134 13:54:19.875015                           [Byte1]: 63

 1135 13:54:19.879412  

 1136 13:54:19.879983  Set Vref, RX VrefLevel [Byte0]: 64

 1137 13:54:19.882676                           [Byte1]: 64

 1138 13:54:19.886964  

 1139 13:54:19.887430  Set Vref, RX VrefLevel [Byte0]: 65

 1140 13:54:19.890251                           [Byte1]: 65

 1141 13:54:19.894481  

 1142 13:54:19.894952  Set Vref, RX VrefLevel [Byte0]: 66

 1143 13:54:19.898076                           [Byte1]: 66

 1144 13:54:19.902543  

 1145 13:54:19.903154  Set Vref, RX VrefLevel [Byte0]: 67

 1146 13:54:19.905334                           [Byte1]: 67

 1147 13:54:19.909526  

 1148 13:54:19.910048  Set Vref, RX VrefLevel [Byte0]: 68

 1149 13:54:19.913335                           [Byte1]: 68

 1150 13:54:19.917648  

 1151 13:54:19.918267  Set Vref, RX VrefLevel [Byte0]: 69

 1152 13:54:19.921139                           [Byte1]: 69

 1153 13:54:19.925303  

 1154 13:54:19.925875  Set Vref, RX VrefLevel [Byte0]: 70

 1155 13:54:19.928261                           [Byte1]: 70

 1156 13:54:19.932774  

 1157 13:54:19.933342  Set Vref, RX VrefLevel [Byte0]: 71

 1158 13:54:19.936029                           [Byte1]: 71

 1159 13:54:19.940505  

 1160 13:54:19.941071  Set Vref, RX VrefLevel [Byte0]: 72

 1161 13:54:19.943323                           [Byte1]: 72

 1162 13:54:19.947665  

 1163 13:54:19.948128  Set Vref, RX VrefLevel [Byte0]: 73

 1164 13:54:19.951398                           [Byte1]: 73

 1165 13:54:19.955328  

 1166 13:54:19.955801  Set Vref, RX VrefLevel [Byte0]: 74

 1167 13:54:19.958548                           [Byte1]: 74

 1168 13:54:19.962995  

 1169 13:54:19.963563  Set Vref, RX VrefLevel [Byte0]: 75

 1170 13:54:19.966549                           [Byte1]: 75

 1171 13:54:19.970637  

 1172 13:54:19.971247  Set Vref, RX VrefLevel [Byte0]: 76

 1173 13:54:19.974015                           [Byte1]: 76

 1174 13:54:19.978033  

 1175 13:54:19.978594  Final RX Vref Byte 0 = 62 to rank0

 1176 13:54:19.981482  Final RX Vref Byte 1 = 61 to rank0

 1177 13:54:19.984545  Final RX Vref Byte 0 = 62 to rank1

 1178 13:54:19.988112  Final RX Vref Byte 1 = 61 to rank1==

 1179 13:54:19.991891  Dram Type= 6, Freq= 0, CH_0, rank 0

 1180 13:54:19.994840  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1181 13:54:19.998390  ==

 1182 13:54:19.998861  DQS Delay:

 1183 13:54:19.999232  DQS0 = 0, DQS1 = 0

 1184 13:54:20.001578  DQM Delay:

 1185 13:54:20.002074  DQM0 = 93, DQM1 = 83

 1186 13:54:20.004898  DQ Delay:

 1187 13:54:20.008274  DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88

 1188 13:54:20.008800  DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104

 1189 13:54:20.011410  DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80

 1190 13:54:20.015050  DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92

 1191 13:54:20.018274  

 1192 13:54:20.018783  

 1193 13:54:20.024988  [DQSOSCAuto] RK0, (LSB)MR18= 0x3a35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps

 1194 13:54:20.028339  CH0 RK0: MR19=606, MR18=3A35

 1195 13:54:20.034930  CH0_RK0: MR19=0x606, MR18=0x3A35, DQSOSC=395, MR23=63, INC=94, DEC=63

 1196 13:54:20.035442  

 1197 13:54:20.038263  ----->DramcWriteLeveling(PI) begin...

 1198 13:54:20.038745  ==

 1199 13:54:20.041795  Dram Type= 6, Freq= 0, CH_0, rank 1

 1200 13:54:20.044718  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1201 13:54:20.045057  ==

 1202 13:54:20.048189  Write leveling (Byte 0): 33 => 33

 1203 13:54:20.051183  Write leveling (Byte 1): 31 => 31

 1204 13:54:20.054585  DramcWriteLeveling(PI) end<-----

 1205 13:54:20.054781  

 1206 13:54:20.054935  ==

 1207 13:54:20.057844  Dram Type= 6, Freq= 0, CH_0, rank 1

 1208 13:54:20.061670  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1209 13:54:20.061834  ==

 1210 13:54:20.064495  [Gating] SW mode calibration

 1211 13:54:20.071612  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1212 13:54:20.078086  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1213 13:54:20.081189   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1214 13:54:20.084620   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1215 13:54:20.091120   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1216 13:54:20.094705   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1217 13:54:20.097976   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1218 13:54:20.104480   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1219 13:54:20.107992   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1220 13:54:20.152216   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1221 13:54:20.152516   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1222 13:54:20.153208   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1223 13:54:20.153309   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1224 13:54:20.153846   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1225 13:54:20.154166   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1226 13:54:20.154450   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1227 13:54:20.154591   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1228 13:54:20.154697   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1229 13:54:20.155026   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1230 13:54:20.196309   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1231 13:54:20.196511   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1232 13:54:20.196657   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1233 13:54:20.197043   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1234 13:54:20.197223   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1235 13:54:20.197407   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1236 13:54:20.197750   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1237 13:54:20.197885   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1238 13:54:20.198066   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1239 13:54:20.198532   0  9  8 | B1->B0 | 2a2a 3434 | 1 0 | (1 1) (0 0)

 1240 13:54:20.218310   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1241 13:54:20.218656   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1242 13:54:20.218859   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1243 13:54:20.219336   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1244 13:54:20.221816   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1245 13:54:20.225074   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1246 13:54:20.228417   0 10  4 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)

 1247 13:54:20.231748   0 10  8 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)

 1248 13:54:20.235133   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1249 13:54:20.238450   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1250 13:54:20.244973   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1251 13:54:20.248658   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1252 13:54:20.251944   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1253 13:54:20.258276   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1254 13:54:20.261143   0 11  4 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)

 1255 13:54:20.264876   0 11  8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)

 1256 13:54:20.271448   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1257 13:54:20.275191   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1258 13:54:20.278019   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1259 13:54:20.285004   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1260 13:54:20.288294   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1261 13:54:20.292559   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1262 13:54:20.295955   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1263 13:54:20.299757   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1264 13:54:20.306300   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1265 13:54:20.309683   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1266 13:54:20.313323   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1267 13:54:20.319864   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1268 13:54:20.323536   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1269 13:54:20.326785   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1270 13:54:20.330095   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1271 13:54:20.336700   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1272 13:54:20.340093   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1273 13:54:20.343379   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1274 13:54:20.350144   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1275 13:54:20.353481   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1276 13:54:20.357153   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1277 13:54:20.363750   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1278 13:54:20.366927   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1279 13:54:20.370690   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1280 13:54:20.373853  Total UI for P1: 0, mck2ui 16

 1281 13:54:20.377253  best dqsien dly found for B0: ( 0, 14,  4)

 1282 13:54:20.380581  Total UI for P1: 0, mck2ui 16

 1283 13:54:20.383694  best dqsien dly found for B1: ( 0, 14,  6)

 1284 13:54:20.386860  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1285 13:54:20.390174  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1286 13:54:20.390260  

 1287 13:54:20.393650  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1288 13:54:20.400641  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1289 13:54:20.400728  [Gating] SW calibration Done

 1290 13:54:20.400813  ==

 1291 13:54:20.403846  Dram Type= 6, Freq= 0, CH_0, rank 1

 1292 13:54:20.410381  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1293 13:54:20.410479  ==

 1294 13:54:20.410556  RX Vref Scan: 0

 1295 13:54:20.410626  

 1296 13:54:20.413526  RX Vref 0 -> 0, step: 1

 1297 13:54:20.413629  

 1298 13:54:20.417317  RX Delay -130 -> 252, step: 16

 1299 13:54:20.420528  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1300 13:54:20.423616  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

 1301 13:54:20.427174  iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224

 1302 13:54:20.433708  iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208

 1303 13:54:20.437237  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1304 13:54:20.440871  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

 1305 13:54:20.444276  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1306 13:54:20.447388  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1307 13:54:20.450638  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1308 13:54:20.457466  iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208

 1309 13:54:20.460904  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

 1310 13:54:20.464127  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1311 13:54:20.467395  iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208

 1312 13:54:20.474053  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1313 13:54:20.477623  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1314 13:54:20.481114  iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208

 1315 13:54:20.481684  ==

 1316 13:54:20.484233  Dram Type= 6, Freq= 0, CH_0, rank 1

 1317 13:54:20.487428  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1318 13:54:20.487903  ==

 1319 13:54:20.490808  DQS Delay:

 1320 13:54:20.491270  DQS0 = 0, DQS1 = 0

 1321 13:54:20.494055  DQM Delay:

 1322 13:54:20.494520  DQM0 = 91, DQM1 = 83

 1323 13:54:20.494944  DQ Delay:

 1324 13:54:20.497495  DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85

 1325 13:54:20.500818  DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93

 1326 13:54:20.504513  DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =85

 1327 13:54:20.507262  DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85

 1328 13:54:20.507733  

 1329 13:54:20.508117  

 1330 13:54:20.508457  ==

 1331 13:54:20.510765  Dram Type= 6, Freq= 0, CH_0, rank 1

 1332 13:54:20.517639  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1333 13:54:20.518259  ==

 1334 13:54:20.518634  

 1335 13:54:20.518974  

 1336 13:54:20.519305  	TX Vref Scan disable

 1337 13:54:20.521272   == TX Byte 0 ==

 1338 13:54:20.524949  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

 1339 13:54:20.527986  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

 1340 13:54:20.531389   == TX Byte 1 ==

 1341 13:54:20.534609  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1342 13:54:20.537680  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1343 13:54:20.541387  ==

 1344 13:54:20.544974  Dram Type= 6, Freq= 0, CH_0, rank 1

 1345 13:54:20.547778  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1346 13:54:20.548265  ==

 1347 13:54:20.560265  TX Vref=22, minBit 8, minWin=27, winSum=451

 1348 13:54:20.563598  TX Vref=24, minBit 8, minWin=27, winSum=449

 1349 13:54:20.566833  TX Vref=26, minBit 8, minWin=27, winSum=451

 1350 13:54:20.570407  TX Vref=28, minBit 8, minWin=27, winSum=454

 1351 13:54:20.573919  TX Vref=30, minBit 8, minWin=27, winSum=457

 1352 13:54:20.577041  TX Vref=32, minBit 6, minWin=28, winSum=461

 1353 13:54:20.584272  [TxChooseVref] Worse bit 6, Min win 28, Win sum 461, Final Vref 32

 1354 13:54:20.584853  

 1355 13:54:20.587360  Final TX Range 1 Vref 32

 1356 13:54:20.587831  

 1357 13:54:20.588202  ==

 1358 13:54:20.590619  Dram Type= 6, Freq= 0, CH_0, rank 1

 1359 13:54:20.594045  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1360 13:54:20.594510  ==

 1361 13:54:20.594942  

 1362 13:54:20.597014  

 1363 13:54:20.597493  	TX Vref Scan disable

 1364 13:54:20.600387   == TX Byte 0 ==

 1365 13:54:20.603912  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

 1366 13:54:20.607218  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

 1367 13:54:20.610625   == TX Byte 1 ==

 1368 13:54:20.613786  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1369 13:54:20.616921  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1370 13:54:20.620267  

 1371 13:54:20.620647  [DATLAT]

 1372 13:54:20.620908  Freq=800, CH0 RK1

 1373 13:54:20.621147  

 1374 13:54:20.623911  DATLAT Default: 0xa

 1375 13:54:20.624356  0, 0xFFFF, sum = 0

 1376 13:54:20.627140  1, 0xFFFF, sum = 0

 1377 13:54:20.627571  2, 0xFFFF, sum = 0

 1378 13:54:20.630529  3, 0xFFFF, sum = 0

 1379 13:54:20.630965  4, 0xFFFF, sum = 0

 1380 13:54:20.634534  5, 0xFFFF, sum = 0

 1381 13:54:20.634966  6, 0xFFFF, sum = 0

 1382 13:54:20.637199  7, 0xFFFF, sum = 0

 1383 13:54:20.640709  8, 0xFFFF, sum = 0

 1384 13:54:20.641142  9, 0x0, sum = 1

 1385 13:54:20.641405  10, 0x0, sum = 2

 1386 13:54:20.643649  11, 0x0, sum = 3

 1387 13:54:20.643977  12, 0x0, sum = 4

 1388 13:54:20.647560  best_step = 10

 1389 13:54:20.647891  

 1390 13:54:20.648144  ==

 1391 13:54:20.650724  Dram Type= 6, Freq= 0, CH_0, rank 1

 1392 13:54:20.653505  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1393 13:54:20.653923  ==

 1394 13:54:20.657259  RX Vref Scan: 0

 1395 13:54:20.657712  

 1396 13:54:20.658100  RX Vref 0 -> 0, step: 1

 1397 13:54:20.658443  

 1398 13:54:20.660802  RX Delay -79 -> 252, step: 8

 1399 13:54:20.667389  iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224

 1400 13:54:20.670396  iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224

 1401 13:54:20.674080  iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224

 1402 13:54:20.677065  iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216

 1403 13:54:20.680797  iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216

 1404 13:54:20.687011  iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216

 1405 13:54:20.690373  iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216

 1406 13:54:20.693892  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1407 13:54:20.697382  iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208

 1408 13:54:20.700393  iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208

 1409 13:54:20.707296  iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208

 1410 13:54:20.710676  iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208

 1411 13:54:20.713446  iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216

 1412 13:54:20.716761  iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216

 1413 13:54:20.720287  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1414 13:54:20.727183  iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216

 1415 13:54:20.727649  ==

 1416 13:54:20.730490  Dram Type= 6, Freq= 0, CH_0, rank 1

 1417 13:54:20.733707  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1418 13:54:20.734196  ==

 1419 13:54:20.734560  DQS Delay:

 1420 13:54:20.737436  DQS0 = 0, DQS1 = 0

 1421 13:54:20.738033  DQM Delay:

 1422 13:54:20.740797  DQM0 = 91, DQM1 = 82

 1423 13:54:20.741354  DQ Delay:

 1424 13:54:20.743660  DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84

 1425 13:54:20.747721  DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100

 1426 13:54:20.750549  DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80

 1427 13:54:20.754509  DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92

 1428 13:54:20.755067  

 1429 13:54:20.755432  

 1430 13:54:20.760464  [DQSOSCAuto] RK1, (LSB)MR18= 0x461f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps

 1431 13:54:20.763889  CH0 RK1: MR19=606, MR18=461F

 1432 13:54:20.770521  CH0_RK1: MR19=0x606, MR18=0x461F, DQSOSC=392, MR23=63, INC=96, DEC=64

 1433 13:54:20.774266  [RxdqsGatingPostProcess] freq 800

 1434 13:54:20.780981  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1435 13:54:20.781543  Pre-setting of DQS Precalculation

 1436 13:54:20.787345  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1437 13:54:20.787933  ==

 1438 13:54:20.790583  Dram Type= 6, Freq= 0, CH_1, rank 0

 1439 13:54:20.794071  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1440 13:54:20.794555  ==

 1441 13:54:20.801051  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1442 13:54:20.807420  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1443 13:54:20.815455  [CA 0] Center 36 (6~67) winsize 62

 1444 13:54:20.818907  [CA 1] Center 36 (6~67) winsize 62

 1445 13:54:20.822056  [CA 2] Center 35 (5~65) winsize 61

 1446 13:54:20.825504  [CA 3] Center 34 (4~65) winsize 62

 1447 13:54:20.829274  [CA 4] Center 34 (4~65) winsize 62

 1448 13:54:20.832546  [CA 5] Center 34 (3~65) winsize 63

 1449 13:54:20.833120  

 1450 13:54:20.835667  [CmdBusTrainingLP45] Vref(ca) range 1: 30

 1451 13:54:20.836140  

 1452 13:54:20.838802  [CATrainingPosCal] consider 1 rank data

 1453 13:54:20.842343  u2DelayCellTimex100 = 270/100 ps

 1454 13:54:20.845711  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1455 13:54:20.849293  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1456 13:54:20.855699  CA2 delay=35 (5~65),Diff = 1 PI (7 cell)

 1457 13:54:20.858926  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1458 13:54:20.862410  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1459 13:54:20.865595  CA5 delay=34 (3~65),Diff = 0 PI (0 cell)

 1460 13:54:20.866105  

 1461 13:54:20.869000  CA PerBit enable=1, Macro0, CA PI delay=34

 1462 13:54:20.869470  

 1463 13:54:20.872766  [CBTSetCACLKResult] CA Dly = 34

 1464 13:54:20.873364  CS Dly: 5 (0~36)

 1465 13:54:20.873742  ==

 1466 13:54:20.875434  Dram Type= 6, Freq= 0, CH_1, rank 1

 1467 13:54:20.882904  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1468 13:54:20.883478  ==

 1469 13:54:20.885990  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1470 13:54:20.892041  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1471 13:54:20.901530  [CA 0] Center 37 (6~68) winsize 63

 1472 13:54:20.905069  [CA 1] Center 37 (6~68) winsize 63

 1473 13:54:20.908048  [CA 2] Center 35 (5~66) winsize 62

 1474 13:54:20.911733  [CA 3] Center 34 (4~65) winsize 62

 1475 13:54:20.915120  [CA 4] Center 34 (4~65) winsize 62

 1476 13:54:20.918385  [CA 5] Center 34 (4~64) winsize 61

 1477 13:54:20.918850  

 1478 13:54:20.921611  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1479 13:54:20.921966  

 1480 13:54:20.925237  [CATrainingPosCal] consider 2 rank data

 1481 13:54:20.928820  u2DelayCellTimex100 = 270/100 ps

 1482 13:54:20.931941  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1483 13:54:20.935110  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1484 13:54:20.938454  CA2 delay=35 (5~65),Diff = 1 PI (7 cell)

 1485 13:54:20.945040  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1486 13:54:20.948211  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1487 13:54:20.952161  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1488 13:54:20.952695  

 1489 13:54:20.955606  CA PerBit enable=1, Macro0, CA PI delay=34

 1490 13:54:20.956078  

 1491 13:54:20.959435  [CBTSetCACLKResult] CA Dly = 34

 1492 13:54:20.959906  CS Dly: 6 (0~38)

 1493 13:54:20.960309  

 1494 13:54:20.963205  ----->DramcWriteLeveling(PI) begin...

 1495 13:54:20.963717  ==

 1496 13:54:20.967065  Dram Type= 6, Freq= 0, CH_1, rank 0

 1497 13:54:20.970869  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1498 13:54:20.971554  ==

 1499 13:54:20.974089  Write leveling (Byte 0): 25 => 25

 1500 13:54:20.978575  Write leveling (Byte 1): 30 => 30

 1501 13:54:20.979070  DramcWriteLeveling(PI) end<-----

 1502 13:54:20.979552  

 1503 13:54:20.982226  ==

 1504 13:54:20.982701  Dram Type= 6, Freq= 0, CH_1, rank 0

 1505 13:54:20.989415  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1506 13:54:20.990090  ==

 1507 13:54:20.990678  [Gating] SW mode calibration

 1508 13:54:20.999446  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1509 13:54:21.002492  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1510 13:54:21.005743   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1511 13:54:21.012312   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1512 13:54:21.015373   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1513 13:54:21.019206   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1514 13:54:21.025523   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1515 13:54:21.029258   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1516 13:54:21.032237   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1517 13:54:21.038871   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1518 13:54:21.042164   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1519 13:54:21.045515   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1520 13:54:21.052102   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1521 13:54:21.055674   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1522 13:54:21.058833   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1523 13:54:21.065479   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1524 13:54:21.069332   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1525 13:54:21.072325   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1526 13:54:21.078785   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1527 13:54:21.082070   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)

 1528 13:54:21.085794   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1529 13:54:21.088795   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1530 13:54:21.095785   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1531 13:54:21.099335   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1532 13:54:21.102405   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1533 13:54:21.108684   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1534 13:54:21.112319   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1535 13:54:21.115609   0  9  4 | B1->B0 | 2323 2c2c | 1 1 | (1 1) (1 1)

 1536 13:54:21.121985   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1537 13:54:21.125335   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1538 13:54:21.129132   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1539 13:54:21.135510   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1540 13:54:21.138673   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1541 13:54:21.142058   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1542 13:54:21.149137   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1543 13:54:21.152115   0 10  4 | B1->B0 | 2c2c 2d2d | 1 0 | (1 0) (0 0)

 1544 13:54:21.155468   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1545 13:54:21.162195   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1546 13:54:21.165505   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1547 13:54:21.168936   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1548 13:54:21.175548   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1549 13:54:21.179431   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1550 13:54:21.182560   0 11  0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 1551 13:54:21.185898   0 11  4 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (1 1)

 1552 13:54:21.192374   0 11  8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 1553 13:54:21.195814   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1554 13:54:21.199316   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1555 13:54:21.206237   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1556 13:54:21.209320   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1557 13:54:21.212639   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1558 13:54:21.219081   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1559 13:54:21.222593   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1560 13:54:21.225602   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1561 13:54:21.232955   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1562 13:54:21.236651   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1563 13:54:21.239713   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1564 13:54:21.246080   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1565 13:54:21.249684   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1566 13:54:21.252627   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1567 13:54:21.259485   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1568 13:54:21.263049   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1569 13:54:21.265988   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1570 13:54:21.269586   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1571 13:54:21.276332   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1572 13:54:21.279525   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1573 13:54:21.282477   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1574 13:54:21.289074   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1575 13:54:21.292379   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1576 13:54:21.296151   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1577 13:54:21.299516  Total UI for P1: 0, mck2ui 16

 1578 13:54:21.302336  best dqsien dly found for B0: ( 0, 14,  4)

 1579 13:54:21.305719  Total UI for P1: 0, mck2ui 16

 1580 13:54:21.309030  best dqsien dly found for B1: ( 0, 14,  4)

 1581 13:54:21.312181  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1582 13:54:21.315866  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1583 13:54:21.319304  

 1584 13:54:21.322332  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1585 13:54:21.325621  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1586 13:54:21.329385  [Gating] SW calibration Done

 1587 13:54:21.329651  ==

 1588 13:54:21.332174  Dram Type= 6, Freq= 0, CH_1, rank 0

 1589 13:54:21.335830  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1590 13:54:21.336123  ==

 1591 13:54:21.336363  RX Vref Scan: 0

 1592 13:54:21.336536  

 1593 13:54:21.339133  RX Vref 0 -> 0, step: 1

 1594 13:54:21.339418  

 1595 13:54:21.342532  RX Delay -130 -> 252, step: 16

 1596 13:54:21.345678  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1597 13:54:21.348863  iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224

 1598 13:54:21.355495  iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224

 1599 13:54:21.358811  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

 1600 13:54:21.362140  iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208

 1601 13:54:21.365580  iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208

 1602 13:54:21.368900  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1603 13:54:21.372241  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1604 13:54:21.378716  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1605 13:54:21.382345  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1606 13:54:21.385783  iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224

 1607 13:54:21.388920  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1608 13:54:21.395292  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1609 13:54:21.399110  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1610 13:54:21.402753  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1611 13:54:21.405626  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1612 13:54:21.405709  ==

 1613 13:54:21.408968  Dram Type= 6, Freq= 0, CH_1, rank 0

 1614 13:54:21.411937  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1615 13:54:21.415578  ==

 1616 13:54:21.415653  DQS Delay:

 1617 13:54:21.415716  DQS0 = 0, DQS1 = 0

 1618 13:54:21.418843  DQM Delay:

 1619 13:54:21.418925  DQM0 = 90, DQM1 = 87

 1620 13:54:21.422192  DQ Delay:

 1621 13:54:21.422267  DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93

 1622 13:54:21.425246  DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93

 1623 13:54:21.428874  DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77

 1624 13:54:21.432262  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1625 13:54:21.435705  

 1626 13:54:21.435791  

 1627 13:54:21.435877  ==

 1628 13:54:21.438682  Dram Type= 6, Freq= 0, CH_1, rank 0

 1629 13:54:21.442296  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1630 13:54:21.442382  ==

 1631 13:54:21.442468  

 1632 13:54:21.442547  

 1633 13:54:21.445424  	TX Vref Scan disable

 1634 13:54:21.445523   == TX Byte 0 ==

 1635 13:54:21.452058  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 1636 13:54:21.455320  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 1637 13:54:21.455406   == TX Byte 1 ==

 1638 13:54:21.462436  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1639 13:54:21.465381  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1640 13:54:21.465513  ==

 1641 13:54:21.468909  Dram Type= 6, Freq= 0, CH_1, rank 0

 1642 13:54:21.471887  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1643 13:54:21.471974  ==

 1644 13:54:21.486242  TX Vref=22, minBit 8, minWin=27, winSum=448

 1645 13:54:21.490027  TX Vref=24, minBit 15, minWin=27, winSum=455

 1646 13:54:21.493193  TX Vref=26, minBit 15, minWin=27, winSum=457

 1647 13:54:21.496500  TX Vref=28, minBit 9, minWin=28, winSum=460

 1648 13:54:21.499581  TX Vref=30, minBit 15, minWin=27, winSum=457

 1649 13:54:21.506646  TX Vref=32, minBit 12, minWin=27, winSum=458

 1650 13:54:21.509604  [TxChooseVref] Worse bit 9, Min win 28, Win sum 460, Final Vref 28

 1651 13:54:21.510075  

 1652 13:54:21.513395  Final TX Range 1 Vref 28

 1653 13:54:21.513972  

 1654 13:54:21.514423  ==

 1655 13:54:21.517246  Dram Type= 6, Freq= 0, CH_1, rank 0

 1656 13:54:21.520011  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1657 13:54:21.523447  ==

 1658 13:54:21.524048  

 1659 13:54:21.524536  

 1660 13:54:21.524987  	TX Vref Scan disable

 1661 13:54:21.527257   == TX Byte 0 ==

 1662 13:54:21.529920  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 1663 13:54:21.534675  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 1664 13:54:21.537753   == TX Byte 1 ==

 1665 13:54:21.541342  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1666 13:54:21.544712  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1667 13:54:21.545185  

 1668 13:54:21.547752  [DATLAT]

 1669 13:54:21.548322  Freq=800, CH1 RK0

 1670 13:54:21.548694  

 1671 13:54:21.551266  DATLAT Default: 0xa

 1672 13:54:21.551837  0, 0xFFFF, sum = 0

 1673 13:54:21.554890  1, 0xFFFF, sum = 0

 1674 13:54:21.555473  2, 0xFFFF, sum = 0

 1675 13:54:21.557986  3, 0xFFFF, sum = 0

 1676 13:54:21.558567  4, 0xFFFF, sum = 0

 1677 13:54:21.561479  5, 0xFFFF, sum = 0

 1678 13:54:21.562329  6, 0xFFFF, sum = 0

 1679 13:54:21.564452  7, 0xFFFF, sum = 0

 1680 13:54:21.564926  8, 0xFFFF, sum = 0

 1681 13:54:21.568080  9, 0x0, sum = 1

 1682 13:54:21.568554  10, 0x0, sum = 2

 1683 13:54:21.571261  11, 0x0, sum = 3

 1684 13:54:21.571857  12, 0x0, sum = 4

 1685 13:54:21.574468  best_step = 10

 1686 13:54:21.574937  

 1687 13:54:21.575306  ==

 1688 13:54:21.577518  Dram Type= 6, Freq= 0, CH_1, rank 0

 1689 13:54:21.581041  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1690 13:54:21.581514  ==

 1691 13:54:21.581883  RX Vref Scan: 1

 1692 13:54:21.582289  

 1693 13:54:21.584276  Set Vref Range= 32 -> 127

 1694 13:54:21.584744  

 1695 13:54:21.587972  RX Vref 32 -> 127, step: 1

 1696 13:54:21.588469  

 1697 13:54:21.591342  RX Delay -79 -> 252, step: 8

 1698 13:54:21.591859  

 1699 13:54:21.594703  Set Vref, RX VrefLevel [Byte0]: 32

 1700 13:54:21.597676                           [Byte1]: 32

 1701 13:54:21.598174  

 1702 13:54:21.601763  Set Vref, RX VrefLevel [Byte0]: 33

 1703 13:54:21.604709                           [Byte1]: 33

 1704 13:54:21.605280  

 1705 13:54:21.608273  Set Vref, RX VrefLevel [Byte0]: 34

 1706 13:54:21.611129                           [Byte1]: 34

 1707 13:54:21.614518  

 1708 13:54:21.614987  Set Vref, RX VrefLevel [Byte0]: 35

 1709 13:54:21.618127                           [Byte1]: 35

 1710 13:54:21.622570  

 1711 13:54:21.623143  Set Vref, RX VrefLevel [Byte0]: 36

 1712 13:54:21.625585                           [Byte1]: 36

 1713 13:54:21.630350  

 1714 13:54:21.630921  Set Vref, RX VrefLevel [Byte0]: 37

 1715 13:54:21.633496                           [Byte1]: 37

 1716 13:54:21.637355  

 1717 13:54:21.637935  Set Vref, RX VrefLevel [Byte0]: 38

 1718 13:54:21.640754                           [Byte1]: 38

 1719 13:54:21.645049  

 1720 13:54:21.645620  Set Vref, RX VrefLevel [Byte0]: 39

 1721 13:54:21.648220                           [Byte1]: 39

 1722 13:54:21.652722  

 1723 13:54:21.653373  Set Vref, RX VrefLevel [Byte0]: 40

 1724 13:54:21.655601                           [Byte1]: 40

 1725 13:54:21.659798  

 1726 13:54:21.660269  Set Vref, RX VrefLevel [Byte0]: 41

 1727 13:54:21.663239                           [Byte1]: 41

 1728 13:54:21.667628  

 1729 13:54:21.668110  Set Vref, RX VrefLevel [Byte0]: 42

 1730 13:54:21.670762                           [Byte1]: 42

 1731 13:54:21.674909  

 1732 13:54:21.675489  Set Vref, RX VrefLevel [Byte0]: 43

 1733 13:54:21.678381                           [Byte1]: 43

 1734 13:54:21.682439  

 1735 13:54:21.683004  Set Vref, RX VrefLevel [Byte0]: 44

 1736 13:54:21.685832                           [Byte1]: 44

 1737 13:54:21.690047  

 1738 13:54:21.690515  Set Vref, RX VrefLevel [Byte0]: 45

 1739 13:54:21.693531                           [Byte1]: 45

 1740 13:54:21.697297  

 1741 13:54:21.697768  Set Vref, RX VrefLevel [Byte0]: 46

 1742 13:54:21.701028                           [Byte1]: 46

 1743 13:54:21.705159  

 1744 13:54:21.705625  Set Vref, RX VrefLevel [Byte0]: 47

 1745 13:54:21.708375                           [Byte1]: 47

 1746 13:54:21.712933  

 1747 13:54:21.713512  Set Vref, RX VrefLevel [Byte0]: 48

 1748 13:54:21.716167                           [Byte1]: 48

 1749 13:54:21.720483  

 1750 13:54:21.721032  Set Vref, RX VrefLevel [Byte0]: 49

 1751 13:54:21.723667                           [Byte1]: 49

 1752 13:54:21.728127  

 1753 13:54:21.728695  Set Vref, RX VrefLevel [Byte0]: 50

 1754 13:54:21.731366                           [Byte1]: 50

 1755 13:54:21.736042  

 1756 13:54:21.736611  Set Vref, RX VrefLevel [Byte0]: 51

 1757 13:54:21.738561                           [Byte1]: 51

 1758 13:54:21.743191  

 1759 13:54:21.743762  Set Vref, RX VrefLevel [Byte0]: 52

 1760 13:54:21.746657                           [Byte1]: 52

 1761 13:54:21.750768  

 1762 13:54:21.751338  Set Vref, RX VrefLevel [Byte0]: 53

 1763 13:54:21.754243                           [Byte1]: 53

 1764 13:54:21.758546  

 1765 13:54:21.759120  Set Vref, RX VrefLevel [Byte0]: 54

 1766 13:54:21.761710                           [Byte1]: 54

 1767 13:54:21.765806  

 1768 13:54:21.766363  Set Vref, RX VrefLevel [Byte0]: 55

 1769 13:54:21.769240                           [Byte1]: 55

 1770 13:54:21.773416  

 1771 13:54:21.774027  Set Vref, RX VrefLevel [Byte0]: 56

 1772 13:54:21.776624                           [Byte1]: 56

 1773 13:54:21.781031  

 1774 13:54:21.781607  Set Vref, RX VrefLevel [Byte0]: 57

 1775 13:54:21.784133                           [Byte1]: 57

 1776 13:54:21.788406  

 1777 13:54:21.789062  Set Vref, RX VrefLevel [Byte0]: 58

 1778 13:54:21.791384                           [Byte1]: 58

 1779 13:54:21.795954  

 1780 13:54:21.796534  Set Vref, RX VrefLevel [Byte0]: 59

 1781 13:54:21.799379                           [Byte1]: 59

 1782 13:54:21.803705  

 1783 13:54:21.804286  Set Vref, RX VrefLevel [Byte0]: 60

 1784 13:54:21.806664                           [Byte1]: 60

 1785 13:54:21.811077  

 1786 13:54:21.811557  Set Vref, RX VrefLevel [Byte0]: 61

 1787 13:54:21.813975                           [Byte1]: 61

 1788 13:54:21.818442  

 1789 13:54:21.818915  Set Vref, RX VrefLevel [Byte0]: 62

 1790 13:54:21.821498                           [Byte1]: 62

 1791 13:54:21.825646  

 1792 13:54:21.826155  Set Vref, RX VrefLevel [Byte0]: 63

 1793 13:54:21.829232                           [Byte1]: 63

 1794 13:54:21.833904  

 1795 13:54:21.834418  Set Vref, RX VrefLevel [Byte0]: 64

 1796 13:54:21.836961                           [Byte1]: 64

 1797 13:54:21.840855  

 1798 13:54:21.841288  Set Vref, RX VrefLevel [Byte0]: 65

 1799 13:54:21.844761                           [Byte1]: 65

 1800 13:54:21.848803  

 1801 13:54:21.849481  Set Vref, RX VrefLevel [Byte0]: 66

 1802 13:54:21.851814                           [Byte1]: 66

 1803 13:54:21.856371  

 1804 13:54:21.856909  Set Vref, RX VrefLevel [Byte0]: 67

 1805 13:54:21.859513                           [Byte1]: 67

 1806 13:54:21.863715  

 1807 13:54:21.864245  Set Vref, RX VrefLevel [Byte0]: 68

 1808 13:54:21.867203                           [Byte1]: 68

 1809 13:54:21.871136  

 1810 13:54:21.871609  Set Vref, RX VrefLevel [Byte0]: 69

 1811 13:54:21.874961                           [Byte1]: 69

 1812 13:54:21.878670  

 1813 13:54:21.879146  Set Vref, RX VrefLevel [Byte0]: 70

 1814 13:54:21.882371                           [Byte1]: 70

 1815 13:54:21.886862  

 1816 13:54:21.887427  Set Vref, RX VrefLevel [Byte0]: 71

 1817 13:54:21.890038                           [Byte1]: 71

 1818 13:54:21.894096  

 1819 13:54:21.894570  Set Vref, RX VrefLevel [Byte0]: 72

 1820 13:54:21.897119                           [Byte1]: 72

 1821 13:54:21.901476  

 1822 13:54:21.901999  Set Vref, RX VrefLevel [Byte0]: 73

 1823 13:54:21.904749                           [Byte1]: 73

 1824 13:54:21.909156  

 1825 13:54:21.909629  Set Vref, RX VrefLevel [Byte0]: 74

 1826 13:54:21.912512                           [Byte1]: 74

 1827 13:54:21.916742  

 1828 13:54:21.917306  Set Vref, RX VrefLevel [Byte0]: 75

 1829 13:54:21.919815                           [Byte1]: 75

 1830 13:54:21.924311  

 1831 13:54:21.924871  Final RX Vref Byte 0 = 51 to rank0

 1832 13:54:21.927410  Final RX Vref Byte 1 = 63 to rank0

 1833 13:54:21.931079  Final RX Vref Byte 0 = 51 to rank1

 1834 13:54:21.934552  Final RX Vref Byte 1 = 63 to rank1==

 1835 13:54:21.937624  Dram Type= 6, Freq= 0, CH_1, rank 0

 1836 13:54:21.941075  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1837 13:54:21.944567  ==

 1838 13:54:21.945131  DQS Delay:

 1839 13:54:21.945511  DQS0 = 0, DQS1 = 0

 1840 13:54:21.947758  DQM Delay:

 1841 13:54:21.948233  DQM0 = 92, DQM1 = 83

 1842 13:54:21.950809  DQ Delay:

 1843 13:54:21.953992  DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88

 1844 13:54:21.957353  DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88

 1845 13:54:21.957825  DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80

 1846 13:54:21.964699  DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88

 1847 13:54:21.965246  

 1848 13:54:21.965620  

 1849 13:54:21.970985  [DQSOSCAuto] RK0, (LSB)MR18= 0x314f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps

 1850 13:54:21.974159  CH1 RK0: MR19=606, MR18=314F

 1851 13:54:21.981250  CH1_RK0: MR19=0x606, MR18=0x314F, DQSOSC=390, MR23=63, INC=97, DEC=64

 1852 13:54:21.981834  

 1853 13:54:21.984524  ----->DramcWriteLeveling(PI) begin...

 1854 13:54:21.985100  ==

 1855 13:54:21.987735  Dram Type= 6, Freq= 0, CH_1, rank 1

 1856 13:54:21.990971  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1857 13:54:21.991544  ==

 1858 13:54:21.994217  Write leveling (Byte 0): 27 => 27

 1859 13:54:21.997997  Write leveling (Byte 1): 28 => 28

 1860 13:54:22.000954  DramcWriteLeveling(PI) end<-----

 1861 13:54:22.001424  

 1862 13:54:22.001795  ==

 1863 13:54:22.004477  Dram Type= 6, Freq= 0, CH_1, rank 1

 1864 13:54:22.007840  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1865 13:54:22.008487  ==

 1866 13:54:22.010808  [Gating] SW mode calibration

 1867 13:54:22.017571  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1868 13:54:22.024234  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1869 13:54:22.027863   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1870 13:54:22.030977   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1871 13:54:22.038084   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1872 13:54:22.041205   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1873 13:54:22.044341   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1874 13:54:22.051154   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1875 13:54:22.054585   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1876 13:54:22.057647   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1877 13:54:22.064270   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1878 13:54:22.067834   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1879 13:54:22.071094   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1880 13:54:22.074594   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1881 13:54:22.081217   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1882 13:54:22.085007   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1883 13:54:22.088147   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1884 13:54:22.094618   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1885 13:54:22.097776   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1886 13:54:22.101099   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1887 13:54:22.107903   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1888 13:54:22.111434   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1889 13:54:22.114431   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1890 13:54:22.121052   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1891 13:54:22.124654   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1892 13:54:22.128221   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1893 13:54:22.134587   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1894 13:54:22.137853   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1895 13:54:22.141685   0  9  8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)

 1896 13:54:22.145188   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1897 13:54:22.151267   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1898 13:54:22.154875   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1899 13:54:22.157802   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1900 13:54:22.164441   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1901 13:54:22.167992   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1902 13:54:22.171097   0 10  4 | B1->B0 | 2d2d 3131 | 1 1 | (1 0) (1 1)

 1903 13:54:22.178046   0 10  8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 1904 13:54:22.181401   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1905 13:54:22.185065   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1906 13:54:22.191340   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1907 13:54:22.194984   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1908 13:54:22.198161   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1909 13:54:22.204718   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1910 13:54:22.208152   0 11  4 | B1->B0 | 3838 3535 | 1 0 | (0 0) (0 0)

 1911 13:54:22.211652   0 11  8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)

 1912 13:54:22.217714   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1913 13:54:22.221333   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1914 13:54:22.224466   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1915 13:54:22.231051   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1916 13:54:22.234037   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1917 13:54:22.237670   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1918 13:54:22.244279   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1919 13:54:22.247816   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 1920 13:54:22.250599   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1921 13:54:22.257534   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1922 13:54:22.260775   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1923 13:54:22.263985   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1924 13:54:22.267654   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1925 13:54:22.274468   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1926 13:54:22.277225   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1927 13:54:22.281023   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1928 13:54:22.287576   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1929 13:54:22.290852   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1930 13:54:22.294374   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1931 13:54:22.300968   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1932 13:54:22.304144   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1933 13:54:22.308144   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1934 13:54:22.314273   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1935 13:54:22.314761  Total UI for P1: 0, mck2ui 16

 1936 13:54:22.321104  best dqsien dly found for B1: ( 0, 14,  2)

 1937 13:54:22.324409   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1938 13:54:22.327914   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1939 13:54:22.331244  Total UI for P1: 0, mck2ui 16

 1940 13:54:22.334871  best dqsien dly found for B0: ( 0, 14,  6)

 1941 13:54:22.338060  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1942 13:54:22.341240  best DQS1 dly(MCK, UI, PI) = (0, 14, 2)

 1943 13:54:22.341713  

 1944 13:54:22.344477  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1945 13:54:22.348009  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1946 13:54:22.351223  [Gating] SW calibration Done

 1947 13:54:22.351832  ==

 1948 13:54:22.354855  Dram Type= 6, Freq= 0, CH_1, rank 1

 1949 13:54:22.361164  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1950 13:54:22.361729  ==

 1951 13:54:22.362143  RX Vref Scan: 0

 1952 13:54:22.362724  

 1953 13:54:22.364452  RX Vref 0 -> 0, step: 1

 1954 13:54:22.365009  

 1955 13:54:22.367780  RX Delay -130 -> 252, step: 16

 1956 13:54:22.370965  iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224

 1957 13:54:22.374795  iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208

 1958 13:54:22.378021  iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224

 1959 13:54:22.384831  iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224

 1960 13:54:22.387837  iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208

 1961 13:54:22.391312  iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224

 1962 13:54:22.394438  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1963 13:54:22.398104  iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208

 1964 13:54:22.401047  iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240

 1965 13:54:22.408028  iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224

 1966 13:54:22.411010  iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240

 1967 13:54:22.414722  iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224

 1968 13:54:22.418139  iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224

 1969 13:54:22.421179  iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240

 1970 13:54:22.428245  iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240

 1971 13:54:22.431474  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

 1972 13:54:22.432059  ==

 1973 13:54:22.434588  Dram Type= 6, Freq= 0, CH_1, rank 1

 1974 13:54:22.438007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1975 13:54:22.438603  ==

 1976 13:54:22.441316  DQS Delay:

 1977 13:54:22.441897  DQS0 = 0, DQS1 = 0

 1978 13:54:22.442330  DQM Delay:

 1979 13:54:22.444561  DQM0 = 88, DQM1 = 82

 1980 13:54:22.445306  DQ Delay:

 1981 13:54:22.447579  DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93

 1982 13:54:22.451369  DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85

 1983 13:54:22.454430  DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77

 1984 13:54:22.457977  DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85

 1985 13:54:22.458552  

 1986 13:54:22.459015  

 1987 13:54:22.459368  ==

 1988 13:54:22.461217  Dram Type= 6, Freq= 0, CH_1, rank 1

 1989 13:54:22.467806  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1990 13:54:22.468287  ==

 1991 13:54:22.468660  

 1992 13:54:22.469003  

 1993 13:54:22.469329  	TX Vref Scan disable

 1994 13:54:22.471146   == TX Byte 0 ==

 1995 13:54:22.474633  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1996 13:54:22.478399  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1997 13:54:22.481414   == TX Byte 1 ==

 1998 13:54:22.484743  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1999 13:54:22.488341  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 2000 13:54:22.491477  ==

 2001 13:54:22.494806  Dram Type= 6, Freq= 0, CH_1, rank 1

 2002 13:54:22.498356  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2003 13:54:22.498932  ==

 2004 13:54:22.510495  TX Vref=22, minBit 13, minWin=27, winSum=455

 2005 13:54:22.513897  TX Vref=24, minBit 3, minWin=28, winSum=458

 2006 13:54:22.517341  TX Vref=26, minBit 7, minWin=28, winSum=459

 2007 13:54:22.520343  TX Vref=28, minBit 8, minWin=28, winSum=462

 2008 13:54:22.523889  TX Vref=30, minBit 8, minWin=28, winSum=460

 2009 13:54:22.527584  TX Vref=32, minBit 8, minWin=28, winSum=460

 2010 13:54:22.533857  [TxChooseVref] Worse bit 8, Min win 28, Win sum 462, Final Vref 28

 2011 13:54:22.534458  

 2012 13:54:22.537191  Final TX Range 1 Vref 28

 2013 13:54:22.537763  

 2014 13:54:22.538181  ==

 2015 13:54:22.540156  Dram Type= 6, Freq= 0, CH_1, rank 1

 2016 13:54:22.543614  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2017 13:54:22.544089  ==

 2018 13:54:22.544466  

 2019 13:54:22.546949  

 2020 13:54:22.547417  	TX Vref Scan disable

 2021 13:54:22.550474   == TX Byte 0 ==

 2022 13:54:22.553759  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 2023 13:54:22.556724  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 2024 13:54:22.560163   == TX Byte 1 ==

 2025 13:54:22.563935  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 2026 13:54:22.566734  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 2027 13:54:22.570277  

 2028 13:54:22.570746  [DATLAT]

 2029 13:54:22.571119  Freq=800, CH1 RK1

 2030 13:54:22.571467  

 2031 13:54:22.573478  DATLAT Default: 0xa

 2032 13:54:22.573977  0, 0xFFFF, sum = 0

 2033 13:54:22.577024  1, 0xFFFF, sum = 0

 2034 13:54:22.577621  2, 0xFFFF, sum = 0

 2035 13:54:22.580072  3, 0xFFFF, sum = 0

 2036 13:54:22.580548  4, 0xFFFF, sum = 0

 2037 13:54:22.584290  5, 0xFFFF, sum = 0

 2038 13:54:22.584869  6, 0xFFFF, sum = 0

 2039 13:54:22.587026  7, 0xFFFF, sum = 0

 2040 13:54:22.587502  8, 0xFFFF, sum = 0

 2041 13:54:22.590284  9, 0x0, sum = 1

 2042 13:54:22.590768  10, 0x0, sum = 2

 2043 13:54:22.593858  11, 0x0, sum = 3

 2044 13:54:22.594396  12, 0x0, sum = 4

 2045 13:54:22.597096  best_step = 10

 2046 13:54:22.597567  

 2047 13:54:22.597935  ==

 2048 13:54:22.600422  Dram Type= 6, Freq= 0, CH_1, rank 1

 2049 13:54:22.603684  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2050 13:54:22.604160  ==

 2051 13:54:22.607013  RX Vref Scan: 0

 2052 13:54:22.607486  

 2053 13:54:22.607855  RX Vref 0 -> 0, step: 1

 2054 13:54:22.608204  

 2055 13:54:22.610480  RX Delay -95 -> 252, step: 8

 2056 13:54:22.617825  iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208

 2057 13:54:22.620853  iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200

 2058 13:54:22.623864  iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208

 2059 13:54:22.627436  iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208

 2060 13:54:22.630413  iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208

 2061 13:54:22.634055  iDelay=209, Bit 5, Center 108 (9 ~ 208) 200

 2062 13:54:22.640670  iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208

 2063 13:54:22.643895  iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208

 2064 13:54:22.647898  iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216

 2065 13:54:22.650712  iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224

 2066 13:54:22.653666  iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224

 2067 13:54:22.660603  iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224

 2068 13:54:22.663835  iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224

 2069 13:54:22.666763  iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224

 2070 13:54:22.670106  iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224

 2071 13:54:22.676738  iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224

 2072 13:54:22.677212  ==

 2073 13:54:22.680340  Dram Type= 6, Freq= 0, CH_1, rank 1

 2074 13:54:22.683630  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2075 13:54:22.684106  ==

 2076 13:54:22.684484  DQS Delay:

 2077 13:54:22.686808  DQS0 = 0, DQS1 = 0

 2078 13:54:22.687279  DQM Delay:

 2079 13:54:22.690234  DQM0 = 92, DQM1 = 82

 2080 13:54:22.690704  DQ Delay:

 2081 13:54:22.693901  DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88

 2082 13:54:22.697015  DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88

 2083 13:54:22.700412  DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80

 2084 13:54:22.703952  DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88

 2085 13:54:22.704448  

 2086 13:54:22.704825  

 2087 13:54:22.710554  [DQSOSCAuto] RK1, (LSB)MR18= 0x3d12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps

 2088 13:54:22.713628  CH1 RK1: MR19=606, MR18=3D12

 2089 13:54:22.720434  CH1_RK1: MR19=0x606, MR18=0x3D12, DQSOSC=394, MR23=63, INC=95, DEC=63

 2090 13:54:22.723800  [RxdqsGatingPostProcess] freq 800

 2091 13:54:22.727052  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2092 13:54:22.730199  Pre-setting of DQS Precalculation

 2093 13:54:22.737116  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2094 13:54:22.743608  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2095 13:54:22.750556  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2096 13:54:22.751155  

 2097 13:54:22.751534  

 2098 13:54:22.753640  [Calibration Summary] 1600 Mbps

 2099 13:54:22.756947  CH 0, Rank 0

 2100 13:54:22.757575  SW Impedance     : PASS

 2101 13:54:22.760308  DUTY Scan        : NO K

 2102 13:54:22.760864  ZQ Calibration   : PASS

 2103 13:54:22.763732  Jitter Meter     : NO K

 2104 13:54:22.766910  CBT Training     : PASS

 2105 13:54:22.767539  Write leveling   : PASS

 2106 13:54:22.770322  RX DQS gating    : PASS

 2107 13:54:22.773643  RX DQ/DQS(RDDQC) : PASS

 2108 13:54:22.774231  TX DQ/DQS        : PASS

 2109 13:54:22.776922  RX DATLAT        : PASS

 2110 13:54:22.781046  RX DQ/DQS(Engine): PASS

 2111 13:54:22.781631  TX OE            : NO K

 2112 13:54:22.783774  All Pass.

 2113 13:54:22.784246  

 2114 13:54:22.784618  CH 0, Rank 1

 2115 13:54:22.787054  SW Impedance     : PASS

 2116 13:54:22.787486  DUTY Scan        : NO K

 2117 13:54:22.790533  ZQ Calibration   : PASS

 2118 13:54:22.793792  Jitter Meter     : NO K

 2119 13:54:22.794417  CBT Training     : PASS

 2120 13:54:22.796944  Write leveling   : PASS

 2121 13:54:22.797418  RX DQS gating    : PASS

 2122 13:54:22.800869  RX DQ/DQS(RDDQC) : PASS

 2123 13:54:22.803823  TX DQ/DQS        : PASS

 2124 13:54:22.804305  RX DATLAT        : PASS

 2125 13:54:22.807400  RX DQ/DQS(Engine): PASS

 2126 13:54:22.810648  TX OE            : NO K

 2127 13:54:22.811128  All Pass.

 2128 13:54:22.811541  

 2129 13:54:22.811915  CH 1, Rank 0

 2130 13:54:22.814026  SW Impedance     : PASS

 2131 13:54:22.817141  DUTY Scan        : NO K

 2132 13:54:22.817615  ZQ Calibration   : PASS

 2133 13:54:22.820574  Jitter Meter     : NO K

 2134 13:54:22.824043  CBT Training     : PASS

 2135 13:54:22.824543  Write leveling   : PASS

 2136 13:54:22.827377  RX DQS gating    : PASS

 2137 13:54:22.830515  RX DQ/DQS(RDDQC) : PASS

 2138 13:54:22.830993  TX DQ/DQS        : PASS

 2139 13:54:22.833679  RX DATLAT        : PASS

 2140 13:54:22.837202  RX DQ/DQS(Engine): PASS

 2141 13:54:22.837680  TX OE            : NO K

 2142 13:54:22.838137  All Pass.

 2143 13:54:22.838503  

 2144 13:54:22.840458  CH 1, Rank 1

 2145 13:54:22.840928  SW Impedance     : PASS

 2146 13:54:22.843722  DUTY Scan        : NO K

 2147 13:54:22.847098  ZQ Calibration   : PASS

 2148 13:54:22.847574  Jitter Meter     : NO K

 2149 13:54:22.850705  CBT Training     : PASS

 2150 13:54:22.854155  Write leveling   : PASS

 2151 13:54:22.854717  RX DQS gating    : PASS

 2152 13:54:22.857696  RX DQ/DQS(RDDQC) : PASS

 2153 13:54:22.860804  TX DQ/DQS        : PASS

 2154 13:54:22.861383  RX DATLAT        : PASS

 2155 13:54:22.864108  RX DQ/DQS(Engine): PASS

 2156 13:54:22.866965  TX OE            : NO K

 2157 13:54:22.867441  All Pass.

 2158 13:54:22.867819  

 2159 13:54:22.868190  DramC Write-DBI off

 2160 13:54:22.870716  	PER_BANK_REFRESH: Hybrid Mode

 2161 13:54:22.873908  TX_TRACKING: ON

 2162 13:54:22.877367  [GetDramInforAfterCalByMRR] Vendor 6.

 2163 13:54:22.880724  [GetDramInforAfterCalByMRR] Revision 606.

 2164 13:54:22.883945  [GetDramInforAfterCalByMRR] Revision 2 0.

 2165 13:54:22.884520  MR0 0x3b3b

 2166 13:54:22.887216  MR8 0x5151

 2167 13:54:22.890737  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2168 13:54:22.891225  

 2169 13:54:22.891645  MR0 0x3b3b

 2170 13:54:22.891996  MR8 0x5151

 2171 13:54:22.893937  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2172 13:54:22.897607  

 2173 13:54:22.903967  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2174 13:54:22.907540  [FAST_K] Save calibration result to emmc

 2175 13:54:22.910548  [FAST_K] Save calibration result to emmc

 2176 13:54:22.913759  dram_init: config_dvfs: 1

 2177 13:54:22.917539  dramc_set_vcore_voltage set vcore to 662500

 2178 13:54:22.920853  Read voltage for 1200, 2

 2179 13:54:22.921423  Vio18 = 0

 2180 13:54:22.924004  Vcore = 662500

 2181 13:54:22.924577  Vdram = 0

 2182 13:54:22.924957  Vddq = 0

 2183 13:54:22.925304  Vmddr = 0

 2184 13:54:22.930587  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2185 13:54:22.937199  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2186 13:54:22.937677  MEM_TYPE=3, freq_sel=15

 2187 13:54:22.940273  sv_algorithm_assistance_LP4_1600 

 2188 13:54:22.944181  ============ PULL DRAM RESETB DOWN ============

 2189 13:54:22.951125  ========== PULL DRAM RESETB DOWN end =========

 2190 13:54:22.953877  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2191 13:54:22.957133  =================================== 

 2192 13:54:22.960688  LPDDR4 DRAM CONFIGURATION

 2193 13:54:22.964440  =================================== 

 2194 13:54:22.965015  EX_ROW_EN[0]    = 0x0

 2195 13:54:22.967495  EX_ROW_EN[1]    = 0x0

 2196 13:54:22.967967  LP4Y_EN      = 0x0

 2197 13:54:22.970648  WORK_FSP     = 0x0

 2198 13:54:22.971117  WL           = 0x4

 2199 13:54:22.974047  RL           = 0x4

 2200 13:54:22.974516  BL           = 0x2

 2201 13:54:22.977504  RPST         = 0x0

 2202 13:54:22.978003  RD_PRE       = 0x0

 2203 13:54:22.980756  WR_PRE       = 0x1

 2204 13:54:22.981351  WR_PST       = 0x0

 2205 13:54:22.984161  DBI_WR       = 0x0

 2206 13:54:22.984632  DBI_RD       = 0x0

 2207 13:54:22.987389  OTF          = 0x1

 2208 13:54:22.990844  =================================== 

 2209 13:54:22.993914  =================================== 

 2210 13:54:22.994537  ANA top config

 2211 13:54:22.997557  =================================== 

 2212 13:54:23.000900  DLL_ASYNC_EN            =  0

 2213 13:54:23.004149  ALL_SLAVE_EN            =  0

 2214 13:54:23.007029  NEW_RANK_MODE           =  1

 2215 13:54:23.007629  DLL_IDLE_MODE           =  1

 2216 13:54:23.010392  LP45_APHY_COMB_EN       =  1

 2217 13:54:23.013753  TX_ODT_DIS              =  1

 2218 13:54:23.017305  NEW_8X_MODE             =  1

 2219 13:54:23.020427  =================================== 

 2220 13:54:23.024282  =================================== 

 2221 13:54:23.027595  data_rate                  = 2400

 2222 13:54:23.028169  CKR                        = 1

 2223 13:54:23.030682  DQ_P2S_RATIO               = 8

 2224 13:54:23.034595  =================================== 

 2225 13:54:23.037789  CA_P2S_RATIO               = 8

 2226 13:54:23.040936  DQ_CA_OPEN                 = 0

 2227 13:54:23.044562  DQ_SEMI_OPEN               = 0

 2228 13:54:23.047430  CA_SEMI_OPEN               = 0

 2229 13:54:23.048004  CA_FULL_RATE               = 0

 2230 13:54:23.050936  DQ_CKDIV4_EN               = 0

 2231 13:54:23.054059  CA_CKDIV4_EN               = 0

 2232 13:54:23.057504  CA_PREDIV_EN               = 0

 2233 13:54:23.061423  PH8_DLY                    = 17

 2234 13:54:23.064863  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2235 13:54:23.065430  DQ_AAMCK_DIV               = 4

 2236 13:54:23.067737  CA_AAMCK_DIV               = 4

 2237 13:54:23.070995  CA_ADMCK_DIV               = 4

 2238 13:54:23.074530  DQ_TRACK_CA_EN             = 0

 2239 13:54:23.078152  CA_PICK                    = 1200

 2240 13:54:23.081314  CA_MCKIO                   = 1200

 2241 13:54:23.081794  MCKIO_SEMI                 = 0

 2242 13:54:23.084563  PLL_FREQ                   = 2366

 2243 13:54:23.087723  DQ_UI_PI_RATIO             = 32

 2244 13:54:23.091505  CA_UI_PI_RATIO             = 0

 2245 13:54:23.094489  =================================== 

 2246 13:54:23.097577  =================================== 

 2247 13:54:23.101460  memory_type:LPDDR4         

 2248 13:54:23.102117  GP_NUM     : 10       

 2249 13:54:23.104719  SRAM_EN    : 1       

 2250 13:54:23.107993  MD32_EN    : 0       

 2251 13:54:23.111090  =================================== 

 2252 13:54:23.111676  [ANA_INIT] >>>>>>>>>>>>>> 

 2253 13:54:23.114344  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2254 13:54:23.118001  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2255 13:54:23.120863  =================================== 

 2256 13:54:23.124524  data_rate = 2400,PCW = 0X5b00

 2257 13:54:23.128026  =================================== 

 2258 13:54:23.131598  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2259 13:54:23.137973  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2260 13:54:23.141172  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2261 13:54:23.147914  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2262 13:54:23.151420  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2263 13:54:23.154493  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2264 13:54:23.154976  [ANA_INIT] flow start 

 2265 13:54:23.158231  [ANA_INIT] PLL >>>>>>>> 

 2266 13:54:23.161355  [ANA_INIT] PLL <<<<<<<< 

 2267 13:54:23.161829  [ANA_INIT] MIDPI >>>>>>>> 

 2268 13:54:23.164796  [ANA_INIT] MIDPI <<<<<<<< 

 2269 13:54:23.168083  [ANA_INIT] DLL >>>>>>>> 

 2270 13:54:23.168589  [ANA_INIT] DLL <<<<<<<< 

 2271 13:54:23.171216  [ANA_INIT] flow end 

 2272 13:54:23.174432  ============ LP4 DIFF to SE enter ============

 2273 13:54:23.178097  ============ LP4 DIFF to SE exit  ============

 2274 13:54:23.181238  [ANA_INIT] <<<<<<<<<<<<< 

 2275 13:54:23.184559  [Flow] Enable top DCM control >>>>> 

 2276 13:54:23.188161  [Flow] Enable top DCM control <<<<< 

 2277 13:54:23.191862  Enable DLL master slave shuffle 

 2278 13:54:23.198259  ============================================================== 

 2279 13:54:23.198735  Gating Mode config

 2280 13:54:23.204619  ============================================================== 

 2281 13:54:23.205092  Config description: 

 2282 13:54:23.214635  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2283 13:54:23.221501  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2284 13:54:23.228791  SELPH_MODE            0: By rank         1: By Phase 

 2285 13:54:23.231346  ============================================================== 

 2286 13:54:23.234756  GAT_TRACK_EN                 =  1

 2287 13:54:23.238033  RX_GATING_MODE               =  2

 2288 13:54:23.241866  RX_GATING_TRACK_MODE         =  2

 2289 13:54:23.245098  SELPH_MODE                   =  1

 2290 13:54:23.248374  PICG_EARLY_EN                =  1

 2291 13:54:23.251747  VALID_LAT_VALUE              =  1

 2292 13:54:23.255001  ============================================================== 

 2293 13:54:23.257805  Enter into Gating configuration >>>> 

 2294 13:54:23.261634  Exit from Gating configuration <<<< 

 2295 13:54:23.264559  Enter into  DVFS_PRE_config >>>>> 

 2296 13:54:23.278257  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2297 13:54:23.281663  Exit from  DVFS_PRE_config <<<<< 

 2298 13:54:23.284731  Enter into PICG configuration >>>> 

 2299 13:54:23.285211  Exit from PICG configuration <<<< 

 2300 13:54:23.288566  [RX_INPUT] configuration >>>>> 

 2301 13:54:23.291793  [RX_INPUT] configuration <<<<< 

 2302 13:54:23.298541  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2303 13:54:23.301614  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2304 13:54:23.308385  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2305 13:54:23.314587  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2306 13:54:23.321706  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2307 13:54:23.328436  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2308 13:54:23.331449  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2309 13:54:23.334767  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2310 13:54:23.338058  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2311 13:54:23.344786  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2312 13:54:23.348211  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2313 13:54:23.351542  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2314 13:54:23.354588  =================================== 

 2315 13:54:23.358308  LPDDR4 DRAM CONFIGURATION

 2316 13:54:23.361824  =================================== 

 2317 13:54:23.362435  EX_ROW_EN[0]    = 0x0

 2318 13:54:23.364621  EX_ROW_EN[1]    = 0x0

 2319 13:54:23.367947  LP4Y_EN      = 0x0

 2320 13:54:23.368422  WORK_FSP     = 0x0

 2321 13:54:23.371157  WL           = 0x4

 2322 13:54:23.371630  RL           = 0x4

 2323 13:54:23.374638  BL           = 0x2

 2324 13:54:23.375110  RPST         = 0x0

 2325 13:54:23.378254  RD_PRE       = 0x0

 2326 13:54:23.378727  WR_PRE       = 0x1

 2327 13:54:23.381451  WR_PST       = 0x0

 2328 13:54:23.381922  DBI_WR       = 0x0

 2329 13:54:23.385059  DBI_RD       = 0x0

 2330 13:54:23.385486  OTF          = 0x1

 2331 13:54:23.388468  =================================== 

 2332 13:54:23.391473  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2333 13:54:23.398311  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2334 13:54:23.401545  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2335 13:54:23.404827  =================================== 

 2336 13:54:23.408497  LPDDR4 DRAM CONFIGURATION

 2337 13:54:23.411337  =================================== 

 2338 13:54:23.411816  EX_ROW_EN[0]    = 0x10

 2339 13:54:23.414981  EX_ROW_EN[1]    = 0x0

 2340 13:54:23.415448  LP4Y_EN      = 0x0

 2341 13:54:23.418180  WORK_FSP     = 0x0

 2342 13:54:23.418772  WL           = 0x4

 2343 13:54:23.421240  RL           = 0x4

 2344 13:54:23.425123  BL           = 0x2

 2345 13:54:23.425668  RPST         = 0x0

 2346 13:54:23.428233  RD_PRE       = 0x0

 2347 13:54:23.428759  WR_PRE       = 0x1

 2348 13:54:23.431572  WR_PST       = 0x0

 2349 13:54:23.432052  DBI_WR       = 0x0

 2350 13:54:23.435018  DBI_RD       = 0x0

 2351 13:54:23.435440  OTF          = 0x1

 2352 13:54:23.438180  =================================== 

 2353 13:54:23.444825  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2354 13:54:23.445396  ==

 2355 13:54:23.448268  Dram Type= 6, Freq= 0, CH_0, rank 0

 2356 13:54:23.451561  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2357 13:54:23.451992  ==

 2358 13:54:23.455070  [Duty_Offset_Calibration]

 2359 13:54:23.455642  	B0:2	B1:0	CA:1

 2360 13:54:23.458308  

 2361 13:54:23.461308  [DutyScan_Calibration_Flow] k_type=0

 2362 13:54:23.468348  

 2363 13:54:23.468773  ==CLK 0==

 2364 13:54:23.471613  Final CLK duty delay cell = -4

 2365 13:54:23.475006  [-4] MAX Duty = 5031%(X100), DQS PI = 22

 2366 13:54:23.478308  [-4] MIN Duty = 4875%(X100), DQS PI = 0

 2367 13:54:23.481811  [-4] AVG Duty = 4953%(X100)

 2368 13:54:23.482263  

 2369 13:54:23.485250  CH0 CLK Duty spec in!! Max-Min= 156%

 2370 13:54:23.488717  [DutyScan_Calibration_Flow] ====Done====

 2371 13:54:23.489140  

 2372 13:54:23.491999  [DutyScan_Calibration_Flow] k_type=1

 2373 13:54:23.507489  

 2374 13:54:23.508043  ==DQS 0 ==

 2375 13:54:23.510985  Final DQS duty delay cell = 0

 2376 13:54:23.513815  [0] MAX Duty = 5187%(X100), DQS PI = 30

 2377 13:54:23.517032  [0] MIN Duty = 4938%(X100), DQS PI = 0

 2378 13:54:23.517496  [0] AVG Duty = 5062%(X100)

 2379 13:54:23.520678  

 2380 13:54:23.521042  ==DQS 1 ==

 2381 13:54:23.524462  Final DQS duty delay cell = -4

 2382 13:54:23.527688  [-4] MAX Duty = 5124%(X100), DQS PI = 32

 2383 13:54:23.530808  [-4] MIN Duty = 4907%(X100), DQS PI = 8

 2384 13:54:23.533804  [-4] AVG Duty = 5015%(X100)

 2385 13:54:23.534389  

 2386 13:54:23.537414  CH0 DQS 0 Duty spec in!! Max-Min= 249%

 2387 13:54:23.538000  

 2388 13:54:23.540509  CH0 DQS 1 Duty spec in!! Max-Min= 217%

 2389 13:54:23.543870  [DutyScan_Calibration_Flow] ====Done====

 2390 13:54:23.544337  

 2391 13:54:23.547297  [DutyScan_Calibration_Flow] k_type=3

 2392 13:54:23.563886  

 2393 13:54:23.564458  ==DQM 0 ==

 2394 13:54:23.567303  Final DQM duty delay cell = 0

 2395 13:54:23.570788  [0] MAX Duty = 5062%(X100), DQS PI = 24

 2396 13:54:23.574055  [0] MIN Duty = 4813%(X100), DQS PI = 0

 2397 13:54:23.574520  [0] AVG Duty = 4937%(X100)

 2398 13:54:23.577561  

 2399 13:54:23.578050  ==DQM 1 ==

 2400 13:54:23.580841  Final DQM duty delay cell = 0

 2401 13:54:23.584518  [0] MAX Duty = 5187%(X100), DQS PI = 48

 2402 13:54:23.587573  [0] MIN Duty = 5000%(X100), DQS PI = 12

 2403 13:54:23.588146  [0] AVG Duty = 5093%(X100)

 2404 13:54:23.590700  

 2405 13:54:23.593936  CH0 DQM 0 Duty spec in!! Max-Min= 249%

 2406 13:54:23.594467  

 2407 13:54:23.597480  CH0 DQM 1 Duty spec in!! Max-Min= 187%

 2408 13:54:23.600981  [DutyScan_Calibration_Flow] ====Done====

 2409 13:54:23.601538  

 2410 13:54:23.604139  [DutyScan_Calibration_Flow] k_type=2

 2411 13:54:23.620729  

 2412 13:54:23.621309  ==DQ 0 ==

 2413 13:54:23.624226  Final DQ duty delay cell = -4

 2414 13:54:23.627519  [-4] MAX Duty = 5062%(X100), DQS PI = 34

 2415 13:54:23.630748  [-4] MIN Duty = 4875%(X100), DQS PI = 14

 2416 13:54:23.634295  [-4] AVG Duty = 4968%(X100)

 2417 13:54:23.634852  

 2418 13:54:23.635217  ==DQ 1 ==

 2419 13:54:23.637605  Final DQ duty delay cell = 4

 2420 13:54:23.640433  [4] MAX Duty = 5093%(X100), DQS PI = 4

 2421 13:54:23.643964  [4] MIN Duty = 5031%(X100), DQS PI = 16

 2422 13:54:23.644431  [4] AVG Duty = 5062%(X100)

 2423 13:54:23.647145  

 2424 13:54:23.650575  CH0 DQ 0 Duty spec in!! Max-Min= 187%

 2425 13:54:23.651045  

 2426 13:54:23.654073  CH0 DQ 1 Duty spec in!! Max-Min= 62%

 2427 13:54:23.657622  [DutyScan_Calibration_Flow] ====Done====

 2428 13:54:23.658241  ==

 2429 13:54:23.660887  Dram Type= 6, Freq= 0, CH_1, rank 0

 2430 13:54:23.664341  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2431 13:54:23.664916  ==

 2432 13:54:23.667149  [Duty_Offset_Calibration]

 2433 13:54:23.667658  	B0:0	B1:-1	CA:2

 2434 13:54:23.668195  

 2435 13:54:23.670486  [DutyScan_Calibration_Flow] k_type=0

 2436 13:54:23.680796  

 2437 13:54:23.681360  ==CLK 0==

 2438 13:54:23.684410  Final CLK duty delay cell = 0

 2439 13:54:23.687832  [0] MAX Duty = 5156%(X100), DQS PI = 36

 2440 13:54:23.690949  [0] MIN Duty = 4938%(X100), DQS PI = 12

 2441 13:54:23.691428  [0] AVG Duty = 5047%(X100)

 2442 13:54:23.694011  

 2443 13:54:23.697248  CH1 CLK Duty spec in!! Max-Min= 218%

 2444 13:54:23.701188  [DutyScan_Calibration_Flow] ====Done====

 2445 13:54:23.701937  

 2446 13:54:23.704093  [DutyScan_Calibration_Flow] k_type=1

 2447 13:54:23.720475  

 2448 13:54:23.721040  ==DQS 0 ==

 2449 13:54:23.723910  Final DQS duty delay cell = 0

 2450 13:54:23.727060  [0] MAX Duty = 5093%(X100), DQS PI = 8

 2451 13:54:23.730262  [0] MIN Duty = 4969%(X100), DQS PI = 34

 2452 13:54:23.730746  [0] AVG Duty = 5031%(X100)

 2453 13:54:23.731121  

 2454 13:54:23.733405  ==DQS 1 ==

 2455 13:54:23.737163  Final DQS duty delay cell = 0

 2456 13:54:23.740373  [0] MAX Duty = 5156%(X100), DQS PI = 28

 2457 13:54:23.744143  [0] MIN Duty = 4813%(X100), DQS PI = 4

 2458 13:54:23.744849  [0] AVG Duty = 4984%(X100)

 2459 13:54:23.745466  

 2460 13:54:23.746880  CH1 DQS 0 Duty spec in!! Max-Min= 124%

 2461 13:54:23.750589  

 2462 13:54:23.753474  CH1 DQS 1 Duty spec in!! Max-Min= 343%

 2463 13:54:23.756778  [DutyScan_Calibration_Flow] ====Done====

 2464 13:54:23.757203  

 2465 13:54:23.759957  [DutyScan_Calibration_Flow] k_type=3

 2466 13:54:23.777808  

 2467 13:54:23.778448  ==DQM 0 ==

 2468 13:54:23.780806  Final DQM duty delay cell = 4

 2469 13:54:23.784280  [4] MAX Duty = 5124%(X100), DQS PI = 22

 2470 13:54:23.787351  [4] MIN Duty = 4969%(X100), DQS PI = 0

 2471 13:54:23.787827  [4] AVG Duty = 5046%(X100)

 2472 13:54:23.790751  

 2473 13:54:23.791176  ==DQM 1 ==

 2474 13:54:23.794029  Final DQM duty delay cell = 0

 2475 13:54:23.797576  [0] MAX Duty = 5249%(X100), DQS PI = 28

 2476 13:54:23.800683  [0] MIN Duty = 4906%(X100), DQS PI = 4

 2477 13:54:23.801124  [0] AVG Duty = 5077%(X100)

 2478 13:54:23.804464  

 2479 13:54:23.807876  CH1 DQM 0 Duty spec in!! Max-Min= 155%

 2480 13:54:23.808299  

 2481 13:54:23.810732  CH1 DQM 1 Duty spec in!! Max-Min= 343%

 2482 13:54:23.813927  [DutyScan_Calibration_Flow] ====Done====

 2483 13:54:23.814387  

 2484 13:54:23.817614  [DutyScan_Calibration_Flow] k_type=2

 2485 13:54:23.834269  

 2486 13:54:23.834839  ==DQ 0 ==

 2487 13:54:23.837500  Final DQ duty delay cell = 0

 2488 13:54:23.840716  [0] MAX Duty = 5062%(X100), DQS PI = 22

 2489 13:54:23.843886  [0] MIN Duty = 4938%(X100), DQS PI = 0

 2490 13:54:23.844456  [0] AVG Duty = 5000%(X100)

 2491 13:54:23.844833  

 2492 13:54:23.847558  ==DQ 1 ==

 2493 13:54:23.851149  Final DQ duty delay cell = 0

 2494 13:54:23.854178  [0] MAX Duty = 5031%(X100), DQS PI = 32

 2495 13:54:23.857502  [0] MIN Duty = 4813%(X100), DQS PI = 2

 2496 13:54:23.858104  [0] AVG Duty = 4922%(X100)

 2497 13:54:23.858486  

 2498 13:54:23.860744  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 2499 13:54:23.861317  

 2500 13:54:23.864069  CH1 DQ 1 Duty spec in!! Max-Min= 218%

 2501 13:54:23.870540  [DutyScan_Calibration_Flow] ====Done====

 2502 13:54:23.874295  nWR fixed to 30

 2503 13:54:23.874864  [ModeRegInit_LP4] CH0 RK0

 2504 13:54:23.877155  [ModeRegInit_LP4] CH0 RK1

 2505 13:54:23.880964  [ModeRegInit_LP4] CH1 RK0

 2506 13:54:23.881538  [ModeRegInit_LP4] CH1 RK1

 2507 13:54:23.883848  match AC timing 7

 2508 13:54:23.887575  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2509 13:54:23.890437  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2510 13:54:23.897079  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2511 13:54:23.900739  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2512 13:54:23.907174  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2513 13:54:23.907735  ==

 2514 13:54:23.911008  Dram Type= 6, Freq= 0, CH_0, rank 0

 2515 13:54:23.913891  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2516 13:54:23.914404  ==

 2517 13:54:23.921083  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2518 13:54:23.924032  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2519 13:54:23.934068  [CA 0] Center 38 (7~69) winsize 63

 2520 13:54:23.936872  [CA 1] Center 38 (8~69) winsize 62

 2521 13:54:23.940715  [CA 2] Center 35 (5~66) winsize 62

 2522 13:54:23.943663  [CA 3] Center 35 (4~66) winsize 63

 2523 13:54:23.947249  [CA 4] Center 34 (4~65) winsize 62

 2524 13:54:23.950375  [CA 5] Center 33 (3~63) winsize 61

 2525 13:54:23.950842  

 2526 13:54:23.953885  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2527 13:54:23.954395  

 2528 13:54:23.957584  [CATrainingPosCal] consider 1 rank data

 2529 13:54:23.960585  u2DelayCellTimex100 = 270/100 ps

 2530 13:54:23.963981  CA0 delay=38 (7~69),Diff = 5 PI (24 cell)

 2531 13:54:23.966945  CA1 delay=38 (8~69),Diff = 5 PI (24 cell)

 2532 13:54:23.973640  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2533 13:54:23.977399  CA3 delay=35 (4~66),Diff = 2 PI (9 cell)

 2534 13:54:23.980418  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2535 13:54:23.983874  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 2536 13:54:23.984346  

 2537 13:54:23.988091  CA PerBit enable=1, Macro0, CA PI delay=33

 2538 13:54:23.988675  

 2539 13:54:23.990607  [CBTSetCACLKResult] CA Dly = 33

 2540 13:54:23.991133  CS Dly: 6 (0~37)

 2541 13:54:23.991505  ==

 2542 13:54:23.993830  Dram Type= 6, Freq= 0, CH_0, rank 1

 2543 13:54:24.000717  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2544 13:54:24.001192  ==

 2545 13:54:24.003823  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2546 13:54:24.010458  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2547 13:54:24.019913  [CA 0] Center 39 (8~70) winsize 63

 2548 13:54:24.022586  [CA 1] Center 38 (8~69) winsize 62

 2549 13:54:24.026473  [CA 2] Center 35 (5~66) winsize 62

 2550 13:54:24.029722  [CA 3] Center 35 (5~66) winsize 62

 2551 13:54:24.032864  [CA 4] Center 34 (4~65) winsize 62

 2552 13:54:24.036409  [CA 5] Center 34 (4~64) winsize 61

 2553 13:54:24.036982  

 2554 13:54:24.039826  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 2555 13:54:24.040397  

 2556 13:54:24.042727  [CATrainingPosCal] consider 2 rank data

 2557 13:54:24.045928  u2DelayCellTimex100 = 270/100 ps

 2558 13:54:24.049716  CA0 delay=38 (8~69),Diff = 5 PI (24 cell)

 2559 13:54:24.052881  CA1 delay=38 (8~69),Diff = 5 PI (24 cell)

 2560 13:54:24.059794  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2561 13:54:24.063003  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2562 13:54:24.066292  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2563 13:54:24.069282  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 2564 13:54:24.069711  

 2565 13:54:24.072877  CA PerBit enable=1, Macro0, CA PI delay=33

 2566 13:54:24.073453  

 2567 13:54:24.076129  [CBTSetCACLKResult] CA Dly = 33

 2568 13:54:24.076606  CS Dly: 7 (0~39)

 2569 13:54:24.076980  

 2570 13:54:24.079300  ----->DramcWriteLeveling(PI) begin...

 2571 13:54:24.083391  ==

 2572 13:54:24.083967  Dram Type= 6, Freq= 0, CH_0, rank 0

 2573 13:54:24.089726  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2574 13:54:24.090395  ==

 2575 13:54:24.093197  Write leveling (Byte 0): 35 => 35

 2576 13:54:24.096460  Write leveling (Byte 1): 32 => 32

 2577 13:54:24.097037  DramcWriteLeveling(PI) end<-----

 2578 13:54:24.099460  

 2579 13:54:24.099932  ==

 2580 13:54:24.103205  Dram Type= 6, Freq= 0, CH_0, rank 0

 2581 13:54:24.106357  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2582 13:54:24.106837  ==

 2583 13:54:24.109437  [Gating] SW mode calibration

 2584 13:54:24.116471  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2585 13:54:24.119902  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2586 13:54:24.126216   0 15  0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 2587 13:54:24.129778   0 15  4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)

 2588 13:54:24.133036   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2589 13:54:24.139588   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2590 13:54:24.572073   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2591 13:54:24.573046   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2592 13:54:24.573554   0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)

 2593 13:54:24.574067   0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)

 2594 13:54:24.574637   1  0  0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)

 2595 13:54:24.575085   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2596 13:54:24.575658   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2597 13:54:24.576182   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2598 13:54:24.576721   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2599 13:54:24.577215   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2600 13:54:24.577688   1  0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)

 2601 13:54:24.578093   1  0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 2602 13:54:24.578173   1  1  0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)

 2603 13:54:24.578276   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2604 13:54:24.578351   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2605 13:54:24.578460   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2606 13:54:24.578579   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2607 13:54:24.578675   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2608 13:54:24.578781   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2609 13:54:24.578897   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2610 13:54:24.579087   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2611 13:54:24.579190   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2612 13:54:24.579304   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2613 13:54:24.579421   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2614 13:54:24.579507   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2615 13:54:24.579593   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2616 13:54:24.579688   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2617 13:54:24.579844   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2618 13:54:24.579973   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2619 13:54:24.580047   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2620 13:54:24.580102   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2621 13:54:24.580155   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2622 13:54:24.580209   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2623 13:54:24.580262   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2624 13:54:24.580315   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2625 13:54:24.580368   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2626 13:54:24.580422   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2627 13:54:24.580474  Total UI for P1: 0, mck2ui 16

 2628 13:54:24.580528  best dqsien dly found for B0: ( 1,  3, 28)

 2629 13:54:24.580582   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2630 13:54:24.580636  Total UI for P1: 0, mck2ui 16

 2631 13:54:24.580689  best dqsien dly found for B1: ( 1,  4,  0)

 2632 13:54:24.580742  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 2633 13:54:24.580796  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2634 13:54:24.580849  

 2635 13:54:24.580902  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2636 13:54:24.580955  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2637 13:54:24.581025  [Gating] SW calibration Done

 2638 13:54:24.581081  ==

 2639 13:54:24.581138  Dram Type= 6, Freq= 0, CH_0, rank 0

 2640 13:54:24.581210  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2641 13:54:24.581271  ==

 2642 13:54:24.581328  RX Vref Scan: 0

 2643 13:54:24.581385  

 2644 13:54:24.581440  RX Vref 0 -> 0, step: 1

 2645 13:54:24.581495  

 2646 13:54:24.581551  RX Delay -40 -> 252, step: 8

 2647 13:54:24.581607  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 2648 13:54:24.581663  iDelay=200, Bit 1, Center 123 (56 ~ 191) 136

 2649 13:54:24.581720  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2650 13:54:24.581776  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2651 13:54:24.581832  iDelay=200, Bit 4, Center 123 (56 ~ 191) 136

 2652 13:54:24.581888  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2653 13:54:24.581953  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2654 13:54:24.582012  iDelay=200, Bit 7, Center 131 (64 ~ 199) 136

 2655 13:54:24.582069  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2656 13:54:24.582125  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 2657 13:54:24.582182  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 2658 13:54:24.582238  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2659 13:54:24.582294  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2660 13:54:24.582351  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2661 13:54:24.582406  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2662 13:54:24.582462  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 2663 13:54:24.582518  ==

 2664 13:54:24.582581  Dram Type= 6, Freq= 0, CH_0, rank 0

 2665 13:54:24.582648  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2666 13:54:24.582709  ==

 2667 13:54:24.582765  DQS Delay:

 2668 13:54:24.582822  DQS0 = 0, DQS1 = 0

 2669 13:54:24.582900  DQM Delay:

 2670 13:54:24.583002  DQM0 = 122, DQM1 = 110

 2671 13:54:24.583070  DQ Delay:

 2672 13:54:24.583139  DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119

 2673 13:54:24.583211  DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =131

 2674 13:54:24.583304  DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107

 2675 13:54:24.583374  DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115

 2676 13:54:24.583432  

 2677 13:54:24.583489  

 2678 13:54:24.583545  ==

 2679 13:54:24.583602  Dram Type= 6, Freq= 0, CH_0, rank 0

 2680 13:54:24.583679  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2681 13:54:24.583770  ==

 2682 13:54:24.583859  

 2683 13:54:24.583946  

 2684 13:54:24.584034  	TX Vref Scan disable

 2685 13:54:24.584122   == TX Byte 0 ==

 2686 13:54:24.584211  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2687 13:54:24.584300  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2688 13:54:24.584388   == TX Byte 1 ==

 2689 13:54:24.584476  Update DQ  dly =849 (3 ,2, 17)  DQ  OEN =(2 ,7)

 2690 13:54:24.584565  Update DQM dly =849 (3 ,2, 17)  DQM OEN =(2 ,7)

 2691 13:54:24.584652  ==

 2692 13:54:24.584740  Dram Type= 6, Freq= 0, CH_0, rank 0

 2693 13:54:24.584829  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2694 13:54:24.584917  ==

 2695 13:54:24.585005  TX Vref=22, minBit 3, minWin=23, winSum=398

 2696 13:54:24.585095  TX Vref=24, minBit 4, minWin=24, winSum=409

 2697 13:54:24.585184  TX Vref=26, minBit 0, minWin=24, winSum=412

 2698 13:54:24.585272  TX Vref=28, minBit 1, minWin=25, winSum=415

 2699 13:54:24.585574  TX Vref=30, minBit 1, minWin=25, winSum=416

 2700 13:54:24.585670  TX Vref=32, minBit 1, minWin=25, winSum=413

 2701 13:54:24.585761  [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 30

 2702 13:54:24.585850  

 2703 13:54:24.585944  Final TX Range 1 Vref 30

 2704 13:54:24.586012  

 2705 13:54:24.586070  ==

 2706 13:54:24.586151  Dram Type= 6, Freq= 0, CH_0, rank 0

 2707 13:54:24.586222  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2708 13:54:24.586302  ==

 2709 13:54:24.586361  

 2710 13:54:24.586416  

 2711 13:54:24.586471  	TX Vref Scan disable

 2712 13:54:24.586527   == TX Byte 0 ==

 2713 13:54:24.586583  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2714 13:54:24.586639  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2715 13:54:24.586694   == TX Byte 1 ==

 2716 13:54:24.586749  Update DQ  dly =848 (3 ,2, 16)  DQ  OEN =(2 ,7)

 2717 13:54:24.586805  Update DQM dly =848 (3 ,2, 16)  DQM OEN =(2 ,7)

 2718 13:54:24.586861  

 2719 13:54:24.586916  [DATLAT]

 2720 13:54:24.586972  Freq=1200, CH0 RK0

 2721 13:54:24.587028  

 2722 13:54:24.587084  DATLAT Default: 0xd

 2723 13:54:24.587141  0, 0xFFFF, sum = 0

 2724 13:54:24.587198  1, 0xFFFF, sum = 0

 2725 13:54:24.587255  2, 0xFFFF, sum = 0

 2726 13:54:24.587312  3, 0xFFFF, sum = 0

 2727 13:54:24.587370  4, 0xFFFF, sum = 0

 2728 13:54:24.587426  5, 0xFFFF, sum = 0

 2729 13:54:24.587483  6, 0xFFFF, sum = 0

 2730 13:54:24.587539  7, 0xFFFF, sum = 0

 2731 13:54:24.587596  8, 0xFFFF, sum = 0

 2732 13:54:24.587653  9, 0xFFFF, sum = 0

 2733 13:54:24.587710  10, 0xFFFF, sum = 0

 2734 13:54:24.587767  11, 0xFFFF, sum = 0

 2735 13:54:24.587824  12, 0x0, sum = 1

 2736 13:54:24.587881  13, 0x0, sum = 2

 2737 13:54:24.587938  14, 0x0, sum = 3

 2738 13:54:24.587995  15, 0x0, sum = 4

 2739 13:54:24.588051  best_step = 13

 2740 13:54:24.588107  

 2741 13:54:24.588178  ==

 2742 13:54:24.588239  Dram Type= 6, Freq= 0, CH_0, rank 0

 2743 13:54:24.593854  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2744 13:54:24.594382  ==

 2745 13:54:24.594746  RX Vref Scan: 1

 2746 13:54:24.595086  

 2747 13:54:24.597059  Set Vref Range= 32 -> 127

 2748 13:54:24.597521  

 2749 13:54:24.600328  RX Vref 32 -> 127, step: 1

 2750 13:54:24.600752  

 2751 13:54:24.603904  RX Delay -13 -> 252, step: 4

 2752 13:54:24.604329  

 2753 13:54:24.606878  Set Vref, RX VrefLevel [Byte0]: 32

 2754 13:54:24.610289                           [Byte1]: 32

 2755 13:54:24.610715  

 2756 13:54:24.614100  Set Vref, RX VrefLevel [Byte0]: 33

 2757 13:54:24.616894                           [Byte1]: 33

 2758 13:54:24.617431  

 2759 13:54:24.620335  Set Vref, RX VrefLevel [Byte0]: 34

 2760 13:54:24.623982                           [Byte1]: 34

 2761 13:54:24.628030  

 2762 13:54:24.628611  Set Vref, RX VrefLevel [Byte0]: 35

 2763 13:54:24.631610                           [Byte1]: 35

 2764 13:54:24.636037  

 2765 13:54:24.636611  Set Vref, RX VrefLevel [Byte0]: 36

 2766 13:54:24.639668                           [Byte1]: 36

 2767 13:54:24.643667  

 2768 13:54:24.644279  Set Vref, RX VrefLevel [Byte0]: 37

 2769 13:54:24.646883                           [Byte1]: 37

 2770 13:54:24.651678  

 2771 13:54:24.652260  Set Vref, RX VrefLevel [Byte0]: 38

 2772 13:54:24.654620                           [Byte1]: 38

 2773 13:54:24.659404  

 2774 13:54:24.659977  Set Vref, RX VrefLevel [Byte0]: 39

 2775 13:54:24.663116                           [Byte1]: 39

 2776 13:54:24.667313  

 2777 13:54:24.667919  Set Vref, RX VrefLevel [Byte0]: 40

 2778 13:54:24.670646                           [Byte1]: 40

 2779 13:54:24.675350  

 2780 13:54:24.675952  Set Vref, RX VrefLevel [Byte0]: 41

 2781 13:54:24.678545                           [Byte1]: 41

 2782 13:54:24.683047  

 2783 13:54:24.683596  Set Vref, RX VrefLevel [Byte0]: 42

 2784 13:54:24.686329                           [Byte1]: 42

 2785 13:54:24.690972  

 2786 13:54:24.691526  Set Vref, RX VrefLevel [Byte0]: 43

 2787 13:54:24.694196                           [Byte1]: 43

 2788 13:54:24.698866  

 2789 13:54:24.699363  Set Vref, RX VrefLevel [Byte0]: 44

 2790 13:54:24.702083                           [Byte1]: 44

 2791 13:54:24.706664  

 2792 13:54:24.707138  Set Vref, RX VrefLevel [Byte0]: 45

 2793 13:54:24.709968                           [Byte1]: 45

 2794 13:54:24.714549  

 2795 13:54:24.715052  Set Vref, RX VrefLevel [Byte0]: 46

 2796 13:54:24.717636                           [Byte1]: 46

 2797 13:54:24.722626  

 2798 13:54:24.723103  Set Vref, RX VrefLevel [Byte0]: 47

 2799 13:54:24.725820                           [Byte1]: 47

 2800 13:54:24.730211  

 2801 13:54:24.730548  Set Vref, RX VrefLevel [Byte0]: 48

 2802 13:54:24.733532                           [Byte1]: 48

 2803 13:54:24.738224  

 2804 13:54:24.738437  Set Vref, RX VrefLevel [Byte0]: 49

 2805 13:54:24.741347                           [Byte1]: 49

 2806 13:54:24.745914  

 2807 13:54:24.746136  Set Vref, RX VrefLevel [Byte0]: 50

 2808 13:54:24.749226                           [Byte1]: 50

 2809 13:54:24.753694  

 2810 13:54:24.753863  Set Vref, RX VrefLevel [Byte0]: 51

 2811 13:54:24.756951                           [Byte1]: 51

 2812 13:54:24.761297  

 2813 13:54:24.761409  Set Vref, RX VrefLevel [Byte0]: 52

 2814 13:54:24.764731                           [Byte1]: 52

 2815 13:54:24.769665  

 2816 13:54:24.769775  Set Vref, RX VrefLevel [Byte0]: 53

 2817 13:54:24.772917                           [Byte1]: 53

 2818 13:54:24.777009  

 2819 13:54:24.777092  Set Vref, RX VrefLevel [Byte0]: 54

 2820 13:54:24.780551                           [Byte1]: 54

 2821 13:54:24.785402  

 2822 13:54:24.785499  Set Vref, RX VrefLevel [Byte0]: 55

 2823 13:54:24.789162                           [Byte1]: 55

 2824 13:54:24.793183  

 2825 13:54:24.793273  Set Vref, RX VrefLevel [Byte0]: 56

 2826 13:54:24.796676                           [Byte1]: 56

 2827 13:54:24.801300  

 2828 13:54:24.801404  Set Vref, RX VrefLevel [Byte0]: 57

 2829 13:54:24.804306                           [Byte1]: 57

 2830 13:54:24.808795  

 2831 13:54:24.808908  Set Vref, RX VrefLevel [Byte0]: 58

 2832 13:54:24.812146                           [Byte1]: 58

 2833 13:54:24.816769  

 2834 13:54:24.816907  Set Vref, RX VrefLevel [Byte0]: 59

 2835 13:54:24.820121                           [Byte1]: 59

 2836 13:54:24.824926  

 2837 13:54:24.825367  Set Vref, RX VrefLevel [Byte0]: 60

 2838 13:54:24.828291                           [Byte1]: 60

 2839 13:54:24.832723  

 2840 13:54:24.833149  Set Vref, RX VrefLevel [Byte0]: 61

 2841 13:54:24.836617                           [Byte1]: 61

 2842 13:54:24.840802  

 2843 13:54:24.841227  Set Vref, RX VrefLevel [Byte0]: 62

 2844 13:54:24.844041                           [Byte1]: 62

 2845 13:54:24.848720  

 2846 13:54:24.849149  Set Vref, RX VrefLevel [Byte0]: 63

 2847 13:54:24.852559                           [Byte1]: 63

 2848 13:54:24.856753  

 2849 13:54:24.857276  Set Vref, RX VrefLevel [Byte0]: 64

 2850 13:54:24.860365                           [Byte1]: 64

 2851 13:54:24.864927  

 2852 13:54:24.865494  Set Vref, RX VrefLevel [Byte0]: 65

 2853 13:54:24.867964                           [Byte1]: 65

 2854 13:54:24.872289  

 2855 13:54:24.872755  Set Vref, RX VrefLevel [Byte0]: 66

 2856 13:54:24.875601                           [Byte1]: 66

 2857 13:54:24.880152  

 2858 13:54:24.880622  Set Vref, RX VrefLevel [Byte0]: 67

 2859 13:54:24.883770                           [Byte1]: 67

 2860 13:54:24.888327  

 2861 13:54:24.888793  Set Vref, RX VrefLevel [Byte0]: 68

 2862 13:54:24.891634                           [Byte1]: 68

 2863 13:54:24.896499  

 2864 13:54:24.897076  Set Vref, RX VrefLevel [Byte0]: 69

 2865 13:54:24.899430                           [Byte1]: 69

 2866 13:54:24.903974  

 2867 13:54:24.904729  Set Vref, RX VrefLevel [Byte0]: 70

 2868 13:54:24.907135                           [Byte1]: 70

 2869 13:54:24.912315  

 2870 13:54:24.912879  Set Vref, RX VrefLevel [Byte0]: 71

 2871 13:54:24.915270                           [Byte1]: 71

 2872 13:54:24.920274  

 2873 13:54:24.920841  Set Vref, RX VrefLevel [Byte0]: 72

 2874 13:54:24.923151                           [Byte1]: 72

 2875 13:54:24.927512  

 2876 13:54:24.928009  Final RX Vref Byte 0 = 62 to rank0

 2877 13:54:24.931364  Final RX Vref Byte 1 = 50 to rank0

 2878 13:54:24.934783  Final RX Vref Byte 0 = 62 to rank1

 2879 13:54:24.937714  Final RX Vref Byte 1 = 50 to rank1==

 2880 13:54:24.941268  Dram Type= 6, Freq= 0, CH_0, rank 0

 2881 13:54:24.947272  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2882 13:54:24.948026  ==

 2883 13:54:24.948561  DQS Delay:

 2884 13:54:24.949071  DQS0 = 0, DQS1 = 0

 2885 13:54:24.950948  DQM Delay:

 2886 13:54:24.951497  DQM0 = 122, DQM1 = 109

 2887 13:54:24.954069  DQ Delay:

 2888 13:54:24.957785  DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120

 2889 13:54:24.961293  DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128

 2890 13:54:24.964381  DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106

 2891 13:54:24.968221  DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116

 2892 13:54:24.968790  

 2893 13:54:24.969162  

 2894 13:54:24.974689  [DQSOSCAuto] RK0, (LSB)MR18= 0xa06, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps

 2895 13:54:24.978101  CH0 RK0: MR19=404, MR18=A06

 2896 13:54:24.984472  CH0_RK0: MR19=0x404, MR18=0xA06, DQSOSC=406, MR23=63, INC=39, DEC=26

 2897 13:54:24.985042  

 2898 13:54:24.987769  ----->DramcWriteLeveling(PI) begin...

 2899 13:54:24.988247  ==

 2900 13:54:24.990869  Dram Type= 6, Freq= 0, CH_0, rank 1

 2901 13:54:24.994397  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2902 13:54:24.994974  ==

 2903 13:54:24.997387  Write leveling (Byte 0): 33 => 33

 2904 13:54:25.001529  Write leveling (Byte 1): 30 => 30

 2905 13:54:25.004278  DramcWriteLeveling(PI) end<-----

 2906 13:54:25.004800  

 2907 13:54:25.005179  ==

 2908 13:54:25.007689  Dram Type= 6, Freq= 0, CH_0, rank 1

 2909 13:54:25.011270  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2910 13:54:25.014503  ==

 2911 13:54:25.015079  [Gating] SW mode calibration

 2912 13:54:25.021320  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2913 13:54:25.028447  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2914 13:54:25.031069   0 15  0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)

 2915 13:54:25.037915   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2916 13:54:25.041470   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2917 13:54:25.044420   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2918 13:54:25.051197   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2919 13:54:25.054300   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2920 13:54:25.057886   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2921 13:54:25.064518   0 15 28 | B1->B0 | 2f2f 2b2b | 1 0 | (1 0) (0 0)

 2922 13:54:25.068153   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2923 13:54:25.071013   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2924 13:54:25.077640   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2925 13:54:25.080884   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2926 13:54:25.084529   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2927 13:54:25.091262   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2928 13:54:25.094416   1  0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 2929 13:54:25.097694   1  0 28 | B1->B0 | 3535 4040 | 1 0 | (0 0) (0 0)

 2930 13:54:25.104452   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2931 13:54:25.107727   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2932 13:54:25.110947   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2933 13:54:25.114378   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2934 13:54:25.121219   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2935 13:54:25.124375   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2936 13:54:25.127782   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2937 13:54:25.134259   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2938 13:54:25.138208   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2939 13:54:25.141525   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2940 13:54:25.148232   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2941 13:54:25.151331   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2942 13:54:25.154259   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2943 13:54:25.161430   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2944 13:54:25.164621   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2945 13:54:25.168102   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2946 13:54:25.174808   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2947 13:54:25.178047   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2948 13:54:25.181111   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2949 13:54:25.184745   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2950 13:54:25.191091   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2951 13:54:25.194536   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2952 13:54:25.197927   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2953 13:54:25.204717   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2954 13:54:25.207680   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2955 13:54:25.211118  Total UI for P1: 0, mck2ui 16

 2956 13:54:25.214481  best dqsien dly found for B0: ( 1,  3, 28)

 2957 13:54:25.217705  Total UI for P1: 0, mck2ui 16

 2958 13:54:25.221351  best dqsien dly found for B1: ( 1,  3, 30)

 2959 13:54:25.224817  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 2960 13:54:25.228110  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2961 13:54:25.228586  

 2962 13:54:25.231441  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2963 13:54:25.234397  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2964 13:54:25.238221  [Gating] SW calibration Done

 2965 13:54:25.238792  ==

 2966 13:54:25.241556  Dram Type= 6, Freq= 0, CH_0, rank 1

 2967 13:54:25.244901  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2968 13:54:25.248358  ==

 2969 13:54:25.248931  RX Vref Scan: 0

 2970 13:54:25.249307  

 2971 13:54:25.251216  RX Vref 0 -> 0, step: 1

 2972 13:54:25.251709  

 2973 13:54:25.252082  RX Delay -40 -> 252, step: 8

 2974 13:54:25.258218  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2975 13:54:25.261502  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2976 13:54:25.265249  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2977 13:54:25.268471  iDelay=200, Bit 3, Center 115 (48 ~ 183) 136

 2978 13:54:25.271704  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2979 13:54:25.278366  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2980 13:54:25.281674  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2981 13:54:25.285126  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2982 13:54:25.288355  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2983 13:54:25.291583  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2984 13:54:25.298124  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 2985 13:54:25.301214  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2986 13:54:25.304748  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2987 13:54:25.308686  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2988 13:54:25.311454  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2989 13:54:25.318044  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 2990 13:54:25.318596  ==

 2991 13:54:25.321601  Dram Type= 6, Freq= 0, CH_0, rank 1

 2992 13:54:25.325040  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2993 13:54:25.325631  ==

 2994 13:54:25.326091  DQS Delay:

 2995 13:54:25.328186  DQS0 = 0, DQS1 = 0

 2996 13:54:25.328751  DQM Delay:

 2997 13:54:25.331567  DQM0 = 120, DQM1 = 108

 2998 13:54:25.332041  DQ Delay:

 2999 13:54:25.334722  DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115

 3000 13:54:25.338153  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 3001 13:54:25.341367  DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107

 3002 13:54:25.344714  DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115

 3003 13:54:25.345182  

 3004 13:54:25.345543  

 3005 13:54:25.348413  ==

 3006 13:54:25.348981  Dram Type= 6, Freq= 0, CH_0, rank 1

 3007 13:54:25.355228  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3008 13:54:25.355921  ==

 3009 13:54:25.356438  

 3010 13:54:25.357016  

 3011 13:54:25.358012  	TX Vref Scan disable

 3012 13:54:25.358407   == TX Byte 0 ==

 3013 13:54:25.361331  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 3014 13:54:25.368531  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 3015 13:54:25.369118   == TX Byte 1 ==

 3016 13:54:25.371605  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3017 13:54:25.378319  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3018 13:54:25.379083  ==

 3019 13:54:25.381697  Dram Type= 6, Freq= 0, CH_0, rank 1

 3020 13:54:25.384596  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3021 13:54:25.385229  ==

 3022 13:54:25.396917  TX Vref=22, minBit 0, minWin=25, winSum=415

 3023 13:54:25.400114  TX Vref=24, minBit 1, minWin=24, winSum=416

 3024 13:54:25.403380  TX Vref=26, minBit 0, minWin=25, winSum=420

 3025 13:54:25.406879  TX Vref=28, minBit 7, minWin=24, winSum=419

 3026 13:54:25.410043  TX Vref=30, minBit 1, minWin=25, winSum=422

 3027 13:54:25.413748  TX Vref=32, minBit 1, minWin=25, winSum=421

 3028 13:54:25.420191  [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 30

 3029 13:54:25.420765  

 3030 13:54:25.423254  Final TX Range 1 Vref 30

 3031 13:54:25.423722  

 3032 13:54:25.424185  ==

 3033 13:54:25.427266  Dram Type= 6, Freq= 0, CH_0, rank 1

 3034 13:54:25.430042  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3035 13:54:25.430515  ==

 3036 13:54:25.430887  

 3037 13:54:25.431226  

 3038 13:54:25.433555  	TX Vref Scan disable

 3039 13:54:25.437190   == TX Byte 0 ==

 3040 13:54:25.440638  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 3041 13:54:25.444018  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 3042 13:54:25.446971   == TX Byte 1 ==

 3043 13:54:25.450214  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3044 13:54:25.454060  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3045 13:54:25.454630  

 3046 13:54:25.457082  [DATLAT]

 3047 13:54:25.457619  Freq=1200, CH0 RK1

 3048 13:54:25.458035  

 3049 13:54:25.461022  DATLAT Default: 0xd

 3050 13:54:25.461606  0, 0xFFFF, sum = 0

 3051 13:54:25.463571  1, 0xFFFF, sum = 0

 3052 13:54:25.464128  2, 0xFFFF, sum = 0

 3053 13:54:25.467351  3, 0xFFFF, sum = 0

 3054 13:54:25.467956  4, 0xFFFF, sum = 0

 3055 13:54:25.470489  5, 0xFFFF, sum = 0

 3056 13:54:25.471220  6, 0xFFFF, sum = 0

 3057 13:54:25.473775  7, 0xFFFF, sum = 0

 3058 13:54:25.474432  8, 0xFFFF, sum = 0

 3059 13:54:25.476918  9, 0xFFFF, sum = 0

 3060 13:54:25.477469  10, 0xFFFF, sum = 0

 3061 13:54:25.480436  11, 0xFFFF, sum = 0

 3062 13:54:25.481072  12, 0x0, sum = 1

 3063 13:54:25.483325  13, 0x0, sum = 2

 3064 13:54:25.483798  14, 0x0, sum = 3

 3065 13:54:25.486687  15, 0x0, sum = 4

 3066 13:54:25.487162  best_step = 13

 3067 13:54:25.487525  

 3068 13:54:25.487866  ==

 3069 13:54:25.490684  Dram Type= 6, Freq= 0, CH_0, rank 1

 3070 13:54:25.496953  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3071 13:54:25.497526  ==

 3072 13:54:25.497896  RX Vref Scan: 0

 3073 13:54:25.498318  

 3074 13:54:25.500253  RX Vref 0 -> 0, step: 1

 3075 13:54:25.500724  

 3076 13:54:25.503596  RX Delay -21 -> 252, step: 4

 3077 13:54:25.507039  iDelay=199, Bit 0, Center 120 (51 ~ 190) 140

 3078 13:54:25.510141  iDelay=199, Bit 1, Center 120 (51 ~ 190) 140

 3079 13:54:25.517130  iDelay=199, Bit 2, Center 118 (51 ~ 186) 136

 3080 13:54:25.520231  iDelay=199, Bit 3, Center 114 (47 ~ 182) 136

 3081 13:54:25.523284  iDelay=199, Bit 4, Center 120 (51 ~ 190) 140

 3082 13:54:25.526808  iDelay=199, Bit 5, Center 114 (51 ~ 178) 128

 3083 13:54:25.530611  iDelay=199, Bit 6, Center 128 (59 ~ 198) 140

 3084 13:54:25.537008  iDelay=199, Bit 7, Center 124 (55 ~ 194) 140

 3085 13:54:25.540135  iDelay=199, Bit 8, Center 98 (35 ~ 162) 128

 3086 13:54:25.544019  iDelay=199, Bit 9, Center 94 (31 ~ 158) 128

 3087 13:54:25.546701  iDelay=199, Bit 10, Center 108 (47 ~ 170) 124

 3088 13:54:25.550363  iDelay=199, Bit 11, Center 104 (43 ~ 166) 124

 3089 13:54:25.556990  iDelay=199, Bit 12, Center 114 (51 ~ 178) 128

 3090 13:54:25.560610  iDelay=199, Bit 13, Center 110 (47 ~ 174) 128

 3091 13:54:25.563514  iDelay=199, Bit 14, Center 118 (55 ~ 182) 128

 3092 13:54:25.566903  iDelay=199, Bit 15, Center 114 (51 ~ 178) 128

 3093 13:54:25.567380  ==

 3094 13:54:25.570233  Dram Type= 6, Freq= 0, CH_0, rank 1

 3095 13:54:25.573680  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3096 13:54:25.577011  ==

 3097 13:54:25.577593  DQS Delay:

 3098 13:54:25.578015  DQS0 = 0, DQS1 = 0

 3099 13:54:25.580521  DQM Delay:

 3100 13:54:25.581102  DQM0 = 119, DQM1 = 107

 3101 13:54:25.583540  DQ Delay:

 3102 13:54:25.587123  DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =114

 3103 13:54:25.590087  DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =124

 3104 13:54:25.593584  DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104

 3105 13:54:25.597234  DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114

 3106 13:54:25.597845  

 3107 13:54:25.598300  

 3108 13:54:25.603638  [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps

 3109 13:54:25.607205  CH0 RK1: MR19=403, MR18=10F7

 3110 13:54:25.613649  CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26

 3111 13:54:25.616947  [RxdqsGatingPostProcess] freq 1200

 3112 13:54:25.623489  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3113 13:54:25.627183  best DQS0 dly(2T, 0.5T) = (0, 11)

 3114 13:54:25.627781  best DQS1 dly(2T, 0.5T) = (0, 12)

 3115 13:54:25.630067  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3116 13:54:25.633748  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3117 13:54:25.636633  best DQS0 dly(2T, 0.5T) = (0, 11)

 3118 13:54:25.639959  best DQS1 dly(2T, 0.5T) = (0, 11)

 3119 13:54:25.643450  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3120 13:54:25.647044  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3121 13:54:25.650315  Pre-setting of DQS Precalculation

 3122 13:54:25.657090  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3123 13:54:25.657559  ==

 3124 13:54:25.660333  Dram Type= 6, Freq= 0, CH_1, rank 0

 3125 13:54:25.663709  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3126 13:54:25.664248  ==

 3127 13:54:25.666976  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3128 13:54:25.673752  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35

 3129 13:54:25.682769  [CA 0] Center 38 (8~68) winsize 61

 3130 13:54:25.686353  [CA 1] Center 38 (8~68) winsize 61

 3131 13:54:25.689773  [CA 2] Center 35 (5~65) winsize 61

 3132 13:54:25.692658  [CA 3] Center 34 (4~65) winsize 62

 3133 13:54:25.696576  [CA 4] Center 34 (4~64) winsize 61

 3134 13:54:25.699424  [CA 5] Center 33 (3~64) winsize 62

 3135 13:54:25.699891  

 3136 13:54:25.702773  [CmdBusTrainingLP45] Vref(ca) range 1: 31

 3137 13:54:25.703238  

 3138 13:54:25.706439  [CATrainingPosCal] consider 1 rank data

 3139 13:54:25.709577  u2DelayCellTimex100 = 270/100 ps

 3140 13:54:25.712823  CA0 delay=38 (8~68),Diff = 5 PI (24 cell)

 3141 13:54:25.716323  CA1 delay=38 (8~68),Diff = 5 PI (24 cell)

 3142 13:54:25.722766  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3143 13:54:25.726221  CA3 delay=34 (4~65),Diff = 1 PI (4 cell)

 3144 13:54:25.729747  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3145 13:54:25.732823  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3146 13:54:25.733297  

 3147 13:54:25.736231  CA PerBit enable=1, Macro0, CA PI delay=33

 3148 13:54:25.736805  

 3149 13:54:25.739690  [CBTSetCACLKResult] CA Dly = 33

 3150 13:54:25.740269  CS Dly: 6 (0~37)

 3151 13:54:25.740743  ==

 3152 13:54:25.743164  Dram Type= 6, Freq= 0, CH_1, rank 1

 3153 13:54:25.750314  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3154 13:54:25.750925  ==

 3155 13:54:25.752758  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3156 13:54:25.759603  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3157 13:54:25.768200  [CA 0] Center 38 (8~68) winsize 61

 3158 13:54:25.772131  [CA 1] Center 38 (8~69) winsize 62

 3159 13:54:25.775366  [CA 2] Center 35 (5~66) winsize 62

 3160 13:54:25.778347  [CA 3] Center 35 (5~65) winsize 61

 3161 13:54:25.781769  [CA 4] Center 35 (5~65) winsize 61

 3162 13:54:25.784899  [CA 5] Center 34 (4~64) winsize 61

 3163 13:54:25.785373  

 3164 13:54:25.788418  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3165 13:54:25.788886  

 3166 13:54:25.791805  [CATrainingPosCal] consider 2 rank data

 3167 13:54:25.795411  u2DelayCellTimex100 = 270/100 ps

 3168 13:54:25.798208  CA0 delay=38 (8~68),Diff = 4 PI (19 cell)

 3169 13:54:25.801605  CA1 delay=38 (8~68),Diff = 4 PI (19 cell)

 3170 13:54:25.808529  CA2 delay=35 (5~65),Diff = 1 PI (4 cell)

 3171 13:54:25.811458  CA3 delay=35 (5~65),Diff = 1 PI (4 cell)

 3172 13:54:25.815120  CA4 delay=34 (5~64),Diff = 0 PI (0 cell)

 3173 13:54:25.818298  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3174 13:54:25.818485  

 3175 13:54:25.821487  CA PerBit enable=1, Macro0, CA PI delay=34

 3176 13:54:25.821632  

 3177 13:54:25.825036  [CBTSetCACLKResult] CA Dly = 34

 3178 13:54:25.825211  CS Dly: 7 (0~39)

 3179 13:54:25.825357  

 3180 13:54:25.828342  ----->DramcWriteLeveling(PI) begin...

 3181 13:54:25.828517  ==

 3182 13:54:25.831517  Dram Type= 6, Freq= 0, CH_1, rank 0

 3183 13:54:25.838488  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3184 13:54:25.838659  ==

 3185 13:54:25.841585  Write leveling (Byte 0): 26 => 26

 3186 13:54:25.845237  Write leveling (Byte 1): 29 => 29

 3187 13:54:25.845415  DramcWriteLeveling(PI) end<-----

 3188 13:54:25.845525  

 3189 13:54:25.848566  ==

 3190 13:54:25.851863  Dram Type= 6, Freq= 0, CH_1, rank 0

 3191 13:54:25.855097  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3192 13:54:25.855296  ==

 3193 13:54:25.858506  [Gating] SW mode calibration

 3194 13:54:25.865037  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3195 13:54:25.868575  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3196 13:54:25.874956   0 15  0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 3197 13:54:25.878632   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3198 13:54:25.881924   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3199 13:54:25.888625   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3200 13:54:25.891773   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3201 13:54:25.895248   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3202 13:54:25.902250   0 15 24 | B1->B0 | 3131 2727 | 1 1 | (1 1) (1 0)

 3203 13:54:25.905086   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 3204 13:54:25.908612   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3205 13:54:25.915766   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3206 13:54:25.918799   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3207 13:54:25.922163   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3208 13:54:25.928481   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3209 13:54:25.931790   1  0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 3210 13:54:25.935315   1  0 24 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)

 3211 13:54:25.938488   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3212 13:54:25.945230   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3213 13:54:25.948568   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3214 13:54:25.951957   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3215 13:54:25.958939   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3216 13:54:25.962004   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3217 13:54:25.965479   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3218 13:54:25.971819   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3219 13:54:25.975529   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 3220 13:54:25.978575   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3221 13:54:25.985200   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3222 13:54:25.988627   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3223 13:54:25.991585   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3224 13:54:25.998099   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3225 13:54:26.001895   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3226 13:54:26.005013   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3227 13:54:26.011587   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3228 13:54:26.014920   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3229 13:54:26.017915   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3230 13:54:26.024919   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3231 13:54:26.028155   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3232 13:54:26.031772   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3233 13:54:26.034806   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3234 13:54:26.041674   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3235 13:54:26.045346   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3236 13:54:26.048581  Total UI for P1: 0, mck2ui 16

 3237 13:54:26.051732  best dqsien dly found for B0: ( 1,  3, 24)

 3238 13:54:26.055537  Total UI for P1: 0, mck2ui 16

 3239 13:54:26.058535  best dqsien dly found for B1: ( 1,  3, 24)

 3240 13:54:26.061843  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 3241 13:54:26.065473  best DQS1 dly(MCK, UI, PI) = (1, 3, 24)

 3242 13:54:26.065640  

 3243 13:54:26.068498  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3244 13:54:26.072039  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3245 13:54:26.075457  [Gating] SW calibration Done

 3246 13:54:26.075656  ==

 3247 13:54:26.078574  Dram Type= 6, Freq= 0, CH_1, rank 0

 3248 13:54:26.082105  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3249 13:54:26.085312  ==

 3250 13:54:26.085779  RX Vref Scan: 0

 3251 13:54:26.086184  

 3252 13:54:26.088703  RX Vref 0 -> 0, step: 1

 3253 13:54:26.089171  

 3254 13:54:26.091911  RX Delay -40 -> 252, step: 8

 3255 13:54:26.095686  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3256 13:54:26.098974  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3257 13:54:26.102179  iDelay=200, Bit 2, Center 111 (48 ~ 175) 128

 3258 13:54:26.105494  iDelay=200, Bit 3, Center 123 (56 ~ 191) 136

 3259 13:54:26.112095  iDelay=200, Bit 4, Center 115 (48 ~ 183) 136

 3260 13:54:26.115265  iDelay=200, Bit 5, Center 127 (64 ~ 191) 128

 3261 13:54:26.118865  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3262 13:54:26.122114  iDelay=200, Bit 7, Center 119 (56 ~ 183) 128

 3263 13:54:26.125414  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3264 13:54:26.128887  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 3265 13:54:26.140048  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3266 13:54:26.140533  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3267 13:54:26.141927  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3268 13:54:26.145386  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3269 13:54:26.149190  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3270 13:54:26.155987  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 3271 13:54:26.156469  ==

 3272 13:54:26.158942  Dram Type= 6, Freq= 0, CH_1, rank 0

 3273 13:54:26.162504  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3274 13:54:26.162987  ==

 3275 13:54:26.163460  DQS Delay:

 3276 13:54:26.165684  DQS0 = 0, DQS1 = 0

 3277 13:54:26.166197  DQM Delay:

 3278 13:54:26.168569  DQM0 = 120, DQM1 = 112

 3279 13:54:26.169046  DQ Delay:

 3280 13:54:26.172110  DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123

 3281 13:54:26.175246  DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119

 3282 13:54:26.178835  DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107

 3283 13:54:26.182001  DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119

 3284 13:54:26.182491  

 3285 13:54:26.182979  

 3286 13:54:26.185282  ==

 3287 13:54:26.189205  Dram Type= 6, Freq= 0, CH_1, rank 0

 3288 13:54:26.192634  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3289 13:54:26.193150  ==

 3290 13:54:26.193635  

 3291 13:54:26.194217  

 3292 13:54:26.195411  	TX Vref Scan disable

 3293 13:54:26.195893   == TX Byte 0 ==

 3294 13:54:26.198791  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3295 13:54:26.205626  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3296 13:54:26.206346   == TX Byte 1 ==

 3297 13:54:26.208691  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3298 13:54:26.215570  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3299 13:54:26.216102  ==

 3300 13:54:26.219080  Dram Type= 6, Freq= 0, CH_1, rank 0

 3301 13:54:26.221922  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3302 13:54:26.222316  ==

 3303 13:54:26.233848  TX Vref=22, minBit 11, minWin=24, winSum=409

 3304 13:54:26.237112  TX Vref=24, minBit 1, minWin=25, winSum=416

 3305 13:54:26.240516  TX Vref=26, minBit 10, minWin=25, winSum=418

 3306 13:54:26.243650  TX Vref=28, minBit 1, minWin=26, winSum=425

 3307 13:54:26.247373  TX Vref=30, minBit 10, minWin=25, winSum=425

 3308 13:54:26.253766  TX Vref=32, minBit 9, minWin=25, winSum=422

 3309 13:54:26.257147  [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 28

 3310 13:54:26.257393  

 3311 13:54:26.260171  Final TX Range 1 Vref 28

 3312 13:54:26.260338  

 3313 13:54:26.260464  ==

 3314 13:54:26.263873  Dram Type= 6, Freq= 0, CH_1, rank 0

 3315 13:54:26.266965  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3316 13:54:26.267194  ==

 3317 13:54:26.270542  

 3318 13:54:26.270830  

 3319 13:54:26.271012  	TX Vref Scan disable

 3320 13:54:26.273784   == TX Byte 0 ==

 3321 13:54:26.276920  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3322 13:54:26.283250  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3323 13:54:26.283493   == TX Byte 1 ==

 3324 13:54:26.287043  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3325 13:54:26.293414  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3326 13:54:26.293618  

 3327 13:54:26.293748  [DATLAT]

 3328 13:54:26.293868  Freq=1200, CH1 RK0

 3329 13:54:26.294009  

 3330 13:54:26.296927  DATLAT Default: 0xd

 3331 13:54:26.297069  0, 0xFFFF, sum = 0

 3332 13:54:26.300287  1, 0xFFFF, sum = 0

 3333 13:54:26.300435  2, 0xFFFF, sum = 0

 3334 13:54:26.303689  3, 0xFFFF, sum = 0

 3335 13:54:26.307018  4, 0xFFFF, sum = 0

 3336 13:54:26.307134  5, 0xFFFF, sum = 0

 3337 13:54:26.310097  6, 0xFFFF, sum = 0

 3338 13:54:26.310275  7, 0xFFFF, sum = 0

 3339 13:54:26.313720  8, 0xFFFF, sum = 0

 3340 13:54:26.313830  9, 0xFFFF, sum = 0

 3341 13:54:26.316947  10, 0xFFFF, sum = 0

 3342 13:54:26.317080  11, 0xFFFF, sum = 0

 3343 13:54:26.320236  12, 0x0, sum = 1

 3344 13:54:26.320380  13, 0x0, sum = 2

 3345 13:54:26.323499  14, 0x0, sum = 3

 3346 13:54:26.323600  15, 0x0, sum = 4

 3347 13:54:26.323672  best_step = 13

 3348 13:54:26.323735  

 3349 13:54:26.327033  ==

 3350 13:54:26.330070  Dram Type= 6, Freq= 0, CH_1, rank 0

 3351 13:54:26.333703  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3352 13:54:26.333854  ==

 3353 13:54:26.333971  RX Vref Scan: 1

 3354 13:54:26.334064  

 3355 13:54:26.337073  Set Vref Range= 32 -> 127

 3356 13:54:26.337179  

 3357 13:54:26.340163  RX Vref 32 -> 127, step: 1

 3358 13:54:26.340294  

 3359 13:54:26.343498  RX Delay -13 -> 252, step: 4

 3360 13:54:26.343601  

 3361 13:54:26.346990  Set Vref, RX VrefLevel [Byte0]: 32

 3362 13:54:26.350266                           [Byte1]: 32

 3363 13:54:26.350355  

 3364 13:54:26.353934  Set Vref, RX VrefLevel [Byte0]: 33

 3365 13:54:26.357222                           [Byte1]: 33

 3366 13:54:26.357385  

 3367 13:54:26.360793  Set Vref, RX VrefLevel [Byte0]: 34

 3368 13:54:26.363920                           [Byte1]: 34

 3369 13:54:26.367971  

 3370 13:54:26.368172  Set Vref, RX VrefLevel [Byte0]: 35

 3371 13:54:26.371266                           [Byte1]: 35

 3372 13:54:26.376184  

 3373 13:54:26.376374  Set Vref, RX VrefLevel [Byte0]: 36

 3374 13:54:26.379212                           [Byte1]: 36

 3375 13:54:26.383941  

 3376 13:54:26.384553  Set Vref, RX VrefLevel [Byte0]: 37

 3377 13:54:26.387779                           [Byte1]: 37

 3378 13:54:26.392229  

 3379 13:54:26.392793  Set Vref, RX VrefLevel [Byte0]: 38

 3380 13:54:26.395053                           [Byte1]: 38

 3381 13:54:26.400071  

 3382 13:54:26.400756  Set Vref, RX VrefLevel [Byte0]: 39

 3383 13:54:26.403115                           [Byte1]: 39

 3384 13:54:26.407710  

 3385 13:54:26.408170  Set Vref, RX VrefLevel [Byte0]: 40

 3386 13:54:26.411082                           [Byte1]: 40

 3387 13:54:26.416204  

 3388 13:54:26.416768  Set Vref, RX VrefLevel [Byte0]: 41

 3389 13:54:26.418914                           [Byte1]: 41

 3390 13:54:26.423607  

 3391 13:54:26.424184  Set Vref, RX VrefLevel [Byte0]: 42

 3392 13:54:26.427175                           [Byte1]: 42

 3393 13:54:26.431712  

 3394 13:54:26.432276  Set Vref, RX VrefLevel [Byte0]: 43

 3395 13:54:26.434874                           [Byte1]: 43

 3396 13:54:26.439164  

 3397 13:54:26.439713  Set Vref, RX VrefLevel [Byte0]: 44

 3398 13:54:26.442632                           [Byte1]: 44

 3399 13:54:26.447248  

 3400 13:54:26.447707  Set Vref, RX VrefLevel [Byte0]: 45

 3401 13:54:26.450415                           [Byte1]: 45

 3402 13:54:26.455068  

 3403 13:54:26.455527  Set Vref, RX VrefLevel [Byte0]: 46

 3404 13:54:26.458275                           [Byte1]: 46

 3405 13:54:26.462679  

 3406 13:54:26.463137  Set Vref, RX VrefLevel [Byte0]: 47

 3407 13:54:26.466432                           [Byte1]: 47

 3408 13:54:26.470601  

 3409 13:54:26.471057  Set Vref, RX VrefLevel [Byte0]: 48

 3410 13:54:26.474108                           [Byte1]: 48

 3411 13:54:26.478808  

 3412 13:54:26.479316  Set Vref, RX VrefLevel [Byte0]: 49

 3413 13:54:26.482112                           [Byte1]: 49

 3414 13:54:26.486637  

 3415 13:54:26.487070  Set Vref, RX VrefLevel [Byte0]: 50

 3416 13:54:26.490362                           [Byte1]: 50

 3417 13:54:26.494360  

 3418 13:54:26.494776  Set Vref, RX VrefLevel [Byte0]: 51

 3419 13:54:26.497903                           [Byte1]: 51

 3420 13:54:26.502466  

 3421 13:54:26.502770  Set Vref, RX VrefLevel [Byte0]: 52

 3422 13:54:26.505373                           [Byte1]: 52

 3423 13:54:26.509745  

 3424 13:54:26.510052  Set Vref, RX VrefLevel [Byte0]: 53

 3425 13:54:26.512960                           [Byte1]: 53

 3426 13:54:26.517827  

 3427 13:54:26.518058  Set Vref, RX VrefLevel [Byte0]: 54

 3428 13:54:26.521159                           [Byte1]: 54

 3429 13:54:26.525784  

 3430 13:54:26.525974  Set Vref, RX VrefLevel [Byte0]: 55

 3431 13:54:26.529170                           [Byte1]: 55

 3432 13:54:26.533395  

 3433 13:54:26.533624  Set Vref, RX VrefLevel [Byte0]: 56

 3434 13:54:26.536947                           [Byte1]: 56

 3435 13:54:26.541232  

 3436 13:54:26.541405  Set Vref, RX VrefLevel [Byte0]: 57

 3437 13:54:26.545133                           [Byte1]: 57

 3438 13:54:26.549127  

 3439 13:54:26.549259  Set Vref, RX VrefLevel [Byte0]: 58

 3440 13:54:26.552896                           [Byte1]: 58

 3441 13:54:26.557269  

 3442 13:54:26.557499  Set Vref, RX VrefLevel [Byte0]: 59

 3443 13:54:26.560686                           [Byte1]: 59

 3444 13:54:26.565736  

 3445 13:54:26.566039  Set Vref, RX VrefLevel [Byte0]: 60

 3446 13:54:26.568921                           [Byte1]: 60

 3447 13:54:26.573091  

 3448 13:54:26.573420  Set Vref, RX VrefLevel [Byte0]: 61

 3449 13:54:26.576865                           [Byte1]: 61

 3450 13:54:26.581441  

 3451 13:54:26.581904  Set Vref, RX VrefLevel [Byte0]: 62

 3452 13:54:26.584897                           [Byte1]: 62

 3453 13:54:26.589378  

 3454 13:54:26.589860  Set Vref, RX VrefLevel [Byte0]: 63

 3455 13:54:26.592658                           [Byte1]: 63

 3456 13:54:26.597476  

 3457 13:54:26.598092  Set Vref, RX VrefLevel [Byte0]: 64

 3458 13:54:26.600038                           [Byte1]: 64

 3459 13:54:26.604817  

 3460 13:54:26.605418  Set Vref, RX VrefLevel [Byte0]: 65

 3461 13:54:26.608151                           [Byte1]: 65

 3462 13:54:26.612803  

 3463 13:54:26.613378  Set Vref, RX VrefLevel [Byte0]: 66

 3464 13:54:26.616120                           [Byte1]: 66

 3465 13:54:26.620582  

 3466 13:54:26.621050  Set Vref, RX VrefLevel [Byte0]: 67

 3467 13:54:26.624026                           [Byte1]: 67

 3468 13:54:26.628437  

 3469 13:54:26.628993  Final RX Vref Byte 0 = 52 to rank0

 3470 13:54:26.632258  Final RX Vref Byte 1 = 50 to rank0

 3471 13:54:26.635101  Final RX Vref Byte 0 = 52 to rank1

 3472 13:54:26.638628  Final RX Vref Byte 1 = 50 to rank1==

 3473 13:54:26.642186  Dram Type= 6, Freq= 0, CH_1, rank 0

 3474 13:54:26.648841  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3475 13:54:26.649431  ==

 3476 13:54:26.649808  DQS Delay:

 3477 13:54:26.650215  DQS0 = 0, DQS1 = 0

 3478 13:54:26.651802  DQM Delay:

 3479 13:54:26.652267  DQM0 = 119, DQM1 = 112

 3480 13:54:26.655271  DQ Delay:

 3481 13:54:26.658783  DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =120

 3482 13:54:26.662298  DQ4 =118, DQ5 =126, DQ6 =128, DQ7 =118

 3483 13:54:26.665503  DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104

 3484 13:54:26.668535  DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118

 3485 13:54:26.669005  

 3486 13:54:26.669375  

 3487 13:54:26.675023  [DQSOSCAuto] RK0, (LSB)MR18= 0x519, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps

 3488 13:54:26.678805  CH1 RK0: MR19=404, MR18=519

 3489 13:54:26.685357  CH1_RK0: MR19=0x404, MR18=0x519, DQSOSC=400, MR23=63, INC=40, DEC=27

 3490 13:54:26.685919  

 3491 13:54:26.688565  ----->DramcWriteLeveling(PI) begin...

 3492 13:54:26.689225  ==

 3493 13:54:26.692108  Dram Type= 6, Freq= 0, CH_1, rank 1

 3494 13:54:26.695269  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3495 13:54:26.695830  ==

 3496 13:54:26.698610  Write leveling (Byte 0): 26 => 26

 3497 13:54:26.702131  Write leveling (Byte 1): 28 => 28

 3498 13:54:26.705306  DramcWriteLeveling(PI) end<-----

 3499 13:54:26.705774  

 3500 13:54:26.706187  ==

 3501 13:54:26.708617  Dram Type= 6, Freq= 0, CH_1, rank 1

 3502 13:54:26.715411  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3503 13:54:26.715992  ==

 3504 13:54:26.716370  [Gating] SW mode calibration

 3505 13:54:26.725378  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3506 13:54:26.728973  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3507 13:54:26.732369   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3508 13:54:26.739033   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3509 13:54:26.741992   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3510 13:54:26.745565   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3511 13:54:26.752431   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3512 13:54:26.755342   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3513 13:54:26.758562   0 15 24 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 0)

 3514 13:54:26.765437   0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 0)

 3515 13:54:26.768652   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3516 13:54:26.772290   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3517 13:54:26.778785   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3518 13:54:26.782452   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3519 13:54:26.785384   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3520 13:54:26.791763   1  0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 3521 13:54:26.795693   1  0 24 | B1->B0 | 3b3b 2c2c | 0 0 | (0 0) (0 0)

 3522 13:54:26.798983   1  0 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)

 3523 13:54:26.802142   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3524 13:54:26.808985   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3525 13:54:26.812186   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3526 13:54:26.815459   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3527 13:54:26.822296   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3528 13:54:26.825256   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3529 13:54:26.828865   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3530 13:54:26.835168   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 3531 13:54:26.838594   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3532 13:54:26.841904   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3533 13:54:26.848602   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3534 13:54:26.852317   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3535 13:54:26.855454   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3536 13:54:26.862052   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3537 13:54:26.865626   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3538 13:54:26.868798   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3539 13:54:26.874977   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3540 13:54:26.878807   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3541 13:54:26.881974   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3542 13:54:26.888398   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3543 13:54:26.891528   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3544 13:54:26.895193   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3545 13:54:26.901778   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3546 13:54:26.904881   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3547 13:54:26.908342  Total UI for P1: 0, mck2ui 16

 3548 13:54:26.911308  best dqsien dly found for B0: ( 1,  3, 24)

 3549 13:54:26.914558  Total UI for P1: 0, mck2ui 16

 3550 13:54:26.918391  best dqsien dly found for B1: ( 1,  3, 24)

 3551 13:54:26.921411  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 3552 13:54:26.924718  best DQS1 dly(MCK, UI, PI) = (1, 3, 24)

 3553 13:54:26.924868  

 3554 13:54:26.928273  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3555 13:54:26.931347  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3556 13:54:26.934551  [Gating] SW calibration Done

 3557 13:54:26.934672  ==

 3558 13:54:26.937754  Dram Type= 6, Freq= 0, CH_1, rank 1

 3559 13:54:26.941145  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3560 13:54:26.941265  ==

 3561 13:54:26.944753  RX Vref Scan: 0

 3562 13:54:26.944953  

 3563 13:54:26.948391  RX Vref 0 -> 0, step: 1

 3564 13:54:26.948531  

 3565 13:54:26.948625  RX Delay -40 -> 252, step: 8

 3566 13:54:26.954792  iDelay=200, Bit 0, Center 123 (64 ~ 183) 120

 3567 13:54:26.957937  iDelay=200, Bit 1, Center 111 (48 ~ 175) 128

 3568 13:54:26.961354  iDelay=200, Bit 2, Center 107 (48 ~ 167) 120

 3569 13:54:26.964659  iDelay=200, Bit 3, Center 123 (56 ~ 191) 136

 3570 13:54:26.967994  iDelay=200, Bit 4, Center 123 (56 ~ 191) 136

 3571 13:54:26.974471  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3572 13:54:26.977896  iDelay=200, Bit 6, Center 127 (64 ~ 191) 128

 3573 13:54:26.980938  iDelay=200, Bit 7, Center 115 (48 ~ 183) 136

 3574 13:54:26.984549  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3575 13:54:26.988137  iDelay=200, Bit 9, Center 103 (40 ~ 167) 128

 3576 13:54:26.994965  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3577 13:54:26.998398  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3578 13:54:27.001618  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3579 13:54:27.004735  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3580 13:54:27.008073  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3581 13:54:27.015169  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3582 13:54:27.015732  ==

 3583 13:54:27.018119  Dram Type= 6, Freq= 0, CH_1, rank 1

 3584 13:54:27.021689  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3585 13:54:27.022214  ==

 3586 13:54:27.022590  DQS Delay:

 3587 13:54:27.025086  DQS0 = 0, DQS1 = 0

 3588 13:54:27.025653  DQM Delay:

 3589 13:54:27.028263  DQM0 = 120, DQM1 = 113

 3590 13:54:27.028830  DQ Delay:

 3591 13:54:27.031311  DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123

 3592 13:54:27.034495  DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115

 3593 13:54:27.038045  DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107

 3594 13:54:27.041443  DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123

 3595 13:54:27.041917  

 3596 13:54:27.042343  

 3597 13:54:27.044889  ==

 3598 13:54:27.048138  Dram Type= 6, Freq= 0, CH_1, rank 1

 3599 13:54:27.051196  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3600 13:54:27.051674  ==

 3601 13:54:27.052049  

 3602 13:54:27.052392  

 3603 13:54:27.054649  	TX Vref Scan disable

 3604 13:54:27.055124   == TX Byte 0 ==

 3605 13:54:27.057995  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3606 13:54:27.064786  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3607 13:54:27.065372   == TX Byte 1 ==

 3608 13:54:27.068362  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3609 13:54:27.074631  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3610 13:54:27.075215  ==

 3611 13:54:27.078017  Dram Type= 6, Freq= 0, CH_1, rank 1

 3612 13:54:27.081296  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3613 13:54:27.081775  ==

 3614 13:54:27.093013  TX Vref=22, minBit 11, minWin=25, winSum=423

 3615 13:54:27.096640  TX Vref=24, minBit 1, minWin=25, winSum=423

 3616 13:54:27.099896  TX Vref=26, minBit 1, minWin=25, winSum=430

 3617 13:54:27.103132  TX Vref=28, minBit 10, minWin=26, winSum=431

 3618 13:54:27.106398  TX Vref=30, minBit 1, minWin=26, winSum=430

 3619 13:54:27.113061  TX Vref=32, minBit 1, minWin=26, winSum=427

 3620 13:54:27.116538  [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 28

 3621 13:54:27.117122  

 3622 13:54:27.119687  Final TX Range 1 Vref 28

 3623 13:54:27.120270  

 3624 13:54:27.120644  ==

 3625 13:54:27.123130  Dram Type= 6, Freq= 0, CH_1, rank 1

 3626 13:54:27.126553  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3627 13:54:27.130177  ==

 3628 13:54:27.130766  

 3629 13:54:27.131142  

 3630 13:54:27.131489  	TX Vref Scan disable

 3631 13:54:27.133095   == TX Byte 0 ==

 3632 13:54:27.136484  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3633 13:54:27.143139  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3634 13:54:27.143607   == TX Byte 1 ==

 3635 13:54:27.146127  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3636 13:54:27.153157  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3637 13:54:27.153624  

 3638 13:54:27.154040  [DATLAT]

 3639 13:54:27.154521  Freq=1200, CH1 RK1

 3640 13:54:27.154892  

 3641 13:54:27.156332  DATLAT Default: 0xd

 3642 13:54:27.156863  0, 0xFFFF, sum = 0

 3643 13:54:27.159480  1, 0xFFFF, sum = 0

 3644 13:54:27.163126  2, 0xFFFF, sum = 0

 3645 13:54:27.163719  3, 0xFFFF, sum = 0

 3646 13:54:27.166346  4, 0xFFFF, sum = 0

 3647 13:54:27.166883  5, 0xFFFF, sum = 0

 3648 13:54:27.169756  6, 0xFFFF, sum = 0

 3649 13:54:27.170347  7, 0xFFFF, sum = 0

 3650 13:54:27.172997  8, 0xFFFF, sum = 0

 3651 13:54:27.173606  9, 0xFFFF, sum = 0

 3652 13:54:27.176619  10, 0xFFFF, sum = 0

 3653 13:54:27.177191  11, 0xFFFF, sum = 0

 3654 13:54:27.179357  12, 0x0, sum = 1

 3655 13:54:27.179825  13, 0x0, sum = 2

 3656 13:54:27.183271  14, 0x0, sum = 3

 3657 13:54:27.183847  15, 0x0, sum = 4

 3658 13:54:27.184229  best_step = 13

 3659 13:54:27.186401  

 3660 13:54:27.186862  ==

 3661 13:54:27.189628  Dram Type= 6, Freq= 0, CH_1, rank 1

 3662 13:54:27.192999  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3663 13:54:27.193470  ==

 3664 13:54:27.193837  RX Vref Scan: 0

 3665 13:54:27.194237  

 3666 13:54:27.196129  RX Vref 0 -> 0, step: 1

 3667 13:54:27.196592  

 3668 13:54:27.199424  RX Delay -13 -> 252, step: 4

 3669 13:54:27.203116  iDelay=195, Bit 0, Center 124 (67 ~ 182) 116

 3670 13:54:27.209630  iDelay=195, Bit 1, Center 114 (55 ~ 174) 120

 3671 13:54:27.212736  iDelay=195, Bit 2, Center 108 (51 ~ 166) 116

 3672 13:54:27.216264  iDelay=195, Bit 3, Center 118 (59 ~ 178) 120

 3673 13:54:27.219372  iDelay=195, Bit 4, Center 122 (63 ~ 182) 120

 3674 13:54:27.223014  iDelay=195, Bit 5, Center 130 (67 ~ 194) 128

 3675 13:54:27.229668  iDelay=195, Bit 6, Center 126 (67 ~ 186) 120

 3676 13:54:27.232849  iDelay=195, Bit 7, Center 118 (59 ~ 178) 120

 3677 13:54:27.235792  iDelay=195, Bit 8, Center 98 (35 ~ 162) 128

 3678 13:54:27.239085  iDelay=195, Bit 9, Center 102 (39 ~ 166) 128

 3679 13:54:27.242520  iDelay=195, Bit 10, Center 114 (51 ~ 178) 128

 3680 13:54:27.249261  iDelay=195, Bit 11, Center 106 (43 ~ 170) 128

 3681 13:54:27.252545  iDelay=195, Bit 12, Center 122 (59 ~ 186) 128

 3682 13:54:27.255889  iDelay=195, Bit 13, Center 118 (55 ~ 182) 128

 3683 13:54:27.259100  iDelay=195, Bit 14, Center 122 (59 ~ 186) 128

 3684 13:54:27.262764  iDelay=195, Bit 15, Center 122 (59 ~ 186) 128

 3685 13:54:27.265976  ==

 3686 13:54:27.269135  Dram Type= 6, Freq= 0, CH_1, rank 1

 3687 13:54:27.272807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3688 13:54:27.273416  ==

 3689 13:54:27.273797  DQS Delay:

 3690 13:54:27.275654  DQS0 = 0, DQS1 = 0

 3691 13:54:27.276144  DQM Delay:

 3692 13:54:27.279335  DQM0 = 120, DQM1 = 113

 3693 13:54:27.279802  DQ Delay:

 3694 13:54:27.282878  DQ0 =124, DQ1 =114, DQ2 =108, DQ3 =118

 3695 13:54:27.286020  DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =118

 3696 13:54:27.289508  DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106

 3697 13:54:27.292687  DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122

 3698 13:54:27.293162  

 3699 13:54:27.293526  

 3700 13:54:27.302498  [DQSOSCAuto] RK1, (LSB)MR18= 0x9ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps

 3701 13:54:27.302972  CH1 RK1: MR19=403, MR18=9ED

 3702 13:54:27.309119  CH1_RK1: MR19=0x403, MR18=0x9ED, DQSOSC=406, MR23=63, INC=39, DEC=26

 3703 13:54:27.313064  [RxdqsGatingPostProcess] freq 1200

 3704 13:54:27.319599  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3705 13:54:27.322621  best DQS0 dly(2T, 0.5T) = (0, 11)

 3706 13:54:27.326008  best DQS1 dly(2T, 0.5T) = (0, 11)

 3707 13:54:27.329696  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3708 13:54:27.332929  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3709 13:54:27.336081  best DQS0 dly(2T, 0.5T) = (0, 11)

 3710 13:54:27.336663  best DQS1 dly(2T, 0.5T) = (0, 11)

 3711 13:54:27.339089  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3712 13:54:27.342375  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3713 13:54:27.345897  Pre-setting of DQS Precalculation

 3714 13:54:27.352274  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3715 13:54:27.359028  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3716 13:54:27.365523  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3717 13:54:27.366049  

 3718 13:54:27.366433  

 3719 13:54:27.369040  [Calibration Summary] 2400 Mbps

 3720 13:54:27.372173  CH 0, Rank 0

 3721 13:54:27.372988  SW Impedance     : PASS

 3722 13:54:27.375276  DUTY Scan        : NO K

 3723 13:54:27.378782  ZQ Calibration   : PASS

 3724 13:54:27.379260  Jitter Meter     : NO K

 3725 13:54:27.382407  CBT Training     : PASS

 3726 13:54:27.382885  Write leveling   : PASS

 3727 13:54:27.385687  RX DQS gating    : PASS

 3728 13:54:27.388801  RX DQ/DQS(RDDQC) : PASS

 3729 13:54:27.389273  TX DQ/DQS        : PASS

 3730 13:54:27.391980  RX DATLAT        : PASS

 3731 13:54:27.395377  RX DQ/DQS(Engine): PASS

 3732 13:54:27.395714  TX OE            : NO K

 3733 13:54:27.398927  All Pass.

 3734 13:54:27.399259  

 3735 13:54:27.399523  CH 0, Rank 1

 3736 13:54:27.401822  SW Impedance     : PASS

 3737 13:54:27.402192  DUTY Scan        : NO K

 3738 13:54:27.405152  ZQ Calibration   : PASS

 3739 13:54:27.409021  Jitter Meter     : NO K

 3740 13:54:27.409466  CBT Training     : PASS

 3741 13:54:27.412095  Write leveling   : PASS

 3742 13:54:27.415175  RX DQS gating    : PASS

 3743 13:54:27.415522  RX DQ/DQS(RDDQC) : PASS

 3744 13:54:27.418486  TX DQ/DQS        : PASS

 3745 13:54:27.422087  RX DATLAT        : PASS

 3746 13:54:27.422424  RX DQ/DQS(Engine): PASS

 3747 13:54:27.425579  TX OE            : NO K

 3748 13:54:27.426106  All Pass.

 3749 13:54:27.426457  

 3750 13:54:27.428934  CH 1, Rank 0

 3751 13:54:27.429469  SW Impedance     : PASS

 3752 13:54:27.432161  DUTY Scan        : NO K

 3753 13:54:27.435240  ZQ Calibration   : PASS

 3754 13:54:27.435782  Jitter Meter     : NO K

 3755 13:54:27.438534  CBT Training     : PASS

 3756 13:54:27.441697  Write leveling   : PASS

 3757 13:54:27.442217  RX DQS gating    : PASS

 3758 13:54:27.445359  RX DQ/DQS(RDDQC) : PASS

 3759 13:54:27.445982  TX DQ/DQS        : PASS

 3760 13:54:27.448535  RX DATLAT        : PASS

 3761 13:54:27.451689  RX DQ/DQS(Engine): PASS

 3762 13:54:27.452164  TX OE            : NO K

 3763 13:54:27.455019  All Pass.

 3764 13:54:27.455488  

 3765 13:54:27.455859  CH 1, Rank 1

 3766 13:54:27.458631  SW Impedance     : PASS

 3767 13:54:27.459102  DUTY Scan        : NO K

 3768 13:54:27.461602  ZQ Calibration   : PASS

 3769 13:54:27.464607  Jitter Meter     : NO K

 3770 13:54:27.465081  CBT Training     : PASS

 3771 13:54:27.468388  Write leveling   : PASS

 3772 13:54:27.471541  RX DQS gating    : PASS

 3773 13:54:27.472113  RX DQ/DQS(RDDQC) : PASS

 3774 13:54:27.474715  TX DQ/DQS        : PASS

 3775 13:54:27.478127  RX DATLAT        : PASS

 3776 13:54:27.478696  RX DQ/DQS(Engine): PASS

 3777 13:54:27.481277  TX OE            : NO K

 3778 13:54:27.481752  All Pass.

 3779 13:54:27.482180  

 3780 13:54:27.484633  DramC Write-DBI off

 3781 13:54:27.487873  	PER_BANK_REFRESH: Hybrid Mode

 3782 13:54:27.488346  TX_TRACKING: ON

 3783 13:54:27.497848  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3784 13:54:27.501486  [FAST_K] Save calibration result to emmc

 3785 13:54:27.504723  dramc_set_vcore_voltage set vcore to 650000

 3786 13:54:27.508167  Read voltage for 600, 5

 3787 13:54:27.508751  Vio18 = 0

 3788 13:54:27.509128  Vcore = 650000

 3789 13:54:27.511306  Vdram = 0

 3790 13:54:27.511777  Vddq = 0

 3791 13:54:27.512148  Vmddr = 0

 3792 13:54:27.517884  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3793 13:54:27.520794  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3794 13:54:27.524613  MEM_TYPE=3, freq_sel=19

 3795 13:54:27.527729  sv_algorithm_assistance_LP4_1600 

 3796 13:54:27.531031  ============ PULL DRAM RESETB DOWN ============

 3797 13:54:27.534473  ========== PULL DRAM RESETB DOWN end =========

 3798 13:54:27.541404  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3799 13:54:27.544724  =================================== 

 3800 13:54:27.547942  LPDDR4 DRAM CONFIGURATION

 3801 13:54:27.551006  =================================== 

 3802 13:54:27.551538  EX_ROW_EN[0]    = 0x0

 3803 13:54:27.554399  EX_ROW_EN[1]    = 0x0

 3804 13:54:27.554871  LP4Y_EN      = 0x0

 3805 13:54:27.557375  WORK_FSP     = 0x0

 3806 13:54:27.557846  WL           = 0x2

 3807 13:54:27.560709  RL           = 0x2

 3808 13:54:27.561184  BL           = 0x2

 3809 13:54:27.563931  RPST         = 0x0

 3810 13:54:27.564550  RD_PRE       = 0x0

 3811 13:54:27.567406  WR_PRE       = 0x1

 3812 13:54:27.567879  WR_PST       = 0x0

 3813 13:54:27.570760  DBI_WR       = 0x0

 3814 13:54:27.571235  DBI_RD       = 0x0

 3815 13:54:27.574252  OTF          = 0x1

 3816 13:54:27.578012  =================================== 

 3817 13:54:27.580694  =================================== 

 3818 13:54:27.581303  ANA top config

 3819 13:54:27.584122  =================================== 

 3820 13:54:27.587205  DLL_ASYNC_EN            =  0

 3821 13:54:27.590761  ALL_SLAVE_EN            =  1

 3822 13:54:27.593868  NEW_RANK_MODE           =  1

 3823 13:54:27.594393  DLL_IDLE_MODE           =  1

 3824 13:54:27.598147  LP45_APHY_COMB_EN       =  1

 3825 13:54:27.601032  TX_ODT_DIS              =  1

 3826 13:54:27.604125  NEW_8X_MODE             =  1

 3827 13:54:27.607192  =================================== 

 3828 13:54:27.610480  =================================== 

 3829 13:54:27.613976  data_rate                  = 1200

 3830 13:54:27.614553  CKR                        = 1

 3831 13:54:27.617267  DQ_P2S_RATIO               = 8

 3832 13:54:27.620783  =================================== 

 3833 13:54:27.623804  CA_P2S_RATIO               = 8

 3834 13:54:27.627431  DQ_CA_OPEN                 = 0

 3835 13:54:27.630612  DQ_SEMI_OPEN               = 0

 3836 13:54:27.634004  CA_SEMI_OPEN               = 0

 3837 13:54:27.634586  CA_FULL_RATE               = 0

 3838 13:54:27.637743  DQ_CKDIV4_EN               = 1

 3839 13:54:27.640803  CA_CKDIV4_EN               = 1

 3840 13:54:27.644378  CA_PREDIV_EN               = 0

 3841 13:54:27.647499  PH8_DLY                    = 0

 3842 13:54:27.650438  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3843 13:54:27.650918  DQ_AAMCK_DIV               = 4

 3844 13:54:27.654066  CA_AAMCK_DIV               = 4

 3845 13:54:27.657492  CA_ADMCK_DIV               = 4

 3846 13:54:27.660628  DQ_TRACK_CA_EN             = 0

 3847 13:54:27.664036  CA_PICK                    = 600

 3848 13:54:27.667249  CA_MCKIO                   = 600

 3849 13:54:27.670651  MCKIO_SEMI                 = 0

 3850 13:54:27.671412  PLL_FREQ                   = 2288

 3851 13:54:27.673472  DQ_UI_PI_RATIO             = 32

 3852 13:54:27.677000  CA_UI_PI_RATIO             = 0

 3853 13:54:27.680834  =================================== 

 3854 13:54:27.684245  =================================== 

 3855 13:54:27.686940  memory_type:LPDDR4         

 3856 13:54:27.687419  GP_NUM     : 10       

 3857 13:54:27.690433  SRAM_EN    : 1       

 3858 13:54:27.693561  MD32_EN    : 0       

 3859 13:54:27.696908  =================================== 

 3860 13:54:27.697381  [ANA_INIT] >>>>>>>>>>>>>> 

 3861 13:54:27.700408  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3862 13:54:27.703566  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3863 13:54:27.706998  =================================== 

 3864 13:54:27.710296  data_rate = 1200,PCW = 0X5800

 3865 13:54:27.713786  =================================== 

 3866 13:54:27.716809  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3867 13:54:27.723730  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3868 13:54:27.726879  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3869 13:54:27.733708  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3870 13:54:27.736950  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3871 13:54:27.740256  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3872 13:54:27.743917  [ANA_INIT] flow start 

 3873 13:54:27.744506  [ANA_INIT] PLL >>>>>>>> 

 3874 13:54:27.746738  [ANA_INIT] PLL <<<<<<<< 

 3875 13:54:27.749896  [ANA_INIT] MIDPI >>>>>>>> 

 3876 13:54:27.750412  [ANA_INIT] MIDPI <<<<<<<< 

 3877 13:54:27.753412  [ANA_INIT] DLL >>>>>>>> 

 3878 13:54:27.756997  [ANA_INIT] flow end 

 3879 13:54:27.759655  ============ LP4 DIFF to SE enter ============

 3880 13:54:27.763246  ============ LP4 DIFF to SE exit  ============

 3881 13:54:27.766576  [ANA_INIT] <<<<<<<<<<<<< 

 3882 13:54:27.770072  [Flow] Enable top DCM control >>>>> 

 3883 13:54:27.773323  [Flow] Enable top DCM control <<<<< 

 3884 13:54:27.776432  Enable DLL master slave shuffle 

 3885 13:54:27.779802  ============================================================== 

 3886 13:54:27.783319  Gating Mode config

 3887 13:54:27.790013  ============================================================== 

 3888 13:54:27.790603  Config description: 

 3889 13:54:27.799907  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3890 13:54:27.806525  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3891 13:54:27.809576  SELPH_MODE            0: By rank         1: By Phase 

 3892 13:54:27.816459  ============================================================== 

 3893 13:54:27.819797  GAT_TRACK_EN                 =  1

 3894 13:54:27.823309  RX_GATING_MODE               =  2

 3895 13:54:27.826754  RX_GATING_TRACK_MODE         =  2

 3896 13:54:27.829926  SELPH_MODE                   =  1

 3897 13:54:27.833190  PICG_EARLY_EN                =  1

 3898 13:54:27.836361  VALID_LAT_VALUE              =  1

 3899 13:54:27.839657  ============================================================== 

 3900 13:54:27.842714  Enter into Gating configuration >>>> 

 3901 13:54:27.846267  Exit from Gating configuration <<<< 

 3902 13:54:27.849723  Enter into  DVFS_PRE_config >>>>> 

 3903 13:54:27.859551  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3904 13:54:27.862760  Exit from  DVFS_PRE_config <<<<< 

 3905 13:54:27.866253  Enter into PICG configuration >>>> 

 3906 13:54:27.869577  Exit from PICG configuration <<<< 

 3907 13:54:27.873304  [RX_INPUT] configuration >>>>> 

 3908 13:54:27.876258  [RX_INPUT] configuration <<<<< 

 3909 13:54:27.883392  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3910 13:54:27.886266  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3911 13:54:27.893172  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3912 13:54:27.899709  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3913 13:54:27.906027  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3914 13:54:27.912854  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3915 13:54:27.916469  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3916 13:54:27.919632  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3917 13:54:27.922706  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3918 13:54:27.929533  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3919 13:54:27.933111  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3920 13:54:27.936303  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3921 13:54:27.939410  =================================== 

 3922 13:54:27.942874  LPDDR4 DRAM CONFIGURATION

 3923 13:54:27.946555  =================================== 

 3924 13:54:27.947140  EX_ROW_EN[0]    = 0x0

 3925 13:54:27.949556  EX_ROW_EN[1]    = 0x0

 3926 13:54:27.950180  LP4Y_EN      = 0x0

 3927 13:54:27.952814  WORK_FSP     = 0x0

 3928 13:54:27.953291  WL           = 0x2

 3929 13:54:27.956205  RL           = 0x2

 3930 13:54:27.959789  BL           = 0x2

 3931 13:54:27.960364  RPST         = 0x0

 3932 13:54:27.962816  RD_PRE       = 0x0

 3933 13:54:27.963394  WR_PRE       = 0x1

 3934 13:54:27.966525  WR_PST       = 0x0

 3935 13:54:27.967105  DBI_WR       = 0x0

 3936 13:54:27.970030  DBI_RD       = 0x0

 3937 13:54:27.970612  OTF          = 0x1

 3938 13:54:27.973188  =================================== 

 3939 13:54:27.975943  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3940 13:54:27.982962  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3941 13:54:27.985974  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3942 13:54:27.989416  =================================== 

 3943 13:54:27.992967  LPDDR4 DRAM CONFIGURATION

 3944 13:54:27.996000  =================================== 

 3945 13:54:27.996477  EX_ROW_EN[0]    = 0x10

 3946 13:54:27.999719  EX_ROW_EN[1]    = 0x0

 3947 13:54:28.000300  LP4Y_EN      = 0x0

 3948 13:54:28.002681  WORK_FSP     = 0x0

 3949 13:54:28.003332  WL           = 0x2

 3950 13:54:28.006403  RL           = 0x2

 3951 13:54:28.006992  BL           = 0x2

 3952 13:54:28.009579  RPST         = 0x0

 3953 13:54:28.010186  RD_PRE       = 0x0

 3954 13:54:28.012741  WR_PRE       = 0x1

 3955 13:54:28.013348  WR_PST       = 0x0

 3956 13:54:28.016201  DBI_WR       = 0x0

 3957 13:54:28.016674  DBI_RD       = 0x0

 3958 13:54:28.019247  OTF          = 0x1

 3959 13:54:28.023012  =================================== 

 3960 13:54:28.029788  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3961 13:54:28.033231  nWR fixed to 30

 3962 13:54:28.036445  [ModeRegInit_LP4] CH0 RK0

 3963 13:54:28.037025  [ModeRegInit_LP4] CH0 RK1

 3964 13:54:28.039517  [ModeRegInit_LP4] CH1 RK0

 3965 13:54:28.042645  [ModeRegInit_LP4] CH1 RK1

 3966 13:54:28.043119  match AC timing 17

 3967 13:54:28.049607  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3968 13:54:28.052726  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3969 13:54:28.056117  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3970 13:54:28.062619  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3971 13:54:28.066332  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3972 13:54:28.066917  ==

 3973 13:54:28.069404  Dram Type= 6, Freq= 0, CH_0, rank 0

 3974 13:54:28.072559  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3975 13:54:28.073141  ==

 3976 13:54:28.079124  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3977 13:54:28.085815  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3978 13:54:28.089424  [CA 0] Center 36 (6~67) winsize 62

 3979 13:54:28.092682  [CA 1] Center 36 (6~67) winsize 62

 3980 13:54:28.095859  [CA 2] Center 34 (4~65) winsize 62

 3981 13:54:28.099403  [CA 3] Center 34 (3~65) winsize 63

 3982 13:54:28.102427  [CA 4] Center 33 (3~64) winsize 62

 3983 13:54:28.105781  [CA 5] Center 33 (2~64) winsize 63

 3984 13:54:28.106329  

 3985 13:54:28.109437  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3986 13:54:28.110074  

 3987 13:54:28.112045  [CATrainingPosCal] consider 1 rank data

 3988 13:54:28.115630  u2DelayCellTimex100 = 270/100 ps

 3989 13:54:28.119003  CA0 delay=36 (6~67),Diff = 3 PI (28 cell)

 3990 13:54:28.122222  CA1 delay=36 (6~67),Diff = 3 PI (28 cell)

 3991 13:54:28.125375  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3992 13:54:28.129060  CA3 delay=34 (3~65),Diff = 1 PI (9 cell)

 3993 13:54:28.132248  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 3994 13:54:28.139392  CA5 delay=33 (2~64),Diff = 0 PI (0 cell)

 3995 13:54:28.139994  

 3996 13:54:28.142054  CA PerBit enable=1, Macro0, CA PI delay=33

 3997 13:54:28.142529  

 3998 13:54:28.145823  [CBTSetCACLKResult] CA Dly = 33

 3999 13:54:28.146477  CS Dly: 5 (0~36)

 4000 13:54:28.146863  ==

 4001 13:54:28.149213  Dram Type= 6, Freq= 0, CH_0, rank 1

 4002 13:54:28.152099  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4003 13:54:28.155627  ==

 4004 13:54:28.159160  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4005 13:54:28.165640  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 4006 13:54:28.168801  [CA 0] Center 36 (6~67) winsize 62

 4007 13:54:28.172427  [CA 1] Center 36 (6~67) winsize 62

 4008 13:54:28.175624  [CA 2] Center 35 (4~66) winsize 63

 4009 13:54:28.178852  [CA 3] Center 35 (4~66) winsize 63

 4010 13:54:28.182559  [CA 4] Center 34 (3~65) winsize 63

 4011 13:54:28.185853  [CA 5] Center 34 (3~65) winsize 63

 4012 13:54:28.186460  

 4013 13:54:28.189046  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 4014 13:54:28.189631  

 4015 13:54:28.192002  [CATrainingPosCal] consider 2 rank data

 4016 13:54:28.195460  u2DelayCellTimex100 = 270/100 ps

 4017 13:54:28.199211  CA0 delay=36 (6~67),Diff = 3 PI (28 cell)

 4018 13:54:28.202455  CA1 delay=36 (6~67),Diff = 3 PI (28 cell)

 4019 13:54:28.205507  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4020 13:54:28.208803  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 4021 13:54:28.215198  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 4022 13:54:28.218723  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4023 13:54:28.219199  

 4024 13:54:28.222269  CA PerBit enable=1, Macro0, CA PI delay=33

 4025 13:54:28.222745  

 4026 13:54:28.225106  [CBTSetCACLKResult] CA Dly = 33

 4027 13:54:28.225579  CS Dly: 5 (0~37)

 4028 13:54:28.226043  

 4029 13:54:28.228959  ----->DramcWriteLeveling(PI) begin...

 4030 13:54:28.229541  ==

 4031 13:54:28.232241  Dram Type= 6, Freq= 0, CH_0, rank 0

 4032 13:54:28.238532  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4033 13:54:28.239107  ==

 4034 13:54:28.241798  Write leveling (Byte 0): 32 => 32

 4035 13:54:28.245446  Write leveling (Byte 1): 31 => 31

 4036 13:54:28.246053  DramcWriteLeveling(PI) end<-----

 4037 13:54:28.246437  

 4038 13:54:28.248642  ==

 4039 13:54:28.251813  Dram Type= 6, Freq= 0, CH_0, rank 0

 4040 13:54:28.255195  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4041 13:54:28.255673  ==

 4042 13:54:28.258150  [Gating] SW mode calibration

 4043 13:54:28.265068  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4044 13:54:28.268760  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4045 13:54:28.275075   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4046 13:54:28.278819   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4047 13:54:28.281916   0  9  8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 4048 13:54:28.288631   0  9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)

 4049 13:54:28.291702   0  9 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)

 4050 13:54:28.294962   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4051 13:54:28.302202   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4052 13:54:28.305342   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4053 13:54:28.308454   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4054 13:54:28.314966   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4055 13:54:28.318290   0 10  8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 4056 13:54:28.321581   0 10 12 | B1->B0 | 2525 3938 | 0 1 | (0 0) (0 0)

 4057 13:54:28.328012   0 10 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)

 4058 13:54:28.331699   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4059 13:54:28.334806   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4060 13:54:28.338705   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4061 13:54:28.344799   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4062 13:54:28.348670   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4063 13:54:28.351931   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4064 13:54:28.359078   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4065 13:54:28.361761   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4066 13:54:28.364895   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4067 13:54:28.371650   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4068 13:54:28.374978   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4069 13:54:28.378332   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4070 13:54:28.385158   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4071 13:54:28.388133   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4072 13:54:28.391422   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4073 13:54:28.398112   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4074 13:54:28.401849   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4075 13:54:28.405225   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4076 13:54:28.411396   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4077 13:54:28.414452   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4078 13:54:28.418251   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4079 13:54:28.424779   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4080 13:54:28.428137   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4081 13:54:28.431056   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4082 13:54:28.434534  Total UI for P1: 0, mck2ui 16

 4083 13:54:28.437777  best dqsien dly found for B0: ( 0, 13, 14)

 4084 13:54:28.441100  Total UI for P1: 0, mck2ui 16

 4085 13:54:28.444650  best dqsien dly found for B1: ( 0, 13, 14)

 4086 13:54:28.447760  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4087 13:54:28.451030  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4088 13:54:28.451517  

 4089 13:54:28.457698  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4090 13:54:28.461087  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4091 13:54:28.461567  [Gating] SW calibration Done

 4092 13:54:28.464405  ==

 4093 13:54:28.467937  Dram Type= 6, Freq= 0, CH_0, rank 0

 4094 13:54:28.470927  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4095 13:54:28.471403  ==

 4096 13:54:28.471778  RX Vref Scan: 0

 4097 13:54:28.472125  

 4098 13:54:28.474150  RX Vref 0 -> 0, step: 1

 4099 13:54:28.474623  

 4100 13:54:28.477907  RX Delay -230 -> 252, step: 16

 4101 13:54:28.481357  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4102 13:54:28.484591  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4103 13:54:28.490687  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4104 13:54:28.494193  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4105 13:54:28.497825  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4106 13:54:28.500731  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4107 13:54:28.507575  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4108 13:54:28.510727  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4109 13:54:28.514583  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4110 13:54:28.517168  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4111 13:54:28.520235  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4112 13:54:28.527622  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4113 13:54:28.530856  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4114 13:54:28.534220  iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320

 4115 13:54:28.537521  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4116 13:54:28.543923  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4117 13:54:28.544492  ==

 4118 13:54:28.547090  Dram Type= 6, Freq= 0, CH_0, rank 0

 4119 13:54:28.550519  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4120 13:54:28.550994  ==

 4121 13:54:28.551364  DQS Delay:

 4122 13:54:28.554056  DQS0 = 0, DQS1 = 0

 4123 13:54:28.554530  DQM Delay:

 4124 13:54:28.557092  DQM0 = 51, DQM1 = 39

 4125 13:54:28.557564  DQ Delay:

 4126 13:54:28.560368  DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41

 4127 13:54:28.563621  DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57

 4128 13:54:28.567270  DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33

 4129 13:54:28.570277  DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41

 4130 13:54:28.570751  

 4131 13:54:28.571122  

 4132 13:54:28.571465  ==

 4133 13:54:28.573879  Dram Type= 6, Freq= 0, CH_0, rank 0

 4134 13:54:28.577037  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4135 13:54:28.577514  ==

 4136 13:54:28.580483  

 4137 13:54:28.581059  

 4138 13:54:28.581439  	TX Vref Scan disable

 4139 13:54:28.584163   == TX Byte 0 ==

 4140 13:54:28.587345  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4141 13:54:28.590716  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4142 13:54:28.593891   == TX Byte 1 ==

 4143 13:54:28.597291  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4144 13:54:28.600356  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4145 13:54:28.600850  ==

 4146 13:54:28.604142  Dram Type= 6, Freq= 0, CH_0, rank 0

 4147 13:54:28.610580  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4148 13:54:28.611170  ==

 4149 13:54:28.611548  

 4150 13:54:28.611892  

 4151 13:54:28.612218  	TX Vref Scan disable

 4152 13:54:28.615054   == TX Byte 0 ==

 4153 13:54:28.618628  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4154 13:54:28.621745  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4155 13:54:28.624926   == TX Byte 1 ==

 4156 13:54:28.628532  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4157 13:54:28.632157  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4158 13:54:28.635099  

 4159 13:54:28.635682  [DATLAT]

 4160 13:54:28.636060  Freq=600, CH0 RK0

 4161 13:54:28.636414  

 4162 13:54:28.638612  DATLAT Default: 0x9

 4163 13:54:28.639196  0, 0xFFFF, sum = 0

 4164 13:54:28.641932  1, 0xFFFF, sum = 0

 4165 13:54:28.642559  2, 0xFFFF, sum = 0

 4166 13:54:28.645444  3, 0xFFFF, sum = 0

 4167 13:54:28.646101  4, 0xFFFF, sum = 0

 4168 13:54:28.648668  5, 0xFFFF, sum = 0

 4169 13:54:28.651784  6, 0xFFFF, sum = 0

 4170 13:54:28.652287  7, 0xFFFF, sum = 0

 4171 13:54:28.652954  8, 0x0, sum = 1

 4172 13:54:28.654770  9, 0x0, sum = 2

 4173 13:54:28.655343  10, 0x0, sum = 3

 4174 13:54:28.657901  11, 0x0, sum = 4

 4175 13:54:28.658424  best_step = 9

 4176 13:54:28.658817  

 4177 13:54:28.659289  ==

 4178 13:54:28.661545  Dram Type= 6, Freq= 0, CH_0, rank 0

 4179 13:54:28.668160  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4180 13:54:28.668688  ==

 4181 13:54:28.669279  RX Vref Scan: 1

 4182 13:54:28.669647  

 4183 13:54:28.671339  RX Vref 0 -> 0, step: 1

 4184 13:54:28.671886  

 4185 13:54:28.675126  RX Delay -179 -> 252, step: 8

 4186 13:54:28.675597  

 4187 13:54:28.678370  Set Vref, RX VrefLevel [Byte0]: 62

 4188 13:54:28.681510                           [Byte1]: 50

 4189 13:54:28.681977  

 4190 13:54:28.685002  Final RX Vref Byte 0 = 62 to rank0

 4191 13:54:28.688112  Final RX Vref Byte 1 = 50 to rank0

 4192 13:54:28.691576  Final RX Vref Byte 0 = 62 to rank1

 4193 13:54:28.694875  Final RX Vref Byte 1 = 50 to rank1==

 4194 13:54:28.698061  Dram Type= 6, Freq= 0, CH_0, rank 0

 4195 13:54:28.701327  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4196 13:54:28.701670  ==

 4197 13:54:28.704767  DQS Delay:

 4198 13:54:28.705100  DQS0 = 0, DQS1 = 0

 4199 13:54:28.705367  DQM Delay:

 4200 13:54:28.707759  DQM0 = 48, DQM1 = 39

 4201 13:54:28.708094  DQ Delay:

 4202 13:54:28.711682  DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44

 4203 13:54:28.714809  DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56

 4204 13:54:28.718202  DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32

 4205 13:54:28.721456  DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48

 4206 13:54:28.721888  

 4207 13:54:28.722206  

 4208 13:54:28.731265  [DQSOSCAuto] RK0, (LSB)MR18= 0x5751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps

 4209 13:54:28.731705  CH0 RK0: MR19=808, MR18=5751

 4210 13:54:28.738235  CH0_RK0: MR19=0x808, MR18=0x5751, DQSOSC=393, MR23=63, INC=169, DEC=113

 4211 13:54:28.738670  

 4212 13:54:28.741552  ----->DramcWriteLeveling(PI) begin...

 4213 13:54:28.744537  ==

 4214 13:54:28.748240  Dram Type= 6, Freq= 0, CH_0, rank 1

 4215 13:54:28.751358  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4216 13:54:28.751702  ==

 4217 13:54:28.754389  Write leveling (Byte 0): 33 => 33

 4218 13:54:28.757747  Write leveling (Byte 1): 30 => 30

 4219 13:54:28.761098  DramcWriteLeveling(PI) end<-----

 4220 13:54:28.761538  

 4221 13:54:28.761876  ==

 4222 13:54:28.764587  Dram Type= 6, Freq= 0, CH_0, rank 1

 4223 13:54:28.767666  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4224 13:54:28.768101  ==

 4225 13:54:28.770928  [Gating] SW mode calibration

 4226 13:54:28.777634  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4227 13:54:28.783911  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4228 13:54:28.787230   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4229 13:54:28.790560   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4230 13:54:28.797179   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4231 13:54:28.800692   0  9 12 | B1->B0 | 3333 3030 | 1 1 | (1 0) (1 0)

 4232 13:54:28.804213   0  9 16 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)

 4233 13:54:28.810536   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4234 13:54:28.813770   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4235 13:54:28.817331   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4236 13:54:28.823743   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4237 13:54:28.827660   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4238 13:54:28.830648   0 10  8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)

 4239 13:54:28.834260   0 10 12 | B1->B0 | 2e2e 3333 | 0 0 | (0 0) (0 0)

 4240 13:54:28.840779   0 10 16 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)

 4241 13:54:28.844079   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4242 13:54:28.847040   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4243 13:54:28.854163   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4244 13:54:28.857276   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4245 13:54:28.860563   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4246 13:54:28.867146   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4247 13:54:28.870174   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4248 13:54:28.873766   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4249 13:54:28.880331   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4250 13:54:28.883926   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4251 13:54:28.886899   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4252 13:54:28.893383   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4253 13:54:28.896668   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4254 13:54:28.899987   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4255 13:54:28.907329   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4256 13:54:28.910206   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4257 13:54:28.913432   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4258 13:54:28.920506   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4259 13:54:28.923629   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4260 13:54:28.927054   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4261 13:54:28.933560   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4262 13:54:28.936492   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4263 13:54:28.940408   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4264 13:54:28.946409   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4265 13:54:28.947004  Total UI for P1: 0, mck2ui 16

 4266 13:54:28.953208  best dqsien dly found for B0: ( 0, 13, 12)

 4267 13:54:28.956628   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4268 13:54:28.959762  Total UI for P1: 0, mck2ui 16

 4269 13:54:28.963463  best dqsien dly found for B1: ( 0, 13, 14)

 4270 13:54:28.966381  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4271 13:54:28.970161  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4272 13:54:28.970643  

 4273 13:54:28.973491  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4274 13:54:28.976627  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4275 13:54:28.980021  [Gating] SW calibration Done

 4276 13:54:28.980490  ==

 4277 13:54:28.983479  Dram Type= 6, Freq= 0, CH_0, rank 1

 4278 13:54:28.986372  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4279 13:54:28.989797  ==

 4280 13:54:28.990167  RX Vref Scan: 0

 4281 13:54:28.990445  

 4282 13:54:28.992960  RX Vref 0 -> 0, step: 1

 4283 13:54:28.993202  

 4284 13:54:28.996315  RX Delay -230 -> 252, step: 16

 4285 13:54:28.999724  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4286 13:54:29.002874  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4287 13:54:29.006324  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4288 13:54:29.009635  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4289 13:54:29.016367  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4290 13:54:29.019901  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4291 13:54:29.022764  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4292 13:54:29.026559  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4293 13:54:29.033155  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4294 13:54:29.036392  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4295 13:54:29.039325  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4296 13:54:29.043132  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4297 13:54:29.049414  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4298 13:54:29.052772  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4299 13:54:29.055868  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4300 13:54:29.059858  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4301 13:54:29.060189  ==

 4302 13:54:29.062671  Dram Type= 6, Freq= 0, CH_0, rank 1

 4303 13:54:29.069683  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4304 13:54:29.070030  ==

 4305 13:54:29.070293  DQS Delay:

 4306 13:54:29.070536  DQS0 = 0, DQS1 = 0

 4307 13:54:29.072728  DQM Delay:

 4308 13:54:29.072969  DQM0 = 48, DQM1 = 42

 4309 13:54:29.076022  DQ Delay:

 4310 13:54:29.079396  DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41

 4311 13:54:29.082670  DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57

 4312 13:54:29.085862  DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41

 4313 13:54:29.089167  DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49

 4314 13:54:29.089307  

 4315 13:54:29.089414  

 4316 13:54:29.089513  ==

 4317 13:54:29.092707  Dram Type= 6, Freq= 0, CH_0, rank 1

 4318 13:54:29.096039  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4319 13:54:29.096184  ==

 4320 13:54:29.096293  

 4321 13:54:29.096392  

 4322 13:54:29.099329  	TX Vref Scan disable

 4323 13:54:29.099552   == TX Byte 0 ==

 4324 13:54:29.106017  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4325 13:54:29.109326  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4326 13:54:29.109547   == TX Byte 1 ==

 4327 13:54:29.115861  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4328 13:54:29.119361  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4329 13:54:29.119645  ==

 4330 13:54:29.122764  Dram Type= 6, Freq= 0, CH_0, rank 1

 4331 13:54:29.125828  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4332 13:54:29.126091  ==

 4333 13:54:29.126282  

 4334 13:54:29.129161  

 4335 13:54:29.129500  	TX Vref Scan disable

 4336 13:54:29.132936   == TX Byte 0 ==

 4337 13:54:29.136320  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4338 13:54:29.139388  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4339 13:54:29.143112   == TX Byte 1 ==

 4340 13:54:29.146291  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4341 13:54:29.149257  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4342 13:54:29.153283  

 4343 13:54:29.153857  [DATLAT]

 4344 13:54:29.154293  Freq=600, CH0 RK1

 4345 13:54:29.154645  

 4346 13:54:29.156448  DATLAT Default: 0x9

 4347 13:54:29.157019  0, 0xFFFF, sum = 0

 4348 13:54:29.159974  1, 0xFFFF, sum = 0

 4349 13:54:29.160555  2, 0xFFFF, sum = 0

 4350 13:54:29.163153  3, 0xFFFF, sum = 0

 4351 13:54:29.163741  4, 0xFFFF, sum = 0

 4352 13:54:29.166071  5, 0xFFFF, sum = 0

 4353 13:54:29.169699  6, 0xFFFF, sum = 0

 4354 13:54:29.170338  7, 0xFFFF, sum = 0

 4355 13:54:29.170719  8, 0x0, sum = 1

 4356 13:54:29.172781  9, 0x0, sum = 2

 4357 13:54:29.173364  10, 0x0, sum = 3

 4358 13:54:29.176208  11, 0x0, sum = 4

 4359 13:54:29.176788  best_step = 9

 4360 13:54:29.177153  

 4361 13:54:29.177485  ==

 4362 13:54:29.179516  Dram Type= 6, Freq= 0, CH_0, rank 1

 4363 13:54:29.185872  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4364 13:54:29.186373  ==

 4365 13:54:29.186733  RX Vref Scan: 0

 4366 13:54:29.187066  

 4367 13:54:29.189451  RX Vref 0 -> 0, step: 1

 4368 13:54:29.190045  

 4369 13:54:29.192682  RX Delay -179 -> 252, step: 8

 4370 13:54:29.196234  iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304

 4371 13:54:29.202643  iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296

 4372 13:54:29.205866  iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296

 4373 13:54:29.209552  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4374 13:54:29.212447  iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296

 4375 13:54:29.215855  iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296

 4376 13:54:29.222298  iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296

 4377 13:54:29.225754  iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296

 4378 13:54:29.228904  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4379 13:54:29.232256  iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288

 4380 13:54:29.235554  iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296

 4381 13:54:29.242514  iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288

 4382 13:54:29.245859  iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296

 4383 13:54:29.248690  iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288

 4384 13:54:29.252404  iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296

 4385 13:54:29.259122  iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296

 4386 13:54:29.259358  ==

 4387 13:54:29.262363  Dram Type= 6, Freq= 0, CH_0, rank 1

 4388 13:54:29.265736  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4389 13:54:29.266024  ==

 4390 13:54:29.266185  DQS Delay:

 4391 13:54:29.269138  DQS0 = 0, DQS1 = 0

 4392 13:54:29.269402  DQM Delay:

 4393 13:54:29.272567  DQM0 = 48, DQM1 = 40

 4394 13:54:29.272868  DQ Delay:

 4395 13:54:29.276098  DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44

 4396 13:54:29.279059  DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56

 4397 13:54:29.282434  DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36

 4398 13:54:29.286049  DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48

 4399 13:54:29.286566  

 4400 13:54:29.286903  

 4401 13:54:29.292490  [DQSOSCAuto] RK1, (LSB)MR18= 0x612f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps

 4402 13:54:29.295669  CH0 RK1: MR19=808, MR18=612F

 4403 13:54:29.302380  CH0_RK1: MR19=0x808, MR18=0x612F, DQSOSC=391, MR23=63, INC=171, DEC=114

 4404 13:54:29.305693  [RxdqsGatingPostProcess] freq 600

 4405 13:54:29.312310  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4406 13:54:29.315310  Pre-setting of DQS Precalculation

 4407 13:54:29.318676  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4408 13:54:29.319191  ==

 4409 13:54:29.322443  Dram Type= 6, Freq= 0, CH_1, rank 0

 4410 13:54:29.325603  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4411 13:54:29.326114  ==

 4412 13:54:29.332258  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4413 13:54:29.338822  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31

 4414 13:54:29.342011  [CA 0] Center 35 (5~66) winsize 62

 4415 13:54:29.345459  [CA 1] Center 35 (5~66) winsize 62

 4416 13:54:29.348684  [CA 2] Center 34 (3~65) winsize 63

 4417 13:54:29.352351  [CA 3] Center 33 (3~64) winsize 62

 4418 13:54:29.355284  [CA 4] Center 33 (3~64) winsize 62

 4419 13:54:29.358456  [CA 5] Center 33 (3~64) winsize 62

 4420 13:54:29.358805  

 4421 13:54:29.361848  [CmdBusTrainingLP45] Vref(ca) range 1: 31

 4422 13:54:29.362252  

 4423 13:54:29.365744  [CATrainingPosCal] consider 1 rank data

 4424 13:54:29.368762  u2DelayCellTimex100 = 270/100 ps

 4425 13:54:29.372218  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4426 13:54:29.375711  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4427 13:54:29.378724  CA2 delay=34 (3~65),Diff = 1 PI (9 cell)

 4428 13:54:29.382452  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4429 13:54:29.385925  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 4430 13:54:29.388941  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4431 13:54:29.389536  

 4432 13:54:29.396011  CA PerBit enable=1, Macro0, CA PI delay=33

 4433 13:54:29.396610  

 4434 13:54:29.398689  [CBTSetCACLKResult] CA Dly = 33

 4435 13:54:29.399202  CS Dly: 4 (0~35)

 4436 13:54:29.399596  ==

 4437 13:54:29.402227  Dram Type= 6, Freq= 0, CH_1, rank 1

 4438 13:54:29.405660  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4439 13:54:29.406174  ==

 4440 13:54:29.412271  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4441 13:54:29.418746  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4442 13:54:29.422366  [CA 0] Center 35 (5~66) winsize 62

 4443 13:54:29.425652  [CA 1] Center 35 (5~66) winsize 62

 4444 13:54:29.428880  [CA 2] Center 34 (4~65) winsize 62

 4445 13:54:29.432887  [CA 3] Center 34 (4~65) winsize 62

 4446 13:54:29.435491  [CA 4] Center 34 (4~65) winsize 62

 4447 13:54:29.439065  [CA 5] Center 33 (3~64) winsize 62

 4448 13:54:29.439548  

 4449 13:54:29.442303  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4450 13:54:29.442777  

 4451 13:54:29.445504  [CATrainingPosCal] consider 2 rank data

 4452 13:54:29.448716  u2DelayCellTimex100 = 270/100 ps

 4453 13:54:29.452100  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4454 13:54:29.455451  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4455 13:54:29.458941  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4456 13:54:29.462104  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 4457 13:54:29.465638  CA4 delay=34 (4~64),Diff = 1 PI (9 cell)

 4458 13:54:29.469136  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4459 13:54:29.469602  

 4460 13:54:29.475458  CA PerBit enable=1, Macro0, CA PI delay=33

 4461 13:54:29.475783  

 4462 13:54:29.478396  [CBTSetCACLKResult] CA Dly = 33

 4463 13:54:29.478638  CS Dly: 5 (0~37)

 4464 13:54:29.478828  

 4465 13:54:29.482177  ----->DramcWriteLeveling(PI) begin...

 4466 13:54:29.482371  ==

 4467 13:54:29.485124  Dram Type= 6, Freq= 0, CH_1, rank 0

 4468 13:54:29.488954  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4469 13:54:29.489267  ==

 4470 13:54:29.492373  Write leveling (Byte 0): 28 => 28

 4471 13:54:29.495281  Write leveling (Byte 1): 31 => 31

 4472 13:54:29.498516  DramcWriteLeveling(PI) end<-----

 4473 13:54:29.498765  

 4474 13:54:29.498902  ==

 4475 13:54:29.502055  Dram Type= 6, Freq= 0, CH_1, rank 0

 4476 13:54:29.508272  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4477 13:54:29.508461  ==

 4478 13:54:29.508588  [Gating] SW mode calibration

 4479 13:54:29.518518  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4480 13:54:29.522499  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4481 13:54:29.525530   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4482 13:54:29.531868   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4483 13:54:29.535703   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4484 13:54:29.538823   0  9 12 | B1->B0 | 2a2a 2626 | 0 0 | (1 0) (1 1)

 4485 13:54:29.545171   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4486 13:54:29.548223   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4487 13:54:29.552206   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4488 13:54:29.558632   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4489 13:54:29.562203   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4490 13:54:29.565065   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4491 13:54:29.571956   0 10  8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 4492 13:54:29.575266   0 10 12 | B1->B0 | 3737 3f3f | 0 0 | (0 0) (0 0)

 4493 13:54:29.578657   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4494 13:54:29.585115   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4495 13:54:29.588571   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4496 13:54:29.591830   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4497 13:54:29.598477   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4498 13:54:29.602058   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4499 13:54:29.605493   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4500 13:54:29.611946   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4501 13:54:29.615241   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4502 13:54:29.618421   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4503 13:54:29.625217   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4504 13:54:29.628274   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4505 13:54:29.632057   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4506 13:54:29.635307   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4507 13:54:29.642302   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4508 13:54:29.645061   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4509 13:54:29.648424   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4510 13:54:29.655208   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4511 13:54:29.658548   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4512 13:54:29.661999   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4513 13:54:29.668986   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4514 13:54:29.672081   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4515 13:54:29.675209   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4516 13:54:29.682082   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4517 13:54:29.685503   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4518 13:54:29.688694  Total UI for P1: 0, mck2ui 16

 4519 13:54:29.691944  best dqsien dly found for B0: ( 0, 13, 10)

 4520 13:54:29.695261  Total UI for P1: 0, mck2ui 16

 4521 13:54:29.698521  best dqsien dly found for B1: ( 0, 13, 12)

 4522 13:54:29.702012  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4523 13:54:29.705155  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4524 13:54:29.705628  

 4525 13:54:29.708534  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4526 13:54:29.711313  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4527 13:54:29.714971  [Gating] SW calibration Done

 4528 13:54:29.715444  ==

 4529 13:54:29.718425  Dram Type= 6, Freq= 0, CH_1, rank 0

 4530 13:54:29.721360  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4531 13:54:29.724678  ==

 4532 13:54:29.725148  RX Vref Scan: 0

 4533 13:54:29.725514  

 4534 13:54:29.728294  RX Vref 0 -> 0, step: 1

 4535 13:54:29.728762  

 4536 13:54:29.731650  RX Delay -230 -> 252, step: 16

 4537 13:54:29.734853  iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288

 4538 13:54:29.738312  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4539 13:54:29.741756  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4540 13:54:29.748112  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4541 13:54:29.751456  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4542 13:54:29.754767  iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304

 4543 13:54:29.758211  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4544 13:54:29.761141  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4545 13:54:29.768248  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4546 13:54:29.771697  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4547 13:54:29.774616  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4548 13:54:29.778375  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4549 13:54:29.784988  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4550 13:54:29.788215  iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320

 4551 13:54:29.791545  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4552 13:54:29.794913  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4553 13:54:29.795520  ==

 4554 13:54:29.798386  Dram Type= 6, Freq= 0, CH_1, rank 0

 4555 13:54:29.805118  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4556 13:54:29.805746  ==

 4557 13:54:29.806277  DQS Delay:

 4558 13:54:29.806735  DQS0 = 0, DQS1 = 0

 4559 13:54:29.807991  DQM Delay:

 4560 13:54:29.808477  DQM0 = 53, DQM1 = 45

 4561 13:54:29.811317  DQ Delay:

 4562 13:54:29.814588  DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49

 4563 13:54:29.818395  DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49

 4564 13:54:29.821666  DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =33

 4565 13:54:29.824529  DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57

 4566 13:54:29.825125  

 4567 13:54:29.825496  

 4568 13:54:29.825843  ==

 4569 13:54:29.827945  Dram Type= 6, Freq= 0, CH_1, rank 0

 4570 13:54:29.831478  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4571 13:54:29.832054  ==

 4572 13:54:29.832427  

 4573 13:54:29.832774  

 4574 13:54:29.834618  	TX Vref Scan disable

 4575 13:54:29.835093   == TX Byte 0 ==

 4576 13:54:29.841286  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4577 13:54:29.844362  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4578 13:54:29.844841   == TX Byte 1 ==

 4579 13:54:29.851043  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4580 13:54:29.854283  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4581 13:54:29.854757  ==

 4582 13:54:29.857764  Dram Type= 6, Freq= 0, CH_1, rank 0

 4583 13:54:29.860868  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4584 13:54:29.861358  ==

 4585 13:54:29.861750  

 4586 13:54:29.864025  

 4587 13:54:29.864504  	TX Vref Scan disable

 4588 13:54:29.867899   == TX Byte 0 ==

 4589 13:54:29.871027  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4590 13:54:29.877472  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4591 13:54:29.877718   == TX Byte 1 ==

 4592 13:54:29.881005  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4593 13:54:29.887682  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4594 13:54:29.888163  

 4595 13:54:29.888463  [DATLAT]

 4596 13:54:29.888691  Freq=600, CH1 RK0

 4597 13:54:29.888869  

 4598 13:54:29.890913  DATLAT Default: 0x9

 4599 13:54:29.891153  0, 0xFFFF, sum = 0

 4600 13:54:29.894115  1, 0xFFFF, sum = 0

 4601 13:54:29.894358  2, 0xFFFF, sum = 0

 4602 13:54:29.897607  3, 0xFFFF, sum = 0

 4603 13:54:29.900598  4, 0xFFFF, sum = 0

 4604 13:54:29.900868  5, 0xFFFF, sum = 0

 4605 13:54:29.903788  6, 0xFFFF, sum = 0

 4606 13:54:29.904111  7, 0xFFFF, sum = 0

 4607 13:54:29.907285  8, 0x0, sum = 1

 4608 13:54:29.907553  9, 0x0, sum = 2

 4609 13:54:29.907751  10, 0x0, sum = 3

 4610 13:54:29.910641  11, 0x0, sum = 4

 4611 13:54:29.910893  best_step = 9

 4612 13:54:29.911088  

 4613 13:54:29.911265  ==

 4614 13:54:29.913842  Dram Type= 6, Freq= 0, CH_1, rank 0

 4615 13:54:29.920877  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4616 13:54:29.921146  ==

 4617 13:54:29.921353  RX Vref Scan: 1

 4618 13:54:29.921549  

 4619 13:54:29.923905  RX Vref 0 -> 0, step: 1

 4620 13:54:29.924161  

 4621 13:54:29.927418  RX Delay -179 -> 252, step: 8

 4622 13:54:29.927745  

 4623 13:54:29.930938  Set Vref, RX VrefLevel [Byte0]: 52

 4624 13:54:29.934009                           [Byte1]: 50

 4625 13:54:29.934264  

 4626 13:54:29.937746  Final RX Vref Byte 0 = 52 to rank0

 4627 13:54:29.941048  Final RX Vref Byte 1 = 50 to rank0

 4628 13:54:29.944635  Final RX Vref Byte 0 = 52 to rank1

 4629 13:54:29.947940  Final RX Vref Byte 1 = 50 to rank1==

 4630 13:54:29.951003  Dram Type= 6, Freq= 0, CH_1, rank 0

 4631 13:54:29.954823  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4632 13:54:29.955397  ==

 4633 13:54:29.958124  DQS Delay:

 4634 13:54:29.958590  DQS0 = 0, DQS1 = 0

 4635 13:54:29.958958  DQM Delay:

 4636 13:54:29.960941  DQM0 = 48, DQM1 = 40

 4637 13:54:29.961406  DQ Delay:

 4638 13:54:29.964693  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4639 13:54:29.967838  DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44

 4640 13:54:29.971181  DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32

 4641 13:54:29.974455  DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48

 4642 13:54:29.975130  

 4643 13:54:29.975742  

 4644 13:54:29.984376  [DQSOSCAuto] RK0, (LSB)MR18= 0x466d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps

 4645 13:54:29.984879  CH1 RK0: MR19=808, MR18=466D

 4646 13:54:29.990752  CH1_RK0: MR19=0x808, MR18=0x466D, DQSOSC=389, MR23=63, INC=173, DEC=115

 4647 13:54:29.991220  

 4648 13:54:29.994027  ----->DramcWriteLeveling(PI) begin...

 4649 13:54:29.997624  ==

 4650 13:54:30.000554  Dram Type= 6, Freq= 0, CH_1, rank 1

 4651 13:54:30.004114  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4652 13:54:30.004584  ==

 4653 13:54:30.007126  Write leveling (Byte 0): 31 => 31

 4654 13:54:30.010579  Write leveling (Byte 1): 30 => 30

 4655 13:54:30.013828  DramcWriteLeveling(PI) end<-----

 4656 13:54:30.014188  

 4657 13:54:30.014395  ==

 4658 13:54:30.017516  Dram Type= 6, Freq= 0, CH_1, rank 1

 4659 13:54:30.020635  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4660 13:54:30.020997  ==

 4661 13:54:30.024036  [Gating] SW mode calibration

 4662 13:54:30.030610  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4663 13:54:30.037704  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4664 13:54:30.040783   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4665 13:54:30.043623   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4666 13:54:30.050838   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4667 13:54:30.053725   0  9 12 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 1)

 4668 13:54:30.057158   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4669 13:54:30.063797   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4670 13:54:30.067113   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4671 13:54:30.070264   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4672 13:54:30.077147   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4673 13:54:30.079979   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4674 13:54:30.083141   0 10  8 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)

 4675 13:54:30.086734   0 10 12 | B1->B0 | 4040 3131 | 0 1 | (0 0) (0 0)

 4676 13:54:30.093763   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4677 13:54:30.096892   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4678 13:54:30.100327   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4679 13:54:30.106582   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4680 13:54:30.110131   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4681 13:54:30.113489   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4682 13:54:30.120018   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4683 13:54:30.123295   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 4684 13:54:30.126633   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4685 13:54:30.133565   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4686 13:54:30.136624   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4687 13:54:30.140461   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4688 13:54:30.146783   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4689 13:54:30.149906   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4690 13:54:30.153429   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4691 13:54:30.159899   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4692 13:54:30.163544   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4693 13:54:30.166523   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4694 13:54:30.173522   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4695 13:54:30.176703   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4696 13:54:30.179792   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4697 13:54:30.186745   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4698 13:54:30.189887   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4699 13:54:30.193272   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4700 13:54:30.199833   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4701 13:54:30.200390  Total UI for P1: 0, mck2ui 16

 4702 13:54:30.202931  best dqsien dly found for B0: ( 0, 13, 12)

 4703 13:54:30.206376  Total UI for P1: 0, mck2ui 16

 4704 13:54:30.209852  best dqsien dly found for B1: ( 0, 13, 12)

 4705 13:54:30.216776  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4706 13:54:30.219947  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4707 13:54:30.220419  

 4708 13:54:30.223371  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4709 13:54:30.226528  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4710 13:54:30.230051  [Gating] SW calibration Done

 4711 13:54:30.230627  ==

 4712 13:54:30.232861  Dram Type= 6, Freq= 0, CH_1, rank 1

 4713 13:54:30.236794  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4714 13:54:30.237376  ==

 4715 13:54:30.240040  RX Vref Scan: 0

 4716 13:54:30.240795  

 4717 13:54:30.241185  RX Vref 0 -> 0, step: 1

 4718 13:54:30.241532  

 4719 13:54:30.243229  RX Delay -230 -> 252, step: 16

 4720 13:54:30.246606  iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288

 4721 13:54:30.252970  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4722 13:54:30.256524  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4723 13:54:30.259665  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4724 13:54:30.262951  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4725 13:54:30.265906  iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304

 4726 13:54:30.272899  iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288

 4727 13:54:30.276160  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4728 13:54:30.279429  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4729 13:54:30.282845  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4730 13:54:30.289848  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4731 13:54:30.292645  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4732 13:54:30.296374  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4733 13:54:30.299628  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4734 13:54:30.306109  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4735 13:54:30.309205  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4736 13:54:30.309531  ==

 4737 13:54:30.312818  Dram Type= 6, Freq= 0, CH_1, rank 1

 4738 13:54:30.316428  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4739 13:54:30.317011  ==

 4740 13:54:30.319415  DQS Delay:

 4741 13:54:30.319882  DQS0 = 0, DQS1 = 0

 4742 13:54:30.320254  DQM Delay:

 4743 13:54:30.322809  DQM0 = 51, DQM1 = 46

 4744 13:54:30.323278  DQ Delay:

 4745 13:54:30.325898  DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49

 4746 13:54:30.329533  DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49

 4747 13:54:30.332886  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4748 13:54:30.336268  DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57

 4749 13:54:30.336837  

 4750 13:54:30.337205  

 4751 13:54:30.337546  ==

 4752 13:54:30.339273  Dram Type= 6, Freq= 0, CH_1, rank 1

 4753 13:54:30.346097  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4754 13:54:30.346668  ==

 4755 13:54:30.347043  

 4756 13:54:30.347389  

 4757 13:54:30.347718  	TX Vref Scan disable

 4758 13:54:30.349588   == TX Byte 0 ==

 4759 13:54:30.352662  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4760 13:54:30.356778  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4761 13:54:30.359271   == TX Byte 1 ==

 4762 13:54:30.362508  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4763 13:54:30.366175  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4764 13:54:30.369644  ==

 4765 13:54:30.372471  Dram Type= 6, Freq= 0, CH_1, rank 1

 4766 13:54:30.375821  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4767 13:54:30.376318  ==

 4768 13:54:30.376701  

 4769 13:54:30.377074  

 4770 13:54:30.379269  	TX Vref Scan disable

 4771 13:54:30.379807   == TX Byte 0 ==

 4772 13:54:30.385785  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4773 13:54:30.389097  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4774 13:54:30.389574   == TX Byte 1 ==

 4775 13:54:30.395622  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4776 13:54:30.399306  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4777 13:54:30.399794  

 4778 13:54:30.400281  [DATLAT]

 4779 13:54:30.402621  Freq=600, CH1 RK1

 4780 13:54:30.403107  

 4781 13:54:30.403586  DATLAT Default: 0x9

 4782 13:54:30.405858  0, 0xFFFF, sum = 0

 4783 13:54:30.406295  1, 0xFFFF, sum = 0

 4784 13:54:30.408981  2, 0xFFFF, sum = 0

 4785 13:54:30.409329  3, 0xFFFF, sum = 0

 4786 13:54:30.412287  4, 0xFFFF, sum = 0

 4787 13:54:30.416311  5, 0xFFFF, sum = 0

 4788 13:54:30.416674  6, 0xFFFF, sum = 0

 4789 13:54:30.419111  7, 0xFFFF, sum = 0

 4790 13:54:30.419461  8, 0x0, sum = 1

 4791 13:54:30.419811  9, 0x0, sum = 2

 4792 13:54:30.422545  10, 0x0, sum = 3

 4793 13:54:30.422895  11, 0x0, sum = 4

 4794 13:54:30.426051  best_step = 9

 4795 13:54:30.426394  

 4796 13:54:30.426737  ==

 4797 13:54:30.429161  Dram Type= 6, Freq= 0, CH_1, rank 1

 4798 13:54:30.432452  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4799 13:54:30.432809  ==

 4800 13:54:30.435990  RX Vref Scan: 0

 4801 13:54:30.436428  

 4802 13:54:30.436779  RX Vref 0 -> 0, step: 1

 4803 13:54:30.437104  

 4804 13:54:30.438987  RX Delay -163 -> 252, step: 8

 4805 13:54:30.446596  iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280

 4806 13:54:30.449752  iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280

 4807 13:54:30.452799  iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280

 4808 13:54:30.456772  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4809 13:54:30.459956  iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280

 4810 13:54:30.466459  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4811 13:54:30.470000  iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280

 4812 13:54:30.473264  iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280

 4813 13:54:30.476341  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4814 13:54:30.479697  iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288

 4815 13:54:30.486562  iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288

 4816 13:54:30.489480  iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288

 4817 13:54:30.493177  iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288

 4818 13:54:30.496329  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4819 13:54:30.503125  iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296

 4820 13:54:30.506228  iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296

 4821 13:54:30.506911  ==

 4822 13:54:30.509100  Dram Type= 6, Freq= 0, CH_1, rank 1

 4823 13:54:30.512729  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4824 13:54:30.513401  ==

 4825 13:54:30.515967  DQS Delay:

 4826 13:54:30.516608  DQS0 = 0, DQS1 = 0

 4827 13:54:30.517217  DQM Delay:

 4828 13:54:30.519193  DQM0 = 49, DQM1 = 44

 4829 13:54:30.519851  DQ Delay:

 4830 13:54:30.522479  DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44

 4831 13:54:30.526267  DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48

 4832 13:54:30.529592  DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36

 4833 13:54:30.532710  DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56

 4834 13:54:30.533167  

 4835 13:54:30.533584  

 4836 13:54:30.542252  [DQSOSCAuto] RK1, (LSB)MR18= 0x561c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps

 4837 13:54:30.542539  CH1 RK1: MR19=808, MR18=561C

 4838 13:54:30.549397  CH1_RK1: MR19=0x808, MR18=0x561C, DQSOSC=393, MR23=63, INC=169, DEC=113

 4839 13:54:30.552545  [RxdqsGatingPostProcess] freq 600

 4840 13:54:30.558802  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4841 13:54:30.562456  Pre-setting of DQS Precalculation

 4842 13:54:30.565831  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4843 13:54:30.572608  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4844 13:54:30.582309  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4845 13:54:30.582629  

 4846 13:54:30.582824  

 4847 13:54:30.582999  [Calibration Summary] 1200 Mbps

 4848 13:54:30.586252  CH 0, Rank 0

 4849 13:54:30.589306  SW Impedance     : PASS

 4850 13:54:30.589685  DUTY Scan        : NO K

 4851 13:54:30.592810  ZQ Calibration   : PASS

 4852 13:54:30.593305  Jitter Meter     : NO K

 4853 13:54:30.596005  CBT Training     : PASS

 4854 13:54:30.599101  Write leveling   : PASS

 4855 13:54:30.599675  RX DQS gating    : PASS

 4856 13:54:30.602787  RX DQ/DQS(RDDQC) : PASS

 4857 13:54:30.606086  TX DQ/DQS        : PASS

 4858 13:54:30.606557  RX DATLAT        : PASS

 4859 13:54:30.608985  RX DQ/DQS(Engine): PASS

 4860 13:54:30.612262  TX OE            : NO K

 4861 13:54:30.612732  All Pass.

 4862 13:54:30.613104  

 4863 13:54:30.613446  CH 0, Rank 1

 4864 13:54:30.616122  SW Impedance     : PASS

 4865 13:54:30.619001  DUTY Scan        : NO K

 4866 13:54:30.619478  ZQ Calibration   : PASS

 4867 13:54:30.622446  Jitter Meter     : NO K

 4868 13:54:30.626100  CBT Training     : PASS

 4869 13:54:30.626591  Write leveling   : PASS

 4870 13:54:30.629089  RX DQS gating    : PASS

 4871 13:54:30.632598  RX DQ/DQS(RDDQC) : PASS

 4872 13:54:30.633068  TX DQ/DQS        : PASS

 4873 13:54:30.635525  RX DATLAT        : PASS

 4874 13:54:30.636028  RX DQ/DQS(Engine): PASS

 4875 13:54:30.638969  TX OE            : NO K

 4876 13:54:30.639628  All Pass.

 4877 13:54:30.640235  

 4878 13:54:30.642216  CH 1, Rank 0

 4879 13:54:30.642882  SW Impedance     : PASS

 4880 13:54:30.645857  DUTY Scan        : NO K

 4881 13:54:30.649228  ZQ Calibration   : PASS

 4882 13:54:30.649892  Jitter Meter     : NO K

 4883 13:54:30.652625  CBT Training     : PASS

 4884 13:54:30.655611  Write leveling   : PASS

 4885 13:54:30.656187  RX DQS gating    : PASS

 4886 13:54:30.658676  RX DQ/DQS(RDDQC) : PASS

 4887 13:54:30.662001  TX DQ/DQS        : PASS

 4888 13:54:30.662351  RX DATLAT        : PASS

 4889 13:54:30.665395  RX DQ/DQS(Engine): PASS

 4890 13:54:30.668784  TX OE            : NO K

 4891 13:54:30.668978  All Pass.

 4892 13:54:30.669130  

 4893 13:54:30.669271  CH 1, Rank 1

 4894 13:54:30.672373  SW Impedance     : PASS

 4895 13:54:30.675425  DUTY Scan        : NO K

 4896 13:54:30.675671  ZQ Calibration   : PASS

 4897 13:54:30.678518  Jitter Meter     : NO K

 4898 13:54:30.681764  CBT Training     : PASS

 4899 13:54:30.681984  Write leveling   : PASS

 4900 13:54:30.685281  RX DQS gating    : PASS

 4901 13:54:30.688490  RX DQ/DQS(RDDQC) : PASS

 4902 13:54:30.688652  TX DQ/DQS        : PASS

 4903 13:54:30.692019  RX DATLAT        : PASS

 4904 13:54:30.692489  RX DQ/DQS(Engine): PASS

 4905 13:54:30.695163  TX OE            : NO K

 4906 13:54:30.695644  All Pass.

 4907 13:54:30.696014  

 4908 13:54:30.699081  DramC Write-DBI off

 4909 13:54:30.702371  	PER_BANK_REFRESH: Hybrid Mode

 4910 13:54:30.702980  TX_TRACKING: ON

 4911 13:54:30.712325  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4912 13:54:30.715571  [FAST_K] Save calibration result to emmc

 4913 13:54:30.718758  dramc_set_vcore_voltage set vcore to 662500

 4914 13:54:30.721973  Read voltage for 933, 3

 4915 13:54:30.722451  Vio18 = 0

 4916 13:54:30.725256  Vcore = 662500

 4917 13:54:30.725923  Vdram = 0

 4918 13:54:30.726581  Vddq = 0

 4919 13:54:30.727023  Vmddr = 0

 4920 13:54:30.732247  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4921 13:54:30.735000  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4922 13:54:30.738514  MEM_TYPE=3, freq_sel=17

 4923 13:54:30.741833  sv_algorithm_assistance_LP4_1600 

 4924 13:54:30.745660  ============ PULL DRAM RESETB DOWN ============

 4925 13:54:30.751635  ========== PULL DRAM RESETB DOWN end =========

 4926 13:54:30.754918  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4927 13:54:30.758635  =================================== 

 4928 13:54:30.761751  LPDDR4 DRAM CONFIGURATION

 4929 13:54:30.765320  =================================== 

 4930 13:54:30.765919  EX_ROW_EN[0]    = 0x0

 4931 13:54:30.768653  EX_ROW_EN[1]    = 0x0

 4932 13:54:30.769236  LP4Y_EN      = 0x0

 4933 13:54:30.772119  WORK_FSP     = 0x0

 4934 13:54:30.772735  WL           = 0x3

 4935 13:54:30.775180  RL           = 0x3

 4936 13:54:30.775853  BL           = 0x2

 4937 13:54:30.778395  RPST         = 0x0

 4938 13:54:30.778868  RD_PRE       = 0x0

 4939 13:54:30.781471  WR_PRE       = 0x1

 4940 13:54:30.784770  WR_PST       = 0x0

 4941 13:54:30.785241  DBI_WR       = 0x0

 4942 13:54:30.788235  DBI_RD       = 0x0

 4943 13:54:30.788891  OTF          = 0x1

 4944 13:54:30.791558  =================================== 

 4945 13:54:30.794751  =================================== 

 4946 13:54:30.795228  ANA top config

 4947 13:54:30.798173  =================================== 

 4948 13:54:30.801214  DLL_ASYNC_EN            =  0

 4949 13:54:30.804637  ALL_SLAVE_EN            =  1

 4950 13:54:30.807780  NEW_RANK_MODE           =  1

 4951 13:54:30.811253  DLL_IDLE_MODE           =  1

 4952 13:54:30.811693  LP45_APHY_COMB_EN       =  1

 4953 13:54:30.814791  TX_ODT_DIS              =  1

 4954 13:54:30.817590  NEW_8X_MODE             =  1

 4955 13:54:30.820887  =================================== 

 4956 13:54:30.824781  =================================== 

 4957 13:54:30.828261  data_rate                  = 1866

 4958 13:54:30.831022  CKR                        = 1

 4959 13:54:30.831269  DQ_P2S_RATIO               = 8

 4960 13:54:30.835024  =================================== 

 4961 13:54:30.837850  CA_P2S_RATIO               = 8

 4962 13:54:30.841686  DQ_CA_OPEN                 = 0

 4963 13:54:30.844455  DQ_SEMI_OPEN               = 0

 4964 13:54:30.847686  CA_SEMI_OPEN               = 0

 4965 13:54:30.851016  CA_FULL_RATE               = 0

 4966 13:54:30.851518  DQ_CKDIV4_EN               = 1

 4967 13:54:30.854804  CA_CKDIV4_EN               = 1

 4968 13:54:30.857639  CA_PREDIV_EN               = 0

 4969 13:54:30.861356  PH8_DLY                    = 0

 4970 13:54:30.864673  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4971 13:54:30.867824  DQ_AAMCK_DIV               = 4

 4972 13:54:30.868398  CA_AAMCK_DIV               = 4

 4973 13:54:30.871213  CA_ADMCK_DIV               = 4

 4974 13:54:30.874692  DQ_TRACK_CA_EN             = 0

 4975 13:54:30.878028  CA_PICK                    = 933

 4976 13:54:30.880873  CA_MCKIO                   = 933

 4977 13:54:30.884593  MCKIO_SEMI                 = 0

 4978 13:54:30.887824  PLL_FREQ                   = 3732

 4979 13:54:30.888302  DQ_UI_PI_RATIO             = 32

 4980 13:54:30.891174  CA_UI_PI_RATIO             = 0

 4981 13:54:30.894345  =================================== 

 4982 13:54:30.897788  =================================== 

 4983 13:54:30.901039  memory_type:LPDDR4         

 4984 13:54:30.904530  GP_NUM     : 10       

 4985 13:54:30.905124  SRAM_EN    : 1       

 4986 13:54:30.907708  MD32_EN    : 0       

 4987 13:54:30.911172  =================================== 

 4988 13:54:30.914245  [ANA_INIT] >>>>>>>>>>>>>> 

 4989 13:54:30.914721  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4990 13:54:30.917582  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4991 13:54:30.920638  =================================== 

 4992 13:54:30.923896  data_rate = 1866,PCW = 0X8f00

 4993 13:54:30.927677  =================================== 

 4994 13:54:30.930529  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4995 13:54:30.937300  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4996 13:54:30.944046  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4997 13:54:30.947273  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4998 13:54:30.950486  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4999 13:54:30.953878  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 5000 13:54:30.957045  [ANA_INIT] flow start 

 5001 13:54:30.957237  [ANA_INIT] PLL >>>>>>>> 

 5002 13:54:30.960042  [ANA_INIT] PLL <<<<<<<< 

 5003 13:54:30.963525  [ANA_INIT] MIDPI >>>>>>>> 

 5004 13:54:30.967249  [ANA_INIT] MIDPI <<<<<<<< 

 5005 13:54:30.967533  [ANA_INIT] DLL >>>>>>>> 

 5006 13:54:30.970297  [ANA_INIT] flow end 

 5007 13:54:30.973832  ============ LP4 DIFF to SE enter ============

 5008 13:54:30.976916  ============ LP4 DIFF to SE exit  ============

 5009 13:54:30.980207  [ANA_INIT] <<<<<<<<<<<<< 

 5010 13:54:30.983504  [Flow] Enable top DCM control >>>>> 

 5011 13:54:30.986905  [Flow] Enable top DCM control <<<<< 

 5012 13:54:30.990284  Enable DLL master slave shuffle 

 5013 13:54:30.993966  ============================================================== 

 5014 13:54:30.997194  Gating Mode config

 5015 13:54:31.003808  ============================================================== 

 5016 13:54:31.004362  Config description: 

 5017 13:54:31.013889  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 5018 13:54:31.020572  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 5019 13:54:31.026934  SELPH_MODE            0: By rank         1: By Phase 

 5020 13:54:31.030718  ============================================================== 

 5021 13:54:31.033843  GAT_TRACK_EN                 =  1

 5022 13:54:31.037413  RX_GATING_MODE               =  2

 5023 13:54:31.040339  RX_GATING_TRACK_MODE         =  2

 5024 13:54:31.043291  SELPH_MODE                   =  1

 5025 13:54:31.046497  PICG_EARLY_EN                =  1

 5026 13:54:31.050158  VALID_LAT_VALUE              =  1

 5027 13:54:31.053478  ============================================================== 

 5028 13:54:31.056825  Enter into Gating configuration >>>> 

 5029 13:54:31.059686  Exit from Gating configuration <<<< 

 5030 13:54:31.063052  Enter into  DVFS_PRE_config >>>>> 

 5031 13:54:31.076564  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 5032 13:54:31.079852  Exit from  DVFS_PRE_config <<<<< 

 5033 13:54:31.083206  Enter into PICG configuration >>>> 

 5034 13:54:31.083344  Exit from PICG configuration <<<< 

 5035 13:54:31.086439  [RX_INPUT] configuration >>>>> 

 5036 13:54:31.089839  [RX_INPUT] configuration <<<<< 

 5037 13:54:31.096549  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 5038 13:54:31.099900  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 5039 13:54:31.106754  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 5040 13:54:31.113281  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 5041 13:54:31.120150  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5042 13:54:31.126702  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5043 13:54:31.130088  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5044 13:54:31.133396  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5045 13:54:31.136750  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5046 13:54:31.143142  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5047 13:54:31.146609  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5048 13:54:31.149893  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5049 13:54:31.153208  =================================== 

 5050 13:54:31.156053  LPDDR4 DRAM CONFIGURATION

 5051 13:54:31.159704  =================================== 

 5052 13:54:31.162964  EX_ROW_EN[0]    = 0x0

 5053 13:54:31.163485  EX_ROW_EN[1]    = 0x0

 5054 13:54:31.166084  LP4Y_EN      = 0x0

 5055 13:54:31.166547  WORK_FSP     = 0x0

 5056 13:54:31.169468  WL           = 0x3

 5057 13:54:31.170082  RL           = 0x3

 5058 13:54:31.173134  BL           = 0x2

 5059 13:54:31.173692  RPST         = 0x0

 5060 13:54:31.176219  RD_PRE       = 0x0

 5061 13:54:31.176687  WR_PRE       = 0x1

 5062 13:54:31.179362  WR_PST       = 0x0

 5063 13:54:31.179836  DBI_WR       = 0x0

 5064 13:54:31.183058  DBI_RD       = 0x0

 5065 13:54:31.183528  OTF          = 0x1

 5066 13:54:31.186060  =================================== 

 5067 13:54:31.192441  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5068 13:54:31.196045  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5069 13:54:31.199376  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5070 13:54:31.202478  =================================== 

 5071 13:54:31.205894  LPDDR4 DRAM CONFIGURATION

 5072 13:54:31.209458  =================================== 

 5073 13:54:31.212422  EX_ROW_EN[0]    = 0x10

 5074 13:54:31.212703  EX_ROW_EN[1]    = 0x0

 5075 13:54:31.216083  LP4Y_EN      = 0x0

 5076 13:54:31.216416  WORK_FSP     = 0x0

 5077 13:54:31.219491  WL           = 0x3

 5078 13:54:31.219825  RL           = 0x3

 5079 13:54:31.222425  BL           = 0x2

 5080 13:54:31.222671  RPST         = 0x0

 5081 13:54:31.225886  RD_PRE       = 0x0

 5082 13:54:31.226242  WR_PRE       = 0x1

 5083 13:54:31.229476  WR_PST       = 0x0

 5084 13:54:31.229724  DBI_WR       = 0x0

 5085 13:54:31.232397  DBI_RD       = 0x0

 5086 13:54:31.232728  OTF          = 0x1

 5087 13:54:31.235707  =================================== 

 5088 13:54:31.242680  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5089 13:54:31.247574  nWR fixed to 30

 5090 13:54:31.250858  [ModeRegInit_LP4] CH0 RK0

 5091 13:54:31.251430  [ModeRegInit_LP4] CH0 RK1

 5092 13:54:31.254003  [ModeRegInit_LP4] CH1 RK0

 5093 13:54:31.257224  [ModeRegInit_LP4] CH1 RK1

 5094 13:54:31.257795  match AC timing 9

 5095 13:54:31.263980  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5096 13:54:31.267396  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5097 13:54:31.270569  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5098 13:54:31.277305  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5099 13:54:31.280176  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5100 13:54:31.280651  ==

 5101 13:54:31.283882  Dram Type= 6, Freq= 0, CH_0, rank 0

 5102 13:54:31.286902  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5103 13:54:31.287376  ==

 5104 13:54:31.293699  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5105 13:54:31.300631  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5106 13:54:31.303774  [CA 0] Center 38 (7~69) winsize 63

 5107 13:54:31.306926  [CA 1] Center 38 (7~69) winsize 63

 5108 13:54:31.310185  [CA 2] Center 35 (5~66) winsize 62

 5109 13:54:31.313654  [CA 3] Center 35 (5~65) winsize 61

 5110 13:54:31.316708  [CA 4] Center 34 (4~64) winsize 61

 5111 13:54:31.320145  [CA 5] Center 33 (3~64) winsize 62

 5112 13:54:31.320617  

 5113 13:54:31.323295  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5114 13:54:31.323770  

 5115 13:54:31.326553  [CATrainingPosCal] consider 1 rank data

 5116 13:54:31.330384  u2DelayCellTimex100 = 270/100 ps

 5117 13:54:31.333786  CA0 delay=38 (7~69),Diff = 5 PI (31 cell)

 5118 13:54:31.336616  CA1 delay=38 (7~69),Diff = 5 PI (31 cell)

 5119 13:54:31.339903  CA2 delay=35 (5~66),Diff = 2 PI (12 cell)

 5120 13:54:31.343067  CA3 delay=35 (5~65),Diff = 2 PI (12 cell)

 5121 13:54:31.346550  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5122 13:54:31.350146  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5123 13:54:31.353522  

 5124 13:54:31.356613  CA PerBit enable=1, Macro0, CA PI delay=33

 5125 13:54:31.356890  

 5126 13:54:31.360385  [CBTSetCACLKResult] CA Dly = 33

 5127 13:54:31.360669  CS Dly: 7 (0~38)

 5128 13:54:31.360834  ==

 5129 13:54:31.363247  Dram Type= 6, Freq= 0, CH_0, rank 1

 5130 13:54:31.366859  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5131 13:54:31.367144  ==

 5132 13:54:31.373588  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5133 13:54:31.380050  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 5134 13:54:31.383106  [CA 0] Center 38 (8~69) winsize 62

 5135 13:54:31.386817  [CA 1] Center 38 (8~69) winsize 62

 5136 13:54:31.390092  [CA 2] Center 36 (6~66) winsize 61

 5137 13:54:31.393476  [CA 3] Center 35 (5~66) winsize 62

 5138 13:54:31.396426  [CA 4] Center 35 (4~66) winsize 63

 5139 13:54:31.399984  [CA 5] Center 34 (4~65) winsize 62

 5140 13:54:31.400561  

 5141 13:54:31.403298  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 5142 13:54:31.403773  

 5143 13:54:31.406635  [CATrainingPosCal] consider 2 rank data

 5144 13:54:31.409788  u2DelayCellTimex100 = 270/100 ps

 5145 13:54:31.413012  CA0 delay=38 (8~69),Diff = 4 PI (24 cell)

 5146 13:54:31.416231  CA1 delay=38 (8~69),Diff = 4 PI (24 cell)

 5147 13:54:31.419802  CA2 delay=36 (6~66),Diff = 2 PI (12 cell)

 5148 13:54:31.423195  CA3 delay=35 (5~65),Diff = 1 PI (6 cell)

 5149 13:54:31.429791  CA4 delay=34 (4~64),Diff = 0 PI (0 cell)

 5150 13:54:31.433103  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5151 13:54:31.433575  

 5152 13:54:31.436328  CA PerBit enable=1, Macro0, CA PI delay=34

 5153 13:54:31.436804  

 5154 13:54:31.439574  [CBTSetCACLKResult] CA Dly = 34

 5155 13:54:31.440168  CS Dly: 7 (0~39)

 5156 13:54:31.440548  

 5157 13:54:31.443317  ----->DramcWriteLeveling(PI) begin...

 5158 13:54:31.443798  ==

 5159 13:54:31.446541  Dram Type= 6, Freq= 0, CH_0, rank 0

 5160 13:54:31.452976  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5161 13:54:31.453455  ==

 5162 13:54:31.456408  Write leveling (Byte 0): 33 => 33

 5163 13:54:31.457030  Write leveling (Byte 1): 29 => 29

 5164 13:54:31.460002  DramcWriteLeveling(PI) end<-----

 5165 13:54:31.460471  

 5166 13:54:31.460840  ==

 5167 13:54:31.462865  Dram Type= 6, Freq= 0, CH_0, rank 0

 5168 13:54:31.469833  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5169 13:54:31.470357  ==

 5170 13:54:31.473036  [Gating] SW mode calibration

 5171 13:54:31.479443  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5172 13:54:31.482762  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5173 13:54:31.489796   0 14  0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)

 5174 13:54:31.493171   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5175 13:54:31.496176   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5176 13:54:31.502867   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5177 13:54:31.506973   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5178 13:54:31.509430   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5179 13:54:31.516019   0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)

 5180 13:54:31.519521   0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)

 5181 13:54:31.522719   0 15  0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)

 5182 13:54:31.529598   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5183 13:54:31.532533   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5184 13:54:31.536137   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5185 13:54:31.542888   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5186 13:54:31.546120   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5187 13:54:31.549568   0 15 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)

 5188 13:54:31.552948   0 15 28 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)

 5189 13:54:31.559043   1  0  0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)

 5190 13:54:31.562603   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5191 13:54:31.566085   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5192 13:54:31.572806   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5193 13:54:31.576079   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5194 13:54:31.579202   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5195 13:54:31.585648   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5196 13:54:31.589352   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 5197 13:54:31.592642   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5198 13:54:31.599211   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5199 13:54:31.602381   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5200 13:54:31.605660   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5201 13:54:31.612167   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5202 13:54:31.615514   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5203 13:54:31.619005   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5204 13:54:31.625636   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5205 13:54:31.628964   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5206 13:54:31.632589   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5207 13:54:31.639173   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5208 13:54:31.642568   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5209 13:54:31.645910   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5210 13:54:31.652600   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5211 13:54:31.656093   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5212 13:54:31.658931   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 5213 13:54:31.662566  Total UI for P1: 0, mck2ui 16

 5214 13:54:31.665877  best dqsien dly found for B0: ( 1,  2, 26)

 5215 13:54:31.669138   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5216 13:54:31.672343  Total UI for P1: 0, mck2ui 16

 5217 13:54:31.675853  best dqsien dly found for B1: ( 1,  2, 30)

 5218 13:54:31.679134  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5219 13:54:31.685738  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5220 13:54:31.686357  

 5221 13:54:31.689588  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5222 13:54:31.692467  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5223 13:54:31.695938  [Gating] SW calibration Done

 5224 13:54:31.696519  ==

 5225 13:54:31.698988  Dram Type= 6, Freq= 0, CH_0, rank 0

 5226 13:54:31.702497  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5227 13:54:31.703132  ==

 5228 13:54:31.703522  RX Vref Scan: 0

 5229 13:54:31.705868  

 5230 13:54:31.706373  RX Vref 0 -> 0, step: 1

 5231 13:54:31.706752  

 5232 13:54:31.708714  RX Delay -80 -> 252, step: 8

 5233 13:54:31.712184  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5234 13:54:31.715408  iDelay=208, Bit 1, Center 111 (24 ~ 199) 176

 5235 13:54:31.722463  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5236 13:54:31.725484  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5237 13:54:31.728619  iDelay=208, Bit 4, Center 111 (24 ~ 199) 176

 5238 13:54:31.732103  iDelay=208, Bit 5, Center 95 (0 ~ 191) 192

 5239 13:54:31.735244  iDelay=208, Bit 6, Center 119 (32 ~ 207) 176

 5240 13:54:31.738712  iDelay=208, Bit 7, Center 119 (32 ~ 207) 176

 5241 13:54:31.745637  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5242 13:54:31.748490  iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176

 5243 13:54:31.752143  iDelay=208, Bit 10, Center 91 (0 ~ 183) 184

 5244 13:54:31.755819  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5245 13:54:31.758809  iDelay=208, Bit 12, Center 95 (8 ~ 183) 176

 5246 13:54:31.761916  iDelay=208, Bit 13, Center 91 (0 ~ 183) 184

 5247 13:54:31.768671  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5248 13:54:31.772126  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5249 13:54:31.772409  ==

 5250 13:54:31.775546  Dram Type= 6, Freq= 0, CH_0, rank 0

 5251 13:54:31.778581  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5252 13:54:31.778905  ==

 5253 13:54:31.782295  DQS Delay:

 5254 13:54:31.782702  DQS0 = 0, DQS1 = 0

 5255 13:54:31.782952  DQM Delay:

 5256 13:54:31.785266  DQM0 = 107, DQM1 = 91

 5257 13:54:31.785551  DQ Delay:

 5258 13:54:31.788938  DQ0 =107, DQ1 =111, DQ2 =99, DQ3 =99

 5259 13:54:31.792291  DQ4 =111, DQ5 =95, DQ6 =119, DQ7 =119

 5260 13:54:31.795683  DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87

 5261 13:54:31.798698  DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99

 5262 13:54:31.799272  

 5263 13:54:31.799644  

 5264 13:54:31.799987  ==

 5265 13:54:31.801980  Dram Type= 6, Freq= 0, CH_0, rank 0

 5266 13:54:31.808967  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5267 13:54:31.809547  ==

 5268 13:54:31.809921  

 5269 13:54:31.810323  

 5270 13:54:31.810654  	TX Vref Scan disable

 5271 13:54:31.812434   == TX Byte 0 ==

 5272 13:54:31.815590  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5273 13:54:31.822545  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5274 13:54:31.823134   == TX Byte 1 ==

 5275 13:54:31.825817  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5276 13:54:31.832404  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5277 13:54:31.832989  ==

 5278 13:54:31.835713  Dram Type= 6, Freq= 0, CH_0, rank 0

 5279 13:54:31.838920  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5280 13:54:31.839400  ==

 5281 13:54:31.839799  

 5282 13:54:31.840143  

 5283 13:54:31.842509  	TX Vref Scan disable

 5284 13:54:31.843066   == TX Byte 0 ==

 5285 13:54:31.848839  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5286 13:54:31.852150  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5287 13:54:31.852760   == TX Byte 1 ==

 5288 13:54:31.858759  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5289 13:54:31.862180  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5290 13:54:31.862735  

 5291 13:54:31.863107  [DATLAT]

 5292 13:54:31.865520  Freq=933, CH0 RK0

 5293 13:54:31.866066  

 5294 13:54:31.866344  DATLAT Default: 0xd

 5295 13:54:31.868621  0, 0xFFFF, sum = 0

 5296 13:54:31.868997  1, 0xFFFF, sum = 0

 5297 13:54:31.872180  2, 0xFFFF, sum = 0

 5298 13:54:31.872432  3, 0xFFFF, sum = 0

 5299 13:54:31.875305  4, 0xFFFF, sum = 0

 5300 13:54:31.875557  5, 0xFFFF, sum = 0

 5301 13:54:31.878496  6, 0xFFFF, sum = 0

 5302 13:54:31.878713  7, 0xFFFF, sum = 0

 5303 13:54:31.881921  8, 0xFFFF, sum = 0

 5304 13:54:31.885398  9, 0xFFFF, sum = 0

 5305 13:54:31.885875  10, 0x0, sum = 1

 5306 13:54:31.886303  11, 0x0, sum = 2

 5307 13:54:31.888842  12, 0x0, sum = 3

 5308 13:54:31.889322  13, 0x0, sum = 4

 5309 13:54:31.892350  best_step = 11

 5310 13:54:31.892930  

 5311 13:54:31.893305  ==

 5312 13:54:31.895387  Dram Type= 6, Freq= 0, CH_0, rank 0

 5313 13:54:31.899199  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5314 13:54:31.899790  ==

 5315 13:54:31.902266  RX Vref Scan: 1

 5316 13:54:31.902849  

 5317 13:54:31.903224  RX Vref 0 -> 0, step: 1

 5318 13:54:31.903575  

 5319 13:54:31.905565  RX Delay -53 -> 252, step: 4

 5320 13:54:31.906188  

 5321 13:54:31.909283  Set Vref, RX VrefLevel [Byte0]: 62

 5322 13:54:31.912430                           [Byte1]: 50

 5323 13:54:31.916503  

 5324 13:54:31.917019  Final RX Vref Byte 0 = 62 to rank0

 5325 13:54:31.919714  Final RX Vref Byte 1 = 50 to rank0

 5326 13:54:31.922922  Final RX Vref Byte 0 = 62 to rank1

 5327 13:54:31.926261  Final RX Vref Byte 1 = 50 to rank1==

 5328 13:54:31.929476  Dram Type= 6, Freq= 0, CH_0, rank 0

 5329 13:54:31.936577  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5330 13:54:31.937157  ==

 5331 13:54:31.937536  DQS Delay:

 5332 13:54:31.937887  DQS0 = 0, DQS1 = 0

 5333 13:54:31.939991  DQM Delay:

 5334 13:54:31.940571  DQM0 = 108, DQM1 = 91

 5335 13:54:31.942702  DQ Delay:

 5336 13:54:31.946208  DQ0 =106, DQ1 =110, DQ2 =106, DQ3 =106

 5337 13:54:31.949287  DQ4 =110, DQ5 =100, DQ6 =116, DQ7 =114

 5338 13:54:31.952666  DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90

 5339 13:54:31.955951  DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =98

 5340 13:54:31.956429  

 5341 13:54:31.956799  

 5342 13:54:31.962773  [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps

 5343 13:54:31.966068  CH0 RK0: MR19=505, MR18=221E

 5344 13:54:31.972512  CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42

 5345 13:54:31.973002  

 5346 13:54:31.975607  ----->DramcWriteLeveling(PI) begin...

 5347 13:54:31.976078  ==

 5348 13:54:31.979135  Dram Type= 6, Freq= 0, CH_0, rank 1

 5349 13:54:31.982698  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5350 13:54:31.983177  ==

 5351 13:54:31.986000  Write leveling (Byte 0): 32 => 32

 5352 13:54:31.989205  Write leveling (Byte 1): 31 => 31

 5353 13:54:31.992620  DramcWriteLeveling(PI) end<-----

 5354 13:54:31.993093  

 5355 13:54:31.993461  ==

 5356 13:54:31.995773  Dram Type= 6, Freq= 0, CH_0, rank 1

 5357 13:54:32.002370  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5358 13:54:32.002619  ==

 5359 13:54:32.002813  [Gating] SW mode calibration

 5360 13:54:32.012460  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5361 13:54:32.015604  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5362 13:54:32.019151   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5363 13:54:32.025812   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5364 13:54:32.028697   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5365 13:54:32.032389   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5366 13:54:32.039030   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5367 13:54:32.042386   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5368 13:54:32.046004   0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)

 5369 13:54:32.052200   0 14 28 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)

 5370 13:54:32.055576   0 15  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 5371 13:54:32.059020   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5372 13:54:32.065815   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5373 13:54:32.068886   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5374 13:54:32.072360   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5375 13:54:32.079068   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5376 13:54:32.082687   0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)

 5377 13:54:32.085382   0 15 28 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)

 5378 13:54:32.092480   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5379 13:54:32.095855   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5380 13:54:32.098897   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5381 13:54:32.105488   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5382 13:54:32.109059   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5383 13:54:32.111819   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5384 13:54:32.118791   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5385 13:54:32.121777   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5386 13:54:32.125210   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5387 13:54:32.132019   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5388 13:54:32.135268   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5389 13:54:32.138379   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5390 13:54:32.144874   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5391 13:54:32.148556   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5392 13:54:32.151927   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5393 13:54:32.154901   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5394 13:54:32.161492   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5395 13:54:32.165027   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5396 13:54:32.168695   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5397 13:54:32.175298   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5398 13:54:32.178575   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5399 13:54:32.182035   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5400 13:54:32.188521   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 5401 13:54:32.191828   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5402 13:54:32.195447  Total UI for P1: 0, mck2ui 16

 5403 13:54:32.198694  best dqsien dly found for B0: ( 1,  2, 26)

 5404 13:54:32.201997   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 5405 13:54:32.205060  Total UI for P1: 0, mck2ui 16

 5406 13:54:32.208584  best dqsien dly found for B1: ( 1,  2, 26)

 5407 13:54:32.211504  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5408 13:54:32.215162  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5409 13:54:32.215760  

 5410 13:54:32.221507  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5411 13:54:32.225262  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5412 13:54:32.225826  [Gating] SW calibration Done

 5413 13:54:32.228506  ==

 5414 13:54:32.231548  Dram Type= 6, Freq= 0, CH_0, rank 1

 5415 13:54:32.235137  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5416 13:54:32.235878  ==

 5417 13:54:32.236262  RX Vref Scan: 0

 5418 13:54:32.236604  

 5419 13:54:32.238330  RX Vref 0 -> 0, step: 1

 5420 13:54:32.238791  

 5421 13:54:32.241988  RX Delay -80 -> 252, step: 8

 5422 13:54:32.244747  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5423 13:54:32.248033  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5424 13:54:32.251375  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5425 13:54:32.258035  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5426 13:54:32.261262  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5427 13:54:32.264774  iDelay=208, Bit 5, Center 99 (8 ~ 191) 184

 5428 13:54:32.268034  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5429 13:54:32.271084  iDelay=208, Bit 7, Center 111 (16 ~ 207) 192

 5430 13:54:32.274482  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5431 13:54:32.281153  iDelay=208, Bit 9, Center 83 (0 ~ 167) 168

 5432 13:54:32.284497  iDelay=208, Bit 10, Center 91 (0 ~ 183) 184

 5433 13:54:32.287810  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5434 13:54:32.291194  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5435 13:54:32.294320  iDelay=208, Bit 13, Center 95 (8 ~ 183) 176

 5436 13:54:32.298174  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5437 13:54:32.304865  iDelay=208, Bit 15, Center 91 (0 ~ 183) 184

 5438 13:54:32.305426  ==

 5439 13:54:32.308086  Dram Type= 6, Freq= 0, CH_0, rank 1

 5440 13:54:32.311583  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5441 13:54:32.312143  ==

 5442 13:54:32.312506  DQS Delay:

 5443 13:54:32.314614  DQS0 = 0, DQS1 = 0

 5444 13:54:32.315071  DQM Delay:

 5445 13:54:32.318139  DQM0 = 105, DQM1 = 91

 5446 13:54:32.318597  DQ Delay:

 5447 13:54:32.321580  DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99

 5448 13:54:32.324532  DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111

 5449 13:54:32.327916  DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87

 5450 13:54:32.331285  DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91

 5451 13:54:32.331754  

 5452 13:54:32.332120  

 5453 13:54:32.332458  ==

 5454 13:54:32.334859  Dram Type= 6, Freq= 0, CH_0, rank 1

 5455 13:54:32.338289  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5456 13:54:32.341500  ==

 5457 13:54:32.342101  

 5458 13:54:32.342476  

 5459 13:54:32.342818  	TX Vref Scan disable

 5460 13:54:32.344917   == TX Byte 0 ==

 5461 13:54:32.348073  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5462 13:54:32.351523  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5463 13:54:32.354821   == TX Byte 1 ==

 5464 13:54:32.358211  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5465 13:54:32.361384  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5466 13:54:32.364753  ==

 5467 13:54:32.365318  Dram Type= 6, Freq= 0, CH_0, rank 1

 5468 13:54:32.371160  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5469 13:54:32.371641  ==

 5470 13:54:32.372013  

 5471 13:54:32.372356  

 5472 13:54:32.374375  	TX Vref Scan disable

 5473 13:54:32.374850   == TX Byte 0 ==

 5474 13:54:32.380912  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5475 13:54:32.384430  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5476 13:54:32.384952   == TX Byte 1 ==

 5477 13:54:32.390703  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5478 13:54:32.393967  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5479 13:54:32.394295  

 5480 13:54:32.394545  [DATLAT]

 5481 13:54:32.397595  Freq=933, CH0 RK1

 5482 13:54:32.397856  

 5483 13:54:32.398086  DATLAT Default: 0xb

 5484 13:54:32.401007  0, 0xFFFF, sum = 0

 5485 13:54:32.401204  1, 0xFFFF, sum = 0

 5486 13:54:32.404002  2, 0xFFFF, sum = 0

 5487 13:54:32.404201  3, 0xFFFF, sum = 0

 5488 13:54:32.407275  4, 0xFFFF, sum = 0

 5489 13:54:32.407473  5, 0xFFFF, sum = 0

 5490 13:54:32.410955  6, 0xFFFF, sum = 0

 5491 13:54:32.411256  7, 0xFFFF, sum = 0

 5492 13:54:32.414206  8, 0xFFFF, sum = 0

 5493 13:54:32.414405  9, 0xFFFF, sum = 0

 5494 13:54:32.417441  10, 0x0, sum = 1

 5495 13:54:32.417639  11, 0x0, sum = 2

 5496 13:54:32.420961  12, 0x0, sum = 3

 5497 13:54:32.421254  13, 0x0, sum = 4

 5498 13:54:32.423832  best_step = 11

 5499 13:54:32.424031  

 5500 13:54:32.424198  ==

 5501 13:54:32.427373  Dram Type= 6, Freq= 0, CH_0, rank 1

 5502 13:54:32.430725  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5503 13:54:32.431014  ==

 5504 13:54:32.433958  RX Vref Scan: 0

 5505 13:54:32.434240  

 5506 13:54:32.434417  RX Vref 0 -> 0, step: 1

 5507 13:54:32.434569  

 5508 13:54:32.437473  RX Delay -45 -> 252, step: 4

 5509 13:54:32.444382  iDelay=203, Bit 0, Center 102 (15 ~ 190) 176

 5510 13:54:32.447724  iDelay=203, Bit 1, Center 106 (19 ~ 194) 176

 5511 13:54:32.450931  iDelay=203, Bit 2, Center 102 (15 ~ 190) 176

 5512 13:54:32.454838  iDelay=203, Bit 3, Center 100 (15 ~ 186) 172

 5513 13:54:32.458030  iDelay=203, Bit 4, Center 106 (19 ~ 194) 176

 5514 13:54:32.464667  iDelay=203, Bit 5, Center 96 (11 ~ 182) 172

 5515 13:54:32.467574  iDelay=203, Bit 6, Center 116 (31 ~ 202) 172

 5516 13:54:32.471399  iDelay=203, Bit 7, Center 112 (27 ~ 198) 172

 5517 13:54:32.474477  iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172

 5518 13:54:32.477936  iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164

 5519 13:54:32.484347  iDelay=203, Bit 10, Center 94 (11 ~ 178) 168

 5520 13:54:32.487885  iDelay=203, Bit 11, Center 92 (11 ~ 174) 164

 5521 13:54:32.491057  iDelay=203, Bit 12, Center 96 (11 ~ 182) 172

 5522 13:54:32.494502  iDelay=203, Bit 13, Center 94 (11 ~ 178) 168

 5523 13:54:32.497992  iDelay=203, Bit 14, Center 100 (15 ~ 186) 172

 5524 13:54:32.504344  iDelay=203, Bit 15, Center 98 (15 ~ 182) 168

 5525 13:54:32.504814  ==

 5526 13:54:32.507538  Dram Type= 6, Freq= 0, CH_0, rank 1

 5527 13:54:32.511176  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5528 13:54:32.511651  ==

 5529 13:54:32.512022  DQS Delay:

 5530 13:54:32.514086  DQS0 = 0, DQS1 = 0

 5531 13:54:32.514557  DQM Delay:

 5532 13:54:32.518018  DQM0 = 105, DQM1 = 92

 5533 13:54:32.518491  DQ Delay:

 5534 13:54:32.521147  DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =100

 5535 13:54:32.524042  DQ4 =106, DQ5 =96, DQ6 =116, DQ7 =112

 5536 13:54:32.527430  DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92

 5537 13:54:32.530453  DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98

 5538 13:54:32.530785  

 5539 13:54:32.531023  

 5540 13:54:32.540871  [DQSOSCAuto] RK1, (LSB)MR18= 0x2707, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps

 5541 13:54:32.541182  CH0 RK1: MR19=505, MR18=2707

 5542 13:54:32.547248  CH0_RK1: MR19=0x505, MR18=0x2707, DQSOSC=409, MR23=63, INC=64, DEC=43

 5543 13:54:32.550496  [RxdqsGatingPostProcess] freq 933

 5544 13:54:32.557290  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5545 13:54:32.560324  best DQS0 dly(2T, 0.5T) = (0, 10)

 5546 13:54:32.563879  best DQS1 dly(2T, 0.5T) = (0, 10)

 5547 13:54:32.567091  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5548 13:54:32.570408  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5549 13:54:32.574096  best DQS0 dly(2T, 0.5T) = (0, 10)

 5550 13:54:32.577765  best DQS1 dly(2T, 0.5T) = (0, 10)

 5551 13:54:32.578380  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5552 13:54:32.580292  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5553 13:54:32.583872  Pre-setting of DQS Precalculation

 5554 13:54:32.590551  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5555 13:54:32.591132  ==

 5556 13:54:32.594219  Dram Type= 6, Freq= 0, CH_1, rank 0

 5557 13:54:32.597236  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5558 13:54:32.597717  ==

 5559 13:54:32.604356  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5560 13:54:32.610852  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31

 5561 13:54:32.613888  [CA 0] Center 37 (7~68) winsize 62

 5562 13:54:32.616917  [CA 1] Center 37 (7~68) winsize 62

 5563 13:54:32.620458  [CA 2] Center 36 (6~66) winsize 61

 5564 13:54:32.623776  [CA 3] Center 34 (4~65) winsize 62

 5565 13:54:32.627171  [CA 4] Center 35 (5~65) winsize 61

 5566 13:54:32.630086  [CA 5] Center 34 (4~65) winsize 62

 5567 13:54:32.630764  

 5568 13:54:32.633491  [CmdBusTrainingLP45] Vref(ca) range 1: 31

 5569 13:54:32.634160  

 5570 13:54:32.636914  [CATrainingPosCal] consider 1 rank data

 5571 13:54:32.640265  u2DelayCellTimex100 = 270/100 ps

 5572 13:54:32.643820  CA0 delay=37 (7~68),Diff = 3 PI (18 cell)

 5573 13:54:32.647279  CA1 delay=37 (7~68),Diff = 3 PI (18 cell)

 5574 13:54:32.650468  CA2 delay=36 (6~66),Diff = 2 PI (12 cell)

 5575 13:54:32.653670  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 5576 13:54:32.656936  CA4 delay=35 (5~65),Diff = 1 PI (6 cell)

 5577 13:54:32.660201  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 5578 13:54:32.660670  

 5579 13:54:32.666700  CA PerBit enable=1, Macro0, CA PI delay=34

 5580 13:54:32.666948  

 5581 13:54:32.667138  [CBTSetCACLKResult] CA Dly = 34

 5582 13:54:32.669986  CS Dly: 6 (0~37)

 5583 13:54:32.670231  ==

 5584 13:54:32.673211  Dram Type= 6, Freq= 0, CH_1, rank 1

 5585 13:54:32.676409  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5586 13:54:32.676604  ==

 5587 13:54:32.683092  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5588 13:54:32.689825  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5589 13:54:32.693356  [CA 0] Center 38 (7~69) winsize 63

 5590 13:54:32.696994  [CA 1] Center 38 (7~69) winsize 63

 5591 13:54:32.699919  [CA 2] Center 36 (6~66) winsize 61

 5592 13:54:32.703472  [CA 3] Center 35 (5~65) winsize 61

 5593 13:54:32.706830  [CA 4] Center 35 (5~66) winsize 62

 5594 13:54:32.710030  [CA 5] Center 35 (5~65) winsize 61

 5595 13:54:32.710414  

 5596 13:54:32.713193  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5597 13:54:32.713751  

 5598 13:54:32.716582  [CATrainingPosCal] consider 2 rank data

 5599 13:54:32.720104  u2DelayCellTimex100 = 270/100 ps

 5600 13:54:32.723453  CA0 delay=37 (7~68),Diff = 2 PI (12 cell)

 5601 13:54:32.726487  CA1 delay=37 (7~68),Diff = 2 PI (12 cell)

 5602 13:54:32.730125  CA2 delay=36 (6~66),Diff = 1 PI (6 cell)

 5603 13:54:32.733244  CA3 delay=35 (5~65),Diff = 0 PI (0 cell)

 5604 13:54:32.736444  CA4 delay=35 (5~65),Diff = 0 PI (0 cell)

 5605 13:54:32.740239  CA5 delay=35 (5~65),Diff = 0 PI (0 cell)

 5606 13:54:32.740811  

 5607 13:54:32.746589  CA PerBit enable=1, Macro0, CA PI delay=35

 5608 13:54:32.747159  

 5609 13:54:32.750354  [CBTSetCACLKResult] CA Dly = 35

 5610 13:54:32.750936  CS Dly: 7 (0~39)

 5611 13:54:32.751315  

 5612 13:54:32.753369  ----->DramcWriteLeveling(PI) begin...

 5613 13:54:32.753968  ==

 5614 13:54:32.756699  Dram Type= 6, Freq= 0, CH_1, rank 0

 5615 13:54:32.760150  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5616 13:54:32.763108  ==

 5617 13:54:32.763642  Write leveling (Byte 0): 27 => 27

 5618 13:54:32.766273  Write leveling (Byte 1): 28 => 28

 5619 13:54:32.769651  DramcWriteLeveling(PI) end<-----

 5620 13:54:32.770308  

 5621 13:54:32.770835  ==

 5622 13:54:32.773176  Dram Type= 6, Freq= 0, CH_1, rank 0

 5623 13:54:32.779702  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5624 13:54:32.780175  ==

 5625 13:54:32.780543  [Gating] SW mode calibration

 5626 13:54:32.789507  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5627 13:54:32.792950  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5628 13:54:32.796176   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5629 13:54:32.802563   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5630 13:54:32.806096   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5631 13:54:32.809236   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5632 13:54:32.815948   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5633 13:54:32.819457   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 5634 13:54:32.823123   0 14 24 | B1->B0 | 3232 3030 | 1 1 | (1 1) (1 0)

 5635 13:54:32.829359   0 14 28 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)

 5636 13:54:32.832703   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5637 13:54:32.835819   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5638 13:54:32.842563   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5639 13:54:32.846066   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5640 13:54:32.849468   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5641 13:54:32.856208   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5642 13:54:32.859471   0 15 24 | B1->B0 | 2929 2c2b | 0 1 | (0 0) (0 0)

 5643 13:54:32.863008   0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)

 5644 13:54:32.869508   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5645 13:54:32.873226   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5646 13:54:32.875991   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5647 13:54:32.882712   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5648 13:54:32.886022   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5649 13:54:32.889635   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5650 13:54:32.895947   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5651 13:54:32.899275   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5652 13:54:32.902464   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5653 13:54:32.909084   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5654 13:54:32.912431   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5655 13:54:32.916092   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5656 13:54:32.922508   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5657 13:54:32.926353   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5658 13:54:32.928847   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5659 13:54:32.932248   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5660 13:54:32.938998   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5661 13:54:32.942363   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5662 13:54:32.946007   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5663 13:54:32.952729   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5664 13:54:32.955601   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5665 13:54:32.959068   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5666 13:54:32.965756   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5667 13:54:32.968923   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5668 13:54:32.972054  Total UI for P1: 0, mck2ui 16

 5669 13:54:32.975640  best dqsien dly found for B0: ( 1,  2, 22)

 5670 13:54:32.979136   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5671 13:54:32.982459  Total UI for P1: 0, mck2ui 16

 5672 13:54:32.985318  best dqsien dly found for B1: ( 1,  2, 28)

 5673 13:54:32.988784  best DQS0 dly(MCK, UI, PI) = (1, 2, 22)

 5674 13:54:32.992338  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5675 13:54:32.992807  

 5676 13:54:32.999091  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)

 5677 13:54:33.002671  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5678 13:54:33.005589  [Gating] SW calibration Done

 5679 13:54:33.006191  ==

 5680 13:54:33.009288  Dram Type= 6, Freq= 0, CH_1, rank 0

 5681 13:54:33.012458  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5682 13:54:33.013031  ==

 5683 13:54:33.013406  RX Vref Scan: 0

 5684 13:54:33.013750  

 5685 13:54:33.015476  RX Vref 0 -> 0, step: 1

 5686 13:54:33.015946  

 5687 13:54:33.018993  RX Delay -80 -> 252, step: 8

 5688 13:54:33.022612  iDelay=208, Bit 0, Center 103 (16 ~ 191) 176

 5689 13:54:33.026033  iDelay=208, Bit 1, Center 95 (8 ~ 183) 176

 5690 13:54:33.028974  iDelay=208, Bit 2, Center 95 (8 ~ 183) 176

 5691 13:54:33.035671  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5692 13:54:33.038982  iDelay=208, Bit 4, Center 99 (8 ~ 191) 184

 5693 13:54:33.042407  iDelay=208, Bit 5, Center 111 (24 ~ 199) 176

 5694 13:54:33.045506  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5695 13:54:33.048839  iDelay=208, Bit 7, Center 99 (8 ~ 191) 184

 5696 13:54:33.051970  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5697 13:54:33.058654  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5698 13:54:33.061947  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5699 13:54:33.065242  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5700 13:54:33.068715  iDelay=208, Bit 12, Center 103 (8 ~ 199) 192

 5701 13:54:33.072036  iDelay=208, Bit 13, Center 103 (8 ~ 199) 192

 5702 13:54:33.075210  iDelay=208, Bit 14, Center 103 (8 ~ 199) 192

 5703 13:54:33.082086  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5704 13:54:33.082372  ==

 5705 13:54:33.085188  Dram Type= 6, Freq= 0, CH_1, rank 0

 5706 13:54:33.088450  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5707 13:54:33.088733  ==

 5708 13:54:33.088898  DQS Delay:

 5709 13:54:33.091578  DQS0 = 0, DQS1 = 0

 5710 13:54:33.091773  DQM Delay:

 5711 13:54:33.095317  DQM0 = 101, DQM1 = 95

 5712 13:54:33.095602  DQ Delay:

 5713 13:54:33.098616  DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99

 5714 13:54:33.101999  DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99

 5715 13:54:33.105325  DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91

 5716 13:54:33.109004  DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99

 5717 13:54:33.109623  

 5718 13:54:33.109990  

 5719 13:54:33.110277  ==

 5720 13:54:33.112073  Dram Type= 6, Freq= 0, CH_1, rank 0

 5721 13:54:33.118414  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5722 13:54:33.118947  ==

 5723 13:54:33.119330  

 5724 13:54:33.119666  

 5725 13:54:33.119990  	TX Vref Scan disable

 5726 13:54:33.122027   == TX Byte 0 ==

 5727 13:54:33.125662  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5728 13:54:33.128949  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5729 13:54:33.132458   == TX Byte 1 ==

 5730 13:54:33.135383  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5731 13:54:33.141834  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5732 13:54:33.142430  ==

 5733 13:54:33.145893  Dram Type= 6, Freq= 0, CH_1, rank 0

 5734 13:54:33.148794  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5735 13:54:33.149373  ==

 5736 13:54:33.149751  

 5737 13:54:33.150154  

 5738 13:54:33.151850  	TX Vref Scan disable

 5739 13:54:33.152315   == TX Byte 0 ==

 5740 13:54:33.158680  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5741 13:54:33.161876  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5742 13:54:33.162410   == TX Byte 1 ==

 5743 13:54:33.168192  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5744 13:54:33.171914  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5745 13:54:33.172621  

 5746 13:54:33.173226  [DATLAT]

 5747 13:54:33.175183  Freq=933, CH1 RK0

 5748 13:54:33.175821  

 5749 13:54:33.176315  DATLAT Default: 0xd

 5750 13:54:33.178690  0, 0xFFFF, sum = 0

 5751 13:54:33.179223  1, 0xFFFF, sum = 0

 5752 13:54:33.181701  2, 0xFFFF, sum = 0

 5753 13:54:33.182376  3, 0xFFFF, sum = 0

 5754 13:54:33.185023  4, 0xFFFF, sum = 0

 5755 13:54:33.185674  5, 0xFFFF, sum = 0

 5756 13:54:33.188399  6, 0xFFFF, sum = 0

 5757 13:54:33.189108  7, 0xFFFF, sum = 0

 5758 13:54:33.191553  8, 0xFFFF, sum = 0

 5759 13:54:33.195196  9, 0xFFFF, sum = 0

 5760 13:54:33.195440  10, 0x0, sum = 1

 5761 13:54:33.195726  11, 0x0, sum = 2

 5762 13:54:33.198259  12, 0x0, sum = 3

 5763 13:54:33.198502  13, 0x0, sum = 4

 5764 13:54:33.202086  best_step = 11

 5765 13:54:33.202412  

 5766 13:54:33.202616  ==

 5767 13:54:33.204944  Dram Type= 6, Freq= 0, CH_1, rank 0

 5768 13:54:33.208811  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5769 13:54:33.209176  ==

 5770 13:54:33.211776  RX Vref Scan: 1

 5771 13:54:33.212128  

 5772 13:54:33.212346  RX Vref 0 -> 0, step: 1

 5773 13:54:33.212534  

 5774 13:54:33.214950  RX Delay -53 -> 252, step: 4

 5775 13:54:33.215296  

 5776 13:54:33.218180  Set Vref, RX VrefLevel [Byte0]: 52

 5777 13:54:33.221417                           [Byte1]: 50

 5778 13:54:33.225742  

 5779 13:54:33.226104  Final RX Vref Byte 0 = 52 to rank0

 5780 13:54:33.229019  Final RX Vref Byte 1 = 50 to rank0

 5781 13:54:33.232212  Final RX Vref Byte 0 = 52 to rank1

 5782 13:54:33.235540  Final RX Vref Byte 1 = 50 to rank1==

 5783 13:54:33.239438  Dram Type= 6, Freq= 0, CH_1, rank 0

 5784 13:54:33.245792  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5785 13:54:33.246400  ==

 5786 13:54:33.246780  DQS Delay:

 5787 13:54:33.247126  DQS0 = 0, DQS1 = 0

 5788 13:54:33.249476  DQM Delay:

 5789 13:54:33.250092  DQM0 = 104, DQM1 = 97

 5790 13:54:33.252600  DQ Delay:

 5791 13:54:33.255938  DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102

 5792 13:54:33.259049  DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102

 5793 13:54:33.262627  DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =90

 5794 13:54:33.265687  DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =102

 5795 13:54:33.266290  

 5796 13:54:33.266926  

 5797 13:54:33.272469  [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps

 5798 13:54:33.275868  CH1 RK0: MR19=505, MR18=1D35

 5799 13:54:33.282610  CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44

 5800 13:54:33.283180  

 5801 13:54:33.285869  ----->DramcWriteLeveling(PI) begin...

 5802 13:54:33.286389  ==

 5803 13:54:33.289502  Dram Type= 6, Freq= 0, CH_1, rank 1

 5804 13:54:33.292053  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5805 13:54:33.292560  ==

 5806 13:54:33.295626  Write leveling (Byte 0): 26 => 26

 5807 13:54:33.298869  Write leveling (Byte 1): 27 => 27

 5808 13:54:33.302222  DramcWriteLeveling(PI) end<-----

 5809 13:54:33.302806  

 5810 13:54:33.303190  ==

 5811 13:54:33.305536  Dram Type= 6, Freq= 0, CH_1, rank 1

 5812 13:54:33.312547  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5813 13:54:33.313025  ==

 5814 13:54:33.313404  [Gating] SW mode calibration

 5815 13:54:33.322153  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5816 13:54:33.325307  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5817 13:54:33.328562   0 14  0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 5818 13:54:33.335127   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5819 13:54:33.338462   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5820 13:54:33.342022   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5821 13:54:33.348770   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5822 13:54:33.351803   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5823 13:54:33.355093   0 14 24 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)

 5824 13:54:33.361509   0 14 28 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 1)

 5825 13:54:33.365262   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5826 13:54:33.368428   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5827 13:54:33.374914   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5828 13:54:33.378267   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5829 13:54:33.381834   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5830 13:54:33.388478   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5831 13:54:33.391656   0 15 24 | B1->B0 | 2d2d 2525 | 0 1 | (0 0) (0 0)

 5832 13:54:33.395080   0 15 28 | B1->B0 | 3d3d 3636 | 0 0 | (1 1) (0 0)

 5833 13:54:33.401708   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5834 13:54:33.405057   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5835 13:54:33.408124   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5836 13:54:33.415074   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5837 13:54:33.417932   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5838 13:54:33.421227   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5839 13:54:33.427981   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5840 13:54:33.431253   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5841 13:54:33.434749   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5842 13:54:33.441419   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5843 13:54:33.444874   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5844 13:54:33.447794   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5845 13:54:33.454432   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5846 13:54:33.457526   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5847 13:54:33.460911   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5848 13:54:33.467582   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5849 13:54:33.471315   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5850 13:54:33.474315   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5851 13:54:33.480910   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5852 13:54:33.484232   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5853 13:54:33.487633   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5854 13:54:33.494678   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5855 13:54:33.497678   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5856 13:54:33.500980   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5857 13:54:33.504840   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5858 13:54:33.507799  Total UI for P1: 0, mck2ui 16

 5859 13:54:33.511074  best dqsien dly found for B0: ( 1,  2, 26)

 5860 13:54:33.514619  Total UI for P1: 0, mck2ui 16

 5861 13:54:33.517851  best dqsien dly found for B1: ( 1,  2, 28)

 5862 13:54:33.521576  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5863 13:54:33.524249  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5864 13:54:33.527561  

 5865 13:54:33.530828  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5866 13:54:33.534323  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5867 13:54:33.537559  [Gating] SW calibration Done

 5868 13:54:33.538172  ==

 5869 13:54:33.541405  Dram Type= 6, Freq= 0, CH_1, rank 1

 5870 13:54:33.544494  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5871 13:54:33.545077  ==

 5872 13:54:33.545457  RX Vref Scan: 0

 5873 13:54:33.547906  

 5874 13:54:33.548489  RX Vref 0 -> 0, step: 1

 5875 13:54:33.548870  

 5876 13:54:33.550552  RX Delay -80 -> 252, step: 8

 5877 13:54:33.554587  iDelay=200, Bit 0, Center 107 (24 ~ 191) 168

 5878 13:54:33.557608  iDelay=200, Bit 1, Center 99 (16 ~ 183) 168

 5879 13:54:33.563949  iDelay=200, Bit 2, Center 87 (0 ~ 175) 176

 5880 13:54:33.567281  iDelay=200, Bit 3, Center 103 (16 ~ 191) 176

 5881 13:54:33.570642  iDelay=200, Bit 4, Center 103 (16 ~ 191) 176

 5882 13:54:33.573798  iDelay=200, Bit 5, Center 111 (24 ~ 199) 176

 5883 13:54:33.577017  iDelay=200, Bit 6, Center 111 (24 ~ 199) 176

 5884 13:54:33.583899  iDelay=200, Bit 7, Center 103 (16 ~ 191) 176

 5885 13:54:33.587173  iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184

 5886 13:54:33.590465  iDelay=200, Bit 9, Center 87 (0 ~ 175) 176

 5887 13:54:33.594036  iDelay=200, Bit 10, Center 99 (8 ~ 191) 184

 5888 13:54:33.597085  iDelay=200, Bit 11, Center 91 (0 ~ 183) 184

 5889 13:54:33.600597  iDelay=200, Bit 12, Center 107 (16 ~ 199) 184

 5890 13:54:33.606990  iDelay=200, Bit 13, Center 99 (8 ~ 191) 184

 5891 13:54:33.610778  iDelay=200, Bit 14, Center 99 (8 ~ 191) 184

 5892 13:54:33.613911  iDelay=200, Bit 15, Center 103 (8 ~ 199) 192

 5893 13:54:33.614208  ==

 5894 13:54:33.617333  Dram Type= 6, Freq= 0, CH_1, rank 1

 5895 13:54:33.620489  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5896 13:54:33.620773  ==

 5897 13:54:33.623565  DQS Delay:

 5898 13:54:33.623761  DQS0 = 0, DQS1 = 0

 5899 13:54:33.626931  DQM Delay:

 5900 13:54:33.627160  DQM0 = 103, DQM1 = 96

 5901 13:54:33.627341  DQ Delay:

 5902 13:54:33.630112  DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103

 5903 13:54:33.633409  DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103

 5904 13:54:33.637212  DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91

 5905 13:54:33.643843  DQ12 =107, DQ13 =99, DQ14 =99, DQ15 =103

 5906 13:54:33.644415  

 5907 13:54:33.644785  

 5908 13:54:33.645126  ==

 5909 13:54:33.647199  Dram Type= 6, Freq= 0, CH_1, rank 1

 5910 13:54:33.650691  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5911 13:54:33.651261  ==

 5912 13:54:33.651633  

 5913 13:54:33.651971  

 5914 13:54:33.653822  	TX Vref Scan disable

 5915 13:54:33.654435   == TX Byte 0 ==

 5916 13:54:33.660598  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5917 13:54:33.663324  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5918 13:54:33.663797   == TX Byte 1 ==

 5919 13:54:33.670083  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5920 13:54:33.673749  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5921 13:54:33.674382  ==

 5922 13:54:33.677084  Dram Type= 6, Freq= 0, CH_1, rank 1

 5923 13:54:33.680557  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5924 13:54:33.681134  ==

 5925 13:54:33.681505  

 5926 13:54:33.681847  

 5927 13:54:33.683630  	TX Vref Scan disable

 5928 13:54:33.686680   == TX Byte 0 ==

 5929 13:54:33.690096  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5930 13:54:33.693219  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5931 13:54:33.696690   == TX Byte 1 ==

 5932 13:54:33.699976  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5933 13:54:33.703410  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5934 13:54:33.704042  

 5935 13:54:33.706762  [DATLAT]

 5936 13:54:33.707524  Freq=933, CH1 RK1

 5937 13:54:33.707915  

 5938 13:54:33.709790  DATLAT Default: 0xb

 5939 13:54:33.710303  0, 0xFFFF, sum = 0

 5940 13:54:33.713282  1, 0xFFFF, sum = 0

 5941 13:54:33.713757  2, 0xFFFF, sum = 0

 5942 13:54:33.716684  3, 0xFFFF, sum = 0

 5943 13:54:33.717160  4, 0xFFFF, sum = 0

 5944 13:54:33.719922  5, 0xFFFF, sum = 0

 5945 13:54:33.720530  6, 0xFFFF, sum = 0

 5946 13:54:33.723062  7, 0xFFFF, sum = 0

 5947 13:54:33.723486  8, 0xFFFF, sum = 0

 5948 13:54:33.726419  9, 0xFFFF, sum = 0

 5949 13:54:33.726793  10, 0x0, sum = 1

 5950 13:54:33.729542  11, 0x0, sum = 2

 5951 13:54:33.729790  12, 0x0, sum = 3

 5952 13:54:33.732983  13, 0x0, sum = 4

 5953 13:54:33.733229  best_step = 11

 5954 13:54:33.733423  

 5955 13:54:33.733600  ==

 5956 13:54:33.736321  Dram Type= 6, Freq= 0, CH_1, rank 1

 5957 13:54:33.743134  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5958 13:54:33.743468  ==

 5959 13:54:33.743672  RX Vref Scan: 0

 5960 13:54:33.743855  

 5961 13:54:33.746586  RX Vref 0 -> 0, step: 1

 5962 13:54:33.746922  

 5963 13:54:33.750203  RX Delay -53 -> 252, step: 4

 5964 13:54:33.753212  iDelay=199, Bit 0, Center 110 (35 ~ 186) 152

 5965 13:54:33.760231  iDelay=199, Bit 1, Center 98 (19 ~ 178) 160

 5966 13:54:33.763252  iDelay=199, Bit 2, Center 94 (15 ~ 174) 160

 5967 13:54:33.766362  iDelay=199, Bit 3, Center 102 (19 ~ 186) 168

 5968 13:54:33.769451  iDelay=199, Bit 4, Center 106 (23 ~ 190) 168

 5969 13:54:33.773443  iDelay=199, Bit 5, Center 116 (35 ~ 198) 164

 5970 13:54:33.776613  iDelay=199, Bit 6, Center 112 (31 ~ 194) 164

 5971 13:54:33.783477  iDelay=199, Bit 7, Center 102 (23 ~ 182) 160

 5972 13:54:33.786581  iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172

 5973 13:54:33.790068  iDelay=199, Bit 9, Center 88 (7 ~ 170) 164

 5974 13:54:33.792868  iDelay=199, Bit 10, Center 98 (15 ~ 182) 168

 5975 13:54:33.796672  iDelay=199, Bit 11, Center 92 (7 ~ 178) 172

 5976 13:54:33.803511  iDelay=199, Bit 12, Center 104 (19 ~ 190) 172

 5977 13:54:33.806163  iDelay=199, Bit 13, Center 102 (15 ~ 190) 176

 5978 13:54:33.809741  iDelay=199, Bit 14, Center 102 (15 ~ 190) 176

 5979 13:54:33.812918  iDelay=199, Bit 15, Center 106 (19 ~ 194) 176

 5980 13:54:33.813394  ==

 5981 13:54:33.816147  Dram Type= 6, Freq= 0, CH_1, rank 1

 5982 13:54:33.822778  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5983 13:54:33.823561  ==

 5984 13:54:33.824099  DQS Delay:

 5985 13:54:33.824801  DQS0 = 0, DQS1 = 0

 5986 13:54:33.826014  DQM Delay:

 5987 13:54:33.826532  DQM0 = 105, DQM1 = 97

 5988 13:54:33.829135  DQ Delay:

 5989 13:54:33.832932  DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102

 5990 13:54:33.836221  DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102

 5991 13:54:33.839164  DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92

 5992 13:54:33.842914  DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =106

 5993 13:54:33.843391  

 5994 13:54:33.843761  

 5995 13:54:33.849272  [DQSOSCAuto] RK1, (LSB)MR18= 0x2603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps

 5996 13:54:33.852525  CH1 RK1: MR19=505, MR18=2603

 5997 13:54:33.859159  CH1_RK1: MR19=0x505, MR18=0x2603, DQSOSC=409, MR23=63, INC=64, DEC=43

 5998 13:54:33.862486  [RxdqsGatingPostProcess] freq 933

 5999 13:54:33.868761  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 6000 13:54:33.869080  best DQS0 dly(2T, 0.5T) = (0, 10)

 6001 13:54:33.872359  best DQS1 dly(2T, 0.5T) = (0, 10)

 6002 13:54:33.875589  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 6003 13:54:33.879033  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 6004 13:54:33.882201  best DQS0 dly(2T, 0.5T) = (0, 10)

 6005 13:54:33.885603  best DQS1 dly(2T, 0.5T) = (0, 10)

 6006 13:54:33.888931  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 6007 13:54:33.892540  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 6008 13:54:33.895811  Pre-setting of DQS Precalculation

 6009 13:54:33.902369  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 6010 13:54:33.908891  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 6011 13:54:33.915702  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6012 13:54:33.916272  

 6013 13:54:33.916642  

 6014 13:54:33.918865  [Calibration Summary] 1866 Mbps

 6015 13:54:33.919342  CH 0, Rank 0

 6016 13:54:33.922034  SW Impedance     : PASS

 6017 13:54:33.925837  DUTY Scan        : NO K

 6018 13:54:33.926361  ZQ Calibration   : PASS

 6019 13:54:33.928746  Jitter Meter     : NO K

 6020 13:54:33.929217  CBT Training     : PASS

 6021 13:54:33.932506  Write leveling   : PASS

 6022 13:54:33.935630  RX DQS gating    : PASS

 6023 13:54:33.936101  RX DQ/DQS(RDDQC) : PASS

 6024 13:54:33.939155  TX DQ/DQS        : PASS

 6025 13:54:33.942421  RX DATLAT        : PASS

 6026 13:54:33.942892  RX DQ/DQS(Engine): PASS

 6027 13:54:33.945758  TX OE            : NO K

 6028 13:54:33.946359  All Pass.

 6029 13:54:33.946732  

 6030 13:54:33.949226  CH 0, Rank 1

 6031 13:54:33.949787  SW Impedance     : PASS

 6032 13:54:33.952502  DUTY Scan        : NO K

 6033 13:54:33.955527  ZQ Calibration   : PASS

 6034 13:54:33.956115  Jitter Meter     : NO K

 6035 13:54:33.958739  CBT Training     : PASS

 6036 13:54:33.962047  Write leveling   : PASS

 6037 13:54:33.962520  RX DQS gating    : PASS

 6038 13:54:33.965480  RX DQ/DQS(RDDQC) : PASS

 6039 13:54:33.968893  TX DQ/DQS        : PASS

 6040 13:54:33.969367  RX DATLAT        : PASS

 6041 13:54:33.972148  RX DQ/DQS(Engine): PASS

 6042 13:54:33.972621  TX OE            : NO K

 6043 13:54:33.975714  All Pass.

 6044 13:54:33.976185  

 6045 13:54:33.976555  CH 1, Rank 0

 6046 13:54:33.978723  SW Impedance     : PASS

 6047 13:54:33.979192  DUTY Scan        : NO K

 6048 13:54:33.982189  ZQ Calibration   : PASS

 6049 13:54:33.985220  Jitter Meter     : NO K

 6050 13:54:33.985648  CBT Training     : PASS

 6051 13:54:33.988663  Write leveling   : PASS

 6052 13:54:33.992025  RX DQS gating    : PASS

 6053 13:54:33.992256  RX DQ/DQS(RDDQC) : PASS

 6054 13:54:33.995311  TX DQ/DQS        : PASS

 6055 13:54:33.998769  RX DATLAT        : PASS

 6056 13:54:33.999102  RX DQ/DQS(Engine): PASS

 6057 13:54:34.001894  TX OE            : NO K

 6058 13:54:34.002154  All Pass.

 6059 13:54:34.002338  

 6060 13:54:34.005016  CH 1, Rank 1

 6061 13:54:34.005248  SW Impedance     : PASS

 6062 13:54:34.008420  DUTY Scan        : NO K

 6063 13:54:34.011595  ZQ Calibration   : PASS

 6064 13:54:34.011829  Jitter Meter     : NO K

 6065 13:54:34.014908  CBT Training     : PASS

 6066 13:54:34.018378  Write leveling   : PASS

 6067 13:54:34.018608  RX DQS gating    : PASS

 6068 13:54:34.021666  RX DQ/DQS(RDDQC) : PASS

 6069 13:54:34.025044  TX DQ/DQS        : PASS

 6070 13:54:34.025278  RX DATLAT        : PASS

 6071 13:54:34.028694  RX DQ/DQS(Engine): PASS

 6072 13:54:34.028929  TX OE            : NO K

 6073 13:54:34.031731  All Pass.

 6074 13:54:34.032000  

 6075 13:54:34.032248  DramC Write-DBI off

 6076 13:54:34.035051  	PER_BANK_REFRESH: Hybrid Mode

 6077 13:54:34.038635  TX_TRACKING: ON

 6078 13:54:34.045350  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6079 13:54:34.048819  [FAST_K] Save calibration result to emmc

 6080 13:54:34.055197  dramc_set_vcore_voltage set vcore to 650000

 6081 13:54:34.055779  Read voltage for 400, 6

 6082 13:54:34.056158  Vio18 = 0

 6083 13:54:34.058742  Vcore = 650000

 6084 13:54:34.059324  Vdram = 0

 6085 13:54:34.059697  Vddq = 0

 6086 13:54:34.062125  Vmddr = 0

 6087 13:54:34.065131  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6088 13:54:34.071658  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6089 13:54:34.072251  MEM_TYPE=3, freq_sel=20

 6090 13:54:34.074900  sv_algorithm_assistance_LP4_800 

 6091 13:54:34.081759  ============ PULL DRAM RESETB DOWN ============

 6092 13:54:34.085368  ========== PULL DRAM RESETB DOWN end =========

 6093 13:54:34.088540  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6094 13:54:34.091558  =================================== 

 6095 13:54:34.094948  LPDDR4 DRAM CONFIGURATION

 6096 13:54:34.098067  =================================== 

 6097 13:54:34.101671  EX_ROW_EN[0]    = 0x0

 6098 13:54:34.102189  EX_ROW_EN[1]    = 0x0

 6099 13:54:34.104767  LP4Y_EN      = 0x0

 6100 13:54:34.105237  WORK_FSP     = 0x0

 6101 13:54:34.108067  WL           = 0x2

 6102 13:54:34.108543  RL           = 0x2

 6103 13:54:34.111526  BL           = 0x2

 6104 13:54:34.112003  RPST         = 0x0

 6105 13:54:34.114763  RD_PRE       = 0x0

 6106 13:54:34.115245  WR_PRE       = 0x1

 6107 13:54:34.118098  WR_PST       = 0x0

 6108 13:54:34.118652  DBI_WR       = 0x0

 6109 13:54:34.121597  DBI_RD       = 0x0

 6110 13:54:34.122057  OTF          = 0x1

 6111 13:54:34.124739  =================================== 

 6112 13:54:34.127900  =================================== 

 6113 13:54:34.131292  ANA top config

 6114 13:54:34.134696  =================================== 

 6115 13:54:34.134956  DLL_ASYNC_EN            =  0

 6116 13:54:34.137775  ALL_SLAVE_EN            =  1

 6117 13:54:34.141112  NEW_RANK_MODE           =  1

 6118 13:54:34.145126  DLL_IDLE_MODE           =  1

 6119 13:54:34.148300  LP45_APHY_COMB_EN       =  1

 6120 13:54:34.148545  TX_ODT_DIS              =  1

 6121 13:54:34.151621  NEW_8X_MODE             =  1

 6122 13:54:34.154860  =================================== 

 6123 13:54:34.158048  =================================== 

 6124 13:54:34.161411  data_rate                  =  800

 6125 13:54:34.164662  CKR                        = 1

 6126 13:54:34.167887  DQ_P2S_RATIO               = 4

 6127 13:54:34.171325  =================================== 

 6128 13:54:34.174309  CA_P2S_RATIO               = 4

 6129 13:54:34.174572  DQ_CA_OPEN                 = 0

 6130 13:54:34.177885  DQ_SEMI_OPEN               = 1

 6131 13:54:34.181579  CA_SEMI_OPEN               = 1

 6132 13:54:34.184914  CA_FULL_RATE               = 0

 6133 13:54:34.187970  DQ_CKDIV4_EN               = 0

 6134 13:54:34.191093  CA_CKDIV4_EN               = 1

 6135 13:54:34.191592  CA_PREDIV_EN               = 0

 6136 13:54:34.194440  PH8_DLY                    = 0

 6137 13:54:34.198088  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6138 13:54:34.201715  DQ_AAMCK_DIV               = 0

 6139 13:54:34.204882  CA_AAMCK_DIV               = 0

 6140 13:54:34.205452  CA_ADMCK_DIV               = 4

 6141 13:54:34.208050  DQ_TRACK_CA_EN             = 0

 6142 13:54:34.211502  CA_PICK                    = 800

 6143 13:54:34.214637  CA_MCKIO                   = 400

 6144 13:54:34.218173  MCKIO_SEMI                 = 400

 6145 13:54:34.221537  PLL_FREQ                   = 3016

 6146 13:54:34.224561  DQ_UI_PI_RATIO             = 32

 6147 13:54:34.227854  CA_UI_PI_RATIO             = 32

 6148 13:54:34.231380  =================================== 

 6149 13:54:34.234525  =================================== 

 6150 13:54:34.235033  memory_type:LPDDR4         

 6151 13:54:34.238010  GP_NUM     : 10       

 6152 13:54:34.241487  SRAM_EN    : 1       

 6153 13:54:34.242037  MD32_EN    : 0       

 6154 13:54:34.244867  =================================== 

 6155 13:54:34.248015  [ANA_INIT] >>>>>>>>>>>>>> 

 6156 13:54:34.251026  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6157 13:54:34.254491  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6158 13:54:34.257786  =================================== 

 6159 13:54:34.258078  data_rate = 800,PCW = 0X7400

 6160 13:54:34.261029  =================================== 

 6161 13:54:34.264442  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6162 13:54:34.271116  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6163 13:54:34.284510  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6164 13:54:34.287821  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6165 13:54:34.291256  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6166 13:54:34.294357  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6167 13:54:34.297865  [ANA_INIT] flow start 

 6168 13:54:34.298192  [ANA_INIT] PLL >>>>>>>> 

 6169 13:54:34.300892  [ANA_INIT] PLL <<<<<<<< 

 6170 13:54:34.304345  [ANA_INIT] MIDPI >>>>>>>> 

 6171 13:54:34.304710  [ANA_INIT] MIDPI <<<<<<<< 

 6172 13:54:34.307770  [ANA_INIT] DLL >>>>>>>> 

 6173 13:54:34.311125  [ANA_INIT] flow end 

 6174 13:54:34.314202  ============ LP4 DIFF to SE enter ============

 6175 13:54:34.317885  ============ LP4 DIFF to SE exit  ============

 6176 13:54:34.320855  [ANA_INIT] <<<<<<<<<<<<< 

 6177 13:54:34.324393  [Flow] Enable top DCM control >>>>> 

 6178 13:54:34.327428  [Flow] Enable top DCM control <<<<< 

 6179 13:54:34.331168  Enable DLL master slave shuffle 

 6180 13:54:34.337710  ============================================================== 

 6181 13:54:34.338341  Gating Mode config

 6182 13:54:34.344623  ============================================================== 

 6183 13:54:34.345203  Config description: 

 6184 13:54:34.354133  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6185 13:54:34.361101  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6186 13:54:34.367518  SELPH_MODE            0: By rank         1: By Phase 

 6187 13:54:34.370643  ============================================================== 

 6188 13:54:34.374311  GAT_TRACK_EN                 =  0

 6189 13:54:34.377496  RX_GATING_MODE               =  2

 6190 13:54:34.380614  RX_GATING_TRACK_MODE         =  2

 6191 13:54:34.383948  SELPH_MODE                   =  1

 6192 13:54:34.387148  PICG_EARLY_EN                =  1

 6193 13:54:34.390257  VALID_LAT_VALUE              =  1

 6194 13:54:34.393867  ============================================================== 

 6195 13:54:34.397047  Enter into Gating configuration >>>> 

 6196 13:54:34.400133  Exit from Gating configuration <<<< 

 6197 13:54:34.403766  Enter into  DVFS_PRE_config >>>>> 

 6198 13:54:34.417481  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6199 13:54:34.420352  Exit from  DVFS_PRE_config <<<<< 

 6200 13:54:34.423724  Enter into PICG configuration >>>> 

 6201 13:54:34.424045  Exit from PICG configuration <<<< 

 6202 13:54:34.426797  [RX_INPUT] configuration >>>>> 

 6203 13:54:34.430832  [RX_INPUT] configuration <<<<< 

 6204 13:54:34.437396  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6205 13:54:34.440611  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6206 13:54:34.447258  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6207 13:54:34.453910  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6208 13:54:34.460501  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6209 13:54:34.467167  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6210 13:54:34.470266  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6211 13:54:34.473560  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6212 13:54:34.476960  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6213 13:54:34.484177  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6214 13:54:34.486939  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6215 13:54:34.490261  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6216 13:54:34.493424  =================================== 

 6217 13:54:34.497048  LPDDR4 DRAM CONFIGURATION

 6218 13:54:34.500410  =================================== 

 6219 13:54:34.503707  EX_ROW_EN[0]    = 0x0

 6220 13:54:34.504183  EX_ROW_EN[1]    = 0x0

 6221 13:54:34.506845  LP4Y_EN      = 0x0

 6222 13:54:34.507550  WORK_FSP     = 0x0

 6223 13:54:34.510267  WL           = 0x2

 6224 13:54:34.510934  RL           = 0x2

 6225 13:54:34.513338  BL           = 0x2

 6226 13:54:34.514002  RPST         = 0x0

 6227 13:54:34.517096  RD_PRE       = 0x0

 6228 13:54:34.517547  WR_PRE       = 0x1

 6229 13:54:34.520424  WR_PST       = 0x0

 6230 13:54:34.520861  DBI_WR       = 0x0

 6231 13:54:34.523493  DBI_RD       = 0x0

 6232 13:54:34.523830  OTF          = 0x1

 6233 13:54:34.527498  =================================== 

 6234 13:54:34.530025  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6235 13:54:34.536873  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6236 13:54:34.540976  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6237 13:54:34.543700  =================================== 

 6238 13:54:34.547154  LPDDR4 DRAM CONFIGURATION

 6239 13:54:34.550393  =================================== 

 6240 13:54:34.550969  EX_ROW_EN[0]    = 0x10

 6241 13:54:34.553686  EX_ROW_EN[1]    = 0x0

 6242 13:54:34.557252  LP4Y_EN      = 0x0

 6243 13:54:34.557821  WORK_FSP     = 0x0

 6244 13:54:34.560784  WL           = 0x2

 6245 13:54:34.561380  RL           = 0x2

 6246 13:54:34.563681  BL           = 0x2

 6247 13:54:34.564249  RPST         = 0x0

 6248 13:54:34.566973  RD_PRE       = 0x0

 6249 13:54:34.567447  WR_PRE       = 0x1

 6250 13:54:34.570247  WR_PST       = 0x0

 6251 13:54:34.570939  DBI_WR       = 0x0

 6252 13:54:34.573550  DBI_RD       = 0x0

 6253 13:54:34.574267  OTF          = 0x1

 6254 13:54:34.576888  =================================== 

 6255 13:54:34.583433  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6256 13:54:34.587732  nWR fixed to 30

 6257 13:54:34.590723  [ModeRegInit_LP4] CH0 RK0

 6258 13:54:34.591194  [ModeRegInit_LP4] CH0 RK1

 6259 13:54:34.594566  [ModeRegInit_LP4] CH1 RK0

 6260 13:54:34.597745  [ModeRegInit_LP4] CH1 RK1

 6261 13:54:34.598343  match AC timing 19

 6262 13:54:34.604644  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6263 13:54:34.607450  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6264 13:54:34.610725  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6265 13:54:34.617426  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6266 13:54:34.620923  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6267 13:54:34.621402  ==

 6268 13:54:34.624347  Dram Type= 6, Freq= 0, CH_0, rank 0

 6269 13:54:34.627728  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6270 13:54:34.628417  ==

 6271 13:54:34.633923  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6272 13:54:34.640869  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6273 13:54:34.643956  [CA 0] Center 36 (8~64) winsize 57

 6274 13:54:34.647430  [CA 1] Center 36 (8~64) winsize 57

 6275 13:54:34.650390  [CA 2] Center 36 (8~64) winsize 57

 6276 13:54:34.650789  [CA 3] Center 36 (8~64) winsize 57

 6277 13:54:34.653848  [CA 4] Center 36 (8~64) winsize 57

 6278 13:54:34.657378  [CA 5] Center 36 (8~64) winsize 57

 6279 13:54:34.657709  

 6280 13:54:34.663893  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6281 13:54:34.664136  

 6282 13:54:34.667189  [CATrainingPosCal] consider 1 rank data

 6283 13:54:34.670429  u2DelayCellTimex100 = 270/100 ps

 6284 13:54:34.673713  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6285 13:54:34.677117  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6286 13:54:34.680572  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6287 13:54:34.683605  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6288 13:54:34.686830  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6289 13:54:34.690449  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6290 13:54:34.690758  

 6291 13:54:34.694031  CA PerBit enable=1, Macro0, CA PI delay=36

 6292 13:54:34.694428  

 6293 13:54:34.697617  [CBTSetCACLKResult] CA Dly = 36

 6294 13:54:34.700847  CS Dly: 1 (0~32)

 6295 13:54:34.701412  ==

 6296 13:54:34.703829  Dram Type= 6, Freq= 0, CH_0, rank 1

 6297 13:54:34.707190  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6298 13:54:34.707870  ==

 6299 13:54:34.714055  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6300 13:54:34.717198  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 6301 13:54:34.720595  [CA 0] Center 36 (8~64) winsize 57

 6302 13:54:34.724118  [CA 1] Center 36 (8~64) winsize 57

 6303 13:54:34.726907  [CA 2] Center 36 (8~64) winsize 57

 6304 13:54:34.730304  [CA 3] Center 36 (8~64) winsize 57

 6305 13:54:34.734010  [CA 4] Center 36 (8~64) winsize 57

 6306 13:54:34.737140  [CA 5] Center 36 (8~64) winsize 57

 6307 13:54:34.737707  

 6308 13:54:34.740553  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 6309 13:54:34.741122  

 6310 13:54:34.743779  [CATrainingPosCal] consider 2 rank data

 6311 13:54:34.746761  u2DelayCellTimex100 = 270/100 ps

 6312 13:54:34.750637  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6313 13:54:34.753499  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6314 13:54:34.760452  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6315 13:54:34.763446  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6316 13:54:34.766863  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6317 13:54:34.770385  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6318 13:54:34.771043  

 6319 13:54:34.773310  CA PerBit enable=1, Macro0, CA PI delay=36

 6320 13:54:34.773803  

 6321 13:54:34.776773  [CBTSetCACLKResult] CA Dly = 36

 6322 13:54:34.777161  CS Dly: 1 (0~32)

 6323 13:54:34.777477  

 6324 13:54:34.780171  ----->DramcWriteLeveling(PI) begin...

 6325 13:54:34.783150  ==

 6326 13:54:34.783424  Dram Type= 6, Freq= 0, CH_0, rank 0

 6327 13:54:34.789933  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6328 13:54:34.790180  ==

 6329 13:54:34.793207  Write leveling (Byte 0): 40 => 8

 6330 13:54:34.796428  Write leveling (Byte 1): 32 => 0

 6331 13:54:34.796570  DramcWriteLeveling(PI) end<-----

 6332 13:54:34.799729  

 6333 13:54:34.799901  ==

 6334 13:54:34.802928  Dram Type= 6, Freq= 0, CH_0, rank 0

 6335 13:54:34.806345  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6336 13:54:34.806454  ==

 6337 13:54:34.809529  [Gating] SW mode calibration

 6338 13:54:34.816530  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6339 13:54:34.819754  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6340 13:54:34.826677   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6341 13:54:34.829809   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6342 13:54:34.833124   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6343 13:54:34.839935   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6344 13:54:34.843140   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6345 13:54:34.846293   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6346 13:54:34.853282   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6347 13:54:34.856521   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6348 13:54:34.859617   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6349 13:54:34.863192  Total UI for P1: 0, mck2ui 16

 6350 13:54:34.866302  best dqsien dly found for B0: ( 0, 14, 24)

 6351 13:54:34.869662  Total UI for P1: 0, mck2ui 16

 6352 13:54:34.872962  best dqsien dly found for B1: ( 0, 14, 24)

 6353 13:54:34.876828  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6354 13:54:34.880007  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6355 13:54:34.880578  

 6356 13:54:34.886464  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6357 13:54:34.889490  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6358 13:54:34.892880  [Gating] SW calibration Done

 6359 13:54:34.893528  ==

 6360 13:54:34.895938  Dram Type= 6, Freq= 0, CH_0, rank 0

 6361 13:54:34.899328  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6362 13:54:34.899970  ==

 6363 13:54:34.900563  RX Vref Scan: 0

 6364 13:54:34.901142  

 6365 13:54:34.902463  RX Vref 0 -> 0, step: 1

 6366 13:54:34.903095  

 6367 13:54:34.905936  RX Delay -410 -> 252, step: 16

 6368 13:54:34.909040  iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480

 6369 13:54:34.915862  iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480

 6370 13:54:34.919033  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6371 13:54:34.922539  iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480

 6372 13:54:34.925957  iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480

 6373 13:54:34.932595  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6374 13:54:34.936006  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6375 13:54:34.939548  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6376 13:54:34.942700  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6377 13:54:34.945741  iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480

 6378 13:54:34.953098  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6379 13:54:34.956236  iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464

 6380 13:54:34.959895  iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480

 6381 13:54:34.966378  iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480

 6382 13:54:34.969514  iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480

 6383 13:54:34.972743  iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480

 6384 13:54:34.973209  ==

 6385 13:54:34.975985  Dram Type= 6, Freq= 0, CH_0, rank 0

 6386 13:54:34.979664  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6387 13:54:34.980131  ==

 6388 13:54:34.983034  DQS Delay:

 6389 13:54:34.983494  DQS0 = 27, DQS1 = 43

 6390 13:54:34.986019  DQM Delay:

 6391 13:54:34.986477  DQM0 = 11, DQM1 = 12

 6392 13:54:34.989641  DQ Delay:

 6393 13:54:34.990150  DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =0

 6394 13:54:34.993019  DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24

 6395 13:54:34.996144  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6396 13:54:34.999524  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6397 13:54:35.000081  

 6398 13:54:35.000447  

 6399 13:54:35.000783  ==

 6400 13:54:35.002771  Dram Type= 6, Freq= 0, CH_0, rank 0

 6401 13:54:35.009311  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6402 13:54:35.009733  ==

 6403 13:54:35.010099  

 6404 13:54:35.010415  

 6405 13:54:35.010709  	TX Vref Scan disable

 6406 13:54:35.012541   == TX Byte 0 ==

 6407 13:54:35.016326  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6408 13:54:35.019260  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6409 13:54:35.022825   == TX Byte 1 ==

 6410 13:54:35.026194  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6411 13:54:35.029657  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6412 13:54:35.032839  ==

 6413 13:54:35.035770  Dram Type= 6, Freq= 0, CH_0, rank 0

 6414 13:54:35.039061  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6415 13:54:35.039657  ==

 6416 13:54:35.040216  

 6417 13:54:35.040748  

 6418 13:54:35.042507  	TX Vref Scan disable

 6419 13:54:35.042805   == TX Byte 0 ==

 6420 13:54:35.045914  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6421 13:54:35.052134  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6422 13:54:35.052316   == TX Byte 1 ==

 6423 13:54:35.055443  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6424 13:54:35.062508  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6425 13:54:35.062930  

 6426 13:54:35.063256  [DATLAT]

 6427 13:54:35.063557  Freq=400, CH0 RK0

 6428 13:54:35.063854  

 6429 13:54:35.065720  DATLAT Default: 0xf

 6430 13:54:35.069112  0, 0xFFFF, sum = 0

 6431 13:54:35.069535  1, 0xFFFF, sum = 0

 6432 13:54:35.072508  2, 0xFFFF, sum = 0

 6433 13:54:35.073033  3, 0xFFFF, sum = 0

 6434 13:54:35.075922  4, 0xFFFF, sum = 0

 6435 13:54:35.076347  5, 0xFFFF, sum = 0

 6436 13:54:35.079494  6, 0xFFFF, sum = 0

 6437 13:54:35.080012  7, 0xFFFF, sum = 0

 6438 13:54:35.082156  8, 0xFFFF, sum = 0

 6439 13:54:35.082581  9, 0xFFFF, sum = 0

 6440 13:54:35.086042  10, 0xFFFF, sum = 0

 6441 13:54:35.086555  11, 0xFFFF, sum = 0

 6442 13:54:35.089115  12, 0xFFFF, sum = 0

 6443 13:54:35.089541  13, 0x0, sum = 1

 6444 13:54:35.092246  14, 0x0, sum = 2

 6445 13:54:35.092781  15, 0x0, sum = 3

 6446 13:54:35.095654  16, 0x0, sum = 4

 6447 13:54:35.096196  best_step = 14

 6448 13:54:35.096541  

 6449 13:54:35.096853  ==

 6450 13:54:35.099291  Dram Type= 6, Freq= 0, CH_0, rank 0

 6451 13:54:35.105604  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6452 13:54:35.106187  ==

 6453 13:54:35.106544  RX Vref Scan: 1

 6454 13:54:35.106862  

 6455 13:54:35.108940  RX Vref 0 -> 0, step: 1

 6456 13:54:35.109371  

 6457 13:54:35.112085  RX Delay -327 -> 252, step: 8

 6458 13:54:35.112516  

 6459 13:54:35.115547  Set Vref, RX VrefLevel [Byte0]: 62

 6460 13:54:35.118756                           [Byte1]: 50

 6461 13:54:35.119287  

 6462 13:54:35.122295  Final RX Vref Byte 0 = 62 to rank0

 6463 13:54:35.125748  Final RX Vref Byte 1 = 50 to rank0

 6464 13:54:35.128813  Final RX Vref Byte 0 = 62 to rank1

 6465 13:54:35.132242  Final RX Vref Byte 1 = 50 to rank1==

 6466 13:54:35.135417  Dram Type= 6, Freq= 0, CH_0, rank 0

 6467 13:54:35.138813  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6468 13:54:35.139250  ==

 6469 13:54:35.142539  DQS Delay:

 6470 13:54:35.143063  DQS0 = 28, DQS1 = 48

 6471 13:54:35.145775  DQM Delay:

 6472 13:54:35.146344  DQM0 = 11, DQM1 = 15

 6473 13:54:35.148670  DQ Delay:

 6474 13:54:35.149215  DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8

 6475 13:54:35.151870  DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20

 6476 13:54:35.155363  DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12

 6477 13:54:35.158539  DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24

 6478 13:54:35.159137  

 6479 13:54:35.159692  

 6480 13:54:35.168746  [DQSOSCAuto] RK0, (LSB)MR18= 0xb4ac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps

 6481 13:54:35.172008  CH0 RK0: MR19=C0C, MR18=B4AC

 6482 13:54:35.175269  CH0_RK0: MR19=0xC0C, MR18=0xB4AC, DQSOSC=387, MR23=63, INC=394, DEC=262

 6483 13:54:35.178590  ==

 6484 13:54:35.181826  Dram Type= 6, Freq= 0, CH_0, rank 1

 6485 13:54:35.185313  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6486 13:54:35.185930  ==

 6487 13:54:35.188499  [Gating] SW mode calibration

 6488 13:54:35.194884  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6489 13:54:35.198727  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6490 13:54:35.204979   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6491 13:54:35.208673   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6492 13:54:35.211874   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6493 13:54:35.218360   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6494 13:54:35.221684   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6495 13:54:35.224907   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6496 13:54:35.232073   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6497 13:54:35.235374   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6498 13:54:35.238459   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6499 13:54:35.241614  Total UI for P1: 0, mck2ui 16

 6500 13:54:35.245419  best dqsien dly found for B0: ( 0, 14, 24)

 6501 13:54:35.248342  Total UI for P1: 0, mck2ui 16

 6502 13:54:35.252157  best dqsien dly found for B1: ( 0, 14, 24)

 6503 13:54:35.255375  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6504 13:54:35.258561  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6505 13:54:35.259137  

 6506 13:54:35.261933  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6507 13:54:35.268490  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6508 13:54:35.269046  [Gating] SW calibration Done

 6509 13:54:35.269504  ==

 6510 13:54:35.271713  Dram Type= 6, Freq= 0, CH_0, rank 1

 6511 13:54:35.278255  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6512 13:54:35.278727  ==

 6513 13:54:35.279445  RX Vref Scan: 0

 6514 13:54:35.280281  

 6515 13:54:35.281706  RX Vref 0 -> 0, step: 1

 6516 13:54:35.282521  

 6517 13:54:35.285115  RX Delay -410 -> 252, step: 16

 6518 13:54:35.288070  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6519 13:54:35.292149  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6520 13:54:35.298411  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6521 13:54:35.301595  iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480

 6522 13:54:35.304943  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6523 13:54:35.308503  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6524 13:54:35.314788  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6525 13:54:35.318038  iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480

 6526 13:54:35.321582  iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480

 6527 13:54:35.324757  iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480

 6528 13:54:35.331395  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6529 13:54:35.334565  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6530 13:54:35.338062  iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480

 6531 13:54:35.344769  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6532 13:54:35.348371  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6533 13:54:35.351302  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6534 13:54:35.351831  ==

 6535 13:54:35.354506  Dram Type= 6, Freq= 0, CH_0, rank 1

 6536 13:54:35.358419  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6537 13:54:35.358950  ==

 6538 13:54:35.361775  DQS Delay:

 6539 13:54:35.362354  DQS0 = 27, DQS1 = 43

 6540 13:54:35.364827  DQM Delay:

 6541 13:54:35.365572  DQM0 = 8, DQM1 = 15

 6542 13:54:35.366155  DQ Delay:

 6543 13:54:35.367977  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0

 6544 13:54:35.371127  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6545 13:54:35.375081  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16

 6546 13:54:35.378125  DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24

 6547 13:54:35.378549  

 6548 13:54:35.378882  

 6549 13:54:35.379189  ==

 6550 13:54:35.381404  Dram Type= 6, Freq= 0, CH_0, rank 1

 6551 13:54:35.388284  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6552 13:54:35.388848  ==

 6553 13:54:35.389184  

 6554 13:54:35.389489  

 6555 13:54:35.389783  	TX Vref Scan disable

 6556 13:54:35.391440   == TX Byte 0 ==

 6557 13:54:35.394547  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6558 13:54:35.398188  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6559 13:54:35.401514   == TX Byte 1 ==

 6560 13:54:35.404916  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6561 13:54:35.408438  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6562 13:54:35.408962  ==

 6563 13:54:35.411064  Dram Type= 6, Freq= 0, CH_0, rank 1

 6564 13:54:35.417732  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6565 13:54:35.418282  ==

 6566 13:54:35.418622  

 6567 13:54:35.419106  

 6568 13:54:35.419426  	TX Vref Scan disable

 6569 13:54:35.420963   == TX Byte 0 ==

 6570 13:54:35.424325  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6571 13:54:35.427673  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6572 13:54:35.430890   == TX Byte 1 ==

 6573 13:54:35.434202  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6574 13:54:35.437302  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6575 13:54:35.437742  

 6576 13:54:35.440831  [DATLAT]

 6577 13:54:35.441280  Freq=400, CH0 RK1

 6578 13:54:35.441639  

 6579 13:54:35.444144  DATLAT Default: 0xe

 6580 13:54:35.444574  0, 0xFFFF, sum = 0

 6581 13:54:35.447315  1, 0xFFFF, sum = 0

 6582 13:54:35.447753  2, 0xFFFF, sum = 0

 6583 13:54:35.450634  3, 0xFFFF, sum = 0

 6584 13:54:35.451070  4, 0xFFFF, sum = 0

 6585 13:54:35.453931  5, 0xFFFF, sum = 0

 6586 13:54:35.454389  6, 0xFFFF, sum = 0

 6587 13:54:35.457443  7, 0xFFFF, sum = 0

 6588 13:54:35.457881  8, 0xFFFF, sum = 0

 6589 13:54:35.460905  9, 0xFFFF, sum = 0

 6590 13:54:35.461503  10, 0xFFFF, sum = 0

 6591 13:54:35.464124  11, 0xFFFF, sum = 0

 6592 13:54:35.468035  12, 0xFFFF, sum = 0

 6593 13:54:35.468586  13, 0x0, sum = 1

 6594 13:54:35.470454  14, 0x0, sum = 2

 6595 13:54:35.470893  15, 0x0, sum = 3

 6596 13:54:35.471237  16, 0x0, sum = 4

 6597 13:54:35.474370  best_step = 14

 6598 13:54:35.474911  

 6599 13:54:35.475254  ==

 6600 13:54:35.477264  Dram Type= 6, Freq= 0, CH_0, rank 1

 6601 13:54:35.480969  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6602 13:54:35.481502  ==

 6603 13:54:35.484172  RX Vref Scan: 0

 6604 13:54:35.484700  

 6605 13:54:35.485042  RX Vref 0 -> 0, step: 1

 6606 13:54:35.487388  

 6607 13:54:35.487816  RX Delay -327 -> 252, step: 8

 6608 13:54:35.496013  iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456

 6609 13:54:35.499000  iDelay=217, Bit 1, Center -20 (-247 ~ 208) 456

 6610 13:54:35.502509  iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456

 6611 13:54:35.505615  iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448

 6612 13:54:35.512432  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6613 13:54:35.515810  iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456

 6614 13:54:35.519344  iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456

 6615 13:54:35.522296  iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456

 6616 13:54:35.528882  iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456

 6617 13:54:35.532771  iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448

 6618 13:54:35.535745  iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448

 6619 13:54:35.539086  iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456

 6620 13:54:35.545737  iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448

 6621 13:54:35.548938  iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448

 6622 13:54:35.552148  iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448

 6623 13:54:35.558566  iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448

 6624 13:54:35.559121  ==

 6625 13:54:35.562603  Dram Type= 6, Freq= 0, CH_0, rank 1

 6626 13:54:35.565330  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6627 13:54:35.565806  ==

 6628 13:54:35.566235  DQS Delay:

 6629 13:54:35.568617  DQS0 = 28, DQS1 = 40

 6630 13:54:35.569178  DQM Delay:

 6631 13:54:35.572308  DQM0 = 9, DQM1 = 12

 6632 13:54:35.572776  DQ Delay:

 6633 13:54:35.575263  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4

 6634 13:54:35.578436  DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16

 6635 13:54:35.582243  DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4

 6636 13:54:35.585119  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6637 13:54:35.585587  

 6638 13:54:35.585993  

 6639 13:54:35.591807  [DQSOSCAuto] RK1, (LSB)MR18= 0xbc6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps

 6640 13:54:35.595244  CH0 RK1: MR19=C0C, MR18=BC6E

 6641 13:54:35.602199  CH0_RK1: MR19=0xC0C, MR18=0xBC6E, DQSOSC=386, MR23=63, INC=396, DEC=264

 6642 13:54:35.605352  [RxdqsGatingPostProcess] freq 400

 6643 13:54:35.611702  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6644 13:54:35.612031  best DQS0 dly(2T, 0.5T) = (0, 10)

 6645 13:54:35.615127  best DQS1 dly(2T, 0.5T) = (0, 10)

 6646 13:54:35.618301  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6647 13:54:35.622020  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6648 13:54:35.625248  best DQS0 dly(2T, 0.5T) = (0, 10)

 6649 13:54:35.628821  best DQS1 dly(2T, 0.5T) = (0, 10)

 6650 13:54:35.631607  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6651 13:54:35.635286  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6652 13:54:35.638561  Pre-setting of DQS Precalculation

 6653 13:54:35.641831  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6654 13:54:35.645273  ==

 6655 13:54:35.648541  Dram Type= 6, Freq= 0, CH_1, rank 0

 6656 13:54:35.651655  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6657 13:54:35.652227  ==

 6658 13:54:35.655083  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6659 13:54:35.661583  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31

 6660 13:54:35.665099  [CA 0] Center 36 (8~64) winsize 57

 6661 13:54:35.668428  [CA 1] Center 36 (8~64) winsize 57

 6662 13:54:35.671653  [CA 2] Center 36 (8~64) winsize 57

 6663 13:54:35.675015  [CA 3] Center 36 (8~64) winsize 57

 6664 13:54:35.678284  [CA 4] Center 36 (8~64) winsize 57

 6665 13:54:35.681549  [CA 5] Center 36 (8~64) winsize 57

 6666 13:54:35.682076  

 6667 13:54:35.684806  [CmdBusTrainingLP45] Vref(ca) range 1: 31

 6668 13:54:35.685278  

 6669 13:54:35.688261  [CATrainingPosCal] consider 1 rank data

 6670 13:54:35.691613  u2DelayCellTimex100 = 270/100 ps

 6671 13:54:35.694867  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6672 13:54:35.698134  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6673 13:54:35.701380  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6674 13:54:35.704458  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6675 13:54:35.711330  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6676 13:54:35.714261  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6677 13:54:35.714593  

 6678 13:54:35.717825  CA PerBit enable=1, Macro0, CA PI delay=36

 6679 13:54:35.718089  

 6680 13:54:35.721280  [CBTSetCACLKResult] CA Dly = 36

 6681 13:54:35.721617  CS Dly: 1 (0~32)

 6682 13:54:35.721825  ==

 6683 13:54:35.724540  Dram Type= 6, Freq= 0, CH_1, rank 1

 6684 13:54:35.731122  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6685 13:54:35.731317  ==

 6686 13:54:35.734105  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6687 13:54:35.741409  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6688 13:54:35.744843  [CA 0] Center 36 (8~64) winsize 57

 6689 13:54:35.748007  [CA 1] Center 36 (8~64) winsize 57

 6690 13:54:35.751209  [CA 2] Center 36 (8~64) winsize 57

 6691 13:54:35.754201  [CA 3] Center 36 (8~64) winsize 57

 6692 13:54:35.757798  [CA 4] Center 36 (8~64) winsize 57

 6693 13:54:35.761149  [CA 5] Center 36 (8~64) winsize 57

 6694 13:54:35.761530  

 6695 13:54:35.764261  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6696 13:54:35.764644  

 6697 13:54:35.768030  [CATrainingPosCal] consider 2 rank data

 6698 13:54:35.771140  u2DelayCellTimex100 = 270/100 ps

 6699 13:54:35.774409  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6700 13:54:35.777840  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6701 13:54:35.781180  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6702 13:54:35.784546  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6703 13:54:35.788035  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6704 13:54:35.791069  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6705 13:54:35.791537  

 6706 13:54:35.797627  CA PerBit enable=1, Macro0, CA PI delay=36

 6707 13:54:35.798242  

 6708 13:54:35.798627  [CBTSetCACLKResult] CA Dly = 36

 6709 13:54:35.801120  CS Dly: 1 (0~32)

 6710 13:54:35.801586  

 6711 13:54:35.804457  ----->DramcWriteLeveling(PI) begin...

 6712 13:54:35.805051  ==

 6713 13:54:35.808050  Dram Type= 6, Freq= 0, CH_1, rank 0

 6714 13:54:35.811271  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6715 13:54:35.811745  ==

 6716 13:54:35.814144  Write leveling (Byte 0): 40 => 8

 6717 13:54:35.817643  Write leveling (Byte 1): 32 => 0

 6718 13:54:35.820859  DramcWriteLeveling(PI) end<-----

 6719 13:54:35.821329  

 6720 13:54:35.821701  ==

 6721 13:54:35.823959  Dram Type= 6, Freq= 0, CH_1, rank 0

 6722 13:54:35.827698  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6723 13:54:35.831000  ==

 6724 13:54:35.831476  [Gating] SW mode calibration

 6725 13:54:35.840863  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6726 13:54:35.844195  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6727 13:54:35.847244   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6728 13:54:35.854002   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6729 13:54:35.857422   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6730 13:54:35.860511   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6731 13:54:35.867755   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6732 13:54:35.870744   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6733 13:54:35.874287   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6734 13:54:35.880933   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6735 13:54:35.883911   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6736 13:54:35.887652  Total UI for P1: 0, mck2ui 16

 6737 13:54:35.890864  best dqsien dly found for B0: ( 0, 14, 24)

 6738 13:54:35.894092  Total UI for P1: 0, mck2ui 16

 6739 13:54:35.897641  best dqsien dly found for B1: ( 0, 14, 24)

 6740 13:54:35.900808  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6741 13:54:35.903830  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6742 13:54:35.904298  

 6743 13:54:35.907339  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6744 13:54:35.910585  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6745 13:54:35.914047  [Gating] SW calibration Done

 6746 13:54:35.914531  ==

 6747 13:54:35.917831  Dram Type= 6, Freq= 0, CH_1, rank 0

 6748 13:54:35.920810  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6749 13:54:35.921311  ==

 6750 13:54:35.924247  RX Vref Scan: 0

 6751 13:54:35.924717  

 6752 13:54:35.927705  RX Vref 0 -> 0, step: 1

 6753 13:54:35.928287  

 6754 13:54:35.928664  RX Delay -410 -> 252, step: 16

 6755 13:54:35.934586  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6756 13:54:35.937713  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6757 13:54:35.941127  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6758 13:54:35.947565  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6759 13:54:35.950720  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6760 13:54:35.953814  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6761 13:54:35.957293  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6762 13:54:35.960691  iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480

 6763 13:54:35.967508  iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480

 6764 13:54:35.970811  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6765 13:54:35.973791  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6766 13:54:35.977220  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6767 13:54:35.983708  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6768 13:54:35.986993  iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480

 6769 13:54:35.990239  iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480

 6770 13:54:35.997326  iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496

 6771 13:54:35.997574  ==

 6772 13:54:36.000345  Dram Type= 6, Freq= 0, CH_1, rank 0

 6773 13:54:36.003575  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6774 13:54:36.003792  ==

 6775 13:54:36.003931  DQS Delay:

 6776 13:54:36.006979  DQS0 = 27, DQS1 = 43

 6777 13:54:36.007226  DQM Delay:

 6778 13:54:36.010353  DQM0 = 9, DQM1 = 18

 6779 13:54:36.010598  DQ Delay:

 6780 13:54:36.013616  DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8

 6781 13:54:36.017240  DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0

 6782 13:54:36.020420  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16

 6783 13:54:36.023547  DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =24

 6784 13:54:36.023778  

 6785 13:54:36.023945  

 6786 13:54:36.024091  ==

 6787 13:54:36.026806  Dram Type= 6, Freq= 0, CH_1, rank 0

 6788 13:54:36.030279  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6789 13:54:36.030584  ==

 6790 13:54:36.030759  

 6791 13:54:36.030918  

 6792 13:54:36.033530  	TX Vref Scan disable

 6793 13:54:36.034041   == TX Byte 0 ==

 6794 13:54:36.040617  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6795 13:54:36.043716  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6796 13:54:36.044208   == TX Byte 1 ==

 6797 13:54:36.050528  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6798 13:54:36.053569  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6799 13:54:36.054073  ==

 6800 13:54:36.056872  Dram Type= 6, Freq= 0, CH_1, rank 0

 6801 13:54:36.060483  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6802 13:54:36.061001  ==

 6803 13:54:36.061420  

 6804 13:54:36.061794  

 6805 13:54:36.063773  	TX Vref Scan disable

 6806 13:54:36.066755   == TX Byte 0 ==

 6807 13:54:36.070301  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6808 13:54:36.073728  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6809 13:54:36.076699   == TX Byte 1 ==

 6810 13:54:36.080120  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6811 13:54:36.083225  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6812 13:54:36.083661  

 6813 13:54:36.083996  [DATLAT]

 6814 13:54:36.086598  Freq=400, CH1 RK0

 6815 13:54:36.087027  

 6816 13:54:36.087433  DATLAT Default: 0xf

 6817 13:54:36.089999  0, 0xFFFF, sum = 0

 6818 13:54:36.090453  1, 0xFFFF, sum = 0

 6819 13:54:36.093532  2, 0xFFFF, sum = 0

 6820 13:54:36.096783  3, 0xFFFF, sum = 0

 6821 13:54:36.097216  4, 0xFFFF, sum = 0

 6822 13:54:36.100011  5, 0xFFFF, sum = 0

 6823 13:54:36.100449  6, 0xFFFF, sum = 0

 6824 13:54:36.103722  7, 0xFFFF, sum = 0

 6825 13:54:36.104150  8, 0xFFFF, sum = 0

 6826 13:54:36.106875  9, 0xFFFF, sum = 0

 6827 13:54:36.107310  10, 0xFFFF, sum = 0

 6828 13:54:36.109931  11, 0xFFFF, sum = 0

 6829 13:54:36.110394  12, 0xFFFF, sum = 0

 6830 13:54:36.113577  13, 0x0, sum = 1

 6831 13:54:36.114033  14, 0x0, sum = 2

 6832 13:54:36.117098  15, 0x0, sum = 3

 6833 13:54:36.117535  16, 0x0, sum = 4

 6834 13:54:36.119918  best_step = 14

 6835 13:54:36.120342  

 6836 13:54:36.120674  ==

 6837 13:54:36.123380  Dram Type= 6, Freq= 0, CH_1, rank 0

 6838 13:54:36.126475  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6839 13:54:36.126902  ==

 6840 13:54:36.127235  RX Vref Scan: 1

 6841 13:54:36.130359  

 6842 13:54:36.130780  RX Vref 0 -> 0, step: 1

 6843 13:54:36.131118  

 6844 13:54:36.133392  RX Delay -327 -> 252, step: 8

 6845 13:54:36.133829  

 6846 13:54:36.136953  Set Vref, RX VrefLevel [Byte0]: 52

 6847 13:54:36.140002                           [Byte1]: 50

 6848 13:54:36.144046  

 6849 13:54:36.144565  Final RX Vref Byte 0 = 52 to rank0

 6850 13:54:36.147603  Final RX Vref Byte 1 = 50 to rank0

 6851 13:54:36.150905  Final RX Vref Byte 0 = 52 to rank1

 6852 13:54:36.154328  Final RX Vref Byte 1 = 50 to rank1==

 6853 13:54:36.157760  Dram Type= 6, Freq= 0, CH_1, rank 0

 6854 13:54:36.164092  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6855 13:54:36.164636  ==

 6856 13:54:36.164985  DQS Delay:

 6857 13:54:36.167202  DQS0 = 32, DQS1 = 40

 6858 13:54:36.167633  DQM Delay:

 6859 13:54:36.167970  DQM0 = 11, DQM1 = 13

 6860 13:54:36.170779  DQ Delay:

 6861 13:54:36.174093  DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8

 6862 13:54:36.174527  DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8

 6863 13:54:36.177474  DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4

 6864 13:54:36.180563  DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20

 6865 13:54:36.181169  

 6866 13:54:36.184165  

 6867 13:54:36.190856  [DQSOSCAuto] RK0, (LSB)MR18= 0x94ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps

 6868 13:54:36.193730  CH1 RK0: MR19=C0C, MR18=94CE

 6869 13:54:36.200755  CH1_RK0: MR19=0xC0C, MR18=0x94CE, DQSOSC=384, MR23=63, INC=400, DEC=267

 6870 13:54:36.201335  ==

 6871 13:54:36.203848  Dram Type= 6, Freq= 0, CH_1, rank 1

 6872 13:54:36.207007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6873 13:54:36.207967  ==

 6874 13:54:36.210345  [Gating] SW mode calibration

 6875 13:54:36.216837  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6876 13:54:36.223603  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6877 13:54:36.226595   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6878 13:54:36.230353   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6879 13:54:36.233430   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6880 13:54:36.240013   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6881 13:54:36.243283   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6882 13:54:36.246635   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6883 13:54:36.253143   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6884 13:54:36.256771   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6885 13:54:36.259867   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6886 13:54:36.263785  Total UI for P1: 0, mck2ui 16

 6887 13:54:36.267222  best dqsien dly found for B0: ( 0, 14, 24)

 6888 13:54:36.270533  Total UI for P1: 0, mck2ui 16

 6889 13:54:36.273680  best dqsien dly found for B1: ( 0, 14, 24)

 6890 13:54:36.277151  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6891 13:54:36.280349  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6892 13:54:36.280826  

 6893 13:54:36.287343  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6894 13:54:36.290380  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6895 13:54:36.293507  [Gating] SW calibration Done

 6896 13:54:36.294146  ==

 6897 13:54:36.297248  Dram Type= 6, Freq= 0, CH_1, rank 1

 6898 13:54:36.300412  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6899 13:54:36.301063  ==

 6900 13:54:36.301451  RX Vref Scan: 0

 6901 13:54:36.301793  

 6902 13:54:36.303997  RX Vref 0 -> 0, step: 1

 6903 13:54:36.304569  

 6904 13:54:36.307034  RX Delay -410 -> 252, step: 16

 6905 13:54:36.310154  iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448

 6906 13:54:36.316956  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6907 13:54:36.320179  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6908 13:54:36.323553  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6909 13:54:36.326575  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6910 13:54:36.333504  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6911 13:54:36.336543  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6912 13:54:36.339834  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6913 13:54:36.343268  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6914 13:54:36.349684  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6915 13:54:36.353584  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6916 13:54:36.356471  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6917 13:54:36.360118  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6918 13:54:36.366418  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6919 13:54:36.369795  iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480

 6920 13:54:36.372885  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6921 13:54:36.373376  ==

 6922 13:54:36.376574  Dram Type= 6, Freq= 0, CH_1, rank 1

 6923 13:54:36.379824  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6924 13:54:36.382960  ==

 6925 13:54:36.383432  DQS Delay:

 6926 13:54:36.383804  DQS0 = 35, DQS1 = 35

 6927 13:54:36.386292  DQM Delay:

 6928 13:54:36.386773  DQM0 = 18, DQM1 = 12

 6929 13:54:36.389450  DQ Delay:

 6930 13:54:36.393314  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6931 13:54:36.393783  DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16

 6932 13:54:36.396433  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6933 13:54:36.399585  DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24

 6934 13:54:36.400155  

 6935 13:54:36.403372  

 6936 13:54:36.403941  ==

 6937 13:54:36.406183  Dram Type= 6, Freq= 0, CH_1, rank 1

 6938 13:54:36.409697  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6939 13:54:36.410368  ==

 6940 13:54:36.410765  

 6941 13:54:36.411106  

 6942 13:54:36.413048  	TX Vref Scan disable

 6943 13:54:36.413538   == TX Byte 0 ==

 6944 13:54:36.416261  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6945 13:54:36.422763  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6946 13:54:36.423236   == TX Byte 1 ==

 6947 13:54:36.426103  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6948 13:54:36.432512  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6949 13:54:36.432981  ==

 6950 13:54:36.436025  Dram Type= 6, Freq= 0, CH_1, rank 1

 6951 13:54:36.439386  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6952 13:54:36.439858  ==

 6953 13:54:36.440226  

 6954 13:54:36.440564  

 6955 13:54:36.442646  	TX Vref Scan disable

 6956 13:54:36.443115   == TX Byte 0 ==

 6957 13:54:36.445811  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6958 13:54:36.452985  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6959 13:54:36.453567   == TX Byte 1 ==

 6960 13:54:36.456216  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6961 13:54:36.462752  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6962 13:54:36.463331  

 6963 13:54:36.463702  [DATLAT]

 6964 13:54:36.464043  Freq=400, CH1 RK1

 6965 13:54:36.466262  

 6966 13:54:36.466837  DATLAT Default: 0xe

 6967 13:54:36.469202  0, 0xFFFF, sum = 0

 6968 13:54:36.469684  1, 0xFFFF, sum = 0

 6969 13:54:36.472598  2, 0xFFFF, sum = 0

 6970 13:54:36.473195  3, 0xFFFF, sum = 0

 6971 13:54:36.476099  4, 0xFFFF, sum = 0

 6972 13:54:36.476753  5, 0xFFFF, sum = 0

 6973 13:54:36.479050  6, 0xFFFF, sum = 0

 6974 13:54:36.479529  7, 0xFFFF, sum = 0

 6975 13:54:36.482207  8, 0xFFFF, sum = 0

 6976 13:54:36.482747  9, 0xFFFF, sum = 0

 6977 13:54:36.485696  10, 0xFFFF, sum = 0

 6978 13:54:36.486386  11, 0xFFFF, sum = 0

 6979 13:54:36.488968  12, 0xFFFF, sum = 0

 6980 13:54:36.489443  13, 0x0, sum = 1

 6981 13:54:36.492950  14, 0x0, sum = 2

 6982 13:54:36.493555  15, 0x0, sum = 3

 6983 13:54:36.495978  16, 0x0, sum = 4

 6984 13:54:36.496664  best_step = 14

 6985 13:54:36.497290  

 6986 13:54:36.497662  ==

 6987 13:54:36.499301  Dram Type= 6, Freq= 0, CH_1, rank 1

 6988 13:54:36.505732  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6989 13:54:36.506456  ==

 6990 13:54:36.507087  RX Vref Scan: 0

 6991 13:54:36.507659  

 6992 13:54:36.509016  RX Vref 0 -> 0, step: 1

 6993 13:54:36.509483  

 6994 13:54:36.512456  RX Delay -311 -> 252, step: 8

 6995 13:54:36.519087  iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432

 6996 13:54:36.522320  iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440

 6997 13:54:36.525510  iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448

 6998 13:54:36.529105  iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448

 6999 13:54:36.535702  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 7000 13:54:36.538795  iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448

 7001 13:54:36.541997  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 7002 13:54:36.545984  iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448

 7003 13:54:36.548962  iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456

 7004 13:54:36.555732  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 7005 13:54:36.559102  iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448

 7006 13:54:36.562080  iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456

 7007 13:54:36.568881  iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456

 7008 13:54:36.572485  iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456

 7009 13:54:36.575723  iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456

 7010 13:54:36.579051  iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456

 7011 13:54:36.579525  ==

 7012 13:54:36.582063  Dram Type= 6, Freq= 0, CH_1, rank 1

 7013 13:54:36.588849  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 7014 13:54:36.589432  ==

 7015 13:54:36.589804  DQS Delay:

 7016 13:54:36.591704  DQS0 = 32, DQS1 = 36

 7017 13:54:36.592175  DQM Delay:

 7018 13:54:36.595548  DQM0 = 12, DQM1 = 12

 7019 13:54:36.596123  DQ Delay:

 7020 13:54:36.598728  DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8

 7021 13:54:36.602049  DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8

 7022 13:54:36.602644  DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8

 7023 13:54:36.608801  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24

 7024 13:54:36.609467  

 7025 13:54:36.609851  

 7026 13:54:36.615193  [DQSOSCAuto] RK1, (LSB)MR18= 0xa64f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps

 7027 13:54:36.618427  CH1 RK1: MR19=C0C, MR18=A64F

 7028 13:54:36.625095  CH1_RK1: MR19=0xC0C, MR18=0xA64F, DQSOSC=389, MR23=63, INC=390, DEC=260

 7029 13:54:36.628608  [RxdqsGatingPostProcess] freq 400

 7030 13:54:36.631977  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 7031 13:54:36.635032  best DQS0 dly(2T, 0.5T) = (0, 10)

 7032 13:54:36.638329  best DQS1 dly(2T, 0.5T) = (0, 10)

 7033 13:54:36.641625  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7034 13:54:36.644980  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7035 13:54:36.648300  best DQS0 dly(2T, 0.5T) = (0, 10)

 7036 13:54:36.651916  best DQS1 dly(2T, 0.5T) = (0, 10)

 7037 13:54:36.655205  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7038 13:54:36.658722  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7039 13:54:36.662131  Pre-setting of DQS Precalculation

 7040 13:54:36.665134  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 7041 13:54:36.672166  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 7042 13:54:36.681895  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 7043 13:54:36.682510  

 7044 13:54:36.682880  

 7045 13:54:36.685142  [Calibration Summary] 800 Mbps

 7046 13:54:36.685610  CH 0, Rank 0

 7047 13:54:36.688883  SW Impedance     : PASS

 7048 13:54:36.689461  DUTY Scan        : NO K

 7049 13:54:36.691859  ZQ Calibration   : PASS

 7050 13:54:36.692330  Jitter Meter     : NO K

 7051 13:54:36.695518  CBT Training     : PASS

 7052 13:54:36.698575  Write leveling   : PASS

 7053 13:54:36.699047  RX DQS gating    : PASS

 7054 13:54:36.701682  RX DQ/DQS(RDDQC) : PASS

 7055 13:54:36.705245  TX DQ/DQS        : PASS

 7056 13:54:36.705819  RX DATLAT        : PASS

 7057 13:54:36.708745  RX DQ/DQS(Engine): PASS

 7058 13:54:36.711640  TX OE            : NO K

 7059 13:54:36.712116  All Pass.

 7060 13:54:36.712484  

 7061 13:54:36.712823  CH 0, Rank 1

 7062 13:54:36.714847  SW Impedance     : PASS

 7063 13:54:36.718611  DUTY Scan        : NO K

 7064 13:54:36.719193  ZQ Calibration   : PASS

 7065 13:54:36.721676  Jitter Meter     : NO K

 7066 13:54:36.725174  CBT Training     : PASS

 7067 13:54:36.725750  Write leveling   : NO K

 7068 13:54:36.728384  RX DQS gating    : PASS

 7069 13:54:36.732053  RX DQ/DQS(RDDQC) : PASS

 7070 13:54:36.732525  TX DQ/DQS        : PASS

 7071 13:54:36.734882  RX DATLAT        : PASS

 7072 13:54:36.735357  RX DQ/DQS(Engine): PASS

 7073 13:54:36.738433  TX OE            : NO K

 7074 13:54:36.739050  All Pass.

 7075 13:54:36.739420  

 7076 13:54:36.741710  CH 1, Rank 0

 7077 13:54:36.742312  SW Impedance     : PASS

 7078 13:54:36.745438  DUTY Scan        : NO K

 7079 13:54:36.748429  ZQ Calibration   : PASS

 7080 13:54:36.749078  Jitter Meter     : NO K

 7081 13:54:36.751426  CBT Training     : PASS

 7082 13:54:36.754847  Write leveling   : PASS

 7083 13:54:36.755320  RX DQS gating    : PASS

 7084 13:54:36.758233  RX DQ/DQS(RDDQC) : PASS

 7085 13:54:36.761330  TX DQ/DQS        : PASS

 7086 13:54:36.761809  RX DATLAT        : PASS

 7087 13:54:36.764749  RX DQ/DQS(Engine): PASS

 7088 13:54:36.768442  TX OE            : NO K

 7089 13:54:36.769071  All Pass.

 7090 13:54:36.769454  

 7091 13:54:36.769804  CH 1, Rank 1

 7092 13:54:36.771212  SW Impedance     : PASS

 7093 13:54:36.774496  DUTY Scan        : NO K

 7094 13:54:36.774970  ZQ Calibration   : PASS

 7095 13:54:36.777915  Jitter Meter     : NO K

 7096 13:54:36.781185  CBT Training     : PASS

 7097 13:54:36.781659  Write leveling   : NO K

 7098 13:54:36.784458  RX DQS gating    : PASS

 7099 13:54:36.787588  RX DQ/DQS(RDDQC) : PASS

 7100 13:54:36.788017  TX DQ/DQS        : PASS

 7101 13:54:36.791029  RX DATLAT        : PASS

 7102 13:54:36.794615  RX DQ/DQS(Engine): PASS

 7103 13:54:36.795045  TX OE            : NO K

 7104 13:54:36.795390  All Pass.

 7105 13:54:36.797826  

 7106 13:54:36.798288  DramC Write-DBI off

 7107 13:54:36.801602  	PER_BANK_REFRESH: Hybrid Mode

 7108 13:54:36.802173  TX_TRACKING: ON

 7109 13:54:36.811314  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7110 13:54:36.814772  [FAST_K] Save calibration result to emmc

 7111 13:54:36.818299  dramc_set_vcore_voltage set vcore to 725000

 7112 13:54:36.821507  Read voltage for 1600, 0

 7113 13:54:36.822099  Vio18 = 0

 7114 13:54:36.824530  Vcore = 725000

 7115 13:54:36.825109  Vdram = 0

 7116 13:54:36.825498  Vddq = 0

 7117 13:54:36.825932  Vmddr = 0

 7118 13:54:36.831176  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7119 13:54:36.837541  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7120 13:54:36.838133  MEM_TYPE=3, freq_sel=13

 7121 13:54:36.841324  sv_algorithm_assistance_LP4_3733 

 7122 13:54:36.844417  ============ PULL DRAM RESETB DOWN ============

 7123 13:54:36.850895  ========== PULL DRAM RESETB DOWN end =========

 7124 13:54:36.854449  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7125 13:54:36.857488  =================================== 

 7126 13:54:36.861140  LPDDR4 DRAM CONFIGURATION

 7127 13:54:36.864481  =================================== 

 7128 13:54:36.865058  EX_ROW_EN[0]    = 0x0

 7129 13:54:36.868185  EX_ROW_EN[1]    = 0x0

 7130 13:54:36.868761  LP4Y_EN      = 0x0

 7131 13:54:36.870966  WORK_FSP     = 0x1

 7132 13:54:36.871443  WL           = 0x5

 7133 13:54:36.874517  RL           = 0x5

 7134 13:54:36.877688  BL           = 0x2

 7135 13:54:36.878209  RPST         = 0x0

 7136 13:54:36.881067  RD_PRE       = 0x0

 7137 13:54:36.881596  WR_PRE       = 0x1

 7138 13:54:36.884234  WR_PST       = 0x1

 7139 13:54:36.884904  DBI_WR       = 0x0

 7140 13:54:36.887685  DBI_RD       = 0x0

 7141 13:54:36.888158  OTF          = 0x1

 7142 13:54:36.890899  =================================== 

 7143 13:54:36.894566  =================================== 

 7144 13:54:36.895041  ANA top config

 7145 13:54:36.897768  =================================== 

 7146 13:54:36.900814  DLL_ASYNC_EN            =  0

 7147 13:54:36.904547  ALL_SLAVE_EN            =  0

 7148 13:54:36.907620  NEW_RANK_MODE           =  1

 7149 13:54:36.910912  DLL_IDLE_MODE           =  1

 7150 13:54:36.911384  LP45_APHY_COMB_EN       =  1

 7151 13:54:36.914104  TX_ODT_DIS              =  0

 7152 13:54:36.917727  NEW_8X_MODE             =  1

 7153 13:54:36.920951  =================================== 

 7154 13:54:36.924102  =================================== 

 7155 13:54:36.927320  data_rate                  = 3200

 7156 13:54:36.931114  CKR                        = 1

 7157 13:54:36.931545  DQ_P2S_RATIO               = 8

 7158 13:54:36.934088  =================================== 

 7159 13:54:36.937639  CA_P2S_RATIO               = 8

 7160 13:54:36.941163  DQ_CA_OPEN                 = 0

 7161 13:54:36.944291  DQ_SEMI_OPEN               = 0

 7162 13:54:36.947493  CA_SEMI_OPEN               = 0

 7163 13:54:36.951018  CA_FULL_RATE               = 0

 7164 13:54:36.951448  DQ_CKDIV4_EN               = 0

 7165 13:54:36.953749  CA_CKDIV4_EN               = 0

 7166 13:54:36.957458  CA_PREDIV_EN               = 0

 7167 13:54:36.960677  PH8_DLY                    = 12

 7168 13:54:36.963917  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7169 13:54:36.967255  DQ_AAMCK_DIV               = 4

 7170 13:54:36.970279  CA_AAMCK_DIV               = 4

 7171 13:54:36.970749  CA_ADMCK_DIV               = 4

 7172 13:54:36.973634  DQ_TRACK_CA_EN             = 0

 7173 13:54:36.977443  CA_PICK                    = 1600

 7174 13:54:36.980464  CA_MCKIO                   = 1600

 7175 13:54:36.983808  MCKIO_SEMI                 = 0

 7176 13:54:36.986984  PLL_FREQ                   = 3068

 7177 13:54:36.990680  DQ_UI_PI_RATIO             = 32

 7178 13:54:36.991257  CA_UI_PI_RATIO             = 0

 7179 13:54:36.993553  =================================== 

 7180 13:54:36.997111  =================================== 

 7181 13:54:37.000201  memory_type:LPDDR4         

 7182 13:54:37.003797  GP_NUM     : 10       

 7183 13:54:37.004464  SRAM_EN    : 1       

 7184 13:54:37.006849  MD32_EN    : 0       

 7185 13:54:37.010757  =================================== 

 7186 13:54:37.013350  [ANA_INIT] >>>>>>>>>>>>>> 

 7187 13:54:37.016732  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7188 13:54:37.020505  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7189 13:54:37.023405  =================================== 

 7190 13:54:37.023879  data_rate = 3200,PCW = 0X7600

 7191 13:54:37.026589  =================================== 

 7192 13:54:37.029997  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7193 13:54:37.036723  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7194 13:54:37.043209  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7195 13:54:37.046818  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7196 13:54:37.050082  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7197 13:54:37.053259  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7198 13:54:37.056575  [ANA_INIT] flow start 

 7199 13:54:37.060078  [ANA_INIT] PLL >>>>>>>> 

 7200 13:54:37.060650  [ANA_INIT] PLL <<<<<<<< 

 7201 13:54:37.063068  [ANA_INIT] MIDPI >>>>>>>> 

 7202 13:54:37.066476  [ANA_INIT] MIDPI <<<<<<<< 

 7203 13:54:37.066953  [ANA_INIT] DLL >>>>>>>> 

 7204 13:54:37.069764  [ANA_INIT] DLL <<<<<<<< 

 7205 13:54:37.073455  [ANA_INIT] flow end 

 7206 13:54:37.076499  ============ LP4 DIFF to SE enter ============

 7207 13:54:37.079593  ============ LP4 DIFF to SE exit  ============

 7208 13:54:37.083158  [ANA_INIT] <<<<<<<<<<<<< 

 7209 13:54:37.086443  [Flow] Enable top DCM control >>>>> 

 7210 13:54:37.089804  [Flow] Enable top DCM control <<<<< 

 7211 13:54:37.093055  Enable DLL master slave shuffle 

 7212 13:54:37.096463  ============================================================== 

 7213 13:54:37.099580  Gating Mode config

 7214 13:54:37.106647  ============================================================== 

 7215 13:54:37.107216  Config description: 

 7216 13:54:37.116698  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7217 13:54:37.123074  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7218 13:54:37.126664  SELPH_MODE            0: By rank         1: By Phase 

 7219 13:54:37.133343  ============================================================== 

 7220 13:54:37.136600  GAT_TRACK_EN                 =  1

 7221 13:54:37.139783  RX_GATING_MODE               =  2

 7222 13:54:37.142967  RX_GATING_TRACK_MODE         =  2

 7223 13:54:37.146342  SELPH_MODE                   =  1

 7224 13:54:37.149796  PICG_EARLY_EN                =  1

 7225 13:54:37.153171  VALID_LAT_VALUE              =  1

 7226 13:54:37.156298  ============================================================== 

 7227 13:54:37.159394  Enter into Gating configuration >>>> 

 7228 13:54:37.163034  Exit from Gating configuration <<<< 

 7229 13:54:37.165845  Enter into  DVFS_PRE_config >>>>> 

 7230 13:54:37.176303  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7231 13:54:37.179198  Exit from  DVFS_PRE_config <<<<< 

 7232 13:54:37.182891  Enter into PICG configuration >>>> 

 7233 13:54:37.186350  Exit from PICG configuration <<<< 

 7234 13:54:37.189294  [RX_INPUT] configuration >>>>> 

 7235 13:54:37.192852  [RX_INPUT] configuration <<<<< 

 7236 13:54:37.199436  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7237 13:54:37.202863  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7238 13:54:37.209630  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7239 13:54:37.215925  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7240 13:54:37.223015  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7241 13:54:37.229448  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7242 13:54:37.232784  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7243 13:54:37.235934  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7244 13:54:37.239014  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7245 13:54:37.245841  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7246 13:54:37.249504  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7247 13:54:37.252727  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7248 13:54:37.256136  =================================== 

 7249 13:54:37.258855  LPDDR4 DRAM CONFIGURATION

 7250 13:54:37.262383  =================================== 

 7251 13:54:37.262968  EX_ROW_EN[0]    = 0x0

 7252 13:54:37.265762  EX_ROW_EN[1]    = 0x0

 7253 13:54:37.269030  LP4Y_EN      = 0x0

 7254 13:54:37.269611  WORK_FSP     = 0x1

 7255 13:54:37.272557  WL           = 0x5

 7256 13:54:37.273116  RL           = 0x5

 7257 13:54:37.275663  BL           = 0x2

 7258 13:54:37.276136  RPST         = 0x0

 7259 13:54:37.278721  RD_PRE       = 0x0

 7260 13:54:37.279359  WR_PRE       = 0x1

 7261 13:54:37.282082  WR_PST       = 0x1

 7262 13:54:37.282568  DBI_WR       = 0x0

 7263 13:54:37.285254  DBI_RD       = 0x0

 7264 13:54:37.285920  OTF          = 0x1

 7265 13:54:37.288637  =================================== 

 7266 13:54:37.292377  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7267 13:54:37.298939  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7268 13:54:37.302406  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7269 13:54:37.305439  =================================== 

 7270 13:54:37.308541  LPDDR4 DRAM CONFIGURATION

 7271 13:54:37.312260  =================================== 

 7272 13:54:37.312863  EX_ROW_EN[0]    = 0x10

 7273 13:54:37.315567  EX_ROW_EN[1]    = 0x0

 7274 13:54:37.316049  LP4Y_EN      = 0x0

 7275 13:54:37.318816  WORK_FSP     = 0x1

 7276 13:54:37.322057  WL           = 0x5

 7277 13:54:37.322530  RL           = 0x5

 7278 13:54:37.325248  BL           = 0x2

 7279 13:54:37.325720  RPST         = 0x0

 7280 13:54:37.328511  RD_PRE       = 0x0

 7281 13:54:37.329033  WR_PRE       = 0x1

 7282 13:54:37.332140  WR_PST       = 0x1

 7283 13:54:37.332613  DBI_WR       = 0x0

 7284 13:54:37.335440  DBI_RD       = 0x0

 7285 13:54:37.335946  OTF          = 0x1

 7286 13:54:37.338708  =================================== 

 7287 13:54:37.345500  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7288 13:54:37.346127  ==

 7289 13:54:37.348434  Dram Type= 6, Freq= 0, CH_0, rank 0

 7290 13:54:37.352272  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7291 13:54:37.352844  ==

 7292 13:54:37.355564  [Duty_Offset_Calibration]

 7293 13:54:37.358788  	B0:2	B1:0	CA:1

 7294 13:54:37.359263  

 7295 13:54:37.361680  [DutyScan_Calibration_Flow] k_type=0

 7296 13:54:37.370626  

 7297 13:54:37.371213  ==CLK 0==

 7298 13:54:37.373728  Final CLK duty delay cell = 0

 7299 13:54:37.377360  [0] MAX Duty = 5187%(X100), DQS PI = 20

 7300 13:54:37.380386  [0] MIN Duty = 5031%(X100), DQS PI = 0

 7301 13:54:37.380863  [0] AVG Duty = 5109%(X100)

 7302 13:54:37.381275  

 7303 13:54:37.383640  CH0 CLK Duty spec in!! Max-Min= 156%

 7304 13:54:37.390414  [DutyScan_Calibration_Flow] ====Done====

 7305 13:54:37.390985  

 7306 13:54:37.393399  [DutyScan_Calibration_Flow] k_type=1

 7307 13:54:37.409309  

 7308 13:54:37.409844  ==DQS 0 ==

 7309 13:54:37.412447  Final DQS duty delay cell = 0

 7310 13:54:37.416135  [0] MAX Duty = 5249%(X100), DQS PI = 32

 7311 13:54:37.419248  [0] MIN Duty = 4969%(X100), DQS PI = 0

 7312 13:54:37.422950  [0] AVG Duty = 5109%(X100)

 7313 13:54:37.423424  

 7314 13:54:37.423792  ==DQS 1 ==

 7315 13:54:37.426101  Final DQS duty delay cell = -4

 7316 13:54:37.429218  [-4] MAX Duty = 5125%(X100), DQS PI = 28

 7317 13:54:37.432575  [-4] MIN Duty = 4844%(X100), DQS PI = 6

 7318 13:54:37.436004  [-4] AVG Duty = 4984%(X100)

 7319 13:54:37.436477  

 7320 13:54:37.439370  CH0 DQS 0 Duty spec in!! Max-Min= 280%

 7321 13:54:37.440039  

 7322 13:54:37.442778  CH0 DQS 1 Duty spec in!! Max-Min= 281%

 7323 13:54:37.445889  [DutyScan_Calibration_Flow] ====Done====

 7324 13:54:37.446356  

 7325 13:54:37.449005  [DutyScan_Calibration_Flow] k_type=3

 7326 13:54:37.466870  

 7327 13:54:37.467438  ==DQM 0 ==

 7328 13:54:37.470221  Final DQM duty delay cell = 0

 7329 13:54:37.473692  [0] MAX Duty = 5093%(X100), DQS PI = 26

 7330 13:54:37.476895  [0] MIN Duty = 4813%(X100), DQS PI = 50

 7331 13:54:37.480252  [0] AVG Duty = 4953%(X100)

 7332 13:54:37.480727  

 7333 13:54:37.481098  ==DQM 1 ==

 7334 13:54:37.483132  Final DQM duty delay cell = 0

 7335 13:54:37.486959  [0] MAX Duty = 5249%(X100), DQS PI = 30

 7336 13:54:37.490180  [0] MIN Duty = 5000%(X100), DQS PI = 20

 7337 13:54:37.493080  [0] AVG Duty = 5124%(X100)

 7338 13:54:37.493555  

 7339 13:54:37.497211  CH0 DQM 0 Duty spec in!! Max-Min= 280%

 7340 13:54:37.497785  

 7341 13:54:37.500179  CH0 DQM 1 Duty spec in!! Max-Min= 249%

 7342 13:54:37.503399  [DutyScan_Calibration_Flow] ====Done====

 7343 13:54:37.503978  

 7344 13:54:37.506611  [DutyScan_Calibration_Flow] k_type=2

 7345 13:54:37.524445  

 7346 13:54:37.525015  ==DQ 0 ==

 7347 13:54:37.527161  Final DQ duty delay cell = 0

 7348 13:54:37.530748  [0] MAX Duty = 5124%(X100), DQS PI = 34

 7349 13:54:37.533756  [0] MIN Duty = 5000%(X100), DQS PI = 0

 7350 13:54:37.534279  [0] AVG Duty = 5062%(X100)

 7351 13:54:37.534655  

 7352 13:54:37.537248  ==DQ 1 ==

 7353 13:54:37.540432  Final DQ duty delay cell = 0

 7354 13:54:37.543984  [0] MAX Duty = 4969%(X100), DQS PI = 28

 7355 13:54:37.547354  [0] MIN Duty = 4875%(X100), DQS PI = 12

 7356 13:54:37.547828  [0] AVG Duty = 4922%(X100)

 7357 13:54:37.548199  

 7358 13:54:37.550848  CH0 DQ 0 Duty spec in!! Max-Min= 124%

 7359 13:54:37.554051  

 7360 13:54:37.554507  CH0 DQ 1 Duty spec in!! Max-Min= 94%

 7361 13:54:37.560666  [DutyScan_Calibration_Flow] ====Done====

 7362 13:54:37.561128  ==

 7363 13:54:37.563790  Dram Type= 6, Freq= 0, CH_1, rank 0

 7364 13:54:37.567378  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7365 13:54:37.567940  ==

 7366 13:54:37.570576  [Duty_Offset_Calibration]

 7367 13:54:37.570992  	B0:0	B1:-1	CA:2

 7368 13:54:37.571318  

 7369 13:54:37.573690  [DutyScan_Calibration_Flow] k_type=0

 7370 13:54:37.584168  

 7371 13:54:37.584430  ==CLK 0==

 7372 13:54:37.587648  Final CLK duty delay cell = 0

 7373 13:54:37.590640  [0] MAX Duty = 5156%(X100), DQS PI = 10

 7374 13:54:37.593963  [0] MIN Duty = 4938%(X100), DQS PI = 44

 7375 13:54:37.594203  [0] AVG Duty = 5047%(X100)

 7376 13:54:37.594351  

 7377 13:54:37.597754  CH1 CLK Duty spec in!! Max-Min= 218%

 7378 13:54:37.604625  [DutyScan_Calibration_Flow] ====Done====

 7379 13:54:37.604899  

 7380 13:54:37.607473  [DutyScan_Calibration_Flow] k_type=1

 7381 13:54:37.624347  

 7382 13:54:37.624920  ==DQS 0 ==

 7383 13:54:37.627506  Final DQS duty delay cell = 0

 7384 13:54:37.630789  [0] MAX Duty = 5124%(X100), DQS PI = 26

 7385 13:54:37.633735  [0] MIN Duty = 4969%(X100), DQS PI = 16

 7386 13:54:37.637204  [0] AVG Duty = 5046%(X100)

 7387 13:54:37.637758  

 7388 13:54:37.638178  ==DQS 1 ==

 7389 13:54:37.640933  Final DQS duty delay cell = 0

 7390 13:54:37.644097  [0] MAX Duty = 5187%(X100), DQS PI = 0

 7391 13:54:37.647405  [0] MIN Duty = 4844%(X100), DQS PI = 34

 7392 13:54:37.650528  [0] AVG Duty = 5015%(X100)

 7393 13:54:37.651091  

 7394 13:54:37.653718  CH1 DQS 0 Duty spec in!! Max-Min= 155%

 7395 13:54:37.654316  

 7396 13:54:37.657438  CH1 DQS 1 Duty spec in!! Max-Min= 343%

 7397 13:54:37.660499  [DutyScan_Calibration_Flow] ====Done====

 7398 13:54:37.661058  

 7399 13:54:37.663793  [DutyScan_Calibration_Flow] k_type=3

 7400 13:54:37.681841  

 7401 13:54:37.682427  ==DQM 0 ==

 7402 13:54:37.684951  Final DQM duty delay cell = 4

 7403 13:54:37.688055  [4] MAX Duty = 5125%(X100), DQS PI = 8

 7404 13:54:37.691338  [4] MIN Duty = 5000%(X100), DQS PI = 32

 7405 13:54:37.691941  [4] AVG Duty = 5062%(X100)

 7406 13:54:37.694558  

 7407 13:54:37.695148  ==DQM 1 ==

 7408 13:54:37.698382  Final DQM duty delay cell = 0

 7409 13:54:37.701460  [0] MAX Duty = 5281%(X100), DQS PI = 58

 7410 13:54:37.704582  [0] MIN Duty = 4876%(X100), DQS PI = 34

 7411 13:54:37.708148  [0] AVG Duty = 5078%(X100)

 7412 13:54:37.708672  

 7413 13:54:37.711492  CH1 DQM 0 Duty spec in!! Max-Min= 125%

 7414 13:54:37.712129  

 7415 13:54:37.714592  CH1 DQM 1 Duty spec in!! Max-Min= 405%

 7416 13:54:37.717896  [DutyScan_Calibration_Flow] ====Done====

 7417 13:54:37.718389  

 7418 13:54:37.721886  [DutyScan_Calibration_Flow] k_type=2

 7419 13:54:37.738480  

 7420 13:54:37.739108  ==DQ 0 ==

 7421 13:54:37.741788  Final DQ duty delay cell = 0

 7422 13:54:37.744730  [0] MAX Duty = 5093%(X100), DQS PI = 20

 7423 13:54:37.748157  [0] MIN Duty = 4969%(X100), DQS PI = 46

 7424 13:54:37.751933  [0] AVG Duty = 5031%(X100)

 7425 13:54:37.752487  

 7426 13:54:37.753014  ==DQ 1 ==

 7427 13:54:37.754558  Final DQ duty delay cell = 0

 7428 13:54:37.758150  [0] MAX Duty = 5062%(X100), DQS PI = 2

 7429 13:54:37.761666  [0] MIN Duty = 4813%(X100), DQS PI = 34

 7430 13:54:37.762246  [0] AVG Duty = 4937%(X100)

 7431 13:54:37.764625  

 7432 13:54:37.768238  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 7433 13:54:37.768800  

 7434 13:54:37.771502  CH1 DQ 1 Duty spec in!! Max-Min= 249%

 7435 13:54:37.774834  [DutyScan_Calibration_Flow] ====Done====

 7436 13:54:37.778233  nWR fixed to 30

 7437 13:54:37.778792  [ModeRegInit_LP4] CH0 RK0

 7438 13:54:37.781918  [ModeRegInit_LP4] CH0 RK1

 7439 13:54:37.785096  [ModeRegInit_LP4] CH1 RK0

 7440 13:54:37.788349  [ModeRegInit_LP4] CH1 RK1

 7441 13:54:37.788900  match AC timing 5

 7442 13:54:37.794741  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7443 13:54:37.797637  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7444 13:54:37.801408  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7445 13:54:37.808405  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7446 13:54:37.811209  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7447 13:54:37.811678  [MiockJmeterHQA]

 7448 13:54:37.812040  

 7449 13:54:37.814837  [DramcMiockJmeter] u1RxGatingPI = 0

 7450 13:54:37.818152  0 : 4253, 4026

 7451 13:54:37.818624  4 : 4365, 4140

 7452 13:54:37.818995  8 : 4252, 4026

 7453 13:54:37.821321  12 : 4253, 4027

 7454 13:54:37.821810  16 : 4255, 4029

 7455 13:54:37.824225  20 : 4252, 4026

 7456 13:54:37.824697  24 : 4255, 4029

 7457 13:54:37.828397  28 : 4253, 4027

 7458 13:54:37.829033  32 : 4257, 4029

 7459 13:54:37.831109  36 : 4365, 4140

 7460 13:54:37.831635  40 : 4252, 4027

 7461 13:54:37.832058  44 : 4255, 4029

 7462 13:54:37.834566  48 : 4253, 4027

 7463 13:54:37.835038  52 : 4363, 4137

 7464 13:54:37.837809  56 : 4252, 4027

 7465 13:54:37.838309  60 : 4363, 4137

 7466 13:54:37.841302  64 : 4252, 4029

 7467 13:54:37.841789  68 : 4363, 4140

 7468 13:54:37.844621  72 : 4249, 4027

 7469 13:54:37.845097  76 : 4250, 4027

 7470 13:54:37.845474  80 : 4360, 4137

 7471 13:54:37.847924  84 : 4250, 4026

 7472 13:54:37.848398  88 : 4360, 3690

 7473 13:54:37.851270  92 : 4363, 0

 7474 13:54:37.851746  96 : 4250, 0

 7475 13:54:37.852113  100 : 4360, 0

 7476 13:54:37.854414  104 : 4252, 0

 7477 13:54:37.854887  108 : 4250, 0

 7478 13:54:37.857768  112 : 4360, 0

 7479 13:54:37.858266  116 : 4250, 0

 7480 13:54:37.858644  120 : 4252, 0

 7481 13:54:37.861255  124 : 4250, 0

 7482 13:54:37.861729  128 : 4255, 0

 7483 13:54:37.864337  132 : 4363, 0

 7484 13:54:37.864770  136 : 4360, 0

 7485 13:54:37.865107  140 : 4250, 0

 7486 13:54:37.868197  144 : 4252, 0

 7487 13:54:37.868738  148 : 4362, 0

 7488 13:54:37.869083  152 : 4250, 0

 7489 13:54:37.871382  156 : 4250, 0

 7490 13:54:37.871923  160 : 4252, 0

 7491 13:54:37.874678  164 : 4250, 0

 7492 13:54:37.875220  168 : 4252, 0

 7493 13:54:37.875566  172 : 4250, 0

 7494 13:54:37.878021  176 : 4249, 0

 7495 13:54:37.878558  180 : 4255, 0

 7496 13:54:37.881059  184 : 4361, 0

 7497 13:54:37.881490  188 : 4360, 0

 7498 13:54:37.881830  192 : 4250, 0

 7499 13:54:37.884955  196 : 4250, 0

 7500 13:54:37.885510  200 : 4361, 17

 7501 13:54:37.887943  204 : 4250, 2667

 7502 13:54:37.888374  208 : 4253, 4029

 7503 13:54:37.891169  212 : 4363, 4140

 7504 13:54:37.891602  216 : 4361, 4137

 7505 13:54:37.891946  220 : 4247, 4025

 7506 13:54:37.894678  224 : 4250, 4027

 7507 13:54:37.895108  228 : 4363, 4140

 7508 13:54:37.897880  232 : 4360, 4137

 7509 13:54:37.898332  236 : 4250, 4027

 7510 13:54:37.901588  240 : 4253, 4029

 7511 13:54:37.902167  244 : 4252, 4030

 7512 13:54:37.904551  248 : 4251, 4027

 7513 13:54:37.905094  252 : 4250, 4027

 7514 13:54:37.907865  256 : 4253, 4029

 7515 13:54:37.908402  260 : 4252, 4030

 7516 13:54:37.911470  264 : 4363, 4140

 7517 13:54:37.912008  268 : 4250, 4026

 7518 13:54:37.914605  272 : 4250, 4027

 7519 13:54:37.915036  276 : 4249, 4027

 7520 13:54:37.915379  280 : 4363, 4140

 7521 13:54:37.917638  284 : 4361, 4137

 7522 13:54:37.918090  288 : 4247, 4025

 7523 13:54:37.921528  292 : 4363, 4140

 7524 13:54:37.922116  296 : 4252, 4030

 7525 13:54:37.924386  300 : 4249, 4027

 7526 13:54:37.924819  304 : 4250, 4027

 7527 13:54:37.927914  308 : 4253, 4029

 7528 13:54:37.928367  312 : 4252, 3817

 7529 13:54:37.931153  316 : 4363, 1785

 7530 13:54:37.931585  

 7531 13:54:37.931926  	MIOCK jitter meter	ch=0

 7532 13:54:37.932246  

 7533 13:54:37.934111  1T = (316-92) = 224 dly cells

 7534 13:54:37.940896  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps

 7535 13:54:37.941330  ==

 7536 13:54:37.943971  Dram Type= 6, Freq= 0, CH_0, rank 0

 7537 13:54:37.947136  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7538 13:54:37.947568  ==

 7539 13:54:37.953781  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7540 13:54:37.957161  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7541 13:54:37.963741  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7542 13:54:37.966916  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7543 13:54:37.977281  [CA 0] Center 43 (13~73) winsize 61

 7544 13:54:37.980667  [CA 1] Center 43 (13~73) winsize 61

 7545 13:54:37.984305  [CA 2] Center 38 (8~68) winsize 61

 7546 13:54:37.987563  [CA 3] Center 37 (8~67) winsize 60

 7547 13:54:37.990521  [CA 4] Center 37 (7~67) winsize 61

 7548 13:54:37.993780  [CA 5] Center 35 (5~66) winsize 62

 7549 13:54:37.994272  

 7550 13:54:37.997219  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7551 13:54:37.997790  

 7552 13:54:38.000277  [CATrainingPosCal] consider 1 rank data

 7553 13:54:38.004165  u2DelayCellTimex100 = 290/100 ps

 7554 13:54:38.010590  CA0 delay=43 (13~73),Diff = 8 PI (26 cell)

 7555 13:54:38.013935  CA1 delay=43 (13~73),Diff = 8 PI (26 cell)

 7556 13:54:38.017395  CA2 delay=38 (8~68),Diff = 3 PI (10 cell)

 7557 13:54:38.020257  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7558 13:54:38.023503  CA4 delay=37 (7~67),Diff = 2 PI (6 cell)

 7559 13:54:38.027020  CA5 delay=35 (5~66),Diff = 0 PI (0 cell)

 7560 13:54:38.027594  

 7561 13:54:38.030347  CA PerBit enable=1, Macro0, CA PI delay=35

 7562 13:54:38.030815  

 7563 13:54:38.033917  [CBTSetCACLKResult] CA Dly = 35

 7564 13:54:38.037290  CS Dly: 10 (0~41)

 7565 13:54:38.040371  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7566 13:54:38.043327  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7567 13:54:38.043796  ==

 7568 13:54:38.047138  Dram Type= 6, Freq= 0, CH_0, rank 1

 7569 13:54:38.053576  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7570 13:54:38.054199  ==

 7571 13:54:38.056666  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7572 13:54:38.060213  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7573 13:54:38.066558  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7574 13:54:38.072913  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7575 13:54:38.080935  [CA 0] Center 43 (13~73) winsize 61

 7576 13:54:38.083918  [CA 1] Center 43 (13~73) winsize 61

 7577 13:54:38.087402  [CA 2] Center 37 (8~67) winsize 60

 7578 13:54:38.090660  [CA 3] Center 38 (9~68) winsize 60

 7579 13:54:38.093935  [CA 4] Center 37 (7~67) winsize 61

 7580 13:54:38.097306  [CA 5] Center 36 (7~66) winsize 60

 7581 13:54:38.097780  

 7582 13:54:38.100602  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7583 13:54:38.101078  

 7584 13:54:38.103857  [CATrainingPosCal] consider 2 rank data

 7585 13:54:38.107455  u2DelayCellTimex100 = 290/100 ps

 7586 13:54:38.110530  CA0 delay=43 (13~73),Diff = 7 PI (23 cell)

 7587 13:54:38.117237  CA1 delay=43 (13~73),Diff = 7 PI (23 cell)

 7588 13:54:38.120383  CA2 delay=37 (8~67),Diff = 1 PI (3 cell)

 7589 13:54:38.123927  CA3 delay=38 (9~67),Diff = 2 PI (6 cell)

 7590 13:54:38.127030  CA4 delay=37 (7~67),Diff = 1 PI (3 cell)

 7591 13:54:38.130596  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 7592 13:54:38.131030  

 7593 13:54:38.134015  CA PerBit enable=1, Macro0, CA PI delay=36

 7594 13:54:38.134560  

 7595 13:54:38.137304  [CBTSetCACLKResult] CA Dly = 36

 7596 13:54:38.140583  CS Dly: 11 (0~43)

 7597 13:54:38.143829  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7598 13:54:38.147045  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7599 13:54:38.147470  

 7600 13:54:38.150377  ----->DramcWriteLeveling(PI) begin...

 7601 13:54:38.150809  ==

 7602 13:54:38.154013  Dram Type= 6, Freq= 0, CH_0, rank 0

 7603 13:54:38.157044  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7604 13:54:38.160684  ==

 7605 13:54:38.161154  Write leveling (Byte 0): 36 => 36

 7606 13:54:38.163683  Write leveling (Byte 1): 29 => 29

 7607 13:54:38.167510  DramcWriteLeveling(PI) end<-----

 7608 13:54:38.168090  

 7609 13:54:38.168462  ==

 7610 13:54:38.170442  Dram Type= 6, Freq= 0, CH_0, rank 0

 7611 13:54:38.177307  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7612 13:54:38.177896  ==

 7613 13:54:38.178305  [Gating] SW mode calibration

 7614 13:54:38.187386  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7615 13:54:38.190509  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7616 13:54:38.196944   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7617 13:54:38.200983   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7618 13:54:38.203556   1  4  8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)

 7619 13:54:38.207260   1  4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 7620 13:54:38.214088   1  4 16 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)

 7621 13:54:38.217429   1  4 20 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)

 7622 13:54:38.220335   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7623 13:54:38.227096   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7624 13:54:38.230461   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7625 13:54:38.233752   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7626 13:54:38.240356   1  5  8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)

 7627 13:54:38.243397   1  5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)

 7628 13:54:38.246719   1  5 16 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)

 7629 13:54:38.253853   1  5 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)

 7630 13:54:38.257065   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7631 13:54:38.260703   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7632 13:54:38.267100   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7633 13:54:38.270371   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7634 13:54:38.274007   1  6  8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)

 7635 13:54:38.280958   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 7636 13:54:38.284077   1  6 16 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)

 7637 13:54:38.286917   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7638 13:54:38.293971   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7639 13:54:38.297157   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7640 13:54:38.300653   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7641 13:54:38.303863   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7642 13:54:38.310743   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7643 13:54:38.314339   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7644 13:54:38.320509   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7645 13:54:38.323936   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7646 13:54:38.326875   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7647 13:54:38.330324   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7648 13:54:38.336491   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7649 13:54:38.340222   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7650 13:54:38.343359   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7651 13:54:38.350082   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7652 13:54:38.353421   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7653 13:54:38.356643   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7654 13:54:38.363252   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7655 13:54:38.367225   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7656 13:54:38.370359   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7657 13:54:38.376497   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7658 13:54:38.380026   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7659 13:54:38.383397   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 7660 13:54:38.386659  Total UI for P1: 0, mck2ui 16

 7661 13:54:38.390144  best dqsien dly found for B0: ( 1,  9,  8)

 7662 13:54:38.396424   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 7663 13:54:38.399803   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7664 13:54:38.402907  Total UI for P1: 0, mck2ui 16

 7665 13:54:38.406218  best dqsien dly found for B1: ( 1,  9, 18)

 7666 13:54:38.410155  best DQS0 dly(MCK, UI, PI) = (1, 9, 8)

 7667 13:54:38.412820  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 7668 13:54:38.413391  

 7669 13:54:38.416056  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)

 7670 13:54:38.419503  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 7671 13:54:38.422635  [Gating] SW calibration Done

 7672 13:54:38.423127  ==

 7673 13:54:38.426118  Dram Type= 6, Freq= 0, CH_0, rank 0

 7674 13:54:38.432699  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7675 13:54:38.433298  ==

 7676 13:54:38.433847  RX Vref Scan: 0

 7677 13:54:38.434398  

 7678 13:54:38.436023  RX Vref 0 -> 0, step: 1

 7679 13:54:38.436460  

 7680 13:54:38.439270  RX Delay 0 -> 252, step: 8

 7681 13:54:38.442464  iDelay=200, Bit 0, Center 135 (88 ~ 183) 96

 7682 13:54:38.446256  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 7683 13:54:38.449010  iDelay=200, Bit 2, Center 131 (80 ~ 183) 104

 7684 13:54:38.452775  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 7685 13:54:38.459336  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7686 13:54:38.462494  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 7687 13:54:38.465820  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 7688 13:54:38.469258  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 7689 13:54:38.472439  iDelay=200, Bit 8, Center 123 (72 ~ 175) 104

 7690 13:54:38.479013  iDelay=200, Bit 9, Center 119 (72 ~ 167) 96

 7691 13:54:38.482030  iDelay=200, Bit 10, Center 127 (80 ~ 175) 96

 7692 13:54:38.485807  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7693 13:54:38.489117  iDelay=200, Bit 12, Center 131 (80 ~ 183) 104

 7694 13:54:38.492123  iDelay=200, Bit 13, Center 131 (88 ~ 175) 88

 7695 13:54:38.498656  iDelay=200, Bit 14, Center 143 (96 ~ 191) 96

 7696 13:54:38.502217  iDelay=200, Bit 15, Center 135 (88 ~ 183) 96

 7697 13:54:38.502637  ==

 7698 13:54:38.505357  Dram Type= 6, Freq= 0, CH_0, rank 0

 7699 13:54:38.509156  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7700 13:54:38.509691  ==

 7701 13:54:38.512191  DQS Delay:

 7702 13:54:38.512610  DQS0 = 0, DQS1 = 0

 7703 13:54:38.512940  DQM Delay:

 7704 13:54:38.515292  DQM0 = 136, DQM1 = 129

 7705 13:54:38.515738  DQ Delay:

 7706 13:54:38.518492  DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131

 7707 13:54:38.522132  DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =143

 7708 13:54:38.525450  DQ8 =123, DQ9 =119, DQ10 =127, DQ11 =123

 7709 13:54:38.532010  DQ12 =131, DQ13 =131, DQ14 =143, DQ15 =135

 7710 13:54:38.532476  

 7711 13:54:38.532835  

 7712 13:54:38.533172  ==

 7713 13:54:38.535376  Dram Type= 6, Freq= 0, CH_0, rank 0

 7714 13:54:38.538679  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7715 13:54:38.539284  ==

 7716 13:54:38.539625  

 7717 13:54:38.539965  

 7718 13:54:38.542384  	TX Vref Scan disable

 7719 13:54:38.542954   == TX Byte 0 ==

 7720 13:54:38.548314  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 7721 13:54:38.551710  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7722 13:54:38.555382   == TX Byte 1 ==

 7723 13:54:38.558299  Update DQ  dly =984 (3 ,6, 24)  DQ  OEN =(3 ,3)

 7724 13:54:38.561602  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 7725 13:54:38.562210  ==

 7726 13:54:38.565177  Dram Type= 6, Freq= 0, CH_0, rank 0

 7727 13:54:38.568429  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7728 13:54:38.569013  ==

 7729 13:54:38.582965  

 7730 13:54:38.586431  TX Vref early break, caculate TX vref

 7731 13:54:38.589571  TX Vref=16, minBit 5, minWin=22, winSum=374

 7732 13:54:38.592955  TX Vref=18, minBit 4, minWin=23, winSum=385

 7733 13:54:38.596032  TX Vref=20, minBit 12, minWin=23, winSum=397

 7734 13:54:38.599653  TX Vref=22, minBit 4, minWin=24, winSum=406

 7735 13:54:38.602755  TX Vref=24, minBit 0, minWin=25, winSum=413

 7736 13:54:38.609540  TX Vref=26, minBit 0, minWin=26, winSum=428

 7737 13:54:38.612787  TX Vref=28, minBit 12, minWin=25, winSum=430

 7738 13:54:38.616162  TX Vref=30, minBit 0, minWin=25, winSum=426

 7739 13:54:38.619442  TX Vref=32, minBit 0, minWin=25, winSum=416

 7740 13:54:38.622475  TX Vref=34, minBit 6, minWin=24, winSum=403

 7741 13:54:38.629390  [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26

 7742 13:54:38.630161  

 7743 13:54:38.632360  Final TX Range 0 Vref 26

 7744 13:54:38.632990  

 7745 13:54:38.633545  ==

 7746 13:54:38.635887  Dram Type= 6, Freq= 0, CH_0, rank 0

 7747 13:54:38.639068  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7748 13:54:38.639565  ==

 7749 13:54:38.639932  

 7750 13:54:38.640269  

 7751 13:54:38.642541  	TX Vref Scan disable

 7752 13:54:38.649658  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 7753 13:54:38.650281   == TX Byte 0 ==

 7754 13:54:38.653065  u2DelayCellOfst[0]=13 cells (4 PI)

 7755 13:54:38.655894  u2DelayCellOfst[1]=20 cells (6 PI)

 7756 13:54:38.659308  u2DelayCellOfst[2]=13 cells (4 PI)

 7757 13:54:38.662413  u2DelayCellOfst[3]=13 cells (4 PI)

 7758 13:54:38.666334  u2DelayCellOfst[4]=10 cells (3 PI)

 7759 13:54:38.669249  u2DelayCellOfst[5]=0 cells (0 PI)

 7760 13:54:38.672618  u2DelayCellOfst[6]=20 cells (6 PI)

 7761 13:54:38.675929  u2DelayCellOfst[7]=16 cells (5 PI)

 7762 13:54:38.679067  Update DQ  dly =988 (3 ,6, 28)  DQ  OEN =(3 ,3)

 7763 13:54:38.682225  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7764 13:54:38.685868   == TX Byte 1 ==

 7765 13:54:38.689100  u2DelayCellOfst[8]=0 cells (0 PI)

 7766 13:54:38.689570  u2DelayCellOfst[9]=0 cells (0 PI)

 7767 13:54:38.692329  u2DelayCellOfst[10]=6 cells (2 PI)

 7768 13:54:38.695986  u2DelayCellOfst[11]=3 cells (1 PI)

 7769 13:54:38.699115  u2DelayCellOfst[12]=13 cells (4 PI)

 7770 13:54:38.702402  u2DelayCellOfst[13]=10 cells (3 PI)

 7771 13:54:38.705771  u2DelayCellOfst[14]=13 cells (4 PI)

 7772 13:54:38.708875  u2DelayCellOfst[15]=10 cells (3 PI)

 7773 13:54:38.712624  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 7774 13:54:38.719230  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 7775 13:54:38.719794  DramC Write-DBI on

 7776 13:54:38.720168  ==

 7777 13:54:38.722317  Dram Type= 6, Freq= 0, CH_0, rank 0

 7778 13:54:38.728901  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7779 13:54:38.729341  ==

 7780 13:54:38.729679  

 7781 13:54:38.730057  

 7782 13:54:38.730420  	TX Vref Scan disable

 7783 13:54:38.732611   == TX Byte 0 ==

 7784 13:54:38.735537  Update DQM dly =735 (2 ,6, 31)  DQM OEN =(3 ,3)

 7785 13:54:38.738992   == TX Byte 1 ==

 7786 13:54:38.742210  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 7787 13:54:38.746167  DramC Write-DBI off

 7788 13:54:38.746594  

 7789 13:54:38.746980  [DATLAT]

 7790 13:54:38.747313  Freq=1600, CH0 RK0

 7791 13:54:38.747708  

 7792 13:54:38.749275  DATLAT Default: 0xf

 7793 13:54:38.749702  0, 0xFFFF, sum = 0

 7794 13:54:38.752532  1, 0xFFFF, sum = 0

 7795 13:54:38.755613  2, 0xFFFF, sum = 0

 7796 13:54:38.756085  3, 0xFFFF, sum = 0

 7797 13:54:38.758856  4, 0xFFFF, sum = 0

 7798 13:54:38.759305  5, 0xFFFF, sum = 0

 7799 13:54:38.762470  6, 0xFFFF, sum = 0

 7800 13:54:38.762957  7, 0xFFFF, sum = 0

 7801 13:54:38.765686  8, 0xFFFF, sum = 0

 7802 13:54:38.766026  9, 0xFFFF, sum = 0

 7803 13:54:38.769122  10, 0xFFFF, sum = 0

 7804 13:54:38.769429  11, 0xFFFF, sum = 0

 7805 13:54:38.772252  12, 0xFFFF, sum = 0

 7806 13:54:38.772561  13, 0xFFFF, sum = 0

 7807 13:54:38.775517  14, 0x0, sum = 1

 7808 13:54:38.775826  15, 0x0, sum = 2

 7809 13:54:38.778956  16, 0x0, sum = 3

 7810 13:54:38.779321  17, 0x0, sum = 4

 7811 13:54:38.782434  best_step = 15

 7812 13:54:38.782737  

 7813 13:54:38.782972  ==

 7814 13:54:38.785700  Dram Type= 6, Freq= 0, CH_0, rank 0

 7815 13:54:38.788841  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7816 13:54:38.789260  ==

 7817 13:54:38.789504  RX Vref Scan: 1

 7818 13:54:38.792362  

 7819 13:54:38.792665  Set Vref Range= 24 -> 127

 7820 13:54:38.792906  

 7821 13:54:38.795462  RX Vref 24 -> 127, step: 1

 7822 13:54:38.795765  

 7823 13:54:38.798828  RX Delay 27 -> 252, step: 4

 7824 13:54:38.799134  

 7825 13:54:38.802464  Set Vref, RX VrefLevel [Byte0]: 24

 7826 13:54:38.805134                           [Byte1]: 24

 7827 13:54:38.805448  

 7828 13:54:38.808632  Set Vref, RX VrefLevel [Byte0]: 25

 7829 13:54:38.812033                           [Byte1]: 25

 7830 13:54:38.812335  

 7831 13:54:38.815411  Set Vref, RX VrefLevel [Byte0]: 26

 7832 13:54:38.818429                           [Byte1]: 26

 7833 13:54:38.822566  

 7834 13:54:38.822917  Set Vref, RX VrefLevel [Byte0]: 27

 7835 13:54:38.825864                           [Byte1]: 27

 7836 13:54:38.829982  

 7837 13:54:38.830281  Set Vref, RX VrefLevel [Byte0]: 28

 7838 13:54:38.833127                           [Byte1]: 28

 7839 13:54:38.837741  

 7840 13:54:38.838126  Set Vref, RX VrefLevel [Byte0]: 29

 7841 13:54:38.840747                           [Byte1]: 29

 7842 13:54:38.845479  

 7843 13:54:38.845781  Set Vref, RX VrefLevel [Byte0]: 30

 7844 13:54:38.848894                           [Byte1]: 30

 7845 13:54:38.853103  

 7846 13:54:38.853604  Set Vref, RX VrefLevel [Byte0]: 31

 7847 13:54:38.856473                           [Byte1]: 31

 7848 13:54:38.860516  

 7849 13:54:38.861088  Set Vref, RX VrefLevel [Byte0]: 32

 7850 13:54:38.864134                           [Byte1]: 32

 7851 13:54:38.868114  

 7852 13:54:38.868594  Set Vref, RX VrefLevel [Byte0]: 33

 7853 13:54:38.871743                           [Byte1]: 33

 7854 13:54:38.875264  

 7855 13:54:38.875741  Set Vref, RX VrefLevel [Byte0]: 34

 7856 13:54:38.878931                           [Byte1]: 34

 7857 13:54:38.882716  

 7858 13:54:38.883428  Set Vref, RX VrefLevel [Byte0]: 35

 7859 13:54:38.886014                           [Byte1]: 35

 7860 13:54:38.890390  

 7861 13:54:38.890897  Set Vref, RX VrefLevel [Byte0]: 36

 7862 13:54:38.893408                           [Byte1]: 36

 7863 13:54:38.898024  

 7864 13:54:38.898517  Set Vref, RX VrefLevel [Byte0]: 37

 7865 13:54:38.900963                           [Byte1]: 37

 7866 13:54:38.905355  

 7867 13:54:38.905772  Set Vref, RX VrefLevel [Byte0]: 38

 7868 13:54:38.908950                           [Byte1]: 38

 7869 13:54:38.913255  

 7870 13:54:38.913672  Set Vref, RX VrefLevel [Byte0]: 39

 7871 13:54:38.916269                           [Byte1]: 39

 7872 13:54:38.920742  

 7873 13:54:38.921159  Set Vref, RX VrefLevel [Byte0]: 40

 7874 13:54:38.923977                           [Byte1]: 40

 7875 13:54:38.928138  

 7876 13:54:38.928558  Set Vref, RX VrefLevel [Byte0]: 41

 7877 13:54:38.931296                           [Byte1]: 41

 7878 13:54:38.935576  

 7879 13:54:38.936017  Set Vref, RX VrefLevel [Byte0]: 42

 7880 13:54:38.938855                           [Byte1]: 42

 7881 13:54:38.942923  

 7882 13:54:38.943428  Set Vref, RX VrefLevel [Byte0]: 43

 7883 13:54:38.946263                           [Byte1]: 43

 7884 13:54:38.950842  

 7885 13:54:38.951266  Set Vref, RX VrefLevel [Byte0]: 44

 7886 13:54:38.953871                           [Byte1]: 44

 7887 13:54:38.958094  

 7888 13:54:38.958517  Set Vref, RX VrefLevel [Byte0]: 45

 7889 13:54:38.961781                           [Byte1]: 45

 7890 13:54:38.966177  

 7891 13:54:38.966629  Set Vref, RX VrefLevel [Byte0]: 46

 7892 13:54:38.968890                           [Byte1]: 46

 7893 13:54:38.973029  

 7894 13:54:38.976384  Set Vref, RX VrefLevel [Byte0]: 47

 7895 13:54:38.976689                           [Byte1]: 47

 7896 13:54:38.980475  

 7897 13:54:38.980704  Set Vref, RX VrefLevel [Byte0]: 48

 7898 13:54:38.984126                           [Byte1]: 48

 7899 13:54:38.988159  

 7900 13:54:38.988313  Set Vref, RX VrefLevel [Byte0]: 49

 7901 13:54:38.991158                           [Byte1]: 49

 7902 13:54:38.995433  

 7903 13:54:38.995578  Set Vref, RX VrefLevel [Byte0]: 50

 7904 13:54:38.998891                           [Byte1]: 50

 7905 13:54:39.003082  

 7906 13:54:39.003166  Set Vref, RX VrefLevel [Byte0]: 51

 7907 13:54:39.006278                           [Byte1]: 51

 7908 13:54:39.010920  

 7909 13:54:39.011003  Set Vref, RX VrefLevel [Byte0]: 52

 7910 13:54:39.014087                           [Byte1]: 52

 7911 13:54:39.018341  

 7912 13:54:39.018766  Set Vref, RX VrefLevel [Byte0]: 53

 7913 13:54:39.021791                           [Byte1]: 53

 7914 13:54:39.026363  

 7915 13:54:39.026941  Set Vref, RX VrefLevel [Byte0]: 54

 7916 13:54:39.029514                           [Byte1]: 54

 7917 13:54:39.033402  

 7918 13:54:39.033705  Set Vref, RX VrefLevel [Byte0]: 55

 7919 13:54:39.036657                           [Byte1]: 55

 7920 13:54:39.041194  

 7921 13:54:39.041506  Set Vref, RX VrefLevel [Byte0]: 56

 7922 13:54:39.044539                           [Byte1]: 56

 7923 13:54:39.048415  

 7924 13:54:39.048718  Set Vref, RX VrefLevel [Byte0]: 57

 7925 13:54:39.051888                           [Byte1]: 57

 7926 13:54:39.056743  

 7927 13:54:39.057143  Set Vref, RX VrefLevel [Byte0]: 58

 7928 13:54:39.059756                           [Byte1]: 58

 7929 13:54:39.063753  

 7930 13:54:39.064062  Set Vref, RX VrefLevel [Byte0]: 59

 7931 13:54:39.067433                           [Byte1]: 59

 7932 13:54:39.071203  

 7933 13:54:39.071509  Set Vref, RX VrefLevel [Byte0]: 60

 7934 13:54:39.074655                           [Byte1]: 60

 7935 13:54:39.078774  

 7936 13:54:39.079503  Set Vref, RX VrefLevel [Byte0]: 61

 7937 13:54:39.082388                           [Byte1]: 61

 7938 13:54:39.086380  

 7939 13:54:39.086882  Set Vref, RX VrefLevel [Byte0]: 62

 7940 13:54:39.089532                           [Byte1]: 62

 7941 13:54:39.093916  

 7942 13:54:39.094375  Set Vref, RX VrefLevel [Byte0]: 63

 7943 13:54:39.096948                           [Byte1]: 63

 7944 13:54:39.101587  

 7945 13:54:39.102033  Set Vref, RX VrefLevel [Byte0]: 64

 7946 13:54:39.104853                           [Byte1]: 64

 7947 13:54:39.108986  

 7948 13:54:39.109516  Set Vref, RX VrefLevel [Byte0]: 65

 7949 13:54:39.112855                           [Byte1]: 65

 7950 13:54:39.117104  

 7951 13:54:39.117657  Set Vref, RX VrefLevel [Byte0]: 66

 7952 13:54:39.120041                           [Byte1]: 66

 7953 13:54:39.123905  

 7954 13:54:39.124324  Set Vref, RX VrefLevel [Byte0]: 67

 7955 13:54:39.127537                           [Byte1]: 67

 7956 13:54:39.131643  

 7957 13:54:39.132396  Set Vref, RX VrefLevel [Byte0]: 68

 7958 13:54:39.134588                           [Byte1]: 68

 7959 13:54:39.139349  

 7960 13:54:39.140032  Set Vref, RX VrefLevel [Byte0]: 69

 7961 13:54:39.142327                           [Byte1]: 69

 7962 13:54:39.146243  

 7963 13:54:39.146857  Set Vref, RX VrefLevel [Byte0]: 70

 7964 13:54:39.149997                           [Byte1]: 70

 7965 13:54:39.154107  

 7966 13:54:39.154641  Set Vref, RX VrefLevel [Byte0]: 71

 7967 13:54:39.157305                           [Byte1]: 71

 7968 13:54:39.161572  

 7969 13:54:39.162184  Set Vref, RX VrefLevel [Byte0]: 72

 7970 13:54:39.164824                           [Byte1]: 72

 7971 13:54:39.169012  

 7972 13:54:39.169297  Set Vref, RX VrefLevel [Byte0]: 73

 7973 13:54:39.172489                           [Byte1]: 73

 7974 13:54:39.176574  

 7975 13:54:39.176759  Set Vref, RX VrefLevel [Byte0]: 74

 7976 13:54:39.179831                           [Byte1]: 74

 7977 13:54:39.184293  

 7978 13:54:39.184478  Set Vref, RX VrefLevel [Byte0]: 75

 7979 13:54:39.187346                           [Byte1]: 75

 7980 13:54:39.191803  

 7981 13:54:39.191988  Set Vref, RX VrefLevel [Byte0]: 76

 7982 13:54:39.194685                           [Byte1]: 76

 7983 13:54:39.198981  

 7984 13:54:39.199235  Set Vref, RX VrefLevel [Byte0]: 77

 7985 13:54:39.202308                           [Byte1]: 77

 7986 13:54:39.206501  

 7987 13:54:39.206681  Set Vref, RX VrefLevel [Byte0]: 78

 7988 13:54:39.209965                           [Byte1]: 78

 7989 13:54:39.214136  

 7990 13:54:39.214425  Set Vref, RX VrefLevel [Byte0]: 79

 7991 13:54:39.217398                           [Byte1]: 79

 7992 13:54:39.221607  

 7993 13:54:39.221819  Set Vref, RX VrefLevel [Byte0]: 80

 7994 13:54:39.224971                           [Byte1]: 80

 7995 13:54:39.229224  

 7996 13:54:39.229439  Final RX Vref Byte 0 = 62 to rank0

 7997 13:54:39.232324  Final RX Vref Byte 1 = 63 to rank0

 7998 13:54:39.235749  Final RX Vref Byte 0 = 62 to rank1

 7999 13:54:39.239626  Final RX Vref Byte 1 = 63 to rank1==

 8000 13:54:39.242520  Dram Type= 6, Freq= 0, CH_0, rank 0

 8001 13:54:39.249117  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8002 13:54:39.249414  ==

 8003 13:54:39.249679  DQS Delay:

 8004 13:54:39.249923  DQS0 = 0, DQS1 = 0

 8005 13:54:39.252758  DQM Delay:

 8006 13:54:39.253041  DQM0 = 134, DQM1 = 127

 8007 13:54:39.255792  DQ Delay:

 8008 13:54:39.259173  DQ0 =134, DQ1 =134, DQ2 =130, DQ3 =132

 8009 13:54:39.262528  DQ4 =136, DQ5 =124, DQ6 =144, DQ7 =142

 8010 13:54:39.265520  DQ8 =118, DQ9 =114, DQ10 =130, DQ11 =122

 8011 13:54:39.269102  DQ12 =130, DQ13 =130, DQ14 =138, DQ15 =136

 8012 13:54:39.269372  

 8013 13:54:39.269576  

 8014 13:54:39.269767  

 8015 13:54:39.272303  [DramC_TX_OE_Calibration] TA2

 8016 13:54:39.275743  Original DQ_B0 (3 6) =30, OEN = 27

 8017 13:54:39.279515  Original DQ_B1 (3 6) =30, OEN = 27

 8018 13:54:39.282604  24, 0x0, End_B0=24 End_B1=24

 8019 13:54:39.283003  25, 0x0, End_B0=25 End_B1=25

 8020 13:54:39.286104  26, 0x0, End_B0=26 End_B1=26

 8021 13:54:39.289375  27, 0x0, End_B0=27 End_B1=27

 8022 13:54:39.292717  28, 0x0, End_B0=28 End_B1=28

 8023 13:54:39.293296  29, 0x0, End_B0=29 End_B1=29

 8024 13:54:39.296076  30, 0x0, End_B0=30 End_B1=30

 8025 13:54:39.299261  31, 0x4141, End_B0=30 End_B1=30

 8026 13:54:39.302616  Byte0 end_step=30  best_step=27

 8027 13:54:39.306109  Byte1 end_step=30  best_step=27

 8028 13:54:39.309459  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8029 13:54:39.309927  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8030 13:54:39.312979  

 8031 13:54:39.313500  

 8032 13:54:39.319262  [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps

 8033 13:54:39.322462  CH0 RK0: MR19=303, MR18=1C1A

 8034 13:54:39.329529  CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15

 8035 13:54:39.330103  

 8036 13:54:39.332463  ----->DramcWriteLeveling(PI) begin...

 8037 13:54:39.332888  ==

 8038 13:54:39.335731  Dram Type= 6, Freq= 0, CH_0, rank 1

 8039 13:54:39.339547  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8040 13:54:39.340120  ==

 8041 13:54:39.342402  Write leveling (Byte 0): 36 => 36

 8042 13:54:39.346033  Write leveling (Byte 1): 28 => 28

 8043 13:54:39.349312  DramcWriteLeveling(PI) end<-----

 8044 13:54:39.349783  

 8045 13:54:39.350197  ==

 8046 13:54:39.352381  Dram Type= 6, Freq= 0, CH_0, rank 1

 8047 13:54:39.356318  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8048 13:54:39.356765  ==

 8049 13:54:39.359335  [Gating] SW mode calibration

 8050 13:54:39.366059  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8051 13:54:39.372679  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8052 13:54:39.375937   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8053 13:54:39.379479   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8054 13:54:39.386032   1  4  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8055 13:54:39.389476   1  4 12 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)

 8056 13:54:39.392890   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8057 13:54:39.399407   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8058 13:54:39.402614   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8059 13:54:39.405663   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8060 13:54:39.412076   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8061 13:54:39.415521   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8062 13:54:39.418878   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8063 13:54:39.425393   1  5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)

 8064 13:54:39.428958   1  5 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)

 8065 13:54:39.431948   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8066 13:54:39.438583   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8067 13:54:39.442156   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8068 13:54:39.445678   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8069 13:54:39.452572   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8070 13:54:39.455888   1  6  8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)

 8071 13:54:39.458875   1  6 12 | B1->B0 | 2f2f 4545 | 0 1 | (0 0) (0 0)

 8072 13:54:39.465714   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8073 13:54:39.468999   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8074 13:54:39.472042   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8075 13:54:39.478665   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8076 13:54:39.482533   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8077 13:54:39.485259   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8078 13:54:39.488726   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8079 13:54:39.495085   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8080 13:54:39.498870   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8081 13:54:39.502009   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8082 13:54:39.509160   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8083 13:54:39.512251   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8084 13:54:39.515122   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8085 13:54:39.521765   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8086 13:54:39.525239   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8087 13:54:39.528445   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8088 13:54:39.535194   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8089 13:54:39.538411   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8090 13:54:39.542009   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8091 13:54:39.548466   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8092 13:54:39.551927   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8093 13:54:39.555252   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8094 13:54:39.561652   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8095 13:54:39.564843   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8096 13:54:39.568345   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8097 13:54:39.571725  Total UI for P1: 0, mck2ui 16

 8098 13:54:39.574986  best dqsien dly found for B0: ( 1,  9, 10)

 8099 13:54:39.578172  Total UI for P1: 0, mck2ui 16

 8100 13:54:39.582081  best dqsien dly found for B1: ( 1,  9, 12)

 8101 13:54:39.585221  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8102 13:54:39.588434  best DQS1 dly(MCK, UI, PI) = (1, 9, 12)

 8103 13:54:39.588963  

 8104 13:54:39.591891  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8105 13:54:39.598286  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8106 13:54:39.598896  [Gating] SW calibration Done

 8107 13:54:39.601660  ==

 8108 13:54:39.605190  Dram Type= 6, Freq= 0, CH_0, rank 1

 8109 13:54:39.608695  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8110 13:54:39.609247  ==

 8111 13:54:39.609587  RX Vref Scan: 0

 8112 13:54:39.609898  

 8113 13:54:39.611540  RX Vref 0 -> 0, step: 1

 8114 13:54:39.611961  

 8115 13:54:39.615212  RX Delay 0 -> 252, step: 8

 8116 13:54:39.618166  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8117 13:54:39.621666  iDelay=200, Bit 1, Center 135 (80 ~ 191) 112

 8118 13:54:39.625012  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8119 13:54:39.631528  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 8120 13:54:39.634766  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 8121 13:54:39.638475  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8122 13:54:39.641664  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8123 13:54:39.644826  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8124 13:54:39.651690  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 8125 13:54:39.654609  iDelay=200, Bit 9, Center 115 (64 ~ 167) 104

 8126 13:54:39.658319  iDelay=200, Bit 10, Center 127 (80 ~ 175) 96

 8127 13:54:39.661374  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 8128 13:54:39.664868  iDelay=200, Bit 12, Center 131 (80 ~ 183) 104

 8129 13:54:39.671807  iDelay=200, Bit 13, Center 131 (80 ~ 183) 104

 8130 13:54:39.675123  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8131 13:54:39.678201  iDelay=200, Bit 15, Center 131 (80 ~ 183) 104

 8132 13:54:39.678851  ==

 8133 13:54:39.681368  Dram Type= 6, Freq= 0, CH_0, rank 1

 8134 13:54:39.684472  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8135 13:54:39.684949  ==

 8136 13:54:39.687671  DQS Delay:

 8137 13:54:39.688188  DQS0 = 0, DQS1 = 0

 8138 13:54:39.691291  DQM Delay:

 8139 13:54:39.691814  DQM0 = 135, DQM1 = 126

 8140 13:54:39.692254  DQ Delay:

 8141 13:54:39.694545  DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131

 8142 13:54:39.701251  DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143

 8143 13:54:39.704350  DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123

 8144 13:54:39.707834  DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131

 8145 13:54:39.708042  

 8146 13:54:39.708187  

 8147 13:54:39.708319  ==

 8148 13:54:39.710930  Dram Type= 6, Freq= 0, CH_0, rank 1

 8149 13:54:39.714434  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8150 13:54:39.714587  ==

 8151 13:54:39.714706  

 8152 13:54:39.714817  

 8153 13:54:39.717606  	TX Vref Scan disable

 8154 13:54:39.721220   == TX Byte 0 ==

 8155 13:54:39.724610  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 8156 13:54:39.727585  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8157 13:54:39.731585   == TX Byte 1 ==

 8158 13:54:39.734288  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8159 13:54:39.737647  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8160 13:54:39.737868  ==

 8161 13:54:39.741187  Dram Type= 6, Freq= 0, CH_0, rank 1

 8162 13:54:39.744661  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8163 13:54:39.747588  ==

 8164 13:54:39.761625  

 8165 13:54:39.765028  TX Vref early break, caculate TX vref

 8166 13:54:39.768081  TX Vref=16, minBit 12, minWin=23, winSum=390

 8167 13:54:39.771584  TX Vref=18, minBit 0, minWin=24, winSum=396

 8168 13:54:39.774793  TX Vref=20, minBit 0, minWin=23, winSum=402

 8169 13:54:39.778050  TX Vref=22, minBit 8, minWin=24, winSum=412

 8170 13:54:39.781374  TX Vref=24, minBit 0, minWin=26, winSum=423

 8171 13:54:39.787808  TX Vref=26, minBit 1, minWin=26, winSum=426

 8172 13:54:39.791489  TX Vref=28, minBit 0, minWin=25, winSum=426

 8173 13:54:39.794181  TX Vref=30, minBit 0, minWin=26, winSum=426

 8174 13:54:39.797810  TX Vref=32, minBit 0, minWin=25, winSum=416

 8175 13:54:39.800909  TX Vref=34, minBit 0, minWin=25, winSum=409

 8176 13:54:39.804136  TX Vref=36, minBit 0, minWin=24, winSum=398

 8177 13:54:39.810601  [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 26

 8178 13:54:39.811079  

 8179 13:54:39.813915  Final TX Range 0 Vref 26

 8180 13:54:39.814429  

 8181 13:54:39.814971  ==

 8182 13:54:39.817627  Dram Type= 6, Freq= 0, CH_0, rank 1

 8183 13:54:39.820795  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8184 13:54:39.821230  ==

 8185 13:54:39.821583  

 8186 13:54:39.823977  

 8187 13:54:39.824278  	TX Vref Scan disable

 8188 13:54:39.830477  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8189 13:54:39.830707   == TX Byte 0 ==

 8190 13:54:39.833774  u2DelayCellOfst[0]=13 cells (4 PI)

 8191 13:54:39.837047  u2DelayCellOfst[1]=16 cells (5 PI)

 8192 13:54:39.840196  u2DelayCellOfst[2]=10 cells (3 PI)

 8193 13:54:39.844074  u2DelayCellOfst[3]=10 cells (3 PI)

 8194 13:54:39.847085  u2DelayCellOfst[4]=6 cells (2 PI)

 8195 13:54:39.850350  u2DelayCellOfst[5]=0 cells (0 PI)

 8196 13:54:39.853856  u2DelayCellOfst[6]=16 cells (5 PI)

 8197 13:54:39.856898  u2DelayCellOfst[7]=16 cells (5 PI)

 8198 13:54:39.860097  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 8199 13:54:39.863446  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8200 13:54:39.866903   == TX Byte 1 ==

 8201 13:54:39.869984  u2DelayCellOfst[8]=0 cells (0 PI)

 8202 13:54:39.873463  u2DelayCellOfst[9]=3 cells (1 PI)

 8203 13:54:39.876917  u2DelayCellOfst[10]=6 cells (2 PI)

 8204 13:54:39.877038  u2DelayCellOfst[11]=3 cells (1 PI)

 8205 13:54:39.880243  u2DelayCellOfst[12]=13 cells (4 PI)

 8206 13:54:39.883527  u2DelayCellOfst[13]=13 cells (4 PI)

 8207 13:54:39.886886  u2DelayCellOfst[14]=13 cells (4 PI)

 8208 13:54:39.890137  u2DelayCellOfst[15]=10 cells (3 PI)

 8209 13:54:39.896454  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8210 13:54:39.899977  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8211 13:54:39.900084  DramC Write-DBI on

 8212 13:54:39.900150  ==

 8213 13:54:39.903212  Dram Type= 6, Freq= 0, CH_0, rank 1

 8214 13:54:39.910259  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8215 13:54:39.910344  ==

 8216 13:54:39.910411  

 8217 13:54:39.910471  

 8218 13:54:39.913020  	TX Vref Scan disable

 8219 13:54:39.913188   == TX Byte 0 ==

 8220 13:54:39.920152  Update DQM dly =736 (2 ,6, 32)  DQM OEN =(3 ,3)

 8221 13:54:39.920296   == TX Byte 1 ==

 8222 13:54:39.923254  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8223 13:54:39.926691  DramC Write-DBI off

 8224 13:54:39.926821  

 8225 13:54:39.926894  [DATLAT]

 8226 13:54:39.930240  Freq=1600, CH0 RK1

 8227 13:54:39.930399  

 8228 13:54:39.930484  DATLAT Default: 0xf

 8229 13:54:39.933111  0, 0xFFFF, sum = 0

 8230 13:54:39.933212  1, 0xFFFF, sum = 0

 8231 13:54:39.936507  2, 0xFFFF, sum = 0

 8232 13:54:39.936686  3, 0xFFFF, sum = 0

 8233 13:54:39.940026  4, 0xFFFF, sum = 0

 8234 13:54:39.940208  5, 0xFFFF, sum = 0

 8235 13:54:39.943086  6, 0xFFFF, sum = 0

 8236 13:54:39.943235  7, 0xFFFF, sum = 0

 8237 13:54:39.946273  8, 0xFFFF, sum = 0

 8238 13:54:39.946463  9, 0xFFFF, sum = 0

 8239 13:54:39.949922  10, 0xFFFF, sum = 0

 8240 13:54:39.953037  11, 0xFFFF, sum = 0

 8241 13:54:39.953249  12, 0xFFFF, sum = 0

 8242 13:54:39.956043  13, 0xFFFF, sum = 0

 8243 13:54:39.956267  14, 0x0, sum = 1

 8244 13:54:39.959428  15, 0x0, sum = 2

 8245 13:54:39.959597  16, 0x0, sum = 3

 8246 13:54:39.963271  17, 0x0, sum = 4

 8247 13:54:39.963519  best_step = 15

 8248 13:54:39.963653  

 8249 13:54:39.963775  ==

 8250 13:54:39.966754  Dram Type= 6, Freq= 0, CH_0, rank 1

 8251 13:54:39.969917  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8252 13:54:39.970207  ==

 8253 13:54:39.973614  RX Vref Scan: 0

 8254 13:54:39.973878  

 8255 13:54:39.976848  RX Vref 0 -> 0, step: 1

 8256 13:54:39.977146  

 8257 13:54:39.977318  RX Delay 19 -> 252, step: 4

 8258 13:54:39.983538  iDelay=191, Bit 0, Center 130 (79 ~ 182) 104

 8259 13:54:39.986565  iDelay=191, Bit 1, Center 134 (83 ~ 186) 104

 8260 13:54:39.990181  iDelay=191, Bit 2, Center 128 (79 ~ 178) 100

 8261 13:54:39.993370  iDelay=191, Bit 3, Center 130 (83 ~ 178) 96

 8262 13:54:39.996857  iDelay=191, Bit 4, Center 134 (83 ~ 186) 104

 8263 13:54:40.003785  iDelay=191, Bit 5, Center 124 (75 ~ 174) 100

 8264 13:54:40.006758  iDelay=191, Bit 6, Center 138 (87 ~ 190) 104

 8265 13:54:40.009922  iDelay=191, Bit 7, Center 138 (87 ~ 190) 104

 8266 13:54:40.013556  iDelay=191, Bit 8, Center 118 (71 ~ 166) 96

 8267 13:54:40.016466  iDelay=191, Bit 9, Center 112 (63 ~ 162) 100

 8268 13:54:40.022905  iDelay=191, Bit 10, Center 124 (79 ~ 170) 92

 8269 13:54:40.026474  iDelay=191, Bit 11, Center 122 (75 ~ 170) 96

 8270 13:54:40.030021  iDelay=191, Bit 12, Center 128 (79 ~ 178) 100

 8271 13:54:40.033371  iDelay=191, Bit 13, Center 130 (83 ~ 178) 96

 8272 13:54:40.036842  iDelay=191, Bit 14, Center 134 (83 ~ 186) 104

 8273 13:54:40.043018  iDelay=191, Bit 15, Center 132 (83 ~ 182) 100

 8274 13:54:40.043532  ==

 8275 13:54:40.046037  Dram Type= 6, Freq= 0, CH_0, rank 1

 8276 13:54:40.049627  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8277 13:54:40.050081  ==

 8278 13:54:40.050421  DQS Delay:

 8279 13:54:40.053004  DQS0 = 0, DQS1 = 0

 8280 13:54:40.053429  DQM Delay:

 8281 13:54:40.056416  DQM0 = 132, DQM1 = 125

 8282 13:54:40.056951  DQ Delay:

 8283 13:54:40.060207  DQ0 =130, DQ1 =134, DQ2 =128, DQ3 =130

 8284 13:54:40.062707  DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =138

 8285 13:54:40.066358  DQ8 =118, DQ9 =112, DQ10 =124, DQ11 =122

 8286 13:54:40.069662  DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132

 8287 13:54:40.070107  

 8288 13:54:40.072636  

 8289 13:54:40.073056  

 8290 13:54:40.073386  [DramC_TX_OE_Calibration] TA2

 8291 13:54:40.076369  Original DQ_B0 (3 6) =30, OEN = 27

 8292 13:54:40.080003  Original DQ_B1 (3 6) =30, OEN = 27

 8293 13:54:40.083291  24, 0x0, End_B0=24 End_B1=24

 8294 13:54:40.086195  25, 0x0, End_B0=25 End_B1=25

 8295 13:54:40.089439  26, 0x0, End_B0=26 End_B1=26

 8296 13:54:40.089870  27, 0x0, End_B0=27 End_B1=27

 8297 13:54:40.093071  28, 0x0, End_B0=28 End_B1=28

 8298 13:54:40.096205  29, 0x0, End_B0=29 End_B1=29

 8299 13:54:40.099639  30, 0x0, End_B0=30 End_B1=30

 8300 13:54:40.102886  31, 0x4141, End_B0=30 End_B1=30

 8301 13:54:40.103333  Byte0 end_step=30  best_step=27

 8302 13:54:40.106357  Byte1 end_step=30  best_step=27

 8303 13:54:40.109556  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8304 13:54:40.112605  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8305 13:54:40.113027  

 8306 13:54:40.113359  

 8307 13:54:40.119501  [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps

 8308 13:54:40.122481  CH0 RK1: MR19=303, MR18=1F0C

 8309 13:54:40.129497  CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15

 8310 13:54:40.132947  [RxdqsGatingPostProcess] freq 1600

 8311 13:54:40.139402  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8312 13:54:40.142576  best DQS0 dly(2T, 0.5T) = (1, 1)

 8313 13:54:40.142805  best DQS1 dly(2T, 0.5T) = (1, 1)

 8314 13:54:40.145928  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8315 13:54:40.149138  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8316 13:54:40.152275  best DQS0 dly(2T, 0.5T) = (1, 1)

 8317 13:54:40.155982  best DQS1 dly(2T, 0.5T) = (1, 1)

 8318 13:54:40.159097  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8319 13:54:40.162367  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8320 13:54:40.165867  Pre-setting of DQS Precalculation

 8321 13:54:40.168939  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8322 13:54:40.169105  ==

 8323 13:54:40.172484  Dram Type= 6, Freq= 0, CH_1, rank 0

 8324 13:54:40.179259  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8325 13:54:40.179369  ==

 8326 13:54:40.182730  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8327 13:54:40.189128  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8328 13:54:40.192746  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8329 13:54:40.199132  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8330 13:54:40.206961  [CA 0] Center 40 (11~70) winsize 60

 8331 13:54:40.210178  [CA 1] Center 40 (10~71) winsize 62

 8332 13:54:40.213458  [CA 2] Center 37 (8~66) winsize 59

 8333 13:54:40.216978  [CA 3] Center 36 (7~66) winsize 60

 8334 13:54:40.220428  [CA 4] Center 36 (6~67) winsize 62

 8335 13:54:40.223323  [CA 5] Center 36 (6~66) winsize 61

 8336 13:54:40.223510  

 8337 13:54:40.227089  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8338 13:54:40.227533  

 8339 13:54:40.230377  [CATrainingPosCal] consider 1 rank data

 8340 13:54:40.233691  u2DelayCellTimex100 = 290/100 ps

 8341 13:54:40.237084  CA0 delay=40 (11~70),Diff = 4 PI (13 cell)

 8342 13:54:40.244194  CA1 delay=40 (10~71),Diff = 4 PI (13 cell)

 8343 13:54:40.246931  CA2 delay=37 (8~66),Diff = 1 PI (3 cell)

 8344 13:54:40.250303  CA3 delay=36 (7~66),Diff = 0 PI (0 cell)

 8345 13:54:40.253559  CA4 delay=36 (6~67),Diff = 0 PI (0 cell)

 8346 13:54:40.256956  CA5 delay=36 (6~66),Diff = 0 PI (0 cell)

 8347 13:54:40.257553  

 8348 13:54:40.260461  CA PerBit enable=1, Macro0, CA PI delay=36

 8349 13:54:40.260982  

 8350 13:54:40.263494  [CBTSetCACLKResult] CA Dly = 36

 8351 13:54:40.266827  CS Dly: 9 (0~40)

 8352 13:54:40.270485  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8353 13:54:40.274308  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8354 13:54:40.274868  ==

 8355 13:54:40.277183  Dram Type= 6, Freq= 0, CH_1, rank 1

 8356 13:54:40.280590  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8357 13:54:40.281126  ==

 8358 13:54:40.287200  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8359 13:54:40.290522  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8360 13:54:40.297014  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8361 13:54:40.300081  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8362 13:54:40.310001  [CA 0] Center 41 (12~71) winsize 60

 8363 13:54:40.313581  [CA 1] Center 41 (12~71) winsize 60

 8364 13:54:40.316866  [CA 2] Center 38 (9~67) winsize 59

 8365 13:54:40.320217  [CA 3] Center 37 (8~67) winsize 60

 8366 13:54:40.323664  [CA 4] Center 37 (8~67) winsize 60

 8367 13:54:40.326939  [CA 5] Center 37 (7~67) winsize 61

 8368 13:54:40.327364  

 8369 13:54:40.330041  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8370 13:54:40.330504  

 8371 13:54:40.333332  [CATrainingPosCal] consider 2 rank data

 8372 13:54:40.336578  u2DelayCellTimex100 = 290/100 ps

 8373 13:54:40.340211  CA0 delay=41 (12~70),Diff = 5 PI (16 cell)

 8374 13:54:40.346823  CA1 delay=41 (12~71),Diff = 5 PI (16 cell)

 8375 13:54:40.349906  CA2 delay=37 (9~66),Diff = 1 PI (3 cell)

 8376 13:54:40.353696  CA3 delay=37 (8~66),Diff = 1 PI (3 cell)

 8377 13:54:40.356830  CA4 delay=37 (8~67),Diff = 1 PI (3 cell)

 8378 13:54:40.360104  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8379 13:54:40.360659  

 8380 13:54:40.363187  CA PerBit enable=1, Macro0, CA PI delay=36

 8381 13:54:40.363639  

 8382 13:54:40.367069  [CBTSetCACLKResult] CA Dly = 36

 8383 13:54:40.370105  CS Dly: 10 (0~42)

 8384 13:54:40.373309  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8385 13:54:40.377082  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8386 13:54:40.377639  

 8387 13:54:40.380321  ----->DramcWriteLeveling(PI) begin...

 8388 13:54:40.380787  ==

 8389 13:54:40.383279  Dram Type= 6, Freq= 0, CH_1, rank 0

 8390 13:54:40.389802  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8391 13:54:40.390258  ==

 8392 13:54:40.393916  Write leveling (Byte 0): 25 => 25

 8393 13:54:40.394514  Write leveling (Byte 1): 28 => 28

 8394 13:54:40.396769  DramcWriteLeveling(PI) end<-----

 8395 13:54:40.397182  

 8396 13:54:40.397509  ==

 8397 13:54:40.399755  Dram Type= 6, Freq= 0, CH_1, rank 0

 8398 13:54:40.406846  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8399 13:54:40.407409  ==

 8400 13:54:40.410188  [Gating] SW mode calibration

 8401 13:54:40.416358  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8402 13:54:40.419796  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8403 13:54:40.426271   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8404 13:54:40.429569   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8405 13:54:40.433217   1  4  8 | B1->B0 | 2323 2b2b | 1 1 | (0 0) (0 0)

 8406 13:54:40.439844   1  4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 8407 13:54:40.443270   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8408 13:54:40.446271   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8409 13:54:40.453118   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8410 13:54:40.456549   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8411 13:54:40.460135   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8412 13:54:40.462891   1  5  4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 8413 13:54:40.469643   1  5  8 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (1 0)

 8414 13:54:40.473317   1  5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8415 13:54:40.476491   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8416 13:54:40.483025   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8417 13:54:40.486360   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8418 13:54:40.489713   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8419 13:54:40.496717   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8420 13:54:40.499754   1  6  4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 8421 13:54:40.502884   1  6  8 | B1->B0 | 2c2c 4444 | 0 0 | (0 0) (0 0)

 8422 13:54:40.509738   1  6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 8423 13:54:40.513036   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8424 13:54:40.516135   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8425 13:54:40.522847   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8426 13:54:40.526018   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8427 13:54:40.529224   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8428 13:54:40.536103   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8429 13:54:40.539493   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8430 13:54:40.542574   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8431 13:54:40.549894   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8432 13:54:40.552989   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8433 13:54:40.556116   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8434 13:54:40.562721   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8435 13:54:40.565835   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8436 13:54:40.569124   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8437 13:54:40.576233   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8438 13:54:40.579444   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8439 13:54:40.582901   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8440 13:54:40.586318   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8441 13:54:40.592938   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8442 13:54:40.596055   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8443 13:54:40.599547   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8444 13:54:40.605807   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8445 13:54:40.609387   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8446 13:54:40.612403   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8447 13:54:40.615825  Total UI for P1: 0, mck2ui 16

 8448 13:54:40.619297  best dqsien dly found for B0: ( 1,  9,  6)

 8449 13:54:40.625685   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8450 13:54:40.629457  Total UI for P1: 0, mck2ui 16

 8451 13:54:40.632663  best dqsien dly found for B1: ( 1,  9, 12)

 8452 13:54:40.635885  best DQS0 dly(MCK, UI, PI) = (1, 9, 6)

 8453 13:54:40.638878  best DQS1 dly(MCK, UI, PI) = (1, 9, 12)

 8454 13:54:40.639310  

 8455 13:54:40.642521  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8456 13:54:40.645655  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8457 13:54:40.649315  [Gating] SW calibration Done

 8458 13:54:40.649856  ==

 8459 13:54:40.652249  Dram Type= 6, Freq= 0, CH_1, rank 0

 8460 13:54:40.656000  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8461 13:54:40.656544  ==

 8462 13:54:40.659088  RX Vref Scan: 0

 8463 13:54:40.659602  

 8464 13:54:40.660097  RX Vref 0 -> 0, step: 1

 8465 13:54:40.662461  

 8466 13:54:40.662888  RX Delay 0 -> 252, step: 8

 8467 13:54:40.665793  iDelay=200, Bit 0, Center 139 (96 ~ 183) 88

 8468 13:54:40.672516  iDelay=200, Bit 1, Center 135 (88 ~ 183) 96

 8469 13:54:40.675856  iDelay=200, Bit 2, Center 127 (80 ~ 175) 96

 8470 13:54:40.679134  iDelay=200, Bit 3, Center 139 (88 ~ 191) 104

 8471 13:54:40.682052  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8472 13:54:40.685761  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8473 13:54:40.692392  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8474 13:54:40.695442  iDelay=200, Bit 7, Center 135 (88 ~ 183) 96

 8475 13:54:40.699392  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8476 13:54:40.702515  iDelay=200, Bit 9, Center 119 (72 ~ 167) 96

 8477 13:54:40.705541  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8478 13:54:40.708792  iDelay=200, Bit 11, Center 127 (80 ~ 175) 96

 8479 13:54:40.715845  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8480 13:54:40.718747  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8481 13:54:40.722360  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8482 13:54:40.725673  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8483 13:54:40.726131  ==

 8484 13:54:40.729070  Dram Type= 6, Freq= 0, CH_1, rank 0

 8485 13:54:40.735400  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8486 13:54:40.735829  ==

 8487 13:54:40.736181  DQS Delay:

 8488 13:54:40.738972  DQS0 = 0, DQS1 = 0

 8489 13:54:40.739411  DQM Delay:

 8490 13:54:40.739738  DQM0 = 138, DQM1 = 130

 8491 13:54:40.742212  DQ Delay:

 8492 13:54:40.745273  DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139

 8493 13:54:40.748745  DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135

 8494 13:54:40.752039  DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127

 8495 13:54:40.755648  DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135

 8496 13:54:40.756088  

 8497 13:54:40.756419  

 8498 13:54:40.756726  ==

 8499 13:54:40.758933  Dram Type= 6, Freq= 0, CH_1, rank 0

 8500 13:54:40.762032  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8501 13:54:40.765753  ==

 8502 13:54:40.766328  

 8503 13:54:40.766686  

 8504 13:54:40.766994  	TX Vref Scan disable

 8505 13:54:40.768881   == TX Byte 0 ==

 8506 13:54:40.771972  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8507 13:54:40.775613  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8508 13:54:40.779032   == TX Byte 1 ==

 8509 13:54:40.782208  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8510 13:54:40.785836  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8511 13:54:40.789408  ==

 8512 13:54:40.789931  Dram Type= 6, Freq= 0, CH_1, rank 0

 8513 13:54:40.795449  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8514 13:54:40.795964  ==

 8515 13:54:40.807247  

 8516 13:54:40.810714  TX Vref early break, caculate TX vref

 8517 13:54:40.814176  TX Vref=16, minBit 13, minWin=22, winSum=372

 8518 13:54:40.817578  TX Vref=18, minBit 9, minWin=23, winSum=386

 8519 13:54:40.820610  TX Vref=20, minBit 15, minWin=23, winSum=395

 8520 13:54:40.823587  TX Vref=22, minBit 12, minWin=24, winSum=407

 8521 13:54:40.830456  TX Vref=24, minBit 15, minWin=24, winSum=413

 8522 13:54:40.834070  TX Vref=26, minBit 15, minWin=25, winSum=424

 8523 13:54:40.836873  TX Vref=28, minBit 5, minWin=25, winSum=425

 8524 13:54:40.840301  TX Vref=30, minBit 13, minWin=25, winSum=421

 8525 13:54:40.843940  TX Vref=32, minBit 5, minWin=24, winSum=410

 8526 13:54:40.846908  TX Vref=34, minBit 5, minWin=24, winSum=401

 8527 13:54:40.853737  [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 28

 8528 13:54:40.854333  

 8529 13:54:40.857002  Final TX Range 0 Vref 28

 8530 13:54:40.857466  

 8531 13:54:40.857827  ==

 8532 13:54:40.860891  Dram Type= 6, Freq= 0, CH_1, rank 0

 8533 13:54:40.863811  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8534 13:54:40.864387  ==

 8535 13:54:40.864756  

 8536 13:54:40.865211  

 8537 13:54:40.866988  	TX Vref Scan disable

 8538 13:54:40.873480  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8539 13:54:40.874104   == TX Byte 0 ==

 8540 13:54:40.876841  u2DelayCellOfst[0]=16 cells (5 PI)

 8541 13:54:40.880288  u2DelayCellOfst[1]=10 cells (3 PI)

 8542 13:54:40.883483  u2DelayCellOfst[2]=0 cells (0 PI)

 8543 13:54:40.887292  u2DelayCellOfst[3]=6 cells (2 PI)

 8544 13:54:40.890164  u2DelayCellOfst[4]=6 cells (2 PI)

 8545 13:54:40.893760  u2DelayCellOfst[5]=16 cells (5 PI)

 8546 13:54:40.896639  u2DelayCellOfst[6]=16 cells (5 PI)

 8547 13:54:40.900120  u2DelayCellOfst[7]=6 cells (2 PI)

 8548 13:54:40.903136  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8549 13:54:40.906816  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8550 13:54:40.910357   == TX Byte 1 ==

 8551 13:54:40.913345  u2DelayCellOfst[8]=0 cells (0 PI)

 8552 13:54:40.913814  u2DelayCellOfst[9]=0 cells (0 PI)

 8553 13:54:40.916812  u2DelayCellOfst[10]=6 cells (2 PI)

 8554 13:54:40.920282  u2DelayCellOfst[11]=0 cells (0 PI)

 8555 13:54:40.923245  u2DelayCellOfst[12]=13 cells (4 PI)

 8556 13:54:40.926575  u2DelayCellOfst[13]=13 cells (4 PI)

 8557 13:54:40.929680  u2DelayCellOfst[14]=13 cells (4 PI)

 8558 13:54:40.933457  u2DelayCellOfst[15]=10 cells (3 PI)

 8559 13:54:40.936411  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8560 13:54:40.943097  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8561 13:54:40.943686  DramC Write-DBI on

 8562 13:54:40.944068  ==

 8563 13:54:40.946560  Dram Type= 6, Freq= 0, CH_1, rank 0

 8564 13:54:40.953228  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8565 13:54:40.953797  ==

 8566 13:54:40.954275  

 8567 13:54:40.954631  

 8568 13:54:40.954961  	TX Vref Scan disable

 8569 13:54:40.956504   == TX Byte 0 ==

 8570 13:54:40.960233  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8571 13:54:40.963507   == TX Byte 1 ==

 8572 13:54:40.967196  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8573 13:54:40.970289  DramC Write-DBI off

 8574 13:54:40.970868  

 8575 13:54:40.971238  [DATLAT]

 8576 13:54:40.971579  Freq=1600, CH1 RK0

 8577 13:54:40.971904  

 8578 13:54:40.973685  DATLAT Default: 0xf

 8579 13:54:40.974301  0, 0xFFFF, sum = 0

 8580 13:54:40.976968  1, 0xFFFF, sum = 0

 8581 13:54:40.980378  2, 0xFFFF, sum = 0

 8582 13:54:40.980960  3, 0xFFFF, sum = 0

 8583 13:54:40.983438  4, 0xFFFF, sum = 0

 8584 13:54:40.984020  5, 0xFFFF, sum = 0

 8585 13:54:40.986951  6, 0xFFFF, sum = 0

 8586 13:54:40.987564  7, 0xFFFF, sum = 0

 8587 13:54:40.990499  8, 0xFFFF, sum = 0

 8588 13:54:40.991082  9, 0xFFFF, sum = 0

 8589 13:54:40.993552  10, 0xFFFF, sum = 0

 8590 13:54:40.994159  11, 0xFFFF, sum = 0

 8591 13:54:40.997116  12, 0xFFFF, sum = 0

 8592 13:54:40.997699  13, 0xFFFF, sum = 0

 8593 13:54:40.999829  14, 0x0, sum = 1

 8594 13:54:41.000306  15, 0x0, sum = 2

 8595 13:54:41.003102  16, 0x0, sum = 3

 8596 13:54:41.003581  17, 0x0, sum = 4

 8597 13:54:41.006620  best_step = 15

 8598 13:54:41.007089  

 8599 13:54:41.007453  ==

 8600 13:54:41.009893  Dram Type= 6, Freq= 0, CH_1, rank 0

 8601 13:54:41.013097  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8602 13:54:41.013568  ==

 8603 13:54:41.013934  RX Vref Scan: 1

 8604 13:54:41.016832  

 8605 13:54:41.017408  Set Vref Range= 24 -> 127

 8606 13:54:41.017785  

 8607 13:54:41.020309  RX Vref 24 -> 127, step: 1

 8608 13:54:41.020883  

 8609 13:54:41.023099  RX Delay 19 -> 252, step: 4

 8610 13:54:41.023569  

 8611 13:54:41.026543  Set Vref, RX VrefLevel [Byte0]: 24

 8612 13:54:41.030247                           [Byte1]: 24

 8613 13:54:41.030882  

 8614 13:54:41.033472  Set Vref, RX VrefLevel [Byte0]: 25

 8615 13:54:41.036581                           [Byte1]: 25

 8616 13:54:41.037176  

 8617 13:54:41.039580  Set Vref, RX VrefLevel [Byte0]: 26

 8618 13:54:41.043524                           [Byte1]: 26

 8619 13:54:41.046939  

 8620 13:54:41.047510  Set Vref, RX VrefLevel [Byte0]: 27

 8621 13:54:41.050691                           [Byte1]: 27

 8622 13:54:41.054639  

 8623 13:54:41.055227  Set Vref, RX VrefLevel [Byte0]: 28

 8624 13:54:41.058154                           [Byte1]: 28

 8625 13:54:41.062078  

 8626 13:54:41.062541  Set Vref, RX VrefLevel [Byte0]: 29

 8627 13:54:41.065697                           [Byte1]: 29

 8628 13:54:41.069911  

 8629 13:54:41.070662  Set Vref, RX VrefLevel [Byte0]: 30

 8630 13:54:41.072981                           [Byte1]: 30

 8631 13:54:41.077340  

 8632 13:54:41.077785  Set Vref, RX VrefLevel [Byte0]: 31

 8633 13:54:41.080703                           [Byte1]: 31

 8634 13:54:41.084948  

 8635 13:54:41.085526  Set Vref, RX VrefLevel [Byte0]: 32

 8636 13:54:41.088029                           [Byte1]: 32

 8637 13:54:41.092877  

 8638 13:54:41.093444  Set Vref, RX VrefLevel [Byte0]: 33

 8639 13:54:41.096265                           [Byte1]: 33

 8640 13:54:41.100043  

 8641 13:54:41.100505  Set Vref, RX VrefLevel [Byte0]: 34

 8642 13:54:41.103393                           [Byte1]: 34

 8643 13:54:41.107552  

 8644 13:54:41.108016  Set Vref, RX VrefLevel [Byte0]: 35

 8645 13:54:41.110768                           [Byte1]: 35

 8646 13:54:41.115503  

 8647 13:54:41.116093  Set Vref, RX VrefLevel [Byte0]: 36

 8648 13:54:41.118440                           [Byte1]: 36

 8649 13:54:41.122830  

 8650 13:54:41.123401  Set Vref, RX VrefLevel [Byte0]: 37

 8651 13:54:41.126339                           [Byte1]: 37

 8652 13:54:41.130504  

 8653 13:54:41.131143  Set Vref, RX VrefLevel [Byte0]: 38

 8654 13:54:41.133656                           [Byte1]: 38

 8655 13:54:41.138135  

 8656 13:54:41.138701  Set Vref, RX VrefLevel [Byte0]: 39

 8657 13:54:41.141204                           [Byte1]: 39

 8658 13:54:41.145279  

 8659 13:54:41.145747  Set Vref, RX VrefLevel [Byte0]: 40

 8660 13:54:41.149139                           [Byte1]: 40

 8661 13:54:41.153759  

 8662 13:54:41.154382  Set Vref, RX VrefLevel [Byte0]: 41

 8663 13:54:41.156494                           [Byte1]: 41

 8664 13:54:41.160564  

 8665 13:54:41.161035  Set Vref, RX VrefLevel [Byte0]: 42

 8666 13:54:41.164046                           [Byte1]: 42

 8667 13:54:41.168170  

 8668 13:54:41.168712  Set Vref, RX VrefLevel [Byte0]: 43

 8669 13:54:41.171644                           [Byte1]: 43

 8670 13:54:41.175733  

 8671 13:54:41.176174  Set Vref, RX VrefLevel [Byte0]: 44

 8672 13:54:41.179152                           [Byte1]: 44

 8673 13:54:41.183060  

 8674 13:54:41.183668  Set Vref, RX VrefLevel [Byte0]: 45

 8675 13:54:41.186233                           [Byte1]: 45

 8676 13:54:41.190442  

 8677 13:54:41.190920  Set Vref, RX VrefLevel [Byte0]: 46

 8678 13:54:41.194154                           [Byte1]: 46

 8679 13:54:41.198318  

 8680 13:54:41.198912  Set Vref, RX VrefLevel [Byte0]: 47

 8681 13:54:41.201386                           [Byte1]: 47

 8682 13:54:41.205917  

 8683 13:54:41.206399  Set Vref, RX VrefLevel [Byte0]: 48

 8684 13:54:41.209413                           [Byte1]: 48

 8685 13:54:41.213746  

 8686 13:54:41.214320  Set Vref, RX VrefLevel [Byte0]: 49

 8687 13:54:41.216662                           [Byte1]: 49

 8688 13:54:41.221169  

 8689 13:54:41.221725  Set Vref, RX VrefLevel [Byte0]: 50

 8690 13:54:41.224686                           [Byte1]: 50

 8691 13:54:41.228932  

 8692 13:54:41.229490  Set Vref, RX VrefLevel [Byte0]: 51

 8693 13:54:41.232171                           [Byte1]: 51

 8694 13:54:41.236172  

 8695 13:54:41.236609  Set Vref, RX VrefLevel [Byte0]: 52

 8696 13:54:41.240142                           [Byte1]: 52

 8697 13:54:41.243904  

 8698 13:54:41.244332  Set Vref, RX VrefLevel [Byte0]: 53

 8699 13:54:41.247066                           [Byte1]: 53

 8700 13:54:41.251878  

 8701 13:54:41.252403  Set Vref, RX VrefLevel [Byte0]: 54

 8702 13:54:41.254730                           [Byte1]: 54

 8703 13:54:41.258829  

 8704 13:54:41.259257  Set Vref, RX VrefLevel [Byte0]: 55

 8705 13:54:41.262529                           [Byte1]: 55

 8706 13:54:41.266591  

 8707 13:54:41.267123  Set Vref, RX VrefLevel [Byte0]: 56

 8708 13:54:41.269869                           [Byte1]: 56

 8709 13:54:41.274368  

 8710 13:54:41.274913  Set Vref, RX VrefLevel [Byte0]: 57

 8711 13:54:41.277577                           [Byte1]: 57

 8712 13:54:41.282126  

 8713 13:54:41.282666  Set Vref, RX VrefLevel [Byte0]: 58

 8714 13:54:41.285289                           [Byte1]: 58

 8715 13:54:41.289444  

 8716 13:54:41.290004  Set Vref, RX VrefLevel [Byte0]: 59

 8717 13:54:41.292747                           [Byte1]: 59

 8718 13:54:41.297329  

 8719 13:54:41.297853  Set Vref, RX VrefLevel [Byte0]: 60

 8720 13:54:41.300137                           [Byte1]: 60

 8721 13:54:41.305017  

 8722 13:54:41.305545  Set Vref, RX VrefLevel [Byte0]: 61

 8723 13:54:41.307762                           [Byte1]: 61

 8724 13:54:41.312420  

 8725 13:54:41.312950  Set Vref, RX VrefLevel [Byte0]: 62

 8726 13:54:41.315538                           [Byte1]: 62

 8727 13:54:41.320226  

 8728 13:54:41.320756  Set Vref, RX VrefLevel [Byte0]: 63

 8729 13:54:41.323250                           [Byte1]: 63

 8730 13:54:41.327611  

 8731 13:54:41.328134  Set Vref, RX VrefLevel [Byte0]: 64

 8732 13:54:41.330893                           [Byte1]: 64

 8733 13:54:41.334809  

 8734 13:54:41.335336  Set Vref, RX VrefLevel [Byte0]: 65

 8735 13:54:41.338421                           [Byte1]: 65

 8736 13:54:41.342621  

 8737 13:54:41.343041  Set Vref, RX VrefLevel [Byte0]: 66

 8738 13:54:41.346324                           [Byte1]: 66

 8739 13:54:41.350097  

 8740 13:54:41.353368  Set Vref, RX VrefLevel [Byte0]: 67

 8741 13:54:41.356485                           [Byte1]: 67

 8742 13:54:41.357055  

 8743 13:54:41.359847  Set Vref, RX VrefLevel [Byte0]: 68

 8744 13:54:41.362852                           [Byte1]: 68

 8745 13:54:41.363351  

 8746 13:54:41.366449  Set Vref, RX VrefLevel [Byte0]: 69

 8747 13:54:41.369607                           [Byte1]: 69

 8748 13:54:41.370230  

 8749 13:54:41.373152  Set Vref, RX VrefLevel [Byte0]: 70

 8750 13:54:41.376238                           [Byte1]: 70

 8751 13:54:41.380412  

 8752 13:54:41.381018  Set Vref, RX VrefLevel [Byte0]: 71

 8753 13:54:41.383329                           [Byte1]: 71

 8754 13:54:41.388081  

 8755 13:54:41.388699  Set Vref, RX VrefLevel [Byte0]: 72

 8756 13:54:41.390925                           [Byte1]: 72

 8757 13:54:41.395765  

 8758 13:54:41.396330  Set Vref, RX VrefLevel [Byte0]: 73

 8759 13:54:41.398823                           [Byte1]: 73

 8760 13:54:41.402973  

 8761 13:54:41.403449  Final RX Vref Byte 0 = 59 to rank0

 8762 13:54:41.406869  Final RX Vref Byte 1 = 62 to rank0

 8763 13:54:41.409669  Final RX Vref Byte 0 = 59 to rank1

 8764 13:54:41.413156  Final RX Vref Byte 1 = 62 to rank1==

 8765 13:54:41.416262  Dram Type= 6, Freq= 0, CH_1, rank 0

 8766 13:54:41.423203  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8767 13:54:41.423772  ==

 8768 13:54:41.424141  DQS Delay:

 8769 13:54:41.424478  DQS0 = 0, DQS1 = 0

 8770 13:54:41.425983  DQM Delay:

 8771 13:54:41.426453  DQM0 = 135, DQM1 = 128

 8772 13:54:41.429753  DQ Delay:

 8773 13:54:41.433013  DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =132

 8774 13:54:41.436164  DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =132

 8775 13:54:41.439780  DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122

 8776 13:54:41.442760  DQ12 =138, DQ13 =134, DQ14 =134, DQ15 =136

 8777 13:54:41.443227  

 8778 13:54:41.443591  

 8779 13:54:41.443924  

 8780 13:54:41.446073  [DramC_TX_OE_Calibration] TA2

 8781 13:54:41.449425  Original DQ_B0 (3 6) =30, OEN = 27

 8782 13:54:41.452449  Original DQ_B1 (3 6) =30, OEN = 27

 8783 13:54:41.456297  24, 0x0, End_B0=24 End_B1=24

 8784 13:54:41.456873  25, 0x0, End_B0=25 End_B1=25

 8785 13:54:41.459214  26, 0x0, End_B0=26 End_B1=26

 8786 13:54:41.462557  27, 0x0, End_B0=27 End_B1=27

 8787 13:54:41.466172  28, 0x0, End_B0=28 End_B1=28

 8788 13:54:41.469490  29, 0x0, End_B0=29 End_B1=29

 8789 13:54:41.470113  30, 0x0, End_B0=30 End_B1=30

 8790 13:54:41.472736  31, 0x4545, End_B0=30 End_B1=30

 8791 13:54:41.475905  Byte0 end_step=30  best_step=27

 8792 13:54:41.479013  Byte1 end_step=30  best_step=27

 8793 13:54:41.482762  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8794 13:54:41.485913  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8795 13:54:41.486427  

 8796 13:54:41.486837  

 8797 13:54:41.492781  [DQSOSCAuto] RK0, (LSB)MR18= 0x1726, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 398 ps

 8798 13:54:41.496159  CH1 RK0: MR19=303, MR18=1726

 8799 13:54:41.502524  CH1_RK0: MR19=0x303, MR18=0x1726, DQSOSC=390, MR23=63, INC=24, DEC=16

 8800 13:54:41.503079  

 8801 13:54:41.506243  ----->DramcWriteLeveling(PI) begin...

 8802 13:54:41.506823  ==

 8803 13:54:41.509175  Dram Type= 6, Freq= 0, CH_1, rank 1

 8804 13:54:41.512646  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8805 13:54:41.513223  ==

 8806 13:54:41.515795  Write leveling (Byte 0): 24 => 24

 8807 13:54:41.519439  Write leveling (Byte 1): 30 => 30

 8808 13:54:41.522998  DramcWriteLeveling(PI) end<-----

 8809 13:54:41.523567  

 8810 13:54:41.523936  ==

 8811 13:54:41.525868  Dram Type= 6, Freq= 0, CH_1, rank 1

 8812 13:54:41.529305  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8813 13:54:41.529881  ==

 8814 13:54:41.532888  [Gating] SW mode calibration

 8815 13:54:41.539071  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8816 13:54:41.546086  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8817 13:54:41.549477   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8818 13:54:41.552660   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8819 13:54:41.559301   1  4  8 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)

 8820 13:54:41.562972   1  4 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)

 8821 13:54:41.565751   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8822 13:54:41.572674   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8823 13:54:41.575474   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8824 13:54:41.579232   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8825 13:54:41.585740   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8826 13:54:41.589148   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8827 13:54:41.592073   1  5  8 | B1->B0 | 2828 3434 | 1 1 | (1 0) (1 0)

 8828 13:54:41.598964   1  5 12 | B1->B0 | 2323 2d2d | 0 0 | (1 0) (1 0)

 8829 13:54:41.602242   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8830 13:54:41.605451   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8831 13:54:41.611869   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8832 13:54:41.615379   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8833 13:54:41.619108   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8834 13:54:41.625403   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8835 13:54:41.628758   1  6  8 | B1->B0 | 3939 2323 | 1 0 | (0 0) (0 0)

 8836 13:54:41.632189   1  6 12 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)

 8837 13:54:41.638920   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8838 13:54:41.642236   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8839 13:54:41.645499   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8840 13:54:41.652323   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8841 13:54:41.655681   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8842 13:54:41.658847   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8843 13:54:41.665664   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8844 13:54:41.668611   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8845 13:54:41.672322   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8846 13:54:41.675204   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8847 13:54:41.681817   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8848 13:54:41.685368   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8849 13:54:41.688473   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8850 13:54:41.695093   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8851 13:54:41.698528   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8852 13:54:41.701793   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8853 13:54:41.708731   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8854 13:54:41.711683   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8855 13:54:41.715561   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8856 13:54:41.721761   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8857 13:54:41.725568   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8858 13:54:41.728350   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8859 13:54:41.735096   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8860 13:54:41.738711   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8861 13:54:41.741776   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8862 13:54:41.745256  Total UI for P1: 0, mck2ui 16

 8863 13:54:41.748215  best dqsien dly found for B0: ( 1,  9, 10)

 8864 13:54:41.751569  Total UI for P1: 0, mck2ui 16

 8865 13:54:41.754934  best dqsien dly found for B1: ( 1,  9, 10)

 8866 13:54:41.758282  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8867 13:54:41.761553  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8868 13:54:41.762125  

 8869 13:54:41.768249  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8870 13:54:41.771969  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8871 13:54:41.775065  [Gating] SW calibration Done

 8872 13:54:41.775638  ==

 8873 13:54:41.778062  Dram Type= 6, Freq= 0, CH_1, rank 1

 8874 13:54:41.781787  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8875 13:54:41.782528  ==

 8876 13:54:41.782907  RX Vref Scan: 0

 8877 13:54:41.783246  

 8878 13:54:41.785177  RX Vref 0 -> 0, step: 1

 8879 13:54:41.785682  

 8880 13:54:41.787902  RX Delay 0 -> 252, step: 8

 8881 13:54:41.791449  iDelay=200, Bit 0, Center 143 (96 ~ 191) 96

 8882 13:54:41.795049  iDelay=200, Bit 1, Center 135 (88 ~ 183) 96

 8883 13:54:41.798427  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8884 13:54:41.804948  iDelay=200, Bit 3, Center 139 (88 ~ 191) 104

 8885 13:54:41.808457  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8886 13:54:41.811427  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8887 13:54:41.814792  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8888 13:54:41.817787  iDelay=200, Bit 7, Center 139 (88 ~ 191) 104

 8889 13:54:41.824538  iDelay=200, Bit 8, Center 115 (64 ~ 167) 104

 8890 13:54:41.828275  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 8891 13:54:41.831364  iDelay=200, Bit 10, Center 135 (80 ~ 191) 112

 8892 13:54:41.834469  iDelay=200, Bit 11, Center 127 (72 ~ 183) 112

 8893 13:54:41.837681  iDelay=200, Bit 12, Center 143 (88 ~ 199) 112

 8894 13:54:41.844762  iDelay=200, Bit 13, Center 139 (80 ~ 199) 120

 8895 13:54:41.847815  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8896 13:54:41.850988  iDelay=200, Bit 15, Center 143 (88 ~ 199) 112

 8897 13:54:41.851456  ==

 8898 13:54:41.854864  Dram Type= 6, Freq= 0, CH_1, rank 1

 8899 13:54:41.858155  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8900 13:54:41.861064  ==

 8901 13:54:41.861540  DQS Delay:

 8902 13:54:41.861911  DQS0 = 0, DQS1 = 0

 8903 13:54:41.864424  DQM Delay:

 8904 13:54:41.864999  DQM0 = 139, DQM1 = 133

 8905 13:54:41.867925  DQ Delay:

 8906 13:54:41.871224  DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139

 8907 13:54:41.874886  DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =139

 8908 13:54:41.878015  DQ8 =115, DQ9 =123, DQ10 =135, DQ11 =127

 8909 13:54:41.880955  DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143

 8910 13:54:41.881422  

 8911 13:54:41.881786  

 8912 13:54:41.882235  ==

 8913 13:54:41.884513  Dram Type= 6, Freq= 0, CH_1, rank 1

 8914 13:54:41.887414  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8915 13:54:41.887887  ==

 8916 13:54:41.888261  

 8917 13:54:41.891378  

 8918 13:54:41.891956  	TX Vref Scan disable

 8919 13:54:41.894674   == TX Byte 0 ==

 8920 13:54:41.897782  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8921 13:54:41.901171  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8922 13:54:41.904545   == TX Byte 1 ==

 8923 13:54:41.907710  Update DQ  dly =984 (3 ,6, 24)  DQ  OEN =(3 ,3)

 8924 13:54:41.910906  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8925 13:54:41.911381  ==

 8926 13:54:41.914526  Dram Type= 6, Freq= 0, CH_1, rank 1

 8927 13:54:41.921521  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8928 13:54:41.922309  ==

 8929 13:54:41.933048  

 8930 13:54:41.936328  TX Vref early break, caculate TX vref

 8931 13:54:41.939281  TX Vref=16, minBit 9, minWin=22, winSum=381

 8932 13:54:41.942716  TX Vref=18, minBit 9, minWin=23, winSum=392

 8933 13:54:41.946087  TX Vref=20, minBit 9, minWin=23, winSum=397

 8934 13:54:41.949412  TX Vref=22, minBit 15, minWin=23, winSum=408

 8935 13:54:41.952740  TX Vref=24, minBit 9, minWin=24, winSum=413

 8936 13:54:41.959534  TX Vref=26, minBit 9, minWin=25, winSum=423

 8937 13:54:41.962528  TX Vref=28, minBit 9, minWin=25, winSum=422

 8938 13:54:41.966265  TX Vref=30, minBit 9, minWin=25, winSum=414

 8939 13:54:41.969522  TX Vref=32, minBit 9, minWin=24, winSum=407

 8940 13:54:41.972818  TX Vref=34, minBit 10, minWin=23, winSum=398

 8941 13:54:41.979633  [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 26

 8942 13:54:41.980212  

 8943 13:54:41.982593  Final TX Range 0 Vref 26

 8944 13:54:41.983072  

 8945 13:54:41.983442  ==

 8946 13:54:41.986034  Dram Type= 6, Freq= 0, CH_1, rank 1

 8947 13:54:41.989240  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8948 13:54:41.989817  ==

 8949 13:54:41.990241  

 8950 13:54:41.990593  

 8951 13:54:41.992250  	TX Vref Scan disable

 8952 13:54:41.999203  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8953 13:54:41.999790   == TX Byte 0 ==

 8954 13:54:42.002424  u2DelayCellOfst[0]=16 cells (5 PI)

 8955 13:54:42.005788  u2DelayCellOfst[1]=10 cells (3 PI)

 8956 13:54:42.009431  u2DelayCellOfst[2]=0 cells (0 PI)

 8957 13:54:42.012527  u2DelayCellOfst[3]=3 cells (1 PI)

 8958 13:54:42.015853  u2DelayCellOfst[4]=6 cells (2 PI)

 8959 13:54:42.018869  u2DelayCellOfst[5]=16 cells (5 PI)

 8960 13:54:42.022306  u2DelayCellOfst[6]=16 cells (5 PI)

 8961 13:54:42.022779  u2DelayCellOfst[7]=3 cells (1 PI)

 8962 13:54:42.029075  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8963 13:54:42.032778  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8964 13:54:42.035593   == TX Byte 1 ==

 8965 13:54:42.036065  u2DelayCellOfst[8]=0 cells (0 PI)

 8966 13:54:42.038856  u2DelayCellOfst[9]=3 cells (1 PI)

 8967 13:54:42.042838  u2DelayCellOfst[10]=10 cells (3 PI)

 8968 13:54:42.045746  u2DelayCellOfst[11]=3 cells (1 PI)

 8969 13:54:42.049496  u2DelayCellOfst[12]=13 cells (4 PI)

 8970 13:54:42.052773  u2DelayCellOfst[13]=13 cells (4 PI)

 8971 13:54:42.055781  u2DelayCellOfst[14]=16 cells (5 PI)

 8972 13:54:42.058979  u2DelayCellOfst[15]=16 cells (5 PI)

 8973 13:54:42.062459  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8974 13:54:42.069175  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8975 13:54:42.069744  DramC Write-DBI on

 8976 13:54:42.070181  ==

 8977 13:54:42.072621  Dram Type= 6, Freq= 0, CH_1, rank 1

 8978 13:54:42.076143  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8979 13:54:42.076716  ==

 8980 13:54:42.079444  

 8981 13:54:42.080009  

 8982 13:54:42.080381  	TX Vref Scan disable

 8983 13:54:42.082601   == TX Byte 0 ==

 8984 13:54:42.085994  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8985 13:54:42.089326   == TX Byte 1 ==

 8986 13:54:42.092535  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 8987 13:54:42.093012  DramC Write-DBI off

 8988 13:54:42.095709  

 8989 13:54:42.096421  [DATLAT]

 8990 13:54:42.096822  Freq=1600, CH1 RK1

 8991 13:54:42.097178  

 8992 13:54:42.099047  DATLAT Default: 0xf

 8993 13:54:42.099523  0, 0xFFFF, sum = 0

 8994 13:54:42.102389  1, 0xFFFF, sum = 0

 8995 13:54:42.102869  2, 0xFFFF, sum = 0

 8996 13:54:42.105685  3, 0xFFFF, sum = 0

 8997 13:54:42.106324  4, 0xFFFF, sum = 0

 8998 13:54:42.109080  5, 0xFFFF, sum = 0

 8999 13:54:42.112164  6, 0xFFFF, sum = 0

 9000 13:54:42.112743  7, 0xFFFF, sum = 0

 9001 13:54:42.115672  8, 0xFFFF, sum = 0

 9002 13:54:42.116154  9, 0xFFFF, sum = 0

 9003 13:54:42.119326  10, 0xFFFF, sum = 0

 9004 13:54:42.119858  11, 0xFFFF, sum = 0

 9005 13:54:42.122019  12, 0xFFFF, sum = 0

 9006 13:54:42.122496  13, 0xFFFF, sum = 0

 9007 13:54:42.126051  14, 0x0, sum = 1

 9008 13:54:42.126644  15, 0x0, sum = 2

 9009 13:54:42.128950  16, 0x0, sum = 3

 9010 13:54:42.129429  17, 0x0, sum = 4

 9011 13:54:42.132207  best_step = 15

 9012 13:54:42.132776  

 9013 13:54:42.133148  ==

 9014 13:54:42.135725  Dram Type= 6, Freq= 0, CH_1, rank 1

 9015 13:54:42.138851  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9016 13:54:42.139426  ==

 9017 13:54:42.139800  RX Vref Scan: 0

 9018 13:54:42.142282  

 9019 13:54:42.142752  RX Vref 0 -> 0, step: 1

 9020 13:54:42.143128  

 9021 13:54:42.145630  RX Delay 19 -> 252, step: 4

 9022 13:54:42.148620  iDelay=195, Bit 0, Center 138 (95 ~ 182) 88

 9023 13:54:42.155553  iDelay=195, Bit 1, Center 132 (87 ~ 178) 92

 9024 13:54:42.158859  iDelay=195, Bit 2, Center 120 (71 ~ 170) 100

 9025 13:54:42.162259  iDelay=195, Bit 3, Center 132 (83 ~ 182) 100

 9026 13:54:42.165224  iDelay=195, Bit 4, Center 134 (87 ~ 182) 96

 9027 13:54:42.168603  iDelay=195, Bit 5, Center 144 (99 ~ 190) 92

 9028 13:54:42.172123  iDelay=195, Bit 6, Center 142 (95 ~ 190) 96

 9029 13:54:42.178633  iDelay=195, Bit 7, Center 134 (87 ~ 182) 96

 9030 13:54:42.182074  iDelay=195, Bit 8, Center 112 (63 ~ 162) 100

 9031 13:54:42.185296  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 9032 13:54:42.188636  iDelay=195, Bit 10, Center 130 (79 ~ 182) 104

 9033 13:54:42.191931  iDelay=195, Bit 11, Center 126 (75 ~ 178) 104

 9034 13:54:42.198337  iDelay=195, Bit 12, Center 138 (87 ~ 190) 104

 9035 13:54:42.201837  iDelay=195, Bit 13, Center 136 (83 ~ 190) 108

 9036 13:54:42.205231  iDelay=195, Bit 14, Center 136 (87 ~ 186) 100

 9037 13:54:42.208282  iDelay=195, Bit 15, Center 140 (87 ~ 194) 108

 9038 13:54:42.208757  ==

 9039 13:54:42.211687  Dram Type= 6, Freq= 0, CH_1, rank 1

 9040 13:54:42.218173  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9041 13:54:42.218652  ==

 9042 13:54:42.219093  DQS Delay:

 9043 13:54:42.221774  DQS0 = 0, DQS1 = 0

 9044 13:54:42.222291  DQM Delay:

 9045 13:54:42.225477  DQM0 = 134, DQM1 = 129

 9046 13:54:42.225985  DQ Delay:

 9047 13:54:42.228223  DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132

 9048 13:54:42.231635  DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134

 9049 13:54:42.234677  DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126

 9050 13:54:42.238107  DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =140

 9051 13:54:42.238597  

 9052 13:54:42.238963  

 9053 13:54:42.239307  

 9054 13:54:42.241492  [DramC_TX_OE_Calibration] TA2

 9055 13:54:42.244868  Original DQ_B0 (3 6) =30, OEN = 27

 9056 13:54:42.248099  Original DQ_B1 (3 6) =30, OEN = 27

 9057 13:54:42.251705  24, 0x0, End_B0=24 End_B1=24

 9058 13:54:42.252182  25, 0x0, End_B0=25 End_B1=25

 9059 13:54:42.255166  26, 0x0, End_B0=26 End_B1=26

 9060 13:54:42.258339  27, 0x0, End_B0=27 End_B1=27

 9061 13:54:42.261530  28, 0x0, End_B0=28 End_B1=28

 9062 13:54:42.264922  29, 0x0, End_B0=29 End_B1=29

 9063 13:54:42.265505  30, 0x0, End_B0=30 End_B1=30

 9064 13:54:42.268418  31, 0x5151, End_B0=30 End_B1=30

 9065 13:54:42.271549  Byte0 end_step=30  best_step=27

 9066 13:54:42.274538  Byte1 end_step=30  best_step=27

 9067 13:54:42.278564  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9068 13:54:42.281571  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9069 13:54:42.282161  

 9070 13:54:42.282532  

 9071 13:54:42.288272  [DQSOSCAuto] RK1, (LSB)MR18= 0x1a05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps

 9072 13:54:42.291194  CH1 RK1: MR19=303, MR18=1A05

 9073 13:54:42.298285  CH1_RK1: MR19=0x303, MR18=0x1A05, DQSOSC=396, MR23=63, INC=23, DEC=15

 9074 13:54:42.301614  [RxdqsGatingPostProcess] freq 1600

 9075 13:54:42.304816  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9076 13:54:42.307795  best DQS0 dly(2T, 0.5T) = (1, 1)

 9077 13:54:42.311134  best DQS1 dly(2T, 0.5T) = (1, 1)

 9078 13:54:42.314648  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9079 13:54:42.318054  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9080 13:54:42.321166  best DQS0 dly(2T, 0.5T) = (1, 1)

 9081 13:54:42.324767  best DQS1 dly(2T, 0.5T) = (1, 1)

 9082 13:54:42.327790  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9083 13:54:42.331303  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9084 13:54:42.335073  Pre-setting of DQS Precalculation

 9085 13:54:42.338843  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9086 13:54:42.344850  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9087 13:54:42.351430  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9088 13:54:42.354863  

 9089 13:54:42.355425  

 9090 13:54:42.355844  [Calibration Summary] 3200 Mbps

 9091 13:54:42.358254  CH 0, Rank 0

 9092 13:54:42.358822  SW Impedance     : PASS

 9093 13:54:42.361874  DUTY Scan        : NO K

 9094 13:54:42.364835  ZQ Calibration   : PASS

 9095 13:54:42.365307  Jitter Meter     : NO K

 9096 13:54:42.368453  CBT Training     : PASS

 9097 13:54:42.371635  Write leveling   : PASS

 9098 13:54:42.372213  RX DQS gating    : PASS

 9099 13:54:42.374791  RX DQ/DQS(RDDQC) : PASS

 9100 13:54:42.378164  TX DQ/DQS        : PASS

 9101 13:54:42.378733  RX DATLAT        : PASS

 9102 13:54:42.381718  RX DQ/DQS(Engine): PASS

 9103 13:54:42.384683  TX OE            : PASS

 9104 13:54:42.385253  All Pass.

 9105 13:54:42.385625  

 9106 13:54:42.386001  CH 0, Rank 1

 9107 13:54:42.388292  SW Impedance     : PASS

 9108 13:54:42.391304  DUTY Scan        : NO K

 9109 13:54:42.391774  ZQ Calibration   : PASS

 9110 13:54:42.394610  Jitter Meter     : NO K

 9111 13:54:42.398035  CBT Training     : PASS

 9112 13:54:42.398606  Write leveling   : PASS

 9113 13:54:42.401072  RX DQS gating    : PASS

 9114 13:54:42.401544  RX DQ/DQS(RDDQC) : PASS

 9115 13:54:42.405072  TX DQ/DQS        : PASS

 9116 13:54:42.407928  RX DATLAT        : PASS

 9117 13:54:42.408398  RX DQ/DQS(Engine): PASS

 9118 13:54:42.411311  TX OE            : PASS

 9119 13:54:42.411781  All Pass.

 9120 13:54:42.412223  

 9121 13:54:42.414684  CH 1, Rank 0

 9122 13:54:42.415155  SW Impedance     : PASS

 9123 13:54:42.418136  DUTY Scan        : NO K

 9124 13:54:42.420927  ZQ Calibration   : PASS

 9125 13:54:42.421395  Jitter Meter     : NO K

 9126 13:54:42.424311  CBT Training     : PASS

 9127 13:54:42.427954  Write leveling   : PASS

 9128 13:54:42.428424  RX DQS gating    : PASS

 9129 13:54:42.431280  RX DQ/DQS(RDDQC) : PASS

 9130 13:54:42.434403  TX DQ/DQS        : PASS

 9131 13:54:42.434874  RX DATLAT        : PASS

 9132 13:54:42.437632  RX DQ/DQS(Engine): PASS

 9133 13:54:42.440975  TX OE            : PASS

 9134 13:54:42.441448  All Pass.

 9135 13:54:42.441810  

 9136 13:54:42.442211  CH 1, Rank 1

 9137 13:54:42.444411  SW Impedance     : PASS

 9138 13:54:42.447557  DUTY Scan        : NO K

 9139 13:54:42.448024  ZQ Calibration   : PASS

 9140 13:54:42.450989  Jitter Meter     : NO K

 9141 13:54:42.451558  CBT Training     : PASS

 9142 13:54:42.454616  Write leveling   : PASS

 9143 13:54:42.457492  RX DQS gating    : PASS

 9144 13:54:42.457993  RX DQ/DQS(RDDQC) : PASS

 9145 13:54:42.460945  TX DQ/DQS        : PASS

 9146 13:54:42.464108  RX DATLAT        : PASS

 9147 13:54:42.464587  RX DQ/DQS(Engine): PASS

 9148 13:54:42.467906  TX OE            : PASS

 9149 13:54:42.468476  All Pass.

 9150 13:54:42.468848  

 9151 13:54:42.471233  DramC Write-DBI on

 9152 13:54:42.474221  	PER_BANK_REFRESH: Hybrid Mode

 9153 13:54:42.474692  TX_TRACKING: ON

 9154 13:54:42.484001  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9155 13:54:42.490845  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9156 13:54:42.497713  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9157 13:54:42.503981  [FAST_K] Save calibration result to emmc

 9158 13:54:42.504558  sync common calibartion params.

 9159 13:54:42.507796  sync cbt_mode0:1, 1:1

 9160 13:54:42.510571  dram_init: ddr_geometry: 2

 9161 13:54:42.511043  dram_init: ddr_geometry: 2

 9162 13:54:42.514016  dram_init: ddr_geometry: 2

 9163 13:54:42.517645  0:dram_rank_size:100000000

 9164 13:54:42.520830  1:dram_rank_size:100000000

 9165 13:54:42.524550  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9166 13:54:42.527566  DFS_SHUFFLE_HW_MODE: ON

 9167 13:54:42.530356  dramc_set_vcore_voltage set vcore to 725000

 9168 13:54:42.534289  Read voltage for 1600, 0

 9169 13:54:42.534858  Vio18 = 0

 9170 13:54:42.535229  Vcore = 725000

 9171 13:54:42.537212  Vdram = 0

 9172 13:54:42.537682  Vddq = 0

 9173 13:54:42.538098  Vmddr = 0

 9174 13:54:42.540391  switch to 3200 Mbps bootup

 9175 13:54:42.543859  [DramcRunTimeConfig]

 9176 13:54:42.544331  PHYPLL

 9177 13:54:42.544698  DPM_CONTROL_AFTERK: ON

 9178 13:54:42.547212  PER_BANK_REFRESH: ON

 9179 13:54:42.550613  REFRESH_OVERHEAD_REDUCTION: ON

 9180 13:54:42.551269  CMD_PICG_NEW_MODE: OFF

 9181 13:54:42.554679  XRTWTW_NEW_MODE: ON

 9182 13:54:42.557344  XRTRTR_NEW_MODE: ON

 9183 13:54:42.557912  TX_TRACKING: ON

 9184 13:54:42.561009  RDSEL_TRACKING: OFF

 9185 13:54:42.561579  DQS Precalculation for DVFS: ON

 9186 13:54:42.564053  RX_TRACKING: OFF

 9187 13:54:42.564522  HW_GATING DBG: ON

 9188 13:54:42.567335  ZQCS_ENABLE_LP4: ON

 9189 13:54:42.567805  RX_PICG_NEW_MODE: ON

 9190 13:54:42.570735  TX_PICG_NEW_MODE: ON

 9191 13:54:42.574314  ENABLE_RX_DCM_DPHY: ON

 9192 13:54:42.577413  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9193 13:54:42.578000  DUMMY_READ_FOR_TRACKING: OFF

 9194 13:54:42.580564  !!! SPM_CONTROL_AFTERK: OFF

 9195 13:54:42.584198  !!! SPM could not control APHY

 9196 13:54:42.587292  IMPEDANCE_TRACKING: ON

 9197 13:54:42.587857  TEMP_SENSOR: ON

 9198 13:54:42.590872  HW_SAVE_FOR_SR: OFF

 9199 13:54:42.591443  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9200 13:54:42.597156  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9201 13:54:42.597723  Read ODT Tracking: ON

 9202 13:54:42.600842  Refresh Rate DeBounce: ON

 9203 13:54:42.601409  DFS_NO_QUEUE_FLUSH: ON

 9204 13:54:42.603700  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9205 13:54:42.607590  ENABLE_DFS_RUNTIME_MRW: OFF

 9206 13:54:42.610635  DDR_RESERVE_NEW_MODE: ON

 9207 13:54:42.611135  MR_CBT_SWITCH_FREQ: ON

 9208 13:54:42.613581  =========================

 9209 13:54:42.633565  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9210 13:54:42.636694  dram_init: ddr_geometry: 2

 9211 13:54:42.654771  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9212 13:54:42.658231  dram_init: dram init end (result: 0)

 9213 13:54:42.664632  DRAM-K: Full calibration passed in 24483 msecs

 9214 13:54:42.668405  MRC: failed to locate region type 0.

 9215 13:54:42.668974  DRAM rank0 size:0x100000000,

 9216 13:54:42.671039  DRAM rank1 size=0x100000000

 9217 13:54:42.681374  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9218 13:54:42.688019  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9219 13:54:42.694845  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9220 13:54:42.701290  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9221 13:54:42.704570  DRAM rank0 size:0x100000000,

 9222 13:54:42.708190  DRAM rank1 size=0x100000000

 9223 13:54:42.708755  CBMEM:

 9224 13:54:42.711476  IMD: root @ 0xfffff000 254 entries.

 9225 13:54:42.714624  IMD: root @ 0xffffec00 62 entries.

 9226 13:54:42.718102  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9227 13:54:42.721360  WARNING: RO_VPD is uninitialized or empty.

 9228 13:54:42.727616  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9229 13:54:42.734812  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9230 13:54:42.747336  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9231 13:54:42.759118  BS: romstage times (exec / console): total (unknown) / 23985 ms

 9232 13:54:42.759707  

 9233 13:54:42.760236  

 9234 13:54:42.769134  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9235 13:54:42.772150  ARM64: Exception handlers installed.

 9236 13:54:42.775500  ARM64: Testing exception

 9237 13:54:42.778659  ARM64: Done test exception

 9238 13:54:42.779132  Enumerating buses...

 9239 13:54:42.782647  Show all devs... Before device enumeration.

 9240 13:54:42.785697  Root Device: enabled 1

 9241 13:54:42.788896  CPU_CLUSTER: 0: enabled 1

 9242 13:54:42.789473  CPU: 00: enabled 1

 9243 13:54:42.791807  Compare with tree...

 9244 13:54:42.792278  Root Device: enabled 1

 9245 13:54:42.795335   CPU_CLUSTER: 0: enabled 1

 9246 13:54:42.799191    CPU: 00: enabled 1

 9247 13:54:42.799757  Root Device scanning...

 9248 13:54:42.802320  scan_static_bus for Root Device

 9249 13:54:42.805530  CPU_CLUSTER: 0 enabled

 9250 13:54:42.808725  scan_static_bus for Root Device done

 9251 13:54:42.812489  scan_bus: bus Root Device finished in 8 msecs

 9252 13:54:42.813061  done

 9253 13:54:42.818511  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9254 13:54:42.821924  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9255 13:54:42.828689  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9256 13:54:42.832019  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9257 13:54:42.835143  Allocating resources...

 9258 13:54:42.838223  Reading resources...

 9259 13:54:42.841846  Root Device read_resources bus 0 link: 0

 9260 13:54:42.842365  DRAM rank0 size:0x100000000,

 9261 13:54:42.845478  DRAM rank1 size=0x100000000

 9262 13:54:42.848113  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9263 13:54:42.851639  CPU: 00 missing read_resources

 9264 13:54:42.858318  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9265 13:54:42.861239  Root Device read_resources bus 0 link: 0 done

 9266 13:54:42.861710  Done reading resources.

 9267 13:54:42.868357  Show resources in subtree (Root Device)...After reading.

 9268 13:54:42.871650   Root Device child on link 0 CPU_CLUSTER: 0

 9269 13:54:42.874866    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9270 13:54:42.885019    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9271 13:54:42.885597     CPU: 00

 9272 13:54:42.888385  Root Device assign_resources, bus 0 link: 0

 9273 13:54:42.891287  CPU_CLUSTER: 0 missing set_resources

 9274 13:54:42.898312  Root Device assign_resources, bus 0 link: 0 done

 9275 13:54:42.898883  Done setting resources.

 9276 13:54:42.904715  Show resources in subtree (Root Device)...After assigning values.

 9277 13:54:42.908290   Root Device child on link 0 CPU_CLUSTER: 0

 9278 13:54:42.911173    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9279 13:54:42.921179    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9280 13:54:42.921750     CPU: 00

 9281 13:54:42.924806  Done allocating resources.

 9282 13:54:42.927978  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9283 13:54:42.931024  Enabling resources...

 9284 13:54:42.931493  done.

 9285 13:54:42.938084  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9286 13:54:42.938654  Initializing devices...

 9287 13:54:42.941349  Root Device init

 9288 13:54:42.942018  init hardware done!

 9289 13:54:42.944542  0x00000018: ctrlr->caps

 9290 13:54:42.947872  52.000 MHz: ctrlr->f_max

 9291 13:54:42.948377  0.400 MHz: ctrlr->f_min

 9292 13:54:42.950918  0x40ff8080: ctrlr->voltages

 9293 13:54:42.954448  sclk: 390625

 9294 13:54:42.955066  Bus Width = 1

 9295 13:54:42.955442  sclk: 390625

 9296 13:54:42.957670  Bus Width = 1

 9297 13:54:42.958158  Early init status = 3

 9298 13:54:42.964065  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9299 13:54:42.967614  in-header: 03 fc 00 00 01 00 00 00 

 9300 13:54:42.970546  in-data: 00 

 9301 13:54:42.974447  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9302 13:54:42.977705  in-header: 03 fd 00 00 00 00 00 00 

 9303 13:54:42.981365  in-data: 

 9304 13:54:42.984352  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9305 13:54:42.987932  in-header: 03 fc 00 00 01 00 00 00 

 9306 13:54:42.990951  in-data: 00 

 9307 13:54:42.994679  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9308 13:54:42.999716  in-header: 03 fd 00 00 00 00 00 00 

 9309 13:54:43.002975  in-data: 

 9310 13:54:43.006309  [SSUSB] Setting up USB HOST controller...

 9311 13:54:43.010070  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9312 13:54:43.012949  [SSUSB] phy power-on done.

 9313 13:54:43.016082  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9314 13:54:43.022804  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9315 13:54:43.026045  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9316 13:54:43.032935  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9317 13:54:43.039351  read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps

 9318 13:54:43.046452  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9319 13:54:43.052892  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9320 13:54:43.059553  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9321 13:54:43.063056  SPM: binary array size = 0x9dc

 9322 13:54:43.065980  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9323 13:54:43.072510  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9324 13:54:43.079419  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9325 13:54:43.082358  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9326 13:54:43.089220  configure_display: Starting display init

 9327 13:54:43.123293  anx7625_power_on_init: Init interface.

 9328 13:54:43.126468  anx7625_disable_pd_protocol: Disabled PD feature.

 9329 13:54:43.129403  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9330 13:54:43.157643  anx7625_start_dp_work: Secure OCM version=00

 9331 13:54:43.160396  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9332 13:54:43.175283  sp_tx_get_edid_block: EDID Block = 1

 9333 13:54:43.278330  Extracted contents:

 9334 13:54:43.281261  header:          00 ff ff ff ff ff ff 00

 9335 13:54:43.284552  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9336 13:54:43.287956  version:         01 04

 9337 13:54:43.291513  basic params:    95 1f 11 78 0a

 9338 13:54:43.294528  chroma info:     76 90 94 55 54 90 27 21 50 54

 9339 13:54:43.298033  established:     00 00 00

 9340 13:54:43.304475  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9341 13:54:43.308104  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9342 13:54:43.314437  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9343 13:54:43.321363  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9344 13:54:43.328232  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9345 13:54:43.331039  extensions:      00

 9346 13:54:43.331606  checksum:        fb

 9347 13:54:43.331982  

 9348 13:54:43.334505  Manufacturer: IVO Model 57d Serial Number 0

 9349 13:54:43.337852  Made week 0 of 2020

 9350 13:54:43.338457  EDID version: 1.4

 9351 13:54:43.341234  Digital display

 9352 13:54:43.344299  6 bits per primary color channel

 9353 13:54:43.344876  DisplayPort interface

 9354 13:54:43.347596  Maximum image size: 31 cm x 17 cm

 9355 13:54:43.350855  Gamma: 220%

 9356 13:54:43.351326  Check DPMS levels

 9357 13:54:43.354476  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9358 13:54:43.357450  First detailed timing is preferred timing

 9359 13:54:43.360970  Established timings supported:

 9360 13:54:43.363863  Standard timings supported:

 9361 13:54:43.367503  Detailed timings

 9362 13:54:43.370558  Hex of detail: 383680a07038204018303c0035ae10000019

 9363 13:54:43.374000  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9364 13:54:43.380432                 0780 0798 07c8 0820 hborder 0

 9365 13:54:43.384095                 0438 043b 0447 0458 vborder 0

 9366 13:54:43.387344                 -hsync -vsync

 9367 13:54:43.387761  Did detailed timing

 9368 13:54:43.394062  Hex of detail: 000000000000000000000000000000000000

 9369 13:54:43.394482  Manufacturer-specified data, tag 0

 9370 13:54:43.400908  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9371 13:54:43.403839  ASCII string: InfoVision

 9372 13:54:43.406986  Hex of detail: 000000fe00523134304e574635205248200a

 9373 13:54:43.410790  ASCII string: R140NWF5 RH 

 9374 13:54:43.411109  Checksum

 9375 13:54:43.413983  Checksum: 0xfb (valid)

 9376 13:54:43.416913  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9377 13:54:43.420347  DSI data_rate: 832800000 bps

 9378 13:54:43.427108  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9379 13:54:43.430274  anx7625_parse_edid: pixelclock(138800).

 9380 13:54:43.433668   hactive(1920), hsync(48), hfp(24), hbp(88)

 9381 13:54:43.437101   vactive(1080), vsync(12), vfp(3), vbp(17)

 9382 13:54:43.440363  anx7625_dsi_config: config dsi.

 9383 13:54:43.446926  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9384 13:54:43.459908  anx7625_dsi_config: success to config DSI

 9385 13:54:43.463579  anx7625_dp_start: MIPI phy setup OK.

 9386 13:54:43.466798  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9387 13:54:43.469648  mtk_ddp_mode_set invalid vrefresh 60

 9388 13:54:43.473279  main_disp_path_setup

 9389 13:54:43.473830  ovl_layer_smi_id_en

 9390 13:54:43.476276  ovl_layer_smi_id_en

 9391 13:54:43.476732  ccorr_config

 9392 13:54:43.477090  aal_config

 9393 13:54:43.480225  gamma_config

 9394 13:54:43.480824  postmask_config

 9395 13:54:43.482994  dither_config

 9396 13:54:43.486640  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9397 13:54:43.493439                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9398 13:54:43.496336  Root Device init finished in 552 msecs

 9399 13:54:43.499763  CPU_CLUSTER: 0 init

 9400 13:54:43.506066  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9401 13:54:43.512691  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9402 13:54:43.513308  APU_MBOX 0x190000b0 = 0x10001

 9403 13:54:43.516267  APU_MBOX 0x190001b0 = 0x10001

 9404 13:54:43.519255  APU_MBOX 0x190005b0 = 0x10001

 9405 13:54:43.522823  APU_MBOX 0x190006b0 = 0x10001

 9406 13:54:43.529306  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9407 13:54:43.539430  read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps

 9408 13:54:43.551166  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9409 13:54:43.558328  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9410 13:54:43.569861  read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps

 9411 13:54:43.579061  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9412 13:54:43.581782  CPU_CLUSTER: 0 init finished in 81 msecs

 9413 13:54:43.585651  Devices initialized

 9414 13:54:43.588860  Show all devs... After init.

 9415 13:54:43.589438  Root Device: enabled 1

 9416 13:54:43.592440  CPU_CLUSTER: 0: enabled 1

 9417 13:54:43.595479  CPU: 00: enabled 1

 9418 13:54:43.598715  BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms

 9419 13:54:43.602064  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9420 13:54:43.605273  ELOG: NV offset 0x57f000 size 0x1000

 9421 13:54:43.612052  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9422 13:54:43.618875  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9423 13:54:43.622068  ELOG: Event(17) added with size 13 at 2024-02-01 13:54:03 UTC

 9424 13:54:43.625700  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9425 13:54:43.628927  in-header: 03 46 00 00 2c 00 00 00 

 9426 13:54:43.642560  in-data: 19 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9427 13:54:43.648877  ELOG: Event(A1) added with size 10 at 2024-02-01 13:54:03 UTC

 9428 13:54:43.655906  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9429 13:54:43.662347  ELOG: Event(A0) added with size 9 at 2024-02-01 13:54:03 UTC

 9430 13:54:43.665909  elog_add_boot_reason: Logged dev mode boot

 9431 13:54:43.668744  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9432 13:54:43.672307  Finalize devices...

 9433 13:54:43.672776  Devices finalized

 9434 13:54:43.678710  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9435 13:54:43.682150  Writing coreboot table at 0xffe64000

 9436 13:54:43.685400   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9437 13:54:43.688926   1. 0000000040000000-00000000400fffff: RAM

 9438 13:54:43.692257   2. 0000000040100000-000000004032afff: RAMSTAGE

 9439 13:54:43.698884   3. 000000004032b000-00000000545fffff: RAM

 9440 13:54:43.702230   4. 0000000054600000-000000005465ffff: BL31

 9441 13:54:43.705402   5. 0000000054660000-00000000ffe63fff: RAM

 9442 13:54:43.708765   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9443 13:54:43.715537   7. 0000000100000000-000000023fffffff: RAM

 9444 13:54:43.716114  Passing 5 GPIOs to payload:

 9445 13:54:43.722231              NAME |       PORT | POLARITY |     VALUE

 9446 13:54:43.725435          EC in RW | 0x000000aa |      low | undefined

 9447 13:54:43.732230      EC interrupt | 0x00000005 |      low | undefined

 9448 13:54:43.735403     TPM interrupt | 0x000000ab |     high | undefined

 9449 13:54:43.738506    SD card detect | 0x00000011 |     high | undefined

 9450 13:54:43.745341    speaker enable | 0x00000093 |     high | undefined

 9451 13:54:43.748598  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9452 13:54:43.752407  in-header: 03 f9 00 00 02 00 00 00 

 9453 13:54:43.752986  in-data: 02 00 

 9454 13:54:43.755375  ADC[4]: Raw value=901770 ID=7

 9455 13:54:43.758844  ADC[3]: Raw value=213179 ID=1

 9456 13:54:43.759420  RAM Code: 0x71

 9457 13:54:43.761711  ADC[6]: Raw value=74502 ID=0

 9458 13:54:43.765514  ADC[5]: Raw value=212810 ID=1

 9459 13:54:43.766159  SKU Code: 0x1

 9460 13:54:43.772373  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4f3d

 9461 13:54:43.775407  coreboot table: 964 bytes.

 9462 13:54:43.778396  IMD ROOT    0. 0xfffff000 0x00001000

 9463 13:54:43.781831  IMD SMALL   1. 0xffffe000 0x00001000

 9464 13:54:43.785448  RO MCACHE   2. 0xffffc000 0x00001104

 9465 13:54:43.788447  CONSOLE     3. 0xfff7c000 0x00080000

 9466 13:54:43.792147  FMAP        4. 0xfff7b000 0x00000452

 9467 13:54:43.795029  TIME STAMP  5. 0xfff7a000 0x00000910

 9468 13:54:43.798284  VBOOT WORK  6. 0xfff66000 0x00014000

 9469 13:54:43.801901  RAMOOPS     7. 0xffe66000 0x00100000

 9470 13:54:43.805044  COREBOOT    8. 0xffe64000 0x00002000

 9471 13:54:43.805513  IMD small region:

 9472 13:54:43.808160    IMD ROOT    0. 0xffffec00 0x00000400

 9473 13:54:43.811544    VPD         1. 0xffffeb80 0x0000006c

 9474 13:54:43.815309    MMC STATUS  2. 0xffffeb60 0x00000004

 9475 13:54:43.821573  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9476 13:54:43.822183  Probing TPM:  done!

 9477 13:54:43.828929  Connected to device vid:did:rid of 1ae0:0028:00

 9478 13:54:43.838631  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9479 13:54:43.842588  Initialized TPM device CR50 revision 0

 9480 13:54:43.843059  Checking cr50 for pending updates

 9481 13:54:43.848328  Reading cr50 TPM mode

 9482 13:54:43.857372  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9483 13:54:43.863715  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9484 13:54:43.903676  read SPI 0x3990ec 0x4f1b0: 34853 us, 9296 KB/s, 74.368 Mbps

 9485 13:54:43.907098  Checking segment from ROM address 0x40100000

 9486 13:54:43.910709  Checking segment from ROM address 0x4010001c

 9487 13:54:43.917382  Loading segment from ROM address 0x40100000

 9488 13:54:43.918006    code (compression=0)

 9489 13:54:43.927404    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9490 13:54:43.933890  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9491 13:54:43.934506  it's not compressed!

 9492 13:54:43.940354  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9493 13:54:43.944295  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9494 13:54:43.964597  Loading segment from ROM address 0x4010001c

 9495 13:54:43.965165    Entry Point 0x80000000

 9496 13:54:43.967878  Loaded segments

 9497 13:54:43.970978  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9498 13:54:43.978330  Jumping to boot code at 0x80000000(0xffe64000)

 9499 13:54:43.984331  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9500 13:54:43.991140  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9501 13:54:43.998751  read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps

 9502 13:54:44.002123  Checking segment from ROM address 0x40100000

 9503 13:54:44.005348  Checking segment from ROM address 0x4010001c

 9504 13:54:44.011996  Loading segment from ROM address 0x40100000

 9505 13:54:44.012644    code (compression=1)

 9506 13:54:44.018620    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9507 13:54:44.029073  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9508 13:54:44.029658  using LZMA

 9509 13:54:44.037289  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9510 13:54:44.043406  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9511 13:54:44.047002  Loading segment from ROM address 0x4010001c

 9512 13:54:44.047572    Entry Point 0x54601000

 9513 13:54:44.050177  Loaded segments

 9514 13:54:44.053271  NOTICE:  MT8192 bl31_setup

 9515 13:54:44.060720  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9516 13:54:44.064190  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9517 13:54:44.067618  WARNING: region 0:

 9518 13:54:44.070709  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9519 13:54:44.071278  WARNING: region 1:

 9520 13:54:44.077812  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9521 13:54:44.080634  WARNING: region 2:

 9522 13:54:44.084350  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9523 13:54:44.087595  WARNING: region 3:

 9524 13:54:44.090783  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9525 13:54:44.094373  WARNING: region 4:

 9526 13:54:44.097698  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9527 13:54:44.100772  WARNING: region 5:

 9528 13:54:44.104337  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9529 13:54:44.107309  WARNING: region 6:

 9530 13:54:44.111388  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9531 13:54:44.111961  WARNING: region 7:

 9532 13:54:44.117580  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9533 13:54:44.124378  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9534 13:54:44.127698  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9535 13:54:44.130874  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9536 13:54:44.137682  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9537 13:54:44.140866  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9538 13:54:44.144170  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9539 13:54:44.151038  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9540 13:54:44.154636  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9541 13:54:44.157888  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9542 13:54:44.164417  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9543 13:54:44.168169  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9544 13:54:44.171151  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9545 13:54:44.177930  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9546 13:54:44.180761  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9547 13:54:44.187820  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9548 13:54:44.191159  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9549 13:54:44.194548  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9550 13:54:44.200920  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9551 13:54:44.204241  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9552 13:54:44.207405  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9553 13:54:44.214592  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9554 13:54:44.217874  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9555 13:54:44.224558  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9556 13:54:44.227545  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9557 13:54:44.230661  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9558 13:54:44.237800  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9559 13:54:44.241031  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9560 13:54:44.248163  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9561 13:54:44.250952  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9562 13:54:44.254375  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9563 13:54:44.260922  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9564 13:54:44.264334  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9565 13:54:44.268174  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9566 13:54:44.274128  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9567 13:54:44.277302  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9568 13:54:44.280890  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9569 13:54:44.284354  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9570 13:54:44.290677  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9571 13:54:44.293906  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9572 13:54:44.297840  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9573 13:54:44.300946  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9574 13:54:44.307165  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9575 13:54:44.310763  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9576 13:54:44.314261  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9577 13:54:44.317658  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9578 13:54:44.324107  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9579 13:54:44.327302  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9580 13:54:44.330852  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9581 13:54:44.337812  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9582 13:54:44.341136  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9583 13:54:44.344158  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9584 13:54:44.350849  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9585 13:54:44.354408  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9586 13:54:44.360850  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9587 13:54:44.364167  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9588 13:54:44.370936  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9589 13:54:44.374075  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9590 13:54:44.380910  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9591 13:54:44.383964  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9592 13:54:44.387500  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9593 13:54:44.394273  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9594 13:54:44.397366  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9595 13:54:44.404165  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9596 13:54:44.407457  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9597 13:54:44.414536  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9598 13:54:44.417713  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9599 13:54:44.420719  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9600 13:54:44.427280  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9601 13:54:44.430685  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9602 13:54:44.437859  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9603 13:54:44.441149  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9604 13:54:44.444369  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9605 13:54:44.451206  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9606 13:54:44.454312  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9607 13:54:44.461044  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9608 13:54:44.464643  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9609 13:54:44.471234  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9610 13:54:44.474534  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9611 13:54:44.481283  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9612 13:54:44.484596  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9613 13:54:44.487850  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9614 13:54:44.494632  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9615 13:54:44.497863  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9616 13:54:44.504113  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9617 13:54:44.507654  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9618 13:54:44.514203  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9619 13:54:44.517317  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9620 13:54:44.520859  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9621 13:54:44.527328  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9622 13:54:44.530892  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9623 13:54:44.537498  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9624 13:54:44.540708  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9625 13:54:44.547547  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9626 13:54:44.550871  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9627 13:54:44.554048  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9628 13:54:44.561092  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9629 13:54:44.564371  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9630 13:54:44.567392  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9631 13:54:44.574266  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9632 13:54:44.577393  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9633 13:54:44.580864  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9634 13:54:44.588028  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9635 13:54:44.590830  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9636 13:54:44.594234  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9637 13:54:44.600950  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9638 13:54:44.604290  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9639 13:54:44.611091  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9640 13:54:44.614076  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9641 13:54:44.617677  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9642 13:54:44.624033  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9643 13:54:44.627776  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9644 13:54:44.634195  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9645 13:54:44.637473  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9646 13:54:44.641054  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9647 13:54:44.647596  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9648 13:54:44.650723  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9649 13:54:44.653909  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9650 13:54:44.661059  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9651 13:54:44.664280  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9652 13:54:44.667603  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9653 13:54:44.670788  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9654 13:54:44.677026  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9655 13:54:44.680895  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9656 13:54:44.684306  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9657 13:54:44.690817  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9658 13:54:44.694094  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9659 13:54:44.697333  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9660 13:54:44.704099  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9661 13:54:44.707377  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9662 13:54:44.714326  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9663 13:54:44.717354  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9664 13:54:44.720367  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9665 13:54:44.727478  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9666 13:54:44.730757  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9667 13:54:44.737642  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9668 13:54:44.740786  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9669 13:54:44.744351  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9670 13:54:44.750947  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9671 13:54:44.754052  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9672 13:54:44.757624  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9673 13:54:44.764480  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9674 13:54:44.768276  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9675 13:54:44.774676  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9676 13:54:44.777660  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9677 13:54:44.781308  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9678 13:54:44.787862  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9679 13:54:44.791366  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9680 13:54:44.794771  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9681 13:54:44.801501  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9682 13:54:44.804384  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9683 13:54:44.811361  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9684 13:54:44.814569  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9685 13:54:44.818112  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9686 13:54:44.824885  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9687 13:54:44.827763  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9688 13:54:44.830853  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9689 13:54:44.838104  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9690 13:54:44.841242  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9691 13:54:44.847946  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9692 13:54:44.850550  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9693 13:54:44.854160  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9694 13:54:44.861209  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9695 13:54:44.864647  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9696 13:54:44.870694  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9697 13:54:44.874093  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9698 13:54:44.877392  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9699 13:54:44.884123  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9700 13:54:44.887668  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9701 13:54:44.894151  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9702 13:54:44.897377  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9703 13:54:44.900529  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9704 13:54:44.907234  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9705 13:54:44.910601  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9706 13:54:44.917571  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9707 13:54:44.920370  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9708 13:54:44.924168  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9709 13:54:44.930389  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9710 13:54:44.933396  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9711 13:54:44.940396  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9712 13:54:44.943749  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9713 13:54:44.946959  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9714 13:54:44.953276  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9715 13:54:44.957026  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9716 13:54:44.963502  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9717 13:54:44.966679  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9718 13:54:44.970242  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9719 13:54:44.976603  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9720 13:54:44.979860  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9721 13:54:44.986479  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9722 13:54:44.990330  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9723 13:54:44.993087  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9724 13:54:45.000097  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9725 13:54:45.003288  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9726 13:54:45.010085  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9727 13:54:45.013350  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9728 13:54:45.016525  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9729 13:54:45.022862  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9730 13:54:45.026255  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9731 13:54:45.033051  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9732 13:54:45.036298  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9733 13:54:45.042740  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9734 13:54:45.046387  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9735 13:54:45.049763  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9736 13:54:45.056142  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9737 13:54:45.059106  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9738 13:54:45.066609  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9739 13:54:45.069379  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9740 13:54:45.072885  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9741 13:54:45.079145  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9742 13:54:45.082459  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9743 13:54:45.089448  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9744 13:54:45.092799  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9745 13:54:45.099238  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9746 13:54:45.102472  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9747 13:54:45.106196  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9748 13:54:45.112462  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9749 13:54:45.116060  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9750 13:54:45.122399  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9751 13:54:45.125772  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9752 13:54:45.132423  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9753 13:54:45.135586  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9754 13:54:45.139058  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9755 13:54:45.145675  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9756 13:54:45.149374  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9757 13:54:45.155410  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9758 13:54:45.158959  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9759 13:54:45.162469  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9760 13:54:45.169054  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9761 13:54:45.172505  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9762 13:54:45.175633  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9763 13:54:45.182133  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9764 13:54:45.185688  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9765 13:54:45.189205  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9766 13:54:45.192181  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9767 13:54:45.199036  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9768 13:54:45.201749  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9769 13:54:45.208364  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9770 13:54:45.212339  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9771 13:54:45.215090  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9772 13:54:45.221606  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9773 13:54:45.225131  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9774 13:54:45.228149  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9775 13:54:45.235256  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9776 13:54:45.238549  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9777 13:54:45.241453  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9778 13:54:45.248662  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9779 13:54:45.251540  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9780 13:54:45.258419  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9781 13:54:45.261983  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9782 13:54:45.265281  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9783 13:54:45.272020  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9784 13:54:45.274945  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9785 13:54:45.278546  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9786 13:54:45.285150  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9787 13:54:45.288542  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9788 13:54:45.291668  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9789 13:54:45.298023  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9790 13:54:45.301304  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9791 13:54:45.308159  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9792 13:54:45.311553  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9793 13:54:45.315179  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9794 13:54:45.321550  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9795 13:54:45.324933  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9796 13:54:45.328026  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9797 13:54:45.334902  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9798 13:54:45.337928  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9799 13:54:45.344786  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9800 13:54:45.348061  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9801 13:54:45.351521  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9802 13:54:45.354535  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9803 13:54:45.361586  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9804 13:54:45.364714  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9805 13:54:45.368507  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9806 13:54:45.371313  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9807 13:54:45.375011  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9808 13:54:45.381609  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9809 13:54:45.384871  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9810 13:54:45.388157  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9811 13:54:45.391384  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9812 13:54:45.397984  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9813 13:54:45.401395  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9814 13:54:45.404502  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9815 13:54:45.411388  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9816 13:54:45.414464  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9817 13:54:45.421049  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9818 13:54:45.424697  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9819 13:54:45.428139  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9820 13:54:45.434771  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9821 13:54:45.438267  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9822 13:54:45.444220  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9823 13:54:45.448218  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9824 13:54:45.451112  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9825 13:54:45.457916  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9826 13:54:45.460962  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9827 13:54:45.467822  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9828 13:54:45.471295  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9829 13:54:45.477644  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9830 13:54:45.481242  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9831 13:54:45.484226  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9832 13:54:45.490834  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9833 13:54:45.494297  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9834 13:54:45.500724  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9835 13:54:45.504136  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9836 13:54:45.507226  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9837 13:54:45.514552  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9838 13:54:45.517451  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9839 13:54:45.523822  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9840 13:54:45.527325  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9841 13:54:45.530940  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9842 13:54:45.537638  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9843 13:54:45.541022  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9844 13:54:45.547242  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9845 13:54:45.551080  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9846 13:54:45.553999  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9847 13:54:45.560970  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9848 13:54:45.563869  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9849 13:54:45.570625  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9850 13:54:45.573772  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9851 13:54:45.580438  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9852 13:54:45.583883  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9853 13:54:45.587307  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9854 13:54:45.593894  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9855 13:54:45.597132  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9856 13:54:45.603642  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9857 13:54:45.607213  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9858 13:54:45.610148  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9859 13:54:45.616812  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9860 13:54:45.619924  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9861 13:54:45.626648  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9862 13:54:45.629684  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9863 13:54:45.633357  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9864 13:54:45.639815  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9865 13:54:45.643239  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9866 13:54:45.650057  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9867 13:54:45.653096  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9868 13:54:45.659867  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9869 13:54:45.663297  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9870 13:54:45.666661  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9871 13:54:45.672957  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9872 13:54:45.676586  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9873 13:54:45.682675  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9874 13:54:45.686228  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9875 13:54:45.693177  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9876 13:54:45.696264  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9877 13:54:45.699741  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9878 13:54:45.706628  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9879 13:54:45.709477  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9880 13:54:45.713164  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9881 13:54:45.719332  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9882 13:54:45.722773  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9883 13:54:45.729275  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9884 13:54:45.732775  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9885 13:54:45.739372  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9886 13:54:45.742392  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9887 13:54:45.745842  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9888 13:54:45.752740  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9889 13:54:45.755904  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9890 13:54:45.762379  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9891 13:54:45.765856  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9892 13:54:45.772261  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9893 13:54:45.775833  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9894 13:54:45.779256  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9895 13:54:45.785788  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9896 13:54:45.789102  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9897 13:54:45.795906  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9898 13:54:45.798883  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9899 13:54:45.805994  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9900 13:54:45.808817  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9901 13:54:45.815834  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9902 13:54:45.819199  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9903 13:54:45.822509  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9904 13:54:45.829109  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9905 13:54:45.831960  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9906 13:54:45.838990  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9907 13:54:45.842053  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9908 13:54:45.848812  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9909 13:54:45.852012  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9910 13:54:45.855567  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9911 13:54:45.862055  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9912 13:54:45.865126  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9913 13:54:45.872327  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9914 13:54:45.875696  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9915 13:54:45.882085  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9916 13:54:45.885486  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9917 13:54:45.889087  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9918 13:54:45.895716  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9919 13:54:45.898657  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9920 13:54:45.905754  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9921 13:54:45.909145  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9922 13:54:45.915256  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9923 13:54:45.918474  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9924 13:54:45.925149  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9925 13:54:45.928755  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9926 13:54:45.931821  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9927 13:54:45.938504  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9928 13:54:45.941735  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9929 13:54:45.948240  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9930 13:54:45.951624  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9931 13:54:45.958269  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9932 13:54:45.961517  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9933 13:54:45.965018  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9934 13:54:45.971583  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9935 13:54:45.975248  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9936 13:54:45.978583  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9937 13:54:45.984962  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9938 13:54:45.988319  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9939 13:54:45.994958  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9940 13:54:45.998369  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9941 13:54:46.004570  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9942 13:54:46.007777  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9943 13:54:46.014849  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9944 13:54:46.018210  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9945 13:54:46.025058  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9946 13:54:46.028162  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9947 13:54:46.034334  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9948 13:54:46.037864  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9949 13:54:46.044319  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9950 13:54:46.047326  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9951 13:54:46.054390  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9952 13:54:46.057554  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9953 13:54:46.064434  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9954 13:54:46.067171  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9955 13:54:46.074078  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9956 13:54:46.077467  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9957 13:54:46.084008  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9958 13:54:46.087220  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9959 13:54:46.093711  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9960 13:54:46.097112  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9961 13:54:46.103518  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9962 13:54:46.106798  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9963 13:54:46.113630  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9964 13:54:46.117017  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9965 13:54:46.123556  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9966 13:54:46.126900  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9967 13:54:46.133153  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9968 13:54:46.133728  INFO:    [APUAPC] vio 0

 9969 13:54:46.140536  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9970 13:54:46.144117  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9971 13:54:46.146888  INFO:    [APUAPC] D0_APC_0: 0x400510

 9972 13:54:46.150554  INFO:    [APUAPC] D0_APC_1: 0x0

 9973 13:54:46.153424  INFO:    [APUAPC] D0_APC_2: 0x1540

 9974 13:54:46.156734  INFO:    [APUAPC] D0_APC_3: 0x0

 9975 13:54:46.160343  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9976 13:54:46.163600  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9977 13:54:46.166731  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9978 13:54:46.170058  INFO:    [APUAPC] D1_APC_3: 0x0

 9979 13:54:46.173750  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9980 13:54:46.177179  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9981 13:54:46.180288  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9982 13:54:46.183712  INFO:    [APUAPC] D2_APC_3: 0x0

 9983 13:54:46.186715  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9984 13:54:46.190398  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9985 13:54:46.193462  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9986 13:54:46.196954  INFO:    [APUAPC] D3_APC_3: 0x0

 9987 13:54:46.200202  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9988 13:54:46.203487  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9989 13:54:46.206733  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9990 13:54:46.207205  INFO:    [APUAPC] D4_APC_3: 0x0

 9991 13:54:46.209997  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9992 13:54:46.217099  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9993 13:54:46.217670  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9994 13:54:46.220644  INFO:    [APUAPC] D5_APC_3: 0x0

 9995 13:54:46.224059  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9996 13:54:46.227232  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9997 13:54:46.230602  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9998 13:54:46.233523  INFO:    [APUAPC] D6_APC_3: 0x0

 9999 13:54:46.236502  INFO:    [APUAPC] D7_APC_0: 0xffffffff

10000 13:54:46.240085  INFO:    [APUAPC] D7_APC_1: 0xffffffff

10001 13:54:46.242839  INFO:    [APUAPC] D7_APC_2: 0x3fffff

10002 13:54:46.246153  INFO:    [APUAPC] D7_APC_3: 0x0

10003 13:54:46.249637  INFO:    [APUAPC] D8_APC_0: 0xffffffff

10004 13:54:46.253062  INFO:    [APUAPC] D8_APC_1: 0xffffffff

10005 13:54:46.256470  INFO:    [APUAPC] D8_APC_2: 0x3fffff

10006 13:54:46.259953  INFO:    [APUAPC] D8_APC_3: 0x0

10007 13:54:46.263153  INFO:    [APUAPC] D9_APC_0: 0xffffffff

10008 13:54:46.266526  INFO:    [APUAPC] D9_APC_1: 0xffffffff

10009 13:54:46.270197  INFO:    [APUAPC] D9_APC_2: 0x3fffff

10010 13:54:46.273033  INFO:    [APUAPC] D9_APC_3: 0x0

10011 13:54:46.277195  INFO:    [APUAPC] D10_APC_0: 0xffffffff

10012 13:54:46.279764  INFO:    [APUAPC] D10_APC_1: 0xffffffff

10013 13:54:46.283159  INFO:    [APUAPC] D10_APC_2: 0x3fffff

10014 13:54:46.286656  INFO:    [APUAPC] D10_APC_3: 0x0

10015 13:54:46.289782  INFO:    [APUAPC] D11_APC_0: 0xffffffff

10016 13:54:46.292980  INFO:    [APUAPC] D11_APC_1: 0xffffffff

10017 13:54:46.296785  INFO:    [APUAPC] D11_APC_2: 0x3fffff

10018 13:54:46.299821  INFO:    [APUAPC] D11_APC_3: 0x0

10019 13:54:46.303038  INFO:    [APUAPC] D12_APC_0: 0xffffffff

10020 13:54:46.306457  INFO:    [APUAPC] D12_APC_1: 0xffffffff

10021 13:54:46.310036  INFO:    [APUAPC] D12_APC_2: 0x3fffff

10022 13:54:46.313594  INFO:    [APUAPC] D12_APC_3: 0x0

10023 13:54:46.316807  INFO:    [APUAPC] D13_APC_0: 0xffffffff

10024 13:54:46.320413  INFO:    [APUAPC] D13_APC_1: 0xffffffff

10025 13:54:46.323235  INFO:    [APUAPC] D13_APC_2: 0x3fffff

10026 13:54:46.326799  INFO:    [APUAPC] D13_APC_3: 0x0

10027 13:54:46.329556  INFO:    [APUAPC] D14_APC_0: 0xffffffff

10028 13:54:46.333354  INFO:    [APUAPC] D14_APC_1: 0xffffffff

10029 13:54:46.336319  INFO:    [APUAPC] D14_APC_2: 0x3fffff

10030 13:54:46.339764  INFO:    [APUAPC] D14_APC_3: 0x0

10031 13:54:46.342856  INFO:    [APUAPC] D15_APC_0: 0xffffffff

10032 13:54:46.346349  INFO:    [APUAPC] D15_APC_1: 0xffffffff

10033 13:54:46.349518  INFO:    [APUAPC] D15_APC_2: 0x3fffff

10034 13:54:46.353173  INFO:    [APUAPC] D15_APC_3: 0x0

10035 13:54:46.356309  INFO:    [APUAPC] APC_CON: 0x4

10036 13:54:46.359652  INFO:    [NOCDAPC] D0_APC_0: 0x0

10037 13:54:46.362906  INFO:    [NOCDAPC] D0_APC_1: 0x0

10038 13:54:46.366896  INFO:    [NOCDAPC] D1_APC_0: 0x0

10039 13:54:46.369847  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10040 13:54:46.370416  INFO:    [NOCDAPC] D2_APC_0: 0x0

10041 13:54:46.373242  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10042 13:54:46.376481  INFO:    [NOCDAPC] D3_APC_0: 0x0

10043 13:54:46.379629  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10044 13:54:46.382745  INFO:    [NOCDAPC] D4_APC_0: 0x0

10045 13:54:46.386047  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10046 13:54:46.389467  INFO:    [NOCDAPC] D5_APC_0: 0x0

10047 13:54:46.392993  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10048 13:54:46.396219  INFO:    [NOCDAPC] D6_APC_0: 0x0

10049 13:54:46.399326  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10050 13:54:46.402796  INFO:    [NOCDAPC] D7_APC_0: 0x0

10051 13:54:46.403224  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10052 13:54:46.406078  INFO:    [NOCDAPC] D8_APC_0: 0x0

10053 13:54:46.409173  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10054 13:54:46.412728  INFO:    [NOCDAPC] D9_APC_0: 0x0

10055 13:54:46.416308  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10056 13:54:46.419304  INFO:    [NOCDAPC] D10_APC_0: 0x0

10057 13:54:46.422957  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10058 13:54:46.426518  INFO:    [NOCDAPC] D11_APC_0: 0x0

10059 13:54:46.429681  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10060 13:54:46.432707  INFO:    [NOCDAPC] D12_APC_0: 0x0

10061 13:54:46.436093  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10062 13:54:46.439296  INFO:    [NOCDAPC] D13_APC_0: 0x0

10063 13:54:46.442716  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10064 13:54:46.443147  INFO:    [NOCDAPC] D14_APC_0: 0x0

10065 13:54:46.446103  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10066 13:54:46.449298  INFO:    [NOCDAPC] D15_APC_0: 0x0

10067 13:54:46.453125  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10068 13:54:46.456266  INFO:    [NOCDAPC] APC_CON: 0x4

10069 13:54:46.459428  INFO:    [APUAPC] set_apusys_apc done

10070 13:54:46.462784  INFO:    [DEVAPC] devapc_init done

10071 13:54:46.465774  INFO:    GICv3 without legacy support detected.

10072 13:54:46.472544  INFO:    ARM GICv3 driver initialized in EL3

10073 13:54:46.475775  INFO:    Maximum SPI INTID supported: 639

10074 13:54:46.479032  INFO:    BL31: Initializing runtime services

10075 13:54:46.486114  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10076 13:54:46.486708  INFO:    SPM: enable CPC mode

10077 13:54:46.492782  INFO:    mcdi ready for mcusys-off-idle and system suspend

10078 13:54:46.496156  INFO:    BL31: Preparing for EL3 exit to normal world

10079 13:54:46.502094  INFO:    Entry point address = 0x80000000

10080 13:54:46.502567  INFO:    SPSR = 0x8

10081 13:54:46.508566  

10082 13:54:46.509127  

10083 13:54:46.509528  

10084 13:54:46.511724  Starting depthcharge on Spherion...

10085 13:54:46.512192  

10086 13:54:46.512561  Wipe memory regions:

10087 13:54:46.512969  

10088 13:54:46.515612  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10089 13:54:46.516170  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10090 13:54:46.516627  Setting prompt string to ['asurada:']
10091 13:54:46.517061  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10092 13:54:46.517837  	[0x00000040000000, 0x00000054600000)

10093 13:54:46.637794  

10094 13:54:46.638402  	[0x00000054660000, 0x00000080000000)

10095 13:54:46.898200  

10096 13:54:46.898763  	[0x000000821a7280, 0x000000ffe64000)

10097 13:54:47.643200  

10098 13:54:47.643766  	[0x00000100000000, 0x00000240000000)

10099 13:54:49.533852  

10100 13:54:49.536766  Initializing XHCI USB controller at 0x11200000.

10101 13:54:50.574557  

10102 13:54:50.577802  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10103 13:54:50.578456  

10104 13:54:50.578837  

10105 13:54:50.579183  

10106 13:54:50.579979  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10108 13:54:50.681175  asurada: tftpboot 192.168.201.1 12682923/tftp-deploy-7f8pea4e/kernel/image.itb 12682923/tftp-deploy-7f8pea4e/kernel/cmdline 

10109 13:54:50.681840  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10110 13:54:50.682376  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10111 13:54:50.686929  tftpboot 192.168.201.1 12682923/tftp-deploy-7f8pea4e/kernel/image.ittp-deploy-7f8pea4e/kernel/cmdline 

10112 13:54:50.687492  

10113 13:54:50.687866  Waiting for link

10114 13:54:50.847362  

10115 13:54:50.847929  R8152: Initializing

10116 13:54:50.848369  

10117 13:54:50.850623  Version 9 (ocp_data = 6010)

10118 13:54:50.851096  

10119 13:54:50.853504  R8152: Done initializing

10120 13:54:50.854194  

10121 13:54:50.854790  Adding net device

10122 13:54:52.795657  

10123 13:54:52.796210  done.

10124 13:54:52.796592  

10125 13:54:52.796947  MAC: 00:e0:4c:72:2d:d6

10126 13:54:52.797293  

10127 13:54:52.799041  Sending DHCP discover... done.

10128 13:54:52.799487  

10129 13:54:56.201535  Waiting for reply... done.

10130 13:54:56.202148  

10131 13:54:56.202521  Sending DHCP request... done.

10132 13:54:56.204817  

10133 13:54:56.212240  Waiting for reply... done.

10134 13:54:56.212795  

10135 13:54:56.213149  My ip is 192.168.201.21

10136 13:54:56.213478  

10137 13:54:56.215655  The DHCP server ip is 192.168.201.1

10138 13:54:56.216212  

10139 13:54:56.222390  TFTP server IP predefined by user: 192.168.201.1

10140 13:54:56.222963  

10141 13:54:56.228899  Bootfile predefined by user: 12682923/tftp-deploy-7f8pea4e/kernel/image.itb

10142 13:54:56.229470  

10143 13:54:56.231785  Sending tftp read request... done.

10144 13:54:56.232241  

10145 13:54:56.237021  Waiting for the transfer... 

10146 13:54:56.237568  

10147 13:54:56.501397  00000000 ################################################################

10148 13:54:56.501536  

10149 13:54:56.752725  00080000 ################################################################

10150 13:54:56.752877  

10151 13:54:57.027543  00100000 ################################################################

10152 13:54:57.027676  

10153 13:54:57.290908  00180000 ################################################################

10154 13:54:57.291061  

10155 13:54:57.576218  00200000 ################################################################

10156 13:54:57.576352  

10157 13:54:57.841501  00280000 ################################################################

10158 13:54:57.841639  

10159 13:54:58.088254  00300000 ################################################################

10160 13:54:58.088372  

10161 13:54:58.345060  00380000 ################################################################

10162 13:54:58.345184  

10163 13:54:58.603318  00400000 ################################################################

10164 13:54:58.603443  

10165 13:54:58.854458  00480000 ################################################################

10166 13:54:58.854600  

10167 13:54:59.103833  00500000 ################################################################

10168 13:54:59.103955  

10169 13:54:59.382953  00580000 ################################################################

10170 13:54:59.383090  

10171 13:54:59.676875  00600000 ################################################################

10172 13:54:59.677008  

10173 13:54:59.961104  00680000 ################################################################

10174 13:54:59.961257  

10175 13:55:00.255086  00700000 ################################################################

10176 13:55:00.255227  

10177 13:55:00.540570  00780000 ################################################################

10178 13:55:00.540715  

10179 13:55:00.820223  00800000 ################################################################

10180 13:55:00.820378  

10181 13:55:01.097187  00880000 ################################################################

10182 13:55:01.097352  

10183 13:55:01.367319  00900000 ################################################################

10184 13:55:01.367452  

10185 13:55:01.632265  00980000 ################################################################

10186 13:55:01.632400  

10187 13:55:01.905775  00a00000 ################################################################

10188 13:55:01.905919  

10189 13:55:02.188758  00a80000 ################################################################

10190 13:55:02.188940  

10191 13:55:02.461759  00b00000 ################################################################

10192 13:55:02.461896  

10193 13:55:02.738504  00b80000 ################################################################

10194 13:55:02.738642  

10195 13:55:03.018542  00c00000 ################################################################

10196 13:55:03.018692  

10197 13:55:03.298666  00c80000 ################################################################

10198 13:55:03.298818  

10199 13:55:03.558340  00d00000 ################################################################

10200 13:55:03.558466  

10201 13:55:03.819532  00d80000 ################################################################

10202 13:55:03.819676  

10203 13:55:04.090907  00e00000 ################################################################

10204 13:55:04.091060  

10205 13:55:04.387062  00e80000 ################################################################

10206 13:55:04.387196  

10207 13:55:04.640732  00f00000 ################################################################

10208 13:55:04.640887  

10209 13:55:04.890087  00f80000 ################################################################

10210 13:55:04.890209  

10211 13:55:05.154860  01000000 ################################################################

10212 13:55:05.155002  

10213 13:55:05.415771  01080000 ################################################################

10214 13:55:05.415914  

10215 13:55:05.710696  01100000 ################################################################

10216 13:55:05.710828  

10217 13:55:06.002194  01180000 ################################################################

10218 13:55:06.002335  

10219 13:55:06.295036  01200000 ################################################################

10220 13:55:06.295174  

10221 13:55:06.556028  01280000 ################################################################

10222 13:55:06.556158  

10223 13:55:06.804898  01300000 ################################################################

10224 13:55:06.805025  

10225 13:55:07.071644  01380000 ################################################################

10226 13:55:07.071769  

10227 13:55:07.366566  01400000 ################################################################

10228 13:55:07.366701  

10229 13:55:07.661354  01480000 ################################################################

10230 13:55:07.661484  

10231 13:55:07.957208  01500000 ################################################################

10232 13:55:07.957333  

10233 13:55:08.249540  01580000 ################################################################

10234 13:55:08.249675  

10235 13:55:08.529741  01600000 ################################################################

10236 13:55:08.529873  

10237 13:55:08.802366  01680000 ################################################################

10238 13:55:08.802505  

10239 13:55:09.084705  01700000 ################################################################

10240 13:55:09.084858  

10241 13:55:09.333593  01780000 ################################################################

10242 13:55:09.333729  

10243 13:55:09.610300  01800000 ################################################################

10244 13:55:09.610438  

10245 13:55:09.900347  01880000 ################################################################

10246 13:55:09.900487  

10247 13:55:10.186531  01900000 ################################################################

10248 13:55:10.186671  

10249 13:55:10.467821  01980000 ################################################################

10250 13:55:10.467969  

10251 13:55:10.731911  01a00000 ################################################################

10252 13:55:10.732059  

10253 13:55:11.006688  01a80000 ################################################################

10254 13:55:11.006838  

10255 13:55:11.293122  01b00000 ################################################################

10256 13:55:11.293253  

10257 13:55:11.559898  01b80000 ################################################################

10258 13:55:11.560049  

10259 13:55:11.817417  01c00000 ################################################################

10260 13:55:11.817546  

10261 13:55:11.826246  01c80000 ### done.

10262 13:55:11.826329  

10263 13:55:11.829451  The bootfile was 29902154 bytes long.

10264 13:55:11.829538  

10265 13:55:11.833014  Sending tftp read request... done.

10266 13:55:11.833194  

10267 13:55:11.836429  Waiting for the transfer... 

10268 13:55:11.836606  

10269 13:55:11.836690  00000000 # done.

10270 13:55:11.836767  

10271 13:55:11.843302  Command line loaded dynamically from TFTP file: 12682923/tftp-deploy-7f8pea4e/kernel/cmdline

10272 13:55:11.846285  

10273 13:55:11.866433  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682923/extract-nfsrootfs-dxzindgm,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10274 13:55:11.866696  

10275 13:55:11.866842  Loading FIT.

10276 13:55:11.866971  

10277 13:55:11.869642  Image ramdisk-1 has 17805982 bytes.

10278 13:55:11.869923  

10279 13:55:11.873316  Image fdt-1 has 47278 bytes.

10280 13:55:11.873635  

10281 13:55:11.876500  Image kernel-1 has 12046857 bytes.

10282 13:55:11.876837  

10283 13:55:11.886824  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10284 13:55:11.887298  

10285 13:55:11.903350  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10286 13:55:11.903953  

10287 13:55:11.910043  Choosing best match conf-1 for compat google,spherion-rev2.

10288 13:55:11.910610  

10289 13:55:11.917500  Connected to device vid:did:rid of 1ae0:0028:00

10290 13:55:11.925572  

10291 13:55:11.929274  tpm_get_response: command 0x17b, return code 0x0

10292 13:55:11.929849  

10293 13:55:11.935712  ec_init: CrosEC protocol v3 supported (256, 248)

10294 13:55:11.936283  

10295 13:55:11.938822  tpm_cleanup: add release locality here.

10296 13:55:11.939295  

10297 13:55:11.942425  Shutting down all USB controllers.

10298 13:55:11.942890  

10299 13:55:11.945326  Removing current net device

10300 13:55:11.945789  

10301 13:55:11.948954  Exiting depthcharge with code 4 at timestamp: 54718839

10302 13:55:11.949423  

10303 13:55:11.952189  LZMA decompressing kernel-1 to 0x821a6718

10304 13:55:11.955826  

10305 13:55:11.958766  LZMA decompressing kernel-1 to 0x40000000

10306 13:55:13.458624  

10307 13:55:13.459203  jumping to kernel

10308 13:55:13.460904  end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10309 13:55:13.461422  start: 2.2.5 auto-login-action (timeout 00:03:58) [common]
10310 13:55:13.461828  Setting prompt string to ['Linux version [0-9]']
10311 13:55:13.462245  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10312 13:55:13.462620  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10313 13:55:13.540322  

10314 13:55:13.543559  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10315 13:55:13.547365  start: 2.2.5.1 login-action (timeout 00:03:58) [common]
10316 13:55:13.547936  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10317 13:55:13.548335  Setting prompt string to []
10318 13:55:13.548738  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10319 13:55:13.549120  Using line separator: #'\n'#
10320 13:55:13.549450  No login prompt set.
10321 13:55:13.549795  Parsing kernel messages
10322 13:55:13.550143  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10323 13:55:13.550704  [login-action] Waiting for messages, (timeout 00:03:58)
10324 13:55:13.566719  [    0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb  1 13:35:47 UTC 2024

10325 13:55:13.570117  [    0.000000] random: crng init done

10326 13:55:13.576775  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10327 13:55:13.580085  [    0.000000] efi: UEFI not found.

10328 13:55:13.586608  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10329 13:55:13.593291  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10330 13:55:13.602934  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10331 13:55:13.613367  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10332 13:55:13.619900  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10333 13:55:13.626589  [    0.000000] printk: bootconsole [mtk8250] enabled

10334 13:55:13.633434  [    0.000000] NUMA: No NUMA configuration found

10335 13:55:13.639821  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10336 13:55:13.643329  [    0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]

10337 13:55:13.646362  [    0.000000] Zone ranges:

10338 13:55:13.653013  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10339 13:55:13.656294  [    0.000000]   DMA32    empty

10340 13:55:13.662870  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10341 13:55:13.666356  [    0.000000] Movable zone start for each node

10342 13:55:13.669645  [    0.000000] Early memory node ranges

10343 13:55:13.676520  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10344 13:55:13.682724  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10345 13:55:13.689328  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10346 13:55:13.695978  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10347 13:55:13.699325  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10348 13:55:13.709190  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10349 13:55:13.765386  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10350 13:55:13.771827  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10351 13:55:13.778475  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10352 13:55:13.781727  [    0.000000] psci: probing for conduit method from DT.

10353 13:55:13.788239  [    0.000000] psci: PSCIv1.1 detected in firmware.

10354 13:55:13.791765  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10355 13:55:13.798346  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10356 13:55:13.801354  [    0.000000] psci: SMC Calling Convention v1.2

10357 13:55:13.808212  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10358 13:55:13.811783  [    0.000000] Detected VIPT I-cache on CPU0

10359 13:55:13.818075  [    0.000000] CPU features: detected: GIC system register CPU interface

10360 13:55:13.825170  [    0.000000] CPU features: detected: Virtualization Host Extensions

10361 13:55:13.831251  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10362 13:55:13.838107  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10363 13:55:13.844420  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10364 13:55:13.854310  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10365 13:55:13.857835  [    0.000000] alternatives: applying boot alternatives

10366 13:55:13.864403  [    0.000000] Fallback order for Node 0: 0 

10367 13:55:13.871272  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10368 13:55:13.874420  [    0.000000] Policy zone: Normal

10369 13:55:13.897618  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12682923/extract-nfsrootfs-dxzindgm,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10370 13:55:13.907650  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10371 13:55:13.917720  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10372 13:55:13.927891  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10373 13:55:13.934489  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10374 13:55:13.937917  <6>[    0.000000] software IO TLB: area num 8.

10375 13:55:13.993663  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10376 13:55:14.142811  <6>[    0.000000] Memory: 7949864K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402904K reserved, 32768K cma-reserved)

10377 13:55:14.149700  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10378 13:55:14.155999  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10379 13:55:14.159320  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10380 13:55:14.166006  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10381 13:55:14.172943  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10382 13:55:14.176293  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10383 13:55:14.185791  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10384 13:55:14.192480  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10385 13:55:14.198989  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10386 13:55:14.205711  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10387 13:55:14.208921  <6>[    0.000000] GICv3: 608 SPIs implemented

10388 13:55:14.212288  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10389 13:55:14.218683  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10390 13:55:14.222346  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10391 13:55:14.228704  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10392 13:55:14.241921  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10393 13:55:14.251739  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10394 13:55:14.261755  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10395 13:55:14.269028  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10396 13:55:14.282660  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10397 13:55:14.289340  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10398 13:55:14.295466  <6>[    0.009178] Console: colour dummy device 80x25

10399 13:55:14.305912  <6>[    0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10400 13:55:14.312764  <6>[    0.024410] pid_max: default: 32768 minimum: 301

10401 13:55:14.315686  <6>[    0.029293] LSM: Security Framework initializing

10402 13:55:14.322854  <6>[    0.034232] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10403 13:55:14.332305  <6>[    0.042046] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10404 13:55:14.338702  <6>[    0.051464] cblist_init_generic: Setting adjustable number of callback queues.

10405 13:55:14.345753  <6>[    0.058906] cblist_init_generic: Setting shift to 3 and lim to 1.

10406 13:55:14.355629  <6>[    0.065246] cblist_init_generic: Setting adjustable number of callback queues.

10407 13:55:14.358932  <6>[    0.072673] cblist_init_generic: Setting shift to 3 and lim to 1.

10408 13:55:14.365468  <6>[    0.079076] rcu: Hierarchical SRCU implementation.

10409 13:55:14.372631  <6>[    0.084091] rcu: 	Max phase no-delay instances is 1000.

10410 13:55:14.379146  <6>[    0.091146] EFI services will not be available.

10411 13:55:14.382210  <6>[    0.096104] smp: Bringing up secondary CPUs ...

10412 13:55:14.390168  <6>[    0.101156] Detected VIPT I-cache on CPU1

10413 13:55:14.396925  <6>[    0.101225] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10414 13:55:14.403230  <6>[    0.101255] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10415 13:55:14.406666  <6>[    0.101584] Detected VIPT I-cache on CPU2

10416 13:55:14.413522  <6>[    0.101632] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10417 13:55:14.420193  <6>[    0.101647] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10418 13:55:14.427092  <6>[    0.101903] Detected VIPT I-cache on CPU3

10419 13:55:14.433566  <6>[    0.101948] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10420 13:55:14.440208  <6>[    0.101962] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10421 13:55:14.443224  <6>[    0.102264] CPU features: detected: Spectre-v4

10422 13:55:14.450546  <6>[    0.102271] CPU features: detected: Spectre-BHB

10423 13:55:14.453507  <6>[    0.102276] Detected PIPT I-cache on CPU4

10424 13:55:14.460542  <6>[    0.102333] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10425 13:55:14.466744  <6>[    0.102349] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10426 13:55:14.470265  <6>[    0.102639] Detected PIPT I-cache on CPU5

10427 13:55:14.479610  <6>[    0.102701] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10428 13:55:14.486507  <6>[    0.102718] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10429 13:55:14.489988  <6>[    0.102996] Detected PIPT I-cache on CPU6

10430 13:55:14.496689  <6>[    0.103060] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10431 13:55:14.503207  <6>[    0.103079] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10432 13:55:14.506682  <6>[    0.103379] Detected PIPT I-cache on CPU7

10433 13:55:14.516603  <6>[    0.103443] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10434 13:55:14.523161  <6>[    0.103459] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10435 13:55:14.526597  <6>[    0.103506] smp: Brought up 1 node, 8 CPUs

10436 13:55:14.532960  <6>[    0.244857] SMP: Total of 8 processors activated.

10437 13:55:14.536868  <6>[    0.249809] CPU features: detected: 32-bit EL0 Support

10438 13:55:14.546227  <6>[    0.255204] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10439 13:55:14.552634  <6>[    0.264059] CPU features: detected: Common not Private translations

10440 13:55:14.556127  <6>[    0.270534] CPU features: detected: CRC32 instructions

10441 13:55:14.562482  <6>[    0.275885] CPU features: detected: RCpc load-acquire (LDAPR)

10442 13:55:14.569440  <6>[    0.281846] CPU features: detected: LSE atomic instructions

10443 13:55:14.575844  <6>[    0.287663] CPU features: detected: Privileged Access Never

10444 13:55:14.578883  <6>[    0.293442] CPU features: detected: RAS Extension Support

10445 13:55:14.589286  <6>[    0.299051] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10446 13:55:14.592283  <6>[    0.306316] CPU: All CPU(s) started at EL2

10447 13:55:14.598950  <6>[    0.310633] alternatives: applying system-wide alternatives

10448 13:55:14.607891  <6>[    0.321390] devtmpfs: initialized

10449 13:55:14.620313  <6>[    0.330369] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10450 13:55:14.630315  <6>[    0.340328] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10451 13:55:14.636725  <6>[    0.348564] pinctrl core: initialized pinctrl subsystem

10452 13:55:14.640312  <6>[    0.355202] DMI not present or invalid.

10453 13:55:14.646884  <6>[    0.359616] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10454 13:55:14.656752  <6>[    0.366496] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10455 13:55:14.663379  <6>[    0.374073] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10456 13:55:14.673454  <6>[    0.382309] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10457 13:55:14.676689  <6>[    0.390551] audit: initializing netlink subsys (disabled)

10458 13:55:14.686610  <5>[    0.396245] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1

10459 13:55:14.693545  <6>[    0.396942] thermal_sys: Registered thermal governor 'step_wise'

10460 13:55:14.699932  <6>[    0.404217] thermal_sys: Registered thermal governor 'power_allocator'

10461 13:55:14.703056  <6>[    0.410476] cpuidle: using governor menu

10462 13:55:14.709892  <6>[    0.421440] NET: Registered PF_QIPCRTR protocol family

10463 13:55:14.716901  <6>[    0.426927] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10464 13:55:14.719653  <6>[    0.434033] ASID allocator initialised with 32768 entries

10465 13:55:14.727280  <6>[    0.440594] Serial: AMBA PL011 UART driver

10466 13:55:14.735788  <4>[    0.449336] Trying to register duplicate clock ID: 134

10467 13:55:14.791660  <6>[    0.508634] KASLR enabled

10468 13:55:14.805813  <6>[    0.516416] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10469 13:55:14.812971  <6>[    0.523430] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10470 13:55:14.819650  <6>[    0.529919] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10471 13:55:14.826558  <6>[    0.536928] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10472 13:55:14.832830  <6>[    0.543416] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10473 13:55:14.839483  <6>[    0.550420] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10474 13:55:14.846184  <6>[    0.556909] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10475 13:55:14.852704  <6>[    0.563916] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10476 13:55:14.856118  <6>[    0.571433] ACPI: Interpreter disabled.

10477 13:55:14.864433  <6>[    0.577861] iommu: Default domain type: Translated 

10478 13:55:14.871505  <6>[    0.582975] iommu: DMA domain TLB invalidation policy: strict mode 

10479 13:55:14.874411  <5>[    0.589637] SCSI subsystem initialized

10480 13:55:14.880575  <6>[    0.593803] usbcore: registered new interface driver usbfs

10481 13:55:14.887602  <6>[    0.599536] usbcore: registered new interface driver hub

10482 13:55:14.890492  <6>[    0.605092] usbcore: registered new device driver usb

10483 13:55:14.897607  <6>[    0.611197] pps_core: LinuxPPS API ver. 1 registered

10484 13:55:14.907653  <6>[    0.616394] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10485 13:55:14.910858  <6>[    0.625747] PTP clock support registered

10486 13:55:14.914191  <6>[    0.629992] EDAC MC: Ver: 3.0.0

10487 13:55:14.921451  <6>[    0.635158] FPGA manager framework

10488 13:55:14.928576  <6>[    0.638840] Advanced Linux Sound Architecture Driver Initialized.

10489 13:55:14.931906  <6>[    0.645622] vgaarb: loaded

10490 13:55:14.938402  <6>[    0.648783] clocksource: Switched to clocksource arch_sys_counter

10491 13:55:14.941565  <5>[    0.655225] VFS: Disk quotas dquot_6.6.0

10492 13:55:14.947999  <6>[    0.659413] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10493 13:55:14.951525  <6>[    0.666607] pnp: PnP ACPI: disabled

10494 13:55:14.959769  <6>[    0.673374] NET: Registered PF_INET protocol family

10495 13:55:14.969906  <6>[    0.678967] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10496 13:55:14.981273  <6>[    0.691284] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10497 13:55:14.991115  <6>[    0.700103] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10498 13:55:14.997853  <6>[    0.708080] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10499 13:55:15.004116  <6>[    0.716785] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10500 13:55:15.016205  <6>[    0.726513] TCP: Hash tables configured (established 65536 bind 65536)

10501 13:55:15.022570  <6>[    0.733381] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10502 13:55:15.029474  <6>[    0.740583] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10503 13:55:15.036153  <6>[    0.748291] NET: Registered PF_UNIX/PF_LOCAL protocol family

10504 13:55:15.042881  <6>[    0.754446] RPC: Registered named UNIX socket transport module.

10505 13:55:15.046265  <6>[    0.760600] RPC: Registered udp transport module.

10506 13:55:15.052717  <6>[    0.765533] RPC: Registered tcp transport module.

10507 13:55:15.059151  <6>[    0.770467] RPC: Registered tcp NFSv4.1 backchannel transport module.

10508 13:55:15.062630  <6>[    0.777135] PCI: CLS 0 bytes, default 64

10509 13:55:15.065771  <6>[    0.781434] Unpacking initramfs...

10510 13:55:15.083284  <6>[    0.793324] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10511 13:55:15.093222  <6>[    0.801968] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10512 13:55:15.096549  <6>[    0.810805] kvm [1]: IPA Size Limit: 40 bits

10513 13:55:15.102776  <6>[    0.815331] kvm [1]: GICv3: no GICV resource entry

10514 13:55:15.106112  <6>[    0.820355] kvm [1]: disabling GICv2 emulation

10515 13:55:15.112957  <6>[    0.825044] kvm [1]: GIC system register CPU interface enabled

10516 13:55:15.116175  <6>[    0.831215] kvm [1]: vgic interrupt IRQ18

10517 13:55:15.122602  <6>[    0.835576] kvm [1]: VHE mode initialized successfully

10518 13:55:15.129429  <5>[    0.842036] Initialise system trusted keyrings

10519 13:55:15.135837  <6>[    0.846847] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10520 13:55:15.143149  <6>[    0.856839] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10521 13:55:15.150101  <5>[    0.863236] NFS: Registering the id_resolver key type

10522 13:55:15.153396  <5>[    0.868537] Key type id_resolver registered

10523 13:55:15.159972  <5>[    0.872955] Key type id_legacy registered

10524 13:55:15.166370  <6>[    0.877234] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10525 13:55:15.173606  <6>[    0.884157] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10526 13:55:15.179927  <6>[    0.891888] 9p: Installing v9fs 9p2000 file system support

10527 13:55:15.216522  <5>[    0.930108] Key type asymmetric registered

10528 13:55:15.220021  <5>[    0.934439] Asymmetric key parser 'x509' registered

10529 13:55:15.229780  <6>[    0.939612] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10530 13:55:15.232948  <6>[    0.947232] io scheduler mq-deadline registered

10531 13:55:15.236500  <6>[    0.951994] io scheduler kyber registered

10532 13:55:15.256080  <6>[    0.969332] EINJ: ACPI disabled.

10533 13:55:15.288112  <4>[    0.995079] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10534 13:55:15.297892  <4>[    1.005729] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10535 13:55:15.313661  <6>[    1.026899] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10536 13:55:15.321865  <6>[    1.035014] printk: console [ttyS0] disabled

10537 13:55:15.349268  <6>[    1.059666] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10538 13:55:15.356002  <6>[    1.069166] printk: console [ttyS0] enabled

10539 13:55:15.359189  <6>[    1.069166] printk: console [ttyS0] enabled

10540 13:55:15.366262  <6>[    1.078063] printk: bootconsole [mtk8250] disabled

10541 13:55:15.369025  <6>[    1.078063] printk: bootconsole [mtk8250] disabled

10542 13:55:15.376007  <6>[    1.089399] SuperH (H)SCI(F) driver initialized

10543 13:55:15.379194  <6>[    1.094649] msm_serial: driver initialized

10544 13:55:15.393514  <6>[    1.103686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10545 13:55:15.403471  <6>[    1.112236] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10546 13:55:15.410286  <6>[    1.120783] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10547 13:55:15.420018  <6>[    1.129414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10548 13:55:15.430085  <6>[    1.138122] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10549 13:55:15.436778  <6>[    1.146844] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10550 13:55:15.446820  <6>[    1.155390] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10551 13:55:15.453099  <6>[    1.164202] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10552 13:55:15.463064  <6>[    1.172747] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10553 13:55:15.474680  <6>[    1.188599] loop: module loaded

10554 13:55:15.481883  <6>[    1.194634] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10555 13:55:15.504365  <4>[    1.218137] mtk-pmic-keys: Failed to locate of_node [id: -1]

10556 13:55:15.511595  <6>[    1.225218] megasas: 07.719.03.00-rc1

10557 13:55:15.521662  <6>[    1.235115] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10558 13:55:15.534388  <6>[    1.248165] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10559 13:55:15.551757  <6>[    1.264887] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10560 13:55:15.607815  <6>[    1.314724] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10561 13:55:15.806457  <6>[    1.519879] Freeing initrd memory: 17388K

10562 13:55:15.816428  <6>[    1.530275] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10563 13:55:15.827832  <6>[    1.541232] tun: Universal TUN/TAP device driver, 1.6

10564 13:55:15.831429  <6>[    1.547287] thunder_xcv, ver 1.0

10565 13:55:15.834338  <6>[    1.550813] thunder_bgx, ver 1.0

10566 13:55:15.837578  <6>[    1.554306] nicpf, ver 1.0

10567 13:55:15.848480  <6>[    1.558331] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10568 13:55:15.851373  <6>[    1.565807] hns3: Copyright (c) 2017 Huawei Corporation.

10569 13:55:15.854769  <6>[    1.571393] hclge is initializing

10570 13:55:15.861826  <6>[    1.574973] e1000: Intel(R) PRO/1000 Network Driver

10571 13:55:15.868384  <6>[    1.580102] e1000: Copyright (c) 1999-2006 Intel Corporation.

10572 13:55:15.871373  <6>[    1.586115] e1000e: Intel(R) PRO/1000 Network Driver

10573 13:55:15.877991  <6>[    1.591330] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10574 13:55:15.884633  <6>[    1.597518] igb: Intel(R) Gigabit Ethernet Network Driver

10575 13:55:15.891452  <6>[    1.603168] igb: Copyright (c) 2007-2014 Intel Corporation.

10576 13:55:15.898055  <6>[    1.609004] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10577 13:55:15.904308  <6>[    1.615522] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10578 13:55:15.907463  <6>[    1.621976] sky2: driver version 1.30

10579 13:55:15.914505  <6>[    1.626959] VFIO - User Level meta-driver version: 0.3

10580 13:55:15.921758  <6>[    1.635181] usbcore: registered new interface driver usb-storage

10581 13:55:15.928413  <6>[    1.641623] usbcore: registered new device driver onboard-usb-hub

10582 13:55:15.937280  <6>[    1.650749] mt6397-rtc mt6359-rtc: registered as rtc0

10583 13:55:15.947046  <6>[    1.656207] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:54:35 UTC (1706795675)

10584 13:55:15.950322  <6>[    1.665795] i2c_dev: i2c /dev entries driver

10585 13:55:15.967220  <6>[    1.677560] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10586 13:55:15.986778  <6>[    1.700542] cpu cpu0: EM: created perf domain

10587 13:55:15.990175  <6>[    1.705467] cpu cpu4: EM: created perf domain

10588 13:55:15.997322  <6>[    1.711053] sdhci: Secure Digital Host Controller Interface driver

10589 13:55:16.004144  <6>[    1.717487] sdhci: Copyright(c) Pierre Ossman

10590 13:55:16.010804  <6>[    1.722441] Synopsys Designware Multimedia Card Interface Driver

10591 13:55:16.017691  <6>[    1.729104] sdhci-pltfm: SDHCI platform and OF driver helper

10592 13:55:16.020933  <6>[    1.729175] mmc0: CQHCI version 5.10

10593 13:55:16.027800  <6>[    1.739080] ledtrig-cpu: registered to indicate activity on CPUs

10594 13:55:16.034264  <6>[    1.746125] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10595 13:55:16.040772  <6>[    1.753195] usbcore: registered new interface driver usbhid

10596 13:55:16.044258  <6>[    1.759018] usbhid: USB HID core driver

10597 13:55:16.050631  <6>[    1.763241] spi_master spi0: will run message pump with realtime priority

10598 13:55:16.095502  <6>[    1.802573] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10599 13:55:16.114433  <6>[    1.817943] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10600 13:55:16.121620  <6>[    1.833806] cros-ec-spi spi0.0: Chrome EC device registered

10601 13:55:16.124592  <6>[    1.839850] mmc0: Command Queue Engine enabled

10602 13:55:16.131434  <6>[    1.844578] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10603 13:55:16.138849  <6>[    1.852054] mmcblk0: mmc0:0001 DA4128 116 GiB 

10604 13:55:16.148518  <6>[    1.853202] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10605 13:55:16.152164  <6>[    1.860823]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10606 13:55:16.158290  <6>[    1.867046] NET: Registered PF_PACKET protocol family

10607 13:55:16.164848  <6>[    1.873736] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10608 13:55:16.168743  <6>[    1.877415] 9pnet: Installing 9P2000 support

10609 13:55:16.174874  <6>[    1.883363] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10610 13:55:16.178367  <5>[    1.887062] Key type dns_resolver registered

10611 13:55:16.185008  <6>[    1.892956] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10612 13:55:16.188336  <6>[    1.897257] registered taskstats version 1

10613 13:55:16.194860  <5>[    1.907666] Loading compiled-in X.509 certificates

10614 13:55:16.222196  <4>[    1.929143] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10615 13:55:16.232217  <4>[    1.940022] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10616 13:55:16.239151  <3>[    1.950563] debugfs: File 'uA_load' in directory '/' already present!

10617 13:55:16.245652  <3>[    1.957275] debugfs: File 'min_uV' in directory '/' already present!

10618 13:55:16.252488  <3>[    1.963888] debugfs: File 'max_uV' in directory '/' already present!

10619 13:55:16.258694  <3>[    1.970498] debugfs: File 'constraint_flags' in directory '/' already present!

10620 13:55:16.270680  <3>[    1.980970] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10621 13:55:16.283206  <6>[    1.996852] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10622 13:55:16.290357  <6>[    2.003831] xhci-mtk 11200000.usb: xHCI Host Controller

10623 13:55:16.296638  <6>[    2.009365] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10624 13:55:16.307098  <6>[    2.017347] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10625 13:55:16.313474  <6>[    2.026812] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10626 13:55:16.320821  <6>[    2.032882] xhci-mtk 11200000.usb: xHCI Host Controller

10627 13:55:16.326689  <6>[    2.038363] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10628 13:55:16.333394  <6>[    2.046014] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10629 13:55:16.339937  <6>[    2.053832] hub 1-0:1.0: USB hub found

10630 13:55:16.343525  <6>[    2.057882] hub 1-0:1.0: 1 port detected

10631 13:55:16.350277  <6>[    2.062189] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10632 13:55:16.357331  <6>[    2.070934] hub 2-0:1.0: USB hub found

10633 13:55:16.360513  <6>[    2.074978] hub 2-0:1.0: 1 port detected

10634 13:55:16.367997  <6>[    2.081605] mtk-msdc 11f70000.mmc: Got CD GPIO

10635 13:55:16.383028  <6>[    2.093371] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10636 13:55:16.389477  <6>[    2.101415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10637 13:55:16.399820  <4>[    2.109331] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10638 13:55:16.409587  <6>[    2.118888] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10639 13:55:16.416272  <6>[    2.126965] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10640 13:55:16.422789  <6>[    2.134992] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10641 13:55:16.433109  <6>[    2.142911] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10642 13:55:16.439737  <6>[    2.150732] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10643 13:55:16.449818  <6>[    2.158552] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10644 13:55:16.459793  <6>[    2.169083] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10645 13:55:16.466464  <6>[    2.177446] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10646 13:55:16.476554  <6>[    2.185795] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10647 13:55:16.483386  <6>[    2.194134] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10648 13:55:16.493207  <6>[    2.202473] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10649 13:55:16.499855  <6>[    2.210811] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10650 13:55:16.509824  <6>[    2.219150] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10651 13:55:16.516202  <6>[    2.227489] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10652 13:55:16.526452  <6>[    2.235827] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10653 13:55:16.532950  <6>[    2.244166] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10654 13:55:16.543025  <6>[    2.252513] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10655 13:55:16.549313  <6>[    2.260864] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10656 13:55:16.559398  <6>[    2.269205] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10657 13:55:16.566398  <6>[    2.277544] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10658 13:55:16.576487  <6>[    2.285884] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10659 13:55:16.582759  <6>[    2.294626] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10660 13:55:16.589376  <6>[    2.301671] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10661 13:55:16.595838  <6>[    2.308446] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10662 13:55:16.602453  <6>[    2.315203] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10663 13:55:16.609174  <6>[    2.322188] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10664 13:55:16.619046  <6>[    2.329056] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10665 13:55:16.629099  <6>[    2.338187] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10666 13:55:16.639152  <6>[    2.347306] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10667 13:55:16.648922  <6>[    2.356600] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10668 13:55:16.655336  <6>[    2.366068] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10669 13:55:16.665305  <6>[    2.375533] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10670 13:55:16.675930  <6>[    2.384652] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10671 13:55:16.685547  <6>[    2.394117] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10672 13:55:16.695105  <6>[    2.403235] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10673 13:55:16.705273  <6>[    2.412529] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10674 13:55:16.714945  <6>[    2.422689] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10675 13:55:16.724891  <6>[    2.434339] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10676 13:55:16.731524  <6>[    2.443958] Trying to probe devices needed for running init ...

10677 13:55:16.774561  <6>[    2.485061] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10678 13:55:16.929416  <6>[    2.643201] hub 1-1:1.0: USB hub found

10679 13:55:16.932792  <6>[    2.647708] hub 1-1:1.0: 4 ports detected

10680 13:55:16.941910  <6>[    2.655969] hub 1-1:1.0: USB hub found

10681 13:55:16.945209  <6>[    2.660313] hub 1-1:1.0: 4 ports detected

10682 13:55:17.054854  <6>[    2.765474] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10683 13:55:17.083275  <6>[    2.796503] hub 2-1:1.0: USB hub found

10684 13:55:17.086031  <6>[    2.801088] hub 2-1:1.0: 3 ports detected

10685 13:55:17.096805  <6>[    2.810321] hub 2-1:1.0: USB hub found

10686 13:55:17.099710  <6>[    2.814861] hub 2-1:1.0: 3 ports detected

10687 13:55:17.266596  <6>[    2.977050] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10688 13:55:17.398489  <6>[    3.112566] hub 1-1.4:1.0: USB hub found

10689 13:55:17.402017  <6>[    3.117243] hub 1-1.4:1.0: 2 ports detected

10690 13:55:17.411260  <6>[    3.125332] hub 1-1.4:1.0: USB hub found

10691 13:55:17.414847  <6>[    3.129939] hub 1-1.4:1.0: 2 ports detected

10692 13:55:17.478722  <6>[    3.189263] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10693 13:55:17.710429  <6>[    3.421107] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10694 13:55:17.902451  <6>[    3.613066] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10695 13:55:29.015572  <6>[   14.734069] ALSA device list:

10696 13:55:29.022021  <6>[   14.737360]   No soundcards found.

10697 13:55:29.030054  <6>[   14.745349] Freeing unused kernel memory: 8448K

10698 13:55:29.033266  <6>[   14.750361] Run /init as init process

10699 13:55:29.045174  Loading, please wait...

10700 13:55:29.065433  Starting version 247.3-7+deb11u2

10701 13:55:29.283593  <6>[   14.995608] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10702 13:55:29.295243  <6>[   15.010640] remoteproc remoteproc0: scp is available

10703 13:55:29.301570  <6>[   15.016574] remoteproc remoteproc0: powering up scp

10704 13:55:29.308244  <6>[   15.022089] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10705 13:55:29.314979  <6>[   15.030610] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10706 13:55:29.327234  <6>[   15.039498] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10707 13:55:29.333848  <3>[   15.039940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10708 13:55:29.344112  <6>[   15.050474] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10709 13:55:29.350370  <6>[   15.051025] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10710 13:55:29.360677  <6>[   15.051038] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10711 13:55:29.367749  <3>[   15.060929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10712 13:55:29.374264  <4>[   15.063327] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10713 13:55:29.381238  <6>[   15.071363] usbcore: registered new device driver r8152-cfgselector

10714 13:55:29.387402  <6>[   15.072032] mc: Linux media interface: v0.10

10715 13:55:29.394321  <3>[   15.072761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10716 13:55:29.404721  <3>[   15.079791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10717 13:55:29.411076  <3>[   15.079806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10718 13:55:29.418908  <3>[   15.079823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10719 13:55:29.429104  <3>[   15.079829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10720 13:55:29.435335  <3>[   15.079833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10721 13:55:29.442008  <3>[   15.080214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10722 13:55:29.452038  <3>[   15.080255] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10723 13:55:29.458643  <3>[   15.080258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10724 13:55:29.468574  <3>[   15.080261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10725 13:55:29.474949  <3>[   15.080301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10726 13:55:29.481583  <4>[   15.081166] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10727 13:55:29.491283  <4>[   15.090288] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10728 13:55:29.498249  <4>[   15.090288] Fallback method does not support PEC.

10729 13:55:29.504740  <3>[   15.095830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10730 13:55:29.511246  <3>[   15.095847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10731 13:55:29.518267  <6>[   15.107639] videodev: Linux video capture interface: v2.00

10732 13:55:29.528379  <3>[   15.114981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10733 13:55:29.534617  <3>[   15.119374] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10734 13:55:29.544504  <3>[   15.142605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10735 13:55:29.551187  <3>[   15.147287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10736 13:55:29.561001  <3>[   15.147321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10737 13:55:29.567436  <6>[   15.161510] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10738 13:55:29.577871  <6>[   15.161537] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10739 13:55:29.580905  <6>[   15.161545] remoteproc remoteproc0: remote processor scp is now up

10740 13:55:29.590846  <6>[   15.174092] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10741 13:55:29.597708  <6>[   15.179975] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10742 13:55:29.607333  <6>[   15.184999] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10743 13:55:29.613898  <6>[   15.187727] pci_bus 0000:00: root bus resource [bus 00-ff]

10744 13:55:29.620794  <6>[   15.187734] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10745 13:55:29.630887  <6>[   15.187738] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10746 13:55:29.637139  <6>[   15.187774] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10747 13:55:29.643587  <6>[   15.188706] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10748 13:55:29.653449  <6>[   15.190829] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10749 13:55:29.663312  <6>[   15.213613] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003

10750 13:55:29.670076  <6>[   15.216786] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10751 13:55:29.680205  <4>[   15.220654] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

10752 13:55:29.686582  <4>[   15.220665] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

10753 13:55:29.696793  <6>[   15.225848] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10754 13:55:29.699730  <6>[   15.233385] pci 0000:00:00.0: supports D1 D2

10755 13:55:29.702891  <6>[   15.281135] Bluetooth: Core ver 2.22

10756 13:55:29.709890  <6>[   15.287612] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10757 13:55:29.716575  <6>[   15.288932] r8152 2-1.3:1.0 eth0: v1.12.13

10758 13:55:29.723145  <6>[   15.289025] usbcore: registered new interface driver r8152

10759 13:55:29.726915  <6>[   15.296198] NET: Registered PF_BLUETOOTH protocol family

10760 13:55:29.736431  <6>[   15.303515] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10761 13:55:29.742627  <6>[   15.309423] Bluetooth: HCI device and connection manager initialized

10762 13:55:29.746341  <6>[   15.309447] Bluetooth: HCI socket layer initialized

10763 13:55:29.752769  <6>[   15.309957] usbcore: registered new interface driver cdc_ether

10764 13:55:29.759134  <6>[   15.310754] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10765 13:55:29.772792  <6>[   15.311821] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10766 13:55:29.779003  <6>[   15.311914] usbcore: registered new interface driver uvcvideo

10767 13:55:29.786182  <6>[   15.317885] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10768 13:55:29.789607  <6>[   15.327070] Bluetooth: L2CAP socket layer initialized

10769 13:55:29.796026  <6>[   15.327378] usbcore: registered new interface driver r8153_ecm

10770 13:55:29.802704  <6>[   15.332832] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10771 13:55:29.809269  <6>[   15.339932] Bluetooth: SCO socket layer initialized

10772 13:55:29.815620  <6>[   15.347736] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0

10773 13:55:29.822248  <6>[   15.349838] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10774 13:55:29.828649  <6>[   15.357192] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10775 13:55:29.835166  <6>[   15.364340] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10776 13:55:29.841999  <6>[   15.416794] usbcore: registered new interface driver btusb

10777 13:55:29.852023  <4>[   15.417546] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10778 13:55:29.858404  <3>[   15.417559] Bluetooth: hci0: Failed to load firmware file (-2)

10779 13:55:29.865155  <3>[   15.417565] Bluetooth: hci0: Failed to set up firmware (-2)

10780 13:55:29.875192  <4>[   15.417570] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10781 13:55:29.878272  <6>[   15.420913] pci 0000:01:00.0: supports D1 D2

10782 13:55:29.884903  <6>[   15.599429] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10783 13:55:29.904772  <6>[   15.616815] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10784 13:55:29.911819  <6>[   15.623697] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10785 13:55:29.918121  <6>[   15.631776] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10786 13:55:29.928573  <6>[   15.639773] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10787 13:55:29.934514  <6>[   15.647775] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10788 13:55:29.944483  <6>[   15.655776] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10789 13:55:29.948079  <6>[   15.663775] pci 0000:00:00.0: PCI bridge to [bus 01]

10790 13:55:29.957792  <6>[   15.668992] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10791 13:55:29.964718  <6>[   15.677102] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10792 13:55:29.970893  <6>[   15.683902] pcieport 0000:00:00.0: PME: Signaling with IRQ 283

10793 13:55:29.977521  <6>[   15.690648] pcieport 0000:00:00.0: AER: enabled with IRQ 283

10794 13:55:29.991702  <5>[   15.703875] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10795 13:55:30.011226  <5>[   15.722971] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10796 13:55:30.017685  <5>[   15.730365] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'

10797 13:55:30.027680  <4>[   15.738817] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10798 13:55:30.031065  <6>[   15.747696] cfg80211: failed to load regulatory.db

10799 13:55:30.081433  <6>[   15.793221] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10800 13:55:30.087678  <6>[   15.800718] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10801 13:55:30.112197  <6>[   15.827352] mt7921e 0000:01:00.0: ASIC revision: 79610010

10802 13:55:30.216024  <6>[   15.928464] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a

10803 13:55:30.219710  <6>[   15.928464] 

10804 13:55:30.222837  Begin: Loading essential drivers ... done.

10805 13:55:30.226221  Begin: Running /scripts/init-premount ... done.

10806 13:55:30.232861  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.

10807 13:55:30.242730  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available

10808 13:55:30.245801  Device /sys/class/net/enx00e04c722dd6 found

10809 13:55:30.246112  done.

10810 13:55:30.301177  IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP

10811 13:55:30.484357  <6>[   16.196037] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959

10812 13:55:31.191088  <6>[   16.906697] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on

10813 13:55:31.327544  <6>[   17.043173] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0

10814 13:55:31.441186  IP-Config: no response after 2 secs - giving up

10815 13:55:31.474177  IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP

10816 13:55:31.489592  IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP

10817 13:55:32.197272  IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):

10818 13:55:32.203845   address: 192.168.201.21   broadcast: 192.168.201.255  netmask: 255.255.255.0   

10819 13:55:32.210590   gateway: 192.168.201.1    dns0     : 192.168.201.1    dns1   : 0.0.0.0         

10820 13:55:32.217059   host   : mt8192-asurada-spherion-r0-cbg-1                                

10821 13:55:32.223800   domain : lava-rack                                                       

10822 13:55:32.226857   rootserver: 192.168.201.1 rootpath: 

10823 13:55:32.229923   filename  : 

10824 13:55:32.353227  done.

10825 13:55:32.359960  Begin: Running /scripts/nfs-bottom ... done.

10826 13:55:32.381920  Begin: Running /scripts/init-bottom ... done.

10827 13:55:33.547062  <6>[   19.262973] NET: Registered PF_INET6 protocol family

10828 13:55:33.555143  <6>[   19.270688] Segment Routing with IPv6

10829 13:55:33.558079  <6>[   19.274640] In-situ OAM (IOAM) with IPv6

10830 13:55:33.681122  <30>[   19.376924] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10831 13:55:33.683721  <30>[   19.401178] systemd[1]: Detected architecture arm64.

10832 13:55:33.704805  

10833 13:55:33.708224  Welcome to Debian GNU/Linux 11 (bullseye)!

10834 13:55:33.708660  

10835 13:55:33.724196  <30>[   19.439997] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10836 13:55:34.605370  <30>[   20.318083] systemd[1]: Queued start job for default target Graphical Interface.

10837 13:55:34.651804  <30>[   20.367560] systemd[1]: Created slice system-getty.slice.

10838 13:55:34.658559  [  OK  ] Created slice system-getty.slice.

10839 13:55:34.674640  <30>[   20.390541] systemd[1]: Created slice system-modprobe.slice.

10840 13:55:34.681366  [  OK  ] Created slice system-modprobe.slice.

10841 13:55:34.699041  <30>[   20.415195] systemd[1]: Created slice system-serial\x2dgetty.slice.

10842 13:55:34.709761  [  OK  ] Created slice system-serial\x2dgetty.slice.

10843 13:55:34.722262  <30>[   20.438162] systemd[1]: Created slice User and Session Slice.

10844 13:55:34.728742  [  OK  ] Created slice User and Session Slice.

10845 13:55:34.749223  <30>[   20.461911] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10846 13:55:34.759207  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10847 13:55:34.777128  <30>[   20.489737] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10848 13:55:34.783997  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10849 13:55:34.808280  <30>[   20.517225] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10850 13:55:34.814810  <30>[   20.529381] systemd[1]: Reached target Local Encrypted Volumes.

10851 13:55:34.821010  [  OK  ] Reached target Local Encrypted Volumes.

10852 13:55:34.838002  <30>[   20.553520] systemd[1]: Reached target Paths.

10853 13:55:34.841110  [  OK  ] Reached target Paths.

10854 13:55:34.857355  <30>[   20.573070] systemd[1]: Reached target Remote File Systems.

10855 13:55:34.863745  [  OK  ] Reached target Remote File Systems.

10856 13:55:34.881770  <30>[   20.597464] systemd[1]: Reached target Slices.

10857 13:55:34.888395  [  OK  ] Reached target Slices.

10858 13:55:34.901127  <30>[   20.617096] systemd[1]: Reached target Swap.

10859 13:55:34.904542  [  OK  ] Reached target Swap.

10860 13:55:34.925158  <30>[   20.637578] systemd[1]: Listening on initctl Compatibility Named Pipe.

10861 13:55:34.931593  [  OK  ] Listening on initctl Compatibility Named Pipe.

10862 13:55:34.938372  <30>[   20.653772] systemd[1]: Listening on Journal Audit Socket.

10863 13:55:34.944784  [  OK  ] Listening on Journal Audit Socket.

10864 13:55:34.962150  <30>[   20.678421] systemd[1]: Listening on Journal Socket (/dev/log).

10865 13:55:34.969153  [  OK  ] Listening on Journal Socket (/dev/log).

10866 13:55:34.985605  <30>[   20.701628] systemd[1]: Listening on Journal Socket.

10867 13:55:34.992255  [  OK  ] Listening on Journal Socket.

10868 13:55:35.006727  <30>[   20.722515] systemd[1]: Listening on Network Service Netlink Socket.

10869 13:55:35.016505  [  OK  ] Listening on Network Service Netlink Socket.

10870 13:55:35.032879  <30>[   20.748378] systemd[1]: Listening on udev Control Socket.

10871 13:55:35.039133  [  OK  ] Listening on udev Control Socket.

10872 13:55:35.053916  <30>[   20.769514] systemd[1]: Listening on udev Kernel Socket.

10873 13:55:35.060318  [  OK  ] Listening on udev Kernel Socket.

10874 13:55:35.109755  <30>[   20.825572] systemd[1]: Mounting Huge Pages File System...

10875 13:55:35.116165           Mounting Huge Pages File System...

10876 13:55:35.131350  <30>[   20.847464] systemd[1]: Mounting POSIX Message Queue File System...

10877 13:55:35.138421           Mounting POSIX Message Queue File System...

10878 13:55:35.157472  <30>[   20.873396] systemd[1]: Mounting Kernel Debug File System...

10879 13:55:35.164266           Mounting Kernel Debug File System...

10880 13:55:35.180854  <30>[   20.893631] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10881 13:55:35.241295  <30>[   20.953962] systemd[1]: Starting Create list of static device nodes for the current kernel...

10882 13:55:35.247895           Starting Create list of st…odes for the current kernel...

10883 13:55:35.268982  <30>[   20.984694] systemd[1]: Starting Load Kernel Module configfs...

10884 13:55:35.275343           Starting Load Kernel Module configfs...

10885 13:55:35.293737  <30>[   21.009686] systemd[1]: Starting Load Kernel Module drm...

10886 13:55:35.300014           Starting Load Kernel Module drm...

10887 13:55:35.318250  <30>[   21.034089] systemd[1]: Starting Load Kernel Module fuse...

10888 13:55:35.324541           Starting Load Kernel Module fuse...

10889 13:55:35.361497  <30>[   21.074807] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10890 13:55:35.368462  <6>[   21.075111] fuse: init (API version 7.37)

10891 13:55:35.405582  <30>[   21.121831] systemd[1]: Starting Journal Service...

10892 13:55:35.412393           Starting Journal Service...

10893 13:55:35.435986  <30>[   21.151940] systemd[1]: Starting Load Kernel Modules...

10894 13:55:35.442377           Starting Load Kernel Modules...

10895 13:55:35.466482  <30>[   21.179344] systemd[1]: Starting Remount Root and Kernel File Systems...

10896 13:55:35.473257           Starting Remount Root and Kernel File Systems...

10897 13:55:35.488785  <30>[   21.204744] systemd[1]: Starting Coldplug All udev Devices...

10898 13:55:35.495781           Starting Coldplug All udev Devices...

10899 13:55:35.512343  <30>[   21.228524] systemd[1]: Mounted Huge Pages File System.

10900 13:55:35.519221  [  OK  ] Mounted Huge Pages File System.

10901 13:55:35.533543  <30>[   21.249615] systemd[1]: Mounted POSIX Message Queue File System.

10902 13:55:35.540399  [  OK  ] Mounted POSIX Message Queue File System.

10903 13:55:35.557437  <30>[   21.273720] systemd[1]: Mounted Kernel Debug File System.

10904 13:55:35.564723  [  OK  ] Mounted Kernel Debug File System.

10905 13:55:35.582472  <3>[   21.295063] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10906 13:55:35.592437  <30>[   21.305093] systemd[1]: Finished Create list of static device nodes for the current kernel.

10907 13:55:35.602370  [  OK  ] Finished Create list of st… nodes for the current kernel.

10908 13:55:35.613272  <3>[   21.325772] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10909 13:55:35.620940  <30>[   21.336996] systemd[1]: modprobe@configfs.service: Succeeded.

10910 13:55:35.627955  <30>[   21.344004] systemd[1]: Finished Load Kernel Module configfs.

10911 13:55:35.634453  [  OK  ] Finished Load Kernel Module configfs.

10912 13:55:35.654158  <30>[   21.370125] systemd[1]: modprobe@drm.service: Succeeded.

10913 13:55:35.661366  <30>[   21.376511] systemd[1]: Finished Load Kernel Module drm.

10914 13:55:35.668577  [  OK  ] Finished Load Kernel Module drm.

10915 13:55:35.678345  <3>[   21.389009] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10916 13:55:35.686475  <30>[   21.402115] systemd[1]: modprobe@fuse.service: Succeeded.

10917 13:55:35.693396  <30>[   21.408998] systemd[1]: Finished Load Kernel Module fuse.

10918 13:55:35.699826  [  OK  ] Finished Load Kernel Module fuse.

10919 13:55:35.717676  <3>[   21.429764] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10920 13:55:35.723632  <30>[   21.431179] systemd[1]: Finished Load Kernel Modules.

10921 13:55:35.730356  [  OK  ] Finished Load Kernel Modules.

10922 13:55:35.743839  <30>[   21.458779] systemd[1]: Finished Remount Root and Kernel File Systems.

10923 13:55:35.753246  <3>[   21.463719] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10924 13:55:35.759898  [  OK  ] Finished Remount Root and Kernel File Systems.

10925 13:55:35.782644  <3>[   21.495311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10926 13:55:35.812500  <3>[   21.525081] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10927 13:55:35.822399  <30>[   21.538644] systemd[1]: Mounting FUSE Control File System...

10928 13:55:35.829109           Mounting FUSE Control File System...

10929 13:55:35.843023  <3>[   21.555385] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10930 13:55:35.854514  <30>[   21.567144] systemd[1]: Mounting Kernel Configuration File System...

10931 13:55:35.857639           Mounting Kernel Configuration File System...

10932 13:55:35.874161  <3>[   21.586671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10933 13:55:35.888177  <30>[   21.600952] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.

10934 13:55:35.898413  <30>[   21.610025] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.

10935 13:55:35.925973  <30>[   21.641754] systemd[1]: Starting Load/Save Random Seed...

10936 13:55:35.939237           Starting Load/Save Random Seed<3>[   21.651901] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10937 13:55:35.939715  ...

10938 13:55:35.964320  <30>[   21.680578] systemd[1]: Starting Apply Kernel Variables...

10939 13:55:35.970791           Starting Apply Kernel Variables...

10940 13:55:35.989541  <30>[   21.705600] systemd[1]: Starting Create System Users...

10941 13:55:35.996026           Starting Create System Users...

10942 13:55:36.011043  <30>[   21.726720] systemd[1]: Mounted FUSE Control File System.

10943 13:55:36.030858  [  OK  ] Mounted [0;<4>[   21.734619] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent

10944 13:55:36.037586  1;39mFUSE Contro<3>[   21.751336] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6

10945 13:55:36.040884  l File System.

10946 13:55:36.062124  <30>[   21.777695] systemd[1]: Started Journal Service.

10947 13:55:36.068613  [  OK  ] Started Journal Service.

10948 13:55:36.094145  [FAILED] Failed to start Coldplug All udev Devices.

10949 13:55:36.108522  See 'systemctl status systemd-udev-trigger.service' for details.

10950 13:55:36.125796  [  OK  ] Mounted Kernel Configuration File System.

10951 13:55:36.142579  [  OK  ] Finished Load/Save Random Seed.

10952 13:55:36.159294  [  OK  ] Finished Apply Kernel Variables.

10953 13:55:36.175310  [  OK  ] Finished Create System Users.

10954 13:55:36.234270           Starting Flush Journal to Persistent Storage...

10955 13:55:36.251362           Starting Create Static Device Nodes in /dev...

10956 13:55:36.297764  <46>[   22.010596] systemd-journald[299]: Received client request to flush runtime journal.

10957 13:55:36.343280  [  OK  ] Finished Create Static Device Nodes in /dev.

10958 13:55:36.361416  [  OK  ] Reached target Local File Systems (Pre).

10959 13:55:36.381154  [  OK  ] Reached target Local File Systems.

10960 13:55:36.433337           Starting Rule-based Manage…for Device Events and Files...

10961 13:55:37.712816  [  OK  ] Finished Flush Journal to Persistent Storage.

10962 13:55:37.749562           Starting Create Volatile Files and Directories...

10963 13:55:37.808626  [  OK  ] Started Rule-based Manager for Device Events and Files.

10964 13:55:37.853315           Starting Network Service...

10965 13:55:38.142443  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10966 13:55:38.197574           Starting Load/Save Screen …of leds:white:kbd_backlight...

10967 13:55:38.219578  [  OK  ] Found device /dev/ttyS0.

10968 13:55:38.308450  [  OK  ] Finished Create Volatile Files and Directories.

10969 13:55:38.493449  [  OK  ] Reached target Bluetooth.

10970 13:55:38.512628  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10971 13:55:38.577750           Starting Network Time Synchronization...

10972 13:55:38.598439           Starting Update UTMP about System Boot/Shutdown...

10973 13:55:38.613827  [  OK  ] Started Network Service.

10974 13:55:38.633863  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10975 13:55:38.716989           Starting Network Name Resolution...

10976 13:55:38.737573           Starting Load/Save RF Kill Switch Status...

10977 13:55:38.757244  [  OK  ] Started Network Time Synchronization.

10978 13:55:38.774694  [  OK  ] Reached target System Time Set.

10979 13:55:38.796566  [  OK  ] Reached target System Time Synchronized.

10980 13:55:38.812903  [  OK  ] Started Load/Save RF Kill Switch Status.

10981 13:55:38.838505  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10982 13:55:38.864984  [  OK  ] Reached target System Initialization.

10983 13:55:38.901525  [  OK  ] Started Daily apt download activities.

10984 13:55:38.927909  [  OK  ] Started Daily apt upgrade and clean activities.

10985 13:55:38.958714  [  OK  ] Started Periodic ext4 Onli…ata Check for All Filesystems.

10986 13:55:38.990201  [  OK  ] Started Discard unused blocks once a week.

10987 13:55:39.007825  [  OK  ] Started Daily Cleanup of Temporary Directories.

10988 13:55:39.020187  [  OK  ] Reached target Timers.

10989 13:55:39.044795  [  OK  ] Listening on D-Bus System Message Bus Socket.

10990 13:55:39.056024  [  OK  ] Reached target Sockets.

10991 13:55:39.072525  [  OK  ] Reached target Basic System.

10992 13:55:39.126071  [  OK  ] Started D-Bus System Message Bus.

10993 13:55:39.273152           Starting Remove Stale Onli…t4 Metadata Check Snapshots...

10994 13:55:39.404862           Starting User Login Management...

10995 13:55:39.643847  [  OK  ] Started Network Name Resolution.

10996 13:55:39.660531  [  OK  ] Reached target Network.

10997 13:55:39.685549  [  OK  ] Reached target Host and Network Name Lookups.

10998 13:55:39.725007           Starting Permit User Sessions...

10999 13:55:39.762761  [  OK  ] Finished Remove Stale Onli…ext4 Metadata Check Snapshots.

11000 13:55:39.785083  [  OK  ] Finished Permit User Sessions.

11001 13:55:39.806768  [  OK  ] Started User Login Management.

11002 13:55:39.854792  [  OK  ] Started Getty on tty1.

11003 13:55:39.875609  [  OK  ] Started Serial Getty on ttyS0.

11004 13:55:39.894192  [  OK  ] Reached target Login Prompts.

11005 13:55:39.909206  [  OK  ] Reached target Multi-User System.

11006 13:55:39.925146  [  OK  ] Reached target Graphical Interface.

11007 13:55:39.965344           Starting Update UTMP about System Runlevel Changes...

11008 13:55:40.009438  [  OK  ] Finished Update UTMP about System Runlevel Changes.

11009 13:55:40.079486  

11010 13:55:40.080046  

11011 13:55:40.082736  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

11012 13:55:40.083203  

11013 13:55:40.085734  debian-bullseye-arm64 login: root (automatic login)

11014 13:55:40.086228  

11015 13:55:40.086597  

11016 13:55:40.430112  Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb  1 13:35:47 UTC 2024 aarch64

11017 13:55:40.430667  

11018 13:55:40.436634  The programs included with the Debian GNU/Linux system are free software;

11019 13:55:40.443161  the exact distribution terms for each program are described in the

11020 13:55:40.446628  individual files in /usr/share/doc/*/copyright.

11021 13:55:40.447051  

11022 13:55:40.453216  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

11023 13:55:40.456379  permitted by applicable law.

11024 13:55:41.376166  Matched prompt #10: / #
11026 13:55:41.376470  Setting prompt string to ['/ #']
11027 13:55:41.376572  end: 2.2.5.1 login-action (duration 00:00:28) [common]
11029 13:55:41.376776  end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11030 13:55:41.376872  start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
11031 13:55:41.376947  Setting prompt string to ['/ #']
11032 13:55:41.377012  Forcing a shell prompt, looking for ['/ #']
11034 13:55:41.427413  / # 

11035 13:55:41.428093  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11036 13:55:41.428586  Waiting using forced prompt support (timeout 00:02:30)
11037 13:55:41.433758  

11038 13:55:41.434649  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11039 13:55:41.435072  start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11041 13:55:41.535877  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682923/extract-nfsrootfs-dxzindgm'

11042 13:55:41.542443  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12682923/extract-nfsrootfs-dxzindgm'

11044 13:55:41.644208  / # export NFS_SERVER_IP='192.168.201.1'

11045 13:55:41.650645  export NFS_SERVER_IP='192.168.201.1'

11046 13:55:41.651599  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11047 13:55:41.652153  end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11048 13:55:41.652654  end: 2 depthcharge-action (duration 00:01:30) [common]
11049 13:55:41.653159  start: 3 lava-test-retry (timeout 00:07:50) [common]
11050 13:55:41.653648  start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11051 13:55:41.654107  Using namespace: common
11053 13:55:41.755366  / # #

11054 13:55:41.756042  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11055 13:55:41.762188  #

11056 13:55:41.763082  Using /lava-12682923
11058 13:55:41.864290  / # export SHELL=/bin/bash

11059 13:55:41.869787  export SHELL=/bin/bash

11061 13:55:41.970814  / # . /lava-12682923/environment

11062 13:55:41.976519  . /lava-12682923/environment

11064 13:55:42.084028  / # /lava-12682923/bin/lava-test-runner /lava-12682923/0

11065 13:55:42.084679  Test shell timeout: 10s (minimum of the action and connection timeout)
11066 13:55:42.090201  /lava-12682923/bin/lava-test-runner /lava-12682923/0

11067 13:55:42.356553  + export TESTRUN_ID=0_timesync-off

11068 13:55:42.359672  + TESTRUN_ID=0_timesync-off

11069 13:55:42.363085  + cd /lava-12682923/0/tests/0_timesync-off

11070 13:55:42.366454  ++ cat uuid

11071 13:55:42.369867  + UUID=12682923_1.6.2.3.1

11072 13:55:42.369977  + set +x

11073 13:55:42.373079  Received signal: <STARTRUN> 0_timesync-off 12682923_1.6.2.3.1
11074 13:55:42.373170  Starting test lava.0_timesync-off (12682923_1.6.2.3.1)
11075 13:55:42.373264  Skipping test definition patterns.
11076 13:55:42.376595  <LAVA_SIGNAL_STARTRUN 0_timesync-off 12682923_1.6.2.3.1>

11077 13:55:42.376680  + systemctl stop systemd-timesyncd

11078 13:55:42.424748  + set +x

11079 13:55:42.428302  <LAVA_SIGNAL_ENDRUN 0_timesync-off 12682923_1.6.2.3.1>

11080 13:55:42.428713  Received signal: <ENDRUN> 0_timesync-off 12682923_1.6.2.3.1
11081 13:55:42.428922  Ending use of test pattern.
11082 13:55:42.429078  Ending test lava.0_timesync-off (12682923_1.6.2.3.1), duration 0.06
11084 13:55:42.511903  + export TESTRUN_ID=1_kselftest-tpm2

11085 13:55:42.515106  + TESTRUN_ID=1_kselftest-tpm2

11086 13:55:42.518339  + cd /lava-12682923/0/tests/1_kselftest-tpm2

11087 13:55:42.521459  ++ cat uuid

11088 13:55:42.527388  + UUID=12682923_1.6.2.3.5

11089 13:55:42.527982  + set +x

11090 13:55:42.534029  <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12682923_1.6.2.3.5>

11091 13:55:42.534771  Received signal: <STARTRUN> 1_kselftest-tpm2 12682923_1.6.2.3.5
11092 13:55:42.535171  Starting test lava.1_kselftest-tpm2 (12682923_1.6.2.3.5)
11093 13:55:42.535607  Skipping test definition patterns.
11094 13:55:42.537318  + cd ./automated/linux/kselftest/

11095 13:55:42.563964  + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1

11096 13:55:42.603928  INFO: install_deps skipped

11097 13:55:42.725574  --2024-02-01 13:55:02--  http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz

11098 13:55:42.737279  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82

11099 13:55:42.870630  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.

11100 13:55:43.003736  HTTP request sent, awaiting response... 200 OK

11101 13:55:43.006763  Length: 2966796 (2.8M) [application/octet-stream]

11102 13:55:43.010066  Saving to: 'kselftest.tar.xz'

11103 13:55:43.010538  

11104 13:55:43.010908  

11105 13:55:43.270028  kselftest.tar.xz      0%[                    ]       0  --.-KB/s               

11106 13:55:43.536504  kselftest.tar.xz      1%[                    ]  49.22K   186KB/s               

11107 13:55:43.851744  kselftest.tar.xz      7%[>                   ] 218.91K   412KB/s               

11108 13:55:44.068921  kselftest.tar.xz     28%[====>               ] 828.37K   978KB/s               

11109 13:55:44.236867  kselftest.tar.xz     70%[=============>      ]   1.98M  1.86MB/s               

11110 13:55:44.243118  kselftest.tar.xz    100%[===================>]   2.83M  2.30MB/s    in 1.2s    

11111 13:55:44.243208  

11112 13:55:44.500555  2024-02-01 13:55:04 (2.30 MB/s) - 'kselftest.tar.xz' saved [2966796/2966796]

11113 13:55:44.500708  

11114 13:55:50.047098  skiplist:

11115 13:55:50.049906  ========================================

11116 13:55:50.052773  ========================================

11117 13:55:50.099670  tpm2:test_smoke.sh

11118 13:55:50.102959  tpm2:test_space.sh

11119 13:55:50.117523  ============== Tests to run ===============

11120 13:55:50.117608  tpm2:test_smoke.sh

11121 13:55:50.121093  tpm2:test_space.sh

11122 13:55:50.124183  ===========End Tests to run ===============

11123 13:55:50.127551  shardfile-tpm2 pass

11124 13:55:50.230758  <12>[   35.948609] kselftest: Running tests in tpm2

11125 13:55:50.240434  TAP version 13

11126 13:55:50.252541  1..2

11127 13:55:50.282108  # selftests: tpm2: test_smoke.sh

11128 13:55:51.747484  # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR

11129 13:55:51.750946  # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR

11130 13:55:51.757547  # Exception ignored in: <function Client.__del__ at 0xffffaf491d30>

11131 13:55:51.760836  # Traceback (most recent call last):

11132 13:55:51.770997  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11133 13:55:51.771595  #     if self.tpm:

11134 13:55:51.777662  # AttributeError: 'Client' object has no attribute 'tpm'

11135 13:55:51.781222  # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR

11136 13:55:51.787543  # Exception ignored in: <function Client.__del__ at 0xffffaf491d30>

11137 13:55:51.790587  # Traceback (most recent call last):

11138 13:55:51.800920  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11139 13:55:51.804447  #     if self.tpm:

11140 13:55:51.807278  # AttributeError: 'Client' object has no attribute 'tpm'

11141 13:55:51.814117  # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR

11142 13:55:51.821011  # Exception ignored in: <function Client.__del__ at 0xffffaf491d30>

11143 13:55:51.823992  # Traceback (most recent call last):

11144 13:55:51.830617  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11145 13:55:51.834153  #     if self.tpm:

11146 13:55:51.837681  # AttributeError: 'Client' object has no attribute 'tpm'

11147 13:55:51.844295  # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR

11148 13:55:51.850619  # Exception ignored in: <function Client.__del__ at 0xffffaf491d30>

11149 13:55:51.853994  # Traceback (most recent call last):

11150 13:55:51.864123  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11151 13:55:51.864605  #     if self.tpm:

11152 13:55:51.870493  # AttributeError: 'Client' object has no attribute 'tpm'

11153 13:55:51.874082  # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR

11154 13:55:51.880827  # Exception ignored in: <function Client.__del__ at 0xffffaf491d30>

11155 13:55:51.884384  # Traceback (most recent call last):

11156 13:55:51.893893  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11157 13:55:51.897501  #     if self.tpm:

11158 13:55:51.900751  # AttributeError: 'Client' object has no attribute 'tpm'

11159 13:55:51.907152  # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR

11160 13:55:51.910965  # Exception ignored in: <function Client.__del__ at 0xffffaf491d30>

11161 13:55:51.913983  # Traceback (most recent call last):

11162 13:55:51.924076  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11163 13:55:51.927175  #     if self.tpm:

11164 13:55:51.930626  # AttributeError: 'Client' object has no attribute 'tpm'

11165 13:55:51.937215  # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR

11166 13:55:51.943791  # Exception ignored in: <function Client.__del__ at 0xffffaf491d30>

11167 13:55:51.947085  # Traceback (most recent call last):

11168 13:55:51.957160  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11169 13:55:51.957738  #     if self.tpm:

11170 13:55:51.963942  # AttributeError: 'Client' object has no attribute 'tpm'

11171 13:55:51.970250  # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR

11172 13:55:51.973609  # Exception ignored in: <function Client.__del__ at 0xffffaf491d30>

11173 13:55:51.977014  # Traceback (most recent call last):

11174 13:55:51.987130  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__

11175 13:55:51.990444  #     if self.tpm:

11176 13:55:51.993903  # AttributeError: 'Client' object has no attribute 'tpm'

11177 13:55:51.994403  # 

11178 13:55:52.000305  # ======================================================================

11179 13:55:52.007133  # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)

11180 13:55:52.013485  # ----------------------------------------------------------------------

11181 13:55:52.017118  # Traceback (most recent call last):

11182 13:55:52.027011  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp

11183 13:55:52.030051  #     self.root_key = self.client.create_root_key()

11184 13:55:52.040416  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11185 13:55:52.046874  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11186 13:55:52.058098  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11187 13:55:52.061930  #     raise ProtocolError(cc, rc)

11188 13:55:52.065514  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11189 13:55:52.066137  # 

11190 13:55:52.072096  # ======================================================================

11191 13:55:52.078518  # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)

11192 13:55:52.085661  # ----------------------------------------------------------------------

11193 13:55:52.089350  # Traceback (most recent call last):

11194 13:55:52.098849  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11195 13:55:52.102634  #     self.client = tpm2.Client()

11196 13:55:52.112380  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11197 13:55:52.115460  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11198 13:55:52.122009  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11199 13:55:52.122494  # 

11200 13:55:52.128973  # ======================================================================

11201 13:55:52.131888  # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)

11202 13:55:52.138783  # ----------------------------------------------------------------------

11203 13:55:52.142080  # Traceback (most recent call last):

11204 13:55:52.151704  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11205 13:55:52.154821  #     self.client = tpm2.Client()

11206 13:55:52.164987  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11207 13:55:52.168704  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11208 13:55:52.175309  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11209 13:55:52.175792  # 

11210 13:55:52.181812  # ======================================================================

11211 13:55:52.184907  # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)

11212 13:55:52.191582  # ----------------------------------------------------------------------

11213 13:55:52.195249  # Traceback (most recent call last):

11214 13:55:52.205344  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11215 13:55:52.208482  #     self.client = tpm2.Client()

11216 13:55:52.218647  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11217 13:55:52.225290  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11218 13:55:52.228537  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11219 13:55:52.229011  # 

11220 13:55:52.235257  # ======================================================================

11221 13:55:52.241791  # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)

11222 13:55:52.248781  # ----------------------------------------------------------------------

11223 13:55:52.251834  # Traceback (most recent call last):

11224 13:55:52.262028  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11225 13:55:52.265317  #     self.client = tpm2.Client()

11226 13:55:52.275055  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11227 13:55:52.278530  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11228 13:55:52.284979  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11229 13:55:52.285410  # 

11230 13:55:52.291630  # ======================================================================

11231 13:55:52.295058  # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)

11232 13:55:52.301651  # ----------------------------------------------------------------------

11233 13:55:52.305114  # Traceback (most recent call last):

11234 13:55:52.315097  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11235 13:55:52.318461  #     self.client = tpm2.Client()

11236 13:55:52.328346  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11237 13:55:52.332367  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11238 13:55:52.341771  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11239 13:55:52.342370  # 

11240 13:55:52.344860  # ======================================================================

11241 13:55:52.348501  # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)

11242 13:55:52.357034  # ----------------------------------------------------------------------

11243 13:55:52.360552  # Traceback (most recent call last):

11244 13:55:52.367631  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11245 13:55:52.371235  #     self.client = tpm2.Client()

11246 13:55:52.381803  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11247 13:55:52.385512  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11248 13:55:52.392997  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11249 13:55:52.393435  # 

11250 13:55:52.400335  # ======================================================================

11251 13:55:52.403918  # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)

11252 13:55:52.410688  # ----------------------------------------------------------------------

11253 13:55:52.413759  # Traceback (most recent call last):

11254 13:55:52.424290  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11255 13:55:52.427917  #     self.client = tpm2.Client()

11256 13:55:52.437741  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11257 13:55:52.440986  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11258 13:55:52.447830  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11259 13:55:52.448420  # 

11260 13:55:52.453795  # ======================================================================

11261 13:55:52.460818  # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)

11262 13:55:52.463820  # ----------------------------------------------------------------------

11263 13:55:52.467318  # Traceback (most recent call last):

11264 13:55:52.477598  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp

11265 13:55:52.480634  #     self.client = tpm2.Client()

11266 13:55:52.490611  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__

11267 13:55:52.496976  #     self.tpm = open('/dev/tpm0', 'r+b', buffering=0)

11268 13:55:52.500598  # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'

11269 13:55:52.504169  # 

11270 13:55:52.507360  # ----------------------------------------------------------------------

11271 13:55:52.510418  # Ran 9 tests in 0.051s

11272 13:55:52.510888  # 

11273 13:55:52.514040  # FAILED (errors=9)

11274 13:55:52.517374  # test_async (tpm2_tests.AsyncTest) ... ok

11275 13:55:52.520695  # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok

11276 13:55:52.523728  # 

11277 13:55:52.527138  # ----------------------------------------------------------------------

11278 13:55:52.530883  # Ran 2 tests in 0.038s

11279 13:55:52.531316  # 

11280 13:55:52.531656  # OK

11281 13:55:52.534197  ok 1 selftests: tpm2: test_smoke.sh

11282 13:55:52.537471  # selftests: tpm2: test_space.sh

11283 13:55:52.543927  # test_flush_context (tpm2_tests.SpaceTest) ... ERROR

11284 13:55:52.547324  # test_get_handles (tpm2_tests.SpaceTest) ... ERROR

11285 13:55:52.550817  # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR

11286 13:55:52.557632  # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR

11287 13:55:52.558223  # 

11288 13:55:52.564179  # ======================================================================

11289 13:55:52.567415  # ERROR: test_flush_context (tpm2_tests.SpaceTest)

11290 13:55:52.573585  # ----------------------------------------------------------------------

11291 13:55:52.577112  # Traceback (most recent call last):

11292 13:55:52.590162  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context

11293 13:55:52.593608  #     root1 = space1.create_root_key()

11294 13:55:52.603603  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11295 13:55:52.610136  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11296 13:55:52.617106  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11297 13:55:52.620727  #     raise ProtocolError(cc, rc)

11298 13:55:52.627165  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11299 13:55:52.627746  # 

11300 13:55:52.633767  # ======================================================================

11301 13:55:52.640525  # ERROR: test_get_handles (tpm2_tests.SpaceTest)

11302 13:55:52.643802  # ----------------------------------------------------------------------

11303 13:55:52.647291  # Traceback (most recent call last):

11304 13:55:52.660493  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles

11305 13:55:52.663958  #     space1.create_root_key()

11306 13:55:52.673452  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11307 13:55:52.676945  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11308 13:55:52.687132  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11309 13:55:52.690226  #     raise ProtocolError(cc, rc)

11310 13:55:52.696907  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11311 13:55:52.697023  # 

11312 13:55:52.703686  # ======================================================================

11313 13:55:52.706781  # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)

11314 13:55:52.713475  # ----------------------------------------------------------------------

11315 13:55:52.717091  # Traceback (most recent call last):

11316 13:55:52.730637  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc

11317 13:55:52.733805  #     root1 = space1.create_root_key()

11318 13:55:52.743881  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11319 13:55:52.747286  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11320 13:55:52.757205  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11321 13:55:52.760579  #     raise ProtocolError(cc, rc)

11322 13:55:52.767392  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11323 13:55:52.767972  # 

11324 13:55:52.773574  # ======================================================================

11325 13:55:52.780309  # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)

11326 13:55:52.786869  # ----------------------------------------------------------------------

11327 13:55:52.790285  # Traceback (most recent call last):

11328 13:55:52.800045  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces

11329 13:55:52.803783  #     root1 = space1.create_root_key()

11330 13:55:52.813642  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key

11331 13:55:52.820169  #     return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]

11332 13:55:52.830240  #   File "/lava-12682923/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd

11333 13:55:52.833380  #     raise ProtocolError(cc, rc)

11334 13:55:52.840039  # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2

11335 13:55:52.840626  # 

11336 13:55:52.846974  # ----------------------------------------------------------------------

11337 13:55:52.847454  # Ran 4 tests in 0.087s

11338 13:55:52.847948  # 

11339 13:55:52.850137  # FAILED (errors=4)

11340 13:55:52.853242  not ok 2 selftests: tpm2: test_space.sh # exit=1

11341 13:55:52.886849  tpm2_test_smoke_sh pass

11342 13:55:52.890119  tpm2_test_space_sh fail

11343 13:55:52.906935  + ../../utils/send-to-lava.sh ./output/result.txt

11344 13:55:52.970161  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>

11345 13:55:52.970982  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11347 13:55:53.024742  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>

11348 13:55:53.025005  Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11350 13:55:53.075286  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>

11351 13:55:53.075565  Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11353 13:55:53.078691  + set +x

11354 13:55:53.081776  <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12682923_1.6.2.3.5>

11355 13:55:53.082163  Received signal: <ENDRUN> 1_kselftest-tpm2 12682923_1.6.2.3.5
11356 13:55:53.082281  Ending use of test pattern.
11357 13:55:53.082368  Ending test lava.1_kselftest-tpm2 (12682923_1.6.2.3.5), duration 10.55
11359 13:55:53.084762  <LAVA_TEST_RUNNER EXIT>

11360 13:55:53.085137  ok: lava_test_shell seems to have completed
11361 13:55:53.085295  shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail

11362 13:55:53.085419  end: 3.1 lava-test-shell (duration 00:00:11) [common]
11363 13:55:53.085533  end: 3 lava-test-retry (duration 00:00:11) [common]
11364 13:55:53.085647  start: 4 finalize (timeout 00:07:38) [common]
11365 13:55:53.085760  start: 4.1 power-off (timeout 00:00:30) [common]
11366 13:55:53.085974  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11367 13:55:53.168717  >> Command sent successfully.

11368 13:55:53.175036  Returned 0 in 0 seconds
11369 13:55:53.276138  end: 4.1 power-off (duration 00:00:00) [common]
11371 13:55:53.278013  start: 4.2 read-feedback (timeout 00:07:38) [common]
11372 13:55:53.279500  Listened to connection for namespace 'common' for up to 1s
11373 13:55:54.280089  Finalising connection for namespace 'common'
11374 13:55:54.280926  Disconnecting from shell: Finalise
11375 13:55:54.281400  / # 
11376 13:55:54.382501  end: 4.2 read-feedback (duration 00:00:01) [common]
11377 13:55:54.383282  end: 4 finalize (duration 00:00:01) [common]
11378 13:55:54.383984  Cleaning after the job
11379 13:55:54.384521  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/ramdisk
11380 13:55:54.395128  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/kernel
11381 13:55:54.427087  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/dtb
11382 13:55:54.427475  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/nfsrootfs
11383 13:55:54.499770  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682923/tftp-deploy-7f8pea4e/modules
11384 13:55:54.505271  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682923
11385 13:55:55.025596  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682923
11386 13:55:55.025792  Job finished correctly