Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 38
- Kernel Errors: 33
1 13:58:43.064572 lava-dispatcher, installed at version: 2023.10
2 13:58:43.064794 start: 0 validate
3 13:58:43.064925 Start time: 2024-02-01 13:58:43.064916+00:00 (UTC)
4 13:58:43.065043 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:58:43.065173 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:58:43.334404 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:58:43.334580 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:58:43.599824 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:58:43.599998 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:58:43.865566 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:58:43.865749 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-31-g9539320ac89dc%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:58:44.132204 validate duration: 1.07
14 13:58:44.132492 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:58:44.132589 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:58:44.132678 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:58:44.132802 Not decompressing ramdisk as can be used compressed.
18 13:58:44.132885 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 13:58:44.132947 saving as /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/ramdisk/rootfs.cpio.gz
20 13:58:44.133009 total size: 84918747 (80 MB)
21 13:58:44.134066 progress 0 % (0 MB)
22 13:58:44.156210 progress 5 % (4 MB)
23 13:58:44.178232 progress 10 % (8 MB)
24 13:58:44.199935 progress 15 % (12 MB)
25 13:58:44.221906 progress 20 % (16 MB)
26 13:58:44.243840 progress 25 % (20 MB)
27 13:58:44.266238 progress 30 % (24 MB)
28 13:58:44.288479 progress 35 % (28 MB)
29 13:58:44.310195 progress 40 % (32 MB)
30 13:58:44.332084 progress 45 % (36 MB)
31 13:58:44.353794 progress 50 % (40 MB)
32 13:58:44.375969 progress 55 % (44 MB)
33 13:58:44.398021 progress 60 % (48 MB)
34 13:58:44.419808 progress 65 % (52 MB)
35 13:58:44.441774 progress 70 % (56 MB)
36 13:58:44.463652 progress 75 % (60 MB)
37 13:58:44.485793 progress 80 % (64 MB)
38 13:58:44.507708 progress 85 % (68 MB)
39 13:58:44.529778 progress 90 % (72 MB)
40 13:58:44.551312 progress 95 % (76 MB)
41 13:58:44.572944 progress 100 % (80 MB)
42 13:58:44.573167 80 MB downloaded in 0.44 s (183.99 MB/s)
43 13:58:44.573335 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:58:44.573581 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:58:44.573668 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:58:44.573751 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:58:44.573888 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:58:44.573959 saving as /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/kernel/Image
50 13:58:44.574018 total size: 51532288 (49 MB)
51 13:58:44.574077 No compression specified
52 13:58:44.575203 progress 0 % (0 MB)
53 13:58:44.588450 progress 5 % (2 MB)
54 13:58:44.601752 progress 10 % (4 MB)
55 13:58:44.615101 progress 15 % (7 MB)
56 13:58:44.628831 progress 20 % (9 MB)
57 13:58:44.642432 progress 25 % (12 MB)
58 13:58:44.655639 progress 30 % (14 MB)
59 13:58:44.669139 progress 35 % (17 MB)
60 13:58:44.682529 progress 40 % (19 MB)
61 13:58:44.695772 progress 45 % (22 MB)
62 13:58:44.709103 progress 50 % (24 MB)
63 13:58:44.722329 progress 55 % (27 MB)
64 13:58:44.735768 progress 60 % (29 MB)
65 13:58:44.749381 progress 65 % (31 MB)
66 13:58:44.762806 progress 70 % (34 MB)
67 13:58:44.776277 progress 75 % (36 MB)
68 13:58:44.789679 progress 80 % (39 MB)
69 13:58:44.802777 progress 85 % (41 MB)
70 13:58:44.816162 progress 90 % (44 MB)
71 13:58:44.829457 progress 95 % (46 MB)
72 13:58:44.842355 progress 100 % (49 MB)
73 13:58:44.842562 49 MB downloaded in 0.27 s (183.01 MB/s)
74 13:58:44.842709 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:58:44.842941 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:58:44.843026 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:58:44.843114 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:58:44.843255 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:58:44.843328 saving as /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/dtb/mt8192-asurada-spherion-r0.dtb
81 13:58:44.843389 total size: 47278 (0 MB)
82 13:58:44.843449 No compression specified
83 13:58:44.844585 progress 69 % (0 MB)
84 13:58:44.844858 progress 100 % (0 MB)
85 13:58:44.845012 0 MB downloaded in 0.00 s (27.82 MB/s)
86 13:58:44.845133 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:58:44.845350 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:58:44.845439 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:58:44.845523 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:58:44.845634 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-31-g9539320ac89dc/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:58:44.845703 saving as /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/modules/modules.tar
93 13:58:44.845762 total size: 8623988 (8 MB)
94 13:58:44.845822 Using unxz to decompress xz
95 13:58:44.850047 progress 0 % (0 MB)
96 13:58:44.871110 progress 5 % (0 MB)
97 13:58:44.894802 progress 10 % (0 MB)
98 13:58:44.918059 progress 15 % (1 MB)
99 13:58:44.941284 progress 20 % (1 MB)
100 13:58:44.966832 progress 25 % (2 MB)
101 13:58:44.993177 progress 30 % (2 MB)
102 13:58:45.019459 progress 35 % (2 MB)
103 13:58:45.042507 progress 40 % (3 MB)
104 13:58:45.066733 progress 45 % (3 MB)
105 13:58:45.091816 progress 50 % (4 MB)
106 13:58:45.115824 progress 55 % (4 MB)
107 13:58:45.140482 progress 60 % (4 MB)
108 13:58:45.167779 progress 65 % (5 MB)
109 13:58:45.192660 progress 70 % (5 MB)
110 13:58:45.215727 progress 75 % (6 MB)
111 13:58:45.242537 progress 80 % (6 MB)
112 13:58:45.268458 progress 85 % (7 MB)
113 13:58:45.293224 progress 90 % (7 MB)
114 13:58:45.324510 progress 95 % (7 MB)
115 13:58:45.352080 progress 100 % (8 MB)
116 13:58:45.357047 8 MB downloaded in 0.51 s (16.09 MB/s)
117 13:58:45.357364 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:58:45.357642 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:58:45.357735 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:58:45.357832 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:58:45.357913 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:58:45.358003 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:58:45.358225 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze
125 13:58:45.358359 makedir: /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin
126 13:58:45.358463 makedir: /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/tests
127 13:58:45.358562 makedir: /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/results
128 13:58:45.358680 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-add-keys
129 13:58:45.358830 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-add-sources
130 13:58:45.358962 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-background-process-start
131 13:58:45.359090 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-background-process-stop
132 13:58:45.359216 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-common-functions
133 13:58:45.359408 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-echo-ipv4
134 13:58:45.359533 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-install-packages
135 13:58:45.359658 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-installed-packages
136 13:58:45.359783 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-os-build
137 13:58:45.359909 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-probe-channel
138 13:58:45.360033 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-probe-ip
139 13:58:45.360157 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-target-ip
140 13:58:45.360280 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-target-mac
141 13:58:45.360445 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-target-storage
142 13:58:45.360573 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-test-case
143 13:58:45.360699 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-test-event
144 13:58:45.360824 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-test-feedback
145 13:58:45.360948 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-test-raise
146 13:58:45.361073 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-test-reference
147 13:58:45.361195 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-test-runner
148 13:58:45.361319 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-test-set
149 13:58:45.361474 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-test-shell
150 13:58:45.361601 Updating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-install-packages (oe)
151 13:58:45.361754 Updating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/bin/lava-installed-packages (oe)
152 13:58:45.361882 Creating /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/environment
153 13:58:45.361982 LAVA metadata
154 13:58:45.362056 - LAVA_JOB_ID=12682961
155 13:58:45.362119 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:58:45.362223 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:58:45.362290 skipped lava-vland-overlay
158 13:58:45.362362 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:58:45.362443 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:58:45.362507 skipped lava-multinode-overlay
161 13:58:45.362579 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:58:45.362663 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:58:45.362737 Loading test definitions
164 13:58:45.362824 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 13:58:45.362899 Using /lava-12682961 at stage 0
166 13:58:45.362997 Fetching tests from https://github.com/kernelci/kernelci-core
167 13:58:45.363079 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/0/tests/0_sleep'
168 13:58:46.387123 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/0/tests/0_sleep
169 13:58:46.388501 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 13:58:46.388903 uuid=12682961_1.5.2.3.1 testdef=None
171 13:58:46.389065 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 13:58:46.389341 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 13:58:46.390056 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 13:58:46.390317 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 13:58:46.391072 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 13:58:46.391337 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 13:58:46.392013 runner path: /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/0/tests/0_sleep test_uuid 12682961_1.5.2.3.1
181 13:58:46.392104 sleep_params='mem'
182 13:58:46.392325 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 13:58:46.392578 Creating lava-test-runner.conf files
185 13:58:46.392665 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12682961/lava-overlay-fy807uze/lava-12682961/0 for stage 0
186 13:58:46.392804 - 0_sleep
187 13:58:46.392955 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 13:58:46.393059 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 13:58:46.528715 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 13:58:46.528872 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 13:58:46.528990 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 13:58:46.529105 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 13:58:46.529207 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 13:58:48.999387 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 13:58:48.999799 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 13:58:48.999987 extracting modules file /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12682961/extract-overlay-ramdisk-b6r4movu/ramdisk
197 13:58:49.242687 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 13:58:49.242872 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 13:58:49.242995 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682961/compress-overlay-bfmjy8zb/overlay-1.5.2.4.tar.gz to ramdisk
200 13:58:49.243080 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12682961/compress-overlay-bfmjy8zb/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12682961/extract-overlay-ramdisk-b6r4movu/ramdisk
201 13:58:49.343200 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 13:58:49.343378 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 13:58:49.343494 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 13:58:49.343599 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 13:58:49.343692 Building ramdisk /var/lib/lava/dispatcher/tmp/12682961/extract-overlay-ramdisk-b6r4movu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12682961/extract-overlay-ramdisk-b6r4movu/ramdisk
206 13:58:50.976563 >> 563683 blocks
207 13:59:00.581679 rename /var/lib/lava/dispatcher/tmp/12682961/extract-overlay-ramdisk-b6r4movu/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/ramdisk/ramdisk.cpio.gz
208 13:59:00.582129 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 13:59:00.582252 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 13:59:00.582348 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 13:59:00.582463 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/kernel/Image'
212 13:59:13.682354 Returned 0 in 13 seconds
213 13:59:13.783100 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/kernel/image.itb
214 13:59:15.152869 output: FIT description: Kernel Image image with one or more FDT blobs
215 13:59:15.153268 output: Created: Thu Feb 1 13:59:14 2024
216 13:59:15.153350 output: Image 0 (kernel-1)
217 13:59:15.153418 output: Description:
218 13:59:15.153481 output: Created: Thu Feb 1 13:59:14 2024
219 13:59:15.153554 output: Type: Kernel Image
220 13:59:15.153614 output: Compression: lzma compressed
221 13:59:15.153670 output: Data Size: 12046857 Bytes = 11764.51 KiB = 11.49 MiB
222 13:59:15.153727 output: Architecture: AArch64
223 13:59:15.153790 output: OS: Linux
224 13:59:15.153883 output: Load Address: 0x00000000
225 13:59:15.153941 output: Entry Point: 0x00000000
226 13:59:15.154031 output: Hash algo: crc32
227 13:59:15.154125 output: Hash value: 5aa40db2
228 13:59:15.154215 output: Image 1 (fdt-1)
229 13:59:15.154301 output: Description: mt8192-asurada-spherion-r0
230 13:59:15.154395 output: Created: Thu Feb 1 13:59:14 2024
231 13:59:15.154479 output: Type: Flat Device Tree
232 13:59:15.154562 output: Compression: uncompressed
233 13:59:15.154652 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 13:59:15.154735 output: Architecture: AArch64
235 13:59:15.154817 output: Hash algo: crc32
236 13:59:15.154909 output: Hash value: cc4352de
237 13:59:15.154995 output: Image 2 (ramdisk-1)
238 13:59:15.155083 output: Description: unavailable
239 13:59:15.155170 output: Created: Thu Feb 1 13:59:14 2024
240 13:59:15.155252 output: Type: RAMDisk Image
241 13:59:15.155341 output: Compression: Unknown Compression
242 13:59:15.155426 output: Data Size: 98353149 Bytes = 96048.00 KiB = 93.80 MiB
243 13:59:15.155511 output: Architecture: AArch64
244 13:59:15.155602 output: OS: Linux
245 13:59:15.155686 output: Load Address: unavailable
246 13:59:15.155768 output: Entry Point: unavailable
247 13:59:15.155857 output: Hash algo: crc32
248 13:59:15.155947 output: Hash value: 2d2f2c39
249 13:59:15.156046 output: Default Configuration: 'conf-1'
250 13:59:15.156121 output: Configuration 0 (conf-1)
251 13:59:15.156175 output: Description: mt8192-asurada-spherion-r0
252 13:59:15.156228 output: Kernel: kernel-1
253 13:59:15.156281 output: Init Ramdisk: ramdisk-1
254 13:59:15.156358 output: FDT: fdt-1
255 13:59:15.156413 output: Loadables: kernel-1
256 13:59:15.156466 output:
257 13:59:15.156690 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 13:59:15.156824 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 13:59:15.156970 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
260 13:59:15.157108 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
261 13:59:15.157193 No LXC device requested
262 13:59:15.157285 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 13:59:15.157407 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
264 13:59:15.157521 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 13:59:15.157631 Checking files for TFTP limit of 4294967296 bytes.
266 13:59:15.158330 end: 1 tftp-deploy (duration 00:00:31) [common]
267 13:59:15.158475 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 13:59:15.158602 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 13:59:15.158776 substitutions:
270 13:59:15.158881 - {DTB}: 12682961/tftp-deploy-w8a_okmr/dtb/mt8192-asurada-spherion-r0.dtb
271 13:59:15.158977 - {INITRD}: 12682961/tftp-deploy-w8a_okmr/ramdisk/ramdisk.cpio.gz
272 13:59:15.159069 - {KERNEL}: 12682961/tftp-deploy-w8a_okmr/kernel/Image
273 13:59:15.159161 - {LAVA_MAC}: None
274 13:59:15.159247 - {PRESEED_CONFIG}: None
275 13:59:15.159340 - {PRESEED_LOCAL}: None
276 13:59:15.159427 - {RAMDISK}: 12682961/tftp-deploy-w8a_okmr/ramdisk/ramdisk.cpio.gz
277 13:59:15.159512 - {ROOT_PART}: None
278 13:59:15.159605 - {ROOT}: None
279 13:59:15.159690 - {SERVER_IP}: 192.168.201.1
280 13:59:15.159774 - {TEE}: None
281 13:59:15.159858 Parsed boot commands:
282 13:59:15.159921 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 13:59:15.160136 Parsed boot commands: tftpboot 192.168.201.1 12682961/tftp-deploy-w8a_okmr/kernel/image.itb 12682961/tftp-deploy-w8a_okmr/kernel/cmdline
284 13:59:15.160257 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 13:59:15.160403 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 13:59:15.160537 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 13:59:15.160661 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 13:59:15.160763 Not connected, no need to disconnect.
289 13:59:15.160906 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 13:59:15.161029 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 13:59:15.161144 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 13:59:15.165603 Setting prompt string to ['lava-test: # ']
293 13:59:15.166032 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 13:59:15.166189 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 13:59:15.166320 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 13:59:15.166455 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 13:59:15.166802 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 13:59:20.299496 >> Command sent successfully.
299 13:59:20.302232 Returned 0 in 5 seconds
300 13:59:20.402666 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 13:59:20.402999 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 13:59:20.403105 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 13:59:20.403191 Setting prompt string to 'Starting depthcharge on Spherion...'
305 13:59:20.403263 Changing prompt to 'Starting depthcharge on Spherion...'
306 13:59:20.403333 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 13:59:20.403602 [Enter `^Ec?' for help]
308 13:59:20.576562
309 13:59:20.576711
310 13:59:20.576786 F0: 102B 0000
311 13:59:20.576860
312 13:59:20.576921 F3: 1001 0000 [0200]
313 13:59:20.576978
314 13:59:20.580449 F3: 1001 0000
315 13:59:20.580523
316 13:59:20.580584 F7: 102D 0000
317 13:59:20.580641
318 13:59:20.580697 F1: 0000 0000
319 13:59:20.580759
320 13:59:20.584014 V0: 0000 0000 [0001]
321 13:59:20.584085
322 13:59:20.584145 00: 0007 8000
323 13:59:20.584207
324 13:59:20.587806 01: 0000 0000
325 13:59:20.587878
326 13:59:20.587939 BP: 0C00 0209 [0000]
327 13:59:20.587997
328 13:59:20.591760 G0: 1182 0000
329 13:59:20.591831
330 13:59:20.591891 EC: 0000 0021 [4000]
331 13:59:20.591954
332 13:59:20.595622 S7: 0000 0000 [0000]
333 13:59:20.595693
334 13:59:20.595761 CC: 0000 0000 [0001]
335 13:59:20.595818
336 13:59:20.598375 T0: 0000 0040 [010F]
337 13:59:20.598445
338 13:59:20.598502 Jump to BL
339 13:59:20.598557
340 13:59:20.623943
341 13:59:20.624057
342 13:59:20.624134
343 13:59:20.631377 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 13:59:20.635133 ARM64: Exception handlers installed.
345 13:59:20.638677 ARM64: Testing exception
346 13:59:20.642110 ARM64: Done test exception
347 13:59:20.649420 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 13:59:20.656491 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 13:59:20.663411 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 13:59:20.674549 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 13:59:20.681091 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 13:59:20.691641 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 13:59:20.702008 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 13:59:20.708497 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 13:59:20.726341 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 13:59:20.729541 WDT: Last reset was cold boot
357 13:59:20.733323 SPI1(PAD0) initialized at 2873684 Hz
358 13:59:20.736687 SPI5(PAD0) initialized at 992727 Hz
359 13:59:20.739716 VBOOT: Loading verstage.
360 13:59:20.746274 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 13:59:20.749569 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 13:59:20.753007 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 13:59:20.756468 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 13:59:20.763927 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 13:59:20.770379 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 13:59:20.781936 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 13:59:20.782019
368 13:59:20.782083
369 13:59:20.791919 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 13:59:20.795217 ARM64: Exception handlers installed.
371 13:59:20.795294 ARM64: Testing exception
372 13:59:20.799048 ARM64: Done test exception
373 13:59:20.802142 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 13:59:20.808716 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 13:59:20.822393 Probing TPM: . done!
376 13:59:20.822500 TPM ready after 0 ms
377 13:59:20.829646 Connected to device vid:did:rid of 1ae0:0028:00
378 13:59:20.837520 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 13:59:20.895572 Initialized TPM device CR50 revision 0
380 13:59:20.906761 tlcl_send_startup: Startup return code is 0
381 13:59:20.906854 TPM: setup succeeded
382 13:59:20.918415 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 13:59:20.927363 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 13:59:20.941844 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 13:59:20.948802 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 13:59:20.952779 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 13:59:20.955964 in-header: 03 07 00 00 08 00 00 00
388 13:59:20.960049 in-data: aa e4 47 04 13 02 00 00
389 13:59:20.960123 Chrome EC: UHEPI supported
390 13:59:20.967405 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 13:59:20.971216 in-header: 03 95 00 00 08 00 00 00
392 13:59:20.975179 in-data: 18 20 20 08 00 00 00 00
393 13:59:20.975252 Phase 1
394 13:59:20.978538 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 13:59:20.986638 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 13:59:20.993660 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 13:59:20.993737 Recovery requested (1009000e)
398 13:59:21.006470 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 13:59:21.009892 tlcl_extend: response is 0
400 13:59:21.021137 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 13:59:21.024967 tlcl_extend: response is 0
402 13:59:21.032056 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 13:59:21.051319 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 13:59:21.058120 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 13:59:21.058199
406 13:59:21.058264
407 13:59:21.067731 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 13:59:21.070994 ARM64: Exception handlers installed.
409 13:59:21.074227 ARM64: Testing exception
410 13:59:21.074303 ARM64: Done test exception
411 13:59:21.096673 pmic_efuse_setting: Set efuses in 11 msecs
412 13:59:21.100624 pmwrap_interface_init: Select PMIF_VLD_RDY
413 13:59:21.107150 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 13:59:21.110376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 13:59:21.113965 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 13:59:21.121264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 13:59:21.124971 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 13:59:21.128628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 13:59:21.136344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 13:59:21.140235 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 13:59:21.143447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 13:59:21.147360 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 13:59:21.154868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 13:59:21.158804 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 13:59:21.162580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 13:59:21.170379 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 13:59:21.173948 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 13:59:21.181381 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 13:59:21.185429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 13:59:21.192787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 13:59:21.197141 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 13:59:21.204599 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 13:59:21.208505 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 13:59:21.215588 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 13:59:21.219606 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 13:59:21.226615 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 13:59:21.230838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 13:59:21.237635 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 13:59:21.241418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 13:59:21.244837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 13:59:21.252518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 13:59:21.255767 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 13:59:21.259574 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 13:59:21.266545 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 13:59:21.270585 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 13:59:21.277678 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 13:59:21.281399 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 13:59:21.285270 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 13:59:21.292529 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 13:59:21.296570 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 13:59:21.300084 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 13:59:21.304001 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 13:59:21.307705 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 13:59:21.314963 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 13:59:21.318923 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 13:59:21.322930 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 13:59:21.326285 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 13:59:21.330494 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 13:59:21.333440 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 13:59:21.341080 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 13:59:21.344608 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 13:59:21.348090 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 13:59:21.352239 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 13:59:21.359681 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 13:59:21.366866 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 13:59:21.374527 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 13:59:21.381775 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 13:59:21.389519 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 13:59:21.392894 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 13:59:21.400269 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 13:59:21.403989 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 13:59:21.411270 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x8
473 13:59:21.414552 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 13:59:21.422526 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 13:59:21.425981 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 13:59:21.434760 [RTC]rtc_get_frequency_meter,154: input=15, output=759
477 13:59:21.443598 [RTC]rtc_get_frequency_meter,154: input=23, output=942
478 13:59:21.453884 [RTC]rtc_get_frequency_meter,154: input=19, output=850
479 13:59:21.463489 [RTC]rtc_get_frequency_meter,154: input=17, output=803
480 13:59:21.472586 [RTC]rtc_get_frequency_meter,154: input=16, output=781
481 13:59:21.482213 [RTC]rtc_get_frequency_meter,154: input=16, output=782
482 13:59:21.491884 [RTC]rtc_get_frequency_meter,154: input=17, output=803
483 13:59:21.495190 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 13:59:21.499285 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 13:59:21.503128 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 13:59:21.510521 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 13:59:21.514435 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 13:59:21.517892 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 13:59:21.520990 ADC[4]: Raw value=905465 ID=7
490 13:59:21.521066 ADC[3]: Raw value=213441 ID=1
491 13:59:21.524857 RAM Code: 0x71
492 13:59:21.528690 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 13:59:21.532810 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 13:59:21.544022 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 13:59:21.548020 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 13:59:21.551903 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 13:59:21.555409 in-header: 03 07 00 00 08 00 00 00
498 13:59:21.559648 in-data: aa e4 47 04 13 02 00 00
499 13:59:21.563391 Chrome EC: UHEPI supported
500 13:59:21.566850 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 13:59:21.572086 in-header: 03 95 00 00 08 00 00 00
502 13:59:21.576065 in-data: 18 20 20 08 00 00 00 00
503 13:59:21.579844 MRC: failed to locate region type 0.
504 13:59:21.587187 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 13:59:21.587265 DRAM-K: Running full calibration
506 13:59:21.594770 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 13:59:21.598006 header.status = 0x0
508 13:59:21.602105 header.version = 0x6 (expected: 0x6)
509 13:59:21.605443 header.size = 0xd00 (expected: 0xd00)
510 13:59:21.605523 header.flags = 0x0
511 13:59:21.612469 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 13:59:21.629561 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
513 13:59:21.637508 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 13:59:21.637587 dram_init: ddr_geometry: 2
515 13:59:21.641401 [EMI] MDL number = 2
516 13:59:21.645089 [EMI] Get MDL freq = 0
517 13:59:21.645163 dram_init: ddr_type: 0
518 13:59:21.648993 is_discrete_lpddr4: 1
519 13:59:21.649071 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 13:59:21.649141
521 13:59:21.652201
522 13:59:21.652300 [Bian_co] ETT version 0.0.0.1
523 13:59:21.656199 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 13:59:21.660516
525 13:59:21.660598 dramc_set_vcore_voltage set vcore to 650000
526 13:59:21.664310 Read voltage for 800, 4
527 13:59:21.664397 Vio18 = 0
528 13:59:21.667878 Vcore = 650000
529 13:59:21.667955 Vdram = 0
530 13:59:21.668045 Vddq = 0
531 13:59:21.668102 Vmddr = 0
532 13:59:21.671885 dram_init: config_dvfs: 1
533 13:59:21.675309 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 13:59:21.683005 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 13:59:21.686819 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 13:59:21.690756 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 13:59:21.694076 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 13:59:21.697097 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 13:59:21.700231 MEM_TYPE=3, freq_sel=18
540 13:59:21.703844 sv_algorithm_assistance_LP4_1600
541 13:59:21.707674 ============ PULL DRAM RESETB DOWN ============
542 13:59:21.710993 ========== PULL DRAM RESETB DOWN end =========
543 13:59:21.714815 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 13:59:21.718102 ===================================
545 13:59:21.721411 LPDDR4 DRAM CONFIGURATION
546 13:59:21.725307 ===================================
547 13:59:21.725385 EX_ROW_EN[0] = 0x0
548 13:59:21.729282 EX_ROW_EN[1] = 0x0
549 13:59:21.729356 LP4Y_EN = 0x0
550 13:59:21.732513 WORK_FSP = 0x0
551 13:59:21.732584 WL = 0x2
552 13:59:21.735787 RL = 0x2
553 13:59:21.735859 BL = 0x2
554 13:59:21.739230 RPST = 0x0
555 13:59:21.739299 RD_PRE = 0x0
556 13:59:21.742559 WR_PRE = 0x1
557 13:59:21.742634 WR_PST = 0x0
558 13:59:21.745946 DBI_WR = 0x0
559 13:59:21.746013 DBI_RD = 0x0
560 13:59:21.749704 OTF = 0x1
561 13:59:21.752758 ===================================
562 13:59:21.756636 ===================================
563 13:59:21.756706 ANA top config
564 13:59:21.760581 ===================================
565 13:59:21.763440 DLL_ASYNC_EN = 0
566 13:59:21.763510 ALL_SLAVE_EN = 1
567 13:59:21.766963 NEW_RANK_MODE = 1
568 13:59:21.770271 DLL_IDLE_MODE = 1
569 13:59:21.773882 LP45_APHY_COMB_EN = 1
570 13:59:21.777781 TX_ODT_DIS = 1
571 13:59:21.777853 NEW_8X_MODE = 1
572 13:59:21.781051 ===================================
573 13:59:21.784305 ===================================
574 13:59:21.788225 data_rate = 1600
575 13:59:21.791314 CKR = 1
576 13:59:21.794352 DQ_P2S_RATIO = 8
577 13:59:21.797835 ===================================
578 13:59:21.797905 CA_P2S_RATIO = 8
579 13:59:21.801061 DQ_CA_OPEN = 0
580 13:59:21.804501 DQ_SEMI_OPEN = 0
581 13:59:21.808064 CA_SEMI_OPEN = 0
582 13:59:21.811337 CA_FULL_RATE = 0
583 13:59:21.814808 DQ_CKDIV4_EN = 1
584 13:59:21.814880 CA_CKDIV4_EN = 1
585 13:59:21.818027 CA_PREDIV_EN = 0
586 13:59:21.821680 PH8_DLY = 0
587 13:59:21.824776 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 13:59:21.828037 DQ_AAMCK_DIV = 4
589 13:59:21.828109 CA_AAMCK_DIV = 4
590 13:59:21.831661 CA_ADMCK_DIV = 4
591 13:59:21.834833 DQ_TRACK_CA_EN = 0
592 13:59:21.838471 CA_PICK = 800
593 13:59:21.841818 CA_MCKIO = 800
594 13:59:21.845727 MCKIO_SEMI = 0
595 13:59:21.845803 PLL_FREQ = 3068
596 13:59:21.849627 DQ_UI_PI_RATIO = 32
597 13:59:21.852996 CA_UI_PI_RATIO = 0
598 13:59:21.856154 ===================================
599 13:59:21.859896 ===================================
600 13:59:21.859970 memory_type:LPDDR4
601 13:59:21.863693 GP_NUM : 10
602 13:59:21.867702 SRAM_EN : 1
603 13:59:21.867775 MD32_EN : 0
604 13:59:21.871267 ===================================
605 13:59:21.874928 [ANA_INIT] >>>>>>>>>>>>>>
606 13:59:21.875007 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 13:59:21.878402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 13:59:21.881972 ===================================
609 13:59:21.885217 data_rate = 1600,PCW = 0X7600
610 13:59:21.888471 ===================================
611 13:59:21.891735 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 13:59:21.898956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 13:59:21.902192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 13:59:21.908840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 13:59:21.912194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 13:59:21.915551 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 13:59:21.915627 [ANA_INIT] flow start
618 13:59:21.918339 [ANA_INIT] PLL >>>>>>>>
619 13:59:21.922295 [ANA_INIT] PLL <<<<<<<<
620 13:59:21.924896 [ANA_INIT] MIDPI >>>>>>>>
621 13:59:21.924970 [ANA_INIT] MIDPI <<<<<<<<
622 13:59:21.928701 [ANA_INIT] DLL >>>>>>>>
623 13:59:21.932115 [ANA_INIT] flow end
624 13:59:21.934839 ============ LP4 DIFF to SE enter ============
625 13:59:21.938628 ============ LP4 DIFF to SE exit ============
626 13:59:21.942081 [ANA_INIT] <<<<<<<<<<<<<
627 13:59:21.944932 [Flow] Enable top DCM control >>>>>
628 13:59:21.948476 [Flow] Enable top DCM control <<<<<
629 13:59:21.951790 Enable DLL master slave shuffle
630 13:59:21.955270 ==============================================================
631 13:59:21.958321 Gating Mode config
632 13:59:21.962104 ==============================================================
633 13:59:21.965282 Config description:
634 13:59:21.975070 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 13:59:21.982121 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 13:59:21.985173 SELPH_MODE 0: By rank 1: By Phase
637 13:59:21.991733 ==============================================================
638 13:59:21.995024 GAT_TRACK_EN = 1
639 13:59:21.998278 RX_GATING_MODE = 2
640 13:59:22.002182 RX_GATING_TRACK_MODE = 2
641 13:59:22.005376 SELPH_MODE = 1
642 13:59:22.005449 PICG_EARLY_EN = 1
643 13:59:22.008646 VALID_LAT_VALUE = 1
644 13:59:22.015817 ==============================================================
645 13:59:22.019019 Enter into Gating configuration >>>>
646 13:59:22.021734 Exit from Gating configuration <<<<
647 13:59:22.025359 Enter into DVFS_PRE_config >>>>>
648 13:59:22.035521 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 13:59:22.038715 Exit from DVFS_PRE_config <<<<<
650 13:59:22.041891 Enter into PICG configuration >>>>
651 13:59:22.045446 Exit from PICG configuration <<<<
652 13:59:22.049168 [RX_INPUT] configuration >>>>>
653 13:59:22.052111 [RX_INPUT] configuration <<<<<
654 13:59:22.055748 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 13:59:22.062297 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 13:59:22.069536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 13:59:22.072532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 13:59:22.079075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 13:59:22.086050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 13:59:22.089302 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 13:59:22.092576 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 13:59:22.099069 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 13:59:22.102375 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 13:59:22.105617 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 13:59:22.112308 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 13:59:22.115438 ===================================
667 13:59:22.115515 LPDDR4 DRAM CONFIGURATION
668 13:59:22.119145 ===================================
669 13:59:22.122522 EX_ROW_EN[0] = 0x0
670 13:59:22.125736 EX_ROW_EN[1] = 0x0
671 13:59:22.125807 LP4Y_EN = 0x0
672 13:59:22.129027 WORK_FSP = 0x0
673 13:59:22.129096 WL = 0x2
674 13:59:22.132229 RL = 0x2
675 13:59:22.132342 BL = 0x2
676 13:59:22.136065 RPST = 0x0
677 13:59:22.136133 RD_PRE = 0x0
678 13:59:22.138955 WR_PRE = 0x1
679 13:59:22.139023 WR_PST = 0x0
680 13:59:22.142378 DBI_WR = 0x0
681 13:59:22.142454 DBI_RD = 0x0
682 13:59:22.145660 OTF = 0x1
683 13:59:22.148901 ===================================
684 13:59:22.152655 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 13:59:22.155900 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 13:59:22.159148 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 13:59:22.162488 ===================================
688 13:59:22.165695 LPDDR4 DRAM CONFIGURATION
689 13:59:22.169350 ===================================
690 13:59:22.172786 EX_ROW_EN[0] = 0x10
691 13:59:22.172859 EX_ROW_EN[1] = 0x0
692 13:59:22.175772 LP4Y_EN = 0x0
693 13:59:22.175846 WORK_FSP = 0x0
694 13:59:22.178969 WL = 0x2
695 13:59:22.179045 RL = 0x2
696 13:59:22.182251 BL = 0x2
697 13:59:22.182325 RPST = 0x0
698 13:59:22.186210 RD_PRE = 0x0
699 13:59:22.186280 WR_PRE = 0x1
700 13:59:22.189136 WR_PST = 0x0
701 13:59:22.192133 DBI_WR = 0x0
702 13:59:22.192203 DBI_RD = 0x0
703 13:59:22.195715 OTF = 0x1
704 13:59:22.199305 ===================================
705 13:59:22.202330 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 13:59:22.207660 nWR fixed to 40
707 13:59:22.211368 [ModeRegInit_LP4] CH0 RK0
708 13:59:22.211445 [ModeRegInit_LP4] CH0 RK1
709 13:59:22.214732 [ModeRegInit_LP4] CH1 RK0
710 13:59:22.217917 [ModeRegInit_LP4] CH1 RK1
711 13:59:22.217989 match AC timing 13
712 13:59:22.224394 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 13:59:22.227708 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 13:59:22.230989 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 13:59:22.238153 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 13:59:22.241564 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 13:59:22.241637 [EMI DOE] emi_dcm 0
718 13:59:22.247972 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 13:59:22.248055 ==
720 13:59:22.251564 Dram Type= 6, Freq= 0, CH_0, rank 0
721 13:59:22.254916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 13:59:22.254988 ==
723 13:59:22.261440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 13:59:22.264988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 13:59:22.274978 [CA 0] Center 36 (6~67) winsize 62
726 13:59:22.278563 [CA 1] Center 36 (6~67) winsize 62
727 13:59:22.281651 [CA 2] Center 34 (4~65) winsize 62
728 13:59:22.284694 [CA 3] Center 33 (3~64) winsize 62
729 13:59:22.288449 [CA 4] Center 33 (3~64) winsize 62
730 13:59:22.291727 [CA 5] Center 32 (3~62) winsize 60
731 13:59:22.291799
732 13:59:22.294870 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 13:59:22.294943
734 13:59:22.298084 [CATrainingPosCal] consider 1 rank data
735 13:59:22.301441 u2DelayCellTimex100 = 270/100 ps
736 13:59:22.305147 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 13:59:22.308241 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
738 13:59:22.315150 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 13:59:22.318459 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
740 13:59:22.321693 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
741 13:59:22.325274 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
742 13:59:22.325355
743 13:59:22.328410 CA PerBit enable=1, Macro0, CA PI delay=32
744 13:59:22.328491
745 13:59:22.331982 [CBTSetCACLKResult] CA Dly = 32
746 13:59:22.332111 CS Dly: 5 (0~36)
747 13:59:22.332177 ==
748 13:59:22.335288 Dram Type= 6, Freq= 0, CH_0, rank 1
749 13:59:22.341902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 13:59:22.341985 ==
751 13:59:22.345151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 13:59:22.351648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 13:59:22.361475 [CA 0] Center 36 (6~67) winsize 62
754 13:59:22.364815 [CA 1] Center 36 (6~67) winsize 62
755 13:59:22.367753 [CA 2] Center 34 (3~65) winsize 63
756 13:59:22.371290 [CA 3] Center 33 (3~64) winsize 62
757 13:59:22.374768 [CA 4] Center 33 (3~63) winsize 61
758 13:59:22.378223 [CA 5] Center 32 (2~63) winsize 62
759 13:59:22.378302
760 13:59:22.381195 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 13:59:22.381265
762 13:59:22.384812 [CATrainingPosCal] consider 2 rank data
763 13:59:22.387962 u2DelayCellTimex100 = 270/100 ps
764 13:59:22.391310 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 13:59:22.394431 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
766 13:59:22.401581 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 13:59:22.404966 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
768 13:59:22.408210 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
769 13:59:22.411395 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
770 13:59:22.411478
771 13:59:22.414587 CA PerBit enable=1, Macro0, CA PI delay=32
772 13:59:22.414670
773 13:59:22.417937 [CBTSetCACLKResult] CA Dly = 32
774 13:59:22.418020 CS Dly: 5 (0~37)
775 13:59:22.418105
776 13:59:22.421695 ----->DramcWriteLeveling(PI) begin...
777 13:59:22.421783 ==
778 13:59:22.425199 Dram Type= 6, Freq= 0, CH_0, rank 0
779 13:59:22.428692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 13:59:22.432862 ==
781 13:59:22.432945 Write leveling (Byte 0): 33 => 33
782 13:59:22.436182 Write leveling (Byte 1): 31 => 31
783 13:59:22.440211 DramcWriteLeveling(PI) end<-----
784 13:59:22.440300
785 13:59:22.440415 ==
786 13:59:22.443044 Dram Type= 6, Freq= 0, CH_0, rank 0
787 13:59:22.446690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 13:59:22.446774 ==
789 13:59:22.450126 [Gating] SW mode calibration
790 13:59:22.457447 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 13:59:22.463889 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 13:59:22.467225 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 13:59:22.470433 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 13:59:22.477439 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 13:59:22.480436 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:59:22.483901 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:59:22.490679 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:59:22.494180 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:59:22.496958 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:59:22.500873 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:59:22.507088 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:59:22.510400 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:59:22.513657 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:59:22.520917 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:59:22.524116 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:59:22.527458 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:59:22.533956 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:59:22.537227 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:59:22.540420 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:59:22.547482 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
811 13:59:22.550773 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
812 13:59:22.554089 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 13:59:22.560540 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 13:59:22.564153 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 13:59:22.567273 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:59:22.574063 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:59:22.577738 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:59:22.580927 0 9 8 | B1->B0 | 2323 2929 | 1 0 | (1 1) (0 0)
819 13:59:22.587472 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 13:59:22.590687 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 13:59:22.593853 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 13:59:22.597453 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 13:59:22.603916 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 13:59:22.607389 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 13:59:22.610860 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
826 13:59:22.617771 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (1 0) (0 0)
827 13:59:22.620809 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
828 13:59:22.624040 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 13:59:22.631221 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 13:59:22.634441 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 13:59:22.637585 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 13:59:22.644466 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 13:59:22.647560 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
834 13:59:22.650746 0 11 8 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (1 1)
835 13:59:22.657818 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
836 13:59:22.660994 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 13:59:22.664330 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 13:59:22.667577 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 13:59:22.674069 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 13:59:22.677553 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 13:59:22.680657 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
842 13:59:22.687384 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 13:59:22.690850 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:59:22.694475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:59:22.700737 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:59:22.704467 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:59:22.707985 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:59:22.714421 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:59:22.717765 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:59:22.720768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:59:22.727685 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:59:22.731170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 13:59:22.734196 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 13:59:22.741130 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 13:59:22.744344 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 13:59:22.747687 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 13:59:22.751546 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 13:59:22.757811 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 13:59:22.761317 Total UI for P1: 0, mck2ui 16
860 13:59:22.764472 best dqsien dly found for B0: ( 0, 14, 6)
861 13:59:22.767883 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 13:59:22.771103 Total UI for P1: 0, mck2ui 16
863 13:59:22.775021 best dqsien dly found for B1: ( 0, 14, 8)
864 13:59:22.778189 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
865 13:59:22.782066 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 13:59:22.782149
867 13:59:22.785036 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
868 13:59:22.788545 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 13:59:22.791613 [Gating] SW calibration Done
870 13:59:22.791696 ==
871 13:59:22.794914 Dram Type= 6, Freq= 0, CH_0, rank 0
872 13:59:22.798160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 13:59:22.798244 ==
874 13:59:22.802066 RX Vref Scan: 0
875 13:59:22.802149
876 13:59:22.802234 RX Vref 0 -> 0, step: 1
877 13:59:22.805425
878 13:59:22.805508 RX Delay -130 -> 252, step: 16
879 13:59:22.812016 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 13:59:22.815142 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 13:59:22.818722 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 13:59:22.822321 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 13:59:22.825372 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 13:59:22.828527 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 13:59:22.835386 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
886 13:59:22.838396 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 13:59:22.841827 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
888 13:59:22.845536 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
889 13:59:22.848502 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 13:59:22.855404 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 13:59:22.858688 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
892 13:59:22.861890 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 13:59:22.865327 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 13:59:22.871913 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 13:59:22.871995 ==
896 13:59:22.875761 Dram Type= 6, Freq= 0, CH_0, rank 0
897 13:59:22.879047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 13:59:22.879122 ==
899 13:59:22.879190 DQS Delay:
900 13:59:22.882316 DQS0 = 0, DQS1 = 0
901 13:59:22.882389 DQM Delay:
902 13:59:22.885545 DQM0 = 89, DQM1 = 81
903 13:59:22.885616 DQ Delay:
904 13:59:22.888795 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
905 13:59:22.891947 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
906 13:59:22.895512 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
907 13:59:22.899034 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
908 13:59:22.899111
909 13:59:22.899174
910 13:59:22.899232 ==
911 13:59:22.902440 Dram Type= 6, Freq= 0, CH_0, rank 0
912 13:59:22.905600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 13:59:22.905669 ==
914 13:59:22.905729
915 13:59:22.905786
916 13:59:22.908916 TX Vref Scan disable
917 13:59:22.912170 == TX Byte 0 ==
918 13:59:22.915480 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
919 13:59:22.918821 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
920 13:59:22.922199 == TX Byte 1 ==
921 13:59:22.925493 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
922 13:59:22.928762 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
923 13:59:22.928836 ==
924 13:59:22.932013 Dram Type= 6, Freq= 0, CH_0, rank 0
925 13:59:22.935188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 13:59:22.938448 ==
927 13:59:22.950283 TX Vref=22, minBit 3, minWin=27, winSum=446
928 13:59:22.953813 TX Vref=24, minBit 10, minWin=27, winSum=451
929 13:59:22.957194 TX Vref=26, minBit 0, minWin=28, winSum=455
930 13:59:22.960603 TX Vref=28, minBit 8, minWin=28, winSum=458
931 13:59:22.963899 TX Vref=30, minBit 0, minWin=28, winSum=457
932 13:59:22.967357 TX Vref=32, minBit 2, minWin=28, winSum=455
933 13:59:22.973671 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
934 13:59:22.973753
935 13:59:22.976846 Final TX Range 1 Vref 28
936 13:59:22.976918
937 13:59:22.977044 ==
938 13:59:22.980231 Dram Type= 6, Freq= 0, CH_0, rank 0
939 13:59:22.983333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 13:59:22.983414 ==
941 13:59:22.983480
942 13:59:22.986886
943 13:59:22.986980 TX Vref Scan disable
944 13:59:22.990224 == TX Byte 0 ==
945 13:59:22.993571 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
946 13:59:22.996732 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
947 13:59:23.000120 == TX Byte 1 ==
948 13:59:23.003554 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 13:59:23.006983 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 13:59:23.010255
951 13:59:23.010332 [DATLAT]
952 13:59:23.010394 Freq=800, CH0 RK0
953 13:59:23.010454
954 13:59:23.013524 DATLAT Default: 0xa
955 13:59:23.013593 0, 0xFFFF, sum = 0
956 13:59:23.016824 1, 0xFFFF, sum = 0
957 13:59:23.016907 2, 0xFFFF, sum = 0
958 13:59:23.020685 3, 0xFFFF, sum = 0
959 13:59:23.020766 4, 0xFFFF, sum = 0
960 13:59:23.023939 5, 0xFFFF, sum = 0
961 13:59:23.024020 6, 0xFFFF, sum = 0
962 13:59:23.027211 7, 0xFFFF, sum = 0
963 13:59:23.027292 8, 0xFFFF, sum = 0
964 13:59:23.030513 9, 0x0, sum = 1
965 13:59:23.030595 10, 0x0, sum = 2
966 13:59:23.033843 11, 0x0, sum = 3
967 13:59:23.033924 12, 0x0, sum = 4
968 13:59:23.037093 best_step = 10
969 13:59:23.037173
970 13:59:23.037237 ==
971 13:59:23.040473 Dram Type= 6, Freq= 0, CH_0, rank 0
972 13:59:23.043725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 13:59:23.043806 ==
974 13:59:23.047037 RX Vref Scan: 1
975 13:59:23.047117
976 13:59:23.047196 Set Vref Range= 32 -> 127
977 13:59:23.047269
978 13:59:23.050313 RX Vref 32 -> 127, step: 1
979 13:59:23.050393
980 13:59:23.054324 RX Delay -79 -> 252, step: 8
981 13:59:23.054404
982 13:59:23.057370 Set Vref, RX VrefLevel [Byte0]: 32
983 13:59:23.060630 [Byte1]: 32
984 13:59:23.060710
985 13:59:23.064033 Set Vref, RX VrefLevel [Byte0]: 33
986 13:59:23.066931 [Byte1]: 33
987 13:59:23.070685
988 13:59:23.070765 Set Vref, RX VrefLevel [Byte0]: 34
989 13:59:23.073561 [Byte1]: 34
990 13:59:23.078374
991 13:59:23.078490 Set Vref, RX VrefLevel [Byte0]: 35
992 13:59:23.081153 [Byte1]: 35
993 13:59:23.086105
994 13:59:23.086205 Set Vref, RX VrefLevel [Byte0]: 36
995 13:59:23.089448 [Byte1]: 36
996 13:59:23.093071
997 13:59:23.093179 Set Vref, RX VrefLevel [Byte0]: 37
998 13:59:23.096636 [Byte1]: 37
999 13:59:23.101102
1000 13:59:23.101208 Set Vref, RX VrefLevel [Byte0]: 38
1001 13:59:23.103895 [Byte1]: 38
1002 13:59:23.108717
1003 13:59:23.108797 Set Vref, RX VrefLevel [Byte0]: 39
1004 13:59:23.111699 [Byte1]: 39
1005 13:59:23.115910
1006 13:59:23.116008 Set Vref, RX VrefLevel [Byte0]: 40
1007 13:59:23.119560 [Byte1]: 40
1008 13:59:23.123456
1009 13:59:23.123539 Set Vref, RX VrefLevel [Byte0]: 41
1010 13:59:23.126636 [Byte1]: 41
1011 13:59:23.130920
1012 13:59:23.131001 Set Vref, RX VrefLevel [Byte0]: 42
1013 13:59:23.134300 [Byte1]: 42
1014 13:59:23.138329
1015 13:59:23.138406 Set Vref, RX VrefLevel [Byte0]: 43
1016 13:59:23.141565 [Byte1]: 43
1017 13:59:23.145581
1018 13:59:23.145652 Set Vref, RX VrefLevel [Byte0]: 44
1019 13:59:23.149520 [Byte1]: 44
1020 13:59:23.153456
1021 13:59:23.153531 Set Vref, RX VrefLevel [Byte0]: 45
1022 13:59:23.156706 [Byte1]: 45
1023 13:59:23.161373
1024 13:59:23.161442 Set Vref, RX VrefLevel [Byte0]: 46
1025 13:59:23.164465 [Byte1]: 46
1026 13:59:23.168403
1027 13:59:23.168473 Set Vref, RX VrefLevel [Byte0]: 47
1028 13:59:23.171716 [Byte1]: 47
1029 13:59:23.176206
1030 13:59:23.176276 Set Vref, RX VrefLevel [Byte0]: 48
1031 13:59:23.179353 [Byte1]: 48
1032 13:59:23.183680
1033 13:59:23.183749 Set Vref, RX VrefLevel [Byte0]: 49
1034 13:59:23.186741 [Byte1]: 49
1035 13:59:23.191368
1036 13:59:23.191436 Set Vref, RX VrefLevel [Byte0]: 50
1037 13:59:23.194793 [Byte1]: 50
1038 13:59:23.198581
1039 13:59:23.198655 Set Vref, RX VrefLevel [Byte0]: 51
1040 13:59:23.202313 [Byte1]: 51
1041 13:59:23.206214
1042 13:59:23.206282 Set Vref, RX VrefLevel [Byte0]: 52
1043 13:59:23.209334 [Byte1]: 52
1044 13:59:23.213675
1045 13:59:23.213746 Set Vref, RX VrefLevel [Byte0]: 53
1046 13:59:23.217203 [Byte1]: 53
1047 13:59:23.221528
1048 13:59:23.221600 Set Vref, RX VrefLevel [Byte0]: 54
1049 13:59:23.224908 [Byte1]: 54
1050 13:59:23.228729
1051 13:59:23.228801 Set Vref, RX VrefLevel [Byte0]: 55
1052 13:59:23.232613 [Byte1]: 55
1053 13:59:23.236739
1054 13:59:23.236807 Set Vref, RX VrefLevel [Byte0]: 56
1055 13:59:23.239676 [Byte1]: 56
1056 13:59:23.243861
1057 13:59:23.247363 Set Vref, RX VrefLevel [Byte0]: 57
1058 13:59:23.247435 [Byte1]: 57
1059 13:59:23.251653
1060 13:59:23.251727 Set Vref, RX VrefLevel [Byte0]: 58
1061 13:59:23.254805 [Byte1]: 58
1062 13:59:23.259453
1063 13:59:23.259535 Set Vref, RX VrefLevel [Byte0]: 59
1064 13:59:23.262384 [Byte1]: 59
1065 13:59:23.266861
1066 13:59:23.266933 Set Vref, RX VrefLevel [Byte0]: 60
1067 13:59:23.269994 [Byte1]: 60
1068 13:59:23.274018
1069 13:59:23.274093 Set Vref, RX VrefLevel [Byte0]: 61
1070 13:59:23.277364 [Byte1]: 61
1071 13:59:23.281769
1072 13:59:23.281840 Set Vref, RX VrefLevel [Byte0]: 62
1073 13:59:23.284841 [Byte1]: 62
1074 13:59:23.289443
1075 13:59:23.289520 Set Vref, RX VrefLevel [Byte0]: 63
1076 13:59:23.292716 [Byte1]: 63
1077 13:59:23.297176
1078 13:59:23.297271 Set Vref, RX VrefLevel [Byte0]: 64
1079 13:59:23.300137 [Byte1]: 64
1080 13:59:23.304295
1081 13:59:23.304368 Set Vref, RX VrefLevel [Byte0]: 65
1082 13:59:23.307825 [Byte1]: 65
1083 13:59:23.311842
1084 13:59:23.311922 Set Vref, RX VrefLevel [Byte0]: 66
1085 13:59:23.315396 [Byte1]: 66
1086 13:59:23.319920
1087 13:59:23.320000 Set Vref, RX VrefLevel [Byte0]: 67
1088 13:59:23.322886 [Byte1]: 67
1089 13:59:23.327269
1090 13:59:23.327351 Set Vref, RX VrefLevel [Byte0]: 68
1091 13:59:23.330574 [Byte1]: 68
1092 13:59:23.334376
1093 13:59:23.334446 Set Vref, RX VrefLevel [Byte0]: 69
1094 13:59:23.337793 [Byte1]: 69
1095 13:59:23.342341
1096 13:59:23.342412 Set Vref, RX VrefLevel [Byte0]: 70
1097 13:59:23.345423 [Byte1]: 70
1098 13:59:23.350017
1099 13:59:23.350084 Set Vref, RX VrefLevel [Byte0]: 71
1100 13:59:23.353271 [Byte1]: 71
1101 13:59:23.357154
1102 13:59:23.357230 Set Vref, RX VrefLevel [Byte0]: 72
1103 13:59:23.360700 [Byte1]: 72
1104 13:59:23.364755
1105 13:59:23.364824 Set Vref, RX VrefLevel [Byte0]: 73
1106 13:59:23.368174 [Byte1]: 73
1107 13:59:23.372400
1108 13:59:23.372472 Set Vref, RX VrefLevel [Byte0]: 74
1109 13:59:23.375416 [Byte1]: 74
1110 13:59:23.379748
1111 13:59:23.379820 Set Vref, RX VrefLevel [Byte0]: 75
1112 13:59:23.383084 [Byte1]: 75
1113 13:59:23.387295
1114 13:59:23.387376 Set Vref, RX VrefLevel [Byte0]: 76
1115 13:59:23.390634 [Byte1]: 76
1116 13:59:23.395173
1117 13:59:23.395247 Set Vref, RX VrefLevel [Byte0]: 77
1118 13:59:23.398489 [Byte1]: 77
1119 13:59:23.402479
1120 13:59:23.402552 Final RX Vref Byte 0 = 59 to rank0
1121 13:59:23.405826 Final RX Vref Byte 1 = 61 to rank0
1122 13:59:23.409599 Final RX Vref Byte 0 = 59 to rank1
1123 13:59:23.412784 Final RX Vref Byte 1 = 61 to rank1==
1124 13:59:23.415804 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 13:59:23.422450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 13:59:23.422528 ==
1127 13:59:23.422589 DQS Delay:
1128 13:59:23.422647 DQS0 = 0, DQS1 = 0
1129 13:59:23.425917 DQM Delay:
1130 13:59:23.425991 DQM0 = 92, DQM1 = 85
1131 13:59:23.429296 DQ Delay:
1132 13:59:23.432485 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1133 13:59:23.435784 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 13:59:23.435856 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1135 13:59:23.442613 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1136 13:59:23.442694
1137 13:59:23.442763
1138 13:59:23.448979 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1139 13:59:23.452830 CH0 RK0: MR19=606, MR18=4C43
1140 13:59:23.459340 CH0_RK0: MR19=0x606, MR18=0x4C43, DQSOSC=390, MR23=63, INC=97, DEC=64
1141 13:59:23.459424
1142 13:59:23.462579 ----->DramcWriteLeveling(PI) begin...
1143 13:59:23.462649 ==
1144 13:59:23.465740 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 13:59:23.469457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 13:59:23.469527 ==
1147 13:59:23.472580 Write leveling (Byte 0): 32 => 32
1148 13:59:23.475731 Write leveling (Byte 1): 29 => 29
1149 13:59:23.479015 DramcWriteLeveling(PI) end<-----
1150 13:59:23.479084
1151 13:59:23.479143 ==
1152 13:59:23.482362 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 13:59:23.486079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 13:59:23.486154 ==
1155 13:59:23.489178 [Gating] SW mode calibration
1156 13:59:23.496128 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 13:59:23.540348 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 13:59:23.540619 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 13:59:23.540690 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1160 13:59:23.540763 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1161 13:59:23.540828 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1162 13:59:23.540899 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:59:23.541143 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:59:23.541205 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:59:23.541449 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:59:23.541577 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:59:23.584173 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:59:23.584441 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:59:23.584512 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:59:23.584573 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:59:23.584635 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:59:23.584703 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:59:23.584947 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:59:23.585009 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:59:23.585248 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:59:23.585308 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1177 13:59:23.613137 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:59:23.613405 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:59:23.613520 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:59:23.613635 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:59:23.613698 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:59:23.613767 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:59:23.617346 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:59:23.620121 0 9 8 | B1->B0 | 2d2d 2727 | 1 1 | (1 1) (0 0)
1185 13:59:23.623428 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 13:59:23.630831 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 13:59:23.633690 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 13:59:23.637332 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 13:59:23.643580 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 13:59:23.647250 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 13:59:23.650649 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1192 13:59:23.657337 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1193 13:59:23.660255 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:59:23.663866 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:59:23.667375 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:59:23.674931 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 13:59:23.679357 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 13:59:23.682608 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 13:59:23.686007 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 13:59:23.689417 0 11 8 | B1->B0 | 3b3b 4343 | 1 0 | (0 0) (0 0)
1201 13:59:23.696731 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 13:59:23.700561 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 13:59:23.703773 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 13:59:23.707007 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 13:59:23.713492 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 13:59:23.716724 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 13:59:23.720734 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 13:59:23.726950 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 13:59:23.730214 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:59:23.734111 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:59:23.740530 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:59:23.743479 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:59:23.746896 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:59:23.753901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:59:23.757310 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:59:23.760493 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:59:23.763911 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 13:59:23.770570 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 13:59:23.773770 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 13:59:23.776831 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 13:59:23.784168 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 13:59:23.786894 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 13:59:23.790546 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 13:59:23.797307 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 13:59:23.800654 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 13:59:23.803917 Total UI for P1: 0, mck2ui 16
1227 13:59:23.807192 best dqsien dly found for B0: ( 0, 14, 8)
1228 13:59:23.810451 Total UI for P1: 0, mck2ui 16
1229 13:59:23.813761 best dqsien dly found for B1: ( 0, 14, 8)
1230 13:59:23.817643 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 13:59:23.820757 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 13:59:23.820827
1233 13:59:23.824086 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 13:59:23.827284 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 13:59:23.830398 [Gating] SW calibration Done
1236 13:59:23.830467 ==
1237 13:59:23.833642 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 13:59:23.837498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 13:59:23.837567 ==
1240 13:59:23.840943 RX Vref Scan: 0
1241 13:59:23.841011
1242 13:59:23.844239 RX Vref 0 -> 0, step: 1
1243 13:59:23.844336
1244 13:59:23.844397 RX Delay -130 -> 252, step: 16
1245 13:59:23.850762 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1246 13:59:23.854176 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1247 13:59:23.857417 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1248 13:59:23.860474 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1249 13:59:23.863865 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1250 13:59:23.870635 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1251 13:59:23.873690 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1252 13:59:23.876807 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1253 13:59:23.880148 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1254 13:59:23.883426 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1255 13:59:23.890212 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1256 13:59:23.893899 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1257 13:59:23.897140 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1258 13:59:23.900127 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1259 13:59:23.906761 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1260 13:59:23.910470 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1261 13:59:23.910541 ==
1262 13:59:23.913276 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 13:59:23.917151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 13:59:23.917226 ==
1265 13:59:23.917294 DQS Delay:
1266 13:59:23.920494 DQS0 = 0, DQS1 = 0
1267 13:59:23.920567 DQM Delay:
1268 13:59:23.923436 DQM0 = 91, DQM1 = 82
1269 13:59:23.923504 DQ Delay:
1270 13:59:23.927198 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1271 13:59:23.930495 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1272 13:59:23.933613 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1273 13:59:23.936794 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =77
1274 13:59:23.936872
1275 13:59:23.936934
1276 13:59:23.936992 ==
1277 13:59:23.940168 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 13:59:23.943472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 13:59:23.947306 ==
1280 13:59:23.947382
1281 13:59:23.947444
1282 13:59:23.947502 TX Vref Scan disable
1283 13:59:23.950522 == TX Byte 0 ==
1284 13:59:23.953895 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1285 13:59:23.957185 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1286 13:59:23.960514 == TX Byte 1 ==
1287 13:59:23.963594 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1288 13:59:23.967513 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1289 13:59:23.967581 ==
1290 13:59:23.970508 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 13:59:23.977008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 13:59:23.977086 ==
1293 13:59:23.989744 TX Vref=22, minBit 10, minWin=27, winSum=448
1294 13:59:23.992606 TX Vref=24, minBit 12, minWin=27, winSum=451
1295 13:59:23.996121 TX Vref=26, minBit 1, minWin=28, winSum=456
1296 13:59:23.999526 TX Vref=28, minBit 11, minWin=28, winSum=462
1297 13:59:24.002709 TX Vref=30, minBit 2, minWin=28, winSum=454
1298 13:59:24.009685 TX Vref=32, minBit 3, minWin=28, winSum=458
1299 13:59:24.012688 [TxChooseVref] Worse bit 11, Min win 28, Win sum 462, Final Vref 28
1300 13:59:24.012757
1301 13:59:24.016016 Final TX Range 1 Vref 28
1302 13:59:24.016091
1303 13:59:24.016150 ==
1304 13:59:24.019351 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 13:59:24.022858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 13:59:24.022962 ==
1307 13:59:24.026220
1308 13:59:24.026331
1309 13:59:24.026396 TX Vref Scan disable
1310 13:59:24.029522 == TX Byte 0 ==
1311 13:59:24.032942 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1312 13:59:24.036253 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1313 13:59:24.039810 == TX Byte 1 ==
1314 13:59:24.043370 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1315 13:59:24.046551 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1316 13:59:24.049770
1317 13:59:24.049840 [DATLAT]
1318 13:59:24.049923 Freq=800, CH0 RK1
1319 13:59:24.049983
1320 13:59:24.053019 DATLAT Default: 0xa
1321 13:59:24.053094 0, 0xFFFF, sum = 0
1322 13:59:24.056321 1, 0xFFFF, sum = 0
1323 13:59:24.056409 2, 0xFFFF, sum = 0
1324 13:59:24.060184 3, 0xFFFF, sum = 0
1325 13:59:24.060259 4, 0xFFFF, sum = 0
1326 13:59:24.063492 5, 0xFFFF, sum = 0
1327 13:59:24.063563 6, 0xFFFF, sum = 0
1328 13:59:24.066753 7, 0xFFFF, sum = 0
1329 13:59:24.066821 8, 0xFFFF, sum = 0
1330 13:59:24.070015 9, 0x0, sum = 1
1331 13:59:24.070086 10, 0x0, sum = 2
1332 13:59:24.073170 11, 0x0, sum = 3
1333 13:59:24.073241 12, 0x0, sum = 4
1334 13:59:24.077013 best_step = 10
1335 13:59:24.077125
1336 13:59:24.077210 ==
1337 13:59:24.080214 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 13:59:24.083434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 13:59:24.083503 ==
1340 13:59:24.086655 RX Vref Scan: 0
1341 13:59:24.086722
1342 13:59:24.086783 RX Vref 0 -> 0, step: 1
1343 13:59:24.086859
1344 13:59:24.089892 RX Delay -79 -> 252, step: 8
1345 13:59:24.096394 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1346 13:59:24.099654 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1347 13:59:24.103650 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 13:59:24.106758 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1349 13:59:24.109968 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1350 13:59:24.116502 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1351 13:59:24.119923 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1352 13:59:24.123200 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 13:59:24.126896 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1354 13:59:24.130075 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1355 13:59:24.136935 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 13:59:24.140007 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 13:59:24.143738 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1358 13:59:24.146600 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1359 13:59:24.149987 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 13:59:24.156698 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1361 13:59:24.156773 ==
1362 13:59:24.160411 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 13:59:24.163454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 13:59:24.163527 ==
1365 13:59:24.163588 DQS Delay:
1366 13:59:24.166460 DQS0 = 0, DQS1 = 0
1367 13:59:24.166530 DQM Delay:
1368 13:59:24.170068 DQM0 = 92, DQM1 = 83
1369 13:59:24.170138 DQ Delay:
1370 13:59:24.173312 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1371 13:59:24.176449 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1372 13:59:24.180176 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1373 13:59:24.183580 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1374 13:59:24.183652
1375 13:59:24.183715
1376 13:59:24.190148 [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1377 13:59:24.193368 CH0 RK1: MR19=606, MR18=4415
1378 13:59:24.200594 CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64
1379 13:59:24.203894 [RxdqsGatingPostProcess] freq 800
1380 13:59:24.210401 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 13:59:24.210477 Pre-setting of DQS Precalculation
1382 13:59:24.216869 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 13:59:24.216944 ==
1384 13:59:24.220184 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 13:59:24.223442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 13:59:24.223514 ==
1387 13:59:24.230380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 13:59:24.236688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 13:59:24.244824 [CA 0] Center 36 (6~67) winsize 62
1390 13:59:24.248152 [CA 1] Center 36 (6~67) winsize 62
1391 13:59:24.251580 [CA 2] Center 35 (5~65) winsize 61
1392 13:59:24.254821 [CA 3] Center 34 (4~65) winsize 62
1393 13:59:24.258570 [CA 4] Center 34 (4~65) winsize 62
1394 13:59:24.261747 [CA 5] Center 34 (4~65) winsize 62
1395 13:59:24.261820
1396 13:59:24.264861 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1397 13:59:24.264937
1398 13:59:24.268094 [CATrainingPosCal] consider 1 rank data
1399 13:59:24.271704 u2DelayCellTimex100 = 270/100 ps
1400 13:59:24.274743 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 13:59:24.278327 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 13:59:24.284936 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1403 13:59:24.288250 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 13:59:24.291565 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 13:59:24.294842 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1406 13:59:24.294915
1407 13:59:24.298224 CA PerBit enable=1, Macro0, CA PI delay=34
1408 13:59:24.298300
1409 13:59:24.301436 [CBTSetCACLKResult] CA Dly = 34
1410 13:59:24.301528 CS Dly: 6 (0~37)
1411 13:59:24.301593 ==
1412 13:59:24.304769 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 13:59:24.312058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 13:59:24.312140 ==
1415 13:59:24.315068 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 13:59:24.321686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 13:59:24.331507 [CA 0] Center 36 (6~67) winsize 62
1418 13:59:24.334831 [CA 1] Center 37 (6~68) winsize 63
1419 13:59:24.338498 [CA 2] Center 35 (5~66) winsize 62
1420 13:59:24.342281 [CA 3] Center 34 (4~65) winsize 62
1421 13:59:24.346175 [CA 4] Center 34 (4~65) winsize 62
1422 13:59:24.349977 [CA 5] Center 34 (4~65) winsize 62
1423 13:59:24.350050
1424 13:59:24.354453 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1425 13:59:24.354531
1426 13:59:24.354595 [CATrainingPosCal] consider 2 rank data
1427 13:59:24.357428 u2DelayCellTimex100 = 270/100 ps
1428 13:59:24.361591 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 13:59:24.365423 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 13:59:24.368745 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1431 13:59:24.372093 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 13:59:24.375262 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 13:59:24.378621 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 13:59:24.382441
1435 13:59:24.385666 CA PerBit enable=1, Macro0, CA PI delay=34
1436 13:59:24.385737
1437 13:59:24.388736 [CBTSetCACLKResult] CA Dly = 34
1438 13:59:24.388807 CS Dly: 7 (0~39)
1439 13:59:24.388867
1440 13:59:24.392361 ----->DramcWriteLeveling(PI) begin...
1441 13:59:24.392456 ==
1442 13:59:24.395586 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 13:59:24.398707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 13:59:24.398781 ==
1445 13:59:24.401998 Write leveling (Byte 0): 28 => 28
1446 13:59:24.405619 Write leveling (Byte 1): 24 => 24
1447 13:59:24.408924 DramcWriteLeveling(PI) end<-----
1448 13:59:24.408995
1449 13:59:24.409055 ==
1450 13:59:24.412210 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 13:59:24.419263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 13:59:24.419340 ==
1453 13:59:24.419416 [Gating] SW mode calibration
1454 13:59:24.428970 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 13:59:24.432170 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 13:59:24.435348 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1457 13:59:24.441963 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:59:24.445656 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:59:24.448898 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:59:24.455843 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:59:24.459006 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:59:24.462109 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:59:24.469117 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:59:24.472174 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:59:24.475686 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:59:24.482166 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:59:24.485694 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:59:24.488878 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:59:24.492598 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:59:24.498552 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:59:24.501931 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:59:24.505276 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1473 13:59:24.512546 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1474 13:59:24.515765 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:59:24.518944 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:59:24.525319 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:59:24.528943 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:59:24.532090 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:59:24.538784 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:59:24.542220 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:59:24.545467 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
1482 13:59:24.552527 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1483 13:59:24.555605 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 13:59:24.558890 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 13:59:24.565613 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 13:59:24.568887 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 13:59:24.572756 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 13:59:24.575970 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 13:59:24.582438 0 10 4 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (1 0)
1490 13:59:24.585620 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1491 13:59:24.588834 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:59:24.595535 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:59:24.599114 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:59:24.602101 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 13:59:24.608870 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 13:59:24.612363 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 13:59:24.615649 0 11 4 | B1->B0 | 3030 3636 | 0 0 | (0 0) (0 0)
1498 13:59:24.622445 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1499 13:59:24.625834 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 13:59:24.629002 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 13:59:24.635398 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 13:59:24.639089 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 13:59:24.642585 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 13:59:24.648877 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 13:59:24.652555 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:59:24.655751 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:59:24.662116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:59:24.665967 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:59:24.669123 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:59:24.675568 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:59:24.678901 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:59:24.682224 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:59:24.685489 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:59:24.692624 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:59:24.695717 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 13:59:24.699119 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 13:59:24.705728 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 13:59:24.709056 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 13:59:24.712130 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 13:59:24.719145 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1521 13:59:24.722462 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1522 13:59:24.725633 Total UI for P1: 0, mck2ui 16
1523 13:59:24.729183 best dqsien dly found for B1: ( 0, 14, 0)
1524 13:59:24.732460 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 13:59:24.735646 Total UI for P1: 0, mck2ui 16
1526 13:59:24.739388 best dqsien dly found for B0: ( 0, 14, 4)
1527 13:59:24.742519 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1528 13:59:24.745737 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1529 13:59:24.745818
1530 13:59:24.749550 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1531 13:59:24.755842 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1532 13:59:24.755923 [Gating] SW calibration Done
1533 13:59:24.755987 ==
1534 13:59:24.759030 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 13:59:24.766077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 13:59:24.766162 ==
1537 13:59:24.766226 RX Vref Scan: 0
1538 13:59:24.766285
1539 13:59:24.769429 RX Vref 0 -> 0, step: 1
1540 13:59:24.769510
1541 13:59:24.772604 RX Delay -130 -> 252, step: 16
1542 13:59:24.775827 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1543 13:59:24.779264 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1544 13:59:24.782268 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1545 13:59:24.789606 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1546 13:59:24.792591 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1547 13:59:24.795818 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1548 13:59:24.799044 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1549 13:59:24.802367 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1550 13:59:24.806162 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1551 13:59:24.812407 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1552 13:59:24.816209 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1553 13:59:24.819205 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1554 13:59:24.822392 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1555 13:59:24.828986 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1556 13:59:24.832942 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1557 13:59:24.836162 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1558 13:59:24.836243 ==
1559 13:59:24.839368 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 13:59:24.842974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 13:59:24.843056 ==
1562 13:59:24.845820 DQS Delay:
1563 13:59:24.845901 DQS0 = 0, DQS1 = 0
1564 13:59:24.849048 DQM Delay:
1565 13:59:24.849129 DQM0 = 95, DQM1 = 91
1566 13:59:24.849192 DQ Delay:
1567 13:59:24.852483 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1568 13:59:24.855598 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1569 13:59:24.858995 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1570 13:59:24.862717 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1571 13:59:24.862798
1572 13:59:24.862861
1573 13:59:24.865941 ==
1574 13:59:24.866021 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 13:59:24.872410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 13:59:24.872491 ==
1577 13:59:24.872555
1578 13:59:24.872613
1579 13:59:24.875690 TX Vref Scan disable
1580 13:59:24.875770 == TX Byte 0 ==
1581 13:59:24.879401 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1582 13:59:24.885727 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1583 13:59:24.885813 == TX Byte 1 ==
1584 13:59:24.889361 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1585 13:59:24.895926 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1586 13:59:24.895997 ==
1587 13:59:24.899166 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 13:59:24.902381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 13:59:24.902453 ==
1590 13:59:24.916572 TX Vref=22, minBit 3, minWin=26, winSum=437
1591 13:59:24.920386 TX Vref=24, minBit 3, minWin=26, winSum=442
1592 13:59:24.923639 TX Vref=26, minBit 0, minWin=27, winSum=446
1593 13:59:24.926850 TX Vref=28, minBit 2, minWin=27, winSum=450
1594 13:59:24.930104 TX Vref=30, minBit 0, minWin=27, winSum=452
1595 13:59:24.933390 TX Vref=32, minBit 0, minWin=27, winSum=451
1596 13:59:24.939900 [TxChooseVref] Worse bit 0, Min win 27, Win sum 452, Final Vref 30
1597 13:59:24.939977
1598 13:59:24.943880 Final TX Range 1 Vref 30
1599 13:59:24.943966
1600 13:59:24.944062 ==
1601 13:59:24.947167 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 13:59:24.950517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 13:59:24.950588 ==
1604 13:59:24.950654
1605 13:59:24.950711
1606 13:59:24.953686 TX Vref Scan disable
1607 13:59:24.956680 == TX Byte 0 ==
1608 13:59:24.960258 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1609 13:59:24.963806 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1610 13:59:24.967097 == TX Byte 1 ==
1611 13:59:24.970030 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1612 13:59:24.973513 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1613 13:59:24.973596
1614 13:59:24.976911 [DATLAT]
1615 13:59:24.976989 Freq=800, CH1 RK0
1616 13:59:24.977049
1617 13:59:24.980091 DATLAT Default: 0xa
1618 13:59:24.980165 0, 0xFFFF, sum = 0
1619 13:59:24.983926 1, 0xFFFF, sum = 0
1620 13:59:24.983998 2, 0xFFFF, sum = 0
1621 13:59:24.986923 3, 0xFFFF, sum = 0
1622 13:59:24.986997 4, 0xFFFF, sum = 0
1623 13:59:24.990149 5, 0xFFFF, sum = 0
1624 13:59:24.990233 6, 0xFFFF, sum = 0
1625 13:59:24.993466 7, 0xFFFF, sum = 0
1626 13:59:24.993544 8, 0xFFFF, sum = 0
1627 13:59:24.996713 9, 0x0, sum = 1
1628 13:59:24.996783 10, 0x0, sum = 2
1629 13:59:25.000041 11, 0x0, sum = 3
1630 13:59:25.000111 12, 0x0, sum = 4
1631 13:59:25.003794 best_step = 10
1632 13:59:25.003868
1633 13:59:25.003927 ==
1634 13:59:25.006880 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 13:59:25.010104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 13:59:25.010174 ==
1637 13:59:25.010234 RX Vref Scan: 1
1638 13:59:25.010299
1639 13:59:25.013819 Set Vref Range= 32 -> 127
1640 13:59:25.013889
1641 13:59:25.016771 RX Vref 32 -> 127, step: 1
1642 13:59:25.016841
1643 13:59:25.020495 RX Delay -63 -> 252, step: 8
1644 13:59:25.020566
1645 13:59:25.023558 Set Vref, RX VrefLevel [Byte0]: 32
1646 13:59:25.027103 [Byte1]: 32
1647 13:59:25.027172
1648 13:59:25.030203 Set Vref, RX VrefLevel [Byte0]: 33
1649 13:59:25.033365 [Byte1]: 33
1650 13:59:25.033446
1651 13:59:25.037178 Set Vref, RX VrefLevel [Byte0]: 34
1652 13:59:25.040481 [Byte1]: 34
1653 13:59:25.043690
1654 13:59:25.043770 Set Vref, RX VrefLevel [Byte0]: 35
1655 13:59:25.047019 [Byte1]: 35
1656 13:59:25.051665
1657 13:59:25.051746 Set Vref, RX VrefLevel [Byte0]: 36
1658 13:59:25.054881 [Byte1]: 36
1659 13:59:25.058850
1660 13:59:25.058930 Set Vref, RX VrefLevel [Byte0]: 37
1661 13:59:25.062019 [Byte1]: 37
1662 13:59:25.066610
1663 13:59:25.066690 Set Vref, RX VrefLevel [Byte0]: 38
1664 13:59:25.069826 [Byte1]: 38
1665 13:59:25.073492
1666 13:59:25.073572 Set Vref, RX VrefLevel [Byte0]: 39
1667 13:59:25.077025 [Byte1]: 39
1668 13:59:25.081636
1669 13:59:25.081716 Set Vref, RX VrefLevel [Byte0]: 40
1670 13:59:25.084670 [Byte1]: 40
1671 13:59:25.088564
1672 13:59:25.088645 Set Vref, RX VrefLevel [Byte0]: 41
1673 13:59:25.092123 [Byte1]: 41
1674 13:59:25.096661
1675 13:59:25.096742 Set Vref, RX VrefLevel [Byte0]: 42
1676 13:59:25.099884 [Byte1]: 42
1677 13:59:25.103832
1678 13:59:25.103912 Set Vref, RX VrefLevel [Byte0]: 43
1679 13:59:25.107049 [Byte1]: 43
1680 13:59:25.111407
1681 13:59:25.111518 Set Vref, RX VrefLevel [Byte0]: 44
1682 13:59:25.114551 [Byte1]: 44
1683 13:59:25.118539
1684 13:59:25.118619 Set Vref, RX VrefLevel [Byte0]: 45
1685 13:59:25.121802 [Byte1]: 45
1686 13:59:25.126227
1687 13:59:25.126308 Set Vref, RX VrefLevel [Byte0]: 46
1688 13:59:25.129578 [Byte1]: 46
1689 13:59:25.133894
1690 13:59:25.133993 Set Vref, RX VrefLevel [Byte0]: 47
1691 13:59:25.137100 [Byte1]: 47
1692 13:59:25.141408
1693 13:59:25.141503 Set Vref, RX VrefLevel [Byte0]: 48
1694 13:59:25.144579 [Byte1]: 48
1695 13:59:25.149188
1696 13:59:25.149268 Set Vref, RX VrefLevel [Byte0]: 49
1697 13:59:25.152146 [Byte1]: 49
1698 13:59:25.156162
1699 13:59:25.156243 Set Vref, RX VrefLevel [Byte0]: 50
1700 13:59:25.159444 [Byte1]: 50
1701 13:59:25.163414
1702 13:59:25.163509 Set Vref, RX VrefLevel [Byte0]: 51
1703 13:59:25.167418 [Byte1]: 51
1704 13:59:25.171298
1705 13:59:25.171378 Set Vref, RX VrefLevel [Byte0]: 52
1706 13:59:25.174638 [Byte1]: 52
1707 13:59:25.178519
1708 13:59:25.178600 Set Vref, RX VrefLevel [Byte0]: 53
1709 13:59:25.182396 [Byte1]: 53
1710 13:59:25.186536
1711 13:59:25.186610 Set Vref, RX VrefLevel [Byte0]: 54
1712 13:59:25.189544 [Byte1]: 54
1713 13:59:25.193671
1714 13:59:25.193747 Set Vref, RX VrefLevel [Byte0]: 55
1715 13:59:25.197142 [Byte1]: 55
1716 13:59:25.201705
1717 13:59:25.201778 Set Vref, RX VrefLevel [Byte0]: 56
1718 13:59:25.204471 [Byte1]: 56
1719 13:59:25.208384
1720 13:59:25.208461 Set Vref, RX VrefLevel [Byte0]: 57
1721 13:59:25.212183 [Byte1]: 57
1722 13:59:25.216035
1723 13:59:25.216111 Set Vref, RX VrefLevel [Byte0]: 58
1724 13:59:25.219464 [Byte1]: 58
1725 13:59:25.223924
1726 13:59:25.224001 Set Vref, RX VrefLevel [Byte0]: 59
1727 13:59:25.227217 [Byte1]: 59
1728 13:59:25.230856
1729 13:59:25.230931 Set Vref, RX VrefLevel [Byte0]: 60
1730 13:59:25.234772 [Byte1]: 60
1731 13:59:25.238690
1732 13:59:25.238760 Set Vref, RX VrefLevel [Byte0]: 61
1733 13:59:25.241876 [Byte1]: 61
1734 13:59:25.246344
1735 13:59:25.246417 Set Vref, RX VrefLevel [Byte0]: 62
1736 13:59:25.249647 [Byte1]: 62
1737 13:59:25.253461
1738 13:59:25.253530 Set Vref, RX VrefLevel [Byte0]: 63
1739 13:59:25.257338 [Byte1]: 63
1740 13:59:25.261367
1741 13:59:25.261443 Set Vref, RX VrefLevel [Byte0]: 64
1742 13:59:25.264509 [Byte1]: 64
1743 13:59:25.268776
1744 13:59:25.268846 Set Vref, RX VrefLevel [Byte0]: 65
1745 13:59:25.272086 [Byte1]: 65
1746 13:59:25.275946
1747 13:59:25.276017 Set Vref, RX VrefLevel [Byte0]: 66
1748 13:59:25.279468 [Byte1]: 66
1749 13:59:25.283629
1750 13:59:25.283709 Set Vref, RX VrefLevel [Byte0]: 67
1751 13:59:25.286922 [Byte1]: 67
1752 13:59:25.290816
1753 13:59:25.290896 Set Vref, RX VrefLevel [Byte0]: 68
1754 13:59:25.294611 [Byte1]: 68
1755 13:59:25.298453
1756 13:59:25.298533 Set Vref, RX VrefLevel [Byte0]: 69
1757 13:59:25.302072 [Byte1]: 69
1758 13:59:25.306291
1759 13:59:25.306372 Set Vref, RX VrefLevel [Byte0]: 70
1760 13:59:25.309095 [Byte1]: 70
1761 13:59:25.313351
1762 13:59:25.313431 Set Vref, RX VrefLevel [Byte0]: 71
1763 13:59:25.317210 [Byte1]: 71
1764 13:59:25.321052
1765 13:59:25.321133 Set Vref, RX VrefLevel [Byte0]: 72
1766 13:59:25.324055 [Byte1]: 72
1767 13:59:25.328708
1768 13:59:25.328788 Set Vref, RX VrefLevel [Byte0]: 73
1769 13:59:25.331965 [Byte1]: 73
1770 13:59:25.336421
1771 13:59:25.336500 Final RX Vref Byte 0 = 58 to rank0
1772 13:59:25.339661 Final RX Vref Byte 1 = 55 to rank0
1773 13:59:25.342973 Final RX Vref Byte 0 = 58 to rank1
1774 13:59:25.346196 Final RX Vref Byte 1 = 55 to rank1==
1775 13:59:25.349252 Dram Type= 6, Freq= 0, CH_1, rank 0
1776 13:59:25.353113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1777 13:59:25.356316 ==
1778 13:59:25.356392 DQS Delay:
1779 13:59:25.356454 DQS0 = 0, DQS1 = 0
1780 13:59:25.359636 DQM Delay:
1781 13:59:25.359712 DQM0 = 95, DQM1 = 90
1782 13:59:25.362915 DQ Delay:
1783 13:59:25.362984 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1784 13:59:25.366649 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1785 13:59:25.369590 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1786 13:59:25.372808 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1787 13:59:25.376088
1788 13:59:25.376166
1789 13:59:25.383252 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1790 13:59:25.386169 CH1 RK0: MR19=606, MR18=2E4A
1791 13:59:25.392887 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1792 13:59:25.392961
1793 13:59:25.396176 ----->DramcWriteLeveling(PI) begin...
1794 13:59:25.396279 ==
1795 13:59:25.399760 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 13:59:25.402993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 13:59:25.403071 ==
1798 13:59:25.406576 Write leveling (Byte 0): 27 => 27
1799 13:59:25.409880 Write leveling (Byte 1): 30 => 30
1800 13:59:25.412804 DramcWriteLeveling(PI) end<-----
1801 13:59:25.412880
1802 13:59:25.412943 ==
1803 13:59:25.416547 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 13:59:25.419496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 13:59:25.419573 ==
1806 13:59:25.422973 [Gating] SW mode calibration
1807 13:59:25.430018 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1808 13:59:25.436247 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1809 13:59:25.440024 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1810 13:59:25.442779 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1811 13:59:25.449891 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:59:25.453009 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:59:25.456192 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:59:25.462773 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:59:25.466190 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:59:25.469469 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:59:25.476424 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:59:25.479380 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:59:25.483233 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:59:25.486640 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:59:25.493073 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:59:25.496387 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:59:25.499647 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:59:25.506500 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:59:25.509884 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1826 13:59:25.512914 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1827 13:59:25.519706 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1828 13:59:25.522827 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:59:25.526299 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:59:25.533280 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:59:25.536840 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:59:25.539789 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:59:25.546474 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:59:25.549839 0 9 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1835 13:59:25.553244 0 9 8 | B1->B0 | 3333 2d2d | 1 1 | (1 1) (1 1)
1836 13:59:25.559737 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 13:59:25.562923 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 13:59:25.566179 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 13:59:25.569526 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 13:59:25.576795 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 13:59:25.579924 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 13:59:25.582969 0 10 4 | B1->B0 | 2a2a 3232 | 1 0 | (1 0) (0 1)
1843 13:59:25.589929 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
1844 13:59:25.593069 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:59:25.596872 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:59:25.603427 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:59:25.606647 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:59:25.609809 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:59:25.616833 0 11 0 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1850 13:59:25.620129 0 11 4 | B1->B0 | 3535 2a2a | 0 0 | (0 0) (0 0)
1851 13:59:25.623537 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1852 13:59:25.629995 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 13:59:25.633291 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 13:59:25.636815 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 13:59:25.643325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 13:59:25.646340 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 13:59:25.649605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1858 13:59:25.653311 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1859 13:59:25.659913 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:59:25.663396 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:59:25.666566 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:59:25.673581 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:59:25.676751 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:59:25.679990 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:59:25.686449 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:59:25.690377 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:59:25.693274 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:59:25.699743 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:59:25.703676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:59:25.706774 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:59:25.713487 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:59:25.716565 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:59:25.720427 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1874 13:59:25.727018 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1875 13:59:25.730358 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 13:59:25.733573 Total UI for P1: 0, mck2ui 16
1877 13:59:25.736736 best dqsien dly found for B0: ( 0, 14, 2)
1878 13:59:25.740047 Total UI for P1: 0, mck2ui 16
1879 13:59:25.743344 best dqsien dly found for B1: ( 0, 14, 2)
1880 13:59:25.747046 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1881 13:59:25.750203 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1882 13:59:25.750280
1883 13:59:25.753393 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1884 13:59:25.757037 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1885 13:59:25.760304 [Gating] SW calibration Done
1886 13:59:25.760379 ==
1887 13:59:25.763566 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 13:59:25.767121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 13:59:25.767237 ==
1890 13:59:25.769824 RX Vref Scan: 0
1891 13:59:25.769901
1892 13:59:25.769962 RX Vref 0 -> 0, step: 1
1893 13:59:25.770019
1894 13:59:25.773731 RX Delay -130 -> 252, step: 16
1895 13:59:25.780488 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1896 13:59:25.783240 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1897 13:59:25.786581 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1898 13:59:25.790006 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1899 13:59:25.793988 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1900 13:59:25.797078 iDelay=222, Bit 5, Center 117 (14 ~ 221) 208
1901 13:59:25.803685 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1902 13:59:25.807277 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1903 13:59:25.810089 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1904 13:59:25.813431 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1905 13:59:25.816839 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1906 13:59:25.823865 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1907 13:59:25.826914 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1908 13:59:25.830230 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1909 13:59:25.833482 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1910 13:59:25.836734 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1911 13:59:25.840409 ==
1912 13:59:25.843589 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 13:59:25.846920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 13:59:25.847002 ==
1915 13:59:25.847066 DQS Delay:
1916 13:59:25.850147 DQS0 = 0, DQS1 = 0
1917 13:59:25.850228 DQM Delay:
1918 13:59:25.853980 DQM0 = 94, DQM1 = 89
1919 13:59:25.854060 DQ Delay:
1920 13:59:25.857267 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1921 13:59:25.860530 DQ4 =85, DQ5 =117, DQ6 =101, DQ7 =93
1922 13:59:25.863689 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1923 13:59:25.867184 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1924 13:59:25.867265
1925 13:59:25.867327
1926 13:59:25.867386 ==
1927 13:59:25.870679 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 13:59:25.874117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 13:59:25.874199 ==
1930 13:59:25.874297
1931 13:59:25.874355
1932 13:59:25.877108 TX Vref Scan disable
1933 13:59:25.880203 == TX Byte 0 ==
1934 13:59:25.884000 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1935 13:59:25.887080 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1936 13:59:25.890885 == TX Byte 1 ==
1937 13:59:25.894182 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1938 13:59:25.897370 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1939 13:59:25.897438 ==
1940 13:59:25.900562 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 13:59:25.903527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 13:59:25.907169 ==
1943 13:59:25.918421 TX Vref=22, minBit 3, minWin=26, winSum=439
1944 13:59:25.921863 TX Vref=24, minBit 2, minWin=26, winSum=442
1945 13:59:25.924907 TX Vref=26, minBit 1, minWin=27, winSum=449
1946 13:59:25.928283 TX Vref=28, minBit 1, minWin=27, winSum=451
1947 13:59:25.932025 TX Vref=30, minBit 1, minWin=27, winSum=449
1948 13:59:25.935366 TX Vref=32, minBit 3, minWin=26, winSum=447
1949 13:59:25.941862 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 28
1950 13:59:25.941941
1951 13:59:25.945467 Final TX Range 1 Vref 28
1952 13:59:25.945538
1953 13:59:25.945603 ==
1954 13:59:25.948743 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 13:59:25.951957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 13:59:25.952029 ==
1957 13:59:25.952088
1958 13:59:25.952144
1959 13:59:25.955194 TX Vref Scan disable
1960 13:59:25.958380 == TX Byte 0 ==
1961 13:59:25.962331 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1962 13:59:25.965453 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1963 13:59:25.968672 == TX Byte 1 ==
1964 13:59:25.971711 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1965 13:59:25.975091 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1966 13:59:25.975161
1967 13:59:25.979001 [DATLAT]
1968 13:59:25.979070 Freq=800, CH1 RK1
1969 13:59:25.979128
1970 13:59:25.982033 DATLAT Default: 0xa
1971 13:59:25.982119 0, 0xFFFF, sum = 0
1972 13:59:25.985313 1, 0xFFFF, sum = 0
1973 13:59:25.985387 2, 0xFFFF, sum = 0
1974 13:59:25.988661 3, 0xFFFF, sum = 0
1975 13:59:25.988727 4, 0xFFFF, sum = 0
1976 13:59:25.991665 5, 0xFFFF, sum = 0
1977 13:59:25.991736 6, 0xFFFF, sum = 0
1978 13:59:25.995345 7, 0xFFFF, sum = 0
1979 13:59:25.995419 8, 0xFFFF, sum = 0
1980 13:59:25.998675 9, 0x0, sum = 1
1981 13:59:25.998744 10, 0x0, sum = 2
1982 13:59:26.002092 11, 0x0, sum = 3
1983 13:59:26.002158 12, 0x0, sum = 4
1984 13:59:26.005688 best_step = 10
1985 13:59:26.005759
1986 13:59:26.005819 ==
1987 13:59:26.008642 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 13:59:26.011921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 13:59:26.011989 ==
1990 13:59:26.015215 RX Vref Scan: 0
1991 13:59:26.015280
1992 13:59:26.015340 RX Vref 0 -> 0, step: 1
1993 13:59:26.015396
1994 13:59:26.018276 RX Delay -79 -> 252, step: 8
1995 13:59:26.025304 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1996 13:59:26.028440 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1997 13:59:26.032003 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1998 13:59:26.035575 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1999 13:59:26.038584 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2000 13:59:26.041591 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2001 13:59:26.048186 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2002 13:59:26.051959 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2003 13:59:26.055391 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2004 13:59:26.058404 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2005 13:59:26.062236 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2006 13:59:26.068893 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2007 13:59:26.072024 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2008 13:59:26.075365 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2009 13:59:26.078455 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2010 13:59:26.082269 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2011 13:59:26.082338 ==
2012 13:59:26.085632 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 13:59:26.091882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 13:59:26.091950 ==
2015 13:59:26.092017 DQS Delay:
2016 13:59:26.095242 DQS0 = 0, DQS1 = 0
2017 13:59:26.095307 DQM Delay:
2018 13:59:26.095363 DQM0 = 97, DQM1 = 91
2019 13:59:26.098466 DQ Delay:
2020 13:59:26.102461 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2021 13:59:26.105477 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2022 13:59:26.108494 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2023 13:59:26.112221 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2024 13:59:26.112300
2025 13:59:26.112373
2026 13:59:26.118636 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2027 13:59:26.122500 CH1 RK1: MR19=606, MR18=440E
2028 13:59:26.128579 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2029 13:59:26.132094 [RxdqsGatingPostProcess] freq 800
2030 13:59:26.135301 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 13:59:26.138605 Pre-setting of DQS Precalculation
2032 13:59:26.145161 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 13:59:26.152062 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 13:59:26.158942 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 13:59:26.159020
2036 13:59:26.159090
2037 13:59:26.162269 [Calibration Summary] 1600 Mbps
2038 13:59:26.162359 CH 0, Rank 0
2039 13:59:26.165478 SW Impedance : PASS
2040 13:59:26.168439 DUTY Scan : NO K
2041 13:59:26.168519 ZQ Calibration : PASS
2042 13:59:26.171870 Jitter Meter : NO K
2043 13:59:26.175089 CBT Training : PASS
2044 13:59:26.175195 Write leveling : PASS
2045 13:59:26.178820 RX DQS gating : PASS
2046 13:59:26.182246 RX DQ/DQS(RDDQC) : PASS
2047 13:59:26.182331 TX DQ/DQS : PASS
2048 13:59:26.185517 RX DATLAT : PASS
2049 13:59:26.185615 RX DQ/DQS(Engine): PASS
2050 13:59:26.188752 TX OE : NO K
2051 13:59:26.188853 All Pass.
2052 13:59:26.188942
2053 13:59:26.191965 CH 0, Rank 1
2054 13:59:26.192061 SW Impedance : PASS
2055 13:59:26.195823 DUTY Scan : NO K
2056 13:59:26.199038 ZQ Calibration : PASS
2057 13:59:26.199135 Jitter Meter : NO K
2058 13:59:26.202274 CBT Training : PASS
2059 13:59:26.205571 Write leveling : PASS
2060 13:59:26.205667 RX DQS gating : PASS
2061 13:59:26.208839 RX DQ/DQS(RDDQC) : PASS
2062 13:59:26.212061 TX DQ/DQS : PASS
2063 13:59:26.212160 RX DATLAT : PASS
2064 13:59:26.215384 RX DQ/DQS(Engine): PASS
2065 13:59:26.219267 TX OE : NO K
2066 13:59:26.219367 All Pass.
2067 13:59:26.219448
2068 13:59:26.219509 CH 1, Rank 0
2069 13:59:26.222483 SW Impedance : PASS
2070 13:59:26.225866 DUTY Scan : NO K
2071 13:59:26.225939 ZQ Calibration : PASS
2072 13:59:26.228905 Jitter Meter : NO K
2073 13:59:26.229004 CBT Training : PASS
2074 13:59:26.232534 Write leveling : PASS
2075 13:59:26.235775 RX DQS gating : PASS
2076 13:59:26.235871 RX DQ/DQS(RDDQC) : PASS
2077 13:59:26.238945 TX DQ/DQS : PASS
2078 13:59:26.242555 RX DATLAT : PASS
2079 13:59:26.242629 RX DQ/DQS(Engine): PASS
2080 13:59:26.245673 TX OE : NO K
2081 13:59:26.245745 All Pass.
2082 13:59:26.245807
2083 13:59:26.249113 CH 1, Rank 1
2084 13:59:26.249186 SW Impedance : PASS
2085 13:59:26.252922 DUTY Scan : NO K
2086 13:59:26.255558 ZQ Calibration : PASS
2087 13:59:26.255630 Jitter Meter : NO K
2088 13:59:26.259459 CBT Training : PASS
2089 13:59:26.262707 Write leveling : PASS
2090 13:59:26.262804 RX DQS gating : PASS
2091 13:59:26.265815 RX DQ/DQS(RDDQC) : PASS
2092 13:59:26.265911 TX DQ/DQS : PASS
2093 13:59:26.269004 RX DATLAT : PASS
2094 13:59:26.272780 RX DQ/DQS(Engine): PASS
2095 13:59:26.272880 TX OE : NO K
2096 13:59:26.275744 All Pass.
2097 13:59:26.275839
2098 13:59:26.275935 DramC Write-DBI off
2099 13:59:26.279443 PER_BANK_REFRESH: Hybrid Mode
2100 13:59:26.282457 TX_TRACKING: ON
2101 13:59:26.286033 [GetDramInforAfterCalByMRR] Vendor 6.
2102 13:59:26.289356 [GetDramInforAfterCalByMRR] Revision 606.
2103 13:59:26.292555 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 13:59:26.292652 MR0 0x3b3b
2105 13:59:26.292740 MR8 0x5151
2106 13:59:26.295646 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 13:59:26.299225
2108 13:59:26.299298 MR0 0x3b3b
2109 13:59:26.299358 MR8 0x5151
2110 13:59:26.302657 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 13:59:26.302754
2112 13:59:26.312809 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 13:59:26.315991 [FAST_K] Save calibration result to emmc
2114 13:59:26.319335 [FAST_K] Save calibration result to emmc
2115 13:59:26.322454 dram_init: config_dvfs: 1
2116 13:59:26.325845 dramc_set_vcore_voltage set vcore to 662500
2117 13:59:26.329136 Read voltage for 1200, 2
2118 13:59:26.329228 Vio18 = 0
2119 13:59:26.329314 Vcore = 662500
2120 13:59:26.332444 Vdram = 0
2121 13:59:26.332513 Vddq = 0
2122 13:59:26.332578 Vmddr = 0
2123 13:59:26.339573 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 13:59:26.342844 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 13:59:26.345851 MEM_TYPE=3, freq_sel=15
2126 13:59:26.349544 sv_algorithm_assistance_LP4_1600
2127 13:59:26.352469 ============ PULL DRAM RESETB DOWN ============
2128 13:59:26.356381 ========== PULL DRAM RESETB DOWN end =========
2129 13:59:26.362493 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 13:59:26.365867 ===================================
2131 13:59:26.365968 LPDDR4 DRAM CONFIGURATION
2132 13:59:26.369614 ===================================
2133 13:59:26.372815 EX_ROW_EN[0] = 0x0
2134 13:59:26.375928 EX_ROW_EN[1] = 0x0
2135 13:59:26.376023 LP4Y_EN = 0x0
2136 13:59:26.379875 WORK_FSP = 0x0
2137 13:59:26.379973 WL = 0x4
2138 13:59:26.382849 RL = 0x4
2139 13:59:26.382946 BL = 0x2
2140 13:59:26.386477 RPST = 0x0
2141 13:59:26.386569 RD_PRE = 0x0
2142 13:59:26.389692 WR_PRE = 0x1
2143 13:59:26.389758 WR_PST = 0x0
2144 13:59:26.392941 DBI_WR = 0x0
2145 13:59:26.393035 DBI_RD = 0x0
2146 13:59:26.396250 OTF = 0x1
2147 13:59:26.399453 ===================================
2148 13:59:26.402726 ===================================
2149 13:59:26.402821 ANA top config
2150 13:59:26.406092 ===================================
2151 13:59:26.409415 DLL_ASYNC_EN = 0
2152 13:59:26.413045 ALL_SLAVE_EN = 0
2153 13:59:26.413120 NEW_RANK_MODE = 1
2154 13:59:26.415832 DLL_IDLE_MODE = 1
2155 13:59:26.419400 LP45_APHY_COMB_EN = 1
2156 13:59:26.422821 TX_ODT_DIS = 1
2157 13:59:26.426231 NEW_8X_MODE = 1
2158 13:59:26.429547 ===================================
2159 13:59:26.432465 ===================================
2160 13:59:26.432539 data_rate = 2400
2161 13:59:26.436412 CKR = 1
2162 13:59:26.439631 DQ_P2S_RATIO = 8
2163 13:59:26.442868 ===================================
2164 13:59:26.446102 CA_P2S_RATIO = 8
2165 13:59:26.449367 DQ_CA_OPEN = 0
2166 13:59:26.452584 DQ_SEMI_OPEN = 0
2167 13:59:26.452657 CA_SEMI_OPEN = 0
2168 13:59:26.455840 CA_FULL_RATE = 0
2169 13:59:26.459027 DQ_CKDIV4_EN = 0
2170 13:59:26.462376 CA_CKDIV4_EN = 0
2171 13:59:26.466050 CA_PREDIV_EN = 0
2172 13:59:26.469143 PH8_DLY = 17
2173 13:59:26.469217 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 13:59:26.472461 DQ_AAMCK_DIV = 4
2175 13:59:26.476195 CA_AAMCK_DIV = 4
2176 13:59:26.479198 CA_ADMCK_DIV = 4
2177 13:59:26.482418 DQ_TRACK_CA_EN = 0
2178 13:59:26.485708 CA_PICK = 1200
2179 13:59:26.489482 CA_MCKIO = 1200
2180 13:59:26.489565 MCKIO_SEMI = 0
2181 13:59:26.492381 PLL_FREQ = 2366
2182 13:59:26.496201 DQ_UI_PI_RATIO = 32
2183 13:59:26.499416 CA_UI_PI_RATIO = 0
2184 13:59:26.502744 ===================================
2185 13:59:26.506030 ===================================
2186 13:59:26.509297 memory_type:LPDDR4
2187 13:59:26.509367 GP_NUM : 10
2188 13:59:26.512366 SRAM_EN : 1
2189 13:59:26.512436 MD32_EN : 0
2190 13:59:26.515972 ===================================
2191 13:59:26.518914 [ANA_INIT] >>>>>>>>>>>>>>
2192 13:59:26.522677 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 13:59:26.526079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 13:59:26.529104 ===================================
2195 13:59:26.532848 data_rate = 2400,PCW = 0X5b00
2196 13:59:26.535863 ===================================
2197 13:59:26.539416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 13:59:26.545687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 13:59:26.549532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 13:59:26.556200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 13:59:26.559419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 13:59:26.562724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 13:59:26.562826 [ANA_INIT] flow start
2204 13:59:26.565902 [ANA_INIT] PLL >>>>>>>>
2205 13:59:26.569192 [ANA_INIT] PLL <<<<<<<<
2206 13:59:26.569260 [ANA_INIT] MIDPI >>>>>>>>
2207 13:59:26.572509 [ANA_INIT] MIDPI <<<<<<<<
2208 13:59:26.576486 [ANA_INIT] DLL >>>>>>>>
2209 13:59:26.576581 [ANA_INIT] DLL <<<<<<<<
2210 13:59:26.579573 [ANA_INIT] flow end
2211 13:59:26.582568 ============ LP4 DIFF to SE enter ============
2212 13:59:26.586143 ============ LP4 DIFF to SE exit ============
2213 13:59:26.589571 [ANA_INIT] <<<<<<<<<<<<<
2214 13:59:26.592777 [Flow] Enable top DCM control >>>>>
2215 13:59:26.595894 [Flow] Enable top DCM control <<<<<
2216 13:59:26.599221 Enable DLL master slave shuffle
2217 13:59:26.605890 ==============================================================
2218 13:59:26.605966 Gating Mode config
2219 13:59:26.612920 ==============================================================
2220 13:59:26.612998 Config description:
2221 13:59:26.622514 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 13:59:26.629559 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 13:59:26.636199 SELPH_MODE 0: By rank 1: By Phase
2224 13:59:26.639597 ==============================================================
2225 13:59:26.642632 GAT_TRACK_EN = 1
2226 13:59:26.646402 RX_GATING_MODE = 2
2227 13:59:26.649479 RX_GATING_TRACK_MODE = 2
2228 13:59:26.653029 SELPH_MODE = 1
2229 13:59:26.656182 PICG_EARLY_EN = 1
2230 13:59:26.659748 VALID_LAT_VALUE = 1
2231 13:59:26.663021 ==============================================================
2232 13:59:26.666060 Enter into Gating configuration >>>>
2233 13:59:26.669866 Exit from Gating configuration <<<<
2234 13:59:26.673061 Enter into DVFS_PRE_config >>>>>
2235 13:59:26.686622 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 13:59:26.686714 Exit from DVFS_PRE_config <<<<<
2237 13:59:26.689609 Enter into PICG configuration >>>>
2238 13:59:26.693212 Exit from PICG configuration <<<<
2239 13:59:26.696544 [RX_INPUT] configuration >>>>>
2240 13:59:26.699755 [RX_INPUT] configuration <<<<<
2241 13:59:26.706124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 13:59:26.709573 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 13:59:26.716208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 13:59:26.723057 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 13:59:26.729782 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 13:59:26.736810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 13:59:26.740011 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 13:59:26.743197 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 13:59:26.746187 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 13:59:26.753004 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 13:59:26.756396 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 13:59:26.759583 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 13:59:26.763294 ===================================
2254 13:59:26.766360 LPDDR4 DRAM CONFIGURATION
2255 13:59:26.769959 ===================================
2256 13:59:26.770058 EX_ROW_EN[0] = 0x0
2257 13:59:26.773299 EX_ROW_EN[1] = 0x0
2258 13:59:26.773404 LP4Y_EN = 0x0
2259 13:59:26.776398 WORK_FSP = 0x0
2260 13:59:26.779574 WL = 0x4
2261 13:59:26.779648 RL = 0x4
2262 13:59:26.783331 BL = 0x2
2263 13:59:26.783438 RPST = 0x0
2264 13:59:26.786676 RD_PRE = 0x0
2265 13:59:26.786771 WR_PRE = 0x1
2266 13:59:26.789839 WR_PST = 0x0
2267 13:59:26.789933 DBI_WR = 0x0
2268 13:59:26.793082 DBI_RD = 0x0
2269 13:59:26.793150 OTF = 0x1
2270 13:59:26.796161 ===================================
2271 13:59:26.799891 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 13:59:26.806351 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 13:59:26.809747 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 13:59:26.813034 ===================================
2275 13:59:26.816244 LPDDR4 DRAM CONFIGURATION
2276 13:59:26.820243 ===================================
2277 13:59:26.820389 EX_ROW_EN[0] = 0x10
2278 13:59:26.822798 EX_ROW_EN[1] = 0x0
2279 13:59:26.822893 LP4Y_EN = 0x0
2280 13:59:26.826604 WORK_FSP = 0x0
2281 13:59:26.826701 WL = 0x4
2282 13:59:26.829655 RL = 0x4
2283 13:59:26.829742 BL = 0x2
2284 13:59:26.833158 RPST = 0x0
2285 13:59:26.833229 RD_PRE = 0x0
2286 13:59:26.836496 WR_PRE = 0x1
2287 13:59:26.836567 WR_PST = 0x0
2288 13:59:26.839821 DBI_WR = 0x0
2289 13:59:26.839943 DBI_RD = 0x0
2290 13:59:26.843185 OTF = 0x1
2291 13:59:26.846456 ===================================
2292 13:59:26.853120 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 13:59:26.853224 ==
2294 13:59:26.856190 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 13:59:26.859939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 13:59:26.860049 ==
2297 13:59:26.863411 [Duty_Offset_Calibration]
2298 13:59:26.863518 B0:1 B1:1 CA:1
2299 13:59:26.863608
2300 13:59:26.866384 [DutyScan_Calibration_Flow] k_type=0
2301 13:59:26.876912
2302 13:59:26.876985 ==CLK 0==
2303 13:59:26.880752 Final CLK duty delay cell = 0
2304 13:59:26.883754 [0] MAX Duty = 5187%(X100), DQS PI = 24
2305 13:59:26.886857 [0] MIN Duty = 4844%(X100), DQS PI = 48
2306 13:59:26.890364 [0] AVG Duty = 5015%(X100)
2307 13:59:26.890459
2308 13:59:26.893642 CH0 CLK Duty spec in!! Max-Min= 343%
2309 13:59:26.897172 [DutyScan_Calibration_Flow] ====Done====
2310 13:59:26.897253
2311 13:59:26.900232 [DutyScan_Calibration_Flow] k_type=1
2312 13:59:26.915740
2313 13:59:26.915845 ==DQS 0 ==
2314 13:59:26.918955 Final DQS duty delay cell = -4
2315 13:59:26.922309 [-4] MAX Duty = 5125%(X100), DQS PI = 22
2316 13:59:26.926223 [-4] MIN Duty = 4750%(X100), DQS PI = 0
2317 13:59:26.929387 [-4] AVG Duty = 4937%(X100)
2318 13:59:26.929488
2319 13:59:26.929577 ==DQS 1 ==
2320 13:59:26.932676 Final DQS duty delay cell = 0
2321 13:59:26.935872 [0] MAX Duty = 5187%(X100), DQS PI = 0
2322 13:59:26.939132 [0] MIN Duty = 5000%(X100), DQS PI = 34
2323 13:59:26.942516 [0] AVG Duty = 5093%(X100)
2324 13:59:26.942585
2325 13:59:26.946036 CH0 DQS 0 Duty spec in!! Max-Min= 375%
2326 13:59:26.946108
2327 13:59:26.949572 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2328 13:59:26.952653 [DutyScan_Calibration_Flow] ====Done====
2329 13:59:26.952729
2330 13:59:26.956129 [DutyScan_Calibration_Flow] k_type=3
2331 13:59:26.972913
2332 13:59:26.973002 ==DQM 0 ==
2333 13:59:26.976162 Final DQM duty delay cell = 0
2334 13:59:26.979220 [0] MAX Duty = 5187%(X100), DQS PI = 26
2335 13:59:26.982707 [0] MIN Duty = 4907%(X100), DQS PI = 50
2336 13:59:26.986022 [0] AVG Duty = 5047%(X100)
2337 13:59:26.986095
2338 13:59:26.986155 ==DQM 1 ==
2339 13:59:26.989194 Final DQM duty delay cell = 0
2340 13:59:26.992428 [0] MAX Duty = 5093%(X100), DQS PI = 0
2341 13:59:26.995697 [0] MIN Duty = 5031%(X100), DQS PI = 14
2342 13:59:26.995802 [0] AVG Duty = 5062%(X100)
2343 13:59:26.999483
2344 13:59:27.002535 CH0 DQM 0 Duty spec in!! Max-Min= 280%
2345 13:59:27.002629
2346 13:59:27.006203 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2347 13:59:27.009614 [DutyScan_Calibration_Flow] ====Done====
2348 13:59:27.009682
2349 13:59:27.013049 [DutyScan_Calibration_Flow] k_type=2
2350 13:59:27.029295
2351 13:59:27.029370 ==DQ 0 ==
2352 13:59:27.032583 Final DQ duty delay cell = 0
2353 13:59:27.035778 [0] MAX Duty = 5031%(X100), DQS PI = 24
2354 13:59:27.039039 [0] MIN Duty = 4876%(X100), DQS PI = 62
2355 13:59:27.039142 [0] AVG Duty = 4953%(X100)
2356 13:59:27.039228
2357 13:59:27.042383 ==DQ 1 ==
2358 13:59:27.045616 Final DQ duty delay cell = 0
2359 13:59:27.048915 [0] MAX Duty = 5093%(X100), DQS PI = 24
2360 13:59:27.052715 [0] MIN Duty = 4969%(X100), DQS PI = 14
2361 13:59:27.052810 [0] AVG Duty = 5031%(X100)
2362 13:59:27.052906
2363 13:59:27.055655 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2364 13:59:27.059398
2365 13:59:27.062533 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2366 13:59:27.065745 [DutyScan_Calibration_Flow] ====Done====
2367 13:59:27.065813 ==
2368 13:59:27.069521 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 13:59:27.072532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 13:59:27.072602 ==
2371 13:59:27.075943 [Duty_Offset_Calibration]
2372 13:59:27.076038 B0:1 B1:0 CA:0
2373 13:59:27.076126
2374 13:59:27.079331 [DutyScan_Calibration_Flow] k_type=0
2375 13:59:27.088640
2376 13:59:27.088713 ==CLK 0==
2377 13:59:27.091533 Final CLK duty delay cell = -4
2378 13:59:27.094893 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2379 13:59:27.098437 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2380 13:59:27.101949 [-4] AVG Duty = 4953%(X100)
2381 13:59:27.102022
2382 13:59:27.105250 CH1 CLK Duty spec in!! Max-Min= 156%
2383 13:59:27.108515 [DutyScan_Calibration_Flow] ====Done====
2384 13:59:27.108610
2385 13:59:27.111916 [DutyScan_Calibration_Flow] k_type=1
2386 13:59:27.128236
2387 13:59:27.128379 ==DQS 0 ==
2388 13:59:27.131328 Final DQS duty delay cell = 0
2389 13:59:27.134557 [0] MAX Duty = 5094%(X100), DQS PI = 26
2390 13:59:27.137965 [0] MIN Duty = 4844%(X100), DQS PI = 0
2391 13:59:27.138037 [0] AVG Duty = 4969%(X100)
2392 13:59:27.141869
2393 13:59:27.141962 ==DQS 1 ==
2394 13:59:27.145153 Final DQS duty delay cell = 0
2395 13:59:27.148551 [0] MAX Duty = 5187%(X100), DQS PI = 18
2396 13:59:27.151779 [0] MIN Duty = 4969%(X100), DQS PI = 8
2397 13:59:27.151881 [0] AVG Duty = 5078%(X100)
2398 13:59:27.151968
2399 13:59:27.158128 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2400 13:59:27.158227
2401 13:59:27.161870 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2402 13:59:27.165082 [DutyScan_Calibration_Flow] ====Done====
2403 13:59:27.165153
2404 13:59:27.168316 [DutyScan_Calibration_Flow] k_type=3
2405 13:59:27.184361
2406 13:59:27.184446 ==DQM 0 ==
2407 13:59:27.188180 Final DQM duty delay cell = 0
2408 13:59:27.191067 [0] MAX Duty = 5156%(X100), DQS PI = 6
2409 13:59:27.194569 [0] MIN Duty = 5031%(X100), DQS PI = 46
2410 13:59:27.194671 [0] AVG Duty = 5093%(X100)
2411 13:59:27.198042
2412 13:59:27.198140 ==DQM 1 ==
2413 13:59:27.201471 Final DQM duty delay cell = 0
2414 13:59:27.205085 [0] MAX Duty = 5031%(X100), DQS PI = 16
2415 13:59:27.207988 [0] MIN Duty = 4907%(X100), DQS PI = 36
2416 13:59:27.208109 [0] AVG Duty = 4969%(X100)
2417 13:59:27.211000
2418 13:59:27.214407 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2419 13:59:27.214510
2420 13:59:27.218160 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2421 13:59:27.221336 [DutyScan_Calibration_Flow] ====Done====
2422 13:59:27.221433
2423 13:59:27.224579 [DutyScan_Calibration_Flow] k_type=2
2424 13:59:27.240374
2425 13:59:27.240450 ==DQ 0 ==
2426 13:59:27.243808 Final DQ duty delay cell = -4
2427 13:59:27.246884 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2428 13:59:27.250744 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2429 13:59:27.253918 [-4] AVG Duty = 4984%(X100)
2430 13:59:27.253987
2431 13:59:27.254047 ==DQ 1 ==
2432 13:59:27.257125 Final DQ duty delay cell = 0
2433 13:59:27.260413 [0] MAX Duty = 5125%(X100), DQS PI = 20
2434 13:59:27.263541 [0] MIN Duty = 4969%(X100), DQS PI = 12
2435 13:59:27.263611 [0] AVG Duty = 5047%(X100)
2436 13:59:27.267364
2437 13:59:27.270166 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2438 13:59:27.270260
2439 13:59:27.273681 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2440 13:59:27.276914 [DutyScan_Calibration_Flow] ====Done====
2441 13:59:27.280977 nWR fixed to 30
2442 13:59:27.281048 [ModeRegInit_LP4] CH0 RK0
2443 13:59:27.284219 [ModeRegInit_LP4] CH0 RK1
2444 13:59:27.287396 [ModeRegInit_LP4] CH1 RK0
2445 13:59:27.287489 [ModeRegInit_LP4] CH1 RK1
2446 13:59:27.290500 match AC timing 7
2447 13:59:27.294153 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 13:59:27.297520 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 13:59:27.304198 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 13:59:27.307270 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 13:59:27.314267 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 13:59:27.314339 ==
2453 13:59:27.317383 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 13:59:27.320926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 13:59:27.321022 ==
2456 13:59:27.327180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 13:59:27.330902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2458 13:59:27.340857 [CA 0] Center 39 (8~70) winsize 63
2459 13:59:27.344019 [CA 1] Center 39 (8~70) winsize 63
2460 13:59:27.347228 [CA 2] Center 35 (5~66) winsize 62
2461 13:59:27.350996 [CA 3] Center 34 (4~65) winsize 62
2462 13:59:27.354559 [CA 4] Center 33 (3~64) winsize 62
2463 13:59:27.357226 [CA 5] Center 32 (3~62) winsize 60
2464 13:59:27.357323
2465 13:59:27.360792 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2466 13:59:27.360868
2467 13:59:27.364213 [CATrainingPosCal] consider 1 rank data
2468 13:59:27.367539 u2DelayCellTimex100 = 270/100 ps
2469 13:59:27.370610 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2470 13:59:27.373811 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2471 13:59:27.380420 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2472 13:59:27.384194 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2473 13:59:27.387594 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2474 13:59:27.390716 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2475 13:59:27.390808
2476 13:59:27.393964 CA PerBit enable=1, Macro0, CA PI delay=32
2477 13:59:27.394032
2478 13:59:27.397637 [CBTSetCACLKResult] CA Dly = 32
2479 13:59:27.397730 CS Dly: 6 (0~37)
2480 13:59:27.400732 ==
2481 13:59:27.400800 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 13:59:27.407137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 13:59:27.407235 ==
2484 13:59:27.410667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 13:59:27.417530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2486 13:59:27.426640 [CA 0] Center 38 (8~69) winsize 62
2487 13:59:27.429635 [CA 1] Center 38 (8~69) winsize 62
2488 13:59:27.433198 [CA 2] Center 35 (5~66) winsize 62
2489 13:59:27.436171 [CA 3] Center 34 (4~65) winsize 62
2490 13:59:27.439725 [CA 4] Center 33 (3~64) winsize 62
2491 13:59:27.443047 [CA 5] Center 32 (2~62) winsize 61
2492 13:59:27.443142
2493 13:59:27.446291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2494 13:59:27.446358
2495 13:59:27.449531 [CATrainingPosCal] consider 2 rank data
2496 13:59:27.452819 u2DelayCellTimex100 = 270/100 ps
2497 13:59:27.456596 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2498 13:59:27.459874 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2499 13:59:27.466096 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2500 13:59:27.469806 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2501 13:59:27.472808 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2502 13:59:27.476775 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2503 13:59:27.476873
2504 13:59:27.479566 CA PerBit enable=1, Macro0, CA PI delay=32
2505 13:59:27.479638
2506 13:59:27.483217 [CBTSetCACLKResult] CA Dly = 32
2507 13:59:27.483317 CS Dly: 6 (0~38)
2508 13:59:27.483384
2509 13:59:27.486089 ----->DramcWriteLeveling(PI) begin...
2510 13:59:27.489582 ==
2511 13:59:27.493422 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 13:59:27.496674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 13:59:27.496746 ==
2514 13:59:27.499786 Write leveling (Byte 0): 33 => 33
2515 13:59:27.502875 Write leveling (Byte 1): 29 => 29
2516 13:59:27.506487 DramcWriteLeveling(PI) end<-----
2517 13:59:27.506584
2518 13:59:27.506673 ==
2519 13:59:27.509690 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 13:59:27.512934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 13:59:27.513007 ==
2522 13:59:27.516817 [Gating] SW mode calibration
2523 13:59:27.522874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 13:59:27.526093 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 13:59:27.533440 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2526 13:59:27.536608 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2527 13:59:27.539689 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 13:59:27.546875 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 13:59:27.550112 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 13:59:27.553411 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 13:59:27.559840 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2532 13:59:27.563627 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
2533 13:59:27.566913 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2534 13:59:27.573378 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 13:59:27.576644 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 13:59:27.580010 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 13:59:27.586601 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 13:59:27.589659 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 13:59:27.593066 1 0 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
2540 13:59:27.599894 1 0 28 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
2541 13:59:27.603071 1 1 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
2542 13:59:27.606510 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 13:59:27.609605 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 13:59:27.616875 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 13:59:27.619942 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 13:59:27.623226 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 13:59:27.629581 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 13:59:27.632817 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 13:59:27.636114 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2550 13:59:27.642781 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 13:59:27.646553 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:59:27.649716 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:59:27.656212 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:59:27.659395 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:59:27.662756 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:59:27.669659 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:59:27.672824 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:59:27.676113 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:59:27.683520 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:59:27.686124 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:59:27.690001 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:59:27.696527 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:59:27.699674 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:59:27.702896 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 13:59:27.709567 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 13:59:27.709643 Total UI for P1: 0, mck2ui 16
2567 13:59:27.713152 best dqsien dly found for B0: ( 1, 3, 28)
2568 13:59:27.719713 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 13:59:27.723063 Total UI for P1: 0, mck2ui 16
2570 13:59:27.726502 best dqsien dly found for B1: ( 1, 4, 0)
2571 13:59:27.729615 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2572 13:59:27.733080 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2573 13:59:27.733191
2574 13:59:27.736485 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2575 13:59:27.739621 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2576 13:59:27.743352 [Gating] SW calibration Done
2577 13:59:27.743425 ==
2578 13:59:27.746633 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 13:59:27.749938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 13:59:27.750036 ==
2581 13:59:27.753198 RX Vref Scan: 0
2582 13:59:27.753267
2583 13:59:27.753327 RX Vref 0 -> 0, step: 1
2584 13:59:27.753383
2585 13:59:27.756359 RX Delay -40 -> 252, step: 8
2586 13:59:27.760042 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2587 13:59:27.766335 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2588 13:59:27.769533 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2589 13:59:27.773369 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2590 13:59:27.776449 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2591 13:59:27.779517 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2592 13:59:27.786618 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2593 13:59:27.789866 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2594 13:59:27.793116 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2595 13:59:27.796368 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2596 13:59:27.799519 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2597 13:59:27.806722 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2598 13:59:27.809770 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2599 13:59:27.813092 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2600 13:59:27.816405 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2601 13:59:27.820135 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2602 13:59:27.820231 ==
2603 13:59:27.823193 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 13:59:27.829793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 13:59:27.829874 ==
2606 13:59:27.829937 DQS Delay:
2607 13:59:27.833371 DQS0 = 0, DQS1 = 0
2608 13:59:27.833450 DQM Delay:
2609 13:59:27.836787 DQM0 = 121, DQM1 = 113
2610 13:59:27.836867 DQ Delay:
2611 13:59:27.839801 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2612 13:59:27.843047 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2613 13:59:27.846849 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2614 13:59:27.849888 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2615 13:59:27.849992
2616 13:59:27.850082
2617 13:59:27.850172 ==
2618 13:59:27.853410 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 13:59:27.856329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 13:59:27.860242 ==
2621 13:59:27.860362
2622 13:59:27.860424
2623 13:59:27.860481 TX Vref Scan disable
2624 13:59:27.863611 == TX Byte 0 ==
2625 13:59:27.866756 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2626 13:59:27.870269 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2627 13:59:27.873251 == TX Byte 1 ==
2628 13:59:27.876857 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2629 13:59:27.879945 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2630 13:59:27.883155 ==
2631 13:59:27.883257 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 13:59:27.890227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 13:59:27.890332 ==
2634 13:59:27.901279 TX Vref=22, minBit 0, minWin=25, winSum=405
2635 13:59:27.904404 TX Vref=24, minBit 0, minWin=25, winSum=414
2636 13:59:27.907909 TX Vref=26, minBit 7, minWin=25, winSum=417
2637 13:59:27.910929 TX Vref=28, minBit 13, minWin=25, winSum=421
2638 13:59:27.914229 TX Vref=30, minBit 0, minWin=26, winSum=424
2639 13:59:27.921137 TX Vref=32, minBit 0, minWin=26, winSum=421
2640 13:59:27.924421 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2641 13:59:27.924493
2642 13:59:27.927657 Final TX Range 1 Vref 30
2643 13:59:27.927728
2644 13:59:27.927790 ==
2645 13:59:27.931381 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 13:59:27.934494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 13:59:27.934588 ==
2648 13:59:27.934677
2649 13:59:27.934761
2650 13:59:27.937677 TX Vref Scan disable
2651 13:59:27.941186 == TX Byte 0 ==
2652 13:59:27.944802 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2653 13:59:27.948104 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2654 13:59:27.951153 == TX Byte 1 ==
2655 13:59:27.954408 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2656 13:59:27.957591 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2657 13:59:27.957664
2658 13:59:27.961288 [DATLAT]
2659 13:59:27.961387 Freq=1200, CH0 RK0
2660 13:59:27.961475
2661 13:59:27.964665 DATLAT Default: 0xd
2662 13:59:27.964733 0, 0xFFFF, sum = 0
2663 13:59:27.968229 1, 0xFFFF, sum = 0
2664 13:59:27.968356 2, 0xFFFF, sum = 0
2665 13:59:27.971394 3, 0xFFFF, sum = 0
2666 13:59:27.971488 4, 0xFFFF, sum = 0
2667 13:59:27.974505 5, 0xFFFF, sum = 0
2668 13:59:27.974606 6, 0xFFFF, sum = 0
2669 13:59:27.978144 7, 0xFFFF, sum = 0
2670 13:59:27.978243 8, 0xFFFF, sum = 0
2671 13:59:27.981380 9, 0xFFFF, sum = 0
2672 13:59:27.981455 10, 0xFFFF, sum = 0
2673 13:59:27.984520 11, 0xFFFF, sum = 0
2674 13:59:27.984620 12, 0x0, sum = 1
2675 13:59:27.988122 13, 0x0, sum = 2
2676 13:59:27.988194 14, 0x0, sum = 3
2677 13:59:27.991177 15, 0x0, sum = 4
2678 13:59:27.991275 best_step = 13
2679 13:59:27.991360
2680 13:59:27.991446 ==
2681 13:59:27.994604 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 13:59:28.001336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 13:59:28.001415 ==
2684 13:59:28.001480 RX Vref Scan: 1
2685 13:59:28.001539
2686 13:59:28.004496 Set Vref Range= 32 -> 127
2687 13:59:28.004569
2688 13:59:28.007801 RX Vref 32 -> 127, step: 1
2689 13:59:28.007893
2690 13:59:28.011729 RX Delay -13 -> 252, step: 4
2691 13:59:28.011800
2692 13:59:28.015058 Set Vref, RX VrefLevel [Byte0]: 32
2693 13:59:28.018088 [Byte1]: 32
2694 13:59:28.018182
2695 13:59:28.021245 Set Vref, RX VrefLevel [Byte0]: 33
2696 13:59:28.025080 [Byte1]: 33
2697 13:59:28.025178
2698 13:59:28.028231 Set Vref, RX VrefLevel [Byte0]: 34
2699 13:59:28.031354 [Byte1]: 34
2700 13:59:28.035225
2701 13:59:28.035294 Set Vref, RX VrefLevel [Byte0]: 35
2702 13:59:28.038349 [Byte1]: 35
2703 13:59:28.042977
2704 13:59:28.043070 Set Vref, RX VrefLevel [Byte0]: 36
2705 13:59:28.046179 [Byte1]: 36
2706 13:59:28.050801
2707 13:59:28.050874 Set Vref, RX VrefLevel [Byte0]: 37
2708 13:59:28.054319 [Byte1]: 37
2709 13:59:28.058858
2710 13:59:28.058956 Set Vref, RX VrefLevel [Byte0]: 38
2711 13:59:28.062117 [Byte1]: 38
2712 13:59:28.066924
2713 13:59:28.066994 Set Vref, RX VrefLevel [Byte0]: 39
2714 13:59:28.070077 [Byte1]: 39
2715 13:59:28.074769
2716 13:59:28.074867 Set Vref, RX VrefLevel [Byte0]: 40
2717 13:59:28.078347 [Byte1]: 40
2718 13:59:28.082820
2719 13:59:28.082920 Set Vref, RX VrefLevel [Byte0]: 41
2720 13:59:28.085828 [Byte1]: 41
2721 13:59:28.090796
2722 13:59:28.090896 Set Vref, RX VrefLevel [Byte0]: 42
2723 13:59:28.093461 [Byte1]: 42
2724 13:59:28.098593
2725 13:59:28.098689 Set Vref, RX VrefLevel [Byte0]: 43
2726 13:59:28.102101 [Byte1]: 43
2727 13:59:28.106188
2728 13:59:28.106284 Set Vref, RX VrefLevel [Byte0]: 44
2729 13:59:28.109701 [Byte1]: 44
2730 13:59:28.114130
2731 13:59:28.114215 Set Vref, RX VrefLevel [Byte0]: 45
2732 13:59:28.117500 [Byte1]: 45
2733 13:59:28.122373
2734 13:59:28.122454 Set Vref, RX VrefLevel [Byte0]: 46
2735 13:59:28.125505 [Byte1]: 46
2736 13:59:28.129795
2737 13:59:28.132990 Set Vref, RX VrefLevel [Byte0]: 47
2738 13:59:28.136758 [Byte1]: 47
2739 13:59:28.136840
2740 13:59:28.139899 Set Vref, RX VrefLevel [Byte0]: 48
2741 13:59:28.143010 [Byte1]: 48
2742 13:59:28.143092
2743 13:59:28.146133 Set Vref, RX VrefLevel [Byte0]: 49
2744 13:59:28.150009 [Byte1]: 49
2745 13:59:28.153333
2746 13:59:28.153423 Set Vref, RX VrefLevel [Byte0]: 50
2747 13:59:28.157223 [Byte1]: 50
2748 13:59:28.161650
2749 13:59:28.161751 Set Vref, RX VrefLevel [Byte0]: 51
2750 13:59:28.164533 [Byte1]: 51
2751 13:59:28.169301
2752 13:59:28.169370 Set Vref, RX VrefLevel [Byte0]: 52
2753 13:59:28.172861 [Byte1]: 52
2754 13:59:28.177083
2755 13:59:28.177155 Set Vref, RX VrefLevel [Byte0]: 53
2756 13:59:28.180761 [Byte1]: 53
2757 13:59:28.185302
2758 13:59:28.185377 Set Vref, RX VrefLevel [Byte0]: 54
2759 13:59:28.188493 [Byte1]: 54
2760 13:59:28.193045
2761 13:59:28.193121 Set Vref, RX VrefLevel [Byte0]: 55
2762 13:59:28.196048 [Byte1]: 55
2763 13:59:28.201314
2764 13:59:28.201390 Set Vref, RX VrefLevel [Byte0]: 56
2765 13:59:28.204566 [Byte1]: 56
2766 13:59:28.209152
2767 13:59:28.209248 Set Vref, RX VrefLevel [Byte0]: 57
2768 13:59:28.212394 [Byte1]: 57
2769 13:59:28.216791
2770 13:59:28.216893 Set Vref, RX VrefLevel [Byte0]: 58
2771 13:59:28.220056 [Byte1]: 58
2772 13:59:28.224900
2773 13:59:28.225005 Set Vref, RX VrefLevel [Byte0]: 59
2774 13:59:28.227757 [Byte1]: 59
2775 13:59:28.232220
2776 13:59:28.232370 Set Vref, RX VrefLevel [Byte0]: 60
2777 13:59:28.235568 [Byte1]: 60
2778 13:59:28.240646
2779 13:59:28.240749 Set Vref, RX VrefLevel [Byte0]: 61
2780 13:59:28.243368 [Byte1]: 61
2781 13:59:28.248807
2782 13:59:28.248900 Set Vref, RX VrefLevel [Byte0]: 62
2783 13:59:28.251319 [Byte1]: 62
2784 13:59:28.256046
2785 13:59:28.256142 Set Vref, RX VrefLevel [Byte0]: 63
2786 13:59:28.259440 [Byte1]: 63
2787 13:59:28.263872
2788 13:59:28.263948 Set Vref, RX VrefLevel [Byte0]: 64
2789 13:59:28.267242 [Byte1]: 64
2790 13:59:28.271713
2791 13:59:28.271783 Set Vref, RX VrefLevel [Byte0]: 65
2792 13:59:28.275477 [Byte1]: 65
2793 13:59:28.279697
2794 13:59:28.279768 Set Vref, RX VrefLevel [Byte0]: 66
2795 13:59:28.283163 [Byte1]: 66
2796 13:59:28.287540
2797 13:59:28.287638 Set Vref, RX VrefLevel [Byte0]: 67
2798 13:59:28.291049 [Byte1]: 67
2799 13:59:28.295409
2800 13:59:28.295480 Set Vref, RX VrefLevel [Byte0]: 68
2801 13:59:28.298949 [Byte1]: 68
2802 13:59:28.303368
2803 13:59:28.303463 Final RX Vref Byte 0 = 56 to rank0
2804 13:59:28.306738 Final RX Vref Byte 1 = 48 to rank0
2805 13:59:28.309933 Final RX Vref Byte 0 = 56 to rank1
2806 13:59:28.313270 Final RX Vref Byte 1 = 48 to rank1==
2807 13:59:28.317173 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 13:59:28.323185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 13:59:28.323282 ==
2810 13:59:28.323373 DQS Delay:
2811 13:59:28.323459 DQS0 = 0, DQS1 = 0
2812 13:59:28.326538 DQM Delay:
2813 13:59:28.326608 DQM0 = 121, DQM1 = 112
2814 13:59:28.329840 DQ Delay:
2815 13:59:28.333075 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =120
2816 13:59:28.336793 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2817 13:59:28.340295 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2818 13:59:28.343447 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2819 13:59:28.343551
2820 13:59:28.343657
2821 13:59:28.353300 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2822 13:59:28.353379 CH0 RK0: MR19=404, MR18=120B
2823 13:59:28.360093 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2824 13:59:28.360191
2825 13:59:28.363098 ----->DramcWriteLeveling(PI) begin...
2826 13:59:28.363203 ==
2827 13:59:28.366428 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 13:59:28.373500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 13:59:28.373598 ==
2830 13:59:28.376787 Write leveling (Byte 0): 32 => 32
2831 13:59:28.376857 Write leveling (Byte 1): 28 => 28
2832 13:59:28.380014 DramcWriteLeveling(PI) end<-----
2833 13:59:28.380106
2834 13:59:28.380195 ==
2835 13:59:28.383368 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 13:59:28.390099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 13:59:28.390178 ==
2838 13:59:28.390239 [Gating] SW mode calibration
2839 13:59:28.399748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 13:59:28.403364 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 13:59:28.409816 0 15 0 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
2842 13:59:28.413426 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 13:59:28.416851 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 13:59:28.419842 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 13:59:28.426806 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 13:59:28.429986 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 13:59:28.433165 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2848 13:59:28.440327 0 15 28 | B1->B0 | 3232 3131 | 0 0 | (0 1) (0 1)
2849 13:59:28.443602 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
2850 13:59:28.446886 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 13:59:28.453146 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 13:59:28.456541 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 13:59:28.460120 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 13:59:28.466591 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 13:59:28.470077 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 13:59:28.473449 1 0 28 | B1->B0 | 3c3c 3d3d | 0 0 | (0 0) (1 1)
2857 13:59:28.480263 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 13:59:28.483429 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 13:59:28.486815 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 13:59:28.493406 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 13:59:28.496722 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 13:59:28.500280 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 13:59:28.503235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 13:59:28.510154 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2865 13:59:28.513588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:59:28.516757 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:59:28.523650 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:59:28.526615 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 13:59:28.529958 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 13:59:28.536611 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 13:59:28.539951 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 13:59:28.543152 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 13:59:28.550279 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 13:59:28.553472 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 13:59:28.556551 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 13:59:28.563583 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 13:59:28.566619 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 13:59:28.570299 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 13:59:28.577147 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 13:59:28.580150 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2881 13:59:28.583454 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 13:59:28.587101 Total UI for P1: 0, mck2ui 16
2883 13:59:28.590838 best dqsien dly found for B0: ( 1, 3, 28)
2884 13:59:28.594189 Total UI for P1: 0, mck2ui 16
2885 13:59:28.597578 best dqsien dly found for B1: ( 1, 3, 28)
2886 13:59:28.600596 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2887 13:59:28.603882 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2888 13:59:28.603960
2889 13:59:28.607255 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2890 13:59:28.610545 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2891 13:59:28.613748 [Gating] SW calibration Done
2892 13:59:28.613827 ==
2893 13:59:28.617346 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 13:59:28.620181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 13:59:28.623602 ==
2896 13:59:28.623683 RX Vref Scan: 0
2897 13:59:28.623746
2898 13:59:28.627102 RX Vref 0 -> 0, step: 1
2899 13:59:28.627181
2900 13:59:28.630322 RX Delay -40 -> 252, step: 8
2901 13:59:28.633380 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2902 13:59:28.636942 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2903 13:59:28.640650 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2904 13:59:28.643832 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2905 13:59:28.650367 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2906 13:59:28.653851 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2907 13:59:28.657075 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2908 13:59:28.660202 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2909 13:59:28.663948 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2910 13:59:28.670433 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2911 13:59:28.674202 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2912 13:59:28.677450 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2913 13:59:28.680866 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2914 13:59:28.683952 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2915 13:59:28.690584 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2916 13:59:28.694228 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2917 13:59:28.694325 ==
2918 13:59:28.697114 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 13:59:28.700292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 13:59:28.700402 ==
2921 13:59:28.700463 DQS Delay:
2922 13:59:28.704188 DQS0 = 0, DQS1 = 0
2923 13:59:28.704268 DQM Delay:
2924 13:59:28.707448 DQM0 = 122, DQM1 = 112
2925 13:59:28.707523 DQ Delay:
2926 13:59:28.710755 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2927 13:59:28.713893 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2928 13:59:28.717072 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2929 13:59:28.720453 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2930 13:59:28.723684
2931 13:59:28.723779
2932 13:59:28.723876 ==
2933 13:59:28.727510 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 13:59:28.730912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 13:59:28.731015 ==
2936 13:59:28.731106
2937 13:59:28.731197
2938 13:59:28.733841 TX Vref Scan disable
2939 13:59:28.733943 == TX Byte 0 ==
2940 13:59:28.740908 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2941 13:59:28.743765 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2942 13:59:28.743845 == TX Byte 1 ==
2943 13:59:28.750585 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2944 13:59:28.754414 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2945 13:59:28.754495 ==
2946 13:59:28.757130 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 13:59:28.760494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 13:59:28.760575 ==
2949 13:59:28.773446 TX Vref=22, minBit 3, minWin=24, winSum=414
2950 13:59:28.776666 TX Vref=24, minBit 3, minWin=25, winSum=418
2951 13:59:28.780231 TX Vref=26, minBit 3, minWin=25, winSum=421
2952 13:59:28.783521 TX Vref=28, minBit 1, minWin=26, winSum=431
2953 13:59:28.786642 TX Vref=30, minBit 3, minWin=25, winSum=431
2954 13:59:28.789773 TX Vref=32, minBit 0, minWin=26, winSum=431
2955 13:59:28.796673 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
2956 13:59:28.796758
2957 13:59:28.800277 Final TX Range 1 Vref 28
2958 13:59:28.800397
2959 13:59:28.800491 ==
2960 13:59:28.803431 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 13:59:28.806599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 13:59:28.806700 ==
2963 13:59:28.806800
2964 13:59:28.806887
2965 13:59:28.809991 TX Vref Scan disable
2966 13:59:28.813736 == TX Byte 0 ==
2967 13:59:28.816576 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2968 13:59:28.820586 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2969 13:59:28.823851 == TX Byte 1 ==
2970 13:59:28.827192 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2971 13:59:28.830441 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2972 13:59:28.830545
2973 13:59:28.833728 [DATLAT]
2974 13:59:28.833821 Freq=1200, CH0 RK1
2975 13:59:28.833908
2976 13:59:28.836908 DATLAT Default: 0xd
2977 13:59:28.836981 0, 0xFFFF, sum = 0
2978 13:59:28.840526 1, 0xFFFF, sum = 0
2979 13:59:28.840612 2, 0xFFFF, sum = 0
2980 13:59:28.843536 3, 0xFFFF, sum = 0
2981 13:59:28.843670 4, 0xFFFF, sum = 0
2982 13:59:28.846576 5, 0xFFFF, sum = 0
2983 13:59:28.846658 6, 0xFFFF, sum = 0
2984 13:59:28.850230 7, 0xFFFF, sum = 0
2985 13:59:28.850312 8, 0xFFFF, sum = 0
2986 13:59:28.853630 9, 0xFFFF, sum = 0
2987 13:59:28.853712 10, 0xFFFF, sum = 0
2988 13:59:28.856492 11, 0xFFFF, sum = 0
2989 13:59:28.856574 12, 0x0, sum = 1
2990 13:59:28.860325 13, 0x0, sum = 2
2991 13:59:28.860422 14, 0x0, sum = 3
2992 13:59:28.863449 15, 0x0, sum = 4
2993 13:59:28.863530 best_step = 13
2994 13:59:28.863610
2995 13:59:28.863717 ==
2996 13:59:28.866944 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 13:59:28.873550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 13:59:28.873642 ==
2999 13:59:28.873707 RX Vref Scan: 0
3000 13:59:28.873766
3001 13:59:28.876476 RX Vref 0 -> 0, step: 1
3002 13:59:28.876556
3003 13:59:28.880106 RX Delay -13 -> 252, step: 4
3004 13:59:28.883388 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3005 13:59:28.886391 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3006 13:59:28.893214 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3007 13:59:28.897023 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3008 13:59:28.900094 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3009 13:59:28.903261 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3010 13:59:28.906411 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3011 13:59:28.913758 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3012 13:59:28.916979 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3013 13:59:28.920123 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3014 13:59:28.923565 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3015 13:59:28.926758 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3016 13:59:28.933183 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3017 13:59:28.936669 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3018 13:59:28.939844 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3019 13:59:28.943606 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3020 13:59:28.943687 ==
3021 13:59:28.946666 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 13:59:28.953513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 13:59:28.953595 ==
3024 13:59:28.953659 DQS Delay:
3025 13:59:28.953717 DQS0 = 0, DQS1 = 0
3026 13:59:28.956592 DQM Delay:
3027 13:59:28.956672 DQM0 = 121, DQM1 = 110
3028 13:59:28.959845 DQ Delay:
3029 13:59:28.963633 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3030 13:59:28.966597 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3031 13:59:28.969865 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =100
3032 13:59:28.973431 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3033 13:59:28.973516
3034 13:59:28.973605
3035 13:59:28.979810 [DQSOSCAuto] RK1, (LSB)MR18= 0xbec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 405 ps
3036 13:59:28.983578 CH0 RK1: MR19=403, MR18=BEC
3037 13:59:28.990270 CH0_RK1: MR19=0x403, MR18=0xBEC, DQSOSC=405, MR23=63, INC=39, DEC=26
3038 13:59:28.993372 [RxdqsGatingPostProcess] freq 1200
3039 13:59:29.000170 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3040 13:59:29.003643 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 13:59:29.003715 best DQS1 dly(2T, 0.5T) = (0, 12)
3042 13:59:29.006789 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 13:59:29.010292 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3044 13:59:29.013463 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 13:59:29.016759 best DQS1 dly(2T, 0.5T) = (0, 11)
3046 13:59:29.019852 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 13:59:29.023723 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3048 13:59:29.026993 Pre-setting of DQS Precalculation
3049 13:59:29.033533 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3050 13:59:29.033621 ==
3051 13:59:29.036861 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 13:59:29.040057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 13:59:29.040154 ==
3054 13:59:29.043402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3055 13:59:29.050458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3056 13:59:29.059601 [CA 0] Center 37 (7~68) winsize 62
3057 13:59:29.062826 [CA 1] Center 37 (7~68) winsize 62
3058 13:59:29.066038 [CA 2] Center 35 (5~65) winsize 61
3059 13:59:29.069112 [CA 3] Center 34 (4~64) winsize 61
3060 13:59:29.072992 [CA 4] Center 34 (4~64) winsize 61
3061 13:59:29.076177 [CA 5] Center 33 (3~63) winsize 61
3062 13:59:29.076325
3063 13:59:29.079444 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3064 13:59:29.079525
3065 13:59:29.082603 [CATrainingPosCal] consider 1 rank data
3066 13:59:29.086195 u2DelayCellTimex100 = 270/100 ps
3067 13:59:29.089637 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3068 13:59:29.092950 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3069 13:59:29.099537 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3070 13:59:29.103126 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3071 13:59:29.106034 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3072 13:59:29.109686 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3073 13:59:29.109767
3074 13:59:29.112777 CA PerBit enable=1, Macro0, CA PI delay=33
3075 13:59:29.112858
3076 13:59:29.116572 [CBTSetCACLKResult] CA Dly = 33
3077 13:59:29.116653 CS Dly: 7 (0~38)
3078 13:59:29.116717 ==
3079 13:59:29.119551 Dram Type= 6, Freq= 0, CH_1, rank 1
3080 13:59:29.126307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 13:59:29.126391 ==
3082 13:59:29.129782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 13:59:29.136102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3084 13:59:29.145154 [CA 0] Center 37 (7~68) winsize 62
3085 13:59:29.148417 [CA 1] Center 37 (7~68) winsize 62
3086 13:59:29.151802 [CA 2] Center 35 (5~65) winsize 61
3087 13:59:29.154957 [CA 3] Center 34 (4~65) winsize 62
3088 13:59:29.158459 [CA 4] Center 34 (4~65) winsize 62
3089 13:59:29.162179 [CA 5] Center 34 (4~64) winsize 61
3090 13:59:29.162260
3091 13:59:29.165215 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3092 13:59:29.165297
3093 13:59:29.168511 [CATrainingPosCal] consider 2 rank data
3094 13:59:29.171707 u2DelayCellTimex100 = 270/100 ps
3095 13:59:29.174891 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3096 13:59:29.178689 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 13:59:29.185317 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3098 13:59:29.188537 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3099 13:59:29.191702 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 13:59:29.195120 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3101 13:59:29.195201
3102 13:59:29.198696 CA PerBit enable=1, Macro0, CA PI delay=33
3103 13:59:29.198777
3104 13:59:29.201625 [CBTSetCACLKResult] CA Dly = 33
3105 13:59:29.201706 CS Dly: 8 (0~41)
3106 13:59:29.201770
3107 13:59:29.204884 ----->DramcWriteLeveling(PI) begin...
3108 13:59:29.204966 ==
3109 13:59:29.208612 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 13:59:29.215500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 13:59:29.215582 ==
3112 13:59:29.218691 Write leveling (Byte 0): 26 => 26
3113 13:59:29.221882 Write leveling (Byte 1): 27 => 27
3114 13:59:29.221963 DramcWriteLeveling(PI) end<-----
3115 13:59:29.224818
3116 13:59:29.224899 ==
3117 13:59:29.228547 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 13:59:29.232018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 13:59:29.232125 ==
3120 13:59:29.234881 [Gating] SW mode calibration
3121 13:59:29.241679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3122 13:59:29.244968 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3123 13:59:29.251712 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 13:59:29.254946 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 13:59:29.258248 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 13:59:29.265102 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 13:59:29.268676 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 13:59:29.271590 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 13:59:29.278066 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (0 0) (0 1)
3130 13:59:29.281974 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3131 13:59:29.285270 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 13:59:29.291849 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 13:59:29.295184 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 13:59:29.298546 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 13:59:29.305146 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 13:59:29.308569 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3137 13:59:29.311589 1 0 24 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (1 1)
3138 13:59:29.318274 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 13:59:29.321467 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 13:59:29.325120 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 13:59:29.328497 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 13:59:29.334969 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 13:59:29.338687 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 13:59:29.341784 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 13:59:29.348209 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 13:59:29.351483 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3147 13:59:29.355073 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:59:29.362000 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:59:29.364823 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:59:29.368181 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:59:29.375326 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 13:59:29.378435 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 13:59:29.381560 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 13:59:29.388687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 13:59:29.392077 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 13:59:29.395339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 13:59:29.398665 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 13:59:29.405179 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 13:59:29.408591 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 13:59:29.411856 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 13:59:29.418561 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3162 13:59:29.422095 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3163 13:59:29.425244 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 13:59:29.428725 Total UI for P1: 0, mck2ui 16
3165 13:59:29.432157 best dqsien dly found for B0: ( 1, 3, 26)
3166 13:59:29.435858 Total UI for P1: 0, mck2ui 16
3167 13:59:29.438838 best dqsien dly found for B1: ( 1, 3, 26)
3168 13:59:29.442240 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3169 13:59:29.445647 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3170 13:59:29.445721
3171 13:59:29.452044 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3172 13:59:29.455130 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3173 13:59:29.455209 [Gating] SW calibration Done
3174 13:59:29.458506 ==
3175 13:59:29.462403 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 13:59:29.465405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 13:59:29.465475 ==
3178 13:59:29.465539 RX Vref Scan: 0
3179 13:59:29.465599
3180 13:59:29.468947 RX Vref 0 -> 0, step: 1
3181 13:59:29.469020
3182 13:59:29.472049 RX Delay -40 -> 252, step: 8
3183 13:59:29.475242 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3184 13:59:29.479045 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3185 13:59:29.482187 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3186 13:59:29.488848 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3187 13:59:29.492118 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3188 13:59:29.495427 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3189 13:59:29.498881 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3190 13:59:29.502124 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3191 13:59:29.508763 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3192 13:59:29.512025 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3193 13:59:29.515404 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3194 13:59:29.518752 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3195 13:59:29.522005 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3196 13:59:29.528967 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3197 13:59:29.532213 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3198 13:59:29.535390 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3199 13:59:29.535461 ==
3200 13:59:29.538882 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 13:59:29.541931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 13:59:29.542004 ==
3203 13:59:29.545726 DQS Delay:
3204 13:59:29.545792 DQS0 = 0, DQS1 = 0
3205 13:59:29.548795 DQM Delay:
3206 13:59:29.548862 DQM0 = 120, DQM1 = 116
3207 13:59:29.548922 DQ Delay:
3208 13:59:29.555575 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3209 13:59:29.558805 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3210 13:59:29.562166 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3211 13:59:29.565290 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3212 13:59:29.565369
3213 13:59:29.565431
3214 13:59:29.565488 ==
3215 13:59:29.568482 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 13:59:29.572118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 13:59:29.572216 ==
3218 13:59:29.572310
3219 13:59:29.572411
3220 13:59:29.575635 TX Vref Scan disable
3221 13:59:29.578857 == TX Byte 0 ==
3222 13:59:29.582298 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3223 13:59:29.585480 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3224 13:59:29.588809 == TX Byte 1 ==
3225 13:59:29.592565 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3226 13:59:29.595575 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3227 13:59:29.595645 ==
3228 13:59:29.599088 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 13:59:29.602405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 13:59:29.602476 ==
3231 13:59:29.615253 TX Vref=22, minBit 1, minWin=25, winSum=413
3232 13:59:29.618437 TX Vref=24, minBit 9, minWin=25, winSum=418
3233 13:59:29.621606 TX Vref=26, minBit 9, minWin=25, winSum=420
3234 13:59:29.625012 TX Vref=28, minBit 9, minWin=25, winSum=425
3235 13:59:29.628270 TX Vref=30, minBit 9, minWin=25, winSum=432
3236 13:59:29.632261 TX Vref=32, minBit 2, minWin=26, winSum=428
3237 13:59:29.638770 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 32
3238 13:59:29.638936
3239 13:59:29.641994 Final TX Range 1 Vref 32
3240 13:59:29.642168
3241 13:59:29.642329 ==
3242 13:59:29.645184 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 13:59:29.648973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 13:59:29.649165 ==
3245 13:59:29.649381
3246 13:59:29.652067
3247 13:59:29.652238 TX Vref Scan disable
3248 13:59:29.655815 == TX Byte 0 ==
3249 13:59:29.658925 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3250 13:59:29.661786 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3251 13:59:29.665497 == TX Byte 1 ==
3252 13:59:29.669034 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3253 13:59:29.672190 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3254 13:59:29.672385
3255 13:59:29.675194 [DATLAT]
3256 13:59:29.675453 Freq=1200, CH1 RK0
3257 13:59:29.675693
3258 13:59:29.678612 DATLAT Default: 0xd
3259 13:59:29.678831 0, 0xFFFF, sum = 0
3260 13:59:29.681974 1, 0xFFFF, sum = 0
3261 13:59:29.682201 2, 0xFFFF, sum = 0
3262 13:59:29.685539 3, 0xFFFF, sum = 0
3263 13:59:29.685713 4, 0xFFFF, sum = 0
3264 13:59:29.688824 5, 0xFFFF, sum = 0
3265 13:59:29.688998 6, 0xFFFF, sum = 0
3266 13:59:29.692252 7, 0xFFFF, sum = 0
3267 13:59:29.692445 8, 0xFFFF, sum = 0
3268 13:59:29.695802 9, 0xFFFF, sum = 0
3269 13:59:29.698879 10, 0xFFFF, sum = 0
3270 13:59:29.699125 11, 0xFFFF, sum = 0
3271 13:59:29.702139 12, 0x0, sum = 1
3272 13:59:29.702360 13, 0x0, sum = 2
3273 13:59:29.702511 14, 0x0, sum = 3
3274 13:59:29.705510 15, 0x0, sum = 4
3275 13:59:29.705795 best_step = 13
3276 13:59:29.705965
3277 13:59:29.708652 ==
3278 13:59:29.708912 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 13:59:29.716094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 13:59:29.716520 ==
3281 13:59:29.716775 RX Vref Scan: 1
3282 13:59:29.716998
3283 13:59:29.719319 Set Vref Range= 32 -> 127
3284 13:59:29.719703
3285 13:59:29.722351 RX Vref 32 -> 127, step: 1
3286 13:59:29.722731
3287 13:59:29.725999 RX Delay -5 -> 252, step: 4
3288 13:59:29.726526
3289 13:59:29.728992 Set Vref, RX VrefLevel [Byte0]: 32
3290 13:59:29.732465 [Byte1]: 32
3291 13:59:29.733070
3292 13:59:29.735657 Set Vref, RX VrefLevel [Byte0]: 33
3293 13:59:29.738991 [Byte1]: 33
3294 13:59:29.739519
3295 13:59:29.742143 Set Vref, RX VrefLevel [Byte0]: 34
3296 13:59:29.746040 [Byte1]: 34
3297 13:59:29.749827
3298 13:59:29.750285 Set Vref, RX VrefLevel [Byte0]: 35
3299 13:59:29.752405 [Byte1]: 35
3300 13:59:29.757189
3301 13:59:29.757599 Set Vref, RX VrefLevel [Byte0]: 36
3302 13:59:29.760538 [Byte1]: 36
3303 13:59:29.764825
3304 13:59:29.765233 Set Vref, RX VrefLevel [Byte0]: 37
3305 13:59:29.768143 [Byte1]: 37
3306 13:59:29.773639
3307 13:59:29.774144 Set Vref, RX VrefLevel [Byte0]: 38
3308 13:59:29.776400 [Byte1]: 38
3309 13:59:29.780901
3310 13:59:29.781319 Set Vref, RX VrefLevel [Byte0]: 39
3311 13:59:29.784040 [Byte1]: 39
3312 13:59:29.788924
3313 13:59:29.789616 Set Vref, RX VrefLevel [Byte0]: 40
3314 13:59:29.792272 [Byte1]: 40
3315 13:59:29.796440
3316 13:59:29.796858 Set Vref, RX VrefLevel [Byte0]: 41
3317 13:59:29.800191 [Byte1]: 41
3318 13:59:29.804082
3319 13:59:29.804585 Set Vref, RX VrefLevel [Byte0]: 42
3320 13:59:29.808017 [Byte1]: 42
3321 13:59:29.812645
3322 13:59:29.813054 Set Vref, RX VrefLevel [Byte0]: 43
3323 13:59:29.816144 [Byte1]: 43
3324 13:59:29.820685
3325 13:59:29.821190 Set Vref, RX VrefLevel [Byte0]: 44
3326 13:59:29.823438 [Byte1]: 44
3327 13:59:29.828076
3328 13:59:29.828535 Set Vref, RX VrefLevel [Byte0]: 45
3329 13:59:29.831595 [Byte1]: 45
3330 13:59:29.836007
3331 13:59:29.836464 Set Vref, RX VrefLevel [Byte0]: 46
3332 13:59:29.839284 [Byte1]: 46
3333 13:59:29.843735
3334 13:59:29.844240 Set Vref, RX VrefLevel [Byte0]: 47
3335 13:59:29.846824 [Byte1]: 47
3336 13:59:29.851906
3337 13:59:29.852372 Set Vref, RX VrefLevel [Byte0]: 48
3338 13:59:29.855307 [Byte1]: 48
3339 13:59:29.859864
3340 13:59:29.860417 Set Vref, RX VrefLevel [Byte0]: 49
3341 13:59:29.862920 [Byte1]: 49
3342 13:59:29.867309
3343 13:59:29.867814 Set Vref, RX VrefLevel [Byte0]: 50
3344 13:59:29.870528 [Byte1]: 50
3345 13:59:29.875632
3346 13:59:29.876144 Set Vref, RX VrefLevel [Byte0]: 51
3347 13:59:29.878578 [Byte1]: 51
3348 13:59:29.883003
3349 13:59:29.883453 Set Vref, RX VrefLevel [Byte0]: 52
3350 13:59:29.886363 [Byte1]: 52
3351 13:59:29.891246
3352 13:59:29.891798 Set Vref, RX VrefLevel [Byte0]: 53
3353 13:59:29.894231 [Byte1]: 53
3354 13:59:29.898843
3355 13:59:29.899393 Set Vref, RX VrefLevel [Byte0]: 54
3356 13:59:29.901975 [Byte1]: 54
3357 13:59:29.906471
3358 13:59:29.907025 Set Vref, RX VrefLevel [Byte0]: 55
3359 13:59:29.910169 [Byte1]: 55
3360 13:59:29.914378
3361 13:59:29.914932 Set Vref, RX VrefLevel [Byte0]: 56
3362 13:59:29.918187 [Byte1]: 56
3363 13:59:29.922492
3364 13:59:29.922947 Set Vref, RX VrefLevel [Byte0]: 57
3365 13:59:29.925707 [Byte1]: 57
3366 13:59:29.930032
3367 13:59:29.930487 Set Vref, RX VrefLevel [Byte0]: 58
3368 13:59:29.933683 [Byte1]: 58
3369 13:59:29.937827
3370 13:59:29.938296 Set Vref, RX VrefLevel [Byte0]: 59
3371 13:59:29.941518 [Byte1]: 59
3372 13:59:29.945590
3373 13:59:29.946001 Set Vref, RX VrefLevel [Byte0]: 60
3374 13:59:29.948770 [Byte1]: 60
3375 13:59:29.953876
3376 13:59:29.954431 Set Vref, RX VrefLevel [Byte0]: 61
3377 13:59:29.957207 [Byte1]: 61
3378 13:59:29.961487
3379 13:59:29.961941 Set Vref, RX VrefLevel [Byte0]: 62
3380 13:59:29.964470 [Byte1]: 62
3381 13:59:29.969540
3382 13:59:29.969992 Set Vref, RX VrefLevel [Byte0]: 63
3383 13:59:29.972820 [Byte1]: 63
3384 13:59:29.977305
3385 13:59:29.977822 Set Vref, RX VrefLevel [Byte0]: 64
3386 13:59:29.980856 [Byte1]: 64
3387 13:59:29.984808
3388 13:59:29.985262 Set Vref, RX VrefLevel [Byte0]: 65
3389 13:59:29.988526 [Byte1]: 65
3390 13:59:29.992894
3391 13:59:29.993445 Set Vref, RX VrefLevel [Byte0]: 66
3392 13:59:29.996126 [Byte1]: 66
3393 13:59:30.001262
3394 13:59:30.001819 Set Vref, RX VrefLevel [Byte0]: 67
3395 13:59:30.004381 [Byte1]: 67
3396 13:59:30.009324
3397 13:59:30.009873 Final RX Vref Byte 0 = 56 to rank0
3398 13:59:30.012376 Final RX Vref Byte 1 = 48 to rank0
3399 13:59:30.015854 Final RX Vref Byte 0 = 56 to rank1
3400 13:59:30.018926 Final RX Vref Byte 1 = 48 to rank1==
3401 13:59:30.022248 Dram Type= 6, Freq= 0, CH_1, rank 0
3402 13:59:30.028457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3403 13:59:30.028918 ==
3404 13:59:30.029277 DQS Delay:
3405 13:59:30.029608 DQS0 = 0, DQS1 = 0
3406 13:59:30.031980 DQM Delay:
3407 13:59:30.032623 DQM0 = 120, DQM1 = 116
3408 13:59:30.035497 DQ Delay:
3409 13:59:30.038618 DQ0 =124, DQ1 =114, DQ2 =112, DQ3 =118
3410 13:59:30.041965 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3411 13:59:30.045490 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3412 13:59:30.048976 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3413 13:59:30.049438
3414 13:59:30.049798
3415 13:59:30.055707 [DQSOSCAuto] RK0, (LSB)MR18= 0x315, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3416 13:59:30.058984 CH1 RK0: MR19=404, MR18=315
3417 13:59:30.065637 CH1_RK0: MR19=0x404, MR18=0x315, DQSOSC=401, MR23=63, INC=40, DEC=27
3418 13:59:30.066190
3419 13:59:30.068573 ----->DramcWriteLeveling(PI) begin...
3420 13:59:30.069041 ==
3421 13:59:30.072025 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 13:59:30.075332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 13:59:30.075795 ==
3424 13:59:30.078995 Write leveling (Byte 0): 26 => 26
3425 13:59:30.082233 Write leveling (Byte 1): 28 => 28
3426 13:59:30.085390 DramcWriteLeveling(PI) end<-----
3427 13:59:30.085849
3428 13:59:30.086207 ==
3429 13:59:30.089054 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 13:59:30.092121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 13:59:30.095748 ==
3432 13:59:30.096348 [Gating] SW mode calibration
3433 13:59:30.105217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3434 13:59:30.108678 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3435 13:59:30.112202 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 13:59:30.118737 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 13:59:30.122661 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 13:59:30.125051 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 13:59:30.132396 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 13:59:30.135395 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3441 13:59:30.138642 0 15 24 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 1)
3442 13:59:30.145596 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3443 13:59:30.148558 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 13:59:30.152179 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 13:59:30.159040 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 13:59:30.162332 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 13:59:30.165776 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 13:59:30.171935 1 0 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
3449 13:59:30.176105 1 0 24 | B1->B0 | 4444 3131 | 1 0 | (0 0) (0 0)
3450 13:59:30.178645 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3451 13:59:30.182369 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 13:59:30.188680 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 13:59:30.192276 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 13:59:30.195486 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 13:59:30.202060 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 13:59:30.205572 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3457 13:59:30.208807 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3458 13:59:30.215626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3459 13:59:30.218999 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 13:59:30.222277 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 13:59:30.229078 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 13:59:30.232380 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 13:59:30.235592 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 13:59:30.242675 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 13:59:30.245575 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 13:59:30.248995 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 13:59:30.255556 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 13:59:30.258958 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 13:59:30.261899 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 13:59:30.269026 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 13:59:30.271906 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 13:59:30.275332 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3473 13:59:30.282334 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3474 13:59:30.285217 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3475 13:59:30.288585 Total UI for P1: 0, mck2ui 16
3476 13:59:30.291940 best dqsien dly found for B1: ( 1, 3, 22)
3477 13:59:30.294981 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 13:59:30.298382 Total UI for P1: 0, mck2ui 16
3479 13:59:30.301881 best dqsien dly found for B0: ( 1, 3, 26)
3480 13:59:30.304817 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3481 13:59:30.308489 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3482 13:59:30.308907
3483 13:59:30.311619 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3484 13:59:30.318594 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3485 13:59:30.319124 [Gating] SW calibration Done
3486 13:59:30.319457 ==
3487 13:59:30.321737 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 13:59:30.328449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 13:59:30.328997 ==
3490 13:59:30.329343 RX Vref Scan: 0
3491 13:59:30.329655
3492 13:59:30.331501 RX Vref 0 -> 0, step: 1
3493 13:59:30.331919
3494 13:59:30.334982 RX Delay -40 -> 252, step: 8
3495 13:59:30.338009 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3496 13:59:30.341396 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3497 13:59:30.344986 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3498 13:59:30.351419 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3499 13:59:30.354725 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3500 13:59:30.358562 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3501 13:59:30.361323 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3502 13:59:30.364263 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3503 13:59:30.371120 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3504 13:59:30.375029 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3505 13:59:30.377970 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3506 13:59:30.381172 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3507 13:59:30.384198 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3508 13:59:30.390955 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3509 13:59:30.394194 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3510 13:59:30.397631 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3511 13:59:30.398142 ==
3512 13:59:30.400651 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 13:59:30.403908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 13:59:30.407490 ==
3515 13:59:30.407995 DQS Delay:
3516 13:59:30.408377 DQS0 = 0, DQS1 = 0
3517 13:59:30.411361 DQM Delay:
3518 13:59:30.411868 DQM0 = 120, DQM1 = 118
3519 13:59:30.414249 DQ Delay:
3520 13:59:30.418006 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3521 13:59:30.420621 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3522 13:59:30.424263 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3523 13:59:30.427187 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3524 13:59:30.427610
3525 13:59:30.427938
3526 13:59:30.428245 ==
3527 13:59:30.430625 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 13:59:30.434128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 13:59:30.434549 ==
3530 13:59:30.437528
3531 13:59:30.438033
3532 13:59:30.438361 TX Vref Scan disable
3533 13:59:30.440496 == TX Byte 0 ==
3534 13:59:30.443785 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3535 13:59:30.447150 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3536 13:59:30.450505 == TX Byte 1 ==
3537 13:59:30.453791 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3538 13:59:30.457041 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3539 13:59:30.457455 ==
3540 13:59:30.460555 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 13:59:30.467662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 13:59:30.468211 ==
3543 13:59:30.478240 TX Vref=22, minBit 7, minWin=25, winSum=421
3544 13:59:30.481222 TX Vref=24, minBit 1, minWin=26, winSum=424
3545 13:59:30.484602 TX Vref=26, minBit 2, minWin=26, winSum=429
3546 13:59:30.487646 TX Vref=28, minBit 2, minWin=26, winSum=435
3547 13:59:30.491689 TX Vref=30, minBit 9, minWin=26, winSum=433
3548 13:59:30.494885 TX Vref=32, minBit 6, minWin=26, winSum=430
3549 13:59:30.501380 [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 28
3550 13:59:30.501932
3551 13:59:30.504644 Final TX Range 1 Vref 28
3552 13:59:30.505198
3553 13:59:30.505559 ==
3554 13:59:30.507535 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 13:59:30.511257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 13:59:30.511814 ==
3557 13:59:30.512180
3558 13:59:30.514481
3559 13:59:30.514933 TX Vref Scan disable
3560 13:59:30.518172 == TX Byte 0 ==
3561 13:59:30.520730 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3562 13:59:30.524126 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3563 13:59:30.527424 == TX Byte 1 ==
3564 13:59:30.531007 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3565 13:59:30.534487 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3566 13:59:30.534945
3567 13:59:30.537577 [DATLAT]
3568 13:59:30.538036 Freq=1200, CH1 RK1
3569 13:59:30.538400
3570 13:59:30.540757 DATLAT Default: 0xd
3571 13:59:30.541219 0, 0xFFFF, sum = 0
3572 13:59:30.544397 1, 0xFFFF, sum = 0
3573 13:59:30.544826 2, 0xFFFF, sum = 0
3574 13:59:30.547512 3, 0xFFFF, sum = 0
3575 13:59:30.547935 4, 0xFFFF, sum = 0
3576 13:59:30.550851 5, 0xFFFF, sum = 0
3577 13:59:30.554129 6, 0xFFFF, sum = 0
3578 13:59:30.554655 7, 0xFFFF, sum = 0
3579 13:59:30.557301 8, 0xFFFF, sum = 0
3580 13:59:30.557784 9, 0xFFFF, sum = 0
3581 13:59:30.560461 10, 0xFFFF, sum = 0
3582 13:59:30.560887 11, 0xFFFF, sum = 0
3583 13:59:30.563926 12, 0x0, sum = 1
3584 13:59:30.564498 13, 0x0, sum = 2
3585 13:59:30.567694 14, 0x0, sum = 3
3586 13:59:30.568114 15, 0x0, sum = 4
3587 13:59:30.568506 best_step = 13
3588 13:59:30.568821
3589 13:59:30.571296 ==
3590 13:59:30.574444 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 13:59:30.577273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 13:59:30.577762 ==
3593 13:59:30.578101 RX Vref Scan: 0
3594 13:59:30.578414
3595 13:59:30.580739 RX Vref 0 -> 0, step: 1
3596 13:59:30.581248
3597 13:59:30.583742 RX Delay -5 -> 252, step: 4
3598 13:59:30.587702 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3599 13:59:30.591069 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3600 13:59:30.597361 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3601 13:59:30.600492 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3602 13:59:30.604030 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3603 13:59:30.606877 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3604 13:59:30.611073 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3605 13:59:30.617835 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3606 13:59:30.621008 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3607 13:59:30.624280 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3608 13:59:30.627186 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3609 13:59:30.630627 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3610 13:59:30.637009 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3611 13:59:30.640620 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3612 13:59:30.644073 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3613 13:59:30.647445 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3614 13:59:30.647906 ==
3615 13:59:30.650615 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 13:59:30.656808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 13:59:30.657231 ==
3618 13:59:30.657562 DQS Delay:
3619 13:59:30.660584 DQS0 = 0, DQS1 = 0
3620 13:59:30.661002 DQM Delay:
3621 13:59:30.663645 DQM0 = 120, DQM1 = 116
3622 13:59:30.664097 DQ Delay:
3623 13:59:30.667313 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3624 13:59:30.670474 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3625 13:59:30.673351 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3626 13:59:30.677204 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =126
3627 13:59:30.677754
3628 13:59:30.678111
3629 13:59:30.686885 [DQSOSCAuto] RK1, (LSB)MR18= 0xfec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3630 13:59:30.687388 CH1 RK1: MR19=403, MR18=FEC
3631 13:59:30.693766 CH1_RK1: MR19=0x403, MR18=0xFEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3632 13:59:30.697171 [RxdqsGatingPostProcess] freq 1200
3633 13:59:30.703544 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3634 13:59:30.706809 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 13:59:30.710216 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 13:59:30.713471 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 13:59:30.717015 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 13:59:30.720243 best DQS0 dly(2T, 0.5T) = (0, 11)
3639 13:59:30.723312 best DQS1 dly(2T, 0.5T) = (0, 11)
3640 13:59:30.726356 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3641 13:59:30.726778 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3642 13:59:30.730160 Pre-setting of DQS Precalculation
3643 13:59:30.736803 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3644 13:59:30.742997 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3645 13:59:30.750106 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3646 13:59:30.750608
3647 13:59:30.751026
3648 13:59:30.753243 [Calibration Summary] 2400 Mbps
3649 13:59:30.756888 CH 0, Rank 0
3650 13:59:30.757305 SW Impedance : PASS
3651 13:59:30.759876 DUTY Scan : NO K
3652 13:59:30.760313 ZQ Calibration : PASS
3653 13:59:30.763681 Jitter Meter : NO K
3654 13:59:30.766695 CBT Training : PASS
3655 13:59:30.767243 Write leveling : PASS
3656 13:59:30.770303 RX DQS gating : PASS
3657 13:59:30.773579 RX DQ/DQS(RDDQC) : PASS
3658 13:59:30.774302 TX DQ/DQS : PASS
3659 13:59:30.776477 RX DATLAT : PASS
3660 13:59:30.780029 RX DQ/DQS(Engine): PASS
3661 13:59:30.780520 TX OE : NO K
3662 13:59:30.783041 All Pass.
3663 13:59:30.783493
3664 13:59:30.783851 CH 0, Rank 1
3665 13:59:30.786598 SW Impedance : PASS
3666 13:59:30.787052 DUTY Scan : NO K
3667 13:59:30.790056 ZQ Calibration : PASS
3668 13:59:30.793098 Jitter Meter : NO K
3669 13:59:30.793509 CBT Training : PASS
3670 13:59:30.796838 Write leveling : PASS
3671 13:59:30.799773 RX DQS gating : PASS
3672 13:59:30.800191 RX DQ/DQS(RDDQC) : PASS
3673 13:59:30.803494 TX DQ/DQS : PASS
3674 13:59:30.806386 RX DATLAT : PASS
3675 13:59:30.806910 RX DQ/DQS(Engine): PASS
3676 13:59:30.810022 TX OE : NO K
3677 13:59:30.810436 All Pass.
3678 13:59:30.810760
3679 13:59:30.813464 CH 1, Rank 0
3680 13:59:30.813976 SW Impedance : PASS
3681 13:59:30.816853 DUTY Scan : NO K
3682 13:59:30.817363 ZQ Calibration : PASS
3683 13:59:30.820163 Jitter Meter : NO K
3684 13:59:30.823436 CBT Training : PASS
3685 13:59:30.823944 Write leveling : PASS
3686 13:59:30.826501 RX DQS gating : PASS
3687 13:59:30.829635 RX DQ/DQS(RDDQC) : PASS
3688 13:59:30.830057 TX DQ/DQS : PASS
3689 13:59:30.833070 RX DATLAT : PASS
3690 13:59:30.836512 RX DQ/DQS(Engine): PASS
3691 13:59:30.837019 TX OE : NO K
3692 13:59:30.839609 All Pass.
3693 13:59:30.840059
3694 13:59:30.840684 CH 1, Rank 1
3695 13:59:30.842671 SW Impedance : PASS
3696 13:59:30.843123 DUTY Scan : NO K
3697 13:59:30.846489 ZQ Calibration : PASS
3698 13:59:30.849917 Jitter Meter : NO K
3699 13:59:30.850594 CBT Training : PASS
3700 13:59:30.852934 Write leveling : PASS
3701 13:59:30.856203 RX DQS gating : PASS
3702 13:59:30.856706 RX DQ/DQS(RDDQC) : PASS
3703 13:59:30.859823 TX DQ/DQS : PASS
3704 13:59:30.860613 RX DATLAT : PASS
3705 13:59:30.862571 RX DQ/DQS(Engine): PASS
3706 13:59:30.866519 TX OE : NO K
3707 13:59:30.867081 All Pass.
3708 13:59:30.867444
3709 13:59:30.869083 DramC Write-DBI off
3710 13:59:30.873278 PER_BANK_REFRESH: Hybrid Mode
3711 13:59:30.873825 TX_TRACKING: ON
3712 13:59:30.882778 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3713 13:59:30.886190 [FAST_K] Save calibration result to emmc
3714 13:59:30.889017 dramc_set_vcore_voltage set vcore to 650000
3715 13:59:30.892502 Read voltage for 600, 5
3716 13:59:30.892999 Vio18 = 0
3717 13:59:30.893324 Vcore = 650000
3718 13:59:30.896544 Vdram = 0
3719 13:59:30.897100 Vddq = 0
3720 13:59:30.897426 Vmddr = 0
3721 13:59:30.902978 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3722 13:59:30.906094 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3723 13:59:30.909303 MEM_TYPE=3, freq_sel=19
3724 13:59:30.913174 sv_algorithm_assistance_LP4_1600
3725 13:59:30.916117 ============ PULL DRAM RESETB DOWN ============
3726 13:59:30.919676 ========== PULL DRAM RESETB DOWN end =========
3727 13:59:30.926058 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3728 13:59:30.929567 ===================================
3729 13:59:30.930096 LPDDR4 DRAM CONFIGURATION
3730 13:59:30.932769 ===================================
3731 13:59:30.936083 EX_ROW_EN[0] = 0x0
3732 13:59:30.939572 EX_ROW_EN[1] = 0x0
3733 13:59:30.940088 LP4Y_EN = 0x0
3734 13:59:30.942899 WORK_FSP = 0x0
3735 13:59:30.943427 WL = 0x2
3736 13:59:30.946019 RL = 0x2
3737 13:59:30.946443 BL = 0x2
3738 13:59:30.949083 RPST = 0x0
3739 13:59:30.949503 RD_PRE = 0x0
3740 13:59:30.952229 WR_PRE = 0x1
3741 13:59:30.952854 WR_PST = 0x0
3742 13:59:30.955527 DBI_WR = 0x0
3743 13:59:30.955948 DBI_RD = 0x0
3744 13:59:30.958929 OTF = 0x1
3745 13:59:30.962669 ===================================
3746 13:59:30.965989 ===================================
3747 13:59:30.966512 ANA top config
3748 13:59:30.969333 ===================================
3749 13:59:30.972184 DLL_ASYNC_EN = 0
3750 13:59:30.975835 ALL_SLAVE_EN = 1
3751 13:59:30.976261 NEW_RANK_MODE = 1
3752 13:59:30.978816 DLL_IDLE_MODE = 1
3753 13:59:30.982700 LP45_APHY_COMB_EN = 1
3754 13:59:30.986008 TX_ODT_DIS = 1
3755 13:59:30.989011 NEW_8X_MODE = 1
3756 13:59:30.992643 ===================================
3757 13:59:30.996244 ===================================
3758 13:59:30.996820 data_rate = 1200
3759 13:59:30.998711 CKR = 1
3760 13:59:31.002694 DQ_P2S_RATIO = 8
3761 13:59:31.005303 ===================================
3762 13:59:31.009175 CA_P2S_RATIO = 8
3763 13:59:31.012207 DQ_CA_OPEN = 0
3764 13:59:31.015755 DQ_SEMI_OPEN = 0
3765 13:59:31.016279 CA_SEMI_OPEN = 0
3766 13:59:31.018934 CA_FULL_RATE = 0
3767 13:59:31.021933 DQ_CKDIV4_EN = 1
3768 13:59:31.025634 CA_CKDIV4_EN = 1
3769 13:59:31.028811 CA_PREDIV_EN = 0
3770 13:59:31.032317 PH8_DLY = 0
3771 13:59:31.032793 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3772 13:59:31.035342 DQ_AAMCK_DIV = 4
3773 13:59:31.038469 CA_AAMCK_DIV = 4
3774 13:59:31.042006 CA_ADMCK_DIV = 4
3775 13:59:31.045575 DQ_TRACK_CA_EN = 0
3776 13:59:31.048575 CA_PICK = 600
3777 13:59:31.052486 CA_MCKIO = 600
3778 13:59:31.052998 MCKIO_SEMI = 0
3779 13:59:31.055443 PLL_FREQ = 2288
3780 13:59:31.058949 DQ_UI_PI_RATIO = 32
3781 13:59:31.062004 CA_UI_PI_RATIO = 0
3782 13:59:31.065295 ===================================
3783 13:59:31.068615 ===================================
3784 13:59:31.071628 memory_type:LPDDR4
3785 13:59:31.072041 GP_NUM : 10
3786 13:59:31.075532 SRAM_EN : 1
3787 13:59:31.076084 MD32_EN : 0
3788 13:59:31.078357 ===================================
3789 13:59:31.082021 [ANA_INIT] >>>>>>>>>>>>>>
3790 13:59:31.085571 <<<<<< [CONFIGURE PHASE]: ANA_TX
3791 13:59:31.088365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3792 13:59:31.092128 ===================================
3793 13:59:31.095501 data_rate = 1200,PCW = 0X5800
3794 13:59:31.098592 ===================================
3795 13:59:31.101855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3796 13:59:31.108642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 13:59:31.112359 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 13:59:31.118385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3799 13:59:31.121762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3800 13:59:31.125610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3801 13:59:31.126182 [ANA_INIT] flow start
3802 13:59:31.128818 [ANA_INIT] PLL >>>>>>>>
3803 13:59:31.132098 [ANA_INIT] PLL <<<<<<<<
3804 13:59:31.132695 [ANA_INIT] MIDPI >>>>>>>>
3805 13:59:31.135485 [ANA_INIT] MIDPI <<<<<<<<
3806 13:59:31.138420 [ANA_INIT] DLL >>>>>>>>
3807 13:59:31.138873 [ANA_INIT] flow end
3808 13:59:31.144806 ============ LP4 DIFF to SE enter ============
3809 13:59:31.148337 ============ LP4 DIFF to SE exit ============
3810 13:59:31.151661 [ANA_INIT] <<<<<<<<<<<<<
3811 13:59:31.155196 [Flow] Enable top DCM control >>>>>
3812 13:59:31.158755 [Flow] Enable top DCM control <<<<<
3813 13:59:31.159316 Enable DLL master slave shuffle
3814 13:59:31.164888 ==============================================================
3815 13:59:31.168422 Gating Mode config
3816 13:59:31.171591 ==============================================================
3817 13:59:31.174833 Config description:
3818 13:59:31.184883 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3819 13:59:31.192015 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3820 13:59:31.195084 SELPH_MODE 0: By rank 1: By Phase
3821 13:59:31.201190 ==============================================================
3822 13:59:31.204644 GAT_TRACK_EN = 1
3823 13:59:31.207749 RX_GATING_MODE = 2
3824 13:59:31.211489 RX_GATING_TRACK_MODE = 2
3825 13:59:31.214438 SELPH_MODE = 1
3826 13:59:31.214898 PICG_EARLY_EN = 1
3827 13:59:31.218203 VALID_LAT_VALUE = 1
3828 13:59:31.224737 ==============================================================
3829 13:59:31.227484 Enter into Gating configuration >>>>
3830 13:59:31.231196 Exit from Gating configuration <<<<
3831 13:59:31.234148 Enter into DVFS_PRE_config >>>>>
3832 13:59:31.244592 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3833 13:59:31.247507 Exit from DVFS_PRE_config <<<<<
3834 13:59:31.251380 Enter into PICG configuration >>>>
3835 13:59:31.254185 Exit from PICG configuration <<<<
3836 13:59:31.257236 [RX_INPUT] configuration >>>>>
3837 13:59:31.261020 [RX_INPUT] configuration <<<<<
3838 13:59:31.264028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3839 13:59:31.270886 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3840 13:59:31.277743 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 13:59:31.283888 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 13:59:31.290698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 13:59:31.297301 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 13:59:31.301014 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3845 13:59:31.304331 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3846 13:59:31.307306 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3847 13:59:31.310676 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3848 13:59:31.317740 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3849 13:59:31.320748 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3850 13:59:31.323789 ===================================
3851 13:59:31.327496 LPDDR4 DRAM CONFIGURATION
3852 13:59:31.330851 ===================================
3853 13:59:31.331263 EX_ROW_EN[0] = 0x0
3854 13:59:31.334055 EX_ROW_EN[1] = 0x0
3855 13:59:31.334464 LP4Y_EN = 0x0
3856 13:59:31.337145 WORK_FSP = 0x0
3857 13:59:31.337654 WL = 0x2
3858 13:59:31.340153 RL = 0x2
3859 13:59:31.340556 BL = 0x2
3860 13:59:31.344248 RPST = 0x0
3861 13:59:31.344735 RD_PRE = 0x0
3862 13:59:31.347561 WR_PRE = 0x1
3863 13:59:31.347996 WR_PST = 0x0
3864 13:59:31.350858 DBI_WR = 0x0
3865 13:59:31.354443 DBI_RD = 0x0
3866 13:59:31.354963 OTF = 0x1
3867 13:59:31.357302 ===================================
3868 13:59:31.360957 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3869 13:59:31.364278 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3870 13:59:31.371009 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3871 13:59:31.374037 ===================================
3872 13:59:31.377142 LPDDR4 DRAM CONFIGURATION
3873 13:59:31.377565 ===================================
3874 13:59:31.380878 EX_ROW_EN[0] = 0x10
3875 13:59:31.383758 EX_ROW_EN[1] = 0x0
3876 13:59:31.384195 LP4Y_EN = 0x0
3877 13:59:31.387283 WORK_FSP = 0x0
3878 13:59:31.387703 WL = 0x2
3879 13:59:31.390831 RL = 0x2
3880 13:59:31.391352 BL = 0x2
3881 13:59:31.393953 RPST = 0x0
3882 13:59:31.394486 RD_PRE = 0x0
3883 13:59:31.396874 WR_PRE = 0x1
3884 13:59:31.397327 WR_PST = 0x0
3885 13:59:31.400400 DBI_WR = 0x0
3886 13:59:31.400822 DBI_RD = 0x0
3887 13:59:31.403569 OTF = 0x1
3888 13:59:31.407311 ===================================
3889 13:59:31.413837 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3890 13:59:31.416903 nWR fixed to 30
3891 13:59:31.420638 [ModeRegInit_LP4] CH0 RK0
3892 13:59:31.421266 [ModeRegInit_LP4] CH0 RK1
3893 13:59:31.423972 [ModeRegInit_LP4] CH1 RK0
3894 13:59:31.427104 [ModeRegInit_LP4] CH1 RK1
3895 13:59:31.427517 match AC timing 17
3896 13:59:31.433318 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3897 13:59:31.437047 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3898 13:59:31.440136 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3899 13:59:31.446657 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3900 13:59:31.449856 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3901 13:59:31.450279 ==
3902 13:59:31.453211 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 13:59:31.457205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3904 13:59:31.457728 ==
3905 13:59:31.463565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3906 13:59:31.470086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3907 13:59:31.473133 [CA 0] Center 36 (5~67) winsize 63
3908 13:59:31.477092 [CA 1] Center 36 (5~67) winsize 63
3909 13:59:31.480060 [CA 2] Center 33 (3~64) winsize 62
3910 13:59:31.483647 [CA 3] Center 33 (2~64) winsize 63
3911 13:59:31.486581 [CA 4] Center 33 (2~64) winsize 63
3912 13:59:31.489992 [CA 5] Center 32 (2~63) winsize 62
3913 13:59:31.490552
3914 13:59:31.493233 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3915 13:59:31.493750
3916 13:59:31.496548 [CATrainingPosCal] consider 1 rank data
3917 13:59:31.499963 u2DelayCellTimex100 = 270/100 ps
3918 13:59:31.503144 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3919 13:59:31.506320 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3920 13:59:31.509634 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3921 13:59:31.513551 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 13:59:31.516496 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3923 13:59:31.523011 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3924 13:59:31.523707
3925 13:59:31.526651 CA PerBit enable=1, Macro0, CA PI delay=32
3926 13:59:31.527084
3927 13:59:31.529604 [CBTSetCACLKResult] CA Dly = 32
3928 13:59:31.530014 CS Dly: 4 (0~35)
3929 13:59:31.530334 ==
3930 13:59:31.533197 Dram Type= 6, Freq= 0, CH_0, rank 1
3931 13:59:31.536390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 13:59:31.539561 ==
3933 13:59:31.542850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 13:59:31.550104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3935 13:59:31.553163 [CA 0] Center 35 (5~66) winsize 62
3936 13:59:31.556744 [CA 1] Center 35 (5~66) winsize 62
3937 13:59:31.559947 [CA 2] Center 34 (3~65) winsize 63
3938 13:59:31.563310 [CA 3] Center 33 (3~64) winsize 62
3939 13:59:31.566318 [CA 4] Center 33 (2~64) winsize 63
3940 13:59:31.570369 [CA 5] Center 32 (1~63) winsize 63
3941 13:59:31.570876
3942 13:59:31.573315 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3943 13:59:31.573802
3944 13:59:31.576370 [CATrainingPosCal] consider 2 rank data
3945 13:59:31.579771 u2DelayCellTimex100 = 270/100 ps
3946 13:59:31.583292 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 13:59:31.586487 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3948 13:59:31.589794 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3949 13:59:31.593020 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3950 13:59:31.599680 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3951 13:59:31.603293 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3952 13:59:31.603931
3953 13:59:31.606078 CA PerBit enable=1, Macro0, CA PI delay=32
3954 13:59:31.606500
3955 13:59:31.609973 [CBTSetCACLKResult] CA Dly = 32
3956 13:59:31.610397 CS Dly: 4 (0~36)
3957 13:59:31.610827
3958 13:59:31.612979 ----->DramcWriteLeveling(PI) begin...
3959 13:59:31.613503 ==
3960 13:59:31.616863 Dram Type= 6, Freq= 0, CH_0, rank 0
3961 13:59:31.623159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 13:59:31.623765 ==
3963 13:59:31.626419 Write leveling (Byte 0): 34 => 34
3964 13:59:31.626842 Write leveling (Byte 1): 29 => 29
3965 13:59:31.629529 DramcWriteLeveling(PI) end<-----
3966 13:59:31.630023
3967 13:59:31.630451 ==
3968 13:59:31.632862 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 13:59:31.639832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 13:59:31.640473 ==
3971 13:59:31.642734 [Gating] SW mode calibration
3972 13:59:31.649283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3973 13:59:31.652799 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3974 13:59:31.659575 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 13:59:31.662953 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 13:59:31.666058 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 13:59:31.672686 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
3978 13:59:31.676172 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
3979 13:59:31.679219 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 13:59:31.685987 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 13:59:31.689246 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 13:59:31.692409 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 13:59:31.699671 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 13:59:31.703187 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 13:59:31.706132 0 10 12 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
3986 13:59:31.709170 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3987 13:59:31.715957 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 13:59:31.719738 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 13:59:31.722808 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 13:59:31.729034 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 13:59:31.732865 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 13:59:31.736102 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 13:59:31.742817 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3994 13:59:31.745633 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 13:59:31.749150 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 13:59:31.756013 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 13:59:31.759140 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 13:59:31.762577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 13:59:31.768982 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 13:59:31.772691 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 13:59:31.775998 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 13:59:31.782867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 13:59:31.785836 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:59:31.789125 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 13:59:31.795571 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 13:59:31.799017 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 13:59:31.802366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 13:59:31.809591 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 13:59:31.812833 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4010 13:59:31.815818 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4011 13:59:31.819217 Total UI for P1: 0, mck2ui 16
4012 13:59:31.822731 best dqsien dly found for B0: ( 0, 13, 12)
4013 13:59:31.825418 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 13:59:31.829124 Total UI for P1: 0, mck2ui 16
4015 13:59:31.832326 best dqsien dly found for B1: ( 0, 13, 16)
4016 13:59:31.835669 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4017 13:59:31.842093 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4018 13:59:31.842578
4019 13:59:31.845566 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4020 13:59:31.848543 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4021 13:59:31.852527 [Gating] SW calibration Done
4022 13:59:31.852938 ==
4023 13:59:31.855203 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 13:59:31.858770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 13:59:31.859193 ==
4026 13:59:31.862010 RX Vref Scan: 0
4027 13:59:31.862420
4028 13:59:31.862742 RX Vref 0 -> 0, step: 1
4029 13:59:31.863042
4030 13:59:31.865203 RX Delay -230 -> 252, step: 16
4031 13:59:31.868406 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4032 13:59:31.875116 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4033 13:59:31.878443 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4034 13:59:31.882129 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4035 13:59:31.885435 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4036 13:59:31.888561 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4037 13:59:31.895504 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4038 13:59:31.898346 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4039 13:59:31.901948 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4040 13:59:31.905252 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4041 13:59:31.911906 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4042 13:59:31.915134 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4043 13:59:31.918491 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4044 13:59:31.921700 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4045 13:59:31.928610 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4046 13:59:31.931825 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4047 13:59:31.932437 ==
4048 13:59:31.934736 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 13:59:31.938444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 13:59:31.938997 ==
4051 13:59:31.941479 DQS Delay:
4052 13:59:31.942022 DQS0 = 0, DQS1 = 0
4053 13:59:31.942362 DQM Delay:
4054 13:59:31.945322 DQM0 = 52, DQM1 = 46
4055 13:59:31.945752 DQ Delay:
4056 13:59:31.948750 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4057 13:59:31.951939 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4058 13:59:31.955330 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4059 13:59:31.958652 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4060 13:59:31.959183
4061 13:59:31.959655
4062 13:59:31.960136 ==
4063 13:59:31.961793 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 13:59:31.967975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 13:59:31.968604 ==
4066 13:59:31.969002
4067 13:59:31.969323
4068 13:59:31.969619 TX Vref Scan disable
4069 13:59:31.971813 == TX Byte 0 ==
4070 13:59:31.975283 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4071 13:59:31.982287 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4072 13:59:31.982702 == TX Byte 1 ==
4073 13:59:31.985332 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4074 13:59:31.991674 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4075 13:59:31.992106 ==
4076 13:59:31.995170 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 13:59:31.998463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 13:59:31.998962 ==
4079 13:59:31.999296
4080 13:59:31.999746
4081 13:59:32.002363 TX Vref Scan disable
4082 13:59:32.005487 == TX Byte 0 ==
4083 13:59:32.008219 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4084 13:59:32.011974 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4085 13:59:32.014929 == TX Byte 1 ==
4086 13:59:32.018134 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4087 13:59:32.021537 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4088 13:59:32.021951
4089 13:59:32.022275 [DATLAT]
4090 13:59:32.024826 Freq=600, CH0 RK0
4091 13:59:32.025241
4092 13:59:32.028168 DATLAT Default: 0x9
4093 13:59:32.028628 0, 0xFFFF, sum = 0
4094 13:59:32.031815 1, 0xFFFF, sum = 0
4095 13:59:32.032231 2, 0xFFFF, sum = 0
4096 13:59:32.034686 3, 0xFFFF, sum = 0
4097 13:59:32.034981 4, 0xFFFF, sum = 0
4098 13:59:32.038055 5, 0xFFFF, sum = 0
4099 13:59:32.038350 6, 0xFFFF, sum = 0
4100 13:59:32.041673 7, 0xFFFF, sum = 0
4101 13:59:32.041897 8, 0x0, sum = 1
4102 13:59:32.044748 9, 0x0, sum = 2
4103 13:59:32.044927 10, 0x0, sum = 3
4104 13:59:32.045069 11, 0x0, sum = 4
4105 13:59:32.047820 best_step = 9
4106 13:59:32.048003
4107 13:59:32.048140 ==
4108 13:59:32.051392 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 13:59:32.054717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 13:59:32.055133 ==
4111 13:59:32.058120 RX Vref Scan: 1
4112 13:59:32.058533
4113 13:59:32.061617 RX Vref 0 -> 0, step: 1
4114 13:59:32.062026
4115 13:59:32.062348 RX Delay -163 -> 252, step: 8
4116 13:59:32.062650
4117 13:59:32.064662 Set Vref, RX VrefLevel [Byte0]: 56
4118 13:59:32.067956 [Byte1]: 48
4119 13:59:32.072152
4120 13:59:32.072602 Final RX Vref Byte 0 = 56 to rank0
4121 13:59:32.075260 Final RX Vref Byte 1 = 48 to rank0
4122 13:59:32.078758 Final RX Vref Byte 0 = 56 to rank1
4123 13:59:32.082559 Final RX Vref Byte 1 = 48 to rank1==
4124 13:59:32.085396 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 13:59:32.092381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 13:59:32.092806 ==
4127 13:59:32.093127 DQS Delay:
4128 13:59:32.093430 DQS0 = 0, DQS1 = 0
4129 13:59:32.095604 DQM Delay:
4130 13:59:32.096010 DQM0 = 53, DQM1 = 45
4131 13:59:32.099047 DQ Delay:
4132 13:59:32.102187 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4133 13:59:32.105429 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4134 13:59:32.109051 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4135 13:59:32.111917 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4136 13:59:32.112357
4137 13:59:32.112685
4138 13:59:32.118612 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4139 13:59:32.122028 CH0 RK0: MR19=808, MR18=6D60
4140 13:59:32.128331 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4141 13:59:32.128654
4142 13:59:32.132024 ----->DramcWriteLeveling(PI) begin...
4143 13:59:32.132334 ==
4144 13:59:32.135091 Dram Type= 6, Freq= 0, CH_0, rank 1
4145 13:59:32.138486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 13:59:32.138697 ==
4147 13:59:32.141731 Write leveling (Byte 0): 36 => 36
4148 13:59:32.144840 Write leveling (Byte 1): 34 => 34
4149 13:59:32.148089 DramcWriteLeveling(PI) end<-----
4150 13:59:32.148266
4151 13:59:32.148419 ==
4152 13:59:32.151262 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 13:59:32.154805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 13:59:32.154997 ==
4155 13:59:32.158565 [Gating] SW mode calibration
4156 13:59:32.164890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4157 13:59:32.171726 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4158 13:59:32.175188 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 13:59:32.181587 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 13:59:32.185283 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 13:59:32.188803 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4162 13:59:32.192011 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
4163 13:59:32.199140 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 13:59:32.201628 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 13:59:32.205267 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 13:59:32.211872 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 13:59:32.215233 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 13:59:32.218837 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 13:59:32.224855 0 10 12 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4170 13:59:32.228357 0 10 16 | B1->B0 | 3e3e 3f3f | 0 0 | (0 0) (0 0)
4171 13:59:32.231526 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 13:59:32.238543 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 13:59:32.241935 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 13:59:32.244680 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 13:59:32.251291 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 13:59:32.254546 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 13:59:32.258630 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4178 13:59:32.264610 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4179 13:59:32.268190 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 13:59:32.271589 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 13:59:32.277986 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 13:59:32.281322 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 13:59:32.284599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 13:59:32.291135 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 13:59:32.294525 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 13:59:32.297762 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 13:59:32.304810 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 13:59:32.307711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 13:59:32.311942 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 13:59:32.317783 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 13:59:32.321728 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 13:59:32.324851 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 13:59:32.331769 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4194 13:59:32.334591 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 13:59:32.337637 Total UI for P1: 0, mck2ui 16
4196 13:59:32.341127 best dqsien dly found for B0: ( 0, 13, 14)
4197 13:59:32.344814 Total UI for P1: 0, mck2ui 16
4198 13:59:32.347955 best dqsien dly found for B1: ( 0, 13, 12)
4199 13:59:32.351121 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4200 13:59:32.354347 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4201 13:59:32.354855
4202 13:59:32.357880 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4203 13:59:32.360961 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4204 13:59:32.364272 [Gating] SW calibration Done
4205 13:59:32.364712 ==
4206 13:59:32.367447 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 13:59:32.370683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 13:59:32.374394 ==
4209 13:59:32.374987 RX Vref Scan: 0
4210 13:59:32.375476
4211 13:59:32.377223 RX Vref 0 -> 0, step: 1
4212 13:59:32.377719
4213 13:59:32.380279 RX Delay -230 -> 252, step: 16
4214 13:59:32.384172 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4215 13:59:32.386927 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4216 13:59:32.390633 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4217 13:59:32.397290 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4218 13:59:32.400570 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4219 13:59:32.404269 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4220 13:59:32.407006 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4221 13:59:32.410758 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4222 13:59:32.414338 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4223 13:59:32.420369 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4224 13:59:32.424173 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4225 13:59:32.427091 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4226 13:59:32.430672 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4227 13:59:32.437924 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4228 13:59:32.440637 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4229 13:59:32.443978 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4230 13:59:32.444405 ==
4231 13:59:32.447250 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 13:59:32.453733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 13:59:32.454119 ==
4234 13:59:32.454421 DQS Delay:
4235 13:59:32.454703 DQS0 = 0, DQS1 = 0
4236 13:59:32.456772 DQM Delay:
4237 13:59:32.457152 DQM0 = 55, DQM1 = 44
4238 13:59:32.460669 DQ Delay:
4239 13:59:32.463331 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4240 13:59:32.463714 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4241 13:59:32.466481 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4242 13:59:32.473568 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4243 13:59:32.473952
4244 13:59:32.474253
4245 13:59:32.474531 ==
4246 13:59:32.476965 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 13:59:32.480236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 13:59:32.480545 ==
4249 13:59:32.480763
4250 13:59:32.480962
4251 13:59:32.483358 TX Vref Scan disable
4252 13:59:32.483584 == TX Byte 0 ==
4253 13:59:32.489967 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4254 13:59:32.493054 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4255 13:59:32.493223 == TX Byte 1 ==
4256 13:59:32.499627 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4257 13:59:32.503406 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4258 13:59:32.503575 ==
4259 13:59:32.506733 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 13:59:32.510058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 13:59:32.510226 ==
4262 13:59:32.510358
4263 13:59:32.510480
4264 13:59:32.513301 TX Vref Scan disable
4265 13:59:32.516490 == TX Byte 0 ==
4266 13:59:32.519878 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4267 13:59:32.523527 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4268 13:59:32.526553 == TX Byte 1 ==
4269 13:59:32.529931 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4270 13:59:32.533189 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4271 13:59:32.533374
4272 13:59:32.536365 [DATLAT]
4273 13:59:32.536534 Freq=600, CH0 RK1
4274 13:59:32.536671
4275 13:59:32.540114 DATLAT Default: 0x9
4276 13:59:32.540297 0, 0xFFFF, sum = 0
4277 13:59:32.543237 1, 0xFFFF, sum = 0
4278 13:59:32.543411 2, 0xFFFF, sum = 0
4279 13:59:32.546411 3, 0xFFFF, sum = 0
4280 13:59:32.546584 4, 0xFFFF, sum = 0
4281 13:59:32.549655 5, 0xFFFF, sum = 0
4282 13:59:32.549828 6, 0xFFFF, sum = 0
4283 13:59:32.553048 7, 0xFFFF, sum = 0
4284 13:59:32.553221 8, 0x0, sum = 1
4285 13:59:32.556281 9, 0x0, sum = 2
4286 13:59:32.556470 10, 0x0, sum = 3
4287 13:59:32.559839 11, 0x0, sum = 4
4288 13:59:32.560012 best_step = 9
4289 13:59:32.560146
4290 13:59:32.560272 ==
4291 13:59:32.563412 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 13:59:32.570123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 13:59:32.570296 ==
4294 13:59:32.570432 RX Vref Scan: 0
4295 13:59:32.570558
4296 13:59:32.573319 RX Vref 0 -> 0, step: 1
4297 13:59:32.573490
4298 13:59:32.576629 RX Delay -163 -> 252, step: 8
4299 13:59:32.579781 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4300 13:59:32.583252 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4301 13:59:32.589851 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4302 13:59:32.593159 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4303 13:59:32.596235 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4304 13:59:32.600072 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4305 13:59:32.603159 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4306 13:59:32.609868 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4307 13:59:32.612984 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4308 13:59:32.616344 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4309 13:59:32.619905 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4310 13:59:32.623108 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4311 13:59:32.629700 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4312 13:59:32.632720 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4313 13:59:32.636560 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4314 13:59:32.639570 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4315 13:59:32.639740 ==
4316 13:59:32.643013 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 13:59:32.649338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 13:59:32.649510 ==
4319 13:59:32.649643 DQS Delay:
4320 13:59:32.652624 DQS0 = 0, DQS1 = 0
4321 13:59:32.652843 DQM Delay:
4322 13:59:32.656037 DQM0 = 54, DQM1 = 46
4323 13:59:32.656255 DQ Delay:
4324 13:59:32.659449 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4325 13:59:32.662566 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4326 13:59:32.665937 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4327 13:59:32.668937 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4328 13:59:32.669108
4329 13:59:32.669240
4330 13:59:32.675985 [DQSOSCAuto] RK1, (LSB)MR18= 0x6628, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4331 13:59:32.679309 CH0 RK1: MR19=808, MR18=6628
4332 13:59:32.686175 CH0_RK1: MR19=0x808, MR18=0x6628, DQSOSC=390, MR23=63, INC=172, DEC=114
4333 13:59:32.689358 [RxdqsGatingPostProcess] freq 600
4334 13:59:32.695900 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4335 13:59:32.696356 Pre-setting of DQS Precalculation
4336 13:59:32.702483 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4337 13:59:32.702903 ==
4338 13:59:32.706679 Dram Type= 6, Freq= 0, CH_1, rank 0
4339 13:59:32.709504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 13:59:32.709919 ==
4341 13:59:32.716261 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4342 13:59:32.722698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4343 13:59:32.725786 [CA 0] Center 35 (5~66) winsize 62
4344 13:59:32.729277 [CA 1] Center 35 (5~66) winsize 62
4345 13:59:32.732661 [CA 2] Center 34 (4~65) winsize 62
4346 13:59:32.735804 [CA 3] Center 34 (4~65) winsize 62
4347 13:59:32.739224 [CA 4] Center 34 (4~65) winsize 62
4348 13:59:32.742528 [CA 5] Center 33 (3~64) winsize 62
4349 13:59:32.742826
4350 13:59:32.746002 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4351 13:59:32.746298
4352 13:59:32.749194 [CATrainingPosCal] consider 1 rank data
4353 13:59:32.752280 u2DelayCellTimex100 = 270/100 ps
4354 13:59:32.756058 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4355 13:59:32.759335 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4356 13:59:32.762531 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4357 13:59:32.765566 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 13:59:32.769086 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4359 13:59:32.772283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4360 13:59:32.772611
4361 13:59:32.779195 CA PerBit enable=1, Macro0, CA PI delay=33
4362 13:59:32.779493
4363 13:59:32.779723 [CBTSetCACLKResult] CA Dly = 33
4364 13:59:32.782068 CS Dly: 5 (0~36)
4365 13:59:32.782365 ==
4366 13:59:32.785592 Dram Type= 6, Freq= 0, CH_1, rank 1
4367 13:59:32.788720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 13:59:32.789021 ==
4369 13:59:32.795356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 13:59:32.801983 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4371 13:59:32.805194 [CA 0] Center 36 (5~67) winsize 63
4372 13:59:32.808960 [CA 1] Center 36 (5~67) winsize 63
4373 13:59:32.812408 [CA 2] Center 34 (4~65) winsize 62
4374 13:59:32.816117 [CA 3] Center 34 (4~65) winsize 62
4375 13:59:32.819217 [CA 4] Center 34 (4~65) winsize 62
4376 13:59:32.822617 [CA 5] Center 34 (3~65) winsize 63
4377 13:59:32.822934
4378 13:59:32.825770 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4379 13:59:32.826063
4380 13:59:32.829161 [CATrainingPosCal] consider 2 rank data
4381 13:59:32.832417 u2DelayCellTimex100 = 270/100 ps
4382 13:59:32.835688 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 13:59:32.839295 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4384 13:59:32.842281 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 13:59:32.845504 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 13:59:32.848614 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 13:59:32.851805 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 13:59:32.852112
4389 13:59:32.858699 CA PerBit enable=1, Macro0, CA PI delay=33
4390 13:59:32.858993
4391 13:59:32.859226 [CBTSetCACLKResult] CA Dly = 33
4392 13:59:32.862244 CS Dly: 6 (0~38)
4393 13:59:32.862537
4394 13:59:32.865854 ----->DramcWriteLeveling(PI) begin...
4395 13:59:32.866156 ==
4396 13:59:32.868541 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 13:59:32.872138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 13:59:32.872470 ==
4399 13:59:32.875298 Write leveling (Byte 0): 31 => 31
4400 13:59:32.879030 Write leveling (Byte 1): 31 => 31
4401 13:59:32.882114 DramcWriteLeveling(PI) end<-----
4402 13:59:32.882410
4403 13:59:32.882645 ==
4404 13:59:32.885480 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 13:59:32.891643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 13:59:32.892034 ==
4407 13:59:32.892418 [Gating] SW mode calibration
4408 13:59:32.901763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4409 13:59:32.905019 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4410 13:59:32.908789 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 13:59:32.915202 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 13:59:32.918502 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4413 13:59:32.921846 0 9 12 | B1->B0 | 2c2c 2f2f | 1 0 | (1 0) (0 1)
4414 13:59:32.928543 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4415 13:59:32.931528 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 13:59:32.934908 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 13:59:32.942107 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 13:59:32.945140 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 13:59:32.948758 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 13:59:32.955338 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 13:59:32.958226 0 10 12 | B1->B0 | 3c3c 3c3c | 1 0 | (0 0) (0 0)
4422 13:59:32.961559 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 13:59:32.968378 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 13:59:32.971809 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 13:59:32.974920 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 13:59:32.981944 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 13:59:32.984965 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 13:59:32.988335 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 13:59:32.991763 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4430 13:59:32.998175 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 13:59:33.001720 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 13:59:33.005304 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 13:59:33.011977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:59:33.015132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:59:33.018056 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 13:59:33.024955 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 13:59:33.028507 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 13:59:33.031854 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 13:59:33.038257 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 13:59:33.041551 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 13:59:33.045098 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 13:59:33.051675 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 13:59:33.054997 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 13:59:33.058337 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 13:59:33.064892 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4446 13:59:33.068180 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 13:59:33.071681 Total UI for P1: 0, mck2ui 16
4448 13:59:33.075159 best dqsien dly found for B0: ( 0, 13, 12)
4449 13:59:33.078076 Total UI for P1: 0, mck2ui 16
4450 13:59:33.081755 best dqsien dly found for B1: ( 0, 13, 14)
4451 13:59:33.084671 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4452 13:59:33.088080 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4453 13:59:33.088207
4454 13:59:33.091314 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4455 13:59:33.095290 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4456 13:59:33.098189 [Gating] SW calibration Done
4457 13:59:33.098309 ==
4458 13:59:33.101751 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 13:59:33.105004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 13:59:33.105178 ==
4461 13:59:33.108062 RX Vref Scan: 0
4462 13:59:33.108194
4463 13:59:33.111362 RX Vref 0 -> 0, step: 1
4464 13:59:33.111559
4465 13:59:33.111733 RX Delay -230 -> 252, step: 16
4466 13:59:33.118291 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4467 13:59:33.121646 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4468 13:59:33.124834 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4469 13:59:33.128590 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4470 13:59:33.135227 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4471 13:59:33.137915 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4472 13:59:33.141557 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4473 13:59:33.144933 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4474 13:59:33.148619 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4475 13:59:33.155287 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4476 13:59:33.158903 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4477 13:59:33.162170 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4478 13:59:33.165192 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4479 13:59:33.171644 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4480 13:59:33.175130 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4481 13:59:33.178180 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4482 13:59:33.178715 ==
4483 13:59:33.181843 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 13:59:33.188424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 13:59:33.189003 ==
4486 13:59:33.189517 DQS Delay:
4487 13:59:33.189989 DQS0 = 0, DQS1 = 0
4488 13:59:33.191336 DQM Delay:
4489 13:59:33.191708 DQM0 = 50, DQM1 = 46
4490 13:59:33.194812 DQ Delay:
4491 13:59:33.198645 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4492 13:59:33.199234 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4493 13:59:33.201183 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4494 13:59:33.205322 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4495 13:59:33.208587
4496 13:59:33.209111
4497 13:59:33.209562 ==
4498 13:59:33.211568 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 13:59:33.214542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 13:59:33.214801 ==
4501 13:59:33.215046
4502 13:59:33.215219
4503 13:59:33.217884 TX Vref Scan disable
4504 13:59:33.218105 == TX Byte 0 ==
4505 13:59:33.224634 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4506 13:59:33.228075 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4507 13:59:33.228397 == TX Byte 1 ==
4508 13:59:33.234633 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 13:59:33.237871 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 13:59:33.238091 ==
4511 13:59:33.241737 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 13:59:33.244899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 13:59:33.245319 ==
4514 13:59:33.245645
4515 13:59:33.245943
4516 13:59:33.248016 TX Vref Scan disable
4517 13:59:33.252047 == TX Byte 0 ==
4518 13:59:33.254914 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4519 13:59:33.258672 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4520 13:59:33.261714 == TX Byte 1 ==
4521 13:59:33.265002 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 13:59:33.268191 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 13:59:33.268834
4524 13:59:33.271498 [DATLAT]
4525 13:59:33.272038 Freq=600, CH1 RK0
4526 13:59:33.272563
4527 13:59:33.274988 DATLAT Default: 0x9
4528 13:59:33.275545 0, 0xFFFF, sum = 0
4529 13:59:33.278415 1, 0xFFFF, sum = 0
4530 13:59:33.278832 2, 0xFFFF, sum = 0
4531 13:59:33.281628 3, 0xFFFF, sum = 0
4532 13:59:33.282044 4, 0xFFFF, sum = 0
4533 13:59:33.284791 5, 0xFFFF, sum = 0
4534 13:59:33.285211 6, 0xFFFF, sum = 0
4535 13:59:33.287975 7, 0xFFFF, sum = 0
4536 13:59:33.288421 8, 0x0, sum = 1
4537 13:59:33.291536 9, 0x0, sum = 2
4538 13:59:33.291955 10, 0x0, sum = 3
4539 13:59:33.294921 11, 0x0, sum = 4
4540 13:59:33.295340 best_step = 9
4541 13:59:33.295663
4542 13:59:33.295959 ==
4543 13:59:33.297840 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 13:59:33.304353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 13:59:33.304861 ==
4546 13:59:33.305382 RX Vref Scan: 1
4547 13:59:33.305784
4548 13:59:33.307933 RX Vref 0 -> 0, step: 1
4549 13:59:33.308513
4550 13:59:33.311348 RX Delay -163 -> 252, step: 8
4551 13:59:33.311910
4552 13:59:33.314782 Set Vref, RX VrefLevel [Byte0]: 56
4553 13:59:33.317921 [Byte1]: 48
4554 13:59:33.318452
4555 13:59:33.321154 Final RX Vref Byte 0 = 56 to rank0
4556 13:59:33.324719 Final RX Vref Byte 1 = 48 to rank0
4557 13:59:33.327849 Final RX Vref Byte 0 = 56 to rank1
4558 13:59:33.330860 Final RX Vref Byte 1 = 48 to rank1==
4559 13:59:33.334411 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 13:59:33.337262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 13:59:33.337796 ==
4562 13:59:33.340727 DQS Delay:
4563 13:59:33.341062 DQS0 = 0, DQS1 = 0
4564 13:59:33.341311 DQM Delay:
4565 13:59:33.344371 DQM0 = 48, DQM1 = 44
4566 13:59:33.344685 DQ Delay:
4567 13:59:33.347518 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4568 13:59:33.350647 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4569 13:59:33.354529 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4570 13:59:33.357469 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4571 13:59:33.357898
4572 13:59:33.358250
4573 13:59:33.367202 [DQSOSCAuto] RK0, (LSB)MR18= 0x4368, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4574 13:59:33.367622 CH1 RK0: MR19=808, MR18=4368
4575 13:59:33.374345 CH1_RK0: MR19=0x808, MR18=0x4368, DQSOSC=390, MR23=63, INC=172, DEC=114
4576 13:59:33.374708
4577 13:59:33.377201 ----->DramcWriteLeveling(PI) begin...
4578 13:59:33.380473 ==
4579 13:59:33.383833 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 13:59:33.387176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 13:59:33.387683 ==
4582 13:59:33.390941 Write leveling (Byte 0): 28 => 28
4583 13:59:33.394213 Write leveling (Byte 1): 31 => 31
4584 13:59:33.397444 DramcWriteLeveling(PI) end<-----
4585 13:59:33.397765
4586 13:59:33.398005 ==
4587 13:59:33.400537 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 13:59:33.403841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 13:59:33.404207 ==
4590 13:59:33.407022 [Gating] SW mode calibration
4591 13:59:33.413933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4592 13:59:33.420517 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4593 13:59:33.423755 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 13:59:33.427304 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 13:59:33.430813 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 13:59:33.437224 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
4597 13:59:33.440488 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 13:59:33.444083 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 13:59:33.450645 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 13:59:33.453594 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 13:59:33.457943 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 13:59:33.463825 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 13:59:33.467426 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 13:59:33.470483 0 10 12 | B1->B0 | 3a3a 3838 | 0 0 | (0 0) (0 0)
4605 13:59:33.477227 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 13:59:33.480535 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 13:59:33.483932 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 13:59:33.490521 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 13:59:33.493598 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 13:59:33.496800 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 13:59:33.503441 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 13:59:33.506843 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4613 13:59:33.510161 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 13:59:33.517076 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 13:59:33.520354 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 13:59:33.523847 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 13:59:33.530099 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 13:59:33.533447 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 13:59:33.536758 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 13:59:33.543403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 13:59:33.546636 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 13:59:33.550035 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 13:59:33.556779 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 13:59:33.560157 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 13:59:33.563447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 13:59:33.569693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 13:59:33.573660 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 13:59:33.576680 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4629 13:59:33.583389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 13:59:33.583958 Total UI for P1: 0, mck2ui 16
4631 13:59:33.586450 best dqsien dly found for B0: ( 0, 13, 12)
4632 13:59:33.590015 Total UI for P1: 0, mck2ui 16
4633 13:59:33.593262 best dqsien dly found for B1: ( 0, 13, 12)
4634 13:59:33.599841 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4635 13:59:33.603513 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4636 13:59:33.604058
4637 13:59:33.606798 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4638 13:59:33.609797 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4639 13:59:33.613382 [Gating] SW calibration Done
4640 13:59:33.613935 ==
4641 13:59:33.616805 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 13:59:33.620237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 13:59:33.620845 ==
4644 13:59:33.623406 RX Vref Scan: 0
4645 13:59:33.623961
4646 13:59:33.624363 RX Vref 0 -> 0, step: 1
4647 13:59:33.624709
4648 13:59:33.626508 RX Delay -230 -> 252, step: 16
4649 13:59:33.629816 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4650 13:59:33.636201 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4651 13:59:33.639764 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4652 13:59:33.642527 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4653 13:59:33.646316 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4654 13:59:33.652905 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4655 13:59:33.656423 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4656 13:59:33.659590 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4657 13:59:33.662665 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4658 13:59:33.665940 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4659 13:59:33.672609 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4660 13:59:33.675768 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4661 13:59:33.679359 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4662 13:59:33.682501 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4663 13:59:33.688942 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4664 13:59:33.692591 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4665 13:59:33.692823 ==
4666 13:59:33.695686 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 13:59:33.699084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 13:59:33.699330 ==
4669 13:59:33.702245 DQS Delay:
4670 13:59:33.702422 DQS0 = 0, DQS1 = 0
4671 13:59:33.702578 DQM Delay:
4672 13:59:33.706024 DQM0 = 49, DQM1 = 47
4673 13:59:33.706210 DQ Delay:
4674 13:59:33.709113 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4675 13:59:33.712221 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4676 13:59:33.715315 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4677 13:59:33.718872 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4678 13:59:33.719072
4679 13:59:33.719220
4680 13:59:33.719381 ==
4681 13:59:33.722413 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 13:59:33.729108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 13:59:33.729358 ==
4684 13:59:33.729523
4685 13:59:33.729657
4686 13:59:33.729809 TX Vref Scan disable
4687 13:59:33.732251 == TX Byte 0 ==
4688 13:59:33.735884 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4689 13:59:33.742186 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4690 13:59:33.742440 == TX Byte 1 ==
4691 13:59:33.745731 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4692 13:59:33.752454 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4693 13:59:33.752686 ==
4694 13:59:33.755482 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 13:59:33.759394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 13:59:33.759573 ==
4697 13:59:33.759713
4698 13:59:33.759841
4699 13:59:33.762461 TX Vref Scan disable
4700 13:59:33.765658 == TX Byte 0 ==
4701 13:59:33.768919 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4702 13:59:33.772783 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4703 13:59:33.776020 == TX Byte 1 ==
4704 13:59:33.779313 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 13:59:33.782398 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 13:59:33.782576
4707 13:59:33.782714 [DATLAT]
4708 13:59:33.785769 Freq=600, CH1 RK1
4709 13:59:33.786039
4710 13:59:33.786184 DATLAT Default: 0x9
4711 13:59:33.789100 0, 0xFFFF, sum = 0
4712 13:59:33.789281 1, 0xFFFF, sum = 0
4713 13:59:33.792260 2, 0xFFFF, sum = 0
4714 13:59:33.796037 3, 0xFFFF, sum = 0
4715 13:59:33.796331 4, 0xFFFF, sum = 0
4716 13:59:33.799263 5, 0xFFFF, sum = 0
4717 13:59:33.799511 6, 0xFFFF, sum = 0
4718 13:59:33.802515 7, 0xFFFF, sum = 0
4719 13:59:33.802792 8, 0x0, sum = 1
4720 13:59:33.803038 9, 0x0, sum = 2
4721 13:59:33.805457 10, 0x0, sum = 3
4722 13:59:33.805546 11, 0x0, sum = 4
4723 13:59:33.808586 best_step = 9
4724 13:59:33.808690
4725 13:59:33.808781 ==
4726 13:59:33.812502 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 13:59:33.815722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 13:59:33.815803 ==
4729 13:59:33.818970 RX Vref Scan: 0
4730 13:59:33.819050
4731 13:59:33.819112 RX Vref 0 -> 0, step: 1
4732 13:59:33.819170
4733 13:59:33.822492 RX Delay -163 -> 252, step: 8
4734 13:59:33.829583 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4735 13:59:33.832739 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4736 13:59:33.836236 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4737 13:59:33.839618 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4738 13:59:33.842848 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4739 13:59:33.849637 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4740 13:59:33.853007 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4741 13:59:33.855811 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4742 13:59:33.859290 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4743 13:59:33.866489 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4744 13:59:33.869310 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4745 13:59:33.872848 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4746 13:59:33.876393 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4747 13:59:33.879766 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4748 13:59:33.886256 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4749 13:59:33.889902 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4750 13:59:33.890505 ==
4751 13:59:33.893240 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 13:59:33.896592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 13:59:33.897049 ==
4754 13:59:33.899746 DQS Delay:
4755 13:59:33.900197 DQS0 = 0, DQS1 = 0
4756 13:59:33.900625 DQM Delay:
4757 13:59:33.902905 DQM0 = 48, DQM1 = 45
4758 13:59:33.903435 DQ Delay:
4759 13:59:33.906031 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4760 13:59:33.909692 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4761 13:59:33.912786 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4762 13:59:33.916025 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4763 13:59:33.916551
4764 13:59:33.916879
4765 13:59:33.926161 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4766 13:59:33.926580 CH1 RK1: MR19=808, MR18=6D25
4767 13:59:33.932856 CH1_RK1: MR19=0x808, MR18=0x6D25, DQSOSC=389, MR23=63, INC=173, DEC=115
4768 13:59:33.936273 [RxdqsGatingPostProcess] freq 600
4769 13:59:33.943400 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4770 13:59:33.946560 Pre-setting of DQS Precalculation
4771 13:59:33.949749 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4772 13:59:33.956179 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4773 13:59:33.966082 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4774 13:59:33.966285
4775 13:59:33.966457
4776 13:59:33.969052 [Calibration Summary] 1200 Mbps
4777 13:59:33.969201 CH 0, Rank 0
4778 13:59:33.972421 SW Impedance : PASS
4779 13:59:33.972501 DUTY Scan : NO K
4780 13:59:33.975982 ZQ Calibration : PASS
4781 13:59:33.976097 Jitter Meter : NO K
4782 13:59:33.978867 CBT Training : PASS
4783 13:59:33.982258 Write leveling : PASS
4784 13:59:33.982338 RX DQS gating : PASS
4785 13:59:33.985761 RX DQ/DQS(RDDQC) : PASS
4786 13:59:33.989329 TX DQ/DQS : PASS
4787 13:59:33.989441 RX DATLAT : PASS
4788 13:59:33.992395 RX DQ/DQS(Engine): PASS
4789 13:59:33.995761 TX OE : NO K
4790 13:59:33.995862 All Pass.
4791 13:59:33.995928
4792 13:59:33.995987 CH 0, Rank 1
4793 13:59:33.999071 SW Impedance : PASS
4794 13:59:34.002401 DUTY Scan : NO K
4795 13:59:34.002481 ZQ Calibration : PASS
4796 13:59:34.005588 Jitter Meter : NO K
4797 13:59:34.008838 CBT Training : PASS
4798 13:59:34.008944 Write leveling : PASS
4799 13:59:34.011981 RX DQS gating : PASS
4800 13:59:34.015734 RX DQ/DQS(RDDQC) : PASS
4801 13:59:34.015819 TX DQ/DQS : PASS
4802 13:59:34.018940 RX DATLAT : PASS
4803 13:59:34.022111 RX DQ/DQS(Engine): PASS
4804 13:59:34.022184 TX OE : NO K
4805 13:59:34.022245 All Pass.
4806 13:59:34.025120
4807 13:59:34.025199 CH 1, Rank 0
4808 13:59:34.028985 SW Impedance : PASS
4809 13:59:34.029082 DUTY Scan : NO K
4810 13:59:34.032318 ZQ Calibration : PASS
4811 13:59:34.032415 Jitter Meter : NO K
4812 13:59:34.035633 CBT Training : PASS
4813 13:59:34.038805 Write leveling : PASS
4814 13:59:34.038885 RX DQS gating : PASS
4815 13:59:34.041839 RX DQ/DQS(RDDQC) : PASS
4816 13:59:34.045393 TX DQ/DQS : PASS
4817 13:59:34.045473 RX DATLAT : PASS
4818 13:59:34.048493 RX DQ/DQS(Engine): PASS
4819 13:59:34.051821 TX OE : NO K
4820 13:59:34.051901 All Pass.
4821 13:59:34.051964
4822 13:59:34.052065 CH 1, Rank 1
4823 13:59:34.055115 SW Impedance : PASS
4824 13:59:34.058527 DUTY Scan : NO K
4825 13:59:34.058607 ZQ Calibration : PASS
4826 13:59:34.062292 Jitter Meter : NO K
4827 13:59:34.065161 CBT Training : PASS
4828 13:59:34.065583 Write leveling : PASS
4829 13:59:34.068863 RX DQS gating : PASS
4830 13:59:34.072182 RX DQ/DQS(RDDQC) : PASS
4831 13:59:34.072886 TX DQ/DQS : PASS
4832 13:59:34.075493 RX DATLAT : PASS
4833 13:59:34.078556 RX DQ/DQS(Engine): PASS
4834 13:59:34.078969 TX OE : NO K
4835 13:59:34.082416 All Pass.
4836 13:59:34.082923
4837 13:59:34.083251 DramC Write-DBI off
4838 13:59:34.085411 PER_BANK_REFRESH: Hybrid Mode
4839 13:59:34.085875 TX_TRACKING: ON
4840 13:59:34.095085 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4841 13:59:34.098619 [FAST_K] Save calibration result to emmc
4842 13:59:34.102106 dramc_set_vcore_voltage set vcore to 662500
4843 13:59:34.105245 Read voltage for 933, 3
4844 13:59:34.105663 Vio18 = 0
4845 13:59:34.108268 Vcore = 662500
4846 13:59:34.108726 Vdram = 0
4847 13:59:34.109059 Vddq = 0
4848 13:59:34.109362 Vmddr = 0
4849 13:59:34.115005 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4850 13:59:34.121901 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4851 13:59:34.122425 MEM_TYPE=3, freq_sel=17
4852 13:59:34.125018 sv_algorithm_assistance_LP4_1600
4853 13:59:34.128241 ============ PULL DRAM RESETB DOWN ============
4854 13:59:34.135148 ========== PULL DRAM RESETB DOWN end =========
4855 13:59:34.138384 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4856 13:59:34.141618 ===================================
4857 13:59:34.145239 LPDDR4 DRAM CONFIGURATION
4858 13:59:34.148764 ===================================
4859 13:59:34.149297 EX_ROW_EN[0] = 0x0
4860 13:59:34.151491 EX_ROW_EN[1] = 0x0
4861 13:59:34.151907 LP4Y_EN = 0x0
4862 13:59:34.154970 WORK_FSP = 0x0
4863 13:59:34.158277 WL = 0x3
4864 13:59:34.158696 RL = 0x3
4865 13:59:34.161476 BL = 0x2
4866 13:59:34.161891 RPST = 0x0
4867 13:59:34.164810 RD_PRE = 0x0
4868 13:59:34.165227 WR_PRE = 0x1
4869 13:59:34.168180 WR_PST = 0x0
4870 13:59:34.168755 DBI_WR = 0x0
4871 13:59:34.171629 DBI_RD = 0x0
4872 13:59:34.172146 OTF = 0x1
4873 13:59:34.175516 ===================================
4874 13:59:34.178435 ===================================
4875 13:59:34.181915 ANA top config
4876 13:59:34.185067 ===================================
4877 13:59:34.185488 DLL_ASYNC_EN = 0
4878 13:59:34.188230 ALL_SLAVE_EN = 1
4879 13:59:34.191351 NEW_RANK_MODE = 1
4880 13:59:34.194882 DLL_IDLE_MODE = 1
4881 13:59:34.195298 LP45_APHY_COMB_EN = 1
4882 13:59:34.198390 TX_ODT_DIS = 1
4883 13:59:34.201575 NEW_8X_MODE = 1
4884 13:59:34.204595 ===================================
4885 13:59:34.207916 ===================================
4886 13:59:34.211265 data_rate = 1866
4887 13:59:34.214480 CKR = 1
4888 13:59:34.217916 DQ_P2S_RATIO = 8
4889 13:59:34.221137 ===================================
4890 13:59:34.221618 CA_P2S_RATIO = 8
4891 13:59:34.224157 DQ_CA_OPEN = 0
4892 13:59:34.228039 DQ_SEMI_OPEN = 0
4893 13:59:34.231334 CA_SEMI_OPEN = 0
4894 13:59:34.234506 CA_FULL_RATE = 0
4895 13:59:34.237509 DQ_CKDIV4_EN = 1
4896 13:59:34.237919 CA_CKDIV4_EN = 1
4897 13:59:34.241439 CA_PREDIV_EN = 0
4898 13:59:34.244890 PH8_DLY = 0
4899 13:59:34.248099 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4900 13:59:34.251170 DQ_AAMCK_DIV = 4
4901 13:59:34.254332 CA_AAMCK_DIV = 4
4902 13:59:34.254806 CA_ADMCK_DIV = 4
4903 13:59:34.257477 DQ_TRACK_CA_EN = 0
4904 13:59:34.261057 CA_PICK = 933
4905 13:59:34.264839 CA_MCKIO = 933
4906 13:59:34.268206 MCKIO_SEMI = 0
4907 13:59:34.271488 PLL_FREQ = 3732
4908 13:59:34.274929 DQ_UI_PI_RATIO = 32
4909 13:59:34.275478 CA_UI_PI_RATIO = 0
4910 13:59:34.278153 ===================================
4911 13:59:34.281079 ===================================
4912 13:59:34.284539 memory_type:LPDDR4
4913 13:59:34.287704 GP_NUM : 10
4914 13:59:34.288374 SRAM_EN : 1
4915 13:59:34.291018 MD32_EN : 0
4916 13:59:34.294541 ===================================
4917 13:59:34.297742 [ANA_INIT] >>>>>>>>>>>>>>
4918 13:59:34.301074 <<<<<< [CONFIGURE PHASE]: ANA_TX
4919 13:59:34.304338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4920 13:59:34.307233 ===================================
4921 13:59:34.307789 data_rate = 1866,PCW = 0X8f00
4922 13:59:34.310582 ===================================
4923 13:59:34.313893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4924 13:59:34.320960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 13:59:34.327587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 13:59:34.330789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4927 13:59:34.333923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4928 13:59:34.337550 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4929 13:59:34.340356 [ANA_INIT] flow start
4930 13:59:34.340814 [ANA_INIT] PLL >>>>>>>>
4931 13:59:34.343734 [ANA_INIT] PLL <<<<<<<<
4932 13:59:34.347503 [ANA_INIT] MIDPI >>>>>>>>
4933 13:59:34.350567 [ANA_INIT] MIDPI <<<<<<<<
4934 13:59:34.351091 [ANA_INIT] DLL >>>>>>>>
4935 13:59:34.353635 [ANA_INIT] flow end
4936 13:59:34.357350 ============ LP4 DIFF to SE enter ============
4937 13:59:34.360565 ============ LP4 DIFF to SE exit ============
4938 13:59:34.363861 [ANA_INIT] <<<<<<<<<<<<<
4939 13:59:34.367036 [Flow] Enable top DCM control >>>>>
4940 13:59:34.370112 [Flow] Enable top DCM control <<<<<
4941 13:59:34.374114 Enable DLL master slave shuffle
4942 13:59:34.380738 ==============================================================
4943 13:59:34.381250 Gating Mode config
4944 13:59:34.387148 ==============================================================
4945 13:59:34.387658 Config description:
4946 13:59:34.397181 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4947 13:59:34.404278 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4948 13:59:34.410468 SELPH_MODE 0: By rank 1: By Phase
4949 13:59:34.413722 ==============================================================
4950 13:59:34.416859 GAT_TRACK_EN = 1
4951 13:59:34.420194 RX_GATING_MODE = 2
4952 13:59:34.423815 RX_GATING_TRACK_MODE = 2
4953 13:59:34.426784 SELPH_MODE = 1
4954 13:59:34.430108 PICG_EARLY_EN = 1
4955 13:59:34.433423 VALID_LAT_VALUE = 1
4956 13:59:34.436833 ==============================================================
4957 13:59:34.440603 Enter into Gating configuration >>>>
4958 13:59:34.443871 Exit from Gating configuration <<<<
4959 13:59:34.447511 Enter into DVFS_PRE_config >>>>>
4960 13:59:34.460083 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4961 13:59:34.463145 Exit from DVFS_PRE_config <<<<<
4962 13:59:34.466666 Enter into PICG configuration >>>>
4963 13:59:34.470165 Exit from PICG configuration <<<<
4964 13:59:34.470626 [RX_INPUT] configuration >>>>>
4965 13:59:34.473440 [RX_INPUT] configuration <<<<<
4966 13:59:34.480062 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4967 13:59:34.482997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4968 13:59:34.489930 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 13:59:34.496681 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 13:59:34.503373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 13:59:34.509696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 13:59:34.512943 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4973 13:59:34.516591 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4974 13:59:34.523048 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4975 13:59:34.526410 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4976 13:59:34.529416 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4977 13:59:34.536410 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 13:59:34.536955 ===================================
4979 13:59:34.539707 LPDDR4 DRAM CONFIGURATION
4980 13:59:34.542864 ===================================
4981 13:59:34.546251 EX_ROW_EN[0] = 0x0
4982 13:59:34.546711 EX_ROW_EN[1] = 0x0
4983 13:59:34.549590 LP4Y_EN = 0x0
4984 13:59:34.550200 WORK_FSP = 0x0
4985 13:59:34.552781 WL = 0x3
4986 13:59:34.553390 RL = 0x3
4987 13:59:34.555956 BL = 0x2
4988 13:59:34.559267 RPST = 0x0
4989 13:59:34.559878 RD_PRE = 0x0
4990 13:59:34.562596 WR_PRE = 0x1
4991 13:59:34.563157 WR_PST = 0x0
4992 13:59:34.566003 DBI_WR = 0x0
4993 13:59:34.566415 DBI_RD = 0x0
4994 13:59:34.569333 OTF = 0x1
4995 13:59:34.572597 ===================================
4996 13:59:34.575833 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4997 13:59:34.579362 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4998 13:59:34.582706 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 13:59:34.585613 ===================================
5000 13:59:34.588953 LPDDR4 DRAM CONFIGURATION
5001 13:59:34.592606 ===================================
5002 13:59:34.595877 EX_ROW_EN[0] = 0x10
5003 13:59:34.596437 EX_ROW_EN[1] = 0x0
5004 13:59:34.598918 LP4Y_EN = 0x0
5005 13:59:34.599330 WORK_FSP = 0x0
5006 13:59:34.602433 WL = 0x3
5007 13:59:34.602841 RL = 0x3
5008 13:59:34.605893 BL = 0x2
5009 13:59:34.606404 RPST = 0x0
5010 13:59:34.609385 RD_PRE = 0x0
5011 13:59:34.609799 WR_PRE = 0x1
5012 13:59:34.612158 WR_PST = 0x0
5013 13:59:34.615704 DBI_WR = 0x0
5014 13:59:34.616128 DBI_RD = 0x0
5015 13:59:34.618612 OTF = 0x1
5016 13:59:34.622438 ===================================
5017 13:59:34.625367 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5018 13:59:34.631084 nWR fixed to 30
5019 13:59:34.634201 [ModeRegInit_LP4] CH0 RK0
5020 13:59:34.634745 [ModeRegInit_LP4] CH0 RK1
5021 13:59:34.637664 [ModeRegInit_LP4] CH1 RK0
5022 13:59:34.640981 [ModeRegInit_LP4] CH1 RK1
5023 13:59:34.641403 match AC timing 9
5024 13:59:34.647617 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5025 13:59:34.650778 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5026 13:59:34.654030 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5027 13:59:34.661136 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5028 13:59:34.663747 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5029 13:59:34.664188 ==
5030 13:59:34.667057 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 13:59:34.670560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5032 13:59:34.671012 ==
5033 13:59:34.677141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5034 13:59:34.683800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5035 13:59:34.687057 [CA 0] Center 37 (6~68) winsize 63
5036 13:59:34.690704 [CA 1] Center 37 (7~68) winsize 62
5037 13:59:34.693657 [CA 2] Center 34 (4~65) winsize 62
5038 13:59:34.696947 [CA 3] Center 34 (3~65) winsize 63
5039 13:59:34.700082 [CA 4] Center 33 (3~63) winsize 61
5040 13:59:34.703408 [CA 5] Center 32 (2~62) winsize 61
5041 13:59:34.703628
5042 13:59:34.707367 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5043 13:59:34.707667
5044 13:59:34.710148 [CATrainingPosCal] consider 1 rank data
5045 13:59:34.713597 u2DelayCellTimex100 = 270/100 ps
5046 13:59:34.716628 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5047 13:59:34.720387 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5048 13:59:34.723402 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5049 13:59:34.726643 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5050 13:59:34.729982 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5051 13:59:34.736839 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5052 13:59:34.737100
5053 13:59:34.740078 CA PerBit enable=1, Macro0, CA PI delay=32
5054 13:59:34.740388
5055 13:59:34.743260 [CBTSetCACLKResult] CA Dly = 32
5056 13:59:34.743582 CS Dly: 5 (0~36)
5057 13:59:34.743878 ==
5058 13:59:34.746390 Dram Type= 6, Freq= 0, CH_0, rank 1
5059 13:59:34.749552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 13:59:34.753486 ==
5061 13:59:34.756417 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 13:59:34.762730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5063 13:59:34.766112 [CA 0] Center 37 (6~68) winsize 63
5064 13:59:34.770019 [CA 1] Center 37 (6~68) winsize 63
5065 13:59:34.772680 [CA 2] Center 34 (4~65) winsize 62
5066 13:59:34.776370 [CA 3] Center 34 (4~65) winsize 62
5067 13:59:34.779888 [CA 4] Center 33 (2~64) winsize 63
5068 13:59:34.783100 [CA 5] Center 32 (2~62) winsize 61
5069 13:59:34.783388
5070 13:59:34.786348 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5071 13:59:34.786621
5072 13:59:34.789680 [CATrainingPosCal] consider 2 rank data
5073 13:59:34.792999 u2DelayCellTimex100 = 270/100 ps
5074 13:59:34.796096 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5075 13:59:34.799253 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5076 13:59:34.802610 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5077 13:59:34.809245 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5078 13:59:34.812638 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5079 13:59:34.816033 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5080 13:59:34.816221
5081 13:59:34.819328 CA PerBit enable=1, Macro0, CA PI delay=32
5082 13:59:34.819513
5083 13:59:34.822585 [CBTSetCACLKResult] CA Dly = 32
5084 13:59:34.822859 CS Dly: 5 (0~37)
5085 13:59:34.823117
5086 13:59:34.825777 ----->DramcWriteLeveling(PI) begin...
5087 13:59:34.828936 ==
5088 13:59:34.829199 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 13:59:34.836060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 13:59:34.836325 ==
5091 13:59:34.839150 Write leveling (Byte 0): 33 => 33
5092 13:59:34.842393 Write leveling (Byte 1): 31 => 31
5093 13:59:34.845560 DramcWriteLeveling(PI) end<-----
5094 13:59:34.845779
5095 13:59:34.845951 ==
5096 13:59:34.849302 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 13:59:34.852676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 13:59:34.852896 ==
5099 13:59:34.856005 [Gating] SW mode calibration
5100 13:59:34.862145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5101 13:59:34.868793 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5102 13:59:34.872480 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
5103 13:59:34.875781 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 13:59:34.879011 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 13:59:34.885690 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 13:59:34.888927 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 13:59:34.892377 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 13:59:34.899122 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5109 13:59:34.902467 0 14 28 | B1->B0 | 3232 2929 | 0 0 | (0 1) (1 0)
5110 13:59:34.905824 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5111 13:59:34.912476 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 13:59:34.916254 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 13:59:34.919519 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 13:59:34.925712 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 13:59:34.929508 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 13:59:34.932496 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5117 13:59:34.938952 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5118 13:59:34.942193 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
5119 13:59:34.945489 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 13:59:34.952464 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 13:59:34.955888 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 13:59:34.958997 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 13:59:34.965307 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 13:59:34.968577 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 13:59:34.972310 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5126 13:59:34.978717 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5127 13:59:34.982041 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 13:59:34.985125 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 13:59:34.991546 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 13:59:34.994987 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 13:59:34.998344 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 13:59:35.005200 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 13:59:35.008115 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 13:59:35.011950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 13:59:35.015102 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 13:59:35.021489 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 13:59:35.024766 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 13:59:35.027872 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 13:59:35.034806 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 13:59:35.038076 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5141 13:59:35.041172 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5142 13:59:35.044562 Total UI for P1: 0, mck2ui 16
5143 13:59:35.047975 best dqsien dly found for B0: ( 1, 2, 24)
5144 13:59:35.054516 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 13:59:35.058029 Total UI for P1: 0, mck2ui 16
5146 13:59:35.061283 best dqsien dly found for B1: ( 1, 2, 28)
5147 13:59:35.064738 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5148 13:59:35.068403 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5149 13:59:35.068497
5150 13:59:35.071710 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5151 13:59:35.075019 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5152 13:59:35.078168 [Gating] SW calibration Done
5153 13:59:35.078269 ==
5154 13:59:35.081430 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 13:59:35.084595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 13:59:35.084696 ==
5157 13:59:35.088035 RX Vref Scan: 0
5158 13:59:35.088137
5159 13:59:35.088215 RX Vref 0 -> 0, step: 1
5160 13:59:35.088299
5161 13:59:35.091320 RX Delay -80 -> 252, step: 8
5162 13:59:35.097852 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5163 13:59:35.101416 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5164 13:59:35.104607 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 13:59:35.108161 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 13:59:35.111047 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5167 13:59:35.114198 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5168 13:59:35.121317 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5169 13:59:35.124195 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5170 13:59:35.127964 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5171 13:59:35.131222 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5172 13:59:35.134279 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5173 13:59:35.137572 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5174 13:59:35.144620 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5175 13:59:35.147596 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5176 13:59:35.150935 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5177 13:59:35.154611 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 13:59:35.154852 ==
5179 13:59:35.157568 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 13:59:35.160985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 13:59:35.164735 ==
5182 13:59:35.165058 DQS Delay:
5183 13:59:35.165337 DQS0 = 0, DQS1 = 0
5184 13:59:35.167889 DQM Delay:
5185 13:59:35.168176 DQM0 = 104, DQM1 = 94
5186 13:59:35.171105 DQ Delay:
5187 13:59:35.174105 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5188 13:59:35.177410 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5189 13:59:35.181480 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5190 13:59:35.184237 DQ12 =99, DQ13 =103, DQ14 =99, DQ15 =99
5191 13:59:35.184889
5192 13:59:35.185463
5193 13:59:35.185953 ==
5194 13:59:35.188053 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 13:59:35.190778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 13:59:35.191396 ==
5197 13:59:35.191965
5198 13:59:35.192576
5199 13:59:35.194801 TX Vref Scan disable
5200 13:59:35.195405 == TX Byte 0 ==
5201 13:59:35.201367 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5202 13:59:35.204455 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5203 13:59:35.207401 == TX Byte 1 ==
5204 13:59:35.210642 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5205 13:59:35.214184 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5206 13:59:35.214575 ==
5207 13:59:35.217987 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 13:59:35.220953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 13:59:35.221343 ==
5210 13:59:35.224476
5211 13:59:35.224862
5212 13:59:35.225112 TX Vref Scan disable
5213 13:59:35.227515 == TX Byte 0 ==
5214 13:59:35.231219 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5215 13:59:35.237632 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5216 13:59:35.237941 == TX Byte 1 ==
5217 13:59:35.240778 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5218 13:59:35.247872 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5219 13:59:35.248169
5220 13:59:35.248440 [DATLAT]
5221 13:59:35.248660 Freq=933, CH0 RK0
5222 13:59:35.248871
5223 13:59:35.251222 DATLAT Default: 0xd
5224 13:59:35.251600 0, 0xFFFF, sum = 0
5225 13:59:35.254462 1, 0xFFFF, sum = 0
5226 13:59:35.254879 2, 0xFFFF, sum = 0
5227 13:59:35.257383 3, 0xFFFF, sum = 0
5228 13:59:35.257802 4, 0xFFFF, sum = 0
5229 13:59:35.260928 5, 0xFFFF, sum = 0
5230 13:59:35.264542 6, 0xFFFF, sum = 0
5231 13:59:35.265073 7, 0xFFFF, sum = 0
5232 13:59:35.267968 8, 0xFFFF, sum = 0
5233 13:59:35.268447 9, 0xFFFF, sum = 0
5234 13:59:35.270619 10, 0x0, sum = 1
5235 13:59:35.271118 11, 0x0, sum = 2
5236 13:59:35.271563 12, 0x0, sum = 3
5237 13:59:35.274242 13, 0x0, sum = 4
5238 13:59:35.274768 best_step = 11
5239 13:59:35.275202
5240 13:59:35.277587 ==
5241 13:59:35.281169 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 13:59:35.284407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 13:59:35.284917 ==
5244 13:59:35.285246 RX Vref Scan: 1
5245 13:59:35.285549
5246 13:59:35.287319 RX Vref 0 -> 0, step: 1
5247 13:59:35.287735
5248 13:59:35.290601 RX Delay -53 -> 252, step: 4
5249 13:59:35.291040
5250 13:59:35.293886 Set Vref, RX VrefLevel [Byte0]: 56
5251 13:59:35.297613 [Byte1]: 48
5252 13:59:35.298131
5253 13:59:35.300773 Final RX Vref Byte 0 = 56 to rank0
5254 13:59:35.304016 Final RX Vref Byte 1 = 48 to rank0
5255 13:59:35.307623 Final RX Vref Byte 0 = 56 to rank1
5256 13:59:35.310652 Final RX Vref Byte 1 = 48 to rank1==
5257 13:59:35.313631 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 13:59:35.317073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 13:59:35.320278 ==
5260 13:59:35.320740 DQS Delay:
5261 13:59:35.321082 DQS0 = 0, DQS1 = 0
5262 13:59:35.324451 DQM Delay:
5263 13:59:35.324967 DQM0 = 105, DQM1 = 94
5264 13:59:35.327263 DQ Delay:
5265 13:59:35.330792 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5266 13:59:35.333669 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5267 13:59:35.336933 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =90
5268 13:59:35.339974 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5269 13:59:35.340423
5270 13:59:35.340750
5271 13:59:35.346555 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5272 13:59:35.350407 CH0 RK0: MR19=505, MR18=322A
5273 13:59:35.356902 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5274 13:59:35.357319
5275 13:59:35.359921 ----->DramcWriteLeveling(PI) begin...
5276 13:59:35.360385 ==
5277 13:59:35.363733 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 13:59:35.367007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 13:59:35.367523 ==
5280 13:59:35.370403 Write leveling (Byte 0): 35 => 35
5281 13:59:35.373406 Write leveling (Byte 1): 30 => 30
5282 13:59:35.376484 DramcWriteLeveling(PI) end<-----
5283 13:59:35.376895
5284 13:59:35.377217 ==
5285 13:59:35.380665 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 13:59:35.383664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 13:59:35.386903 ==
5288 13:59:35.387317 [Gating] SW mode calibration
5289 13:59:35.396889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 13:59:35.400562 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 13:59:35.403308 0 14 0 | B1->B0 | 3333 3131 | 1 0 | (1 1) (1 1)
5292 13:59:35.409851 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 13:59:35.413401 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 13:59:35.416886 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 13:59:35.423551 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 13:59:35.426912 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 13:59:35.430418 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (0 0) (0 0)
5298 13:59:35.436640 0 14 28 | B1->B0 | 2c2c 2929 | 0 0 | (0 1) (0 1)
5299 13:59:35.439812 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5300 13:59:35.443558 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 13:59:35.449949 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 13:59:35.453152 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 13:59:35.456330 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 13:59:35.463308 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 13:59:35.466390 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5306 13:59:35.469762 0 15 28 | B1->B0 | 3e3e 4040 | 0 0 | (0 0) (0 0)
5307 13:59:35.476045 1 0 0 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
5308 13:59:35.479657 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 13:59:35.482689 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 13:59:35.489719 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 13:59:35.493250 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 13:59:35.496477 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 13:59:35.499829 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 13:59:35.506377 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 13:59:35.509739 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 13:59:35.513170 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 13:59:35.519912 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 13:59:35.523018 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 13:59:35.526004 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 13:59:35.532614 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 13:59:35.535990 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 13:59:35.539589 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 13:59:35.545942 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 13:59:35.549561 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 13:59:35.552789 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 13:59:35.559216 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 13:59:35.562412 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 13:59:35.566531 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 13:59:35.572782 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 13:59:35.575810 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5331 13:59:35.579184 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 13:59:35.583068 Total UI for P1: 0, mck2ui 16
5333 13:59:35.586059 best dqsien dly found for B0: ( 1, 2, 28)
5334 13:59:35.588840 Total UI for P1: 0, mck2ui 16
5335 13:59:35.592968 best dqsien dly found for B1: ( 1, 2, 28)
5336 13:59:35.595956 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5337 13:59:35.599483 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5338 13:59:35.600035
5339 13:59:35.605846 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 13:59:35.609623 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5341 13:59:35.612453 [Gating] SW calibration Done
5342 13:59:35.612907 ==
5343 13:59:35.615745 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 13:59:35.619703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 13:59:35.620254 ==
5346 13:59:35.620662 RX Vref Scan: 0
5347 13:59:35.621037
5348 13:59:35.622372 RX Vref 0 -> 0, step: 1
5349 13:59:35.622821
5350 13:59:35.625527 RX Delay -80 -> 252, step: 8
5351 13:59:35.629250 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5352 13:59:35.632380 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5353 13:59:35.638815 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5354 13:59:35.642239 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5355 13:59:35.645780 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5356 13:59:35.649028 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5357 13:59:35.652409 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5358 13:59:35.655505 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5359 13:59:35.662462 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5360 13:59:35.665191 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5361 13:59:35.668688 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5362 13:59:35.671822 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5363 13:59:35.675286 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5364 13:59:35.678693 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5365 13:59:35.685395 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5366 13:59:35.688813 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5367 13:59:35.689418 ==
5368 13:59:35.691991 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 13:59:35.695763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 13:59:35.696376 ==
5371 13:59:35.696747 DQS Delay:
5372 13:59:35.698424 DQS0 = 0, DQS1 = 0
5373 13:59:35.698878 DQM Delay:
5374 13:59:35.702383 DQM0 = 104, DQM1 = 93
5375 13:59:35.702837 DQ Delay:
5376 13:59:35.705663 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5377 13:59:35.709276 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5378 13:59:35.712382 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5379 13:59:35.715221 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5380 13:59:35.715673
5381 13:59:35.716026
5382 13:59:35.716401 ==
5383 13:59:35.718491 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 13:59:35.725350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 13:59:35.725845 ==
5386 13:59:35.726203
5387 13:59:35.726531
5388 13:59:35.726848 TX Vref Scan disable
5389 13:59:35.728591 == TX Byte 0 ==
5390 13:59:35.732164 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5391 13:59:35.738467 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5392 13:59:35.738926 == TX Byte 1 ==
5393 13:59:35.742270 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5394 13:59:35.745330 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5395 13:59:35.749241 ==
5396 13:59:35.752905 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 13:59:35.756154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 13:59:35.756784 ==
5399 13:59:35.757153
5400 13:59:35.757484
5401 13:59:35.759341 TX Vref Scan disable
5402 13:59:35.759892 == TX Byte 0 ==
5403 13:59:35.765650 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5404 13:59:35.768908 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5405 13:59:35.769367 == TX Byte 1 ==
5406 13:59:35.775539 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5407 13:59:35.778897 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5408 13:59:35.779455
5409 13:59:35.779856 [DATLAT]
5410 13:59:35.782451 Freq=933, CH0 RK1
5411 13:59:35.782908
5412 13:59:35.783261 DATLAT Default: 0xb
5413 13:59:35.785225 0, 0xFFFF, sum = 0
5414 13:59:35.785690 1, 0xFFFF, sum = 0
5415 13:59:35.788401 2, 0xFFFF, sum = 0
5416 13:59:35.788863 3, 0xFFFF, sum = 0
5417 13:59:35.791892 4, 0xFFFF, sum = 0
5418 13:59:35.792397 5, 0xFFFF, sum = 0
5419 13:59:35.795383 6, 0xFFFF, sum = 0
5420 13:59:35.798509 7, 0xFFFF, sum = 0
5421 13:59:35.798971 8, 0xFFFF, sum = 0
5422 13:59:35.801919 9, 0xFFFF, sum = 0
5423 13:59:35.802480 10, 0x0, sum = 1
5424 13:59:35.802849 11, 0x0, sum = 2
5425 13:59:35.805076 12, 0x0, sum = 3
5426 13:59:35.805541 13, 0x0, sum = 4
5427 13:59:35.808446 best_step = 11
5428 13:59:35.808907
5429 13:59:35.809267 ==
5430 13:59:35.812023 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 13:59:35.814907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 13:59:35.815373 ==
5433 13:59:35.818801 RX Vref Scan: 0
5434 13:59:35.819290
5435 13:59:35.819651 RX Vref 0 -> 0, step: 1
5436 13:59:35.821858
5437 13:59:35.822314 RX Delay -53 -> 252, step: 4
5438 13:59:35.829237 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5439 13:59:35.833041 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5440 13:59:35.836031 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5441 13:59:35.839625 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5442 13:59:35.842653 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5443 13:59:35.849179 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5444 13:59:35.852519 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5445 13:59:35.855965 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5446 13:59:35.859297 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5447 13:59:35.862137 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5448 13:59:35.869569 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5449 13:59:35.872662 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5450 13:59:35.876265 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5451 13:59:35.879445 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5452 13:59:35.882529 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5453 13:59:35.885741 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5454 13:59:35.889289 ==
5455 13:59:35.892416 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 13:59:35.895657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 13:59:35.896121 ==
5458 13:59:35.896553 DQS Delay:
5459 13:59:35.898649 DQS0 = 0, DQS1 = 0
5460 13:59:35.899109 DQM Delay:
5461 13:59:35.902521 DQM0 = 104, DQM1 = 93
5462 13:59:35.903080 DQ Delay:
5463 13:59:35.905684 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5464 13:59:35.909155 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5465 13:59:35.912246 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5466 13:59:35.915774 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5467 13:59:35.916235
5468 13:59:35.916633
5469 13:59:35.925718 [DQSOSCAuto] RK1, (LSB)MR18= 0x27ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5470 13:59:35.926332 CH0 RK1: MR19=504, MR18=27FF
5471 13:59:35.932748 CH0_RK1: MR19=0x504, MR18=0x27FF, DQSOSC=409, MR23=63, INC=64, DEC=43
5472 13:59:35.935854 [RxdqsGatingPostProcess] freq 933
5473 13:59:35.943071 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 13:59:35.945407 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 13:59:35.948940 best DQS1 dly(2T, 0.5T) = (0, 10)
5476 13:59:35.952426 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 13:59:35.956038 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5478 13:59:35.956646 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 13:59:35.959019 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 13:59:35.962594 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 13:59:35.965917 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 13:59:35.969019 Pre-setting of DQS Precalculation
5483 13:59:35.975680 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 13:59:35.976242 ==
5485 13:59:35.979023 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 13:59:35.982363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 13:59:35.982945 ==
5488 13:59:35.989419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 13:59:35.992372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5490 13:59:35.996635 [CA 0] Center 36 (6~67) winsize 62
5491 13:59:35.999901 [CA 1] Center 36 (6~67) winsize 62
5492 13:59:36.003522 [CA 2] Center 34 (4~65) winsize 62
5493 13:59:36.006341 [CA 3] Center 34 (4~64) winsize 61
5494 13:59:36.010244 [CA 4] Center 34 (4~64) winsize 61
5495 13:59:36.013053 [CA 5] Center 33 (3~64) winsize 62
5496 13:59:36.013520
5497 13:59:36.016704 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5498 13:59:36.017261
5499 13:59:36.019838 [CATrainingPosCal] consider 1 rank data
5500 13:59:36.022817 u2DelayCellTimex100 = 270/100 ps
5501 13:59:36.026318 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 13:59:36.033306 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 13:59:36.036548 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 13:59:36.039763 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5505 13:59:36.042997 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5506 13:59:36.046546 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 13:59:36.047109
5508 13:59:36.049691 CA PerBit enable=1, Macro0, CA PI delay=33
5509 13:59:36.050146
5510 13:59:36.053207 [CBTSetCACLKResult] CA Dly = 33
5511 13:59:36.056085 CS Dly: 7 (0~38)
5512 13:59:36.056715 ==
5513 13:59:36.059795 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 13:59:36.062980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 13:59:36.063538 ==
5516 13:59:36.066110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 13:59:36.072565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5518 13:59:36.076683 [CA 0] Center 37 (6~68) winsize 63
5519 13:59:36.080525 [CA 1] Center 37 (6~68) winsize 63
5520 13:59:36.083577 [CA 2] Center 35 (5~66) winsize 62
5521 13:59:36.086889 [CA 3] Center 34 (4~65) winsize 62
5522 13:59:36.089939 [CA 4] Center 34 (4~65) winsize 62
5523 13:59:36.093236 [CA 5] Center 34 (4~64) winsize 61
5524 13:59:36.093692
5525 13:59:36.096666 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5526 13:59:36.097122
5527 13:59:36.099654 [CATrainingPosCal] consider 2 rank data
5528 13:59:36.103340 u2DelayCellTimex100 = 270/100 ps
5529 13:59:36.106968 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5530 13:59:36.110245 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5531 13:59:36.116376 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5532 13:59:36.119989 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5533 13:59:36.123017 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5534 13:59:36.126711 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5535 13:59:36.127240
5536 13:59:36.129746 CA PerBit enable=1, Macro0, CA PI delay=34
5537 13:59:36.130207
5538 13:59:36.133244 [CBTSetCACLKResult] CA Dly = 34
5539 13:59:36.133807 CS Dly: 8 (0~40)
5540 13:59:36.134177
5541 13:59:36.136197 ----->DramcWriteLeveling(PI) begin...
5542 13:59:36.139829 ==
5543 13:59:36.142983 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 13:59:36.146737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 13:59:36.147298 ==
5546 13:59:36.149485 Write leveling (Byte 0): 26 => 26
5547 13:59:36.153436 Write leveling (Byte 1): 26 => 26
5548 13:59:36.156725 DramcWriteLeveling(PI) end<-----
5549 13:59:36.157290
5550 13:59:36.157656 ==
5551 13:59:36.160213 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 13:59:36.163325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 13:59:36.163790 ==
5554 13:59:36.166382 [Gating] SW mode calibration
5555 13:59:36.172891 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 13:59:36.179725 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 13:59:36.182945 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 13:59:36.186328 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 13:59:36.192689 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 13:59:36.195913 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 13:59:36.199569 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 13:59:36.206041 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 13:59:36.209620 0 14 24 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (0 0)
5564 13:59:36.212884 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5565 13:59:36.216156 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 13:59:36.222776 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 13:59:36.226100 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 13:59:36.229585 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 13:59:36.236052 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 13:59:36.239203 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 13:59:36.242993 0 15 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5572 13:59:36.249507 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5573 13:59:36.252451 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 13:59:36.256183 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 13:59:36.262397 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 13:59:36.265938 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 13:59:36.269317 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 13:59:36.275959 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 13:59:36.279133 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5580 13:59:36.282319 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5581 13:59:36.288716 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 13:59:36.291823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 13:59:36.295549 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 13:59:36.302004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 13:59:36.305243 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 13:59:36.308747 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 13:59:36.315622 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 13:59:36.318481 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 13:59:36.321987 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 13:59:36.329042 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 13:59:36.331923 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 13:59:36.334858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 13:59:36.341985 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 13:59:36.345246 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 13:59:36.348415 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5596 13:59:36.354897 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 13:59:36.355000 Total UI for P1: 0, mck2ui 16
5598 13:59:36.358441 best dqsien dly found for B0: ( 1, 2, 24)
5599 13:59:36.361399 Total UI for P1: 0, mck2ui 16
5600 13:59:36.364553 best dqsien dly found for B1: ( 1, 2, 24)
5601 13:59:36.371056 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5602 13:59:36.374246 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5603 13:59:36.374329
5604 13:59:36.377990 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5605 13:59:36.380955 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5606 13:59:36.384775 [Gating] SW calibration Done
5607 13:59:36.384857 ==
5608 13:59:36.387817 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 13:59:36.391502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 13:59:36.391583 ==
5611 13:59:36.394903 RX Vref Scan: 0
5612 13:59:36.394984
5613 13:59:36.395046 RX Vref 0 -> 0, step: 1
5614 13:59:36.395105
5615 13:59:36.397932 RX Delay -80 -> 252, step: 8
5616 13:59:36.401017 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5617 13:59:36.407438 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5618 13:59:36.411331 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5619 13:59:36.414623 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5620 13:59:36.417761 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5621 13:59:36.421249 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5622 13:59:36.424412 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5623 13:59:36.430866 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5624 13:59:36.434616 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5625 13:59:36.437816 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5626 13:59:36.440902 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5627 13:59:36.443982 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5628 13:59:36.447759 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5629 13:59:36.454101 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5630 13:59:36.457224 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5631 13:59:36.460950 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5632 13:59:36.461032 ==
5633 13:59:36.464545 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 13:59:36.467277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 13:59:36.467389 ==
5636 13:59:36.470638 DQS Delay:
5637 13:59:36.470733 DQS0 = 0, DQS1 = 0
5638 13:59:36.474273 DQM Delay:
5639 13:59:36.474367 DQM0 = 103, DQM1 = 98
5640 13:59:36.474458 DQ Delay:
5641 13:59:36.477351 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5642 13:59:36.481202 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5643 13:59:36.484157 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5644 13:59:36.490713 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5645 13:59:36.490798
5646 13:59:36.490861
5647 13:59:36.490918 ==
5648 13:59:36.494364 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 13:59:36.497699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 13:59:36.497780 ==
5651 13:59:36.497843
5652 13:59:36.497901
5653 13:59:36.500828 TX Vref Scan disable
5654 13:59:36.500981 == TX Byte 0 ==
5655 13:59:36.507257 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5656 13:59:36.511176 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5657 13:59:36.511312 == TX Byte 1 ==
5658 13:59:36.517656 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5659 13:59:36.520881 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5660 13:59:36.520960 ==
5661 13:59:36.524164 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 13:59:36.527261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 13:59:36.527341 ==
5664 13:59:36.527403
5665 13:59:36.527460
5666 13:59:36.531109 TX Vref Scan disable
5667 13:59:36.534254 == TX Byte 0 ==
5668 13:59:36.537443 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5669 13:59:36.541134 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5670 13:59:36.544037 == TX Byte 1 ==
5671 13:59:36.547625 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5672 13:59:36.551067 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5673 13:59:36.551147
5674 13:59:36.554135 [DATLAT]
5675 13:59:36.554215 Freq=933, CH1 RK0
5676 13:59:36.554279
5677 13:59:36.557346 DATLAT Default: 0xd
5678 13:59:36.557426 0, 0xFFFF, sum = 0
5679 13:59:36.560746 1, 0xFFFF, sum = 0
5680 13:59:36.560828 2, 0xFFFF, sum = 0
5681 13:59:36.564216 3, 0xFFFF, sum = 0
5682 13:59:36.564350 4, 0xFFFF, sum = 0
5683 13:59:36.567377 5, 0xFFFF, sum = 0
5684 13:59:36.567458 6, 0xFFFF, sum = 0
5685 13:59:36.571324 7, 0xFFFF, sum = 0
5686 13:59:36.571481 8, 0xFFFF, sum = 0
5687 13:59:36.574135 9, 0xFFFF, sum = 0
5688 13:59:36.574264 10, 0x0, sum = 1
5689 13:59:36.577744 11, 0x0, sum = 2
5690 13:59:36.577928 12, 0x0, sum = 3
5691 13:59:36.581100 13, 0x0, sum = 4
5692 13:59:36.581236 best_step = 11
5693 13:59:36.581310
5694 13:59:36.581374 ==
5695 13:59:36.583944 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 13:59:36.590494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 13:59:36.590577 ==
5698 13:59:36.590642 RX Vref Scan: 1
5699 13:59:36.590702
5700 13:59:36.594147 RX Vref 0 -> 0, step: 1
5701 13:59:36.594229
5702 13:59:36.597270 RX Delay -45 -> 252, step: 4
5703 13:59:36.597353
5704 13:59:36.600499 Set Vref, RX VrefLevel [Byte0]: 56
5705 13:59:36.604249 [Byte1]: 48
5706 13:59:36.604439
5707 13:59:36.608012 Final RX Vref Byte 0 = 56 to rank0
5708 13:59:36.611239 Final RX Vref Byte 1 = 48 to rank0
5709 13:59:36.614195 Final RX Vref Byte 0 = 56 to rank1
5710 13:59:36.617244 Final RX Vref Byte 1 = 48 to rank1==
5711 13:59:36.620706 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 13:59:36.624024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 13:59:36.624186 ==
5714 13:59:36.627245 DQS Delay:
5715 13:59:36.627384 DQS0 = 0, DQS1 = 0
5716 13:59:36.627493 DQM Delay:
5717 13:59:36.630556 DQM0 = 103, DQM1 = 97
5718 13:59:36.630715 DQ Delay:
5719 13:59:36.634158 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5720 13:59:36.637489 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5721 13:59:36.640702 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5722 13:59:36.644032 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =108
5723 13:59:36.644240
5724 13:59:36.644402
5725 13:59:36.654158 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5726 13:59:36.657136 CH1 RK0: MR19=505, MR18=1A32
5727 13:59:36.663797 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5728 13:59:36.664012
5729 13:59:36.667286 ----->DramcWriteLeveling(PI) begin...
5730 13:59:36.667439 ==
5731 13:59:36.670870 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 13:59:36.674186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 13:59:36.674306 ==
5734 13:59:36.677252 Write leveling (Byte 0): 28 => 28
5735 13:59:36.680569 Write leveling (Byte 1): 29 => 29
5736 13:59:36.683869 DramcWriteLeveling(PI) end<-----
5737 13:59:36.684036
5738 13:59:36.684117 ==
5739 13:59:36.687203 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 13:59:36.690748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 13:59:36.690916 ==
5742 13:59:36.694173 [Gating] SW mode calibration
5743 13:59:36.700696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5744 13:59:36.706780 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5745 13:59:36.710239 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 13:59:36.713547 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 13:59:36.720703 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 13:59:36.723634 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 13:59:36.726958 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 13:59:36.733575 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5751 13:59:36.736848 0 14 24 | B1->B0 | 2e2e 3333 | 0 0 | (0 1) (0 0)
5752 13:59:36.740041 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5753 13:59:36.747468 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 13:59:36.750683 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 13:59:36.753884 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 13:59:36.760586 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 13:59:36.763717 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 13:59:36.767102 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 13:59:36.774171 0 15 24 | B1->B0 | 3131 2a2a | 0 0 | (0 0) (0 0)
5760 13:59:36.777511 0 15 28 | B1->B0 | 4646 3e3e | 0 1 | (0 0) (0 0)
5761 13:59:36.780930 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 13:59:36.784138 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 13:59:36.791182 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 13:59:36.793866 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 13:59:36.797468 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 13:59:36.804704 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 13:59:36.807853 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5768 13:59:36.811005 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5769 13:59:36.817399 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 13:59:36.820404 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 13:59:36.823649 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 13:59:36.830499 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 13:59:36.833596 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 13:59:36.836938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 13:59:36.843884 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 13:59:36.847582 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 13:59:36.850235 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 13:59:36.857301 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 13:59:36.860622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 13:59:36.863796 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 13:59:36.870467 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 13:59:36.873507 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 13:59:36.877327 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5784 13:59:36.883970 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 13:59:36.884545 Total UI for P1: 0, mck2ui 16
5786 13:59:36.887463 best dqsien dly found for B0: ( 1, 2, 24)
5787 13:59:36.890496 Total UI for P1: 0, mck2ui 16
5788 13:59:36.893779 best dqsien dly found for B1: ( 1, 2, 26)
5789 13:59:36.900176 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5790 13:59:36.903655 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5791 13:59:36.904190
5792 13:59:36.906600 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5793 13:59:36.910289 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5794 13:59:36.913123 [Gating] SW calibration Done
5795 13:59:36.913537 ==
5796 13:59:36.917116 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 13:59:36.920239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 13:59:36.920788 ==
5799 13:59:36.923426 RX Vref Scan: 0
5800 13:59:36.923928
5801 13:59:36.924257 RX Vref 0 -> 0, step: 1
5802 13:59:36.924627
5803 13:59:36.926942 RX Delay -80 -> 252, step: 8
5804 13:59:36.930291 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5805 13:59:36.936432 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5806 13:59:36.939869 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5807 13:59:36.943624 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5808 13:59:36.946847 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5809 13:59:36.949983 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5810 13:59:36.953650 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5811 13:59:36.959855 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5812 13:59:36.963558 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5813 13:59:36.966341 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5814 13:59:36.969896 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5815 13:59:36.973344 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5816 13:59:36.976706 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5817 13:59:36.983435 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5818 13:59:36.986541 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5819 13:59:36.989933 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5820 13:59:36.990474 ==
5821 13:59:36.993341 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 13:59:36.996746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 13:59:37.000202 ==
5824 13:59:37.000792 DQS Delay:
5825 13:59:37.001154 DQS0 = 0, DQS1 = 0
5826 13:59:37.003154 DQM Delay:
5827 13:59:37.003622 DQM0 = 105, DQM1 = 99
5828 13:59:37.006263 DQ Delay:
5829 13:59:37.010339 DQ0 =111, DQ1 =103, DQ2 =95, DQ3 =99
5830 13:59:37.012985 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5831 13:59:37.016647 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =95
5832 13:59:37.020200 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5833 13:59:37.020793
5834 13:59:37.021151
5835 13:59:37.021480 ==
5836 13:59:37.023112 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 13:59:37.026357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 13:59:37.026907 ==
5839 13:59:37.027266
5840 13:59:37.027599
5841 13:59:37.030181 TX Vref Scan disable
5842 13:59:37.033030 == TX Byte 0 ==
5843 13:59:37.036377 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5844 13:59:37.039442 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5845 13:59:37.042561 == TX Byte 1 ==
5846 13:59:37.046231 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5847 13:59:37.049486 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5848 13:59:37.049945 ==
5849 13:59:37.052868 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 13:59:37.056342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 13:59:37.056806 ==
5852 13:59:37.059954
5853 13:59:37.060543
5854 13:59:37.060909 TX Vref Scan disable
5855 13:59:37.062671 == TX Byte 0 ==
5856 13:59:37.066441 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5857 13:59:37.069722 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5858 13:59:37.073444 == TX Byte 1 ==
5859 13:59:37.076538 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5860 13:59:37.079829 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5861 13:59:37.082678
5862 13:59:37.083130 [DATLAT]
5863 13:59:37.083488 Freq=933, CH1 RK1
5864 13:59:37.083825
5865 13:59:37.086664 DATLAT Default: 0xb
5866 13:59:37.087257 0, 0xFFFF, sum = 0
5867 13:59:37.089424 1, 0xFFFF, sum = 0
5868 13:59:37.089884 2, 0xFFFF, sum = 0
5869 13:59:37.092783 3, 0xFFFF, sum = 0
5870 13:59:37.093306 4, 0xFFFF, sum = 0
5871 13:59:37.096371 5, 0xFFFF, sum = 0
5872 13:59:37.096836 6, 0xFFFF, sum = 0
5873 13:59:37.099437 7, 0xFFFF, sum = 0
5874 13:59:37.102962 8, 0xFFFF, sum = 0
5875 13:59:37.103517 9, 0xFFFF, sum = 0
5876 13:59:37.106174 10, 0x0, sum = 1
5877 13:59:37.106817 11, 0x0, sum = 2
5878 13:59:37.107251 12, 0x0, sum = 3
5879 13:59:37.109859 13, 0x0, sum = 4
5880 13:59:37.110418 best_step = 11
5881 13:59:37.110777
5882 13:59:37.111107 ==
5883 13:59:37.113107 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 13:59:37.119725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 13:59:37.120186 ==
5886 13:59:37.120635 RX Vref Scan: 0
5887 13:59:37.120953
5888 13:59:37.122708 RX Vref 0 -> 0, step: 1
5889 13:59:37.123120
5890 13:59:37.126442 RX Delay -45 -> 252, step: 4
5891 13:59:37.129714 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5892 13:59:37.136055 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5893 13:59:37.139957 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5894 13:59:37.143058 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5895 13:59:37.146608 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5896 13:59:37.149581 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5897 13:59:37.156366 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5898 13:59:37.159724 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5899 13:59:37.162556 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5900 13:59:37.166128 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5901 13:59:37.169687 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5902 13:59:37.172964 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5903 13:59:37.179702 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5904 13:59:37.182737 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5905 13:59:37.186264 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5906 13:59:37.189350 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5907 13:59:37.189807 ==
5908 13:59:37.192879 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 13:59:37.199371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 13:59:37.199925 ==
5911 13:59:37.200317 DQS Delay:
5912 13:59:37.200660 DQS0 = 0, DQS1 = 0
5913 13:59:37.202358 DQM Delay:
5914 13:59:37.202811 DQM0 = 104, DQM1 = 99
5915 13:59:37.206104 DQ Delay:
5916 13:59:37.209301 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5917 13:59:37.212429 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5918 13:59:37.215615 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
5919 13:59:37.219314 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5920 13:59:37.219929
5921 13:59:37.220345
5922 13:59:37.225713 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5923 13:59:37.228906 CH1 RK1: MR19=504, MR18=2BFE
5924 13:59:37.235514 CH1_RK1: MR19=0x504, MR18=0x2BFE, DQSOSC=408, MR23=63, INC=65, DEC=43
5925 13:59:37.239042 [RxdqsGatingPostProcess] freq 933
5926 13:59:37.246725 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 13:59:37.249465 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 13:59:37.250022 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 13:59:37.252411 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 13:59:37.255561 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 13:59:37.258843 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 13:59:37.261890 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 13:59:37.265771 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 13:59:37.268373 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 13:59:37.272257 Pre-setting of DQS Precalculation
5936 13:59:37.278868 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 13:59:37.285387 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 13:59:37.291726 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 13:59:37.292263
5940 13:59:37.292700
5941 13:59:37.294874 [Calibration Summary] 1866 Mbps
5942 13:59:37.295327 CH 0, Rank 0
5943 13:59:37.298756 SW Impedance : PASS
5944 13:59:37.302052 DUTY Scan : NO K
5945 13:59:37.302505 ZQ Calibration : PASS
5946 13:59:37.305264 Jitter Meter : NO K
5947 13:59:37.308606 CBT Training : PASS
5948 13:59:37.309157 Write leveling : PASS
5949 13:59:37.311998 RX DQS gating : PASS
5950 13:59:37.314953 RX DQ/DQS(RDDQC) : PASS
5951 13:59:37.315629 TX DQ/DQS : PASS
5952 13:59:37.318671 RX DATLAT : PASS
5953 13:59:37.321854 RX DQ/DQS(Engine): PASS
5954 13:59:37.322405 TX OE : NO K
5955 13:59:37.322766 All Pass.
5956 13:59:37.325222
5957 13:59:37.325669 CH 0, Rank 1
5958 13:59:37.328458 SW Impedance : PASS
5959 13:59:37.329019 DUTY Scan : NO K
5960 13:59:37.331910 ZQ Calibration : PASS
5961 13:59:37.332515 Jitter Meter : NO K
5962 13:59:37.335267 CBT Training : PASS
5963 13:59:37.338414 Write leveling : PASS
5964 13:59:37.338886 RX DQS gating : PASS
5965 13:59:37.341706 RX DQ/DQS(RDDQC) : PASS
5966 13:59:37.344930 TX DQ/DQS : PASS
5967 13:59:37.345386 RX DATLAT : PASS
5968 13:59:37.349223 RX DQ/DQS(Engine): PASS
5969 13:59:37.351883 TX OE : NO K
5970 13:59:37.352380 All Pass.
5971 13:59:37.352749
5972 13:59:37.353084 CH 1, Rank 0
5973 13:59:37.355025 SW Impedance : PASS
5974 13:59:37.358360 DUTY Scan : NO K
5975 13:59:37.358928 ZQ Calibration : PASS
5976 13:59:37.361736 Jitter Meter : NO K
5977 13:59:37.365290 CBT Training : PASS
5978 13:59:37.365870 Write leveling : PASS
5979 13:59:37.368527 RX DQS gating : PASS
5980 13:59:37.368980 RX DQ/DQS(RDDQC) : PASS
5981 13:59:37.371535 TX DQ/DQS : PASS
5982 13:59:37.374938 RX DATLAT : PASS
5983 13:59:37.375401 RX DQ/DQS(Engine): PASS
5984 13:59:37.378432 TX OE : NO K
5985 13:59:37.378985 All Pass.
5986 13:59:37.379342
5987 13:59:37.382280 CH 1, Rank 1
5988 13:59:37.382824 SW Impedance : PASS
5989 13:59:37.385162 DUTY Scan : NO K
5990 13:59:37.388569 ZQ Calibration : PASS
5991 13:59:37.389153 Jitter Meter : NO K
5992 13:59:37.392114 CBT Training : PASS
5993 13:59:37.395470 Write leveling : PASS
5994 13:59:37.395926 RX DQS gating : PASS
5995 13:59:37.398669 RX DQ/DQS(RDDQC) : PASS
5996 13:59:37.401871 TX DQ/DQS : PASS
5997 13:59:37.402329 RX DATLAT : PASS
5998 13:59:37.404816 RX DQ/DQS(Engine): PASS
5999 13:59:37.408150 TX OE : NO K
6000 13:59:37.408658 All Pass.
6001 13:59:37.409021
6002 13:59:37.409351 DramC Write-DBI off
6003 13:59:37.411536 PER_BANK_REFRESH: Hybrid Mode
6004 13:59:37.414745 TX_TRACKING: ON
6005 13:59:37.421892 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 13:59:37.425330 [FAST_K] Save calibration result to emmc
6007 13:59:37.431876 dramc_set_vcore_voltage set vcore to 650000
6008 13:59:37.432429 Read voltage for 400, 6
6009 13:59:37.435670 Vio18 = 0
6010 13:59:37.436173 Vcore = 650000
6011 13:59:37.436563 Vdram = 0
6012 13:59:37.436872 Vddq = 0
6013 13:59:37.438147 Vmddr = 0
6014 13:59:37.441887 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 13:59:37.448938 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 13:59:37.451538 MEM_TYPE=3, freq_sel=20
6017 13:59:37.452041 sv_algorithm_assistance_LP4_800
6018 13:59:37.458760 ============ PULL DRAM RESETB DOWN ============
6019 13:59:37.461984 ========== PULL DRAM RESETB DOWN end =========
6020 13:59:37.465172 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 13:59:37.468052 ===================================
6022 13:59:37.471268 LPDDR4 DRAM CONFIGURATION
6023 13:59:37.474503 ===================================
6024 13:59:37.478359 EX_ROW_EN[0] = 0x0
6025 13:59:37.478864 EX_ROW_EN[1] = 0x0
6026 13:59:37.481125 LP4Y_EN = 0x0
6027 13:59:37.481533 WORK_FSP = 0x0
6028 13:59:37.484228 WL = 0x2
6029 13:59:37.484652 RL = 0x2
6030 13:59:37.487968 BL = 0x2
6031 13:59:37.488485 RPST = 0x0
6032 13:59:37.491422 RD_PRE = 0x0
6033 13:59:37.491898 WR_PRE = 0x1
6034 13:59:37.494641 WR_PST = 0x0
6035 13:59:37.495052 DBI_WR = 0x0
6036 13:59:37.498182 DBI_RD = 0x0
6037 13:59:37.498594 OTF = 0x1
6038 13:59:37.501265 ===================================
6039 13:59:37.504644 ===================================
6040 13:59:37.507582 ANA top config
6041 13:59:37.511278 ===================================
6042 13:59:37.514567 DLL_ASYNC_EN = 0
6043 13:59:37.514980 ALL_SLAVE_EN = 1
6044 13:59:37.517946 NEW_RANK_MODE = 1
6045 13:59:37.521169 DLL_IDLE_MODE = 1
6046 13:59:37.524832 LP45_APHY_COMB_EN = 1
6047 13:59:37.527941 TX_ODT_DIS = 1
6048 13:59:37.528590 NEW_8X_MODE = 1
6049 13:59:37.530769 ===================================
6050 13:59:37.534183 ===================================
6051 13:59:37.537684 data_rate = 800
6052 13:59:37.540816 CKR = 1
6053 13:59:37.544362 DQ_P2S_RATIO = 4
6054 13:59:37.547939 ===================================
6055 13:59:37.550724 CA_P2S_RATIO = 4
6056 13:59:37.551139 DQ_CA_OPEN = 0
6057 13:59:37.554742 DQ_SEMI_OPEN = 1
6058 13:59:37.558017 CA_SEMI_OPEN = 1
6059 13:59:37.561082 CA_FULL_RATE = 0
6060 13:59:37.564451 DQ_CKDIV4_EN = 0
6061 13:59:37.567290 CA_CKDIV4_EN = 1
6062 13:59:37.571293 CA_PREDIV_EN = 0
6063 13:59:37.571809 PH8_DLY = 0
6064 13:59:37.574079 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 13:59:37.577330 DQ_AAMCK_DIV = 0
6066 13:59:37.580891 CA_AAMCK_DIV = 0
6067 13:59:37.584759 CA_ADMCK_DIV = 4
6068 13:59:37.585267 DQ_TRACK_CA_EN = 0
6069 13:59:37.587526 CA_PICK = 800
6070 13:59:37.590703 CA_MCKIO = 400
6071 13:59:37.594230 MCKIO_SEMI = 400
6072 13:59:37.597613 PLL_FREQ = 3016
6073 13:59:37.600996 DQ_UI_PI_RATIO = 32
6074 13:59:37.604346 CA_UI_PI_RATIO = 32
6075 13:59:37.607447 ===================================
6076 13:59:37.610909 ===================================
6077 13:59:37.611440 memory_type:LPDDR4
6078 13:59:37.614445 GP_NUM : 10
6079 13:59:37.617525 SRAM_EN : 1
6080 13:59:37.618049 MD32_EN : 0
6081 13:59:37.620809 ===================================
6082 13:59:37.624840 [ANA_INIT] >>>>>>>>>>>>>>
6083 13:59:37.627771 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 13:59:37.631184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 13:59:37.634030 ===================================
6086 13:59:37.637567 data_rate = 800,PCW = 0X7400
6087 13:59:37.640826 ===================================
6088 13:59:37.644023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 13:59:37.647100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 13:59:37.660792 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 13:59:37.664062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 13:59:37.667457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 13:59:37.670537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 13:59:37.673745 [ANA_INIT] flow start
6095 13:59:37.677634 [ANA_INIT] PLL >>>>>>>>
6096 13:59:37.678050 [ANA_INIT] PLL <<<<<<<<
6097 13:59:37.680995 [ANA_INIT] MIDPI >>>>>>>>
6098 13:59:37.684281 [ANA_INIT] MIDPI <<<<<<<<
6099 13:59:37.684815 [ANA_INIT] DLL >>>>>>>>
6100 13:59:37.687269 [ANA_INIT] flow end
6101 13:59:37.690823 ============ LP4 DIFF to SE enter ============
6102 13:59:37.693870 ============ LP4 DIFF to SE exit ============
6103 13:59:37.697127 [ANA_INIT] <<<<<<<<<<<<<
6104 13:59:37.700941 [Flow] Enable top DCM control >>>>>
6105 13:59:37.704282 [Flow] Enable top DCM control <<<<<
6106 13:59:37.707326 Enable DLL master slave shuffle
6107 13:59:37.714012 ==============================================================
6108 13:59:37.714510 Gating Mode config
6109 13:59:37.720989 ==============================================================
6110 13:59:37.721444 Config description:
6111 13:59:37.731089 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 13:59:37.737822 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 13:59:37.744352 SELPH_MODE 0: By rank 1: By Phase
6114 13:59:37.747258 ==============================================================
6115 13:59:37.751054 GAT_TRACK_EN = 0
6116 13:59:37.753966 RX_GATING_MODE = 2
6117 13:59:37.757722 RX_GATING_TRACK_MODE = 2
6118 13:59:37.760879 SELPH_MODE = 1
6119 13:59:37.763822 PICG_EARLY_EN = 1
6120 13:59:37.767115 VALID_LAT_VALUE = 1
6121 13:59:37.770634 ==============================================================
6122 13:59:37.774839 Enter into Gating configuration >>>>
6123 13:59:37.777885 Exit from Gating configuration <<<<
6124 13:59:37.781276 Enter into DVFS_PRE_config >>>>>
6125 13:59:37.794188 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 13:59:37.797427 Exit from DVFS_PRE_config <<<<<
6127 13:59:37.797885 Enter into PICG configuration >>>>
6128 13:59:37.800699 Exit from PICG configuration <<<<
6129 13:59:37.803844 [RX_INPUT] configuration >>>>>
6130 13:59:37.807742 [RX_INPUT] configuration <<<<<
6131 13:59:37.814354 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 13:59:37.817699 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 13:59:37.824546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 13:59:37.830710 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 13:59:37.837322 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 13:59:37.843867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 13:59:37.847026 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 13:59:37.850825 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 13:59:37.854098 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 13:59:37.860470 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 13:59:37.863775 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 13:59:37.866677 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 13:59:37.870005 ===================================
6144 13:59:37.873688 LPDDR4 DRAM CONFIGURATION
6145 13:59:37.876753 ===================================
6146 13:59:37.880228 EX_ROW_EN[0] = 0x0
6147 13:59:37.880822 EX_ROW_EN[1] = 0x0
6148 13:59:37.883860 LP4Y_EN = 0x0
6149 13:59:37.884452 WORK_FSP = 0x0
6150 13:59:37.887144 WL = 0x2
6151 13:59:37.887688 RL = 0x2
6152 13:59:37.890107 BL = 0x2
6153 13:59:37.890562 RPST = 0x0
6154 13:59:37.893093 RD_PRE = 0x0
6155 13:59:37.893549 WR_PRE = 0x1
6156 13:59:37.896584 WR_PST = 0x0
6157 13:59:37.897078 DBI_WR = 0x0
6158 13:59:37.899876 DBI_RD = 0x0
6159 13:59:37.900367 OTF = 0x1
6160 13:59:37.903335 ===================================
6161 13:59:37.910183 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 13:59:37.913557 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 13:59:37.916888 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 13:59:37.920188 ===================================
6165 13:59:37.923427 LPDDR4 DRAM CONFIGURATION
6166 13:59:37.926565 ===================================
6167 13:59:37.930458 EX_ROW_EN[0] = 0x10
6168 13:59:37.931007 EX_ROW_EN[1] = 0x0
6169 13:59:37.933538 LP4Y_EN = 0x0
6170 13:59:37.934084 WORK_FSP = 0x0
6171 13:59:37.936436 WL = 0x2
6172 13:59:37.936891 RL = 0x2
6173 13:59:37.940346 BL = 0x2
6174 13:59:37.940803 RPST = 0x0
6175 13:59:37.943456 RD_PRE = 0x0
6176 13:59:37.943909 WR_PRE = 0x1
6177 13:59:37.946785 WR_PST = 0x0
6178 13:59:37.947238 DBI_WR = 0x0
6179 13:59:37.949989 DBI_RD = 0x0
6180 13:59:37.950444 OTF = 0x1
6181 13:59:37.953533 ===================================
6182 13:59:37.960417 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 13:59:37.964109 nWR fixed to 30
6184 13:59:37.967685 [ModeRegInit_LP4] CH0 RK0
6185 13:59:37.968138 [ModeRegInit_LP4] CH0 RK1
6186 13:59:37.971075 [ModeRegInit_LP4] CH1 RK0
6187 13:59:37.974156 [ModeRegInit_LP4] CH1 RK1
6188 13:59:37.974630 match AC timing 19
6189 13:59:37.980748 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 13:59:37.984595 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 13:59:37.987936 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 13:59:37.994409 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 13:59:37.997461 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 13:59:37.997918 ==
6195 13:59:38.000644 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 13:59:38.004079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 13:59:38.004675 ==
6198 13:59:38.010960 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 13:59:38.017471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6200 13:59:38.020661 [CA 0] Center 36 (8~64) winsize 57
6201 13:59:38.024689 [CA 1] Center 36 (8~64) winsize 57
6202 13:59:38.027711 [CA 2] Center 36 (8~64) winsize 57
6203 13:59:38.031062 [CA 3] Center 36 (8~64) winsize 57
6204 13:59:38.031612 [CA 4] Center 36 (8~64) winsize 57
6205 13:59:38.034640 [CA 5] Center 36 (8~64) winsize 57
6206 13:59:38.035192
6207 13:59:38.040712 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6208 13:59:38.041163
6209 13:59:38.044265 [CATrainingPosCal] consider 1 rank data
6210 13:59:38.047216 u2DelayCellTimex100 = 270/100 ps
6211 13:59:38.051025 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 13:59:38.053982 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 13:59:38.057010 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 13:59:38.060810 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 13:59:38.064372 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 13:59:38.067170 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 13:59:38.067627
6218 13:59:38.070406 CA PerBit enable=1, Macro0, CA PI delay=36
6219 13:59:38.070861
6220 13:59:38.073731 [CBTSetCACLKResult] CA Dly = 36
6221 13:59:38.076969 CS Dly: 1 (0~32)
6222 13:59:38.077424 ==
6223 13:59:38.081071 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 13:59:38.084081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 13:59:38.084690 ==
6226 13:59:38.090380 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 13:59:38.093847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 13:59:38.097193 [CA 0] Center 36 (8~64) winsize 57
6229 13:59:38.100554 [CA 1] Center 36 (8~64) winsize 57
6230 13:59:38.103960 [CA 2] Center 36 (8~64) winsize 57
6231 13:59:38.107164 [CA 3] Center 36 (8~64) winsize 57
6232 13:59:38.110399 [CA 4] Center 36 (8~64) winsize 57
6233 13:59:38.114308 [CA 5] Center 36 (8~64) winsize 57
6234 13:59:38.114857
6235 13:59:38.117338 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 13:59:38.117796
6237 13:59:38.120721 [CATrainingPosCal] consider 2 rank data
6238 13:59:38.123557 u2DelayCellTimex100 = 270/100 ps
6239 13:59:38.126716 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 13:59:38.130623 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:59:38.137261 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 13:59:38.140378 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 13:59:38.143761 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 13:59:38.147155 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 13:59:38.147704
6246 13:59:38.150813 CA PerBit enable=1, Macro0, CA PI delay=36
6247 13:59:38.151402
6248 13:59:38.153517 [CBTSetCACLKResult] CA Dly = 36
6249 13:59:38.153973 CS Dly: 1 (0~32)
6250 13:59:38.154332
6251 13:59:38.156842 ----->DramcWriteLeveling(PI) begin...
6252 13:59:38.160865 ==
6253 13:59:38.161413 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 13:59:38.167204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 13:59:38.167686 ==
6256 13:59:38.170519 Write leveling (Byte 0): 40 => 8
6257 13:59:38.173579 Write leveling (Byte 1): 40 => 8
6258 13:59:38.174039 DramcWriteLeveling(PI) end<-----
6259 13:59:38.176827
6260 13:59:38.177280 ==
6261 13:59:38.179998 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 13:59:38.183896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 13:59:38.184490 ==
6264 13:59:38.186497 [Gating] SW mode calibration
6265 13:59:38.193625 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 13:59:38.196783 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 13:59:38.203779 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 13:59:38.206397 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 13:59:38.209966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 13:59:38.216903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 13:59:38.220176 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 13:59:38.223015 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 13:59:38.229569 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 13:59:38.232959 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 13:59:38.236578 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 13:59:38.239617 Total UI for P1: 0, mck2ui 16
6277 13:59:38.242862 best dqsien dly found for B0: ( 0, 14, 24)
6278 13:59:38.246511 Total UI for P1: 0, mck2ui 16
6279 13:59:38.249738 best dqsien dly found for B1: ( 0, 14, 24)
6280 13:59:38.253015 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 13:59:38.256386 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 13:59:38.260260
6283 13:59:38.263541 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 13:59:38.266839 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 13:59:38.269880 [Gating] SW calibration Done
6286 13:59:38.270336 ==
6287 13:59:38.273058 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 13:59:38.276234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 13:59:38.276825 ==
6290 13:59:38.277188 RX Vref Scan: 0
6291 13:59:38.277527
6292 13:59:38.280144 RX Vref 0 -> 0, step: 1
6293 13:59:38.280745
6294 13:59:38.282998 RX Delay -410 -> 252, step: 16
6295 13:59:38.286488 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6296 13:59:38.293290 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6297 13:59:38.296003 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6298 13:59:38.299510 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6299 13:59:38.302641 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6300 13:59:38.309193 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6301 13:59:38.312674 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6302 13:59:38.315955 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6303 13:59:38.319404 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6304 13:59:38.326402 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6305 13:59:38.329152 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6306 13:59:38.332898 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6307 13:59:38.336248 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6308 13:59:38.342668 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6309 13:59:38.345895 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6310 13:59:38.349660 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6311 13:59:38.350313 ==
6312 13:59:38.352973 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 13:59:38.356264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 13:59:38.359510 ==
6315 13:59:38.359955 DQS Delay:
6316 13:59:38.360347 DQS0 = 27, DQS1 = 35
6317 13:59:38.362533 DQM Delay:
6318 13:59:38.362978 DQM0 = 10, DQM1 = 12
6319 13:59:38.365882 DQ Delay:
6320 13:59:38.366384 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6321 13:59:38.369032 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6322 13:59:38.372624 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6323 13:59:38.375709 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6324 13:59:38.376452
6325 13:59:38.376825
6326 13:59:38.379717 ==
6327 13:59:38.380260 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 13:59:38.385971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 13:59:38.386521 ==
6330 13:59:38.386874
6331 13:59:38.387196
6332 13:59:38.389194 TX Vref Scan disable
6333 13:59:38.389646 == TX Byte 0 ==
6334 13:59:38.392235 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 13:59:38.399086 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 13:59:38.399710 == TX Byte 1 ==
6337 13:59:38.402638 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 13:59:38.406367 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 13:59:38.409064 ==
6340 13:59:38.412749 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 13:59:38.416162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 13:59:38.416774 ==
6343 13:59:38.417205
6344 13:59:38.417541
6345 13:59:38.419028 TX Vref Scan disable
6346 13:59:38.419474 == TX Byte 0 ==
6347 13:59:38.421733 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 13:59:38.428621 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 13:59:38.429154 == TX Byte 1 ==
6350 13:59:38.432447 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 13:59:38.438924 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 13:59:38.439471
6353 13:59:38.439824 [DATLAT]
6354 13:59:38.440148 Freq=400, CH0 RK0
6355 13:59:38.440531
6356 13:59:38.442043 DATLAT Default: 0xf
6357 13:59:38.445182 0, 0xFFFF, sum = 0
6358 13:59:38.445635 1, 0xFFFF, sum = 0
6359 13:59:38.448935 2, 0xFFFF, sum = 0
6360 13:59:38.449388 3, 0xFFFF, sum = 0
6361 13:59:38.452030 4, 0xFFFF, sum = 0
6362 13:59:38.452668 5, 0xFFFF, sum = 0
6363 13:59:38.455160 6, 0xFFFF, sum = 0
6364 13:59:38.455615 7, 0xFFFF, sum = 0
6365 13:59:38.459271 8, 0xFFFF, sum = 0
6366 13:59:38.459818 9, 0xFFFF, sum = 0
6367 13:59:38.461906 10, 0xFFFF, sum = 0
6368 13:59:38.462417 11, 0xFFFF, sum = 0
6369 13:59:38.465132 12, 0xFFFF, sum = 0
6370 13:59:38.465584 13, 0x0, sum = 1
6371 13:59:38.468537 14, 0x0, sum = 2
6372 13:59:38.468992 15, 0x0, sum = 3
6373 13:59:38.472390 16, 0x0, sum = 4
6374 13:59:38.472935 best_step = 14
6375 13:59:38.473327
6376 13:59:38.473844 ==
6377 13:59:38.475528 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 13:59:38.478862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 13:59:38.482357 ==
6380 13:59:38.482899 RX Vref Scan: 1
6381 13:59:38.483251
6382 13:59:38.485534 RX Vref 0 -> 0, step: 1
6383 13:59:38.486078
6384 13:59:38.488832 RX Delay -311 -> 252, step: 8
6385 13:59:38.489384
6386 13:59:38.491944 Set Vref, RX VrefLevel [Byte0]: 56
6387 13:59:38.495288 [Byte1]: 48
6388 13:59:38.495740
6389 13:59:38.498921 Final RX Vref Byte 0 = 56 to rank0
6390 13:59:38.502241 Final RX Vref Byte 1 = 48 to rank0
6391 13:59:38.505296 Final RX Vref Byte 0 = 56 to rank1
6392 13:59:38.508484 Final RX Vref Byte 1 = 48 to rank1==
6393 13:59:38.511937 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 13:59:38.514962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 13:59:38.515523 ==
6396 13:59:38.518838 DQS Delay:
6397 13:59:38.519383 DQS0 = 24, DQS1 = 32
6398 13:59:38.521898 DQM Delay:
6399 13:59:38.522345 DQM0 = 7, DQM1 = 9
6400 13:59:38.522698 DQ Delay:
6401 13:59:38.524679 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6402 13:59:38.528118 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6403 13:59:38.531738 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6404 13:59:38.534907 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6405 13:59:38.535359
6406 13:59:38.535709
6407 13:59:38.545194 [DQSOSCAuto] RK0, (LSB)MR18= 0xc5b2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6408 13:59:38.545745 CH0 RK0: MR19=C0C, MR18=C5B2
6409 13:59:38.551348 CH0_RK0: MR19=0xC0C, MR18=0xC5B2, DQSOSC=385, MR23=63, INC=398, DEC=265
6410 13:59:38.551939 ==
6411 13:59:38.555233 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 13:59:38.561625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 13:59:38.562397 ==
6414 13:59:38.563055 [Gating] SW mode calibration
6415 13:59:38.571352 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 13:59:38.574726 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 13:59:38.577959 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 13:59:38.585190 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 13:59:38.588261 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 13:59:38.591522 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 13:59:38.598260 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 13:59:38.601234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 13:59:38.604773 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 13:59:38.611721 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 13:59:38.614991 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 13:59:38.618198 Total UI for P1: 0, mck2ui 16
6427 13:59:38.622061 best dqsien dly found for B0: ( 0, 14, 24)
6428 13:59:38.624974 Total UI for P1: 0, mck2ui 16
6429 13:59:38.628390 best dqsien dly found for B1: ( 0, 14, 24)
6430 13:59:38.631870 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 13:59:38.635131 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 13:59:38.635684
6433 13:59:38.638517 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 13:59:38.641615 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 13:59:38.644793 [Gating] SW calibration Done
6436 13:59:38.645246 ==
6437 13:59:38.648182 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 13:59:38.654946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 13:59:38.655497 ==
6440 13:59:38.655853 RX Vref Scan: 0
6441 13:59:38.656182
6442 13:59:38.657929 RX Vref 0 -> 0, step: 1
6443 13:59:38.658395
6444 13:59:38.661518 RX Delay -410 -> 252, step: 16
6445 13:59:38.664847 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6446 13:59:38.668122 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6447 13:59:38.671349 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6448 13:59:38.677911 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6449 13:59:38.681727 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6450 13:59:38.684530 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6451 13:59:38.688405 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6452 13:59:38.694492 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6453 13:59:38.697995 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6454 13:59:38.701242 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6455 13:59:38.704603 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6456 13:59:38.711502 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6457 13:59:38.714756 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6458 13:59:38.718395 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6459 13:59:38.721247 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6460 13:59:38.728331 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6461 13:59:38.728870 ==
6462 13:59:38.731765 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 13:59:38.734832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 13:59:38.735378 ==
6465 13:59:38.735737 DQS Delay:
6466 13:59:38.738457 DQS0 = 27, DQS1 = 35
6467 13:59:38.739002 DQM Delay:
6468 13:59:38.741408 DQM0 = 11, DQM1 = 11
6469 13:59:38.741888 DQ Delay:
6470 13:59:38.744738 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6471 13:59:38.747775 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6472 13:59:38.751070 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6473 13:59:38.755027 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6474 13:59:38.755578
6475 13:59:38.755935
6476 13:59:38.756266 ==
6477 13:59:38.757761 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 13:59:38.761221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 13:59:38.761800 ==
6480 13:59:38.762171
6481 13:59:38.764562
6482 13:59:38.765099 TX Vref Scan disable
6483 13:59:38.767423 == TX Byte 0 ==
6484 13:59:38.771600 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6485 13:59:38.774401 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6486 13:59:38.777470 == TX Byte 1 ==
6487 13:59:38.781019 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6488 13:59:38.784560 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6489 13:59:38.785141 ==
6490 13:59:38.787903 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 13:59:38.791288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 13:59:38.791866 ==
6493 13:59:38.792230
6494 13:59:38.794274
6495 13:59:38.794765 TX Vref Scan disable
6496 13:59:38.797866 == TX Byte 0 ==
6497 13:59:38.801304 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6498 13:59:38.804529 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6499 13:59:38.807611 == TX Byte 1 ==
6500 13:59:38.810960 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6501 13:59:38.814626 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6502 13:59:38.815086
6503 13:59:38.815484 [DATLAT]
6504 13:59:38.817584 Freq=400, CH0 RK1
6505 13:59:38.818038
6506 13:59:38.818394 DATLAT Default: 0xe
6507 13:59:38.821003 0, 0xFFFF, sum = 0
6508 13:59:38.821497 1, 0xFFFF, sum = 0
6509 13:59:38.824094 2, 0xFFFF, sum = 0
6510 13:59:38.827809 3, 0xFFFF, sum = 0
6511 13:59:38.828413 4, 0xFFFF, sum = 0
6512 13:59:38.830812 5, 0xFFFF, sum = 0
6513 13:59:38.831276 6, 0xFFFF, sum = 0
6514 13:59:38.834161 7, 0xFFFF, sum = 0
6515 13:59:38.834625 8, 0xFFFF, sum = 0
6516 13:59:38.837822 9, 0xFFFF, sum = 0
6517 13:59:38.838378 10, 0xFFFF, sum = 0
6518 13:59:38.840743 11, 0xFFFF, sum = 0
6519 13:59:38.841204 12, 0xFFFF, sum = 0
6520 13:59:38.844633 13, 0x0, sum = 1
6521 13:59:38.845189 14, 0x0, sum = 2
6522 13:59:38.847823 15, 0x0, sum = 3
6523 13:59:38.848405 16, 0x0, sum = 4
6524 13:59:38.850992 best_step = 14
6525 13:59:38.851538
6526 13:59:38.851898 ==
6527 13:59:38.854062 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 13:59:38.857451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 13:59:38.858007 ==
6530 13:59:38.858370 RX Vref Scan: 0
6531 13:59:38.860918
6532 13:59:38.861372 RX Vref 0 -> 0, step: 1
6533 13:59:38.861731
6534 13:59:38.864231 RX Delay -311 -> 252, step: 8
6535 13:59:38.871299 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6536 13:59:38.874938 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6537 13:59:38.878030 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6538 13:59:38.881267 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6539 13:59:38.888210 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6540 13:59:38.891621 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6541 13:59:38.894377 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6542 13:59:38.898163 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6543 13:59:38.904448 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6544 13:59:38.907985 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6545 13:59:38.911772 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6546 13:59:38.914628 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6547 13:59:38.921078 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6548 13:59:38.924352 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6549 13:59:38.927914 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6550 13:59:38.935094 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6551 13:59:38.935646 ==
6552 13:59:38.938208 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 13:59:38.942272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 13:59:38.942733 ==
6555 13:59:38.943090 DQS Delay:
6556 13:59:38.944249 DQS0 = 24, DQS1 = 32
6557 13:59:38.944747 DQM Delay:
6558 13:59:38.947593 DQM0 = 8, DQM1 = 10
6559 13:59:38.948059 DQ Delay:
6560 13:59:38.951165 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6561 13:59:38.954721 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6562 13:59:38.958104 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6563 13:59:38.961038 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6564 13:59:38.961497
6565 13:59:38.961852
6566 13:59:38.968341 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6567 13:59:38.971489 CH0 RK1: MR19=C0C, MR18=BC5B
6568 13:59:38.977769 CH0_RK1: MR19=0xC0C, MR18=0xBC5B, DQSOSC=386, MR23=63, INC=396, DEC=264
6569 13:59:38.981374 [RxdqsGatingPostProcess] freq 400
6570 13:59:38.984533 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 13:59:38.987987 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 13:59:38.991580 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 13:59:38.994638 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 13:59:38.998443 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 13:59:39.001360 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 13:59:39.004505 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 13:59:39.008695 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 13:59:39.011718 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 13:59:39.014925 Pre-setting of DQS Precalculation
6580 13:59:39.017917 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 13:59:39.018375 ==
6582 13:59:39.021077 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 13:59:39.027774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 13:59:39.028378 ==
6585 13:59:39.031511 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 13:59:39.038253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6587 13:59:39.041316 [CA 0] Center 36 (8~64) winsize 57
6588 13:59:39.044587 [CA 1] Center 36 (8~64) winsize 57
6589 13:59:39.047872 [CA 2] Center 36 (8~64) winsize 57
6590 13:59:39.051297 [CA 3] Center 36 (8~64) winsize 57
6591 13:59:39.054174 [CA 4] Center 36 (8~64) winsize 57
6592 13:59:39.058170 [CA 5] Center 36 (8~64) winsize 57
6593 13:59:39.058721
6594 13:59:39.061103 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6595 13:59:39.061652
6596 13:59:39.064052 [CATrainingPosCal] consider 1 rank data
6597 13:59:39.068171 u2DelayCellTimex100 = 270/100 ps
6598 13:59:39.070757 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 13:59:39.074549 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 13:59:39.077571 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 13:59:39.080486 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 13:59:39.084241 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 13:59:39.091353 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 13:59:39.091904
6605 13:59:39.094455 CA PerBit enable=1, Macro0, CA PI delay=36
6606 13:59:39.094985
6607 13:59:39.097616 [CBTSetCACLKResult] CA Dly = 36
6608 13:59:39.098073 CS Dly: 1 (0~32)
6609 13:59:39.098432 ==
6610 13:59:39.100609 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 13:59:39.104238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 13:59:39.107481 ==
6613 13:59:39.110815 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 13:59:39.117600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 13:59:39.120545 [CA 0] Center 36 (8~64) winsize 57
6616 13:59:39.124677 [CA 1] Center 36 (8~64) winsize 57
6617 13:59:39.127737 [CA 2] Center 36 (8~64) winsize 57
6618 13:59:39.130577 [CA 3] Center 36 (8~64) winsize 57
6619 13:59:39.134004 [CA 4] Center 36 (8~64) winsize 57
6620 13:59:39.137493 [CA 5] Center 36 (8~64) winsize 57
6621 13:59:39.138047
6622 13:59:39.140889 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 13:59:39.141445
6624 13:59:39.144357 [CATrainingPosCal] consider 2 rank data
6625 13:59:39.148046 u2DelayCellTimex100 = 270/100 ps
6626 13:59:39.150295 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 13:59:39.154176 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:59:39.157613 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 13:59:39.160700 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 13:59:39.163966 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 13:59:39.167766 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 13:59:39.168349
6633 13:59:39.170531 CA PerBit enable=1, Macro0, CA PI delay=36
6634 13:59:39.170989
6635 13:59:39.174123 [CBTSetCACLKResult] CA Dly = 36
6636 13:59:39.177061 CS Dly: 1 (0~32)
6637 13:59:39.177627
6638 13:59:39.180374 ----->DramcWriteLeveling(PI) begin...
6639 13:59:39.180837 ==
6640 13:59:39.184008 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 13:59:39.187228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 13:59:39.187684 ==
6643 13:59:39.190650 Write leveling (Byte 0): 40 => 8
6644 13:59:39.193627 Write leveling (Byte 1): 40 => 8
6645 13:59:39.196910 DramcWriteLeveling(PI) end<-----
6646 13:59:39.197550
6647 13:59:39.197936 ==
6648 13:59:39.200513 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 13:59:39.203714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 13:59:39.204260 ==
6651 13:59:39.207149 [Gating] SW mode calibration
6652 13:59:39.213593 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 13:59:39.220277 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 13:59:39.223444 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 13:59:39.227259 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 13:59:39.234071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 13:59:39.237178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 13:59:39.240756 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 13:59:39.247005 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 13:59:39.250541 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 13:59:39.253395 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 13:59:39.260121 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 13:59:39.264019 Total UI for P1: 0, mck2ui 16
6664 13:59:39.267094 best dqsien dly found for B0: ( 0, 14, 24)
6665 13:59:39.270095 Total UI for P1: 0, mck2ui 16
6666 13:59:39.273671 best dqsien dly found for B1: ( 0, 14, 24)
6667 13:59:39.276918 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 13:59:39.280349 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 13:59:39.280808
6670 13:59:39.283322 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 13:59:39.287043 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 13:59:39.290141 [Gating] SW calibration Done
6673 13:59:39.290687 ==
6674 13:59:39.293840 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 13:59:39.297053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 13:59:39.297547 ==
6677 13:59:39.300412 RX Vref Scan: 0
6678 13:59:39.300963
6679 13:59:39.303400 RX Vref 0 -> 0, step: 1
6680 13:59:39.303953
6681 13:59:39.304348 RX Delay -410 -> 252, step: 16
6682 13:59:39.309962 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6683 13:59:39.313303 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6684 13:59:39.316419 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6685 13:59:39.319948 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6686 13:59:39.326445 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6687 13:59:39.329835 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6688 13:59:39.332989 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6689 13:59:39.336856 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6690 13:59:39.343370 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6691 13:59:39.346369 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6692 13:59:39.350085 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6693 13:59:39.353169 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6694 13:59:39.359858 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6695 13:59:39.363351 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6696 13:59:39.366461 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6697 13:59:39.373169 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6698 13:59:39.373673 ==
6699 13:59:39.376958 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 13:59:39.379914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 13:59:39.380383 ==
6702 13:59:39.380734 DQS Delay:
6703 13:59:39.383309 DQS0 = 27, DQS1 = 35
6704 13:59:39.383815 DQM Delay:
6705 13:59:39.386232 DQM0 = 11, DQM1 = 13
6706 13:59:39.386643 DQ Delay:
6707 13:59:39.390147 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6708 13:59:39.392925 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6709 13:59:39.396265 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6710 13:59:39.399576 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6711 13:59:39.400155
6712 13:59:39.400531
6713 13:59:39.400836 ==
6714 13:59:39.403542 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 13:59:39.405967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 13:59:39.406385 ==
6717 13:59:39.406706
6718 13:59:39.407002
6719 13:59:39.409847 TX Vref Scan disable
6720 13:59:39.410259 == TX Byte 0 ==
6721 13:59:39.416905 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 13:59:39.419577 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 13:59:39.419992 == TX Byte 1 ==
6724 13:59:39.426508 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 13:59:39.429791 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 13:59:39.430301 ==
6727 13:59:39.433066 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 13:59:39.436232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 13:59:39.436691 ==
6730 13:59:39.437021
6731 13:59:39.437323
6732 13:59:39.439608 TX Vref Scan disable
6733 13:59:39.440110 == TX Byte 0 ==
6734 13:59:39.446449 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 13:59:39.449998 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 13:59:39.450528 == TX Byte 1 ==
6737 13:59:39.456240 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 13:59:39.460058 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 13:59:39.460629
6740 13:59:39.460986 [DATLAT]
6741 13:59:39.462844 Freq=400, CH1 RK0
6742 13:59:39.463385
6743 13:59:39.463715 DATLAT Default: 0xf
6744 13:59:39.465957 0, 0xFFFF, sum = 0
6745 13:59:39.466384 1, 0xFFFF, sum = 0
6746 13:59:39.469957 2, 0xFFFF, sum = 0
6747 13:59:39.470369 3, 0xFFFF, sum = 0
6748 13:59:39.472657 4, 0xFFFF, sum = 0
6749 13:59:39.473103 5, 0xFFFF, sum = 0
6750 13:59:39.476773 6, 0xFFFF, sum = 0
6751 13:59:39.477324 7, 0xFFFF, sum = 0
6752 13:59:39.479621 8, 0xFFFF, sum = 0
6753 13:59:39.480035 9, 0xFFFF, sum = 0
6754 13:59:39.483628 10, 0xFFFF, sum = 0
6755 13:59:39.486153 11, 0xFFFF, sum = 0
6756 13:59:39.486678 12, 0xFFFF, sum = 0
6757 13:59:39.490022 13, 0x0, sum = 1
6758 13:59:39.490486 14, 0x0, sum = 2
6759 13:59:39.490814 15, 0x0, sum = 3
6760 13:59:39.492996 16, 0x0, sum = 4
6761 13:59:39.493426 best_step = 14
6762 13:59:39.493746
6763 13:59:39.494044 ==
6764 13:59:39.496074 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 13:59:39.502589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 13:59:39.503000 ==
6767 13:59:39.503324 RX Vref Scan: 1
6768 13:59:39.503619
6769 13:59:39.505917 RX Vref 0 -> 0, step: 1
6770 13:59:39.506325
6771 13:59:39.509075 RX Delay -311 -> 252, step: 8
6772 13:59:39.509483
6773 13:59:39.512413 Set Vref, RX VrefLevel [Byte0]: 56
6774 13:59:39.516012 [Byte1]: 48
6775 13:59:39.519551
6776 13:59:39.519957 Final RX Vref Byte 0 = 56 to rank0
6777 13:59:39.522857 Final RX Vref Byte 1 = 48 to rank0
6778 13:59:39.525991 Final RX Vref Byte 0 = 56 to rank1
6779 13:59:39.528886 Final RX Vref Byte 1 = 48 to rank1==
6780 13:59:39.532239 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 13:59:39.538889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 13:59:39.539429 ==
6783 13:59:39.539755 DQS Delay:
6784 13:59:39.542185 DQS0 = 28, DQS1 = 32
6785 13:59:39.542595 DQM Delay:
6786 13:59:39.542913 DQM0 = 10, DQM1 = 11
6787 13:59:39.545465 DQ Delay:
6788 13:59:39.548750 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6789 13:59:39.549160 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6790 13:59:39.552523 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6791 13:59:39.555543 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6792 13:59:39.555950
6793 13:59:39.559171
6794 13:59:39.565950 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6795 13:59:39.569275 CH1 RK0: MR19=C0C, MR18=8FC8
6796 13:59:39.575669 CH1_RK0: MR19=0xC0C, MR18=0x8FC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6797 13:59:39.576081 ==
6798 13:59:39.578822 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 13:59:39.582425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 13:59:39.582848 ==
6801 13:59:39.585526 [Gating] SW mode calibration
6802 13:59:39.592272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 13:59:39.595363 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 13:59:39.602061 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 13:59:39.605341 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 13:59:39.608930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 13:59:39.616075 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 13:59:39.619054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 13:59:39.622602 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 13:59:39.628797 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 13:59:39.632679 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 13:59:39.635804 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 13:59:39.639230 Total UI for P1: 0, mck2ui 16
6814 13:59:39.642924 best dqsien dly found for B0: ( 0, 14, 24)
6815 13:59:39.645854 Total UI for P1: 0, mck2ui 16
6816 13:59:39.649072 best dqsien dly found for B1: ( 0, 14, 24)
6817 13:59:39.652488 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 13:59:39.655557 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 13:59:39.656188
6820 13:59:39.662531 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 13:59:39.666073 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 13:59:39.669122 [Gating] SW calibration Done
6823 13:59:39.669580 ==
6824 13:59:39.672008 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 13:59:39.675751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 13:59:39.676352 ==
6827 13:59:39.676725 RX Vref Scan: 0
6828 13:59:39.677065
6829 13:59:39.678668 RX Vref 0 -> 0, step: 1
6830 13:59:39.679124
6831 13:59:39.681863 RX Delay -410 -> 252, step: 16
6832 13:59:39.685224 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6833 13:59:39.692725 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6834 13:59:39.695817 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6835 13:59:39.698529 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6836 13:59:39.701662 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6837 13:59:39.708851 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6838 13:59:39.711657 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6839 13:59:39.715075 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6840 13:59:39.718444 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6841 13:59:39.725314 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6842 13:59:39.728785 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6843 13:59:39.731621 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6844 13:59:39.734719 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6845 13:59:39.741535 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6846 13:59:39.745019 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6847 13:59:39.748191 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6848 13:59:39.748678 ==
6849 13:59:39.751766 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 13:59:39.755219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 13:59:39.758266 ==
6852 13:59:39.758816 DQS Delay:
6853 13:59:39.759173 DQS0 = 35, DQS1 = 35
6854 13:59:39.761989 DQM Delay:
6855 13:59:39.762538 DQM0 = 18, DQM1 = 14
6856 13:59:39.764477 DQ Delay:
6857 13:59:39.768154 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6858 13:59:39.768808 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6859 13:59:39.771538 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6860 13:59:39.775383 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6861 13:59:39.777839
6862 13:59:39.778286
6863 13:59:39.778639 ==
6864 13:59:39.781274 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 13:59:39.784835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 13:59:39.785292 ==
6867 13:59:39.785644
6868 13:59:39.785972
6869 13:59:39.788327 TX Vref Scan disable
6870 13:59:39.788782 == TX Byte 0 ==
6871 13:59:39.791873 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6872 13:59:39.797930 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6873 13:59:39.798424 == TX Byte 1 ==
6874 13:59:39.801053 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6875 13:59:39.807928 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6876 13:59:39.808533 ==
6877 13:59:39.811821 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 13:59:39.814514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 13:59:39.815065 ==
6880 13:59:39.815423
6881 13:59:39.815752
6882 13:59:39.817457 TX Vref Scan disable
6883 13:59:39.817908 == TX Byte 0 ==
6884 13:59:39.821347 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6885 13:59:39.827616 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6886 13:59:39.828157 == TX Byte 1 ==
6887 13:59:39.831199 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6888 13:59:39.837993 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6889 13:59:39.838543
6890 13:59:39.838904 [DATLAT]
6891 13:59:39.839240 Freq=400, CH1 RK1
6892 13:59:39.841024
6893 13:59:39.841478 DATLAT Default: 0xe
6894 13:59:39.844195 0, 0xFFFF, sum = 0
6895 13:59:39.844715 1, 0xFFFF, sum = 0
6896 13:59:39.848067 2, 0xFFFF, sum = 0
6897 13:59:39.848752 3, 0xFFFF, sum = 0
6898 13:59:39.851111 4, 0xFFFF, sum = 0
6899 13:59:39.851579 5, 0xFFFF, sum = 0
6900 13:59:39.854332 6, 0xFFFF, sum = 0
6901 13:59:39.854846 7, 0xFFFF, sum = 0
6902 13:59:39.858067 8, 0xFFFF, sum = 0
6903 13:59:39.858640 9, 0xFFFF, sum = 0
6904 13:59:39.861216 10, 0xFFFF, sum = 0
6905 13:59:39.861787 11, 0xFFFF, sum = 0
6906 13:59:39.864358 12, 0xFFFF, sum = 0
6907 13:59:39.864842 13, 0x0, sum = 1
6908 13:59:39.867576 14, 0x0, sum = 2
6909 13:59:39.868057 15, 0x0, sum = 3
6910 13:59:39.871273 16, 0x0, sum = 4
6911 13:59:39.871708 best_step = 14
6912 13:59:39.872145
6913 13:59:39.872605 ==
6914 13:59:39.874592 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 13:59:39.881126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 13:59:39.881701 ==
6917 13:59:39.882150 RX Vref Scan: 0
6918 13:59:39.882697
6919 13:59:39.884257 RX Vref 0 -> 0, step: 1
6920 13:59:39.884735
6921 13:59:39.887689 RX Delay -311 -> 252, step: 8
6922 13:59:39.894025 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6923 13:59:39.897587 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6924 13:59:39.900933 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6925 13:59:39.904156 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6926 13:59:39.908440 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6927 13:59:39.914694 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6928 13:59:39.917819 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6929 13:59:39.921087 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6930 13:59:39.924906 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6931 13:59:39.931047 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6932 13:59:39.934594 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6933 13:59:39.937498 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6934 13:59:39.940789 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6935 13:59:39.947754 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6936 13:59:39.951455 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6937 13:59:39.953864 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6938 13:59:39.954325 ==
6939 13:59:39.957975 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 13:59:39.964668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 13:59:39.965223 ==
6942 13:59:39.965591 DQS Delay:
6943 13:59:39.967321 DQS0 = 28, DQS1 = 32
6944 13:59:39.967777 DQM Delay:
6945 13:59:39.968136 DQM0 = 11, DQM1 = 12
6946 13:59:39.971099 DQ Delay:
6947 13:59:39.974165 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6948 13:59:39.974731 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6949 13:59:39.977614 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6950 13:59:39.980906 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6951 13:59:39.981515
6952 13:59:39.983882
6953 13:59:39.990798 [DQSOSCAuto] RK1, (LSB)MR18= 0xc558, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6954 13:59:39.993969 CH1 RK1: MR19=C0C, MR18=C558
6955 13:59:40.000439 CH1_RK1: MR19=0xC0C, MR18=0xC558, DQSOSC=385, MR23=63, INC=398, DEC=265
6956 13:59:40.003966 [RxdqsGatingPostProcess] freq 400
6957 13:59:40.007282 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 13:59:40.010312 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 13:59:40.014124 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 13:59:40.017430 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 13:59:40.020576 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 13:59:40.023906 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 13:59:40.027406 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 13:59:40.030564 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 13:59:40.033829 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 13:59:40.037523 Pre-setting of DQS Precalculation
6967 13:59:40.040934 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 13:59:40.047127 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 13:59:40.057093 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 13:59:40.057604
6971 13:59:40.058046
6972 13:59:40.058461 [Calibration Summary] 800 Mbps
6973 13:59:40.060662 CH 0, Rank 0
6974 13:59:40.063794 SW Impedance : PASS
6975 13:59:40.064355 DUTY Scan : NO K
6976 13:59:40.066868 ZQ Calibration : PASS
6977 13:59:40.067299 Jitter Meter : NO K
6978 13:59:40.070470 CBT Training : PASS
6979 13:59:40.073451 Write leveling : PASS
6980 13:59:40.073884 RX DQS gating : PASS
6981 13:59:40.076970 RX DQ/DQS(RDDQC) : PASS
6982 13:59:40.080402 TX DQ/DQS : PASS
6983 13:59:40.080932 RX DATLAT : PASS
6984 13:59:40.083772 RX DQ/DQS(Engine): PASS
6985 13:59:40.086681 TX OE : NO K
6986 13:59:40.087117 All Pass.
6987 13:59:40.087553
6988 13:59:40.087967 CH 0, Rank 1
6989 13:59:40.090134 SW Impedance : PASS
6990 13:59:40.093179 DUTY Scan : NO K
6991 13:59:40.093613 ZQ Calibration : PASS
6992 13:59:40.096914 Jitter Meter : NO K
6993 13:59:40.100034 CBT Training : PASS
6994 13:59:40.100502 Write leveling : NO K
6995 13:59:40.103312 RX DQS gating : PASS
6996 13:59:40.107349 RX DQ/DQS(RDDQC) : PASS
6997 13:59:40.107855 TX DQ/DQS : PASS
6998 13:59:40.110359 RX DATLAT : PASS
6999 13:59:40.110884 RX DQ/DQS(Engine): PASS
7000 13:59:40.113250 TX OE : NO K
7001 13:59:40.113671 All Pass.
7002 13:59:40.114014
7003 13:59:40.117075 CH 1, Rank 0
7004 13:59:40.120134 SW Impedance : PASS
7005 13:59:40.120759 DUTY Scan : NO K
7006 13:59:40.123527 ZQ Calibration : PASS
7007 13:59:40.123956 Jitter Meter : NO K
7008 13:59:40.126856 CBT Training : PASS
7009 13:59:40.130148 Write leveling : PASS
7010 13:59:40.130610 RX DQS gating : PASS
7011 13:59:40.133741 RX DQ/DQS(RDDQC) : PASS
7012 13:59:40.136831 TX DQ/DQS : PASS
7013 13:59:40.137374 RX DATLAT : PASS
7014 13:59:40.140700 RX DQ/DQS(Engine): PASS
7015 13:59:40.143652 TX OE : NO K
7016 13:59:40.144199 All Pass.
7017 13:59:40.144743
7018 13:59:40.145072 CH 1, Rank 1
7019 13:59:40.146673 SW Impedance : PASS
7020 13:59:40.149934 DUTY Scan : NO K
7021 13:59:40.150351 ZQ Calibration : PASS
7022 13:59:40.153430 Jitter Meter : NO K
7023 13:59:40.156805 CBT Training : PASS
7024 13:59:40.157222 Write leveling : NO K
7025 13:59:40.160225 RX DQS gating : PASS
7026 13:59:40.163554 RX DQ/DQS(RDDQC) : PASS
7027 13:59:40.164058 TX DQ/DQS : PASS
7028 13:59:40.166740 RX DATLAT : PASS
7029 13:59:40.167246 RX DQ/DQS(Engine): PASS
7030 13:59:40.169981 TX OE : NO K
7031 13:59:40.170488 All Pass.
7032 13:59:40.170818
7033 13:59:40.173522 DramC Write-DBI off
7034 13:59:40.177180 PER_BANK_REFRESH: Hybrid Mode
7035 13:59:40.177689 TX_TRACKING: ON
7036 13:59:40.186867 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 13:59:40.190291 [FAST_K] Save calibration result to emmc
7038 13:59:40.193096 dramc_set_vcore_voltage set vcore to 725000
7039 13:59:40.196044 Read voltage for 1600, 0
7040 13:59:40.196504 Vio18 = 0
7041 13:59:40.199768 Vcore = 725000
7042 13:59:40.200279 Vdram = 0
7043 13:59:40.200673 Vddq = 0
7044 13:59:40.200984 Vmddr = 0
7045 13:59:40.206444 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 13:59:40.213385 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 13:59:40.213821 MEM_TYPE=3, freq_sel=13
7048 13:59:40.216693 sv_algorithm_assistance_LP4_3733
7049 13:59:40.219753 ============ PULL DRAM RESETB DOWN ============
7050 13:59:40.226334 ========== PULL DRAM RESETB DOWN end =========
7051 13:59:40.229961 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 13:59:40.233081 ===================================
7053 13:59:40.236572 LPDDR4 DRAM CONFIGURATION
7054 13:59:40.239795 ===================================
7055 13:59:40.240419 EX_ROW_EN[0] = 0x0
7056 13:59:40.243078 EX_ROW_EN[1] = 0x0
7057 13:59:40.243651 LP4Y_EN = 0x0
7058 13:59:40.246345 WORK_FSP = 0x1
7059 13:59:40.246818 WL = 0x5
7060 13:59:40.249735 RL = 0x5
7061 13:59:40.250208 BL = 0x2
7062 13:59:40.252985 RPST = 0x0
7063 13:59:40.253425 RD_PRE = 0x0
7064 13:59:40.256390 WR_PRE = 0x1
7065 13:59:40.259395 WR_PST = 0x1
7066 13:59:40.259813 DBI_WR = 0x0
7067 13:59:40.263038 DBI_RD = 0x0
7068 13:59:40.263539 OTF = 0x1
7069 13:59:40.265888 ===================================
7070 13:59:40.269446 ===================================
7071 13:59:40.269867 ANA top config
7072 13:59:40.272967 ===================================
7073 13:59:40.276203 DLL_ASYNC_EN = 0
7074 13:59:40.279666 ALL_SLAVE_EN = 0
7075 13:59:40.282840 NEW_RANK_MODE = 1
7076 13:59:40.286233 DLL_IDLE_MODE = 1
7077 13:59:40.286651 LP45_APHY_COMB_EN = 1
7078 13:59:40.289328 TX_ODT_DIS = 0
7079 13:59:40.292704 NEW_8X_MODE = 1
7080 13:59:40.295868 ===================================
7081 13:59:40.299857 ===================================
7082 13:59:40.302823 data_rate = 3200
7083 13:59:40.306335 CKR = 1
7084 13:59:40.306767 DQ_P2S_RATIO = 8
7085 13:59:40.309451 ===================================
7086 13:59:40.313027 CA_P2S_RATIO = 8
7087 13:59:40.316602 DQ_CA_OPEN = 0
7088 13:59:40.319655 DQ_SEMI_OPEN = 0
7089 13:59:40.322836 CA_SEMI_OPEN = 0
7090 13:59:40.326007 CA_FULL_RATE = 0
7091 13:59:40.326442 DQ_CKDIV4_EN = 0
7092 13:59:40.329214 CA_CKDIV4_EN = 0
7093 13:59:40.332569 CA_PREDIV_EN = 0
7094 13:59:40.336126 PH8_DLY = 12
7095 13:59:40.339977 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 13:59:40.343108 DQ_AAMCK_DIV = 4
7097 13:59:40.343628 CA_AAMCK_DIV = 4
7098 13:59:40.345997 CA_ADMCK_DIV = 4
7099 13:59:40.349227 DQ_TRACK_CA_EN = 0
7100 13:59:40.353049 CA_PICK = 1600
7101 13:59:40.356075 CA_MCKIO = 1600
7102 13:59:40.359750 MCKIO_SEMI = 0
7103 13:59:40.362704 PLL_FREQ = 3068
7104 13:59:40.363137 DQ_UI_PI_RATIO = 32
7105 13:59:40.366330 CA_UI_PI_RATIO = 0
7106 13:59:40.369559 ===================================
7107 13:59:40.372666 ===================================
7108 13:59:40.376378 memory_type:LPDDR4
7109 13:59:40.379336 GP_NUM : 10
7110 13:59:40.379857 SRAM_EN : 1
7111 13:59:40.382417 MD32_EN : 0
7112 13:59:40.386124 ===================================
7113 13:59:40.389097 [ANA_INIT] >>>>>>>>>>>>>>
7114 13:59:40.389527 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 13:59:40.392686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 13:59:40.395973 ===================================
7117 13:59:40.399555 data_rate = 3200,PCW = 0X7600
7118 13:59:40.402754 ===================================
7119 13:59:40.406124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 13:59:40.412485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 13:59:40.419218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 13:59:40.422294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 13:59:40.425621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 13:59:40.429034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 13:59:40.432387 [ANA_INIT] flow start
7126 13:59:40.432823 [ANA_INIT] PLL >>>>>>>>
7127 13:59:40.435811 [ANA_INIT] PLL <<<<<<<<
7128 13:59:40.439295 [ANA_INIT] MIDPI >>>>>>>>
7129 13:59:40.439726 [ANA_INIT] MIDPI <<<<<<<<
7130 13:59:40.442847 [ANA_INIT] DLL >>>>>>>>
7131 13:59:40.445762 [ANA_INIT] DLL <<<<<<<<
7132 13:59:40.446205 [ANA_INIT] flow end
7133 13:59:40.452381 ============ LP4 DIFF to SE enter ============
7134 13:59:40.455487 ============ LP4 DIFF to SE exit ============
7135 13:59:40.459018 [ANA_INIT] <<<<<<<<<<<<<
7136 13:59:40.462672 [Flow] Enable top DCM control >>>>>
7137 13:59:40.465683 [Flow] Enable top DCM control <<<<<
7138 13:59:40.466116 Enable DLL master slave shuffle
7139 13:59:40.472448 ==============================================================
7140 13:59:40.475808 Gating Mode config
7141 13:59:40.479048 ==============================================================
7142 13:59:40.482422 Config description:
7143 13:59:40.492168 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 13:59:40.499217 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 13:59:40.502001 SELPH_MODE 0: By rank 1: By Phase
7146 13:59:40.508980 ==============================================================
7147 13:59:40.512464 GAT_TRACK_EN = 1
7148 13:59:40.515702 RX_GATING_MODE = 2
7149 13:59:40.519323 RX_GATING_TRACK_MODE = 2
7150 13:59:40.522311 SELPH_MODE = 1
7151 13:59:40.522902 PICG_EARLY_EN = 1
7152 13:59:40.525507 VALID_LAT_VALUE = 1
7153 13:59:40.532037 ==============================================================
7154 13:59:40.535381 Enter into Gating configuration >>>>
7155 13:59:40.538652 Exit from Gating configuration <<<<
7156 13:59:40.541933 Enter into DVFS_PRE_config >>>>>
7157 13:59:40.551440 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 13:59:40.555468 Exit from DVFS_PRE_config <<<<<
7159 13:59:40.558358 Enter into PICG configuration >>>>
7160 13:59:40.561759 Exit from PICG configuration <<<<
7161 13:59:40.565288 [RX_INPUT] configuration >>>>>
7162 13:59:40.568475 [RX_INPUT] configuration <<<<<
7163 13:59:40.571816 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 13:59:40.578544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 13:59:40.585062 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 13:59:40.591569 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 13:59:40.598136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 13:59:40.601270 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 13:59:40.608425 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 13:59:40.611433 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 13:59:40.614955 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 13:59:40.618087 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 13:59:40.624443 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 13:59:40.627784 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 13:59:40.631586 ===================================
7176 13:59:40.634842 LPDDR4 DRAM CONFIGURATION
7177 13:59:40.638079 ===================================
7178 13:59:40.638496 EX_ROW_EN[0] = 0x0
7179 13:59:40.641366 EX_ROW_EN[1] = 0x0
7180 13:59:40.641780 LP4Y_EN = 0x0
7181 13:59:40.644979 WORK_FSP = 0x1
7182 13:59:40.645499 WL = 0x5
7183 13:59:40.647698 RL = 0x5
7184 13:59:40.648178 BL = 0x2
7185 13:59:40.651334 RPST = 0x0
7186 13:59:40.651913 RD_PRE = 0x0
7187 13:59:40.654607 WR_PRE = 0x1
7188 13:59:40.657839 WR_PST = 0x1
7189 13:59:40.658251 DBI_WR = 0x0
7190 13:59:40.661253 DBI_RD = 0x0
7191 13:59:40.661824 OTF = 0x1
7192 13:59:40.664490 ===================================
7193 13:59:40.667734 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 13:59:40.671310 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 13:59:40.677990 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 13:59:40.681192 ===================================
7197 13:59:40.684841 LPDDR4 DRAM CONFIGURATION
7198 13:59:40.687910 ===================================
7199 13:59:40.688425 EX_ROW_EN[0] = 0x10
7200 13:59:40.691273 EX_ROW_EN[1] = 0x0
7201 13:59:40.691711 LP4Y_EN = 0x0
7202 13:59:40.694735 WORK_FSP = 0x1
7203 13:59:40.695242 WL = 0x5
7204 13:59:40.697519 RL = 0x5
7205 13:59:40.698144 BL = 0x2
7206 13:59:40.701248 RPST = 0x0
7207 13:59:40.701691 RD_PRE = 0x0
7208 13:59:40.704150 WR_PRE = 0x1
7209 13:59:40.704593 WR_PST = 0x1
7210 13:59:40.707774 DBI_WR = 0x0
7211 13:59:40.708332 DBI_RD = 0x0
7212 13:59:40.710815 OTF = 0x1
7213 13:59:40.713976 ===================================
7214 13:59:40.721265 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 13:59:40.721791 ==
7216 13:59:40.724257 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 13:59:40.727612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 13:59:40.728128 ==
7219 13:59:40.731358 [Duty_Offset_Calibration]
7220 13:59:40.731922 B0:2 B1:1 CA:1
7221 13:59:40.732324
7222 13:59:40.734594 [DutyScan_Calibration_Flow] k_type=0
7223 13:59:40.745974
7224 13:59:40.746521 ==CLK 0==
7225 13:59:40.749288 Final CLK duty delay cell = 0
7226 13:59:40.752611 [0] MAX Duty = 5156%(X100), DQS PI = 22
7227 13:59:40.755657 [0] MIN Duty = 4907%(X100), DQS PI = 0
7228 13:59:40.756213 [0] AVG Duty = 5031%(X100)
7229 13:59:40.758783
7230 13:59:40.762151 CH0 CLK Duty spec in!! Max-Min= 249%
7231 13:59:40.765218 [DutyScan_Calibration_Flow] ====Done====
7232 13:59:40.765773
7233 13:59:40.768993 [DutyScan_Calibration_Flow] k_type=1
7234 13:59:40.785090
7235 13:59:40.785642 ==DQS 0 ==
7236 13:59:40.788268 Final DQS duty delay cell = -4
7237 13:59:40.791348 [-4] MAX Duty = 5094%(X100), DQS PI = 24
7238 13:59:40.794701 [-4] MIN Duty = 4626%(X100), DQS PI = 0
7239 13:59:40.798077 [-4] AVG Duty = 4860%(X100)
7240 13:59:40.798574
7241 13:59:40.798935 ==DQS 1 ==
7242 13:59:40.801345 Final DQS duty delay cell = 0
7243 13:59:40.804181 [0] MAX Duty = 5187%(X100), DQS PI = 4
7244 13:59:40.807587 [0] MIN Duty = 5062%(X100), DQS PI = 34
7245 13:59:40.811431 [0] AVG Duty = 5124%(X100)
7246 13:59:40.811985
7247 13:59:40.814575 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7248 13:59:40.815029
7249 13:59:40.818067 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7250 13:59:40.820918 [DutyScan_Calibration_Flow] ====Done====
7251 13:59:40.821374
7252 13:59:40.824526 [DutyScan_Calibration_Flow] k_type=3
7253 13:59:40.842140
7254 13:59:40.842862 ==DQM 0 ==
7255 13:59:40.845598 Final DQM duty delay cell = 0
7256 13:59:40.849192 [0] MAX Duty = 5187%(X100), DQS PI = 32
7257 13:59:40.852394 [0] MIN Duty = 4875%(X100), DQS PI = 60
7258 13:59:40.855375 [0] AVG Duty = 5031%(X100)
7259 13:59:40.855830
7260 13:59:40.856183 ==DQM 1 ==
7261 13:59:40.858655 Final DQM duty delay cell = 0
7262 13:59:40.862228 [0] MAX Duty = 5187%(X100), DQS PI = 6
7263 13:59:40.865276 [0] MIN Duty = 5062%(X100), DQS PI = 12
7264 13:59:40.869016 [0] AVG Duty = 5124%(X100)
7265 13:59:40.869570
7266 13:59:40.872310 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7267 13:59:40.872882
7268 13:59:40.875391 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7269 13:59:40.879142 [DutyScan_Calibration_Flow] ====Done====
7270 13:59:40.879710
7271 13:59:40.881731 [DutyScan_Calibration_Flow] k_type=2
7272 13:59:40.899058
7273 13:59:40.899609 ==DQ 0 ==
7274 13:59:40.902729 Final DQ duty delay cell = 0
7275 13:59:40.905647 [0] MAX Duty = 5062%(X100), DQS PI = 24
7276 13:59:40.909544 [0] MIN Duty = 4907%(X100), DQS PI = 0
7277 13:59:40.910105 [0] AVG Duty = 4984%(X100)
7278 13:59:40.910461
7279 13:59:40.912786 ==DQ 1 ==
7280 13:59:40.915911 Final DQ duty delay cell = 0
7281 13:59:40.919310 [0] MAX Duty = 5125%(X100), DQS PI = 6
7282 13:59:40.922859 [0] MIN Duty = 4907%(X100), DQS PI = 34
7283 13:59:40.923330 [0] AVG Duty = 5016%(X100)
7284 13:59:40.923686
7285 13:59:40.926317 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7286 13:59:40.926869
7287 13:59:40.929512 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7288 13:59:40.936406 [DutyScan_Calibration_Flow] ====Done====
7289 13:59:40.936951 ==
7290 13:59:40.939457 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 13:59:40.942325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 13:59:40.942797 ==
7293 13:59:40.945584 [Duty_Offset_Calibration]
7294 13:59:40.946051 B0:1 B1:0 CA:0
7295 13:59:40.946415
7296 13:59:40.948754 [DutyScan_Calibration_Flow] k_type=0
7297 13:59:40.958204
7298 13:59:40.958712 ==CLK 0==
7299 13:59:40.961862 Final CLK duty delay cell = -4
7300 13:59:40.965194 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7301 13:59:40.968108 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7302 13:59:40.971976 [-4] AVG Duty = 4922%(X100)
7303 13:59:40.972407
7304 13:59:40.975146 CH1 CLK Duty spec in!! Max-Min= 156%
7305 13:59:40.978324 [DutyScan_Calibration_Flow] ====Done====
7306 13:59:40.978726
7307 13:59:40.981613 [DutyScan_Calibration_Flow] k_type=1
7308 13:59:40.998494
7309 13:59:40.999028 ==DQS 0 ==
7310 13:59:41.001905 Final DQS duty delay cell = 0
7311 13:59:41.004878 [0] MAX Duty = 5094%(X100), DQS PI = 16
7312 13:59:41.008360 [0] MIN Duty = 4844%(X100), DQS PI = 48
7313 13:59:41.008855 [0] AVG Duty = 4969%(X100)
7314 13:59:41.011775
7315 13:59:41.012120 ==DQS 1 ==
7316 13:59:41.015414 Final DQS duty delay cell = 0
7317 13:59:41.018689 [0] MAX Duty = 5249%(X100), DQS PI = 16
7318 13:59:41.022016 [0] MIN Duty = 4969%(X100), DQS PI = 8
7319 13:59:41.024925 [0] AVG Duty = 5109%(X100)
7320 13:59:41.025330
7321 13:59:41.028274 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7322 13:59:41.028839
7323 13:59:41.031653 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7324 13:59:41.035320 [DutyScan_Calibration_Flow] ====Done====
7325 13:59:41.035868
7326 13:59:41.038575 [DutyScan_Calibration_Flow] k_type=3
7327 13:59:41.055614
7328 13:59:41.056156 ==DQM 0 ==
7329 13:59:41.058771 Final DQM duty delay cell = 0
7330 13:59:41.061980 [0] MAX Duty = 5187%(X100), DQS PI = 8
7331 13:59:41.065146 [0] MIN Duty = 4969%(X100), DQS PI = 48
7332 13:59:41.068702 [0] AVG Duty = 5078%(X100)
7333 13:59:41.069147
7334 13:59:41.069498 ==DQM 1 ==
7335 13:59:41.072198 Final DQM duty delay cell = 0
7336 13:59:41.075244 [0] MAX Duty = 5093%(X100), DQS PI = 16
7337 13:59:41.078838 [0] MIN Duty = 4907%(X100), DQS PI = 34
7338 13:59:41.081744 [0] AVG Duty = 5000%(X100)
7339 13:59:41.082248
7340 13:59:41.085119 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7341 13:59:41.085532
7342 13:59:41.088009 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7343 13:59:41.091925 [DutyScan_Calibration_Flow] ====Done====
7344 13:59:41.092532
7345 13:59:41.094858 [DutyScan_Calibration_Flow] k_type=2
7346 13:59:41.111800
7347 13:59:41.112350 ==DQ 0 ==
7348 13:59:41.114798 Final DQ duty delay cell = -4
7349 13:59:41.118334 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7350 13:59:41.121353 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7351 13:59:41.124236 [-4] AVG Duty = 4953%(X100)
7352 13:59:41.124686
7353 13:59:41.125005 ==DQ 1 ==
7354 13:59:41.128028 Final DQ duty delay cell = 0
7355 13:59:41.131798 [0] MAX Duty = 5093%(X100), DQS PI = 16
7356 13:59:41.134884 [0] MIN Duty = 4938%(X100), DQS PI = 8
7357 13:59:41.138019 [0] AVG Duty = 5015%(X100)
7358 13:59:41.138523
7359 13:59:41.141546 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7360 13:59:41.142048
7361 13:59:41.144857 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7362 13:59:41.147729 [DutyScan_Calibration_Flow] ====Done====
7363 13:59:41.150824 nWR fixed to 30
7364 13:59:41.154244 [ModeRegInit_LP4] CH0 RK0
7365 13:59:41.154726 [ModeRegInit_LP4] CH0 RK1
7366 13:59:41.157441 [ModeRegInit_LP4] CH1 RK0
7367 13:59:41.161578 [ModeRegInit_LP4] CH1 RK1
7368 13:59:41.162081 match AC timing 5
7369 13:59:41.167776 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 13:59:41.170931 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 13:59:41.175077 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 13:59:41.181223 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 13:59:41.184768 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 13:59:41.185276 [MiockJmeterHQA]
7375 13:59:41.185598
7376 13:59:41.188085 [DramcMiockJmeter] u1RxGatingPI = 0
7377 13:59:41.191067 0 : 4255, 4029
7378 13:59:41.191782 4 : 4254, 4029
7379 13:59:41.194680 8 : 4253, 4027
7380 13:59:41.195194 12 : 4253, 4026
7381 13:59:41.195527 16 : 4253, 4027
7382 13:59:41.198147 20 : 4252, 4027
7383 13:59:41.198662 24 : 4254, 4029
7384 13:59:41.201059 28 : 4363, 4137
7385 13:59:41.201476 32 : 4253, 4027
7386 13:59:41.204220 36 : 4252, 4027
7387 13:59:41.204688 40 : 4252, 4027
7388 13:59:41.207756 44 : 4252, 4027
7389 13:59:41.208269 48 : 4252, 4027
7390 13:59:41.208656 52 : 4363, 4139
7391 13:59:41.211144 56 : 4361, 4137
7392 13:59:41.211656 60 : 4250, 4027
7393 13:59:41.214719 64 : 4252, 4029
7394 13:59:41.215273 68 : 4250, 4026
7395 13:59:41.217764 72 : 4250, 4027
7396 13:59:41.218276 76 : 4253, 4029
7397 13:59:41.218608 80 : 4360, 4137
7398 13:59:41.221205 84 : 4253, 4026
7399 13:59:41.221740 88 : 4250, 152
7400 13:59:41.224322 92 : 4360, 0
7401 13:59:41.224748 96 : 4253, 0
7402 13:59:41.225137 100 : 4252, 0
7403 13:59:41.227829 104 : 4250, 0
7404 13:59:41.228243 108 : 4250, 0
7405 13:59:41.231431 112 : 4250, 0
7406 13:59:41.231951 116 : 4363, 0
7407 13:59:41.232281 120 : 4250, 0
7408 13:59:41.234964 124 : 4250, 0
7409 13:59:41.235479 128 : 4250, 0
7410 13:59:41.238067 132 : 4253, 0
7411 13:59:41.238582 136 : 4250, 0
7412 13:59:41.238912 140 : 4250, 0
7413 13:59:41.240894 144 : 4252, 0
7414 13:59:41.241314 148 : 4250, 0
7415 13:59:41.241638 152 : 4361, 0
7416 13:59:41.244928 156 : 4361, 0
7417 13:59:41.245647 160 : 4250, 0
7418 13:59:41.247673 164 : 4250, 0
7419 13:59:41.248087 168 : 4250, 0
7420 13:59:41.248456 172 : 4250, 0
7421 13:59:41.251014 176 : 4250, 0
7422 13:59:41.251426 180 : 4250, 0
7423 13:59:41.254681 184 : 4253, 0
7424 13:59:41.255196 188 : 4250, 0
7425 13:59:41.255527 192 : 4250, 0
7426 13:59:41.257527 196 : 4253, 0
7427 13:59:41.257996 200 : 4360, 0
7428 13:59:41.261168 204 : 4361, 1066
7429 13:59:41.261680 208 : 4250, 3999
7430 13:59:41.264384 212 : 4250, 4026
7431 13:59:41.264798 216 : 4361, 4137
7432 13:59:41.265124 220 : 4250, 4026
7433 13:59:41.268440 224 : 4250, 4027
7434 13:59:41.268955 228 : 4250, 4027
7435 13:59:41.270883 232 : 4252, 4029
7436 13:59:41.271401 236 : 4250, 4026
7437 13:59:41.274850 240 : 4250, 4027
7438 13:59:41.275370 244 : 4360, 4138
7439 13:59:41.278110 248 : 4250, 4027
7440 13:59:41.278621 252 : 4250, 4027
7441 13:59:41.281257 256 : 4360, 4137
7442 13:59:41.281766 260 : 4250, 4027
7443 13:59:41.284383 264 : 4250, 4027
7444 13:59:41.284799 268 : 4363, 4140
7445 13:59:41.285122 272 : 4250, 4027
7446 13:59:41.287741 276 : 4250, 4027
7447 13:59:41.288252 280 : 4250, 4026
7448 13:59:41.291007 284 : 4253, 4029
7449 13:59:41.291423 288 : 4250, 4026
7450 13:59:41.294279 292 : 4250, 4027
7451 13:59:41.294794 296 : 4360, 4138
7452 13:59:41.298185 300 : 4250, 4027
7453 13:59:41.298700 304 : 4250, 4026
7454 13:59:41.301224 308 : 4360, 4110
7455 13:59:41.301640 312 : 4250, 2221
7456 13:59:41.304281 316 : 4250, 19
7457 13:59:41.304762
7458 13:59:41.305084 MIOCK jitter meter ch=0
7459 13:59:41.305439
7460 13:59:41.307389 1T = (316-88) = 228 dly cells
7461 13:59:41.314354 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7462 13:59:41.314852 ==
7463 13:59:41.317500 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 13:59:41.320971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7465 13:59:41.321482 ==
7466 13:59:41.327621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7467 13:59:41.331074 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7468 13:59:41.334378 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7469 13:59:41.340607 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7470 13:59:41.350360 [CA 0] Center 42 (12~73) winsize 62
7471 13:59:41.353525 [CA 1] Center 42 (12~73) winsize 62
7472 13:59:41.357339 [CA 2] Center 37 (8~67) winsize 60
7473 13:59:41.360089 [CA 3] Center 37 (7~67) winsize 61
7474 13:59:41.364078 [CA 4] Center 36 (6~66) winsize 61
7475 13:59:41.367407 [CA 5] Center 35 (6~64) winsize 59
7476 13:59:41.367910
7477 13:59:41.370554 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7478 13:59:41.370962
7479 13:59:41.374015 [CATrainingPosCal] consider 1 rank data
7480 13:59:41.377233 u2DelayCellTimex100 = 285/100 ps
7481 13:59:41.380736 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7482 13:59:41.387273 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7483 13:59:41.390166 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7484 13:59:41.394225 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7485 13:59:41.397108 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7486 13:59:41.400059 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7487 13:59:41.400551
7488 13:59:41.403828 CA PerBit enable=1, Macro0, CA PI delay=35
7489 13:59:41.404281
7490 13:59:41.407449 [CBTSetCACLKResult] CA Dly = 35
7491 13:59:41.407997 CS Dly: 9 (0~40)
7492 13:59:41.413613 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7493 13:59:41.417121 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7494 13:59:41.417574 ==
7495 13:59:41.420164 Dram Type= 6, Freq= 0, CH_0, rank 1
7496 13:59:41.423494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 13:59:41.424004 ==
7498 13:59:41.430694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 13:59:41.433673 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 13:59:41.440487 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 13:59:41.443795 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 13:59:41.453856 [CA 0] Center 42 (12~73) winsize 62
7503 13:59:41.457047 [CA 1] Center 42 (12~73) winsize 62
7504 13:59:41.460396 [CA 2] Center 37 (8~67) winsize 60
7505 13:59:41.463711 [CA 3] Center 38 (8~68) winsize 61
7506 13:59:41.467427 [CA 4] Center 35 (5~65) winsize 61
7507 13:59:41.470405 [CA 5] Center 35 (5~65) winsize 61
7508 13:59:41.470860
7509 13:59:41.473669 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7510 13:59:41.474124
7511 13:59:41.476957 [CATrainingPosCal] consider 2 rank data
7512 13:59:41.480484 u2DelayCellTimex100 = 285/100 ps
7513 13:59:41.483691 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7514 13:59:41.490000 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7515 13:59:41.493426 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 13:59:41.496793 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7517 13:59:41.499899 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7518 13:59:41.503892 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7519 13:59:41.504402
7520 13:59:41.506840 CA PerBit enable=1, Macro0, CA PI delay=35
7521 13:59:41.507300
7522 13:59:41.510592 [CBTSetCACLKResult] CA Dly = 35
7523 13:59:41.511113 CS Dly: 10 (0~42)
7524 13:59:41.516945 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 13:59:41.520352 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 13:59:41.520915
7527 13:59:41.523955 ----->DramcWriteLeveling(PI) begin...
7528 13:59:41.524562 ==
7529 13:59:41.527198 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 13:59:41.530197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 13:59:41.530791 ==
7532 13:59:41.533305 Write leveling (Byte 0): 35 => 35
7533 13:59:41.536992 Write leveling (Byte 1): 27 => 27
7534 13:59:41.540444 DramcWriteLeveling(PI) end<-----
7535 13:59:41.541009
7536 13:59:41.541376 ==
7537 13:59:41.543573 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 13:59:41.550306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 13:59:41.550876 ==
7540 13:59:41.551246 [Gating] SW mode calibration
7541 13:59:41.559971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7542 13:59:41.563547 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7543 13:59:41.567101 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7544 13:59:41.573537 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7545 13:59:41.576483 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7546 13:59:41.579984 1 4 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
7547 13:59:41.586713 1 4 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7548 13:59:41.590194 1 4 20 | B1->B0 | 3434 3636 | 0 1 | (0 0) (0 0)
7549 13:59:41.593535 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7550 13:59:41.600239 1 4 28 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (1 1)
7551 13:59:41.603168 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7552 13:59:41.606446 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7553 13:59:41.613024 1 5 8 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 0)
7554 13:59:41.616419 1 5 12 | B1->B0 | 3434 2a29 | 1 1 | (1 1) (1 0)
7555 13:59:41.619800 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7556 13:59:41.626979 1 5 20 | B1->B0 | 2828 2a2a | 1 0 | (1 0) (0 0)
7557 13:59:41.629915 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7558 13:59:41.633258 1 5 28 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7559 13:59:41.639468 1 6 0 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7560 13:59:41.643240 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7561 13:59:41.646431 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7562 13:59:41.652818 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7563 13:59:41.656106 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7564 13:59:41.660111 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 13:59:41.667079 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 13:59:41.669988 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 13:59:41.673121 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 13:59:41.680004 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 13:59:41.683140 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 13:59:41.686517 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 13:59:41.693388 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7572 13:59:41.696688 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 13:59:41.699804 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 13:59:41.706470 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 13:59:41.709202 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 13:59:41.712591 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 13:59:41.715816 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 13:59:41.722929 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 13:59:41.726573 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 13:59:41.729656 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 13:59:41.736362 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 13:59:41.739018 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 13:59:41.743059 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 13:59:41.749031 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 13:59:41.752229 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 13:59:41.755907 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 13:59:41.762377 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 13:59:41.765502 Total UI for P1: 0, mck2ui 16
7589 13:59:41.768882 best dqsien dly found for B0: ( 1, 9, 12)
7590 13:59:41.772083 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7591 13:59:41.775611 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 13:59:41.778905 Total UI for P1: 0, mck2ui 16
7593 13:59:41.782320 best dqsien dly found for B1: ( 1, 9, 18)
7594 13:59:41.785816 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7595 13:59:41.788726 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7596 13:59:41.792044
7597 13:59:41.795202 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7598 13:59:41.798869 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7599 13:59:41.801879 [Gating] SW calibration Done
7600 13:59:41.802310 ==
7601 13:59:41.805341 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 13:59:41.808741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 13:59:41.809201 ==
7604 13:59:41.811946 RX Vref Scan: 0
7605 13:59:41.812556
7606 13:59:41.812938 RX Vref 0 -> 0, step: 1
7607 13:59:41.813276
7608 13:59:41.815155 RX Delay 0 -> 252, step: 8
7609 13:59:41.818725 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7610 13:59:41.822578 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7611 13:59:41.828773 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7612 13:59:41.832101 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7613 13:59:41.835195 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7614 13:59:41.839156 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7615 13:59:41.841934 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7616 13:59:41.848761 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7617 13:59:41.852001 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7618 13:59:41.855103 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7619 13:59:41.858573 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7620 13:59:41.862059 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7621 13:59:41.868419 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7622 13:59:41.871663 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7623 13:59:41.874966 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7624 13:59:41.878288 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7625 13:59:41.878746 ==
7626 13:59:41.882094 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 13:59:41.888332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 13:59:41.888895 ==
7629 13:59:41.889255 DQS Delay:
7630 13:59:41.889634 DQS0 = 0, DQS1 = 0
7631 13:59:41.891453 DQM Delay:
7632 13:59:41.891905 DQM0 = 137, DQM1 = 129
7633 13:59:41.894756 DQ Delay:
7634 13:59:41.898651 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7635 13:59:41.901828 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7636 13:59:41.904995 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7637 13:59:41.907998 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7638 13:59:41.908520
7639 13:59:41.908996
7640 13:59:41.909447 ==
7641 13:59:41.911892 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 13:59:41.914627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 13:59:41.918670 ==
7644 13:59:41.919230
7645 13:59:41.919814
7646 13:59:41.920419 TX Vref Scan disable
7647 13:59:41.921235 == TX Byte 0 ==
7648 13:59:41.924597 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7649 13:59:41.928211 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7650 13:59:41.931827 == TX Byte 1 ==
7651 13:59:41.934701 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7652 13:59:41.938264 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7653 13:59:41.941307 ==
7654 13:59:41.941832 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 13:59:41.948159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 13:59:41.948789 ==
7657 13:59:41.961019
7658 13:59:41.964156 TX Vref early break, caculate TX vref
7659 13:59:41.968224 TX Vref=16, minBit 0, minWin=22, winSum=376
7660 13:59:41.970610 TX Vref=18, minBit 0, minWin=22, winSum=382
7661 13:59:41.974145 TX Vref=20, minBit 0, minWin=24, winSum=402
7662 13:59:41.977622 TX Vref=22, minBit 0, minWin=25, winSum=412
7663 13:59:41.980851 TX Vref=24, minBit 7, minWin=23, winSum=414
7664 13:59:41.988020 TX Vref=26, minBit 6, minWin=25, winSum=423
7665 13:59:41.990795 TX Vref=28, minBit 2, minWin=25, winSum=424
7666 13:59:41.993852 TX Vref=30, minBit 1, minWin=24, winSum=411
7667 13:59:41.997036 TX Vref=32, minBit 6, minWin=23, winSum=402
7668 13:59:42.001101 TX Vref=34, minBit 0, minWin=23, winSum=390
7669 13:59:42.007153 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 28
7670 13:59:42.007702
7671 13:59:42.010649 Final TX Range 0 Vref 28
7672 13:59:42.011167
7673 13:59:42.011658 ==
7674 13:59:42.013575 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 13:59:42.017206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 13:59:42.017680 ==
7677 13:59:42.018159
7678 13:59:42.018608
7679 13:59:42.020678 TX Vref Scan disable
7680 13:59:42.026949 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7681 13:59:42.027518 == TX Byte 0 ==
7682 13:59:42.030609 u2DelayCellOfst[0]=10 cells (3 PI)
7683 13:59:42.033903 u2DelayCellOfst[1]=13 cells (4 PI)
7684 13:59:42.037289 u2DelayCellOfst[2]=10 cells (3 PI)
7685 13:59:42.040567 u2DelayCellOfst[3]=10 cells (3 PI)
7686 13:59:42.044010 u2DelayCellOfst[4]=6 cells (2 PI)
7687 13:59:42.047666 u2DelayCellOfst[5]=0 cells (0 PI)
7688 13:59:42.050390 u2DelayCellOfst[6]=17 cells (5 PI)
7689 13:59:42.053447 u2DelayCellOfst[7]=17 cells (5 PI)
7690 13:59:42.056923 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7691 13:59:42.060194 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7692 13:59:42.063767 == TX Byte 1 ==
7693 13:59:42.064373 u2DelayCellOfst[8]=0 cells (0 PI)
7694 13:59:42.067501 u2DelayCellOfst[9]=3 cells (1 PI)
7695 13:59:42.070247 u2DelayCellOfst[10]=10 cells (3 PI)
7696 13:59:42.073807 u2DelayCellOfst[11]=3 cells (1 PI)
7697 13:59:42.077448 u2DelayCellOfst[12]=10 cells (3 PI)
7698 13:59:42.080663 u2DelayCellOfst[13]=10 cells (3 PI)
7699 13:59:42.084229 u2DelayCellOfst[14]=13 cells (4 PI)
7700 13:59:42.087396 u2DelayCellOfst[15]=10 cells (3 PI)
7701 13:59:42.090484 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7702 13:59:42.096690 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7703 13:59:42.097163 DramC Write-DBI on
7704 13:59:42.097639 ==
7705 13:59:42.100190 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 13:59:42.103873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 13:59:42.107194 ==
7708 13:59:42.107759
7709 13:59:42.108351
7710 13:59:42.108805 TX Vref Scan disable
7711 13:59:42.110278 == TX Byte 0 ==
7712 13:59:42.113811 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7713 13:59:42.116963 == TX Byte 1 ==
7714 13:59:42.120342 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7715 13:59:42.123757 DramC Write-DBI off
7716 13:59:42.124362
7717 13:59:42.124847 [DATLAT]
7718 13:59:42.125296 Freq=1600, CH0 RK0
7719 13:59:42.125736
7720 13:59:42.126775 DATLAT Default: 0xf
7721 13:59:42.127244 0, 0xFFFF, sum = 0
7722 13:59:42.130314 1, 0xFFFF, sum = 0
7723 13:59:42.133826 2, 0xFFFF, sum = 0
7724 13:59:42.134396 3, 0xFFFF, sum = 0
7725 13:59:42.137139 4, 0xFFFF, sum = 0
7726 13:59:42.137616 5, 0xFFFF, sum = 0
7727 13:59:42.140344 6, 0xFFFF, sum = 0
7728 13:59:42.140821 7, 0xFFFF, sum = 0
7729 13:59:42.143741 8, 0xFFFF, sum = 0
7730 13:59:42.144361 9, 0xFFFF, sum = 0
7731 13:59:42.147309 10, 0xFFFF, sum = 0
7732 13:59:42.147875 11, 0xFFFF, sum = 0
7733 13:59:42.150457 12, 0xFFFF, sum = 0
7734 13:59:42.150931 13, 0xFFFF, sum = 0
7735 13:59:42.153373 14, 0x0, sum = 1
7736 13:59:42.153851 15, 0x0, sum = 2
7737 13:59:42.157020 16, 0x0, sum = 3
7738 13:59:42.157560 17, 0x0, sum = 4
7739 13:59:42.160248 best_step = 15
7740 13:59:42.160748
7741 13:59:42.161222 ==
7742 13:59:42.163624 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 13:59:42.167339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 13:59:42.167907 ==
7745 13:59:42.168495 RX Vref Scan: 1
7746 13:59:42.170146
7747 13:59:42.170612 Set Vref Range= 24 -> 127
7748 13:59:42.171088
7749 13:59:42.173649 RX Vref 24 -> 127, step: 1
7750 13:59:42.174220
7751 13:59:42.177074 RX Delay 19 -> 252, step: 4
7752 13:59:42.177544
7753 13:59:42.180205 Set Vref, RX VrefLevel [Byte0]: 24
7754 13:59:42.183560 [Byte1]: 24
7755 13:59:42.184088
7756 13:59:42.186970 Set Vref, RX VrefLevel [Byte0]: 25
7757 13:59:42.190555 [Byte1]: 25
7758 13:59:42.191116
7759 13:59:42.193523 Set Vref, RX VrefLevel [Byte0]: 26
7760 13:59:42.196471 [Byte1]: 26
7761 13:59:42.200571
7762 13:59:42.204190 Set Vref, RX VrefLevel [Byte0]: 27
7763 13:59:42.204802 [Byte1]: 27
7764 13:59:42.208262
7765 13:59:42.208764 Set Vref, RX VrefLevel [Byte0]: 28
7766 13:59:42.211674 [Byte1]: 28
7767 13:59:42.216466
7768 13:59:42.217032 Set Vref, RX VrefLevel [Byte0]: 29
7769 13:59:42.219337 [Byte1]: 29
7770 13:59:42.223577
7771 13:59:42.224142 Set Vref, RX VrefLevel [Byte0]: 30
7772 13:59:42.226779 [Byte1]: 30
7773 13:59:42.231222
7774 13:59:42.231783 Set Vref, RX VrefLevel [Byte0]: 31
7775 13:59:42.234499 [Byte1]: 31
7776 13:59:42.239053
7777 13:59:42.239613 Set Vref, RX VrefLevel [Byte0]: 32
7778 13:59:42.242033 [Byte1]: 32
7779 13:59:42.246677
7780 13:59:42.247258 Set Vref, RX VrefLevel [Byte0]: 33
7781 13:59:42.249438 [Byte1]: 33
7782 13:59:42.253426
7783 13:59:42.253874 Set Vref, RX VrefLevel [Byte0]: 34
7784 13:59:42.257363 [Byte1]: 34
7785 13:59:42.261045
7786 13:59:42.261494 Set Vref, RX VrefLevel [Byte0]: 35
7787 13:59:42.265301 [Byte1]: 35
7788 13:59:42.269046
7789 13:59:42.269598 Set Vref, RX VrefLevel [Byte0]: 36
7790 13:59:42.272593 [Byte1]: 36
7791 13:59:42.276419
7792 13:59:42.276868 Set Vref, RX VrefLevel [Byte0]: 37
7793 13:59:42.280168 [Byte1]: 37
7794 13:59:42.283863
7795 13:59:42.284452 Set Vref, RX VrefLevel [Byte0]: 38
7796 13:59:42.287051 [Byte1]: 38
7797 13:59:42.291616
7798 13:59:42.292163 Set Vref, RX VrefLevel [Byte0]: 39
7799 13:59:42.294586 [Byte1]: 39
7800 13:59:42.299595
7801 13:59:42.300152 Set Vref, RX VrefLevel [Byte0]: 40
7802 13:59:42.303239 [Byte1]: 40
7803 13:59:42.306525
7804 13:59:42.307168 Set Vref, RX VrefLevel [Byte0]: 41
7805 13:59:42.310106 [Byte1]: 41
7806 13:59:42.314686
7807 13:59:42.315258 Set Vref, RX VrefLevel [Byte0]: 42
7808 13:59:42.317574 [Byte1]: 42
7809 13:59:42.321761
7810 13:59:42.322298 Set Vref, RX VrefLevel [Byte0]: 43
7811 13:59:42.324982 [Byte1]: 43
7812 13:59:42.329160
7813 13:59:42.329726 Set Vref, RX VrefLevel [Byte0]: 44
7814 13:59:42.336049 [Byte1]: 44
7815 13:59:42.336688
7816 13:59:42.339498 Set Vref, RX VrefLevel [Byte0]: 45
7817 13:59:42.342710 [Byte1]: 45
7818 13:59:42.343276
7819 13:59:42.345878 Set Vref, RX VrefLevel [Byte0]: 46
7820 13:59:42.349252 [Byte1]: 46
7821 13:59:42.349815
7822 13:59:42.352571 Set Vref, RX VrefLevel [Byte0]: 47
7823 13:59:42.355876 [Byte1]: 47
7824 13:59:42.359788
7825 13:59:42.360398 Set Vref, RX VrefLevel [Byte0]: 48
7826 13:59:42.363131 [Byte1]: 48
7827 13:59:42.367491
7828 13:59:42.368049 Set Vref, RX VrefLevel [Byte0]: 49
7829 13:59:42.370772 [Byte1]: 49
7830 13:59:42.375333
7831 13:59:42.375892 Set Vref, RX VrefLevel [Byte0]: 50
7832 13:59:42.378307 [Byte1]: 50
7833 13:59:42.382845
7834 13:59:42.383415 Set Vref, RX VrefLevel [Byte0]: 51
7835 13:59:42.385696 [Byte1]: 51
7836 13:59:42.390083
7837 13:59:42.390641 Set Vref, RX VrefLevel [Byte0]: 52
7838 13:59:42.393419 [Byte1]: 52
7839 13:59:42.398229
7840 13:59:42.398781 Set Vref, RX VrefLevel [Byte0]: 53
7841 13:59:42.400674 [Byte1]: 53
7842 13:59:42.405353
7843 13:59:42.405942 Set Vref, RX VrefLevel [Byte0]: 54
7844 13:59:42.408690 [Byte1]: 54
7845 13:59:42.413005
7846 13:59:42.413550 Set Vref, RX VrefLevel [Byte0]: 55
7847 13:59:42.416454 [Byte1]: 55
7848 13:59:42.420665
7849 13:59:42.421222 Set Vref, RX VrefLevel [Byte0]: 56
7850 13:59:42.424156 [Byte1]: 56
7851 13:59:42.427890
7852 13:59:42.428401 Set Vref, RX VrefLevel [Byte0]: 57
7853 13:59:42.431336 [Byte1]: 57
7854 13:59:42.435198
7855 13:59:42.435645 Set Vref, RX VrefLevel [Byte0]: 58
7856 13:59:42.438821 [Byte1]: 58
7857 13:59:42.443129
7858 13:59:42.443671 Set Vref, RX VrefLevel [Byte0]: 59
7859 13:59:42.446135 [Byte1]: 59
7860 13:59:42.450574
7861 13:59:42.451065 Set Vref, RX VrefLevel [Byte0]: 60
7862 13:59:42.453743 [Byte1]: 60
7863 13:59:42.458096
7864 13:59:42.458564 Set Vref, RX VrefLevel [Byte0]: 61
7865 13:59:42.461692 [Byte1]: 61
7866 13:59:42.465648
7867 13:59:42.466230 Set Vref, RX VrefLevel [Byte0]: 62
7868 13:59:42.468883 [Byte1]: 62
7869 13:59:42.473501
7870 13:59:42.474061 Set Vref, RX VrefLevel [Byte0]: 63
7871 13:59:42.476572 [Byte1]: 63
7872 13:59:42.481253
7873 13:59:42.481816 Set Vref, RX VrefLevel [Byte0]: 64
7874 13:59:42.484364 [Byte1]: 64
7875 13:59:42.488932
7876 13:59:42.489495 Set Vref, RX VrefLevel [Byte0]: 65
7877 13:59:42.492131 [Byte1]: 65
7878 13:59:42.496138
7879 13:59:42.496751 Set Vref, RX VrefLevel [Byte0]: 66
7880 13:59:42.499640 [Byte1]: 66
7881 13:59:42.503658
7882 13:59:42.504215 Set Vref, RX VrefLevel [Byte0]: 67
7883 13:59:42.507254 [Byte1]: 67
7884 13:59:42.511325
7885 13:59:42.511883 Set Vref, RX VrefLevel [Byte0]: 68
7886 13:59:42.514557 [Byte1]: 68
7887 13:59:42.519097
7888 13:59:42.519660 Set Vref, RX VrefLevel [Byte0]: 69
7889 13:59:42.522449 [Byte1]: 69
7890 13:59:42.526388
7891 13:59:42.526949 Set Vref, RX VrefLevel [Byte0]: 70
7892 13:59:42.529425 [Byte1]: 70
7893 13:59:42.534116
7894 13:59:42.534679 Set Vref, RX VrefLevel [Byte0]: 71
7895 13:59:42.537722 [Byte1]: 71
7896 13:59:42.542000
7897 13:59:42.542559 Set Vref, RX VrefLevel [Byte0]: 72
7898 13:59:42.545081 [Byte1]: 72
7899 13:59:42.549220
7900 13:59:42.549686 Set Vref, RX VrefLevel [Byte0]: 73
7901 13:59:42.552615 [Byte1]: 73
7902 13:59:42.556907
7903 13:59:42.557375 Set Vref, RX VrefLevel [Byte0]: 74
7904 13:59:42.559570 [Byte1]: 74
7905 13:59:42.564383
7906 13:59:42.564859 Set Vref, RX VrefLevel [Byte0]: 75
7907 13:59:42.567259 [Byte1]: 75
7908 13:59:42.571964
7909 13:59:42.572594 Final RX Vref Byte 0 = 55 to rank0
7910 13:59:42.574883 Final RX Vref Byte 1 = 59 to rank0
7911 13:59:42.578623 Final RX Vref Byte 0 = 55 to rank1
7912 13:59:42.581766 Final RX Vref Byte 1 = 59 to rank1==
7913 13:59:42.584883 Dram Type= 6, Freq= 0, CH_0, rank 0
7914 13:59:42.588364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7915 13:59:42.591970 ==
7916 13:59:42.592573 DQS Delay:
7917 13:59:42.593018 DQS0 = 0, DQS1 = 0
7918 13:59:42.594951 DQM Delay:
7919 13:59:42.595377 DQM0 = 133, DQM1 = 127
7920 13:59:42.598572 DQ Delay:
7921 13:59:42.601627 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =130
7922 13:59:42.605288 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7923 13:59:42.608617 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7924 13:59:42.611910 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7925 13:59:42.612536
7926 13:59:42.613024
7927 13:59:42.613521
7928 13:59:42.615467 [DramC_TX_OE_Calibration] TA2
7929 13:59:42.618857 Original DQ_B0 (3 6) =30, OEN = 27
7930 13:59:42.622392 Original DQ_B1 (3 6) =30, OEN = 27
7931 13:59:42.622960 24, 0x0, End_B0=24 End_B1=24
7932 13:59:42.625305 25, 0x0, End_B0=25 End_B1=25
7933 13:59:42.628495 26, 0x0, End_B0=26 End_B1=26
7934 13:59:42.631728 27, 0x0, End_B0=27 End_B1=27
7935 13:59:42.635882 28, 0x0, End_B0=28 End_B1=28
7936 13:59:42.636474 29, 0x0, End_B0=29 End_B1=29
7937 13:59:42.638926 30, 0x0, End_B0=30 End_B1=30
7938 13:59:42.642075 31, 0x4545, End_B0=30 End_B1=30
7939 13:59:42.645057 Byte0 end_step=30 best_step=27
7940 13:59:42.649056 Byte1 end_step=30 best_step=27
7941 13:59:42.652161 Byte0 TX OE(2T, 0.5T) = (3, 3)
7942 13:59:42.652721 Byte1 TX OE(2T, 0.5T) = (3, 3)
7943 13:59:42.653163
7944 13:59:42.653571
7945 13:59:42.661829 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7946 13:59:42.665070 CH0 RK0: MR19=303, MR18=2521
7947 13:59:42.671504 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7948 13:59:42.672134
7949 13:59:42.675187 ----->DramcWriteLeveling(PI) begin...
7950 13:59:42.675665 ==
7951 13:59:42.678029 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 13:59:42.681941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 13:59:42.682355 ==
7954 13:59:42.684618 Write leveling (Byte 0): 38 => 38
7955 13:59:42.688446 Write leveling (Byte 1): 27 => 27
7956 13:59:42.691853 DramcWriteLeveling(PI) end<-----
7957 13:59:42.692405
7958 13:59:42.692737 ==
7959 13:59:42.695186 Dram Type= 6, Freq= 0, CH_0, rank 1
7960 13:59:42.698216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 13:59:42.698773 ==
7962 13:59:42.701782 [Gating] SW mode calibration
7963 13:59:42.707823 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7964 13:59:42.715022 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7965 13:59:42.718312 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7966 13:59:42.721493 1 4 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7967 13:59:42.727902 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7968 13:59:42.731423 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7969 13:59:42.734837 1 4 16 | B1->B0 | 2d2d 3838 | 1 0 | (1 1) (0 0)
7970 13:59:42.741283 1 4 20 | B1->B0 | 3434 3a3a | 1 0 | (1 1) (1 1)
7971 13:59:42.745102 1 4 24 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7972 13:59:42.748534 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7973 13:59:42.754386 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7974 13:59:42.757799 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7975 13:59:42.760945 1 5 8 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7976 13:59:42.768121 1 5 12 | B1->B0 | 3434 3636 | 1 1 | (1 0) (1 0)
7977 13:59:42.771534 1 5 16 | B1->B0 | 3232 2e2e | 1 1 | (1 0) (0 0)
7978 13:59:42.774835 1 5 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7979 13:59:42.781078 1 5 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7980 13:59:42.784529 1 5 28 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (1 1)
7981 13:59:42.787835 1 6 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7982 13:59:42.794056 1 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
7983 13:59:42.797707 1 6 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7984 13:59:42.800987 1 6 12 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (1 1)
7985 13:59:42.804186 1 6 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
7986 13:59:42.810506 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7987 13:59:42.814244 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 13:59:42.817394 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 13:59:42.824022 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 13:59:42.827159 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 13:59:42.830910 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 13:59:42.837015 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7993 13:59:42.840541 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7994 13:59:42.843753 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 13:59:42.850638 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 13:59:42.853641 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 13:59:42.857415 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 13:59:42.863618 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 13:59:42.866905 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 13:59:42.870159 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 13:59:42.877077 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 13:59:42.880273 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 13:59:42.884045 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 13:59:42.890276 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 13:59:42.893865 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 13:59:42.897317 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 13:59:42.903660 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8008 13:59:42.906994 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8009 13:59:42.910209 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8010 13:59:42.917417 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 13:59:42.917509 Total UI for P1: 0, mck2ui 16
8012 13:59:42.920781 best dqsien dly found for B0: ( 1, 9, 12)
8013 13:59:42.923866 Total UI for P1: 0, mck2ui 16
8014 13:59:42.926876 best dqsien dly found for B1: ( 1, 9, 14)
8015 13:59:42.930571 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8016 13:59:42.937060 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8017 13:59:42.937164
8018 13:59:42.940290 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8019 13:59:42.943424 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8020 13:59:42.946996 [Gating] SW calibration Done
8021 13:59:42.947090 ==
8022 13:59:42.950554 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 13:59:42.954110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 13:59:42.954197 ==
8025 13:59:42.957365 RX Vref Scan: 0
8026 13:59:42.957446
8027 13:59:42.957509 RX Vref 0 -> 0, step: 1
8028 13:59:42.957568
8029 13:59:42.960559 RX Delay 0 -> 252, step: 8
8030 13:59:42.963840 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8031 13:59:42.967339 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8032 13:59:42.974132 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8033 13:59:42.977234 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8034 13:59:42.980435 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8035 13:59:42.983472 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8036 13:59:42.987011 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8037 13:59:42.993316 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8038 13:59:42.996876 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8039 13:59:43.000761 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8040 13:59:43.003426 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8041 13:59:43.006781 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8042 13:59:43.013498 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8043 13:59:43.016702 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8044 13:59:43.020089 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8045 13:59:43.024058 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8046 13:59:43.024533 ==
8047 13:59:43.027811 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 13:59:43.034168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 13:59:43.034690 ==
8050 13:59:43.035015 DQS Delay:
8051 13:59:43.035315 DQS0 = 0, DQS1 = 0
8052 13:59:43.037476 DQM Delay:
8053 13:59:43.037886 DQM0 = 136, DQM1 = 128
8054 13:59:43.040838 DQ Delay:
8055 13:59:43.044563 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8056 13:59:43.047853 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8057 13:59:43.051189 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8058 13:59:43.054154 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8059 13:59:43.054608
8060 13:59:43.054962
8061 13:59:43.055290 ==
8062 13:59:43.057670 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 13:59:43.060904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 13:59:43.061379 ==
8065 13:59:43.064246
8066 13:59:43.064865
8067 13:59:43.065357 TX Vref Scan disable
8068 13:59:43.067193 == TX Byte 0 ==
8069 13:59:43.071264 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8070 13:59:43.074252 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8071 13:59:43.077771 == TX Byte 1 ==
8072 13:59:43.080440 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8073 13:59:43.084175 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8074 13:59:43.084768 ==
8075 13:59:43.087764 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 13:59:43.094288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 13:59:43.094847 ==
8078 13:59:43.108611
8079 13:59:43.111921 TX Vref early break, caculate TX vref
8080 13:59:43.114713 TX Vref=16, minBit 0, minWin=23, winSum=385
8081 13:59:43.117661 TX Vref=18, minBit 1, minWin=23, winSum=394
8082 13:59:43.121420 TX Vref=20, minBit 1, minWin=24, winSum=403
8083 13:59:43.124575 TX Vref=22, minBit 1, minWin=24, winSum=410
8084 13:59:43.127690 TX Vref=24, minBit 0, minWin=25, winSum=420
8085 13:59:43.134419 TX Vref=26, minBit 3, minWin=24, winSum=422
8086 13:59:43.137671 TX Vref=28, minBit 0, minWin=26, winSum=423
8087 13:59:43.140951 TX Vref=30, minBit 4, minWin=24, winSum=416
8088 13:59:43.144486 TX Vref=32, minBit 0, minWin=25, winSum=410
8089 13:59:43.147784 TX Vref=34, minBit 0, minWin=24, winSum=404
8090 13:59:43.151034 TX Vref=36, minBit 0, minWin=24, winSum=393
8091 13:59:43.157482 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
8092 13:59:43.157573
8093 13:59:43.161183 Final TX Range 0 Vref 28
8094 13:59:43.161270
8095 13:59:43.161333 ==
8096 13:59:43.164164 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 13:59:43.167813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 13:59:43.167898 ==
8099 13:59:43.167961
8100 13:59:43.168026
8101 13:59:43.170984 TX Vref Scan disable
8102 13:59:43.177383 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8103 13:59:43.177469 == TX Byte 0 ==
8104 13:59:43.181138 u2DelayCellOfst[0]=13 cells (4 PI)
8105 13:59:43.184590 u2DelayCellOfst[1]=17 cells (5 PI)
8106 13:59:43.187511 u2DelayCellOfst[2]=13 cells (4 PI)
8107 13:59:43.191315 u2DelayCellOfst[3]=13 cells (4 PI)
8108 13:59:43.194579 u2DelayCellOfst[4]=10 cells (3 PI)
8109 13:59:43.197763 u2DelayCellOfst[5]=0 cells (0 PI)
8110 13:59:43.201008 u2DelayCellOfst[6]=17 cells (5 PI)
8111 13:59:43.204249 u2DelayCellOfst[7]=17 cells (5 PI)
8112 13:59:43.207432 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8113 13:59:43.211166 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8114 13:59:43.214503 == TX Byte 1 ==
8115 13:59:43.217768 u2DelayCellOfst[8]=0 cells (0 PI)
8116 13:59:43.220953 u2DelayCellOfst[9]=0 cells (0 PI)
8117 13:59:43.221043 u2DelayCellOfst[10]=3 cells (1 PI)
8118 13:59:43.224458 u2DelayCellOfst[11]=3 cells (1 PI)
8119 13:59:43.227429 u2DelayCellOfst[12]=10 cells (3 PI)
8120 13:59:43.230627 u2DelayCellOfst[13]=6 cells (2 PI)
8121 13:59:43.234308 u2DelayCellOfst[14]=10 cells (3 PI)
8122 13:59:43.237620 u2DelayCellOfst[15]=10 cells (3 PI)
8123 13:59:43.240845 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8124 13:59:43.247455 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8125 13:59:43.247541 DramC Write-DBI on
8126 13:59:43.247605 ==
8127 13:59:43.250639 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 13:59:43.257107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 13:59:43.257207 ==
8130 13:59:43.257271
8131 13:59:43.257330
8132 13:59:43.257387 TX Vref Scan disable
8133 13:59:43.261438 == TX Byte 0 ==
8134 13:59:43.265013 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8135 13:59:43.267993 == TX Byte 1 ==
8136 13:59:43.271416 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8137 13:59:43.274224 DramC Write-DBI off
8138 13:59:43.274317
8139 13:59:43.274388 [DATLAT]
8140 13:59:43.274518 Freq=1600, CH0 RK1
8141 13:59:43.274615
8142 13:59:43.277703 DATLAT Default: 0xf
8143 13:59:43.281043 0, 0xFFFF, sum = 0
8144 13:59:43.281125 1, 0xFFFF, sum = 0
8145 13:59:43.284428 2, 0xFFFF, sum = 0
8146 13:59:43.284510 3, 0xFFFF, sum = 0
8147 13:59:43.287477 4, 0xFFFF, sum = 0
8148 13:59:43.287560 5, 0xFFFF, sum = 0
8149 13:59:43.291017 6, 0xFFFF, sum = 0
8150 13:59:43.291106 7, 0xFFFF, sum = 0
8151 13:59:43.294336 8, 0xFFFF, sum = 0
8152 13:59:43.294428 9, 0xFFFF, sum = 0
8153 13:59:43.297692 10, 0xFFFF, sum = 0
8154 13:59:43.297775 11, 0xFFFF, sum = 0
8155 13:59:43.301049 12, 0xFFFF, sum = 0
8156 13:59:43.301132 13, 0xFFFF, sum = 0
8157 13:59:43.304324 14, 0x0, sum = 1
8158 13:59:43.304431 15, 0x0, sum = 2
8159 13:59:43.307592 16, 0x0, sum = 3
8160 13:59:43.307673 17, 0x0, sum = 4
8161 13:59:43.310929 best_step = 15
8162 13:59:43.311008
8163 13:59:43.311071 ==
8164 13:59:43.314200 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 13:59:43.317943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 13:59:43.318030 ==
8167 13:59:43.321213 RX Vref Scan: 0
8168 13:59:43.321317
8169 13:59:43.321407 RX Vref 0 -> 0, step: 1
8170 13:59:43.321493
8171 13:59:43.324481 RX Delay 19 -> 252, step: 4
8172 13:59:43.327911 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8173 13:59:43.334596 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8174 13:59:43.337842 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8175 13:59:43.340910 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8176 13:59:43.344888 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8177 13:59:43.347943 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8178 13:59:43.354750 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8179 13:59:43.357641 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8180 13:59:43.361325 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8181 13:59:43.364339 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8182 13:59:43.368101 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8183 13:59:43.374466 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8184 13:59:43.377950 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8185 13:59:43.381397 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8186 13:59:43.384403 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8187 13:59:43.387803 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8188 13:59:43.391131 ==
8189 13:59:43.391363 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 13:59:43.397671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 13:59:43.397994 ==
8192 13:59:43.398163 DQS Delay:
8193 13:59:43.401336 DQS0 = 0, DQS1 = 0
8194 13:59:43.401534 DQM Delay:
8195 13:59:43.404631 DQM0 = 134, DQM1 = 127
8196 13:59:43.404945 DQ Delay:
8197 13:59:43.407700 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8198 13:59:43.410766 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =142
8199 13:59:43.414186 DQ8 =118, DQ9 =116, DQ10 =130, DQ11 =118
8200 13:59:43.417721 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8201 13:59:43.417820
8202 13:59:43.417892
8203 13:59:43.417958
8204 13:59:43.420828 [DramC_TX_OE_Calibration] TA2
8205 13:59:43.424068 Original DQ_B0 (3 6) =30, OEN = 27
8206 13:59:43.427632 Original DQ_B1 (3 6) =30, OEN = 27
8207 13:59:43.430759 24, 0x0, End_B0=24 End_B1=24
8208 13:59:43.433954 25, 0x0, End_B0=25 End_B1=25
8209 13:59:43.434048 26, 0x0, End_B0=26 End_B1=26
8210 13:59:43.437533 27, 0x0, End_B0=27 End_B1=27
8211 13:59:43.441042 28, 0x0, End_B0=28 End_B1=28
8212 13:59:43.443879 29, 0x0, End_B0=29 End_B1=29
8213 13:59:43.443965 30, 0x0, End_B0=30 End_B1=30
8214 13:59:43.447332 31, 0x4141, End_B0=30 End_B1=30
8215 13:59:43.450442 Byte0 end_step=30 best_step=27
8216 13:59:43.453845 Byte1 end_step=30 best_step=27
8217 13:59:43.456941 Byte0 TX OE(2T, 0.5T) = (3, 3)
8218 13:59:43.460310 Byte1 TX OE(2T, 0.5T) = (3, 3)
8219 13:59:43.460446
8220 13:59:43.460538
8221 13:59:43.467411 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8222 13:59:43.470542 CH0 RK1: MR19=303, MR18=220A
8223 13:59:43.477348 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8224 13:59:43.480600 [RxdqsGatingPostProcess] freq 1600
8225 13:59:43.487364 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8226 13:59:43.487469 best DQS0 dly(2T, 0.5T) = (1, 1)
8227 13:59:43.490302 best DQS1 dly(2T, 0.5T) = (1, 1)
8228 13:59:43.493998 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8229 13:59:43.497281 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8230 13:59:43.500572 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 13:59:43.503765 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 13:59:43.506948 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 13:59:43.510673 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 13:59:43.513922 Pre-setting of DQS Precalculation
8235 13:59:43.516932 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8236 13:59:43.517021 ==
8237 13:59:43.520535 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 13:59:43.527190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 13:59:43.527276 ==
8240 13:59:43.530235 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8241 13:59:43.537364 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8242 13:59:43.540590 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8243 13:59:43.547016 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8244 13:59:43.554557 [CA 0] Center 41 (12~71) winsize 60
8245 13:59:43.557836 [CA 1] Center 41 (12~71) winsize 60
8246 13:59:43.560802 [CA 2] Center 38 (9~68) winsize 60
8247 13:59:43.564005 [CA 3] Center 37 (9~66) winsize 58
8248 13:59:43.567610 [CA 4] Center 37 (8~67) winsize 60
8249 13:59:43.570897 [CA 5] Center 36 (7~66) winsize 60
8250 13:59:43.570981
8251 13:59:43.573948 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8252 13:59:43.574030
8253 13:59:43.577665 [CATrainingPosCal] consider 1 rank data
8254 13:59:43.580681 u2DelayCellTimex100 = 285/100 ps
8255 13:59:43.584060 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8256 13:59:43.591054 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8257 13:59:43.593928 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8258 13:59:43.597040 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8259 13:59:43.600481 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8260 13:59:43.604002 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8261 13:59:43.604130
8262 13:59:43.607046 CA PerBit enable=1, Macro0, CA PI delay=36
8263 13:59:43.607170
8264 13:59:43.610657 [CBTSetCACLKResult] CA Dly = 36
8265 13:59:43.614266 CS Dly: 10 (0~41)
8266 13:59:43.617502 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8267 13:59:43.620678 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8268 13:59:43.620790 ==
8269 13:59:43.623861 Dram Type= 6, Freq= 0, CH_1, rank 1
8270 13:59:43.626911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 13:59:43.630263 ==
8272 13:59:43.634027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8273 13:59:43.636988 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8274 13:59:43.644108 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8275 13:59:43.647342 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8276 13:59:43.657695 [CA 0] Center 42 (12~72) winsize 61
8277 13:59:43.660879 [CA 1] Center 41 (12~71) winsize 60
8278 13:59:43.664090 [CA 2] Center 38 (9~68) winsize 60
8279 13:59:43.667326 [CA 3] Center 38 (8~68) winsize 61
8280 13:59:43.670557 [CA 4] Center 38 (8~69) winsize 62
8281 13:59:43.674479 [CA 5] Center 37 (7~67) winsize 61
8282 13:59:43.674623
8283 13:59:43.677614 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8284 13:59:43.677729
8285 13:59:43.680832 [CATrainingPosCal] consider 2 rank data
8286 13:59:43.683924 u2DelayCellTimex100 = 285/100 ps
8287 13:59:43.687052 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8288 13:59:43.693855 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8289 13:59:43.697582 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8290 13:59:43.700581 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8291 13:59:43.703765 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8292 13:59:43.707296 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8293 13:59:43.707375
8294 13:59:43.710289 CA PerBit enable=1, Macro0, CA PI delay=36
8295 13:59:43.710376
8296 13:59:43.713701 [CBTSetCACLKResult] CA Dly = 36
8297 13:59:43.717012 CS Dly: 12 (0~45)
8298 13:59:43.720586 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8299 13:59:43.723853 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8300 13:59:43.723952
8301 13:59:43.727229 ----->DramcWriteLeveling(PI) begin...
8302 13:59:43.727318 ==
8303 13:59:43.730515 Dram Type= 6, Freq= 0, CH_1, rank 0
8304 13:59:43.734175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 13:59:43.737351 ==
8306 13:59:43.737470 Write leveling (Byte 0): 26 => 26
8307 13:59:43.740211 Write leveling (Byte 1): 29 => 29
8308 13:59:43.743927 DramcWriteLeveling(PI) end<-----
8309 13:59:43.744053
8310 13:59:43.744154 ==
8311 13:59:43.747220 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 13:59:43.753514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 13:59:43.753633 ==
8314 13:59:43.756786 [Gating] SW mode calibration
8315 13:59:43.763321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8316 13:59:43.767176 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8317 13:59:43.773628 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 13:59:43.776731 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 13:59:43.780222 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8320 13:59:43.787114 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8321 13:59:43.790103 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 13:59:43.793412 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 13:59:43.800251 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 13:59:43.803579 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 13:59:43.806885 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 13:59:43.810080 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 13:59:43.816878 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8328 13:59:43.820589 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8329 13:59:43.823955 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 13:59:43.830521 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 13:59:43.833498 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 13:59:43.837105 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 13:59:43.843243 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 13:59:43.846706 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 13:59:43.850092 1 6 8 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8336 13:59:43.856475 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 13:59:43.859778 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 13:59:43.863201 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 13:59:43.869793 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 13:59:43.873695 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 13:59:43.876888 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 13:59:43.883660 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 13:59:43.886854 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8344 13:59:43.890629 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8345 13:59:43.896896 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8346 13:59:43.900106 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 13:59:43.903977 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 13:59:43.910348 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 13:59:43.913454 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 13:59:43.916836 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 13:59:43.923330 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 13:59:43.926612 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 13:59:43.929910 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 13:59:43.933166 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 13:59:43.940183 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 13:59:43.943242 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 13:59:43.946349 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 13:59:43.952962 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 13:59:43.956194 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 13:59:43.959486 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8361 13:59:43.966524 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 13:59:43.969663 Total UI for P1: 0, mck2ui 16
8363 13:59:43.972870 best dqsien dly found for B0: ( 1, 9, 10)
8364 13:59:43.976682 Total UI for P1: 0, mck2ui 16
8365 13:59:43.979841 best dqsien dly found for B1: ( 1, 9, 10)
8366 13:59:43.983238 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8367 13:59:43.986184 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8368 13:59:43.986267
8369 13:59:43.989767 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 13:59:43.992676 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8371 13:59:43.996005 [Gating] SW calibration Done
8372 13:59:43.996088 ==
8373 13:59:43.999456 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 13:59:44.003146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 13:59:44.003247 ==
8376 13:59:44.005987 RX Vref Scan: 0
8377 13:59:44.006067
8378 13:59:44.009491 RX Vref 0 -> 0, step: 1
8379 13:59:44.009572
8380 13:59:44.009634 RX Delay 0 -> 252, step: 8
8381 13:59:44.015873 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8382 13:59:44.019120 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8383 13:59:44.022673 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8384 13:59:44.025899 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8385 13:59:44.029897 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8386 13:59:44.032611 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8387 13:59:44.039186 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8388 13:59:44.042453 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8389 13:59:44.046084 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8390 13:59:44.049401 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8391 13:59:44.052986 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8392 13:59:44.059251 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8393 13:59:44.062356 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8394 13:59:44.065675 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8395 13:59:44.069559 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8396 13:59:44.075818 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8397 13:59:44.075903 ==
8398 13:59:44.079019 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 13:59:44.082859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 13:59:44.082942 ==
8401 13:59:44.083005 DQS Delay:
8402 13:59:44.085903 DQS0 = 0, DQS1 = 0
8403 13:59:44.085984 DQM Delay:
8404 13:59:44.089231 DQM0 = 136, DQM1 = 133
8405 13:59:44.089318 DQ Delay:
8406 13:59:44.092304 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8407 13:59:44.096174 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8408 13:59:44.099443 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8409 13:59:44.102617 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8410 13:59:44.102697
8411 13:59:44.102759
8412 13:59:44.102816 ==
8413 13:59:44.105681 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 13:59:44.112478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 13:59:44.112603 ==
8416 13:59:44.112669
8417 13:59:44.112727
8418 13:59:44.112782 TX Vref Scan disable
8419 13:59:44.116415 == TX Byte 0 ==
8420 13:59:44.119556 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8421 13:59:44.126365 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8422 13:59:44.126454 == TX Byte 1 ==
8423 13:59:44.129185 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8424 13:59:44.135990 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8425 13:59:44.136076 ==
8426 13:59:44.139183 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 13:59:44.142461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 13:59:44.142544 ==
8429 13:59:44.154859
8430 13:59:44.158090 TX Vref early break, caculate TX vref
8431 13:59:44.161529 TX Vref=16, minBit 1, minWin=22, winSum=371
8432 13:59:44.164851 TX Vref=18, minBit 0, minWin=23, winSum=382
8433 13:59:44.168539 TX Vref=20, minBit 0, minWin=23, winSum=396
8434 13:59:44.171784 TX Vref=22, minBit 0, minWin=24, winSum=405
8435 13:59:44.174724 TX Vref=24, minBit 0, minWin=25, winSum=417
8436 13:59:44.181380 TX Vref=26, minBit 0, minWin=25, winSum=425
8437 13:59:44.185059 TX Vref=28, minBit 1, minWin=25, winSum=428
8438 13:59:44.188239 TX Vref=30, minBit 0, minWin=25, winSum=423
8439 13:59:44.191482 TX Vref=32, minBit 6, minWin=24, winSum=414
8440 13:59:44.194825 TX Vref=34, minBit 0, minWin=23, winSum=401
8441 13:59:44.201740 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 28
8442 13:59:44.201890
8443 13:59:44.204963 Final TX Range 0 Vref 28
8444 13:59:44.205047
8445 13:59:44.205110 ==
8446 13:59:44.208122 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 13:59:44.211765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 13:59:44.211857 ==
8449 13:59:44.211924
8450 13:59:44.211982
8451 13:59:44.214816 TX Vref Scan disable
8452 13:59:44.221271 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8453 13:59:44.221359 == TX Byte 0 ==
8454 13:59:44.225086 u2DelayCellOfst[0]=17 cells (5 PI)
8455 13:59:44.228102 u2DelayCellOfst[1]=10 cells (3 PI)
8456 13:59:44.231188 u2DelayCellOfst[2]=0 cells (0 PI)
8457 13:59:44.235027 u2DelayCellOfst[3]=6 cells (2 PI)
8458 13:59:44.238116 u2DelayCellOfst[4]=10 cells (3 PI)
8459 13:59:44.241301 u2DelayCellOfst[5]=17 cells (5 PI)
8460 13:59:44.244688 u2DelayCellOfst[6]=17 cells (5 PI)
8461 13:59:44.244787 u2DelayCellOfst[7]=6 cells (2 PI)
8462 13:59:44.251345 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8463 13:59:44.255024 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8464 13:59:44.255127 == TX Byte 1 ==
8465 13:59:44.257971 u2DelayCellOfst[8]=0 cells (0 PI)
8466 13:59:44.261173 u2DelayCellOfst[9]=0 cells (0 PI)
8467 13:59:44.264710 u2DelayCellOfst[10]=10 cells (3 PI)
8468 13:59:44.267594 u2DelayCellOfst[11]=3 cells (1 PI)
8469 13:59:44.271346 u2DelayCellOfst[12]=13 cells (4 PI)
8470 13:59:44.274236 u2DelayCellOfst[13]=13 cells (4 PI)
8471 13:59:44.277851 u2DelayCellOfst[14]=13 cells (4 PI)
8472 13:59:44.281065 u2DelayCellOfst[15]=13 cells (4 PI)
8473 13:59:44.284435 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8474 13:59:44.291159 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8475 13:59:44.291275 DramC Write-DBI on
8476 13:59:44.291344 ==
8477 13:59:44.294178 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 13:59:44.298104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 13:59:44.300727 ==
8480 13:59:44.300808
8481 13:59:44.300871
8482 13:59:44.300929 TX Vref Scan disable
8483 13:59:44.304259 == TX Byte 0 ==
8484 13:59:44.307595 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8485 13:59:44.311160 == TX Byte 1 ==
8486 13:59:44.314402 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8487 13:59:44.314726 DramC Write-DBI off
8488 13:59:44.318187
8489 13:59:44.318421 [DATLAT]
8490 13:59:44.318605 Freq=1600, CH1 RK0
8491 13:59:44.318780
8492 13:59:44.321457 DATLAT Default: 0xf
8493 13:59:44.321779 0, 0xFFFF, sum = 0
8494 13:59:44.324811 1, 0xFFFF, sum = 0
8495 13:59:44.325084 2, 0xFFFF, sum = 0
8496 13:59:44.327651 3, 0xFFFF, sum = 0
8497 13:59:44.331442 4, 0xFFFF, sum = 0
8498 13:59:44.331633 5, 0xFFFF, sum = 0
8499 13:59:44.334566 6, 0xFFFF, sum = 0
8500 13:59:44.334761 7, 0xFFFF, sum = 0
8501 13:59:44.337391 8, 0xFFFF, sum = 0
8502 13:59:44.337474 9, 0xFFFF, sum = 0
8503 13:59:44.341333 10, 0xFFFF, sum = 0
8504 13:59:44.341423 11, 0xFFFF, sum = 0
8505 13:59:44.344500 12, 0xFFFF, sum = 0
8506 13:59:44.344585 13, 0xFFFF, sum = 0
8507 13:59:44.347715 14, 0x0, sum = 1
8508 13:59:44.347797 15, 0x0, sum = 2
8509 13:59:44.350928 16, 0x0, sum = 3
8510 13:59:44.351010 17, 0x0, sum = 4
8511 13:59:44.354620 best_step = 15
8512 13:59:44.354703
8513 13:59:44.354766 ==
8514 13:59:44.357767 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 13:59:44.360753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 13:59:44.360836 ==
8517 13:59:44.360900 RX Vref Scan: 1
8518 13:59:44.364384
8519 13:59:44.364495 Set Vref Range= 24 -> 127
8520 13:59:44.364562
8521 13:59:44.367656 RX Vref 24 -> 127, step: 1
8522 13:59:44.367738
8523 13:59:44.371196 RX Delay 27 -> 252, step: 4
8524 13:59:44.371277
8525 13:59:44.374668 Set Vref, RX VrefLevel [Byte0]: 24
8526 13:59:44.377820 [Byte1]: 24
8527 13:59:44.377905
8528 13:59:44.380931 Set Vref, RX VrefLevel [Byte0]: 25
8529 13:59:44.384206 [Byte1]: 25
8530 13:59:44.384298
8531 13:59:44.387495 Set Vref, RX VrefLevel [Byte0]: 26
8532 13:59:44.390834 [Byte1]: 26
8533 13:59:44.394704
8534 13:59:44.394786 Set Vref, RX VrefLevel [Byte0]: 27
8535 13:59:44.397946 [Byte1]: 27
8536 13:59:44.402420
8537 13:59:44.402516 Set Vref, RX VrefLevel [Byte0]: 28
8538 13:59:44.405578 [Byte1]: 28
8539 13:59:44.409930
8540 13:59:44.410014 Set Vref, RX VrefLevel [Byte0]: 29
8541 13:59:44.412833 [Byte1]: 29
8542 13:59:44.417062
8543 13:59:44.417144 Set Vref, RX VrefLevel [Byte0]: 30
8544 13:59:44.420294 [Byte1]: 30
8545 13:59:44.424405
8546 13:59:44.424492 Set Vref, RX VrefLevel [Byte0]: 31
8547 13:59:44.427956 [Byte1]: 31
8548 13:59:44.432182
8549 13:59:44.432333 Set Vref, RX VrefLevel [Byte0]: 32
8550 13:59:44.435207 [Byte1]: 32
8551 13:59:44.439419
8552 13:59:44.439504 Set Vref, RX VrefLevel [Byte0]: 33
8553 13:59:44.442768 [Byte1]: 33
8554 13:59:44.447023
8555 13:59:44.447104 Set Vref, RX VrefLevel [Byte0]: 34
8556 13:59:44.450862 [Byte1]: 34
8557 13:59:44.454949
8558 13:59:44.455039 Set Vref, RX VrefLevel [Byte0]: 35
8559 13:59:44.458117 [Byte1]: 35
8560 13:59:44.462586
8561 13:59:44.462678 Set Vref, RX VrefLevel [Byte0]: 36
8562 13:59:44.465490 [Byte1]: 36
8563 13:59:44.470005
8564 13:59:44.470122 Set Vref, RX VrefLevel [Byte0]: 37
8565 13:59:44.473193 [Byte1]: 37
8566 13:59:44.477321
8567 13:59:44.477416 Set Vref, RX VrefLevel [Byte0]: 38
8568 13:59:44.480794 [Byte1]: 38
8569 13:59:44.485291
8570 13:59:44.485395 Set Vref, RX VrefLevel [Byte0]: 39
8571 13:59:44.488422 [Byte1]: 39
8572 13:59:44.492547
8573 13:59:44.492628 Set Vref, RX VrefLevel [Byte0]: 40
8574 13:59:44.495587 [Byte1]: 40
8575 13:59:44.500064
8576 13:59:44.500145 Set Vref, RX VrefLevel [Byte0]: 41
8577 13:59:44.503195 [Byte1]: 41
8578 13:59:44.507608
8579 13:59:44.507716 Set Vref, RX VrefLevel [Byte0]: 42
8580 13:59:44.510696 [Byte1]: 42
8581 13:59:44.515191
8582 13:59:44.515275 Set Vref, RX VrefLevel [Byte0]: 43
8583 13:59:44.518176 [Byte1]: 43
8584 13:59:44.522834
8585 13:59:44.522913 Set Vref, RX VrefLevel [Byte0]: 44
8586 13:59:44.525963 [Byte1]: 44
8587 13:59:44.530542
8588 13:59:44.530624 Set Vref, RX VrefLevel [Byte0]: 45
8589 13:59:44.533688 [Byte1]: 45
8590 13:59:44.538020
8591 13:59:44.538100 Set Vref, RX VrefLevel [Byte0]: 46
8592 13:59:44.541256 [Byte1]: 46
8593 13:59:44.545408
8594 13:59:44.545564 Set Vref, RX VrefLevel [Byte0]: 47
8595 13:59:44.549101 [Byte1]: 47
8596 13:59:44.552606
8597 13:59:44.552761 Set Vref, RX VrefLevel [Byte0]: 48
8598 13:59:44.555956 [Byte1]: 48
8599 13:59:44.559981
8600 13:59:44.560123 Set Vref, RX VrefLevel [Byte0]: 49
8601 13:59:44.563510 [Byte1]: 49
8602 13:59:44.568444
8603 13:59:44.568524 Set Vref, RX VrefLevel [Byte0]: 50
8604 13:59:44.571405 [Byte1]: 50
8605 13:59:44.575391
8606 13:59:44.575526 Set Vref, RX VrefLevel [Byte0]: 51
8607 13:59:44.579489 [Byte1]: 51
8608 13:59:44.582788
8609 13:59:44.582949 Set Vref, RX VrefLevel [Byte0]: 52
8610 13:59:44.586202 [Byte1]: 52
8611 13:59:44.590488
8612 13:59:44.590675 Set Vref, RX VrefLevel [Byte0]: 53
8613 13:59:44.593908 [Byte1]: 53
8614 13:59:44.598016
8615 13:59:44.598225 Set Vref, RX VrefLevel [Byte0]: 54
8616 13:59:44.601086 [Byte1]: 54
8617 13:59:44.605784
8618 13:59:44.606011 Set Vref, RX VrefLevel [Byte0]: 55
8619 13:59:44.608866 [Byte1]: 55
8620 13:59:44.613135
8621 13:59:44.613333 Set Vref, RX VrefLevel [Byte0]: 56
8622 13:59:44.616170 [Byte1]: 56
8623 13:59:44.620812
8624 13:59:44.621147 Set Vref, RX VrefLevel [Byte0]: 57
8625 13:59:44.624140 [Byte1]: 57
8626 13:59:44.628418
8627 13:59:44.628890 Set Vref, RX VrefLevel [Byte0]: 58
8628 13:59:44.631628 [Byte1]: 58
8629 13:59:44.636281
8630 13:59:44.636877 Set Vref, RX VrefLevel [Byte0]: 59
8631 13:59:44.639217 [Byte1]: 59
8632 13:59:44.643645
8633 13:59:44.644193 Set Vref, RX VrefLevel [Byte0]: 60
8634 13:59:44.646615 [Byte1]: 60
8635 13:59:44.651540
8636 13:59:44.652084 Set Vref, RX VrefLevel [Byte0]: 61
8637 13:59:44.654390 [Byte1]: 61
8638 13:59:44.658499
8639 13:59:44.659048 Set Vref, RX VrefLevel [Byte0]: 62
8640 13:59:44.662058 [Byte1]: 62
8641 13:59:44.666030
8642 13:59:44.666545 Set Vref, RX VrefLevel [Byte0]: 63
8643 13:59:44.669726 [Byte1]: 63
8644 13:59:44.673743
8645 13:59:44.674282 Set Vref, RX VrefLevel [Byte0]: 64
8646 13:59:44.676788 [Byte1]: 64
8647 13:59:44.681531
8648 13:59:44.682064 Set Vref, RX VrefLevel [Byte0]: 65
8649 13:59:44.684721 [Byte1]: 65
8650 13:59:44.688760
8651 13:59:44.689387 Set Vref, RX VrefLevel [Byte0]: 66
8652 13:59:44.691948 [Byte1]: 66
8653 13:59:44.696072
8654 13:59:44.696639 Set Vref, RX VrefLevel [Byte0]: 67
8655 13:59:44.699561 [Byte1]: 67
8656 13:59:44.704212
8657 13:59:44.704723 Set Vref, RX VrefLevel [Byte0]: 68
8658 13:59:44.707173 [Byte1]: 68
8659 13:59:44.711242
8660 13:59:44.711652 Set Vref, RX VrefLevel [Byte0]: 69
8661 13:59:44.714768 [Byte1]: 69
8662 13:59:44.718697
8663 13:59:44.719233 Set Vref, RX VrefLevel [Byte0]: 70
8664 13:59:44.721990 [Byte1]: 70
8665 13:59:44.725972
8666 13:59:44.726675 Set Vref, RX VrefLevel [Byte0]: 71
8667 13:59:44.729329 [Byte1]: 71
8668 13:59:44.733721
8669 13:59:44.734133 Set Vref, RX VrefLevel [Byte0]: 72
8670 13:59:44.736986 [Byte1]: 72
8671 13:59:44.741258
8672 13:59:44.741669 Set Vref, RX VrefLevel [Byte0]: 73
8673 13:59:44.744563 [Byte1]: 73
8674 13:59:44.748839
8675 13:59:44.749254 Set Vref, RX VrefLevel [Byte0]: 74
8676 13:59:44.752371 [Byte1]: 74
8677 13:59:44.756410
8678 13:59:44.756836 Set Vref, RX VrefLevel [Byte0]: 75
8679 13:59:44.759463 [Byte1]: 75
8680 13:59:44.764005
8681 13:59:44.764695 Final RX Vref Byte 0 = 57 to rank0
8682 13:59:44.767334 Final RX Vref Byte 1 = 55 to rank0
8683 13:59:44.770435 Final RX Vref Byte 0 = 57 to rank1
8684 13:59:44.773972 Final RX Vref Byte 1 = 55 to rank1==
8685 13:59:44.777246 Dram Type= 6, Freq= 0, CH_1, rank 0
8686 13:59:44.783724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8687 13:59:44.784194 ==
8688 13:59:44.784666 DQS Delay:
8689 13:59:44.785078 DQS0 = 0, DQS1 = 0
8690 13:59:44.787399 DQM Delay:
8691 13:59:44.787824 DQM0 = 134, DQM1 = 131
8692 13:59:44.790494 DQ Delay:
8693 13:59:44.793715 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8694 13:59:44.797014 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8695 13:59:44.801179 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8696 13:59:44.804089 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8697 13:59:44.804605
8698 13:59:44.804933
8699 13:59:44.805235
8700 13:59:44.807309 [DramC_TX_OE_Calibration] TA2
8701 13:59:44.810630 Original DQ_B0 (3 6) =30, OEN = 27
8702 13:59:44.813861 Original DQ_B1 (3 6) =30, OEN = 27
8703 13:59:44.816920 24, 0x0, End_B0=24 End_B1=24
8704 13:59:44.817450 25, 0x0, End_B0=25 End_B1=25
8705 13:59:44.820179 26, 0x0, End_B0=26 End_B1=26
8706 13:59:44.824149 27, 0x0, End_B0=27 End_B1=27
8707 13:59:44.827043 28, 0x0, End_B0=28 End_B1=28
8708 13:59:44.827461 29, 0x0, End_B0=29 End_B1=29
8709 13:59:44.831135 30, 0x0, End_B0=30 End_B1=30
8710 13:59:44.833967 31, 0x4141, End_B0=30 End_B1=30
8711 13:59:44.837020 Byte0 end_step=30 best_step=27
8712 13:59:44.840752 Byte1 end_step=30 best_step=27
8713 13:59:44.843721 Byte0 TX OE(2T, 0.5T) = (3, 3)
8714 13:59:44.844239 Byte1 TX OE(2T, 0.5T) = (3, 3)
8715 13:59:44.847177
8716 13:59:44.847586
8717 13:59:44.854207 [DQSOSCAuto] RK0, (LSB)MR18= 0x1926, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8718 13:59:44.857159 CH1 RK0: MR19=303, MR18=1926
8719 13:59:44.864060 CH1_RK0: MR19=0x303, MR18=0x1926, DQSOSC=390, MR23=63, INC=24, DEC=16
8720 13:59:44.864624
8721 13:59:44.867462 ----->DramcWriteLeveling(PI) begin...
8722 13:59:44.867877 ==
8723 13:59:44.870375 Dram Type= 6, Freq= 0, CH_1, rank 1
8724 13:59:44.873678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 13:59:44.874093 ==
8726 13:59:44.876889 Write leveling (Byte 0): 26 => 26
8727 13:59:44.880330 Write leveling (Byte 1): 28 => 28
8728 13:59:44.883481 DramcWriteLeveling(PI) end<-----
8729 13:59:44.883935
8730 13:59:44.884321 ==
8731 13:59:44.886723 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 13:59:44.890112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 13:59:44.890529 ==
8734 13:59:44.893301 [Gating] SW mode calibration
8735 13:59:44.900087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8736 13:59:44.906790 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8737 13:59:44.910518 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 13:59:44.913201 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 13:59:44.920245 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8740 13:59:44.923447 1 4 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
8741 13:59:44.927409 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 13:59:44.934087 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 13:59:44.937347 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 13:59:44.940570 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 13:59:44.947156 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 13:59:44.949903 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8747 13:59:44.953469 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8748 13:59:44.960257 1 5 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8749 13:59:44.963346 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 13:59:44.966625 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 13:59:44.973907 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 13:59:44.977100 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 13:59:44.980571 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 13:59:44.986934 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 13:59:44.990391 1 6 8 | B1->B0 | 3d3d 2323 | 0 0 | (0 0) (0 0)
8756 13:59:44.993521 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8757 13:59:45.000573 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 13:59:45.003430 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 13:59:45.006724 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 13:59:45.012905 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 13:59:45.016747 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 13:59:45.019798 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8763 13:59:45.023181 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8764 13:59:45.029906 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8765 13:59:45.032909 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8766 13:59:45.036550 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 13:59:45.043801 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 13:59:45.046832 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 13:59:45.050016 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 13:59:45.056224 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 13:59:45.059617 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 13:59:45.063412 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 13:59:45.069810 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 13:59:45.073013 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 13:59:45.076790 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 13:59:45.083467 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 13:59:45.086460 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 13:59:45.089721 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8779 13:59:45.096740 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8780 13:59:45.099634 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8781 13:59:45.102617 Total UI for P1: 0, mck2ui 16
8782 13:59:45.106461 best dqsien dly found for B1: ( 1, 9, 6)
8783 13:59:45.109230 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8784 13:59:45.116375 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 13:59:45.116834 Total UI for P1: 0, mck2ui 16
8786 13:59:45.122764 best dqsien dly found for B0: ( 1, 9, 14)
8787 13:59:45.126107 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8788 13:59:45.129413 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8789 13:59:45.129867
8790 13:59:45.132645 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8791 13:59:45.136475 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8792 13:59:45.139597 [Gating] SW calibration Done
8793 13:59:45.140152 ==
8794 13:59:45.143428 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 13:59:45.145903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 13:59:45.146364 ==
8797 13:59:45.149489 RX Vref Scan: 0
8798 13:59:45.149943
8799 13:59:45.150297 RX Vref 0 -> 0, step: 1
8800 13:59:45.150631
8801 13:59:45.152491 RX Delay 0 -> 252, step: 8
8802 13:59:45.155743 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8803 13:59:45.162984 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8804 13:59:45.165861 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8805 13:59:45.169208 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8806 13:59:45.172707 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8807 13:59:45.175836 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8808 13:59:45.182422 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8809 13:59:45.185839 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8810 13:59:45.188973 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8811 13:59:45.192405 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8812 13:59:45.196514 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8813 13:59:45.199431 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8814 13:59:45.205561 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8815 13:59:45.208809 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8816 13:59:45.212282 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8817 13:59:45.215559 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8818 13:59:45.216019 ==
8819 13:59:45.219570 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 13:59:45.225886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 13:59:45.226448 ==
8822 13:59:45.226814 DQS Delay:
8823 13:59:45.228846 DQS0 = 0, DQS1 = 0
8824 13:59:45.229306 DQM Delay:
8825 13:59:45.232687 DQM0 = 136, DQM1 = 134
8826 13:59:45.233142 DQ Delay:
8827 13:59:45.235743 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8828 13:59:45.239057 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8829 13:59:45.242505 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8830 13:59:45.245693 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8831 13:59:45.246254
8832 13:59:45.246619
8833 13:59:45.246951 ==
8834 13:59:45.249375 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 13:59:45.255663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 13:59:45.256233 ==
8837 13:59:45.256639
8838 13:59:45.256977
8839 13:59:45.257297 TX Vref Scan disable
8840 13:59:45.259223 == TX Byte 0 ==
8841 13:59:45.262258 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8842 13:59:45.268697 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8843 13:59:45.269155 == TX Byte 1 ==
8844 13:59:45.272040 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8845 13:59:45.279237 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8846 13:59:45.279657 ==
8847 13:59:45.282202 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 13:59:45.285159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 13:59:45.285573 ==
8850 13:59:45.299146
8851 13:59:45.302198 TX Vref early break, caculate TX vref
8852 13:59:45.305388 TX Vref=16, minBit 0, minWin=23, winSum=382
8853 13:59:45.308870 TX Vref=18, minBit 0, minWin=23, winSum=389
8854 13:59:45.311920 TX Vref=20, minBit 0, minWin=24, winSum=399
8855 13:59:45.315437 TX Vref=22, minBit 0, minWin=25, winSum=415
8856 13:59:45.318630 TX Vref=24, minBit 0, minWin=25, winSum=418
8857 13:59:45.325338 TX Vref=26, minBit 0, minWin=25, winSum=425
8858 13:59:45.328923 TX Vref=28, minBit 0, minWin=24, winSum=427
8859 13:59:45.332077 TX Vref=30, minBit 1, minWin=25, winSum=420
8860 13:59:45.335399 TX Vref=32, minBit 0, minWin=25, winSum=414
8861 13:59:45.338387 TX Vref=34, minBit 0, minWin=24, winSum=405
8862 13:59:45.341667 TX Vref=36, minBit 0, minWin=24, winSum=397
8863 13:59:45.348838 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8864 13:59:45.349344
8865 13:59:45.352326 Final TX Range 0 Vref 26
8866 13:59:45.352842
8867 13:59:45.353163 ==
8868 13:59:45.355298 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 13:59:45.358470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 13:59:45.358931 ==
8871 13:59:45.359255
8872 13:59:45.359550
8873 13:59:45.362188 TX Vref Scan disable
8874 13:59:45.368807 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8875 13:59:45.369217 == TX Byte 0 ==
8876 13:59:45.372223 u2DelayCellOfst[0]=17 cells (5 PI)
8877 13:59:45.375517 u2DelayCellOfst[1]=10 cells (3 PI)
8878 13:59:45.378845 u2DelayCellOfst[2]=0 cells (0 PI)
8879 13:59:45.381698 u2DelayCellOfst[3]=6 cells (2 PI)
8880 13:59:45.384989 u2DelayCellOfst[4]=6 cells (2 PI)
8881 13:59:45.388487 u2DelayCellOfst[5]=17 cells (5 PI)
8882 13:59:45.391985 u2DelayCellOfst[6]=17 cells (5 PI)
8883 13:59:45.395301 u2DelayCellOfst[7]=6 cells (2 PI)
8884 13:59:45.398536 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8885 13:59:45.401647 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8886 13:59:45.404756 == TX Byte 1 ==
8887 13:59:45.405164 u2DelayCellOfst[8]=0 cells (0 PI)
8888 13:59:45.408367 u2DelayCellOfst[9]=3 cells (1 PI)
8889 13:59:45.411833 u2DelayCellOfst[10]=10 cells (3 PI)
8890 13:59:45.414569 u2DelayCellOfst[11]=3 cells (1 PI)
8891 13:59:45.418248 u2DelayCellOfst[12]=13 cells (4 PI)
8892 13:59:45.421357 u2DelayCellOfst[13]=17 cells (5 PI)
8893 13:59:45.425259 u2DelayCellOfst[14]=17 cells (5 PI)
8894 13:59:45.428405 u2DelayCellOfst[15]=17 cells (5 PI)
8895 13:59:45.431496 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8896 13:59:45.437843 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8897 13:59:45.438064 DramC Write-DBI on
8898 13:59:45.438237 ==
8899 13:59:45.441421 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 13:59:45.447917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 13:59:45.448066 ==
8902 13:59:45.448182
8903 13:59:45.448304
8904 13:59:45.448412 TX Vref Scan disable
8905 13:59:45.451256 == TX Byte 0 ==
8906 13:59:45.455261 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8907 13:59:45.458058 == TX Byte 1 ==
8908 13:59:45.461545 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8909 13:59:45.461666 DramC Write-DBI off
8910 13:59:45.464487
8911 13:59:45.464605 [DATLAT]
8912 13:59:45.464690 Freq=1600, CH1 RK1
8913 13:59:45.464785
8914 13:59:45.468036 DATLAT Default: 0xf
8915 13:59:45.468175 0, 0xFFFF, sum = 0
8916 13:59:45.471262 1, 0xFFFF, sum = 0
8917 13:59:45.471411 2, 0xFFFF, sum = 0
8918 13:59:45.474494 3, 0xFFFF, sum = 0
8919 13:59:45.478408 4, 0xFFFF, sum = 0
8920 13:59:45.478520 5, 0xFFFF, sum = 0
8921 13:59:45.481413 6, 0xFFFF, sum = 0
8922 13:59:45.481525 7, 0xFFFF, sum = 0
8923 13:59:45.484636 8, 0xFFFF, sum = 0
8924 13:59:45.484753 9, 0xFFFF, sum = 0
8925 13:59:45.488510 10, 0xFFFF, sum = 0
8926 13:59:45.489198 11, 0xFFFF, sum = 0
8927 13:59:45.491743 12, 0xFFFF, sum = 0
8928 13:59:45.492161 13, 0xFFFF, sum = 0
8929 13:59:45.494910 14, 0x0, sum = 1
8930 13:59:45.495324 15, 0x0, sum = 2
8931 13:59:45.498364 16, 0x0, sum = 3
8932 13:59:45.499010 17, 0x0, sum = 4
8933 13:59:45.501553 best_step = 15
8934 13:59:45.501957
8935 13:59:45.502275 ==
8936 13:59:45.504772 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 13:59:45.508107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 13:59:45.508651 ==
8939 13:59:45.508980 RX Vref Scan: 0
8940 13:59:45.511471
8941 13:59:45.511877 RX Vref 0 -> 0, step: 1
8942 13:59:45.512200
8943 13:59:45.515313 RX Delay 19 -> 252, step: 4
8944 13:59:45.518377 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8945 13:59:45.524709 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8946 13:59:45.528437 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8947 13:59:45.531523 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8948 13:59:45.535168 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8949 13:59:45.538563 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8950 13:59:45.541713 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8951 13:59:45.547942 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8952 13:59:45.551662 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8953 13:59:45.554998 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8954 13:59:45.558513 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8955 13:59:45.561597 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8956 13:59:45.568078 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8957 13:59:45.571706 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8958 13:59:45.574584 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8959 13:59:45.578330 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8960 13:59:45.578878 ==
8961 13:59:45.581468 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 13:59:45.588498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 13:59:45.589188 ==
8964 13:59:45.589848 DQS Delay:
8965 13:59:45.591202 DQS0 = 0, DQS1 = 0
8966 13:59:45.591827 DQM Delay:
8967 13:59:45.594653 DQM0 = 134, DQM1 = 130
8968 13:59:45.595103 DQ Delay:
8969 13:59:45.598011 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8970 13:59:45.601480 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8971 13:59:45.604553 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =126
8972 13:59:45.607888 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8973 13:59:45.608387
8974 13:59:45.608751
8975 13:59:45.609078
8976 13:59:45.611122 [DramC_TX_OE_Calibration] TA2
8977 13:59:45.614504 Original DQ_B0 (3 6) =30, OEN = 27
8978 13:59:45.618407 Original DQ_B1 (3 6) =30, OEN = 27
8979 13:59:45.621244 24, 0x0, End_B0=24 End_B1=24
8980 13:59:45.621706 25, 0x0, End_B0=25 End_B1=25
8981 13:59:45.624678 26, 0x0, End_B0=26 End_B1=26
8982 13:59:45.628403 27, 0x0, End_B0=27 End_B1=27
8983 13:59:45.631130 28, 0x0, End_B0=28 End_B1=28
8984 13:59:45.635021 29, 0x0, End_B0=29 End_B1=29
8985 13:59:45.635579 30, 0x0, End_B0=30 End_B1=30
8986 13:59:45.637654 31, 0x5151, End_B0=30 End_B1=30
8987 13:59:45.641648 Byte0 end_step=30 best_step=27
8988 13:59:45.644901 Byte1 end_step=30 best_step=27
8989 13:59:45.647970 Byte0 TX OE(2T, 0.5T) = (3, 3)
8990 13:59:45.651269 Byte1 TX OE(2T, 0.5T) = (3, 3)
8991 13:59:45.651818
8992 13:59:45.652176
8993 13:59:45.657949 [DQSOSCAuto] RK1, (LSB)MR18= 0x240a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
8994 13:59:45.661043 CH1 RK1: MR19=303, MR18=240A
8995 13:59:45.667529 CH1_RK1: MR19=0x303, MR18=0x240A, DQSOSC=391, MR23=63, INC=24, DEC=16
8996 13:59:45.670970 [RxdqsGatingPostProcess] freq 1600
8997 13:59:45.674743 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8998 13:59:45.677781 best DQS0 dly(2T, 0.5T) = (1, 1)
8999 13:59:45.681025 best DQS1 dly(2T, 0.5T) = (1, 1)
9000 13:59:45.684514 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9001 13:59:45.687534 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9002 13:59:45.691357 best DQS0 dly(2T, 0.5T) = (1, 1)
9003 13:59:45.694474 best DQS1 dly(2T, 0.5T) = (1, 1)
9004 13:59:45.697931 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9005 13:59:45.701020 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9006 13:59:45.704165 Pre-setting of DQS Precalculation
9007 13:59:45.707741 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9008 13:59:45.714508 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9009 13:59:45.724068 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9010 13:59:45.724589
9011 13:59:45.724954
9012 13:59:45.727185 [Calibration Summary] 3200 Mbps
9013 13:59:45.727640 CH 0, Rank 0
9014 13:59:45.730812 SW Impedance : PASS
9015 13:59:45.731269 DUTY Scan : NO K
9016 13:59:45.734062 ZQ Calibration : PASS
9017 13:59:45.737316 Jitter Meter : NO K
9018 13:59:45.737866 CBT Training : PASS
9019 13:59:45.740686 Write leveling : PASS
9020 13:59:45.741144 RX DQS gating : PASS
9021 13:59:45.743787 RX DQ/DQS(RDDQC) : PASS
9022 13:59:45.747084 TX DQ/DQS : PASS
9023 13:59:45.747618 RX DATLAT : PASS
9024 13:59:45.750666 RX DQ/DQS(Engine): PASS
9025 13:59:45.753773 TX OE : PASS
9026 13:59:45.754250 All Pass.
9027 13:59:45.754665
9028 13:59:45.754981 CH 0, Rank 1
9029 13:59:45.756746 SW Impedance : PASS
9030 13:59:45.760527 DUTY Scan : NO K
9031 13:59:45.760974 ZQ Calibration : PASS
9032 13:59:45.763673 Jitter Meter : NO K
9033 13:59:45.767087 CBT Training : PASS
9034 13:59:45.767572 Write leveling : PASS
9035 13:59:45.770201 RX DQS gating : PASS
9036 13:59:45.773535 RX DQ/DQS(RDDQC) : PASS
9037 13:59:45.773952 TX DQ/DQS : PASS
9038 13:59:45.777066 RX DATLAT : PASS
9039 13:59:45.780155 RX DQ/DQS(Engine): PASS
9040 13:59:45.780603 TX OE : PASS
9041 13:59:45.784392 All Pass.
9042 13:59:45.784896
9043 13:59:45.785215 CH 1, Rank 0
9044 13:59:45.787285 SW Impedance : PASS
9045 13:59:45.787694 DUTY Scan : NO K
9046 13:59:45.790608 ZQ Calibration : PASS
9047 13:59:45.793850 Jitter Meter : NO K
9048 13:59:45.794256 CBT Training : PASS
9049 13:59:45.797003 Write leveling : PASS
9050 13:59:45.797411 RX DQS gating : PASS
9051 13:59:45.800506 RX DQ/DQS(RDDQC) : PASS
9052 13:59:45.803796 TX DQ/DQS : PASS
9053 13:59:45.804384 RX DATLAT : PASS
9054 13:59:45.806660 RX DQ/DQS(Engine): PASS
9055 13:59:45.809939 TX OE : PASS
9056 13:59:45.810394 All Pass.
9057 13:59:45.810746
9058 13:59:45.811071 CH 1, Rank 1
9059 13:59:45.813716 SW Impedance : PASS
9060 13:59:45.816890 DUTY Scan : NO K
9061 13:59:45.817341 ZQ Calibration : PASS
9062 13:59:45.819960 Jitter Meter : NO K
9063 13:59:45.823194 CBT Training : PASS
9064 13:59:45.823602 Write leveling : PASS
9065 13:59:45.826942 RX DQS gating : PASS
9066 13:59:45.830065 RX DQ/DQS(RDDQC) : PASS
9067 13:59:45.830475 TX DQ/DQS : PASS
9068 13:59:45.833580 RX DATLAT : PASS
9069 13:59:45.836983 RX DQ/DQS(Engine): PASS
9070 13:59:45.837493 TX OE : PASS
9071 13:59:45.837817 All Pass.
9072 13:59:45.840137
9073 13:59:45.840739 DramC Write-DBI on
9074 13:59:45.843671 PER_BANK_REFRESH: Hybrid Mode
9075 13:59:45.844126 TX_TRACKING: ON
9076 13:59:45.853311 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9077 13:59:45.860019 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9078 13:59:45.869756 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9079 13:59:45.872998 [FAST_K] Save calibration result to emmc
9080 13:59:45.873411 sync common calibartion params.
9081 13:59:45.876341 sync cbt_mode0:1, 1:1
9082 13:59:45.879516 dram_init: ddr_geometry: 2
9083 13:59:45.882920 dram_init: ddr_geometry: 2
9084 13:59:45.883140 dram_init: ddr_geometry: 2
9085 13:59:45.886508 0:dram_rank_size:100000000
9086 13:59:45.889619 1:dram_rank_size:100000000
9087 13:59:45.893190 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9088 13:59:45.896151 DFS_SHUFFLE_HW_MODE: ON
9089 13:59:45.899320 dramc_set_vcore_voltage set vcore to 725000
9090 13:59:45.903237 Read voltage for 1600, 0
9091 13:59:45.903348 Vio18 = 0
9092 13:59:45.906006 Vcore = 725000
9093 13:59:45.906118 Vdram = 0
9094 13:59:45.906205 Vddq = 0
9095 13:59:45.906285 Vmddr = 0
9096 13:59:45.909415 switch to 3200 Mbps bootup
9097 13:59:45.912902 [DramcRunTimeConfig]
9098 13:59:45.912993 PHYPLL
9099 13:59:45.915984 DPM_CONTROL_AFTERK: ON
9100 13:59:45.916073 PER_BANK_REFRESH: ON
9101 13:59:45.919583 REFRESH_OVERHEAD_REDUCTION: ON
9102 13:59:45.922699 CMD_PICG_NEW_MODE: OFF
9103 13:59:45.922779 XRTWTW_NEW_MODE: ON
9104 13:59:45.925828 XRTRTR_NEW_MODE: ON
9105 13:59:45.925934 TX_TRACKING: ON
9106 13:59:45.929675 RDSEL_TRACKING: OFF
9107 13:59:45.932933 DQS Precalculation for DVFS: ON
9108 13:59:45.933014 RX_TRACKING: OFF
9109 13:59:45.933077 HW_GATING DBG: ON
9110 13:59:45.936177 ZQCS_ENABLE_LP4: ON
9111 13:59:45.939486 RX_PICG_NEW_MODE: ON
9112 13:59:45.939566 TX_PICG_NEW_MODE: ON
9113 13:59:45.942751 ENABLE_RX_DCM_DPHY: ON
9114 13:59:45.945895 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9115 13:59:45.945975 DUMMY_READ_FOR_TRACKING: OFF
9116 13:59:45.949695 !!! SPM_CONTROL_AFTERK: OFF
9117 13:59:45.952910 !!! SPM could not control APHY
9118 13:59:45.955634 IMPEDANCE_TRACKING: ON
9119 13:59:45.955714 TEMP_SENSOR: ON
9120 13:59:45.959191 HW_SAVE_FOR_SR: OFF
9121 13:59:45.962870 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9122 13:59:45.966147 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9123 13:59:45.966228 Read ODT Tracking: ON
9124 13:59:45.969210 Refresh Rate DeBounce: ON
9125 13:59:45.972377 DFS_NO_QUEUE_FLUSH: ON
9126 13:59:45.975563 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9127 13:59:45.975643 ENABLE_DFS_RUNTIME_MRW: OFF
9128 13:59:45.979223 DDR_RESERVE_NEW_MODE: ON
9129 13:59:45.982274 MR_CBT_SWITCH_FREQ: ON
9130 13:59:45.982354 =========================
9131 13:59:46.002656 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9132 13:59:46.005865 dram_init: ddr_geometry: 2
9133 13:59:46.024191 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9134 13:59:46.027378 dram_init: dram init end (result: 0)
9135 13:59:46.034039 DRAM-K: Full calibration passed in 24433 msecs
9136 13:59:46.037117 MRC: failed to locate region type 0.
9137 13:59:46.037198 DRAM rank0 size:0x100000000,
9138 13:59:46.040867 DRAM rank1 size=0x100000000
9139 13:59:46.050677 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9140 13:59:46.057351 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9141 13:59:46.063763 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9142 13:59:46.070582 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9143 13:59:46.073721 DRAM rank0 size:0x100000000,
9144 13:59:46.077475 DRAM rank1 size=0x100000000
9145 13:59:46.077557 CBMEM:
9146 13:59:46.080628 IMD: root @ 0xfffff000 254 entries.
9147 13:59:46.083796 IMD: root @ 0xffffec00 62 entries.
9148 13:59:46.087403 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9149 13:59:46.090452 WARNING: RO_VPD is uninitialized or empty.
9150 13:59:46.097495 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9151 13:59:46.103987 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9152 13:59:46.116965 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9153 13:59:46.128430 BS: romstage times (exec / console): total (unknown) / 23967 ms
9154 13:59:46.128522
9155 13:59:46.128584
9156 13:59:46.138577 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9157 13:59:46.141313 ARM64: Exception handlers installed.
9158 13:59:46.145044 ARM64: Testing exception
9159 13:59:46.147998 ARM64: Done test exception
9160 13:59:46.148078 Enumerating buses...
9161 13:59:46.151438 Show all devs... Before device enumeration.
9162 13:59:46.154626 Root Device: enabled 1
9163 13:59:46.157956 CPU_CLUSTER: 0: enabled 1
9164 13:59:46.158038 CPU: 00: enabled 1
9165 13:59:46.161263 Compare with tree...
9166 13:59:46.161343 Root Device: enabled 1
9167 13:59:46.164484 CPU_CLUSTER: 0: enabled 1
9168 13:59:46.167861 CPU: 00: enabled 1
9169 13:59:46.167946 Root Device scanning...
9170 13:59:46.171052 scan_static_bus for Root Device
9171 13:59:46.174383 CPU_CLUSTER: 0 enabled
9172 13:59:46.177671 scan_static_bus for Root Device done
9173 13:59:46.181274 scan_bus: bus Root Device finished in 8 msecs
9174 13:59:46.181355 done
9175 13:59:46.188105 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9176 13:59:46.190959 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9177 13:59:46.197762 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9178 13:59:46.201279 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9179 13:59:46.204454 Allocating resources...
9180 13:59:46.207750 Reading resources...
9181 13:59:46.211535 Root Device read_resources bus 0 link: 0
9182 13:59:46.211678 DRAM rank0 size:0x100000000,
9183 13:59:46.214478 DRAM rank1 size=0x100000000
9184 13:59:46.217796 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9185 13:59:46.221338 CPU: 00 missing read_resources
9186 13:59:46.224267 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9187 13:59:46.231530 Root Device read_resources bus 0 link: 0 done
9188 13:59:46.232019 Done reading resources.
9189 13:59:46.237971 Show resources in subtree (Root Device)...After reading.
9190 13:59:46.241275 Root Device child on link 0 CPU_CLUSTER: 0
9191 13:59:46.244721 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 13:59:46.254621 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 13:59:46.255042 CPU: 00
9194 13:59:46.258180 Root Device assign_resources, bus 0 link: 0
9195 13:59:46.261062 CPU_CLUSTER: 0 missing set_resources
9196 13:59:46.268009 Root Device assign_resources, bus 0 link: 0 done
9197 13:59:46.268462 Done setting resources.
9198 13:59:46.274434 Show resources in subtree (Root Device)...After assigning values.
9199 13:59:46.278199 Root Device child on link 0 CPU_CLUSTER: 0
9200 13:59:46.281432 CPU_CLUSTER: 0 child on link 0 CPU: 00
9201 13:59:46.291093 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9202 13:59:46.291674 CPU: 00
9203 13:59:46.294403 Done allocating resources.
9204 13:59:46.297651 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9205 13:59:46.301103 Enabling resources...
9206 13:59:46.301472 done.
9207 13:59:46.307640 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9208 13:59:46.307878 Initializing devices...
9209 13:59:46.310892 Root Device init
9210 13:59:46.311141 init hardware done!
9211 13:59:46.314689 0x00000018: ctrlr->caps
9212 13:59:46.317796 52.000 MHz: ctrlr->f_max
9213 13:59:46.317970 0.400 MHz: ctrlr->f_min
9214 13:59:46.321041 0x40ff8080: ctrlr->voltages
9215 13:59:46.321217 sclk: 390625
9216 13:59:46.324205 Bus Width = 1
9217 13:59:46.324360 sclk: 390625
9218 13:59:46.324498 Bus Width = 1
9219 13:59:46.327729 Early init status = 3
9220 13:59:46.330963 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9221 13:59:46.335359 in-header: 03 fc 00 00 01 00 00 00
9222 13:59:46.338901 in-data: 00
9223 13:59:46.342535 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9224 13:59:46.347004 in-header: 03 fd 00 00 00 00 00 00
9225 13:59:46.350115 in-data:
9226 13:59:46.353323 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9227 13:59:46.357073 in-header: 03 fc 00 00 01 00 00 00
9228 13:59:46.360254 in-data: 00
9229 13:59:46.363472 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9230 13:59:46.368225 in-header: 03 fd 00 00 00 00 00 00
9231 13:59:46.371754 in-data:
9232 13:59:46.374904 [SSUSB] Setting up USB HOST controller...
9233 13:59:46.378073 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9234 13:59:46.381276 [SSUSB] phy power-on done.
9235 13:59:46.385021 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9236 13:59:46.391395 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9237 13:59:46.394696 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9238 13:59:46.401571 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9239 13:59:46.408094 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9240 13:59:46.414456 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9241 13:59:46.421028 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9242 13:59:46.427848 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9243 13:59:46.431386 SPM: binary array size = 0x9dc
9244 13:59:46.434785 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9245 13:59:46.441007 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9246 13:59:46.447757 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9247 13:59:46.451001 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9248 13:59:46.457576 configure_display: Starting display init
9249 13:59:46.491367 anx7625_power_on_init: Init interface.
9250 13:59:46.494464 anx7625_disable_pd_protocol: Disabled PD feature.
9251 13:59:46.498188 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9252 13:59:46.525763 anx7625_start_dp_work: Secure OCM version=00
9253 13:59:46.528788 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9254 13:59:46.543771 sp_tx_get_edid_block: EDID Block = 1
9255 13:59:46.646533 Extracted contents:
9256 13:59:46.649820 header: 00 ff ff ff ff ff ff 00
9257 13:59:46.653454 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9258 13:59:46.656688 version: 01 04
9259 13:59:46.659595 basic params: 95 1f 11 78 0a
9260 13:59:46.663053 chroma info: 76 90 94 55 54 90 27 21 50 54
9261 13:59:46.666263 established: 00 00 00
9262 13:59:46.672948 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9263 13:59:46.676132 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9264 13:59:46.682496 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9265 13:59:46.689642 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9266 13:59:46.696011 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9267 13:59:46.699367 extensions: 00
9268 13:59:46.699469 checksum: fb
9269 13:59:46.699563
9270 13:59:46.702489 Manufacturer: IVO Model 57d Serial Number 0
9271 13:59:46.705715 Made week 0 of 2020
9272 13:59:46.709637 EDID version: 1.4
9273 13:59:46.709771 Digital display
9274 13:59:46.712642 6 bits per primary color channel
9275 13:59:46.712753 DisplayPort interface
9276 13:59:46.715942 Maximum image size: 31 cm x 17 cm
9277 13:59:46.719219 Gamma: 220%
9278 13:59:46.719321 Check DPMS levels
9279 13:59:46.722580 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9280 13:59:46.725721 First detailed timing is preferred timing
9281 13:59:46.729529 Established timings supported:
9282 13:59:46.732690 Standard timings supported:
9283 13:59:46.735919 Detailed timings
9284 13:59:46.739556 Hex of detail: 383680a07038204018303c0035ae10000019
9285 13:59:46.742423 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9286 13:59:46.749135 0780 0798 07c8 0820 hborder 0
9287 13:59:46.752875 0438 043b 0447 0458 vborder 0
9288 13:59:46.755536 -hsync -vsync
9289 13:59:46.755616 Did detailed timing
9290 13:59:46.762355 Hex of detail: 000000000000000000000000000000000000
9291 13:59:46.762436 Manufacturer-specified data, tag 0
9292 13:59:46.769381 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9293 13:59:46.772526 ASCII string: InfoVision
9294 13:59:46.775794 Hex of detail: 000000fe00523134304e574635205248200a
9295 13:59:46.778926 ASCII string: R140NWF5 RH
9296 13:59:46.779010 Checksum
9297 13:59:46.781928 Checksum: 0xfb (valid)
9298 13:59:46.785680 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9299 13:59:46.788939 DSI data_rate: 832800000 bps
9300 13:59:46.795302 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9301 13:59:46.798661 anx7625_parse_edid: pixelclock(138800).
9302 13:59:46.802035 hactive(1920), hsync(48), hfp(24), hbp(88)
9303 13:59:46.805286 vactive(1080), vsync(12), vfp(3), vbp(17)
9304 13:59:46.808551 anx7625_dsi_config: config dsi.
9305 13:59:46.815453 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9306 13:59:46.828408 anx7625_dsi_config: success to config DSI
9307 13:59:46.831496 anx7625_dp_start: MIPI phy setup OK.
9308 13:59:46.835495 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9309 13:59:46.838689 mtk_ddp_mode_set invalid vrefresh 60
9310 13:59:46.841665 main_disp_path_setup
9311 13:59:46.841782 ovl_layer_smi_id_en
9312 13:59:46.845342 ovl_layer_smi_id_en
9313 13:59:46.845449 ccorr_config
9314 13:59:46.845546 aal_config
9315 13:59:46.848539 gamma_config
9316 13:59:46.848645 postmask_config
9317 13:59:46.851547 dither_config
9318 13:59:46.855192 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9319 13:59:46.861444 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9320 13:59:46.865146 Root Device init finished in 551 msecs
9321 13:59:46.865255 CPU_CLUSTER: 0 init
9322 13:59:46.875072 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9323 13:59:46.878175 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9324 13:59:46.881629 APU_MBOX 0x190000b0 = 0x10001
9325 13:59:46.884920 APU_MBOX 0x190001b0 = 0x10001
9326 13:59:46.888258 APU_MBOX 0x190005b0 = 0x10001
9327 13:59:46.891572 APU_MBOX 0x190006b0 = 0x10001
9328 13:59:46.894968 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9329 13:59:46.907668 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9330 13:59:46.919760 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9331 13:59:46.926741 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9332 13:59:46.938314 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9333 13:59:46.947364 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9334 13:59:46.950912 CPU_CLUSTER: 0 init finished in 81 msecs
9335 13:59:46.953926 Devices initialized
9336 13:59:46.957148 Show all devs... After init.
9337 13:59:46.957254 Root Device: enabled 1
9338 13:59:46.960473 CPU_CLUSTER: 0: enabled 1
9339 13:59:46.963414 CPU: 00: enabled 1
9340 13:59:46.967074 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9341 13:59:46.970381 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9342 13:59:46.973576 ELOG: NV offset 0x57f000 size 0x1000
9343 13:59:46.980645 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9344 13:59:46.986830 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9345 13:59:46.990473 ELOG: Event(17) added with size 13 at 2024-02-01 13:57:04 UTC
9346 13:59:46.993464 out: cmd=0x121: 03 db 21 01 00 00 00 00
9347 13:59:46.997478 in-header: 03 f6 00 00 2c 00 00 00
9348 13:59:47.010747 in-data: 69 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9349 13:59:47.017361 ELOG: Event(A1) added with size 10 at 2024-02-01 13:57:04 UTC
9350 13:59:47.023850 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9351 13:59:47.030883 ELOG: Event(A0) added with size 9 at 2024-02-01 13:57:04 UTC
9352 13:59:47.034096 elog_add_boot_reason: Logged dev mode boot
9353 13:59:47.037389 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9354 13:59:47.040604 Finalize devices...
9355 13:59:47.040706 Devices finalized
9356 13:59:47.047451 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9357 13:59:47.050752 Writing coreboot table at 0xffe64000
9358 13:59:47.053916 0. 000000000010a000-0000000000113fff: RAMSTAGE
9359 13:59:47.056884 1. 0000000040000000-00000000400fffff: RAM
9360 13:59:47.063838 2. 0000000040100000-000000004032afff: RAMSTAGE
9361 13:59:47.067481 3. 000000004032b000-00000000545fffff: RAM
9362 13:59:47.070399 4. 0000000054600000-000000005465ffff: BL31
9363 13:59:47.074130 5. 0000000054660000-00000000ffe63fff: RAM
9364 13:59:47.080540 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9365 13:59:47.083617 7. 0000000100000000-000000023fffffff: RAM
9366 13:59:47.083718 Passing 5 GPIOs to payload:
9367 13:59:47.090501 NAME | PORT | POLARITY | VALUE
9368 13:59:47.093684 EC in RW | 0x000000aa | low | undefined
9369 13:59:47.100505 EC interrupt | 0x00000005 | low | undefined
9370 13:59:47.103582 TPM interrupt | 0x000000ab | high | undefined
9371 13:59:47.106688 SD card detect | 0x00000011 | high | undefined
9372 13:59:47.113700 speaker enable | 0x00000093 | high | undefined
9373 13:59:47.116964 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9374 13:59:47.120408 in-header: 03 f9 00 00 02 00 00 00
9375 13:59:47.120510 in-data: 02 00
9376 13:59:47.123823 ADC[4]: Raw value=904357 ID=7
9377 13:59:47.126581 ADC[3]: Raw value=213441 ID=1
9378 13:59:47.126683 RAM Code: 0x71
9379 13:59:47.130028 ADC[6]: Raw value=75332 ID=0
9380 13:59:47.133250 ADC[5]: Raw value=213072 ID=1
9381 13:59:47.133351 SKU Code: 0x1
9382 13:59:47.140279 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum fb11
9383 13:59:47.143846 coreboot table: 964 bytes.
9384 13:59:47.146919 IMD ROOT 0. 0xfffff000 0x00001000
9385 13:59:47.150004 IMD SMALL 1. 0xffffe000 0x00001000
9386 13:59:47.153333 RO MCACHE 2. 0xffffc000 0x00001104
9387 13:59:47.156528 CONSOLE 3. 0xfff7c000 0x00080000
9388 13:59:47.159707 FMAP 4. 0xfff7b000 0x00000452
9389 13:59:47.163344 TIME STAMP 5. 0xfff7a000 0x00000910
9390 13:59:47.166331 VBOOT WORK 6. 0xfff66000 0x00014000
9391 13:59:47.169722 RAMOOPS 7. 0xffe66000 0x00100000
9392 13:59:47.173073 COREBOOT 8. 0xffe64000 0x00002000
9393 13:59:47.173154 IMD small region:
9394 13:59:47.176601 IMD ROOT 0. 0xffffec00 0x00000400
9395 13:59:47.180027 VPD 1. 0xffffeb80 0x0000006c
9396 13:59:47.183100 MMC STATUS 2. 0xffffeb60 0x00000004
9397 13:59:47.189967 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9398 13:59:47.193150 Probing TPM: done!
9399 13:59:47.196463 Connected to device vid:did:rid of 1ae0:0028:00
9400 13:59:47.206689 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9401 13:59:47.209895 Initialized TPM device CR50 revision 0
9402 13:59:47.213749 Checking cr50 for pending updates
9403 13:59:47.217435 Reading cr50 TPM mode
9404 13:59:47.225500 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9405 13:59:47.232186 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9406 13:59:47.272437 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9407 13:59:47.275927 Checking segment from ROM address 0x40100000
9408 13:59:47.278904 Checking segment from ROM address 0x4010001c
9409 13:59:47.285739 Loading segment from ROM address 0x40100000
9410 13:59:47.285844 code (compression=0)
9411 13:59:47.292457 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9412 13:59:47.302417 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9413 13:59:47.302525 it's not compressed!
9414 13:59:47.309277 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9415 13:59:47.312416 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9416 13:59:47.332841 Loading segment from ROM address 0x4010001c
9417 13:59:47.332956 Entry Point 0x80000000
9418 13:59:47.336454 Loaded segments
9419 13:59:47.339446 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9420 13:59:47.345979 Jumping to boot code at 0x80000000(0xffe64000)
9421 13:59:47.352505 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9422 13:59:47.359109 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9423 13:59:47.367244 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9424 13:59:47.371128 Checking segment from ROM address 0x40100000
9425 13:59:47.373855 Checking segment from ROM address 0x4010001c
9426 13:59:47.380620 Loading segment from ROM address 0x40100000
9427 13:59:47.380730 code (compression=1)
9428 13:59:47.387442 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9429 13:59:47.397413 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9430 13:59:47.397536 using LZMA
9431 13:59:47.405492 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9432 13:59:47.412283 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9433 13:59:47.415728 Loading segment from ROM address 0x4010001c
9434 13:59:47.415841 Entry Point 0x54601000
9435 13:59:47.418854 Loaded segments
9436 13:59:47.422487 NOTICE: MT8192 bl31_setup
9437 13:59:47.429481 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9438 13:59:47.432733 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9439 13:59:47.435646 WARNING: region 0:
9440 13:59:47.439437 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 13:59:47.439553 WARNING: region 1:
9442 13:59:47.446037 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9443 13:59:47.449154 WARNING: region 2:
9444 13:59:47.452530 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9445 13:59:47.455786 WARNING: region 3:
9446 13:59:47.459004 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9447 13:59:47.462874 WARNING: region 4:
9448 13:59:47.469104 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9449 13:59:47.469212 WARNING: region 5:
9450 13:59:47.472841 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 13:59:47.476417 WARNING: region 6:
9452 13:59:47.479043 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 13:59:47.479151 WARNING: region 7:
9454 13:59:47.486135 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 13:59:47.493067 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9456 13:59:47.496074 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9457 13:59:47.499190 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9458 13:59:47.505912 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9459 13:59:47.509456 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9460 13:59:47.512868 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9461 13:59:47.519589 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9462 13:59:47.522265 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9463 13:59:47.529372 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9464 13:59:47.532512 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9465 13:59:47.536120 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9466 13:59:47.542391 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9467 13:59:47.546143 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9468 13:59:47.549200 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9469 13:59:47.555705 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9470 13:59:47.558915 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9471 13:59:47.562996 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9472 13:59:47.568980 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9473 13:59:47.572587 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9474 13:59:47.579101 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9475 13:59:47.582415 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9476 13:59:47.585877 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9477 13:59:47.592554 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9478 13:59:47.596164 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9479 13:59:47.602620 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9480 13:59:47.606157 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9481 13:59:47.609561 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9482 13:59:47.616262 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9483 13:59:47.619463 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9484 13:59:47.622929 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9485 13:59:47.629316 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9486 13:59:47.632536 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9487 13:59:47.639426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9488 13:59:47.642423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9489 13:59:47.646225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9490 13:59:47.649450 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9491 13:59:47.652672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9492 13:59:47.659693 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9493 13:59:47.662842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9494 13:59:47.666442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9495 13:59:47.669560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9496 13:59:47.676623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9497 13:59:47.679688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9498 13:59:47.682635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9499 13:59:47.686376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9500 13:59:47.693215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9501 13:59:47.696271 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9502 13:59:47.699385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9503 13:59:47.706066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9504 13:59:47.709402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9505 13:59:47.712694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9506 13:59:47.719378 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9507 13:59:47.722983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9508 13:59:47.729900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9509 13:59:47.733188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9510 13:59:47.739410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9511 13:59:47.743168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9512 13:59:47.746182 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9513 13:59:47.753325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9514 13:59:47.756670 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9515 13:59:47.762816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9516 13:59:47.766230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9517 13:59:47.772830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9518 13:59:47.776080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9519 13:59:47.779708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9520 13:59:47.786863 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9521 13:59:47.789959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9522 13:59:47.796445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9523 13:59:47.799901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9524 13:59:47.806164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9525 13:59:47.809569 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9526 13:59:47.812915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9527 13:59:47.819387 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9528 13:59:47.823345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9529 13:59:47.829711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9530 13:59:47.833235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9531 13:59:47.839878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9532 13:59:47.843506 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9533 13:59:47.846613 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9534 13:59:47.853461 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9535 13:59:47.856437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9536 13:59:47.863266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9537 13:59:47.866699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9538 13:59:47.873182 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9539 13:59:47.876555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9540 13:59:47.879958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9541 13:59:47.886841 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9542 13:59:47.889984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9543 13:59:47.896927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9544 13:59:47.900105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9545 13:59:47.906447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9546 13:59:47.909837 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9547 13:59:47.913517 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9548 13:59:47.919886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9549 13:59:47.923756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9550 13:59:47.930071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9551 13:59:47.933321 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9552 13:59:47.936679 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9553 13:59:47.940174 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9554 13:59:47.946644 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9555 13:59:47.949914 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9556 13:59:47.953519 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9557 13:59:47.960225 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9558 13:59:47.963390 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9559 13:59:47.970409 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9560 13:59:47.973463 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9561 13:59:47.977060 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9562 13:59:47.983622 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9563 13:59:47.986681 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9564 13:59:47.993780 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9565 13:59:47.997112 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9566 13:59:47.999938 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9567 13:59:48.006722 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9568 13:59:48.010726 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9569 13:59:48.016879 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9570 13:59:48.020051 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9571 13:59:48.023398 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9572 13:59:48.027080 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9573 13:59:48.033517 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9574 13:59:48.036774 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9575 13:59:48.040818 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9576 13:59:48.044061 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9577 13:59:48.050200 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9578 13:59:48.053769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9579 13:59:48.057289 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9580 13:59:48.063743 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9581 13:59:48.066828 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9582 13:59:48.070699 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9583 13:59:48.076901 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9584 13:59:48.080661 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9585 13:59:48.087239 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9586 13:59:48.090570 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9587 13:59:48.093627 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9588 13:59:48.100636 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9589 13:59:48.103685 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9590 13:59:48.110738 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9591 13:59:48.114078 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9592 13:59:48.116973 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9593 13:59:48.124228 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9594 13:59:48.127550 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9595 13:59:48.130782 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9596 13:59:48.137172 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9597 13:59:48.140531 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9598 13:59:48.147310 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9599 13:59:48.150556 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9600 13:59:48.154190 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9601 13:59:48.160465 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9602 13:59:48.163662 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9603 13:59:48.167419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9604 13:59:48.174178 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9605 13:59:48.177512 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9606 13:59:48.184094 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9607 13:59:48.187159 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9608 13:59:48.190755 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9609 13:59:48.197646 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9610 13:59:48.200897 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9611 13:59:48.204038 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9612 13:59:48.210840 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9613 13:59:48.213913 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9614 13:59:48.220876 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9615 13:59:48.224467 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9616 13:59:48.227547 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9617 13:59:48.234512 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9618 13:59:48.237732 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9619 13:59:48.244238 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9620 13:59:48.247782 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9621 13:59:48.250745 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9622 13:59:48.257798 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9623 13:59:48.260762 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9624 13:59:48.264526 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9625 13:59:48.270947 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9626 13:59:48.274172 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9627 13:59:48.280978 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9628 13:59:48.284171 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9629 13:59:48.287536 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9630 13:59:48.294040 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9631 13:59:48.297381 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9632 13:59:48.303993 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9633 13:59:48.307208 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9634 13:59:48.310471 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9635 13:59:48.317328 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9636 13:59:48.320572 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9637 13:59:48.327037 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9638 13:59:48.330262 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9639 13:59:48.334002 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9640 13:59:48.340561 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9641 13:59:48.343474 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9642 13:59:48.350301 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9643 13:59:48.353413 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9644 13:59:48.356824 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9645 13:59:48.363343 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9646 13:59:48.366671 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9647 13:59:48.373989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9648 13:59:48.377194 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9649 13:59:48.380428 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9650 13:59:48.386808 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9651 13:59:48.390023 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9652 13:59:48.397006 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9653 13:59:48.400378 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9654 13:59:48.406938 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9655 13:59:48.410109 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9656 13:59:48.413336 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9657 13:59:48.420189 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9658 13:59:48.423496 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9659 13:59:48.430067 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9660 13:59:48.433328 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9661 13:59:48.439770 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9662 13:59:48.442985 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9663 13:59:48.446660 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9664 13:59:48.453001 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9665 13:59:48.456398 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9666 13:59:48.462908 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9667 13:59:48.466650 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9668 13:59:48.469854 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9669 13:59:48.476381 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9670 13:59:48.479774 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9671 13:59:48.486490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9672 13:59:48.489703 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9673 13:59:48.496402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9674 13:59:48.499798 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9675 13:59:48.502885 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9676 13:59:48.509826 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9677 13:59:48.512906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9678 13:59:48.519562 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9679 13:59:48.522676 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9680 13:59:48.525982 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9681 13:59:48.532799 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9682 13:59:48.536174 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9683 13:59:48.542952 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9684 13:59:48.545991 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9685 13:59:48.549198 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9686 13:59:48.552847 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9687 13:59:48.559077 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9688 13:59:48.562650 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9689 13:59:48.566215 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9690 13:59:48.572585 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9691 13:59:48.575682 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9692 13:59:48.579425 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9693 13:59:48.585923 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9694 13:59:48.588920 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9695 13:59:48.592700 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9696 13:59:48.599159 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9697 13:59:48.602720 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9698 13:59:48.605691 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9699 13:59:48.612554 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9700 13:59:48.615938 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9701 13:59:48.622300 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9702 13:59:48.625513 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9703 13:59:48.629314 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9704 13:59:48.635678 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9705 13:59:48.638690 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9706 13:59:48.642179 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9707 13:59:48.649208 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9708 13:59:48.652041 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9709 13:59:48.655443 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9710 13:59:48.662223 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9711 13:59:48.665273 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9712 13:59:48.672100 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9713 13:59:48.675089 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9714 13:59:48.678550 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9715 13:59:48.685255 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9716 13:59:48.688517 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9717 13:59:48.695548 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9718 13:59:48.698740 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9719 13:59:48.701937 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9720 13:59:48.708577 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9721 13:59:48.712030 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9722 13:59:48.714945 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9723 13:59:48.721892 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9724 13:59:48.725421 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9725 13:59:48.728655 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9726 13:59:48.732069 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9727 13:59:48.735179 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9728 13:59:48.741943 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9729 13:59:48.744957 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9730 13:59:48.748849 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9731 13:59:48.751828 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9732 13:59:48.758655 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9733 13:59:48.761987 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9734 13:59:48.764834 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9735 13:59:48.771409 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9736 13:59:48.775076 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9737 13:59:48.778372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9738 13:59:48.785148 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9739 13:59:48.788125 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9740 13:59:48.791443 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9741 13:59:48.798286 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9742 13:59:48.801604 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9743 13:59:48.808013 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9744 13:59:48.811307 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9745 13:59:48.814682 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9746 13:59:48.821571 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9747 13:59:48.824868 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9748 13:59:48.831370 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9749 13:59:48.834838 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9750 13:59:48.841321 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9751 13:59:48.844457 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9752 13:59:48.848229 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9753 13:59:48.854967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9754 13:59:48.857919 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9755 13:59:48.864440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9756 13:59:48.867643 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9757 13:59:48.871344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9758 13:59:48.877959 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9759 13:59:48.881265 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9760 13:59:48.888124 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9761 13:59:48.891383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9762 13:59:48.894416 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9763 13:59:48.901426 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9764 13:59:48.904465 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9765 13:59:48.911508 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9766 13:59:48.914786 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9767 13:59:48.921165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9768 13:59:48.924507 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9769 13:59:48.928207 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9770 13:59:48.934673 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9771 13:59:48.937669 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9772 13:59:48.944260 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9773 13:59:48.948036 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9774 13:59:48.951148 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9775 13:59:48.957738 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9776 13:59:48.961658 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9777 13:59:48.967661 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9778 13:59:48.971026 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9779 13:59:48.974378 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9780 13:59:48.981004 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9781 13:59:48.984185 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9782 13:59:48.991298 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9783 13:59:48.994260 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9784 13:59:48.997450 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9785 13:59:49.004063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9786 13:59:49.007906 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9787 13:59:49.014333 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9788 13:59:49.017834 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9789 13:59:49.020724 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9790 13:59:49.027615 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9791 13:59:49.030843 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9792 13:59:49.037948 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9793 13:59:49.041133 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9794 13:59:49.044176 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9795 13:59:49.051280 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9796 13:59:49.054554 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9797 13:59:49.060808 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9798 13:59:49.063800 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9799 13:59:49.070806 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9800 13:59:49.074063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9801 13:59:49.077521 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9802 13:59:49.083882 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9803 13:59:49.087681 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9804 13:59:49.094275 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9805 13:59:49.097167 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9806 13:59:49.100612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9807 13:59:49.107523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9808 13:59:49.110248 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9809 13:59:49.116943 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9810 13:59:49.120525 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9811 13:59:49.123759 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9812 13:59:49.130599 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9813 13:59:49.133742 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9814 13:59:49.140972 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9815 13:59:49.144228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9816 13:59:49.150542 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9817 13:59:49.153678 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9818 13:59:49.157447 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9819 13:59:49.163938 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9820 13:59:49.167243 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9821 13:59:49.174310 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9822 13:59:49.177391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9823 13:59:49.183558 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9824 13:59:49.187312 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9825 13:59:49.190165 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9826 13:59:49.196975 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9827 13:59:49.200467 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9828 13:59:49.206931 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9829 13:59:49.210074 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9830 13:59:49.217019 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9831 13:59:49.220054 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9832 13:59:49.223615 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9833 13:59:49.229951 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9834 13:59:49.233347 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9835 13:59:49.239922 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9836 13:59:49.243354 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9837 13:59:49.249978 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9838 13:59:49.253722 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9839 13:59:49.259772 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9840 13:59:49.263426 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9841 13:59:49.266561 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9842 13:59:49.273353 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9843 13:59:49.276658 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9844 13:59:49.283365 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9845 13:59:49.286656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9846 13:59:49.293908 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9847 13:59:49.296877 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9848 13:59:49.300020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9849 13:59:49.306934 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9850 13:59:49.309843 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9851 13:59:49.316837 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9852 13:59:49.320031 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9853 13:59:49.326780 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9854 13:59:49.329682 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9855 13:59:49.336151 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9856 13:59:49.339897 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9857 13:59:49.342938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9858 13:59:49.349924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9859 13:59:49.353124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9860 13:59:49.359487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9861 13:59:49.363499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9862 13:59:49.369604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9863 13:59:49.372952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9864 13:59:49.376057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9865 13:59:49.383180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9866 13:59:49.386274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9867 13:59:49.393328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9868 13:59:49.396498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9869 13:59:49.402796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9870 13:59:49.406314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9871 13:59:49.413032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9872 13:59:49.415972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9873 13:59:49.422652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9874 13:59:49.426066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9875 13:59:49.433244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9876 13:59:49.436245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9877 13:59:49.443111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9878 13:59:49.446384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9879 13:59:49.452625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9880 13:59:49.456183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9881 13:59:49.462715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9882 13:59:49.465963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9883 13:59:49.472587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9884 13:59:49.476274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9885 13:59:49.482807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9886 13:59:49.486119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9887 13:59:49.492252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9888 13:59:49.496175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9889 13:59:49.499384 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9890 13:59:49.502448 INFO: [APUAPC] vio 0
9891 13:59:49.509143 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9892 13:59:49.512682 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9893 13:59:49.515718 INFO: [APUAPC] D0_APC_0: 0x400510
9894 13:59:49.519605 INFO: [APUAPC] D0_APC_1: 0x0
9895 13:59:49.522681 INFO: [APUAPC] D0_APC_2: 0x1540
9896 13:59:49.525675 INFO: [APUAPC] D0_APC_3: 0x0
9897 13:59:49.529345 INFO: [APUAPC] D1_APC_0: 0xffffffff
9898 13:59:49.532502 INFO: [APUAPC] D1_APC_1: 0xffffffff
9899 13:59:49.535560 INFO: [APUAPC] D1_APC_2: 0x3fffff
9900 13:59:49.539080 INFO: [APUAPC] D1_APC_3: 0x0
9901 13:59:49.542225 INFO: [APUAPC] D2_APC_0: 0xffffffff
9902 13:59:49.545590 INFO: [APUAPC] D2_APC_1: 0xffffffff
9903 13:59:49.549180 INFO: [APUAPC] D2_APC_2: 0x3fffff
9904 13:59:49.552316 INFO: [APUAPC] D2_APC_3: 0x0
9905 13:59:49.555461 INFO: [APUAPC] D3_APC_0: 0xffffffff
9906 13:59:49.559160 INFO: [APUAPC] D3_APC_1: 0xffffffff
9907 13:59:49.562278 INFO: [APUAPC] D3_APC_2: 0x3fffff
9908 13:59:49.565498 INFO: [APUAPC] D3_APC_3: 0x0
9909 13:59:49.568501 INFO: [APUAPC] D4_APC_0: 0xffffffff
9910 13:59:49.571789 INFO: [APUAPC] D4_APC_1: 0xffffffff
9911 13:59:49.575365 INFO: [APUAPC] D4_APC_2: 0x3fffff
9912 13:59:49.575447 INFO: [APUAPC] D4_APC_3: 0x0
9913 13:59:49.578447 INFO: [APUAPC] D5_APC_0: 0xffffffff
9914 13:59:49.585690 INFO: [APUAPC] D5_APC_1: 0xffffffff
9915 13:59:49.588698 INFO: [APUAPC] D5_APC_2: 0x3fffff
9916 13:59:49.588780 INFO: [APUAPC] D5_APC_3: 0x0
9917 13:59:49.592006 INFO: [APUAPC] D6_APC_0: 0xffffffff
9918 13:59:49.595048 INFO: [APUAPC] D6_APC_1: 0xffffffff
9919 13:59:49.598914 INFO: [APUAPC] D6_APC_2: 0x3fffff
9920 13:59:49.601982 INFO: [APUAPC] D6_APC_3: 0x0
9921 13:59:49.604897 INFO: [APUAPC] D7_APC_0: 0xffffffff
9922 13:59:49.608827 INFO: [APUAPC] D7_APC_1: 0xffffffff
9923 13:59:49.612194 INFO: [APUAPC] D7_APC_2: 0x3fffff
9924 13:59:49.615264 INFO: [APUAPC] D7_APC_3: 0x0
9925 13:59:49.618742 INFO: [APUAPC] D8_APC_0: 0xffffffff
9926 13:59:49.621632 INFO: [APUAPC] D8_APC_1: 0xffffffff
9927 13:59:49.625135 INFO: [APUAPC] D8_APC_2: 0x3fffff
9928 13:59:49.628153 INFO: [APUAPC] D8_APC_3: 0x0
9929 13:59:49.631708 INFO: [APUAPC] D9_APC_0: 0xffffffff
9930 13:59:49.635148 INFO: [APUAPC] D9_APC_1: 0xffffffff
9931 13:59:49.638712 INFO: [APUAPC] D9_APC_2: 0x3fffff
9932 13:59:49.641592 INFO: [APUAPC] D9_APC_3: 0x0
9933 13:59:49.644912 INFO: [APUAPC] D10_APC_0: 0xffffffff
9934 13:59:49.648021 INFO: [APUAPC] D10_APC_1: 0xffffffff
9935 13:59:49.651477 INFO: [APUAPC] D10_APC_2: 0x3fffff
9936 13:59:49.654968 INFO: [APUAPC] D10_APC_3: 0x0
9937 13:59:49.657971 INFO: [APUAPC] D11_APC_0: 0xffffffff
9938 13:59:49.661783 INFO: [APUAPC] D11_APC_1: 0xffffffff
9939 13:59:49.665049 INFO: [APUAPC] D11_APC_2: 0x3fffff
9940 13:59:49.668184 INFO: [APUAPC] D11_APC_3: 0x0
9941 13:59:49.671422 INFO: [APUAPC] D12_APC_0: 0xffffffff
9942 13:59:49.674670 INFO: [APUAPC] D12_APC_1: 0xffffffff
9943 13:59:49.678293 INFO: [APUAPC] D12_APC_2: 0x3fffff
9944 13:59:49.681704 INFO: [APUAPC] D12_APC_3: 0x0
9945 13:59:49.684580 INFO: [APUAPC] D13_APC_0: 0xffffffff
9946 13:59:49.688130 INFO: [APUAPC] D13_APC_1: 0xffffffff
9947 13:59:49.691292 INFO: [APUAPC] D13_APC_2: 0x3fffff
9948 13:59:49.694931 INFO: [APUAPC] D13_APC_3: 0x0
9949 13:59:49.698039 INFO: [APUAPC] D14_APC_0: 0xffffffff
9950 13:59:49.701527 INFO: [APUAPC] D14_APC_1: 0xffffffff
9951 13:59:49.705117 INFO: [APUAPC] D14_APC_2: 0x3fffff
9952 13:59:49.707939 INFO: [APUAPC] D14_APC_3: 0x0
9953 13:59:49.711763 INFO: [APUAPC] D15_APC_0: 0xffffffff
9954 13:59:49.714800 INFO: [APUAPC] D15_APC_1: 0xffffffff
9955 13:59:49.718059 INFO: [APUAPC] D15_APC_2: 0x3fffff
9956 13:59:49.721863 INFO: [APUAPC] D15_APC_3: 0x0
9957 13:59:49.724969 INFO: [APUAPC] APC_CON: 0x4
9958 13:59:49.728036 INFO: [NOCDAPC] D0_APC_0: 0x0
9959 13:59:49.731467 INFO: [NOCDAPC] D0_APC_1: 0x0
9960 13:59:49.734413 INFO: [NOCDAPC] D1_APC_0: 0x0
9961 13:59:49.737666 INFO: [NOCDAPC] D1_APC_1: 0xfff
9962 13:59:49.741154 INFO: [NOCDAPC] D2_APC_0: 0x0
9963 13:59:49.741236 INFO: [NOCDAPC] D2_APC_1: 0xfff
9964 13:59:49.744616 INFO: [NOCDAPC] D3_APC_0: 0x0
9965 13:59:49.748187 INFO: [NOCDAPC] D3_APC_1: 0xfff
9966 13:59:49.751148 INFO: [NOCDAPC] D4_APC_0: 0x0
9967 13:59:49.754967 INFO: [NOCDAPC] D4_APC_1: 0xfff
9968 13:59:49.758162 INFO: [NOCDAPC] D5_APC_0: 0x0
9969 13:59:49.761519 INFO: [NOCDAPC] D5_APC_1: 0xfff
9970 13:59:49.764247 INFO: [NOCDAPC] D6_APC_0: 0x0
9971 13:59:49.768083 INFO: [NOCDAPC] D6_APC_1: 0xfff
9972 13:59:49.771354 INFO: [NOCDAPC] D7_APC_0: 0x0
9973 13:59:49.771436 INFO: [NOCDAPC] D7_APC_1: 0xfff
9974 13:59:49.774657 INFO: [NOCDAPC] D8_APC_0: 0x0
9975 13:59:49.777878 INFO: [NOCDAPC] D8_APC_1: 0xfff
9976 13:59:49.781037 INFO: [NOCDAPC] D9_APC_0: 0x0
9977 13:59:49.784408 INFO: [NOCDAPC] D9_APC_1: 0xfff
9978 13:59:49.787598 INFO: [NOCDAPC] D10_APC_0: 0x0
9979 13:59:49.791192 INFO: [NOCDAPC] D10_APC_1: 0xfff
9980 13:59:49.794199 INFO: [NOCDAPC] D11_APC_0: 0x0
9981 13:59:49.797514 INFO: [NOCDAPC] D11_APC_1: 0xfff
9982 13:59:49.801041 INFO: [NOCDAPC] D12_APC_0: 0x0
9983 13:59:49.804032 INFO: [NOCDAPC] D12_APC_1: 0xfff
9984 13:59:49.807267 INFO: [NOCDAPC] D13_APC_0: 0x0
9985 13:59:49.810565 INFO: [NOCDAPC] D13_APC_1: 0xfff
9986 13:59:49.813654 INFO: [NOCDAPC] D14_APC_0: 0x0
9987 13:59:49.817792 INFO: [NOCDAPC] D14_APC_1: 0xfff
9988 13:59:49.817874 INFO: [NOCDAPC] D15_APC_0: 0x0
9989 13:59:49.820403 INFO: [NOCDAPC] D15_APC_1: 0xfff
9990 13:59:49.823789 INFO: [NOCDAPC] APC_CON: 0x4
9991 13:59:49.827419 INFO: [APUAPC] set_apusys_apc done
9992 13:59:49.830850 INFO: [DEVAPC] devapc_init done
9993 13:59:49.837165 INFO: GICv3 without legacy support detected.
9994 13:59:49.840956 INFO: ARM GICv3 driver initialized in EL3
9995 13:59:49.844050 INFO: Maximum SPI INTID supported: 639
9996 13:59:49.847337 INFO: BL31: Initializing runtime services
9997 13:59:49.853674 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9998 13:59:49.857001 INFO: SPM: enable CPC mode
9999 13:59:49.860614 INFO: mcdi ready for mcusys-off-idle and system suspend
10000 13:59:49.867060 INFO: BL31: Preparing for EL3 exit to normal world
10001 13:59:49.870478 INFO: Entry point address = 0x80000000
10002 13:59:49.870583 INFO: SPSR = 0x8
10003 13:59:49.876773
10004 13:59:49.876859
10005 13:59:49.876924
10006 13:59:49.880086 Starting depthcharge on Spherion...
10007 13:59:49.880193
10008 13:59:49.880290 Wipe memory regions:
10009 13:59:49.880394
10010 13:59:49.881022 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10011 13:59:49.881123 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10012 13:59:49.881207 Setting prompt string to ['asurada:']
10013 13:59:49.881289 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10014 13:59:49.883903 [0x00000040000000, 0x00000054600000)
10015 13:59:50.005937
10016 13:59:50.006077 [0x00000054660000, 0x00000080000000)
10017 13:59:50.266737
10018 13:59:50.266886 [0x000000821a7280, 0x000000ffe64000)
10019 13:59:51.011567
10020 13:59:51.011702 [0x00000100000000, 0x00000240000000)
10021 13:59:52.900557
10022 13:59:52.904239 Initializing XHCI USB controller at 0x11200000.
10023 13:59:53.941796
10024 13:59:53.945065 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10025 13:59:53.945216
10026 13:59:53.945320
10027 13:59:53.945420
10028 13:59:53.945757 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 13:59:54.046201 asurada: tftpboot 192.168.201.1 12682961/tftp-deploy-w8a_okmr/kernel/image.itb 12682961/tftp-deploy-w8a_okmr/kernel/cmdline
10031 13:59:54.046368 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 13:59:54.046490 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10033 13:59:54.050677 tftpboot 192.168.201.1 12682961/tftp-deploy-w8a_okmr/kernel/image.itp-deploy-w8a_okmr/kernel/cmdline
10034 13:59:54.050803
10035 13:59:54.050901 Waiting for link
10036 13:59:54.211010
10037 13:59:54.211197 R8152: Initializing
10038 13:59:54.211306
10039 13:59:54.214880 Version 9 (ocp_data = 6010)
10040 13:59:54.215013
10041 13:59:54.218021 R8152: Done initializing
10042 13:59:54.218146
10043 13:59:54.218247 Adding net device
10044 13:59:56.090144
10045 13:59:56.090304 done.
10046 13:59:56.090415
10047 13:59:56.090523 MAC: 00:e0:4c:78:7a:aa
10048 13:59:56.090618
10049 13:59:56.093022 Sending DHCP discover... done.
10050 13:59:56.093107
10051 13:59:56.096366 Waiting for reply... done.
10052 13:59:56.096482
10053 13:59:56.100080 Sending DHCP request... done.
10054 13:59:56.100175
10055 13:59:56.103629 Waiting for reply... done.
10056 13:59:56.103729
10057 13:59:56.103828 My ip is 192.168.201.12
10058 13:59:56.103932
10059 13:59:56.106971 The DHCP server ip is 192.168.201.1
10060 13:59:56.107081
10061 13:59:56.113392 TFTP server IP predefined by user: 192.168.201.1
10062 13:59:56.113526
10063 13:59:56.120026 Bootfile predefined by user: 12682961/tftp-deploy-w8a_okmr/kernel/image.itb
10064 13:59:56.120153
10065 13:59:56.123287 Sending tftp read request... done.
10066 13:59:56.123457
10067 13:59:56.126989 Waiting for the transfer...
10068 13:59:56.127122
10069 13:59:56.420014 00000000 ################################################################
10070 13:59:56.420175
10071 13:59:56.713782 00080000 ################################################################
10072 13:59:56.713983
10073 13:59:56.988149 00100000 ################################################################
10074 13:59:56.988368
10075 13:59:57.265683 00180000 ################################################################
10076 13:59:57.265830
10077 13:59:57.547248 00200000 ################################################################
10078 13:59:57.547448
10079 13:59:57.815932 00280000 ################################################################
10080 13:59:57.816124
10081 13:59:58.085722 00300000 ################################################################
10082 13:59:58.085914
10083 13:59:58.356738 00380000 ################################################################
10084 13:59:58.356991
10085 13:59:58.631022 00400000 ################################################################
10086 13:59:58.631195
10087 13:59:58.907127 00480000 ################################################################
10088 13:59:58.907303
10089 13:59:59.189076 00500000 ################################################################
10090 13:59:59.189263
10091 13:59:59.478451 00580000 ################################################################
10092 13:59:59.478593
10093 13:59:59.765441 00600000 ################################################################
10094 13:59:59.765597
10095 14:00:00.058206 00680000 ################################################################
10096 14:00:00.058396
10097 14:00:00.355722 00700000 ################################################################
10098 14:00:00.355898
10099 14:00:00.705047 00780000 ################################################################
10100 14:00:00.705287
10101 14:00:01.055422 00800000 ################################################################
10102 14:00:01.055625
10103 14:00:01.404170 00880000 ################################################################
10104 14:00:01.404348
10105 14:00:01.746426 00900000 ################################################################
10106 14:00:01.746602
10107 14:00:02.056260 00980000 ################################################################
10108 14:00:02.056444
10109 14:00:02.361513 00a00000 ################################################################
10110 14:00:02.361703
10111 14:00:02.674500 00a80000 ################################################################
10112 14:00:02.674706
10113 14:00:02.988090 00b00000 ################################################################
10114 14:00:02.988317
10115 14:00:03.308445 00b80000 ################################################################
10116 14:00:03.308685
10117 14:00:03.656989 00c00000 ################################################################
10118 14:00:03.657205
10119 14:00:03.979343 00c80000 ################################################################
10120 14:00:03.979576
10121 14:00:04.314842 00d00000 ################################################################
10122 14:00:04.315032
10123 14:00:04.578586 00d80000 ################################################################
10124 14:00:04.578797
10125 14:00:04.839508 00e00000 ################################################################
10126 14:00:04.839713
10127 14:00:05.090563 00e80000 ################################################################
10128 14:00:05.090717
10129 14:00:05.347089 00f00000 ################################################################
10130 14:00:05.347283
10131 14:00:05.615228 00f80000 ################################################################
10132 14:00:05.615366
10133 14:00:05.898193 01000000 ################################################################
10134 14:00:05.898377
10135 14:00:06.188550 01080000 ################################################################
10136 14:00:06.188696
10137 14:00:06.491352 01100000 ################################################################
10138 14:00:06.491533
10139 14:00:06.768668 01180000 ################################################################
10140 14:00:06.768815
10141 14:00:07.046328 01200000 ################################################################
10142 14:00:07.046538
10143 14:00:07.325009 01280000 ################################################################
10144 14:00:07.325198
10145 14:00:07.606262 01300000 ################################################################
10146 14:00:07.606439
10147 14:00:07.893856 01380000 ################################################################
10148 14:00:07.894056
10149 14:00:08.177077 01400000 ################################################################
10150 14:00:08.177233
10151 14:00:08.452229 01480000 ################################################################
10152 14:00:08.452409
10153 14:00:08.729657 01500000 ################################################################
10154 14:00:08.729835
10155 14:00:09.004655 01580000 ################################################################
10156 14:00:09.004807
10157 14:00:09.286586 01600000 ################################################################
10158 14:00:09.286754
10159 14:00:09.540745 01680000 ################################################################
10160 14:00:09.540923
10161 14:00:09.794530 01700000 ################################################################
10162 14:00:09.794710
10163 14:00:10.038860 01780000 ################################################################
10164 14:00:10.039040
10165 14:00:10.298949 01800000 ################################################################
10166 14:00:10.299112
10167 14:00:10.552640 01880000 ################################################################
10168 14:00:10.552827
10169 14:00:10.813216 01900000 ################################################################
10170 14:00:10.813419
10171 14:00:11.071054 01980000 ################################################################
10172 14:00:11.071241
10173 14:00:11.332369 01a00000 ################################################################
10174 14:00:11.332569
10175 14:00:11.593984 01a80000 ################################################################
10176 14:00:11.594165
10177 14:00:11.847271 01b00000 ################################################################
10178 14:00:11.847465
10179 14:00:12.100445 01b80000 ################################################################
10180 14:00:12.100636
10181 14:00:12.354899 01c00000 ################################################################
10182 14:00:12.355092
10183 14:00:12.607302 01c80000 ################################################################
10184 14:00:12.607562
10185 14:00:12.864504 01d00000 ################################################################
10186 14:00:12.864716
10187 14:00:13.120639 01d80000 ################################################################
10188 14:00:13.120839
10189 14:00:13.376521 01e00000 ################################################################
10190 14:00:13.376708
10191 14:00:13.631706 01e80000 ################################################################
10192 14:00:13.631908
10193 14:00:13.887796 01f00000 ################################################################
10194 14:00:13.887985
10195 14:00:14.143118 01f80000 ################################################################
10196 14:00:14.143307
10197 14:00:14.398753 02000000 ################################################################
10198 14:00:14.398948
10199 14:00:14.648628 02080000 ################################################################
10200 14:00:14.648818
10201 14:00:14.902415 02100000 ################################################################
10202 14:00:14.902602
10203 14:00:15.156701 02180000 ################################################################
10204 14:00:15.156888
10205 14:00:15.411538 02200000 ################################################################
10206 14:00:15.411726
10207 14:00:15.665272 02280000 ################################################################
10208 14:00:15.665459
10209 14:00:15.919627 02300000 ################################################################
10210 14:00:15.919805
10211 14:00:16.173944 02380000 ################################################################
10212 14:00:16.174113
10213 14:00:16.428231 02400000 ################################################################
10214 14:00:16.428412
10215 14:00:16.681684 02480000 ################################################################
10216 14:00:16.681851
10217 14:00:16.936313 02500000 ################################################################
10218 14:00:16.936498
10219 14:00:17.190925 02580000 ################################################################
10220 14:00:17.191097
10221 14:00:17.443876 02600000 ################################################################
10222 14:00:17.444056
10223 14:00:17.696441 02680000 ################################################################
10224 14:00:17.696584
10225 14:00:17.950011 02700000 ################################################################
10226 14:00:17.950175
10227 14:00:18.210952 02780000 ################################################################
10228 14:00:18.211124
10229 14:00:18.468142 02800000 ################################################################
10230 14:00:18.468324
10231 14:00:18.722074 02880000 ################################################################
10232 14:00:18.722248
10233 14:00:18.978705 02900000 ################################################################
10234 14:00:18.978886
10235 14:00:19.234502 02980000 ################################################################
10236 14:00:19.234732
10237 14:00:19.494478 02a00000 ################################################################
10238 14:00:19.494645
10239 14:00:19.756910 02a80000 ################################################################
10240 14:00:19.757084
10241 14:00:20.011238 02b00000 ################################################################
10242 14:00:20.011412
10243 14:00:20.273123 02b80000 ################################################################
10244 14:00:20.273287
10245 14:00:20.535786 02c00000 ################################################################
10246 14:00:20.535921
10247 14:00:20.807255 02c80000 ################################################################
10248 14:00:20.807408
10249 14:00:21.072845 02d00000 ################################################################
10250 14:00:21.073009
10251 14:00:21.338839 02d80000 ################################################################
10252 14:00:21.338978
10253 14:00:21.596936 02e00000 ################################################################
10254 14:00:21.597074
10255 14:00:21.847932 02e80000 ################################################################
10256 14:00:21.848098
10257 14:00:22.110079 02f00000 ################################################################
10258 14:00:22.110260
10259 14:00:22.360681 02f80000 ################################################################
10260 14:00:22.360815
10261 14:00:22.615363 03000000 ################################################################
10262 14:00:22.615515
10263 14:00:22.867755 03080000 ################################################################
10264 14:00:22.867911
10265 14:00:23.132251 03100000 ################################################################
10266 14:00:23.132429
10267 14:00:23.394754 03180000 ################################################################
10268 14:00:23.394907
10269 14:00:23.638839 03200000 ################################################################
10270 14:00:23.638999
10271 14:00:23.902638 03280000 ################################################################
10272 14:00:23.902786
10273 14:00:24.169855 03300000 ################################################################
10274 14:00:24.170050
10275 14:00:24.430374 03380000 ################################################################
10276 14:00:24.430518
10277 14:00:24.681771 03400000 ################################################################
10278 14:00:24.681924
10279 14:00:24.927845 03480000 ################################################################
10280 14:00:24.927996
10281 14:00:25.184296 03500000 ################################################################
10282 14:00:25.184467
10283 14:00:25.437762 03580000 ################################################################
10284 14:00:25.437954
10285 14:00:25.684120 03600000 ################################################################
10286 14:00:25.684270
10287 14:00:25.927906 03680000 ################################################################
10288 14:00:25.928056
10289 14:00:26.178055 03700000 ################################################################
10290 14:00:26.178192
10291 14:00:26.427858 03780000 ################################################################
10292 14:00:26.428030
10293 14:00:26.678165 03800000 ################################################################
10294 14:00:26.678326
10295 14:00:26.929088 03880000 ################################################################
10296 14:00:26.929242
10297 14:00:27.177813 03900000 ################################################################
10298 14:00:27.177962
10299 14:00:27.425403 03980000 ################################################################
10300 14:00:27.425574
10301 14:00:27.671936 03a00000 ################################################################
10302 14:00:27.672105
10303 14:00:27.917889 03a80000 ################################################################
10304 14:00:27.918064
10305 14:00:28.170824 03b00000 ################################################################
10306 14:00:28.170963
10307 14:00:28.417476 03b80000 ################################################################
10308 14:00:28.417625
10309 14:00:28.664040 03c00000 ################################################################
10310 14:00:28.664176
10311 14:00:28.916231 03c80000 ################################################################
10312 14:00:28.916391
10313 14:00:29.162875 03d00000 ################################################################
10314 14:00:29.163060
10315 14:00:29.411833 03d80000 ################################################################
10316 14:00:29.411995
10317 14:00:29.667757 03e00000 ################################################################
10318 14:00:29.667891
10319 14:00:29.920009 03e80000 ################################################################
10320 14:00:29.920191
10321 14:00:30.170072 03f00000 ################################################################
10322 14:00:30.170254
10323 14:00:30.426809 03f80000 ################################################################
10324 14:00:30.426951
10325 14:00:30.682366 04000000 ################################################################
10326 14:00:30.682495
10327 14:00:30.944703 04080000 ################################################################
10328 14:00:30.944877
10329 14:00:31.207259 04100000 ################################################################
10330 14:00:31.207391
10331 14:00:31.463996 04180000 ################################################################
10332 14:00:31.464132
10333 14:00:31.714708 04200000 ################################################################
10334 14:00:31.714878
10335 14:00:31.974595 04280000 ################################################################
10336 14:00:31.974765
10337 14:00:32.223885 04300000 ################################################################
10338 14:00:32.224046
10339 14:00:32.471110 04380000 ################################################################
10340 14:00:32.471243
10341 14:00:32.726165 04400000 ################################################################
10342 14:00:32.726323
10343 14:00:32.980296 04480000 ################################################################
10344 14:00:32.980430
10345 14:00:33.231024 04500000 ################################################################
10346 14:00:33.231195
10347 14:00:33.477679 04580000 ################################################################
10348 14:00:33.477841
10349 14:00:33.724812 04600000 ################################################################
10350 14:00:33.724949
10351 14:00:33.972681 04680000 ################################################################
10352 14:00:33.972818
10353 14:00:34.227595 04700000 ################################################################
10354 14:00:34.227730
10355 14:00:34.484927 04780000 ################################################################
10356 14:00:34.485103
10357 14:00:34.734246 04800000 ################################################################
10358 14:00:34.734422
10359 14:00:34.988990 04880000 ################################################################
10360 14:00:34.989137
10361 14:00:35.239392 04900000 ################################################################
10362 14:00:35.239553
10363 14:00:35.484258 04980000 ################################################################
10364 14:00:35.484427
10365 14:00:35.731491 04a00000 ################################################################
10366 14:00:35.731664
10367 14:00:35.973948 04a80000 ################################################################
10368 14:00:35.974117
10369 14:00:36.224659 04b00000 ################################################################
10370 14:00:36.224792
10371 14:00:36.473299 04b80000 ################################################################
10372 14:00:36.473471
10373 14:00:36.722600 04c00000 ################################################################
10374 14:00:36.722772
10375 14:00:36.971309 04c80000 ################################################################
10376 14:00:36.971528
10377 14:00:37.230874 04d00000 ################################################################
10378 14:00:37.231036
10379 14:00:37.487579 04d80000 ################################################################
10380 14:00:37.487747
10381 14:00:37.742051 04e00000 ################################################################
10382 14:00:37.742190
10383 14:00:38.004415 04e80000 ################################################################
10384 14:00:38.004547
10385 14:00:38.261865 04f00000 ################################################################
10386 14:00:38.262016
10387 14:00:38.524750 04f80000 ################################################################
10388 14:00:38.524919
10389 14:00:38.809756 05000000 ################################################################
10390 14:00:38.809905
10391 14:00:39.084276 05080000 ################################################################
10392 14:00:39.084449
10393 14:00:39.359360 05100000 ################################################################
10394 14:00:39.359525
10395 14:00:39.632863 05180000 ################################################################
10396 14:00:39.633018
10397 14:00:39.904987 05200000 ################################################################
10398 14:00:39.905124
10399 14:00:40.178918 05280000 ################################################################
10400 14:00:40.179076
10401 14:00:40.448713 05300000 ################################################################
10402 14:00:40.448873
10403 14:00:40.720511 05380000 ################################################################
10404 14:00:40.720652
10405 14:00:40.990593 05400000 ################################################################
10406 14:00:40.990777
10407 14:00:41.258722 05480000 ################################################################
10408 14:00:41.258898
10409 14:00:41.530261 05500000 ################################################################
10410 14:00:41.530394
10411 14:00:41.792186 05580000 ################################################################
10412 14:00:41.792370
10413 14:00:42.045513 05600000 ################################################################
10414 14:00:42.045698
10415 14:00:42.299787 05680000 ################################################################
10416 14:00:42.299965
10417 14:00:42.554453 05700000 ################################################################
10418 14:00:42.554590
10419 14:00:42.808111 05780000 ################################################################
10420 14:00:42.808274
10421 14:00:43.056703 05800000 ################################################################
10422 14:00:43.056834
10423 14:00:43.306621 05880000 ################################################################
10424 14:00:43.306783
10425 14:00:43.558014 05900000 ################################################################
10426 14:00:43.558176
10427 14:00:43.809430 05980000 ################################################################
10428 14:00:43.809588
10429 14:00:44.064020 05a00000 ################################################################
10430 14:00:44.064196
10431 14:00:44.318581 05a80000 ################################################################
10432 14:00:44.318751
10433 14:00:44.576172 05b00000 ################################################################
10434 14:00:44.576351
10435 14:00:44.832716 05b80000 ################################################################
10436 14:00:44.832895
10437 14:00:45.090525 05c00000 ################################################################
10438 14:00:45.090758
10439 14:00:45.348377 05c80000 ################################################################
10440 14:00:45.348535
10441 14:00:45.604414 05d00000 ################################################################
10442 14:00:45.604555
10443 14:00:45.859746 05d80000 ################################################################
10444 14:00:45.859913
10445 14:00:46.116425 05e00000 ################################################################
10446 14:00:46.116606
10447 14:00:46.372483 05e80000 ################################################################
10448 14:00:46.372640
10449 14:00:46.627183 05f00000 ################################################################
10450 14:00:46.627387
10451 14:00:46.882685 05f80000 ################################################################
10452 14:00:46.882869
10453 14:00:47.138664 06000000 ################################################################
10454 14:00:47.138823
10455 14:00:47.394911 06080000 ################################################################
10456 14:00:47.395083
10457 14:00:47.649105 06100000 ################################################################
10458 14:00:47.649268
10459 14:00:47.904194 06180000 ################################################################
10460 14:00:47.904357
10461 14:00:48.161709 06200000 ################################################################
10462 14:00:48.161869
10463 14:00:48.419530 06280000 ################################################################
10464 14:00:48.419703
10465 14:00:48.677003 06300000 ################################################################
10466 14:00:48.677143
10467 14:00:48.932988 06380000 ################################################################
10468 14:00:48.933162
10469 14:00:49.188426 06400000 ################################################################
10470 14:00:49.188599
10471 14:00:49.442040 06480000 ################################################################
10472 14:00:49.442226
10473 14:00:49.698590 06500000 ################################################################
10474 14:00:49.698723
10475 14:00:49.956954 06580000 ################################################################
10476 14:00:49.957132
10477 14:00:50.213517 06600000 ################################################################
10478 14:00:50.213685
10479 14:00:50.469869 06680000 ################################################################
10480 14:00:50.470092
10481 14:00:50.727919 06700000 ################################################################
10482 14:00:50.728093
10483 14:00:50.985251 06780000 ################################################################
10484 14:00:50.985450
10485 14:00:51.242247 06800000 ################################################################
10486 14:00:51.242391
10487 14:00:51.501253 06880000 ################################################################
10488 14:00:51.501429
10489 14:00:51.671499 06900000 ########################################### done.
10490 14:00:51.671661
10491 14:00:51.674989 The bootfile was 110449322 bytes long.
10492 14:00:51.675072
10493 14:00:51.678496 Sending tftp read request... done.
10494 14:00:51.678581
10495 14:00:51.681278 Waiting for the transfer...
10496 14:00:51.681363
10497 14:00:51.684626 00000000 # done.
10498 14:00:51.684781
10499 14:00:51.691320 Command line loaded dynamically from TFTP file: 12682961/tftp-deploy-w8a_okmr/kernel/cmdline
10500 14:00:51.691438
10501 14:00:51.704786 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10502 14:00:51.704914
10503 14:00:51.704998 Loading FIT.
10504 14:00:51.707662
10505 14:00:51.707738 Image ramdisk-1 has 98353149 bytes.
10506 14:00:51.711082
10507 14:00:51.711172 Image fdt-1 has 47278 bytes.
10508 14:00:51.711252
10509 14:00:51.714620 Image kernel-1 has 12046857 bytes.
10510 14:00:51.714708
10511 14:00:51.724546 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10512 14:00:51.724687
10513 14:00:51.741064 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10514 14:00:51.741228
10515 14:00:51.747283 Choosing best match conf-1 for compat google,spherion-rev2.
10516 14:00:51.750805
10517 14:00:51.827221 Connected to device vid:did:rid of 1ae0:0028:00
10518 14:00:51.837580
10519 14:00:51.841156 tpm_get_response: command 0x17b, return code 0x0
10520 14:00:51.841258
10521 14:00:51.847685 ec_init: CrosEC protocol v3 supported (256, 248)
10522 14:00:51.847783
10523 14:00:51.851288 tpm_cleanup: add release locality here.
10524 14:00:51.851377
10525 14:00:51.854334 Shutting down all USB controllers.
10526 14:00:51.854444
10527 14:00:51.857765 Removing current net device
10528 14:00:51.857874
10529 14:00:51.861114 Exiting depthcharge with code 4 at timestamp: 91235917
10530 14:00:51.861221
10531 14:00:51.864413 LZMA decompressing kernel-1 to 0x821a6718
10532 14:00:51.864520
10533 14:00:51.871340 LZMA decompressing kernel-1 to 0x40000000
10534 14:00:54.249130
10535 14:00:54.249307 jumping to kernel
10536 14:00:54.249417
10537 14:00:54.249510 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10538 14:00:54.249614 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j94721-arm64-gcc-10-defconfig-arm64-chromebook-24hbd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024
10539 14:00:54.249745 [ 0.000000] random: crng init done
10540 14:00:54.249856 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10541 14:00:54.249968 [ 0.000000] efi: UEFI not found.
10542 14:00:54.250066 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10543 14:00:54.250165 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10544 14:00:54.250263 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10545 14:00:54.250359 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10546 14:00:54.250455 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10547 14:00:54.250550 [ 0.000000] printk: bootconsole [mtk8250] enabled
10548 14:00:54.250644 [ 0.000000] NUMA: No NUMA configuration found
10549 14:00:54.250738 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10550 14:00:54.250832 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10551 14:00:54.250926 [ 0.000000] Zone ranges:
10552 14:00:54.251018 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10553 14:00:54.251111 [ 0.000000] DMA32 empty
10554 14:00:54.251201 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10555 14:00:54.251291 [ 0.000000] Movable zone start for each node
10556 14:00:54.251377 [ 0.000000] Early memory node ranges
10557 14:00:54.251470 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10558 14:00:54.251564 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10559 14:00:54.251671 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10560 14:00:54.251762 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10561 14:00:54.251902 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10562 14:00:54.251997 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10563 14:00:54.252091 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10564 14:00:54.252186 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10565 14:00:54.252281 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10566 14:00:54.252387 [ 0.000000] psci: probing for conduit method from DT.
10567 14:00:54.252482 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10568 14:00:54.252577 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10569 14:00:54.252671 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10570 14:00:54.252765 [ 0.000000] psci: SMC Calling Convention v1.2
10571 14:00:54.252858 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10572 14:00:54.252952 [ 0.000000] Detected VIPT I-cache on CPU0
10573 14:00:54.253045 [ 0.000000] CPU features: detected: GIC system register CPU interface
10574 14:00:54.253140 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10575 14:00:54.253234 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10576 14:00:54.253328 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10577 14:00:54.253422 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10578 14:00:54.253517 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10579 14:00:54.253614 [ 0.000000] alternatives: applying boot alternatives
10580 14:00:54.253710 [ 0.000000] Fallback order for Node 0: 0
10581 14:00:54.253805 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10582 14:00:54.253899 [ 0.000000] Policy zone: Normal
10583 14:00:54.253993 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10584 14:00:54.254091 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10585 14:00:54.254197 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10586 14:00:54.254292 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10587 14:00:54.254378 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10588 14:00:54.254472 <6>[ 0.000000] software IO TLB: area num 8.
10589 14:00:54.254567 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10590 14:00:54.255405 end: 2.2.4 bootloader-commands (duration 00:01:04) [common]
10591 14:00:54.255549 start: 2.2.5 auto-login-action (timeout 00:03:21) [common]
10592 14:00:54.255662 Setting prompt string to ['Linux version [0-9]']
10593 14:00:54.255771 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10594 14:00:54.255883 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10595 14:00:54.256359 start: 2.2.5.1 login-action (timeout 00:03:21) [common]
10596 14:00:54.256488 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10597 14:00:54.256596 Setting prompt string to []
10598 14:00:54.256715 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10599 14:00:54.256831 Using line separator: #'\n'#
10600 14:00:54.256928 No login prompt set.
10601 14:00:54.257034 Parsing kernel messages
10602 14:00:54.257128 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10603 14:00:54.257302 [login-action] Waiting for messages, (timeout 00:03:21)
10604 14:00:54.258335 <6>[ 0.000000] Memory: 7871208K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 481560K reserved, 32768K cma-reserved)
10605 14:00:54.258443 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10606 14:00:54.258537 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10607 14:00:54.258630 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10608 14:00:54.258728 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10609 14:00:54.258825 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10610 14:00:54.258922 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10611 14:00:54.259019 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10612 14:00:54.259115 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10613 14:00:54.259210 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10614 14:00:54.259305 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10615 14:00:54.259400 <6>[ 0.000000] GICv3: 608 SPIs implemented
10616 14:00:54.259494 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10617 14:00:54.259589 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10618 14:00:54.259683 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10619 14:00:54.259806 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10620 14:00:54.259902 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10621 14:00:54.259997 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10622 14:00:54.260093 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10623 14:00:54.260188 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10624 14:00:54.260283 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10625 14:00:54.260386 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10626 14:00:54.260481 <6>[ 0.009190] Console: colour dummy device 80x25
10627 14:00:54.260576 <6>[ 0.013918] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10628 14:00:54.260671 <6>[ 0.024361] pid_max: default: 32768 minimum: 301
10629 14:00:54.260766 <6>[ 0.029231] LSM: Security Framework initializing
10630 14:00:54.260861 <6>[ 0.034169] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10631 14:00:54.260957 <6>[ 0.041983] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10632 14:00:54.261051 <6>[ 0.051398] cblist_init_generic: Setting adjustable number of callback queues.
10633 14:00:54.261146 <6>[ 0.058887] cblist_init_generic: Setting shift to 3 and lim to 1.
10634 14:00:54.261266 <6>[ 0.065227] cblist_init_generic: Setting adjustable number of callback queues.
10635 14:00:54.263208 <6>[ 0.072654] cblist_init_generic: Setting shift to 3 and lim to 1.
10636 14:00:54.269806 <6>[ 0.079095] rcu: Hierarchical SRCU implementation.
10637 14:00:54.276742 <6>[ 0.084142] rcu: Max phase no-delay instances is 1000.
10638 14:00:54.282974 <6>[ 0.091169] EFI services will not be available.
10639 14:00:54.286216 <6>[ 0.096132] smp: Bringing up secondary CPUs ...
10640 14:00:54.294622 <6>[ 0.101179] Detected VIPT I-cache on CPU1
10641 14:00:54.301261 <6>[ 0.101249] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10642 14:00:54.307483 <6>[ 0.101280] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10643 14:00:54.310856 <6>[ 0.101626] Detected VIPT I-cache on CPU2
10644 14:00:54.317347 <6>[ 0.101679] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10645 14:00:54.324028 <6>[ 0.101696] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10646 14:00:54.330838 <6>[ 0.101957] Detected VIPT I-cache on CPU3
10647 14:00:54.337195 <6>[ 0.102004] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10648 14:00:54.344046 <6>[ 0.102018] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10649 14:00:54.347568 <6>[ 0.102326] CPU features: detected: Spectre-v4
10650 14:00:54.353824 <6>[ 0.102333] CPU features: detected: Spectre-BHB
10651 14:00:54.357303 <6>[ 0.102338] Detected PIPT I-cache on CPU4
10652 14:00:54.363600 <6>[ 0.102395] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10653 14:00:54.370227 <6>[ 0.102412] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10654 14:00:54.377433 <6>[ 0.102705] Detected PIPT I-cache on CPU5
10655 14:00:54.384070 <6>[ 0.102768] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10656 14:00:54.390202 <6>[ 0.102785] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10657 14:00:54.393575 <6>[ 0.103063] Detected PIPT I-cache on CPU6
10658 14:00:54.399849 <6>[ 0.103126] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10659 14:00:54.406947 <6>[ 0.103143] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10660 14:00:54.413188 <6>[ 0.103439] Detected PIPT I-cache on CPU7
10661 14:00:54.420279 <6>[ 0.103502] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10662 14:00:54.426404 <6>[ 0.103519] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10663 14:00:54.429704 <6>[ 0.103567] smp: Brought up 1 node, 8 CPUs
10664 14:00:54.436789 <6>[ 0.244774] SMP: Total of 8 processors activated.
10665 14:00:54.439976 <6>[ 0.249716] CPU features: detected: 32-bit EL0 Support
10666 14:00:54.450002 <6>[ 0.255112] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10667 14:00:54.456360 <6>[ 0.263912] CPU features: detected: Common not Private translations
10668 14:00:54.463434 <6>[ 0.270428] CPU features: detected: CRC32 instructions
10669 14:00:54.466218 <6>[ 0.275812] CPU features: detected: RCpc load-acquire (LDAPR)
10670 14:00:54.473062 <6>[ 0.281808] CPU features: detected: LSE atomic instructions
10671 14:00:54.479406 <6>[ 0.287589] CPU features: detected: Privileged Access Never
10672 14:00:54.486522 <6>[ 0.293369] CPU features: detected: RAS Extension Support
10673 14:00:54.492846 <6>[ 0.299013] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10674 14:00:54.496334 <6>[ 0.306230] CPU: All CPU(s) started at EL2
10675 14:00:54.503120 <6>[ 0.310574] alternatives: applying system-wide alternatives
10676 14:00:54.512096 <6>[ 0.321242] devtmpfs: initialized
10677 14:00:54.527502 <6>[ 0.330224] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10678 14:00:54.534412 <6>[ 0.340187] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10679 14:00:54.540839 <6>[ 0.348428] pinctrl core: initialized pinctrl subsystem
10680 14:00:54.543926 <6>[ 0.355074] DMI not present or invalid.
10681 14:00:54.550772 <6>[ 0.359488] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10682 14:00:54.560740 <6>[ 0.366355] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10683 14:00:54.567454 <6>[ 0.373943] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10684 14:00:54.576984 <6>[ 0.382176] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10685 14:00:54.580423 <6>[ 0.390419] audit: initializing netlink subsys (disabled)
10686 14:00:54.590290 <5>[ 0.396110] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10687 14:00:54.596850 <6>[ 0.396809] thermal_sys: Registered thermal governor 'step_wise'
10688 14:00:54.603338 <6>[ 0.404078] thermal_sys: Registered thermal governor 'power_allocator'
10689 14:00:54.607072 <6>[ 0.410332] cpuidle: using governor menu
10690 14:00:54.613746 <6>[ 0.421293] NET: Registered PF_QIPCRTR protocol family
10691 14:00:54.620548 <6>[ 0.426770] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10692 14:00:54.623419 <6>[ 0.433870] ASID allocator initialised with 32768 entries
10693 14:00:54.631074 <6>[ 0.440435] Serial: AMBA PL011 UART driver
10694 14:00:54.640248 <4>[ 0.449222] Trying to register duplicate clock ID: 134
10695 14:00:54.696156 <6>[ 0.508543] KASLR enabled
10696 14:00:54.710316 <6>[ 0.516317] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10697 14:00:54.717077 <6>[ 0.523333] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10698 14:00:54.723607 <6>[ 0.529822] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10699 14:00:54.729825 <6>[ 0.536828] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10700 14:00:54.736854 <6>[ 0.543314] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10701 14:00:54.743117 <6>[ 0.550317] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10702 14:00:54.750281 <6>[ 0.556802] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10703 14:00:54.756367 <6>[ 0.563805] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10704 14:00:54.759718 <6>[ 0.571332] ACPI: Interpreter disabled.
10705 14:00:54.768634 <6>[ 0.577767] iommu: Default domain type: Translated
10706 14:00:54.775350 <6>[ 0.582881] iommu: DMA domain TLB invalidation policy: strict mode
10707 14:00:54.778246 <5>[ 0.589539] SCSI subsystem initialized
10708 14:00:54.784671 <6>[ 0.593706] usbcore: registered new interface driver usbfs
10709 14:00:54.791831 <6>[ 0.599439] usbcore: registered new interface driver hub
10710 14:00:54.794491 <6>[ 0.604992] usbcore: registered new device driver usb
10711 14:00:54.802002 <6>[ 0.611091] pps_core: LinuxPPS API ver. 1 registered
10712 14:00:54.811949 <6>[ 0.616286] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10713 14:00:54.815361 <6>[ 0.625633] PTP clock support registered
10714 14:00:54.818531 <6>[ 0.629874] EDAC MC: Ver: 3.0.0
10715 14:00:54.825567 <6>[ 0.635031] FPGA manager framework
10716 14:00:54.829434 <6>[ 0.638712] Advanced Linux Sound Architecture Driver Initialized.
10717 14:00:54.832656 <6>[ 0.645487] vgaarb: loaded
10718 14:00:54.839332 <6>[ 0.648636] clocksource: Switched to clocksource arch_sys_counter
10719 14:00:54.846373 <5>[ 0.655078] VFS: Disk quotas dquot_6.6.0
10720 14:00:54.852745 <6>[ 0.659262] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10721 14:00:54.856207 <6>[ 0.666450] pnp: PnP ACPI: disabled
10722 14:00:54.863705 <6>[ 0.673211] NET: Registered PF_INET protocol family
10723 14:00:54.870461 <6>[ 0.678797] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10724 14:00:54.884854 <6>[ 0.691110] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10725 14:00:54.895229 <6>[ 0.699922] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10726 14:00:54.901406 <6>[ 0.707891] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10727 14:00:54.911608 <6>[ 0.716594] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10728 14:00:54.917898 <6>[ 0.726343] TCP: Hash tables configured (established 65536 bind 65536)
10729 14:00:54.924568 <6>[ 0.733202] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10730 14:00:54.935056 <6>[ 0.740402] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10731 14:00:54.938313 <6>[ 0.748104] NET: Registered PF_UNIX/PF_LOCAL protocol family
10732 14:00:54.944796 <6>[ 0.754281] RPC: Registered named UNIX socket transport module.
10733 14:00:54.951737 <6>[ 0.760433] RPC: Registered udp transport module.
10734 14:00:54.954849 <6>[ 0.765366] RPC: Registered tcp transport module.
10735 14:00:54.961771 <6>[ 0.770300] RPC: Registered tcp NFSv4.1 backchannel transport module.
10736 14:00:54.968145 <6>[ 0.776964] PCI: CLS 0 bytes, default 64
10737 14:00:54.971409 <6>[ 0.781353] Unpacking initramfs...
10738 14:00:54.987575 <6>[ 0.793226] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10739 14:00:54.997497 <6>[ 0.801896] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10740 14:00:55.000895 <6>[ 0.810759] kvm [1]: IPA Size Limit: 40 bits
10741 14:00:55.007200 <6>[ 0.815287] kvm [1]: GICv3: no GICV resource entry
10742 14:00:55.010692 <6>[ 0.820308] kvm [1]: disabling GICv2 emulation
10743 14:00:55.016712 <6>[ 0.824993] kvm [1]: GIC system register CPU interface enabled
10744 14:00:55.027285 <6>[ 0.836674] kvm [1]: vgic interrupt IRQ18
10745 14:00:55.030773 <6>[ 0.841081] kvm [1]: VHE mode initialized successfully
10746 14:00:55.038428 <5>[ 0.847561] Initialise system trusted keyrings
10747 14:00:55.044952 <6>[ 0.852375] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10748 14:00:55.053175 <6>[ 0.862370] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10749 14:00:55.059498 <5>[ 0.868797] NFS: Registering the id_resolver key type
10750 14:00:55.063014 <5>[ 0.874095] Key type id_resolver registered
10751 14:00:55.069702 <5>[ 0.878509] Key type id_legacy registered
10752 14:00:55.076422 <6>[ 0.882784] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10753 14:00:55.082809 <6>[ 0.889708] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10754 14:00:55.089576 <6>[ 0.897419] 9p: Installing v9fs 9p2000 file system support
10755 14:00:55.126022 <5>[ 0.935334] Key type asymmetric registered
10756 14:00:55.129319 <5>[ 0.939664] Asymmetric key parser 'x509' registered
10757 14:00:55.139155 <6>[ 0.944803] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10758 14:00:55.142519 <6>[ 0.952414] io scheduler mq-deadline registered
10759 14:00:55.146000 <6>[ 0.957179] io scheduler kyber registered
10760 14:00:55.164854 <6>[ 0.974240] EINJ: ACPI disabled.
10761 14:00:55.197470 <4>[ 1.000018] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10762 14:00:55.207316 <4>[ 1.010657] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10763 14:00:55.222415 <6>[ 1.031441] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10764 14:00:55.230203 <6>[ 1.039396] printk: console [ttyS0] disabled
10765 14:00:55.257882 <6>[ 1.064049] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10766 14:00:55.264976 <6>[ 1.073521] printk: console [ttyS0] enabled
10767 14:00:55.268214 <6>[ 1.073521] printk: console [ttyS0] enabled
10768 14:00:55.274460 <6>[ 1.082415] printk: bootconsole [mtk8250] disabled
10769 14:00:55.277889 <6>[ 1.082415] printk: bootconsole [mtk8250] disabled
10770 14:00:55.284897 <6>[ 1.093487] SuperH (H)SCI(F) driver initialized
10771 14:00:55.287748 <6>[ 1.098766] msm_serial: driver initialized
10772 14:00:55.301820 <6>[ 1.107665] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10773 14:00:55.311459 <6>[ 1.116212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10774 14:00:55.318174 <6>[ 1.124755] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10775 14:00:55.328152 <6>[ 1.133384] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10776 14:00:55.337971 <6>[ 1.142091] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10777 14:00:55.344590 <6>[ 1.150805] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10778 14:00:55.354937 <6>[ 1.159346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10779 14:00:55.361568 <6>[ 1.168140] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10780 14:00:55.371175 <6>[ 1.176683] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10781 14:00:55.382969 <6>[ 1.192010] loop: module loaded
10782 14:00:55.388987 <6>[ 1.197884] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10783 14:00:55.411683 <4>[ 1.221200] mtk-pmic-keys: Failed to locate of_node [id: -1]
10784 14:00:55.418638 <6>[ 1.227954] megasas: 07.719.03.00-rc1
10785 14:00:55.428308 <6>[ 1.237679] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10786 14:00:55.434836 <6>[ 1.244013] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10787 14:00:55.451401 <6>[ 1.260600] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10788 14:00:55.508329 <6>[ 1.310677] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10789 14:00:58.954442 <6>[ 4.764179] Freeing initrd memory: 96044K
10790 14:00:58.964641 <6>[ 4.774609] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10791 14:00:58.975840 <6>[ 4.785652] tun: Universal TUN/TAP device driver, 1.6
10792 14:00:58.979180 <6>[ 4.791718] thunder_xcv, ver 1.0
10793 14:00:58.982670 <6>[ 4.795224] thunder_bgx, ver 1.0
10794 14:00:58.986238 <6>[ 4.798720] nicpf, ver 1.0
10795 14:00:58.996636 <6>[ 4.802749] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10796 14:00:58.999456 <6>[ 4.810225] hns3: Copyright (c) 2017 Huawei Corporation.
10797 14:00:59.005979 <6>[ 4.815813] hclge is initializing
10798 14:00:59.010043 <6>[ 4.819389] e1000: Intel(R) PRO/1000 Network Driver
10799 14:00:59.016446 <6>[ 4.824518] e1000: Copyright (c) 1999-2006 Intel Corporation.
10800 14:00:59.019237 <6>[ 4.830530] e1000e: Intel(R) PRO/1000 Network Driver
10801 14:00:59.026084 <6>[ 4.835746] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10802 14:00:59.032955 <6>[ 4.841936] igb: Intel(R) Gigabit Ethernet Network Driver
10803 14:00:59.039719 <6>[ 4.847587] igb: Copyright (c) 2007-2014 Intel Corporation.
10804 14:00:59.045838 <6>[ 4.853423] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10805 14:00:59.052613 <6>[ 4.859941] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10806 14:00:59.056048 <6>[ 4.866402] sky2: driver version 1.30
10807 14:00:59.062373 <6>[ 4.871399] VFIO - User Level meta-driver version: 0.3
10808 14:00:59.069991 <6>[ 4.879640] usbcore: registered new interface driver usb-storage
10809 14:00:59.076910 <6>[ 4.886090] usbcore: registered new device driver onboard-usb-hub
10810 14:00:59.085538 <6>[ 4.895260] mt6397-rtc mt6359-rtc: registered as rtc0
10811 14:00:59.095234 <6>[ 4.900746] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-01T13:58:16 UTC (1706795896)
10812 14:00:59.098777 <6>[ 4.910321] i2c_dev: i2c /dev entries driver
10813 14:00:59.115521 <6>[ 4.922174] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10814 14:00:59.135285 <6>[ 4.945182] cpu cpu0: EM: created perf domain
10815 14:00:59.138945 <6>[ 4.950127] cpu cpu4: EM: created perf domain
10816 14:00:59.146058 <6>[ 4.955773] sdhci: Secure Digital Host Controller Interface driver
10817 14:00:59.152746 <6>[ 4.962206] sdhci: Copyright(c) Pierre Ossman
10818 14:00:59.159812 <6>[ 4.967150] Synopsys Designware Multimedia Card Interface Driver
10819 14:00:59.162846 <6>[ 4.973783] mmc0: CQHCI version 5.10
10820 14:00:59.169093 <6>[ 4.973791] sdhci-pltfm: SDHCI platform and OF driver helper
10821 14:00:59.176271 <6>[ 4.984613] ledtrig-cpu: registered to indicate activity on CPUs
10822 14:00:59.182767 <6>[ 4.991642] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10823 14:00:59.189319 <6>[ 4.998694] usbcore: registered new interface driver usbhid
10824 14:00:59.192551 <6>[ 5.004516] usbhid: USB HID core driver
10825 14:00:59.202703 <6>[ 5.008714] spi_master spi0: will run message pump with realtime priority
10826 14:00:59.245040 <6>[ 5.048198] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10827 14:00:59.264124 <6>[ 5.064119] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10828 14:00:59.267564 <6>[ 5.077751] mmc0: Command Queue Engine enabled
10829 14:00:59.274353 <6>[ 5.082530] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10830 14:00:59.281336 <6>[ 5.089801] mmcblk0: mmc0:0001 DA4128 116 GiB
10831 14:00:59.284150 <6>[ 5.094722] cros-ec-spi spi0.0: Chrome EC device registered
10832 14:00:59.292421 <6>[ 5.102137] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10833 14:00:59.300380 <6>[ 5.109571] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10834 14:00:59.306421 <6>[ 5.115746] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10835 14:00:59.313338 <6>[ 5.121868] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10836 14:00:59.331263 <6>[ 5.137491] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10837 14:00:59.338826 <6>[ 5.148370] NET: Registered PF_PACKET protocol family
10838 14:00:59.341643 <6>[ 5.153760] 9pnet: Installing 9P2000 support
10839 14:00:59.348524 <5>[ 5.158325] Key type dns_resolver registered
10840 14:00:59.351897 <6>[ 5.163321] registered taskstats version 1
10841 14:00:59.358563 <5>[ 5.167709] Loading compiled-in X.509 certificates
10842 14:00:59.391000 <4>[ 5.193616] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10843 14:00:59.400847 <4>[ 5.204363] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10844 14:00:59.407343 <3>[ 5.214898] debugfs: File 'uA_load' in directory '/' already present!
10845 14:00:59.414092 <3>[ 5.221601] debugfs: File 'min_uV' in directory '/' already present!
10846 14:00:59.420169 <3>[ 5.228212] debugfs: File 'max_uV' in directory '/' already present!
10847 14:00:59.426891 <3>[ 5.234818] debugfs: File 'constraint_flags' in directory '/' already present!
10848 14:00:59.437892 <3>[ 5.244591] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10849 14:00:59.450043 <6>[ 5.260058] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10850 14:00:59.457267 <6>[ 5.266814] xhci-mtk 11200000.usb: xHCI Host Controller
10851 14:00:59.463612 <6>[ 5.272326] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10852 14:00:59.473530 <6>[ 5.280198] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10853 14:00:59.480107 <6>[ 5.289646] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10854 14:00:59.487289 <6>[ 5.295847] xhci-mtk 11200000.usb: xHCI Host Controller
10855 14:00:59.493677 <6>[ 5.301344] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10856 14:00:59.500029 <6>[ 5.309111] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10857 14:00:59.507313 <6>[ 5.317014] hub 1-0:1.0: USB hub found
10858 14:00:59.510715 <6>[ 5.321049] hub 1-0:1.0: 1 port detected
10859 14:00:59.520583 <6>[ 5.325358] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10860 14:00:59.524187 <6>[ 5.334165] hub 2-0:1.0: USB hub found
10861 14:00:59.526986 <6>[ 5.338190] hub 2-0:1.0: 1 port detected
10862 14:00:59.535860 <6>[ 5.345419] mtk-msdc 11f70000.mmc: Got CD GPIO
10863 14:00:59.549704 <6>[ 5.356250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10864 14:00:59.556244 <6>[ 5.364280] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10865 14:00:59.566370 <4>[ 5.372213] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10866 14:00:59.575996 <6>[ 5.381784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10867 14:00:59.583031 <6>[ 5.389863] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10868 14:00:59.589860 <6>[ 5.397884] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10869 14:00:59.599432 <6>[ 5.405801] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10870 14:00:59.606192 <6>[ 5.413619] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10871 14:00:59.616206 <6>[ 5.421436] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10872 14:00:59.628796 <6>[ 5.431872] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10873 14:00:59.632682 <6>[ 5.440237] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10874 14:00:59.642568 <6>[ 5.448584] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10875 14:00:59.648999 <6>[ 5.456925] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10876 14:00:59.658957 <6>[ 5.465265] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10877 14:00:59.665831 <6>[ 5.473608] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10878 14:00:59.675652 <6>[ 5.481947] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10879 14:00:59.682344 <6>[ 5.490286] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10880 14:00:59.692247 <6>[ 5.498624] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10881 14:00:59.699250 <6>[ 5.506963] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10882 14:00:59.708782 <6>[ 5.515301] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10883 14:00:59.715597 <6>[ 5.523639] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10884 14:00:59.726065 <6>[ 5.531977] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10885 14:00:59.735610 <6>[ 5.540318] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10886 14:00:59.741813 <6>[ 5.548658] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10887 14:00:59.748749 <6>[ 5.557393] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10888 14:00:59.755783 <6>[ 5.564570] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10889 14:00:59.762107 <6>[ 5.571335] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10890 14:00:59.768522 <6>[ 5.578095] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10891 14:00:59.775302 <6>[ 5.585030] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10892 14:00:59.785346 <6>[ 5.591883] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10893 14:00:59.795320 <6>[ 5.601018] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10894 14:00:59.805093 <6>[ 5.610136] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10895 14:00:59.814962 <6>[ 5.619431] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10896 14:00:59.824783 <6>[ 5.628898] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10897 14:00:59.831716 <6>[ 5.638364] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10898 14:00:59.841743 <6>[ 5.647485] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10899 14:00:59.851919 <6>[ 5.656951] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10900 14:00:59.861620 <6>[ 5.666069] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10901 14:00:59.871417 <6>[ 5.675362] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10902 14:00:59.881495 <6>[ 5.685522] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10903 14:00:59.891564 <6>[ 5.697023] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10904 14:00:59.942001 <6>[ 5.748914] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10905 14:01:00.096871 <6>[ 5.906329] hub 1-1:1.0: USB hub found
10906 14:01:00.099754 <6>[ 5.910802] hub 1-1:1.0: 4 ports detected
10907 14:01:00.108836 <6>[ 5.918666] hub 1-1:1.0: USB hub found
10908 14:01:00.112074 <6>[ 5.923192] hub 1-1:1.0: 4 ports detected
10909 14:01:00.222410 <6>[ 6.029304] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10910 14:01:00.248756 <6>[ 6.058710] hub 2-1:1.0: USB hub found
10911 14:01:00.251810 <6>[ 6.063217] hub 2-1:1.0: 3 ports detected
10912 14:01:00.261798 <6>[ 6.071441] hub 2-1:1.0: USB hub found
10913 14:01:00.265055 <6>[ 6.075885] hub 2-1:1.0: 3 ports detected
10914 14:01:00.438564 <6>[ 6.244962] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10915 14:01:00.571029 <6>[ 6.381001] hub 1-1.4:1.0: USB hub found
10916 14:01:00.574472 <6>[ 6.385684] hub 1-1.4:1.0: 2 ports detected
10917 14:01:00.583544 <6>[ 6.393515] hub 1-1.4:1.0: USB hub found
10918 14:01:00.586875 <6>[ 6.398029] hub 1-1.4:1.0: 2 ports detected
10919 14:01:00.654372 <6>[ 6.460809] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10920 14:01:00.882302 <6>[ 6.688933] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10921 14:01:01.074536 <6>[ 6.880959] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10922 14:01:12.183242 <6>[ 17.997983] ALSA device list:
10923 14:01:12.190052 <6>[ 18.001285] No soundcards found.
10924 14:01:12.198048 <6>[ 18.009402] Freeing unused kernel memory: 8448K
10925 14:01:12.201183 <6>[ 18.014447] Run /init as init process
10926 14:01:12.255080 <6>[ 18.066104] NET: Registered PF_INET6 protocol family
10927 14:01:12.261614 <6>[ 18.072692] Segment Routing with IPv6
10928 14:01:12.264988 <6>[ 18.076622] In-situ OAM (IOAM) with IPv6
10929 14:01:12.298970 <30>[ 18.090241] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10930 14:01:12.302323 <30>[ 18.113950] systemd[1]: Detected architecture arm64.
10931 14:01:12.302404
10932 14:01:12.308494 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10933 14:01:12.308568
10934 14:01:12.322120 <30>[ 18.132969] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10935 14:01:12.479897 <30>[ 18.288005] systemd[1]: Queued start job for default target Graphical Interface.
10936 14:01:12.510282 <30>[ 18.321725] systemd[1]: Created slice system-getty.slice.
10937 14:01:12.516762 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10938 14:01:12.534290 <30>[ 18.345218] systemd[1]: Created slice system-modprobe.slice.
10939 14:01:12.540573 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10940 14:01:12.558411 <30>[ 18.369577] systemd[1]: Created slice system-serial\x2dgetty.slice.
10941 14:01:12.568172 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10942 14:01:12.582476 <30>[ 18.393332] systemd[1]: Created slice User and Session Slice.
10943 14:01:12.588501 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10944 14:01:12.609750 <30>[ 18.417578] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10945 14:01:12.619728 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10946 14:01:12.637344 <30>[ 18.445524] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10947 14:01:12.644330 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10948 14:01:12.664499 <30>[ 18.468913] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10949 14:01:12.671072 <30>[ 18.481006] systemd[1]: Reached target Local Encrypted Volumes.
10950 14:01:12.677291 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10951 14:01:12.693949 <30>[ 18.505378] systemd[1]: Reached target Paths.
10952 14:01:12.697463 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10953 14:01:12.713403 <30>[ 18.524944] systemd[1]: Reached target Remote File Systems.
10954 14:01:12.719984 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10955 14:01:12.734004 <30>[ 18.544921] systemd[1]: Reached target Slices.
10956 14:01:12.736842 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10957 14:01:12.753999 <30>[ 18.564963] systemd[1]: Reached target Swap.
10958 14:01:12.756899 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10959 14:01:12.777524 <30>[ 18.585453] systemd[1]: Listening on initctl Compatibility Named Pipe.
10960 14:01:12.784157 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10961 14:01:12.791039 <30>[ 18.600730] systemd[1]: Listening on Journal Audit Socket.
10962 14:01:13.342871 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10963 14:01:13.343038 <30>[ 18.622189] systemd[1]: Listening on Journal Socket (/dev/log).
10964 14:01:13.343140 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10965 14:01:13.343249 <30>[ 18.645538] systemd[1]: Listening on Journal Socket.
10966 14:01:13.343350 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10967 14:01:13.343446 <30>[ 18.665583] systemd[1]: Listening on udev Control Socket.
10968 14:01:13.343541 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10969 14:01:13.343616 <30>[ 18.690063] systemd[1]: Listening on udev Kernel Socket.
10970 14:01:13.343703 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10971 14:01:13.343772 <30>[ 18.745137] systemd[1]: Mounting Huge Pages File System...
10972 14:01:13.343835 Mounting [0;1;39mHuge Pages File System[0m...
10973 14:01:13.343906 <30>[ 18.769483] systemd[1]: Mounting POSIX Message Queue File System...
10974 14:01:13.344001 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10975 14:01:13.344093 <30>[ 18.821029] systemd[1]: Mounting Kernel Debug File System...
10976 14:01:13.344185 Mounting [0;1;39mKernel Debug File System[0m...
10977 14:01:13.344282 <30>[ 18.845507] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10978 14:01:13.344364 <30>[ 18.859071] systemd[1]: Starting Create list of static device nodes for the current kernel...
10979 14:01:13.344425 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10980 14:01:13.344486 <30>[ 18.893872] systemd[1]: Starting Load Kernel Module configfs...
10981 14:01:13.344545 Starting [0;1;39mLoad Kernel Module configfs[0m...
10982 14:01:13.344615 <30>[ 18.933173] systemd[1]: Starting Load Kernel Module drm...
10983 14:01:13.344681 Starting [0;1;39mLoad Kernel Module drm[0m...
10984 14:01:13.344741 <30>[ 18.957064] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10985 14:01:13.344801 <30>[ 18.975516] systemd[1]: Starting Journal Service...
10986 14:01:13.344860 Starting [0;1;39mJournal Service[0m...
10987 14:01:13.344920 <30>[ 19.029880] systemd[1]: Starting Load Kernel Modules...
10988 14:01:13.344980 Starting [0;1;39mLoad Kernel Modules[0m...
10989 14:01:13.345039 <30>[ 19.051302] systemd[1]: Starting Remount Root and Kernel File Systems...
10990 14:01:13.345098 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10991 14:01:13.345163 <30>[ 19.079387] systemd[1]: Starting Coldplug All udev Devices...
10992 14:01:13.345251 Starting [0;1;39mColdplug All udev Devices[0m...
10993 14:01:13.345312 <30>[ 19.107986] systemd[1]: Started Journal Service.
10994 14:01:13.345381 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10995 14:01:13.345442 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10996 14:01:13.346567 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10997 14:01:13.366458 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10998 14:01:13.390978 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10999 14:01:13.413194 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11000 14:01:13.437063 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11001 14:01:13.459710 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11002 14:01:13.484463 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11003 14:01:13.497641 See 'systemctl status systemd-remount-fs.service' for details.
11004 14:01:13.539425 Mounting [0;1;39mKernel Configuration File System[0m...
11005 14:01:13.557041 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11006 14:01:13.571419 <46>[ 19.379484] systemd-journald[175]: Received client request to flush runtime journal.
11007 14:01:13.582473 Starting [0;1;39mLoad/Save Random Seed[0m...
11008 14:01:13.602825 Starting [0;1;39mApply Kernel Variables[0m...
11009 14:01:13.621958 Starting [0;1;39mCreate System Users[0m...
11010 14:01:13.640252 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11011 14:01:13.660013 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11012 14:01:13.683284 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11013 14:01:13.699704 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11014 14:01:13.715475 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11015 14:01:13.731302 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11016 14:01:13.770311 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11017 14:01:13.793774 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11018 14:01:13.810040 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11019 14:01:13.829977 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11020 14:01:13.870628 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11021 14:01:13.897749 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11022 14:01:13.922586 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11023 14:01:13.944308 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11024 14:01:14.004004 Starting [0;1;39mNetwork Time Synchronization[0m...
11025 14:01:14.024516 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11026 14:01:14.065987 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11027 14:01:14.087316 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11028 14:01:14.112816 <6>[ 19.920472] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11029 14:01:14.131342 <6>[ 19.942663] remoteproc remoteproc0: scp is available
11030 14:01:14.138250 <6>[ 19.949312] remoteproc remoteproc0: powering up scp
11031 14:01:14.147804 <6>[ 19.954499] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11032 14:01:14.151607 <6>[ 19.954534] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11033 14:01:14.161030 <6>[ 19.961282] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11034 14:01:14.168125 <6>[ 19.961316] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11035 14:01:14.177812 <6>[ 19.961326] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11036 14:01:14.184088 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11037 14:01:14.198415 <3>[ 20.006128] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11038 14:01:14.205053 <3>[ 20.014274] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11039 14:01:14.214994 <3>[ 20.022368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11040 14:01:14.224581 [[0;32m OK [0m] Started [0;<3>[ 20.032527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11041 14:01:14.235090 1;39mNetwork Tim<3>[ 20.042120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11042 14:01:14.241093 e Synchronizatio<6>[ 20.047179] mc: Linux media interface: v0.10
11043 14:01:14.248107 <3>[ 20.051175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11044 14:01:14.248215 n[0m.
11045 14:01:14.258395 <4>[ 20.058700] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11046 14:01:14.265021 <3>[ 20.065211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11047 14:01:14.274735 <3>[ 20.065216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11048 14:01:14.281382 <3>[ 20.073383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11049 14:01:14.287922 <6>[ 20.077975] usbcore: registered new device driver r8152-cfgselector
11050 14:01:14.294723 <4>[ 20.098516] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11051 14:01:14.304620 <3>[ 20.109414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11052 14:01:14.310934 <6>[ 20.112267] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11053 14:01:14.318221 <6>[ 20.119026] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11054 14:01:14.324660 <6>[ 20.119029] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11055 14:01:14.331548 <6>[ 20.119037] remoteproc remoteproc0: remote processor scp is now up
11056 14:01:14.341450 <3>[ 20.119832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11057 14:01:14.347655 <3>[ 20.119838] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11058 14:01:14.357500 <3>[ 20.122292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11059 14:01:14.360792 <6>[ 20.126721] pci_bus 0000:00: root bus resource [bus 00-ff]
11060 14:01:14.370985 <6>[ 20.133208] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11061 14:01:14.381322 <3>[ 20.135248] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11062 14:01:14.387711 <6>[ 20.137806] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11063 14:01:14.397456 <6>[ 20.141499] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11064 14:01:14.404023 <6>[ 20.142282] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11065 14:01:14.414202 <3>[ 20.148710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11066 14:01:14.420386 <3>[ 20.148720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11067 14:01:14.431134 <6>[ 20.156811] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11068 14:01:14.438069 <6>[ 20.156930] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11069 14:01:14.444826 <3>[ 20.165233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11070 14:01:14.451608 <6>[ 20.173200] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11071 14:01:14.461785 <3>[ 20.178942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11072 14:01:14.465186 <6>[ 20.188986] pci 0000:00:00.0: supports D1 D2
11073 14:01:14.474655 <6>[ 20.198088] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11074 14:01:14.481560 <6>[ 20.205286] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11075 14:01:14.487886 <4>[ 20.208082] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11076 14:01:14.494653 <4>[ 20.208082] Fallback method does not support PEC.
11077 14:01:14.501550 <6>[ 20.215806] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11078 14:01:14.511186 <6>[ 20.220881] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11079 14:01:14.521263 <6>[ 20.224516] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11080 14:01:14.527856 <6>[ 20.233010] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11081 14:01:14.534840 <6>[ 20.237409] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11082 14:01:14.541157 <6>[ 20.246897] videodev: Linux video capture interface: v2.00
11083 14:01:14.544448 <6>[ 20.262324] Bluetooth: Core ver 2.22
11084 14:01:14.550845 <6>[ 20.268986] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11085 14:01:14.561020 <4>[ 20.271789] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11086 14:01:14.567462 <4>[ 20.271799] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11087 14:01:14.574381 <6>[ 20.277120] NET: Registered PF_BLUETOOTH protocol family
11088 14:01:14.581335 <6>[ 20.281577] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11089 14:01:14.588338 <6>[ 20.289872] Bluetooth: HCI device and connection manager initialized
11090 14:01:14.596051 <6>[ 20.296707] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11091 14:01:14.603023 <6>[ 20.297636] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11092 14:01:14.616280 <6>[ 20.298711] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11093 14:01:14.619715 <6>[ 20.298804] usbcore: registered new interface driver uvcvideo
11094 14:01:14.627381 <6>[ 20.310362] Bluetooth: HCI socket layer initialized
11095 14:01:14.630205 <6>[ 20.318721] pci 0000:01:00.0: supports D1 D2
11096 14:01:14.633639 <6>[ 20.320774] r8152 2-1.3:1.0 eth0: v1.12.13
11097 14:01:14.640554 <6>[ 20.320841] usbcore: registered new interface driver r8152
11098 14:01:14.651436 <3>[ 20.327890] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11099 14:01:14.654810 <6>[ 20.328405] Bluetooth: L2CAP socket layer initialized
11100 14:01:14.661262 <6>[ 20.328428] Bluetooth: SCO socket layer initialized
11101 14:01:14.667647 <6>[ 20.336131] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11102 14:01:14.674875 <6>[ 20.336974] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11103 14:01:14.678266 <6>[ 20.344806] usbcore: registered new interface driver cdc_ether
11104 14:01:14.685116 <6>[ 20.368881] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11105 14:01:14.691599 <6>[ 20.377668] usbcore: registered new interface driver btusb
11106 14:01:14.701808 <4>[ 20.378473] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11107 14:01:14.708704 <3>[ 20.378488] Bluetooth: hci0: Failed to load firmware file (-2)
11108 14:01:14.715932 <3>[ 20.378491] Bluetooth: hci0: Failed to set up firmware (-2)
11109 14:01:14.726013 <4>[ 20.378495] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11110 14:01:14.732116 <6>[ 20.385064] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11111 14:01:14.738828 <6>[ 20.385150] usbcore: registered new interface driver r8153_ecm
11112 14:01:14.746402 <6>[ 20.403518] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11113 14:01:14.753134 <6>[ 20.404613] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11114 14:01:14.762786 <3>[ 20.413622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11115 14:01:14.769785 <3>[ 20.414416] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11116 14:01:14.779892 <3>[ 20.415324] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11117 14:01:14.787085 <3>[ 20.416099] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11118 14:01:14.793883 <6>[ 20.419120] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11119 14:01:14.804842 <6>[ 20.419133] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11120 14:01:14.810900 <3>[ 20.441694] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11121 14:01:14.821059 <6>[ 20.442673] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11122 14:01:14.828348 <3>[ 20.470879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11123 14:01:14.835246 <6>[ 20.471341] pci 0000:00:00.0: PCI bridge to [bus 01]
11124 14:01:14.841812 <3>[ 20.497379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11125 14:01:14.849437 <6>[ 20.502768] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11126 14:01:14.855704 <6>[ 20.502931] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11127 14:01:14.865493 <3>[ 20.529663] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11128 14:01:14.872439 <6>[ 20.531566] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11129 14:01:14.882310 <3>[ 20.563893] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11130 14:01:14.885626 <6>[ 20.570037] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11131 14:01:14.895413 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11132 14:01:14.905608 <5>[ 20.712268] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11133 14:01:14.911667 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11134 14:01:14.923852 <5>[ 20.731667] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11135 14:01:14.930111 <5>[ 20.739110] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11136 14:01:14.939906 <4>[ 20.747616] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11137 14:01:14.946448 <6>[ 20.756530] cfg80211: failed to load regulatory.db
11138 14:01:14.994613 <6>[ 20.802410] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11139 14:01:15.000925 <6>[ 20.809969] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11140 14:01:15.024977 <6>[ 20.836632] mt7921e 0000:01:00.0: ASIC revision: 79610010
11141 14:01:15.046331 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11142 14:01:15.061714 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11143 14:01:15.080396 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11144 14:01:15.093189 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11145 14:01:15.109728 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11146 14:01:15.128461 <6>[ 20.936755] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11147 14:01:15.131654 <6>[ 20.936755]
11148 14:01:15.138273 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11149 14:01:15.153812 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11150 14:01:15.173573 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11151 14:01:15.185468 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11152 14:01:15.201320 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11153 14:01:15.221337 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11154 14:01:15.290411 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11155 14:01:15.331886 Starting [0;1;39mUser Login Management[0m...
11156 14:01:15.350384 Starting [0;1;39mPermit User Sessions[0m...
11157 14:01:15.372129 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11158 14:01:15.401705 [[0;32m OK [<6>[ 21.206592] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11159 14:01:15.404589 0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11160 14:01:15.422905 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11161 14:01:15.442878 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11162 14:01:15.483644 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11163 14:01:15.504121 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11164 14:01:15.522151 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11165 14:01:15.538244 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11166 14:01:15.554149 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11167 14:01:15.595067 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11168 14:01:15.636603 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11169 14:01:15.675980
11170 14:01:15.676109
11171 14:01:15.679014 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11172 14:01:15.679103
11173 14:01:15.682661 debian-bullseye-arm64 login: root (automatic login)
11174 14:01:15.682745
11175 14:01:15.682807
11176 14:01:15.708141 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Thu Feb 1 13:35:47 UTC 2024 aarch64
11177 14:01:15.708256
11178 14:01:15.714923 The programs included with the Debian GNU/Linux system are free software;
11179 14:01:15.721464 the exact distribution terms for each program are described in the
11180 14:01:15.724950 individual files in /usr/share/doc/*/copyright.
11181 14:01:15.725031
11182 14:01:15.731880 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11183 14:01:15.734672 permitted by applicable law.
11184 14:01:15.735033 Matched prompt #10: / #
11186 14:01:15.735260 Setting prompt string to ['/ #']
11187 14:01:15.735358 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11189 14:01:15.735552 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11190 14:01:15.735645 start: 2.2.6 expect-shell-connection (timeout 00:02:59) [common]
11191 14:01:15.735714 Setting prompt string to ['/ #']
11192 14:01:15.735772 Forcing a shell prompt, looking for ['/ #']
11194 14:01:15.785965 / #
11195 14:01:15.786115 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11196 14:01:15.786239 Waiting using forced prompt support (timeout 00:02:30)
11197 14:01:15.791512
11198 14:01:15.791887 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11199 14:01:15.792055 start: 2.2.7 export-device-env (timeout 00:02:59) [common]
11200 14:01:15.792220 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11201 14:01:15.792371 end: 2.2 depthcharge-retry (duration 00:02:01) [common]
11202 14:01:15.792523 end: 2 depthcharge-action (duration 00:02:01) [common]
11203 14:01:15.792674 start: 3 lava-test-retry (timeout 00:05:00) [common]
11204 14:01:15.792831 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11205 14:01:15.792935 Using namespace: common
11207 14:01:15.893288 / # #
11208 14:01:15.893471 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11209 14:01:15.898198 #
11210 14:01:15.898503 Using /lava-12682961
11212 14:01:15.998846 / # export SHELL=/bin/sh
11213 14:01:16.003766 export SHELL=/bin/sh
11215 14:01:16.104315 / # . /lava-12682961/environment
11216 14:01:16.109444 . /lava-12682961/environment
11218 14:01:16.210019 / # /lava-12682961/bin/lava-test-runner /lava-12682961/0
11219 14:01:16.210192 Test shell timeout: 10s (minimum of the action and connection timeout)
11220 14:01:16.214934 /lava-12682961/bin/lava-test-runner /lava-12682961/0
11221 14:01:16.236779 + export TESTRUN_ID=0_sleep
11222 14:01:16.240218 + cd /lava-12682961/0/tests/0_sleep
11223 14:01:16.243742 + cat uuid
11224 14:01:16.249981 + UUID=12682961_1.<6>[ 22.059708] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11225 14:01:16.250096 5.2.3.1
11226 14:01:16.250193 + set +x
11227 14:01:16.256869 <LAVA_SIGNAL_STARTRUN 0_sleep 12682961_1.5.2.3.1>
11228 14:01:16.257189 Received signal: <STARTRUN> 0_sleep 12682961_1.5.2.3.1
11229 14:01:16.257304 Starting test lava.0_sleep (12682961_1.5.2.3.1)
11230 14:01:16.257426 Skipping test definition patterns.
11231 14:01:16.260215 + ./config/lava/sleep/sleep.sh mem
11232 14:01:16.263305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11233 14:01:16.263558 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11235 14:01:16.269800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11236 14:01:16.270088 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11238 14:01:16.273287 rtcwake: assuming RTC uses UTC ...
11239 14:01:16.280235 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:58:39 2024
11240 14:01:16.283557 <6>[ 22.096789] PM: suspend entry (deep)
11241 14:01:16.289955 <6>[ 22.100686] Filesystems sync: 0.000 seconds
11242 14:01:16.293298 <6>[ 22.106972] Freezing user space processes
11243 14:01:16.304554 <6>[ 22.112775] Freezing user space processes completed (elapsed 0.001 seconds)
11244 14:01:16.307587 <6>[ 22.120067] OOM killer disabled.
11245 14:01:16.310806 <6>[ 22.123557] Freezing remaining freezable tasks
11246 14:01:16.321272 <6>[ 22.129484] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11247 14:01:16.327850 <6>[ 22.137135] printk: Suspending console(s) (use no_console_suspend to debug)
11248 14:01:22.024214 <6>[ 22.280547] Disabling non-boot CPUs ...
11249 14:01:22.027844 <4>[ 22.281619] IRQ283: set affinity failed(-22).
11250 14:01:22.030769 <4>[ 22.281636] IRQ284: set affinity failed(-22).
11251 14:01:22.037712 <6>[ 22.282727] psci: CPU1 killed (polled 0 ms)
11252 14:01:22.040985 <4>[ 22.284459] IRQ283: set affinity failed(-22).
11253 14:01:22.047635 <4>[ 22.284472] IRQ284: set affinity failed(-22).
11254 14:01:22.050511 <6>[ 22.284661] psci: CPU2 killed (polled 4 ms)
11255 14:01:22.053968 <4>[ 22.285767] IRQ283: set affinity failed(-22).
11256 14:01:22.060931 <4>[ 22.285780] IRQ284: set affinity failed(-22).
11257 14:01:22.064489 <6>[ 22.286851] psci: CPU3 killed (polled 0 ms)
11258 14:01:22.067304 <4>[ 22.287484] IRQ283: set affinity failed(-22).
11259 14:01:22.074084 <4>[ 22.287487] IRQ284: set affinity failed(-22).
11260 14:01:22.077572 <6>[ 22.287539] psci: CPU4 killed (polled 0 ms)
11261 14:01:22.083868 <4>[ 22.288389] IRQ283: set affinity failed(-22).
11262 14:01:22.087337 <4>[ 22.288395] IRQ284: set affinity failed(-22).
11263 14:01:22.091185 <6>[ 22.288431] psci: CPU5 killed (polled 0 ms)
11264 14:01:22.097520 <6>[ 22.289367] psci: CPU6 killed (polled 0 ms)
11265 14:01:22.101004 <6>[ 22.290243] psci: CPU7 killed (polled 0 ms)
11266 14:01:22.103764 <6>[ 22.290870] Enabling non-boot CPUs ...
11267 14:01:22.107289 <6>[ 22.291116] Detected VIPT I-cache on CPU1
11268 14:01:22.117132 <6>[ 22.291211] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11269 14:01:22.124073 <6>[ 22.291276] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11270 14:01:22.124249 <6>[ 22.291929] CPU1 is up
11271 14:01:22.131029 <6>[ 22.292085] Detected VIPT I-cache on CPU2
11272 14:01:22.137054 <6>[ 22.292148] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11273 14:01:22.143710 <6>[ 22.292191] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11274 14:01:22.146856 <6>[ 22.292753] CPU2 is up
11275 14:01:22.150494 <6>[ 22.292904] Detected VIPT I-cache on CPU3
11276 14:01:22.156859 <6>[ 22.292967] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11277 14:01:22.163742 <6>[ 22.293009] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11278 14:01:22.166978 <6>[ 22.293561] CPU3 is up
11279 14:01:22.173589 <6>[ 22.293680] CPU features: detected: Hardware dirty bit management
11280 14:01:22.176763 <6>[ 22.293696] Detected PIPT I-cache on CPU4
11281 14:01:22.183507 <6>[ 22.293715] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11282 14:01:22.193935 <6>[ 22.293730] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11283 14:01:22.194105 <6>[ 22.294004] CPU4 is up
11284 14:01:22.200366 <6>[ 22.294131] Detected PIPT I-cache on CPU5
11285 14:01:22.207198 <6>[ 22.294152] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11286 14:01:22.213394 <6>[ 22.294166] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11287 14:01:22.216902 <6>[ 22.294383] CPU5 is up
11288 14:01:22.220507 <6>[ 22.294511] Detected PIPT I-cache on CPU6
11289 14:01:22.226936 <6>[ 22.294532] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11290 14:01:22.233312 <6>[ 22.294546] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11291 14:01:22.236964 <6>[ 22.294783] CPU6 is up
11292 14:01:22.240260 <6>[ 22.294909] Detected PIPT I-cache on CPU7
11293 14:01:22.246718 <6>[ 22.294936] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11294 14:01:22.253866 <6>[ 22.294950] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11295 14:01:22.256746 <6>[ 22.295193] CPU7 is up
11296 14:01:22.263569 <4>[ 22.434676] typec port0-partner: PM: parent port0 should not be sleeping
11297 14:01:22.267135 <6>[ 22.896228] OOM killer enabled.
11298 14:01:22.273575 <6>[ 22.899620] Restarting tasks ... done.
11299 14:01:22.276838 <5>[ 22.903998] random: crng reseeded on system resumption
11300 14:01:22.281169 <6>[ 22.911077] PM: suspend exit
11301 14:01:22.291421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11302 14:01:22.291748 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11304 14:01:22.294583 rtcwake: assuming RTC uses UTC ...
11305 14:01:22.301277 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:58:45 2024
11306 14:01:22.313868 <6>[ 22.940724] PM: suspend entry (deep)
11307 14:01:22.317425 <6>[ 22.944594] Filesystems sync: 0.000 seconds
11308 14:01:22.320396 <6>[ 22.949340] Freezing user space processes
11309 14:01:22.331661 <6>[ 22.954956] Freezing user space processes completed (elapsed 0.001 seconds)
11310 14:01:22.335264 <6>[ 22.962179] OOM killer disabled.
11311 14:01:22.338107 <6>[ 22.965660] Freezing remaining freezable tasks
11312 14:01:22.348040 <6>[ 22.971482] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11313 14:01:22.354919 <6>[ 22.979141] printk: Suspending console(s) (use no_console_suspend to debug)
11314 14:01:28.019178 <6>[ 23.051466] Disabling non-boot CPUs ...
11315 14:01:28.022251 <6>[ 23.052209] psci: CPU1 killed (polled 0 ms)
11316 14:01:28.025604 <6>[ 23.054110] psci: CPU2 killed (polled 0 ms)
11317 14:01:28.032353 <6>[ 23.055162] psci: CPU3 killed (polled 0 ms)
11318 14:01:28.035357 <6>[ 23.055730] psci: CPU4 killed (polled 0 ms)
11319 14:01:28.038863 <6>[ 23.056252] psci: CPU5 killed (polled 0 ms)
11320 14:01:28.045467 <6>[ 23.057861] psci: CPU6 killed (polled 0 ms)
11321 14:01:28.048985 <6>[ 23.058490] psci: CPU7 killed (polled 0 ms)
11322 14:01:28.052227 <6>[ 23.058859] Enabling non-boot CPUs ...
11323 14:01:28.059367 <6>[ 23.059061] Detected VIPT I-cache on CPU1
11324 14:01:28.065606 <6>[ 23.059131] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11325 14:01:28.072556 <6>[ 23.059181] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11326 14:01:28.076010 <6>[ 23.059716] CPU1 is up
11327 14:01:28.079172 <6>[ 23.059829] Detected VIPT I-cache on CPU2
11328 14:01:28.086007 <6>[ 23.059871] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11329 14:01:28.092395 <6>[ 23.059900] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11330 14:01:28.095811 <6>[ 23.060290] CPU2 is up
11331 14:01:28.099271 <6>[ 23.060398] Detected VIPT I-cache on CPU3
11332 14:01:28.105929 <6>[ 23.060440] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11333 14:01:28.112379 <6>[ 23.060469] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11334 14:01:28.116049 <6>[ 23.060885] CPU3 is up
11335 14:01:28.119238 <6>[ 23.060996] Detected PIPT I-cache on CPU4
11336 14:01:28.128885 <6>[ 23.061017] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11337 14:01:28.135891 <6>[ 23.061031] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11338 14:01:28.135985 <6>[ 23.061297] CPU4 is up
11339 14:01:28.142231 <6>[ 23.061413] Detected PIPT I-cache on CPU5
11340 14:01:28.148938 <6>[ 23.061435] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11341 14:01:28.155746 <6>[ 23.061449] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11342 14:01:28.158907 <6>[ 23.061668] CPU5 is up
11343 14:01:28.162647 <6>[ 23.061774] Detected PIPT I-cache on CPU6
11344 14:01:28.168928 <6>[ 23.061795] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11345 14:01:28.175742 <6>[ 23.061809] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11346 14:01:28.179240 <6>[ 23.062039] CPU6 is up
11347 14:01:28.182063 <6>[ 23.062145] Detected PIPT I-cache on CPU7
11348 14:01:28.192505 <6>[ 23.062172] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11349 14:01:28.198605 <6>[ 23.062186] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11350 14:01:28.198718 <6>[ 23.062420] CPU7 is up
11351 14:01:28.202028 <6>[ 23.600637] OOM killer enabled.
11352 14:01:28.208914 <6>[ 23.604027] Restarting tasks ... done.
11353 14:01:28.212293 <5>[ 23.608415] random: crng reseeded on system resumption
11354 14:01:28.215766 <6>[ 23.614708] PM: suspend exit
11355 14:01:28.225936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11356 14:01:28.226203 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11358 14:01:28.229119 rtcwake: assuming RTC uses UTC ...
11359 14:01:28.235136 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:58:51 2024
11360 14:01:28.247841 <6>[ 23.643285] PM: suspend entry (deep)
11361 14:01:28.251272 <6>[ 23.647153] Filesystems sync: 0.000 seconds
11362 14:01:28.254363 <6>[ 23.651880] Freezing user space processes
11363 14:01:28.265816 <6>[ 23.657506] Freezing user space processes completed (elapsed 0.001 seconds)
11364 14:01:28.268422 <6>[ 23.664725] OOM killer disabled.
11365 14:01:28.271680 <6>[ 23.668201] Freezing remaining freezable tasks
11366 14:01:28.282130 <6>[ 23.674121] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11367 14:01:28.288847 <6>[ 23.681792] printk: Suspending console(s) (use no_console_suspend to debug)
11368 14:01:34.030801 <6>[ 23.755324] Disabling non-boot CPUs ...
11369 14:01:34.033618 <6>[ 23.757165] psci: CPU1 killed (polled 4 ms)
11370 14:01:34.037165 <6>[ 23.758114] psci: CPU2 killed (polled 0 ms)
11371 14:01:34.043495 <6>[ 23.759924] psci: CPU3 killed (polled 0 ms)
11372 14:01:34.047034 <6>[ 23.760419] psci: CPU4 killed (polled 0 ms)
11373 14:01:34.050450 <6>[ 23.761016] psci: CPU5 killed (polled 0 ms)
11374 14:01:34.057223 <6>[ 23.761555] psci: CPU6 killed (polled 0 ms)
11375 14:01:34.060595 <6>[ 23.762089] psci: CPU7 killed (polled 0 ms)
11376 14:01:34.064058 <6>[ 23.762515] Enabling non-boot CPUs ...
11377 14:01:34.070175 <6>[ 23.762724] Detected VIPT I-cache on CPU1
11378 14:01:34.077209 <6>[ 23.762801] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11379 14:01:34.083465 <6>[ 23.762854] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11380 14:01:34.087003 <6>[ 23.763414] CPU1 is up
11381 14:01:34.090228 <6>[ 23.763534] Detected VIPT I-cache on CPU2
11382 14:01:34.097293 <6>[ 23.763580] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11383 14:01:34.103809 <6>[ 23.763612] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11384 14:01:34.106836 <6>[ 23.764048] CPU2 is up
11385 14:01:34.110214 <6>[ 23.764167] Detected VIPT I-cache on CPU3
11386 14:01:34.117033 <6>[ 23.764213] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11387 14:01:34.123687 <6>[ 23.764243] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11388 14:01:34.127318 <6>[ 23.764692] CPU3 is up
11389 14:01:34.130441 <6>[ 23.764808] Detected PIPT I-cache on CPU4
11390 14:01:34.140255 <6>[ 23.764831] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11391 14:01:34.147377 <6>[ 23.764846] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11392 14:01:34.147488 <6>[ 23.765130] CPU4 is up
11393 14:01:34.153651 <6>[ 23.765252] Detected PIPT I-cache on CPU5
11394 14:01:34.160516 <6>[ 23.765275] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11395 14:01:34.166696 <6>[ 23.765290] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11396 14:01:34.170180 <6>[ 23.765519] CPU5 is up
11397 14:01:34.173630 <6>[ 23.765633] Detected PIPT I-cache on CPU6
11398 14:01:34.179986 <6>[ 23.765656] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11399 14:01:34.186859 <6>[ 23.765671] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11400 14:01:34.190348 <6>[ 23.765919] CPU6 is up
11401 14:01:34.193846 <6>[ 23.766031] Detected PIPT I-cache on CPU7
11402 14:01:34.203364 <6>[ 23.766055] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11403 14:01:34.210049 <6>[ 23.766070] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11404 14:01:34.210173 <6>[ 23.766326] CPU7 is up
11405 14:01:34.213182 <6>[ 24.316595] OOM killer enabled.
11406 14:01:34.220653 <6>[ 24.319985] Restarting tasks ... done.
11407 14:01:34.223969 <5>[ 24.324357] random: crng reseeded on system resumption
11408 14:01:34.227245 <6>[ 24.330673] PM: suspend exit
11409 14:01:34.237658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11410 14:01:34.237944 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11412 14:01:34.241345 rtcwake: assuming RTC uses UTC ...
11413 14:01:34.247800 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:58:57 2024
11414 14:01:34.260222 <6>[ 24.360348] PM: suspend entry (deep)
11415 14:01:34.263580 <6>[ 24.364213] Filesystems sync: 0.000 seconds
11416 14:01:34.267190 <6>[ 24.368969] Freezing user space processes
11417 14:01:34.278090 <6>[ 24.374646] Freezing user space processes completed (elapsed 0.001 seconds)
11418 14:01:34.281415 <6>[ 24.381880] OOM killer disabled.
11419 14:01:34.284876 <6>[ 24.385365] Freezing remaining freezable tasks
11420 14:01:34.294862 <6>[ 24.391298] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11421 14:01:34.301214 <6>[ 24.398970] printk: Suspending console(s) (use no_console_suspend to debug)
11422 14:01:40.015410 <6>[ 24.472968] Disabling non-boot CPUs ...
11423 14:01:40.018731 <6>[ 24.474834] psci: CPU1 killed (polled 0 ms)
11424 14:01:40.021786 <6>[ 24.476532] psci: CPU2 killed (polled 4 ms)
11425 14:01:40.028664 <6>[ 24.478392] psci: CPU3 killed (polled 0 ms)
11426 14:01:40.031882 <6>[ 24.478844] psci: CPU4 killed (polled 0 ms)
11427 14:01:40.035201 <6>[ 24.479400] psci: CPU5 killed (polled 0 ms)
11428 14:01:40.042049 <6>[ 24.479942] psci: CPU6 killed (polled 0 ms)
11429 14:01:40.045628 <6>[ 24.480470] psci: CPU7 killed (polled 0 ms)
11430 14:01:40.048999 <6>[ 24.480871] Enabling non-boot CPUs ...
11431 14:01:40.052481 <6>[ 24.481081] Detected VIPT I-cache on CPU1
11432 14:01:40.062218 <6>[ 24.481157] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11433 14:01:40.068603 <6>[ 24.481211] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11434 14:01:40.071895 <6>[ 24.481786] CPU1 is up
11435 14:01:40.074964 <6>[ 24.481905] Detected VIPT I-cache on CPU2
11436 14:01:40.082092 <6>[ 24.481951] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11437 14:01:40.088716 <6>[ 24.481983] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11438 14:01:40.091629 <6>[ 24.482414] CPU2 is up
11439 14:01:40.095126 <6>[ 24.482533] Detected VIPT I-cache on CPU3
11440 14:01:40.101962 <6>[ 24.482579] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11441 14:01:40.108777 <6>[ 24.482610] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11442 14:01:40.111922 <6>[ 24.483037] CPU3 is up
11443 14:01:40.115371 <6>[ 24.483154] Detected PIPT I-cache on CPU4
11444 14:01:40.124850 <6>[ 24.483176] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11445 14:01:40.131940 <6>[ 24.483191] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11446 14:01:40.132055 <6>[ 24.483475] CPU4 is up
11447 14:01:40.138281 <6>[ 24.483598] Detected PIPT I-cache on CPU5
11448 14:01:40.144987 <6>[ 24.483620] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11449 14:01:40.151564 <6>[ 24.483635] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11450 14:01:40.155129 <6>[ 24.483870] CPU5 is up
11451 14:01:40.158543 <6>[ 24.483982] Detected PIPT I-cache on CPU6
11452 14:01:40.164874 <6>[ 24.484006] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11453 14:01:40.171954 <6>[ 24.484020] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11454 14:01:40.174834 <6>[ 24.484264] CPU6 is up
11455 14:01:40.178194 <6>[ 24.484377] Detected PIPT I-cache on CPU7
11456 14:01:40.188375 <6>[ 24.484401] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11457 14:01:40.195423 <6>[ 24.484416] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11458 14:01:40.195498 <6>[ 24.484695] CPU7 is up
11459 14:01:40.198565 <6>[ 25.020551] OOM killer enabled.
11460 14:01:40.204883 <6>[ 25.023941] Restarting tasks ... done.
11461 14:01:40.208241 <5>[ 25.028331] random: crng reseeded on system resumption
11462 14:01:40.212268 <6>[ 25.034601] PM: suspend exit
11463 14:01:40.222204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11464 14:01:40.222516 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11466 14:01:40.225328 rtcwake: assuming RTC uses UTC ...
11467 14:01:40.232020 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:59:03 2024
11468 14:01:40.243888 <6>[ 25.063378] PM: suspend entry (deep)
11469 14:01:40.247262 <6>[ 25.067245] Filesystems sync: 0.000 seconds
11470 14:01:40.250561 <6>[ 25.071975] Freezing user space processes
11471 14:01:40.261960 <6>[ 25.077625] Freezing user space processes completed (elapsed 0.001 seconds)
11472 14:01:40.264884 <6>[ 25.084868] OOM killer disabled.
11473 14:01:40.268161 <6>[ 25.088344] Freezing remaining freezable tasks
11474 14:01:40.278527 <6>[ 25.094260] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11475 14:01:40.284905 <6>[ 25.101922] printk: Suspending console(s) (use no_console_suspend to debug)
11476 14:01:46.019499 <6>[ 25.176681] Disabling non-boot CPUs ...
11477 14:01:46.022968 <6>[ 25.177664] psci: CPU1 killed (polled 0 ms)
11478 14:01:46.026217 <6>[ 25.179718] psci: CPU2 killed (polled 0 ms)
11479 14:01:46.032994 <6>[ 25.181668] psci: CPU3 killed (polled 0 ms)
11480 14:01:46.036077 <6>[ 25.182171] psci: CPU4 killed (polled 0 ms)
11481 14:01:46.039174 <6>[ 25.182772] psci: CPU5 killed (polled 0 ms)
11482 14:01:46.046067 <6>[ 25.183329] psci: CPU6 killed (polled 0 ms)
11483 14:01:46.049586 <6>[ 25.183839] psci: CPU7 killed (polled 0 ms)
11484 14:01:46.052462 <6>[ 25.184274] Enabling non-boot CPUs ...
11485 14:01:46.059457 <6>[ 25.184500] Detected VIPT I-cache on CPU1
11486 14:01:46.066266 <6>[ 25.184585] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11487 14:01:46.072774 <6>[ 25.184644] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11488 14:01:46.075934 <6>[ 25.185293] CPU1 is up
11489 14:01:46.079666 <6>[ 25.185435] Detected VIPT I-cache on CPU2
11490 14:01:46.086412 <6>[ 25.185489] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11491 14:01:46.092744 <6>[ 25.185526] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11492 14:01:46.096122 <6>[ 25.186046] CPU2 is up
11493 14:01:46.099512 <6>[ 25.186179] Detected VIPT I-cache on CPU3
11494 14:01:46.106264 <6>[ 25.186233] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11495 14:01:46.112618 <6>[ 25.186270] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11496 14:01:46.116162 <6>[ 25.186781] CPU3 is up
11497 14:01:46.119695 <6>[ 25.186905] Detected PIPT I-cache on CPU4
11498 14:01:46.129585 <6>[ 25.186925] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11499 14:01:46.135836 <6>[ 25.186938] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11500 14:01:46.135920 <6>[ 25.187199] CPU4 is up
11501 14:01:46.142498 <6>[ 25.187317] Detected PIPT I-cache on CPU5
11502 14:01:46.149456 <6>[ 25.187338] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11503 14:01:46.155733 <6>[ 25.187351] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11504 14:01:46.159247 <6>[ 25.187563] CPU5 is up
11505 14:01:46.162700 <6>[ 25.187680] Detected PIPT I-cache on CPU6
11506 14:01:46.169500 <6>[ 25.187700] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11507 14:01:46.175829 <6>[ 25.187713] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11508 14:01:46.179315 <6>[ 25.187936] CPU6 is up
11509 14:01:46.182331 <6>[ 25.188055] Detected PIPT I-cache on CPU7
11510 14:01:46.192738 <6>[ 25.188075] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11511 14:01:46.199260 <6>[ 25.188088] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11512 14:01:46.199367 <6>[ 25.188327] CPU7 is up
11513 14:01:46.202564 <6>[ 25.728786] OOM killer enabled.
11514 14:01:46.208919 <6>[ 25.732176] Restarting tasks ... done.
11515 14:01:46.212674 <5>[ 25.736534] random: crng reseeded on system resumption
11516 14:01:46.217045 <6>[ 25.743670] PM: suspend exit
11517 14:01:46.227677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11518 14:01:46.227947 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11520 14:01:46.231207 rtcwake: assuming RTC uses UTC ...
11521 14:01:46.237314 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:59:09 2024
11522 14:01:46.250194 <6>[ 25.773453] PM: suspend entry (deep)
11523 14:01:46.253510 <6>[ 25.777319] Filesystems sync: 0.000 seconds
11524 14:01:46.256393 <6>[ 25.782055] Freezing user space processes
11525 14:01:46.267447 <6>[ 25.787749] Freezing user space processes completed (elapsed 0.001 seconds)
11526 14:01:46.270932 <6>[ 25.794976] OOM killer disabled.
11527 14:01:46.274484 <6>[ 25.798456] Freezing remaining freezable tasks
11528 14:01:46.284151 <6>[ 25.804443] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11529 14:01:46.290882 <6>[ 25.812103] printk: Suspending console(s) (use no_console_suspend to debug)
11530 14:01:52.015775 <6>[ 25.896183] Disabling non-boot CPUs ...
11531 14:01:52.019224 <6>[ 25.897038] psci: CPU1 killed (polled 0 ms)
11532 14:01:52.022006 <6>[ 25.898928] psci: CPU2 killed (polled 0 ms)
11533 14:01:52.028877 <6>[ 25.900444] psci: CPU3 killed (polled 4 ms)
11534 14:01:52.032280 <6>[ 25.901012] psci: CPU4 killed (polled 0 ms)
11535 14:01:52.035384 <6>[ 25.901619] psci: CPU5 killed (polled 0 ms)
11536 14:01:52.041849 <6>[ 25.902206] psci: CPU6 killed (polled 0 ms)
11537 14:01:52.045523 <6>[ 25.902715] psci: CPU7 killed (polled 0 ms)
11538 14:01:52.048580 <6>[ 25.902999] Enabling non-boot CPUs ...
11539 14:01:52.055675 <6>[ 25.903207] Detected VIPT I-cache on CPU1
11540 14:01:52.062029 <6>[ 25.903283] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11541 14:01:52.068729 <6>[ 25.903337] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11542 14:01:52.071870 <6>[ 25.903907] CPU1 is up
11543 14:01:52.075343 <6>[ 25.904030] Detected VIPT I-cache on CPU2
11544 14:01:52.082110 <6>[ 25.904076] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11545 14:01:52.089003 <6>[ 25.904108] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11546 14:01:52.092232 <6>[ 25.904558] CPU2 is up
11547 14:01:52.095010 <6>[ 25.904676] Detected VIPT I-cache on CPU3
11548 14:01:52.101976 <6>[ 25.904722] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11549 14:01:52.108597 <6>[ 25.904753] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11550 14:01:52.112097 <6>[ 25.905181] CPU3 is up
11551 14:01:52.115575 <6>[ 25.905296] Detected PIPT I-cache on CPU4
11552 14:01:52.125062 <6>[ 25.905318] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11553 14:01:52.132015 <6>[ 25.905333] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11554 14:01:52.132123 <6>[ 25.905613] CPU4 is up
11555 14:01:52.138675 <6>[ 25.905726] Detected PIPT I-cache on CPU5
11556 14:01:52.145627 <6>[ 25.905749] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11557 14:01:52.152154 <6>[ 25.905764] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11558 14:01:52.155759 <6>[ 25.905995] CPU5 is up
11559 14:01:52.158816 <6>[ 25.906107] Detected PIPT I-cache on CPU6
11560 14:01:52.165582 <6>[ 25.906130] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11561 14:01:52.172324 <6>[ 25.906144] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11562 14:01:52.175596 <6>[ 25.906389] CPU6 is up
11563 14:01:52.178986 <6>[ 25.906499] Detected PIPT I-cache on CPU7
11564 14:01:52.185101 <6>[ 25.906522] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11565 14:01:52.192231 <6>[ 25.906536] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11566 14:01:52.195555 <6>[ 25.906788] CPU7 is up
11567 14:01:52.198886 <6>[ 26.444495] OOM killer enabled.
11568 14:01:52.205400 <6>[ 26.447885] Restarting tasks ... done.
11569 14:01:52.208603 <5>[ 26.452251] random: crng reseeded on system resumption
11570 14:01:52.211959 <6>[ 26.458618] PM: suspend exit
11571 14:01:52.222701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11572 14:01:52.222962 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11574 14:01:52.226100 rtcwake: assuming RTC uses UTC ...
11575 14:01:52.232385 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:59:15 2024
11576 14:01:52.245180 <6>[ 26.488535] PM: suspend entry (deep)
11577 14:01:52.248596 <6>[ 26.492406] Filesystems sync: 0.000 seconds
11578 14:01:52.252173 <6>[ 26.497136] Freezing user space processes
11579 14:01:52.263333 <6>[ 26.502812] Freezing user space processes completed (elapsed 0.001 seconds)
11580 14:01:52.266405 <6>[ 26.510038] OOM killer disabled.
11581 14:01:52.269365 <6>[ 26.513545] Freezing remaining freezable tasks
11582 14:01:52.279716 <6>[ 26.519466] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11583 14:01:52.286512 <6>[ 26.527135] printk: Suspending console(s) (use no_console_suspend to debug)
11584 14:01:58.016372 <6>[ 26.602009] Disabling non-boot CPUs ...
11585 14:01:58.019763 <6>[ 26.603064] psci: CPU1 killed (polled 0 ms)
11586 14:01:58.023139 <6>[ 26.604418] psci: CPU2 killed (polled 0 ms)
11587 14:01:58.029824 <6>[ 26.606562] psci: CPU3 killed (polled 0 ms)
11588 14:01:58.033338 <6>[ 26.607081] psci: CPU4 killed (polled 0 ms)
11589 14:01:58.037152 <6>[ 26.607751] psci: CPU5 killed (polled 0 ms)
11590 14:01:58.043672 <6>[ 26.608354] psci: CPU6 killed (polled 0 ms)
11591 14:01:58.046620 <6>[ 26.609018] psci: CPU7 killed (polled 0 ms)
11592 14:01:58.049870 <6>[ 26.609432] Enabling non-boot CPUs ...
11593 14:01:58.056578 <6>[ 26.609678] Detected VIPT I-cache on CPU1
11594 14:01:58.063482 <6>[ 26.609772] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11595 14:01:58.069849 <6>[ 26.609837] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11596 14:01:58.073155 <6>[ 26.610582] CPU1 is up
11597 14:01:58.076549 <6>[ 26.610735] Detected VIPT I-cache on CPU2
11598 14:01:58.083541 <6>[ 26.610799] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11599 14:01:58.090124 <6>[ 26.610841] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11600 14:01:58.093578 <6>[ 26.611434] CPU2 is up
11601 14:01:58.096962 <6>[ 26.611587] Detected VIPT I-cache on CPU3
11602 14:01:58.102982 <6>[ 26.611650] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11603 14:01:58.109963 <6>[ 26.611692] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11604 14:01:58.113393 <6>[ 26.612278] CPU3 is up
11605 14:01:58.116702 <6>[ 26.612470] Detected PIPT I-cache on CPU4
11606 14:01:58.126393 <6>[ 26.612492] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11607 14:01:58.133242 <6>[ 26.612506] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11608 14:01:58.133322 <6>[ 26.612785] CPU4 is up
11609 14:01:58.139556 <6>[ 26.612914] Detected PIPT I-cache on CPU5
11610 14:01:58.146515 <6>[ 26.612936] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11611 14:01:58.153496 <6>[ 26.612950] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11612 14:01:58.156163 <6>[ 26.613186] CPU5 is up
11613 14:01:58.159566 <6>[ 26.613314] Detected PIPT I-cache on CPU6
11614 14:01:58.166825 <6>[ 26.613337] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11615 14:01:58.173082 <6>[ 26.613351] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11616 14:01:58.176629 <6>[ 26.613593] CPU6 is up
11617 14:01:58.179951 <6>[ 26.613722] Detected PIPT I-cache on CPU7
11618 14:01:58.189755 <6>[ 26.613744] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11619 14:01:58.196410 <6>[ 26.613758] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11620 14:01:58.196503 <6>[ 26.614015] CPU7 is up
11621 14:01:58.199675 <6>[ 27.152891] OOM killer enabled.
11622 14:01:58.206175 <6>[ 27.156281] Restarting tasks ... done.
11623 14:01:58.209962 <5>[ 27.160670] random: crng reseeded on system resumption
11624 14:01:58.213449 <6>[ 27.167036] PM: suspend exit
11625 14:01:58.224148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11626 14:01:58.224443 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11628 14:01:58.227341 rtcwake: assuming RTC uses UTC ...
11629 14:01:58.233649 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:59:21 2024
11630 14:01:58.245972 <6>[ 27.196420] PM: suspend entry (deep)
11631 14:01:58.249436 <6>[ 27.200274] Filesystems sync: 0.000 seconds
11632 14:01:58.252921 <6>[ 27.205034] Freezing user space processes
11633 14:01:58.263731 <6>[ 27.210699] Freezing user space processes completed (elapsed 0.001 seconds)
11634 14:01:58.267196 <6>[ 27.217925] OOM killer disabled.
11635 14:01:58.270603 <6>[ 27.221409] Freezing remaining freezable tasks
11636 14:01:58.280238 <6>[ 27.227338] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11637 14:01:58.287001 <6>[ 27.235008] printk: Suspending console(s) (use no_console_suspend to debug)
11638 14:02:04.019768 <6>[ 27.308295] Disabling non-boot CPUs ...
11639 14:02:04.023346 <4>[ 27.309350] migrate_one_irq: 88 callbacks suppressed
11640 14:02:04.029879 <4>[ 27.309363] IRQ283: set affinity failed(-22).
11641 14:02:04.033233 <4>[ 27.309373] IRQ284: set affinity failed(-22).
11642 14:02:04.036333 <6>[ 27.310454] psci: CPU1 killed (polled 0 ms)
11643 14:02:04.043291 <4>[ 27.311585] IRQ283: set affinity failed(-22).
11644 14:02:04.046120 <4>[ 27.311595] IRQ284: set affinity failed(-22).
11645 14:02:04.053367 <6>[ 27.312363] psci: CPU2 killed (polled 4 ms)
11646 14:02:04.056133 <4>[ 27.313301] IRQ283: set affinity failed(-22).
11647 14:02:04.059868 <4>[ 27.313312] IRQ284: set affinity failed(-22).
11648 14:02:04.066086 <6>[ 27.314376] psci: CPU3 killed (polled 0 ms)
11649 14:02:04.069786 <4>[ 27.314842] IRQ283: set affinity failed(-22).
11650 14:02:04.073027 <4>[ 27.314846] IRQ284: set affinity failed(-22).
11651 14:02:04.079316 <6>[ 27.314875] psci: CPU4 killed (polled 0 ms)
11652 14:02:04.083098 <4>[ 27.315461] IRQ283: set affinity failed(-22).
11653 14:02:04.089632 <4>[ 27.315466] IRQ284: set affinity failed(-22).
11654 14:02:04.093132 <6>[ 27.315501] psci: CPU5 killed (polled 0 ms)
11655 14:02:04.096566 <6>[ 27.316077] psci: CPU6 killed (polled 0 ms)
11656 14:02:04.099299 <6>[ 27.316710] psci: CPU7 killed (polled 0 ms)
11657 14:02:04.106175 <6>[ 27.317049] Enabling non-boot CPUs ...
11658 14:02:04.109800 <6>[ 27.317279] Detected VIPT I-cache on CPU1
11659 14:02:04.116366 <6>[ 27.317365] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11660 14:02:04.123289 <6>[ 27.317425] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11661 14:02:04.126477 <6>[ 27.318089] CPU1 is up
11662 14:02:04.129891 <6>[ 27.318226] Detected VIPT I-cache on CPU2
11663 14:02:04.136230 <6>[ 27.318282] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11664 14:02:04.143336 <6>[ 27.318320] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11665 14:02:04.146726 <6>[ 27.318840] CPU2 is up
11666 14:02:04.153366 <6>[ 27.318978] Detected VIPT I-cache on CPU3
11667 14:02:04.159574 <6>[ 27.319034] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11668 14:02:04.166621 <6>[ 27.319070] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11669 14:02:04.170142 <6>[ 27.319592] CPU3 is up
11670 14:02:04.172956 <6>[ 27.319716] Detected PIPT I-cache on CPU4
11671 14:02:04.180072 <6>[ 27.319738] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11672 14:02:04.186851 <6>[ 27.319753] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11673 14:02:04.189709 <6>[ 27.320048] CPU4 is up
11674 14:02:04.193228 <6>[ 27.320183] Detected PIPT I-cache on CPU5
11675 14:02:04.200116 <6>[ 27.320206] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11676 14:02:04.206545 <6>[ 27.320221] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11677 14:02:04.209931 <6>[ 27.320488] CPU5 is up
11678 14:02:04.213174 <6>[ 27.320612] Detected PIPT I-cache on CPU6
11679 14:02:04.223501 <6>[ 27.320635] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11680 14:02:04.229865 <6>[ 27.320650] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11681 14:02:04.229960 <6>[ 27.320912] CPU6 is up
11682 14:02:04.236318 <6>[ 27.321036] Detected PIPT I-cache on CPU7
11683 14:02:04.243322 <6>[ 27.321059] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11684 14:02:04.250031 <6>[ 27.321074] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11685 14:02:04.253013 <6>[ 27.321335] CPU7 is up
11686 14:02:04.256754 <6>[ 27.915741] OOM killer enabled.
11687 14:02:04.259579 <6>[ 27.919133] Restarting tasks ... done.
11688 14:02:04.266607 <5>[ 27.923509] random: crng reseeded on system resumption
11689 14:02:04.269398 <6>[ 27.930009] PM: suspend exit
11690 14:02:04.278192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11691 14:02:04.278507 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11693 14:02:04.281894 rtcwake: assuming RTC uses UTC ...
11694 14:02:04.288009 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:59:27 2024
11695 14:02:04.301352 <6>[ 27.959826] PM: suspend entry (deep)
11696 14:02:04.304245 <6>[ 27.963736] Filesystems sync: 0.000 seconds
11697 14:02:04.307869 <6>[ 27.968510] Freezing user space processes
11698 14:02:04.318761 <6>[ 27.974169] Freezing user space processes completed (elapsed 0.001 seconds)
11699 14:02:04.322244 <6>[ 27.981400] OOM killer disabled.
11700 14:02:04.325098 <6>[ 27.984882] Freezing remaining freezable tasks
11701 14:02:04.335448 <6>[ 27.990793] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11702 14:02:04.342207 <6>[ 27.998458] printk: Suspending console(s) (use no_console_suspend to debug)
11703 14:02:10.027181 <6>[ 28.094353] Disabling non-boot CPUs ...
11704 14:02:10.030616 <6>[ 28.095956] psci: CPU1 killed (polled 0 ms)
11705 14:02:10.033291 <6>[ 28.097569] psci: CPU2 killed (polled 0 ms)
11706 14:02:10.040206 <6>[ 28.099119] psci: CPU3 killed (polled 0 ms)
11707 14:02:10.043645 <6>[ 28.100313] psci: CPU4 killed (polled 4 ms)
11708 14:02:10.047294 <6>[ 28.101776] psci: CPU5 killed (polled 0 ms)
11709 14:02:10.053337 <6>[ 28.103276] psci: CPU6 killed (polled 0 ms)
11710 14:02:10.056668 <6>[ 28.104306] psci: CPU7 killed (polled 4 ms)
11711 14:02:10.060022 <6>[ 28.104511] Enabling non-boot CPUs ...
11712 14:02:10.066820 <6>[ 28.104676] Detected VIPT I-cache on CPU1
11713 14:02:10.073852 <6>[ 28.104731] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11714 14:02:10.080189 <6>[ 28.104771] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11715 14:02:10.083571 <6>[ 28.105161] CPU1 is up
11716 14:02:10.086955 <6>[ 28.105241] Detected VIPT I-cache on CPU2
11717 14:02:10.094033 <6>[ 28.105267] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11718 14:02:10.100470 <6>[ 28.105285] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11719 14:02:10.103565 <6>[ 28.105529] CPU2 is up
11720 14:02:10.106880 <6>[ 28.105608] Detected VIPT I-cache on CPU3
11721 14:02:10.113542 <6>[ 28.105634] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11722 14:02:10.120238 <6>[ 28.105652] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11723 14:02:10.123749 <6>[ 28.105893] CPU3 is up
11724 14:02:10.126854 <6>[ 28.105985] Detected PIPT I-cache on CPU4
11725 14:02:10.136844 <6>[ 28.106006] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11726 14:02:10.143629 <6>[ 28.106019] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11727 14:02:10.143748 <6>[ 28.106271] CPU4 is up
11728 14:02:10.150496 <6>[ 28.106366] Detected PIPT I-cache on CPU5
11729 14:02:10.156670 <6>[ 28.106387] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11730 14:02:10.163562 <6>[ 28.106400] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11731 14:02:10.166930 <6>[ 28.106603] CPU5 is up
11732 14:02:10.170408 <6>[ 28.106694] Detected PIPT I-cache on CPU6
11733 14:02:10.177109 <6>[ 28.106714] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11734 14:02:10.183610 <6>[ 28.106727] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11735 14:02:10.187039 <6>[ 28.106945] CPU6 is up
11736 14:02:10.190276 <6>[ 28.107035] Detected PIPT I-cache on CPU7
11737 14:02:10.197078 <6>[ 28.107055] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11738 14:02:10.206570 <6>[ 28.107068] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11739 14:02:10.206659 <6>[ 28.107291] CPU7 is up
11740 14:02:10.210489 <6>[ 28.660004] OOM killer enabled.
11741 14:02:10.217187 <6>[ 28.663396] Restarting tasks ... done.
11742 14:02:10.219824 <5>[ 28.667791] random: crng reseeded on system resumption
11743 14:02:10.223904 <6>[ 28.674366] PM: suspend exit
11744 14:02:10.234497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11745 14:02:10.234766 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11747 14:02:10.237480 rtcwake: assuming RTC uses UTC ...
11748 14:02:10.244596 rtcwake: wakeup from "mem" using rtc0 at Thu Feb 1 13:59:33 2024
11749 14:02:10.256283 <6>[ 28.703726] PM: suspend entry (deep)
11750 14:02:10.259682 <6>[ 28.707592] Filesystems sync: 0.000 seconds
11751 14:02:10.263100 <6>[ 28.712375] Freezing user space processes
11752 14:02:10.274390 <6>[ 28.718066] Freezing user space processes completed (elapsed 0.001 seconds)
11753 14:02:10.277780 <6>[ 28.725296] OOM killer disabled.
11754 14:02:10.281281 <6>[ 28.728783] Freezing remaining freezable tasks
11755 14:02:10.291311 <6>[ 28.734714] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11756 14:02:10.297943 <6>[ 28.742376] printk: Suspending console(s) (use no_console_suspend to debug)
11757 14:02:16.015375 <6>[ 28.833449] Disabling non-boot CPUs ...
11758 14:02:16.018208 <6>[ 28.834453] psci: CPU1 killed (polled 0 ms)
11759 14:02:16.021658 <6>[ 28.835507] psci: CPU2 killed (polled 0 ms)
11760 14:02:16.028233 <6>[ 28.837519] psci: CPU3 killed (polled 0 ms)
11761 14:02:16.031968 <6>[ 28.838026] psci: CPU4 killed (polled 0 ms)
11762 14:02:16.034937 <6>[ 28.838632] psci: CPU5 killed (polled 0 ms)
11763 14:02:16.041849 <6>[ 28.839208] psci: CPU6 killed (polled 0 ms)
11764 14:02:16.045290 <6>[ 28.839796] psci: CPU7 killed (polled 0 ms)
11765 14:02:16.048779 <6>[ 28.840125] Enabling non-boot CPUs ...
11766 14:02:16.054889 <6>[ 28.840436] Detected VIPT I-cache on CPU1
11767 14:02:16.061901 <6>[ 28.840521] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11768 14:02:16.068812 <6>[ 28.840579] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11769 14:02:16.072014 <6>[ 28.841236] CPU1 is up
11770 14:02:16.075147 <6>[ 28.841380] Detected VIPT I-cache on CPU2
11771 14:02:16.081464 <6>[ 28.841435] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11772 14:02:16.088206 <6>[ 28.841473] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11773 14:02:16.091635 <6>[ 28.841997] CPU2 is up
11774 14:02:16.094951 <6>[ 28.842132] Detected VIPT I-cache on CPU3
11775 14:02:16.101748 <6>[ 28.842187] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11776 14:02:16.108083 <6>[ 28.842224] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11777 14:02:16.111517 <6>[ 28.842748] CPU3 is up
11778 14:02:16.117987 <6>[ 28.842872] Detected PIPT I-cache on CPU4
11779 14:02:16.124933 <6>[ 28.842894] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11780 14:02:16.131537 <6>[ 28.842909] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11781 14:02:16.135060 <6>[ 28.843182] CPU4 is up
11782 14:02:16.138470 <6>[ 28.843304] Detected PIPT I-cache on CPU5
11783 14:02:16.144648 <6>[ 28.843326] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11784 14:02:16.151098 <6>[ 28.843340] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11785 14:02:16.154779 <6>[ 28.843565] CPU5 is up
11786 14:02:16.158284 <6>[ 28.843685] Detected PIPT I-cache on CPU6
11787 14:02:16.164577 <6>[ 28.843708] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11788 14:02:16.171355 <6>[ 28.843722] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11789 14:02:16.174620 <6>[ 28.843963] CPU6 is up
11790 14:02:16.177898 <6>[ 28.844090] Detected PIPT I-cache on CPU7
11791 14:02:16.187630 <6>[ 28.844112] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11792 14:02:16.194225 <6>[ 28.844126] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11793 14:02:16.194310 <6>[ 28.844382] CPU7 is up
11794 14:02:16.201227 <6>[ 29.384692] OOM killer enabled.
11795 14:02:16.204624 <6>[ 29.388082] Restarting tasks ... done.
11796 14:02:16.208120 <5>[ 29.392468] random: crng reseeded on system resumption
11797 14:02:16.211641 <6>[ 29.398704] PM: suspend exit
11798 14:02:16.222571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11799 14:02:16.222687 + set +x
11800 14:02:16.222954 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11802 14:02:16.229223 <LAVA_SIGNAL_ENDRUN 0_sleep 12682961_1.5.2.3.1>
11803 14:02:16.229306 <LAVA_TEST_RUNNER EXIT>
11804 14:02:16.229562 Received signal: <ENDRUN> 0_sleep 12682961_1.5.2.3.1
11805 14:02:16.229650 Ending use of test pattern.
11806 14:02:16.229724 Ending test lava.0_sleep (12682961_1.5.2.3.1), duration 59.97
11808 14:02:16.229990 ok: lava_test_shell seems to have completed
11809 14:02:16.230236 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11810 14:02:16.230366 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11811 14:02:16.230462 end: 3 lava-test-retry (duration 00:01:00) [common]
11812 14:02:16.230564 start: 4 finalize (timeout 00:06:28) [common]
11813 14:02:16.230673 start: 4.1 power-off (timeout 00:00:30) [common]
11814 14:02:16.230859 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11815 14:02:16.306997 >> Command sent successfully.
11816 14:02:16.309435 Returned 0 in 0 seconds
11817 14:02:16.409857 end: 4.1 power-off (duration 00:00:00) [common]
11819 14:02:16.410186 start: 4.2 read-feedback (timeout 00:06:28) [common]
11820 14:02:16.410458 Listened to connection for namespace 'common' for up to 1s
11821 14:02:17.411380 Finalising connection for namespace 'common'
11822 14:02:17.411560 Disconnecting from shell: Finalise
11823 14:02:17.411640 / #
11824 14:02:17.511952 end: 4.2 read-feedback (duration 00:00:01) [common]
11825 14:02:17.512106 end: 4 finalize (duration 00:00:01) [common]
11826 14:02:17.512227 Cleaning after the job
11827 14:02:17.512392 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/ramdisk
11828 14:02:17.525878 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/kernel
11829 14:02:17.550476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/dtb
11830 14:02:17.550731 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12682961/tftp-deploy-w8a_okmr/modules
11831 14:02:17.557937 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12682961
11832 14:02:17.734934 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12682961
11833 14:02:17.735113 Job finished correctly