Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 16
- Kernel Errors: 27
1 06:47:02.713877 lava-dispatcher, installed at version: 2023.10
2 06:47:02.714080 start: 0 validate
3 06:47:02.714207 Start time: 2024-02-03 06:47:02.714200+00:00 (UTC)
4 06:47:02.714317 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:47:02.714446 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:47:02.982321 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:47:02.982486 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:47:32.998848 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:47:32.999072 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:47:33.267310 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:47:33.268093 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.75-cip14%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:47:36.035022 validate duration: 33.32
14 06:47:36.035283 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:47:36.035407 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:47:36.035522 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:47:36.035642 Not decompressing ramdisk as can be used compressed.
18 06:47:36.035727 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 06:47:36.035791 saving as /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/ramdisk/rootfs.cpio.gz
20 06:47:36.035853 total size: 8181372 (7 MB)
21 06:47:36.302230 progress 0 % (0 MB)
22 06:47:36.304604 progress 5 % (0 MB)
23 06:47:36.306768 progress 10 % (0 MB)
24 06:47:36.309065 progress 15 % (1 MB)
25 06:47:36.311184 progress 20 % (1 MB)
26 06:47:36.313488 progress 25 % (1 MB)
27 06:47:36.315626 progress 30 % (2 MB)
28 06:47:36.317932 progress 35 % (2 MB)
29 06:47:36.320030 progress 40 % (3 MB)
30 06:47:36.322377 progress 45 % (3 MB)
31 06:47:36.324536 progress 50 % (3 MB)
32 06:47:36.326840 progress 55 % (4 MB)
33 06:47:36.328965 progress 60 % (4 MB)
34 06:47:36.331184 progress 65 % (5 MB)
35 06:47:36.333274 progress 70 % (5 MB)
36 06:47:36.335533 progress 75 % (5 MB)
37 06:47:36.337634 progress 80 % (6 MB)
38 06:47:36.340085 progress 85 % (6 MB)
39 06:47:36.342130 progress 90 % (7 MB)
40 06:47:36.344340 progress 95 % (7 MB)
41 06:47:36.346429 progress 100 % (7 MB)
42 06:47:36.346625 7 MB downloaded in 0.31 s (25.11 MB/s)
43 06:47:36.346780 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:47:36.347018 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:47:36.347103 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:47:36.347185 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:47:36.347320 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:47:36.347393 saving as /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/kernel/Image
50 06:47:36.347452 total size: 51532288 (49 MB)
51 06:47:36.347511 No compression specified
52 06:47:36.348614 progress 0 % (0 MB)
53 06:47:36.361826 progress 5 % (2 MB)
54 06:47:36.375108 progress 10 % (4 MB)
55 06:47:36.388437 progress 15 % (7 MB)
56 06:47:36.401823 progress 20 % (9 MB)
57 06:47:36.415260 progress 25 % (12 MB)
58 06:47:36.428622 progress 30 % (14 MB)
59 06:47:36.442292 progress 35 % (17 MB)
60 06:47:36.456101 progress 40 % (19 MB)
61 06:47:36.469462 progress 45 % (22 MB)
62 06:47:36.482982 progress 50 % (24 MB)
63 06:47:36.496234 progress 55 % (27 MB)
64 06:47:36.509833 progress 60 % (29 MB)
65 06:47:36.524379 progress 65 % (31 MB)
66 06:47:36.539008 progress 70 % (34 MB)
67 06:47:36.553023 progress 75 % (36 MB)
68 06:47:36.566983 progress 80 % (39 MB)
69 06:47:36.581189 progress 85 % (41 MB)
70 06:47:36.594645 progress 90 % (44 MB)
71 06:47:36.608007 progress 95 % (46 MB)
72 06:47:36.621056 progress 100 % (49 MB)
73 06:47:36.621299 49 MB downloaded in 0.27 s (179.46 MB/s)
74 06:47:36.621486 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:47:36.621749 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:47:36.621835 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:47:36.621953 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:47:36.622091 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:47:36.622163 saving as /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/dtb/mt8192-asurada-spherion-r0.dtb
81 06:47:36.622223 total size: 47278 (0 MB)
82 06:47:36.622283 No compression specified
83 06:47:36.623470 progress 69 % (0 MB)
84 06:47:36.623776 progress 100 % (0 MB)
85 06:47:36.623930 0 MB downloaded in 0.00 s (26.44 MB/s)
86 06:47:36.624082 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:47:36.624299 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:47:36.624385 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:47:36.624466 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:47:36.624615 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.75-cip14/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:47:36.624681 saving as /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/modules/modules.tar
93 06:47:36.624739 total size: 8624064 (8 MB)
94 06:47:36.624799 Using unxz to decompress xz
95 06:47:36.629189 progress 0 % (0 MB)
96 06:47:36.650848 progress 5 % (0 MB)
97 06:47:36.674346 progress 10 % (0 MB)
98 06:47:36.699919 progress 15 % (1 MB)
99 06:47:36.724718 progress 20 % (1 MB)
100 06:47:36.749792 progress 25 % (2 MB)
101 06:47:36.776504 progress 30 % (2 MB)
102 06:47:36.803390 progress 35 % (2 MB)
103 06:47:36.827435 progress 40 % (3 MB)
104 06:47:36.852271 progress 45 % (3 MB)
105 06:47:36.878109 progress 50 % (4 MB)
106 06:47:36.903173 progress 55 % (4 MB)
107 06:47:36.928661 progress 60 % (4 MB)
108 06:47:36.956997 progress 65 % (5 MB)
109 06:47:36.982512 progress 70 % (5 MB)
110 06:47:37.006449 progress 75 % (6 MB)
111 06:47:37.034513 progress 80 % (6 MB)
112 06:47:37.061902 progress 85 % (7 MB)
113 06:47:37.087687 progress 90 % (7 MB)
114 06:47:37.120180 progress 95 % (7 MB)
115 06:47:37.148790 progress 100 % (8 MB)
116 06:47:37.153761 8 MB downloaded in 0.53 s (15.55 MB/s)
117 06:47:37.154108 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:47:37.154495 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:47:37.154621 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 06:47:37.154760 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 06:47:37.154881 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:47:37.154999 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 06:47:37.155296 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6
125 06:47:37.155497 makedir: /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin
126 06:47:37.155667 makedir: /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/tests
127 06:47:37.155829 makedir: /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/results
128 06:47:37.156004 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-add-keys
129 06:47:37.156221 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-add-sources
130 06:47:37.156416 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-background-process-start
131 06:47:37.156603 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-background-process-stop
132 06:47:37.156792 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-common-functions
133 06:47:37.156981 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-echo-ipv4
134 06:47:37.157174 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-install-packages
135 06:47:37.157361 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-installed-packages
136 06:47:37.157550 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-os-build
137 06:47:37.157736 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-probe-channel
138 06:47:37.157924 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-probe-ip
139 06:47:37.158111 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-target-ip
140 06:47:37.158296 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-target-mac
141 06:47:37.158480 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-target-storage
142 06:47:37.158673 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-test-case
143 06:47:37.158867 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-test-event
144 06:47:37.159053 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-test-feedback
145 06:47:37.159248 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-test-raise
146 06:47:37.159448 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-test-reference
147 06:47:37.159637 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-test-runner
148 06:47:37.159826 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-test-set
149 06:47:37.160019 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-test-shell
150 06:47:37.160212 Updating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-install-packages (oe)
151 06:47:37.160440 Updating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/bin/lava-installed-packages (oe)
152 06:47:37.160623 Creating /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/environment
153 06:47:37.160776 LAVA metadata
154 06:47:37.160890 - LAVA_JOB_ID=12694830
155 06:47:37.160998 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:47:37.161158 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 06:47:37.161274 skipped lava-vland-overlay
158 06:47:37.161394 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:47:37.161525 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 06:47:37.161625 skipped lava-multinode-overlay
161 06:47:37.161753 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:47:37.161894 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 06:47:37.162018 Loading test definitions
164 06:47:37.162164 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 06:47:37.162290 Using /lava-12694830 at stage 0
166 06:47:37.162767 uuid=12694830_1.5.2.3.1 testdef=None
167 06:47:37.162903 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:47:37.163036 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 06:47:37.163864 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:47:37.164228 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 06:47:37.165214 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:47:37.165583 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 06:47:37.166528 runner path: /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/0/tests/0_dmesg test_uuid 12694830_1.5.2.3.1
176 06:47:37.166750 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:47:37.167124 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 06:47:37.167239 Using /lava-12694830 at stage 1
180 06:47:37.167717 uuid=12694830_1.5.2.3.5 testdef=None
181 06:47:37.167848 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 06:47:37.167977 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 06:47:37.168716 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 06:47:37.169081 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 06:47:37.170698 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 06:47:37.171062 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 06:47:37.172035 runner path: /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/1/tests/1_bootrr test_uuid 12694830_1.5.2.3.5
190 06:47:37.172249 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 06:47:37.172588 Creating lava-test-runner.conf files
193 06:47:37.172687 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/0 for stage 0
194 06:47:37.172830 - 0_dmesg
195 06:47:37.172955 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12694830/lava-overlay-28923he6/lava-12694830/1 for stage 1
196 06:47:37.173106 - 1_bootrr
197 06:47:37.173250 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 06:47:37.173380 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 06:47:37.185124 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 06:47:37.185317 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 06:47:37.185468 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 06:47:37.185616 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 06:47:37.185755 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 06:47:37.439173 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 06:47:37.439638 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 06:47:37.439756 extracting modules file /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12694830/extract-overlay-ramdisk-y9q3c0tb/ramdisk
207 06:47:37.683895 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 06:47:37.684074 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 06:47:37.684177 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694830/compress-overlay-5n1lcxx2/overlay-1.5.2.4.tar.gz to ramdisk
210 06:47:37.684247 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12694830/compress-overlay-5n1lcxx2/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12694830/extract-overlay-ramdisk-y9q3c0tb/ramdisk
211 06:47:37.692390 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 06:47:37.692514 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 06:47:37.692606 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 06:47:37.692696 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 06:47:37.692777 Building ramdisk /var/lib/lava/dispatcher/tmp/12694830/extract-overlay-ramdisk-y9q3c0tb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12694830/extract-overlay-ramdisk-y9q3c0tb/ramdisk
216 06:47:38.071931 >> 145342 blocks
217 06:47:40.365638 rename /var/lib/lava/dispatcher/tmp/12694830/extract-overlay-ramdisk-y9q3c0tb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/ramdisk/ramdisk.cpio.gz
218 06:47:40.366091 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 06:47:40.366218 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 06:47:40.366316 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 06:47:40.366425 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/kernel/Image'
222 06:47:53.892456 Returned 0 in 13 seconds
223 06:47:53.993120 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/kernel/image.itb
224 06:47:54.414222 output: FIT description: Kernel Image image with one or more FDT blobs
225 06:47:54.414617 output: Created: Sat Feb 3 06:47:54 2024
226 06:47:54.414714 output: Image 0 (kernel-1)
227 06:47:54.414783 output: Description:
228 06:47:54.414849 output: Created: Sat Feb 3 06:47:54 2024
229 06:47:54.414911 output: Type: Kernel Image
230 06:47:54.414970 output: Compression: lzma compressed
231 06:47:54.415028 output: Data Size: 12050581 Bytes = 11768.15 KiB = 11.49 MiB
232 06:47:54.415088 output: Architecture: AArch64
233 06:47:54.415146 output: OS: Linux
234 06:47:54.415200 output: Load Address: 0x00000000
235 06:47:54.415254 output: Entry Point: 0x00000000
236 06:47:54.415308 output: Hash algo: crc32
237 06:47:54.415391 output: Hash value: 380e7c3c
238 06:47:54.415463 output: Image 1 (fdt-1)
239 06:47:54.415518 output: Description: mt8192-asurada-spherion-r0
240 06:47:54.415572 output: Created: Sat Feb 3 06:47:54 2024
241 06:47:54.415625 output: Type: Flat Device Tree
242 06:47:54.415677 output: Compression: uncompressed
243 06:47:54.415730 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 06:47:54.415782 output: Architecture: AArch64
245 06:47:54.415834 output: Hash algo: crc32
246 06:47:54.415887 output: Hash value: cc4352de
247 06:47:54.415939 output: Image 2 (ramdisk-1)
248 06:47:54.415990 output: Description: unavailable
249 06:47:54.416042 output: Created: Sat Feb 3 06:47:54 2024
250 06:47:54.416094 output: Type: RAMDisk Image
251 06:47:54.416147 output: Compression: Unknown Compression
252 06:47:54.416199 output: Data Size: 21387037 Bytes = 20885.78 KiB = 20.40 MiB
253 06:47:54.416251 output: Architecture: AArch64
254 06:47:54.416303 output: OS: Linux
255 06:47:54.416355 output: Load Address: unavailable
256 06:47:54.416407 output: Entry Point: unavailable
257 06:47:54.416458 output: Hash algo: crc32
258 06:47:54.416510 output: Hash value: 6af8164d
259 06:47:54.416562 output: Default Configuration: 'conf-1'
260 06:47:54.416618 output: Configuration 0 (conf-1)
261 06:47:54.416683 output: Description: mt8192-asurada-spherion-r0
262 06:47:54.416759 output: Kernel: kernel-1
263 06:47:54.416847 output: Init Ramdisk: ramdisk-1
264 06:47:54.416947 output: FDT: fdt-1
265 06:47:54.417030 output: Loadables: kernel-1
266 06:47:54.417112 output:
267 06:47:54.417346 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 06:47:54.417476 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 06:47:54.417613 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 06:47:54.417739 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 06:47:54.417845 No LXC device requested
272 06:47:54.417955 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 06:47:54.418071 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 06:47:54.418177 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 06:47:54.418275 Checking files for TFTP limit of 4294967296 bytes.
276 06:47:54.418960 end: 1 tftp-deploy (duration 00:00:18) [common]
277 06:47:54.419146 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 06:47:54.419268 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 06:47:54.419447 substitutions:
280 06:47:54.419757 - {DTB}: 12694830/tftp-deploy-m4akf261/dtb/mt8192-asurada-spherion-r0.dtb
281 06:47:54.419842 - {INITRD}: 12694830/tftp-deploy-m4akf261/ramdisk/ramdisk.cpio.gz
282 06:47:54.419906 - {KERNEL}: 12694830/tftp-deploy-m4akf261/kernel/Image
283 06:47:54.419966 - {LAVA_MAC}: None
284 06:47:54.420026 - {PRESEED_CONFIG}: None
285 06:47:54.420082 - {PRESEED_LOCAL}: None
286 06:47:54.420137 - {RAMDISK}: 12694830/tftp-deploy-m4akf261/ramdisk/ramdisk.cpio.gz
287 06:47:54.420191 - {ROOT_PART}: None
288 06:47:54.420245 - {ROOT}: None
289 06:47:54.420298 - {SERVER_IP}: 192.168.201.1
290 06:47:54.420351 - {TEE}: None
291 06:47:54.420404 Parsed boot commands:
292 06:47:54.420457 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 06:47:54.420647 Parsed boot commands: tftpboot 192.168.201.1 12694830/tftp-deploy-m4akf261/kernel/image.itb 12694830/tftp-deploy-m4akf261/kernel/cmdline
294 06:47:54.420738 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 06:47:54.420824 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 06:47:54.420923 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 06:47:54.421008 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 06:47:54.421080 Not connected, no need to disconnect.
299 06:47:54.421153 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 06:47:54.421236 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 06:47:54.421302 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
302 06:47:54.425433 Setting prompt string to ['lava-test: # ']
303 06:47:54.425843 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 06:47:54.425972 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 06:47:54.426092 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 06:47:54.426405 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 06:47:54.426612 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
308 06:47:59.565293 >> Command sent successfully.
309 06:47:59.567800 Returned 0 in 5 seconds
310 06:47:59.668199 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 06:47:59.668593 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 06:47:59.668706 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 06:47:59.668816 Setting prompt string to 'Starting depthcharge on Spherion...'
315 06:47:59.668895 Changing prompt to 'Starting depthcharge on Spherion...'
316 06:47:59.668970 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 06:47:59.669274 [Enter `^Ec?' for help]
318 06:47:59.845641
319 06:47:59.845810
320 06:47:59.845884 F0: 102B 0000
321 06:47:59.845949
322 06:47:59.846009 F3: 1001 0000 [0200]
323 06:47:59.848511
324 06:47:59.848596 F3: 1001 0000
325 06:47:59.848661
326 06:47:59.848722 F7: 102D 0000
327 06:47:59.848780
328 06:47:59.852419 F1: 0000 0000
329 06:47:59.852502
330 06:47:59.852567 V0: 0000 0000 [0001]
331 06:47:59.852627
332 06:47:59.855579 00: 0007 8000
333 06:47:59.855666
334 06:47:59.855731 01: 0000 0000
335 06:47:59.855793
336 06:47:59.858564 BP: 0C00 0209 [0000]
337 06:47:59.858645
338 06:47:59.858710 G0: 1182 0000
339 06:47:59.858769
340 06:47:59.862189 EC: 0000 0021 [4000]
341 06:47:59.862270
342 06:47:59.862334 S7: 0000 0000 [0000]
343 06:47:59.862394
344 06:47:59.865664 CC: 0000 0000 [0001]
345 06:47:59.865775
346 06:47:59.865890 T0: 0000 0040 [010F]
347 06:47:59.865993
348 06:47:59.869050 Jump to BL
349 06:47:59.869132
350 06:47:59.892443
351 06:47:59.892547
352 06:47:59.892612
353 06:47:59.899462 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 06:47:59.903377 ARM64: Exception handlers installed.
355 06:47:59.906688 ARM64: Testing exception
356 06:47:59.910152 ARM64: Done test exception
357 06:47:59.916259 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 06:47:59.927018 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 06:47:59.933451 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 06:47:59.943794 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 06:47:59.950047 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 06:47:59.960510 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 06:47:59.969883 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 06:47:59.977134 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 06:47:59.995169 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 06:47:59.999081 WDT: Last reset was cold boot
367 06:48:00.001523 SPI1(PAD0) initialized at 2873684 Hz
368 06:48:00.005006 SPI5(PAD0) initialized at 992727 Hz
369 06:48:00.008052 VBOOT: Loading verstage.
370 06:48:00.014996 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 06:48:00.017960 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 06:48:00.021868 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 06:48:00.025140 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 06:48:00.032205 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 06:48:00.039862 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 06:48:00.049896 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 06:48:00.049981
378 06:48:00.050047
379 06:48:00.060368 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 06:48:00.063335 ARM64: Exception handlers installed.
381 06:48:00.067334 ARM64: Testing exception
382 06:48:00.067466 ARM64: Done test exception
383 06:48:00.073669 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 06:48:00.077032 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 06:48:00.091128 Probing TPM: . done!
386 06:48:00.091215 TPM ready after 0 ms
387 06:48:00.099263 Connected to device vid:did:rid of 1ae0:0028:00
388 06:48:00.105843 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 06:48:00.162604 Initialized TPM device CR50 revision 0
390 06:48:00.174294 tlcl_send_startup: Startup return code is 0
391 06:48:00.174406 TPM: setup succeeded
392 06:48:00.185593 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 06:48:00.194320 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 06:48:00.205727 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 06:48:00.215750 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 06:48:00.219030 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 06:48:00.227912 in-header: 03 07 00 00 08 00 00 00
398 06:48:00.230836 in-data: aa e4 47 04 13 02 00 00
399 06:48:00.234816 Chrome EC: UHEPI supported
400 06:48:00.242493 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 06:48:00.246056 in-header: 03 95 00 00 08 00 00 00
402 06:48:00.246139 in-data: 18 20 20 08 00 00 00 00
403 06:48:00.250036 Phase 1
404 06:48:00.253104 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 06:48:00.257000 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 06:48:00.265412 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 06:48:00.268565 Recovery requested (1009000e)
408 06:48:00.275928 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 06:48:00.281257 tlcl_extend: response is 0
410 06:48:00.290969 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 06:48:00.296745 tlcl_extend: response is 0
412 06:48:00.303580 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 06:48:00.323015 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 06:48:00.329703 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 06:48:00.329832
416 06:48:00.329902
417 06:48:00.339607 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 06:48:00.342702 ARM64: Exception handlers installed.
419 06:48:00.346139 ARM64: Testing exception
420 06:48:00.346227 ARM64: Done test exception
421 06:48:00.368723 pmic_efuse_setting: Set efuses in 11 msecs
422 06:48:00.372118 pmwrap_interface_init: Select PMIF_VLD_RDY
423 06:48:00.378472 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 06:48:00.381945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 06:48:00.389285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 06:48:00.393003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 06:48:00.396429 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 06:48:00.403251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 06:48:00.407393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 06:48:00.411172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 06:48:00.414871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 06:48:00.421524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 06:48:00.425935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 06:48:00.429557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 06:48:00.433034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 06:48:00.441038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 06:48:00.447765 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 06:48:00.451607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 06:48:00.458629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 06:48:00.462261 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 06:48:00.469904 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 06:48:00.477119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 06:48:00.480918 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 06:48:00.488484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 06:48:00.491702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 06:48:00.499290 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 06:48:00.503052 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 06:48:00.510298 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 06:48:00.513629 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 06:48:00.517515 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 06:48:00.524386 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 06:48:00.527977 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 06:48:00.531947 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 06:48:00.538924 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 06:48:00.542503 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 06:48:00.549933 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 06:48:00.553217 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 06:48:00.557079 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 06:48:00.563963 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 06:48:00.567903 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 06:48:00.572098 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 06:48:00.575669 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 06:48:00.582798 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 06:48:00.586427 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 06:48:00.590383 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 06:48:00.593561 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 06:48:00.597363 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 06:48:00.604795 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 06:48:00.608537 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 06:48:00.611640 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 06:48:00.615003 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 06:48:00.618659 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 06:48:00.622122 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 06:48:00.633423 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 06:48:00.641125 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 06:48:00.644665 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 06:48:00.651552 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 06:48:00.663588 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 06:48:00.667311 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 06:48:00.670557 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 06:48:00.674006 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 06:48:00.682504 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
483 06:48:00.686090 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 06:48:00.693936 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
485 06:48:00.697495 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 06:48:00.706483 [RTC]rtc_get_frequency_meter,154: input=15, output=853
487 06:48:00.716238 [RTC]rtc_get_frequency_meter,154: input=7, output=725
488 06:48:00.725154 [RTC]rtc_get_frequency_meter,154: input=11, output=789
489 06:48:00.735128 [RTC]rtc_get_frequency_meter,154: input=13, output=821
490 06:48:00.744409 [RTC]rtc_get_frequency_meter,154: input=12, output=805
491 06:48:00.754135 [RTC]rtc_get_frequency_meter,154: input=11, output=790
492 06:48:00.763930 [RTC]rtc_get_frequency_meter,154: input=12, output=806
493 06:48:00.767773 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
494 06:48:00.774212 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
495 06:48:00.777755 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 06:48:00.781587 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 06:48:00.785942 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 06:48:00.788980 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 06:48:00.792835 ADC[4]: Raw value=905172 ID=7
500 06:48:00.796228 ADC[3]: Raw value=213916 ID=1
501 06:48:00.796621 RAM Code: 0x71
502 06:48:00.800247 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 06:48:00.807232 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 06:48:00.815078 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 06:48:00.821972 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 06:48:00.825946 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 06:48:00.830502 in-header: 03 07 00 00 08 00 00 00
508 06:48:00.831043 in-data: aa e4 47 04 13 02 00 00
509 06:48:00.833785 Chrome EC: UHEPI supported
510 06:48:00.840998 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 06:48:00.844691 in-header: 03 95 00 00 08 00 00 00
512 06:48:00.848212 in-data: 18 20 20 08 00 00 00 00
513 06:48:00.852179 MRC: failed to locate region type 0.
514 06:48:00.856018 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 06:48:00.859490 DRAM-K: Running full calibration
516 06:48:00.867211 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 06:48:00.868039 header.status = 0x0
518 06:48:00.870999 header.version = 0x6 (expected: 0x6)
519 06:48:00.874755 header.size = 0xd00 (expected: 0xd00)
520 06:48:00.875268 header.flags = 0x0
521 06:48:00.881701 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 06:48:00.900680 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
523 06:48:00.907943 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 06:48:00.912394 dram_init: ddr_geometry: 2
525 06:48:00.912823 [EMI] MDL number = 2
526 06:48:00.915176 [EMI] Get MDL freq = 0
527 06:48:00.915554 dram_init: ddr_type: 0
528 06:48:00.918799 is_discrete_lpddr4: 1
529 06:48:00.922630 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 06:48:00.923073
531 06:48:00.923431
532 06:48:00.923793 [Bian_co] ETT version 0.0.0.1
533 06:48:00.930221 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 06:48:00.930613
535 06:48:00.933762 dramc_set_vcore_voltage set vcore to 650000
536 06:48:00.934154 Read voltage for 800, 4
537 06:48:00.937173 Vio18 = 0
538 06:48:00.937563 Vcore = 650000
539 06:48:00.937871 Vdram = 0
540 06:48:00.940824 Vddq = 0
541 06:48:00.941212 Vmddr = 0
542 06:48:00.941523 dram_init: config_dvfs: 1
543 06:48:00.948626 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 06:48:00.952092 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 06:48:00.955343 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 06:48:00.958801 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 06:48:00.965604 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 06:48:00.969047 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 06:48:00.969476 MEM_TYPE=3, freq_sel=18
550 06:48:00.972236 sv_algorithm_assistance_LP4_1600
551 06:48:00.975676 ============ PULL DRAM RESETB DOWN ============
552 06:48:00.983257 ========== PULL DRAM RESETB DOWN end =========
553 06:48:00.986750 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 06:48:00.990263 ===================================
555 06:48:00.990653 LPDDR4 DRAM CONFIGURATION
556 06:48:00.994222 ===================================
557 06:48:00.997305 EX_ROW_EN[0] = 0x0
558 06:48:01.000420 EX_ROW_EN[1] = 0x0
559 06:48:01.000809 LP4Y_EN = 0x0
560 06:48:01.004304 WORK_FSP = 0x0
561 06:48:01.004796 WL = 0x2
562 06:48:01.007744 RL = 0x2
563 06:48:01.008238 BL = 0x2
564 06:48:01.010624 RPST = 0x0
565 06:48:01.011116 RD_PRE = 0x0
566 06:48:01.014352 WR_PRE = 0x1
567 06:48:01.014860 WR_PST = 0x0
568 06:48:01.017382 DBI_WR = 0x0
569 06:48:01.017872 DBI_RD = 0x0
570 06:48:01.020474 OTF = 0x1
571 06:48:01.024403 ===================================
572 06:48:01.027058 ===================================
573 06:48:01.027702 ANA top config
574 06:48:01.030614 ===================================
575 06:48:01.034332 DLL_ASYNC_EN = 0
576 06:48:01.037243 ALL_SLAVE_EN = 1
577 06:48:01.037634 NEW_RANK_MODE = 1
578 06:48:01.040586 DLL_IDLE_MODE = 1
579 06:48:01.043872 LP45_APHY_COMB_EN = 1
580 06:48:01.046861 TX_ODT_DIS = 1
581 06:48:01.050499 NEW_8X_MODE = 1
582 06:48:01.054240 ===================================
583 06:48:01.057371 ===================================
584 06:48:01.058040 data_rate = 1600
585 06:48:01.060790 CKR = 1
586 06:48:01.064062 DQ_P2S_RATIO = 8
587 06:48:01.066819 ===================================
588 06:48:01.070399 CA_P2S_RATIO = 8
589 06:48:01.073794 DQ_CA_OPEN = 0
590 06:48:01.074197 DQ_SEMI_OPEN = 0
591 06:48:01.077395 CA_SEMI_OPEN = 0
592 06:48:01.080878 CA_FULL_RATE = 0
593 06:48:01.084110 DQ_CKDIV4_EN = 1
594 06:48:01.087326 CA_CKDIV4_EN = 1
595 06:48:01.090933 CA_PREDIV_EN = 0
596 06:48:01.091500 PH8_DLY = 0
597 06:48:01.094148 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 06:48:01.097107 DQ_AAMCK_DIV = 4
599 06:48:01.100559 CA_AAMCK_DIV = 4
600 06:48:01.104035 CA_ADMCK_DIV = 4
601 06:48:01.107175 DQ_TRACK_CA_EN = 0
602 06:48:01.107692 CA_PICK = 800
603 06:48:01.110558 CA_MCKIO = 800
604 06:48:01.114176 MCKIO_SEMI = 0
605 06:48:01.117836 PLL_FREQ = 3068
606 06:48:01.121366 DQ_UI_PI_RATIO = 32
607 06:48:01.124876 CA_UI_PI_RATIO = 0
608 06:48:01.125403 ===================================
609 06:48:01.128397 ===================================
610 06:48:01.131881 memory_type:LPDDR4
611 06:48:01.135899 GP_NUM : 10
612 06:48:01.136325 SRAM_EN : 1
613 06:48:01.139694 MD32_EN : 0
614 06:48:01.143646 ===================================
615 06:48:01.144075 [ANA_INIT] >>>>>>>>>>>>>>
616 06:48:01.146719 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 06:48:01.150740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 06:48:01.154386 ===================================
619 06:48:01.157193 data_rate = 1600,PCW = 0X7600
620 06:48:01.160976 ===================================
621 06:48:01.164116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 06:48:01.167836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 06:48:01.173532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 06:48:01.177071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 06:48:01.180452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 06:48:01.187423 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 06:48:01.187957 [ANA_INIT] flow start
628 06:48:01.190869 [ANA_INIT] PLL >>>>>>>>
629 06:48:01.191428 [ANA_INIT] PLL <<<<<<<<
630 06:48:01.193488 [ANA_INIT] MIDPI >>>>>>>>
631 06:48:01.196934 [ANA_INIT] MIDPI <<<<<<<<
632 06:48:01.201004 [ANA_INIT] DLL >>>>>>>>
633 06:48:01.201538 [ANA_INIT] flow end
634 06:48:01.203473 ============ LP4 DIFF to SE enter ============
635 06:48:01.210831 ============ LP4 DIFF to SE exit ============
636 06:48:01.211605 [ANA_INIT] <<<<<<<<<<<<<
637 06:48:01.213551 [Flow] Enable top DCM control >>>>>
638 06:48:01.217277 [Flow] Enable top DCM control <<<<<
639 06:48:01.221001 Enable DLL master slave shuffle
640 06:48:01.226738 ==============================================================
641 06:48:01.227295 Gating Mode config
642 06:48:01.234055 ==============================================================
643 06:48:01.236614 Config description:
644 06:48:01.246601 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 06:48:01.253649 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 06:48:01.257317 SELPH_MODE 0: By rank 1: By Phase
647 06:48:01.263484 ==============================================================
648 06:48:01.267063 GAT_TRACK_EN = 1
649 06:48:01.269787 RX_GATING_MODE = 2
650 06:48:01.270230 RX_GATING_TRACK_MODE = 2
651 06:48:01.273228 SELPH_MODE = 1
652 06:48:01.276497 PICG_EARLY_EN = 1
653 06:48:01.280537 VALID_LAT_VALUE = 1
654 06:48:01.286918 ==============================================================
655 06:48:01.290156 Enter into Gating configuration >>>>
656 06:48:01.292910 Exit from Gating configuration <<<<
657 06:48:01.296513 Enter into DVFS_PRE_config >>>>>
658 06:48:01.306796 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 06:48:01.309739 Exit from DVFS_PRE_config <<<<<
660 06:48:01.313217 Enter into PICG configuration >>>>
661 06:48:01.316314 Exit from PICG configuration <<<<
662 06:48:01.319959 [RX_INPUT] configuration >>>>>
663 06:48:01.323011 [RX_INPUT] configuration <<<<<
664 06:48:01.326521 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 06:48:01.333223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 06:48:01.339579 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 06:48:01.346536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 06:48:01.350022 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 06:48:01.355973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 06:48:01.359447 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 06:48:01.366707 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 06:48:01.369585 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 06:48:01.372919 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 06:48:01.376553 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 06:48:01.383588 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 06:48:01.386681 ===================================
677 06:48:01.387229 LPDDR4 DRAM CONFIGURATION
678 06:48:01.389173 ===================================
679 06:48:01.392753 EX_ROW_EN[0] = 0x0
680 06:48:01.396362 EX_ROW_EN[1] = 0x0
681 06:48:01.396912 LP4Y_EN = 0x0
682 06:48:01.399758 WORK_FSP = 0x0
683 06:48:01.400328 WL = 0x2
684 06:48:01.402570 RL = 0x2
685 06:48:01.403009 BL = 0x2
686 06:48:01.406189 RPST = 0x0
687 06:48:01.406737 RD_PRE = 0x0
688 06:48:01.409439 WR_PRE = 0x1
689 06:48:01.409988 WR_PST = 0x0
690 06:48:01.412559 DBI_WR = 0x0
691 06:48:01.413000 DBI_RD = 0x0
692 06:48:01.415980 OTF = 0x1
693 06:48:01.419918 ===================================
694 06:48:01.422346 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 06:48:01.425490 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 06:48:01.432314 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 06:48:01.435622 ===================================
698 06:48:01.436196 LPDDR4 DRAM CONFIGURATION
699 06:48:01.438778 ===================================
700 06:48:01.442578 EX_ROW_EN[0] = 0x10
701 06:48:01.445964 EX_ROW_EN[1] = 0x0
702 06:48:01.446516 LP4Y_EN = 0x0
703 06:48:01.449325 WORK_FSP = 0x0
704 06:48:01.449768 WL = 0x2
705 06:48:01.452809 RL = 0x2
706 06:48:01.453354 BL = 0x2
707 06:48:01.455743 RPST = 0x0
708 06:48:01.456182 RD_PRE = 0x0
709 06:48:01.458796 WR_PRE = 0x1
710 06:48:01.459236 WR_PST = 0x0
711 06:48:01.462650 DBI_WR = 0x0
712 06:48:01.463200 DBI_RD = 0x0
713 06:48:01.465305 OTF = 0x1
714 06:48:01.468515 ===================================
715 06:48:01.475233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 06:48:01.478840 nWR fixed to 40
717 06:48:01.482436 [ModeRegInit_LP4] CH0 RK0
718 06:48:01.482874 [ModeRegInit_LP4] CH0 RK1
719 06:48:01.486111 [ModeRegInit_LP4] CH1 RK0
720 06:48:01.489052 [ModeRegInit_LP4] CH1 RK1
721 06:48:01.489487 match AC timing 13
722 06:48:01.495739 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 06:48:01.498615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 06:48:01.502064 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 06:48:01.508626 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 06:48:01.512019 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 06:48:01.512452 [EMI DOE] emi_dcm 0
728 06:48:01.518903 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 06:48:01.519340 ==
730 06:48:01.521735 Dram Type= 6, Freq= 0, CH_0, rank 0
731 06:48:01.525160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 06:48:01.525692 ==
733 06:48:01.531960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 06:48:01.535329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 06:48:01.545847 [CA 0] Center 38 (7~69) winsize 63
736 06:48:01.549707 [CA 1] Center 37 (6~68) winsize 63
737 06:48:01.552198 [CA 2] Center 34 (4~65) winsize 62
738 06:48:01.555976 [CA 3] Center 35 (4~66) winsize 63
739 06:48:01.559217 [CA 4] Center 33 (3~64) winsize 62
740 06:48:01.562332 [CA 5] Center 33 (3~64) winsize 62
741 06:48:01.562854
742 06:48:01.565924 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 06:48:01.566357
744 06:48:01.569150 [CATrainingPosCal] consider 1 rank data
745 06:48:01.572695 u2DelayCellTimex100 = 270/100 ps
746 06:48:01.575508 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
747 06:48:01.579522 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
748 06:48:01.586191 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 06:48:01.589472 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
750 06:48:01.592900 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 06:48:01.596453 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 06:48:01.597004
753 06:48:01.599682 CA PerBit enable=1, Macro0, CA PI delay=33
754 06:48:01.600121
755 06:48:01.602458 [CBTSetCACLKResult] CA Dly = 33
756 06:48:01.602896 CS Dly: 5 (0~36)
757 06:48:01.606183 ==
758 06:48:01.606735 Dram Type= 6, Freq= 0, CH_0, rank 1
759 06:48:01.612609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 06:48:01.613166 ==
761 06:48:01.615591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 06:48:01.622254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 06:48:01.632467 [CA 0] Center 38 (7~69) winsize 63
764 06:48:01.635744 [CA 1] Center 37 (7~68) winsize 62
765 06:48:01.638638 [CA 2] Center 35 (5~66) winsize 62
766 06:48:01.642101 [CA 3] Center 35 (4~66) winsize 63
767 06:48:01.645424 [CA 4] Center 34 (3~65) winsize 63
768 06:48:01.649051 [CA 5] Center 33 (3~64) winsize 62
769 06:48:01.649577
770 06:48:01.651985 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 06:48:01.652414
772 06:48:01.655473 [CATrainingPosCal] consider 2 rank data
773 06:48:01.658802 u2DelayCellTimex100 = 270/100 ps
774 06:48:01.662003 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
775 06:48:01.668555 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 06:48:01.671867 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
777 06:48:01.675562 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
778 06:48:01.679114 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 06:48:01.681976 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 06:48:01.682527
781 06:48:01.684984 CA PerBit enable=1, Macro0, CA PI delay=33
782 06:48:01.685600
783 06:48:01.688190 [CBTSetCACLKResult] CA Dly = 33
784 06:48:01.691895 CS Dly: 6 (0~38)
785 06:48:01.692438
786 06:48:01.695190 ----->DramcWriteLeveling(PI) begin...
787 06:48:01.695787 ==
788 06:48:01.699071 Dram Type= 6, Freq= 0, CH_0, rank 0
789 06:48:01.702349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 06:48:01.702934 ==
791 06:48:01.706435 Write leveling (Byte 0): 30 => 30
792 06:48:01.706997 Write leveling (Byte 1): 26 => 26
793 06:48:01.709949 DramcWriteLeveling(PI) end<-----
794 06:48:01.710492
795 06:48:01.710840 ==
796 06:48:01.713788 Dram Type= 6, Freq= 0, CH_0, rank 0
797 06:48:01.719829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 06:48:01.720346 ==
799 06:48:01.720718 [Gating] SW mode calibration
800 06:48:01.730474 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 06:48:01.734005 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 06:48:01.737544 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 06:48:01.743539 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 06:48:01.747322 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 06:48:01.750891 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 06:48:01.757727 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 06:48:01.761191 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 06:48:01.763735 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 06:48:01.770486 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 06:48:01.773460 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 06:48:01.777405 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 06:48:01.783502 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 06:48:01.787115 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 06:48:01.790085 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 06:48:01.797249 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 06:48:01.800725 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 06:48:01.803436 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 06:48:01.810555 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 06:48:01.814054 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
820 06:48:01.816699 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
821 06:48:01.823927 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
822 06:48:01.826683 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 06:48:01.830113 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 06:48:01.836818 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 06:48:01.839608 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 06:48:01.843726 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 06:48:01.846717 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 06:48:01.853359 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
829 06:48:01.856682 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
830 06:48:01.859691 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 06:48:01.866863 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 06:48:01.869968 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 06:48:01.873610 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 06:48:01.879820 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 06:48:01.883260 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
836 06:48:01.886702 0 10 8 | B1->B0 | 3232 2929 | 0 0 | (0 1) (0 0)
837 06:48:01.892924 0 10 12 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
838 06:48:01.896286 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 06:48:01.899768 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 06:48:01.906110 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 06:48:01.909985 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 06:48:01.912955 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 06:48:01.919752 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
844 06:48:01.923322 0 11 8 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
845 06:48:01.926581 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
846 06:48:01.933052 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 06:48:01.936668 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 06:48:01.940059 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 06:48:01.946210 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 06:48:01.949694 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 06:48:01.953510 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 06:48:01.959311 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 06:48:01.962768 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 06:48:01.966392 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 06:48:01.972613 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 06:48:01.976263 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 06:48:01.979561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 06:48:01.986002 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 06:48:01.989234 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 06:48:01.992246 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 06:48:01.999163 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 06:48:02.002529 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 06:48:02.006153 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 06:48:02.008817 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 06:48:02.015780 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 06:48:02.019445 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 06:48:02.022518 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 06:48:02.029111 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
869 06:48:02.032392 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 06:48:02.035579 Total UI for P1: 0, mck2ui 16
871 06:48:02.039160 best dqsien dly found for B0: ( 0, 14, 6)
872 06:48:02.041890 Total UI for P1: 0, mck2ui 16
873 06:48:02.046007 best dqsien dly found for B1: ( 0, 14, 8)
874 06:48:02.048581 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
875 06:48:02.051973 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 06:48:02.052413
877 06:48:02.055594 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
878 06:48:02.059123 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 06:48:02.062187 [Gating] SW calibration Done
880 06:48:02.062738 ==
881 06:48:02.065140 Dram Type= 6, Freq= 0, CH_0, rank 0
882 06:48:02.069034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 06:48:02.072390 ==
884 06:48:02.072835 RX Vref Scan: 0
885 06:48:02.073287
886 06:48:02.075782 RX Vref 0 -> 0, step: 1
887 06:48:02.076236
888 06:48:02.079271 RX Delay -130 -> 252, step: 16
889 06:48:02.083053 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
890 06:48:02.085686 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
891 06:48:02.089229 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 06:48:02.092577 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 06:48:02.099067 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
894 06:48:02.101974 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
895 06:48:02.105853 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
896 06:48:02.109550 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
897 06:48:02.112287 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
898 06:48:02.119284 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
899 06:48:02.122160 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
900 06:48:02.126178 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
901 06:48:02.129128 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
902 06:48:02.132273 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
903 06:48:02.138953 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
904 06:48:02.142037 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
905 06:48:02.142497 ==
906 06:48:02.145528 Dram Type= 6, Freq= 0, CH_0, rank 0
907 06:48:02.149193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 06:48:02.149746 ==
909 06:48:02.152411 DQS Delay:
910 06:48:02.152959 DQS0 = 0, DQS1 = 0
911 06:48:02.153417 DQM Delay:
912 06:48:02.155184 DQM0 = 88, DQM1 = 75
913 06:48:02.155673 DQ Delay:
914 06:48:02.158919 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
915 06:48:02.162091 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
916 06:48:02.165960 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
917 06:48:02.168727 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
918 06:48:02.169172
919 06:48:02.169622
920 06:48:02.170249 ==
921 06:48:02.171958 Dram Type= 6, Freq= 0, CH_0, rank 0
922 06:48:02.179149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 06:48:02.179609 ==
924 06:48:02.179945
925 06:48:02.180257
926 06:48:02.180586 TX Vref Scan disable
927 06:48:02.182089 == TX Byte 0 ==
928 06:48:02.185401 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
929 06:48:02.192006 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
930 06:48:02.192637 == TX Byte 1 ==
931 06:48:02.195634 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
932 06:48:02.201974 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
933 06:48:02.202496 ==
934 06:48:02.205648 Dram Type= 6, Freq= 0, CH_0, rank 0
935 06:48:02.209232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 06:48:02.209783 ==
937 06:48:02.221167 TX Vref=22, minBit 1, minWin=26, winSum=437
938 06:48:02.225480 TX Vref=24, minBit 5, minWin=26, winSum=439
939 06:48:02.228186 TX Vref=26, minBit 0, minWin=27, winSum=445
940 06:48:02.231535 TX Vref=28, minBit 7, minWin=27, winSum=449
941 06:48:02.234630 TX Vref=30, minBit 0, minWin=28, winSum=451
942 06:48:02.241246 TX Vref=32, minBit 2, minWin=27, winSum=447
943 06:48:02.244442 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
944 06:48:02.244888
945 06:48:02.248090 Final TX Range 1 Vref 30
946 06:48:02.248515
947 06:48:02.248988 ==
948 06:48:02.251239 Dram Type= 6, Freq= 0, CH_0, rank 0
949 06:48:02.254555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 06:48:02.254984 ==
951 06:48:02.255321
952 06:48:02.258013
953 06:48:02.258441 TX Vref Scan disable
954 06:48:02.261582 == TX Byte 0 ==
955 06:48:02.265185 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
956 06:48:02.271244 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
957 06:48:02.271738 == TX Byte 1 ==
958 06:48:02.274841 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
959 06:48:02.281786 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
960 06:48:02.282326
961 06:48:02.282661 [DATLAT]
962 06:48:02.282975 Freq=800, CH0 RK0
963 06:48:02.283281
964 06:48:02.284285 DATLAT Default: 0xa
965 06:48:02.284710 0, 0xFFFF, sum = 0
966 06:48:02.287901 1, 0xFFFF, sum = 0
967 06:48:02.288347 2, 0xFFFF, sum = 0
968 06:48:02.291359 3, 0xFFFF, sum = 0
969 06:48:02.294226 4, 0xFFFF, sum = 0
970 06:48:02.294656 5, 0xFFFF, sum = 0
971 06:48:02.297910 6, 0xFFFF, sum = 0
972 06:48:02.298342 7, 0xFFFF, sum = 0
973 06:48:02.301257 8, 0xFFFF, sum = 0
974 06:48:02.301686 9, 0x0, sum = 1
975 06:48:02.302026 10, 0x0, sum = 2
976 06:48:02.305081 11, 0x0, sum = 3
977 06:48:02.305511 12, 0x0, sum = 4
978 06:48:02.308027 best_step = 10
979 06:48:02.308448
980 06:48:02.308780 ==
981 06:48:02.312109 Dram Type= 6, Freq= 0, CH_0, rank 0
982 06:48:02.314703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 06:48:02.315131 ==
984 06:48:02.318611 RX Vref Scan: 1
985 06:48:02.319150
986 06:48:02.319538 Set Vref Range= 32 -> 127
987 06:48:02.321290
988 06:48:02.321816 RX Vref 32 -> 127, step: 1
989 06:48:02.322156
990 06:48:02.324753 RX Delay -111 -> 252, step: 8
991 06:48:02.325279
992 06:48:02.328114 Set Vref, RX VrefLevel [Byte0]: 32
993 06:48:02.331736 [Byte1]: 32
994 06:48:02.332495
995 06:48:02.334409 Set Vref, RX VrefLevel [Byte0]: 33
996 06:48:02.337852 [Byte1]: 33
997 06:48:02.341936
998 06:48:02.342363 Set Vref, RX VrefLevel [Byte0]: 34
999 06:48:02.345075 [Byte1]: 34
1000 06:48:02.349644
1001 06:48:02.350215 Set Vref, RX VrefLevel [Byte0]: 35
1002 06:48:02.353066 [Byte1]: 35
1003 06:48:02.357270
1004 06:48:02.357693 Set Vref, RX VrefLevel [Byte0]: 36
1005 06:48:02.360329 [Byte1]: 36
1006 06:48:02.365476
1007 06:48:02.365998 Set Vref, RX VrefLevel [Byte0]: 37
1008 06:48:02.368792 [Byte1]: 37
1009 06:48:02.372689
1010 06:48:02.373114 Set Vref, RX VrefLevel [Byte0]: 38
1011 06:48:02.376120 [Byte1]: 38
1012 06:48:02.380151
1013 06:48:02.380572 Set Vref, RX VrefLevel [Byte0]: 39
1014 06:48:02.383801 [Byte1]: 39
1015 06:48:02.388141
1016 06:48:02.388561 Set Vref, RX VrefLevel [Byte0]: 40
1017 06:48:02.391301 [Byte1]: 40
1018 06:48:02.395632
1019 06:48:02.396149 Set Vref, RX VrefLevel [Byte0]: 41
1020 06:48:02.399388 [Byte1]: 41
1021 06:48:02.403254
1022 06:48:02.403729 Set Vref, RX VrefLevel [Byte0]: 42
1023 06:48:02.406147 [Byte1]: 42
1024 06:48:02.410726
1025 06:48:02.411267 Set Vref, RX VrefLevel [Byte0]: 43
1026 06:48:02.414080 [Byte1]: 43
1027 06:48:02.418411
1028 06:48:02.419146 Set Vref, RX VrefLevel [Byte0]: 44
1029 06:48:02.421678 [Byte1]: 44
1030 06:48:02.425929
1031 06:48:02.426534 Set Vref, RX VrefLevel [Byte0]: 45
1032 06:48:02.429706 [Byte1]: 45
1033 06:48:02.433594
1034 06:48:02.434013 Set Vref, RX VrefLevel [Byte0]: 46
1035 06:48:02.436965 [Byte1]: 46
1036 06:48:02.441635
1037 06:48:02.442159 Set Vref, RX VrefLevel [Byte0]: 47
1038 06:48:02.444606 [Byte1]: 47
1039 06:48:02.448901
1040 06:48:02.449321 Set Vref, RX VrefLevel [Byte0]: 48
1041 06:48:02.452152 [Byte1]: 48
1042 06:48:02.456935
1043 06:48:02.457348 Set Vref, RX VrefLevel [Byte0]: 49
1044 06:48:02.460447 [Byte1]: 49
1045 06:48:02.464436
1046 06:48:02.464851 Set Vref, RX VrefLevel [Byte0]: 50
1047 06:48:02.467224 [Byte1]: 50
1048 06:48:02.471435
1049 06:48:02.475138 Set Vref, RX VrefLevel [Byte0]: 51
1050 06:48:02.478391 [Byte1]: 51
1051 06:48:02.478811
1052 06:48:02.482368 Set Vref, RX VrefLevel [Byte0]: 52
1053 06:48:02.485055 [Byte1]: 52
1054 06:48:02.485602
1055 06:48:02.488624 Set Vref, RX VrefLevel [Byte0]: 53
1056 06:48:02.492120 [Byte1]: 53
1057 06:48:02.495591
1058 06:48:02.496105 Set Vref, RX VrefLevel [Byte0]: 54
1059 06:48:02.498607 [Byte1]: 54
1060 06:48:02.502205
1061 06:48:02.502618 Set Vref, RX VrefLevel [Byte0]: 55
1062 06:48:02.505877 [Byte1]: 55
1063 06:48:02.510116
1064 06:48:02.510684 Set Vref, RX VrefLevel [Byte0]: 56
1065 06:48:02.513481 [Byte1]: 56
1066 06:48:02.517690
1067 06:48:02.518111 Set Vref, RX VrefLevel [Byte0]: 57
1068 06:48:02.521237 [Byte1]: 57
1069 06:48:02.525682
1070 06:48:02.526207 Set Vref, RX VrefLevel [Byte0]: 58
1071 06:48:02.528976 [Byte1]: 58
1072 06:48:02.533382
1073 06:48:02.533896 Set Vref, RX VrefLevel [Byte0]: 59
1074 06:48:02.536616 [Byte1]: 59
1075 06:48:02.541322
1076 06:48:02.541864 Set Vref, RX VrefLevel [Byte0]: 60
1077 06:48:02.544071 [Byte1]: 60
1078 06:48:02.548677
1079 06:48:02.549205 Set Vref, RX VrefLevel [Byte0]: 61
1080 06:48:02.551831 [Byte1]: 61
1081 06:48:02.556015
1082 06:48:02.556567 Set Vref, RX VrefLevel [Byte0]: 62
1083 06:48:02.559026 [Byte1]: 62
1084 06:48:02.563754
1085 06:48:02.564172 Set Vref, RX VrefLevel [Byte0]: 63
1086 06:48:02.566833 [Byte1]: 63
1087 06:48:02.571210
1088 06:48:02.571670 Set Vref, RX VrefLevel [Byte0]: 64
1089 06:48:02.574259 [Byte1]: 64
1090 06:48:02.578745
1091 06:48:02.579159 Set Vref, RX VrefLevel [Byte0]: 65
1092 06:48:02.581844 [Byte1]: 65
1093 06:48:02.586716
1094 06:48:02.587132 Set Vref, RX VrefLevel [Byte0]: 66
1095 06:48:02.589892 [Byte1]: 66
1096 06:48:02.593919
1097 06:48:02.594333 Set Vref, RX VrefLevel [Byte0]: 67
1098 06:48:02.597104 [Byte1]: 67
1099 06:48:02.601574
1100 06:48:02.601990 Set Vref, RX VrefLevel [Byte0]: 68
1101 06:48:02.605204 [Byte1]: 68
1102 06:48:02.609449
1103 06:48:02.609860 Set Vref, RX VrefLevel [Byte0]: 69
1104 06:48:02.612985 [Byte1]: 69
1105 06:48:02.616926
1106 06:48:02.617345 Set Vref, RX VrefLevel [Byte0]: 70
1107 06:48:02.620379 [Byte1]: 70
1108 06:48:02.624687
1109 06:48:02.625103 Set Vref, RX VrefLevel [Byte0]: 71
1110 06:48:02.627914 [Byte1]: 71
1111 06:48:02.632475
1112 06:48:02.632890 Set Vref, RX VrefLevel [Byte0]: 72
1113 06:48:02.635637 [Byte1]: 72
1114 06:48:02.640075
1115 06:48:02.640488 Set Vref, RX VrefLevel [Byte0]: 73
1116 06:48:02.643080 [Byte1]: 73
1117 06:48:02.647724
1118 06:48:02.648141 Set Vref, RX VrefLevel [Byte0]: 74
1119 06:48:02.651099 [Byte1]: 74
1120 06:48:02.656038
1121 06:48:02.656551 Set Vref, RX VrefLevel [Byte0]: 75
1122 06:48:02.658418 [Byte1]: 75
1123 06:48:02.663255
1124 06:48:02.663831 Set Vref, RX VrefLevel [Byte0]: 76
1125 06:48:02.666581 [Byte1]: 76
1126 06:48:02.670360
1127 06:48:02.670878 Final RX Vref Byte 0 = 55 to rank0
1128 06:48:02.673775 Final RX Vref Byte 1 = 61 to rank0
1129 06:48:02.677074 Final RX Vref Byte 0 = 55 to rank1
1130 06:48:02.680850 Final RX Vref Byte 1 = 61 to rank1==
1131 06:48:02.684127 Dram Type= 6, Freq= 0, CH_0, rank 0
1132 06:48:02.690327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 06:48:02.690826 ==
1134 06:48:02.691161 DQS Delay:
1135 06:48:02.691531 DQS0 = 0, DQS1 = 0
1136 06:48:02.693635 DQM Delay:
1137 06:48:02.694058 DQM0 = 89, DQM1 = 76
1138 06:48:02.696938 DQ Delay:
1139 06:48:02.700537 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =88
1140 06:48:02.703828 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1141 06:48:02.704291 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
1142 06:48:02.710457 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1143 06:48:02.711100
1144 06:48:02.711497
1145 06:48:02.716781 [DQSOSCAuto] RK0, (LSB)MR18= 0x362f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
1146 06:48:02.720095 CH0 RK0: MR19=606, MR18=362F
1147 06:48:02.726763 CH0_RK0: MR19=0x606, MR18=0x362F, DQSOSC=396, MR23=63, INC=94, DEC=62
1148 06:48:02.727352
1149 06:48:02.730251 ----->DramcWriteLeveling(PI) begin...
1150 06:48:02.730803 ==
1151 06:48:02.733759 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 06:48:02.736839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 06:48:02.737367 ==
1154 06:48:02.740349 Write leveling (Byte 0): 31 => 31
1155 06:48:02.743925 Write leveling (Byte 1): 25 => 25
1156 06:48:02.746987 DramcWriteLeveling(PI) end<-----
1157 06:48:02.747461
1158 06:48:02.747805 ==
1159 06:48:02.750590 Dram Type= 6, Freq= 0, CH_0, rank 1
1160 06:48:02.753861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 06:48:02.754389 ==
1162 06:48:02.757008 [Gating] SW mode calibration
1163 06:48:02.804177 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1164 06:48:02.805103 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1165 06:48:02.805468 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1166 06:48:02.805797 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1167 06:48:02.806267 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1168 06:48:02.806613 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:48:02.806947 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 06:48:02.807273 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:48:02.807627 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 06:48:02.808023 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 06:48:02.848580 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 06:48:02.849078 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 06:48:02.849771 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 06:48:02.850114 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 06:48:02.850426 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 06:48:02.850725 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 06:48:02.851015 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 06:48:02.851297 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 06:48:02.851621 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 06:48:02.851963 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1183 06:48:02.864305 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1184 06:48:02.864853 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 06:48:02.868452 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 06:48:02.868873 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 06:48:02.871022 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 06:48:02.874257 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 06:48:02.881044 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 06:48:02.884600 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1191 06:48:02.887761 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
1192 06:48:02.894104 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1193 06:48:02.898013 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 06:48:02.900671 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 06:48:02.904229 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 06:48:02.910800 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 06:48:02.914467 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 06:48:02.918261 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1199 06:48:02.924876 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
1200 06:48:02.927538 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 06:48:02.930921 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 06:48:02.937440 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 06:48:02.941292 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 06:48:02.944838 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 06:48:02.951430 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 06:48:02.955688 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1207 06:48:02.959676 0 11 8 | B1->B0 | 3434 4545 | 1 0 | (0 0) (0 0)
1208 06:48:02.962593 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 06:48:02.966567 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 06:48:02.972642 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 06:48:02.976258 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 06:48:02.979598 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 06:48:02.986769 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 06:48:02.990200 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1215 06:48:02.993105 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1216 06:48:02.997424 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 06:48:03.003772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 06:48:03.006308 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 06:48:03.010106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 06:48:03.016688 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 06:48:03.019907 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 06:48:03.023579 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 06:48:03.029376 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 06:48:03.033091 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 06:48:03.036412 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 06:48:03.043215 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 06:48:03.046541 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 06:48:03.050078 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 06:48:03.056767 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 06:48:03.059347 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1231 06:48:03.062935 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 06:48:03.066383 Total UI for P1: 0, mck2ui 16
1233 06:48:03.069474 best dqsien dly found for B0: ( 0, 14, 4)
1234 06:48:03.072905 Total UI for P1: 0, mck2ui 16
1235 06:48:03.076205 best dqsien dly found for B1: ( 0, 14, 4)
1236 06:48:03.079068 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1237 06:48:03.082633 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1238 06:48:03.083052
1239 06:48:03.089316 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1240 06:48:03.092757 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1241 06:48:03.093206 [Gating] SW calibration Done
1242 06:48:03.095620 ==
1243 06:48:03.099473 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 06:48:03.102670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1245 06:48:03.103322 ==
1246 06:48:03.103772 RX Vref Scan: 0
1247 06:48:03.104090
1248 06:48:03.105740 RX Vref 0 -> 0, step: 1
1249 06:48:03.106156
1250 06:48:03.109231 RX Delay -130 -> 252, step: 16
1251 06:48:03.113126 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1252 06:48:03.116305 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1253 06:48:03.119257 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1254 06:48:03.125862 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1255 06:48:03.129317 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1256 06:48:03.133116 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1257 06:48:03.135692 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1258 06:48:03.139349 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1259 06:48:03.145794 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1260 06:48:03.149201 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1261 06:48:03.152372 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1262 06:48:03.156131 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1263 06:48:03.159110 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1264 06:48:03.166296 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1265 06:48:03.169088 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1266 06:48:03.172579 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1267 06:48:03.173012 ==
1268 06:48:03.175692 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 06:48:03.178887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 06:48:03.182271 ==
1271 06:48:03.182774 DQS Delay:
1272 06:48:03.183122 DQS0 = 0, DQS1 = 0
1273 06:48:03.186579 DQM Delay:
1274 06:48:03.187107 DQM0 = 83, DQM1 = 76
1275 06:48:03.188865 DQ Delay:
1276 06:48:03.189295 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1277 06:48:03.192543 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1278 06:48:03.195696 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1279 06:48:03.199136 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1280 06:48:03.199619
1281 06:48:03.202629
1282 06:48:03.203049 ==
1283 06:48:03.205733 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 06:48:03.208880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 06:48:03.209385 ==
1286 06:48:03.209727
1287 06:48:03.210040
1288 06:48:03.212254 TX Vref Scan disable
1289 06:48:03.212677 == TX Byte 0 ==
1290 06:48:03.219095 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1291 06:48:03.221956 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1292 06:48:03.222379 == TX Byte 1 ==
1293 06:48:03.228965 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1294 06:48:03.232593 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1295 06:48:03.233019 ==
1296 06:48:03.235469 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 06:48:03.239778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 06:48:03.240308 ==
1299 06:48:03.252919 TX Vref=22, minBit 0, minWin=27, winSum=440
1300 06:48:03.256562 TX Vref=24, minBit 1, minWin=27, winSum=446
1301 06:48:03.259584 TX Vref=26, minBit 0, minWin=27, winSum=448
1302 06:48:03.262949 TX Vref=28, minBit 2, minWin=27, winSum=450
1303 06:48:03.266474 TX Vref=30, minBit 7, minWin=27, winSum=452
1304 06:48:03.272682 TX Vref=32, minBit 2, minWin=27, winSum=451
1305 06:48:03.276101 [TxChooseVref] Worse bit 7, Min win 27, Win sum 452, Final Vref 30
1306 06:48:03.276519
1307 06:48:03.279198 Final TX Range 1 Vref 30
1308 06:48:03.279650
1309 06:48:03.279981 ==
1310 06:48:03.282805 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 06:48:03.286476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 06:48:03.286895 ==
1313 06:48:03.289721
1314 06:48:03.290137
1315 06:48:03.290463 TX Vref Scan disable
1316 06:48:03.293171 == TX Byte 0 ==
1317 06:48:03.296210 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1318 06:48:03.302842 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1319 06:48:03.303265 == TX Byte 1 ==
1320 06:48:03.306055 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1321 06:48:03.312880 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1322 06:48:03.313278
1323 06:48:03.313515 [DATLAT]
1324 06:48:03.313734 Freq=800, CH0 RK1
1325 06:48:03.313946
1326 06:48:03.315989 DATLAT Default: 0xa
1327 06:48:03.316384 0, 0xFFFF, sum = 0
1328 06:48:03.319969 1, 0xFFFF, sum = 0
1329 06:48:03.320368 2, 0xFFFF, sum = 0
1330 06:48:03.322855 3, 0xFFFF, sum = 0
1331 06:48:03.323252 4, 0xFFFF, sum = 0
1332 06:48:03.326324 5, 0xFFFF, sum = 0
1333 06:48:03.329845 6, 0xFFFF, sum = 0
1334 06:48:03.330178 7, 0xFFFF, sum = 0
1335 06:48:03.333173 8, 0xFFFF, sum = 0
1336 06:48:03.333579 9, 0x0, sum = 1
1337 06:48:03.333829 10, 0x0, sum = 2
1338 06:48:03.336474 11, 0x0, sum = 3
1339 06:48:03.336866 12, 0x0, sum = 4
1340 06:48:03.339394 best_step = 10
1341 06:48:03.339821
1342 06:48:03.340149 ==
1343 06:48:03.343222 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 06:48:03.346317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 06:48:03.346860 ==
1346 06:48:03.349432 RX Vref Scan: 0
1347 06:48:03.350052
1348 06:48:03.350398 RX Vref 0 -> 0, step: 1
1349 06:48:03.350710
1350 06:48:03.353193 RX Delay -95 -> 252, step: 8
1351 06:48:03.360214 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1352 06:48:03.363254 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1353 06:48:03.366430 iDelay=209, Bit 2, Center 84 (-23 ~ 192) 216
1354 06:48:03.370092 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1355 06:48:03.372814 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1356 06:48:03.379679 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1357 06:48:03.383260 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1358 06:48:03.386401 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1359 06:48:03.389404 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1360 06:48:03.392659 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1361 06:48:03.399568 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1362 06:48:03.402718 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1363 06:48:03.406291 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1364 06:48:03.409797 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1365 06:48:03.416086 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1366 06:48:03.420037 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1367 06:48:03.420565 ==
1368 06:48:03.422720 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 06:48:03.426269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 06:48:03.426800 ==
1371 06:48:03.427134 DQS Delay:
1372 06:48:03.429307 DQS0 = 0, DQS1 = 0
1373 06:48:03.429721 DQM Delay:
1374 06:48:03.433321 DQM0 = 87, DQM1 = 77
1375 06:48:03.433843 DQ Delay:
1376 06:48:03.435993 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1377 06:48:03.439554 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1378 06:48:03.442884 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1379 06:48:03.445902 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1380 06:48:03.446423
1381 06:48:03.446786
1382 06:48:03.456822 [DQSOSCAuto] RK1, (LSB)MR18= 0x2723, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1383 06:48:03.457355 CH0 RK1: MR19=606, MR18=2723
1384 06:48:03.462808 CH0_RK1: MR19=0x606, MR18=0x2723, DQSOSC=400, MR23=63, INC=92, DEC=61
1385 06:48:03.466005 [RxdqsGatingPostProcess] freq 800
1386 06:48:03.472447 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1387 06:48:03.475951 Pre-setting of DQS Precalculation
1388 06:48:03.479208 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1389 06:48:03.479692 ==
1390 06:48:03.482623 Dram Type= 6, Freq= 0, CH_1, rank 0
1391 06:48:03.485798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 06:48:03.489529 ==
1393 06:48:03.492603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1394 06:48:03.498923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1395 06:48:03.508236 [CA 0] Center 36 (6~67) winsize 62
1396 06:48:03.511850 [CA 1] Center 37 (6~68) winsize 63
1397 06:48:03.515340 [CA 2] Center 35 (5~65) winsize 61
1398 06:48:03.517824 [CA 3] Center 34 (4~65) winsize 62
1399 06:48:03.521348 [CA 4] Center 34 (4~65) winsize 62
1400 06:48:03.524845 [CA 5] Center 34 (3~65) winsize 63
1401 06:48:03.525369
1402 06:48:03.528197 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1403 06:48:03.528741
1404 06:48:03.531204 [CATrainingPosCal] consider 1 rank data
1405 06:48:03.535150 u2DelayCellTimex100 = 270/100 ps
1406 06:48:03.538403 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1407 06:48:03.541373 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1408 06:48:03.547969 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1409 06:48:03.551245 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 06:48:03.554960 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1411 06:48:03.558022 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1412 06:48:03.558446
1413 06:48:03.561523 CA PerBit enable=1, Macro0, CA PI delay=34
1414 06:48:03.561943
1415 06:48:03.565375 [CBTSetCACLKResult] CA Dly = 34
1416 06:48:03.565904 CS Dly: 5 (0~36)
1417 06:48:03.566239 ==
1418 06:48:03.567817 Dram Type= 6, Freq= 0, CH_1, rank 1
1419 06:48:03.574671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 06:48:03.575119 ==
1421 06:48:03.577730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1422 06:48:03.584731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1423 06:48:03.594229 [CA 0] Center 36 (6~67) winsize 62
1424 06:48:03.597528 [CA 1] Center 36 (6~67) winsize 62
1425 06:48:03.601485 [CA 2] Center 34 (4~65) winsize 62
1426 06:48:03.604456 [CA 3] Center 34 (3~65) winsize 63
1427 06:48:03.607905 [CA 4] Center 34 (4~65) winsize 62
1428 06:48:03.611734 [CA 5] Center 33 (3~64) winsize 62
1429 06:48:03.612335
1430 06:48:03.614676 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1431 06:48:03.615113
1432 06:48:03.618772 [CATrainingPosCal] consider 2 rank data
1433 06:48:03.622271 u2DelayCellTimex100 = 270/100 ps
1434 06:48:03.625826 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1435 06:48:03.629197 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1436 06:48:03.633252 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1437 06:48:03.637623 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1438 06:48:03.640690 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1439 06:48:03.645073 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1440 06:48:03.645600
1441 06:48:03.647912 CA PerBit enable=1, Macro0, CA PI delay=33
1442 06:48:03.648352
1443 06:48:03.651222 [CBTSetCACLKResult] CA Dly = 33
1444 06:48:03.651940 CS Dly: 5 (0~37)
1445 06:48:03.652384
1446 06:48:03.654557 ----->DramcWriteLeveling(PI) begin...
1447 06:48:03.655060 ==
1448 06:48:03.657803 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 06:48:03.664040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 06:48:03.664465 ==
1451 06:48:03.667359 Write leveling (Byte 0): 27 => 27
1452 06:48:03.670842 Write leveling (Byte 1): 31 => 31
1453 06:48:03.674193 DramcWriteLeveling(PI) end<-----
1454 06:48:03.674885
1455 06:48:03.675415 ==
1456 06:48:03.677498 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 06:48:03.680862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 06:48:03.681290 ==
1459 06:48:03.684239 [Gating] SW mode calibration
1460 06:48:03.690563 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1461 06:48:03.697668 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1462 06:48:03.700599 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1463 06:48:03.704020 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1464 06:48:03.707358 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 06:48:03.714096 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 06:48:03.717736 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:48:03.720845 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 06:48:03.726773 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 06:48:03.730140 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 06:48:03.733966 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 06:48:03.740174 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 06:48:03.743770 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 06:48:03.746936 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 06:48:03.753654 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 06:48:03.756497 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 06:48:03.760358 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 06:48:03.767035 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 06:48:03.770112 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1479 06:48:03.773363 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1480 06:48:03.780731 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1481 06:48:03.783712 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 06:48:03.787215 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 06:48:03.793359 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 06:48:03.797012 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 06:48:03.800199 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 06:48:03.806905 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 06:48:03.810170 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1488 06:48:03.813373 0 9 8 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 1)
1489 06:48:03.820588 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 06:48:03.823704 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 06:48:03.826875 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 06:48:03.829921 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 06:48:03.837099 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 06:48:03.840056 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1495 06:48:03.843796 0 10 4 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 1)
1496 06:48:03.849888 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 06:48:03.853315 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 06:48:03.857566 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 06:48:03.863059 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 06:48:03.866919 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 06:48:03.869577 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 06:48:03.876259 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 06:48:03.879569 0 11 4 | B1->B0 | 2727 3030 | 1 0 | (0 0) (0 0)
1504 06:48:03.882858 0 11 8 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1505 06:48:03.889547 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 06:48:03.892922 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 06:48:03.895947 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 06:48:03.903476 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 06:48:03.906263 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 06:48:03.909699 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 06:48:03.916624 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1512 06:48:03.919949 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1513 06:48:03.923123 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 06:48:03.929623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 06:48:03.932780 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 06:48:03.936668 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 06:48:03.942917 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 06:48:03.946112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 06:48:03.949267 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 06:48:03.955924 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 06:48:03.959520 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 06:48:03.962769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 06:48:03.969317 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 06:48:03.972639 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 06:48:03.975850 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 06:48:03.982445 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 06:48:03.986067 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1528 06:48:03.988910 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1529 06:48:03.992088 Total UI for P1: 0, mck2ui 16
1530 06:48:03.995791 best dqsien dly found for B0: ( 0, 14, 4)
1531 06:48:04.002245 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 06:48:04.002737 Total UI for P1: 0, mck2ui 16
1533 06:48:04.008892 best dqsien dly found for B1: ( 0, 14, 8)
1534 06:48:04.012468 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1535 06:48:04.015738 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1536 06:48:04.016159
1537 06:48:04.019038 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1538 06:48:04.021978 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1539 06:48:04.025429 [Gating] SW calibration Done
1540 06:48:04.025932 ==
1541 06:48:04.028621 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 06:48:04.032276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 06:48:04.032740 ==
1544 06:48:04.035557 RX Vref Scan: 0
1545 06:48:04.035974
1546 06:48:04.036389 RX Vref 0 -> 0, step: 1
1547 06:48:04.036703
1548 06:48:04.038896 RX Delay -130 -> 252, step: 16
1549 06:48:04.042102 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1550 06:48:04.048719 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1551 06:48:04.052164 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1552 06:48:04.055328 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1553 06:48:04.058716 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1554 06:48:04.062124 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1555 06:48:04.068553 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1556 06:48:04.071992 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1557 06:48:04.075322 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1558 06:48:04.078546 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1559 06:48:04.081722 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1560 06:48:04.089037 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1561 06:48:04.091702 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1562 06:48:04.095230 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1563 06:48:04.098278 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1564 06:48:04.101752 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1565 06:48:04.104779 ==
1566 06:48:04.108289 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 06:48:04.111739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 06:48:04.112161 ==
1569 06:48:04.112491 DQS Delay:
1570 06:48:04.115028 DQS0 = 0, DQS1 = 0
1571 06:48:04.115476 DQM Delay:
1572 06:48:04.118463 DQM0 = 86, DQM1 = 83
1573 06:48:04.118880 DQ Delay:
1574 06:48:04.121512 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1575 06:48:04.124816 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1576 06:48:04.127939 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1577 06:48:04.131502 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1578 06:48:04.132019
1579 06:48:04.132367
1580 06:48:04.132675 ==
1581 06:48:04.134997 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 06:48:04.137821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 06:48:04.138241 ==
1584 06:48:04.138569
1585 06:48:04.138874
1586 06:48:04.141440 TX Vref Scan disable
1587 06:48:04.144942 == TX Byte 0 ==
1588 06:48:04.148375 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1589 06:48:04.151274 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1590 06:48:04.155189 == TX Byte 1 ==
1591 06:48:04.158048 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1592 06:48:04.161295 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1593 06:48:04.161844 ==
1594 06:48:04.164729 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 06:48:04.171248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 06:48:04.171707 ==
1597 06:48:04.183597 TX Vref=22, minBit 2, minWin=27, winSum=444
1598 06:48:04.186729 TX Vref=24, minBit 0, minWin=27, winSum=444
1599 06:48:04.190131 TX Vref=26, minBit 4, minWin=27, winSum=449
1600 06:48:04.193698 TX Vref=28, minBit 1, minWin=27, winSum=453
1601 06:48:04.196895 TX Vref=30, minBit 1, minWin=27, winSum=451
1602 06:48:04.200682 TX Vref=32, minBit 1, minWin=27, winSum=450
1603 06:48:04.206944 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 28
1604 06:48:04.207232
1605 06:48:04.210110 Final TX Range 1 Vref 28
1606 06:48:04.210336
1607 06:48:04.210477 ==
1608 06:48:04.213626 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 06:48:04.217102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 06:48:04.217382 ==
1611 06:48:04.217607
1612 06:48:04.217787
1613 06:48:04.220273 TX Vref Scan disable
1614 06:48:04.223678 == TX Byte 0 ==
1615 06:48:04.226775 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1616 06:48:04.230173 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1617 06:48:04.233325 == TX Byte 1 ==
1618 06:48:04.236957 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1619 06:48:04.239977 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1620 06:48:04.240300
1621 06:48:04.243165 [DATLAT]
1622 06:48:04.243513 Freq=800, CH1 RK0
1623 06:48:04.243768
1624 06:48:04.246414 DATLAT Default: 0xa
1625 06:48:04.246731 0, 0xFFFF, sum = 0
1626 06:48:04.250280 1, 0xFFFF, sum = 0
1627 06:48:04.250684 2, 0xFFFF, sum = 0
1628 06:48:04.253556 3, 0xFFFF, sum = 0
1629 06:48:04.253895 4, 0xFFFF, sum = 0
1630 06:48:04.256682 5, 0xFFFF, sum = 0
1631 06:48:04.257077 6, 0xFFFF, sum = 0
1632 06:48:04.259990 7, 0xFFFF, sum = 0
1633 06:48:04.263632 8, 0xFFFF, sum = 0
1634 06:48:04.263958 9, 0x0, sum = 1
1635 06:48:04.264216 10, 0x0, sum = 2
1636 06:48:04.266385 11, 0x0, sum = 3
1637 06:48:04.266712 12, 0x0, sum = 4
1638 06:48:04.269630 best_step = 10
1639 06:48:04.270089
1640 06:48:04.270530 ==
1641 06:48:04.273230 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 06:48:04.276723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 06:48:04.277139 ==
1644 06:48:04.279885 RX Vref Scan: 1
1645 06:48:04.280384
1646 06:48:04.280716 Set Vref Range= 32 -> 127
1647 06:48:04.281060
1648 06:48:04.283102 RX Vref 32 -> 127, step: 1
1649 06:48:04.283581
1650 06:48:04.286373 RX Delay -95 -> 252, step: 8
1651 06:48:04.286789
1652 06:48:04.290063 Set Vref, RX VrefLevel [Byte0]: 32
1653 06:48:04.293443 [Byte1]: 32
1654 06:48:04.293960
1655 06:48:04.296565 Set Vref, RX VrefLevel [Byte0]: 33
1656 06:48:04.299834 [Byte1]: 33
1657 06:48:04.303408
1658 06:48:04.303829 Set Vref, RX VrefLevel [Byte0]: 34
1659 06:48:04.306858 [Byte1]: 34
1660 06:48:04.311229
1661 06:48:04.311804 Set Vref, RX VrefLevel [Byte0]: 35
1662 06:48:04.314280 [Byte1]: 35
1663 06:48:04.318967
1664 06:48:04.319555 Set Vref, RX VrefLevel [Byte0]: 36
1665 06:48:04.322295 [Byte1]: 36
1666 06:48:04.326602
1667 06:48:04.327112 Set Vref, RX VrefLevel [Byte0]: 37
1668 06:48:04.329521 [Byte1]: 37
1669 06:48:04.333711
1670 06:48:04.334158 Set Vref, RX VrefLevel [Byte0]: 38
1671 06:48:04.337570 [Byte1]: 38
1672 06:48:04.341318
1673 06:48:04.341754 Set Vref, RX VrefLevel [Byte0]: 39
1674 06:48:04.344919 [Byte1]: 39
1675 06:48:04.349137
1676 06:48:04.349768 Set Vref, RX VrefLevel [Byte0]: 40
1677 06:48:04.352641 [Byte1]: 40
1678 06:48:04.356852
1679 06:48:04.357282 Set Vref, RX VrefLevel [Byte0]: 41
1680 06:48:04.359834 [Byte1]: 41
1681 06:48:04.364623
1682 06:48:04.365195 Set Vref, RX VrefLevel [Byte0]: 42
1683 06:48:04.367751 [Byte1]: 42
1684 06:48:04.371820
1685 06:48:04.372253 Set Vref, RX VrefLevel [Byte0]: 43
1686 06:48:04.375675 [Byte1]: 43
1687 06:48:04.379763
1688 06:48:04.380175 Set Vref, RX VrefLevel [Byte0]: 44
1689 06:48:04.383536 [Byte1]: 44
1690 06:48:04.387457
1691 06:48:04.387974 Set Vref, RX VrefLevel [Byte0]: 45
1692 06:48:04.390470 [Byte1]: 45
1693 06:48:04.395068
1694 06:48:04.395639 Set Vref, RX VrefLevel [Byte0]: 46
1695 06:48:04.398050 [Byte1]: 46
1696 06:48:04.402173
1697 06:48:04.402675 Set Vref, RX VrefLevel [Byte0]: 47
1698 06:48:04.405613 [Byte1]: 47
1699 06:48:04.409813
1700 06:48:04.413263 Set Vref, RX VrefLevel [Byte0]: 48
1701 06:48:04.416553 [Byte1]: 48
1702 06:48:04.416992
1703 06:48:04.419644 Set Vref, RX VrefLevel [Byte0]: 49
1704 06:48:04.423320 [Byte1]: 49
1705 06:48:04.423824
1706 06:48:04.426100 Set Vref, RX VrefLevel [Byte0]: 50
1707 06:48:04.430199 [Byte1]: 50
1708 06:48:04.430618
1709 06:48:04.432778 Set Vref, RX VrefLevel [Byte0]: 51
1710 06:48:04.436354 [Byte1]: 51
1711 06:48:04.440364
1712 06:48:04.440780 Set Vref, RX VrefLevel [Byte0]: 52
1713 06:48:04.443252 [Byte1]: 52
1714 06:48:04.448263
1715 06:48:04.448677 Set Vref, RX VrefLevel [Byte0]: 53
1716 06:48:04.451425 [Byte1]: 53
1717 06:48:04.455652
1718 06:48:04.456282 Set Vref, RX VrefLevel [Byte0]: 54
1719 06:48:04.458576 [Byte1]: 54
1720 06:48:04.463301
1721 06:48:04.463841 Set Vref, RX VrefLevel [Byte0]: 55
1722 06:48:04.466178 [Byte1]: 55
1723 06:48:04.470607
1724 06:48:04.471039 Set Vref, RX VrefLevel [Byte0]: 56
1725 06:48:04.473654 [Byte1]: 56
1726 06:48:04.478329
1727 06:48:04.478798 Set Vref, RX VrefLevel [Byte0]: 57
1728 06:48:04.481366 [Byte1]: 57
1729 06:48:04.486219
1730 06:48:04.486908 Set Vref, RX VrefLevel [Byte0]: 58
1731 06:48:04.489649 [Byte1]: 58
1732 06:48:04.493463
1733 06:48:04.493884 Set Vref, RX VrefLevel [Byte0]: 59
1734 06:48:04.496621 [Byte1]: 59
1735 06:48:04.501212
1736 06:48:04.501697 Set Vref, RX VrefLevel [Byte0]: 60
1737 06:48:04.505234 [Byte1]: 60
1738 06:48:04.509474
1739 06:48:04.509992 Set Vref, RX VrefLevel [Byte0]: 61
1740 06:48:04.512102 [Byte1]: 61
1741 06:48:04.516444
1742 06:48:04.516980 Set Vref, RX VrefLevel [Byte0]: 62
1743 06:48:04.519749 [Byte1]: 62
1744 06:48:04.524150
1745 06:48:04.524567 Set Vref, RX VrefLevel [Byte0]: 63
1746 06:48:04.527275 [Byte1]: 63
1747 06:48:04.531248
1748 06:48:04.531785 Set Vref, RX VrefLevel [Byte0]: 64
1749 06:48:04.534843 [Byte1]: 64
1750 06:48:04.539085
1751 06:48:04.539590 Set Vref, RX VrefLevel [Byte0]: 65
1752 06:48:04.542268 [Byte1]: 65
1753 06:48:04.546458
1754 06:48:04.546882 Set Vref, RX VrefLevel [Byte0]: 66
1755 06:48:04.550011 [Byte1]: 66
1756 06:48:04.554328
1757 06:48:04.554744 Set Vref, RX VrefLevel [Byte0]: 67
1758 06:48:04.557358 [Byte1]: 67
1759 06:48:04.561556
1760 06:48:04.561977 Set Vref, RX VrefLevel [Byte0]: 68
1761 06:48:04.564925 [Byte1]: 68
1762 06:48:04.569696
1763 06:48:04.570449 Set Vref, RX VrefLevel [Byte0]: 69
1764 06:48:04.572680 [Byte1]: 69
1765 06:48:04.577039
1766 06:48:04.577494 Set Vref, RX VrefLevel [Byte0]: 70
1767 06:48:04.580133 [Byte1]: 70
1768 06:48:04.584874
1769 06:48:04.585290 Set Vref, RX VrefLevel [Byte0]: 71
1770 06:48:04.588243 [Byte1]: 71
1771 06:48:04.592235
1772 06:48:04.592651 Set Vref, RX VrefLevel [Byte0]: 72
1773 06:48:04.595271 [Byte1]: 72
1774 06:48:04.599789
1775 06:48:04.600409 Set Vref, RX VrefLevel [Byte0]: 73
1776 06:48:04.603070 [Byte1]: 73
1777 06:48:04.608018
1778 06:48:04.608416 Set Vref, RX VrefLevel [Byte0]: 74
1779 06:48:04.610757 [Byte1]: 74
1780 06:48:04.615124
1781 06:48:04.615575 Set Vref, RX VrefLevel [Byte0]: 75
1782 06:48:04.618026 [Byte1]: 75
1783 06:48:04.622700
1784 06:48:04.623292 Final RX Vref Byte 0 = 55 to rank0
1785 06:48:04.626007 Final RX Vref Byte 1 = 54 to rank0
1786 06:48:04.629162 Final RX Vref Byte 0 = 55 to rank1
1787 06:48:04.632617 Final RX Vref Byte 1 = 54 to rank1==
1788 06:48:04.636064 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 06:48:04.642328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 06:48:04.642878 ==
1791 06:48:04.643451 DQS Delay:
1792 06:48:04.643797 DQS0 = 0, DQS1 = 0
1793 06:48:04.646739 DQM Delay:
1794 06:48:04.647233 DQM0 = 84, DQM1 = 80
1795 06:48:04.649323 DQ Delay:
1796 06:48:04.652420 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1797 06:48:04.655625 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1798 06:48:04.658979 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1799 06:48:04.662425 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1800 06:48:04.662869
1801 06:48:04.663198
1802 06:48:04.669292 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1803 06:48:04.672009 CH1 RK0: MR19=606, MR18=1C2F
1804 06:48:04.678733 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1805 06:48:04.679180
1806 06:48:04.682146 ----->DramcWriteLeveling(PI) begin...
1807 06:48:04.682573 ==
1808 06:48:04.685318 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 06:48:04.688662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 06:48:04.689087 ==
1811 06:48:04.692152 Write leveling (Byte 0): 24 => 24
1812 06:48:04.695618 Write leveling (Byte 1): 30 => 30
1813 06:48:04.699142 DramcWriteLeveling(PI) end<-----
1814 06:48:04.699647
1815 06:48:04.699987 ==
1816 06:48:04.701964 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 06:48:04.705655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 06:48:04.706079 ==
1819 06:48:04.709389 [Gating] SW mode calibration
1820 06:48:04.715184 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 06:48:04.722171 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 06:48:04.725699 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1823 06:48:04.729071 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1824 06:48:04.735601 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 06:48:04.738682 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 06:48:04.742114 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 06:48:04.748422 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 06:48:04.751804 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 06:48:04.755433 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 06:48:04.762028 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 06:48:04.765825 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 06:48:04.768702 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 06:48:04.775190 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 06:48:04.778689 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 06:48:04.781609 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 06:48:04.788574 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 06:48:04.791892 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 06:48:04.795120 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1839 06:48:04.801754 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1840 06:48:04.805256 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1841 06:48:04.808417 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 06:48:04.815164 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 06:48:04.818845 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 06:48:04.821641 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 06:48:04.828989 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 06:48:04.832287 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 06:48:04.835521 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1848 06:48:04.841669 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1849 06:48:04.844844 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 06:48:04.848259 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 06:48:04.854820 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 06:48:04.858105 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 06:48:04.861345 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 06:48:04.868088 0 10 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1855 06:48:04.871354 0 10 4 | B1->B0 | 3333 2929 | 1 0 | (1 1) (1 0)
1856 06:48:04.874585 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 06:48:04.878026 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 06:48:04.884634 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 06:48:04.888630 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 06:48:04.891102 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 06:48:04.898134 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 06:48:04.901331 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 06:48:04.904533 0 11 4 | B1->B0 | 2727 3939 | 0 0 | (0 0) (1 1)
1864 06:48:04.911459 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 06:48:04.914314 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 06:48:04.917577 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 06:48:04.924180 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 06:48:04.928445 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 06:48:04.931112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 06:48:04.937750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1871 06:48:04.941266 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1872 06:48:04.944219 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1873 06:48:04.951063 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 06:48:04.954193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 06:48:04.957607 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 06:48:04.964142 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 06:48:04.967543 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 06:48:04.971210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 06:48:04.977441 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 06:48:04.980355 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 06:48:04.983857 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 06:48:04.990671 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 06:48:04.993934 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 06:48:04.997293 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 06:48:05.003858 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 06:48:05.007453 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1887 06:48:05.010597 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1888 06:48:05.014157 Total UI for P1: 0, mck2ui 16
1889 06:48:05.017400 best dqsien dly found for B0: ( 0, 14, 0)
1890 06:48:05.023860 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 06:48:05.024368 Total UI for P1: 0, mck2ui 16
1892 06:48:05.030392 best dqsien dly found for B1: ( 0, 14, 4)
1893 06:48:05.033852 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1894 06:48:05.037107 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1895 06:48:05.037537
1896 06:48:05.040088 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1897 06:48:05.043242 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 06:48:05.046443 [Gating] SW calibration Done
1899 06:48:05.046861 ==
1900 06:48:05.050440 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 06:48:05.053382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 06:48:05.053808 ==
1903 06:48:05.056693 RX Vref Scan: 0
1904 06:48:05.057129
1905 06:48:05.057466 RX Vref 0 -> 0, step: 1
1906 06:48:05.057949
1907 06:48:05.060416 RX Delay -130 -> 252, step: 16
1908 06:48:05.063817 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1909 06:48:05.070312 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1910 06:48:05.073544 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1911 06:48:05.077047 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1912 06:48:05.080143 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1913 06:48:05.083286 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1914 06:48:05.090047 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1915 06:48:05.093127 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1916 06:48:05.096347 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1917 06:48:05.099915 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1918 06:48:05.103040 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1919 06:48:05.109610 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1920 06:48:05.113381 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1921 06:48:05.116563 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1922 06:48:05.119797 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1923 06:48:05.127143 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1924 06:48:05.127703 ==
1925 06:48:05.129757 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 06:48:05.133078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 06:48:05.133769 ==
1928 06:48:05.134197 DQS Delay:
1929 06:48:05.136573 DQS0 = 0, DQS1 = 0
1930 06:48:05.137048 DQM Delay:
1931 06:48:05.139926 DQM0 = 82, DQM1 = 79
1932 06:48:05.140345 DQ Delay:
1933 06:48:05.142851 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1934 06:48:05.146485 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1935 06:48:05.149837 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1936 06:48:05.153349 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1937 06:48:05.153874
1938 06:48:05.154215
1939 06:48:05.154556 ==
1940 06:48:05.156457 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 06:48:05.159473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 06:48:05.159927 ==
1943 06:48:05.160464
1944 06:48:05.160867
1945 06:48:05.162514 TX Vref Scan disable
1946 06:48:05.166342 == TX Byte 0 ==
1947 06:48:05.169665 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1948 06:48:05.172612 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1949 06:48:05.176198 == TX Byte 1 ==
1950 06:48:05.179759 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1951 06:48:05.182708 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1952 06:48:05.183136 ==
1953 06:48:05.185942 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 06:48:05.193174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 06:48:05.193730 ==
1956 06:48:05.205347 TX Vref=22, minBit 2, minWin=26, winSum=441
1957 06:48:05.208372 TX Vref=24, minBit 0, minWin=27, winSum=445
1958 06:48:05.211691 TX Vref=26, minBit 1, minWin=27, winSum=448
1959 06:48:05.214965 TX Vref=28, minBit 0, minWin=28, winSum=455
1960 06:48:05.218488 TX Vref=30, minBit 1, minWin=27, winSum=453
1961 06:48:05.221793 TX Vref=32, minBit 3, minWin=27, winSum=451
1962 06:48:05.228868 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1963 06:48:05.229386
1964 06:48:05.231481 Final TX Range 1 Vref 28
1965 06:48:05.231908
1966 06:48:05.232243 ==
1967 06:48:05.235055 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 06:48:05.238586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 06:48:05.239008 ==
1970 06:48:05.239339
1971 06:48:05.241525
1972 06:48:05.241945 TX Vref Scan disable
1973 06:48:05.245368 == TX Byte 0 ==
1974 06:48:05.248278 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1975 06:48:05.251844 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1976 06:48:05.255228 == TX Byte 1 ==
1977 06:48:05.258644 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1978 06:48:05.261841 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1979 06:48:05.264858
1980 06:48:05.265383 [DATLAT]
1981 06:48:05.265767 Freq=800, CH1 RK1
1982 06:48:05.266106
1983 06:48:05.268295 DATLAT Default: 0xa
1984 06:48:05.268829 0, 0xFFFF, sum = 0
1985 06:48:05.271639 1, 0xFFFF, sum = 0
1986 06:48:05.272082 2, 0xFFFF, sum = 0
1987 06:48:05.274730 3, 0xFFFF, sum = 0
1988 06:48:05.275199 4, 0xFFFF, sum = 0
1989 06:48:05.278121 5, 0xFFFF, sum = 0
1990 06:48:05.281730 6, 0xFFFF, sum = 0
1991 06:48:05.282158 7, 0xFFFF, sum = 0
1992 06:48:05.285162 8, 0xFFFF, sum = 0
1993 06:48:05.285601 9, 0x0, sum = 1
1994 06:48:05.285941 10, 0x0, sum = 2
1995 06:48:05.288139 11, 0x0, sum = 3
1996 06:48:05.288664 12, 0x0, sum = 4
1997 06:48:05.291838 best_step = 10
1998 06:48:05.292392
1999 06:48:05.292726 ==
2000 06:48:05.295121 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 06:48:05.298303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 06:48:05.298743 ==
2003 06:48:05.301814 RX Vref Scan: 0
2004 06:48:05.302252
2005 06:48:05.302685 RX Vref 0 -> 0, step: 1
2006 06:48:05.304818
2007 06:48:05.305333 RX Delay -95 -> 252, step: 8
2008 06:48:05.312090 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2009 06:48:05.315470 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2010 06:48:05.318311 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2011 06:48:05.321537 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2012 06:48:05.324802 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2013 06:48:05.331658 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2014 06:48:05.334589 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2015 06:48:05.337888 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2016 06:48:05.341203 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2017 06:48:05.348131 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2018 06:48:05.351307 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2019 06:48:05.355028 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2020 06:48:05.357649 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2021 06:48:05.361169 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2022 06:48:05.368193 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2023 06:48:05.371163 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2024 06:48:05.371623 ==
2025 06:48:05.374260 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 06:48:05.377871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 06:48:05.378297 ==
2028 06:48:05.381241 DQS Delay:
2029 06:48:05.381662 DQS0 = 0, DQS1 = 0
2030 06:48:05.381998 DQM Delay:
2031 06:48:05.384114 DQM0 = 86, DQM1 = 82
2032 06:48:05.384534 DQ Delay:
2033 06:48:05.387478 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2034 06:48:05.390976 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2035 06:48:05.394544 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =76
2036 06:48:05.397642 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2037 06:48:05.398085
2038 06:48:05.398419
2039 06:48:05.407537 [DQSOSCAuto] RK1, (LSB)MR18= 0x203c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2040 06:48:05.408060 CH1 RK1: MR19=606, MR18=203C
2041 06:48:05.414033 CH1_RK1: MR19=0x606, MR18=0x203C, DQSOSC=394, MR23=63, INC=95, DEC=63
2042 06:48:05.417320 [RxdqsGatingPostProcess] freq 800
2043 06:48:05.424109 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 06:48:05.427905 Pre-setting of DQS Precalculation
2045 06:48:05.430746 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 06:48:05.437482 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 06:48:05.447643 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 06:48:05.448065
2049 06:48:05.448389
2050 06:48:05.451041 [Calibration Summary] 1600 Mbps
2051 06:48:05.451485 CH 0, Rank 0
2052 06:48:05.453866 SW Impedance : PASS
2053 06:48:05.454436 DUTY Scan : NO K
2054 06:48:05.457069 ZQ Calibration : PASS
2055 06:48:05.460452 Jitter Meter : NO K
2056 06:48:05.461043 CBT Training : PASS
2057 06:48:05.463959 Write leveling : PASS
2058 06:48:05.467451 RX DQS gating : PASS
2059 06:48:05.468170 RX DQ/DQS(RDDQC) : PASS
2060 06:48:05.470623 TX DQ/DQS : PASS
2061 06:48:05.471251 RX DATLAT : PASS
2062 06:48:05.474177 RX DQ/DQS(Engine): PASS
2063 06:48:05.476943 TX OE : NO K
2064 06:48:05.477358 All Pass.
2065 06:48:05.477684
2066 06:48:05.478001 CH 0, Rank 1
2067 06:48:05.480522 SW Impedance : PASS
2068 06:48:05.483854 DUTY Scan : NO K
2069 06:48:05.484270 ZQ Calibration : PASS
2070 06:48:05.487670 Jitter Meter : NO K
2071 06:48:05.490911 CBT Training : PASS
2072 06:48:05.491327 Write leveling : PASS
2073 06:48:05.493651 RX DQS gating : PASS
2074 06:48:05.497554 RX DQ/DQS(RDDQC) : PASS
2075 06:48:05.497980 TX DQ/DQS : PASS
2076 06:48:05.500655 RX DATLAT : PASS
2077 06:48:05.503707 RX DQ/DQS(Engine): PASS
2078 06:48:05.504127 TX OE : NO K
2079 06:48:05.507282 All Pass.
2080 06:48:05.507831
2081 06:48:05.508164 CH 1, Rank 0
2082 06:48:05.510461 SW Impedance : PASS
2083 06:48:05.510983 DUTY Scan : NO K
2084 06:48:05.513860 ZQ Calibration : PASS
2085 06:48:05.517572 Jitter Meter : NO K
2086 06:48:05.518114 CBT Training : PASS
2087 06:48:05.520581 Write leveling : PASS
2088 06:48:05.523888 RX DQS gating : PASS
2089 06:48:05.524399 RX DQ/DQS(RDDQC) : PASS
2090 06:48:05.527032 TX DQ/DQS : PASS
2091 06:48:05.527599 RX DATLAT : PASS
2092 06:48:05.530344 RX DQ/DQS(Engine): PASS
2093 06:48:05.533660 TX OE : NO K
2094 06:48:05.534085 All Pass.
2095 06:48:05.534420
2096 06:48:05.534730 CH 1, Rank 1
2097 06:48:05.536923 SW Impedance : PASS
2098 06:48:05.540711 DUTY Scan : NO K
2099 06:48:05.541232 ZQ Calibration : PASS
2100 06:48:05.543240 Jitter Meter : NO K
2101 06:48:05.546827 CBT Training : PASS
2102 06:48:05.547247 Write leveling : PASS
2103 06:48:05.550410 RX DQS gating : PASS
2104 06:48:05.553492 RX DQ/DQS(RDDQC) : PASS
2105 06:48:05.553914 TX DQ/DQS : PASS
2106 06:48:05.556752 RX DATLAT : PASS
2107 06:48:05.559800 RX DQ/DQS(Engine): PASS
2108 06:48:05.560220 TX OE : NO K
2109 06:48:05.563162 All Pass.
2110 06:48:05.563634
2111 06:48:05.563968 DramC Write-DBI off
2112 06:48:05.566758 PER_BANK_REFRESH: Hybrid Mode
2113 06:48:05.567180 TX_TRACKING: ON
2114 06:48:05.570319 [GetDramInforAfterCalByMRR] Vendor 6.
2115 06:48:05.576626 [GetDramInforAfterCalByMRR] Revision 606.
2116 06:48:05.580000 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 06:48:05.580418 MR0 0x3b3b
2118 06:48:05.580823 MR8 0x5151
2119 06:48:05.583279 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 06:48:05.583819
2121 06:48:05.586932 MR0 0x3b3b
2122 06:48:05.587314 MR8 0x5151
2123 06:48:05.590401 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 06:48:05.590814
2125 06:48:05.599932 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 06:48:05.603311 [FAST_K] Save calibration result to emmc
2127 06:48:05.606799 [FAST_K] Save calibration result to emmc
2128 06:48:05.609851 dram_init: config_dvfs: 1
2129 06:48:05.613290 dramc_set_vcore_voltage set vcore to 662500
2130 06:48:05.616920 Read voltage for 1200, 2
2131 06:48:05.617452 Vio18 = 0
2132 06:48:05.617790 Vcore = 662500
2133 06:48:05.620050 Vdram = 0
2134 06:48:05.620493 Vddq = 0
2135 06:48:05.620822 Vmddr = 0
2136 06:48:05.626608 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 06:48:05.629846 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 06:48:05.633476 MEM_TYPE=3, freq_sel=15
2139 06:48:05.636476 sv_algorithm_assistance_LP4_1600
2140 06:48:05.639908 ============ PULL DRAM RESETB DOWN ============
2141 06:48:05.642898 ========== PULL DRAM RESETB DOWN end =========
2142 06:48:05.649510 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 06:48:05.653504 ===================================
2144 06:48:05.654020 LPDDR4 DRAM CONFIGURATION
2145 06:48:05.656105 ===================================
2146 06:48:05.659793 EX_ROW_EN[0] = 0x0
2147 06:48:05.663447 EX_ROW_EN[1] = 0x0
2148 06:48:05.663867 LP4Y_EN = 0x0
2149 06:48:05.666524 WORK_FSP = 0x0
2150 06:48:05.666937 WL = 0x4
2151 06:48:05.669980 RL = 0x4
2152 06:48:05.670394 BL = 0x2
2153 06:48:05.673443 RPST = 0x0
2154 06:48:05.674034 RD_PRE = 0x0
2155 06:48:05.675780 WR_PRE = 0x1
2156 06:48:05.676281 WR_PST = 0x0
2157 06:48:05.679139 DBI_WR = 0x0
2158 06:48:05.679604 DBI_RD = 0x0
2159 06:48:05.682692 OTF = 0x1
2160 06:48:05.685901 ===================================
2161 06:48:05.689554 ===================================
2162 06:48:05.689981 ANA top config
2163 06:48:05.693228 ===================================
2164 06:48:05.696188 DLL_ASYNC_EN = 0
2165 06:48:05.699899 ALL_SLAVE_EN = 0
2166 06:48:05.703016 NEW_RANK_MODE = 1
2167 06:48:05.703482 DLL_IDLE_MODE = 1
2168 06:48:05.706350 LP45_APHY_COMB_EN = 1
2169 06:48:05.709562 TX_ODT_DIS = 1
2170 06:48:05.712980 NEW_8X_MODE = 1
2171 06:48:05.715980 ===================================
2172 06:48:05.719484 ===================================
2173 06:48:05.722693 data_rate = 2400
2174 06:48:05.723221 CKR = 1
2175 06:48:05.726047 DQ_P2S_RATIO = 8
2176 06:48:05.729272 ===================================
2177 06:48:05.732499 CA_P2S_RATIO = 8
2178 06:48:05.735888 DQ_CA_OPEN = 0
2179 06:48:05.738896 DQ_SEMI_OPEN = 0
2180 06:48:05.742245 CA_SEMI_OPEN = 0
2181 06:48:05.742683 CA_FULL_RATE = 0
2182 06:48:05.745964 DQ_CKDIV4_EN = 0
2183 06:48:05.748989 CA_CKDIV4_EN = 0
2184 06:48:05.752419 CA_PREDIV_EN = 0
2185 06:48:05.755521 PH8_DLY = 17
2186 06:48:05.759010 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 06:48:05.759664 DQ_AAMCK_DIV = 4
2188 06:48:05.762540 CA_AAMCK_DIV = 4
2189 06:48:05.766242 CA_ADMCK_DIV = 4
2190 06:48:05.769026 DQ_TRACK_CA_EN = 0
2191 06:48:05.772673 CA_PICK = 1200
2192 06:48:05.776044 CA_MCKIO = 1200
2193 06:48:05.779321 MCKIO_SEMI = 0
2194 06:48:05.779779 PLL_FREQ = 2366
2195 06:48:05.782371 DQ_UI_PI_RATIO = 32
2196 06:48:05.785808 CA_UI_PI_RATIO = 0
2197 06:48:05.788941 ===================================
2198 06:48:05.792343 ===================================
2199 06:48:05.795709 memory_type:LPDDR4
2200 06:48:05.796342 GP_NUM : 10
2201 06:48:05.798761 SRAM_EN : 1
2202 06:48:05.802527 MD32_EN : 0
2203 06:48:05.805781 ===================================
2204 06:48:05.806421 [ANA_INIT] >>>>>>>>>>>>>>
2205 06:48:05.809050 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 06:48:05.812878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 06:48:05.815909 ===================================
2208 06:48:05.819236 data_rate = 2400,PCW = 0X5b00
2209 06:48:05.822757 ===================================
2210 06:48:05.825251 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 06:48:05.832079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 06:48:05.835591 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 06:48:05.841940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 06:48:05.845191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 06:48:05.848955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 06:48:05.851859 [ANA_INIT] flow start
2217 06:48:05.852278 [ANA_INIT] PLL >>>>>>>>
2218 06:48:05.855521 [ANA_INIT] PLL <<<<<<<<
2219 06:48:05.858735 [ANA_INIT] MIDPI >>>>>>>>
2220 06:48:05.859152 [ANA_INIT] MIDPI <<<<<<<<
2221 06:48:05.861811 [ANA_INIT] DLL >>>>>>>>
2222 06:48:05.865076 [ANA_INIT] DLL <<<<<<<<
2223 06:48:05.865505 [ANA_INIT] flow end
2224 06:48:05.871956 ============ LP4 DIFF to SE enter ============
2225 06:48:05.875061 ============ LP4 DIFF to SE exit ============
2226 06:48:05.878649 [ANA_INIT] <<<<<<<<<<<<<
2227 06:48:05.879272 [Flow] Enable top DCM control >>>>>
2228 06:48:05.881751 [Flow] Enable top DCM control <<<<<
2229 06:48:05.884989 Enable DLL master slave shuffle
2230 06:48:05.891615 ==============================================================
2231 06:48:05.895073 Gating Mode config
2232 06:48:05.898085 ==============================================================
2233 06:48:05.901749 Config description:
2234 06:48:05.911841 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 06:48:05.918655 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 06:48:05.921403 SELPH_MODE 0: By rank 1: By Phase
2237 06:48:05.928065 ==============================================================
2238 06:48:05.931887 GAT_TRACK_EN = 1
2239 06:48:05.934865 RX_GATING_MODE = 2
2240 06:48:05.938350 RX_GATING_TRACK_MODE = 2
2241 06:48:05.938772 SELPH_MODE = 1
2242 06:48:05.941411 PICG_EARLY_EN = 1
2243 06:48:05.945040 VALID_LAT_VALUE = 1
2244 06:48:05.951459 ==============================================================
2245 06:48:05.955395 Enter into Gating configuration >>>>
2246 06:48:05.958644 Exit from Gating configuration <<<<
2247 06:48:05.961498 Enter into DVFS_PRE_config >>>>>
2248 06:48:05.971219 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 06:48:05.974912 Exit from DVFS_PRE_config <<<<<
2250 06:48:05.977813 Enter into PICG configuration >>>>
2251 06:48:05.981729 Exit from PICG configuration <<<<
2252 06:48:05.984621 [RX_INPUT] configuration >>>>>
2253 06:48:05.987549 [RX_INPUT] configuration <<<<<
2254 06:48:05.991632 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 06:48:05.997829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 06:48:06.004668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 06:48:06.011230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 06:48:06.017793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 06:48:06.020873 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 06:48:06.027903 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 06:48:06.031123 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 06:48:06.034375 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 06:48:06.037344 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 06:48:06.044115 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 06:48:06.047865 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 06:48:06.051192 ===================================
2267 06:48:06.054389 LPDDR4 DRAM CONFIGURATION
2268 06:48:06.057548 ===================================
2269 06:48:06.058049 EX_ROW_EN[0] = 0x0
2270 06:48:06.060800 EX_ROW_EN[1] = 0x0
2271 06:48:06.061267 LP4Y_EN = 0x0
2272 06:48:06.064021 WORK_FSP = 0x0
2273 06:48:06.064693 WL = 0x4
2274 06:48:06.067236 RL = 0x4
2275 06:48:06.067711 BL = 0x2
2276 06:48:06.070687 RPST = 0x0
2277 06:48:06.071107 RD_PRE = 0x0
2278 06:48:06.073798 WR_PRE = 0x1
2279 06:48:06.074219 WR_PST = 0x0
2280 06:48:06.077195 DBI_WR = 0x0
2281 06:48:06.080856 DBI_RD = 0x0
2282 06:48:06.081276 OTF = 0x1
2283 06:48:06.084024 ===================================
2284 06:48:06.087039 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 06:48:06.090862 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 06:48:06.097339 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 06:48:06.100261 ===================================
2288 06:48:06.103931 LPDDR4 DRAM CONFIGURATION
2289 06:48:06.107318 ===================================
2290 06:48:06.107809 EX_ROW_EN[0] = 0x10
2291 06:48:06.110480 EX_ROW_EN[1] = 0x0
2292 06:48:06.111099 LP4Y_EN = 0x0
2293 06:48:06.113605 WORK_FSP = 0x0
2294 06:48:06.114011 WL = 0x4
2295 06:48:06.117239 RL = 0x4
2296 06:48:06.117706 BL = 0x2
2297 06:48:06.120372 RPST = 0x0
2298 06:48:06.120794 RD_PRE = 0x0
2299 06:48:06.123665 WR_PRE = 0x1
2300 06:48:06.124084 WR_PST = 0x0
2301 06:48:06.127497 DBI_WR = 0x0
2302 06:48:06.128096 DBI_RD = 0x0
2303 06:48:06.130739 OTF = 0x1
2304 06:48:06.133599 ===================================
2305 06:48:06.140586 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 06:48:06.141052 ==
2307 06:48:06.143994 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 06:48:06.147092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 06:48:06.147528 ==
2310 06:48:06.150494 [Duty_Offset_Calibration]
2311 06:48:06.150978 B0:2 B1:0 CA:4
2312 06:48:06.151307
2313 06:48:06.154022 [DutyScan_Calibration_Flow] k_type=0
2314 06:48:06.164078
2315 06:48:06.164499 ==CLK 0==
2316 06:48:06.167020 Final CLK duty delay cell = -4
2317 06:48:06.170249 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2318 06:48:06.173373 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2319 06:48:06.176779 [-4] AVG Duty = 4937%(X100)
2320 06:48:06.177005
2321 06:48:06.179848 CH0 CLK Duty spec in!! Max-Min= 187%
2322 06:48:06.183305 [DutyScan_Calibration_Flow] ====Done====
2323 06:48:06.183630
2324 06:48:06.186520 [DutyScan_Calibration_Flow] k_type=1
2325 06:48:06.202880
2326 06:48:06.203176 ==DQS 0 ==
2327 06:48:06.206464 Final DQS duty delay cell = 0
2328 06:48:06.209780 [0] MAX Duty = 5156%(X100), DQS PI = 18
2329 06:48:06.213224 [0] MIN Duty = 5093%(X100), DQS PI = 2
2330 06:48:06.213591 [0] AVG Duty = 5124%(X100)
2331 06:48:06.216736
2332 06:48:06.217189 ==DQS 1 ==
2333 06:48:06.220584 Final DQS duty delay cell = 0
2334 06:48:06.223424 [0] MAX Duty = 5125%(X100), DQS PI = 50
2335 06:48:06.226232 [0] MIN Duty = 5000%(X100), DQS PI = 0
2336 06:48:06.226674 [0] AVG Duty = 5062%(X100)
2337 06:48:06.229991
2338 06:48:06.233066 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2339 06:48:06.233492
2340 06:48:06.236892 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2341 06:48:06.239932 [DutyScan_Calibration_Flow] ====Done====
2342 06:48:06.240350
2343 06:48:06.243530 [DutyScan_Calibration_Flow] k_type=3
2344 06:48:06.259840
2345 06:48:06.260328 ==DQM 0 ==
2346 06:48:06.263021 Final DQM duty delay cell = 0
2347 06:48:06.266133 [0] MAX Duty = 5094%(X100), DQS PI = 20
2348 06:48:06.269166 [0] MIN Duty = 4844%(X100), DQS PI = 54
2349 06:48:06.272474 [0] AVG Duty = 4969%(X100)
2350 06:48:06.272891
2351 06:48:06.273221 ==DQM 1 ==
2352 06:48:06.276005 Final DQM duty delay cell = 0
2353 06:48:06.279887 [0] MAX Duty = 5000%(X100), DQS PI = 6
2354 06:48:06.282544 [0] MIN Duty = 4875%(X100), DQS PI = 12
2355 06:48:06.286021 [0] AVG Duty = 4937%(X100)
2356 06:48:06.286439
2357 06:48:06.289385 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2358 06:48:06.289877
2359 06:48:06.292923 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2360 06:48:06.296153 [DutyScan_Calibration_Flow] ====Done====
2361 06:48:06.296572
2362 06:48:06.299466 [DutyScan_Calibration_Flow] k_type=2
2363 06:48:06.315993
2364 06:48:06.316512 ==DQ 0 ==
2365 06:48:06.319737 Final DQ duty delay cell = 0
2366 06:48:06.322386 [0] MAX Duty = 5125%(X100), DQS PI = 18
2367 06:48:06.325973 [0] MIN Duty = 5000%(X100), DQS PI = 10
2368 06:48:06.326394 [0] AVG Duty = 5062%(X100)
2369 06:48:06.329435
2370 06:48:06.329851 ==DQ 1 ==
2371 06:48:06.332613 Final DQ duty delay cell = 0
2372 06:48:06.335847 [0] MAX Duty = 5125%(X100), DQS PI = 6
2373 06:48:06.339069 [0] MIN Duty = 4938%(X100), DQS PI = 16
2374 06:48:06.339534 [0] AVG Duty = 5031%(X100)
2375 06:48:06.342421
2376 06:48:06.345733 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2377 06:48:06.346256
2378 06:48:06.349434 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2379 06:48:06.352773 [DutyScan_Calibration_Flow] ====Done====
2380 06:48:06.353294 ==
2381 06:48:06.355531 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 06:48:06.359205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 06:48:06.359677 ==
2384 06:48:06.362156 [Duty_Offset_Calibration]
2385 06:48:06.362571 B0:0 B1:-1 CA:3
2386 06:48:06.362926
2387 06:48:06.365524 [DutyScan_Calibration_Flow] k_type=0
2388 06:48:06.375302
2389 06:48:06.375861 ==CLK 0==
2390 06:48:06.378761 Final CLK duty delay cell = -4
2391 06:48:06.381853 [-4] MAX Duty = 5031%(X100), DQS PI = 44
2392 06:48:06.385708 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2393 06:48:06.388308 [-4] AVG Duty = 4953%(X100)
2394 06:48:06.388780
2395 06:48:06.392074 CH1 CLK Duty spec in!! Max-Min= 155%
2396 06:48:06.395833 [DutyScan_Calibration_Flow] ====Done====
2397 06:48:06.396252
2398 06:48:06.398845 [DutyScan_Calibration_Flow] k_type=1
2399 06:48:06.414755
2400 06:48:06.415274 ==DQS 0 ==
2401 06:48:06.418289 Final DQS duty delay cell = 0
2402 06:48:06.421440 [0] MAX Duty = 5187%(X100), DQS PI = 28
2403 06:48:06.424696 [0] MIN Duty = 4907%(X100), DQS PI = 38
2404 06:48:06.428487 [0] AVG Duty = 5047%(X100)
2405 06:48:06.429025
2406 06:48:06.429387 ==DQS 1 ==
2407 06:48:06.431176 Final DQS duty delay cell = 0
2408 06:48:06.434610 [0] MAX Duty = 5156%(X100), DQS PI = 8
2409 06:48:06.438163 [0] MIN Duty = 5031%(X100), DQS PI = 18
2410 06:48:06.441336 [0] AVG Duty = 5093%(X100)
2411 06:48:06.441757
2412 06:48:06.444974 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2413 06:48:06.445392
2414 06:48:06.448112 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2415 06:48:06.451918 [DutyScan_Calibration_Flow] ====Done====
2416 06:48:06.452442
2417 06:48:06.454696 [DutyScan_Calibration_Flow] k_type=3
2418 06:48:06.471270
2419 06:48:06.471754 ==DQM 0 ==
2420 06:48:06.474959 Final DQM duty delay cell = 0
2421 06:48:06.477796 [0] MAX Duty = 5031%(X100), DQS PI = 26
2422 06:48:06.481120 [0] MIN Duty = 4813%(X100), DQS PI = 38
2423 06:48:06.484647 [0] AVG Duty = 4922%(X100)
2424 06:48:06.485065
2425 06:48:06.485393 ==DQM 1 ==
2426 06:48:06.487958 Final DQM duty delay cell = 0
2427 06:48:06.491526 [0] MAX Duty = 4969%(X100), DQS PI = 32
2428 06:48:06.494762 [0] MIN Duty = 4844%(X100), DQS PI = 0
2429 06:48:06.498231 [0] AVG Duty = 4906%(X100)
2430 06:48:06.498649
2431 06:48:06.501029 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2432 06:48:06.501448
2433 06:48:06.504668 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2434 06:48:06.508076 [DutyScan_Calibration_Flow] ====Done====
2435 06:48:06.508493
2436 06:48:06.511123 [DutyScan_Calibration_Flow] k_type=2
2437 06:48:06.527157
2438 06:48:06.527689 ==DQ 0 ==
2439 06:48:06.530345 Final DQ duty delay cell = -4
2440 06:48:06.533557 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2441 06:48:06.536823 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2442 06:48:06.540749 [-4] AVG Duty = 4953%(X100)
2443 06:48:06.541185
2444 06:48:06.541619 ==DQ 1 ==
2445 06:48:06.543873 Final DQ duty delay cell = 0
2446 06:48:06.546980 [0] MAX Duty = 5031%(X100), DQS PI = 34
2447 06:48:06.550710 [0] MIN Duty = 4844%(X100), DQS PI = 62
2448 06:48:06.553927 [0] AVG Duty = 4937%(X100)
2449 06:48:06.554346
2450 06:48:06.557098 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2451 06:48:06.557540
2452 06:48:06.560441 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2453 06:48:06.563620 [DutyScan_Calibration_Flow] ====Done====
2454 06:48:06.567246 nWR fixed to 30
2455 06:48:06.567776 [ModeRegInit_LP4] CH0 RK0
2456 06:48:06.570379 [ModeRegInit_LP4] CH0 RK1
2457 06:48:06.573953 [ModeRegInit_LP4] CH1 RK0
2458 06:48:06.576988 [ModeRegInit_LP4] CH1 RK1
2459 06:48:06.577423 match AC timing 7
2460 06:48:06.583485 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 06:48:06.587124 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 06:48:06.590140 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 06:48:06.597149 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 06:48:06.600323 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 06:48:06.600838 ==
2466 06:48:06.603956 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 06:48:06.606739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 06:48:06.607161 ==
2469 06:48:06.613570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 06:48:06.620032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 06:48:06.627135 [CA 0] Center 39 (9~70) winsize 62
2472 06:48:06.630627 [CA 1] Center 39 (9~70) winsize 62
2473 06:48:06.634095 [CA 2] Center 35 (5~66) winsize 62
2474 06:48:06.637127 [CA 3] Center 35 (5~66) winsize 62
2475 06:48:06.640758 [CA 4] Center 33 (3~64) winsize 62
2476 06:48:06.643928 [CA 5] Center 33 (3~63) winsize 61
2477 06:48:06.644452
2478 06:48:06.647248 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2479 06:48:06.647717
2480 06:48:06.650491 [CATrainingPosCal] consider 1 rank data
2481 06:48:06.654176 u2DelayCellTimex100 = 270/100 ps
2482 06:48:06.657247 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2483 06:48:06.663491 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2484 06:48:06.666860 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2485 06:48:06.670502 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 06:48:06.673985 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2487 06:48:06.677268 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2488 06:48:06.677863
2489 06:48:06.680659 CA PerBit enable=1, Macro0, CA PI delay=33
2490 06:48:06.681079
2491 06:48:06.683691 [CBTSetCACLKResult] CA Dly = 33
2492 06:48:06.684225 CS Dly: 7 (0~38)
2493 06:48:06.687232 ==
2494 06:48:06.690385 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 06:48:06.694239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 06:48:06.694728 ==
2497 06:48:06.696938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 06:48:06.703421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2499 06:48:06.712982 [CA 0] Center 39 (9~70) winsize 62
2500 06:48:06.716872 [CA 1] Center 39 (9~70) winsize 62
2501 06:48:06.719737 [CA 2] Center 35 (5~66) winsize 62
2502 06:48:06.723068 [CA 3] Center 35 (5~66) winsize 62
2503 06:48:06.726169 [CA 4] Center 34 (4~65) winsize 62
2504 06:48:06.729734 [CA 5] Center 33 (3~64) winsize 62
2505 06:48:06.730141
2506 06:48:06.732901 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2507 06:48:06.733409
2508 06:48:06.736477 [CATrainingPosCal] consider 2 rank data
2509 06:48:06.739544 u2DelayCellTimex100 = 270/100 ps
2510 06:48:06.742837 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2511 06:48:06.746196 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2512 06:48:06.752878 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 06:48:06.756158 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 06:48:06.759051 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2515 06:48:06.762629 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2516 06:48:06.762774
2517 06:48:06.765786 CA PerBit enable=1, Macro0, CA PI delay=33
2518 06:48:06.765924
2519 06:48:06.769556 [CBTSetCACLKResult] CA Dly = 33
2520 06:48:06.769684 CS Dly: 8 (0~41)
2521 06:48:06.769784
2522 06:48:06.775830 ----->DramcWriteLeveling(PI) begin...
2523 06:48:06.775938 ==
2524 06:48:06.779185 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 06:48:06.782569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 06:48:06.782675 ==
2527 06:48:06.785541 Write leveling (Byte 0): 31 => 31
2528 06:48:06.788859 Write leveling (Byte 1): 26 => 26
2529 06:48:06.792877 DramcWriteLeveling(PI) end<-----
2530 06:48:06.792986
2531 06:48:06.793058 ==
2532 06:48:06.795758 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 06:48:06.799301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 06:48:06.799450 ==
2535 06:48:06.802062 [Gating] SW mode calibration
2536 06:48:06.809205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 06:48:06.815429 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 06:48:06.818517 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2539 06:48:06.822214 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2540 06:48:06.828742 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 06:48:06.831855 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 06:48:06.835171 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 06:48:06.842069 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 06:48:06.845834 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2545 06:48:06.848517 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2546 06:48:06.852020 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2547 06:48:06.858710 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 06:48:06.861939 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 06:48:06.865272 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 06:48:06.871970 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 06:48:06.875370 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 06:48:06.878732 1 0 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
2553 06:48:06.885367 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2554 06:48:06.888666 1 1 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2555 06:48:06.892009 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 06:48:06.898362 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 06:48:06.901812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 06:48:06.905250 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 06:48:06.911389 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 06:48:06.914806 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2561 06:48:06.917955 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 06:48:06.925136 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2563 06:48:06.928599 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 06:48:06.931523 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 06:48:06.938396 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 06:48:06.941585 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 06:48:06.945172 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 06:48:06.951229 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 06:48:06.954582 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 06:48:06.958058 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 06:48:06.964625 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 06:48:06.967786 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 06:48:06.971463 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 06:48:06.978361 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 06:48:06.981198 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 06:48:06.984671 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 06:48:06.991079 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 06:48:06.994693 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2579 06:48:06.998231 Total UI for P1: 0, mck2ui 16
2580 06:48:07.001122 best dqsien dly found for B0: ( 1, 3, 26)
2581 06:48:07.004734 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 06:48:07.008417 Total UI for P1: 0, mck2ui 16
2583 06:48:07.011275 best dqsien dly found for B1: ( 1, 4, 0)
2584 06:48:07.014943 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2585 06:48:07.018515 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2586 06:48:07.018588
2587 06:48:07.021269 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2588 06:48:07.028068 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2589 06:48:07.028171 [Gating] SW calibration Done
2590 06:48:07.028262 ==
2591 06:48:07.031135 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 06:48:07.037711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 06:48:07.037786 ==
2594 06:48:07.037852 RX Vref Scan: 0
2595 06:48:07.037909
2596 06:48:07.041101 RX Vref 0 -> 0, step: 1
2597 06:48:07.041176
2598 06:48:07.044442 RX Delay -40 -> 252, step: 8
2599 06:48:07.047951 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2600 06:48:07.051246 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2601 06:48:07.054441 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2602 06:48:07.060950 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2603 06:48:07.064475 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2604 06:48:07.067747 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2605 06:48:07.070778 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2606 06:48:07.073927 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2607 06:48:07.080880 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2608 06:48:07.083988 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2609 06:48:07.087064 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2610 06:48:07.090589 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2611 06:48:07.093967 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2612 06:48:07.100431 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2613 06:48:07.103911 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2614 06:48:07.107244 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2615 06:48:07.107344 ==
2616 06:48:07.110575 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 06:48:07.113646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 06:48:07.113718 ==
2619 06:48:07.117217 DQS Delay:
2620 06:48:07.117290 DQS0 = 0, DQS1 = 0
2621 06:48:07.120559 DQM Delay:
2622 06:48:07.120632 DQM0 = 117, DQM1 = 108
2623 06:48:07.123624 DQ Delay:
2624 06:48:07.126897 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2625 06:48:07.130697 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2626 06:48:07.134025 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2627 06:48:07.136702 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2628 06:48:07.136774
2629 06:48:07.136833
2630 06:48:07.136891 ==
2631 06:48:07.140842 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 06:48:07.143658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 06:48:07.143734 ==
2634 06:48:07.143795
2635 06:48:07.143857
2636 06:48:07.146822 TX Vref Scan disable
2637 06:48:07.150391 == TX Byte 0 ==
2638 06:48:07.153290 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2639 06:48:07.156871 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2640 06:48:07.160377 == TX Byte 1 ==
2641 06:48:07.163268 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2642 06:48:07.167314 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2643 06:48:07.167429 ==
2644 06:48:07.170410 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 06:48:07.176547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 06:48:07.176629 ==
2647 06:48:07.187334 TX Vref=22, minBit 3, minWin=24, winSum=409
2648 06:48:07.190809 TX Vref=24, minBit 4, minWin=25, winSum=415
2649 06:48:07.193762 TX Vref=26, minBit 1, minWin=25, winSum=420
2650 06:48:07.197146 TX Vref=28, minBit 3, minWin=26, winSum=427
2651 06:48:07.200700 TX Vref=30, minBit 1, minWin=26, winSum=429
2652 06:48:07.207842 TX Vref=32, minBit 5, minWin=25, winSum=424
2653 06:48:07.210398 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
2654 06:48:07.210474
2655 06:48:07.213742 Final TX Range 1 Vref 30
2656 06:48:07.213816
2657 06:48:07.213887 ==
2658 06:48:07.217296 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 06:48:07.220458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 06:48:07.223736 ==
2661 06:48:07.223810
2662 06:48:07.223871
2663 06:48:07.223928 TX Vref Scan disable
2664 06:48:07.226984 == TX Byte 0 ==
2665 06:48:07.230617 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2666 06:48:07.233714 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2667 06:48:07.236995 == TX Byte 1 ==
2668 06:48:07.240445 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2669 06:48:07.243751 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2670 06:48:07.247555
2671 06:48:07.247660 [DATLAT]
2672 06:48:07.247751 Freq=1200, CH0 RK0
2673 06:48:07.247838
2674 06:48:07.250579 DATLAT Default: 0xd
2675 06:48:07.250648 0, 0xFFFF, sum = 0
2676 06:48:07.253847 1, 0xFFFF, sum = 0
2677 06:48:07.253925 2, 0xFFFF, sum = 0
2678 06:48:07.257032 3, 0xFFFF, sum = 0
2679 06:48:07.257111 4, 0xFFFF, sum = 0
2680 06:48:07.260402 5, 0xFFFF, sum = 0
2681 06:48:07.260478 6, 0xFFFF, sum = 0
2682 06:48:07.264091 7, 0xFFFF, sum = 0
2683 06:48:07.267317 8, 0xFFFF, sum = 0
2684 06:48:07.267443 9, 0xFFFF, sum = 0
2685 06:48:07.270326 10, 0xFFFF, sum = 0
2686 06:48:07.270435 11, 0xFFFF, sum = 0
2687 06:48:07.273962 12, 0x0, sum = 1
2688 06:48:07.274036 13, 0x0, sum = 2
2689 06:48:07.277277 14, 0x0, sum = 3
2690 06:48:07.277353 15, 0x0, sum = 4
2691 06:48:07.277415 best_step = 13
2692 06:48:07.277472
2693 06:48:07.280181 ==
2694 06:48:07.283711 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 06:48:07.286933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 06:48:07.287031 ==
2697 06:48:07.287121 RX Vref Scan: 1
2698 06:48:07.287210
2699 06:48:07.290355 Set Vref Range= 32 -> 127
2700 06:48:07.290453
2701 06:48:07.293568 RX Vref 32 -> 127, step: 1
2702 06:48:07.293642
2703 06:48:07.297107 RX Delay -21 -> 252, step: 4
2704 06:48:07.297180
2705 06:48:07.300715 Set Vref, RX VrefLevel [Byte0]: 32
2706 06:48:07.304290 [Byte1]: 32
2707 06:48:07.304387
2708 06:48:07.307055 Set Vref, RX VrefLevel [Byte0]: 33
2709 06:48:07.310140 [Byte1]: 33
2710 06:48:07.313424
2711 06:48:07.313501 Set Vref, RX VrefLevel [Byte0]: 34
2712 06:48:07.316688 [Byte1]: 34
2713 06:48:07.321228
2714 06:48:07.321315 Set Vref, RX VrefLevel [Byte0]: 35
2715 06:48:07.324467 [Byte1]: 35
2716 06:48:07.329116
2717 06:48:07.329187 Set Vref, RX VrefLevel [Byte0]: 36
2718 06:48:07.332849 [Byte1]: 36
2719 06:48:07.337045
2720 06:48:07.340678 Set Vref, RX VrefLevel [Byte0]: 37
2721 06:48:07.343564 [Byte1]: 37
2722 06:48:07.343640
2723 06:48:07.347510 Set Vref, RX VrefLevel [Byte0]: 38
2724 06:48:07.350189 [Byte1]: 38
2725 06:48:07.350259
2726 06:48:07.353653 Set Vref, RX VrefLevel [Byte0]: 39
2727 06:48:07.356778 [Byte1]: 39
2728 06:48:07.360881
2729 06:48:07.360954 Set Vref, RX VrefLevel [Byte0]: 40
2730 06:48:07.364189 [Byte1]: 40
2731 06:48:07.368826
2732 06:48:07.368924 Set Vref, RX VrefLevel [Byte0]: 41
2733 06:48:07.372413 [Byte1]: 41
2734 06:48:07.376786
2735 06:48:07.376864 Set Vref, RX VrefLevel [Byte0]: 42
2736 06:48:07.380334 [Byte1]: 42
2737 06:48:07.385380
2738 06:48:07.385462 Set Vref, RX VrefLevel [Byte0]: 43
2739 06:48:07.387983 [Byte1]: 43
2740 06:48:07.393001
2741 06:48:07.393078 Set Vref, RX VrefLevel [Byte0]: 44
2742 06:48:07.396671 [Byte1]: 44
2743 06:48:07.400719
2744 06:48:07.400797 Set Vref, RX VrefLevel [Byte0]: 45
2745 06:48:07.404242 [Byte1]: 45
2746 06:48:07.408515
2747 06:48:07.408592 Set Vref, RX VrefLevel [Byte0]: 46
2748 06:48:07.411836 [Byte1]: 46
2749 06:48:07.416279
2750 06:48:07.416355 Set Vref, RX VrefLevel [Byte0]: 47
2751 06:48:07.419691 [Byte1]: 47
2752 06:48:07.424455
2753 06:48:07.424535 Set Vref, RX VrefLevel [Byte0]: 48
2754 06:48:07.427997 [Byte1]: 48
2755 06:48:07.432244
2756 06:48:07.432322 Set Vref, RX VrefLevel [Byte0]: 49
2757 06:48:07.435564 [Byte1]: 49
2758 06:48:07.440225
2759 06:48:07.440301 Set Vref, RX VrefLevel [Byte0]: 50
2760 06:48:07.443685 [Byte1]: 50
2761 06:48:07.448346
2762 06:48:07.448424 Set Vref, RX VrefLevel [Byte0]: 51
2763 06:48:07.451557 [Byte1]: 51
2764 06:48:07.456700
2765 06:48:07.456776 Set Vref, RX VrefLevel [Byte0]: 52
2766 06:48:07.459284 [Byte1]: 52
2767 06:48:07.464177
2768 06:48:07.464255 Set Vref, RX VrefLevel [Byte0]: 53
2769 06:48:07.467359 [Byte1]: 53
2770 06:48:07.472748
2771 06:48:07.472831 Set Vref, RX VrefLevel [Byte0]: 54
2772 06:48:07.475188 [Byte1]: 54
2773 06:48:07.479894
2774 06:48:07.479973 Set Vref, RX VrefLevel [Byte0]: 55
2775 06:48:07.483098 [Byte1]: 55
2776 06:48:07.487973
2777 06:48:07.488079 Set Vref, RX VrefLevel [Byte0]: 56
2778 06:48:07.491029 [Byte1]: 56
2779 06:48:07.495741
2780 06:48:07.495820 Set Vref, RX VrefLevel [Byte0]: 57
2781 06:48:07.499557 [Byte1]: 57
2782 06:48:07.504210
2783 06:48:07.504287 Set Vref, RX VrefLevel [Byte0]: 58
2784 06:48:07.506869 [Byte1]: 58
2785 06:48:07.511851
2786 06:48:07.511928 Set Vref, RX VrefLevel [Byte0]: 59
2787 06:48:07.514926 [Byte1]: 59
2788 06:48:07.519869
2789 06:48:07.519946 Set Vref, RX VrefLevel [Byte0]: 60
2790 06:48:07.522797 [Byte1]: 60
2791 06:48:07.527348
2792 06:48:07.527468 Set Vref, RX VrefLevel [Byte0]: 61
2793 06:48:07.530869 [Byte1]: 61
2794 06:48:07.535764
2795 06:48:07.535839 Set Vref, RX VrefLevel [Byte0]: 62
2796 06:48:07.538769 [Byte1]: 62
2797 06:48:07.543549
2798 06:48:07.543618 Set Vref, RX VrefLevel [Byte0]: 63
2799 06:48:07.546714 [Byte1]: 63
2800 06:48:07.551513
2801 06:48:07.551587 Set Vref, RX VrefLevel [Byte0]: 64
2802 06:48:07.554891 [Byte1]: 64
2803 06:48:07.559956
2804 06:48:07.560031 Set Vref, RX VrefLevel [Byte0]: 65
2805 06:48:07.562538 [Byte1]: 65
2806 06:48:07.567391
2807 06:48:07.567474 Set Vref, RX VrefLevel [Byte0]: 66
2808 06:48:07.570354 [Byte1]: 66
2809 06:48:07.575002
2810 06:48:07.575091 Set Vref, RX VrefLevel [Byte0]: 67
2811 06:48:07.578049 [Byte1]: 67
2812 06:48:07.583102
2813 06:48:07.583203 Set Vref, RX VrefLevel [Byte0]: 68
2814 06:48:07.586374 [Byte1]: 68
2815 06:48:07.590774
2816 06:48:07.590849 Final RX Vref Byte 0 = 52 to rank0
2817 06:48:07.594614 Final RX Vref Byte 1 = 49 to rank0
2818 06:48:07.597609 Final RX Vref Byte 0 = 52 to rank1
2819 06:48:07.600836 Final RX Vref Byte 1 = 49 to rank1==
2820 06:48:07.604295 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 06:48:07.610861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 06:48:07.610939 ==
2823 06:48:07.611003 DQS Delay:
2824 06:48:07.611063 DQS0 = 0, DQS1 = 0
2825 06:48:07.614056 DQM Delay:
2826 06:48:07.614156 DQM0 = 117, DQM1 = 104
2827 06:48:07.617428 DQ Delay:
2828 06:48:07.620569 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2829 06:48:07.624255 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2830 06:48:07.627456 DQ8 =92, DQ9 =88, DQ10 =104, DQ11 =98
2831 06:48:07.631061 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =112
2832 06:48:07.631136
2833 06:48:07.631197
2834 06:48:07.637205 [DQSOSCAuto] RK0, (LSB)MR18= 0x601, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
2835 06:48:07.640454 CH0 RK0: MR19=404, MR18=601
2836 06:48:07.647580 CH0_RK0: MR19=0x404, MR18=0x601, DQSOSC=407, MR23=63, INC=39, DEC=26
2837 06:48:07.647682
2838 06:48:07.650431 ----->DramcWriteLeveling(PI) begin...
2839 06:48:07.650534 ==
2840 06:48:07.654021 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 06:48:07.657070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 06:48:07.657144 ==
2843 06:48:07.660792 Write leveling (Byte 0): 33 => 33
2844 06:48:07.664197 Write leveling (Byte 1): 28 => 28
2845 06:48:07.667372 DramcWriteLeveling(PI) end<-----
2846 06:48:07.667480
2847 06:48:07.667541 ==
2848 06:48:07.670627 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 06:48:07.677151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 06:48:07.677230 ==
2851 06:48:07.677293 [Gating] SW mode calibration
2852 06:48:07.687336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 06:48:07.690825 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 06:48:07.693630 0 15 0 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
2855 06:48:07.700537 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 06:48:07.703997 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 06:48:07.707021 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 06:48:07.713946 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 06:48:07.716861 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 06:48:07.720135 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2861 06:48:07.726869 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
2862 06:48:07.730511 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2863 06:48:07.733737 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 06:48:07.740367 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 06:48:07.743592 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 06:48:07.746807 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 06:48:07.753534 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 06:48:07.757318 1 0 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2869 06:48:07.760839 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2870 06:48:07.766767 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2871 06:48:07.770235 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 06:48:07.773375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 06:48:07.780450 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 06:48:07.783566 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 06:48:07.786939 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 06:48:07.794109 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2877 06:48:07.796840 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2878 06:48:07.800120 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2879 06:48:07.806949 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 06:48:07.810286 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 06:48:07.813634 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 06:48:07.816899 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 06:48:07.823420 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 06:48:07.826991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 06:48:07.829851 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 06:48:07.836662 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 06:48:07.839864 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 06:48:07.843018 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 06:48:07.850055 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 06:48:07.853354 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 06:48:07.856971 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 06:48:07.863211 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2893 06:48:07.866397 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 06:48:07.869869 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 06:48:07.873092 Total UI for P1: 0, mck2ui 16
2896 06:48:07.876445 best dqsien dly found for B0: ( 1, 3, 26)
2897 06:48:07.883521 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 06:48:07.883595 Total UI for P1: 0, mck2ui 16
2899 06:48:07.890152 best dqsien dly found for B1: ( 1, 4, 0)
2900 06:48:07.893065 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2901 06:48:07.896538 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2902 06:48:07.896608
2903 06:48:07.899925 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2904 06:48:07.903219 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2905 06:48:07.906417 [Gating] SW calibration Done
2906 06:48:07.906493 ==
2907 06:48:07.909587 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 06:48:07.913097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 06:48:07.913174 ==
2910 06:48:07.916430 RX Vref Scan: 0
2911 06:48:07.916518
2912 06:48:07.916582 RX Vref 0 -> 0, step: 1
2913 06:48:07.916639
2914 06:48:07.919672 RX Delay -40 -> 252, step: 8
2915 06:48:07.923252 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2916 06:48:07.929609 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2917 06:48:07.933180 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2918 06:48:07.936832 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2919 06:48:07.939650 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2920 06:48:07.943174 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2921 06:48:07.949581 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2922 06:48:07.953113 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2923 06:48:07.956184 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2924 06:48:07.959751 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2925 06:48:07.962874 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2926 06:48:07.969399 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2927 06:48:07.972864 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2928 06:48:07.976271 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2929 06:48:07.979479 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2930 06:48:07.982960 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2931 06:48:07.983036 ==
2932 06:48:07.986493 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 06:48:07.993021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 06:48:07.993101 ==
2935 06:48:07.993164 DQS Delay:
2936 06:48:07.996195 DQS0 = 0, DQS1 = 0
2937 06:48:07.996268 DQM Delay:
2938 06:48:07.999485 DQM0 = 116, DQM1 = 106
2939 06:48:07.999555 DQ Delay:
2940 06:48:08.002863 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2941 06:48:08.006649 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2942 06:48:08.009638 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2943 06:48:08.012739 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2944 06:48:08.012816
2945 06:48:08.012875
2946 06:48:08.012933 ==
2947 06:48:08.016207 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 06:48:08.019661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 06:48:08.022978 ==
2950 06:48:08.023052
2951 06:48:08.023114
2952 06:48:08.023171 TX Vref Scan disable
2953 06:48:08.026514 == TX Byte 0 ==
2954 06:48:08.029664 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2955 06:48:08.033149 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2956 06:48:08.036059 == TX Byte 1 ==
2957 06:48:08.039328 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2958 06:48:08.042854 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2959 06:48:08.046024 ==
2960 06:48:08.046100 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 06:48:08.052484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 06:48:08.052559 ==
2963 06:48:08.064310 TX Vref=22, minBit 1, minWin=26, winSum=422
2964 06:48:08.067194 TX Vref=24, minBit 1, minWin=26, winSum=426
2965 06:48:08.070876 TX Vref=26, minBit 14, minWin=26, winSum=431
2966 06:48:08.073881 TX Vref=28, minBit 12, minWin=26, winSum=431
2967 06:48:08.077227 TX Vref=30, minBit 12, minWin=26, winSum=433
2968 06:48:08.084322 TX Vref=32, minBit 5, minWin=26, winSum=429
2969 06:48:08.087432 [TxChooseVref] Worse bit 12, Min win 26, Win sum 433, Final Vref 30
2970 06:48:08.087507
2971 06:48:08.090466 Final TX Range 1 Vref 30
2972 06:48:08.090547
2973 06:48:08.090611 ==
2974 06:48:08.093488 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 06:48:08.100402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 06:48:08.100477 ==
2977 06:48:08.100543
2978 06:48:08.100603
2979 06:48:08.100658 TX Vref Scan disable
2980 06:48:08.104196 == TX Byte 0 ==
2981 06:48:08.107643 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2982 06:48:08.114411 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2983 06:48:08.114485 == TX Byte 1 ==
2984 06:48:08.117396 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2985 06:48:08.124310 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2986 06:48:08.124414
2987 06:48:08.124507 [DATLAT]
2988 06:48:08.124595 Freq=1200, CH0 RK1
2989 06:48:08.124680
2990 06:48:08.127709 DATLAT Default: 0xd
2991 06:48:08.127808 0, 0xFFFF, sum = 0
2992 06:48:08.130864 1, 0xFFFF, sum = 0
2993 06:48:08.133905 2, 0xFFFF, sum = 0
2994 06:48:08.134032 3, 0xFFFF, sum = 0
2995 06:48:08.137491 4, 0xFFFF, sum = 0
2996 06:48:08.137584 5, 0xFFFF, sum = 0
2997 06:48:08.140530 6, 0xFFFF, sum = 0
2998 06:48:08.140606 7, 0xFFFF, sum = 0
2999 06:48:08.144331 8, 0xFFFF, sum = 0
3000 06:48:08.144406 9, 0xFFFF, sum = 0
3001 06:48:08.147052 10, 0xFFFF, sum = 0
3002 06:48:08.147127 11, 0xFFFF, sum = 0
3003 06:48:08.150682 12, 0x0, sum = 1
3004 06:48:08.150785 13, 0x0, sum = 2
3005 06:48:08.153987 14, 0x0, sum = 3
3006 06:48:08.154090 15, 0x0, sum = 4
3007 06:48:08.157717 best_step = 13
3008 06:48:08.157813
3009 06:48:08.157903 ==
3010 06:48:08.160720 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 06:48:08.164121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 06:48:08.164197 ==
3013 06:48:08.164259 RX Vref Scan: 0
3014 06:48:08.164317
3015 06:48:08.167480 RX Vref 0 -> 0, step: 1
3016 06:48:08.167578
3017 06:48:08.170470 RX Delay -21 -> 252, step: 4
3018 06:48:08.177574 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3019 06:48:08.180372 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3020 06:48:08.183544 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3021 06:48:08.187270 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3022 06:48:08.190370 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3023 06:48:08.193605 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3024 06:48:08.200121 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3025 06:48:08.203641 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3026 06:48:08.207101 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3027 06:48:08.210637 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3028 06:48:08.213412 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3029 06:48:08.220470 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3030 06:48:08.223421 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3031 06:48:08.227397 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3032 06:48:08.230421 iDelay=195, Bit 14, Center 118 (51 ~ 186) 136
3033 06:48:08.236605 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3034 06:48:08.236686 ==
3035 06:48:08.240052 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 06:48:08.243497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 06:48:08.243579 ==
3038 06:48:08.243643 DQS Delay:
3039 06:48:08.246891 DQS0 = 0, DQS1 = 0
3040 06:48:08.246986 DQM Delay:
3041 06:48:08.250353 DQM0 = 115, DQM1 = 105
3042 06:48:08.250433 DQ Delay:
3043 06:48:08.253304 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3044 06:48:08.256704 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3045 06:48:08.259768 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3046 06:48:08.263217 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3047 06:48:08.263319
3048 06:48:08.263451
3049 06:48:08.273095 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3050 06:48:08.273200 CH0 RK1: MR19=403, MR18=FC
3051 06:48:08.279676 CH0_RK1: MR19=0x403, MR18=0xFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3052 06:48:08.282862 [RxdqsGatingPostProcess] freq 1200
3053 06:48:08.289715 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 06:48:08.293032 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 06:48:08.296521 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 06:48:08.299653 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 06:48:08.303264 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 06:48:08.306672 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 06:48:08.306748 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 06:48:08.309725 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 06:48:08.312861 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 06:48:08.316556 Pre-setting of DQS Precalculation
3063 06:48:08.323083 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 06:48:08.323175 ==
3065 06:48:08.326061 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 06:48:08.329463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 06:48:08.329544 ==
3068 06:48:08.336149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 06:48:08.342663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3070 06:48:08.350037 [CA 0] Center 38 (8~68) winsize 61
3071 06:48:08.352962 [CA 1] Center 37 (7~68) winsize 62
3072 06:48:08.356771 [CA 2] Center 35 (5~65) winsize 61
3073 06:48:08.359744 [CA 3] Center 34 (4~64) winsize 61
3074 06:48:08.363153 [CA 4] Center 34 (4~65) winsize 62
3075 06:48:08.366189 [CA 5] Center 33 (4~63) winsize 60
3076 06:48:08.366291
3077 06:48:08.369819 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3078 06:48:08.369904
3079 06:48:08.373340 [CATrainingPosCal] consider 1 rank data
3080 06:48:08.376273 u2DelayCellTimex100 = 270/100 ps
3081 06:48:08.379782 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3082 06:48:08.386481 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 06:48:08.389866 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3084 06:48:08.393140 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 06:48:08.396219 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3086 06:48:08.399552 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3087 06:48:08.399663
3088 06:48:08.402891 CA PerBit enable=1, Macro0, CA PI delay=33
3089 06:48:08.402993
3090 06:48:08.406237 [CBTSetCACLKResult] CA Dly = 33
3091 06:48:08.406316 CS Dly: 5 (0~36)
3092 06:48:08.409699 ==
3093 06:48:08.413233 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 06:48:08.416088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 06:48:08.416163 ==
3096 06:48:08.419733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 06:48:08.426560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3098 06:48:08.435841 [CA 0] Center 37 (7~68) winsize 62
3099 06:48:08.438733 [CA 1] Center 38 (8~68) winsize 61
3100 06:48:08.442735 [CA 2] Center 34 (4~65) winsize 62
3101 06:48:08.445816 [CA 3] Center 33 (3~64) winsize 62
3102 06:48:08.448474 [CA 4] Center 34 (4~64) winsize 61
3103 06:48:08.451887 [CA 5] Center 33 (3~63) winsize 61
3104 06:48:08.451987
3105 06:48:08.455173 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3106 06:48:08.455277
3107 06:48:08.458712 [CATrainingPosCal] consider 2 rank data
3108 06:48:08.461811 u2DelayCellTimex100 = 270/100 ps
3109 06:48:08.465060 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3110 06:48:08.472056 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3111 06:48:08.475171 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3112 06:48:08.478448 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 06:48:08.481864 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 06:48:08.485638 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3115 06:48:08.485738
3116 06:48:08.488640 CA PerBit enable=1, Macro0, CA PI delay=33
3117 06:48:08.488718
3118 06:48:08.491756 [CBTSetCACLKResult] CA Dly = 33
3119 06:48:08.491838 CS Dly: 6 (0~38)
3120 06:48:08.494960
3121 06:48:08.498704 ----->DramcWriteLeveling(PI) begin...
3122 06:48:08.498780 ==
3123 06:48:08.501796 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 06:48:08.504800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 06:48:08.504875 ==
3126 06:48:08.508645 Write leveling (Byte 0): 26 => 26
3127 06:48:08.511393 Write leveling (Byte 1): 27 => 27
3128 06:48:08.515143 DramcWriteLeveling(PI) end<-----
3129 06:48:08.515241
3130 06:48:08.515333 ==
3131 06:48:08.518406 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 06:48:08.521794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 06:48:08.521864 ==
3134 06:48:08.524541 [Gating] SW mode calibration
3135 06:48:08.531229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 06:48:08.537865 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 06:48:08.541229 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
3138 06:48:08.544563 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 06:48:08.551198 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 06:48:08.554361 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 06:48:08.558300 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 06:48:08.564663 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 06:48:08.567510 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3144 06:48:08.570842 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
3145 06:48:08.578059 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 06:48:08.580748 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 06:48:08.584033 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 06:48:08.590822 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 06:48:08.594085 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 06:48:08.597497 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 06:48:08.604014 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3152 06:48:08.607597 1 0 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (1 1)
3153 06:48:08.611008 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 06:48:08.617768 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 06:48:08.620953 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 06:48:08.624366 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 06:48:08.630739 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 06:48:08.634389 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 06:48:08.637262 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 06:48:08.640791 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3161 06:48:08.647325 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 06:48:08.650934 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 06:48:08.654023 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 06:48:08.660595 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 06:48:08.664254 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 06:48:08.667038 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 06:48:08.673910 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 06:48:08.677112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 06:48:08.680503 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 06:48:08.686870 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 06:48:08.690493 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 06:48:08.693705 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 06:48:08.700273 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 06:48:08.703639 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 06:48:08.707176 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3176 06:48:08.713841 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 06:48:08.717118 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 06:48:08.720005 Total UI for P1: 0, mck2ui 16
3179 06:48:08.723914 best dqsien dly found for B0: ( 1, 3, 26)
3180 06:48:08.727515 Total UI for P1: 0, mck2ui 16
3181 06:48:08.730284 best dqsien dly found for B1: ( 1, 3, 28)
3182 06:48:08.733696 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3183 06:48:08.737234 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3184 06:48:08.737315
3185 06:48:08.739868 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3186 06:48:08.743174 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3187 06:48:08.746609 [Gating] SW calibration Done
3188 06:48:08.746682 ==
3189 06:48:08.750360 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 06:48:08.756919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 06:48:08.756993 ==
3192 06:48:08.757056 RX Vref Scan: 0
3193 06:48:08.757117
3194 06:48:08.760304 RX Vref 0 -> 0, step: 1
3195 06:48:08.760378
3196 06:48:08.763517 RX Delay -40 -> 252, step: 8
3197 06:48:08.766493 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3198 06:48:08.769891 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3199 06:48:08.773341 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3200 06:48:08.776641 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3201 06:48:08.783564 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3202 06:48:08.787159 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3203 06:48:08.790101 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3204 06:48:08.793057 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3205 06:48:08.796575 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3206 06:48:08.803122 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3207 06:48:08.806861 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3208 06:48:08.810318 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3209 06:48:08.813232 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3210 06:48:08.816882 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3211 06:48:08.823186 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3212 06:48:08.826218 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3213 06:48:08.826293 ==
3214 06:48:08.829611 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 06:48:08.833680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 06:48:08.833763 ==
3217 06:48:08.836413 DQS Delay:
3218 06:48:08.836493 DQS0 = 0, DQS1 = 0
3219 06:48:08.836557 DQM Delay:
3220 06:48:08.839900 DQM0 = 116, DQM1 = 112
3221 06:48:08.839981 DQ Delay:
3222 06:48:08.842887 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3223 06:48:08.846173 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3224 06:48:08.852987 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3225 06:48:08.856065 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3226 06:48:08.856173
3227 06:48:08.856265
3228 06:48:08.856351 ==
3229 06:48:08.859605 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 06:48:08.862876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 06:48:08.862952 ==
3232 06:48:08.863015
3233 06:48:08.863073
3234 06:48:08.865917 TX Vref Scan disable
3235 06:48:08.866015 == TX Byte 0 ==
3236 06:48:08.872560 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3237 06:48:08.876171 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3238 06:48:08.876247 == TX Byte 1 ==
3239 06:48:08.882855 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3240 06:48:08.886234 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3241 06:48:08.886339 ==
3242 06:48:08.889363 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 06:48:08.892806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 06:48:08.892887 ==
3245 06:48:08.906035 TX Vref=22, minBit 9, minWin=24, winSum=407
3246 06:48:08.909121 TX Vref=24, minBit 11, minWin=24, winSum=412
3247 06:48:08.912153 TX Vref=26, minBit 9, minWin=24, winSum=421
3248 06:48:08.915701 TX Vref=28, minBit 3, minWin=25, winSum=423
3249 06:48:08.918964 TX Vref=30, minBit 9, minWin=25, winSum=424
3250 06:48:08.925929 TX Vref=32, minBit 9, minWin=25, winSum=422
3251 06:48:08.928579 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 30
3252 06:48:08.928656
3253 06:48:08.931878 Final TX Range 1 Vref 30
3254 06:48:08.931956
3255 06:48:08.932018 ==
3256 06:48:08.935584 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 06:48:08.938572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 06:48:08.942008 ==
3259 06:48:08.942081
3260 06:48:08.942141
3261 06:48:08.942198 TX Vref Scan disable
3262 06:48:08.945649 == TX Byte 0 ==
3263 06:48:08.948591 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3264 06:48:08.955465 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3265 06:48:08.955546 == TX Byte 1 ==
3266 06:48:08.958819 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3267 06:48:08.965194 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3268 06:48:08.965272
3269 06:48:08.965334 [DATLAT]
3270 06:48:08.965393 Freq=1200, CH1 RK0
3271 06:48:08.965454
3272 06:48:08.968481 DATLAT Default: 0xd
3273 06:48:08.968572 0, 0xFFFF, sum = 0
3274 06:48:08.971504 1, 0xFFFF, sum = 0
3275 06:48:08.975357 2, 0xFFFF, sum = 0
3276 06:48:08.975482 3, 0xFFFF, sum = 0
3277 06:48:08.978493 4, 0xFFFF, sum = 0
3278 06:48:08.978615 5, 0xFFFF, sum = 0
3279 06:48:08.981765 6, 0xFFFF, sum = 0
3280 06:48:08.981839 7, 0xFFFF, sum = 0
3281 06:48:08.985237 8, 0xFFFF, sum = 0
3282 06:48:08.985341 9, 0xFFFF, sum = 0
3283 06:48:08.988464 10, 0xFFFF, sum = 0
3284 06:48:08.988542 11, 0xFFFF, sum = 0
3285 06:48:08.991499 12, 0x0, sum = 1
3286 06:48:08.991577 13, 0x0, sum = 2
3287 06:48:08.995179 14, 0x0, sum = 3
3288 06:48:08.995306 15, 0x0, sum = 4
3289 06:48:08.998121 best_step = 13
3290 06:48:08.998272
3291 06:48:08.998365 ==
3292 06:48:09.001552 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 06:48:09.004701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 06:48:09.004783 ==
3295 06:48:09.004847 RX Vref Scan: 1
3296 06:48:09.004907
3297 06:48:09.008415 Set Vref Range= 32 -> 127
3298 06:48:09.008495
3299 06:48:09.011605 RX Vref 32 -> 127, step: 1
3300 06:48:09.011697
3301 06:48:09.014563 RX Delay -13 -> 252, step: 4
3302 06:48:09.014676
3303 06:48:09.018450 Set Vref, RX VrefLevel [Byte0]: 32
3304 06:48:09.021868 [Byte1]: 32
3305 06:48:09.021974
3306 06:48:09.024964 Set Vref, RX VrefLevel [Byte0]: 33
3307 06:48:09.028194 [Byte1]: 33
3308 06:48:09.031379
3309 06:48:09.031466 Set Vref, RX VrefLevel [Byte0]: 34
3310 06:48:09.034907 [Byte1]: 34
3311 06:48:09.039625
3312 06:48:09.039723 Set Vref, RX VrefLevel [Byte0]: 35
3313 06:48:09.043066 [Byte1]: 35
3314 06:48:09.048287
3315 06:48:09.048363 Set Vref, RX VrefLevel [Byte0]: 36
3316 06:48:09.051001 [Byte1]: 36
3317 06:48:09.055103
3318 06:48:09.055175 Set Vref, RX VrefLevel [Byte0]: 37
3319 06:48:09.058642 [Byte1]: 37
3320 06:48:09.063036
3321 06:48:09.063119 Set Vref, RX VrefLevel [Byte0]: 38
3322 06:48:09.066657 [Byte1]: 38
3323 06:48:09.071425
3324 06:48:09.071545 Set Vref, RX VrefLevel [Byte0]: 39
3325 06:48:09.074229 [Byte1]: 39
3326 06:48:09.079127
3327 06:48:09.079225 Set Vref, RX VrefLevel [Byte0]: 40
3328 06:48:09.082171 [Byte1]: 40
3329 06:48:09.086878
3330 06:48:09.086950 Set Vref, RX VrefLevel [Byte0]: 41
3331 06:48:09.089974 [Byte1]: 41
3332 06:48:09.094575
3333 06:48:09.094646 Set Vref, RX VrefLevel [Byte0]: 42
3334 06:48:09.098058 [Byte1]: 42
3335 06:48:09.102499
3336 06:48:09.102611 Set Vref, RX VrefLevel [Byte0]: 43
3337 06:48:09.106405 [Byte1]: 43
3338 06:48:09.110628
3339 06:48:09.110724 Set Vref, RX VrefLevel [Byte0]: 44
3340 06:48:09.113508 [Byte1]: 44
3341 06:48:09.118169
3342 06:48:09.118268 Set Vref, RX VrefLevel [Byte0]: 45
3343 06:48:09.121547 [Byte1]: 45
3344 06:48:09.126239
3345 06:48:09.126337 Set Vref, RX VrefLevel [Byte0]: 46
3346 06:48:09.129575 [Byte1]: 46
3347 06:48:09.134800
3348 06:48:09.134900 Set Vref, RX VrefLevel [Byte0]: 47
3349 06:48:09.137545 [Byte1]: 47
3350 06:48:09.142214
3351 06:48:09.142284 Set Vref, RX VrefLevel [Byte0]: 48
3352 06:48:09.145026 [Byte1]: 48
3353 06:48:09.150346
3354 06:48:09.150418 Set Vref, RX VrefLevel [Byte0]: 49
3355 06:48:09.153389 [Byte1]: 49
3356 06:48:09.157626
3357 06:48:09.157768 Set Vref, RX VrefLevel [Byte0]: 50
3358 06:48:09.161690 [Byte1]: 50
3359 06:48:09.166028
3360 06:48:09.166108 Set Vref, RX VrefLevel [Byte0]: 51
3361 06:48:09.168982 [Byte1]: 51
3362 06:48:09.173488
3363 06:48:09.173595 Set Vref, RX VrefLevel [Byte0]: 52
3364 06:48:09.176658 [Byte1]: 52
3365 06:48:09.181173
3366 06:48:09.181286 Set Vref, RX VrefLevel [Byte0]: 53
3367 06:48:09.184572 [Byte1]: 53
3368 06:48:09.190083
3369 06:48:09.190163 Set Vref, RX VrefLevel [Byte0]: 54
3370 06:48:09.192444 [Byte1]: 54
3371 06:48:09.197211
3372 06:48:09.197282 Set Vref, RX VrefLevel [Byte0]: 55
3373 06:48:09.200181 [Byte1]: 55
3374 06:48:09.205110
3375 06:48:09.205190 Set Vref, RX VrefLevel [Byte0]: 56
3376 06:48:09.208704 [Byte1]: 56
3377 06:48:09.213111
3378 06:48:09.213182 Set Vref, RX VrefLevel [Byte0]: 57
3379 06:48:09.216579 [Byte1]: 57
3380 06:48:09.221249
3381 06:48:09.221325 Set Vref, RX VrefLevel [Byte0]: 58
3382 06:48:09.223906 [Byte1]: 58
3383 06:48:09.228726
3384 06:48:09.228803 Set Vref, RX VrefLevel [Byte0]: 59
3385 06:48:09.232266 [Byte1]: 59
3386 06:48:09.236314
3387 06:48:09.236384 Set Vref, RX VrefLevel [Byte0]: 60
3388 06:48:09.239779 [Byte1]: 60
3389 06:48:09.244311
3390 06:48:09.244385 Set Vref, RX VrefLevel [Byte0]: 61
3391 06:48:09.248006 [Byte1]: 61
3392 06:48:09.252689
3393 06:48:09.252765 Set Vref, RX VrefLevel [Byte0]: 62
3394 06:48:09.255355 [Byte1]: 62
3395 06:48:09.259972
3396 06:48:09.260076 Set Vref, RX VrefLevel [Byte0]: 63
3397 06:48:09.263313 [Byte1]: 63
3398 06:48:09.268126
3399 06:48:09.268203 Set Vref, RX VrefLevel [Byte0]: 64
3400 06:48:09.271537 [Byte1]: 64
3401 06:48:09.276098
3402 06:48:09.276180 Set Vref, RX VrefLevel [Byte0]: 65
3403 06:48:09.279315 [Byte1]: 65
3404 06:48:09.284050
3405 06:48:09.284127 Final RX Vref Byte 0 = 53 to rank0
3406 06:48:09.287334 Final RX Vref Byte 1 = 49 to rank0
3407 06:48:09.290557 Final RX Vref Byte 0 = 53 to rank1
3408 06:48:09.293719 Final RX Vref Byte 1 = 49 to rank1==
3409 06:48:09.297087 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 06:48:09.303473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 06:48:09.303576 ==
3412 06:48:09.303667 DQS Delay:
3413 06:48:09.303757 DQS0 = 0, DQS1 = 0
3414 06:48:09.306894 DQM Delay:
3415 06:48:09.306999 DQM0 = 114, DQM1 = 112
3416 06:48:09.310466 DQ Delay:
3417 06:48:09.313683 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3418 06:48:09.317316 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3419 06:48:09.321012 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3420 06:48:09.324083 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =118
3421 06:48:09.324158
3422 06:48:09.324218
3423 06:48:09.330530 [DQSOSCAuto] RK0, (LSB)MR18= 0xf401, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
3424 06:48:09.334133 CH1 RK0: MR19=304, MR18=F401
3425 06:48:09.340534 CH1_RK0: MR19=0x304, MR18=0xF401, DQSOSC=409, MR23=63, INC=39, DEC=26
3426 06:48:09.340609
3427 06:48:09.344181 ----->DramcWriteLeveling(PI) begin...
3428 06:48:09.344256 ==
3429 06:48:09.347112 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 06:48:09.354080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 06:48:09.354157 ==
3432 06:48:09.356979 Write leveling (Byte 0): 25 => 25
3433 06:48:09.357050 Write leveling (Byte 1): 30 => 30
3434 06:48:09.360246 DramcWriteLeveling(PI) end<-----
3435 06:48:09.360320
3436 06:48:09.360381 ==
3437 06:48:09.363622 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 06:48:09.369931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 06:48:09.370031 ==
3440 06:48:09.373527 [Gating] SW mode calibration
3441 06:48:09.379667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3442 06:48:09.383902 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3443 06:48:09.389756 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 06:48:09.393207 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 06:48:09.396345 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 06:48:09.403200 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 06:48:09.406481 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 06:48:09.409647 0 15 20 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3449 06:48:09.416854 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
3450 06:48:09.419445 0 15 28 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
3451 06:48:09.422893 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 06:48:09.429841 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 06:48:09.433054 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 06:48:09.436751 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 06:48:09.443007 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 06:48:09.446209 1 0 20 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
3457 06:48:09.449620 1 0 24 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
3458 06:48:09.456167 1 0 28 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
3459 06:48:09.459496 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 06:48:09.462703 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 06:48:09.469046 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 06:48:09.472501 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 06:48:09.475736 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 06:48:09.482211 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3465 06:48:09.485913 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3466 06:48:09.489419 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3467 06:48:09.495672 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 06:48:09.499083 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 06:48:09.502251 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 06:48:09.508754 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 06:48:09.512449 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 06:48:09.515463 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 06:48:09.521836 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 06:48:09.525710 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 06:48:09.528465 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 06:48:09.535183 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 06:48:09.538848 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 06:48:09.541903 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 06:48:09.548794 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 06:48:09.551496 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3481 06:48:09.555272 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 06:48:09.561543 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3483 06:48:09.561618 Total UI for P1: 0, mck2ui 16
3484 06:48:09.564990 best dqsien dly found for B0: ( 1, 3, 22)
3485 06:48:09.571684 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 06:48:09.575033 Total UI for P1: 0, mck2ui 16
3487 06:48:09.578270 best dqsien dly found for B1: ( 1, 3, 26)
3488 06:48:09.581194 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3489 06:48:09.585158 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3490 06:48:09.585230
3491 06:48:09.588068 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3492 06:48:09.591507 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3493 06:48:09.594340 [Gating] SW calibration Done
3494 06:48:09.594411 ==
3495 06:48:09.597734 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 06:48:09.601209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 06:48:09.604510 ==
3498 06:48:09.604579 RX Vref Scan: 0
3499 06:48:09.604638
3500 06:48:09.607572 RX Vref 0 -> 0, step: 1
3501 06:48:09.607641
3502 06:48:09.611124 RX Delay -40 -> 252, step: 8
3503 06:48:09.614314 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3504 06:48:09.617688 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3505 06:48:09.620689 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3506 06:48:09.624383 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3507 06:48:09.630991 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3508 06:48:09.634009 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3509 06:48:09.637292 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3510 06:48:09.640358 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3511 06:48:09.643868 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3512 06:48:09.650810 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3513 06:48:09.654002 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3514 06:48:09.657411 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3515 06:48:09.660526 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3516 06:48:09.663543 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3517 06:48:09.670371 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3518 06:48:09.673433 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3519 06:48:09.673536 ==
3520 06:48:09.677051 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 06:48:09.680049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 06:48:09.680127 ==
3523 06:48:09.683506 DQS Delay:
3524 06:48:09.683580 DQS0 = 0, DQS1 = 0
3525 06:48:09.686757 DQM Delay:
3526 06:48:09.686857 DQM0 = 114, DQM1 = 111
3527 06:48:09.686945 DQ Delay:
3528 06:48:09.690043 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3529 06:48:09.696888 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3530 06:48:09.699933 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3531 06:48:09.703438 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3532 06:48:09.703516
3533 06:48:09.703577
3534 06:48:09.703635 ==
3535 06:48:09.706615 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 06:48:09.709624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 06:48:09.709699 ==
3538 06:48:09.709765
3539 06:48:09.709824
3540 06:48:09.713242 TX Vref Scan disable
3541 06:48:09.716607 == TX Byte 0 ==
3542 06:48:09.719426 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3543 06:48:09.723329 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3544 06:48:09.726032 == TX Byte 1 ==
3545 06:48:09.729730 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3546 06:48:09.733156 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3547 06:48:09.733228 ==
3548 06:48:09.736216 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 06:48:09.742620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 06:48:09.742694 ==
3551 06:48:09.753075 TX Vref=22, minBit 3, minWin=25, winSum=422
3552 06:48:09.756734 TX Vref=24, minBit 9, minWin=25, winSum=424
3553 06:48:09.759864 TX Vref=26, minBit 1, minWin=26, winSum=430
3554 06:48:09.763043 TX Vref=28, minBit 1, minWin=26, winSum=430
3555 06:48:09.766694 TX Vref=30, minBit 7, minWin=26, winSum=432
3556 06:48:09.772627 TX Vref=32, minBit 2, minWin=26, winSum=433
3557 06:48:09.775944 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 32
3558 06:48:09.776024
3559 06:48:09.779571 Final TX Range 1 Vref 32
3560 06:48:09.779645
3561 06:48:09.779714 ==
3562 06:48:09.782745 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 06:48:09.785939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 06:48:09.789574 ==
3565 06:48:09.789651
3566 06:48:09.789714
3567 06:48:09.789771 TX Vref Scan disable
3568 06:48:09.792822 == TX Byte 0 ==
3569 06:48:09.796125 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3570 06:48:09.803050 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3571 06:48:09.803128 == TX Byte 1 ==
3572 06:48:09.806088 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3573 06:48:09.813492 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3574 06:48:09.813568
3575 06:48:09.813642 [DATLAT]
3576 06:48:09.813707 Freq=1200, CH1 RK1
3577 06:48:09.813766
3578 06:48:09.815925 DATLAT Default: 0xd
3579 06:48:09.815995 0, 0xFFFF, sum = 0
3580 06:48:09.819212 1, 0xFFFF, sum = 0
3581 06:48:09.822960 2, 0xFFFF, sum = 0
3582 06:48:09.823039 3, 0xFFFF, sum = 0
3583 06:48:09.825927 4, 0xFFFF, sum = 0
3584 06:48:09.825999 5, 0xFFFF, sum = 0
3585 06:48:09.829340 6, 0xFFFF, sum = 0
3586 06:48:09.829412 7, 0xFFFF, sum = 0
3587 06:48:09.832519 8, 0xFFFF, sum = 0
3588 06:48:09.832591 9, 0xFFFF, sum = 0
3589 06:48:09.835816 10, 0xFFFF, sum = 0
3590 06:48:09.835889 11, 0xFFFF, sum = 0
3591 06:48:09.839684 12, 0x0, sum = 1
3592 06:48:09.839764 13, 0x0, sum = 2
3593 06:48:09.842405 14, 0x0, sum = 3
3594 06:48:09.842481 15, 0x0, sum = 4
3595 06:48:09.845778 best_step = 13
3596 06:48:09.845851
3597 06:48:09.845916 ==
3598 06:48:09.849214 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 06:48:09.852672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 06:48:09.852745 ==
3601 06:48:09.855960 RX Vref Scan: 0
3602 06:48:09.856031
3603 06:48:09.856102 RX Vref 0 -> 0, step: 1
3604 06:48:09.856161
3605 06:48:09.858823 RX Delay -13 -> 252, step: 4
3606 06:48:09.865499 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3607 06:48:09.869087 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3608 06:48:09.872236 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3609 06:48:09.875508 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3610 06:48:09.878775 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3611 06:48:09.885687 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3612 06:48:09.889386 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3613 06:48:09.891979 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3614 06:48:09.894937 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3615 06:48:09.898102 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3616 06:48:09.905362 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3617 06:48:09.908100 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3618 06:48:09.911698 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3619 06:48:09.914488 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3620 06:48:09.921298 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3621 06:48:09.924752 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3622 06:48:09.924834 ==
3623 06:48:09.927717 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 06:48:09.931246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 06:48:09.931320 ==
3626 06:48:09.934555 DQS Delay:
3627 06:48:09.934634 DQS0 = 0, DQS1 = 0
3628 06:48:09.934696 DQM Delay:
3629 06:48:09.937507 DQM0 = 115, DQM1 = 111
3630 06:48:09.937587 DQ Delay:
3631 06:48:09.941424 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3632 06:48:09.944739 DQ4 =116, DQ5 =124, DQ6 =120, DQ7 =114
3633 06:48:09.951040 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3634 06:48:09.954048 DQ12 =120, DQ13 =116, DQ14 =116, DQ15 =120
3635 06:48:09.954129
3636 06:48:09.954197
3637 06:48:09.960857 [DQSOSCAuto] RK1, (LSB)MR18= 0xf80a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3638 06:48:09.964359 CH1 RK1: MR19=304, MR18=F80A
3639 06:48:09.970896 CH1_RK1: MR19=0x304, MR18=0xF80A, DQSOSC=406, MR23=63, INC=39, DEC=26
3640 06:48:09.973747 [RxdqsGatingPostProcess] freq 1200
3641 06:48:09.980819 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3642 06:48:09.980923 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 06:48:09.984171 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 06:48:09.987455 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 06:48:09.990419 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 06:48:09.993474 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 06:48:09.996774 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 06:48:10.000219 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 06:48:10.003879 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 06:48:10.006855 Pre-setting of DQS Precalculation
3651 06:48:10.013554 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3652 06:48:10.019935 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3653 06:48:10.026635 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3654 06:48:10.026727
3655 06:48:10.026792
3656 06:48:10.030112 [Calibration Summary] 2400 Mbps
3657 06:48:10.030184 CH 0, Rank 0
3658 06:48:10.033477 SW Impedance : PASS
3659 06:48:10.036394 DUTY Scan : NO K
3660 06:48:10.036469 ZQ Calibration : PASS
3661 06:48:10.039720 Jitter Meter : NO K
3662 06:48:10.043107 CBT Training : PASS
3663 06:48:10.043182 Write leveling : PASS
3664 06:48:10.046319 RX DQS gating : PASS
3665 06:48:10.049727 RX DQ/DQS(RDDQC) : PASS
3666 06:48:10.049800 TX DQ/DQS : PASS
3667 06:48:10.053272 RX DATLAT : PASS
3668 06:48:10.056363 RX DQ/DQS(Engine): PASS
3669 06:48:10.056442 TX OE : NO K
3670 06:48:10.056507 All Pass.
3671 06:48:10.059674
3672 06:48:10.059748 CH 0, Rank 1
3673 06:48:10.063179 SW Impedance : PASS
3674 06:48:10.063254 DUTY Scan : NO K
3675 06:48:10.066588 ZQ Calibration : PASS
3676 06:48:10.066674 Jitter Meter : NO K
3677 06:48:10.070077 CBT Training : PASS
3678 06:48:10.073187 Write leveling : PASS
3679 06:48:10.073280 RX DQS gating : PASS
3680 06:48:10.076248 RX DQ/DQS(RDDQC) : PASS
3681 06:48:10.079634 TX DQ/DQS : PASS
3682 06:48:10.079714 RX DATLAT : PASS
3683 06:48:10.083104 RX DQ/DQS(Engine): PASS
3684 06:48:10.085947 TX OE : NO K
3685 06:48:10.086050 All Pass.
3686 06:48:10.086149
3687 06:48:10.086239 CH 1, Rank 0
3688 06:48:10.089240 SW Impedance : PASS
3689 06:48:10.092572 DUTY Scan : NO K
3690 06:48:10.092645 ZQ Calibration : PASS
3691 06:48:10.095813 Jitter Meter : NO K
3692 06:48:10.099052 CBT Training : PASS
3693 06:48:10.099152 Write leveling : PASS
3694 06:48:10.102559 RX DQS gating : PASS
3695 06:48:10.105662 RX DQ/DQS(RDDQC) : PASS
3696 06:48:10.105763 TX DQ/DQS : PASS
3697 06:48:10.109198 RX DATLAT : PASS
3698 06:48:10.112448 RX DQ/DQS(Engine): PASS
3699 06:48:10.112524 TX OE : NO K
3700 06:48:10.116252 All Pass.
3701 06:48:10.116339
3702 06:48:10.116407 CH 1, Rank 1
3703 06:48:10.119018 SW Impedance : PASS
3704 06:48:10.119095 DUTY Scan : NO K
3705 06:48:10.122838 ZQ Calibration : PASS
3706 06:48:10.125649 Jitter Meter : NO K
3707 06:48:10.125729 CBT Training : PASS
3708 06:48:10.129751 Write leveling : PASS
3709 06:48:10.132303 RX DQS gating : PASS
3710 06:48:10.132382 RX DQ/DQS(RDDQC) : PASS
3711 06:48:10.135551 TX DQ/DQS : PASS
3712 06:48:10.135627 RX DATLAT : PASS
3713 06:48:10.138745 RX DQ/DQS(Engine): PASS
3714 06:48:10.142343 TX OE : NO K
3715 06:48:10.142419 All Pass.
3716 06:48:10.142490
3717 06:48:10.145576 DramC Write-DBI off
3718 06:48:10.148800 PER_BANK_REFRESH: Hybrid Mode
3719 06:48:10.148921 TX_TRACKING: ON
3720 06:48:10.158531 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3721 06:48:10.161782 [FAST_K] Save calibration result to emmc
3722 06:48:10.165398 dramc_set_vcore_voltage set vcore to 650000
3723 06:48:10.168680 Read voltage for 600, 5
3724 06:48:10.168755 Vio18 = 0
3725 06:48:10.168824 Vcore = 650000
3726 06:48:10.172260 Vdram = 0
3727 06:48:10.172332 Vddq = 0
3728 06:48:10.172400 Vmddr = 0
3729 06:48:10.178427 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3730 06:48:10.181812 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3731 06:48:10.185110 MEM_TYPE=3, freq_sel=19
3732 06:48:10.188592 sv_algorithm_assistance_LP4_1600
3733 06:48:10.191557 ============ PULL DRAM RESETB DOWN ============
3734 06:48:10.195040 ========== PULL DRAM RESETB DOWN end =========
3735 06:48:10.201852 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3736 06:48:10.204772 ===================================
3737 06:48:10.207803 LPDDR4 DRAM CONFIGURATION
3738 06:48:10.211115 ===================================
3739 06:48:10.211214 EX_ROW_EN[0] = 0x0
3740 06:48:10.214657 EX_ROW_EN[1] = 0x0
3741 06:48:10.214730 LP4Y_EN = 0x0
3742 06:48:10.217857 WORK_FSP = 0x0
3743 06:48:10.217926 WL = 0x2
3744 06:48:10.221410 RL = 0x2
3745 06:48:10.221482 BL = 0x2
3746 06:48:10.224507 RPST = 0x0
3747 06:48:10.224579 RD_PRE = 0x0
3748 06:48:10.228044 WR_PRE = 0x1
3749 06:48:10.228115 WR_PST = 0x0
3750 06:48:10.231461 DBI_WR = 0x0
3751 06:48:10.231533 DBI_RD = 0x0
3752 06:48:10.234552 OTF = 0x1
3753 06:48:10.238043 ===================================
3754 06:48:10.240847 ===================================
3755 06:48:10.240961 ANA top config
3756 06:48:10.244106 ===================================
3757 06:48:10.247724 DLL_ASYNC_EN = 0
3758 06:48:10.250860 ALL_SLAVE_EN = 1
3759 06:48:10.253946 NEW_RANK_MODE = 1
3760 06:48:10.254020 DLL_IDLE_MODE = 1
3761 06:48:10.257227 LP45_APHY_COMB_EN = 1
3762 06:48:10.260624 TX_ODT_DIS = 1
3763 06:48:10.264076 NEW_8X_MODE = 1
3764 06:48:10.267860 ===================================
3765 06:48:10.270655 ===================================
3766 06:48:10.274064 data_rate = 1200
3767 06:48:10.277426 CKR = 1
3768 06:48:10.277506 DQ_P2S_RATIO = 8
3769 06:48:10.280566 ===================================
3770 06:48:10.283817 CA_P2S_RATIO = 8
3771 06:48:10.286880 DQ_CA_OPEN = 0
3772 06:48:10.290306 DQ_SEMI_OPEN = 0
3773 06:48:10.293840 CA_SEMI_OPEN = 0
3774 06:48:10.296707 CA_FULL_RATE = 0
3775 06:48:10.296779 DQ_CKDIV4_EN = 1
3776 06:48:10.300178 CA_CKDIV4_EN = 1
3777 06:48:10.303658 CA_PREDIV_EN = 0
3778 06:48:10.307427 PH8_DLY = 0
3779 06:48:10.310322 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3780 06:48:10.313733 DQ_AAMCK_DIV = 4
3781 06:48:10.313807 CA_AAMCK_DIV = 4
3782 06:48:10.316913 CA_ADMCK_DIV = 4
3783 06:48:10.320059 DQ_TRACK_CA_EN = 0
3784 06:48:10.323377 CA_PICK = 600
3785 06:48:10.326645 CA_MCKIO = 600
3786 06:48:10.330175 MCKIO_SEMI = 0
3787 06:48:10.333828 PLL_FREQ = 2288
3788 06:48:10.336352 DQ_UI_PI_RATIO = 32
3789 06:48:10.336426 CA_UI_PI_RATIO = 0
3790 06:48:10.339687 ===================================
3791 06:48:10.343056 ===================================
3792 06:48:10.346289 memory_type:LPDDR4
3793 06:48:10.349560 GP_NUM : 10
3794 06:48:10.349657 SRAM_EN : 1
3795 06:48:10.353089 MD32_EN : 0
3796 06:48:10.356428 ===================================
3797 06:48:10.359664 [ANA_INIT] >>>>>>>>>>>>>>
3798 06:48:10.362775 <<<<<< [CONFIGURE PHASE]: ANA_TX
3799 06:48:10.366243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3800 06:48:10.369560 ===================================
3801 06:48:10.369639 data_rate = 1200,PCW = 0X5800
3802 06:48:10.372837 ===================================
3803 06:48:10.376185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3804 06:48:10.382562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 06:48:10.389443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 06:48:10.393049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3807 06:48:10.395624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3808 06:48:10.399271 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3809 06:48:10.402431 [ANA_INIT] flow start
3810 06:48:10.405990 [ANA_INIT] PLL >>>>>>>>
3811 06:48:10.406063 [ANA_INIT] PLL <<<<<<<<
3812 06:48:10.409420 [ANA_INIT] MIDPI >>>>>>>>
3813 06:48:10.412347 [ANA_INIT] MIDPI <<<<<<<<
3814 06:48:10.412422 [ANA_INIT] DLL >>>>>>>>
3815 06:48:10.415731 [ANA_INIT] flow end
3816 06:48:10.418903 ============ LP4 DIFF to SE enter ============
3817 06:48:10.422292 ============ LP4 DIFF to SE exit ============
3818 06:48:10.425697 [ANA_INIT] <<<<<<<<<<<<<
3819 06:48:10.428918 [Flow] Enable top DCM control >>>>>
3820 06:48:10.432099 [Flow] Enable top DCM control <<<<<
3821 06:48:10.435123 Enable DLL master slave shuffle
3822 06:48:10.442658 ==============================================================
3823 06:48:10.442738 Gating Mode config
3824 06:48:10.448880 ==============================================================
3825 06:48:10.451795 Config description:
3826 06:48:10.458303 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3827 06:48:10.468351 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3828 06:48:10.471605 SELPH_MODE 0: By rank 1: By Phase
3829 06:48:10.478317 ==============================================================
3830 06:48:10.481567 GAT_TRACK_EN = 1
3831 06:48:10.481646 RX_GATING_MODE = 2
3832 06:48:10.484883 RX_GATING_TRACK_MODE = 2
3833 06:48:10.488779 SELPH_MODE = 1
3834 06:48:10.491650 PICG_EARLY_EN = 1
3835 06:48:10.494439 VALID_LAT_VALUE = 1
3836 06:48:10.501292 ==============================================================
3837 06:48:10.504380 Enter into Gating configuration >>>>
3838 06:48:10.507798 Exit from Gating configuration <<<<
3839 06:48:10.511033 Enter into DVFS_PRE_config >>>>>
3840 06:48:10.520619 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3841 06:48:10.523938 Exit from DVFS_PRE_config <<<<<
3842 06:48:10.527078 Enter into PICG configuration >>>>
3843 06:48:10.530656 Exit from PICG configuration <<<<
3844 06:48:10.534122 [RX_INPUT] configuration >>>>>
3845 06:48:10.537730 [RX_INPUT] configuration <<<<<
3846 06:48:10.540693 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3847 06:48:10.547142 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3848 06:48:10.554065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 06:48:10.560712 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 06:48:10.567585 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 06:48:10.570706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 06:48:10.576839 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3853 06:48:10.580266 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3854 06:48:10.583814 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3855 06:48:10.586764 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3856 06:48:10.593145 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3857 06:48:10.596425 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3858 06:48:10.599754 ===================================
3859 06:48:10.603187 LPDDR4 DRAM CONFIGURATION
3860 06:48:10.606793 ===================================
3861 06:48:10.606873 EX_ROW_EN[0] = 0x0
3862 06:48:10.609716 EX_ROW_EN[1] = 0x0
3863 06:48:10.609788 LP4Y_EN = 0x0
3864 06:48:10.612751 WORK_FSP = 0x0
3865 06:48:10.612825 WL = 0x2
3866 06:48:10.616367 RL = 0x2
3867 06:48:10.619715 BL = 0x2
3868 06:48:10.619802 RPST = 0x0
3869 06:48:10.622795 RD_PRE = 0x0
3870 06:48:10.622895 WR_PRE = 0x1
3871 06:48:10.626445 WR_PST = 0x0
3872 06:48:10.626520 DBI_WR = 0x0
3873 06:48:10.629668 DBI_RD = 0x0
3874 06:48:10.629745 OTF = 0x1
3875 06:48:10.632773 ===================================
3876 06:48:10.636140 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3877 06:48:10.642446 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3878 06:48:10.646164 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 06:48:10.649502 ===================================
3880 06:48:10.652236 LPDDR4 DRAM CONFIGURATION
3881 06:48:10.655682 ===================================
3882 06:48:10.655763 EX_ROW_EN[0] = 0x10
3883 06:48:10.659174 EX_ROW_EN[1] = 0x0
3884 06:48:10.662645 LP4Y_EN = 0x0
3885 06:48:10.662726 WORK_FSP = 0x0
3886 06:48:10.665784 WL = 0x2
3887 06:48:10.665864 RL = 0x2
3888 06:48:10.669287 BL = 0x2
3889 06:48:10.669368 RPST = 0x0
3890 06:48:10.672050 RD_PRE = 0x0
3891 06:48:10.672131 WR_PRE = 0x1
3892 06:48:10.675515 WR_PST = 0x0
3893 06:48:10.675596 DBI_WR = 0x0
3894 06:48:10.678715 DBI_RD = 0x0
3895 06:48:10.678795 OTF = 0x1
3896 06:48:10.682226 ===================================
3897 06:48:10.688605 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3898 06:48:10.692993 nWR fixed to 30
3899 06:48:10.696239 [ModeRegInit_LP4] CH0 RK0
3900 06:48:10.696318 [ModeRegInit_LP4] CH0 RK1
3901 06:48:10.699603 [ModeRegInit_LP4] CH1 RK0
3902 06:48:10.703514 [ModeRegInit_LP4] CH1 RK1
3903 06:48:10.703591 match AC timing 17
3904 06:48:10.709613 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3905 06:48:10.712773 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3906 06:48:10.716096 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3907 06:48:10.722996 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3908 06:48:10.725862 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3909 06:48:10.725936 ==
3910 06:48:10.729062 Dram Type= 6, Freq= 0, CH_0, rank 0
3911 06:48:10.732475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3912 06:48:10.732551 ==
3913 06:48:10.738788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3914 06:48:10.746062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3915 06:48:10.748723 [CA 0] Center 36 (6~67) winsize 62
3916 06:48:10.752183 [CA 1] Center 36 (6~67) winsize 62
3917 06:48:10.755546 [CA 2] Center 34 (4~65) winsize 62
3918 06:48:10.758842 [CA 3] Center 34 (4~65) winsize 62
3919 06:48:10.762168 [CA 4] Center 34 (3~65) winsize 63
3920 06:48:10.765736 [CA 5] Center 33 (3~64) winsize 62
3921 06:48:10.765819
3922 06:48:10.768486 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3923 06:48:10.768567
3924 06:48:10.772234 [CATrainingPosCal] consider 1 rank data
3925 06:48:10.775207 u2DelayCellTimex100 = 270/100 ps
3926 06:48:10.779157 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 06:48:10.782083 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 06:48:10.788191 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3929 06:48:10.791805 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 06:48:10.795224 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3931 06:48:10.798722 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3932 06:48:10.798796
3933 06:48:10.801367 CA PerBit enable=1, Macro0, CA PI delay=33
3934 06:48:10.801438
3935 06:48:10.804777 [CBTSetCACLKResult] CA Dly = 33
3936 06:48:10.804848 CS Dly: 5 (0~36)
3937 06:48:10.804911 ==
3938 06:48:10.808329 Dram Type= 6, Freq= 0, CH_0, rank 1
3939 06:48:10.815247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3940 06:48:10.815350 ==
3941 06:48:10.818291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3942 06:48:10.824864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3943 06:48:10.828479 [CA 0] Center 36 (6~67) winsize 62
3944 06:48:10.831693 [CA 1] Center 36 (6~67) winsize 62
3945 06:48:10.834740 [CA 2] Center 34 (4~65) winsize 62
3946 06:48:10.838182 [CA 3] Center 34 (4~65) winsize 62
3947 06:48:10.841398 [CA 4] Center 34 (3~65) winsize 63
3948 06:48:10.844818 [CA 5] Center 34 (3~65) winsize 63
3949 06:48:10.844890
3950 06:48:10.848014 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3951 06:48:10.848086
3952 06:48:10.851253 [CATrainingPosCal] consider 2 rank data
3953 06:48:10.854543 u2DelayCellTimex100 = 270/100 ps
3954 06:48:10.858020 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3955 06:48:10.864907 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3956 06:48:10.867784 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3957 06:48:10.871342 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 06:48:10.874150 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3959 06:48:10.877550 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3960 06:48:10.877632
3961 06:48:10.880843 CA PerBit enable=1, Macro0, CA PI delay=33
3962 06:48:10.880950
3963 06:48:10.884436 [CBTSetCACLKResult] CA Dly = 33
3964 06:48:10.887280 CS Dly: 5 (0~37)
3965 06:48:10.887384
3966 06:48:10.890746 ----->DramcWriteLeveling(PI) begin...
3967 06:48:10.890828 ==
3968 06:48:10.894269 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 06:48:10.897432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 06:48:10.897530 ==
3971 06:48:10.900736 Write leveling (Byte 0): 33 => 33
3972 06:48:10.903898 Write leveling (Byte 1): 29 => 29
3973 06:48:10.907296 DramcWriteLeveling(PI) end<-----
3974 06:48:10.907399
3975 06:48:10.907476 ==
3976 06:48:10.910724 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 06:48:10.913687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 06:48:10.913768 ==
3979 06:48:10.917187 [Gating] SW mode calibration
3980 06:48:10.923895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3981 06:48:10.930261 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3982 06:48:10.933741 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 06:48:10.937335 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 06:48:10.943296 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 06:48:10.947080 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
3986 06:48:10.953398 0 9 16 | B1->B0 | 2f2f 2727 | 1 0 | (1 1) (0 0)
3987 06:48:10.956909 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 06:48:10.959687 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 06:48:10.966489 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 06:48:10.969622 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 06:48:10.973185 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 06:48:10.979462 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 06:48:10.982839 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
3994 06:48:10.986344 0 10 16 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
3995 06:48:10.992879 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 06:48:10.996134 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 06:48:10.999325 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 06:48:11.006140 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 06:48:11.009396 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 06:48:11.012727 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 06:48:11.019298 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4002 06:48:11.022335 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4003 06:48:11.026017 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 06:48:11.032247 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 06:48:11.035648 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 06:48:11.038743 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 06:48:11.045509 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 06:48:11.048869 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 06:48:11.051940 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 06:48:11.058419 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 06:48:11.061927 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 06:48:11.065097 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 06:48:11.071710 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 06:48:11.075047 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 06:48:11.078405 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 06:48:11.084611 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 06:48:11.088020 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4018 06:48:11.091551 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4019 06:48:11.094792 Total UI for P1: 0, mck2ui 16
4020 06:48:11.097978 best dqsien dly found for B0: ( 0, 13, 12)
4021 06:48:11.104641 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 06:48:11.104722 Total UI for P1: 0, mck2ui 16
4023 06:48:11.111374 best dqsien dly found for B1: ( 0, 13, 16)
4024 06:48:11.114474 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4025 06:48:11.117938 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4026 06:48:11.118020
4027 06:48:11.120838 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4028 06:48:11.124382 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4029 06:48:11.127937 [Gating] SW calibration Done
4030 06:48:11.128018 ==
4031 06:48:11.131372 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 06:48:11.134375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 06:48:11.134456 ==
4034 06:48:11.137786 RX Vref Scan: 0
4035 06:48:11.137867
4036 06:48:11.137969 RX Vref 0 -> 0, step: 1
4037 06:48:11.140668
4038 06:48:11.140748 RX Delay -230 -> 252, step: 16
4039 06:48:11.147601 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4040 06:48:11.150468 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4041 06:48:11.153846 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4042 06:48:11.157372 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4043 06:48:11.164128 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4044 06:48:11.167200 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4045 06:48:11.170607 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4046 06:48:11.173956 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4047 06:48:11.177299 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4048 06:48:11.183798 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4049 06:48:11.187518 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4050 06:48:11.190816 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4051 06:48:11.193641 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4052 06:48:11.200387 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4053 06:48:11.203264 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4054 06:48:11.206709 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4055 06:48:11.206793 ==
4056 06:48:11.210253 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 06:48:11.213643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 06:48:11.216769 ==
4059 06:48:11.216848 DQS Delay:
4060 06:48:11.216916 DQS0 = 0, DQS1 = 0
4061 06:48:11.220161 DQM Delay:
4062 06:48:11.220232 DQM0 = 43, DQM1 = 32
4063 06:48:11.223417 DQ Delay:
4064 06:48:11.226751 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4065 06:48:11.226827 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4066 06:48:11.230251 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4067 06:48:11.236447 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =33
4068 06:48:11.236551
4069 06:48:11.236667
4070 06:48:11.236728 ==
4071 06:48:11.239615 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 06:48:11.243500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 06:48:11.243585 ==
4074 06:48:11.243657
4075 06:48:11.243715
4076 06:48:11.246631 TX Vref Scan disable
4077 06:48:11.246728 == TX Byte 0 ==
4078 06:48:11.253314 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4079 06:48:11.256672 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4080 06:48:11.256762 == TX Byte 1 ==
4081 06:48:11.263126 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4082 06:48:11.266064 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4083 06:48:11.266164 ==
4084 06:48:11.269292 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 06:48:11.272988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 06:48:11.273087 ==
4087 06:48:11.276155
4088 06:48:11.276261
4089 06:48:11.276351 TX Vref Scan disable
4090 06:48:11.279618 == TX Byte 0 ==
4091 06:48:11.283062 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4092 06:48:11.289506 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4093 06:48:11.289583 == TX Byte 1 ==
4094 06:48:11.292939 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4095 06:48:11.299702 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4096 06:48:11.299782
4097 06:48:11.299844 [DATLAT]
4098 06:48:11.299904 Freq=600, CH0 RK0
4099 06:48:11.299961
4100 06:48:11.302845 DATLAT Default: 0x9
4101 06:48:11.305939 0, 0xFFFF, sum = 0
4102 06:48:11.306012 1, 0xFFFF, sum = 0
4103 06:48:11.309630 2, 0xFFFF, sum = 0
4104 06:48:11.309709 3, 0xFFFF, sum = 0
4105 06:48:11.312738 4, 0xFFFF, sum = 0
4106 06:48:11.312813 5, 0xFFFF, sum = 0
4107 06:48:11.316290 6, 0xFFFF, sum = 0
4108 06:48:11.316396 7, 0xFFFF, sum = 0
4109 06:48:11.319210 8, 0x0, sum = 1
4110 06:48:11.319283 9, 0x0, sum = 2
4111 06:48:11.322445 10, 0x0, sum = 3
4112 06:48:11.322518 11, 0x0, sum = 4
4113 06:48:11.322642 best_step = 9
4114 06:48:11.322702
4115 06:48:11.326071 ==
4116 06:48:11.329674 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 06:48:11.332789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 06:48:11.332865 ==
4119 06:48:11.332928 RX Vref Scan: 1
4120 06:48:11.332986
4121 06:48:11.335636 RX Vref 0 -> 0, step: 1
4122 06:48:11.335738
4123 06:48:11.338992 RX Delay -195 -> 252, step: 8
4124 06:48:11.339062
4125 06:48:11.342686 Set Vref, RX VrefLevel [Byte0]: 52
4126 06:48:11.345869 [Byte1]: 49
4127 06:48:11.345940
4128 06:48:11.348785 Final RX Vref Byte 0 = 52 to rank0
4129 06:48:11.352282 Final RX Vref Byte 1 = 49 to rank0
4130 06:48:11.355699 Final RX Vref Byte 0 = 52 to rank1
4131 06:48:11.358867 Final RX Vref Byte 1 = 49 to rank1==
4132 06:48:11.361961 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 06:48:11.368478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 06:48:11.368553 ==
4135 06:48:11.368613 DQS Delay:
4136 06:48:11.368671 DQS0 = 0, DQS1 = 0
4137 06:48:11.371909 DQM Delay:
4138 06:48:11.371981 DQM0 = 40, DQM1 = 33
4139 06:48:11.375336 DQ Delay:
4140 06:48:11.378809 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4141 06:48:11.378887 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4142 06:48:11.382268 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4143 06:48:11.388488 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4144 06:48:11.388563
4145 06:48:11.388631
4146 06:48:11.395275 [DQSOSCAuto] RK0, (LSB)MR18= 0x483f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4147 06:48:11.398548 CH0 RK0: MR19=808, MR18=483F
4148 06:48:11.404892 CH0_RK0: MR19=0x808, MR18=0x483F, DQSOSC=396, MR23=63, INC=167, DEC=111
4149 06:48:11.404968
4150 06:48:11.408757 ----->DramcWriteLeveling(PI) begin...
4151 06:48:11.408831 ==
4152 06:48:11.411612 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 06:48:11.415064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 06:48:11.415138 ==
4155 06:48:11.418409 Write leveling (Byte 0): 35 => 35
4156 06:48:11.421393 Write leveling (Byte 1): 31 => 31
4157 06:48:11.424982 DramcWriteLeveling(PI) end<-----
4158 06:48:11.425056
4159 06:48:11.425117 ==
4160 06:48:11.427960 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 06:48:11.431248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 06:48:11.434283 ==
4163 06:48:11.434358 [Gating] SW mode calibration
4164 06:48:11.444640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4165 06:48:11.447769 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4166 06:48:11.450720 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 06:48:11.457520 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 06:48:11.460755 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 06:48:11.464759 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
4170 06:48:11.471201 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4171 06:48:11.474054 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 06:48:11.477047 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 06:48:11.483799 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 06:48:11.487413 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 06:48:11.490659 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 06:48:11.496729 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 06:48:11.500090 0 10 12 | B1->B0 | 2929 3434 | 1 1 | (1 1) (0 0)
4178 06:48:11.503409 0 10 16 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
4179 06:48:11.510264 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 06:48:11.513547 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 06:48:11.516737 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 06:48:11.523569 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 06:48:11.526536 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 06:48:11.529929 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 06:48:11.536646 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4186 06:48:11.539811 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4187 06:48:11.543016 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 06:48:11.550589 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 06:48:11.553127 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 06:48:11.556299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 06:48:11.563024 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 06:48:11.566390 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 06:48:11.569448 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 06:48:11.576389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 06:48:11.579494 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 06:48:11.582823 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 06:48:11.589303 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 06:48:11.592803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 06:48:11.595730 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 06:48:11.602779 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 06:48:11.605770 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4202 06:48:11.609272 Total UI for P1: 0, mck2ui 16
4203 06:48:11.612734 best dqsien dly found for B0: ( 0, 13, 10)
4204 06:48:11.616218 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 06:48:11.619108 Total UI for P1: 0, mck2ui 16
4206 06:48:11.622386 best dqsien dly found for B1: ( 0, 13, 12)
4207 06:48:11.625793 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4208 06:48:11.629388 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4209 06:48:11.632040
4210 06:48:11.635428 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4211 06:48:11.638805 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4212 06:48:11.641938 [Gating] SW calibration Done
4213 06:48:11.642035 ==
4214 06:48:11.645774 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 06:48:11.648856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 06:48:11.648939 ==
4217 06:48:11.651892 RX Vref Scan: 0
4218 06:48:11.651973
4219 06:48:11.652037 RX Vref 0 -> 0, step: 1
4220 06:48:11.652097
4221 06:48:11.655475 RX Delay -230 -> 252, step: 16
4222 06:48:11.658683 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4223 06:48:11.665044 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4224 06:48:11.668975 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4225 06:48:11.671874 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4226 06:48:11.674907 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4227 06:48:11.681946 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4228 06:48:11.685008 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4229 06:48:11.688156 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4230 06:48:11.691261 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4231 06:48:11.694543 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4232 06:48:11.701493 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4233 06:48:11.704437 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4234 06:48:11.707826 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4235 06:48:11.714477 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4236 06:48:11.718035 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4237 06:48:11.720701 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4238 06:48:11.720782 ==
4239 06:48:11.724043 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 06:48:11.727516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 06:48:11.727593 ==
4242 06:48:11.731048 DQS Delay:
4243 06:48:11.731145 DQS0 = 0, DQS1 = 0
4244 06:48:11.734477 DQM Delay:
4245 06:48:11.734550 DQM0 = 40, DQM1 = 34
4246 06:48:11.734611 DQ Delay:
4247 06:48:11.737416 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4248 06:48:11.740478 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =49
4249 06:48:11.743842 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4250 06:48:11.747490 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4251 06:48:11.747567
4252 06:48:11.747629
4253 06:48:11.750938 ==
4254 06:48:11.754118 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 06:48:11.757338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 06:48:11.757445 ==
4257 06:48:11.757536
4258 06:48:11.757623
4259 06:48:11.760698 TX Vref Scan disable
4260 06:48:11.760769 == TX Byte 0 ==
4261 06:48:11.767144 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4262 06:48:11.770405 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4263 06:48:11.770476 == TX Byte 1 ==
4264 06:48:11.777367 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4265 06:48:11.780580 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4266 06:48:11.780656 ==
4267 06:48:11.783575 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 06:48:11.787039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 06:48:11.787138 ==
4270 06:48:11.787226
4271 06:48:11.787313
4272 06:48:11.790073 TX Vref Scan disable
4273 06:48:11.793987 == TX Byte 0 ==
4274 06:48:11.797236 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4275 06:48:11.800279 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4276 06:48:11.803575 == TX Byte 1 ==
4277 06:48:11.807173 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4278 06:48:11.810057 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4279 06:48:11.813599
4280 06:48:11.813680 [DATLAT]
4281 06:48:11.813744 Freq=600, CH0 RK1
4282 06:48:11.813805
4283 06:48:11.817062 DATLAT Default: 0x9
4284 06:48:11.817143 0, 0xFFFF, sum = 0
4285 06:48:11.820205 1, 0xFFFF, sum = 0
4286 06:48:11.820300 2, 0xFFFF, sum = 0
4287 06:48:11.823069 3, 0xFFFF, sum = 0
4288 06:48:11.826613 4, 0xFFFF, sum = 0
4289 06:48:11.826698 5, 0xFFFF, sum = 0
4290 06:48:11.830049 6, 0xFFFF, sum = 0
4291 06:48:11.830123 7, 0xFFFF, sum = 0
4292 06:48:11.833279 8, 0x0, sum = 1
4293 06:48:11.833348 9, 0x0, sum = 2
4294 06:48:11.833408 10, 0x0, sum = 3
4295 06:48:11.836836 11, 0x0, sum = 4
4296 06:48:11.836918 best_step = 9
4297 06:48:11.836981
4298 06:48:11.837040 ==
4299 06:48:11.839996 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 06:48:11.846304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 06:48:11.846385 ==
4302 06:48:11.846449 RX Vref Scan: 0
4303 06:48:11.846508
4304 06:48:11.849980 RX Vref 0 -> 0, step: 1
4305 06:48:11.850061
4306 06:48:11.853633 RX Delay -195 -> 252, step: 8
4307 06:48:11.856126 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4308 06:48:11.862984 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4309 06:48:11.866235 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4310 06:48:11.869552 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4311 06:48:11.872867 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4312 06:48:11.879438 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4313 06:48:11.882359 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4314 06:48:11.885801 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4315 06:48:11.889129 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4316 06:48:11.895874 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4317 06:48:11.899294 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4318 06:48:11.902245 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4319 06:48:11.905421 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4320 06:48:11.911897 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4321 06:48:11.915693 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4322 06:48:11.918775 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4323 06:48:11.918855 ==
4324 06:48:11.921816 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 06:48:11.925484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 06:48:11.925565 ==
4327 06:48:11.928860 DQS Delay:
4328 06:48:11.928941 DQS0 = 0, DQS1 = 0
4329 06:48:11.931746 DQM Delay:
4330 06:48:11.931826 DQM0 = 40, DQM1 = 34
4331 06:48:11.935079 DQ Delay:
4332 06:48:11.935159 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4333 06:48:11.938725 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4334 06:48:11.941625 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4335 06:48:11.945041 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4336 06:48:11.948094
4337 06:48:11.948174
4338 06:48:11.954927 [DQSOSCAuto] RK1, (LSB)MR18= 0x413b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4339 06:48:11.958478 CH0 RK1: MR19=808, MR18=413B
4340 06:48:11.964727 CH0_RK1: MR19=0x808, MR18=0x413B, DQSOSC=397, MR23=63, INC=166, DEC=110
4341 06:48:11.968293 [RxdqsGatingPostProcess] freq 600
4342 06:48:11.971209 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4343 06:48:11.974498 Pre-setting of DQS Precalculation
4344 06:48:11.981045 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4345 06:48:11.981126 ==
4346 06:48:11.984248 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 06:48:11.987698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 06:48:11.987779 ==
4349 06:48:11.994352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 06:48:12.001004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4351 06:48:12.004652 [CA 0] Center 36 (6~66) winsize 61
4352 06:48:12.007305 [CA 1] Center 35 (5~66) winsize 62
4353 06:48:12.010877 [CA 2] Center 34 (4~65) winsize 62
4354 06:48:12.014428 [CA 3] Center 34 (3~65) winsize 63
4355 06:48:12.017225 [CA 4] Center 34 (4~65) winsize 62
4356 06:48:12.020464 [CA 5] Center 34 (3~65) winsize 63
4357 06:48:12.020553
4358 06:48:12.024009 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4359 06:48:12.024089
4360 06:48:12.027243 [CATrainingPosCal] consider 1 rank data
4361 06:48:12.030469 u2DelayCellTimex100 = 270/100 ps
4362 06:48:12.033957 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4363 06:48:12.037465 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4364 06:48:12.040522 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4365 06:48:12.043489 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4366 06:48:12.047186 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4367 06:48:12.050404 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4368 06:48:12.050512
4369 06:48:12.056796 CA PerBit enable=1, Macro0, CA PI delay=34
4370 06:48:12.056874
4371 06:48:12.056943 [CBTSetCACLKResult] CA Dly = 34
4372 06:48:12.060445 CS Dly: 4 (0~35)
4373 06:48:12.060517 ==
4374 06:48:12.063722 Dram Type= 6, Freq= 0, CH_1, rank 1
4375 06:48:12.067148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 06:48:12.067257 ==
4377 06:48:12.073254 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 06:48:12.080700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4379 06:48:12.083770 [CA 0] Center 35 (5~66) winsize 62
4380 06:48:12.086868 [CA 1] Center 36 (6~66) winsize 61
4381 06:48:12.089895 [CA 2] Center 34 (4~65) winsize 62
4382 06:48:12.093119 [CA 3] Center 34 (3~65) winsize 63
4383 06:48:12.097158 [CA 4] Center 34 (3~65) winsize 63
4384 06:48:12.099900 [CA 5] Center 34 (3~65) winsize 63
4385 06:48:12.099978
4386 06:48:12.103173 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4387 06:48:12.103279
4388 06:48:12.106261 [CATrainingPosCal] consider 2 rank data
4389 06:48:12.109775 u2DelayCellTimex100 = 270/100 ps
4390 06:48:12.113456 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4391 06:48:12.116642 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4392 06:48:12.119995 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 06:48:12.122828 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4394 06:48:12.129745 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4395 06:48:12.133139 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4396 06:48:12.133239
4397 06:48:12.136040 CA PerBit enable=1, Macro0, CA PI delay=34
4398 06:48:12.136140
4399 06:48:12.139489 [CBTSetCACLKResult] CA Dly = 34
4400 06:48:12.139594 CS Dly: 4 (0~36)
4401 06:48:12.139684
4402 06:48:12.142813 ----->DramcWriteLeveling(PI) begin...
4403 06:48:12.142947 ==
4404 06:48:12.146138 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 06:48:12.152652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 06:48:12.152813 ==
4407 06:48:12.155970 Write leveling (Byte 0): 27 => 27
4408 06:48:12.159190 Write leveling (Byte 1): 31 => 31
4409 06:48:12.159318 DramcWriteLeveling(PI) end<-----
4410 06:48:12.162558
4411 06:48:12.162663 ==
4412 06:48:12.165552 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 06:48:12.169123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 06:48:12.169232 ==
4415 06:48:12.172223 [Gating] SW mode calibration
4416 06:48:12.178559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 06:48:12.182027 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4418 06:48:12.188994 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 06:48:12.191938 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 06:48:12.194996 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 06:48:12.201897 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (0 1) (1 0)
4422 06:48:12.205096 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 06:48:12.208295 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 06:48:12.214811 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 06:48:12.218225 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 06:48:12.221814 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 06:48:12.228146 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 06:48:12.231689 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 06:48:12.234932 0 10 12 | B1->B0 | 3535 3939 | 0 0 | (1 1) (1 1)
4430 06:48:12.241148 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 06:48:12.244599 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 06:48:12.247897 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 06:48:12.254385 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 06:48:12.258091 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 06:48:12.261081 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 06:48:12.267874 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 06:48:12.271352 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4438 06:48:12.274623 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 06:48:12.280574 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 06:48:12.284096 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 06:48:12.290429 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 06:48:12.293677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 06:48:12.297390 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 06:48:12.304244 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 06:48:12.306975 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 06:48:12.310378 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 06:48:12.317125 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 06:48:12.320126 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 06:48:12.323646 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 06:48:12.330071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 06:48:12.333232 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 06:48:12.336725 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 06:48:12.343164 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 06:48:12.343293 Total UI for P1: 0, mck2ui 16
4455 06:48:12.346572 best dqsien dly found for B0: ( 0, 13, 10)
4456 06:48:12.349995 Total UI for P1: 0, mck2ui 16
4457 06:48:12.353650 best dqsien dly found for B1: ( 0, 13, 10)
4458 06:48:12.359738 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4459 06:48:12.363324 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4460 06:48:12.363434
4461 06:48:12.366645 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4462 06:48:12.369974 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4463 06:48:12.373059 [Gating] SW calibration Done
4464 06:48:12.373141 ==
4465 06:48:12.376536 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 06:48:12.379883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 06:48:12.379967 ==
4468 06:48:12.382865 RX Vref Scan: 0
4469 06:48:12.382946
4470 06:48:12.383011 RX Vref 0 -> 0, step: 1
4471 06:48:12.383072
4472 06:48:12.386300 RX Delay -230 -> 252, step: 16
4473 06:48:12.393144 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4474 06:48:12.396328 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4475 06:48:12.399535 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4476 06:48:12.402537 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4477 06:48:12.405727 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4478 06:48:12.412595 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4479 06:48:12.415921 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4480 06:48:12.419195 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4481 06:48:12.422606 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4482 06:48:12.429243 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4483 06:48:12.432845 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4484 06:48:12.435616 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4485 06:48:12.438889 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4486 06:48:12.445646 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4487 06:48:12.448823 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4488 06:48:12.452078 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4489 06:48:12.452160 ==
4490 06:48:12.455166 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 06:48:12.458440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 06:48:12.462258 ==
4493 06:48:12.462340 DQS Delay:
4494 06:48:12.462405 DQS0 = 0, DQS1 = 0
4495 06:48:12.465083 DQM Delay:
4496 06:48:12.465165 DQM0 = 44, DQM1 = 39
4497 06:48:12.468423 DQ Delay:
4498 06:48:12.471592 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4499 06:48:12.475023 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4500 06:48:12.478109 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4501 06:48:12.481805 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4502 06:48:12.481898
4503 06:48:12.481964
4504 06:48:12.482024 ==
4505 06:48:12.485113 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 06:48:12.487992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 06:48:12.488123 ==
4508 06:48:12.488244
4509 06:48:12.488354
4510 06:48:12.491338 TX Vref Scan disable
4511 06:48:12.494417 == TX Byte 0 ==
4512 06:48:12.497806 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4513 06:48:12.501106 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4514 06:48:12.504698 == TX Byte 1 ==
4515 06:48:12.508065 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4516 06:48:12.511108 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4517 06:48:12.511180 ==
4518 06:48:12.514944 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 06:48:12.518392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 06:48:12.520987 ==
4521 06:48:12.521073
4522 06:48:12.521139
4523 06:48:12.521206 TX Vref Scan disable
4524 06:48:12.524855 == TX Byte 0 ==
4525 06:48:12.527919 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4526 06:48:12.534429 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4527 06:48:12.534514 == TX Byte 1 ==
4528 06:48:12.538239 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4529 06:48:12.544373 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4530 06:48:12.544455
4531 06:48:12.544520 [DATLAT]
4532 06:48:12.544581 Freq=600, CH1 RK0
4533 06:48:12.544639
4534 06:48:12.547764 DATLAT Default: 0x9
4535 06:48:12.550891 0, 0xFFFF, sum = 0
4536 06:48:12.550973 1, 0xFFFF, sum = 0
4537 06:48:12.554204 2, 0xFFFF, sum = 0
4538 06:48:12.554286 3, 0xFFFF, sum = 0
4539 06:48:12.557609 4, 0xFFFF, sum = 0
4540 06:48:12.557691 5, 0xFFFF, sum = 0
4541 06:48:12.561608 6, 0xFFFF, sum = 0
4542 06:48:12.561706 7, 0xFFFF, sum = 0
4543 06:48:12.564630 8, 0x0, sum = 1
4544 06:48:12.564712 9, 0x0, sum = 2
4545 06:48:12.567458 10, 0x0, sum = 3
4546 06:48:12.567540 11, 0x0, sum = 4
4547 06:48:12.567605 best_step = 9
4548 06:48:12.567688
4549 06:48:12.571054 ==
4550 06:48:12.574132 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 06:48:12.577758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 06:48:12.577841 ==
4553 06:48:12.577906 RX Vref Scan: 1
4554 06:48:12.577966
4555 06:48:12.581259 RX Vref 0 -> 0, step: 1
4556 06:48:12.581340
4557 06:48:12.584318 RX Delay -179 -> 252, step: 8
4558 06:48:12.584400
4559 06:48:12.587185 Set Vref, RX VrefLevel [Byte0]: 53
4560 06:48:12.590558 [Byte1]: 49
4561 06:48:12.590666
4562 06:48:12.593935 Final RX Vref Byte 0 = 53 to rank0
4563 06:48:12.597162 Final RX Vref Byte 1 = 49 to rank0
4564 06:48:12.600462 Final RX Vref Byte 0 = 53 to rank1
4565 06:48:12.603808 Final RX Vref Byte 1 = 49 to rank1==
4566 06:48:12.607508 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 06:48:12.610846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 06:48:12.613790 ==
4569 06:48:12.613872 DQS Delay:
4570 06:48:12.613936 DQS0 = 0, DQS1 = 0
4571 06:48:12.617037 DQM Delay:
4572 06:48:12.617118 DQM0 = 41, DQM1 = 34
4573 06:48:12.620610 DQ Delay:
4574 06:48:12.623799 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4575 06:48:12.623885 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4576 06:48:12.627051 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4577 06:48:12.633304 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4578 06:48:12.633385
4579 06:48:12.633449
4580 06:48:12.640014 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4581 06:48:12.643718 CH1 RK0: MR19=808, MR18=2A45
4582 06:48:12.649742 CH1_RK0: MR19=0x808, MR18=0x2A45, DQSOSC=396, MR23=63, INC=167, DEC=111
4583 06:48:12.649824
4584 06:48:12.653200 ----->DramcWriteLeveling(PI) begin...
4585 06:48:12.653290 ==
4586 06:48:12.656539 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 06:48:12.660167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 06:48:12.660243 ==
4589 06:48:12.663469 Write leveling (Byte 0): 30 => 30
4590 06:48:12.666690 Write leveling (Byte 1): 30 => 30
4591 06:48:12.669509 DramcWriteLeveling(PI) end<-----
4592 06:48:12.669587
4593 06:48:12.669649 ==
4594 06:48:12.673249 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 06:48:12.676869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 06:48:12.676953 ==
4597 06:48:12.679893 [Gating] SW mode calibration
4598 06:48:12.686284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4599 06:48:12.693105 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4600 06:48:12.696710 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 06:48:12.703228 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 06:48:12.706215 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4603 06:48:12.709293 0 9 12 | B1->B0 | 3131 2d2d | 0 0 | (1 1) (1 1)
4604 06:48:12.716107 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4605 06:48:12.719051 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 06:48:12.722469 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 06:48:12.729385 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 06:48:12.732817 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 06:48:12.736020 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 06:48:12.742603 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4611 06:48:12.745801 0 10 12 | B1->B0 | 3131 3d3d | 0 0 | (0 0) (0 0)
4612 06:48:12.749336 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 06:48:12.756278 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 06:48:12.758955 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 06:48:12.762122 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 06:48:12.768831 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 06:48:12.772212 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 06:48:12.775267 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4619 06:48:12.782208 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4620 06:48:12.785129 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 06:48:12.788708 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 06:48:12.795345 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 06:48:12.798263 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 06:48:12.801839 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 06:48:12.808535 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 06:48:12.811421 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 06:48:12.814869 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 06:48:12.821506 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 06:48:12.825254 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 06:48:12.828120 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 06:48:12.834419 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 06:48:12.837989 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 06:48:12.841083 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 06:48:12.847874 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 06:48:12.851094 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4636 06:48:12.854097 Total UI for P1: 0, mck2ui 16
4637 06:48:12.857456 best dqsien dly found for B0: ( 0, 13, 10)
4638 06:48:12.860706 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 06:48:12.864076 Total UI for P1: 0, mck2ui 16
4640 06:48:12.867673 best dqsien dly found for B1: ( 0, 13, 12)
4641 06:48:12.870814 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4642 06:48:12.874241 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4643 06:48:12.874349
4644 06:48:12.880669 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4645 06:48:12.884241 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4646 06:48:12.887148 [Gating] SW calibration Done
4647 06:48:12.887262 ==
4648 06:48:12.890918 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 06:48:12.893632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 06:48:12.893708 ==
4651 06:48:12.893770 RX Vref Scan: 0
4652 06:48:12.893828
4653 06:48:12.897163 RX Vref 0 -> 0, step: 1
4654 06:48:12.897238
4655 06:48:12.900463 RX Delay -230 -> 252, step: 16
4656 06:48:12.903456 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4657 06:48:12.910183 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4658 06:48:12.913556 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4659 06:48:12.916948 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4660 06:48:12.920463 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4661 06:48:12.923847 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4662 06:48:12.930018 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4663 06:48:12.933361 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4664 06:48:12.936835 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4665 06:48:12.939734 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4666 06:48:12.946619 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4667 06:48:12.949569 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4668 06:48:12.953160 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4669 06:48:12.956536 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4670 06:48:12.962999 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4671 06:48:12.966299 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4672 06:48:12.966379 ==
4673 06:48:12.969864 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 06:48:12.972768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 06:48:12.972839 ==
4676 06:48:12.976102 DQS Delay:
4677 06:48:12.976179 DQS0 = 0, DQS1 = 0
4678 06:48:12.976240 DQM Delay:
4679 06:48:12.979387 DQM0 = 43, DQM1 = 39
4680 06:48:12.979489 DQ Delay:
4681 06:48:12.982810 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4682 06:48:12.986060 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4683 06:48:12.989672 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4684 06:48:12.993154 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4685 06:48:12.993236
4686 06:48:12.993299
4687 06:48:12.993357 ==
4688 06:48:12.995795 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 06:48:13.002558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 06:48:13.002641 ==
4691 06:48:13.002704
4692 06:48:13.002763
4693 06:48:13.006089 TX Vref Scan disable
4694 06:48:13.006170 == TX Byte 0 ==
4695 06:48:13.009406 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4696 06:48:13.015419 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4697 06:48:13.015500 == TX Byte 1 ==
4698 06:48:13.022115 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4699 06:48:13.025626 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4700 06:48:13.025704 ==
4701 06:48:13.029054 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 06:48:13.032591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 06:48:13.032668 ==
4704 06:48:13.032733
4705 06:48:13.032797
4706 06:48:13.035277 TX Vref Scan disable
4707 06:48:13.038796 == TX Byte 0 ==
4708 06:48:13.042086 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4709 06:48:13.045798 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4710 06:48:13.048395 == TX Byte 1 ==
4711 06:48:13.052067 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4712 06:48:13.055162 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4713 06:48:13.055233
4714 06:48:13.058500 [DATLAT]
4715 06:48:13.058570 Freq=600, CH1 RK1
4716 06:48:13.058630
4717 06:48:13.061761 DATLAT Default: 0x9
4718 06:48:13.061832 0, 0xFFFF, sum = 0
4719 06:48:13.064819 1, 0xFFFF, sum = 0
4720 06:48:13.064891 2, 0xFFFF, sum = 0
4721 06:48:13.068583 3, 0xFFFF, sum = 0
4722 06:48:13.068654 4, 0xFFFF, sum = 0
4723 06:48:13.071672 5, 0xFFFF, sum = 0
4724 06:48:13.071749 6, 0xFFFF, sum = 0
4725 06:48:13.074764 7, 0xFFFF, sum = 0
4726 06:48:13.074873 8, 0x0, sum = 1
4727 06:48:13.078183 9, 0x0, sum = 2
4728 06:48:13.078270 10, 0x0, sum = 3
4729 06:48:13.081424 11, 0x0, sum = 4
4730 06:48:13.081506 best_step = 9
4731 06:48:13.081575
4732 06:48:13.081637 ==
4733 06:48:13.084781 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 06:48:13.091444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 06:48:13.091546 ==
4736 06:48:13.091610 RX Vref Scan: 0
4737 06:48:13.091669
4738 06:48:13.095288 RX Vref 0 -> 0, step: 1
4739 06:48:13.095440
4740 06:48:13.097928 RX Delay -179 -> 252, step: 8
4741 06:48:13.101623 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4742 06:48:13.108266 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4743 06:48:13.111425 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4744 06:48:13.114795 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4745 06:48:13.118205 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4746 06:48:13.124283 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4747 06:48:13.127529 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4748 06:48:13.130933 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4749 06:48:13.134461 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4750 06:48:13.137843 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4751 06:48:13.144248 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4752 06:48:13.147411 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4753 06:48:13.150729 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4754 06:48:13.154034 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4755 06:48:13.160583 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4756 06:48:13.163740 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4757 06:48:13.163826 ==
4758 06:48:13.167657 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 06:48:13.170736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 06:48:13.170810 ==
4761 06:48:13.173852 DQS Delay:
4762 06:48:13.173930 DQS0 = 0, DQS1 = 0
4763 06:48:13.177229 DQM Delay:
4764 06:48:13.177308 DQM0 = 37, DQM1 = 35
4765 06:48:13.177369 DQ Delay:
4766 06:48:13.180721 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4767 06:48:13.183860 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4768 06:48:13.187244 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4769 06:48:13.190592 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4770 06:48:13.190676
4771 06:48:13.190739
4772 06:48:13.200780 [DQSOSCAuto] RK1, (LSB)MR18= 0x3357, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4773 06:48:13.203602 CH1 RK1: MR19=808, MR18=3357
4774 06:48:13.210079 CH1_RK1: MR19=0x808, MR18=0x3357, DQSOSC=393, MR23=63, INC=169, DEC=113
4775 06:48:13.210160 [RxdqsGatingPostProcess] freq 600
4776 06:48:13.217053 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4777 06:48:13.219860 Pre-setting of DQS Precalculation
4778 06:48:13.223292 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4779 06:48:13.233940 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4780 06:48:13.240056 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4781 06:48:13.240133
4782 06:48:13.240196
4783 06:48:13.243457 [Calibration Summary] 1200 Mbps
4784 06:48:13.243530 CH 0, Rank 0
4785 06:48:13.246189 SW Impedance : PASS
4786 06:48:13.249832 DUTY Scan : NO K
4787 06:48:13.249912 ZQ Calibration : PASS
4788 06:48:13.253398 Jitter Meter : NO K
4789 06:48:13.256527 CBT Training : PASS
4790 06:48:13.256604 Write leveling : PASS
4791 06:48:13.259414 RX DQS gating : PASS
4792 06:48:13.259491 RX DQ/DQS(RDDQC) : PASS
4793 06:48:13.262683 TX DQ/DQS : PASS
4794 06:48:13.265870 RX DATLAT : PASS
4795 06:48:13.265949 RX DQ/DQS(Engine): PASS
4796 06:48:13.269240 TX OE : NO K
4797 06:48:13.269311 All Pass.
4798 06:48:13.269378
4799 06:48:13.272347 CH 0, Rank 1
4800 06:48:13.272424 SW Impedance : PASS
4801 06:48:13.276059 DUTY Scan : NO K
4802 06:48:13.278871 ZQ Calibration : PASS
4803 06:48:13.278947 Jitter Meter : NO K
4804 06:48:13.282956 CBT Training : PASS
4805 06:48:13.286034 Write leveling : PASS
4806 06:48:13.286113 RX DQS gating : PASS
4807 06:48:13.288863 RX DQ/DQS(RDDQC) : PASS
4808 06:48:13.292550 TX DQ/DQS : PASS
4809 06:48:13.292634 RX DATLAT : PASS
4810 06:48:13.295930 RX DQ/DQS(Engine): PASS
4811 06:48:13.299004 TX OE : NO K
4812 06:48:13.299086 All Pass.
4813 06:48:13.299150
4814 06:48:13.299210 CH 1, Rank 0
4815 06:48:13.302485 SW Impedance : PASS
4816 06:48:13.305598 DUTY Scan : NO K
4817 06:48:13.305706 ZQ Calibration : PASS
4818 06:48:13.309147 Jitter Meter : NO K
4819 06:48:13.312018 CBT Training : PASS
4820 06:48:13.312126 Write leveling : PASS
4821 06:48:13.315192 RX DQS gating : PASS
4822 06:48:13.318596 RX DQ/DQS(RDDQC) : PASS
4823 06:48:13.318677 TX DQ/DQS : PASS
4824 06:48:13.322095 RX DATLAT : PASS
4825 06:48:13.325635 RX DQ/DQS(Engine): PASS
4826 06:48:13.325716 TX OE : NO K
4827 06:48:13.328935 All Pass.
4828 06:48:13.329016
4829 06:48:13.329079 CH 1, Rank 1
4830 06:48:13.332266 SW Impedance : PASS
4831 06:48:13.332348 DUTY Scan : NO K
4832 06:48:13.335129 ZQ Calibration : PASS
4833 06:48:13.338465 Jitter Meter : NO K
4834 06:48:13.338555 CBT Training : PASS
4835 06:48:13.342187 Write leveling : PASS
4836 06:48:13.342267 RX DQS gating : PASS
4837 06:48:13.345079 RX DQ/DQS(RDDQC) : PASS
4838 06:48:13.348426 TX DQ/DQS : PASS
4839 06:48:13.348528 RX DATLAT : PASS
4840 06:48:13.351807 RX DQ/DQS(Engine): PASS
4841 06:48:13.355431 TX OE : NO K
4842 06:48:13.355508 All Pass.
4843 06:48:13.355597
4844 06:48:13.358261 DramC Write-DBI off
4845 06:48:13.358346 PER_BANK_REFRESH: Hybrid Mode
4846 06:48:13.362242 TX_TRACKING: ON
4847 06:48:13.371335 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4848 06:48:13.375115 [FAST_K] Save calibration result to emmc
4849 06:48:13.378305 dramc_set_vcore_voltage set vcore to 662500
4850 06:48:13.378382 Read voltage for 933, 3
4851 06:48:13.381384 Vio18 = 0
4852 06:48:13.381462 Vcore = 662500
4853 06:48:13.381525 Vdram = 0
4854 06:48:13.384734 Vddq = 0
4855 06:48:13.384808 Vmddr = 0
4856 06:48:13.391562 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4857 06:48:13.394761 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4858 06:48:13.398376 MEM_TYPE=3, freq_sel=17
4859 06:48:13.401122 sv_algorithm_assistance_LP4_1600
4860 06:48:13.404403 ============ PULL DRAM RESETB DOWN ============
4861 06:48:13.407789 ========== PULL DRAM RESETB DOWN end =========
4862 06:48:13.414338 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4863 06:48:13.417851 ===================================
4864 06:48:13.417932 LPDDR4 DRAM CONFIGURATION
4865 06:48:13.421038 ===================================
4866 06:48:13.423993 EX_ROW_EN[0] = 0x0
4867 06:48:13.427463 EX_ROW_EN[1] = 0x0
4868 06:48:13.427564 LP4Y_EN = 0x0
4869 06:48:13.430825 WORK_FSP = 0x0
4870 06:48:13.430906 WL = 0x3
4871 06:48:13.434300 RL = 0x3
4872 06:48:13.434380 BL = 0x2
4873 06:48:13.437151 RPST = 0x0
4874 06:48:13.437241 RD_PRE = 0x0
4875 06:48:13.440753 WR_PRE = 0x1
4876 06:48:13.440850 WR_PST = 0x0
4877 06:48:13.443662 DBI_WR = 0x0
4878 06:48:13.443743 DBI_RD = 0x0
4879 06:48:13.447318 OTF = 0x1
4880 06:48:13.450505 ===================================
4881 06:48:13.453767 ===================================
4882 06:48:13.453848 ANA top config
4883 06:48:13.456721 ===================================
4884 06:48:13.460253 DLL_ASYNC_EN = 0
4885 06:48:13.463400 ALL_SLAVE_EN = 1
4886 06:48:13.466698 NEW_RANK_MODE = 1
4887 06:48:13.466780 DLL_IDLE_MODE = 1
4888 06:48:13.470261 LP45_APHY_COMB_EN = 1
4889 06:48:13.473272 TX_ODT_DIS = 1
4890 06:48:13.477182 NEW_8X_MODE = 1
4891 06:48:13.480168 ===================================
4892 06:48:13.483390 ===================================
4893 06:48:13.486613 data_rate = 1866
4894 06:48:13.490208 CKR = 1
4895 06:48:13.490289 DQ_P2S_RATIO = 8
4896 06:48:13.493467 ===================================
4897 06:48:13.496222 CA_P2S_RATIO = 8
4898 06:48:13.499570 DQ_CA_OPEN = 0
4899 06:48:13.502950 DQ_SEMI_OPEN = 0
4900 06:48:13.506454 CA_SEMI_OPEN = 0
4901 06:48:13.509520 CA_FULL_RATE = 0
4902 06:48:13.509601 DQ_CKDIV4_EN = 1
4903 06:48:13.512795 CA_CKDIV4_EN = 1
4904 06:48:13.516183 CA_PREDIV_EN = 0
4905 06:48:13.519529 PH8_DLY = 0
4906 06:48:13.522818 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4907 06:48:13.526601 DQ_AAMCK_DIV = 4
4908 06:48:13.526695 CA_AAMCK_DIV = 4
4909 06:48:13.529456 CA_ADMCK_DIV = 4
4910 06:48:13.532680 DQ_TRACK_CA_EN = 0
4911 06:48:13.536376 CA_PICK = 933
4912 06:48:13.539511 CA_MCKIO = 933
4913 06:48:13.542797 MCKIO_SEMI = 0
4914 06:48:13.545908 PLL_FREQ = 3732
4915 06:48:13.549301 DQ_UI_PI_RATIO = 32
4916 06:48:13.549391 CA_UI_PI_RATIO = 0
4917 06:48:13.552460 ===================================
4918 06:48:13.555518 ===================================
4919 06:48:13.559491 memory_type:LPDDR4
4920 06:48:13.562346 GP_NUM : 10
4921 06:48:13.562427 SRAM_EN : 1
4922 06:48:13.565490 MD32_EN : 0
4923 06:48:13.568761 ===================================
4924 06:48:13.572514 [ANA_INIT] >>>>>>>>>>>>>>
4925 06:48:13.575721 <<<<<< [CONFIGURE PHASE]: ANA_TX
4926 06:48:13.578846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4927 06:48:13.582157 ===================================
4928 06:48:13.582232 data_rate = 1866,PCW = 0X8f00
4929 06:48:13.585158 ===================================
4930 06:48:13.591862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4931 06:48:13.595105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 06:48:13.602198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 06:48:13.605282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4934 06:48:13.608205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4935 06:48:13.611569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4936 06:48:13.614859 [ANA_INIT] flow start
4937 06:48:13.618611 [ANA_INIT] PLL >>>>>>>>
4938 06:48:13.618692 [ANA_INIT] PLL <<<<<<<<
4939 06:48:13.621317 [ANA_INIT] MIDPI >>>>>>>>
4940 06:48:13.624703 [ANA_INIT] MIDPI <<<<<<<<
4941 06:48:13.624785 [ANA_INIT] DLL >>>>>>>>
4942 06:48:13.628272 [ANA_INIT] flow end
4943 06:48:13.631660 ============ LP4 DIFF to SE enter ============
4944 06:48:13.638197 ============ LP4 DIFF to SE exit ============
4945 06:48:13.638278 [ANA_INIT] <<<<<<<<<<<<<
4946 06:48:13.641904 [Flow] Enable top DCM control >>>>>
4947 06:48:13.644508 [Flow] Enable top DCM control <<<<<
4948 06:48:13.647856 Enable DLL master slave shuffle
4949 06:48:13.654535 ==============================================================
4950 06:48:13.654616 Gating Mode config
4951 06:48:13.660865 ==============================================================
4952 06:48:13.664380 Config description:
4953 06:48:13.673956 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4954 06:48:13.680713 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4955 06:48:13.684090 SELPH_MODE 0: By rank 1: By Phase
4956 06:48:13.691021 ==============================================================
4957 06:48:13.694135 GAT_TRACK_EN = 1
4958 06:48:13.694217 RX_GATING_MODE = 2
4959 06:48:13.697656 RX_GATING_TRACK_MODE = 2
4960 06:48:13.700456 SELPH_MODE = 1
4961 06:48:13.703769 PICG_EARLY_EN = 1
4962 06:48:13.707333 VALID_LAT_VALUE = 1
4963 06:48:13.714138 ==============================================================
4964 06:48:13.716845 Enter into Gating configuration >>>>
4965 06:48:13.720168 Exit from Gating configuration <<<<
4966 06:48:13.723485 Enter into DVFS_PRE_config >>>>>
4967 06:48:13.733444 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4968 06:48:13.737227 Exit from DVFS_PRE_config <<<<<
4969 06:48:13.740240 Enter into PICG configuration >>>>
4970 06:48:13.743814 Exit from PICG configuration <<<<
4971 06:48:13.747118 [RX_INPUT] configuration >>>>>
4972 06:48:13.750220 [RX_INPUT] configuration <<<<<
4973 06:48:13.753360 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4974 06:48:13.759988 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4975 06:48:13.766878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 06:48:13.773536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 06:48:13.779848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 06:48:13.783049 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 06:48:13.789723 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4980 06:48:13.792942 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4981 06:48:13.796701 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4982 06:48:13.799635 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4983 06:48:13.805930 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4984 06:48:13.809131 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 06:48:13.812319 ===================================
4986 06:48:13.816292 LPDDR4 DRAM CONFIGURATION
4987 06:48:13.818852 ===================================
4988 06:48:13.818933 EX_ROW_EN[0] = 0x0
4989 06:48:13.822551 EX_ROW_EN[1] = 0x0
4990 06:48:13.822625 LP4Y_EN = 0x0
4991 06:48:13.825437 WORK_FSP = 0x0
4992 06:48:13.825505 WL = 0x3
4993 06:48:13.828877 RL = 0x3
4994 06:48:13.832113 BL = 0x2
4995 06:48:13.832211 RPST = 0x0
4996 06:48:13.835272 RD_PRE = 0x0
4997 06:48:13.835370 WR_PRE = 0x1
4998 06:48:13.839396 WR_PST = 0x0
4999 06:48:13.839469 DBI_WR = 0x0
5000 06:48:13.841910 DBI_RD = 0x0
5001 06:48:13.841986 OTF = 0x1
5002 06:48:13.845427 ===================================
5003 06:48:13.848769 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5004 06:48:13.855383 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5005 06:48:13.859037 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 06:48:13.862459 ===================================
5007 06:48:13.865498 LPDDR4 DRAM CONFIGURATION
5008 06:48:13.869062 ===================================
5009 06:48:13.869140 EX_ROW_EN[0] = 0x10
5010 06:48:13.871707 EX_ROW_EN[1] = 0x0
5011 06:48:13.871778 LP4Y_EN = 0x0
5012 06:48:13.875068 WORK_FSP = 0x0
5013 06:48:13.875142 WL = 0x3
5014 06:48:13.878529 RL = 0x3
5015 06:48:13.881683 BL = 0x2
5016 06:48:13.881756 RPST = 0x0
5017 06:48:13.885760 RD_PRE = 0x0
5018 06:48:13.885833 WR_PRE = 0x1
5019 06:48:13.888307 WR_PST = 0x0
5020 06:48:13.888378 DBI_WR = 0x0
5021 06:48:13.891490 DBI_RD = 0x0
5022 06:48:13.891559 OTF = 0x1
5023 06:48:13.895071 ===================================
5024 06:48:13.901846 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5025 06:48:13.906139 nWR fixed to 30
5026 06:48:13.909285 [ModeRegInit_LP4] CH0 RK0
5027 06:48:13.909358 [ModeRegInit_LP4] CH0 RK1
5028 06:48:13.912351 [ModeRegInit_LP4] CH1 RK0
5029 06:48:13.915796 [ModeRegInit_LP4] CH1 RK1
5030 06:48:13.915903 match AC timing 9
5031 06:48:13.921771 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5032 06:48:13.925429 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5033 06:48:13.928724 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5034 06:48:13.935136 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5035 06:48:13.938185 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5036 06:48:13.938285 ==
5037 06:48:13.941775 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 06:48:13.945329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 06:48:13.948286 ==
5040 06:48:13.951981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 06:48:13.958093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5042 06:48:13.961609 [CA 0] Center 37 (7~68) winsize 62
5043 06:48:13.965049 [CA 1] Center 37 (7~68) winsize 62
5044 06:48:13.968153 [CA 2] Center 34 (4~64) winsize 61
5045 06:48:13.971810 [CA 3] Center 34 (4~65) winsize 62
5046 06:48:13.975058 [CA 4] Center 33 (3~63) winsize 61
5047 06:48:13.978198 [CA 5] Center 32 (2~63) winsize 62
5048 06:48:13.978265
5049 06:48:13.981569 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5050 06:48:13.981652
5051 06:48:13.984546 [CATrainingPosCal] consider 1 rank data
5052 06:48:13.988332 u2DelayCellTimex100 = 270/100 ps
5053 06:48:13.991089 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5054 06:48:13.994505 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5055 06:48:13.997785 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5056 06:48:14.004498 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5057 06:48:14.007864 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5058 06:48:14.011131 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5059 06:48:14.011212
5060 06:48:14.014422 CA PerBit enable=1, Macro0, CA PI delay=32
5061 06:48:14.014503
5062 06:48:14.017776 [CBTSetCACLKResult] CA Dly = 32
5063 06:48:14.017855 CS Dly: 5 (0~36)
5064 06:48:14.017918 ==
5065 06:48:14.021079 Dram Type= 6, Freq= 0, CH_0, rank 1
5066 06:48:14.027592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 06:48:14.027675 ==
5068 06:48:14.030828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 06:48:14.037150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5070 06:48:14.040604 [CA 0] Center 38 (8~68) winsize 61
5071 06:48:14.044305 [CA 1] Center 37 (7~68) winsize 62
5072 06:48:14.047150 [CA 2] Center 35 (5~65) winsize 61
5073 06:48:14.050548 [CA 3] Center 34 (4~65) winsize 62
5074 06:48:14.053848 [CA 4] Center 33 (3~64) winsize 62
5075 06:48:14.057296 [CA 5] Center 32 (2~63) winsize 62
5076 06:48:14.057378
5077 06:48:14.060874 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5078 06:48:14.060956
5079 06:48:14.064023 [CATrainingPosCal] consider 2 rank data
5080 06:48:14.067140 u2DelayCellTimex100 = 270/100 ps
5081 06:48:14.070614 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5082 06:48:14.077216 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5083 06:48:14.079938 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5084 06:48:14.083530 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5085 06:48:14.087666 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5086 06:48:14.090355 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5087 06:48:14.090437
5088 06:48:14.093210 CA PerBit enable=1, Macro0, CA PI delay=32
5089 06:48:14.093293
5090 06:48:14.096668 [CBTSetCACLKResult] CA Dly = 32
5091 06:48:14.100569 CS Dly: 6 (0~39)
5092 06:48:14.100651
5093 06:48:14.103592 ----->DramcWriteLeveling(PI) begin...
5094 06:48:14.103675 ==
5095 06:48:14.106598 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 06:48:14.109862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 06:48:14.109944 ==
5098 06:48:14.113360 Write leveling (Byte 0): 31 => 31
5099 06:48:14.116868 Write leveling (Byte 1): 29 => 29
5100 06:48:14.119705 DramcWriteLeveling(PI) end<-----
5101 06:48:14.119787
5102 06:48:14.119851 ==
5103 06:48:14.123119 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 06:48:14.126140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 06:48:14.126222 ==
5106 06:48:14.129963 [Gating] SW mode calibration
5107 06:48:14.136671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 06:48:14.142829 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5109 06:48:14.146063 0 14 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
5110 06:48:14.152704 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 06:48:14.155930 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 06:48:14.159388 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 06:48:14.165942 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 06:48:14.169156 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 06:48:14.172216 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 06:48:14.178900 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5117 06:48:14.182357 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5118 06:48:14.185721 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5119 06:48:14.191969 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 06:48:14.195177 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 06:48:14.199033 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 06:48:14.205150 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 06:48:14.208780 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5124 06:48:14.211991 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5125 06:48:14.218651 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5126 06:48:14.222447 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 06:48:14.224992 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 06:48:14.231568 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 06:48:14.234809 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 06:48:14.238554 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 06:48:14.245085 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5132 06:48:14.248239 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5133 06:48:14.251909 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5134 06:48:14.258277 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5135 06:48:14.261503 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 06:48:14.264641 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 06:48:14.271570 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 06:48:14.274526 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 06:48:14.277858 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 06:48:14.284554 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 06:48:14.287682 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 06:48:14.291328 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 06:48:14.297397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 06:48:14.300925 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 06:48:14.304187 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 06:48:14.310864 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 06:48:14.314230 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 06:48:14.317162 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5149 06:48:14.320597 Total UI for P1: 0, mck2ui 16
5150 06:48:14.323909 best dqsien dly found for B0: ( 1, 2, 24)
5151 06:48:14.330176 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5152 06:48:14.333597 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 06:48:14.337124 Total UI for P1: 0, mck2ui 16
5154 06:48:14.340139 best dqsien dly found for B1: ( 1, 3, 2)
5155 06:48:14.343346 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5156 06:48:14.347062 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5157 06:48:14.347144
5158 06:48:14.350197 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5159 06:48:14.353390 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5160 06:48:14.356777 [Gating] SW calibration Done
5161 06:48:14.356859 ==
5162 06:48:14.359802 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 06:48:14.363224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 06:48:14.366818 ==
5165 06:48:14.366900 RX Vref Scan: 0
5166 06:48:14.366965
5167 06:48:14.370158 RX Vref 0 -> 0, step: 1
5168 06:48:14.370239
5169 06:48:14.373490 RX Delay -80 -> 252, step: 8
5170 06:48:14.376386 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5171 06:48:14.379783 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5172 06:48:14.383119 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5173 06:48:14.386316 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5174 06:48:14.389803 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5175 06:48:14.395804 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5176 06:48:14.399152 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5177 06:48:14.402538 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5178 06:48:14.405872 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5179 06:48:14.409199 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5180 06:48:14.415953 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5181 06:48:14.419183 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5182 06:48:14.422668 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5183 06:48:14.425541 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5184 06:48:14.429075 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5185 06:48:14.432449 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5186 06:48:14.435353 ==
5187 06:48:14.438886 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 06:48:14.442088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 06:48:14.442170 ==
5190 06:48:14.442235 DQS Delay:
5191 06:48:14.445582 DQS0 = 0, DQS1 = 0
5192 06:48:14.445665 DQM Delay:
5193 06:48:14.449218 DQM0 = 98, DQM1 = 89
5194 06:48:14.449299 DQ Delay:
5195 06:48:14.452341 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5196 06:48:14.455447 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5197 06:48:14.458822 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5198 06:48:14.461923 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5199 06:48:14.461993
5200 06:48:14.462054
5201 06:48:14.462119 ==
5202 06:48:14.465094 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 06:48:14.468584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 06:48:14.468655 ==
5205 06:48:14.471714
5206 06:48:14.471781
5207 06:48:14.471843 TX Vref Scan disable
5208 06:48:14.475134 == TX Byte 0 ==
5209 06:48:14.478592 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5210 06:48:14.481787 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5211 06:48:14.485015 == TX Byte 1 ==
5212 06:48:14.488288 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5213 06:48:14.491647 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5214 06:48:14.491721 ==
5215 06:48:14.495130 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 06:48:14.501393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 06:48:14.501502 ==
5218 06:48:14.501593
5219 06:48:14.501681
5220 06:48:14.504619 TX Vref Scan disable
5221 06:48:14.504688 == TX Byte 0 ==
5222 06:48:14.511479 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5223 06:48:14.514785 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5224 06:48:14.514885 == TX Byte 1 ==
5225 06:48:14.521249 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5226 06:48:14.524368 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5227 06:48:14.524441
5228 06:48:14.524502 [DATLAT]
5229 06:48:14.527751 Freq=933, CH0 RK0
5230 06:48:14.527828
5231 06:48:14.527889 DATLAT Default: 0xd
5232 06:48:14.531251 0, 0xFFFF, sum = 0
5233 06:48:14.531353 1, 0xFFFF, sum = 0
5234 06:48:14.534322 2, 0xFFFF, sum = 0
5235 06:48:14.534418 3, 0xFFFF, sum = 0
5236 06:48:14.537550 4, 0xFFFF, sum = 0
5237 06:48:14.537620 5, 0xFFFF, sum = 0
5238 06:48:14.541026 6, 0xFFFF, sum = 0
5239 06:48:14.544411 7, 0xFFFF, sum = 0
5240 06:48:14.544481 8, 0xFFFF, sum = 0
5241 06:48:14.547787 9, 0xFFFF, sum = 0
5242 06:48:14.547858 10, 0x0, sum = 1
5243 06:48:14.547919 11, 0x0, sum = 2
5244 06:48:14.551550 12, 0x0, sum = 3
5245 06:48:14.551651 13, 0x0, sum = 4
5246 06:48:14.554222 best_step = 11
5247 06:48:14.554292
5248 06:48:14.554353 ==
5249 06:48:14.557167 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 06:48:14.560741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 06:48:14.560812 ==
5252 06:48:14.563861 RX Vref Scan: 1
5253 06:48:14.563929
5254 06:48:14.567700 RX Vref 0 -> 0, step: 1
5255 06:48:14.567774
5256 06:48:14.567834 RX Delay -61 -> 252, step: 4
5257 06:48:14.567892
5258 06:48:14.570597 Set Vref, RX VrefLevel [Byte0]: 52
5259 06:48:14.573714 [Byte1]: 49
5260 06:48:14.578286
5261 06:48:14.578354 Final RX Vref Byte 0 = 52 to rank0
5262 06:48:14.581703 Final RX Vref Byte 1 = 49 to rank0
5263 06:48:14.584844 Final RX Vref Byte 0 = 52 to rank1
5264 06:48:14.588057 Final RX Vref Byte 1 = 49 to rank1==
5265 06:48:14.591506 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 06:48:14.598249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 06:48:14.598327 ==
5268 06:48:14.598389 DQS Delay:
5269 06:48:14.598447 DQS0 = 0, DQS1 = 0
5270 06:48:14.601720 DQM Delay:
5271 06:48:14.601817 DQM0 = 99, DQM1 = 87
5272 06:48:14.605102 DQ Delay:
5273 06:48:14.608335 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5274 06:48:14.611217 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5275 06:48:14.615058 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5276 06:48:14.618268 DQ12 =94, DQ13 =90, DQ14 =94, DQ15 =96
5277 06:48:14.618337
5278 06:48:14.618398
5279 06:48:14.624675 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5280 06:48:14.628156 CH0 RK0: MR19=505, MR18=1F19
5281 06:48:14.634874 CH0_RK0: MR19=0x505, MR18=0x1F19, DQSOSC=412, MR23=63, INC=63, DEC=42
5282 06:48:14.634949
5283 06:48:14.637737 ----->DramcWriteLeveling(PI) begin...
5284 06:48:14.637809 ==
5285 06:48:14.641319 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 06:48:14.644414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 06:48:14.644484 ==
5288 06:48:14.647777 Write leveling (Byte 0): 31 => 31
5289 06:48:14.650893 Write leveling (Byte 1): 28 => 28
5290 06:48:14.654021 DramcWriteLeveling(PI) end<-----
5291 06:48:14.654096
5292 06:48:14.654158 ==
5293 06:48:14.657450 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 06:48:14.664081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 06:48:14.664152 ==
5296 06:48:14.664213 [Gating] SW mode calibration
5297 06:48:14.674667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5298 06:48:14.677269 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5299 06:48:14.680875 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
5300 06:48:14.687422 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 06:48:14.690563 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 06:48:14.697278 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 06:48:14.700413 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 06:48:14.703679 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 06:48:14.710478 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5306 06:48:14.713810 0 14 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
5307 06:48:14.716966 0 15 0 | B1->B0 | 3030 2525 | 0 0 | (1 1) (0 0)
5308 06:48:14.723131 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 06:48:14.726802 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 06:48:14.730044 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 06:48:14.736811 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 06:48:14.739687 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 06:48:14.743124 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5314 06:48:14.749798 0 15 28 | B1->B0 | 2a2a 4343 | 0 0 | (0 0) (0 0)
5315 06:48:14.752733 1 0 0 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5316 06:48:14.757431 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 06:48:14.763073 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 06:48:14.765945 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 06:48:14.769474 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 06:48:14.776025 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 06:48:14.779427 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 06:48:14.782594 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5323 06:48:14.789406 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5324 06:48:14.792951 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 06:48:14.796315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 06:48:14.802128 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 06:48:14.806013 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 06:48:14.808732 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 06:48:14.815867 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 06:48:14.818786 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 06:48:14.822185 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 06:48:14.828503 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 06:48:14.831905 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 06:48:14.835179 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 06:48:14.841773 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 06:48:14.845155 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 06:48:14.848137 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5338 06:48:14.855072 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5339 06:48:14.858480 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 06:48:14.861423 Total UI for P1: 0, mck2ui 16
5341 06:48:14.865187 best dqsien dly found for B0: ( 1, 2, 26)
5342 06:48:14.868283 Total UI for P1: 0, mck2ui 16
5343 06:48:14.871358 best dqsien dly found for B1: ( 1, 2, 28)
5344 06:48:14.874532 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5345 06:48:14.878062 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5346 06:48:14.878144
5347 06:48:14.881352 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5348 06:48:14.884752 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5349 06:48:14.888134 [Gating] SW calibration Done
5350 06:48:14.888216 ==
5351 06:48:14.891083 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 06:48:14.894514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 06:48:14.897924 ==
5354 06:48:14.898006 RX Vref Scan: 0
5355 06:48:14.898070
5356 06:48:14.901285 RX Vref 0 -> 0, step: 1
5357 06:48:14.901366
5358 06:48:14.904409 RX Delay -80 -> 252, step: 8
5359 06:48:14.907717 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5360 06:48:14.911175 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5361 06:48:14.914606 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5362 06:48:14.917529 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5363 06:48:14.921179 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5364 06:48:14.927471 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5365 06:48:14.930690 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5366 06:48:14.934688 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5367 06:48:14.937177 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5368 06:48:14.940903 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5369 06:48:14.947750 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5370 06:48:14.950534 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5371 06:48:14.953672 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5372 06:48:14.957106 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5373 06:48:14.960828 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5374 06:48:14.963854 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5375 06:48:14.967055 ==
5376 06:48:14.970191 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 06:48:14.973578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 06:48:14.973661 ==
5379 06:48:14.973726 DQS Delay:
5380 06:48:14.977153 DQS0 = 0, DQS1 = 0
5381 06:48:14.977235 DQM Delay:
5382 06:48:14.980361 DQM0 = 97, DQM1 = 89
5383 06:48:14.980443 DQ Delay:
5384 06:48:14.983172 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =95
5385 06:48:14.986533 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5386 06:48:14.990534 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5387 06:48:14.993582 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5388 06:48:14.993664
5389 06:48:14.993727
5390 06:48:14.993786 ==
5391 06:48:14.996487 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 06:48:14.999971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 06:48:15.000054 ==
5394 06:48:15.000119
5395 06:48:15.003318
5396 06:48:15.003463 TX Vref Scan disable
5397 06:48:15.006494 == TX Byte 0 ==
5398 06:48:15.010062 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5399 06:48:15.013112 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5400 06:48:15.016792 == TX Byte 1 ==
5401 06:48:15.020122 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5402 06:48:15.023003 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5403 06:48:15.023085 ==
5404 06:48:15.026274 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 06:48:15.033047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 06:48:15.033155 ==
5407 06:48:15.033249
5408 06:48:15.033325
5409 06:48:15.033383 TX Vref Scan disable
5410 06:48:15.037324 == TX Byte 0 ==
5411 06:48:15.040402 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5412 06:48:15.047539 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5413 06:48:15.047621 == TX Byte 1 ==
5414 06:48:15.050254 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5415 06:48:15.056738 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5416 06:48:15.056821
5417 06:48:15.056885 [DATLAT]
5418 06:48:15.056946 Freq=933, CH0 RK1
5419 06:48:15.057004
5420 06:48:15.060588 DATLAT Default: 0xb
5421 06:48:15.063585 0, 0xFFFF, sum = 0
5422 06:48:15.063669 1, 0xFFFF, sum = 0
5423 06:48:15.066834 2, 0xFFFF, sum = 0
5424 06:48:15.066917 3, 0xFFFF, sum = 0
5425 06:48:15.069850 4, 0xFFFF, sum = 0
5426 06:48:15.069933 5, 0xFFFF, sum = 0
5427 06:48:15.073234 6, 0xFFFF, sum = 0
5428 06:48:15.073318 7, 0xFFFF, sum = 0
5429 06:48:15.076635 8, 0xFFFF, sum = 0
5430 06:48:15.076718 9, 0xFFFF, sum = 0
5431 06:48:15.080051 10, 0x0, sum = 1
5432 06:48:15.080135 11, 0x0, sum = 2
5433 06:48:15.083183 12, 0x0, sum = 3
5434 06:48:15.083294 13, 0x0, sum = 4
5435 06:48:15.086444 best_step = 11
5436 06:48:15.086519
5437 06:48:15.086603 ==
5438 06:48:15.090003 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 06:48:15.093337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 06:48:15.093438 ==
5441 06:48:15.096403 RX Vref Scan: 0
5442 06:48:15.096485
5443 06:48:15.096567 RX Vref 0 -> 0, step: 1
5444 06:48:15.096645
5445 06:48:15.099662 RX Delay -53 -> 252, step: 4
5446 06:48:15.106130 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5447 06:48:15.109932 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5448 06:48:15.112496 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5449 06:48:15.115736 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5450 06:48:15.119169 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5451 06:48:15.125749 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5452 06:48:15.129095 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5453 06:48:15.132233 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5454 06:48:15.135774 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5455 06:48:15.138731 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5456 06:48:15.145539 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5457 06:48:15.148941 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5458 06:48:15.152361 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5459 06:48:15.155434 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5460 06:48:15.158661 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5461 06:48:15.162204 iDelay=195, Bit 15, Center 92 (3 ~ 182) 180
5462 06:48:15.165201 ==
5463 06:48:15.168644 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 06:48:15.171827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 06:48:15.171910 ==
5466 06:48:15.171975 DQS Delay:
5467 06:48:15.174954 DQS0 = 0, DQS1 = 0
5468 06:48:15.175035 DQM Delay:
5469 06:48:15.178103 DQM0 = 97, DQM1 = 87
5470 06:48:15.178214 DQ Delay:
5471 06:48:15.181544 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5472 06:48:15.184725 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5473 06:48:15.188263 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5474 06:48:15.191592 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5475 06:48:15.191674
5476 06:48:15.191738
5477 06:48:15.201286 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5478 06:48:15.201369 CH0 RK1: MR19=505, MR18=1B18
5479 06:48:15.207897 CH0_RK1: MR19=0x505, MR18=0x1B18, DQSOSC=413, MR23=63, INC=63, DEC=42
5480 06:48:15.211285 [RxdqsGatingPostProcess] freq 933
5481 06:48:15.217435 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5482 06:48:15.221144 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 06:48:15.223912 best DQS1 dly(2T, 0.5T) = (0, 11)
5484 06:48:15.227267 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 06:48:15.230625 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5486 06:48:15.234630 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 06:48:15.234712 best DQS1 dly(2T, 0.5T) = (0, 10)
5488 06:48:15.237170 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 06:48:15.241083 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5490 06:48:15.243763 Pre-setting of DQS Precalculation
5491 06:48:15.250376 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5492 06:48:15.250459 ==
5493 06:48:15.254195 Dram Type= 6, Freq= 0, CH_1, rank 0
5494 06:48:15.257437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 06:48:15.257520 ==
5496 06:48:15.263852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5497 06:48:15.270422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5498 06:48:15.273288 [CA 0] Center 36 (6~67) winsize 62
5499 06:48:15.276559 [CA 1] Center 36 (6~67) winsize 62
5500 06:48:15.280161 [CA 2] Center 34 (4~64) winsize 61
5501 06:48:15.283228 [CA 3] Center 34 (4~64) winsize 61
5502 06:48:15.286831 [CA 4] Center 34 (4~64) winsize 61
5503 06:48:15.289981 [CA 5] Center 33 (3~64) winsize 62
5504 06:48:15.290064
5505 06:48:15.293112 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5506 06:48:15.293211
5507 06:48:15.296262 [CATrainingPosCal] consider 1 rank data
5508 06:48:15.299797 u2DelayCellTimex100 = 270/100 ps
5509 06:48:15.302988 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5510 06:48:15.306388 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5511 06:48:15.309851 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5512 06:48:15.312765 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5513 06:48:15.319182 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5514 06:48:15.322788 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5515 06:48:15.322870
5516 06:48:15.326049 CA PerBit enable=1, Macro0, CA PI delay=33
5517 06:48:15.326131
5518 06:48:15.329517 [CBTSetCACLKResult] CA Dly = 33
5519 06:48:15.329622 CS Dly: 5 (0~36)
5520 06:48:15.329689 ==
5521 06:48:15.332482 Dram Type= 6, Freq= 0, CH_1, rank 1
5522 06:48:15.339300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 06:48:15.339446 ==
5524 06:48:15.342402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 06:48:15.349169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 06:48:15.352403 [CA 0] Center 36 (6~67) winsize 62
5527 06:48:15.356090 [CA 1] Center 36 (6~67) winsize 62
5528 06:48:15.358783 [CA 2] Center 34 (4~65) winsize 62
5529 06:48:15.362139 [CA 3] Center 33 (3~64) winsize 62
5530 06:48:15.365834 [CA 4] Center 33 (3~64) winsize 62
5531 06:48:15.368869 [CA 5] Center 33 (3~64) winsize 62
5532 06:48:15.368951
5533 06:48:15.372096 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 06:48:15.372204
5535 06:48:15.375465 [CATrainingPosCal] consider 2 rank data
5536 06:48:15.378813 u2DelayCellTimex100 = 270/100 ps
5537 06:48:15.381679 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 06:48:15.388438 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5539 06:48:15.391548 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 06:48:15.395601 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5541 06:48:15.398332 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5542 06:48:15.401318 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5543 06:48:15.401400
5544 06:48:15.404765 CA PerBit enable=1, Macro0, CA PI delay=33
5545 06:48:15.404871
5546 06:48:15.408121 [CBTSetCACLKResult] CA Dly = 33
5547 06:48:15.411645 CS Dly: 6 (0~38)
5548 06:48:15.411754
5549 06:48:15.415053 ----->DramcWriteLeveling(PI) begin...
5550 06:48:15.415136 ==
5551 06:48:15.417954 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 06:48:15.421113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 06:48:15.421218 ==
5554 06:48:15.424381 Write leveling (Byte 0): 27 => 27
5555 06:48:15.427818 Write leveling (Byte 1): 28 => 28
5556 06:48:15.431154 DramcWriteLeveling(PI) end<-----
5557 06:48:15.431236
5558 06:48:15.431301 ==
5559 06:48:15.434581 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 06:48:15.437515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 06:48:15.437627 ==
5562 06:48:15.440930 [Gating] SW mode calibration
5563 06:48:15.447535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5564 06:48:15.454401 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5565 06:48:15.457784 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5566 06:48:15.460712 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 06:48:15.467538 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 06:48:15.471078 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 06:48:15.474324 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 06:48:15.480653 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 06:48:15.483880 0 14 24 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
5572 06:48:15.487134 0 14 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (1 0)
5573 06:48:15.493818 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 06:48:15.497092 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 06:48:15.500471 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 06:48:15.507515 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 06:48:15.510280 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 06:48:15.514229 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 06:48:15.520337 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5580 06:48:15.523356 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
5581 06:48:15.527199 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 06:48:15.534191 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 06:48:15.536780 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 06:48:15.540202 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 06:48:15.546822 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 06:48:15.550259 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 06:48:15.553122 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 06:48:15.560573 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 06:48:15.563484 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 06:48:15.566401 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 06:48:15.573113 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 06:48:15.576346 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 06:48:15.579748 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 06:48:15.586364 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 06:48:15.589803 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 06:48:15.593035 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 06:48:15.599343 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 06:48:15.602627 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 06:48:15.606113 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 06:48:15.612916 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 06:48:15.616329 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 06:48:15.619553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 06:48:15.625691 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5604 06:48:15.629397 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5605 06:48:15.632418 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 06:48:15.636083 Total UI for P1: 0, mck2ui 16
5607 06:48:15.638896 best dqsien dly found for B0: ( 1, 2, 28)
5608 06:48:15.642692 Total UI for P1: 0, mck2ui 16
5609 06:48:15.645486 best dqsien dly found for B1: ( 1, 2, 26)
5610 06:48:15.649144 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5611 06:48:15.652204 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5612 06:48:15.652286
5613 06:48:15.658634 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5614 06:48:15.661978 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5615 06:48:15.665294 [Gating] SW calibration Done
5616 06:48:15.665376 ==
5617 06:48:15.668454 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 06:48:15.671986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 06:48:15.672069 ==
5620 06:48:15.672134 RX Vref Scan: 0
5621 06:48:15.674955
5622 06:48:15.675036 RX Vref 0 -> 0, step: 1
5623 06:48:15.675101
5624 06:48:15.678214 RX Delay -80 -> 252, step: 8
5625 06:48:15.681692 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5626 06:48:15.685227 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5627 06:48:15.691569 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5628 06:48:15.695094 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5629 06:48:15.697864 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5630 06:48:15.701565 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5631 06:48:15.704795 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5632 06:48:15.707998 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5633 06:48:15.715100 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5634 06:48:15.718117 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5635 06:48:15.721062 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5636 06:48:15.724352 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5637 06:48:15.727589 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5638 06:48:15.734325 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5639 06:48:15.737710 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5640 06:48:15.740753 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5641 06:48:15.740835 ==
5642 06:48:15.744254 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 06:48:15.747548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 06:48:15.747631 ==
5645 06:48:15.750894 DQS Delay:
5646 06:48:15.750976 DQS0 = 0, DQS1 = 0
5647 06:48:15.754233 DQM Delay:
5648 06:48:15.754315 DQM0 = 99, DQM1 = 96
5649 06:48:15.754380 DQ Delay:
5650 06:48:15.757716 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5651 06:48:15.760700 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =99
5652 06:48:15.764033 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5653 06:48:15.770597 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5654 06:48:15.770737
5655 06:48:15.770802
5656 06:48:15.770862 ==
5657 06:48:15.773660 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 06:48:15.777456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 06:48:15.777539 ==
5660 06:48:15.777603
5661 06:48:15.777663
5662 06:48:15.780703 TX Vref Scan disable
5663 06:48:15.780786 == TX Byte 0 ==
5664 06:48:15.787088 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5665 06:48:15.790325 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5666 06:48:15.790438 == TX Byte 1 ==
5667 06:48:15.796908 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5668 06:48:15.800200 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5669 06:48:15.800282 ==
5670 06:48:15.803677 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 06:48:15.806895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 06:48:15.806977 ==
5673 06:48:15.807043
5674 06:48:15.810160
5675 06:48:15.810242 TX Vref Scan disable
5676 06:48:15.813914 == TX Byte 0 ==
5677 06:48:15.816592 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5678 06:48:15.819812 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5679 06:48:15.823390 == TX Byte 1 ==
5680 06:48:15.827146 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5681 06:48:15.829927 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5682 06:48:15.833206
5683 06:48:15.833288 [DATLAT]
5684 06:48:15.833352 Freq=933, CH1 RK0
5685 06:48:15.833413
5686 06:48:15.836582 DATLAT Default: 0xd
5687 06:48:15.836664 0, 0xFFFF, sum = 0
5688 06:48:15.840025 1, 0xFFFF, sum = 0
5689 06:48:15.840108 2, 0xFFFF, sum = 0
5690 06:48:15.843098 3, 0xFFFF, sum = 0
5691 06:48:15.846622 4, 0xFFFF, sum = 0
5692 06:48:15.846706 5, 0xFFFF, sum = 0
5693 06:48:15.849572 6, 0xFFFF, sum = 0
5694 06:48:15.849656 7, 0xFFFF, sum = 0
5695 06:48:15.852945 8, 0xFFFF, sum = 0
5696 06:48:15.853028 9, 0xFFFF, sum = 0
5697 06:48:15.856422 10, 0x0, sum = 1
5698 06:48:15.856520 11, 0x0, sum = 2
5699 06:48:15.859735 12, 0x0, sum = 3
5700 06:48:15.859818 13, 0x0, sum = 4
5701 06:48:15.859883 best_step = 11
5702 06:48:15.859943
5703 06:48:15.862689 ==
5704 06:48:15.865965 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 06:48:15.869639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 06:48:15.869722 ==
5707 06:48:15.869786 RX Vref Scan: 1
5708 06:48:15.869847
5709 06:48:15.872524 RX Vref 0 -> 0, step: 1
5710 06:48:15.872606
5711 06:48:15.875776 RX Delay -53 -> 252, step: 4
5712 06:48:15.875858
5713 06:48:15.879549 Set Vref, RX VrefLevel [Byte0]: 53
5714 06:48:15.882749 [Byte1]: 49
5715 06:48:15.882868
5716 06:48:15.885741 Final RX Vref Byte 0 = 53 to rank0
5717 06:48:15.889162 Final RX Vref Byte 1 = 49 to rank0
5718 06:48:15.892168 Final RX Vref Byte 0 = 53 to rank1
5719 06:48:15.895993 Final RX Vref Byte 1 = 49 to rank1==
5720 06:48:15.899048 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 06:48:15.905893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 06:48:15.905979 ==
5723 06:48:15.906044 DQS Delay:
5724 06:48:15.906104 DQS0 = 0, DQS1 = 0
5725 06:48:15.909307 DQM Delay:
5726 06:48:15.909389 DQM0 = 98, DQM1 = 94
5727 06:48:15.912265 DQ Delay:
5728 06:48:15.915501 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =96
5729 06:48:15.919144 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5730 06:48:15.921938 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5731 06:48:15.925489 DQ12 =100, DQ13 =104, DQ14 =100, DQ15 =102
5732 06:48:15.925571
5733 06:48:15.925635
5734 06:48:15.932066 [DQSOSCAuto] RK0, (LSB)MR18= 0x818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5735 06:48:15.935829 CH1 RK0: MR19=505, MR18=818
5736 06:48:15.941572 CH1_RK0: MR19=0x505, MR18=0x818, DQSOSC=414, MR23=63, INC=63, DEC=42
5737 06:48:15.941654
5738 06:48:15.945246 ----->DramcWriteLeveling(PI) begin...
5739 06:48:15.945330 ==
5740 06:48:15.948143 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 06:48:15.951492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 06:48:15.951575 ==
5743 06:48:15.954731 Write leveling (Byte 0): 27 => 27
5744 06:48:15.958247 Write leveling (Byte 1): 27 => 27
5745 06:48:15.961488 DramcWriteLeveling(PI) end<-----
5746 06:48:15.961570
5747 06:48:15.961634 ==
5748 06:48:15.964701 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 06:48:15.971336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 06:48:15.971459 ==
5751 06:48:15.971525 [Gating] SW mode calibration
5752 06:48:15.981744 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5753 06:48:15.984404 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5754 06:48:15.987855 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 06:48:15.994126 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 06:48:15.997571 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 06:48:16.000957 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 06:48:16.008087 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 06:48:16.011150 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5760 06:48:16.014235 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
5761 06:48:16.020742 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (1 0) (0 0)
5762 06:48:16.023938 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 06:48:16.030659 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 06:48:16.034033 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 06:48:16.037305 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 06:48:16.043924 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 06:48:16.047149 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 06:48:16.050350 0 15 24 | B1->B0 | 2828 3636 | 0 0 | (1 1) (0 0)
5769 06:48:16.056744 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5770 06:48:16.060190 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 06:48:16.063577 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 06:48:16.070505 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 06:48:16.073393 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 06:48:16.077086 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 06:48:16.083306 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 06:48:16.086578 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5777 06:48:16.089925 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5778 06:48:16.096803 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 06:48:16.099811 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 06:48:16.102987 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 06:48:16.109427 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 06:48:16.112594 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 06:48:16.116154 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 06:48:16.122701 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 06:48:16.126189 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 06:48:16.129588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 06:48:16.136163 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 06:48:16.139236 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 06:48:16.142751 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 06:48:16.149095 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 06:48:16.152417 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 06:48:16.155773 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5793 06:48:16.162391 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5794 06:48:16.162473 Total UI for P1: 0, mck2ui 16
5795 06:48:16.168884 best dqsien dly found for B0: ( 1, 2, 24)
5796 06:48:16.172249 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 06:48:16.175502 Total UI for P1: 0, mck2ui 16
5798 06:48:16.178417 best dqsien dly found for B1: ( 1, 2, 28)
5799 06:48:16.182113 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5800 06:48:16.185100 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5801 06:48:16.185183
5802 06:48:16.188377 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5803 06:48:16.191567 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5804 06:48:16.195123 [Gating] SW calibration Done
5805 06:48:16.195231 ==
5806 06:48:16.198421 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 06:48:16.201889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 06:48:16.204774 ==
5809 06:48:16.204856 RX Vref Scan: 0
5810 06:48:16.204922
5811 06:48:16.208518 RX Vref 0 -> 0, step: 1
5812 06:48:16.208600
5813 06:48:16.211614 RX Delay -80 -> 252, step: 8
5814 06:48:16.214800 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5815 06:48:16.217951 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5816 06:48:16.221663 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5817 06:48:16.224644 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5818 06:48:16.231398 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5819 06:48:16.234488 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5820 06:48:16.237883 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5821 06:48:16.241251 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5822 06:48:16.244564 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5823 06:48:16.247668 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5824 06:48:16.254574 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5825 06:48:16.257883 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5826 06:48:16.261006 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5827 06:48:16.264258 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5828 06:48:16.267323 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5829 06:48:16.273888 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5830 06:48:16.273970 ==
5831 06:48:16.277185 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 06:48:16.280488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 06:48:16.280596 ==
5834 06:48:16.280691 DQS Delay:
5835 06:48:16.283980 DQS0 = 0, DQS1 = 0
5836 06:48:16.284063 DQM Delay:
5837 06:48:16.287315 DQM0 = 97, DQM1 = 94
5838 06:48:16.287448 DQ Delay:
5839 06:48:16.290274 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5840 06:48:16.293768 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5841 06:48:16.297022 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5842 06:48:16.300190 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5843 06:48:16.300272
5844 06:48:16.300337
5845 06:48:16.300398 ==
5846 06:48:16.303503 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 06:48:16.310013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 06:48:16.310095 ==
5849 06:48:16.310160
5850 06:48:16.310219
5851 06:48:16.310276 TX Vref Scan disable
5852 06:48:16.313783 == TX Byte 0 ==
5853 06:48:16.316873 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5854 06:48:16.323452 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5855 06:48:16.323559 == TX Byte 1 ==
5856 06:48:16.326991 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 06:48:16.333313 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 06:48:16.333396 ==
5859 06:48:16.336872 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 06:48:16.339748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 06:48:16.339831 ==
5862 06:48:16.339896
5863 06:48:16.339955
5864 06:48:16.342955 TX Vref Scan disable
5865 06:48:16.346558 == TX Byte 0 ==
5866 06:48:16.349474 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 06:48:16.352721 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 06:48:16.356308 == TX Byte 1 ==
5869 06:48:16.359970 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 06:48:16.363025 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 06:48:16.363175
5872 06:48:16.363279 [DATLAT]
5873 06:48:16.366385 Freq=933, CH1 RK1
5874 06:48:16.366467
5875 06:48:16.369741 DATLAT Default: 0xb
5876 06:48:16.369823 0, 0xFFFF, sum = 0
5877 06:48:16.372660 1, 0xFFFF, sum = 0
5878 06:48:16.372744 2, 0xFFFF, sum = 0
5879 06:48:16.375924 3, 0xFFFF, sum = 0
5880 06:48:16.376008 4, 0xFFFF, sum = 0
5881 06:48:16.379352 5, 0xFFFF, sum = 0
5882 06:48:16.379473 6, 0xFFFF, sum = 0
5883 06:48:16.382949 7, 0xFFFF, sum = 0
5884 06:48:16.383033 8, 0xFFFF, sum = 0
5885 06:48:16.385755 9, 0xFFFF, sum = 0
5886 06:48:16.385838 10, 0x0, sum = 1
5887 06:48:16.389464 11, 0x0, sum = 2
5888 06:48:16.389547 12, 0x0, sum = 3
5889 06:48:16.392563 13, 0x0, sum = 4
5890 06:48:16.392646 best_step = 11
5891 06:48:16.392711
5892 06:48:16.392771 ==
5893 06:48:16.395564 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 06:48:16.398828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 06:48:16.402240 ==
5896 06:48:16.402322 RX Vref Scan: 0
5897 06:48:16.402386
5898 06:48:16.405715 RX Vref 0 -> 0, step: 1
5899 06:48:16.405797
5900 06:48:16.408830 RX Delay -61 -> 252, step: 4
5901 06:48:16.412157 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5902 06:48:16.415694 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5903 06:48:16.422475 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5904 06:48:16.425613 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5905 06:48:16.428478 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5906 06:48:16.432362 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5907 06:48:16.435463 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5908 06:48:16.438608 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5909 06:48:16.445203 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5910 06:48:16.448469 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5911 06:48:16.451788 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5912 06:48:16.455168 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5913 06:48:16.458396 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5914 06:48:16.464768 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5915 06:48:16.468327 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5916 06:48:16.471960 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5917 06:48:16.472042 ==
5918 06:48:16.474512 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 06:48:16.477876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 06:48:16.481522 ==
5921 06:48:16.481604 DQS Delay:
5922 06:48:16.481669 DQS0 = 0, DQS1 = 0
5923 06:48:16.484591 DQM Delay:
5924 06:48:16.484673 DQM0 = 97, DQM1 = 92
5925 06:48:16.487747 DQ Delay:
5926 06:48:16.491349 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =94
5927 06:48:16.494492 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =92
5928 06:48:16.497437 DQ8 =78, DQ9 =82, DQ10 =94, DQ11 =86
5929 06:48:16.501166 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5930 06:48:16.501249
5931 06:48:16.501314
5932 06:48:16.507571 [DQSOSCAuto] RK1, (LSB)MR18= 0x1026, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5933 06:48:16.510893 CH1 RK1: MR19=505, MR18=1026
5934 06:48:16.517421 CH1_RK1: MR19=0x505, MR18=0x1026, DQSOSC=409, MR23=63, INC=64, DEC=43
5935 06:48:16.520847 [RxdqsGatingPostProcess] freq 933
5936 06:48:16.524149 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5937 06:48:16.527227 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 06:48:16.530722 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 06:48:16.534023 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 06:48:16.537130 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 06:48:16.540689 best DQS0 dly(2T, 0.5T) = (0, 10)
5942 06:48:16.544131 best DQS1 dly(2T, 0.5T) = (0, 10)
5943 06:48:16.547215 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5944 06:48:16.550304 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5945 06:48:16.553728 Pre-setting of DQS Precalculation
5946 06:48:16.557404 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5947 06:48:16.567080 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5948 06:48:16.574586 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5949 06:48:16.574670
5950 06:48:16.574734
5951 06:48:16.576987 [Calibration Summary] 1866 Mbps
5952 06:48:16.577099 CH 0, Rank 0
5953 06:48:16.580228 SW Impedance : PASS
5954 06:48:16.583609 DUTY Scan : NO K
5955 06:48:16.583718 ZQ Calibration : PASS
5956 06:48:16.587078 Jitter Meter : NO K
5957 06:48:16.587187 CBT Training : PASS
5958 06:48:16.590308 Write leveling : PASS
5959 06:48:16.593541 RX DQS gating : PASS
5960 06:48:16.593623 RX DQ/DQS(RDDQC) : PASS
5961 06:48:16.597055 TX DQ/DQS : PASS
5962 06:48:16.600120 RX DATLAT : PASS
5963 06:48:16.600201 RX DQ/DQS(Engine): PASS
5964 06:48:16.603179 TX OE : NO K
5965 06:48:16.603287 All Pass.
5966 06:48:16.603415
5967 06:48:16.606517 CH 0, Rank 1
5968 06:48:16.606599 SW Impedance : PASS
5969 06:48:16.609803 DUTY Scan : NO K
5970 06:48:16.613017 ZQ Calibration : PASS
5971 06:48:16.613100 Jitter Meter : NO K
5972 06:48:16.616399 CBT Training : PASS
5973 06:48:16.619770 Write leveling : PASS
5974 06:48:16.619852 RX DQS gating : PASS
5975 06:48:16.623285 RX DQ/DQS(RDDQC) : PASS
5976 06:48:16.626244 TX DQ/DQS : PASS
5977 06:48:16.626342 RX DATLAT : PASS
5978 06:48:16.629766 RX DQ/DQS(Engine): PASS
5979 06:48:16.633262 TX OE : NO K
5980 06:48:16.633345 All Pass.
5981 06:48:16.633410
5982 06:48:16.633470 CH 1, Rank 0
5983 06:48:16.636213 SW Impedance : PASS
5984 06:48:16.639731 DUTY Scan : NO K
5985 06:48:16.639813 ZQ Calibration : PASS
5986 06:48:16.642878 Jitter Meter : NO K
5987 06:48:16.646196 CBT Training : PASS
5988 06:48:16.646278 Write leveling : PASS
5989 06:48:16.649444 RX DQS gating : PASS
5990 06:48:16.652715 RX DQ/DQS(RDDQC) : PASS
5991 06:48:16.652797 TX DQ/DQS : PASS
5992 06:48:16.655714 RX DATLAT : PASS
5993 06:48:16.659073 RX DQ/DQS(Engine): PASS
5994 06:48:16.659155 TX OE : NO K
5995 06:48:16.659220 All Pass.
5996 06:48:16.662901
5997 06:48:16.662982 CH 1, Rank 1
5998 06:48:16.665869 SW Impedance : PASS
5999 06:48:16.665967 DUTY Scan : NO K
6000 06:48:16.669289 ZQ Calibration : PASS
6001 06:48:16.669371 Jitter Meter : NO K
6002 06:48:16.672455 CBT Training : PASS
6003 06:48:16.675620 Write leveling : PASS
6004 06:48:16.675729 RX DQS gating : PASS
6005 06:48:16.678828 RX DQ/DQS(RDDQC) : PASS
6006 06:48:16.682135 TX DQ/DQS : PASS
6007 06:48:16.682217 RX DATLAT : PASS
6008 06:48:16.685580 RX DQ/DQS(Engine): PASS
6009 06:48:16.689128 TX OE : NO K
6010 06:48:16.689210 All Pass.
6011 06:48:16.689291
6012 06:48:16.691903 DramC Write-DBI off
6013 06:48:16.691984 PER_BANK_REFRESH: Hybrid Mode
6014 06:48:16.695608 TX_TRACKING: ON
6015 06:48:16.705886 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6016 06:48:16.708682 [FAST_K] Save calibration result to emmc
6017 06:48:16.712421 dramc_set_vcore_voltage set vcore to 650000
6018 06:48:16.712503 Read voltage for 400, 6
6019 06:48:16.715407 Vio18 = 0
6020 06:48:16.715503 Vcore = 650000
6021 06:48:16.715568 Vdram = 0
6022 06:48:16.718631 Vddq = 0
6023 06:48:16.718712 Vmddr = 0
6024 06:48:16.725215 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6025 06:48:16.728450 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6026 06:48:16.731908 MEM_TYPE=3, freq_sel=20
6027 06:48:16.734737 sv_algorithm_assistance_LP4_800
6028 06:48:16.738126 ============ PULL DRAM RESETB DOWN ============
6029 06:48:16.741580 ========== PULL DRAM RESETB DOWN end =========
6030 06:48:16.748035 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6031 06:48:16.751521 ===================================
6032 06:48:16.751603 LPDDR4 DRAM CONFIGURATION
6033 06:48:16.754526 ===================================
6034 06:48:16.757798 EX_ROW_EN[0] = 0x0
6035 06:48:16.761984 EX_ROW_EN[1] = 0x0
6036 06:48:16.762066 LP4Y_EN = 0x0
6037 06:48:16.764664 WORK_FSP = 0x0
6038 06:48:16.764746 WL = 0x2
6039 06:48:16.768118 RL = 0x2
6040 06:48:16.768201 BL = 0x2
6041 06:48:16.771232 RPST = 0x0
6042 06:48:16.771313 RD_PRE = 0x0
6043 06:48:16.774778 WR_PRE = 0x1
6044 06:48:16.774859 WR_PST = 0x0
6045 06:48:16.777588 DBI_WR = 0x0
6046 06:48:16.777670 DBI_RD = 0x0
6047 06:48:16.780958 OTF = 0x1
6048 06:48:16.784656 ===================================
6049 06:48:16.787604 ===================================
6050 06:48:16.787686 ANA top config
6051 06:48:16.790912 ===================================
6052 06:48:16.794207 DLL_ASYNC_EN = 0
6053 06:48:16.797567 ALL_SLAVE_EN = 1
6054 06:48:16.800931 NEW_RANK_MODE = 1
6055 06:48:16.801014 DLL_IDLE_MODE = 1
6056 06:48:16.804082 LP45_APHY_COMB_EN = 1
6057 06:48:16.807183 TX_ODT_DIS = 1
6058 06:48:16.810725 NEW_8X_MODE = 1
6059 06:48:16.814338 ===================================
6060 06:48:16.816906 ===================================
6061 06:48:16.820232 data_rate = 800
6062 06:48:16.823517 CKR = 1
6063 06:48:16.823602 DQ_P2S_RATIO = 4
6064 06:48:16.826879 ===================================
6065 06:48:16.830525 CA_P2S_RATIO = 4
6066 06:48:16.833768 DQ_CA_OPEN = 0
6067 06:48:16.837099 DQ_SEMI_OPEN = 1
6068 06:48:16.839842 CA_SEMI_OPEN = 1
6069 06:48:16.843359 CA_FULL_RATE = 0
6070 06:48:16.843477 DQ_CKDIV4_EN = 0
6071 06:48:16.846793 CA_CKDIV4_EN = 1
6072 06:48:16.850226 CA_PREDIV_EN = 0
6073 06:48:16.853592 PH8_DLY = 0
6074 06:48:16.856796 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6075 06:48:16.860678 DQ_AAMCK_DIV = 0
6076 06:48:16.860759 CA_AAMCK_DIV = 0
6077 06:48:16.863515 CA_ADMCK_DIV = 4
6078 06:48:16.866608 DQ_TRACK_CA_EN = 0
6079 06:48:16.870021 CA_PICK = 800
6080 06:48:16.873385 CA_MCKIO = 400
6081 06:48:16.876297 MCKIO_SEMI = 400
6082 06:48:16.879921 PLL_FREQ = 3016
6083 06:48:16.883515 DQ_UI_PI_RATIO = 32
6084 06:48:16.883597 CA_UI_PI_RATIO = 32
6085 06:48:16.886358 ===================================
6086 06:48:16.889987 ===================================
6087 06:48:16.893215 memory_type:LPDDR4
6088 06:48:16.896267 GP_NUM : 10
6089 06:48:16.896349 SRAM_EN : 1
6090 06:48:16.899527 MD32_EN : 0
6091 06:48:16.902950 ===================================
6092 06:48:16.906645 [ANA_INIT] >>>>>>>>>>>>>>
6093 06:48:16.909391 <<<<<< [CONFIGURE PHASE]: ANA_TX
6094 06:48:16.912457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6095 06:48:16.915740 ===================================
6096 06:48:16.915822 data_rate = 800,PCW = 0X7400
6097 06:48:16.919425 ===================================
6098 06:48:16.922259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6099 06:48:16.929318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 06:48:16.942064 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 06:48:16.945587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6102 06:48:16.948972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6103 06:48:16.951869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6104 06:48:16.955182 [ANA_INIT] flow start
6105 06:48:16.955264 [ANA_INIT] PLL >>>>>>>>
6106 06:48:16.958433 [ANA_INIT] PLL <<<<<<<<
6107 06:48:16.962174 [ANA_INIT] MIDPI >>>>>>>>
6108 06:48:16.965079 [ANA_INIT] MIDPI <<<<<<<<
6109 06:48:16.965189 [ANA_INIT] DLL >>>>>>>>
6110 06:48:16.968548 [ANA_INIT] flow end
6111 06:48:16.971820 ============ LP4 DIFF to SE enter ============
6112 06:48:16.975331 ============ LP4 DIFF to SE exit ============
6113 06:48:16.978455 [ANA_INIT] <<<<<<<<<<<<<
6114 06:48:16.981467 [Flow] Enable top DCM control >>>>>
6115 06:48:16.984848 [Flow] Enable top DCM control <<<<<
6116 06:48:16.988160 Enable DLL master slave shuffle
6117 06:48:16.994706 ==============================================================
6118 06:48:16.994788 Gating Mode config
6119 06:48:17.001251 ==============================================================
6120 06:48:17.001334 Config description:
6121 06:48:17.011248 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6122 06:48:17.018306 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6123 06:48:17.024982 SELPH_MODE 0: By rank 1: By Phase
6124 06:48:17.028196 ==============================================================
6125 06:48:17.031029 GAT_TRACK_EN = 0
6126 06:48:17.034736 RX_GATING_MODE = 2
6127 06:48:17.037582 RX_GATING_TRACK_MODE = 2
6128 06:48:17.040921 SELPH_MODE = 1
6129 06:48:17.044137 PICG_EARLY_EN = 1
6130 06:48:17.047274 VALID_LAT_VALUE = 1
6131 06:48:17.054108 ==============================================================
6132 06:48:17.057385 Enter into Gating configuration >>>>
6133 06:48:17.060604 Exit from Gating configuration <<<<
6134 06:48:17.064023 Enter into DVFS_PRE_config >>>>>
6135 06:48:17.074126 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6136 06:48:17.077645 Exit from DVFS_PRE_config <<<<<
6137 06:48:17.080559 Enter into PICG configuration >>>>
6138 06:48:17.083698 Exit from PICG configuration <<<<
6139 06:48:17.086861 [RX_INPUT] configuration >>>>>
6140 06:48:17.090028 [RX_INPUT] configuration <<<<<
6141 06:48:17.093403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6142 06:48:17.100069 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6143 06:48:17.107353 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 06:48:17.113346 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 06:48:17.116532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 06:48:17.123222 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 06:48:17.126501 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6148 06:48:17.133126 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6149 06:48:17.136534 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6150 06:48:17.139714 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6151 06:48:17.143038 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6152 06:48:17.149630 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 06:48:17.153075 ===================================
6154 06:48:17.156267 LPDDR4 DRAM CONFIGURATION
6155 06:48:17.159383 ===================================
6156 06:48:17.159481 EX_ROW_EN[0] = 0x0
6157 06:48:17.163065 EX_ROW_EN[1] = 0x0
6158 06:48:17.163149 LP4Y_EN = 0x0
6159 06:48:17.166105 WORK_FSP = 0x0
6160 06:48:17.166189 WL = 0x2
6161 06:48:17.169453 RL = 0x2
6162 06:48:17.169534 BL = 0x2
6163 06:48:17.172417 RPST = 0x0
6164 06:48:17.172497 RD_PRE = 0x0
6165 06:48:17.175901 WR_PRE = 0x1
6166 06:48:17.175982 WR_PST = 0x0
6167 06:48:17.178837 DBI_WR = 0x0
6168 06:48:17.182493 DBI_RD = 0x0
6169 06:48:17.182573 OTF = 0x1
6170 06:48:17.185734 ===================================
6171 06:48:17.189450 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6172 06:48:17.192494 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6173 06:48:17.198866 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 06:48:17.202330 ===================================
6175 06:48:17.205749 LPDDR4 DRAM CONFIGURATION
6176 06:48:17.208897 ===================================
6177 06:48:17.208979 EX_ROW_EN[0] = 0x10
6178 06:48:17.211970 EX_ROW_EN[1] = 0x0
6179 06:48:17.212052 LP4Y_EN = 0x0
6180 06:48:17.215254 WORK_FSP = 0x0
6181 06:48:17.215369 WL = 0x2
6182 06:48:17.218543 RL = 0x2
6183 06:48:17.218625 BL = 0x2
6184 06:48:17.222002 RPST = 0x0
6185 06:48:17.224992 RD_PRE = 0x0
6186 06:48:17.225073 WR_PRE = 0x1
6187 06:48:17.228882 WR_PST = 0x0
6188 06:48:17.228964 DBI_WR = 0x0
6189 06:48:17.231941 DBI_RD = 0x0
6190 06:48:17.232023 OTF = 0x1
6191 06:48:17.235486 ===================================
6192 06:48:17.242053 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6193 06:48:17.245407 nWR fixed to 30
6194 06:48:17.248758 [ModeRegInit_LP4] CH0 RK0
6195 06:48:17.248840 [ModeRegInit_LP4] CH0 RK1
6196 06:48:17.252078 [ModeRegInit_LP4] CH1 RK0
6197 06:48:17.255495 [ModeRegInit_LP4] CH1 RK1
6198 06:48:17.255580 match AC timing 19
6199 06:48:17.261822 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6200 06:48:17.265345 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6201 06:48:17.268418 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6202 06:48:17.274798 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6203 06:48:17.278097 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6204 06:48:17.278179 ==
6205 06:48:17.281418 Dram Type= 6, Freq= 0, CH_0, rank 0
6206 06:48:17.284600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6207 06:48:17.284682 ==
6208 06:48:17.291751 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6209 06:48:17.298267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6210 06:48:17.301116 [CA 0] Center 36 (8~64) winsize 57
6211 06:48:17.304613 [CA 1] Center 36 (8~64) winsize 57
6212 06:48:17.307921 [CA 2] Center 36 (8~64) winsize 57
6213 06:48:17.311191 [CA 3] Center 36 (8~64) winsize 57
6214 06:48:17.314087 [CA 4] Center 36 (8~64) winsize 57
6215 06:48:17.317654 [CA 5] Center 36 (8~64) winsize 57
6216 06:48:17.317736
6217 06:48:17.320817 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6218 06:48:17.320898
6219 06:48:17.324472 [CATrainingPosCal] consider 1 rank data
6220 06:48:17.327438 u2DelayCellTimex100 = 270/100 ps
6221 06:48:17.330578 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 06:48:17.333847 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 06:48:17.337461 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 06:48:17.340598 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 06:48:17.343766 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 06:48:17.346963 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 06:48:17.347044
6228 06:48:17.354014 CA PerBit enable=1, Macro0, CA PI delay=36
6229 06:48:17.354097
6230 06:48:17.356823 [CBTSetCACLKResult] CA Dly = 36
6231 06:48:17.356907 CS Dly: 1 (0~32)
6232 06:48:17.356993 ==
6233 06:48:17.360060 Dram Type= 6, Freq= 0, CH_0, rank 1
6234 06:48:17.363460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 06:48:17.363544 ==
6236 06:48:17.369887 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 06:48:17.376795 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6238 06:48:17.380336 [CA 0] Center 36 (8~64) winsize 57
6239 06:48:17.383143 [CA 1] Center 36 (8~64) winsize 57
6240 06:48:17.386506 [CA 2] Center 36 (8~64) winsize 57
6241 06:48:17.389770 [CA 3] Center 36 (8~64) winsize 57
6242 06:48:17.393218 [CA 4] Center 36 (8~64) winsize 57
6243 06:48:17.396275 [CA 5] Center 36 (8~64) winsize 57
6244 06:48:17.396359
6245 06:48:17.399694 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6246 06:48:17.399778
6247 06:48:17.403086 [CATrainingPosCal] consider 2 rank data
6248 06:48:17.406417 u2DelayCellTimex100 = 270/100 ps
6249 06:48:17.409352 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 06:48:17.412774 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 06:48:17.415931 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 06:48:17.419237 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 06:48:17.422351 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 06:48:17.425816 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 06:48:17.425900
6256 06:48:17.432431 CA PerBit enable=1, Macro0, CA PI delay=36
6257 06:48:17.432519
6258 06:48:17.435715 [CBTSetCACLKResult] CA Dly = 36
6259 06:48:17.435799 CS Dly: 1 (0~32)
6260 06:48:17.435884
6261 06:48:17.439184 ----->DramcWriteLeveling(PI) begin...
6262 06:48:17.439270 ==
6263 06:48:17.441982 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 06:48:17.445943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 06:48:17.448655 ==
6266 06:48:17.448738 Write leveling (Byte 0): 40 => 8
6267 06:48:17.452057 Write leveling (Byte 1): 40 => 8
6268 06:48:17.455631 DramcWriteLeveling(PI) end<-----
6269 06:48:17.455715
6270 06:48:17.455801 ==
6271 06:48:17.458683 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 06:48:17.465553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 06:48:17.465637 ==
6274 06:48:17.468706 [Gating] SW mode calibration
6275 06:48:17.474780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6276 06:48:17.478688 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6277 06:48:17.485140 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 06:48:17.488480 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 06:48:17.491446 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 06:48:17.498053 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 06:48:17.501458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 06:48:17.504754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 06:48:17.511389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 06:48:17.515069 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 06:48:17.517684 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 06:48:17.521071 Total UI for P1: 0, mck2ui 16
6287 06:48:17.524805 best dqsien dly found for B0: ( 0, 14, 24)
6288 06:48:17.528305 Total UI for P1: 0, mck2ui 16
6289 06:48:17.531341 best dqsien dly found for B1: ( 0, 14, 24)
6290 06:48:17.534239 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6291 06:48:17.537848 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6292 06:48:17.537932
6293 06:48:17.543916 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 06:48:17.547258 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 06:48:17.550995 [Gating] SW calibration Done
6296 06:48:17.551079 ==
6297 06:48:17.553898 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 06:48:17.557182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 06:48:17.557266 ==
6300 06:48:17.557351 RX Vref Scan: 0
6301 06:48:17.561374
6302 06:48:17.561458 RX Vref 0 -> 0, step: 1
6303 06:48:17.561544
6304 06:48:17.563883 RX Delay -410 -> 252, step: 16
6305 06:48:17.567118 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6306 06:48:17.573614 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6307 06:48:17.577018 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6308 06:48:17.580648 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6309 06:48:17.583477 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6310 06:48:17.590400 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6311 06:48:17.593814 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6312 06:48:17.597507 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6313 06:48:17.600487 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6314 06:48:17.606975 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6315 06:48:17.609758 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6316 06:48:17.613852 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6317 06:48:17.619715 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6318 06:48:17.623045 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6319 06:48:17.626306 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6320 06:48:17.629715 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6321 06:48:17.632818 ==
6322 06:48:17.632899 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 06:48:17.639502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 06:48:17.639588 ==
6325 06:48:17.639652 DQS Delay:
6326 06:48:17.642820 DQS0 = 35, DQS1 = 59
6327 06:48:17.642900 DQM Delay:
6328 06:48:17.646263 DQM0 = 5, DQM1 = 17
6329 06:48:17.646343 DQ Delay:
6330 06:48:17.649506 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6331 06:48:17.652657 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6332 06:48:17.656030 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6333 06:48:17.659574 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6334 06:48:17.659655
6335 06:48:17.659718
6336 06:48:17.659777 ==
6337 06:48:17.662912 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 06:48:17.665555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 06:48:17.665630 ==
6340 06:48:17.665691
6341 06:48:17.665750
6342 06:48:17.669199 TX Vref Scan disable
6343 06:48:17.669279 == TX Byte 0 ==
6344 06:48:17.675554 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 06:48:17.679180 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 06:48:17.679260 == TX Byte 1 ==
6347 06:48:17.685663 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 06:48:17.689237 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 06:48:17.689319 ==
6350 06:48:17.692119 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 06:48:17.695559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 06:48:17.695639 ==
6353 06:48:17.695703
6354 06:48:17.695762
6355 06:48:17.698808 TX Vref Scan disable
6356 06:48:17.701985 == TX Byte 0 ==
6357 06:48:17.705662 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 06:48:17.709241 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 06:48:17.709322 == TX Byte 1 ==
6360 06:48:17.715165 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 06:48:17.718829 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 06:48:17.718909
6363 06:48:17.718972 [DATLAT]
6364 06:48:17.721674 Freq=400, CH0 RK0
6365 06:48:17.721755
6366 06:48:17.721818 DATLAT Default: 0xf
6367 06:48:17.724937 0, 0xFFFF, sum = 0
6368 06:48:17.725019 1, 0xFFFF, sum = 0
6369 06:48:17.728751 2, 0xFFFF, sum = 0
6370 06:48:17.731958 3, 0xFFFF, sum = 0
6371 06:48:17.732041 4, 0xFFFF, sum = 0
6372 06:48:17.734999 5, 0xFFFF, sum = 0
6373 06:48:17.735081 6, 0xFFFF, sum = 0
6374 06:48:17.738645 7, 0xFFFF, sum = 0
6375 06:48:17.738728 8, 0xFFFF, sum = 0
6376 06:48:17.741924 9, 0xFFFF, sum = 0
6377 06:48:17.742007 10, 0xFFFF, sum = 0
6378 06:48:17.744769 11, 0xFFFF, sum = 0
6379 06:48:17.744852 12, 0xFFFF, sum = 0
6380 06:48:17.748116 13, 0x0, sum = 1
6381 06:48:17.748199 14, 0x0, sum = 2
6382 06:48:17.751354 15, 0x0, sum = 3
6383 06:48:17.751476 16, 0x0, sum = 4
6384 06:48:17.755046 best_step = 14
6385 06:48:17.755127
6386 06:48:17.755190 ==
6387 06:48:17.758294 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 06:48:17.761299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 06:48:17.761381 ==
6390 06:48:17.765158 RX Vref Scan: 1
6391 06:48:17.765242
6392 06:48:17.765327 RX Vref 0 -> 0, step: 1
6393 06:48:17.765408
6394 06:48:17.767757 RX Delay -359 -> 252, step: 8
6395 06:48:17.767840
6396 06:48:17.771275 Set Vref, RX VrefLevel [Byte0]: 52
6397 06:48:17.774186 [Byte1]: 49
6398 06:48:17.778672
6399 06:48:17.778756 Final RX Vref Byte 0 = 52 to rank0
6400 06:48:17.782622 Final RX Vref Byte 1 = 49 to rank0
6401 06:48:17.785812 Final RX Vref Byte 0 = 52 to rank1
6402 06:48:17.788750 Final RX Vref Byte 1 = 49 to rank1==
6403 06:48:17.791951 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 06:48:17.798603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 06:48:17.798692 ==
6406 06:48:17.798777 DQS Delay:
6407 06:48:17.801988 DQS0 = 44, DQS1 = 56
6408 06:48:17.802072 DQM Delay:
6409 06:48:17.802172 DQM0 = 10, DQM1 = 13
6410 06:48:17.805508 DQ Delay:
6411 06:48:17.808363 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6412 06:48:17.811763 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6413 06:48:17.811847 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6414 06:48:17.818351 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6415 06:48:17.818435
6416 06:48:17.818519
6417 06:48:17.824922 [DQSOSCAuto] RK0, (LSB)MR18= 0x9588, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6418 06:48:17.828231 CH0 RK0: MR19=C0C, MR18=9588
6419 06:48:17.834837 CH0_RK0: MR19=0xC0C, MR18=0x9588, DQSOSC=391, MR23=63, INC=386, DEC=257
6420 06:48:17.834921 ==
6421 06:48:17.838278 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 06:48:17.841380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 06:48:17.841464 ==
6424 06:48:17.844782 [Gating] SW mode calibration
6425 06:48:17.851214 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6426 06:48:17.858007 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6427 06:48:17.861124 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 06:48:17.864418 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 06:48:17.871528 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 06:48:17.874442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 06:48:17.877653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 06:48:17.884629 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 06:48:17.887211 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 06:48:17.890967 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 06:48:17.897841 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 06:48:17.900380 Total UI for P1: 0, mck2ui 16
6437 06:48:17.904174 best dqsien dly found for B0: ( 0, 14, 24)
6438 06:48:17.907398 Total UI for P1: 0, mck2ui 16
6439 06:48:17.910807 best dqsien dly found for B1: ( 0, 14, 24)
6440 06:48:17.913706 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6441 06:48:17.917418 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6442 06:48:17.917503
6443 06:48:17.920529 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 06:48:17.924110 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 06:48:17.927389 [Gating] SW calibration Done
6446 06:48:17.927486 ==
6447 06:48:17.930657 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 06:48:17.933620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 06:48:17.933704 ==
6450 06:48:17.937163 RX Vref Scan: 0
6451 06:48:17.937247
6452 06:48:17.940082 RX Vref 0 -> 0, step: 1
6453 06:48:17.940166
6454 06:48:17.940255 RX Delay -410 -> 252, step: 16
6455 06:48:17.947504 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6456 06:48:17.950562 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6457 06:48:17.953544 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6458 06:48:17.960158 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6459 06:48:17.963642 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6460 06:48:17.966704 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6461 06:48:17.969991 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6462 06:48:17.976707 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6463 06:48:17.980005 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6464 06:48:17.983243 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6465 06:48:17.986895 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6466 06:48:17.993260 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6467 06:48:17.996576 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6468 06:48:18.000085 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6469 06:48:18.003624 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6470 06:48:18.009773 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6471 06:48:18.009856 ==
6472 06:48:18.013557 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 06:48:18.016644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 06:48:18.016729 ==
6475 06:48:18.016815 DQS Delay:
6476 06:48:18.019842 DQS0 = 35, DQS1 = 59
6477 06:48:18.019926 DQM Delay:
6478 06:48:18.022946 DQM0 = 6, DQM1 = 17
6479 06:48:18.023029 DQ Delay:
6480 06:48:18.026140 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6481 06:48:18.029594 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6482 06:48:18.033675 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6483 06:48:18.036110 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6484 06:48:18.036194
6485 06:48:18.036279
6486 06:48:18.036360 ==
6487 06:48:18.039720 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 06:48:18.042722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 06:48:18.042806 ==
6490 06:48:18.042892
6491 06:48:18.042971
6492 06:48:18.046239 TX Vref Scan disable
6493 06:48:18.049606 == TX Byte 0 ==
6494 06:48:18.052503 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6495 06:48:18.056509 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6496 06:48:18.059173 == TX Byte 1 ==
6497 06:48:18.063185 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6498 06:48:18.065675 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6499 06:48:18.065760 ==
6500 06:48:18.069230 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 06:48:18.072440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 06:48:18.072525 ==
6503 06:48:18.075670
6504 06:48:18.075753
6505 06:48:18.075838 TX Vref Scan disable
6506 06:48:18.079149 == TX Byte 0 ==
6507 06:48:18.082293 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6508 06:48:18.085857 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6509 06:48:18.089056 == TX Byte 1 ==
6510 06:48:18.092449 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6511 06:48:18.095385 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6512 06:48:18.095484
6513 06:48:18.095569 [DATLAT]
6514 06:48:18.098759 Freq=400, CH0 RK1
6515 06:48:18.098843
6516 06:48:18.101843 DATLAT Default: 0xe
6517 06:48:18.101926 0, 0xFFFF, sum = 0
6518 06:48:18.105444 1, 0xFFFF, sum = 0
6519 06:48:18.105529 2, 0xFFFF, sum = 0
6520 06:48:18.109217 3, 0xFFFF, sum = 0
6521 06:48:18.109306 4, 0xFFFF, sum = 0
6522 06:48:18.111960 5, 0xFFFF, sum = 0
6523 06:48:18.112046 6, 0xFFFF, sum = 0
6524 06:48:18.115444 7, 0xFFFF, sum = 0
6525 06:48:18.115545 8, 0xFFFF, sum = 0
6526 06:48:18.118637 9, 0xFFFF, sum = 0
6527 06:48:18.118739 10, 0xFFFF, sum = 0
6528 06:48:18.121882 11, 0xFFFF, sum = 0
6529 06:48:18.121967 12, 0xFFFF, sum = 0
6530 06:48:18.125206 13, 0x0, sum = 1
6531 06:48:18.125291 14, 0x0, sum = 2
6532 06:48:18.128354 15, 0x0, sum = 3
6533 06:48:18.128440 16, 0x0, sum = 4
6534 06:48:18.131842 best_step = 14
6535 06:48:18.131926
6536 06:48:18.132011 ==
6537 06:48:18.134928 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 06:48:18.138225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 06:48:18.138309 ==
6540 06:48:18.141910 RX Vref Scan: 0
6541 06:48:18.141994
6542 06:48:18.142079 RX Vref 0 -> 0, step: 1
6543 06:48:18.142160
6544 06:48:18.145155 RX Delay -359 -> 252, step: 8
6545 06:48:18.152966 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6546 06:48:18.156486 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6547 06:48:18.160042 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6548 06:48:18.162775 iDelay=209, Bit 3, Center -40 (-279 ~ 200) 480
6549 06:48:18.169494 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6550 06:48:18.172838 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6551 06:48:18.176435 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6552 06:48:18.182723 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6553 06:48:18.185959 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6554 06:48:18.189382 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6555 06:48:18.192940 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6556 06:48:18.199684 iDelay=209, Bit 11, Center -48 (-287 ~ 192) 480
6557 06:48:18.202677 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6558 06:48:18.205667 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6559 06:48:18.209249 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6560 06:48:18.215697 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6561 06:48:18.215781 ==
6562 06:48:18.219088 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 06:48:18.222382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 06:48:18.222470 ==
6565 06:48:18.222557 DQS Delay:
6566 06:48:18.225817 DQS0 = 44, DQS1 = 60
6567 06:48:18.225910 DQM Delay:
6568 06:48:18.229496 DQM0 = 9, DQM1 = 15
6569 06:48:18.229580 DQ Delay:
6570 06:48:18.232115 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6571 06:48:18.235314 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6572 06:48:18.238794 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6573 06:48:18.241895 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6574 06:48:18.241979
6575 06:48:18.242064
6576 06:48:18.251812 [DQSOSCAuto] RK1, (LSB)MR18= 0x8f87, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6577 06:48:18.251898 CH0 RK1: MR19=C0C, MR18=8F87
6578 06:48:18.258480 CH0_RK1: MR19=0xC0C, MR18=0x8F87, DQSOSC=391, MR23=63, INC=386, DEC=257
6579 06:48:18.261486 [RxdqsGatingPostProcess] freq 400
6580 06:48:18.268079 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6581 06:48:18.271516 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 06:48:18.274964 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 06:48:18.278387 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 06:48:18.282185 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 06:48:18.284760 best DQS0 dly(2T, 0.5T) = (0, 10)
6586 06:48:18.284842 best DQS1 dly(2T, 0.5T) = (0, 10)
6587 06:48:18.288361 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6588 06:48:18.294786 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6589 06:48:18.294895 Pre-setting of DQS Precalculation
6590 06:48:18.301445 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6591 06:48:18.301527 ==
6592 06:48:18.304894 Dram Type= 6, Freq= 0, CH_1, rank 0
6593 06:48:18.307691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 06:48:18.307773 ==
6595 06:48:18.314494 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6596 06:48:18.321024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6597 06:48:18.324206 [CA 0] Center 36 (8~64) winsize 57
6598 06:48:18.328080 [CA 1] Center 36 (8~64) winsize 57
6599 06:48:18.331316 [CA 2] Center 36 (8~64) winsize 57
6600 06:48:18.334044 [CA 3] Center 36 (8~64) winsize 57
6601 06:48:18.334126 [CA 4] Center 36 (8~64) winsize 57
6602 06:48:18.338151 [CA 5] Center 36 (8~64) winsize 57
6603 06:48:18.338233
6604 06:48:18.344166 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6605 06:48:18.344248
6606 06:48:18.347489 [CATrainingPosCal] consider 1 rank data
6607 06:48:18.350777 u2DelayCellTimex100 = 270/100 ps
6608 06:48:18.353775 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 06:48:18.357301 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 06:48:18.360544 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 06:48:18.363642 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 06:48:18.367243 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 06:48:18.370211 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 06:48:18.370293
6615 06:48:18.373712 CA PerBit enable=1, Macro0, CA PI delay=36
6616 06:48:18.377378
6617 06:48:18.377459 [CBTSetCACLKResult] CA Dly = 36
6618 06:48:18.380432 CS Dly: 1 (0~32)
6619 06:48:18.380513 ==
6620 06:48:18.383271 Dram Type= 6, Freq= 0, CH_1, rank 1
6621 06:48:18.386666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 06:48:18.386749 ==
6623 06:48:18.393562 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 06:48:18.400070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6625 06:48:18.403219 [CA 0] Center 36 (8~64) winsize 57
6626 06:48:18.406829 [CA 1] Center 36 (8~64) winsize 57
6627 06:48:18.409935 [CA 2] Center 36 (8~64) winsize 57
6628 06:48:18.413443 [CA 3] Center 36 (8~64) winsize 57
6629 06:48:18.413525 [CA 4] Center 36 (8~64) winsize 57
6630 06:48:18.416462 [CA 5] Center 36 (8~64) winsize 57
6631 06:48:18.416545
6632 06:48:18.422905 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6633 06:48:18.422987
6634 06:48:18.426299 [CATrainingPosCal] consider 2 rank data
6635 06:48:18.429181 u2DelayCellTimex100 = 270/100 ps
6636 06:48:18.433215 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 06:48:18.436197 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 06:48:18.439580 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 06:48:18.442669 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 06:48:18.446094 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 06:48:18.449325 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 06:48:18.449407
6643 06:48:18.452743 CA PerBit enable=1, Macro0, CA PI delay=36
6644 06:48:18.452826
6645 06:48:18.455898 [CBTSetCACLKResult] CA Dly = 36
6646 06:48:18.458802 CS Dly: 1 (0~32)
6647 06:48:18.458884
6648 06:48:18.462127 ----->DramcWriteLeveling(PI) begin...
6649 06:48:18.462211 ==
6650 06:48:18.465557 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 06:48:18.468840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 06:48:18.468923 ==
6653 06:48:18.472259 Write leveling (Byte 0): 40 => 8
6654 06:48:18.475719 Write leveling (Byte 1): 40 => 8
6655 06:48:18.478726 DramcWriteLeveling(PI) end<-----
6656 06:48:18.478808
6657 06:48:18.478873 ==
6658 06:48:18.482004 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 06:48:18.485519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 06:48:18.485602 ==
6661 06:48:18.488656 [Gating] SW mode calibration
6662 06:48:18.495550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6663 06:48:18.502071 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6664 06:48:18.505203 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 06:48:18.511899 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 06:48:18.514919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 06:48:18.518433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 06:48:18.525044 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 06:48:18.527984 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 06:48:18.531341 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 06:48:18.538085 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 06:48:18.541297 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 06:48:18.544437 Total UI for P1: 0, mck2ui 16
6674 06:48:18.548127 best dqsien dly found for B0: ( 0, 14, 24)
6675 06:48:18.551097 Total UI for P1: 0, mck2ui 16
6676 06:48:18.554523 best dqsien dly found for B1: ( 0, 14, 24)
6677 06:48:18.557677 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6678 06:48:18.561386 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6679 06:48:18.561468
6680 06:48:18.564013 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 06:48:18.570788 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 06:48:18.570870 [Gating] SW calibration Done
6683 06:48:18.570937 ==
6684 06:48:18.574102 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 06:48:18.580729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 06:48:18.580812 ==
6687 06:48:18.580876 RX Vref Scan: 0
6688 06:48:18.580936
6689 06:48:18.584052 RX Vref 0 -> 0, step: 1
6690 06:48:18.584134
6691 06:48:18.587087 RX Delay -410 -> 252, step: 16
6692 06:48:18.590461 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6693 06:48:18.593764 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6694 06:48:18.600719 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6695 06:48:18.603914 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6696 06:48:18.607182 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6697 06:48:18.610191 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6698 06:48:18.617023 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6699 06:48:18.620043 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6700 06:48:18.623385 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6701 06:48:18.626936 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6702 06:48:18.633491 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6703 06:48:18.637208 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6704 06:48:18.640253 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6705 06:48:18.646588 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6706 06:48:18.649722 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6707 06:48:18.653095 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6708 06:48:18.653178 ==
6709 06:48:18.656372 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 06:48:18.659598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 06:48:18.663251 ==
6712 06:48:18.663333 DQS Delay:
6713 06:48:18.663435 DQS0 = 35, DQS1 = 51
6714 06:48:18.666574 DQM Delay:
6715 06:48:18.666655 DQM0 = 6, DQM1 = 13
6716 06:48:18.669781 DQ Delay:
6717 06:48:18.669877 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6718 06:48:18.673463 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6719 06:48:18.676092 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6720 06:48:18.679254 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6721 06:48:18.679368
6722 06:48:18.679448
6723 06:48:18.682737 ==
6724 06:48:18.685843 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 06:48:18.689351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 06:48:18.689434 ==
6727 06:48:18.689520
6728 06:48:18.689612
6729 06:48:18.692378 TX Vref Scan disable
6730 06:48:18.692492 == TX Byte 0 ==
6731 06:48:18.695786 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 06:48:18.702502 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 06:48:18.702597 == TX Byte 1 ==
6734 06:48:18.705635 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 06:48:18.712726 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 06:48:18.712808 ==
6737 06:48:18.715508 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 06:48:18.718593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 06:48:18.718675 ==
6740 06:48:18.718740
6741 06:48:18.718800
6742 06:48:18.722013 TX Vref Scan disable
6743 06:48:18.722094 == TX Byte 0 ==
6744 06:48:18.725238 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 06:48:18.732045 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 06:48:18.732127 == TX Byte 1 ==
6747 06:48:18.735690 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 06:48:18.741963 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 06:48:18.742045
6750 06:48:18.742109 [DATLAT]
6751 06:48:18.745194 Freq=400, CH1 RK0
6752 06:48:18.745276
6753 06:48:18.745340 DATLAT Default: 0xf
6754 06:48:18.748370 0, 0xFFFF, sum = 0
6755 06:48:18.748453 1, 0xFFFF, sum = 0
6756 06:48:18.751964 2, 0xFFFF, sum = 0
6757 06:48:18.752046 3, 0xFFFF, sum = 0
6758 06:48:18.755229 4, 0xFFFF, sum = 0
6759 06:48:18.755313 5, 0xFFFF, sum = 0
6760 06:48:18.758630 6, 0xFFFF, sum = 0
6761 06:48:18.758713 7, 0xFFFF, sum = 0
6762 06:48:18.761445 8, 0xFFFF, sum = 0
6763 06:48:18.761528 9, 0xFFFF, sum = 0
6764 06:48:18.765150 10, 0xFFFF, sum = 0
6765 06:48:18.765234 11, 0xFFFF, sum = 0
6766 06:48:18.768744 12, 0xFFFF, sum = 0
6767 06:48:18.768827 13, 0x0, sum = 1
6768 06:48:18.771641 14, 0x0, sum = 2
6769 06:48:18.771724 15, 0x0, sum = 3
6770 06:48:18.775209 16, 0x0, sum = 4
6771 06:48:18.775292 best_step = 14
6772 06:48:18.775357
6773 06:48:18.775463 ==
6774 06:48:18.778364 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 06:48:18.784572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 06:48:18.784654 ==
6777 06:48:18.784718 RX Vref Scan: 1
6778 06:48:18.784779
6779 06:48:18.787978 RX Vref 0 -> 0, step: 1
6780 06:48:18.788059
6781 06:48:18.791240 RX Delay -343 -> 252, step: 8
6782 06:48:18.791323
6783 06:48:18.794691 Set Vref, RX VrefLevel [Byte0]: 53
6784 06:48:18.798142 [Byte1]: 49
6785 06:48:18.801200
6786 06:48:18.801281 Final RX Vref Byte 0 = 53 to rank0
6787 06:48:18.804512 Final RX Vref Byte 1 = 49 to rank0
6788 06:48:18.807767 Final RX Vref Byte 0 = 53 to rank1
6789 06:48:18.811266 Final RX Vref Byte 1 = 49 to rank1==
6790 06:48:18.814420 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 06:48:18.821185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 06:48:18.821267 ==
6793 06:48:18.821333 DQS Delay:
6794 06:48:18.824120 DQS0 = 44, DQS1 = 56
6795 06:48:18.824202 DQM Delay:
6796 06:48:18.827672 DQM0 = 11, DQM1 = 15
6797 06:48:18.827753 DQ Delay:
6798 06:48:18.830970 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6799 06:48:18.834363 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6800 06:48:18.834446 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6801 06:48:18.840776 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6802 06:48:18.840858
6803 06:48:18.840923
6804 06:48:18.847149 [DQSOSCAuto] RK0, (LSB)MR18= 0x729a, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6805 06:48:18.850597 CH1 RK0: MR19=C0C, MR18=729A
6806 06:48:18.857137 CH1_RK0: MR19=0xC0C, MR18=0x729A, DQSOSC=390, MR23=63, INC=388, DEC=258
6807 06:48:18.857220 ==
6808 06:48:18.861079 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 06:48:18.863659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 06:48:18.863742 ==
6811 06:48:18.866999 [Gating] SW mode calibration
6812 06:48:18.873588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6813 06:48:18.880500 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6814 06:48:18.883926 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 06:48:18.886880 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 06:48:18.893588 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 06:48:18.897030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 06:48:18.899887 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 06:48:18.906531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 06:48:18.910048 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 06:48:18.913543 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 06:48:18.919871 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 06:48:18.923091 Total UI for P1: 0, mck2ui 16
6824 06:48:18.926246 best dqsien dly found for B0: ( 0, 14, 24)
6825 06:48:18.929412 Total UI for P1: 0, mck2ui 16
6826 06:48:18.932865 best dqsien dly found for B1: ( 0, 14, 24)
6827 06:48:18.936271 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6828 06:48:18.939529 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6829 06:48:18.939611
6830 06:48:18.942694 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 06:48:18.946166 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 06:48:18.949582 [Gating] SW calibration Done
6833 06:48:18.949664 ==
6834 06:48:18.952480 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 06:48:18.956101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 06:48:18.956184 ==
6837 06:48:18.959302 RX Vref Scan: 0
6838 06:48:18.959409
6839 06:48:18.962470 RX Vref 0 -> 0, step: 1
6840 06:48:18.962552
6841 06:48:18.962617 RX Delay -410 -> 252, step: 16
6842 06:48:18.969431 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6843 06:48:18.973091 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6844 06:48:18.975976 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6845 06:48:18.982609 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6846 06:48:18.985883 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6847 06:48:18.989217 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6848 06:48:18.992701 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6849 06:48:18.999298 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6850 06:48:19.002145 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6851 06:48:19.005453 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6852 06:48:19.008966 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6853 06:48:19.015233 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6854 06:48:19.018915 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6855 06:48:19.022650 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6856 06:48:19.025702 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6857 06:48:19.031984 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6858 06:48:19.032065 ==
6859 06:48:19.035331 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 06:48:19.038652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 06:48:19.038734 ==
6862 06:48:19.041927 DQS Delay:
6863 06:48:19.042016 DQS0 = 43, DQS1 = 51
6864 06:48:19.042081 DQM Delay:
6865 06:48:19.044863 DQM0 = 10, DQM1 = 15
6866 06:48:19.044944 DQ Delay:
6867 06:48:19.048432 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6868 06:48:19.051366 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6869 06:48:19.054899 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6870 06:48:19.058370 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6871 06:48:19.058451
6872 06:48:19.058515
6873 06:48:19.058573 ==
6874 06:48:19.061499 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 06:48:19.065291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 06:48:19.068308 ==
6877 06:48:19.068417
6878 06:48:19.068482
6879 06:48:19.068541 TX Vref Scan disable
6880 06:48:19.071489 == TX Byte 0 ==
6881 06:48:19.074419 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6882 06:48:19.077898 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6883 06:48:19.081108 == TX Byte 1 ==
6884 06:48:19.084554 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6885 06:48:19.087656 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6886 06:48:19.087738 ==
6887 06:48:19.091137 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 06:48:19.097590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 06:48:19.097673 ==
6890 06:48:19.097738
6891 06:48:19.097798
6892 06:48:19.097855 TX Vref Scan disable
6893 06:48:19.101024 == TX Byte 0 ==
6894 06:48:19.104619 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6895 06:48:19.107524 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6896 06:48:19.111306 == TX Byte 1 ==
6897 06:48:19.114013 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6898 06:48:19.117329 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6899 06:48:19.117425
6900 06:48:19.120749 [DATLAT]
6901 06:48:19.120830 Freq=400, CH1 RK1
6902 06:48:19.120894
6903 06:48:19.124158 DATLAT Default: 0xe
6904 06:48:19.124238 0, 0xFFFF, sum = 0
6905 06:48:19.127260 1, 0xFFFF, sum = 0
6906 06:48:19.127343 2, 0xFFFF, sum = 0
6907 06:48:19.130597 3, 0xFFFF, sum = 0
6908 06:48:19.130680 4, 0xFFFF, sum = 0
6909 06:48:19.133892 5, 0xFFFF, sum = 0
6910 06:48:19.133975 6, 0xFFFF, sum = 0
6911 06:48:19.137554 7, 0xFFFF, sum = 0
6912 06:48:19.137636 8, 0xFFFF, sum = 0
6913 06:48:19.140391 9, 0xFFFF, sum = 0
6914 06:48:19.143799 10, 0xFFFF, sum = 0
6915 06:48:19.143882 11, 0xFFFF, sum = 0
6916 06:48:19.147266 12, 0xFFFF, sum = 0
6917 06:48:19.147348 13, 0x0, sum = 1
6918 06:48:19.150922 14, 0x0, sum = 2
6919 06:48:19.151004 15, 0x0, sum = 3
6920 06:48:19.153472 16, 0x0, sum = 4
6921 06:48:19.153555 best_step = 14
6922 06:48:19.153618
6923 06:48:19.153678 ==
6924 06:48:19.157021 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 06:48:19.160468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 06:48:19.160550 ==
6927 06:48:19.163565 RX Vref Scan: 0
6928 06:48:19.163646
6929 06:48:19.166871 RX Vref 0 -> 0, step: 1
6930 06:48:19.166952
6931 06:48:19.167016 RX Delay -343 -> 252, step: 8
6932 06:48:19.175720 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6933 06:48:19.179123 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6934 06:48:19.182036 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6935 06:48:19.189064 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6936 06:48:19.192331 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6937 06:48:19.195716 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6938 06:48:19.198464 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6939 06:48:19.205174 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6940 06:48:19.208654 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6941 06:48:19.212020 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6942 06:48:19.215119 iDelay=217, Bit 10, Center -36 (-279 ~ 208) 488
6943 06:48:19.221754 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6944 06:48:19.224928 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6945 06:48:19.228251 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6946 06:48:19.231959 iDelay=217, Bit 14, Center -40 (-279 ~ 200) 480
6947 06:48:19.238437 iDelay=217, Bit 15, Center -32 (-271 ~ 208) 480
6948 06:48:19.238520 ==
6949 06:48:19.241701 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 06:48:19.244710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 06:48:19.244793 ==
6952 06:48:19.244863 DQS Delay:
6953 06:48:19.247881 DQS0 = 48, DQS1 = 56
6954 06:48:19.247964 DQM Delay:
6955 06:48:19.252034 DQM0 = 11, DQM1 = 15
6956 06:48:19.252115 DQ Delay:
6957 06:48:19.254628 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6958 06:48:19.258093 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6959 06:48:19.261474 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6960 06:48:19.264989 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6961 06:48:19.265071
6962 06:48:19.265135
6963 06:48:19.274351 [DQSOSCAuto] RK1, (LSB)MR18= 0x7db5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6964 06:48:19.274434 CH1 RK1: MR19=C0C, MR18=7DB5
6965 06:48:19.280958 CH1_RK1: MR19=0xC0C, MR18=0x7DB5, DQSOSC=387, MR23=63, INC=394, DEC=262
6966 06:48:19.284228 [RxdqsGatingPostProcess] freq 400
6967 06:48:19.290785 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6968 06:48:19.294241 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 06:48:19.297552 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 06:48:19.300793 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 06:48:19.303999 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 06:48:19.307371 best DQS0 dly(2T, 0.5T) = (0, 10)
6973 06:48:19.310454 best DQS1 dly(2T, 0.5T) = (0, 10)
6974 06:48:19.313688 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6975 06:48:19.317480 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6976 06:48:19.317562 Pre-setting of DQS Precalculation
6977 06:48:19.323668 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6978 06:48:19.330434 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6979 06:48:19.337418 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6980 06:48:19.337499
6981 06:48:19.337563
6982 06:48:19.340267 [Calibration Summary] 800 Mbps
6983 06:48:19.343631 CH 0, Rank 0
6984 06:48:19.343712 SW Impedance : PASS
6985 06:48:19.347173 DUTY Scan : NO K
6986 06:48:19.350098 ZQ Calibration : PASS
6987 06:48:19.350179 Jitter Meter : NO K
6988 06:48:19.353555 CBT Training : PASS
6989 06:48:19.357179 Write leveling : PASS
6990 06:48:19.357259 RX DQS gating : PASS
6991 06:48:19.360220 RX DQ/DQS(RDDQC) : PASS
6992 06:48:19.363264 TX DQ/DQS : PASS
6993 06:48:19.363346 RX DATLAT : PASS
6994 06:48:19.366793 RX DQ/DQS(Engine): PASS
6995 06:48:19.366874 TX OE : NO K
6996 06:48:19.369718 All Pass.
6997 06:48:19.369798
6998 06:48:19.369862 CH 0, Rank 1
6999 06:48:19.372997 SW Impedance : PASS
7000 06:48:19.373078 DUTY Scan : NO K
7001 06:48:19.376451 ZQ Calibration : PASS
7002 06:48:19.380206 Jitter Meter : NO K
7003 06:48:19.380279 CBT Training : PASS
7004 06:48:19.383419 Write leveling : NO K
7005 06:48:19.386390 RX DQS gating : PASS
7006 06:48:19.386471 RX DQ/DQS(RDDQC) : PASS
7007 06:48:19.389567 TX DQ/DQS : PASS
7008 06:48:19.392953 RX DATLAT : PASS
7009 06:48:19.393034 RX DQ/DQS(Engine): PASS
7010 06:48:19.396117 TX OE : NO K
7011 06:48:19.396224 All Pass.
7012 06:48:19.396304
7013 06:48:19.399881 CH 1, Rank 0
7014 06:48:19.399961 SW Impedance : PASS
7015 06:48:19.403296 DUTY Scan : NO K
7016 06:48:19.406353 ZQ Calibration : PASS
7017 06:48:19.406434 Jitter Meter : NO K
7018 06:48:19.409870 CBT Training : PASS
7019 06:48:19.412941 Write leveling : PASS
7020 06:48:19.413024 RX DQS gating : PASS
7021 06:48:19.416421 RX DQ/DQS(RDDQC) : PASS
7022 06:48:19.419827 TX DQ/DQS : PASS
7023 06:48:19.419912 RX DATLAT : PASS
7024 06:48:19.422898 RX DQ/DQS(Engine): PASS
7025 06:48:19.426151 TX OE : NO K
7026 06:48:19.426235 All Pass.
7027 06:48:19.426321
7028 06:48:19.426409 CH 1, Rank 1
7029 06:48:19.429573 SW Impedance : PASS
7030 06:48:19.429656 DUTY Scan : NO K
7031 06:48:19.433199 ZQ Calibration : PASS
7032 06:48:19.436406 Jitter Meter : NO K
7033 06:48:19.436490 CBT Training : PASS
7034 06:48:19.439703 Write leveling : NO K
7035 06:48:19.442549 RX DQS gating : PASS
7036 06:48:19.442634 RX DQ/DQS(RDDQC) : PASS
7037 06:48:19.446004 TX DQ/DQS : PASS
7038 06:48:19.449121 RX DATLAT : PASS
7039 06:48:19.449205 RX DQ/DQS(Engine): PASS
7040 06:48:19.452756 TX OE : NO K
7041 06:48:19.452839 All Pass.
7042 06:48:19.452925
7043 06:48:19.456039 DramC Write-DBI off
7044 06:48:19.459101 PER_BANK_REFRESH: Hybrid Mode
7045 06:48:19.459185 TX_TRACKING: ON
7046 06:48:19.469063 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7047 06:48:19.472405 [FAST_K] Save calibration result to emmc
7048 06:48:19.475253 dramc_set_vcore_voltage set vcore to 725000
7049 06:48:19.479482 Read voltage for 1600, 0
7050 06:48:19.479574 Vio18 = 0
7051 06:48:19.481923 Vcore = 725000
7052 06:48:19.482007 Vdram = 0
7053 06:48:19.482092 Vddq = 0
7054 06:48:19.482172 Vmddr = 0
7055 06:48:19.489040 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7056 06:48:19.495377 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7057 06:48:19.495500 MEM_TYPE=3, freq_sel=13
7058 06:48:19.498771 sv_algorithm_assistance_LP4_3733
7059 06:48:19.502115 ============ PULL DRAM RESETB DOWN ============
7060 06:48:19.508266 ========== PULL DRAM RESETB DOWN end =========
7061 06:48:19.511713 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7062 06:48:19.515473 ===================================
7063 06:48:19.518834 LPDDR4 DRAM CONFIGURATION
7064 06:48:19.521512 ===================================
7065 06:48:19.521596 EX_ROW_EN[0] = 0x0
7066 06:48:19.524741 EX_ROW_EN[1] = 0x0
7067 06:48:19.528128 LP4Y_EN = 0x0
7068 06:48:19.528212 WORK_FSP = 0x1
7069 06:48:19.531325 WL = 0x5
7070 06:48:19.531446 RL = 0x5
7071 06:48:19.534523 BL = 0x2
7072 06:48:19.534607 RPST = 0x0
7073 06:48:19.537946 RD_PRE = 0x0
7074 06:48:19.538030 WR_PRE = 0x1
7075 06:48:19.541198 WR_PST = 0x1
7076 06:48:19.541282 DBI_WR = 0x0
7077 06:48:19.544536 DBI_RD = 0x0
7078 06:48:19.544622 OTF = 0x1
7079 06:48:19.548278 ===================================
7080 06:48:19.551399 ===================================
7081 06:48:19.554688 ANA top config
7082 06:48:19.557476 ===================================
7083 06:48:19.561273 DLL_ASYNC_EN = 0
7084 06:48:19.561357 ALL_SLAVE_EN = 0
7085 06:48:19.564517 NEW_RANK_MODE = 1
7086 06:48:19.567549 DLL_IDLE_MODE = 1
7087 06:48:19.571006 LP45_APHY_COMB_EN = 1
7088 06:48:19.571090 TX_ODT_DIS = 0
7089 06:48:19.574317 NEW_8X_MODE = 1
7090 06:48:19.577427 ===================================
7091 06:48:19.580920 ===================================
7092 06:48:19.583826 data_rate = 3200
7093 06:48:19.587134 CKR = 1
7094 06:48:19.590415 DQ_P2S_RATIO = 8
7095 06:48:19.593841 ===================================
7096 06:48:19.597608 CA_P2S_RATIO = 8
7097 06:48:19.600282 DQ_CA_OPEN = 0
7098 06:48:19.600369 DQ_SEMI_OPEN = 0
7099 06:48:19.603611 CA_SEMI_OPEN = 0
7100 06:48:19.606943 CA_FULL_RATE = 0
7101 06:48:19.610387 DQ_CKDIV4_EN = 0
7102 06:48:19.613565 CA_CKDIV4_EN = 0
7103 06:48:19.617210 CA_PREDIV_EN = 0
7104 06:48:19.617295 PH8_DLY = 12
7105 06:48:19.620430 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7106 06:48:19.623535 DQ_AAMCK_DIV = 4
7107 06:48:19.626590 CA_AAMCK_DIV = 4
7108 06:48:19.630122 CA_ADMCK_DIV = 4
7109 06:48:19.633851 DQ_TRACK_CA_EN = 0
7110 06:48:19.633935 CA_PICK = 1600
7111 06:48:19.636955 CA_MCKIO = 1600
7112 06:48:19.639809 MCKIO_SEMI = 0
7113 06:48:19.643005 PLL_FREQ = 3068
7114 06:48:19.646696 DQ_UI_PI_RATIO = 32
7115 06:48:19.650045 CA_UI_PI_RATIO = 0
7116 06:48:19.652877 ===================================
7117 06:48:19.656337 ===================================
7118 06:48:19.659635 memory_type:LPDDR4
7119 06:48:19.659719 GP_NUM : 10
7120 06:48:19.663072 SRAM_EN : 1
7121 06:48:19.663155 MD32_EN : 0
7122 06:48:19.666072 ===================================
7123 06:48:19.669421 [ANA_INIT] >>>>>>>>>>>>>>
7124 06:48:19.673113 <<<<<< [CONFIGURE PHASE]: ANA_TX
7125 06:48:19.676161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7126 06:48:19.679200 ===================================
7127 06:48:19.682874 data_rate = 3200,PCW = 0X7600
7128 06:48:19.685749 ===================================
7129 06:48:19.689569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7130 06:48:19.695780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 06:48:19.698993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 06:48:19.705583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7133 06:48:19.709048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7134 06:48:19.712731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7135 06:48:19.712813 [ANA_INIT] flow start
7136 06:48:19.715886 [ANA_INIT] PLL >>>>>>>>
7137 06:48:19.718689 [ANA_INIT] PLL <<<<<<<<
7138 06:48:19.718801 [ANA_INIT] MIDPI >>>>>>>>
7139 06:48:19.722921 [ANA_INIT] MIDPI <<<<<<<<
7140 06:48:19.725692 [ANA_INIT] DLL >>>>>>>>
7141 06:48:19.728778 [ANA_INIT] DLL <<<<<<<<
7142 06:48:19.728856 [ANA_INIT] flow end
7143 06:48:19.732411 ============ LP4 DIFF to SE enter ============
7144 06:48:19.738966 ============ LP4 DIFF to SE exit ============
7145 06:48:19.739048 [ANA_INIT] <<<<<<<<<<<<<
7146 06:48:19.741828 [Flow] Enable top DCM control >>>>>
7147 06:48:19.745499 [Flow] Enable top DCM control <<<<<
7148 06:48:19.748892 Enable DLL master slave shuffle
7149 06:48:19.755160 ==============================================================
7150 06:48:19.755246 Gating Mode config
7151 06:48:19.761710 ==============================================================
7152 06:48:19.765446 Config description:
7153 06:48:19.775015 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7154 06:48:19.781398 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7155 06:48:19.784982 SELPH_MODE 0: By rank 1: By Phase
7156 06:48:19.791509 ==============================================================
7157 06:48:19.794508 GAT_TRACK_EN = 1
7158 06:48:19.798058 RX_GATING_MODE = 2
7159 06:48:19.801200 RX_GATING_TRACK_MODE = 2
7160 06:48:19.801282 SELPH_MODE = 1
7161 06:48:19.804515 PICG_EARLY_EN = 1
7162 06:48:19.807875 VALID_LAT_VALUE = 1
7163 06:48:19.814591 ==============================================================
7164 06:48:19.817481 Enter into Gating configuration >>>>
7165 06:48:19.821166 Exit from Gating configuration <<<<
7166 06:48:19.824621 Enter into DVFS_PRE_config >>>>>
7167 06:48:19.834001 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7168 06:48:19.837640 Exit from DVFS_PRE_config <<<<<
7169 06:48:19.841080 Enter into PICG configuration >>>>
7170 06:48:19.843933 Exit from PICG configuration <<<<
7171 06:48:19.847562 [RX_INPUT] configuration >>>>>
7172 06:48:19.850475 [RX_INPUT] configuration <<<<<
7173 06:48:19.853760 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7174 06:48:19.861398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7175 06:48:19.867034 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 06:48:19.873570 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 06:48:19.880210 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 06:48:19.886817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 06:48:19.889879 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7180 06:48:19.893150 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7181 06:48:19.896819 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7182 06:48:19.903043 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7183 06:48:19.906621 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7184 06:48:19.909616 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7185 06:48:19.913165 ===================================
7186 06:48:19.916311 LPDDR4 DRAM CONFIGURATION
7187 06:48:19.919632 ===================================
7188 06:48:19.923034 EX_ROW_EN[0] = 0x0
7189 06:48:19.923144 EX_ROW_EN[1] = 0x0
7190 06:48:19.926023 LP4Y_EN = 0x0
7191 06:48:19.926121 WORK_FSP = 0x1
7192 06:48:19.929399 WL = 0x5
7193 06:48:19.929499 RL = 0x5
7194 06:48:19.932652 BL = 0x2
7195 06:48:19.932726 RPST = 0x0
7196 06:48:19.936236 RD_PRE = 0x0
7197 06:48:19.936341 WR_PRE = 0x1
7198 06:48:19.939282 WR_PST = 0x1
7199 06:48:19.939425 DBI_WR = 0x0
7200 06:48:19.942874 DBI_RD = 0x0
7201 06:48:19.942980 OTF = 0x1
7202 06:48:19.945798 ===================================
7203 06:48:19.949211 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7204 06:48:19.956075 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7205 06:48:19.959286 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 06:48:19.962696 ===================================
7207 06:48:19.966058 LPDDR4 DRAM CONFIGURATION
7208 06:48:19.969009 ===================================
7209 06:48:19.973077 EX_ROW_EN[0] = 0x10
7210 06:48:19.973188 EX_ROW_EN[1] = 0x0
7211 06:48:19.975536 LP4Y_EN = 0x0
7212 06:48:19.975635 WORK_FSP = 0x1
7213 06:48:19.978904 WL = 0x5
7214 06:48:19.979000 RL = 0x5
7215 06:48:19.982075 BL = 0x2
7216 06:48:19.982178 RPST = 0x0
7217 06:48:19.985513 RD_PRE = 0x0
7218 06:48:19.985624 WR_PRE = 0x1
7219 06:48:19.988760 WR_PST = 0x1
7220 06:48:19.988897 DBI_WR = 0x0
7221 06:48:19.991917 DBI_RD = 0x0
7222 06:48:19.991998 OTF = 0x1
7223 06:48:19.995218 ===================================
7224 06:48:20.001818 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7225 06:48:20.001903 ==
7226 06:48:20.005162 Dram Type= 6, Freq= 0, CH_0, rank 0
7227 06:48:20.012160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7228 06:48:20.012243 ==
7229 06:48:20.012308 [Duty_Offset_Calibration]
7230 06:48:20.014936 B0:2 B1:0 CA:4
7231 06:48:20.015017
7232 06:48:20.018379 [DutyScan_Calibration_Flow] k_type=0
7233 06:48:20.027127
7234 06:48:20.027207 ==CLK 0==
7235 06:48:20.030295 Final CLK duty delay cell = -4
7236 06:48:20.034150 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7237 06:48:20.037007 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7238 06:48:20.040488 [-4] AVG Duty = 4937%(X100)
7239 06:48:20.040569
7240 06:48:20.044270 CH0 CLK Duty spec in!! Max-Min= 187%
7241 06:48:20.046992 [DutyScan_Calibration_Flow] ====Done====
7242 06:48:20.047073
7243 06:48:20.049879 [DutyScan_Calibration_Flow] k_type=1
7244 06:48:20.067825
7245 06:48:20.067906 ==DQS 0 ==
7246 06:48:20.070580 Final DQS duty delay cell = 0
7247 06:48:20.074233 [0] MAX Duty = 5218%(X100), DQS PI = 22
7248 06:48:20.077514 [0] MIN Duty = 5093%(X100), DQS PI = 10
7249 06:48:20.077596 [0] AVG Duty = 5155%(X100)
7250 06:48:20.080929
7251 06:48:20.081009 ==DQS 1 ==
7252 06:48:20.084417 Final DQS duty delay cell = 0
7253 06:48:20.087348 [0] MAX Duty = 5156%(X100), DQS PI = 0
7254 06:48:20.090596 [0] MIN Duty = 4969%(X100), DQS PI = 10
7255 06:48:20.093578 [0] AVG Duty = 5062%(X100)
7256 06:48:20.093688
7257 06:48:20.097119 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7258 06:48:20.097230
7259 06:48:20.100489 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7260 06:48:20.103784 [DutyScan_Calibration_Flow] ====Done====
7261 06:48:20.103893
7262 06:48:20.107160 [DutyScan_Calibration_Flow] k_type=3
7263 06:48:20.124352
7264 06:48:20.124435 ==DQM 0 ==
7265 06:48:20.127949 Final DQM duty delay cell = 0
7266 06:48:20.131004 [0] MAX Duty = 5124%(X100), DQS PI = 22
7267 06:48:20.134077 [0] MIN Duty = 4875%(X100), DQS PI = 54
7268 06:48:20.137793 [0] AVG Duty = 4999%(X100)
7269 06:48:20.137874
7270 06:48:20.137938 ==DQM 1 ==
7271 06:48:20.141400 Final DQM duty delay cell = 0
7272 06:48:20.144037 [0] MAX Duty = 5000%(X100), DQS PI = 2
7273 06:48:20.147322 [0] MIN Duty = 4844%(X100), DQS PI = 14
7274 06:48:20.151124 [0] AVG Duty = 4922%(X100)
7275 06:48:20.151205
7276 06:48:20.154299 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7277 06:48:20.154380
7278 06:48:20.157678 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7279 06:48:20.160750 [DutyScan_Calibration_Flow] ====Done====
7280 06:48:20.160831
7281 06:48:20.164186 [DutyScan_Calibration_Flow] k_type=2
7282 06:48:20.181615
7283 06:48:20.181736 ==DQ 0 ==
7284 06:48:20.184697 Final DQ duty delay cell = 0
7285 06:48:20.188198 [0] MAX Duty = 5156%(X100), DQS PI = 20
7286 06:48:20.191352 [0] MIN Duty = 4938%(X100), DQS PI = 14
7287 06:48:20.191474 [0] AVG Duty = 5047%(X100)
7288 06:48:20.194800
7289 06:48:20.194881 ==DQ 1 ==
7290 06:48:20.198033 Final DQ duty delay cell = 0
7291 06:48:20.201451 [0] MAX Duty = 5187%(X100), DQS PI = 2
7292 06:48:20.204958 [0] MIN Duty = 4907%(X100), DQS PI = 34
7293 06:48:20.205039 [0] AVG Duty = 5047%(X100)
7294 06:48:20.205104
7295 06:48:20.211709 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7296 06:48:20.211817
7297 06:48:20.214861 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7298 06:48:20.217726 [DutyScan_Calibration_Flow] ====Done====
7299 06:48:20.217824 ==
7300 06:48:20.221058 Dram Type= 6, Freq= 0, CH_1, rank 0
7301 06:48:20.224246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7302 06:48:20.224354 ==
7303 06:48:20.227711 [Duty_Offset_Calibration]
7304 06:48:20.227808 B0:0 B1:-1 CA:3
7305 06:48:20.227907
7306 06:48:20.231010 [DutyScan_Calibration_Flow] k_type=0
7307 06:48:20.241942
7308 06:48:20.242024 ==CLK 0==
7309 06:48:20.244744 Final CLK duty delay cell = -4
7310 06:48:20.247583 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7311 06:48:20.250822 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7312 06:48:20.254190 [-4] AVG Duty = 4922%(X100)
7313 06:48:20.254274
7314 06:48:20.257319 CH1 CLK Duty spec in!! Max-Min= 156%
7315 06:48:20.260683 [DutyScan_Calibration_Flow] ====Done====
7316 06:48:20.260764
7317 06:48:20.263788 [DutyScan_Calibration_Flow] k_type=1
7318 06:48:20.280281
7319 06:48:20.280406 ==DQS 0 ==
7320 06:48:20.283621 Final DQS duty delay cell = 0
7321 06:48:20.287045 [0] MAX Duty = 5250%(X100), DQS PI = 30
7322 06:48:20.290182 [0] MIN Duty = 4938%(X100), DQS PI = 58
7323 06:48:20.293706 [0] AVG Duty = 5094%(X100)
7324 06:48:20.293787
7325 06:48:20.293851 ==DQS 1 ==
7326 06:48:20.296791 Final DQS duty delay cell = -4
7327 06:48:20.299903 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7328 06:48:20.303266 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7329 06:48:20.306666 [-4] AVG Duty = 4937%(X100)
7330 06:48:20.306773
7331 06:48:20.310091 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7332 06:48:20.310189
7333 06:48:20.313096 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7334 06:48:20.316438 [DutyScan_Calibration_Flow] ====Done====
7335 06:48:20.316522
7336 06:48:20.319641 [DutyScan_Calibration_Flow] k_type=3
7337 06:48:20.337659
7338 06:48:20.337769 ==DQM 0 ==
7339 06:48:20.340742 Final DQM duty delay cell = 0
7340 06:48:20.344228 [0] MAX Duty = 5062%(X100), DQS PI = 30
7341 06:48:20.347618 [0] MIN Duty = 4782%(X100), DQS PI = 40
7342 06:48:20.350643 [0] AVG Duty = 4922%(X100)
7343 06:48:20.350744
7344 06:48:20.350839 ==DQM 1 ==
7345 06:48:20.353773 Final DQM duty delay cell = 0
7346 06:48:20.357261 [0] MAX Duty = 5000%(X100), DQS PI = 30
7347 06:48:20.360422 [0] MIN Duty = 4813%(X100), DQS PI = 0
7348 06:48:20.364030 [0] AVG Duty = 4906%(X100)
7349 06:48:20.364107
7350 06:48:20.367236 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7351 06:48:20.367307
7352 06:48:20.370427 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7353 06:48:20.373865 [DutyScan_Calibration_Flow] ====Done====
7354 06:48:20.373946
7355 06:48:20.377255 [DutyScan_Calibration_Flow] k_type=2
7356 06:48:20.393287
7357 06:48:20.393370 ==DQ 0 ==
7358 06:48:20.396666 Final DQ duty delay cell = -4
7359 06:48:20.400559 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7360 06:48:20.403526 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7361 06:48:20.406693 [-4] AVG Duty = 4891%(X100)
7362 06:48:20.406774
7363 06:48:20.406838 ==DQ 1 ==
7364 06:48:20.410124 Final DQ duty delay cell = 0
7365 06:48:20.413553 [0] MAX Duty = 5062%(X100), DQS PI = 32
7366 06:48:20.416262 [0] MIN Duty = 4875%(X100), DQS PI = 58
7367 06:48:20.419605 [0] AVG Duty = 4968%(X100)
7368 06:48:20.419748
7369 06:48:20.422923 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7370 06:48:20.423008
7371 06:48:20.426513 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7372 06:48:20.429550 [DutyScan_Calibration_Flow] ====Done====
7373 06:48:20.432892 nWR fixed to 30
7374 06:48:20.436083 [ModeRegInit_LP4] CH0 RK0
7375 06:48:20.436164 [ModeRegInit_LP4] CH0 RK1
7376 06:48:20.439813 [ModeRegInit_LP4] CH1 RK0
7377 06:48:20.443015 [ModeRegInit_LP4] CH1 RK1
7378 06:48:20.443096 match AC timing 5
7379 06:48:20.449299 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7380 06:48:20.452750 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7381 06:48:20.456052 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7382 06:48:20.462469 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7383 06:48:20.465613 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7384 06:48:20.468835 [MiockJmeterHQA]
7385 06:48:20.468918
7386 06:48:20.472268 [DramcMiockJmeter] u1RxGatingPI = 0
7387 06:48:20.472351 0 : 4253, 4027
7388 06:48:20.472418 4 : 4364, 4137
7389 06:48:20.475692 8 : 4252, 4026
7390 06:48:20.475776 12 : 4363, 4138
7391 06:48:20.479126 16 : 4253, 4027
7392 06:48:20.479195 20 : 4253, 4027
7393 06:48:20.482201 24 : 4253, 4026
7394 06:48:20.482283 28 : 4252, 4030
7395 06:48:20.485509 32 : 4360, 4137
7396 06:48:20.485593 36 : 4252, 4027
7397 06:48:20.485658 40 : 4250, 4027
7398 06:48:20.488600 44 : 4250, 4026
7399 06:48:20.488683 48 : 4252, 4030
7400 06:48:20.492305 52 : 4249, 4027
7401 06:48:20.492389 56 : 4361, 4138
7402 06:48:20.495273 60 : 4363, 4138
7403 06:48:20.495356 64 : 4250, 4026
7404 06:48:20.498940 68 : 4250, 4027
7405 06:48:20.499022 72 : 4250, 4027
7406 06:48:20.499088 76 : 4250, 4027
7407 06:48:20.502481 80 : 4252, 4029
7408 06:48:20.502564 84 : 4361, 4137
7409 06:48:20.505767 88 : 4252, 4027
7410 06:48:20.505852 92 : 4249, 4027
7411 06:48:20.508569 96 : 4250, 2986
7412 06:48:20.508652 100 : 4252, 0
7413 06:48:20.508717 104 : 4250, 0
7414 06:48:20.512001 108 : 4250, 0
7415 06:48:20.512084 112 : 4253, 0
7416 06:48:20.515317 116 : 4361, 0
7417 06:48:20.515424 120 : 4360, 0
7418 06:48:20.515490 124 : 4363, 0
7419 06:48:20.518437 128 : 4250, 0
7420 06:48:20.518519 132 : 4250, 0
7421 06:48:20.521751 136 : 4250, 0
7422 06:48:20.521837 140 : 4250, 0
7423 06:48:20.521902 144 : 4250, 0
7424 06:48:20.525242 148 : 4250, 0
7425 06:48:20.525354 152 : 4253, 0
7426 06:48:20.525449 156 : 4250, 0
7427 06:48:20.528524 160 : 4250, 0
7428 06:48:20.528606 164 : 4253, 0
7429 06:48:20.532159 168 : 4361, 0
7430 06:48:20.532242 172 : 4361, 0
7431 06:48:20.532307 176 : 4363, 0
7432 06:48:20.535341 180 : 4250, 0
7433 06:48:20.535459 184 : 4250, 0
7434 06:48:20.538147 188 : 4250, 0
7435 06:48:20.538229 192 : 4250, 0
7436 06:48:20.538294 196 : 4250, 0
7437 06:48:20.541804 200 : 4250, 0
7438 06:48:20.541887 204 : 4253, 0
7439 06:48:20.545046 208 : 4250, 0
7440 06:48:20.545128 212 : 4249, 0
7441 06:48:20.545193 216 : 4253, 0
7442 06:48:20.548126 220 : 4250, 489
7443 06:48:20.548209 224 : 4360, 4127
7444 06:48:20.551308 228 : 4252, 4030
7445 06:48:20.551434 232 : 4250, 4027
7446 06:48:20.554534 236 : 4250, 4027
7447 06:48:20.554617 240 : 4252, 4030
7448 06:48:20.558372 244 : 4250, 4027
7449 06:48:20.558454 248 : 4250, 4026
7450 06:48:20.561023 252 : 4361, 4137
7451 06:48:20.561106 256 : 4250, 4027
7452 06:48:20.565030 260 : 4250, 4026
7453 06:48:20.565116 264 : 4361, 4138
7454 06:48:20.565181 268 : 4250, 4027
7455 06:48:20.568236 272 : 4250, 4027
7456 06:48:20.568319 276 : 4363, 4140
7457 06:48:20.571230 280 : 4250, 4027
7458 06:48:20.571312 284 : 4250, 4027
7459 06:48:20.574803 288 : 4250, 4027
7460 06:48:20.574916 292 : 4253, 4029
7461 06:48:20.577825 296 : 4250, 4027
7462 06:48:20.577907 300 : 4250, 4026
7463 06:48:20.581243 304 : 4361, 4137
7464 06:48:20.581326 308 : 4250, 4027
7465 06:48:20.584612 312 : 4250, 4026
7466 06:48:20.584694 316 : 4361, 4138
7467 06:48:20.587504 320 : 4250, 4026
7468 06:48:20.587586 324 : 4250, 4027
7469 06:48:20.591067 328 : 4363, 4140
7470 06:48:20.591149 332 : 4250, 3973
7471 06:48:20.591214 336 : 4250, 1798
7472 06:48:20.594123
7473 06:48:20.594206 MIOCK jitter meter ch=0
7474 06:48:20.594272
7475 06:48:20.597624 1T = (336-100) = 236 dly cells
7476 06:48:20.604028 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7477 06:48:20.604112 ==
7478 06:48:20.607606 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 06:48:20.611294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7480 06:48:20.611401 ==
7481 06:48:20.617343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7482 06:48:20.620747 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7483 06:48:20.624111 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7484 06:48:20.630609 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7485 06:48:20.640158 [CA 0] Center 44 (14~74) winsize 61
7486 06:48:20.643710 [CA 1] Center 43 (13~74) winsize 62
7487 06:48:20.646804 [CA 2] Center 39 (10~68) winsize 59
7488 06:48:20.650132 [CA 3] Center 38 (9~68) winsize 60
7489 06:48:20.653581 [CA 4] Center 36 (7~66) winsize 60
7490 06:48:20.657161 [CA 5] Center 36 (6~66) winsize 61
7491 06:48:20.657244
7492 06:48:20.659895 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7493 06:48:20.659977
7494 06:48:20.663541 [CATrainingPosCal] consider 1 rank data
7495 06:48:20.666526 u2DelayCellTimex100 = 275/100 ps
7496 06:48:20.673408 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7497 06:48:20.676451 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7498 06:48:20.679857 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7499 06:48:20.683333 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7500 06:48:20.686323 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7501 06:48:20.689707 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7502 06:48:20.689789
7503 06:48:20.693227 CA PerBit enable=1, Macro0, CA PI delay=36
7504 06:48:20.693309
7505 06:48:20.696408 [CBTSetCACLKResult] CA Dly = 36
7506 06:48:20.699559 CS Dly: 10 (0~41)
7507 06:48:20.703081 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7508 06:48:20.706137 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7509 06:48:20.706220 ==
7510 06:48:20.709349 Dram Type= 6, Freq= 0, CH_0, rank 1
7511 06:48:20.716358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 06:48:20.716440 ==
7513 06:48:20.719170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 06:48:20.726162 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 06:48:20.729053 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 06:48:20.735973 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 06:48:20.743654 [CA 0] Center 44 (14~75) winsize 62
7518 06:48:20.747658 [CA 1] Center 44 (14~74) winsize 61
7519 06:48:20.750680 [CA 2] Center 39 (10~69) winsize 60
7520 06:48:20.753634 [CA 3] Center 39 (10~68) winsize 59
7521 06:48:20.757149 [CA 4] Center 37 (7~67) winsize 61
7522 06:48:20.760289 [CA 5] Center 36 (7~66) winsize 60
7523 06:48:20.760364
7524 06:48:20.763783 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7525 06:48:20.763854
7526 06:48:20.770413 [CATrainingPosCal] consider 2 rank data
7527 06:48:20.770496 u2DelayCellTimex100 = 275/100 ps
7528 06:48:20.776929 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7529 06:48:20.780346 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7530 06:48:20.783461 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7531 06:48:20.786591 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7532 06:48:20.789993 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7533 06:48:20.793734 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7534 06:48:20.793845
7535 06:48:20.796640 CA PerBit enable=1, Macro0, CA PI delay=36
7536 06:48:20.796718
7537 06:48:20.799924 [CBTSetCACLKResult] CA Dly = 36
7538 06:48:20.802971 CS Dly: 11 (0~43)
7539 06:48:20.806611 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 06:48:20.809898 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 06:48:20.809971
7542 06:48:20.812969 ----->DramcWriteLeveling(PI) begin...
7543 06:48:20.816591 ==
7544 06:48:20.819500 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 06:48:20.822857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 06:48:20.822941 ==
7547 06:48:20.826367 Write leveling (Byte 0): 35 => 35
7548 06:48:20.829287 Write leveling (Byte 1): 25 => 25
7549 06:48:20.832489 DramcWriteLeveling(PI) end<-----
7550 06:48:20.832570
7551 06:48:20.832634 ==
7552 06:48:20.836052 Dram Type= 6, Freq= 0, CH_0, rank 0
7553 06:48:20.840044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 06:48:20.840127 ==
7555 06:48:20.843117 [Gating] SW mode calibration
7556 06:48:20.848899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7557 06:48:20.855964 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7558 06:48:20.859130 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 06:48:20.862132 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 06:48:20.868989 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7561 06:48:20.872058 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7562 06:48:20.875331 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7563 06:48:20.882337 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
7564 06:48:20.885378 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 06:48:20.889043 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7566 06:48:20.895338 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 06:48:20.898591 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7568 06:48:20.901844 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7569 06:48:20.908098 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 1)
7570 06:48:20.911987 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7571 06:48:20.915140 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7572 06:48:20.921456 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7573 06:48:20.924603 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 06:48:20.927869 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 06:48:20.934661 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 06:48:20.938678 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7577 06:48:20.941530 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7578 06:48:20.947816 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7579 06:48:20.951057 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7580 06:48:20.955161 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7581 06:48:20.961705 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 06:48:20.964283 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 06:48:20.967696 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 06:48:20.974787 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7585 06:48:20.977718 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7586 06:48:20.981015 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7587 06:48:20.987779 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7588 06:48:20.990629 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7589 06:48:20.993892 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 06:48:21.000576 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 06:48:21.003977 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 06:48:21.007484 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 06:48:21.014013 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 06:48:21.017159 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 06:48:21.020409 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 06:48:21.026881 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 06:48:21.030519 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 06:48:21.033790 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 06:48:21.040242 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 06:48:21.043336 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7601 06:48:21.046764 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7602 06:48:21.052949 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7603 06:48:21.057014 Total UI for P1: 0, mck2ui 16
7604 06:48:21.059720 best dqsien dly found for B0: ( 1, 9, 10)
7605 06:48:21.063442 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7606 06:48:21.066261 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 06:48:21.072711 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 06:48:21.076371 Total UI for P1: 0, mck2ui 16
7609 06:48:21.079328 best dqsien dly found for B1: ( 1, 9, 22)
7610 06:48:21.083046 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7611 06:48:21.086123 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7612 06:48:21.086207
7613 06:48:21.089511 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7614 06:48:21.092872 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7615 06:48:21.096092 [Gating] SW calibration Done
7616 06:48:21.096182 ==
7617 06:48:21.099557 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 06:48:21.102562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 06:48:21.102645 ==
7620 06:48:21.106059 RX Vref Scan: 0
7621 06:48:21.106140
7622 06:48:21.109503 RX Vref 0 -> 0, step: 1
7623 06:48:21.109599
7624 06:48:21.109680 RX Delay 0 -> 252, step: 8
7625 06:48:21.116368 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7626 06:48:21.119578 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7627 06:48:21.122462 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7628 06:48:21.126227 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7629 06:48:21.129091 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7630 06:48:21.135703 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7631 06:48:21.139399 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7632 06:48:21.142210 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7633 06:48:21.145458 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7634 06:48:21.148957 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7635 06:48:21.155311 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7636 06:48:21.158888 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7637 06:48:21.162013 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7638 06:48:21.165302 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7639 06:48:21.171676 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7640 06:48:21.175114 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7641 06:48:21.175196 ==
7642 06:48:21.178214 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 06:48:21.181912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 06:48:21.181995 ==
7645 06:48:21.185126 DQS Delay:
7646 06:48:21.185208 DQS0 = 0, DQS1 = 0
7647 06:48:21.185272 DQM Delay:
7648 06:48:21.188202 DQM0 = 132, DQM1 = 126
7649 06:48:21.188284 DQ Delay:
7650 06:48:21.191358 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7651 06:48:21.195616 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7652 06:48:21.198447 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7653 06:48:21.204633 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
7654 06:48:21.204713
7655 06:48:21.204776
7656 06:48:21.204841 ==
7657 06:48:21.207793 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 06:48:21.211255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 06:48:21.211353 ==
7660 06:48:21.211475
7661 06:48:21.211566
7662 06:48:21.214729 TX Vref Scan disable
7663 06:48:21.214811 == TX Byte 0 ==
7664 06:48:21.221005 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7665 06:48:21.224642 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7666 06:48:21.227949 == TX Byte 1 ==
7667 06:48:21.230955 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7668 06:48:21.234591 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7669 06:48:21.234673 ==
7670 06:48:21.237732 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 06:48:21.241082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 06:48:21.244090 ==
7673 06:48:21.256030
7674 06:48:21.259896 TX Vref early break, caculate TX vref
7675 06:48:21.262673 TX Vref=16, minBit 4, minWin=22, winSum=372
7676 06:48:21.266263 TX Vref=18, minBit 1, minWin=23, winSum=382
7677 06:48:21.269591 TX Vref=20, minBit 1, minWin=23, winSum=386
7678 06:48:21.272667 TX Vref=22, minBit 1, minWin=23, winSum=396
7679 06:48:21.276131 TX Vref=24, minBit 4, minWin=24, winSum=404
7680 06:48:21.282548 TX Vref=26, minBit 1, minWin=25, winSum=414
7681 06:48:21.285972 TX Vref=28, minBit 4, minWin=25, winSum=418
7682 06:48:21.289164 TX Vref=30, minBit 2, minWin=25, winSum=414
7683 06:48:21.292390 TX Vref=32, minBit 4, minWin=24, winSum=408
7684 06:48:21.295679 TX Vref=34, minBit 0, minWin=24, winSum=393
7685 06:48:21.302853 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
7686 06:48:21.302935
7687 06:48:21.305645 Final TX Range 0 Vref 28
7688 06:48:21.305727
7689 06:48:21.305791 ==
7690 06:48:21.309408 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 06:48:21.311988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 06:48:21.312071 ==
7693 06:48:21.312135
7694 06:48:21.312195
7695 06:48:21.315319 TX Vref Scan disable
7696 06:48:21.322169 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7697 06:48:21.322250 == TX Byte 0 ==
7698 06:48:21.325690 u2DelayCellOfst[0]=10 cells (3 PI)
7699 06:48:21.328539 u2DelayCellOfst[1]=14 cells (4 PI)
7700 06:48:21.331898 u2DelayCellOfst[2]=10 cells (3 PI)
7701 06:48:21.335144 u2DelayCellOfst[3]=7 cells (2 PI)
7702 06:48:21.338999 u2DelayCellOfst[4]=7 cells (2 PI)
7703 06:48:21.341715 u2DelayCellOfst[5]=0 cells (0 PI)
7704 06:48:21.345070 u2DelayCellOfst[6]=14 cells (4 PI)
7705 06:48:21.348684 u2DelayCellOfst[7]=14 cells (4 PI)
7706 06:48:21.352238 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7707 06:48:21.355052 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7708 06:48:21.358698 == TX Byte 1 ==
7709 06:48:21.361800 u2DelayCellOfst[8]=0 cells (0 PI)
7710 06:48:21.365236 u2DelayCellOfst[9]=0 cells (0 PI)
7711 06:48:21.368420 u2DelayCellOfst[10]=3 cells (1 PI)
7712 06:48:21.368501 u2DelayCellOfst[11]=0 cells (0 PI)
7713 06:48:21.371802 u2DelayCellOfst[12]=7 cells (2 PI)
7714 06:48:21.374782 u2DelayCellOfst[13]=7 cells (2 PI)
7715 06:48:21.378434 u2DelayCellOfst[14]=10 cells (3 PI)
7716 06:48:21.381507 u2DelayCellOfst[15]=10 cells (3 PI)
7717 06:48:21.388053 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7718 06:48:21.391106 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7719 06:48:21.391189 DramC Write-DBI on
7720 06:48:21.394665 ==
7721 06:48:21.394810 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 06:48:21.400880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 06:48:21.400988 ==
7724 06:48:21.401080
7725 06:48:21.401168
7726 06:48:21.404591 TX Vref Scan disable
7727 06:48:21.404673 == TX Byte 0 ==
7728 06:48:21.410967 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7729 06:48:21.411050 == TX Byte 1 ==
7730 06:48:21.414024 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7731 06:48:21.417388 DramC Write-DBI off
7732 06:48:21.417469
7733 06:48:21.417533 [DATLAT]
7734 06:48:21.420514 Freq=1600, CH0 RK0
7735 06:48:21.420596
7736 06:48:21.420660 DATLAT Default: 0xf
7737 06:48:21.423762 0, 0xFFFF, sum = 0
7738 06:48:21.423846 1, 0xFFFF, sum = 0
7739 06:48:21.427409 2, 0xFFFF, sum = 0
7740 06:48:21.430708 3, 0xFFFF, sum = 0
7741 06:48:21.430791 4, 0xFFFF, sum = 0
7742 06:48:21.433605 5, 0xFFFF, sum = 0
7743 06:48:21.433688 6, 0xFFFF, sum = 0
7744 06:48:21.437335 7, 0xFFFF, sum = 0
7745 06:48:21.437417 8, 0xFFFF, sum = 0
7746 06:48:21.441151 9, 0xFFFF, sum = 0
7747 06:48:21.441233 10, 0xFFFF, sum = 0
7748 06:48:21.443547 11, 0xFFFF, sum = 0
7749 06:48:21.443629 12, 0xFFFF, sum = 0
7750 06:48:21.447054 13, 0xFFFF, sum = 0
7751 06:48:21.447137 14, 0x0, sum = 1
7752 06:48:21.450206 15, 0x0, sum = 2
7753 06:48:21.450289 16, 0x0, sum = 3
7754 06:48:21.453585 17, 0x0, sum = 4
7755 06:48:21.453667 best_step = 15
7756 06:48:21.453732
7757 06:48:21.453791 ==
7758 06:48:21.456792 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 06:48:21.463726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 06:48:21.463808 ==
7761 06:48:21.463871 RX Vref Scan: 1
7762 06:48:21.463931
7763 06:48:21.466725 Set Vref Range= 24 -> 127
7764 06:48:21.466836
7765 06:48:21.470566 RX Vref 24 -> 127, step: 1
7766 06:48:21.470647
7767 06:48:21.470710 RX Delay 11 -> 252, step: 4
7768 06:48:21.470770
7769 06:48:21.473656 Set Vref, RX VrefLevel [Byte0]: 24
7770 06:48:21.476788 [Byte1]: 24
7771 06:48:21.480670
7772 06:48:21.480751 Set Vref, RX VrefLevel [Byte0]: 25
7773 06:48:21.484326 [Byte1]: 25
7774 06:48:21.488091
7775 06:48:21.488171 Set Vref, RX VrefLevel [Byte0]: 26
7776 06:48:21.492077 [Byte1]: 26
7777 06:48:21.495825
7778 06:48:21.495905 Set Vref, RX VrefLevel [Byte0]: 27
7779 06:48:21.499539 [Byte1]: 27
7780 06:48:21.503640
7781 06:48:21.503733 Set Vref, RX VrefLevel [Byte0]: 28
7782 06:48:21.507370 [Byte1]: 28
7783 06:48:21.511767
7784 06:48:21.511851 Set Vref, RX VrefLevel [Byte0]: 29
7785 06:48:21.514322 [Byte1]: 29
7786 06:48:21.518655
7787 06:48:21.518737 Set Vref, RX VrefLevel [Byte0]: 30
7788 06:48:21.521842 [Byte1]: 30
7789 06:48:21.526499
7790 06:48:21.526581 Set Vref, RX VrefLevel [Byte0]: 31
7791 06:48:21.529750 [Byte1]: 31
7792 06:48:21.534242
7793 06:48:21.534324 Set Vref, RX VrefLevel [Byte0]: 32
7794 06:48:21.537361 [Byte1]: 32
7795 06:48:21.542037
7796 06:48:21.542154 Set Vref, RX VrefLevel [Byte0]: 33
7797 06:48:21.544800 [Byte1]: 33
7798 06:48:21.549495
7799 06:48:21.549576 Set Vref, RX VrefLevel [Byte0]: 34
7800 06:48:21.552869 [Byte1]: 34
7801 06:48:21.556680
7802 06:48:21.556789 Set Vref, RX VrefLevel [Byte0]: 35
7803 06:48:21.560302 [Byte1]: 35
7804 06:48:21.564347
7805 06:48:21.564428 Set Vref, RX VrefLevel [Byte0]: 36
7806 06:48:21.567743 [Byte1]: 36
7807 06:48:21.571862
7808 06:48:21.571943 Set Vref, RX VrefLevel [Byte0]: 37
7809 06:48:21.576206 [Byte1]: 37
7810 06:48:21.579497
7811 06:48:21.579582 Set Vref, RX VrefLevel [Byte0]: 38
7812 06:48:21.582921 [Byte1]: 38
7813 06:48:21.587574
7814 06:48:21.587656 Set Vref, RX VrefLevel [Byte0]: 39
7815 06:48:21.590542 [Byte1]: 39
7816 06:48:21.594793
7817 06:48:21.594875 Set Vref, RX VrefLevel [Byte0]: 40
7818 06:48:21.598555 [Byte1]: 40
7819 06:48:21.602853
7820 06:48:21.602934 Set Vref, RX VrefLevel [Byte0]: 41
7821 06:48:21.605710 [Byte1]: 41
7822 06:48:21.610099
7823 06:48:21.610200 Set Vref, RX VrefLevel [Byte0]: 42
7824 06:48:21.613283 [Byte1]: 42
7825 06:48:21.617565
7826 06:48:21.617647 Set Vref, RX VrefLevel [Byte0]: 43
7827 06:48:21.620873 [Byte1]: 43
7828 06:48:21.625637
7829 06:48:21.625718 Set Vref, RX VrefLevel [Byte0]: 44
7830 06:48:21.628552 [Byte1]: 44
7831 06:48:21.632939
7832 06:48:21.633046 Set Vref, RX VrefLevel [Byte0]: 45
7833 06:48:21.636529 [Byte1]: 45
7834 06:48:21.641231
7835 06:48:21.641312 Set Vref, RX VrefLevel [Byte0]: 46
7836 06:48:21.643867 [Byte1]: 46
7837 06:48:21.648538
7838 06:48:21.648647 Set Vref, RX VrefLevel [Byte0]: 47
7839 06:48:21.651697 [Byte1]: 47
7840 06:48:21.656227
7841 06:48:21.656309 Set Vref, RX VrefLevel [Byte0]: 48
7842 06:48:21.659016 [Byte1]: 48
7843 06:48:21.663293
7844 06:48:21.663382 Set Vref, RX VrefLevel [Byte0]: 49
7845 06:48:21.666739 [Byte1]: 49
7846 06:48:21.671061
7847 06:48:21.671139 Set Vref, RX VrefLevel [Byte0]: 50
7848 06:48:21.675017 [Byte1]: 50
7849 06:48:21.678427
7850 06:48:21.678509 Set Vref, RX VrefLevel [Byte0]: 51
7851 06:48:21.682044 [Byte1]: 51
7852 06:48:21.686577
7853 06:48:21.686662 Set Vref, RX VrefLevel [Byte0]: 52
7854 06:48:21.689457 [Byte1]: 52
7855 06:48:21.694012
7856 06:48:21.694095 Set Vref, RX VrefLevel [Byte0]: 53
7857 06:48:21.697352 [Byte1]: 53
7858 06:48:21.701628
7859 06:48:21.701709 Set Vref, RX VrefLevel [Byte0]: 54
7860 06:48:21.704802 [Byte1]: 54
7861 06:48:21.708920
7862 06:48:21.709001 Set Vref, RX VrefLevel [Byte0]: 55
7863 06:48:21.712296 [Byte1]: 55
7864 06:48:21.716874
7865 06:48:21.716951 Set Vref, RX VrefLevel [Byte0]: 56
7866 06:48:21.719765 [Byte1]: 56
7867 06:48:21.724403
7868 06:48:21.724484 Set Vref, RX VrefLevel [Byte0]: 57
7869 06:48:21.727596 [Byte1]: 57
7870 06:48:21.732254
7871 06:48:21.732341 Set Vref, RX VrefLevel [Byte0]: 58
7872 06:48:21.735197 [Byte1]: 58
7873 06:48:21.739434
7874 06:48:21.739519 Set Vref, RX VrefLevel [Byte0]: 59
7875 06:48:21.742823 [Byte1]: 59
7876 06:48:21.747346
7877 06:48:21.747452 Set Vref, RX VrefLevel [Byte0]: 60
7878 06:48:21.750696 [Byte1]: 60
7879 06:48:21.754627
7880 06:48:21.754737 Set Vref, RX VrefLevel [Byte0]: 61
7881 06:48:21.758281 [Byte1]: 61
7882 06:48:21.762252
7883 06:48:21.762333 Set Vref, RX VrefLevel [Byte0]: 62
7884 06:48:21.765920 [Byte1]: 62
7885 06:48:21.770511
7886 06:48:21.770593 Set Vref, RX VrefLevel [Byte0]: 63
7887 06:48:21.773565 [Byte1]: 63
7888 06:48:21.777560
7889 06:48:21.777641 Set Vref, RX VrefLevel [Byte0]: 64
7890 06:48:21.781149 [Byte1]: 64
7891 06:48:21.785117
7892 06:48:21.785199 Set Vref, RX VrefLevel [Byte0]: 65
7893 06:48:21.788809 [Byte1]: 65
7894 06:48:21.793042
7895 06:48:21.793161 Set Vref, RX VrefLevel [Byte0]: 66
7896 06:48:21.796353 [Byte1]: 66
7897 06:48:21.800383
7898 06:48:21.800491 Set Vref, RX VrefLevel [Byte0]: 67
7899 06:48:21.803540 [Byte1]: 67
7900 06:48:21.807981
7901 06:48:21.808063 Set Vref, RX VrefLevel [Byte0]: 68
7902 06:48:21.811266 [Byte1]: 68
7903 06:48:21.815536
7904 06:48:21.815617 Set Vref, RX VrefLevel [Byte0]: 69
7905 06:48:21.818886 [Byte1]: 69
7906 06:48:21.823079
7907 06:48:21.823160 Set Vref, RX VrefLevel [Byte0]: 70
7908 06:48:21.826456 [Byte1]: 70
7909 06:48:21.831104
7910 06:48:21.831186 Set Vref, RX VrefLevel [Byte0]: 71
7911 06:48:21.833999 [Byte1]: 71
7912 06:48:21.838513
7913 06:48:21.838595 Set Vref, RX VrefLevel [Byte0]: 72
7914 06:48:21.842024 [Byte1]: 72
7915 06:48:21.846003
7916 06:48:21.846084 Set Vref, RX VrefLevel [Byte0]: 73
7917 06:48:21.849467 [Byte1]: 73
7918 06:48:21.853812
7919 06:48:21.853894 Final RX Vref Byte 0 = 54 to rank0
7920 06:48:21.856980 Final RX Vref Byte 1 = 61 to rank0
7921 06:48:21.860480 Final RX Vref Byte 0 = 54 to rank1
7922 06:48:21.863405 Final RX Vref Byte 1 = 61 to rank1==
7923 06:48:21.867058 Dram Type= 6, Freq= 0, CH_0, rank 0
7924 06:48:21.873369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7925 06:48:21.873464 ==
7926 06:48:21.873529 DQS Delay:
7927 06:48:21.876799 DQS0 = 0, DQS1 = 0
7928 06:48:21.876881 DQM Delay:
7929 06:48:21.876946 DQM0 = 128, DQM1 = 123
7930 06:48:21.879768 DQ Delay:
7931 06:48:21.883504 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7932 06:48:21.886594 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7933 06:48:21.890727 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7934 06:48:21.893272 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =128
7935 06:48:21.893393
7936 06:48:21.893491
7937 06:48:21.893618
7938 06:48:21.896736 [DramC_TX_OE_Calibration] TA2
7939 06:48:21.900215 Original DQ_B0 (3 6) =30, OEN = 27
7940 06:48:21.903536 Original DQ_B1 (3 6) =30, OEN = 27
7941 06:48:21.906756 24, 0x0, End_B0=24 End_B1=24
7942 06:48:21.909390 25, 0x0, End_B0=25 End_B1=25
7943 06:48:21.909473 26, 0x0, End_B0=26 End_B1=26
7944 06:48:21.912916 27, 0x0, End_B0=27 End_B1=27
7945 06:48:21.916054 28, 0x0, End_B0=28 End_B1=28
7946 06:48:21.919535 29, 0x0, End_B0=29 End_B1=29
7947 06:48:21.919618 30, 0x0, End_B0=30 End_B1=30
7948 06:48:21.922590 31, 0x4141, End_B0=30 End_B1=30
7949 06:48:21.926085 Byte0 end_step=30 best_step=27
7950 06:48:21.929281 Byte1 end_step=30 best_step=27
7951 06:48:21.932687 Byte0 TX OE(2T, 0.5T) = (3, 3)
7952 06:48:21.936199 Byte1 TX OE(2T, 0.5T) = (3, 3)
7953 06:48:21.936280
7954 06:48:21.936404
7955 06:48:21.942795 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7956 06:48:21.946051 CH0 RK0: MR19=303, MR18=1916
7957 06:48:21.952358 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7958 06:48:21.952440
7959 06:48:21.955543 ----->DramcWriteLeveling(PI) begin...
7960 06:48:21.955626 ==
7961 06:48:21.958908 Dram Type= 6, Freq= 0, CH_0, rank 1
7962 06:48:21.962057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 06:48:21.962139 ==
7964 06:48:21.965729 Write leveling (Byte 0): 36 => 36
7965 06:48:21.969053 Write leveling (Byte 1): 25 => 25
7966 06:48:21.971984 DramcWriteLeveling(PI) end<-----
7967 06:48:21.972088
7968 06:48:21.972180 ==
7969 06:48:21.975510 Dram Type= 6, Freq= 0, CH_0, rank 1
7970 06:48:21.982602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 06:48:21.982684 ==
7972 06:48:21.982749 [Gating] SW mode calibration
7973 06:48:21.991978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7974 06:48:21.995321 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7975 06:48:22.001871 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7976 06:48:22.005249 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 06:48:22.007995 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7978 06:48:22.015318 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7979 06:48:22.018221 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7980 06:48:22.021565 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7981 06:48:22.028002 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7982 06:48:22.031285 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7983 06:48:22.034668 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 06:48:22.041218 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7985 06:48:22.044627 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7986 06:48:22.047748 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 1)
7987 06:48:22.054105 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7988 06:48:22.057467 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
7989 06:48:22.060744 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 06:48:22.067057 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 06:48:22.070979 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 06:48:22.073962 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7993 06:48:22.080387 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7994 06:48:22.083739 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7995 06:48:22.086989 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
7996 06:48:22.093870 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7997 06:48:22.097494 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 06:48:22.100104 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 06:48:22.106906 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 06:48:22.110011 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 06:48:22.113406 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8002 06:48:22.120021 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8003 06:48:22.123725 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8004 06:48:22.127049 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8005 06:48:22.133430 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 06:48:22.136930 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 06:48:22.140061 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 06:48:22.146418 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 06:48:22.149912 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 06:48:22.153411 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 06:48:22.160026 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 06:48:22.162916 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 06:48:22.166344 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 06:48:22.172944 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 06:48:22.176321 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 06:48:22.179313 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 06:48:22.185728 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8018 06:48:22.189314 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8019 06:48:22.192659 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8020 06:48:22.195962 Total UI for P1: 0, mck2ui 16
8021 06:48:22.199061 best dqsien dly found for B0: ( 1, 9, 10)
8022 06:48:22.205574 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8023 06:48:22.208844 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8024 06:48:22.212203 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 06:48:22.215508 Total UI for P1: 0, mck2ui 16
8026 06:48:22.218488 best dqsien dly found for B1: ( 1, 9, 20)
8027 06:48:22.222309 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8028 06:48:22.225783 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8029 06:48:22.225864
8030 06:48:22.232141 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8031 06:48:22.235316 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8032 06:48:22.238946 [Gating] SW calibration Done
8033 06:48:22.239053 ==
8034 06:48:22.241922 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 06:48:22.244980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 06:48:22.245062 ==
8037 06:48:22.245125 RX Vref Scan: 0
8038 06:48:22.248196
8039 06:48:22.248276 RX Vref 0 -> 0, step: 1
8040 06:48:22.248340
8041 06:48:22.251758 RX Delay 0 -> 252, step: 8
8042 06:48:22.255146 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8043 06:48:22.258433 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8044 06:48:22.264953 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8045 06:48:22.268111 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8046 06:48:22.271592 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8047 06:48:22.274873 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8048 06:48:22.277735 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8049 06:48:22.284802 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8050 06:48:22.288051 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8051 06:48:22.291316 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8052 06:48:22.294986 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8053 06:48:22.301310 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8054 06:48:22.304690 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8055 06:48:22.307446 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8056 06:48:22.310683 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8057 06:48:22.314073 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8058 06:48:22.317475 ==
8059 06:48:22.320672 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 06:48:22.324045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 06:48:22.324127 ==
8062 06:48:22.324192 DQS Delay:
8063 06:48:22.327483 DQS0 = 0, DQS1 = 0
8064 06:48:22.327568 DQM Delay:
8065 06:48:22.330674 DQM0 = 132, DQM1 = 127
8066 06:48:22.330756 DQ Delay:
8067 06:48:22.333762 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8068 06:48:22.337143 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8069 06:48:22.340347 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8070 06:48:22.343884 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8071 06:48:22.343980
8072 06:48:22.344044
8073 06:48:22.347391 ==
8074 06:48:22.347474 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 06:48:22.353790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 06:48:22.353872 ==
8077 06:48:22.353937
8078 06:48:22.353998
8079 06:48:22.356819 TX Vref Scan disable
8080 06:48:22.356900 == TX Byte 0 ==
8081 06:48:22.360213 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8082 06:48:22.367262 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8083 06:48:22.367372 == TX Byte 1 ==
8084 06:48:22.373601 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8085 06:48:22.376426 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8086 06:48:22.376508 ==
8087 06:48:22.379998 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 06:48:22.382943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 06:48:22.383025 ==
8090 06:48:22.399136
8091 06:48:22.402080 TX Vref early break, caculate TX vref
8092 06:48:22.405378 TX Vref=16, minBit 2, minWin=23, winSum=380
8093 06:48:22.408838 TX Vref=18, minBit 1, minWin=23, winSum=387
8094 06:48:22.412476 TX Vref=20, minBit 4, minWin=24, winSum=393
8095 06:48:22.415602 TX Vref=22, minBit 1, minWin=25, winSum=406
8096 06:48:22.418831 TX Vref=24, minBit 1, minWin=25, winSum=409
8097 06:48:22.425492 TX Vref=26, minBit 3, minWin=25, winSum=411
8098 06:48:22.428502 TX Vref=28, minBit 7, minWin=25, winSum=416
8099 06:48:22.432035 TX Vref=30, minBit 1, minWin=25, winSum=412
8100 06:48:22.434904 TX Vref=32, minBit 8, minWin=24, winSum=403
8101 06:48:22.438325 TX Vref=34, minBit 0, minWin=24, winSum=395
8102 06:48:22.444888 TX Vref=36, minBit 0, minWin=24, winSum=387
8103 06:48:22.448313 [TxChooseVref] Worse bit 7, Min win 25, Win sum 416, Final Vref 28
8104 06:48:22.448396
8105 06:48:22.451769 Final TX Range 0 Vref 28
8106 06:48:22.451884
8107 06:48:22.451948 ==
8108 06:48:22.455050 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 06:48:22.457832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 06:48:22.461540 ==
8111 06:48:22.461621
8112 06:48:22.461686
8113 06:48:22.461745 TX Vref Scan disable
8114 06:48:22.468434 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8115 06:48:22.468546 == TX Byte 0 ==
8116 06:48:22.471821 u2DelayCellOfst[0]=10 cells (3 PI)
8117 06:48:22.474822 u2DelayCellOfst[1]=14 cells (4 PI)
8118 06:48:22.478108 u2DelayCellOfst[2]=7 cells (2 PI)
8119 06:48:22.481593 u2DelayCellOfst[3]=7 cells (2 PI)
8120 06:48:22.484463 u2DelayCellOfst[4]=3 cells (1 PI)
8121 06:48:22.488222 u2DelayCellOfst[5]=0 cells (0 PI)
8122 06:48:22.491238 u2DelayCellOfst[6]=14 cells (4 PI)
8123 06:48:22.494622 u2DelayCellOfst[7]=14 cells (4 PI)
8124 06:48:22.497883 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8125 06:48:22.501270 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8126 06:48:22.504445 == TX Byte 1 ==
8127 06:48:22.507714 u2DelayCellOfst[8]=3 cells (1 PI)
8128 06:48:22.510945 u2DelayCellOfst[9]=0 cells (0 PI)
8129 06:48:22.514252 u2DelayCellOfst[10]=7 cells (2 PI)
8130 06:48:22.517597 u2DelayCellOfst[11]=3 cells (1 PI)
8131 06:48:22.520963 u2DelayCellOfst[12]=10 cells (3 PI)
8132 06:48:22.524331 u2DelayCellOfst[13]=14 cells (4 PI)
8133 06:48:22.524424 u2DelayCellOfst[14]=14 cells (4 PI)
8134 06:48:22.527426 u2DelayCellOfst[15]=14 cells (4 PI)
8135 06:48:22.534186 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8136 06:48:22.537676 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8137 06:48:22.540770 DramC Write-DBI on
8138 06:48:22.540851 ==
8139 06:48:22.544378 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 06:48:22.547761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 06:48:22.547844 ==
8142 06:48:22.547908
8143 06:48:22.547967
8144 06:48:22.550907 TX Vref Scan disable
8145 06:48:22.550989 == TX Byte 0 ==
8146 06:48:22.557365 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8147 06:48:22.557462 == TX Byte 1 ==
8148 06:48:22.560815 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8149 06:48:22.564038 DramC Write-DBI off
8150 06:48:22.564119
8151 06:48:22.564214 [DATLAT]
8152 06:48:22.567007 Freq=1600, CH0 RK1
8153 06:48:22.567089
8154 06:48:22.567153 DATLAT Default: 0xf
8155 06:48:22.570329 0, 0xFFFF, sum = 0
8156 06:48:22.574092 1, 0xFFFF, sum = 0
8157 06:48:22.574175 2, 0xFFFF, sum = 0
8158 06:48:22.577212 3, 0xFFFF, sum = 0
8159 06:48:22.577314 4, 0xFFFF, sum = 0
8160 06:48:22.580425 5, 0xFFFF, sum = 0
8161 06:48:22.580546 6, 0xFFFF, sum = 0
8162 06:48:22.583913 7, 0xFFFF, sum = 0
8163 06:48:22.583996 8, 0xFFFF, sum = 0
8164 06:48:22.587225 9, 0xFFFF, sum = 0
8165 06:48:22.587323 10, 0xFFFF, sum = 0
8166 06:48:22.590372 11, 0xFFFF, sum = 0
8167 06:48:22.590455 12, 0xFFFF, sum = 0
8168 06:48:22.593510 13, 0xFFFF, sum = 0
8169 06:48:22.593624 14, 0x0, sum = 1
8170 06:48:22.596734 15, 0x0, sum = 2
8171 06:48:22.596817 16, 0x0, sum = 3
8172 06:48:22.600090 17, 0x0, sum = 4
8173 06:48:22.600200 best_step = 15
8174 06:48:22.600299
8175 06:48:22.600376 ==
8176 06:48:22.603569 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 06:48:22.609927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 06:48:22.610011 ==
8179 06:48:22.610075 RX Vref Scan: 0
8180 06:48:22.610135
8181 06:48:22.613378 RX Vref 0 -> 0, step: 1
8182 06:48:22.613460
8183 06:48:22.616519 RX Delay 11 -> 252, step: 4
8184 06:48:22.620332 iDelay=187, Bit 0, Center 126 (79 ~ 174) 96
8185 06:48:22.623004 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8186 06:48:22.626428 iDelay=187, Bit 2, Center 124 (71 ~ 178) 108
8187 06:48:22.633111 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8188 06:48:22.636230 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8189 06:48:22.639944 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8190 06:48:22.643084 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8191 06:48:22.646267 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8192 06:48:22.653026 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8193 06:48:22.656155 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8194 06:48:22.659132 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8195 06:48:22.662430 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8196 06:48:22.669308 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8197 06:48:22.672919 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8198 06:48:22.676069 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8199 06:48:22.679227 iDelay=187, Bit 15, Center 130 (79 ~ 182) 104
8200 06:48:22.679345 ==
8201 06:48:22.682300 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 06:48:22.688969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 06:48:22.689051 ==
8204 06:48:22.689116 DQS Delay:
8205 06:48:22.692629 DQS0 = 0, DQS1 = 0
8206 06:48:22.692710 DQM Delay:
8207 06:48:22.692775 DQM0 = 128, DQM1 = 123
8208 06:48:22.695716 DQ Delay:
8209 06:48:22.699142 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8210 06:48:22.702033 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8211 06:48:22.705653 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8212 06:48:22.708554 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8213 06:48:22.708636
8214 06:48:22.708700
8215 06:48:22.708760
8216 06:48:22.711878 [DramC_TX_OE_Calibration] TA2
8217 06:48:22.715307 Original DQ_B0 (3 6) =30, OEN = 27
8218 06:48:22.718896 Original DQ_B1 (3 6) =30, OEN = 27
8219 06:48:22.722187 24, 0x0, End_B0=24 End_B1=24
8220 06:48:22.725162 25, 0x0, End_B0=25 End_B1=25
8221 06:48:22.725245 26, 0x0, End_B0=26 End_B1=26
8222 06:48:22.729028 27, 0x0, End_B0=27 End_B1=27
8223 06:48:22.732322 28, 0x0, End_B0=28 End_B1=28
8224 06:48:22.735424 29, 0x0, End_B0=29 End_B1=29
8225 06:48:22.735507 30, 0x0, End_B0=30 End_B1=30
8226 06:48:22.738513 31, 0x4141, End_B0=30 End_B1=30
8227 06:48:22.742027 Byte0 end_step=30 best_step=27
8228 06:48:22.745070 Byte1 end_step=30 best_step=27
8229 06:48:22.748611 Byte0 TX OE(2T, 0.5T) = (3, 3)
8230 06:48:22.751857 Byte1 TX OE(2T, 0.5T) = (3, 3)
8231 06:48:22.751969
8232 06:48:22.752033
8233 06:48:22.758642 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8234 06:48:22.761770 CH0 RK1: MR19=303, MR18=1412
8235 06:48:22.768442 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8236 06:48:22.771529 [RxdqsGatingPostProcess] freq 1600
8237 06:48:22.777783 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8238 06:48:22.777865 best DQS0 dly(2T, 0.5T) = (1, 1)
8239 06:48:22.781256 best DQS1 dly(2T, 0.5T) = (1, 1)
8240 06:48:22.784594 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8241 06:48:22.788008 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8242 06:48:22.791072 best DQS0 dly(2T, 0.5T) = (1, 1)
8243 06:48:22.794442 best DQS1 dly(2T, 0.5T) = (1, 1)
8244 06:48:22.797929 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8245 06:48:22.800856 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8246 06:48:22.804269 Pre-setting of DQS Precalculation
8247 06:48:22.807662 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8248 06:48:22.811063 ==
8249 06:48:22.811176 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 06:48:22.817911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 06:48:22.817995 ==
8252 06:48:22.820924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8253 06:48:22.827605 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8254 06:48:22.830324 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8255 06:48:22.837130 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8256 06:48:22.845527 [CA 0] Center 42 (12~72) winsize 61
8257 06:48:22.848788 [CA 1] Center 42 (12~72) winsize 61
8258 06:48:22.851995 [CA 2] Center 38 (9~67) winsize 59
8259 06:48:22.855749 [CA 3] Center 37 (8~66) winsize 59
8260 06:48:22.858217 [CA 4] Center 38 (8~68) winsize 61
8261 06:48:22.862604 [CA 5] Center 36 (6~66) winsize 61
8262 06:48:22.862686
8263 06:48:22.865306 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8264 06:48:22.865388
8265 06:48:22.868343 [CATrainingPosCal] consider 1 rank data
8266 06:48:22.871803 u2DelayCellTimex100 = 275/100 ps
8267 06:48:22.875235 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8268 06:48:22.881534 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8269 06:48:22.884840 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8270 06:48:22.888401 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8271 06:48:22.892030 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8272 06:48:22.895387 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8273 06:48:22.895489
8274 06:48:22.897963 CA PerBit enable=1, Macro0, CA PI delay=36
8275 06:48:22.898045
8276 06:48:22.901159 [CBTSetCACLKResult] CA Dly = 36
8277 06:48:22.904660 CS Dly: 8 (0~39)
8278 06:48:22.907979 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8279 06:48:22.911005 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8280 06:48:22.911087 ==
8281 06:48:22.914506 Dram Type= 6, Freq= 0, CH_1, rank 1
8282 06:48:22.921487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 06:48:22.921570 ==
8284 06:48:22.924614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 06:48:22.930982 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 06:48:22.934185 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 06:48:22.941032 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 06:48:22.948332 [CA 0] Center 41 (12~71) winsize 60
8289 06:48:22.951826 [CA 1] Center 42 (13~71) winsize 59
8290 06:48:22.955147 [CA 2] Center 37 (8~67) winsize 60
8291 06:48:22.958437 [CA 3] Center 36 (7~65) winsize 59
8292 06:48:22.961753 [CA 4] Center 37 (7~67) winsize 61
8293 06:48:22.964936 [CA 5] Center 36 (7~65) winsize 59
8294 06:48:22.965014
8295 06:48:22.968119 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8296 06:48:22.968200
8297 06:48:22.971898 [CATrainingPosCal] consider 2 rank data
8298 06:48:22.974978 u2DelayCellTimex100 = 275/100 ps
8299 06:48:22.981442 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8300 06:48:22.984602 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8301 06:48:22.987918 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8302 06:48:22.991420 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8303 06:48:22.994438 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8304 06:48:22.998205 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8305 06:48:22.998312
8306 06:48:23.001312 CA PerBit enable=1, Macro0, CA PI delay=36
8307 06:48:23.001425
8308 06:48:23.004687 [CBTSetCACLKResult] CA Dly = 36
8309 06:48:23.008048 CS Dly: 9 (0~42)
8310 06:48:23.011430 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 06:48:23.014419 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 06:48:23.014505
8313 06:48:23.017976 ----->DramcWriteLeveling(PI) begin...
8314 06:48:23.018090 ==
8315 06:48:23.021119 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 06:48:23.027598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 06:48:23.027704 ==
8318 06:48:23.031047 Write leveling (Byte 0): 26 => 26
8319 06:48:23.033969 Write leveling (Byte 1): 27 => 27
8320 06:48:23.034054 DramcWriteLeveling(PI) end<-----
8321 06:48:23.034119
8322 06:48:23.037290 ==
8323 06:48:23.041194 Dram Type= 6, Freq= 0, CH_1, rank 0
8324 06:48:23.044048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 06:48:23.044162 ==
8326 06:48:23.047053 [Gating] SW mode calibration
8327 06:48:23.053714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8328 06:48:23.057518 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8329 06:48:23.063518 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 06:48:23.067236 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 06:48:23.070086 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8332 06:48:23.076793 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8333 06:48:23.080789 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 06:48:23.086419 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 06:48:23.090102 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 06:48:23.093425 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 06:48:23.100058 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 06:48:23.103287 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 06:48:23.106533 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8340 06:48:23.112838 1 5 12 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
8341 06:48:23.116101 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 06:48:23.119372 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 06:48:23.126569 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 06:48:23.129544 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 06:48:23.132791 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 06:48:23.139309 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 06:48:23.142716 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8348 06:48:23.145548 1 6 12 | B1->B0 | 3434 4444 | 0 1 | (0 0) (0 0)
8349 06:48:23.152380 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 06:48:23.155530 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 06:48:23.158801 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 06:48:23.165679 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 06:48:23.168996 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 06:48:23.172552 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 06:48:23.178495 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8356 06:48:23.181796 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8357 06:48:23.185611 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8358 06:48:23.191957 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 06:48:23.195786 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 06:48:23.198962 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 06:48:23.205087 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 06:48:23.208469 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 06:48:23.211914 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 06:48:23.218521 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 06:48:23.221758 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 06:48:23.225170 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 06:48:23.231863 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 06:48:23.235085 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 06:48:23.238432 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 06:48:23.244807 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 06:48:23.247815 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 06:48:23.250947 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8373 06:48:23.257763 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 06:48:23.257851 Total UI for P1: 0, mck2ui 16
8375 06:48:23.264510 best dqsien dly found for B0: ( 1, 9, 12)
8376 06:48:23.264587 Total UI for P1: 0, mck2ui 16
8377 06:48:23.270786 best dqsien dly found for B1: ( 1, 9, 12)
8378 06:48:23.274495 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8379 06:48:23.277657 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8380 06:48:23.277729
8381 06:48:23.280644 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8382 06:48:23.284510 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8383 06:48:23.287773 [Gating] SW calibration Done
8384 06:48:23.287854 ==
8385 06:48:23.291200 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 06:48:23.294181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 06:48:23.294267 ==
8388 06:48:23.297239 RX Vref Scan: 0
8389 06:48:23.297318
8390 06:48:23.297380 RX Vref 0 -> 0, step: 1
8391 06:48:23.297438
8392 06:48:23.300697 RX Delay 0 -> 252, step: 8
8393 06:48:23.304191 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8394 06:48:23.310608 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8395 06:48:23.314055 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8396 06:48:23.317120 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8397 06:48:23.320723 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8398 06:48:23.323848 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8399 06:48:23.330489 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8400 06:48:23.333687 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8401 06:48:23.336919 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8402 06:48:23.340243 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8403 06:48:23.346620 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8404 06:48:23.350013 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8405 06:48:23.353207 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8406 06:48:23.356720 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8407 06:48:23.360179 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8408 06:48:23.366248 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8409 06:48:23.366324 ==
8410 06:48:23.369595 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 06:48:23.373153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 06:48:23.373235 ==
8413 06:48:23.373299 DQS Delay:
8414 06:48:23.376240 DQS0 = 0, DQS1 = 0
8415 06:48:23.376321 DQM Delay:
8416 06:48:23.379565 DQM0 = 134, DQM1 = 130
8417 06:48:23.379646 DQ Delay:
8418 06:48:23.382626 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8419 06:48:23.385898 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8420 06:48:23.389147 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =123
8421 06:48:23.396116 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8422 06:48:23.396199
8423 06:48:23.396262
8424 06:48:23.396321 ==
8425 06:48:23.399224 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 06:48:23.402527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 06:48:23.402605 ==
8428 06:48:23.402669
8429 06:48:23.402728
8430 06:48:23.405680 TX Vref Scan disable
8431 06:48:23.405754 == TX Byte 0 ==
8432 06:48:23.412330 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8433 06:48:23.415566 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8434 06:48:23.415642 == TX Byte 1 ==
8435 06:48:23.422512 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8436 06:48:23.425490 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8437 06:48:23.425563 ==
8438 06:48:23.428859 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 06:48:23.432203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 06:48:23.432277 ==
8441 06:48:23.447649
8442 06:48:23.450019 TX Vref early break, caculate TX vref
8443 06:48:23.453382 TX Vref=16, minBit 8, minWin=21, winSum=366
8444 06:48:23.457301 TX Vref=18, minBit 1, minWin=23, winSum=381
8445 06:48:23.460444 TX Vref=20, minBit 3, minWin=23, winSum=384
8446 06:48:23.463398 TX Vref=22, minBit 8, minWin=23, winSum=394
8447 06:48:23.467228 TX Vref=24, minBit 9, minWin=24, winSum=406
8448 06:48:23.473452 TX Vref=26, minBit 8, minWin=24, winSum=408
8449 06:48:23.476635 TX Vref=28, minBit 6, minWin=25, winSum=416
8450 06:48:23.479838 TX Vref=30, minBit 0, minWin=25, winSum=415
8451 06:48:23.483266 TX Vref=32, minBit 0, minWin=24, winSum=405
8452 06:48:23.486586 TX Vref=34, minBit 11, minWin=23, winSum=398
8453 06:48:23.493798 TX Vref=36, minBit 9, minWin=22, winSum=388
8454 06:48:23.496542 [TxChooseVref] Worse bit 6, Min win 25, Win sum 416, Final Vref 28
8455 06:48:23.496625
8456 06:48:23.499741 Final TX Range 0 Vref 28
8457 06:48:23.499836
8458 06:48:23.499927 ==
8459 06:48:23.503496 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 06:48:23.506498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 06:48:23.509515 ==
8462 06:48:23.509597
8463 06:48:23.509661
8464 06:48:23.509720 TX Vref Scan disable
8465 06:48:23.516615 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8466 06:48:23.516697 == TX Byte 0 ==
8467 06:48:23.519680 u2DelayCellOfst[0]=14 cells (4 PI)
8468 06:48:23.523151 u2DelayCellOfst[1]=10 cells (3 PI)
8469 06:48:23.526254 u2DelayCellOfst[2]=0 cells (0 PI)
8470 06:48:23.529582 u2DelayCellOfst[3]=3 cells (1 PI)
8471 06:48:23.532553 u2DelayCellOfst[4]=10 cells (3 PI)
8472 06:48:23.536298 u2DelayCellOfst[5]=17 cells (5 PI)
8473 06:48:23.539338 u2DelayCellOfst[6]=14 cells (4 PI)
8474 06:48:23.542669 u2DelayCellOfst[7]=7 cells (2 PI)
8475 06:48:23.545960 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8476 06:48:23.549003 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8477 06:48:23.552684 == TX Byte 1 ==
8478 06:48:23.556173 u2DelayCellOfst[8]=0 cells (0 PI)
8479 06:48:23.559468 u2DelayCellOfst[9]=3 cells (1 PI)
8480 06:48:23.562821 u2DelayCellOfst[10]=10 cells (3 PI)
8481 06:48:23.565564 u2DelayCellOfst[11]=7 cells (2 PI)
8482 06:48:23.569031 u2DelayCellOfst[12]=14 cells (4 PI)
8483 06:48:23.572301 u2DelayCellOfst[13]=14 cells (4 PI)
8484 06:48:23.572382 u2DelayCellOfst[14]=17 cells (5 PI)
8485 06:48:23.575759 u2DelayCellOfst[15]=17 cells (5 PI)
8486 06:48:23.582605 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8487 06:48:23.585766 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8488 06:48:23.589015 DramC Write-DBI on
8489 06:48:23.589096 ==
8490 06:48:23.592546 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 06:48:23.595176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 06:48:23.595259 ==
8493 06:48:23.595346
8494 06:48:23.595433
8495 06:48:23.598714 TX Vref Scan disable
8496 06:48:23.598796 == TX Byte 0 ==
8497 06:48:23.605227 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8498 06:48:23.605310 == TX Byte 1 ==
8499 06:48:23.608786 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8500 06:48:23.611997 DramC Write-DBI off
8501 06:48:23.612078
8502 06:48:23.612142 [DATLAT]
8503 06:48:23.615343 Freq=1600, CH1 RK0
8504 06:48:23.615469
8505 06:48:23.615533 DATLAT Default: 0xf
8506 06:48:23.618992 0, 0xFFFF, sum = 0
8507 06:48:23.619074 1, 0xFFFF, sum = 0
8508 06:48:23.621785 2, 0xFFFF, sum = 0
8509 06:48:23.624923 3, 0xFFFF, sum = 0
8510 06:48:23.625006 4, 0xFFFF, sum = 0
8511 06:48:23.628371 5, 0xFFFF, sum = 0
8512 06:48:23.628454 6, 0xFFFF, sum = 0
8513 06:48:23.631806 7, 0xFFFF, sum = 0
8514 06:48:23.631889 8, 0xFFFF, sum = 0
8515 06:48:23.635199 9, 0xFFFF, sum = 0
8516 06:48:23.635308 10, 0xFFFF, sum = 0
8517 06:48:23.638463 11, 0xFFFF, sum = 0
8518 06:48:23.638562 12, 0xFFFF, sum = 0
8519 06:48:23.642104 13, 0xFFFF, sum = 0
8520 06:48:23.642186 14, 0x0, sum = 1
8521 06:48:23.644755 15, 0x0, sum = 2
8522 06:48:23.644838 16, 0x0, sum = 3
8523 06:48:23.648185 17, 0x0, sum = 4
8524 06:48:23.648296 best_step = 15
8525 06:48:23.648360
8526 06:48:23.648419 ==
8527 06:48:23.651485 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 06:48:23.657938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 06:48:23.658020 ==
8530 06:48:23.658084 RX Vref Scan: 1
8531 06:48:23.658144
8532 06:48:23.661525 Set Vref Range= 24 -> 127
8533 06:48:23.661605
8534 06:48:23.664862 RX Vref 24 -> 127, step: 1
8535 06:48:23.664943
8536 06:48:23.665006 RX Delay 11 -> 252, step: 4
8537 06:48:23.667739
8538 06:48:23.667819 Set Vref, RX VrefLevel [Byte0]: 24
8539 06:48:23.671006 [Byte1]: 24
8540 06:48:23.675600
8541 06:48:23.675681 Set Vref, RX VrefLevel [Byte0]: 25
8542 06:48:23.678719 [Byte1]: 25
8543 06:48:23.683052
8544 06:48:23.683132 Set Vref, RX VrefLevel [Byte0]: 26
8545 06:48:23.686261 [Byte1]: 26
8546 06:48:23.690787
8547 06:48:23.690867 Set Vref, RX VrefLevel [Byte0]: 27
8548 06:48:23.694048 [Byte1]: 27
8549 06:48:23.698175
8550 06:48:23.698256 Set Vref, RX VrefLevel [Byte0]: 28
8551 06:48:23.701606 [Byte1]: 28
8552 06:48:23.705887
8553 06:48:23.705969 Set Vref, RX VrefLevel [Byte0]: 29
8554 06:48:23.709498 [Byte1]: 29
8555 06:48:23.713739
8556 06:48:23.713820 Set Vref, RX VrefLevel [Byte0]: 30
8557 06:48:23.716950 [Byte1]: 30
8558 06:48:23.721275
8559 06:48:23.721356 Set Vref, RX VrefLevel [Byte0]: 31
8560 06:48:23.724822 [Byte1]: 31
8561 06:48:23.729031
8562 06:48:23.729112 Set Vref, RX VrefLevel [Byte0]: 32
8563 06:48:23.731982 [Byte1]: 32
8564 06:48:23.736374
8565 06:48:23.736454 Set Vref, RX VrefLevel [Byte0]: 33
8566 06:48:23.739710 [Byte1]: 33
8567 06:48:23.743995
8568 06:48:23.744076 Set Vref, RX VrefLevel [Byte0]: 34
8569 06:48:23.747259 [Byte1]: 34
8570 06:48:23.751558
8571 06:48:23.751638 Set Vref, RX VrefLevel [Byte0]: 35
8572 06:48:23.754637 [Byte1]: 35
8573 06:48:23.759720
8574 06:48:23.759816 Set Vref, RX VrefLevel [Byte0]: 36
8575 06:48:23.762418 [Byte1]: 36
8576 06:48:23.767626
8577 06:48:23.767706 Set Vref, RX VrefLevel [Byte0]: 37
8578 06:48:23.770027 [Byte1]: 37
8579 06:48:23.774228
8580 06:48:23.774309 Set Vref, RX VrefLevel [Byte0]: 38
8581 06:48:23.777698 [Byte1]: 38
8582 06:48:23.782034
8583 06:48:23.782115 Set Vref, RX VrefLevel [Byte0]: 39
8584 06:48:23.785747 [Byte1]: 39
8585 06:48:23.789772
8586 06:48:23.789852 Set Vref, RX VrefLevel [Byte0]: 40
8587 06:48:23.792773 [Byte1]: 40
8588 06:48:23.797234
8589 06:48:23.797362 Set Vref, RX VrefLevel [Byte0]: 41
8590 06:48:23.800673 [Byte1]: 41
8591 06:48:23.804897
8592 06:48:23.804978 Set Vref, RX VrefLevel [Byte0]: 42
8593 06:48:23.808546 [Byte1]: 42
8594 06:48:23.812990
8595 06:48:23.813072 Set Vref, RX VrefLevel [Byte0]: 43
8596 06:48:23.815492 [Byte1]: 43
8597 06:48:23.819832
8598 06:48:23.819914 Set Vref, RX VrefLevel [Byte0]: 44
8599 06:48:23.823639 [Byte1]: 44
8600 06:48:23.827559
8601 06:48:23.827641 Set Vref, RX VrefLevel [Byte0]: 45
8602 06:48:23.830739 [Byte1]: 45
8603 06:48:23.835453
8604 06:48:23.835535 Set Vref, RX VrefLevel [Byte0]: 46
8605 06:48:23.838381 [Byte1]: 46
8606 06:48:23.842832
8607 06:48:23.842913 Set Vref, RX VrefLevel [Byte0]: 47
8608 06:48:23.846088 [Byte1]: 47
8609 06:48:23.850780
8610 06:48:23.850861 Set Vref, RX VrefLevel [Byte0]: 48
8611 06:48:23.853560 [Byte1]: 48
8612 06:48:23.857930
8613 06:48:23.858013 Set Vref, RX VrefLevel [Byte0]: 49
8614 06:48:23.861510 [Byte1]: 49
8615 06:48:23.865897
8616 06:48:23.865972 Set Vref, RX VrefLevel [Byte0]: 50
8617 06:48:23.869360 [Byte1]: 50
8618 06:48:23.873383
8619 06:48:23.873464 Set Vref, RX VrefLevel [Byte0]: 51
8620 06:48:23.876775 [Byte1]: 51
8621 06:48:23.881321
8622 06:48:23.881402 Set Vref, RX VrefLevel [Byte0]: 52
8623 06:48:23.884200 [Byte1]: 52
8624 06:48:23.888834
8625 06:48:23.888915 Set Vref, RX VrefLevel [Byte0]: 53
8626 06:48:23.891770 [Byte1]: 53
8627 06:48:23.896230
8628 06:48:23.896311 Set Vref, RX VrefLevel [Byte0]: 54
8629 06:48:23.900080 [Byte1]: 54
8630 06:48:23.903873
8631 06:48:23.903954 Set Vref, RX VrefLevel [Byte0]: 55
8632 06:48:23.907026 [Byte1]: 55
8633 06:48:23.911777
8634 06:48:23.911884 Set Vref, RX VrefLevel [Byte0]: 56
8635 06:48:23.914896 [Byte1]: 56
8636 06:48:23.919483
8637 06:48:23.919564 Set Vref, RX VrefLevel [Byte0]: 57
8638 06:48:23.922500 [Byte1]: 57
8639 06:48:23.927254
8640 06:48:23.927370 Set Vref, RX VrefLevel [Byte0]: 58
8641 06:48:23.929845 [Byte1]: 58
8642 06:48:23.934337
8643 06:48:23.934418 Set Vref, RX VrefLevel [Byte0]: 59
8644 06:48:23.937570 [Byte1]: 59
8645 06:48:23.941870
8646 06:48:23.941951 Set Vref, RX VrefLevel [Byte0]: 60
8647 06:48:23.945373 [Byte1]: 60
8648 06:48:23.949666
8649 06:48:23.949747 Set Vref, RX VrefLevel [Byte0]: 61
8650 06:48:23.953017 [Byte1]: 61
8651 06:48:23.957051
8652 06:48:23.957132 Set Vref, RX VrefLevel [Byte0]: 62
8653 06:48:23.960590 [Byte1]: 62
8654 06:48:23.964635
8655 06:48:23.964716 Set Vref, RX VrefLevel [Byte0]: 63
8656 06:48:23.967794 [Byte1]: 63
8657 06:48:23.972259
8658 06:48:23.972340 Set Vref, RX VrefLevel [Byte0]: 64
8659 06:48:23.975687 [Byte1]: 64
8660 06:48:23.980223
8661 06:48:23.980304 Set Vref, RX VrefLevel [Byte0]: 65
8662 06:48:23.983478 [Byte1]: 65
8663 06:48:23.987518
8664 06:48:23.987631 Set Vref, RX VrefLevel [Byte0]: 66
8665 06:48:23.991091 [Byte1]: 66
8666 06:48:23.994835
8667 06:48:23.994921 Set Vref, RX VrefLevel [Byte0]: 67
8668 06:48:23.998645 [Byte1]: 67
8669 06:48:24.002589
8670 06:48:24.002670 Set Vref, RX VrefLevel [Byte0]: 68
8671 06:48:24.006000 [Byte1]: 68
8672 06:48:24.010633
8673 06:48:24.010715 Set Vref, RX VrefLevel [Byte0]: 69
8674 06:48:24.013887 [Byte1]: 69
8675 06:48:24.018003
8676 06:48:24.018079 Set Vref, RX VrefLevel [Byte0]: 70
8677 06:48:24.021284 [Byte1]: 70
8678 06:48:24.025930
8679 06:48:24.026006 Set Vref, RX VrefLevel [Byte0]: 71
8680 06:48:24.028863 [Byte1]: 71
8681 06:48:24.033309
8682 06:48:24.033384 Set Vref, RX VrefLevel [Byte0]: 72
8683 06:48:24.036740 [Byte1]: 72
8684 06:48:24.040935
8685 06:48:24.041006 Set Vref, RX VrefLevel [Byte0]: 73
8686 06:48:24.044227 [Byte1]: 73
8687 06:48:24.048666
8688 06:48:24.048761 Final RX Vref Byte 0 = 61 to rank0
8689 06:48:24.051992 Final RX Vref Byte 1 = 55 to rank0
8690 06:48:24.054967 Final RX Vref Byte 0 = 61 to rank1
8691 06:48:24.058531 Final RX Vref Byte 1 = 55 to rank1==
8692 06:48:24.061358 Dram Type= 6, Freq= 0, CH_1, rank 0
8693 06:48:24.068218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8694 06:48:24.068301 ==
8695 06:48:24.068366 DQS Delay:
8696 06:48:24.071564 DQS0 = 0, DQS1 = 0
8697 06:48:24.071662 DQM Delay:
8698 06:48:24.071757 DQM0 = 132, DQM1 = 128
8699 06:48:24.074872 DQ Delay:
8700 06:48:24.078187 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =130
8701 06:48:24.081064 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8702 06:48:24.084383 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =122
8703 06:48:24.087884 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =140
8704 06:48:24.087961
8705 06:48:24.088024
8706 06:48:24.088083
8707 06:48:24.090993 [DramC_TX_OE_Calibration] TA2
8708 06:48:24.094130 Original DQ_B0 (3 6) =30, OEN = 27
8709 06:48:24.097610 Original DQ_B1 (3 6) =30, OEN = 27
8710 06:48:24.101200 24, 0x0, End_B0=24 End_B1=24
8711 06:48:24.104082 25, 0x0, End_B0=25 End_B1=25
8712 06:48:24.104165 26, 0x0, End_B0=26 End_B1=26
8713 06:48:24.107149 27, 0x0, End_B0=27 End_B1=27
8714 06:48:24.110577 28, 0x0, End_B0=28 End_B1=28
8715 06:48:24.114029 29, 0x0, End_B0=29 End_B1=29
8716 06:48:24.117248 30, 0x0, End_B0=30 End_B1=30
8717 06:48:24.117348 31, 0x5151, End_B0=30 End_B1=30
8718 06:48:24.121002 Byte0 end_step=30 best_step=27
8719 06:48:24.124242 Byte1 end_step=30 best_step=27
8720 06:48:24.127343 Byte0 TX OE(2T, 0.5T) = (3, 3)
8721 06:48:24.130670 Byte1 TX OE(2T, 0.5T) = (3, 3)
8722 06:48:24.130756
8723 06:48:24.130820
8724 06:48:24.137243 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8725 06:48:24.140807 CH1 RK0: MR19=303, MR18=F19
8726 06:48:24.146622 CH1_RK0: MR19=0x303, MR18=0xF19, DQSOSC=397, MR23=63, INC=23, DEC=15
8727 06:48:24.146720
8728 06:48:24.149972 ----->DramcWriteLeveling(PI) begin...
8729 06:48:24.150072 ==
8730 06:48:24.153894 Dram Type= 6, Freq= 0, CH_1, rank 1
8731 06:48:24.157119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 06:48:24.157218 ==
8733 06:48:24.160240 Write leveling (Byte 0): 25 => 25
8734 06:48:24.163507 Write leveling (Byte 1): 27 => 27
8735 06:48:24.167498 DramcWriteLeveling(PI) end<-----
8736 06:48:24.167571
8737 06:48:24.167631 ==
8738 06:48:24.170102 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 06:48:24.176408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 06:48:24.176490 ==
8741 06:48:24.176555 [Gating] SW mode calibration
8742 06:48:24.186371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8743 06:48:24.189574 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8744 06:48:24.196444 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 06:48:24.199750 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 06:48:24.202943 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8747 06:48:24.209563 1 4 12 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
8748 06:48:24.212850 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 06:48:24.216222 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 06:48:24.223034 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 06:48:24.225795 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 06:48:24.228914 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 06:48:24.235695 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8754 06:48:24.238679 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8755 06:48:24.242253 1 5 12 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8756 06:48:24.248981 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 06:48:24.251857 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 06:48:24.255285 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 06:48:24.262378 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 06:48:24.264988 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 06:48:24.268330 1 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8762 06:48:24.275158 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8763 06:48:24.278595 1 6 12 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8764 06:48:24.281515 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 06:48:24.288425 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 06:48:24.291280 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 06:48:24.294659 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 06:48:24.301394 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 06:48:24.305159 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8770 06:48:24.307996 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8771 06:48:24.315167 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8772 06:48:24.318247 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8773 06:48:24.321212 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 06:48:24.328086 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 06:48:24.331288 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 06:48:24.334290 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 06:48:24.341038 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 06:48:24.344451 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 06:48:24.347865 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 06:48:24.354556 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 06:48:24.357867 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 06:48:24.360991 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 06:48:24.367210 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 06:48:24.371269 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 06:48:24.374388 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8786 06:48:24.380621 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8787 06:48:24.383974 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8788 06:48:24.386989 Total UI for P1: 0, mck2ui 16
8789 06:48:24.390422 best dqsien dly found for B0: ( 1, 9, 6)
8790 06:48:24.393922 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8791 06:48:24.400664 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 06:48:24.400747 Total UI for P1: 0, mck2ui 16
8793 06:48:24.403631 best dqsien dly found for B1: ( 1, 9, 14)
8794 06:48:24.410554 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8795 06:48:24.413298 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8796 06:48:24.413380
8797 06:48:24.416724 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8798 06:48:24.420004 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8799 06:48:24.423242 [Gating] SW calibration Done
8800 06:48:24.423349 ==
8801 06:48:24.426629 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 06:48:24.429703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 06:48:24.429788 ==
8804 06:48:24.433188 RX Vref Scan: 0
8805 06:48:24.433271
8806 06:48:24.433356 RX Vref 0 -> 0, step: 1
8807 06:48:24.433436
8808 06:48:24.436743 RX Delay 0 -> 252, step: 8
8809 06:48:24.440217 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8810 06:48:24.446797 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8811 06:48:24.450052 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8812 06:48:24.453110 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8813 06:48:24.456400 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8814 06:48:24.459636 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8815 06:48:24.466792 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8816 06:48:24.469518 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8817 06:48:24.472627 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8818 06:48:24.476017 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8819 06:48:24.479567 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8820 06:48:24.486362 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8821 06:48:24.489243 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8822 06:48:24.493150 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8823 06:48:24.496173 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8824 06:48:24.502585 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8825 06:48:24.502672 ==
8826 06:48:24.505761 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 06:48:24.509166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 06:48:24.509251 ==
8829 06:48:24.509337 DQS Delay:
8830 06:48:24.512420 DQS0 = 0, DQS1 = 0
8831 06:48:24.512504 DQM Delay:
8832 06:48:24.515915 DQM0 = 133, DQM1 = 130
8833 06:48:24.515999 DQ Delay:
8834 06:48:24.519101 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =127
8835 06:48:24.522300 DQ4 =135, DQ5 =143, DQ6 =139, DQ7 =135
8836 06:48:24.525455 DQ8 =115, DQ9 =115, DQ10 =135, DQ11 =123
8837 06:48:24.528858 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8838 06:48:24.531938
8839 06:48:24.532018
8840 06:48:24.532082 ==
8841 06:48:24.535489 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 06:48:24.538750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 06:48:24.538832 ==
8844 06:48:24.538897
8845 06:48:24.539000
8846 06:48:24.542626 TX Vref Scan disable
8847 06:48:24.542707 == TX Byte 0 ==
8848 06:48:24.548816 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8849 06:48:24.551748 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8850 06:48:24.551829 == TX Byte 1 ==
8851 06:48:24.558416 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8852 06:48:24.561365 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8853 06:48:24.561447 ==
8854 06:48:24.564995 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 06:48:24.568530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 06:48:24.568642 ==
8857 06:48:24.583272
8858 06:48:24.586002 TX Vref early break, caculate TX vref
8859 06:48:24.589596 TX Vref=16, minBit 9, minWin=21, winSum=377
8860 06:48:24.592662 TX Vref=18, minBit 9, minWin=22, winSum=387
8861 06:48:24.595907 TX Vref=20, minBit 9, minWin=22, winSum=392
8862 06:48:24.599996 TX Vref=22, minBit 9, minWin=22, winSum=402
8863 06:48:24.602546 TX Vref=24, minBit 9, minWin=23, winSum=406
8864 06:48:24.609640 TX Vref=26, minBit 9, minWin=23, winSum=413
8865 06:48:24.613164 TX Vref=28, minBit 9, minWin=25, winSum=420
8866 06:48:24.616100 TX Vref=30, minBit 8, minWin=24, winSum=416
8867 06:48:24.619465 TX Vref=32, minBit 0, minWin=24, winSum=409
8868 06:48:24.622237 TX Vref=34, minBit 0, minWin=24, winSum=402
8869 06:48:24.628738 TX Vref=36, minBit 8, minWin=23, winSum=397
8870 06:48:24.632407 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8871 06:48:24.632489
8872 06:48:24.635913 Final TX Range 0 Vref 28
8873 06:48:24.635995
8874 06:48:24.636060 ==
8875 06:48:24.638786 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 06:48:24.642116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 06:48:24.645435 ==
8878 06:48:24.645516
8879 06:48:24.645580
8880 06:48:24.645638 TX Vref Scan disable
8881 06:48:24.651894 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8882 06:48:24.652012 == TX Byte 0 ==
8883 06:48:24.655310 u2DelayCellOfst[0]=14 cells (4 PI)
8884 06:48:24.658917 u2DelayCellOfst[1]=10 cells (3 PI)
8885 06:48:24.662109 u2DelayCellOfst[2]=0 cells (0 PI)
8886 06:48:24.665452 u2DelayCellOfst[3]=7 cells (2 PI)
8887 06:48:24.668658 u2DelayCellOfst[4]=7 cells (2 PI)
8888 06:48:24.672017 u2DelayCellOfst[5]=14 cells (4 PI)
8889 06:48:24.675252 u2DelayCellOfst[6]=14 cells (4 PI)
8890 06:48:24.679222 u2DelayCellOfst[7]=3 cells (1 PI)
8891 06:48:24.681654 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8892 06:48:24.685501 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8893 06:48:24.688500 == TX Byte 1 ==
8894 06:48:24.691829 u2DelayCellOfst[8]=0 cells (0 PI)
8895 06:48:24.695015 u2DelayCellOfst[9]=7 cells (2 PI)
8896 06:48:24.698119 u2DelayCellOfst[10]=14 cells (4 PI)
8897 06:48:24.701389 u2DelayCellOfst[11]=7 cells (2 PI)
8898 06:48:24.704777 u2DelayCellOfst[12]=14 cells (4 PI)
8899 06:48:24.707992 u2DelayCellOfst[13]=17 cells (5 PI)
8900 06:48:24.711336 u2DelayCellOfst[14]=21 cells (6 PI)
8901 06:48:24.711439 u2DelayCellOfst[15]=21 cells (6 PI)
8902 06:48:24.718291 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8903 06:48:24.721619 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8904 06:48:24.724952 DramC Write-DBI on
8905 06:48:24.725033 ==
8906 06:48:24.727828 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 06:48:24.731318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 06:48:24.731434 ==
8909 06:48:24.731499
8910 06:48:24.731559
8911 06:48:24.734769 TX Vref Scan disable
8912 06:48:24.734850 == TX Byte 0 ==
8913 06:48:24.741240 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8914 06:48:24.741336 == TX Byte 1 ==
8915 06:48:24.744485 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8916 06:48:24.748230 DramC Write-DBI off
8917 06:48:24.748312
8918 06:48:24.748376 [DATLAT]
8919 06:48:24.751162 Freq=1600, CH1 RK1
8920 06:48:24.751260
8921 06:48:24.751325 DATLAT Default: 0xf
8922 06:48:24.754653 0, 0xFFFF, sum = 0
8923 06:48:24.757298 1, 0xFFFF, sum = 0
8924 06:48:24.757381 2, 0xFFFF, sum = 0
8925 06:48:24.761258 3, 0xFFFF, sum = 0
8926 06:48:24.761340 4, 0xFFFF, sum = 0
8927 06:48:24.763970 5, 0xFFFF, sum = 0
8928 06:48:24.764053 6, 0xFFFF, sum = 0
8929 06:48:24.767585 7, 0xFFFF, sum = 0
8930 06:48:24.767713 8, 0xFFFF, sum = 0
8931 06:48:24.770796 9, 0xFFFF, sum = 0
8932 06:48:24.770879 10, 0xFFFF, sum = 0
8933 06:48:24.774096 11, 0xFFFF, sum = 0
8934 06:48:24.774179 12, 0xFFFF, sum = 0
8935 06:48:24.777183 13, 0xFFFF, sum = 0
8936 06:48:24.777266 14, 0x0, sum = 1
8937 06:48:24.780495 15, 0x0, sum = 2
8938 06:48:24.780577 16, 0x0, sum = 3
8939 06:48:24.783722 17, 0x0, sum = 4
8940 06:48:24.783804 best_step = 15
8941 06:48:24.783868
8942 06:48:24.783927 ==
8943 06:48:24.787212 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 06:48:24.793818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 06:48:24.793901 ==
8946 06:48:24.793966 RX Vref Scan: 0
8947 06:48:24.794025
8948 06:48:24.797539 RX Vref 0 -> 0, step: 1
8949 06:48:24.797621
8950 06:48:24.800538 RX Delay 11 -> 252, step: 4
8951 06:48:24.803559 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
8952 06:48:24.807032 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8953 06:48:24.810118 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8954 06:48:24.816726 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8955 06:48:24.819889 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8956 06:48:24.823230 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8957 06:48:24.826789 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8958 06:48:24.833110 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8959 06:48:24.837067 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8960 06:48:24.839673 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8961 06:48:24.843618 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8962 06:48:24.846671 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8963 06:48:24.853320 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8964 06:48:24.856825 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8965 06:48:24.859812 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8966 06:48:24.862983 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8967 06:48:24.863064 ==
8968 06:48:24.866198 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 06:48:24.872821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 06:48:24.872903 ==
8971 06:48:24.872967 DQS Delay:
8972 06:48:24.876316 DQS0 = 0, DQS1 = 0
8973 06:48:24.876397 DQM Delay:
8974 06:48:24.876461 DQM0 = 131, DQM1 = 127
8975 06:48:24.879583 DQ Delay:
8976 06:48:24.882513 DQ0 =136, DQ1 =130, DQ2 =118, DQ3 =126
8977 06:48:24.886221 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =130
8978 06:48:24.889159 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8979 06:48:24.892629 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
8980 06:48:24.892711
8981 06:48:24.892774
8982 06:48:24.892832
8983 06:48:24.896275 [DramC_TX_OE_Calibration] TA2
8984 06:48:24.899324 Original DQ_B0 (3 6) =30, OEN = 27
8985 06:48:24.902584 Original DQ_B1 (3 6) =30, OEN = 27
8986 06:48:24.905978 24, 0x0, End_B0=24 End_B1=24
8987 06:48:24.909549 25, 0x0, End_B0=25 End_B1=25
8988 06:48:24.909632 26, 0x0, End_B0=26 End_B1=26
8989 06:48:24.912327 27, 0x0, End_B0=27 End_B1=27
8990 06:48:24.915727 28, 0x0, End_B0=28 End_B1=28
8991 06:48:24.919124 29, 0x0, End_B0=29 End_B1=29
8992 06:48:24.919233 30, 0x0, End_B0=30 End_B1=30
8993 06:48:24.922294 31, 0x4141, End_B0=30 End_B1=30
8994 06:48:24.925667 Byte0 end_step=30 best_step=27
8995 06:48:24.928878 Byte1 end_step=30 best_step=27
8996 06:48:24.932184 Byte0 TX OE(2T, 0.5T) = (3, 3)
8997 06:48:24.935723 Byte1 TX OE(2T, 0.5T) = (3, 3)
8998 06:48:24.935805
8999 06:48:24.935868
9000 06:48:24.942087 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9001 06:48:24.945277 CH1 RK1: MR19=303, MR18=111E
9002 06:48:24.952016 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
9003 06:48:24.955512 [RxdqsGatingPostProcess] freq 1600
9004 06:48:24.961886 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9005 06:48:24.961973 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 06:48:24.965033 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 06:48:24.968449 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 06:48:24.971941 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 06:48:24.975085 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 06:48:24.978311 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 06:48:24.981727 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 06:48:24.985008 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 06:48:24.988367 Pre-setting of DQS Precalculation
9014 06:48:24.991519 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9015 06:48:25.001627 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9016 06:48:25.008324 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9017 06:48:25.008408
9018 06:48:25.008473
9019 06:48:25.011441 [Calibration Summary] 3200 Mbps
9020 06:48:25.011524 CH 0, Rank 0
9021 06:48:25.014490 SW Impedance : PASS
9022 06:48:25.014571 DUTY Scan : NO K
9023 06:48:25.017654 ZQ Calibration : PASS
9024 06:48:25.020913 Jitter Meter : NO K
9025 06:48:25.020995 CBT Training : PASS
9026 06:48:25.024106 Write leveling : PASS
9027 06:48:25.027259 RX DQS gating : PASS
9028 06:48:25.027342 RX DQ/DQS(RDDQC) : PASS
9029 06:48:25.030703 TX DQ/DQS : PASS
9030 06:48:25.033890 RX DATLAT : PASS
9031 06:48:25.033972 RX DQ/DQS(Engine): PASS
9032 06:48:25.037729 TX OE : PASS
9033 06:48:25.037804 All Pass.
9034 06:48:25.037866
9035 06:48:25.040721 CH 0, Rank 1
9036 06:48:25.040795 SW Impedance : PASS
9037 06:48:25.044011 DUTY Scan : NO K
9038 06:48:25.047215 ZQ Calibration : PASS
9039 06:48:25.047320 Jitter Meter : NO K
9040 06:48:25.050694 CBT Training : PASS
9041 06:48:25.053771 Write leveling : PASS
9042 06:48:25.053852 RX DQS gating : PASS
9043 06:48:25.057595 RX DQ/DQS(RDDQC) : PASS
9044 06:48:25.060741 TX DQ/DQS : PASS
9045 06:48:25.060822 RX DATLAT : PASS
9046 06:48:25.063857 RX DQ/DQS(Engine): PASS
9047 06:48:25.067345 TX OE : PASS
9048 06:48:25.067450 All Pass.
9049 06:48:25.067514
9050 06:48:25.067574 CH 1, Rank 0
9051 06:48:25.070392 SW Impedance : PASS
9052 06:48:25.074139 DUTY Scan : NO K
9053 06:48:25.074218 ZQ Calibration : PASS
9054 06:48:25.077204 Jitter Meter : NO K
9055 06:48:25.080423 CBT Training : PASS
9056 06:48:25.080495 Write leveling : PASS
9057 06:48:25.083616 RX DQS gating : PASS
9058 06:48:25.087082 RX DQ/DQS(RDDQC) : PASS
9059 06:48:25.087153 TX DQ/DQS : PASS
9060 06:48:25.090305 RX DATLAT : PASS
9061 06:48:25.090387 RX DQ/DQS(Engine): PASS
9062 06:48:25.093805 TX OE : PASS
9063 06:48:25.093887 All Pass.
9064 06:48:25.093951
9065 06:48:25.097301 CH 1, Rank 1
9066 06:48:25.097382 SW Impedance : PASS
9067 06:48:25.099949 DUTY Scan : NO K
9068 06:48:25.103192 ZQ Calibration : PASS
9069 06:48:25.103273 Jitter Meter : NO K
9070 06:48:25.106779 CBT Training : PASS
9071 06:48:25.109959 Write leveling : PASS
9072 06:48:25.110040 RX DQS gating : PASS
9073 06:48:25.113180 RX DQ/DQS(RDDQC) : PASS
9074 06:48:25.116544 TX DQ/DQS : PASS
9075 06:48:25.116625 RX DATLAT : PASS
9076 06:48:25.120006 RX DQ/DQS(Engine): PASS
9077 06:48:25.123507 TX OE : PASS
9078 06:48:25.123588 All Pass.
9079 06:48:25.123653
9080 06:48:25.126290 DramC Write-DBI on
9081 06:48:25.126372 PER_BANK_REFRESH: Hybrid Mode
9082 06:48:25.129362 TX_TRACKING: ON
9083 06:48:25.139290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9084 06:48:25.146451 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9085 06:48:25.152566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 06:48:25.155709 [FAST_K] Save calibration result to emmc
9087 06:48:25.159502 sync common calibartion params.
9088 06:48:25.162349 sync cbt_mode0:1, 1:1
9089 06:48:25.162425 dram_init: ddr_geometry: 2
9090 06:48:25.166129 dram_init: ddr_geometry: 2
9091 06:48:25.168954 dram_init: ddr_geometry: 2
9092 06:48:25.172335 0:dram_rank_size:100000000
9093 06:48:25.172419 1:dram_rank_size:100000000
9094 06:48:25.178839 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9095 06:48:25.182158 DFS_SHUFFLE_HW_MODE: ON
9096 06:48:25.185781 dramc_set_vcore_voltage set vcore to 725000
9097 06:48:25.188742 Read voltage for 1600, 0
9098 06:48:25.188824 Vio18 = 0
9099 06:48:25.188889 Vcore = 725000
9100 06:48:25.192064 Vdram = 0
9101 06:48:25.192146 Vddq = 0
9102 06:48:25.192210 Vmddr = 0
9103 06:48:25.195170 switch to 3200 Mbps bootup
9104 06:48:25.198965 [DramcRunTimeConfig]
9105 06:48:25.199061 PHYPLL
9106 06:48:25.199127 DPM_CONTROL_AFTERK: ON
9107 06:48:25.202001 PER_BANK_REFRESH: ON
9108 06:48:25.205241 REFRESH_OVERHEAD_REDUCTION: ON
9109 06:48:25.205344 CMD_PICG_NEW_MODE: OFF
9110 06:48:25.208799 XRTWTW_NEW_MODE: ON
9111 06:48:25.208877 XRTRTR_NEW_MODE: ON
9112 06:48:25.211753 TX_TRACKING: ON
9113 06:48:25.211835 RDSEL_TRACKING: OFF
9114 06:48:25.215285 DQS Precalculation for DVFS: ON
9115 06:48:25.218493 RX_TRACKING: OFF
9116 06:48:25.218574 HW_GATING DBG: ON
9117 06:48:25.222021 ZQCS_ENABLE_LP4: ON
9118 06:48:25.222102 RX_PICG_NEW_MODE: ON
9119 06:48:25.224795 TX_PICG_NEW_MODE: ON
9120 06:48:25.228277 ENABLE_RX_DCM_DPHY: ON
9121 06:48:25.231778 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9122 06:48:25.231859 DUMMY_READ_FOR_TRACKING: OFF
9123 06:48:25.234629 !!! SPM_CONTROL_AFTERK: OFF
9124 06:48:25.238158 !!! SPM could not control APHY
9125 06:48:25.241305 IMPEDANCE_TRACKING: ON
9126 06:48:25.241386 TEMP_SENSOR: ON
9127 06:48:25.244457 HW_SAVE_FOR_SR: OFF
9128 06:48:25.244538 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9129 06:48:25.251351 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9130 06:48:25.251442 Read ODT Tracking: ON
9131 06:48:25.254826 Refresh Rate DeBounce: ON
9132 06:48:25.257662 DFS_NO_QUEUE_FLUSH: ON
9133 06:48:25.261433 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9134 06:48:25.261514 ENABLE_DFS_RUNTIME_MRW: OFF
9135 06:48:25.264395 DDR_RESERVE_NEW_MODE: ON
9136 06:48:25.267892 MR_CBT_SWITCH_FREQ: ON
9137 06:48:25.267973 =========================
9138 06:48:25.287651 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9139 06:48:25.290939 dram_init: ddr_geometry: 2
9140 06:48:25.309314 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9141 06:48:25.312554 dram_init: dram init end (result: 0)
9142 06:48:25.319064 DRAM-K: Full calibration passed in 24447 msecs
9143 06:48:25.322669 MRC: failed to locate region type 0.
9144 06:48:25.322751 DRAM rank0 size:0x100000000,
9145 06:48:25.325588 DRAM rank1 size=0x100000000
9146 06:48:25.335454 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9147 06:48:25.342199 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9148 06:48:25.348830 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9149 06:48:25.358542 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9150 06:48:25.358638 DRAM rank0 size:0x100000000,
9151 06:48:25.361867 DRAM rank1 size=0x100000000
9152 06:48:25.361948 CBMEM:
9153 06:48:25.365047 IMD: root @ 0xfffff000 254 entries.
9154 06:48:25.368595 IMD: root @ 0xffffec00 62 entries.
9155 06:48:25.372224 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9156 06:48:25.378629 WARNING: RO_VPD is uninitialized or empty.
9157 06:48:25.381462 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9158 06:48:25.389445 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9159 06:48:25.401823 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9160 06:48:25.413227 BS: romstage times (exec / console): total (unknown) / 23968 ms
9161 06:48:25.413310
9162 06:48:25.413379
9163 06:48:25.422981 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9164 06:48:25.426526 ARM64: Exception handlers installed.
9165 06:48:25.429829 ARM64: Testing exception
9166 06:48:25.433352 ARM64: Done test exception
9167 06:48:25.433435 Enumerating buses...
9168 06:48:25.436482 Show all devs... Before device enumeration.
9169 06:48:25.439935 Root Device: enabled 1
9170 06:48:25.442838 CPU_CLUSTER: 0: enabled 1
9171 06:48:25.442947 CPU: 00: enabled 1
9172 06:48:25.446302 Compare with tree...
9173 06:48:25.446384 Root Device: enabled 1
9174 06:48:25.449530 CPU_CLUSTER: 0: enabled 1
9175 06:48:25.452606 CPU: 00: enabled 1
9176 06:48:25.452688 Root Device scanning...
9177 06:48:25.456306 scan_static_bus for Root Device
9178 06:48:25.459434 CPU_CLUSTER: 0 enabled
9179 06:48:25.462798 scan_static_bus for Root Device done
9180 06:48:25.466229 scan_bus: bus Root Device finished in 8 msecs
9181 06:48:25.466311 done
9182 06:48:25.472619 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9183 06:48:25.475988 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9184 06:48:25.482480 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9185 06:48:25.488832 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9186 06:48:25.488915 Allocating resources...
9187 06:48:25.492613 Reading resources...
9188 06:48:25.495478 Root Device read_resources bus 0 link: 0
9189 06:48:25.498992 DRAM rank0 size:0x100000000,
9190 06:48:25.499099 DRAM rank1 size=0x100000000
9191 06:48:25.505239 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9192 06:48:25.505322 CPU: 00 missing read_resources
9193 06:48:25.512061 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9194 06:48:25.515547 Root Device read_resources bus 0 link: 0 done
9195 06:48:25.518985 Done reading resources.
9196 06:48:25.522023 Show resources in subtree (Root Device)...After reading.
9197 06:48:25.525780 Root Device child on link 0 CPU_CLUSTER: 0
9198 06:48:25.528683 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 06:48:25.538761 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 06:48:25.538876 CPU: 00
9201 06:48:25.545400 Root Device assign_resources, bus 0 link: 0
9202 06:48:25.548388 CPU_CLUSTER: 0 missing set_resources
9203 06:48:25.551781 Root Device assign_resources, bus 0 link: 0 done
9204 06:48:25.551864 Done setting resources.
9205 06:48:25.558689 Show resources in subtree (Root Device)...After assigning values.
9206 06:48:25.562236 Root Device child on link 0 CPU_CLUSTER: 0
9207 06:48:25.568147 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 06:48:25.574847 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 06:48:25.578392 CPU: 00
9210 06:48:25.578473 Done allocating resources.
9211 06:48:25.584502 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9212 06:48:25.584584 Enabling resources...
9213 06:48:25.588022 done.
9214 06:48:25.591047 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9215 06:48:25.594654 Initializing devices...
9216 06:48:25.594763 Root Device init
9217 06:48:25.597551 init hardware done!
9218 06:48:25.597632 0x00000018: ctrlr->caps
9219 06:48:25.601064 52.000 MHz: ctrlr->f_max
9220 06:48:25.604043 0.400 MHz: ctrlr->f_min
9221 06:48:25.607311 0x40ff8080: ctrlr->voltages
9222 06:48:25.607435 sclk: 390625
9223 06:48:25.607519 Bus Width = 1
9224 06:48:25.610769 sclk: 390625
9225 06:48:25.610850 Bus Width = 1
9226 06:48:25.614661 Early init status = 3
9227 06:48:25.617602 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9228 06:48:25.621667 in-header: 03 fc 00 00 01 00 00 00
9229 06:48:25.625036 in-data: 00
9230 06:48:25.628319 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9231 06:48:25.633977 in-header: 03 fd 00 00 00 00 00 00
9232 06:48:25.637503 in-data:
9233 06:48:25.640310 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9234 06:48:25.644993 in-header: 03 fc 00 00 01 00 00 00
9235 06:48:25.648363 in-data: 00
9236 06:48:25.651973 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9237 06:48:25.657766 in-header: 03 fd 00 00 00 00 00 00
9238 06:48:25.660333 in-data:
9239 06:48:25.664084 [SSUSB] Setting up USB HOST controller...
9240 06:48:25.667593 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9241 06:48:25.671010 [SSUSB] phy power-on done.
9242 06:48:25.673738 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9243 06:48:25.680557 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9244 06:48:25.684110 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9245 06:48:25.690440 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9246 06:48:25.697014 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9247 06:48:25.703573 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9248 06:48:25.710462 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9249 06:48:25.716786 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9250 06:48:25.719794 SPM: binary array size = 0x9dc
9251 06:48:25.723205 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9252 06:48:25.730244 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9253 06:48:25.736230 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9254 06:48:25.743197 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9255 06:48:25.746543 configure_display: Starting display init
9256 06:48:25.780528 anx7625_power_on_init: Init interface.
9257 06:48:25.784195 anx7625_disable_pd_protocol: Disabled PD feature.
9258 06:48:25.787043 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9259 06:48:25.815284 anx7625_start_dp_work: Secure OCM version=00
9260 06:48:25.818330 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9261 06:48:25.833177 sp_tx_get_edid_block: EDID Block = 1
9262 06:48:25.935724 Extracted contents:
9263 06:48:25.938797 header: 00 ff ff ff ff ff ff 00
9264 06:48:25.942412 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9265 06:48:25.945601 version: 01 04
9266 06:48:25.949183 basic params: 95 1f 11 78 0a
9267 06:48:25.952142 chroma info: 76 90 94 55 54 90 27 21 50 54
9268 06:48:25.955256 established: 00 00 00
9269 06:48:25.962046 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9270 06:48:25.965658 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9271 06:48:25.971853 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9272 06:48:25.978526 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9273 06:48:25.985148 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9274 06:48:25.988111 extensions: 00
9275 06:48:25.988192 checksum: fb
9276 06:48:25.988256
9277 06:48:25.995075 Manufacturer: IVO Model 57d Serial Number 0
9278 06:48:25.995157 Made week 0 of 2020
9279 06:48:25.997980 EDID version: 1.4
9280 06:48:25.998070 Digital display
9281 06:48:26.001716 6 bits per primary color channel
9282 06:48:26.001799 DisplayPort interface
9283 06:48:26.004954 Maximum image size: 31 cm x 17 cm
9284 06:48:26.007993 Gamma: 220%
9285 06:48:26.008074 Check DPMS levels
9286 06:48:26.014957 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9287 06:48:26.018080 First detailed timing is preferred timing
9288 06:48:26.018162 Established timings supported:
9289 06:48:26.021608 Standard timings supported:
9290 06:48:26.024515 Detailed timings
9291 06:48:26.028195 Hex of detail: 383680a07038204018303c0035ae10000019
9292 06:48:26.034724 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9293 06:48:26.037606 0780 0798 07c8 0820 hborder 0
9294 06:48:26.040962 0438 043b 0447 0458 vborder 0
9295 06:48:26.044490 -hsync -vsync
9296 06:48:26.044571 Did detailed timing
9297 06:48:26.051031 Hex of detail: 000000000000000000000000000000000000
9298 06:48:26.054164 Manufacturer-specified data, tag 0
9299 06:48:26.057672 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9300 06:48:26.061225 ASCII string: InfoVision
9301 06:48:26.064209 Hex of detail: 000000fe00523134304e574635205248200a
9302 06:48:26.067221 ASCII string: R140NWF5 RH
9303 06:48:26.067302 Checksum
9304 06:48:26.070583 Checksum: 0xfb (valid)
9305 06:48:26.074097 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9306 06:48:26.077309 DSI data_rate: 832800000 bps
9307 06:48:26.084022 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9308 06:48:26.087510 anx7625_parse_edid: pixelclock(138800).
9309 06:48:26.090503 hactive(1920), hsync(48), hfp(24), hbp(88)
9310 06:48:26.093873 vactive(1080), vsync(12), vfp(3), vbp(17)
9311 06:48:26.097386 anx7625_dsi_config: config dsi.
9312 06:48:26.103683 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9313 06:48:26.117968 anx7625_dsi_config: success to config DSI
9314 06:48:26.120992 anx7625_dp_start: MIPI phy setup OK.
9315 06:48:26.124636 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9316 06:48:26.127299 mtk_ddp_mode_set invalid vrefresh 60
9317 06:48:26.131078 main_disp_path_setup
9318 06:48:26.131158 ovl_layer_smi_id_en
9319 06:48:26.133963 ovl_layer_smi_id_en
9320 06:48:26.134043 ccorr_config
9321 06:48:26.134105 aal_config
9322 06:48:26.137335 gamma_config
9323 06:48:26.137415 postmask_config
9324 06:48:26.140526 dither_config
9325 06:48:26.144374 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9326 06:48:26.150640 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9327 06:48:26.154081 Root Device init finished in 555 msecs
9328 06:48:26.157358 CPU_CLUSTER: 0 init
9329 06:48:26.163775 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9330 06:48:26.170411 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9331 06:48:26.170492 APU_MBOX 0x190000b0 = 0x10001
9332 06:48:26.173800 APU_MBOX 0x190001b0 = 0x10001
9333 06:48:26.176794 APU_MBOX 0x190005b0 = 0x10001
9334 06:48:26.180649 APU_MBOX 0x190006b0 = 0x10001
9335 06:48:26.186629 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9336 06:48:26.196558 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9337 06:48:26.209028 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9338 06:48:26.215669 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9339 06:48:26.227599 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9340 06:48:26.237004 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9341 06:48:26.239557 CPU_CLUSTER: 0 init finished in 81 msecs
9342 06:48:26.242972 Devices initialized
9343 06:48:26.246458 Show all devs... After init.
9344 06:48:26.246533 Root Device: enabled 1
9345 06:48:26.249400 CPU_CLUSTER: 0: enabled 1
9346 06:48:26.253264 CPU: 00: enabled 1
9347 06:48:26.256142 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9348 06:48:26.259210 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9349 06:48:26.262510 ELOG: NV offset 0x57f000 size 0x1000
9350 06:48:26.269725 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9351 06:48:26.276318 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9352 06:48:26.279402 ELOG: Event(17) added with size 13 at 2024-02-03 06:48:30 UTC
9353 06:48:26.286214 out: cmd=0x121: 03 db 21 01 00 00 00 00
9354 06:48:26.289716 in-header: 03 14 00 00 2c 00 00 00
9355 06:48:26.299289 in-data: 4b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 06:48:26.305708 ELOG: Event(A1) added with size 10 at 2024-02-03 06:48:30 UTC
9357 06:48:26.312251 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9358 06:48:26.318930 ELOG: Event(A0) added with size 9 at 2024-02-03 06:48:30 UTC
9359 06:48:26.322185 elog_add_boot_reason: Logged dev mode boot
9360 06:48:26.328797 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9361 06:48:26.328886 Finalize devices...
9362 06:48:26.332790 Devices finalized
9363 06:48:26.335760 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9364 06:48:26.338868 Writing coreboot table at 0xffe64000
9365 06:48:26.341925 0. 000000000010a000-0000000000113fff: RAMSTAGE
9366 06:48:26.348878 1. 0000000040000000-00000000400fffff: RAM
9367 06:48:26.352228 2. 0000000040100000-000000004032afff: RAMSTAGE
9368 06:48:26.355527 3. 000000004032b000-00000000545fffff: RAM
9369 06:48:26.359205 4. 0000000054600000-000000005465ffff: BL31
9370 06:48:26.362008 5. 0000000054660000-00000000ffe63fff: RAM
9371 06:48:26.368361 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9372 06:48:26.371802 7. 0000000100000000-000000023fffffff: RAM
9373 06:48:26.375266 Passing 5 GPIOs to payload:
9374 06:48:26.378634 NAME | PORT | POLARITY | VALUE
9375 06:48:26.384841 EC in RW | 0x000000aa | low | undefined
9376 06:48:26.388304 EC interrupt | 0x00000005 | low | undefined
9377 06:48:26.391613 TPM interrupt | 0x000000ab | high | undefined
9378 06:48:26.398396 SD card detect | 0x00000011 | high | undefined
9379 06:48:26.401538 speaker enable | 0x00000093 | high | undefined
9380 06:48:26.404752 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9381 06:48:26.409040 in-header: 03 f9 00 00 02 00 00 00
9382 06:48:26.411950 in-data: 02 00
9383 06:48:26.415157 ADC[4]: Raw value=902216 ID=7
9384 06:48:26.418269 ADC[3]: Raw value=213546 ID=1
9385 06:48:26.418352 RAM Code: 0x71
9386 06:48:26.422108 ADC[6]: Raw value=74630 ID=0
9387 06:48:26.425308 ADC[5]: Raw value=213916 ID=1
9388 06:48:26.425418 SKU Code: 0x1
9389 06:48:26.431634 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5ea0
9390 06:48:26.431716 coreboot table: 964 bytes.
9391 06:48:26.434955 IMD ROOT 0. 0xfffff000 0x00001000
9392 06:48:26.438264 IMD SMALL 1. 0xffffe000 0x00001000
9393 06:48:26.441934 RO MCACHE 2. 0xffffc000 0x00001104
9394 06:48:26.444711 CONSOLE 3. 0xfff7c000 0x00080000
9395 06:48:26.448276 FMAP 4. 0xfff7b000 0x00000452
9396 06:48:26.451632 TIME STAMP 5. 0xfff7a000 0x00000910
9397 06:48:26.454652 VBOOT WORK 6. 0xfff66000 0x00014000
9398 06:48:26.457849 RAMOOPS 7. 0xffe66000 0x00100000
9399 06:48:26.461143 COREBOOT 8. 0xffe64000 0x00002000
9400 06:48:26.464523 IMD small region:
9401 06:48:26.467731 IMD ROOT 0. 0xffffec00 0x00000400
9402 06:48:26.471265 VPD 1. 0xffffeb80 0x0000006c
9403 06:48:26.474645 MMC STATUS 2. 0xffffeb60 0x00000004
9404 06:48:26.481212 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9405 06:48:26.481310 Probing TPM: done!
9406 06:48:26.487746 Connected to device vid:did:rid of 1ae0:0028:00
9407 06:48:26.494348 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9408 06:48:26.497944 Initialized TPM device CR50 revision 0
9409 06:48:26.501317 Checking cr50 for pending updates
9410 06:48:26.507095 Reading cr50 TPM mode
9411 06:48:26.515251 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9412 06:48:26.521790 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9413 06:48:26.561768 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9414 06:48:26.565198 Checking segment from ROM address 0x40100000
9415 06:48:26.569039 Checking segment from ROM address 0x4010001c
9416 06:48:26.575676 Loading segment from ROM address 0x40100000
9417 06:48:26.575757 code (compression=0)
9418 06:48:26.585547 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9419 06:48:26.591996 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9420 06:48:26.592098 it's not compressed!
9421 06:48:26.598822 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9422 06:48:26.601932 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9423 06:48:26.622407 Loading segment from ROM address 0x4010001c
9424 06:48:26.622492 Entry Point 0x80000000
9425 06:48:26.625906 Loaded segments
9426 06:48:26.628955 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9427 06:48:26.635670 Jumping to boot code at 0x80000000(0xffe64000)
9428 06:48:26.642603 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9429 06:48:26.648696 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9430 06:48:26.657162 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9431 06:48:26.660555 Checking segment from ROM address 0x40100000
9432 06:48:26.663718 Checking segment from ROM address 0x4010001c
9433 06:48:26.670320 Loading segment from ROM address 0x40100000
9434 06:48:26.670402 code (compression=1)
9435 06:48:26.676433 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9436 06:48:26.686730 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9437 06:48:26.686826 using LZMA
9438 06:48:26.695391 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9439 06:48:26.701962 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9440 06:48:26.705088 Loading segment from ROM address 0x4010001c
9441 06:48:26.705199 Entry Point 0x54601000
9442 06:48:26.708805 Loaded segments
9443 06:48:26.711557 NOTICE: MT8192 bl31_setup
9444 06:48:26.719029 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9445 06:48:26.722507 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9446 06:48:26.725750 WARNING: region 0:
9447 06:48:26.728866 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 06:48:26.728950 WARNING: region 1:
9449 06:48:26.735280 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9450 06:48:26.738742 WARNING: region 2:
9451 06:48:26.741986 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9452 06:48:26.745676 WARNING: region 3:
9453 06:48:26.748875 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 06:48:26.752283 WARNING: region 4:
9455 06:48:26.758774 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9456 06:48:26.758857 WARNING: region 5:
9457 06:48:26.761985 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 06:48:26.765454 WARNING: region 6:
9459 06:48:26.768921 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 06:48:26.772216 WARNING: region 7:
9461 06:48:26.775401 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 06:48:26.781885 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9463 06:48:26.785207 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9464 06:48:26.788178 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9465 06:48:26.795005 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9466 06:48:26.798520 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9467 06:48:26.804686 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9468 06:48:26.808016 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9469 06:48:26.811846 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9470 06:48:26.817994 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9471 06:48:26.821311 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9472 06:48:26.828067 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9473 06:48:26.831415 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9474 06:48:26.834619 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9475 06:48:26.841602 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9476 06:48:26.844529 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9477 06:48:26.847965 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9478 06:48:26.854541 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9479 06:48:26.857606 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9480 06:48:26.864646 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9481 06:48:26.867914 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9482 06:48:26.871358 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9483 06:48:26.877354 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9484 06:48:26.880845 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9485 06:48:26.887455 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9486 06:48:26.891000 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9487 06:48:26.894001 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9488 06:48:26.900758 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9489 06:48:26.904056 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9490 06:48:26.910657 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9491 06:48:26.914082 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9492 06:48:26.917602 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9493 06:48:26.924236 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9494 06:48:26.927777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9495 06:48:26.930844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9496 06:48:26.934513 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9497 06:48:26.941115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9498 06:48:26.944134 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9499 06:48:26.947742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9500 06:48:26.950797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9501 06:48:26.957692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9502 06:48:26.960779 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9503 06:48:26.964466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9504 06:48:26.967237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9505 06:48:26.974748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9506 06:48:26.977118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9507 06:48:26.980823 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9508 06:48:26.987461 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9509 06:48:26.990398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9510 06:48:26.993706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9511 06:48:27.001066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9512 06:48:27.004124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9513 06:48:27.007242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9514 06:48:27.013680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9515 06:48:27.017368 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9516 06:48:27.023877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9517 06:48:27.027639 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9518 06:48:27.033614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9519 06:48:27.037522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9520 06:48:27.043945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9521 06:48:27.046764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9522 06:48:27.050279 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9523 06:48:27.056809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9524 06:48:27.060633 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9525 06:48:27.066676 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9526 06:48:27.070389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9527 06:48:27.076639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9528 06:48:27.080025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9529 06:48:27.086878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9530 06:48:27.090038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9531 06:48:27.093452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9532 06:48:27.099941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9533 06:48:27.103787 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9534 06:48:27.109783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9535 06:48:27.113314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9536 06:48:27.119864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9537 06:48:27.123855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9538 06:48:27.126336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9539 06:48:27.133418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9540 06:48:27.136175 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9541 06:48:27.142997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9542 06:48:27.146257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9543 06:48:27.153272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9544 06:48:27.156277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9545 06:48:27.162908 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9546 06:48:27.166146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9547 06:48:27.170001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9548 06:48:27.176943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9549 06:48:27.179774 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9550 06:48:27.186346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9551 06:48:27.189927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9552 06:48:27.196418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9553 06:48:27.200145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9554 06:48:27.203275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9555 06:48:27.209762 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9556 06:48:27.213314 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9557 06:48:27.220315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9558 06:48:27.223054 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9559 06:48:27.226269 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9560 06:48:27.233491 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9561 06:48:27.236119 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9562 06:48:27.239396 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9563 06:48:27.242630 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9564 06:48:27.249893 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9565 06:48:27.252937 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9566 06:48:27.259437 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9567 06:48:27.263210 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9568 06:48:27.266554 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9569 06:48:27.273032 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9570 06:48:27.275942 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9571 06:48:27.282805 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9572 06:48:27.286472 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9573 06:48:27.289749 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9574 06:48:27.296114 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9575 06:48:27.299510 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9576 06:48:27.305768 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9577 06:48:27.309587 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9578 06:48:27.312886 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9579 06:48:27.319527 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9580 06:48:27.322990 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9581 06:48:27.326253 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9582 06:48:27.329508 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9583 06:48:27.335893 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9584 06:48:27.338964 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9585 06:48:27.342344 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9586 06:48:27.348976 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9587 06:48:27.352445 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9588 06:48:27.356024 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9589 06:48:27.362639 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9590 06:48:27.366428 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9591 06:48:27.372884 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9592 06:48:27.375680 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9593 06:48:27.379143 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9594 06:48:27.386019 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9595 06:48:27.389222 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9596 06:48:27.392291 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9597 06:48:27.398858 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9598 06:48:27.402562 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9599 06:48:27.409199 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9600 06:48:27.412164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9601 06:48:27.415934 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9602 06:48:27.422589 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9603 06:48:27.425883 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9604 06:48:27.432338 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9605 06:48:27.435578 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9606 06:48:27.439064 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9607 06:48:27.445960 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9608 06:48:27.449071 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9609 06:48:27.455687 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9610 06:48:27.458543 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9611 06:48:27.462837 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9612 06:48:27.468651 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9613 06:48:27.472387 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9614 06:48:27.475904 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9615 06:48:27.482171 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9616 06:48:27.485805 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9617 06:48:27.491962 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9618 06:48:27.495652 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9619 06:48:27.499098 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9620 06:48:27.505430 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9621 06:48:27.508970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9622 06:48:27.515289 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9623 06:48:27.518405 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9624 06:48:27.521767 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9625 06:48:27.528390 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9626 06:48:27.531519 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9627 06:48:27.538181 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9628 06:48:27.541763 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9629 06:48:27.544791 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9630 06:48:27.551535 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9631 06:48:27.554981 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9632 06:48:27.561159 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9633 06:48:27.564483 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9634 06:48:27.567727 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9635 06:48:27.574349 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9636 06:48:27.577607 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9637 06:48:27.584331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9638 06:48:27.587790 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9639 06:48:27.591041 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9640 06:48:27.597436 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9641 06:48:27.600724 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9642 06:48:27.607218 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9643 06:48:27.610745 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9644 06:48:27.614059 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9645 06:48:27.620382 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9646 06:48:27.623883 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9647 06:48:27.630351 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9648 06:48:27.633473 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9649 06:48:27.640272 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9650 06:48:27.643306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9651 06:48:27.646960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9652 06:48:27.653193 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9653 06:48:27.656814 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9654 06:48:27.663053 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9655 06:48:27.666490 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9656 06:48:27.673049 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9657 06:48:27.676490 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9658 06:48:27.680018 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9659 06:48:27.686280 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9660 06:48:27.689605 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9661 06:48:27.696228 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9662 06:48:27.699584 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9663 06:48:27.705897 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9664 06:48:27.708978 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9665 06:48:27.712580 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9666 06:48:27.719092 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9667 06:48:27.722394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9668 06:48:27.728996 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9669 06:48:27.732124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9670 06:48:27.739332 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9671 06:48:27.742228 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9672 06:48:27.745909 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9673 06:48:27.752012 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9674 06:48:27.755349 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9675 06:48:27.761943 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9676 06:48:27.765174 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9677 06:48:27.772162 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9678 06:48:27.775256 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9679 06:48:27.778517 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9680 06:48:27.785033 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9681 06:48:27.787955 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9682 06:48:27.794967 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9683 06:48:27.797874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9684 06:48:27.804699 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9685 06:48:27.808385 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9686 06:48:27.811002 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9687 06:48:27.817788 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9688 06:48:27.821231 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9689 06:48:27.828135 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9690 06:48:27.830968 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9691 06:48:27.834087 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9692 06:48:27.840832 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9693 06:48:27.844523 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9694 06:48:27.847706 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9695 06:48:27.851108 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9696 06:48:27.857796 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9697 06:48:27.861144 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9698 06:48:27.864229 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9699 06:48:27.871274 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9700 06:48:27.874390 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9701 06:48:27.877187 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9702 06:48:27.884162 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9703 06:48:27.887787 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9704 06:48:27.894097 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9705 06:48:27.897550 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9706 06:48:27.900474 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9707 06:48:27.907266 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9708 06:48:27.910505 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9709 06:48:27.913612 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9710 06:48:27.920618 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9711 06:48:27.924343 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9712 06:48:27.930418 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9713 06:48:27.934018 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9714 06:48:27.937196 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9715 06:48:27.943550 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9716 06:48:27.946636 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9717 06:48:27.950216 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9718 06:48:27.957028 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9719 06:48:27.960151 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9720 06:48:27.963568 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9721 06:48:27.969886 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9722 06:48:27.973175 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9723 06:48:27.979523 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9724 06:48:27.982984 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9725 06:48:27.986321 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9726 06:48:27.992838 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9727 06:48:27.996204 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9728 06:48:28.002569 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9729 06:48:28.005958 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9730 06:48:28.009386 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9731 06:48:28.015758 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9732 06:48:28.018976 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9733 06:48:28.022575 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9734 06:48:28.025606 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9735 06:48:28.028868 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9736 06:48:28.035793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9737 06:48:28.038696 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9738 06:48:28.042314 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9739 06:48:28.046093 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9740 06:48:28.052438 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9741 06:48:28.055240 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9742 06:48:28.058720 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9743 06:48:28.065183 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9744 06:48:28.068353 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9745 06:48:28.075328 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9746 06:48:28.078647 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9747 06:48:28.081965 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9748 06:48:28.088097 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9749 06:48:28.091726 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9750 06:48:28.097967 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9751 06:48:28.101363 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9752 06:48:28.104789 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9753 06:48:28.111288 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9754 06:48:28.114801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9755 06:48:28.121502 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9756 06:48:28.124441 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9757 06:48:28.130769 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9758 06:48:28.134227 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9759 06:48:28.137706 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9760 06:48:28.144215 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9761 06:48:28.147761 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9762 06:48:28.154407 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9763 06:48:28.157582 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9764 06:48:28.163761 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9765 06:48:28.167331 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9766 06:48:28.170543 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9767 06:48:28.177433 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9768 06:48:28.180733 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9769 06:48:28.187141 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9770 06:48:28.190083 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9771 06:48:28.193565 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9772 06:48:28.200036 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9773 06:48:28.203721 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9774 06:48:28.209953 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9775 06:48:28.213259 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9776 06:48:28.219955 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9777 06:48:28.223852 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9778 06:48:28.226548 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9779 06:48:28.232829 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9780 06:48:28.236765 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9781 06:48:28.243227 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9782 06:48:28.246079 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9783 06:48:28.249415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9784 06:48:28.256479 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9785 06:48:28.259774 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9786 06:48:28.266091 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9787 06:48:28.269458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9788 06:48:28.275849 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9789 06:48:28.279309 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9790 06:48:28.285981 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9791 06:48:28.288870 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9792 06:48:28.292368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9793 06:48:28.299163 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9794 06:48:28.302291 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9795 06:48:28.308948 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9796 06:48:28.312071 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9797 06:48:28.315522 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9798 06:48:28.321960 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9799 06:48:28.325598 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9800 06:48:28.332200 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9801 06:48:28.335474 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9802 06:48:28.338372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9803 06:48:28.345281 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9804 06:48:28.348577 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9805 06:48:28.354748 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9806 06:48:28.358288 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9807 06:48:28.361699 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9808 06:48:28.368298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9809 06:48:28.371788 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9810 06:48:28.378103 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9811 06:48:28.381543 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9812 06:48:28.388217 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9813 06:48:28.390977 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9814 06:48:28.397785 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9815 06:48:28.400985 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9816 06:48:28.404464 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9817 06:48:28.411231 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9818 06:48:28.414262 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9819 06:48:28.420881 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9820 06:48:28.424269 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9821 06:48:28.430656 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9822 06:48:28.434260 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9823 06:48:28.437528 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9824 06:48:28.444714 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9825 06:48:28.447063 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9826 06:48:28.453760 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9827 06:48:28.457127 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9828 06:48:28.463932 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9829 06:48:28.467109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9830 06:48:28.473364 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9831 06:48:28.476685 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9832 06:48:28.480041 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9833 06:48:28.486899 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9834 06:48:28.490384 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9835 06:48:28.496304 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9836 06:48:28.499764 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9837 06:48:28.506669 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9838 06:48:28.509534 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9839 06:48:28.516658 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9840 06:48:28.519514 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9841 06:48:28.522757 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9842 06:48:28.529224 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9843 06:48:28.532884 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9844 06:48:28.539851 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9845 06:48:28.542664 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9846 06:48:28.549196 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9847 06:48:28.552982 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9848 06:48:28.559016 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9849 06:48:28.562241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9850 06:48:28.565839 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9851 06:48:28.572485 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9852 06:48:28.575750 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9853 06:48:28.582611 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9854 06:48:28.585379 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9855 06:48:28.592424 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9856 06:48:28.595439 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9857 06:48:28.602136 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9858 06:48:28.605273 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9859 06:48:28.611636 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9860 06:48:28.615160 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9861 06:48:28.618467 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9862 06:48:28.624911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9863 06:48:28.628102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9864 06:48:28.634988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9865 06:48:28.638162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9866 06:48:28.641623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9867 06:48:28.648311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9868 06:48:28.651596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9869 06:48:28.657800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9870 06:48:28.661138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9871 06:48:28.667765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9872 06:48:28.671052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9873 06:48:28.677731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9874 06:48:28.681303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9875 06:48:28.688092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9876 06:48:28.691123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9877 06:48:28.697743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9878 06:48:28.701007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9879 06:48:28.707516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9880 06:48:28.710769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9881 06:48:28.717531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9882 06:48:28.720820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9883 06:48:28.727199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9884 06:48:28.730340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9885 06:48:28.737003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9886 06:48:28.740318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9887 06:48:28.746612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9888 06:48:28.750227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9889 06:48:28.757050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9890 06:48:28.760181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9891 06:48:28.766757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9892 06:48:28.770216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9893 06:48:28.777281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9894 06:48:28.780286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9895 06:48:28.786968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9896 06:48:28.789964 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9897 06:48:28.792853 INFO: [APUAPC] vio 0
9898 06:48:28.796486 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9899 06:48:28.803080 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9900 06:48:28.806521 INFO: [APUAPC] D0_APC_0: 0x400510
9901 06:48:28.809931 INFO: [APUAPC] D0_APC_1: 0x0
9902 06:48:28.813655 INFO: [APUAPC] D0_APC_2: 0x1540
9903 06:48:28.813769 INFO: [APUAPC] D0_APC_3: 0x0
9904 06:48:28.819691 INFO: [APUAPC] D1_APC_0: 0xffffffff
9905 06:48:28.823020 INFO: [APUAPC] D1_APC_1: 0xffffffff
9906 06:48:28.826313 INFO: [APUAPC] D1_APC_2: 0x3fffff
9907 06:48:28.826395 INFO: [APUAPC] D1_APC_3: 0x0
9908 06:48:28.829719 INFO: [APUAPC] D2_APC_0: 0xffffffff
9909 06:48:28.836337 INFO: [APUAPC] D2_APC_1: 0xffffffff
9910 06:48:28.836419 INFO: [APUAPC] D2_APC_2: 0x3fffff
9911 06:48:28.839228 INFO: [APUAPC] D2_APC_3: 0x0
9912 06:48:28.842506 INFO: [APUAPC] D3_APC_0: 0xffffffff
9913 06:48:28.845794 INFO: [APUAPC] D3_APC_1: 0xffffffff
9914 06:48:28.849044 INFO: [APUAPC] D3_APC_2: 0x3fffff
9915 06:48:28.852446 INFO: [APUAPC] D3_APC_3: 0x0
9916 06:48:28.855694 INFO: [APUAPC] D4_APC_0: 0xffffffff
9917 06:48:28.859299 INFO: [APUAPC] D4_APC_1: 0xffffffff
9918 06:48:28.862654 INFO: [APUAPC] D4_APC_2: 0x3fffff
9919 06:48:28.865529 INFO: [APUAPC] D4_APC_3: 0x0
9920 06:48:28.869176 INFO: [APUAPC] D5_APC_0: 0xffffffff
9921 06:48:28.872371 INFO: [APUAPC] D5_APC_1: 0xffffffff
9922 06:48:28.875935 INFO: [APUAPC] D5_APC_2: 0x3fffff
9923 06:48:28.878844 INFO: [APUAPC] D5_APC_3: 0x0
9924 06:48:28.882042 INFO: [APUAPC] D6_APC_0: 0xffffffff
9925 06:48:28.885434 INFO: [APUAPC] D6_APC_1: 0xffffffff
9926 06:48:28.888790 INFO: [APUAPC] D6_APC_2: 0x3fffff
9927 06:48:28.892083 INFO: [APUAPC] D6_APC_3: 0x0
9928 06:48:28.895502 INFO: [APUAPC] D7_APC_0: 0xffffffff
9929 06:48:28.898649 INFO: [APUAPC] D7_APC_1: 0xffffffff
9930 06:48:28.901712 INFO: [APUAPC] D7_APC_2: 0x3fffff
9931 06:48:28.905256 INFO: [APUAPC] D7_APC_3: 0x0
9932 06:48:28.908439 INFO: [APUAPC] D8_APC_0: 0xffffffff
9933 06:48:28.912051 INFO: [APUAPC] D8_APC_1: 0xffffffff
9934 06:48:28.915112 INFO: [APUAPC] D8_APC_2: 0x3fffff
9935 06:48:28.918315 INFO: [APUAPC] D8_APC_3: 0x0
9936 06:48:28.921506 INFO: [APUAPC] D9_APC_0: 0xffffffff
9937 06:48:28.924742 INFO: [APUAPC] D9_APC_1: 0xffffffff
9938 06:48:28.928076 INFO: [APUAPC] D9_APC_2: 0x3fffff
9939 06:48:28.931335 INFO: [APUAPC] D9_APC_3: 0x0
9940 06:48:28.934752 INFO: [APUAPC] D10_APC_0: 0xffffffff
9941 06:48:28.938056 INFO: [APUAPC] D10_APC_1: 0xffffffff
9942 06:48:28.941460 INFO: [APUAPC] D10_APC_2: 0x3fffff
9943 06:48:28.944850 INFO: [APUAPC] D10_APC_3: 0x0
9944 06:48:28.947795 INFO: [APUAPC] D11_APC_0: 0xffffffff
9945 06:48:28.951146 INFO: [APUAPC] D11_APC_1: 0xffffffff
9946 06:48:28.954596 INFO: [APUAPC] D11_APC_2: 0x3fffff
9947 06:48:28.958006 INFO: [APUAPC] D11_APC_3: 0x0
9948 06:48:28.961390 INFO: [APUAPC] D12_APC_0: 0xffffffff
9949 06:48:28.964283 INFO: [APUAPC] D12_APC_1: 0xffffffff
9950 06:48:28.967669 INFO: [APUAPC] D12_APC_2: 0x3fffff
9951 06:48:28.971136 INFO: [APUAPC] D12_APC_3: 0x0
9952 06:48:28.974139 INFO: [APUAPC] D13_APC_0: 0xffffffff
9953 06:48:28.977252 INFO: [APUAPC] D13_APC_1: 0xffffffff
9954 06:48:28.981074 INFO: [APUAPC] D13_APC_2: 0x3fffff
9955 06:48:28.984350 INFO: [APUAPC] D13_APC_3: 0x0
9956 06:48:28.987641 INFO: [APUAPC] D14_APC_0: 0xffffffff
9957 06:48:28.990769 INFO: [APUAPC] D14_APC_1: 0xffffffff
9958 06:48:28.994038 INFO: [APUAPC] D14_APC_2: 0x3fffff
9959 06:48:28.998090 INFO: [APUAPC] D14_APC_3: 0x0
9960 06:48:29.000551 INFO: [APUAPC] D15_APC_0: 0xffffffff
9961 06:48:29.007156 INFO: [APUAPC] D15_APC_1: 0xffffffff
9962 06:48:29.010527 INFO: [APUAPC] D15_APC_2: 0x3fffff
9963 06:48:29.010608 INFO: [APUAPC] D15_APC_3: 0x0
9964 06:48:29.014058 INFO: [APUAPC] APC_CON: 0x4
9965 06:48:29.016766 INFO: [NOCDAPC] D0_APC_0: 0x0
9966 06:48:29.020681 INFO: [NOCDAPC] D0_APC_1: 0x0
9967 06:48:29.023500 INFO: [NOCDAPC] D1_APC_0: 0x0
9968 06:48:29.026615 INFO: [NOCDAPC] D1_APC_1: 0xfff
9969 06:48:29.029959 INFO: [NOCDAPC] D2_APC_0: 0x0
9970 06:48:29.033257 INFO: [NOCDAPC] D2_APC_1: 0xfff
9971 06:48:29.037017 INFO: [NOCDAPC] D3_APC_0: 0x0
9972 06:48:29.040000 INFO: [NOCDAPC] D3_APC_1: 0xfff
9973 06:48:29.040086 INFO: [NOCDAPC] D4_APC_0: 0x0
9974 06:48:29.043066 INFO: [NOCDAPC] D4_APC_1: 0xfff
9975 06:48:29.046488 INFO: [NOCDAPC] D5_APC_0: 0x0
9976 06:48:29.050044 INFO: [NOCDAPC] D5_APC_1: 0xfff
9977 06:48:29.053263 INFO: [NOCDAPC] D6_APC_0: 0x0
9978 06:48:29.056604 INFO: [NOCDAPC] D6_APC_1: 0xfff
9979 06:48:29.059801 INFO: [NOCDAPC] D7_APC_0: 0x0
9980 06:48:29.063140 INFO: [NOCDAPC] D7_APC_1: 0xfff
9981 06:48:29.066519 INFO: [NOCDAPC] D8_APC_0: 0x0
9982 06:48:29.069844 INFO: [NOCDAPC] D8_APC_1: 0xfff
9983 06:48:29.072804 INFO: [NOCDAPC] D9_APC_0: 0x0
9984 06:48:29.076296 INFO: [NOCDAPC] D9_APC_1: 0xfff
9985 06:48:29.076377 INFO: [NOCDAPC] D10_APC_0: 0x0
9986 06:48:29.079193 INFO: [NOCDAPC] D10_APC_1: 0xfff
9987 06:48:29.082530 INFO: [NOCDAPC] D11_APC_0: 0x0
9988 06:48:29.085888 INFO: [NOCDAPC] D11_APC_1: 0xfff
9989 06:48:29.089355 INFO: [NOCDAPC] D12_APC_0: 0x0
9990 06:48:29.092810 INFO: [NOCDAPC] D12_APC_1: 0xfff
9991 06:48:29.096055 INFO: [NOCDAPC] D13_APC_0: 0x0
9992 06:48:29.099385 INFO: [NOCDAPC] D13_APC_1: 0xfff
9993 06:48:29.102393 INFO: [NOCDAPC] D14_APC_0: 0x0
9994 06:48:29.105973 INFO: [NOCDAPC] D14_APC_1: 0xfff
9995 06:48:29.109684 INFO: [NOCDAPC] D15_APC_0: 0x0
9996 06:48:29.112346 INFO: [NOCDAPC] D15_APC_1: 0xfff
9997 06:48:29.115959 INFO: [NOCDAPC] APC_CON: 0x4
9998 06:48:29.119245 INFO: [APUAPC] set_apusys_apc done
9999 06:48:29.122191 INFO: [DEVAPC] devapc_init done
10000 06:48:29.125470 INFO: GICv3 without legacy support detected.
10001 06:48:29.128644 INFO: ARM GICv3 driver initialized in EL3
10002 06:48:29.131918 INFO: Maximum SPI INTID supported: 639
10003 06:48:29.136157 INFO: BL31: Initializing runtime services
10004 06:48:29.142464 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10005 06:48:29.145174 INFO: SPM: enable CPC mode
10006 06:48:29.152106 INFO: mcdi ready for mcusys-off-idle and system suspend
10007 06:48:29.155467 INFO: BL31: Preparing for EL3 exit to normal world
10008 06:48:29.158849 INFO: Entry point address = 0x80000000
10009 06:48:29.161600 INFO: SPSR = 0x8
10010 06:48:29.166679
10011 06:48:29.166760
10012 06:48:29.166824
10013 06:48:29.170157 Starting depthcharge on Spherion...
10014 06:48:29.170239
10015 06:48:29.170304 Wipe memory regions:
10016 06:48:29.170365
10017 06:48:29.171023 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10018 06:48:29.171123 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10019 06:48:29.171203 Setting prompt string to ['asurada:']
10020 06:48:29.171284 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10021 06:48:29.173676 [0x00000040000000, 0x00000054600000)
10022 06:48:29.295796
10023 06:48:29.295920 [0x00000054660000, 0x00000080000000)
10024 06:48:29.556249
10025 06:48:29.556386 [0x000000821a7280, 0x000000ffe64000)
10026 06:48:30.301213
10027 06:48:30.301348 [0x00000100000000, 0x00000240000000)
10028 06:48:32.191900
10029 06:48:32.194769 Initializing XHCI USB controller at 0x11200000.
10030 06:48:33.232180
10031 06:48:33.236130 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10032 06:48:33.236235
10033 06:48:33.236319
10034 06:48:33.236397
10035 06:48:33.236707 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 06:48:33.337027 asurada: tftpboot 192.168.201.1 12694830/tftp-deploy-m4akf261/kernel/image.itb 12694830/tftp-deploy-m4akf261/kernel/cmdline
10038 06:48:33.337173 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 06:48:33.337287 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10040 06:48:33.341473 tftpboot 192.168.201.1 12694830/tftp-deploy-m4akf261/kernel/image.itp-deploy-m4akf261/kernel/cmdline
10041 06:48:33.341567
10042 06:48:33.341650 Waiting for link
10043 06:48:33.502004
10044 06:48:33.502130 R8152: Initializing
10045 06:48:33.502229
10046 06:48:33.504995 Version 6 (ocp_data = 5c30)
10047 06:48:33.505078
10048 06:48:33.508089 R8152: Done initializing
10049 06:48:33.508208
10050 06:48:33.508316 Adding net device
10051 06:48:35.473683
10052 06:48:35.473830 done.
10053 06:48:35.473932
10054 06:48:35.474012 MAC: 00:24:32:30:7c:7b
10055 06:48:35.474097
10056 06:48:35.476960 Sending DHCP discover... done.
10057 06:48:35.477041
10058 06:48:35.480179 Waiting for reply... done.
10059 06:48:35.480258
10060 06:48:35.483664 Sending DHCP request... done.
10061 06:48:35.483744
10062 06:48:35.483831 Waiting for reply... done.
10063 06:48:35.483909
10064 06:48:35.486794 My ip is 192.168.201.14
10065 06:48:35.486875
10066 06:48:35.490400 The DHCP server ip is 192.168.201.1
10067 06:48:35.490476
10068 06:48:35.493198 TFTP server IP predefined by user: 192.168.201.1
10069 06:48:35.493275
10070 06:48:35.499842 Bootfile predefined by user: 12694830/tftp-deploy-m4akf261/kernel/image.itb
10071 06:48:35.499945
10072 06:48:35.503288 Sending tftp read request... done.
10073 06:48:35.503378
10074 06:48:35.506765 Waiting for the transfer...
10075 06:48:35.506854
10076 06:48:36.045644 00000000 ################################################################
10077 06:48:36.045780
10078 06:48:36.571979 00080000 ################################################################
10079 06:48:36.572112
10080 06:48:37.108223 00100000 ################################################################
10081 06:48:37.108359
10082 06:48:37.649696 00180000 ################################################################
10083 06:48:37.649846
10084 06:48:38.183123 00200000 ################################################################
10085 06:48:38.183257
10086 06:48:38.717896 00280000 ################################################################
10087 06:48:38.718033
10088 06:48:39.248236 00300000 ################################################################
10089 06:48:39.248374
10090 06:48:39.802337 00380000 ################################################################
10091 06:48:39.802471
10092 06:48:40.345616 00400000 ################################################################
10093 06:48:40.345761
10094 06:48:40.884536 00480000 ################################################################
10095 06:48:40.884683
10096 06:48:41.418846 00500000 ################################################################
10097 06:48:41.418998
10098 06:48:41.944636 00580000 ################################################################
10099 06:48:41.944832
10100 06:48:42.471681 00600000 ################################################################
10101 06:48:42.471834
10102 06:48:43.003551 00680000 ################################################################
10103 06:48:43.003698
10104 06:48:43.530896 00700000 ################################################################
10105 06:48:43.531043
10106 06:48:44.075631 00780000 ################################################################
10107 06:48:44.075784
10108 06:48:44.610570 00800000 ################################################################
10109 06:48:44.610753
10110 06:48:45.147942 00880000 ################################################################
10111 06:48:45.148103
10112 06:48:45.679998 00900000 ################################################################
10113 06:48:45.680144
10114 06:48:46.211699 00980000 ################################################################
10115 06:48:46.211847
10116 06:48:46.751319 00a00000 ################################################################
10117 06:48:46.751513
10118 06:48:47.280902 00a80000 ################################################################
10119 06:48:47.281050
10120 06:48:47.819436 00b00000 ################################################################
10121 06:48:47.819593
10122 06:48:48.347660 00b80000 ################################################################
10123 06:48:48.347814
10124 06:48:48.882194 00c00000 ################################################################
10125 06:48:48.882373
10126 06:48:49.412243 00c80000 ################################################################
10127 06:48:49.412399
10128 06:48:49.947058 00d00000 ################################################################
10129 06:48:49.947236
10130 06:48:50.478998 00d80000 ################################################################
10131 06:48:50.479165
10132 06:48:51.011386 00e00000 ################################################################
10133 06:48:51.011587
10134 06:48:51.547092 00e80000 ################################################################
10135 06:48:51.547271
10136 06:48:52.084854 00f00000 ################################################################
10137 06:48:52.085031
10138 06:48:52.619825 00f80000 ################################################################
10139 06:48:52.619968
10140 06:48:53.180038 01000000 ################################################################
10141 06:48:53.180192
10142 06:48:53.730081 01080000 ################################################################
10143 06:48:53.730232
10144 06:48:54.283191 01100000 ################################################################
10145 06:48:54.283329
10146 06:48:54.837416 01180000 ################################################################
10147 06:48:54.837556
10148 06:48:55.384563 01200000 ################################################################
10149 06:48:55.384701
10150 06:48:55.927418 01280000 ################################################################
10151 06:48:55.927553
10152 06:48:56.468422 01300000 ################################################################
10153 06:48:56.468585
10154 06:48:56.998191 01380000 ################################################################
10155 06:48:56.998329
10156 06:48:57.526966 01400000 ################################################################
10157 06:48:57.527120
10158 06:48:58.057043 01480000 ################################################################
10159 06:48:58.057199
10160 06:48:58.586434 01500000 ################################################################
10161 06:48:58.586585
10162 06:48:59.129262 01580000 ################################################################
10163 06:48:59.129395
10164 06:48:59.666900 01600000 ################################################################
10165 06:48:59.667051
10166 06:49:00.215289 01680000 ################################################################
10167 06:49:00.215474
10168 06:49:00.764544 01700000 ################################################################
10169 06:49:00.764693
10170 06:49:01.316522 01780000 ################################################################
10171 06:49:01.316677
10172 06:49:01.910901 01800000 ################################################################
10173 06:49:01.911046
10174 06:49:02.511099 01880000 ################################################################
10175 06:49:02.511255
10176 06:49:03.079891 01900000 ################################################################
10177 06:49:03.080049
10178 06:49:03.679351 01980000 ################################################################
10179 06:49:03.679522
10180 06:49:04.297102 01a00000 ################################################################
10181 06:49:04.297236
10182 06:49:04.906559 01a80000 ################################################################
10183 06:49:04.906692
10184 06:49:05.543513 01b00000 ################################################################
10185 06:49:05.543650
10186 06:49:06.153985 01b80000 ################################################################
10187 06:49:06.154125
10188 06:49:06.753451 01c00000 ################################################################
10189 06:49:06.753624
10190 06:49:07.390989 01c80000 ################################################################
10191 06:49:07.391120
10192 06:49:07.951568 01d00000 ################################################################
10193 06:49:07.951702
10194 06:49:08.511300 01d80000 ################################################################
10195 06:49:08.511496
10196 06:49:09.062382 01e00000 ################################################################
10197 06:49:09.062522
10198 06:49:09.671346 01e80000 ################################################################
10199 06:49:09.672031
10200 06:49:10.339796 01f00000 ################################################################
10201 06:49:10.339949
10202 06:49:10.867384 01f80000 ######################################################## done.
10203 06:49:10.867543
10204 06:49:10.870378 The bootfile was 33486934 bytes long.
10205 06:49:10.870464
10206 06:49:10.873257 Sending tftp read request... done.
10207 06:49:10.873340
10208 06:49:10.873406 Waiting for the transfer...
10209 06:49:10.873489
10210 06:49:10.877168 00000000 # done.
10211 06:49:10.877282
10212 06:49:10.883425 Command line loaded dynamically from TFTP file: 12694830/tftp-deploy-m4akf261/kernel/cmdline
10213 06:49:10.883515
10214 06:49:10.899679 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10215 06:49:10.899764
10216 06:49:10.899830 Loading FIT.
10217 06:49:10.899890
10218 06:49:10.903133 Image ramdisk-1 has 21387037 bytes.
10219 06:49:10.903215
10220 06:49:10.906429 Image fdt-1 has 47278 bytes.
10221 06:49:10.906512
10222 06:49:10.909435 Image kernel-1 has 12050581 bytes.
10223 06:49:10.909518
10224 06:49:10.916323 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10225 06:49:10.916407
10226 06:49:10.935964 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10227 06:49:10.936052
10228 06:49:10.939788 Choosing best match conf-1 for compat google,spherion-rev2.
10229 06:49:10.943922
10230 06:49:10.948847 Connected to device vid:did:rid of 1ae0:0028:00
10231 06:49:10.956790
10232 06:49:10.960411 tpm_get_response: command 0x17b, return code 0x0
10233 06:49:10.960494
10234 06:49:10.963411 ec_init: CrosEC protocol v3 supported (256, 248)
10235 06:49:10.967571
10236 06:49:10.971000 tpm_cleanup: add release locality here.
10237 06:49:10.971083
10238 06:49:10.971148 Shutting down all USB controllers.
10239 06:49:10.974339
10240 06:49:10.974425 Removing current net device
10241 06:49:10.974491
10242 06:49:10.980591 Exiting depthcharge with code 4 at timestamp: 71085051
10243 06:49:10.980674
10244 06:49:10.983867 LZMA decompressing kernel-1 to 0x821a6718
10245 06:49:10.983950
10246 06:49:10.986949 LZMA decompressing kernel-1 to 0x40000000
10247 06:49:12.486401
10248 06:49:12.486567 jumping to kernel
10249 06:49:12.487029 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10250 06:49:12.487175 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10251 06:49:12.487282 Setting prompt string to ['Linux version [0-9]']
10252 06:49:12.487354 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10253 06:49:12.487448 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10254 06:49:12.568619
10255 06:49:12.572085 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10256 06:49:12.575144 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10257 06:49:12.575238 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10258 06:49:12.575310 Setting prompt string to []
10259 06:49:12.575430 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10260 06:49:12.575507 Using line separator: #'\n'#
10261 06:49:12.575566 No login prompt set.
10262 06:49:12.575629 Parsing kernel messages
10263 06:49:12.575685 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10264 06:49:12.575786 [login-action] Waiting for messages, (timeout 00:03:42)
10265 06:49:12.595056 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j96464-arm64-gcc-10-defconfig-arm64-chromebook-9ff9l) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Feb 3 06:30:39 UTC 2024
10266 06:49:12.598402 [ 0.000000] random: crng init done
10267 06:49:12.604554 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10268 06:49:12.607753 [ 0.000000] efi: UEFI not found.
10269 06:49:12.614490 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10270 06:49:12.621263 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10271 06:49:12.630885 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10272 06:49:12.640594 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10273 06:49:12.647299 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10274 06:49:12.654644 [ 0.000000] printk: bootconsole [mtk8250] enabled
10275 06:49:12.660901 [ 0.000000] NUMA: No NUMA configuration found
10276 06:49:12.667781 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10277 06:49:12.670494 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10278 06:49:12.673867 [ 0.000000] Zone ranges:
10279 06:49:12.680383 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10280 06:49:12.684696 [ 0.000000] DMA32 empty
10281 06:49:12.690469 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10282 06:49:12.693734 [ 0.000000] Movable zone start for each node
10283 06:49:12.697469 [ 0.000000] Early memory node ranges
10284 06:49:12.703329 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10285 06:49:12.710360 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10286 06:49:12.716757 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10287 06:49:12.723398 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10288 06:49:12.729755 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10289 06:49:12.736651 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10290 06:49:12.793040 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10291 06:49:12.799348 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10292 06:49:12.806488 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10293 06:49:12.809407 [ 0.000000] psci: probing for conduit method from DT.
10294 06:49:12.815897 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10295 06:49:12.819527 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10296 06:49:12.826245 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10297 06:49:12.828866 [ 0.000000] psci: SMC Calling Convention v1.2
10298 06:49:12.835808 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10299 06:49:12.838844 [ 0.000000] Detected VIPT I-cache on CPU0
10300 06:49:12.845359 [ 0.000000] CPU features: detected: GIC system register CPU interface
10301 06:49:12.852217 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10302 06:49:12.858642 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10303 06:49:12.865389 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10304 06:49:12.875737 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10305 06:49:12.881840 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10306 06:49:12.885163 [ 0.000000] alternatives: applying boot alternatives
10307 06:49:12.891859 [ 0.000000] Fallback order for Node 0: 0
10308 06:49:12.898071 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10309 06:49:12.901644 [ 0.000000] Policy zone: Normal
10310 06:49:12.914936 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10311 06:49:12.925139 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10312 06:49:12.937312 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10313 06:49:12.947578 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10314 06:49:12.953874 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10315 06:49:12.957179 <6>[ 0.000000] software IO TLB: area num 8.
10316 06:49:13.014166 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10317 06:49:13.162812 <6>[ 0.000000] Memory: 7946368K/8385536K available (17984K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 615K bss, 406400K reserved, 32768K cma-reserved)
10318 06:49:13.169800 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10319 06:49:13.176495 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10320 06:49:13.179889 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10321 06:49:13.186052 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10322 06:49:13.192578 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10323 06:49:13.195703 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10324 06:49:13.205644 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10325 06:49:13.212341 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10326 06:49:13.218878 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10327 06:49:13.225640 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10328 06:49:13.228834 <6>[ 0.000000] GICv3: 608 SPIs implemented
10329 06:49:13.232167 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10330 06:49:13.238675 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10331 06:49:13.242024 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10332 06:49:13.248545 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10333 06:49:13.262011 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10334 06:49:13.274836 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10335 06:49:13.281577 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10336 06:49:13.289318 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10337 06:49:13.302351 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10338 06:49:13.309031 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10339 06:49:13.315625 <6>[ 0.009236] Console: colour dummy device 80x25
10340 06:49:13.325889 <6>[ 0.013952] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10341 06:49:13.332483 <6>[ 0.024394] pid_max: default: 32768 minimum: 301
10342 06:49:13.335727 <6>[ 0.029264] LSM: Security Framework initializing
10343 06:49:13.342274 <6>[ 0.034204] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10344 06:49:13.352038 <6>[ 0.042018] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10345 06:49:13.362284 <6>[ 0.051434] cblist_init_generic: Setting adjustable number of callback queues.
10346 06:49:13.365646 <6>[ 0.058878] cblist_init_generic: Setting shift to 3 and lim to 1.
10347 06:49:13.375572 <6>[ 0.065217] cblist_init_generic: Setting adjustable number of callback queues.
10348 06:49:13.381629 <6>[ 0.072644] cblist_init_generic: Setting shift to 3 and lim to 1.
10349 06:49:13.384951 <6>[ 0.079045] rcu: Hierarchical SRCU implementation.
10350 06:49:13.391662 <6>[ 0.084061] rcu: Max phase no-delay instances is 1000.
10351 06:49:13.398836 <6>[ 0.091122] EFI services will not be available.
10352 06:49:13.401839 <6>[ 0.096075] smp: Bringing up secondary CPUs ...
10353 06:49:13.410378 <6>[ 0.101125] Detected VIPT I-cache on CPU1
10354 06:49:13.417175 <6>[ 0.101192] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10355 06:49:13.423375 <6>[ 0.101224] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10356 06:49:13.426439 <6>[ 0.101562] Detected VIPT I-cache on CPU2
10357 06:49:13.436636 <6>[ 0.101613] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10358 06:49:13.443027 <6>[ 0.101630] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10359 06:49:13.446099 <6>[ 0.101886] Detected VIPT I-cache on CPU3
10360 06:49:13.453025 <6>[ 0.101932] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10361 06:49:13.459502 <6>[ 0.101946] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10362 06:49:13.466327 <6>[ 0.102252] CPU features: detected: Spectre-v4
10363 06:49:13.469438 <6>[ 0.102258] CPU features: detected: Spectre-BHB
10364 06:49:13.472551 <6>[ 0.102263] Detected PIPT I-cache on CPU4
10365 06:49:13.479228 <6>[ 0.102321] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10366 06:49:13.485904 <6>[ 0.102337] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10367 06:49:13.492506 <6>[ 0.102631] Detected PIPT I-cache on CPU5
10368 06:49:13.499210 <6>[ 0.102694] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10369 06:49:13.505529 <6>[ 0.102711] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10370 06:49:13.508650 <6>[ 0.102995] Detected PIPT I-cache on CPU6
10371 06:49:13.515531 <6>[ 0.103059] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10372 06:49:13.525247 <6>[ 0.103075] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10373 06:49:13.528803 <6>[ 0.103373] Detected PIPT I-cache on CPU7
10374 06:49:13.535286 <6>[ 0.103436] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10375 06:49:13.541837 <6>[ 0.103453] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10376 06:49:13.545050 <6>[ 0.103499] smp: Brought up 1 node, 8 CPUs
10377 06:49:13.552184 <6>[ 0.244786] SMP: Total of 8 processors activated.
10378 06:49:13.555084 <6>[ 0.249737] CPU features: detected: 32-bit EL0 Support
10379 06:49:13.565478 <6>[ 0.255100] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10380 06:49:13.571458 <6>[ 0.263900] CPU features: detected: Common not Private translations
10381 06:49:13.578242 <6>[ 0.270376] CPU features: detected: CRC32 instructions
10382 06:49:13.584833 <6>[ 0.275727] CPU features: detected: RCpc load-acquire (LDAPR)
10383 06:49:13.588104 <6>[ 0.281688] CPU features: detected: LSE atomic instructions
10384 06:49:13.594804 <6>[ 0.287469] CPU features: detected: Privileged Access Never
10385 06:49:13.601345 <6>[ 0.293284] CPU features: detected: RAS Extension Support
10386 06:49:13.607633 <6>[ 0.298893] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10387 06:49:13.610919 <6>[ 0.306158] CPU: All CPU(s) started at EL2
10388 06:49:13.617617 <6>[ 0.310474] alternatives: applying system-wide alternatives
10389 06:49:13.627805 <6>[ 0.321202] devtmpfs: initialized
10390 06:49:13.643701 <6>[ 0.330344] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10391 06:49:13.650107 <6>[ 0.340302] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10392 06:49:13.656555 <6>[ 0.348516] pinctrl core: initialized pinctrl subsystem
10393 06:49:13.660255 <6>[ 0.355191] DMI not present or invalid.
10394 06:49:13.666768 <6>[ 0.359603] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10395 06:49:13.676352 <6>[ 0.366389] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10396 06:49:13.682857 <6>[ 0.373971] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10397 06:49:13.692674 <6>[ 0.382197] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10398 06:49:13.696489 <6>[ 0.390435] audit: initializing netlink subsys (disabled)
10399 06:49:13.705962 <5>[ 0.396127] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10400 06:49:13.712540 <6>[ 0.396823] thermal_sys: Registered thermal governor 'step_wise'
10401 06:49:13.719627 <6>[ 0.404095] thermal_sys: Registered thermal governor 'power_allocator'
10402 06:49:13.722589 <6>[ 0.410348] cpuidle: using governor menu
10403 06:49:13.729152 <6>[ 0.421307] NET: Registered PF_QIPCRTR protocol family
10404 06:49:13.735613 <6>[ 0.426785] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10405 06:49:13.742715 <6>[ 0.433886] ASID allocator initialised with 32768 entries
10406 06:49:13.745727 <6>[ 0.440445] Serial: AMBA PL011 UART driver
10407 06:49:13.756023 <4>[ 0.449237] Trying to register duplicate clock ID: 134
10408 06:49:13.809741 <6>[ 0.506132] KASLR enabled
10409 06:49:13.823431 <6>[ 0.513836] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10410 06:49:13.830269 <6>[ 0.520845] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10411 06:49:13.836635 <6>[ 0.527330] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10412 06:49:13.843443 <6>[ 0.534334] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10413 06:49:13.850213 <6>[ 0.540822] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10414 06:49:13.856756 <6>[ 0.547826] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10415 06:49:13.863170 <6>[ 0.554315] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10416 06:49:13.869830 <6>[ 0.561320] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10417 06:49:13.873368 <6>[ 0.568784] ACPI: Interpreter disabled.
10418 06:49:13.881900 <6>[ 0.575234] iommu: Default domain type: Translated
10419 06:49:13.888441 <6>[ 0.580346] iommu: DMA domain TLB invalidation policy: strict mode
10420 06:49:13.891499 <5>[ 0.587013] SCSI subsystem initialized
10421 06:49:13.898623 <6>[ 0.591259] usbcore: registered new interface driver usbfs
10422 06:49:13.904872 <6>[ 0.596988] usbcore: registered new interface driver hub
10423 06:49:13.908311 <6>[ 0.602540] usbcore: registered new device driver usb
10424 06:49:13.915249 <6>[ 0.608659] pps_core: LinuxPPS API ver. 1 registered
10425 06:49:13.925085 <6>[ 0.613851] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10426 06:49:13.928923 <6>[ 0.623193] PTP clock support registered
10427 06:49:13.931696 <6>[ 0.627435] EDAC MC: Ver: 3.0.0
10428 06:49:13.938977 <6>[ 0.632628] FPGA manager framework
10429 06:49:13.942594 <6>[ 0.636301] Advanced Linux Sound Architecture Driver Initialized.
10430 06:49:13.946483 <6>[ 0.643061] vgaarb: loaded
10431 06:49:13.953132 <6>[ 0.646195] clocksource: Switched to clocksource arch_sys_counter
10432 06:49:13.959324 <5>[ 0.652641] VFS: Disk quotas dquot_6.6.0
10433 06:49:13.966053 <6>[ 0.656828] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10434 06:49:13.969341 <6>[ 0.664018] pnp: PnP ACPI: disabled
10435 06:49:13.977454 <6>[ 0.670668] NET: Registered PF_INET protocol family
10436 06:49:13.986810 <6>[ 0.676257] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10437 06:49:13.998572 <6>[ 0.688599] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10438 06:49:14.008305 <6>[ 0.697415] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10439 06:49:14.014823 <6>[ 0.705387] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10440 06:49:14.022076 <6>[ 0.714090] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10441 06:49:14.033494 <6>[ 0.723846] TCP: Hash tables configured (established 65536 bind 65536)
10442 06:49:14.040126 <6>[ 0.730716] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10443 06:49:14.047138 <6>[ 0.737915] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10444 06:49:14.053220 <6>[ 0.745620] NET: Registered PF_UNIX/PF_LOCAL protocol family
10445 06:49:14.060083 <6>[ 0.751711] RPC: Registered named UNIX socket transport module.
10446 06:49:14.063585 <6>[ 0.757865] RPC: Registered udp transport module.
10447 06:49:14.070020 <6>[ 0.762800] RPC: Registered tcp transport module.
10448 06:49:14.076556 <6>[ 0.767731] RPC: Registered tcp NFSv4.1 backchannel transport module.
10449 06:49:14.079658 <6>[ 0.774395] PCI: CLS 0 bytes, default 64
10450 06:49:14.083127 <6>[ 0.778735] Unpacking initramfs...
10451 06:49:14.093542 <6>[ 0.782523] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10452 06:49:14.099259 <6>[ 0.791137] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10453 06:49:14.106609 <6>[ 0.799922] kvm [1]: IPA Size Limit: 40 bits
10454 06:49:14.109926 <6>[ 0.804445] kvm [1]: GICv3: no GICV resource entry
10455 06:49:14.116273 <6>[ 0.809468] kvm [1]: disabling GICv2 emulation
10456 06:49:14.122963 <6>[ 0.814151] kvm [1]: GIC system register CPU interface enabled
10457 06:49:14.126362 <6>[ 0.820313] kvm [1]: vgic interrupt IRQ18
10458 06:49:14.132794 <6>[ 0.826264] kvm [1]: VHE mode initialized successfully
10459 06:49:14.139901 <5>[ 0.832592] Initialise system trusted keyrings
10460 06:49:14.146514 <6>[ 0.837359] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10461 06:49:14.153529 <6>[ 0.847311] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10462 06:49:14.160707 <5>[ 0.853700] NFS: Registering the id_resolver key type
10463 06:49:14.163441 <5>[ 0.859001] Key type id_resolver registered
10464 06:49:14.170726 <5>[ 0.863414] Key type id_legacy registered
10465 06:49:14.177661 <6>[ 0.867690] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10466 06:49:14.183457 <6>[ 0.874614] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10467 06:49:14.189967 <6>[ 0.882348] 9p: Installing v9fs 9p2000 file system support
10468 06:49:14.225961 <5>[ 0.919572] Key type asymmetric registered
10469 06:49:14.229266 <5>[ 0.923903] Asymmetric key parser 'x509' registered
10470 06:49:14.239488 <6>[ 0.929045] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10471 06:49:14.242753 <6>[ 0.936660] io scheduler mq-deadline registered
10472 06:49:14.246080 <6>[ 0.941422] io scheduler kyber registered
10473 06:49:14.265043 <6>[ 0.958818] EINJ: ACPI disabled.
10474 06:49:14.297281 <4>[ 0.984341] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10475 06:49:14.307119 <4>[ 0.994995] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10476 06:49:14.322456 <6>[ 1.015933] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10477 06:49:14.330742 <6>[ 1.024140] printk: console [ttyS0] disabled
10478 06:49:14.358262 <6>[ 1.048767] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10479 06:49:14.365363 <6>[ 1.058258] printk: console [ttyS0] enabled
10480 06:49:14.368845 <6>[ 1.058258] printk: console [ttyS0] enabled
10481 06:49:14.375157 <6>[ 1.067153] printk: bootconsole [mtk8250] disabled
10482 06:49:14.378398 <6>[ 1.067153] printk: bootconsole [mtk8250] disabled
10483 06:49:14.385152 <6>[ 1.078429] SuperH (H)SCI(F) driver initialized
10484 06:49:14.388705 <6>[ 1.083699] msm_serial: driver initialized
10485 06:49:14.402456 <6>[ 1.092649] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10486 06:49:14.413267 <6>[ 1.101196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10487 06:49:14.418886 <6>[ 1.109737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10488 06:49:14.428870 <6>[ 1.118367] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10489 06:49:14.439128 <6>[ 1.127073] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10490 06:49:14.445375 <6>[ 1.135786] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10491 06:49:14.455706 <6>[ 1.144327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10492 06:49:14.462188 <6>[ 1.153148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10493 06:49:14.471580 <6>[ 1.161694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10494 06:49:14.484050 <6>[ 1.177371] loop: module loaded
10495 06:49:14.490371 <6>[ 1.183329] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10496 06:49:14.512946 <4>[ 1.206508] mtk-pmic-keys: Failed to locate of_node [id: -1]
10497 06:49:14.519580 <6>[ 1.213300] megasas: 07.719.03.00-rc1
10498 06:49:14.529427 <6>[ 1.222860] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10499 06:49:14.536383 <6>[ 1.229634] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10500 06:49:14.552968 <6>[ 1.246377] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10501 06:49:14.609559 <6>[ 1.296262] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10502 06:49:14.990250 <6>[ 1.683968] Freeing initrd memory: 20884K
10503 06:49:15.006106 <6>[ 1.699803] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10504 06:49:15.017445 <6>[ 1.710809] tun: Universal TUN/TAP device driver, 1.6
10505 06:49:15.020377 <6>[ 1.716873] thunder_xcv, ver 1.0
10506 06:49:15.023849 <6>[ 1.720377] thunder_bgx, ver 1.0
10507 06:49:15.027093 <6>[ 1.723872] nicpf, ver 1.0
10508 06:49:15.037848 <6>[ 1.727879] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10509 06:49:15.040947 <6>[ 1.735356] hns3: Copyright (c) 2017 Huawei Corporation.
10510 06:49:15.047329 <6>[ 1.740948] hclge is initializing
10511 06:49:15.051058 <6>[ 1.744529] e1000: Intel(R) PRO/1000 Network Driver
10512 06:49:15.057687 <6>[ 1.749657] e1000: Copyright (c) 1999-2006 Intel Corporation.
10513 06:49:15.061069 <6>[ 1.755672] e1000e: Intel(R) PRO/1000 Network Driver
10514 06:49:15.067302 <6>[ 1.760887] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10515 06:49:15.074121 <6>[ 1.767073] igb: Intel(R) Gigabit Ethernet Network Driver
10516 06:49:15.080796 <6>[ 1.772723] igb: Copyright (c) 2007-2014 Intel Corporation.
10517 06:49:15.087348 <6>[ 1.778559] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10518 06:49:15.094485 <6>[ 1.785076] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10519 06:49:15.097646 <6>[ 1.791556] sky2: driver version 1.30
10520 06:49:15.104281 <6>[ 1.796552] VFIO - User Level meta-driver version: 0.3
10521 06:49:15.111029 <6>[ 1.804788] usbcore: registered new interface driver usb-storage
10522 06:49:15.117945 <6>[ 1.811236] usbcore: registered new device driver onboard-usb-hub
10523 06:49:15.126892 <6>[ 1.820397] mt6397-rtc mt6359-rtc: registered as rtc0
10524 06:49:15.136621 <6>[ 1.825868] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-03T06:49:18 UTC (1706942958)
10525 06:49:15.139939 <6>[ 1.835455] i2c_dev: i2c /dev entries driver
10526 06:49:15.157168 <6>[ 1.847117] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10527 06:49:15.176780 <6>[ 1.870106] cpu cpu0: EM: created perf domain
10528 06:49:15.179750 <6>[ 1.875060] cpu cpu4: EM: created perf domain
10529 06:49:15.187355 <6>[ 1.880719] sdhci: Secure Digital Host Controller Interface driver
10530 06:49:15.193654 <6>[ 1.887153] sdhci: Copyright(c) Pierre Ossman
10531 06:49:15.200535 <6>[ 1.892105] Synopsys Designware Multimedia Card Interface Driver
10532 06:49:15.206946 <6>[ 1.898734] sdhci-pltfm: SDHCI platform and OF driver helper
10533 06:49:15.210503 <6>[ 1.898810] mmc0: CQHCI version 5.10
10534 06:49:15.217076 <6>[ 1.908614] ledtrig-cpu: registered to indicate activity on CPUs
10535 06:49:15.223793 <6>[ 1.915647] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10536 06:49:15.230068 <6>[ 1.922703] usbcore: registered new interface driver usbhid
10537 06:49:15.233308 <6>[ 1.928525] usbhid: USB HID core driver
10538 06:49:15.240111 <6>[ 1.932732] spi_master spi0: will run message pump with realtime priority
10539 06:49:15.288087 <6>[ 1.975099] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10540 06:49:15.307634 <6>[ 1.991314] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10541 06:49:15.311119 <6>[ 2.004930] mmc0: Command Queue Engine enabled
10542 06:49:15.317873 <6>[ 2.009713] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10543 06:49:15.324566 <6>[ 2.017155] mmcblk0: mmc0:0001 DA4128 116 GiB
10544 06:49:15.327660 <6>[ 2.022000] cros-ec-spi spi0.0: Chrome EC device registered
10545 06:49:15.334111 <6>[ 2.026401] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10546 06:49:15.342648 <6>[ 2.035738] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10547 06:49:15.349301 <6>[ 2.041682] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10548 06:49:15.355270 <6>[ 2.047822] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10549 06:49:15.374135 <6>[ 2.064660] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10550 06:49:15.382051 <6>[ 2.075236] NET: Registered PF_PACKET protocol family
10551 06:49:15.385037 <6>[ 2.080626] 9pnet: Installing 9P2000 support
10552 06:49:15.391481 <5>[ 2.085199] Key type dns_resolver registered
10553 06:49:15.394783 <6>[ 2.090215] registered taskstats version 1
10554 06:49:15.401243 <5>[ 2.094583] Loading compiled-in X.509 certificates
10555 06:49:15.434099 <4>[ 2.120782] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 06:49:15.444034 <4>[ 2.131626] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 06:49:15.450350 <3>[ 2.142173] debugfs: File 'uA_load' in directory '/' already present!
10558 06:49:15.457052 <3>[ 2.148886] debugfs: File 'min_uV' in directory '/' already present!
10559 06:49:15.464067 <3>[ 2.155498] debugfs: File 'max_uV' in directory '/' already present!
10560 06:49:15.470701 <3>[ 2.162108] debugfs: File 'constraint_flags' in directory '/' already present!
10561 06:49:15.482330 <3>[ 2.172201] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10562 06:49:15.494618 <6>[ 2.187937] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10563 06:49:15.500954 <6>[ 2.194827] xhci-mtk 11200000.usb: xHCI Host Controller
10564 06:49:15.507613 <6>[ 2.200360] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10565 06:49:15.518070 <6>[ 2.208287] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10566 06:49:15.524581 <6>[ 2.217721] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10567 06:49:15.531272 <6>[ 2.223792] xhci-mtk 11200000.usb: xHCI Host Controller
10568 06:49:15.537780 <6>[ 2.229273] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10569 06:49:15.545024 <6>[ 2.236925] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10570 06:49:15.551037 <6>[ 2.244777] hub 1-0:1.0: USB hub found
10571 06:49:15.554534 <6>[ 2.248800] hub 1-0:1.0: 1 port detected
10572 06:49:15.564488 <6>[ 2.253112] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10573 06:49:15.567525 <6>[ 2.261830] hub 2-0:1.0: USB hub found
10574 06:49:15.571283 <6>[ 2.265852] hub 2-0:1.0: 1 port detected
10575 06:49:15.579997 <6>[ 2.273017] mtk-msdc 11f70000.mmc: Got CD GPIO
10576 06:49:15.597298 <6>[ 2.287594] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10577 06:49:15.603852 <6>[ 2.295628] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10578 06:49:15.613785 <4>[ 2.303554] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10579 06:49:15.624119 <6>[ 2.313096] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10580 06:49:15.630387 <6>[ 2.321175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10581 06:49:15.637071 <6>[ 2.329209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10582 06:49:15.646835 <6>[ 2.337129] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10583 06:49:15.653845 <6>[ 2.344950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10584 06:49:15.663490 <6>[ 2.352768] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10585 06:49:15.673165 <6>[ 2.363158] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10586 06:49:15.679882 <6>[ 2.371558] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10587 06:49:15.689953 <6>[ 2.379899] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10588 06:49:15.696252 <6>[ 2.388238] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10589 06:49:15.707063 <6>[ 2.396578] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10590 06:49:15.713169 <6>[ 2.404917] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10591 06:49:15.722705 <6>[ 2.413255] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10592 06:49:15.732572 <6>[ 2.421593] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10593 06:49:15.739625 <6>[ 2.429933] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10594 06:49:15.749374 <6>[ 2.438272] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10595 06:49:15.755660 <6>[ 2.446610] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10596 06:49:15.765923 <6>[ 2.454952] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10597 06:49:15.772484 <6>[ 2.463291] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10598 06:49:15.782647 <6>[ 2.471630] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10599 06:49:15.788695 <6>[ 2.479968] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10600 06:49:15.796174 <6>[ 2.488691] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10601 06:49:15.802337 <6>[ 2.495805] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10602 06:49:15.808939 <6>[ 2.502570] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10603 06:49:15.818916 <6>[ 2.509330] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10604 06:49:15.825449 <6>[ 2.516268] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10605 06:49:15.832287 <6>[ 2.523105] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10606 06:49:15.841956 <6>[ 2.532239] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10607 06:49:15.852152 <6>[ 2.541358] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10608 06:49:15.862182 <6>[ 2.550651] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10609 06:49:15.872248 <6>[ 2.560117] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10610 06:49:15.879261 <6>[ 2.569583] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10611 06:49:15.888591 <6>[ 2.578702] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10612 06:49:15.898645 <6>[ 2.588167] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10613 06:49:15.908555 <6>[ 2.597285] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10614 06:49:15.918366 <6>[ 2.606579] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10615 06:49:15.928218 <6>[ 2.616740] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10616 06:49:15.938369 <6>[ 2.627895] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10617 06:49:15.960464 <6>[ 2.650547] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10618 06:49:15.988419 <6>[ 2.681939] hub 2-1:1.0: USB hub found
10619 06:49:15.991930 <6>[ 2.686397] hub 2-1:1.0: 3 ports detected
10620 06:49:16.000632 <6>[ 2.693744] hub 2-1:1.0: USB hub found
10621 06:49:16.003634 <6>[ 2.698071] hub 2-1:1.0: 3 ports detected
10622 06:49:16.112148 <6>[ 2.802471] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10623 06:49:16.266889 <6>[ 2.960466] hub 1-1:1.0: USB hub found
10624 06:49:16.269982 <6>[ 2.964930] hub 1-1:1.0: 4 ports detected
10625 06:49:16.279132 <6>[ 2.972970] hub 1-1:1.0: USB hub found
10626 06:49:16.282792 <6>[ 2.977507] hub 1-1:1.0: 4 ports detected
10627 06:49:16.352017 <6>[ 3.042652] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10628 06:49:16.603824 <6>[ 3.294513] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10629 06:49:16.736500 <6>[ 3.430470] hub 1-1.4:1.0: USB hub found
10630 06:49:16.740083 <6>[ 3.435146] hub 1-1.4:1.0: 2 ports detected
10631 06:49:16.749814 <6>[ 3.443468] hub 1-1.4:1.0: USB hub found
10632 06:49:16.753198 <6>[ 3.448067] hub 1-1.4:1.0: 2 ports detected
10633 06:49:17.052182 <6>[ 3.742493] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10634 06:49:17.244341 <6>[ 3.934561] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10635 06:49:28.229598 <6>[ 14.927475] ALSA device list:
10636 06:49:28.236321 <6>[ 14.930767] No soundcards found.
10637 06:49:28.244080 <6>[ 14.938803] Freeing unused kernel memory: 8448K
10638 06:49:28.247984 <6>[ 14.943776] Run /init as init process
10639 06:49:28.283682 Starting syslogd: OK
10640 06:49:28.287762 Starting klogd: OK
10641 06:49:28.298291 Running sysctl: OK
10642 06:49:28.308036 Populating /dev using udev: <30>[ 15.001183] udevd[193]: starting version 3.2.9
10643 06:49:28.314479 <27>[ 15.008144] udevd[193]: specified user 'tss' unknown
10644 06:49:28.321034 <27>[ 15.013560] udevd[193]: specified group 'tss' unknown
10645 06:49:28.324655 <30>[ 15.020205] udevd[194]: starting eudev-3.2.9
10646 06:49:28.343308 <27>[ 15.037948] udevd[194]: specified user 'tss' unknown
10647 06:49:28.350164 <27>[ 15.043363] udevd[194]: specified group 'tss' unknown
10648 06:49:28.481736 <6>[ 15.172992] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10649 06:49:28.488553 <6>[ 15.180824] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10650 06:49:28.498463 <6>[ 15.189667] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10651 06:49:28.529921 <6>[ 15.221185] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10652 06:49:28.536717 <3>[ 15.221767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 06:49:28.543076 <6>[ 15.233896] remoteproc remoteproc0: scp is available
10654 06:49:28.550154 <3>[ 15.237753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 06:49:28.556200 <6>[ 15.242620] remoteproc remoteproc0: powering up scp
10656 06:49:28.563478 <6>[ 15.247151] usbcore: registered new device driver r8152-cfgselector
10657 06:49:28.573343 <3>[ 15.250199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 06:49:28.579520 <3>[ 15.251847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 06:49:28.589550 <6>[ 15.256131] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10660 06:49:28.596437 <3>[ 15.262660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 06:49:28.603359 <3>[ 15.262672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 06:49:28.612769 <3>[ 15.262679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 06:49:28.619210 <3>[ 15.262683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 06:49:28.629585 <3>[ 15.262792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 06:49:28.635529 <3>[ 15.262854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10666 06:49:28.643180 <6>[ 15.263150] mc: Linux media interface: v0.10
10667 06:49:28.648831 <4>[ 15.263573] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10668 06:49:28.655893 <4>[ 15.263641] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10669 06:49:28.662756 <6>[ 15.270990] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10670 06:49:28.668849 <3>[ 15.278983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 06:49:28.679091 <3>[ 15.278986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 06:49:28.685982 <3>[ 15.279024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 06:49:28.692578 <3>[ 15.279027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 06:49:28.702899 <3>[ 15.279029] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 06:49:28.709056 <3>[ 15.279031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 06:49:28.719085 <3>[ 15.279034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 06:49:28.725920 <3>[ 15.279066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 06:49:28.734007 <6>[ 15.279520] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10679 06:49:28.743202 <6>[ 15.319074] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10680 06:49:28.749976 <6>[ 15.323593] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10681 06:49:28.759435 <6>[ 15.328553] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10682 06:49:28.766595 <6>[ 15.336378] pci_bus 0000:00: root bus resource [bus 00-ff]
10683 06:49:28.776297 <4>[ 15.348481] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10684 06:49:28.779577 <4>[ 15.348481] Fallback method does not support PEC.
10685 06:49:28.785554 <6>[ 15.355308] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10686 06:49:28.792654 <6>[ 15.369645] videodev: Linux video capture interface: v2.00
10687 06:49:28.799616 <6>[ 15.370516] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10688 06:49:28.809568 <6>[ 15.377148] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10689 06:49:28.819591 <3>[ 15.377455] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10690 06:49:28.829321 <6>[ 15.389361] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10691 06:49:28.836064 <6>[ 15.393458] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10692 06:49:28.845918 <4>[ 15.406800] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10693 06:49:28.852314 <6>[ 15.409551] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10694 06:49:28.858991 <6>[ 15.417873] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10695 06:49:28.862539 <6>[ 15.425790] pci 0000:00:00.0: supports D1 D2
10696 06:49:28.869338 <6>[ 15.425794] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10697 06:49:28.879136 <6>[ 15.427268] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10698 06:49:28.885462 <6>[ 15.433854] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10699 06:49:28.892506 <6>[ 15.444135] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10700 06:49:28.902305 <4>[ 15.450707] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10701 06:49:28.905825 <6>[ 15.451163] Bluetooth: Core ver 2.22
10702 06:49:28.912044 <6>[ 15.451220] NET: Registered PF_BLUETOOTH protocol family
10703 06:49:28.918531 <6>[ 15.451222] Bluetooth: HCI device and connection manager initialized
10704 06:49:28.921875 <6>[ 15.451243] Bluetooth: HCI socket layer initialized
10705 06:49:28.928377 <6>[ 15.451248] Bluetooth: L2CAP socket layer initialized
10706 06:49:28.931286 <6>[ 15.451259] Bluetooth: SCO socket layer initialized
10707 06:49:28.941653 <6>[ 15.459658] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10708 06:49:28.948014 <6>[ 15.459689] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10709 06:49:28.954561 <6>[ 15.465474] remoteproc remoteproc0: remote processor scp is now up
10710 06:49:28.961297 <6>[ 15.479064] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10711 06:49:28.967435 <6>[ 15.479186] pci 0000:01:00.0: supports D1 D2
10712 06:49:28.974092 <6>[ 15.480152] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10713 06:49:28.980548 <6>[ 15.486360] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10714 06:49:28.987470 <3>[ 15.490640] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10715 06:49:28.994033 <6>[ 15.491939] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10716 06:49:29.004025 <6>[ 15.501698] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10717 06:49:29.010126 <6>[ 15.502279] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10718 06:49:29.016786 <6>[ 15.502307] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10719 06:49:29.026744 <6>[ 15.502310] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10720 06:49:29.033393 <6>[ 15.502318] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10721 06:49:29.043355 <6>[ 15.502330] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10722 06:49:29.049914 <6>[ 15.502343] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10723 06:49:29.056369 <6>[ 15.502355] pci 0000:00:00.0: PCI bridge to [bus 01]
10724 06:49:29.063345 <6>[ 15.502359] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10725 06:49:29.069727 <6>[ 15.502495] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10726 06:49:29.076744 <6>[ 15.502942] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10727 06:49:29.082840 <6>[ 15.503455] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10728 06:49:29.086280 <6>[ 15.511376] usbcore: registered new interface driver btusb
10729 06:49:29.099547 <4>[ 15.519692] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10730 06:49:29.109572 <6>[ 15.521090] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10731 06:49:29.115980 <6>[ 15.521257] usbcore: registered new interface driver uvcvideo
10732 06:49:29.125766 <6>[ 15.522615] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10733 06:49:29.132120 <5>[ 15.532009] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10734 06:49:29.139580 <3>[ 15.534855] Bluetooth: hci0: Failed to load firmware file (-2)
10735 06:49:29.142608 <6>[ 15.538549] r8152 2-1.3:1.0 eth0: v1.12.13
10736 06:49:29.149418 <6>[ 15.538608] usbcore: registered new interface driver r8152
10737 06:49:29.155330 <6>[ 15.558723] usbcore: registered new interface driver cdc_ether
10738 06:49:29.162180 <3>[ 15.563024] Bluetooth: hci0: Failed to set up firmware (-2)
10739 06:49:29.168923 <5>[ 15.567969] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10740 06:49:29.175859 <5>[ 15.568420] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10741 06:49:29.185180 <4>[ 15.568514] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10742 06:49:29.188635 <6>[ 15.568523] cfg80211: failed to load regulatory.db
10743 06:49:29.195316 <6>[ 15.587450] usbcore: registered new interface driver r8153_ecm
10744 06:49:29.205129 <4>[ 15.592860] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10745 06:49:29.215039 <6>[ 15.659089] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10746 06:49:29.221964 <6>[ 15.913772] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10747 06:49:29.243679 <6>[ 15.938566] mt7921e 0000:01:00.0: ASIC revision: 79610010
10748 06:49:29.347050 <6>[ 16.038411] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10749 06:49:29.350502 <6>[ 16.038411]
10750 06:49:29.357822 done
10751 06:49:29.368186 Saving random seed: OK
10752 06:49:29.386216 Starting network: OK
10753 06:49:29.427020 Starting dropbear sshd: <6>[ 16.121850] NET: Registered PF_INET6 protocol family
10754 06:49:29.434307 <6>[ 16.128785] Segment Routing with IPv6
10755 06:49:29.437960 <6>[ 16.132732] In-situ OAM (IOAM) with IPv6
10756 06:49:29.440918 OK
10757 06:49:29.450945 /bin/sh: can't access tty; job control turned off
10758 06:49:29.452264 Matched prompt #10: / #
10760 06:49:29.453350 Setting prompt string to ['/ #']
10761 06:49:29.453816 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10763 06:49:29.454945 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10764 06:49:29.455501 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10765 06:49:29.455900 Setting prompt string to ['/ #']
10766 06:49:29.456240 Forcing a shell prompt, looking for ['/ #']
10768 06:49:29.507094 / #
10769 06:49:29.507789 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10770 06:49:29.508225 Waiting using forced prompt support (timeout 00:02:30)
10771 06:49:29.513521
10772 06:49:29.514483 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10773 06:49:29.515005 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10774 06:49:29.515544 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10775 06:49:29.516057 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10776 06:49:29.516538 end: 2 depthcharge-action (duration 00:01:35) [common]
10777 06:49:29.517026 start: 3 lava-test-retry (timeout 00:01:00) [common]
10778 06:49:29.517504 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10779 06:49:29.517904 Using namespace: common
10781 06:49:29.619298 / # #
10782 06:49:29.619999 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10783 06:49:29.620580 #<6>[ 16.311795] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10784 06:49:29.664092
10785 06:49:29.664972 Using /lava-12694830
10787 06:49:29.766283 / # export SHELL=/bin/sh
10788 06:49:29.773129 export SHELL=/bin/sh
10790 06:49:29.874928 / # . /lava-12694830/environment
10791 06:49:29.882871 . /lava-12694830/environment
10793 06:49:29.984625 / # /lava-12694830/bin/lava-test-runner /lava-12694830/0
10794 06:49:29.985252 Test shell timeout: 10s (minimum of the action and connection timeout)
10795 06:49:29.992966 /lava-12694830/bin/lava-test-runner /lava-12694830/0
10796 06:49:30.011233 + export 'TESTRUN_ID=0_dmesg'
10797 06:49:30.017756 +<8>[ 16.711581] <LAVA_SIGNAL_STARTRUN 0_dmesg 12694830_1.5.2.3.1>
10798 06:49:30.018775 Received signal: <STARTRUN> 0_dmesg 12694830_1.5.2.3.1
10799 06:49:30.019214 Starting test lava.0_dmesg (12694830_1.5.2.3.1)
10800 06:49:30.019739 Skipping test definition patterns.
10801 06:49:30.020664 cd /lava-12694830/0/tests/0_dmesg
10802 06:49:30.021124 + cat uuid
10803 06:49:30.024422 + UUID=12694830_1.5.2.3.1
10804 06:49:30.024887 + set +x
10805 06:49:30.030731 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10806 06:49:30.046491 <8>[ 16.737854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10807 06:49:30.047438 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10809 06:49:30.069340 <8>[ 16.761023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10810 06:49:30.070020 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10812 06:49:30.091945 <8>[ 16.783724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10813 06:49:30.092652 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10815 06:49:30.095852 + set +x
10816 06:49:30.098932 <8>[ 16.793320] <LAVA_SIGNAL_ENDRUN 0_dmesg 12694830_1.5.2.3.1>
10817 06:49:30.099728 Received signal: <ENDRUN> 0_dmesg 12694830_1.5.2.3.1
10818 06:49:30.100325 Ending use of test pattern.
10819 06:49:30.100816 Ending test lava.0_dmesg (12694830_1.5.2.3.1), duration 0.08
10821 06:49:30.102990 <LAVA_TEST_RUNNER EXIT>
10822 06:49:30.103668 ok: lava_test_shell seems to have completed
10823 06:49:30.104225 alert: pass
crit: pass
emerg: pass
10824 06:49:30.104683 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10825 06:49:30.105141 end: 3 lava-test-retry (duration 00:00:01) [common]
10826 06:49:30.105574 start: 4 lava-test-retry (timeout 00:01:00) [common]
10827 06:49:30.106027 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10828 06:49:30.106399 Using namespace: common
10830 06:49:30.207644 / # #
10831 06:49:30.208255 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10832 06:49:30.208815 Using /lava-12694830
10834 06:49:30.309780 export SHELL=/bin/sh
10835 06:49:30.309934 #
10837 06:49:30.410672 / # export SHELL=/bin/sh. /lava-12694830/environment
10838 06:49:30.411697
10840 06:49:30.513063 / # . /lava-12694830/environment/lava-12694830/bin/lava-test-runner /lava-12694830/1
10841 06:49:30.513754 Test shell timeout: 10s (minimum of the action and connection timeout)
10842 06:49:30.514508
10843 06:49:30.515057 / # <6>[ 17.160254] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10844 06:49:30.519434 /lava-12694830/bin/lava-test-runner /lava-12694830/1
10845 06:49:30.559656 + export 'TESTRUN_ID=1_bootrr'
10846 06:49:30.560230 <8>[ 17.237848] <LAVA_SIGNAL_STARTRUN 1_bootrr 12694830_1.5.2.3.5>
10847 06:49:30.560603 + cd /lava-12694830/1/tests/1_bootrr
10848 06:49:30.561032 + cat uuid
10849 06:49:30.561769 Received signal: <STARTRUN> 1_bootrr 12694830_1.5.2.3.5
10850 06:49:30.562113 Starting test lava.1_bootrr (12694830_1.5.2.3.5)
10851 06:49:30.562661 Skipping test definition patterns.
10852 06:49:30.563392 + UUID=12694830_1.5.2.3.5
10853 06:49:30.563922 + set +x
10854 06:49:30.564329 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12694830/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10855 06:49:30.567328 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10857 06:49:30.570427 <8>[ 17.260910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10858 06:49:30.570925
10859 06:49:30.571438 + cd /opt/bootrr/libexec/bootrr
10860 06:49:30.573896 + sh helpers/bootrr-auto
10861 06:49:30.576855 /lava-12694830/1/../bin/lava-test-case
10862 06:49:30.580611 /lava-12694830/1/../bin/lava-test-case
10863 06:49:30.586791 <8>[ 17.279881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10864 06:49:30.587692 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10866 06:49:30.594986 /usr/bin/tpm2_getcap
10867 06:49:30.627877 /lava-12694830/1/../bin/lava-test-case
10868 06:49:30.633790 <8>[ 17.326752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10869 06:49:30.634314 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10871 06:49:30.652637 /lava-12694830/1/../bin/lava-test-case
10872 06:49:30.659622 <8>[ 17.351201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10873 06:49:30.660145 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10875 06:49:30.670878 /lava-12694830/1/../bin/lava-test-case
10876 06:49:30.677837 <8>[ 17.369933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10877 06:49:30.678494 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10879 06:49:30.689437 /lava-12694830/1/../bin/lava-test-case
10880 06:49:30.695907 <8>[ 17.387361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10881 06:49:30.696573 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10883 06:49:30.711987 /lava-12694830/1/../bin/lava-test-case
10884 06:49:30.718657 <8>[ 17.411151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10885 06:49:30.719383 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10887 06:49:30.731022 /lava-12694830/1/../bin/lava-test-case
10888 06:49:30.737892 <8>[ 17.429822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10889 06:49:30.738519 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10891 06:49:30.749451 /lava-12694830/1/../bin/lava-test-case
10892 06:49:30.759316 <8>[ 17.449852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10893 06:49:30.759988 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10895 06:49:30.770173 /lava-12694830/1/../bin/lava-test-case
10896 06:49:30.775893 <8>[ 17.467872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10897 06:49:30.776175 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10899 06:49:30.786576 /lava-12694830/1/../bin/lava-test-case
10900 06:49:30.793243 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10902 06:49:30.795950 <8>[ 17.485894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10903 06:49:30.805212 /lava-12694830/1/../bin/lava-test-case
10904 06:49:30.815067 <8>[ 17.505866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10905 06:49:30.815948 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10907 06:49:30.826348 /lava-12694830/1/../bin/lava-test-case
10908 06:49:30.835802 <8>[ 17.526384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10909 06:49:30.836612 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10911 06:49:30.848259 /lava-12694830/1/../bin/lava-test-case
10912 06:49:30.854386 <8>[ 17.545892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10913 06:49:30.854905 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10915 06:49:30.866431 /lava-12694830/1/../bin/lava-test-case
10916 06:49:30.872789 <8>[ 17.564069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10917 06:49:30.873159 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10919 06:49:30.890514 /lava-12694830/1/../bin/lava-tes<8>[ 17.581956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10920 06:49:30.890619 t-case
10921 06:49:30.890882 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10923 06:49:30.902944 /lava-12694830/1/../bin/lava-test-case
10924 06:49:30.909681 <8>[ 17.600825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10925 06:49:30.909933 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10927 06:49:30.917811 /lava-12694830/1/../bin/lava-test-case
10928 06:49:30.924055 <8>[ 17.616654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10929 06:49:30.924407 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10931 06:49:30.936533 /lava-12694830/1/../bin/lava-test-case
10932 06:49:30.943091 <8>[ 17.634690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10933 06:49:30.943404 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10935 06:49:30.952340 /lava-12694830/1/../bin/lava-test-case
10936 06:49:30.959166 <8>[ 17.651429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10937 06:49:30.959507 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10939 06:49:30.970195 /lava-12694830/1/../bin/lava-test-case
10940 06:49:30.976682 <8>[ 17.669805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10941 06:49:30.977122 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10943 06:49:30.987244 /lava-12694830/1/../bin/lava-test-case
10944 06:49:30.993465 <8>[ 17.685591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10945 06:49:30.993861 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10947 06:49:31.004052 /lava-12694830/1/../bin/lava-test-case
10948 06:49:31.010672 <8>[ 17.703207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10949 06:49:31.011116 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10951 06:49:31.030928 /lava-12694830/1/../bin/lava-tes<8>[ 17.722058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10952 06:49:31.031260 t-case
10953 06:49:31.031705 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10955 06:49:31.043658 /lava-12694830/1/../bin/lava-test-case
10956 06:49:31.050259 <8>[ 17.741968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10957 06:49:31.050542 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10959 06:49:31.062742 /lava-12694830/1/../bin/lava-test-case
10960 06:49:31.069581 <8>[ 17.761037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10961 06:49:31.069864 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10963 06:49:31.087887 /lava-12694830/1/../bin/lava-tes<8>[ 17.778676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10964 06:49:31.088004 t-case
10965 06:49:31.088286 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10967 06:49:31.098733 /lava-12694830/1/../bin/lava-test-case
10968 06:49:31.105125 <8>[ 17.797914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10969 06:49:31.105393 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10971 06:49:31.114622 /lava-12694830/1/../bin/lava-test-case
10972 06:49:31.120537 <8>[ 17.813024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10973 06:49:31.120793 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10975 06:49:31.133955 /lava-12694830/1/../bin/lava-test-case
10976 06:49:31.140107 <8>[ 17.831193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10977 06:49:31.140958 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10979 06:49:31.151955 /lava-12694830/1/../bin/lava-test-case
10980 06:49:31.158686 <8>[ 17.851599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10981 06:49:31.159556 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10983 06:49:31.177791 /lava-12694830/1/../bin/lava-tes<8>[ 17.869213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10984 06:49:31.177986 t-case
10985 06:49:31.178324 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10987 06:49:31.189750 /lava-12694830/1/../bin/lava-test-case
10988 06:49:31.196583 <8>[ 17.888591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10989 06:49:31.196966 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10991 06:49:31.206995 /lava-12694830/1/../bin/lava-test-case
10992 06:49:31.213880 <8>[ 17.905702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10993 06:49:31.214259 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10995 06:49:31.226611 /lava-12694830/1/../bin/lava-test-case
10996 06:49:31.232922 <8>[ 17.925382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10997 06:49:31.233302 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10999 06:49:31.245506 /lava-12694830/1/../bin/lava-test-case
11000 06:49:31.251593 <8>[ 17.944808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11001 06:49:31.252323 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11003 06:49:31.262186 /lava-12694830/1/../bin/lava-test-case
11004 06:49:31.268785 <8>[ 17.961598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11005 06:49:31.269222 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11007 06:49:31.283924 /lava-12694830/1/../bin/lava-test-case
11008 06:49:31.290425 <8>[ 17.981750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11009 06:49:31.290772 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11011 06:49:31.298936 /lava-12694830/1/../bin/lava-test-case
11012 06:49:31.305097 <8>[ 17.997873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11013 06:49:31.305408 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11015 06:49:31.318596 /lava-12694830/1/../bin/lava-test-case
11016 06:49:31.324900 <8>[ 18.016805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11017 06:49:31.325234 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11019 06:49:31.333432 /lava-12694830/1/../bin/lava-test-case
11020 06:49:31.340139 <8>[ 18.032362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11021 06:49:31.340587 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11023 06:49:31.353934 /lava-12694830/1/../bin/lava-test-case
11024 06:49:31.360165 <8>[ 18.052169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11025 06:49:31.360965 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11027 06:49:31.370133 /lava-12694830/1/../bin/lava-test-case
11028 06:49:31.380307 <8>[ 18.070475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11029 06:49:31.381247 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11031 06:49:31.392236 /lava-12694830/1/../bin/lava-test-case
11032 06:49:31.398861 <8>[ 18.090648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11033 06:49:31.399535 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11035 06:49:31.407697 /lava-12694830/1/../bin/lava-test-case
11036 06:49:31.414504 <8>[ 18.105558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11037 06:49:31.415414 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11039 06:49:31.430077 /lava-12694830/1/../bin/lava-test-case
11040 06:49:31.436595 <8>[ 18.128238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11041 06:49:31.437262 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11043 06:49:31.455159 /lava-12694830/1/../bin/lava-tes<8>[ 18.145778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11044 06:49:31.455741 t-case
11045 06:49:31.456345 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11047 06:49:31.465319 /lava-12694830/1/../bin/lava-test-case
11048 06:49:31.472309 <8>[ 18.163483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11049 06:49:31.473015 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11051 06:49:31.483799 /lava-12694830/1/../bin/lava-test-case
11052 06:49:31.490586 <8>[ 18.182561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11053 06:49:31.491474 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11055 06:49:31.502647 /lava-12694830/1/../bin/lava-test-case
11056 06:49:31.509545 <8>[ 18.201525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11057 06:49:31.510223 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11059 06:49:31.520044 /lava-12694830/1/../bin/lava-test-case
11060 06:49:31.526167 <8>[ 18.218400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11061 06:49:31.526995 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11063 06:49:31.538487 /lava-12694830/1/../bin/lava-test-case
11064 06:49:31.544804 <8>[ 18.236494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11065 06:49:31.545692 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11067 06:49:31.564268 /lava-12694830/1/../bin/lava-tes<8>[ 18.255370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11068 06:49:31.564957 t-case
11069 06:49:31.565741 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11071 06:49:31.575236 /lava-12694830/1/../bin/lava-test-case
11072 06:49:31.581936 <8>[ 18.274476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11073 06:49:31.582569 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11075 06:49:31.594354 /lava-12694830/1/../bin/lava-test-case
11076 06:49:31.600668 <8>[ 18.292422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11077 06:49:31.601195 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11079 06:49:31.612849 /lava-12694830/1/../bin/lava-test-case
11080 06:49:31.619144 <8>[ 18.310715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11081 06:49:31.619683 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11083 06:49:31.633075 /lava-12694830/1/../bin/lava-test-case
11084 06:49:31.639426 <8>[ 18.332377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11085 06:49:31.640230 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11087 06:49:31.650891 /lava-12694830/1/../bin/lava-test-case
11088 06:49:31.657606 <8>[ 18.348244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11089 06:49:31.658486 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11091 06:49:31.677260 /lava-12694830/1/../bin/lava-tes<8>[ 18.368406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11092 06:49:31.677876 t-case
11093 06:49:31.678552 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11095 06:49:31.688201 /lava-12694830/1/../bin/lava-test-case
11096 06:49:31.694523 <8>[ 18.385260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11097 06:49:31.695429 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11099 06:49:31.705704 /lava-12694830/1/../bin/lava-test-case
11100 06:49:31.712663 <8>[ 18.403704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11101 06:49:31.713511 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11103 06:49:31.726211 /lava-12694830/1/../bin/lava-test-case
11104 06:49:31.732458 <8>[ 18.424233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11105 06:49:31.733337 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11107 06:49:31.741454 /lava-12694830/1/../bin/lava-test-case
11108 06:49:31.748286 <8>[ 18.439057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11109 06:49:31.749159 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11111 06:49:31.760681 /lava-12694830/1/../bin/lava-test-case
11112 06:49:31.767617 <8>[ 18.459655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11113 06:49:31.768494 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11115 06:49:31.777650 /lava-12694830/1/../bin/lava-test-case
11116 06:49:31.785614 <8>[ 18.475189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11117 06:49:31.786490 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11119 06:49:31.802502 /lava-12694830/1/../bin/lava-tes<8>[ 18.493655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11120 06:49:31.803062 t-case
11121 06:49:31.803879 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11123 06:49:31.812333 /lava-12694830/1/../bin/lava-test-case
11124 06:49:31.818316 <8>[ 18.509591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11125 06:49:31.819166 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11127 06:49:31.831653 /lava-12694830/1/../bin/lava-test-case
11128 06:49:31.838203 <8>[ 18.529303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11129 06:49:31.839094 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11131 06:49:31.850242 /lava-12694830/1/../bin/lava-test-case
11132 06:49:31.856655 <8>[ 18.547564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11133 06:49:31.857537 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11135 06:49:31.870004 /lava-12694830/1/../bin/lava-test-case
11136 06:49:31.875981 <8>[ 18.569122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11137 06:49:31.876875 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11139 06:49:31.889944 /lava-12694830/1/../bin/lava-test-case
11140 06:49:31.896594 <8>[ 18.588471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11141 06:49:31.897507 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11143 06:49:31.909449 /lava-12694830/1/../bin/lava-test-case
11144 06:49:31.915733 <8>[ 18.608984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11145 06:49:31.916443 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11147 06:49:31.927043 /lava-12694830/1/../bin/lava-test-case
11148 06:49:31.933623 <8>[ 18.625850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11149 06:49:31.934302 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11151 06:49:31.949343 /lava-12694830/1/../bin/lava-test-case
11152 06:49:31.955438 <8>[ 18.648106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11153 06:49:31.956329 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11155 06:49:31.966023 /lava-12694830/1/../bin/lava-test-case
11156 06:49:31.972928 <8>[ 18.666157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11157 06:49:31.973804 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11159 06:49:31.984242 /lava-12694830/1/../bin/lava-test-case
11160 06:49:31.991221 <8>[ 18.683831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11161 06:49:31.992137 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11163 06:49:32.003726 /lava-12694830/1/../bin/lava-test-case
11164 06:49:32.010253 <8>[ 18.701722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11165 06:49:32.010783 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11167 06:49:32.021259 /lava-12694830/1/../bin/lava-test-case
11168 06:49:32.027989 <8>[ 18.720144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11169 06:49:32.028392 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11171 06:49:32.040778 /lava-12694830/1/../bin/lava-test-case
11172 06:49:32.046732 <8>[ 18.738426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11173 06:49:32.047084 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11175 06:49:32.058042 /lava-12694830/1/../bin/lava-test-case
11176 06:49:32.064561 <8>[ 18.756553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11177 06:49:32.064903 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11179 06:49:32.077368 /lava-12694830/1/../bin/lava-test-case
11180 06:49:32.084025 <8>[ 18.775587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11181 06:49:32.084531 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11183 06:49:32.094030 /lava-12694830/1/../bin/lava-test-case
11184 06:49:32.101043 <8>[ 18.793837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11185 06:49:32.101739 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11187 06:49:32.111899 /lava-12694830/1/../bin/lava-test-case
11188 06:49:32.118402 <8>[ 18.809624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11189 06:49:32.119223 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11191 06:49:32.134056 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11193 06:49:32.137068 /lava-12694830/1/../bin/lava-tes<8>[ 18.828309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11194 06:49:32.137494 t-case
11195 06:49:32.145685 /lava-12694830/1/../bin/lava-test-case
11196 06:49:32.152176 <8>[ 18.844304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11197 06:49:32.152931 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11199 06:49:32.166179 /lava-12694830/1/../bin/lava-test-case
11200 06:49:32.172778 <8>[ 18.864234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11201 06:49:32.173483 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11203 06:49:32.181830 /lava-12694830/1/../bin/lava-test-case
11204 06:49:32.188498 <8>[ 18.881218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11205 06:49:32.188973 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11207 06:49:32.200300 /lava-12694830/1/../bin/lava-test-case
11208 06:49:32.207072 <8>[ 18.900637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11209 06:49:32.207420 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11211 06:49:32.218241 /lava-12694830/1/../bin/lava-test-case
11212 06:49:32.224970 <8>[ 18.917560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11213 06:49:32.225352 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11215 06:49:32.236832 /lava-12694830/1/../bin/lava-test-case
11216 06:49:32.243048 <8>[ 18.935659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11217 06:49:32.243414 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11219 06:49:32.251761 /lava-12694830/1/../bin/lava-test-case
11220 06:49:32.258378 <8>[ 18.950713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11221 06:49:32.258822 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11223 06:49:32.270253 /lava-12694830/1/../bin/lava-test-case
11224 06:49:32.277111 <8>[ 18.969269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11225 06:49:32.277509 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11227 06:49:32.285429 /lava-12694830/1/../bin/lava-test-case
11228 06:49:32.291623 <8>[ 18.984109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11229 06:49:32.291964 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11231 06:49:32.305430 /lava-12694830/1/../bin/lava-test-case
11232 06:49:32.312200 <8>[ 19.004495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11233 06:49:32.312454 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11235 06:49:32.322263 /lava-12694830/1/../bin/lava-test-case
11236 06:49:32.329144 <8>[ 19.022582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11237 06:49:32.329406 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11239 06:49:32.340478 /lava-12694830/1/../bin/lava-test-case
11240 06:49:32.347026 <8>[ 19.038393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11241 06:49:32.347754 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11243 06:49:32.358485 /lava-12694830/1/../bin/lava-test-case
11244 06:49:32.365584 <8>[ 19.056667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11245 06:49:32.366278 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11247 06:49:32.375128 /lava-12694830/1/../bin/lava-test-case
11248 06:49:32.381330 <8>[ 19.073091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11249 06:49:32.382006 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11251 06:49:32.393754 /lava-12694830/1/../bin/lava-test-case
11252 06:49:32.400553 <8>[ 19.092891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11253 06:49:32.401258 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11255 06:49:32.409404 /lava-12694830/1/../bin/lava-test-case
11256 06:49:32.415438 <8>[ 19.107721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11257 06:49:32.415973 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11259 06:49:33.429848 /lava-12694830/1/../bin/lava-test-case
11260 06:49:33.436239 <8>[ 20.128729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11261 06:49:33.436924 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11263 06:49:33.447789 /lava-12694830/1/../bin/lava-test-case
11264 06:49:33.454556 <8>[ 20.147898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11265 06:49:33.455305 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11267 06:49:34.469770 /lava-12694830/1/../bin/lava-test-case
11268 06:49:34.475976 <8>[ 21.169338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11269 06:49:34.476726 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11271 06:49:34.486262 /lava-12694830/1/../bin/lava-test-case
11272 06:49:34.492467 <8>[ 21.185245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11273 06:49:34.493181 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11275 06:49:35.508004 /lava-12694830/1/../bin/lava-test-case
11276 06:49:35.514585 <8>[ 22.208207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11277 06:49:35.515434 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11279 06:49:35.525929 /lava-12694830/1/../bin/lava-test-case
11280 06:49:35.532287 <8>[ 22.224565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11281 06:49:35.533209 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11283 06:49:36.546151 /lava-12694830/1/../bin/lava-test-case
11284 06:49:36.552555 <8>[ 23.244658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11285 06:49:36.553400 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11287 06:49:36.570114 /lava-12694830/1/../bin/lava-tes<8>[ 23.261370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11288 06:49:36.570679 t-case
11289 06:49:36.571325 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11291 06:49:37.583021 /lava-12694830/1/../bin/lava-test-case
11292 06:49:37.589336 <8>[ 24.282845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11293 06:49:37.590170 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11295 06:49:37.599768 /lava-12694830/1/../bin/lava-test-case
11296 06:49:37.605623 <8>[ 24.298309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11297 06:49:37.606501 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11299 06:49:38.621606 /lava-12694830/1/../bin/lava-test-case
11300 06:49:38.627292 <8>[ 25.321780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11301 06:49:38.627574 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11303 06:49:38.638298 /lava-12694830/1/../bin/lava-test-case
11304 06:49:38.644739 <8>[ 25.338309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11305 06:49:38.645119 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11307 06:49:39.659770 /lava-12694830/1/../bin/lava-test-case
11308 06:49:39.666147 <8>[ 26.359375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11309 06:49:39.666614 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11311 06:49:39.686448 /lava-12694830/1/../bin/lava-tes<8>[ 26.378417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11312 06:49:39.686893 t-case
11313 06:49:39.687445 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11315 06:49:39.702448 /lava-12694830/1/../bin/lava-tes<8>[ 26.394908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11316 06:49:39.702612 t-case
11317 06:49:39.702870 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11319 06:49:40.718772 /lava-12694830/1/../bin/lava-test-case
11320 06:49:40.724837 <8>[ 27.417699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11321 06:49:40.725574 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11323 06:49:40.744281 /lava-12694830/1/../bin/lava-tes<8>[ 27.435900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11324 06:49:40.744853 t-case
11325 06:49:40.745496 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11327 06:49:40.756563 /lava-12694830/1/../bin/lava-test-case
11328 06:49:40.762868 <8>[ 27.454989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11329 06:49:40.763601 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11331 06:49:40.780760 /lava-12694830/1/../bin/lava-tes<8>[ 27.472646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11332 06:49:40.781329 t-case
11333 06:49:40.781979 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11335 06:49:40.792914 /lava-12694830/1/../bin/lava-test-case
11336 06:49:40.798888 <8>[ 27.491198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11337 06:49:40.799745 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11339 06:49:40.812336 /lava-12694830/1/../bin/lava-test-case
11340 06:49:40.818650 <8>[ 27.511419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11341 06:49:40.819518 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11343 06:49:40.833057 /lava-12694830/1/../bin/lava-test-case
11344 06:49:40.839546 <8>[ 27.531884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11345 06:49:40.840384 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11347 06:49:40.857303 /lava-12694830/1/../bin/lava-tes<8>[ 27.549153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11348 06:49:40.857890 t-case
11349 06:49:40.858538 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11351 06:49:40.869996 /lava-12694830/1/../bin/lava-test-case
11352 06:49:40.876145 <8>[ 27.568466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11353 06:49:40.876965 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11355 06:49:40.890248 /lava-12694830/1/../bin/lava-test-case
11356 06:49:40.896906 <8>[ 27.590768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11357 06:49:40.897755 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11359 06:49:40.907780 /lava-12694830/1/../bin/lava-test-case
11360 06:49:40.914527 <8>[ 27.606717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11361 06:49:40.915402 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11363 06:49:40.928798 /lava-12694830/1/../bin/lava-test-case
11364 06:49:40.935552 <8>[ 27.629113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11365 06:49:40.936385 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11367 06:49:40.946201 /lava-12694830/1/../bin/lava-test-case
11368 06:49:40.956392 <8>[ 27.646481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11369 06:49:40.957231 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11371 06:49:40.966221 /lava-12694830/1/../bin/lava-test-case
11372 06:49:40.972044 <8>[ 27.665146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11373 06:49:40.972861 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11375 06:49:40.980839 /lava-12694830/1/../bin/lava-test-case
11376 06:49:40.987827 <8>[ 27.680951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11377 06:49:40.988647 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11379 06:49:41.002253 /lava-12694830/1/../bin/lava-test-case
11380 06:49:41.008533 <8>[ 27.700961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11381 06:49:41.009354 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11383 06:49:41.025681 /lava-12694830/1/../bin/lava-tes<8>[ 27.717890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11384 06:49:41.026425 t-case
11385 06:49:41.027122 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11387 06:49:41.038188 /lava-12694830/1/../bin/lava-test-case
11388 06:49:41.044349 <8>[ 27.736897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11389 06:49:41.045027 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11391 06:49:41.061335 /lava-12694830/1/../bin/lava-tes<8>[ 27.753446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11392 06:49:41.061991 t-case
11393 06:49:41.062778 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11395 06:49:41.078007 /lava-12694830/1/../bin/lava-tes<8>[ 27.770087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11396 06:49:41.078516 t-case
11397 06:49:41.079112 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11399 06:49:41.086858 /lava-12694830/1/../bin/lava-test-case
11400 06:49:41.093344 <8>[ 27.786669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11401 06:49:41.094158 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11403 06:49:42.106732 /lava-12694830/1/../bin/lava-test-case
11404 06:49:42.113425 <8>[ 28.806078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11405 06:49:42.114277 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11407 06:49:43.130234 /lava-12694830/1/../bin/lava-test-case
11408 06:49:43.138229 <8>[ 29.830259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11409 06:49:43.139089 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11411 06:49:43.147559 /lava-12694830/1/../bin/lava-test-case
11412 06:49:43.154365 <8>[ 29.847317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11413 06:49:43.155218 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11415 06:49:43.167246 /lava-12694830/1/../bin/lava-test-case
11416 06:49:43.172798 <8>[ 29.865632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11417 06:49:43.173873 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11419 06:49:43.185977 /lava-12694830/1/../bin/lava-test-case
11420 06:49:43.192990 <8>[ 29.885276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11421 06:49:43.193837 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11423 06:49:43.204594 /lava-12694830/1/../bin/lava-test-case
11424 06:49:43.211768 <8>[ 29.903628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11425 06:49:43.212610 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11427 06:49:43.230837 /lava-12694830/1/../bin/lava-tes<8>[ 29.922948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11428 06:49:43.231430 t-case
11429 06:49:43.232085 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11431 06:49:43.242842 /lava-12694830/1/../bin/lava-test-case
11432 06:49:43.249451 <8>[ 29.943338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11433 06:49:43.250327 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11435 06:49:43.258386 /lava-12694830/1/../bin/lava-test-case
11436 06:49:43.264579 <8>[ 29.957016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11437 06:49:43.265464 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11439 06:49:43.280391 /lava-12694830/1/../bin/lava-test-case
11440 06:49:43.286779 <8>[ 29.979949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11441 06:49:43.287482 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11443 06:49:43.302822 /lava-12694830/1/../bin/lava-tes<8>[ 29.995136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11444 06:49:43.303253 t-case
11445 06:49:43.304011 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11447 06:49:43.314987 /lava-12694830/1/../bin/lava-test-case
11448 06:49:43.320687 <8>[ 30.013124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11449 06:49:43.321491 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11451 06:49:43.331052 /lava-12694830/1/../bin/lava-test-case
11452 06:49:43.338111 <8>[ 30.030283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11453 06:49:43.338798 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11455 06:49:43.351010 /lava-12694830/1/../bin/lava-test-case
11456 06:49:43.357144 <8>[ 30.050297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11457 06:49:43.357999 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11459 06:49:43.366051 /lava-12694830/1/../bin/lava-test-case
11460 06:49:43.372624 <8>[ 30.066275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11461 06:49:43.373456 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11463 06:49:43.389112 /lava-12694830/1/../bin/lava-test-case
11464 06:49:43.395327 <8>[ 30.088747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11465 06:49:43.396217 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11467 06:49:43.406734 /lava-12694830/1/../bin/lava-test-case
11468 06:49:43.413246 <8>[ 30.105495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11469 06:49:43.414121 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11471 06:49:43.423587 /lava-12694830/1/../bin/lava-test-case
11472 06:49:43.429626 <8>[ 30.123508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11473 06:49:43.430458 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11475 06:49:43.439593 /lava-12694830/1/../bin/lava-test-case
11476 06:49:43.445950 <8>[ 30.138748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11477 06:49:43.446822 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11479 06:49:43.456918 /lava-12694830/1/../bin/lava-test-case
11480 06:49:43.462458 <8>[ 30.155806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11481 06:49:43.463307 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11483 06:49:43.472108 /lava-12694830/1/../bin/lava-test-case
11484 06:49:43.478575 <8>[ 30.171455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11485 06:49:43.479563 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11487 06:49:43.490781 /lava-12694830/1/../bin/lava-test-case
11488 06:49:43.497106 <8>[ 30.189528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11489 06:49:43.497958 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11491 06:49:44.511992 /lava-12694830/1/../bin/lava-test-case
11492 06:49:44.518421 <8>[ 31.213437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11493 06:49:44.518708 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11495 06:49:45.531517 /lava-12694830/1/../bin/lava-test-case
11496 06:49:45.541630 <8>[ 32.235465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11497 06:49:45.541962 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11498 06:49:45.542066 Bad test result: blocked
11499 06:49:45.550633 /lava-12694830/1/../bin/lava-test-case
11500 06:49:45.557031 <8>[ 32.251220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11501 06:49:45.557292 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11503 06:49:46.571118 /lava-12694830/1/../bin/lava-test-case
11504 06:49:46.577678 <8>[ 33.272004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11505 06:49:46.577963 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11507 06:49:46.588494 /lava-12694830/1/../bin/lava-test-case
11508 06:49:46.594980 <8>[ 33.289320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11509 06:49:46.595273 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11511 06:49:46.606278 /lava-12694830/1/../bin/lava-test-case
11512 06:49:46.613173 <8>[ 33.306438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11513 06:49:46.613476 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11515 06:49:46.627213 /lava-12694830/1/../bin/lava-test-case
11516 06:49:46.633493 <8>[ 33.328187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11517 06:49:46.633772 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11519 06:49:46.642262 /lava-12694830/1/../bin/lava-test-case
11520 06:49:46.648515 <8>[ 33.343785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11521 06:49:46.648790 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11523 06:49:46.661779 /lava-12694830/1/../bin/lava-test-case
11524 06:49:46.668291 <8>[ 33.362539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11525 06:49:46.668564 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11527 06:49:46.677734 /lava-12694830/1/../bin/lava-test-case
11528 06:49:46.683272 <8>[ 33.378168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11529 06:49:46.683604 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11531 06:49:47.697659 /lava-12694830/1/../bin/lava-test-case
11532 06:49:47.703862 <8>[ 34.398234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11533 06:49:47.704176 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11535 06:49:47.722453 /lava-12694830/1/../bin/lava-tes<8>[ 34.415938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11536 06:49:47.722573 t-case
11537 06:49:47.722840 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11539 06:49:48.735783 /lava-12694830/1/../bin/lava-test-case
11540 06:49:48.742686 <8>[ 35.437835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11541 06:49:48.742965 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11543 06:49:48.751180 /lava-12694830/1/../bin/lava-test-case
11544 06:49:48.757700 <8>[ 35.452074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11545 06:49:48.757955 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11547 06:49:49.771836 /lava-12694830/1/../bin/lava-test-case
11548 06:49:49.777780 <8>[ 36.472125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11549 06:49:49.778058 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11551 06:49:49.797538 /lava-12694830/1/../bin/lava-tes<8>[ 36.491099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11552 06:49:49.797658 t-case
11553 06:49:49.797897 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11555 06:49:50.813105 /lava-12694830/1/../bin/lava-test-case
11556 06:49:50.820204 <8>[ 37.515065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11557 06:49:50.820514 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11559 06:49:50.830523 /lava-12694830/1/../bin/lava-test-case
11560 06:49:50.836555 <8>[ 37.531020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11561 06:49:50.836810 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11563 06:49:50.848306 /lava-12694830/1/../bin/lava-test-case
11564 06:49:50.855087 <8>[ 37.548799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11565 06:49:50.855386 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11567 06:49:50.866291 /lava-12694830/1/../bin/lava-test-case
11568 06:49:50.872398 <8>[ 37.566371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11569 06:49:50.872671 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11571 06:49:50.888428 /lava-12694830/1/../bin/lava-tes<8>[ 37.582089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11572 06:49:50.888517 t-case
11573 06:49:50.888786 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11575 06:49:50.899291 /lava-12694830/1/../bin/lava-test-case
11576 06:49:50.906267 <8>[ 37.600449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11577 06:49:50.906543 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11579 06:49:50.913357 /lava-12694830/1/../bin/lava-test-case
11580 06:49:50.921195 <8>[ 37.613929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11581 06:49:50.921485 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11583 06:49:50.934603 /lava-12694830/1/../bin/lava-test-case
11584 06:49:50.941290 <8>[ 37.635802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11585 06:49:50.941580 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11587 06:49:50.952967 /lava-12694830/1/../bin/lava-test-case
11588 06:49:50.958942 <8>[ 37.653294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11589 06:49:50.959210 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11591 06:49:50.978348 /lava-12694830/1/../bin/lava-tes<8>[ 37.672052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11592 06:49:50.978482 t-case
11593 06:49:50.978727 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11595 06:49:50.981878 + set +x
11596 06:49:50.985595 Received signal: <ENDRUN> 1_bootrr 12694830_1.5.2.3.5
11597 06:49:50.985692 Ending use of test pattern.
11598 06:49:50.985759 Ending test lava.1_bootrr (12694830_1.5.2.3.5), duration 20.42
11600 06:49:50.988027 <8>[ 37.682629] <LAVA_SIGNAL_ENDRUN 1_bootrr 12694830_1.5.2.3.5>
11601 06:49:50.988110 <LAVA_TEST_RUNNER EXIT>
11602 06:49:50.988343 ok: lava_test_shell seems to have completed
11603 06:49:50.989311 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11604 06:49:50.989454 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11605 06:49:50.989542 end: 4 lava-test-retry (duration 00:00:21) [common]
11606 06:49:50.989631 start: 5 finalize (timeout 00:07:45) [common]
11607 06:49:50.989724 start: 5.1 power-off (timeout 00:00:30) [common]
11608 06:49:50.989882 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11609 06:49:51.066767 >> Command sent successfully.
11610 06:49:51.069418 Returned 0 in 0 seconds
11611 06:49:51.169833 end: 5.1 power-off (duration 00:00:00) [common]
11613 06:49:51.170158 start: 5.2 read-feedback (timeout 00:07:45) [common]
11614 06:49:51.170424 Listened to connection for namespace 'common' for up to 1s
11615 06:49:51.170758 Listened to connection for namespace 'common' for up to 1s
11616 06:49:52.171384 Finalising connection for namespace 'common'
11617 06:49:52.171557 Disconnecting from shell: Finalise
11618 06:49:52.171648 / #
11619 06:49:52.272007 end: 5.2 read-feedback (duration 00:00:01) [common]
11620 06:49:52.272197 end: 5 finalize (duration 00:00:01) [common]
11621 06:49:52.272315 Cleaning after the job
11622 06:49:52.272416 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/ramdisk
11623 06:49:52.275480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/kernel
11624 06:49:52.284412 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/dtb
11625 06:49:52.284598 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12694830/tftp-deploy-m4akf261/modules
11626 06:49:52.291913 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12694830
11627 06:49:52.337790 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12694830
11628 06:49:52.337955 Job finished correctly